From f46bae1317c370f70cbffeb9e9b829d1fca167f5 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 13 Apr 2023 16:07:58 +0200 Subject: [PATCH 001/207] Moved defines to parameters. --- Bender.yml | 5 ++- include/cluster_bus_defines.sv | 2 +- rtl/cluster_bus_wrap.sv | 27 +++++++--------- rtl/cluster_interconnect_wrap.sv | 5 +-- rtl/cluster_peripherals.sv | 1 - rtl/core_demux.sv | 13 +++----- rtl/core_region.sv | 9 ++---- rtl/periph_demux.sv | 1 - rtl/pulp_cluster.sv | 54 +++++++++++--------------------- rtl/xbar_pe_wrap.sv | 11 +++---- 10 files changed, 48 insertions(+), 80 deletions(-) diff --git a/Bender.yml b/Bender.yml index 03df5197..c1f44427 100644 --- a/Bender.yml +++ b/Bender.yml @@ -28,12 +28,15 @@ dependencies: timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "pulpissimo-v3.4.0-rev4"} + cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: "9b7d500" } # michaero/safety-island ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", version: 1.1.0} hwpe-datamover-example: { git: "https://github.com/pulp-platform/hwpe-datamover-example.git", version: 1.0.1 } hci: { git: "https://github.com/pulp-platform/hci.git", version: 1.0.8 } +export_include_dirs: + - include + sources: # Source files grouped in levels. Files in level 0 have no dependencies on files in this # package. Files in level 1 only depend on files in level 0, files in level 2 on files in diff --git a/include/cluster_bus_defines.sv b/include/cluster_bus_defines.sv index 9306c090..487e2629 100644 --- a/include/cluster_bus_defines.sv +++ b/include/cluster_bus_defines.sv @@ -26,7 +26,7 @@ `define MASTER_1_START_ADDR 32'h1020_0000 `define MASTER_1_END_ADDR 32'h103F_FFFF -`define TCDM_ASSIGN_MASTER(lhs, rhs) \ +`define TCDM_ASSIGN_MASTER(lhs, rhs) \ assign lhs.req = rhs.req; \ assign lhs.add = rhs.add; \ assign lhs.wen = rhs.wen; \ diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index 3cf9895d..42cafdaf 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -17,7 +17,6 @@ */ -`include "cluster_bus_defines.sv" `include "axi/assign.svh" `include "axi/typedef.svh" @@ -26,17 +25,17 @@ module cluster_bus_wrap import axi_pkg::xbar_cfg_t; import pulp_cluster_package::addr_map_rule_t; #( - parameter NB_CORES = 4 , - parameter AXI_ADDR_WIDTH = 32, - parameter AXI_DATA_WIDTH = 64, - parameter AXI_ID_IN_WIDTH = 4 , - parameter AXI_ID_OUT_WIDTH = 6 , - parameter AXI_USER_WIDTH = 6 , - parameter DMA_NB_OUTSND_BURSTS = 8 , - parameter TCDM_SIZE = 0 - -) -( + parameter int unsigned NB_MASTER = 3 , + parameter int unsigned NB_SLAVE = 4 , + parameter int unsigned NB_CORES = 4 , + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 64, + parameter int unsigned AXI_ID_IN_WIDTH = 4 , + parameter int unsigned AXI_ID_OUT_WIDTH = 6 , + parameter int unsigned AXI_USER_WIDTH = 6 , + parameter int unsigned DMA_NB_OUTSND_BURSTS = 8 , + parameter int unsigned TCDM_SIZE = 0 +)( input logic clk_i, input logic rst_ni, input logic test_en_i, @@ -52,10 +51,6 @@ module cluster_bus_wrap ); - localparam NB_MASTER = `NB_MASTER; - localparam NB_SLAVE = `NB_SLAVE; - - //Ensure that AXI_ID out width has the correct size with an elaboration system task if (AXI_ID_OUT_WIDTH < AXI_ID_IN_WIDTH + $clog2(NB_SLAVE)) $error("ID width of AXI output ports is to small. The output id width must be input ID width + clog2() which is %d but it was %d", AXI_ID_IN_WIDTH + $clog2(NB_SLAVE), AXI_ID_OUT_WIDTH); diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index 1e32a79d..07fd047c 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -13,8 +13,7 @@ * (http://www.pulp-platform.org), under the copyright of ETH Zurich and the * University of Bologna. */ - -`include "pulp_soc_defines.sv" + import hci_package::*; @@ -38,6 +37,7 @@ module cluster_interconnect_wrap parameter LOG_CLUSTER = 5, parameter PE_ROUTING_LSB = 16, parameter PE_ROUTING_MSB = PE_ROUTING_LSB+$clog2(NB_SPERIPHS)-1, //differ + parameter CLUSTER_ALIAS = 1, parameter CLUSTER_ALIAS_BASE = 12'h000, parameter USE_HETEROGENEOUS_INTERCONNECT = 1 @@ -173,6 +173,7 @@ module cluster_interconnect_wrap .BE_WIDTH ( BE_WIDTH ), .PE_ROUTING_LSB ( PE_ROUTING_LSB ), .PE_ROUTING_MSB ( PE_ROUTING_MSB ), + .CLUSTER_ALIAS ( CLUSTER_ALIAS ), .CLUSTER_ALIAS_BASE ( CLUSTER_ALIAS_BASE ) ) xbar_pe_inst diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index 6fe4d653..2d2b6001 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -18,7 +18,6 @@ import pulp_cluster_package::*; -`include "pulp_soc_defines.sv" module cluster_peripherals #( diff --git a/rtl/core_demux.sv b/rtl/core_demux.sv index cec08d0a..0a9b864c 100644 --- a/rtl/core_demux.sv +++ b/rtl/core_demux.sv @@ -13,24 +13,21 @@ * (http://www.pulp-platform.org), under the copyright of ETH Zurich and the * University of Bologna. */ - -`include "pulp_soc_defines.sv" -//`define PERF_CNT + module core_demux #( parameter ADDR_WIDTH = 32, parameter DATA_WIDTH = 32, parameter BYTE_ENABLE_BIT = DATA_WIDTH/8, + parameter REMAP_ADDRESS = 0, parameter CLUSTER_ALIAS_BASE = 12'h000 ) ( input logic clk, input logic rst_ni, input logic test_en_i, -`ifdef REMAP_ADDRESS input logic [3:0] base_addr_i, -`endif // CORE SIDE input logic data_req_i, @@ -153,7 +150,7 @@ module core_demux assign data_add_int[27:0] = data_add_i[27:0]; -`ifdef REMAP_ADDRESS +if (REMAP_ADDRESS) begin always_comb begin if(data_add_i[31:28] == base_addr_i) @@ -169,9 +166,9 @@ module core_demux data_add_int[31:28] = data_add_i[31:28]; end end -`else +end else begin assign data_add_int[31:28] = data_add_i[31:28]; -`endif +end //******************************************************** //************** LEVEL 1 REQUEST ARBITER ***************** diff --git a/rtl/core_region.sv b/rtl/core_region.sv index aae0bd35..32840029 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -16,10 +16,6 @@ * Francesco Conti */ -`include "pulp_soc_defines.sv" -`include "periph_bus_defines.sv" - - // USER DEFINED MACROS to improve self-testing capabilities `ifndef PULP_FPGA_SIM `define DEBUG_FETCH_INTERFACE @@ -52,7 +48,7 @@ module core_region parameter SHARED_FP = 0, parameter SHARED_FP_DIVSQRT = 0, - parameter DEBUG_START_ADDR = `DEBUG_START_ADDR, + parameter DEBUG_START_ADDR = 32'h1A110000, parameter L2_SLM_FILE = "./slm_files/l2_stim.slm", parameter ROM_SLM_FILE = "../sw/apps/boot/slm_files/l2_stim.slm" @@ -434,14 +430,13 @@ module core_region .ADDR_WIDTH ( 32 ), .DATA_WIDTH ( 32 ), .BYTE_ENABLE_BIT ( DATA_WIDTH/8 ), + .REMAP_ADDRESS ( REMAP_ADDRESS ), .CLUSTER_ALIAS_BASE ( CLUSTER_ALIAS_BASE ) ) core_demux_i ( .clk ( clk_int ), .rst_ni ( rst_ni ), .test_en_i ( test_mode_i ), - `ifdef REMAP_ADDRESS .base_addr_i ( base_addr_i ), -`endif .data_req_i ( s_core_bus.req ), .data_add_i ( s_core_bus.add ), .data_wen_i ( ~s_core_bus.we ), //inverted when using OR10N diff --git a/rtl/periph_demux.sv b/rtl/periph_demux.sv index 8e5c559b..19d8e2ae 100644 --- a/rtl/periph_demux.sv +++ b/rtl/periph_demux.sv @@ -16,7 +16,6 @@ * Francesco Conti */ -`include "pulp_soc_defines.sv" module periph_demux #( diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index cabbca77..3570a9aa 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -17,16 +17,13 @@ * Angelo Garofalo */ -import pulp_cluster_package::*; -import hci_package::*; - -`include "pulp_soc_defines.sv" -`include "cluster_bus_defines.sv" `include "axi/typedef.svh" `include "axi/assign.svh" - +`include "cluster_bus_defines.sv" module pulp_cluster + import pulp_cluster_package::*; + import hci_package::*; #( // cluster parameters parameter CORE_TYPE_CL = 0, // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) @@ -35,10 +32,11 @@ module pulp_cluster // number of DMA TCDM plugs, NOT number of DMA slave peripherals! // Everything will go to hell if you change this! parameter NB_DMAS = 4, - parameter NB_MPERIPHS = NB_MPERIPHS, - parameter NB_SPERIPHS = NB_SPERIPHS, - - parameter CLUSTER_ALIAS_BASE = 12'h000, + parameter NB_MPERIPHS = 1, + parameter NB_SPERIPHS = 10, + + parameter CLUSTER_ALIAS = 1, + parameter CLUSTER_ALIAS_BASE = 12'h000, parameter TCDM_SIZE = 64*1024, // [B], must be 2**N parameter NB_TCDM_BANKS = 16, // must be 2**N @@ -71,6 +69,7 @@ module pulp_cluster parameter USE_REDUCED_TAG = "TRUE", // core parameters + parameter DEBUG_START_ADDR = 32'h1A110000, parameter ROM_BOOT_ADDR = 32'h1A000000, parameter BOOT_ADDR = 32'h1C000000, parameter INSTR_RDATA_WIDTH = 32, @@ -81,6 +80,8 @@ module pulp_cluster parameter CLUST_SHARED_FP_DIVSQRT = 2, // AXI parameters + parameter int unsigned NumAxiMst = 3 , + parameter int unsigned NumAxiSlv = 4 , parameter AXI_ADDR_WIDTH = 32, parameter AXI_DATA_C2S_WIDTH = 64, parameter AXI_DATA_S2C_WIDTH = 32, @@ -134,7 +135,7 @@ module pulp_cluster parameter PE_ROUTING_LSB = 10, // LSB used as routing BIT in periph interco // parameter PE_ROUTING_MSB = 13, // MSB used as routing BIT in periph interco parameter EVNT_WIDTH = 8, // size of the event bus - parameter REMAP_ADDRESS = 1, // for cluster virtualization + parameter REMAP_ADDRESS = 0, // for cluster virtualization localparam ASYNC_EVENT_DATA_WIDTH = (2**LOG_DEPTH)*EVNT_WIDTH, // FPU PARAMETERS @@ -549,6 +550,8 @@ module pulp_cluster /* cluster bus and attached peripherals */ cluster_bus_wrap #( + .NumAxiMst ( NumAxiMst ), + .NumAxiSlv ( NumAxiSlv ), .NB_CORES ( NB_CORES ), .DMA_NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), .TCDM_SIZE ( TCDM_SIZE ), @@ -610,30 +613,8 @@ module pulp_cluster .masters ( s_mperiph_demux_bus ) ); - `TCDM_ASSIGN_MASTER (s_mperiph_xbar_bus[`NB_MPERIPHS-1], s_mperiph_demux_bus[0]) - - // assign s_mperiph_xbar_bus[NB_MPERIPHS-1].req = s_mperiph_demux_bus[0].req; - // assign s_mperiph_xbar_bus[NB_MPERIPHS-1].add = s_mperiph_demux_bus[0].add; - // assign s_mperiph_xbar_bus[NB_MPERIPHS-1].wen = s_mperiph_demux_bus[0].wen; - // assign s_mperiph_xbar_bus[NB_MPERIPHS-1].wdata = s_mperiph_demux_bus[0].wdata; - // assign s_mperiph_xbar_bus[NB_MPERIPHS-1].be = s_mperiph_demux_bus[0].be; - - // assign s_mperiph_demux_bus[0].gnt = s_mperiph_xbar_bus[NB_MPERIPHS-1].gnt; - // assign s_mperiph_demux_bus[0].r_valid = s_mperiph_xbar_bus[NB_MPERIPHS-1].r_valid; - // assign s_mperiph_demux_bus[0].r_opc = s_mperiph_xbar_bus[NB_MPERIPHS-1].r_opc; - // assign s_mperiph_demux_bus[0].r_rdata = s_mperiph_xbar_bus[NB_MPERIPHS-1].r_rdata; - -/* not used in vega - per_demux_wrap #( - .NB_MASTERS ( NB_CORES ), - .ADDR_OFFSET ( 15 ) - ) debug_interconect_i ( - .clk_i ( clk_cluster ), - .rst_ni ( rst_ni ), - .slave ( s_mperiph_demux_bus[1] ), - .masters ( s_debug_bus ) - ); - */ + `TCDM_ASSIGN_MASTER (s_mperiph_xbar_bus[NB_MPERIPHS-1], s_mperiph_demux_bus[0]) + per2axi_wrap #( .NB_CORES ( NB_CORES ), .PER_ADDR_WIDTH ( 32 ), @@ -674,6 +655,7 @@ module pulp_cluster .LOG_CLUSTER ( LOG_CLUSTER ), .PE_ROUTING_LSB ( PE_ROUTING_LSB ), + .CLUSTER_ALIAS ( CLUSTER_ALIAS ), .USE_HETEROGENEOUS_INTERCONNECT ( USE_HETEROGENEOUS_INTERCONNECT ) ) cluster_interconnect_wrap_i ( @@ -862,7 +844,7 @@ module pulp_cluster .WAPUTYPE ( WAPUTYPE ), //= 3, .APU_NDSFLAGS_CPU ( APU_NDSFLAGS_CPU ), //= 3, .APU_NUSFLAGS_CPU ( APU_NUSFLAGS_CPU ), //= 5, - + .DEBUG_START_ADDR ( DEBUG_START_ADDR ), .FPU ( CLUST_FPU ), .FP_DIVSQRT ( CLUST_FP_DIVSQRT ), .SHARED_FP ( CLUST_SHARED_FP ), diff --git a/rtl/xbar_pe_wrap.sv b/rtl/xbar_pe_wrap.sv index e7b93468..98887f60 100644 --- a/rtl/xbar_pe_wrap.sv +++ b/rtl/xbar_pe_wrap.sv @@ -22,7 +22,6 @@ Each rr_arb_tree performes arbitration using an internal round robin counter. For each Slave Port, there is a stream_mux to multiplex the NB_SPERIPH responses. */ -`include "pulp_soc_defines.sv" module xbar_pe_wrap import pulp_cluster_package::*; @@ -36,6 +35,7 @@ module xbar_pe_wrap parameter PE_ROUTING_LSB = 10, parameter PE_ROUTING_MSB = 13, parameter bit HWPE_PRESENT = 1'b1, + parameter CLUSTER_ALIAS = 1, parameter CLUSTER_ALIAS_BASE = 12'h000, parameter ADDREXT = 1'b0 ) @@ -47,13 +47,10 @@ module xbar_pe_wrap XBAR_TCDM_BUS.Slave mperiph_slave[NB_MPERIPHS-1:0] ); - logic cluster_alias; + logic cluster_alias; -`ifdef CLUSTER_ALIAS - assign cluster_alias=1'b1; -`else - assign cluster_alias=1'b0; -`endif + assign cluster_alias = (CLUSTER_ALIAS) ? 1'b1 : 1'b0; + localparam int unsigned PE_XBAR_N_INPS = NB_CORES + NB_MPERIPHS; localparam int unsigned PE_XBAR_N_OUPS = NB_SPERIPHS; typedef logic [ADDR_WIDTH-1:0] pe_addr_t; From 09da40b26082fcb3e3ffae06d4954dd590c669f0 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 17 Apr 2023 19:10:37 +0200 Subject: [PATCH 002/207] Updated core, fixed assertions and parameters. --- include/pulp_soc_defines.sv | 2 +- rtl/cluster_bus_wrap.sv | 8 +- rtl/core_region.sv | 158 +++++++++++++++++------------------- rtl/pulp_cluster.sv | 15 ++-- 4 files changed, 88 insertions(+), 95 deletions(-) diff --git a/include/pulp_soc_defines.sv b/include/pulp_soc_defines.sv index 49d9ad3d..5ad5c032 100644 --- a/include/pulp_soc_defines.sv +++ b/include/pulp_soc_defines.sv @@ -22,7 +22,7 @@ `define CLUSTER_ALIAS `define PRIVATE_ICACHE `define HIERARCHY_ICACHE_32BIT -`define SHARED_FPU_CLUSTER +// `define SHARED_FPU_CLUSTER `define FEATURE_ICACHE_STAT `define FC_FPU 1 diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index 42cafdaf..50f27a57 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -57,13 +57,13 @@ module cluster_bus_wrap else if (AXI_ID_OUT_WIDTH > AXI_ID_IN_WIDTH + $clog2(NB_SLAVE)) $warning("ID width of the AXI output port has the wrong length. It is larger than the required value. Trim it to the right length to get rid of this warning."); - if (AXI_ADDR_WIDTH != 32) - $fatal(1,"Address map is only defined for 32-bit addresses!"); + if (AXI_ADDR_WIDTH != 48) + $fatal(1,"Address map is only defined for 48-bit addresses!"); if (TCDM_SIZE == 0) $fatal(1,"TCDM size must be non-zero!"); - if (TCDM_SIZE >128*1024) + if (TCDM_SIZE >2048*1024) // Periph start address is at offset 0x0020_0000, which actually allows for up to 2 MiB of TCDM, + // do not know why to trigger te assertion for more than 128 KiB TCDM size... $fatal(1,"TCDM size exceeds available address space in cluster bus!"); - // Crossbar AXI_BUS #( diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 32840029..a44357df 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -30,6 +30,7 @@ module core_region // parameter USE_FPU = 1, // parameter USE_HWPE = 1, parameter N_EXT_PERF_COUNTERS = 1, + parameter NUM_INTERRUPTS = 32, parameter CORE_ID = 0, parameter ADDR_WIDTH = 32, parameter DATA_WIDTH = 32, @@ -85,11 +86,10 @@ module core_region input logic instr_r_valid_i, input logic debug_req_i, - - //XBAR_TCDM_BUS.Slave debug_bus, - //output logic debug_core_halted_o, - //input logic debug_core_halt_i, - //input logic debug_core_resume_i, + output logic debug_havereset_o, + output logic debug_running_o, + output logic debug_halted_o, + // input logic debug_core_resume_i, // Useful for HMR, consider keeping // Interface for DEMUX to TCDM INTERCONNECT ,PERIPHERAL INTERCONNECT and DMA CONTROLLER hci_core_intf.master tcdm_data_master, @@ -98,8 +98,8 @@ module core_region XBAR_PERIPH_BUS.Master periph_data_master // new interface signals - `ifdef SHARED_FPU_CLUSTER - // TODO: Ensure disable if CORE_TYPE_CL != 0 +`ifdef SHARED_FPU_CLUSTER +// TODO: Ensure disable if CORE_TYPE_CL != 0 , output logic apu_master_req_o, input logic apu_master_gnt_i, @@ -131,8 +131,6 @@ module core_region input logic [31:0] apu_master_result_i, input logic [APU_NUSFLAGS_CPU-1:0] apu_master_flags_i `endif - - ); localparam N_EXT_PERF_COUNTERS_ACTUAL = 5; @@ -156,11 +154,11 @@ module core_region XBAR_PERIPH_BUS periph_demux_bus(); // Internal interface between CORE_DEMUX <--> PERIPHERAL DEMUX logic [N_EXT_PERF_COUNTERS_ACTUAL-1:0] perf_counters; - logic clk_int; - logic [31:0] hart_id; - logic core_sleep; - logic [31:0] boot_addr; - logic [31:0] core_irq_x; + logic clk_int; + logic [31:0] hart_id; + logic core_sleep; + logic [31:0] boot_addr; + logic [NUM_INTERRUPTS-1:0] core_irq_x; logic core_instr_req; logic core_instr_gnt; @@ -210,74 +208,69 @@ module core_region generate if ( CORE_TYPE_CL == 0 ) begin: CL_CORE assign boot_addr = boot_addr_i; - riscv_core #( - .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), - .N_EXT_PERF_COUNTERS ( N_EXT_PERF_COUNTERS_ACTUAL ), - .PULP_SECURE ( 0 ), - .FPU ( FPU ), - .FP_DIVSQRT ( FP_DIVSQRT ), - .SHARED_FP ( SHARED_FP ), - .SHARED_DSP_MULT ( 0 ), - .SHARED_INT_DIV ( 0 ), - .SHARED_FP_DIVSQRT ( SHARED_FP_DIVSQRT ), - .WAPUTYPE ( WAPUTYPE ), - .DM_HaltAddress ( DEBUG_START_ADDR + 16'h0800 ) - + cv32e40p_core #( + // .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), + .PULP_XPULP ( 0 ), // For now this is a no + .PULP_CLUSTER ( 1 ), + .FPU ( FPU ), + .NUM_EXTERNAL_PERF ( N_EXT_PERF_COUNTERS_ACTUAL ), + .NUM_INTERRUPTS ( NUM_INTERRUPTS ), + .PULP_ZFINX ( 0 ) ) RISCV_CORE ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .clock_en_i ( clock_en_i ), - .test_en_i ( test_mode_i ), - - .boot_addr_i ( boot_addr ), - .core_id_i ( CORE_ID[3:0] ), - .cluster_id_i ( cluster_id_i ), - - .instr_addr_o ( instr_addr_o ), - .instr_req_o ( instr_req_o ), - .instr_rdata_i ( instr_r_rdata_i ), - .instr_gnt_i ( instr_gnt_i ), - .instr_rvalid_i ( instr_r_valid_i ), - - .data_addr_o ( s_core_bus.add ), - .data_wdata_o ( s_core_bus.wdata ), - .data_we_o ( s_core_bus.we ), - .data_req_o ( s_core_bus.req ), - .data_be_o ( s_core_bus.be ), - .data_rdata_i ( s_core_bus.r_rdata ), - .data_gnt_i ( s_core_bus.gnt ), - .data_rvalid_i ( s_core_bus.r_valid ), - - .irq_i ( irq_req_i ), - .irq_id_i ( irq_id_i ), - .irq_id_o ( irq_ack_id_o ), - .irq_ack_o ( irq_ack_o ), - - .sec_lvl_o ( ), - .irq_sec_i ( 1'b0 ), - - .debug_req_i ( debug_req_i ), - - .fetch_enable_i ( fetch_en_i ), - .core_busy_o ( core_busy_o ), - - - // apu-interconnect - .apu_master_req_o ( apu_master_req_o ), - .apu_master_gnt_i ( apu_master_gnt_i ), - .apu_master_type_o ( apu_master_type_o ), - .apu_master_operands_o ( apu_master_operands_o ), - .apu_master_op_o ( apu_master_op_o ), - .apu_master_flags_o ( apu_master_flags_o ), - - .apu_master_valid_i ( apu_master_valid_i ), - .apu_master_ready_o ( apu_master_ready_o ), - .apu_master_result_i ( apu_master_result_i ), - .apu_master_flags_i ( apu_master_flags_i ), - - .ext_perf_counters_i ( perf_counters ), - .fregfile_disable_i ( 1'b1 ) //disable FP regfile + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + // Control Interface + .pulp_clock_en_i ( clock_en_i ), + .scan_cg_en_i ( test_mode_i ), + .boot_addr_i ( boot_addr ), + .mtvec_addr_i ( '0 ), + .mtvt_addr_i ( '0 ), + .dm_halt_addr_i ( DEBUG_START_ADDR + 16'h0800 ), + .hart_id_i ( hart_id ), + .dm_exception_addr_i ( DEBUG_START_ADDR + 16'h080C ), // From Control PULP, to be checked + // Instruction Interface + .instr_addr_o ( instr_addr_o ), + .instr_req_o ( instr_req_o ), + .instr_rdata_i ( instr_r_rdata_i ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_r_valid_i ), + // Data Interface + .data_addr_o ( s_core_bus.add ), + .data_wdata_o ( s_core_bus.wdata ), + .data_we_o ( s_core_bus.we ), + .data_req_o ( s_core_bus.req ), + .data_be_o ( s_core_bus.be ), + .data_rdata_i ( s_core_bus.r_rdata ), + .data_gnt_i ( s_core_bus.gnt ), + .data_rvalid_i ( s_core_bus.r_valid ), + // apu-interconnect + // Handshake + .apu_req_o ( apu_master_req_o ), + .apu_gnt_i ( apu_master_gnt_i ), + // Request Bus + .apu_operands_o ( apu_master_operands_o ), + .apu_op_o ( apu_master_op_o ), + .apu_flags_o ( apu_master_flags_o ), + // Response Bus + .apu_rvalid_i ( apu_master_valid_i ), + .apu_result_i ( apu_master_result_i ), + .apu_flags_i ( apu_master_flags_i ), + // IRQ Interface + .irq_i ( core_irq_x ), + .irq_level_i ( '0 ), // CLIC interrupt level + .irq_shv_i ( '0 ), // CLIC selective hardware vectoring + .irq_ack_o ( irq_ack_o ), + .irq_id_o ( irq_ack_id_o ), + // Debug Interface + .debug_req_i ( debug_req_i ), + .debug_havereset_o ( debug_havereset_o ), + .debug_running_o ( debug_running_o ), + .debug_halted_o ( debug_halted_o ), + // Yet other control signals + .fetch_enable_i ( fetch_en_i ), + .core_sleep_o ( core_sleep ), + // External performance monitoring signals + .external_perf_i ( perf_counters ) ); end else begin: CL_CORE assign boot_addr = boot_addr_i & 32'hFFFFFF00; // RI5CY expects 0x80 offset, Ibex expects 0x00 offset (adds reset offset 0x80 internally) @@ -396,7 +389,6 @@ module core_region .alert_major_o (), .core_sleep_o ( core_sleep ) ); - assign core_busy_o = ~core_sleep; // Ibex supports 32 additional fast interrupts and reads the interrupt lines directly. // Convert ID back to interrupt lines @@ -420,6 +412,8 @@ module core_region // Performance Counters assign perf_counters[4] = tcdm_data_master.req & (~tcdm_data_master.gnt); // Cycles lost due to contention + // Core busy + assign core_busy_o = ~core_sleep; //******************************************************** //****** DEMUX TO TCDM AND PERIPHERAL INTERCONNECT ******* diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 3570a9aa..20619d2c 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -20,6 +20,7 @@ `include "axi/typedef.svh" `include "axi/assign.svh" `include "cluster_bus_defines.sv" +`include "pulp_interfaces.sv" module pulp_cluster import pulp_cluster_package::*; @@ -550,8 +551,8 @@ module pulp_cluster /* cluster bus and attached peripherals */ cluster_bus_wrap #( - .NumAxiMst ( NumAxiMst ), - .NumAxiSlv ( NumAxiSlv ), + .NB_MASTER ( NumAxiMst ), + .NB_SLAVE ( NumAxiSlv ), .NB_CORES ( NB_CORES ), .DMA_NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), .TCDM_SIZE ( TCDM_SIZE ), @@ -876,12 +877,10 @@ module pulp_cluster .instr_r_valid_i ( instr_r_valid[i] ), //debug unit bind - .debug_req_i ( s_core_dbg_irq[i] ), - //.debug_bus ( s_debug_bus[i] ), - //.debug_core_halted_o ( dbg_core_halted[i] ), - //.debug_core_halt_i ( dbg_core_halt[i] ), - //.debug_core_resume_i ( dbg_core_resume[i] ), - .tcdm_data_master ( s_hci_core[i] ), + .debug_req_i ( s_core_dbg_irq[i] ), + .debug_halted_o ( dbg_core_halted[i] ), + // .debug_resume_i ( dbg_core_resume[i] ), // Useful for HMR, consider keeping + .tcdm_data_master ( s_hci_core[i] ), //tcdm, dma ctrl unit, periph interco interfaces .dma_ctrl_master ( s_core_dmactrl_bus[i] ), From d8d9aa4c236d009593858595c1158d1f96b29a7d Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 17 Apr 2023 19:52:36 +0200 Subject: [PATCH 003/207] Allowed FPU instantiation via top-level parameter. --- include/pulp_soc_defines.sv | 1 - rtl/core_region.sv | 47 +----------- rtl/pulp_cluster.sv | 147 +++++++++++++++--------------------- 3 files changed, 61 insertions(+), 134 deletions(-) diff --git a/include/pulp_soc_defines.sv b/include/pulp_soc_defines.sv index 5ad5c032..fd5d065e 100644 --- a/include/pulp_soc_defines.sv +++ b/include/pulp_soc_defines.sv @@ -22,7 +22,6 @@ `define CLUSTER_ALIAS `define PRIVATE_ICACHE `define HIERARCHY_ICACHE_32BIT -// `define SHARED_FPU_CLUSTER `define FEATURE_ICACHE_STAT `define FC_FPU 1 diff --git a/rtl/core_region.sv b/rtl/core_region.sv index a44357df..e37edd2a 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -95,12 +95,8 @@ module core_region hci_core_intf.master tcdm_data_master, XBAR_TCDM_BUS.Master dma_ctrl_master, XBAR_PERIPH_BUS.Master eu_ctrl_master, - XBAR_PERIPH_BUS.Master periph_data_master + XBAR_PERIPH_BUS.Master periph_data_master, - // new interface signals -`ifdef SHARED_FPU_CLUSTER -// TODO: Ensure disable if CORE_TYPE_CL != 0 - , output logic apu_master_req_o, input logic apu_master_gnt_i, // request channel @@ -113,24 +109,6 @@ module core_region input logic apu_master_valid_i, input logic [31:0] apu_master_result_i, input logic [APU_NUSFLAGS_CPU-1:0] apu_master_flags_i -`endif - -`ifdef APU_CLUSTER - // TODO: Ensure disable if CORE_TYPE_CL != 0 - , - output logic apu_master_req_o, - input logic apu_master_gnt_i, - // request channel - output logic [WAPUTYPE-1:0] apu_master_type_o, - output logic [APU_NARGS_CPU-1:0][31:0] apu_master_operands_o, - output logic [APU_WOP_CPU-1:0] apu_master_op_o, - output logic [APU_NDSFLAGS_CPU-1:0] apu_master_flags_o, - // response channel - output logic apu_master_ready_o, - input logic apu_master_valid_i, - input logic [31:0] apu_master_result_i, - input logic [APU_NUSFLAGS_CPU-1:0] apu_master_flags_i -`endif ); localparam N_EXT_PERF_COUNTERS_ACTUAL = 5; @@ -178,29 +156,6 @@ module core_region assign hart_id = {21'b0, cluster_id_i[5:0], 1'b0, CORE_ID[3:0]}; -`ifndef APU_CLUSTER - `ifndef SHARED_FPU_CLUSTER - // TODO: Disable if CORE_TYPE_CL != 0 - logic apu_master_req_o; - logic apu_master_gnt_i; - // request channel - logic [WAPUTYPE-1:0] apu_master_type_o; - logic [APU_NARGS_CPU-1:0][31:0] apu_master_operands_o; - logic [APU_WOP_CPU-1:0] apu_master_op_o; - logic [APU_NDSFLAGS_CPU-1:0] apu_master_flags_o; - // response channel - logic apu_master_ready_o; - logic apu_master_valid_i; - logic [31:0] apu_master_result_i; - logic [APU_NUSFLAGS_CPU-1:0] apu_master_flags_i; - - assign apu_master_gnt_i = '1; - assign apu_master_valid_i = '0; - assign apu_master_result_i = '0; - assign apu_master_flags_i = '0; - `endif -`endif - //******************************************************** //***************** PROCESSOR **************************** //******************************************************** diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 20619d2c..1c812023 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -409,7 +409,6 @@ module pulp_cluster XBAR_PERIPH_BUS s_core_euctrl_bus[NB_CORES-1:0](); -`ifdef SHARED_FPU_CLUSTER // apu-interconnect // handshake signals logic [NB_CORES-1:0] s_apu_master_req; @@ -424,7 +423,6 @@ module pulp_cluster logic [NB_CORES-1:0] s_apu_master_rvalid; logic [NB_CORES-1:0][31:0] s_apu_master_rdata; logic [NB_CORES-1:0][APU_NUSFLAGS_CPU-1:0] s_apu_master_rflags; -`endif //----------------------------------------------------------------------// // Interfaces between ICache - L0 - Icache_Interco and Icache_ctrl_unit // @@ -831,7 +829,6 @@ module pulp_cluster .serial_o(s_dbg_irq[i]) ); - core_region #( .CORE_TYPE_CL ( CORE_TYPE_CL ), .CORE_ID ( i ), @@ -887,9 +884,7 @@ module pulp_cluster .eu_ctrl_master ( s_core_euctrl_bus[i] ), .periph_data_master ( s_core_periph_bus[i] ), - .fregfile_disable_i ( s_fregfile_disable ) -`ifdef SHARED_FPU_CLUSTER - , + .fregfile_disable_i ( s_fregfile_disable ), .apu_master_req_o ( s_apu_master_req [i] ), .apu_master_gnt_i ( s_apu_master_gnt [i] ), .apu_master_type_o ( s_apu_master_type [i] ), @@ -900,44 +895,14 @@ module pulp_cluster .apu_master_ready_o ( s_apu_master_rready [i] ), .apu_master_result_i ( s_apu_master_rdata [i] ), .apu_master_flags_i ( s_apu_master_rflags [i] ) -`endif ); end endgenerate -//********************************************** -//**** APU cluster - Shared execution units **** -//********************************************** - -`ifdef APU_CLUSTER - - apu_cluster #( - .C_NB_CORES ( NB_CORES ), - .NDSFLAGS_CPU ( APU_NDSFLAGS_CPU ), - .NUSFLAGS_CPU ( APU_NUSFLAGS_CPU ), - .WOP_CPU ( APU_WOP_CPU ), - .NARGS_CPU ( APU_NARGS_CPU ), - .WAPUTYPE ( WAPUTYPE ), - .SHARED_FP ( CLUST_SHARED_FP ), - .SHARED_DSP_MULT ( 0 ), - .SHARED_INT_MULT ( 0 ), - .SHARED_INT_DIV ( 0 ), - .SHARED_FP_DIVSQRT ( CLUST_SHARED_FP_DIVSQRT ) - ) apu_cluster_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .cpus ( s_apu_cluster_bus ) - ); - -`endif - - - //**************************************************** - //**** Shared FPU cluster - Shared execution units *** - //**************************************************** - -`ifdef SHARED_FPU_CLUSTER +//**************************************************** +//**** Shared FPU cluster - Shared execution units *** +//**************************************************** // request channel logic [NB_CORES-1:0][2:0][31:0] s_apu__operands; @@ -957,54 +922,62 @@ module pulp_cluster assign s_apu_master_rflags[k][4:0] = s_apu__rflags[k][4:0]; end - shared_fpu_cluster #( - .NB_CORES ( NB_CORES ), - .NB_APUS ( 1 ), - .NB_FPNEW ( 4 ), - .FP_TYPE_WIDTH ( 3 ), - - .NB_CORE_ARGS ( 3 ), - .CORE_DATA_WIDTH ( 32 ), - .CORE_OPCODE_WIDTH ( 6 ), - .CORE_DSFLAGS_CPU ( 15 ), - .CORE_USFLAGS_CPU ( 5 ), - - .NB_APU_ARGS ( 2 ), - .APU_OPCODE_WIDTH ( 6 ), - .APU_DSFLAGS_CPU ( 15 ), - .APU_USFLAGS_CPU ( 5 ), - - .NB_FPNEW_ARGS ( 3 ), //= 3, - .FPNEW_OPCODE_WIDTH ( 6 ), //= 6, - .FPNEW_DSFLAGS_CPU ( 15 ), //= 15, - .FPNEW_USFLAGS_CPU ( 5 ), //= 5, - - .APUTYPE_ID ( 1 ), - .FPNEWTYPE_ID ( 0 ), - - .C_FPNEW_FMTBITS (fpnew_pkg::FP_FORMAT_BITS ), - .C_FPNEW_IFMTBITS (fpnew_pkg::INT_FORMAT_BITS ), - .C_ROUND_BITS (3 ), - .C_FPNEW_OPBITS (fpnew_pkg::OP_BITS ), - .USE_FPU_OPT_ALLOC ("FALSE"), - .USE_FPNEW_OPT_ALLOC ("TRUE"), - .FPNEW_INTECO_TYPE ("SINGLE_INTERCO") - ) i_shared_fpu_cluster ( - .clk ( clk_cluster ), - .rst_n ( s_rst_n ), - .test_mode_i ( test_mode_i ), - .core_slave_req_i ( s_apu_master_req ), - .core_slave_gnt_o ( s_apu_master_gnt ), - .core_slave_type_i ( s_apu__type ), - .core_slave_operands_i ( s_apu__operands ), - .core_slave_op_i ( s_apu__op ), - .core_slave_flags_i ( s_apu__flags ), - .core_slave_rready_i ( s_apu_master_rready ), - .core_slave_rvalid_o ( s_apu_master_rvalid ), - .core_slave_rdata_o ( s_apu_master_rdata ), - .core_slave_rflags_o ( s_apu__rflags ) - ); -`endif +generate + if (CLUST_FPU) begin + shared_fpu_cluster #( + .NB_CORES ( NB_CORES ), + .NB_APUS ( 1 ), + .NB_FPNEW ( 4 ), + .FP_TYPE_WIDTH ( 3 ), + + .NB_CORE_ARGS ( 3 ), + .CORE_DATA_WIDTH ( 32 ), + .CORE_OPCODE_WIDTH ( 6 ), + .CORE_DSFLAGS_CPU ( 15 ), + .CORE_USFLAGS_CPU ( 5 ), + + .NB_APU_ARGS ( 2 ), + .APU_OPCODE_WIDTH ( 6 ), + .APU_DSFLAGS_CPU ( 15 ), + .APU_USFLAGS_CPU ( 5 ), + + .NB_FPNEW_ARGS ( 3 ), //= 3, + .FPNEW_OPCODE_WIDTH ( 6 ), //= 6, + .FPNEW_DSFLAGS_CPU ( 15 ), //= 15, + .FPNEW_USFLAGS_CPU ( 5 ), //= 5, + + .APUTYPE_ID ( 1 ), + .FPNEWTYPE_ID ( 0 ), + + .C_FPNEW_FMTBITS (fpnew_pkg::FP_FORMAT_BITS ), + .C_FPNEW_IFMTBITS (fpnew_pkg::INT_FORMAT_BITS ), + .C_ROUND_BITS (3 ), + .C_FPNEW_OPBITS (fpnew_pkg::OP_BITS ), + .USE_FPU_OPT_ALLOC ("FALSE"), + .USE_FPNEW_OPT_ALLOC ("TRUE"), + .FPNEW_INTECO_TYPE ("SINGLE_INTERCO") + ) i_shared_fpu_cluster ( + .clk ( clk_cluster ), + .rst_n ( s_rst_n ), + .test_mode_i ( test_mode_i ), + .core_slave_req_i ( s_apu_master_req ), + .core_slave_gnt_o ( s_apu_master_gnt ), + .core_slave_type_i ( s_apu__type ), + .core_slave_operands_i ( s_apu__operands ), + .core_slave_op_i ( s_apu__op ), + .core_slave_flags_i ( s_apu__flags ), + .core_slave_rready_i ( s_apu_master_rready ), + .core_slave_rvalid_o ( s_apu_master_rvalid ), + .core_slave_rdata_o ( s_apu_master_rdata ), + .core_slave_rflags_o ( s_apu__rflags ) + ); + end else begin + assign s_apu_master_gnt = '0; + assign s_apu_master_rvalid = '0; + assign s_apu_master_rdata = '0; + assign s_apu__rflags = '0; + end +endgenerate //************************************************************** //**** HW Processing Engines / Cluster-Coupled Accelerators **** From b318463fa740e3939627e9b734c2f422705bf943 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 17 Apr 2023 20:02:03 +0200 Subject: [PATCH 004/207] Indentation. --- rtl/pulp_cluster.sv | 1690 +++++++++++++++++++++---------------------- 1 file changed, 835 insertions(+), 855 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 1c812023..b4547235 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -256,539 +256,535 @@ module pulp_cluster localparam bit FEATURE_STAT = 1'b0; `endif +//******************************************************** +//***************** SIGNALS DECLARATION ****************** +//******************************************************** + +logic [NB_CORES-1:0] fetch_enable_reg_int; +logic [NB_CORES-1:0] fetch_en_int; +logic s_rst_n; +logic s_init_n; +logic [NB_CORES-1:0][31:0] boot_addr; +logic [NB_CORES-1:0] dbg_core_halt; +logic [NB_CORES-1:0] dbg_core_resume; +logic [NB_CORES-1:0] dbg_core_halted; +logic [NB_CORES-1:0] s_dbg_irq; +logic s_hwpe_en; + +logic s_cluster_periphs_busy; +logic s_axi2mem_busy; +logic s_per2axi_busy; +logic s_axi2per_busy; +logic s_dmac_busy; +logic s_cluster_cg_en; +logic [NB_CORES-1:0] s_dma_event; +logic [NB_CORES-1:0] s_dma_irq; +logic [NB_CORES-1:0][3:0] s_hwpe_remap_evt; +logic [NB_CORES-1:0][1:0] s_hwpe_evt; +logic s_hwpe_busy; +hci_package::hci_interconnect_ctrl_t s_hci_ctrl; + +logic [NB_CORES-1:0] clk_core_en; +logic clk_cluster; + +// CLK reset, and other control signals + +logic s_cluster_int_busy; +logic s_fregfile_disable; + +logic [NB_CORES-1:0] core_busy; + +logic s_incoming_req; +logic s_isolate_cluster; +logic s_events_async; + +logic s_events_valid; +logic s_events_ready; +logic [EVNT_WIDTH-1:0] s_events_data; + +// Signals Between CORE_ISLAND and INSTRUCTION CACHES +logic [NB_CORES-1:0] instr_req; +logic [NB_CORES-1:0][31:0] instr_addr; +logic [NB_CORES-1:0] instr_gnt; +logic [NB_CORES-1:0] instr_r_valid; +logic [NB_CORES-1:0][INSTR_RDATA_WIDTH-1:0] instr_r_rdata; + +logic [1:0] s_TCDM_arb_policy; +logic tcdm_sleep; + +logic s_dma_pe_event; +logic s_dma_pe_irq; +logic s_pf_event; + +logic[NB_CORES-1:0][4:0] irq_id; +logic[NB_CORES-1:0][4:0] irq_ack_id; +logic[NB_CORES-1:0] irq_req; +logic[NB_CORES-1:0] irq_ack; + +logic [NB_CORES-1:0] s_core_dbg_irq; + + +logic [NB_L1_CUTS-1:0][RW_MARGIN_WIDTH-1:0] s_rw_margin_L1; + +logic s_dma_cl_event; +logic s_dma_cl_irq; +logic s_dma_fc_event; +logic s_dma_fc_irq; + - //******************************************************** - //***************** SIGNALS DECLARATION ****************** - //******************************************************** - - - logic [NB_CORES-1:0] fetch_enable_reg_int; - logic [NB_CORES-1:0] fetch_en_int; - logic s_rst_n; - logic s_init_n; - logic [NB_CORES-1:0][31:0] boot_addr; - logic [NB_CORES-1:0] dbg_core_halt; - logic [NB_CORES-1:0] dbg_core_resume; - logic [NB_CORES-1:0] dbg_core_halted; - logic [NB_CORES-1:0] s_dbg_irq; - logic s_hwpe_en; - - logic s_cluster_periphs_busy; - logic s_axi2mem_busy; - logic s_per2axi_busy; - logic s_axi2per_busy; - logic s_dmac_busy; - logic s_cluster_cg_en; - logic [NB_CORES-1:0] s_dma_event; - logic [NB_CORES-1:0] s_dma_irq; - logic [NB_CORES-1:0][3:0] s_hwpe_remap_evt; - logic [NB_CORES-1:0][1:0] s_hwpe_evt; - logic s_hwpe_busy; - hci_package::hci_interconnect_ctrl_t s_hci_ctrl; - - logic [NB_CORES-1:0] clk_core_en; - logic clk_cluster; - - // CLK reset, and other control signals - - logic s_cluster_int_busy; - logic s_fregfile_disable; - - logic [NB_CORES-1:0] core_busy; - - logic s_incoming_req; - logic s_isolate_cluster; - logic s_events_async; - - logic s_events_valid; - logic s_events_ready; - logic [EVNT_WIDTH-1:0] s_events_data; - - // Signals Between CORE_ISLAND and INSTRUCTION CACHES - logic [NB_CORES-1:0] instr_req; - logic [NB_CORES-1:0][31:0] instr_addr; - logic [NB_CORES-1:0] instr_gnt; - logic [NB_CORES-1:0] instr_r_valid; - logic [NB_CORES-1:0][INSTR_RDATA_WIDTH-1:0] instr_r_rdata; - - logic [1:0] s_TCDM_arb_policy; - logic tcdm_sleep; - - logic s_dma_pe_event; - logic s_dma_pe_irq; - logic s_pf_event; - - logic[NB_CORES-1:0][4:0] irq_id; - logic[NB_CORES-1:0][4:0] irq_ack_id; - logic[NB_CORES-1:0] irq_req; - logic[NB_CORES-1:0] irq_ack; +logic s_dma_decompr_event; +logic s_dma_decompr_irq; - logic [NB_CORES-1:0] s_core_dbg_irq; +logic s_decompr_done_evt; - - logic [NB_L1_CUTS-1:0][RW_MARGIN_WIDTH-1:0] s_rw_margin_L1; +assign s_dma_fc_irq = s_decompr_done_evt; - logic s_dma_cl_event; - logic s_dma_cl_irq; - logic s_dma_fc_event; - logic s_dma_fc_irq; - - - logic s_dma_decompr_event; - logic s_dma_decompr_irq; - logic s_decompr_done_evt; - assign s_dma_fc_irq = s_decompr_done_evt; +/* logarithmic and peripheral interconnect interfaces */ +// ext -> log interconnect +hci_core_intf #( + .DW ( DATA_WIDTH ), + .AW ( ADDR_WIDTH ), + .OW ( 1 ) +) s_hci_ext[NB_DMAS-1:0] ( + .clk ( clk_cluster ) +); +// periph interconnect -> slave peripherals +XBAR_PERIPH_BUS s_xbar_speriph_bus[NB_SPERIPHS-1:0](); +// periph interconnect -> HWPE subsystem +XBAR_PERIPH_BUS s_hwpe_cfg_bus(); - /* logarithmic and peripheral interconnect interfaces */ - // ext -> log interconnect - hci_core_intf #( - .DW ( DATA_WIDTH ), - .AW ( ADDR_WIDTH ), - .OW ( 1 ) - ) s_hci_ext[NB_DMAS-1:0] ( - .clk ( clk_cluster ) - ); +// DMA -> log interconnect +hci_core_intf #( + .DW ( DATA_WIDTH ), + .AW ( ADDR_WIDTH ), + .OW ( 1 ) +) s_hci_dma[NB_DMAS-1:0] ( + .clk ( clk_cluster ) +); +XBAR_TCDM_BUS s_dma_plugin_xbar_bus[NB_DMAS-1:0](); + +// ext -> xbar periphs FIXME +XBAR_TCDM_BUS s_mperiph_xbar_bus[NB_MPERIPHS-1:0](); + +// periph demux +XBAR_TCDM_BUS s_mperiph_bus(); +XBAR_TCDM_BUS s_mperiph_demux_bus[1:0](); + +// cores & accelerators -> log interconnect +hci_core_intf #( + .DW ( NB_HWPE_PORTS*DATA_WIDTH ), + .AW ( ADDR_WIDTH ), + .OW ( 1 ) +) s_hci_hwpe [0:0] ( + .clk ( clk_cluster ) +); +hci_core_intf #( + .DW ( DATA_WIDTH ), + .AW ( ADDR_WIDTH ), + .OW ( 1 ) +) s_hci_core [NB_CORES-1:0] ( + .clk ( clk_cluster ) +); - // periph interconnect -> slave peripherals - XBAR_PERIPH_BUS s_xbar_speriph_bus[NB_SPERIPHS-1:0](); +// cores -> periph interconnect +XBAR_PERIPH_BUS s_core_periph_bus[NB_CORES-1:0](); + +// periph interconnect -> DMA +XBAR_PERIPH_BUS s_periph_dma_bus[1:0](); + +// debug +XBAR_TCDM_BUS s_debug_bus[NB_CORES-1:0](); + +/* other interfaces */ +// cores -> DMA ctrl +XBAR_TCDM_BUS s_core_dmactrl_bus[NB_CORES-1:0](); + +// cores -> event unit ctrl +XBAR_PERIPH_BUS s_core_euctrl_bus[NB_CORES-1:0](); + + +// apu-interconnect +// handshake signals +logic [NB_CORES-1:0] s_apu_master_req; +logic [NB_CORES-1:0] s_apu_master_gnt; +// request channel +logic [NB_CORES-1:0][APU_NARGS_CPU-1:0][31:0] s_apu_master_operands; +logic [NB_CORES-1:0][APU_WOP_CPU-1:0] s_apu_master_op; +logic [NB_CORES-1:0][WAPUTYPE-1:0] s_apu_master_type; +logic [NB_CORES-1:0][APU_NDSFLAGS_CPU-1:0] s_apu_master_flags; +// response channel +logic [NB_CORES-1:0] s_apu_master_rready; +logic [NB_CORES-1:0] s_apu_master_rvalid; +logic [NB_CORES-1:0][31:0] s_apu_master_rdata; +logic [NB_CORES-1:0][APU_NUSFLAGS_CPU-1:0] s_apu_master_rflags; + +//----------------------------------------------------------------------// +// Interfaces between ICache - L0 - Icache_Interco and Icache_ctrl_unit // +// // +`ifdef PRIVATE_ICACHE + SP_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_main[NB_CACHE_BANKS](); + PRI_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_pri[NB_CORES](); + logic s_special_core_icache_cfg; + logic[NB_CORES-1:0] s_enable_l1_l15_prefetch; - // periph interconnect -> HWPE subsystem - XBAR_PERIPH_BUS s_hwpe_cfg_bus(); +`else + `ifdef SP_ICACHE + SP_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus[NB_CACHE_BANKS](); + L0_CTRL_UNIT_BUS L0_ctrl_unit_bus[NB_CORES](); + `else + `ifdef MP_ICACHE + MP_PF_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus(); + `endif + `endif +`endif +//----------------------------------------------------------------------// + +localparam TCDM_ID_WIDTH = NB_CORES+NB_DMAS+4+NB_HWPE_PORTS; + +// log interconnect -> TCDM memory banks (SRAM) +hci_mem_intf #( + .AW (ADDR_WIDTH ), + .DW ( DATA_WIDTH ), + .BW ( 8 ), + .IW ( TCDM_ID_WIDTH ) +) s_tcdm_bus_sram[NB_TCDM_BANKS-1:0] ( + .clk ( clk_cluster ) +); - // DMA -> log interconnect - hci_core_intf #( - .DW ( DATA_WIDTH ), - .AW ( ADDR_WIDTH ), - .OW ( 1 ) - ) s_hci_dma[NB_DMAS-1:0] ( - .clk ( clk_cluster ) - ); - XBAR_TCDM_BUS s_dma_plugin_xbar_bus[NB_DMAS-1:0](); +//*************************************************** +/* synchronous AXI interfaces at CLUSTER/SOC interface */ +//*************************************************** +AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) +) s_data_slave_64(); + +AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) +) s_data_slave_32(); + +AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) +) s_data_master(); + +AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) +) s_core_instr_bus(); + + +// ***********************************************************************************************+ +// ***********************************************************************************************+ +// ***********************************************************************************************+ +// ***********************************************************************************************+ +// ***********************************************************************************************+ + +//*************************************************** +/* synchronous AXI interfaces internal to the cluster */ +//*************************************************** + +// core per2axi -> ext +AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) +) s_core_ext_bus(); + +// DMA -> ext +AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) +) s_dma_ext_bus(); + +// ext -> axi2mem +AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) +) s_ext_tcdm_bus(); + +// cluster bus -> axi2per +AXI_BUS #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) +) s_ext_mperiph_bus(); + +/* reset generator */ +rstgen rstgen_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i( test_mode_i ), + .rst_no ( s_rst_n ), + .init_no ( s_init_n ) +); - // ext -> xbar periphs FIXME - XBAR_TCDM_BUS s_mperiph_xbar_bus[NB_MPERIPHS-1:0](); +/* fetch & busy genertion */ +assign s_cluster_int_busy = s_cluster_periphs_busy | s_per2axi_busy | s_axi2per_busy | s_axi2mem_busy | s_dmac_busy | s_hwpe_busy; +assign busy_o = s_cluster_int_busy | (|core_busy); +assign fetch_en_int = fetch_enable_reg_int; + +/* cluster bus and attached peripherals */ +cluster_bus_wrap #( + .NB_MASTER ( NumAxiMst ), + .NB_SLAVE ( NumAxiSlv ), + .NB_CORES ( NB_CORES ), + .DMA_NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), + .TCDM_SIZE ( TCDM_SIZE ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_ID_IN_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_ID_OUT_WIDTH ( AXI_ID_OUT_WIDTH ) +) cluster_bus_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .test_en_i ( test_mode_i ), + .cluster_id_i ( cluster_id_i ), + .instr_slave ( s_core_instr_bus ), + .data_slave ( s_core_ext_bus ), + .dma_slave ( s_dma_ext_bus ), + .ext_slave ( s_data_slave_64 ), + .tcdm_master ( s_ext_tcdm_bus ), + .periph_master ( s_ext_mperiph_bus ), + .ext_master ( s_data_master ) +); - // periph demux - XBAR_TCDM_BUS s_mperiph_bus(); - XBAR_TCDM_BUS s_mperiph_demux_bus[1:0](); - - // cores & accelerators -> log interconnect - hci_core_intf #( - .DW ( NB_HWPE_PORTS*DATA_WIDTH ), - .AW ( ADDR_WIDTH ), - .OW ( 1 ) - ) s_hci_hwpe [0:0] ( - .clk ( clk_cluster ) - ); - hci_core_intf #( - .DW ( DATA_WIDTH ), - .AW ( ADDR_WIDTH ), - .OW ( 1 ) - ) s_hci_core [NB_CORES-1:0] ( - .clk ( clk_cluster ) - ); +axi2mem_wrap #( + .NB_DMAS ( NB_DMAS ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ) +) axi2mem_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .test_en_i ( test_mode_i ), + .axi_slave ( s_ext_tcdm_bus ), + .tcdm_master ( s_hci_ext ), + .busy_o ( s_axi2mem_busy ) +); - // cores -> periph interconnect - XBAR_PERIPH_BUS s_core_periph_bus[NB_CORES-1:0](); - - // periph interconnect -> DMA - XBAR_PERIPH_BUS s_periph_dma_bus[1:0](); - - // debug - XBAR_TCDM_BUS s_debug_bus[NB_CORES-1:0](); - - /* other interfaces */ - // cores -> DMA ctrl - XBAR_TCDM_BUS s_core_dmactrl_bus[NB_CORES-1:0](); - - // cores -> event unit ctrl - XBAR_PERIPH_BUS s_core_euctrl_bus[NB_CORES-1:0](); - - - // apu-interconnect - // handshake signals - logic [NB_CORES-1:0] s_apu_master_req; - logic [NB_CORES-1:0] s_apu_master_gnt; - // request channel - logic [NB_CORES-1:0][APU_NARGS_CPU-1:0][31:0] s_apu_master_operands; - logic [NB_CORES-1:0][APU_WOP_CPU-1:0] s_apu_master_op; - logic [NB_CORES-1:0][WAPUTYPE-1:0] s_apu_master_type; - logic [NB_CORES-1:0][APU_NDSFLAGS_CPU-1:0] s_apu_master_flags; - // response channel - logic [NB_CORES-1:0] s_apu_master_rready; - logic [NB_CORES-1:0] s_apu_master_rvalid; - logic [NB_CORES-1:0][31:0] s_apu_master_rdata; - logic [NB_CORES-1:0][APU_NUSFLAGS_CPU-1:0] s_apu_master_rflags; - - //----------------------------------------------------------------------// - // Interfaces between ICache - L0 - Icache_Interco and Icache_ctrl_unit // - // // - `ifdef PRIVATE_ICACHE - SP_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_main[NB_CACHE_BANKS](); - PRI_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_pri[NB_CORES](); - logic s_special_core_icache_cfg; - logic[NB_CORES-1:0] s_enable_l1_l15_prefetch; +axi2per_wrap #( + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ) +) axi2per_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .test_en_i ( test_mode_i ), + .axi_slave ( s_ext_mperiph_bus ), + .periph_master ( s_mperiph_bus ), + .busy_o ( s_axi2per_busy ) +); - `else - `ifdef SP_ICACHE - SP_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus[NB_CACHE_BANKS](); - L0_CTRL_UNIT_BUS L0_ctrl_unit_bus[NB_CORES](); - `else - `ifdef MP_ICACHE - MP_PF_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus(); - `endif - `endif - `endif - //----------------------------------------------------------------------// - - localparam TCDM_ID_WIDTH = NB_CORES+NB_DMAS+4+NB_HWPE_PORTS; - - // log interconnect -> TCDM memory banks (SRAM) - hci_mem_intf #( - .AW (ADDR_WIDTH ), - .DW ( DATA_WIDTH ), - .BW ( 8 ), - .IW ( TCDM_ID_WIDTH ) - ) s_tcdm_bus_sram[NB_TCDM_BANKS-1:0] ( - .clk ( clk_cluster ) - ); +per_demux_wrap #( + .NB_MASTERS ( 2 ), + .ADDR_OFFSET ( 20 ) +) per_demux_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .slave ( s_mperiph_bus ), + .masters ( s_mperiph_demux_bus ) +); - //*************************************************** - /* synchronous AXI interfaces at CLUSTER/SOC interface */ - //*************************************************** +`TCDM_ASSIGN_MASTER (s_mperiph_xbar_bus[NB_MPERIPHS-1], s_mperiph_demux_bus[0]) + +per2axi_wrap #( + .NB_CORES ( NB_CORES ), + .PER_ADDR_WIDTH ( 32 ), + .PER_ID_WIDTH ( NB_CORES+NB_MPERIPHS ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ) +) per2axi_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .test_en_i ( test_mode_i ), + .periph_slave ( s_xbar_speriph_bus[SPER_EXT_ID] ), + .axi_master ( s_core_ext_bus ), + .busy_o ( s_per2axi_busy ) +); - - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_data_slave_64(); - - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_data_slave_32(); - - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_data_master(); - - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_core_instr_bus(); - - - // ***********************************************************************************************+ - // ***********************************************************************************************+ - // ***********************************************************************************************+ - // ***********************************************************************************************+ - // ***********************************************************************************************+ - - //*************************************************** - /* synchronous AXI interfaces internal to the cluster */ - //*************************************************** - - // core per2axi -> ext - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_core_ext_bus(); - - // DMA -> ext - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_dma_ext_bus(); - - // ext -> axi2mem - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_ext_tcdm_bus(); - - // cluster bus -> axi2per - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) s_ext_mperiph_bus(); - - /* reset generator */ - rstgen rstgen_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_mode_i( test_mode_i ), - .rst_no ( s_rst_n ), - .init_no ( s_init_n ) - ); - - /* fetch & busy genertion */ - assign s_cluster_int_busy = s_cluster_periphs_busy | s_per2axi_busy | s_axi2per_busy | s_axi2mem_busy | s_dmac_busy | s_hwpe_busy; - assign busy_o = s_cluster_int_busy | (|core_busy); - assign fetch_en_int = fetch_enable_reg_int; - - /* cluster bus and attached peripherals */ - cluster_bus_wrap #( - .NB_MASTER ( NumAxiMst ), - .NB_SLAVE ( NumAxiSlv ), - .NB_CORES ( NB_CORES ), - .DMA_NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), - .TCDM_SIZE ( TCDM_SIZE ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_IN_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_ID_OUT_WIDTH ( AXI_ID_OUT_WIDTH ) - ) cluster_bus_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .cluster_id_i ( cluster_id_i ), - .instr_slave ( s_core_instr_bus ), - .data_slave ( s_core_ext_bus ), - .dma_slave ( s_dma_ext_bus ), - .ext_slave ( s_data_slave_64 ), - .tcdm_master ( s_ext_tcdm_bus ), - .periph_master ( s_ext_mperiph_bus ), - .ext_master ( s_data_master ) - ); - axi2mem_wrap #( - .NB_DMAS ( NB_DMAS ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ) - ) axi2mem_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .axi_slave ( s_ext_tcdm_bus ), - .tcdm_master ( s_hci_ext ), - .busy_o ( s_axi2mem_busy ) - ); +//*************************************************** +/* cluster (log + periph) interconnect and attached peripherals */ +//*************************************************** - axi2per_wrap #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) axi2per_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .axi_slave ( s_ext_mperiph_bus ), - .periph_master ( s_mperiph_bus ), - .busy_o ( s_axi2per_busy ) - ); +cluster_interconnect_wrap #( + .NB_CORES ( NB_CORES ), + .HWPE_PRESENT ( HWPE_PRESENT ), + .NB_HWPE_PORTS ( NB_HWPE_PORTS ), + .NB_DMAS ( NB_DMAS ), + .NB_MPERIPHS ( NB_MPERIPHS ), + .NB_TCDM_BANKS ( NB_TCDM_BANKS ), + .NB_SPERIPHS ( NB_SPERIPHS ), - per_demux_wrap #( - .NB_MASTERS ( 2 ), - .ADDR_OFFSET ( 20 ) - ) per_demux_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .slave ( s_mperiph_bus ), - .masters ( s_mperiph_demux_bus ) - ); + .DATA_WIDTH ( DATA_WIDTH ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .BE_WIDTH ( BE_WIDTH ), - `TCDM_ASSIGN_MASTER (s_mperiph_xbar_bus[NB_MPERIPHS-1], s_mperiph_demux_bus[0]) - - per2axi_wrap #( - .NB_CORES ( NB_CORES ), - .PER_ADDR_WIDTH ( 32 ), - .PER_ID_WIDTH ( NB_CORES+NB_MPERIPHS ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ) - ) per2axi_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_en_i ( test_mode_i ), - .periph_slave ( s_xbar_speriph_bus[SPER_EXT_ID] ), - .axi_master ( s_core_ext_bus ), - .busy_o ( s_per2axi_busy ) - ); - + .TEST_SET_BIT ( TEST_SET_BIT ), + .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH ), - //*************************************************** - /* cluster (log + periph) interconnect and attached peripherals */ - //*************************************************** - - cluster_interconnect_wrap #( - .NB_CORES ( NB_CORES ), - .HWPE_PRESENT ( HWPE_PRESENT ), - .NB_HWPE_PORTS ( NB_HWPE_PORTS ), - .NB_DMAS ( NB_DMAS ), - .NB_MPERIPHS ( NB_MPERIPHS ), - .NB_TCDM_BANKS ( NB_TCDM_BANKS ), - .NB_SPERIPHS ( NB_SPERIPHS ), - - .DATA_WIDTH ( DATA_WIDTH ), - .ADDR_WIDTH ( ADDR_WIDTH ), - .BE_WIDTH ( BE_WIDTH ), - - .TEST_SET_BIT ( TEST_SET_BIT ), - .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH ), - - .LOG_CLUSTER ( LOG_CLUSTER ), - .PE_ROUTING_LSB ( PE_ROUTING_LSB ), - .CLUSTER_ALIAS ( CLUSTER_ALIAS ), - .USE_HETEROGENEOUS_INTERCONNECT ( USE_HETEROGENEOUS_INTERCONNECT ) - - ) cluster_interconnect_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - - .core_tcdm_slave ( s_hci_core ), - .hwpe_tcdm_slave ( s_hci_hwpe ), - .ext_slave ( s_hci_ext ), - .dma_slave ( s_hci_dma ), - - .tcdm_sram_master ( s_tcdm_bus_sram ), - - .core_periph_slave ( s_core_periph_bus ), - .mperiph_slave ( s_mperiph_xbar_bus[NB_MPERIPHS-1:0] ), - .speriph_master ( s_xbar_speriph_bus ), - - .hci_ctrl_i ( s_hci_ctrl ), - .TCDM_arb_policy_i ( s_TCDM_arb_policy ) - ); + .LOG_CLUSTER ( LOG_CLUSTER ), + .PE_ROUTING_LSB ( PE_ROUTING_LSB ), + .CLUSTER_ALIAS ( CLUSTER_ALIAS ), + .USE_HETEROGENEOUS_INTERCONNECT ( USE_HETEROGENEOUS_INTERCONNECT ) - //*************************************************** - //*********************DMAC WRAP********************* - //*************************************************** +) cluster_interconnect_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + + .core_tcdm_slave ( s_hci_core ), + .hwpe_tcdm_slave ( s_hci_hwpe ), + .ext_slave ( s_hci_ext ), + .dma_slave ( s_hci_dma ), + + .tcdm_sram_master ( s_tcdm_bus_sram ), + + .core_periph_slave ( s_core_periph_bus ), + .mperiph_slave ( s_mperiph_xbar_bus[NB_MPERIPHS-1:0] ), + .speriph_master ( s_xbar_speriph_bus ), + + .hci_ctrl_i ( s_hci_ctrl ), + .TCDM_arb_policy_i ( s_TCDM_arb_policy ) +); + +//*************************************************** +//*********************DMAC WRAP********************* +//*************************************************** - dmac_wrap #( - .NB_CTRLS ( 10 ), - .NB_CORES ( NB_CORES ), - .NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), - .MCHAN_BURST_LENGTH ( MCHAN_BURST_LENGTH ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .PE_ID_WIDTH ( NB_CORES + 1 ), - .TCDM_ADD_WIDTH ( TCDM_ADD_WIDTH ), - .DATA_WIDTH ( DATA_WIDTH ), - .ADDR_WIDTH ( ADDR_WIDTH ), - .BE_WIDTH ( BE_WIDTH ) - ) dmac_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .test_mode_i ( test_mode_i ), - .ctrl_slave ( s_core_dmactrl_bus ), - .cl_ctrl_slave ( s_periph_dma_bus[0]), - .fc_ctrl_slave ( s_periph_dma_bus[1]), - .tcdm_master ( s_hci_dma ), - .ext_master ( s_dma_ext_bus ), - .term_event_cl_o ( s_dma_cl_event ), - .term_irq_cl_o ( s_dma_cl_irq ), - .term_event_pe_o ( s_dma_fc_event ), - .term_irq_pe_o ( s_dma_pe_irq ), - .term_event_o ( s_dma_event ), - .term_irq_o ( s_dma_irq ), - .busy_o ( s_dmac_busy ) - ); +dmac_wrap #( + .NB_CTRLS ( 10 ), + .NB_CORES ( NB_CORES ), + .NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), + .MCHAN_BURST_LENGTH ( MCHAN_BURST_LENGTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .PE_ID_WIDTH ( NB_CORES + 1 ), + .TCDM_ADD_WIDTH ( TCDM_ADD_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .BE_WIDTH ( BE_WIDTH ) +) dmac_wrap_i ( + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .test_mode_i ( test_mode_i ), + .ctrl_slave ( s_core_dmactrl_bus ), + .cl_ctrl_slave ( s_periph_dma_bus[0]), + .fc_ctrl_slave ( s_periph_dma_bus[1]), + .tcdm_master ( s_hci_dma ), + .ext_master ( s_dma_ext_bus ), + .term_event_cl_o ( s_dma_cl_event ), + .term_irq_cl_o ( s_dma_cl_irq ), + .term_event_pe_o ( s_dma_fc_event ), + .term_irq_pe_o ( s_dma_pe_irq ), + .term_event_o ( s_dma_event ), + .term_irq_o ( s_dma_irq ), + .busy_o ( s_dmac_busy ) +); - //*************************************************** - //**************CLUSTER PERIPHERALS****************** - //*************************************************** - - cluster_peripherals #( - .NB_CORES ( NB_CORES ), - .NB_MPERIPHS ( NB_MPERIPHS ), - .NB_CACHE_BANKS ( NB_CACHE_BANKS ), - .NB_SPERIPHS ( NB_SPERIPHS ), - .NB_TCDM_BANKS ( NB_TCDM_BANKS ), - .ROM_BOOT_ADDR ( ROM_BOOT_ADDR ), - .BOOT_ADDR ( BOOT_ADDR ), - .EVNT_WIDTH ( EVNT_WIDTH ), - - .NB_L1_CUTS ( NB_L1_CUTS ), - .RW_MARGIN_WIDTH ( RW_MARGIN_WIDTH ) +//*************************************************** +//**************CLUSTER PERIPHERALS****************** +//*************************************************** + +cluster_peripherals #( + .NB_CORES ( NB_CORES ), + .NB_MPERIPHS ( NB_MPERIPHS ), + .NB_CACHE_BANKS ( NB_CACHE_BANKS ), + .NB_SPERIPHS ( NB_SPERIPHS ), + .NB_TCDM_BANKS ( NB_TCDM_BANKS ), + .ROM_BOOT_ADDR ( ROM_BOOT_ADDR ), + .BOOT_ADDR ( BOOT_ADDR ), + .EVNT_WIDTH ( EVNT_WIDTH ), + + .NB_L1_CUTS ( NB_L1_CUTS ), + .RW_MARGIN_WIDTH ( RW_MARGIN_WIDTH ) + +) cluster_peripherals_i ( + + .clk_i ( clk_cluster ), + .rst_ni ( s_rst_n ), + .ref_clk_i ( ref_clk_i ), + .test_mode_i ( test_mode_i ), + .busy_o ( s_cluster_periphs_busy ), + + .en_sa_boot_i ( en_sa_boot_i ), + .fetch_en_i ( fetch_en_i ), + .boot_addr_o ( boot_addr ), + .core_busy_i ( core_busy ), + .core_clk_en_o ( clk_core_en ), + + .speriph_slave ( s_xbar_speriph_bus[NB_SPERIPHS-2:0]), + .core_eu_direct_link ( s_core_euctrl_bus ), + + .dma_cfg_master ( s_periph_dma_bus ), + + .dma_cl_event_i ( s_dma_cl_event ), + .dma_cl_irq_i ( s_dma_cl_irq ), + .dma_event_i ( s_dma_event ), + .dma_irq_i ( s_dma_irq ), + + // NEW_SIGNALS .decompr_done_evt_i ( s_decompr_done_evt ), + + .dma_fc_event_i ( s_dma_fc_event ), + .dma_fc_irq_i ( ), + + .soc_periph_evt_ready_o ( s_events_ready ), + .soc_periph_evt_valid_i ( s_events_valid ), + .soc_periph_evt_data_i ( s_events_data ), + + .dbg_core_halt_o ( dbg_core_halt ), + .dbg_core_halted_i ( dbg_core_halted ), + .dbg_core_resume_o ( dbg_core_resume ), + + .eoc_o ( eoc_o ), + .cluster_cg_en_o ( s_cluster_cg_en ), + .fetch_enable_reg_o ( fetch_enable_reg_int ), + .irq_id_o ( irq_id ), + .irq_ack_id_i ( irq_ack_id ), + .irq_req_o ( irq_req ), + .irq_ack_i ( irq_ack ), + .dbg_req_i ( s_dbg_irq ), + .dbg_req_o ( s_core_dbg_irq ), + + .fregfile_disable_o ( s_fregfile_disable ), - ) cluster_peripherals_i ( - - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), - .ref_clk_i ( ref_clk_i ), - .test_mode_i ( test_mode_i ), - .busy_o ( s_cluster_periphs_busy ), - - .en_sa_boot_i ( en_sa_boot_i ), - .fetch_en_i ( fetch_en_i ), - .boot_addr_o ( boot_addr ), - .core_busy_i ( core_busy ), - .core_clk_en_o ( clk_core_en ), - - .speriph_slave ( s_xbar_speriph_bus[NB_SPERIPHS-2:0]), - .core_eu_direct_link ( s_core_euctrl_bus ), - - .dma_cfg_master ( s_periph_dma_bus ), - - .dma_cl_event_i ( s_dma_cl_event ), - .dma_cl_irq_i ( s_dma_cl_irq ), - .dma_event_i ( s_dma_event ), - .dma_irq_i ( s_dma_irq ), - - // NEW_SIGNALS .decompr_done_evt_i ( s_decompr_done_evt ), - - .dma_fc_event_i ( s_dma_fc_event ), - .dma_fc_irq_i ( ), - - .soc_periph_evt_ready_o ( s_events_ready ), - .soc_periph_evt_valid_i ( s_events_valid ), - .soc_periph_evt_data_i ( s_events_data ), - - .dbg_core_halt_o ( dbg_core_halt ), - .dbg_core_halted_i ( dbg_core_halted ), - .dbg_core_resume_o ( dbg_core_resume ), - - .eoc_o ( eoc_o ), - .cluster_cg_en_o ( s_cluster_cg_en ), - .fetch_enable_reg_o ( fetch_enable_reg_int ), - .irq_id_o ( irq_id ), - .irq_ack_id_i ( irq_ack_id ), - .irq_req_o ( irq_req ), - .irq_ack_i ( irq_ack ), - .dbg_req_i ( s_dbg_irq ), - .dbg_req_o ( s_core_dbg_irq ), - - .fregfile_disable_o ( s_fregfile_disable ), - - .TCDM_arb_policy_o ( s_TCDM_arb_policy ), - - .hwpe_cfg_master ( s_hwpe_cfg_bus ), - .hwpe_events_i ( s_hwpe_remap_evt ), - .hwpe_en_o ( s_hwpe_en ), - .hci_ctrl_o ( s_hci_ctrl ) + .TCDM_arb_policy_o ( s_TCDM_arb_policy ), + + .hwpe_cfg_master ( s_hwpe_cfg_bus ), + .hwpe_events_i ( s_hwpe_remap_evt ), + .hwpe_en_o ( s_hwpe_en ), + .hci_ctrl_o ( s_hci_ctrl ) `ifdef PRIVATE_ICACHE - , - .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), - .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), - .enable_l1_l15_prefetch_o ( s_enable_l1_l15_prefetch ) + , + .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), + .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), + .enable_l1_l15_prefetch_o ( s_enable_l1_l15_prefetch ) `else `ifdef SP_ICACHE , @@ -804,123 +800,119 @@ module pulp_cluster //.rw_margin_L1_o ( s_rw_margin_L1 ) ); +//******************************************************** +//***************** CORE ISLANDS ************************* +//******************************************************** +//------------------------------------------------------// +// ██████╗ ██████╗ ██████╗ ███████╗ // +// ██╔════╝██╔═══██╗██╔══██╗██╔════╝ // +// ██║ ██║ ██║██████╔╝█████╗ // +// ██║ ██║ ██║██╔══██╗██╔══╝ // +// ╚██████╗╚██████╔╝██║ ██║███████╗ // +// ╚═════╝ ╚═════╝ ╚═╝ ╚═╝╚══════╝ // +//------------------------------------------------------// + +/* cluster cores + core-coupled accelerators / shared execution units */ +generate + for (genvar i=0; i Minimum SIZE - - //ICACHE BUS PARAMETERS - .ICACHE_DATA_WIDTH ( ICACHE_DATA_WIDTH ), - .ICACHE_ID_WIDTH ( NB_CORES ), - .ICACHE_ADDR_WIDTH ( 32 ), - - .L0_BUFFER_FEATURE ( L0_BUFFER_FEATURE ), - .L0_SIZE ( ICACHE_DATA_WIDTH ), - - .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), - - .SUPPORT_BOTH_PRI_SH ( "FALSE" ), - .SHARED_ICACHE ( SHARED_ICACHE ), - .MULTICAST_FEATURE ( MULTICAST_FEATURE ), - .MULTICAST_GRANULARITY ( 1 ), - .DIRECT_MAPPED_FEATURE ( DIRECT_MAPPED_FEATURE), - - .L2_SIZE ( L2_SIZE ), - .USE_REDUCED_TAG ( USE_REDUCED_TAG ), - - //AXI PARAMETER - .AXI_ID ( AXI_ID_IN_WIDTH ), - .AXI_USER ( AXI_USER_WIDTH ), - .AXI_DATA ( AXI_DATA_C2S_WIDTH ), - .AXI_ADDR ( AXI_ADDR_WIDTH ) - ) icache_top_i ( - // --------------------------------------------------------------- - // CORES I$ PLUG ----------------------------------------- - // --------------------------------------------------------------- - .clk ( clk_cluster ), - .rst_n ( s_rst_n ), - .test_en_i ( test_mode_i ), - - .instr_req_i ( instr_req ), - .instr_add_i ( instr_addr ), - .instr_gnt_o ( instr_gnt ) , - - .instr_r_valid_o ( instr_r_valid ), - .instr_r_rdata_o ( instr_r_rdata ), - - - // --------------------------------------------------------------- - // Refill BUS I$ ----------------------------------------- - // --------------------------------------------------------------- - .init_awid_o ( s_core_instr_bus.aw_id ), - .init_awaddr_o ( s_core_instr_bus.aw_addr ), - .init_awlen_o ( s_core_instr_bus.aw_len ), - .init_awsize_o ( s_core_instr_bus.aw_size ), - .init_awburst_o ( s_core_instr_bus.aw_burst ), - .init_awlock_o ( s_core_instr_bus.aw_lock ), - .init_awcache_o ( s_core_instr_bus.aw_cache ), - .init_awprot_o ( s_core_instr_bus.aw_prot ), - .init_awregion_o ( s_core_instr_bus.aw_region ), - .init_awuser_o ( s_core_instr_bus.aw_user ), - .init_awqos_o ( s_core_instr_bus.aw_qos ), - .init_awvalid_o ( s_core_instr_bus.aw_valid ), - .init_awready_i ( s_core_instr_bus.aw_ready ), - - - //AXI write data bus -------------- // // -------------- - .init_wdata_o ( s_core_instr_bus.w_data ), - .init_wstrb_o ( s_core_instr_bus.w_strb ), - .init_wlast_o ( s_core_instr_bus.w_last ), - .init_wuser_o ( s_core_instr_bus.w_user ), - .init_wvalid_o ( s_core_instr_bus.w_valid ), - .init_wready_i ( s_core_instr_bus.w_ready ), - // --------------------------------------------------------------- - - //AXI BACKWARD write response bus -------------- // // -------------- - .init_bid_i ( s_core_instr_bus.b_id ), - .init_bresp_i ( s_core_instr_bus.b_resp ), - .init_buser_i ( s_core_instr_bus.b_user ), - .init_bvalid_i ( s_core_instr_bus.b_valid ), - .init_bready_o ( s_core_instr_bus.b_ready ), - // --------------------------------------------------------------- - - //AXI read address bus ------------------------------------------- - .init_arid_o ( s_core_instr_bus.ar_id ), - .init_araddr_o ( s_core_instr_bus.ar_addr ), - .init_arlen_o ( s_core_instr_bus.ar_len ), - .init_arsize_o ( s_core_instr_bus.ar_size ), - .init_arburst_o ( s_core_instr_bus.ar_burst ), - .init_arlock_o ( s_core_instr_bus.ar_lock ), - .init_arcache_o ( s_core_instr_bus.ar_cache ), - .init_arprot_o ( s_core_instr_bus.ar_prot ), - .init_arregion_o ( s_core_instr_bus.ar_region ), - .init_aruser_o ( s_core_instr_bus.ar_user ), - .init_arqos_o ( s_core_instr_bus.ar_qos ), - .init_arvalid_o ( s_core_instr_bus.ar_valid ), - .init_arready_i ( s_core_instr_bus.ar_ready ), - // --------------------------------------------------------------- - - - //AXI BACKWARD read data bus ---------------------------------------------- - .init_rid_i ( s_core_instr_bus.r_id ), - .init_rdata_i ( s_core_instr_bus.r_data ), - .init_rresp_i ( s_core_instr_bus.r_resp ), - .init_rlast_i ( s_core_instr_bus.r_last ), - .init_ruser_i ( s_core_instr_bus.r_user ), - .init_rvalid_i ( s_core_instr_bus.r_valid ), - .init_rready_o ( s_core_instr_bus.r_ready ), - - // Control ports - .IC_ctrl_unit_slave_if ( IC_ctrl_unit_bus ), - .L0_ctrl_unit_slave_if ( L0_ctrl_unit_bus ) - ); - `endif // Closes `ifdef SP_ICACHE - `endif // Closes `ifdef MP_ICACHE -`endif // Closes `ifdef PRI_ICACHE - assign s_core_instr_bus.aw_atop = '0; /* TCDM banks */ From 701b4d908f15d5746d033b70fa1f79298380f5ea Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 18 Apr 2023 10:31:11 +0200 Subject: [PATCH 007/207] Bumped core, FPU interco, and icache. --- Bender.yml | 6 +++--- rtl/core_region.sv | 14 +++++++------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/Bender.yml b/Bender.yml index 8c2016b7..102e232f 100644 --- a/Bender.yml +++ b/Bender.yml @@ -18,15 +18,15 @@ dependencies: cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", version: 1.1.1 } event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: "1.4.1" } mchan: { git: "https://github.com/pulp-platform/mchan.git", version: 1.2.3 } - hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "fc231dfc9559c6715c3577049eae3d1887282cb0" } + hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "9e53e957f7e0fd88616a5f3fbcc2617fbc3c9d0d" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 } - fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "66b4084117546d5b748c30b5500769805f489d2f" } + fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "c05d793cb0638b43fdaa067aef48cbcc4ea40e81" } axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0-beta.4 } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: "9b7d500" } # michaero/safety-island + cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: "b26d1d6c5043bc6c535e23bf61b51313c802e44a" } # branch: michaero/safety-island-clic ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", version: 1.1.0} hwpe-datamover-example: { git: "https://github.com/pulp-platform/hwpe-datamover-example.git", version: 1.0.1 } diff --git a/rtl/core_region.sv b/rtl/core_region.sv index e37edd2a..60569dee 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -184,20 +184,20 @@ module core_region .hart_id_i ( hart_id ), .dm_exception_addr_i ( DEBUG_START_ADDR + 16'h080C ), // From Control PULP, to be checked // Instruction Interface - .instr_addr_o ( instr_addr_o ), .instr_req_o ( instr_req_o ), - .instr_rdata_i ( instr_r_rdata_i ), .instr_gnt_i ( instr_gnt_i ), .instr_rvalid_i ( instr_r_valid_i ), + .instr_addr_o ( instr_addr_o ), + .instr_rdata_i ( instr_r_rdata_i ), // Data Interface - .data_addr_o ( s_core_bus.add ), - .data_wdata_o ( s_core_bus.wdata ), - .data_we_o ( s_core_bus.we ), .data_req_o ( s_core_bus.req ), - .data_be_o ( s_core_bus.be ), - .data_rdata_i ( s_core_bus.r_rdata ), .data_gnt_i ( s_core_bus.gnt ), .data_rvalid_i ( s_core_bus.r_valid ), + .data_we_o ( s_core_bus.we ), + .data_be_o ( s_core_bus.be ), + .data_addr_o ( s_core_bus.add ), + .data_wdata_o ( s_core_bus.wdata ), + .data_rdata_i ( s_core_bus.r_rdata ), // apu-interconnect // Handshake .apu_req_o ( apu_master_req_o ), From 035b12c92610a00170f246dbb5ccb9a1cc23dabc Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 18 Apr 2023 10:47:12 +0200 Subject: [PATCH 008/207] Bumped fpu_interco. --- Bender.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index 102e232f..7bfc8efb 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,7 +20,7 @@ dependencies: mchan: { git: "https://github.com/pulp-platform/mchan.git", version: 1.2.3 } hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "9e53e957f7e0fd88616a5f3fbcc2617fbc3c9d0d" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 } - fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "c05d793cb0638b43fdaa067aef48cbcc4ea40e81" } + fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "250b376bb68bd3b4b13c5b8f5ac2155e32152733" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0-beta.4 } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } From 09d9dd192f4f236e427eaa8a51812d3a722b0bf9 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 18 Apr 2023 16:22:37 +0200 Subject: [PATCH 009/207] Removed internal reset synchronizer and clock gating cell. --- rtl/pulp_cluster.sv | 114 ++++++++++++++++---------------------------- 1 file changed, 41 insertions(+), 73 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 6091f5e4..17ba5a5e 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -248,7 +248,6 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; logic [NB_CORES-1:0] fetch_enable_reg_int; logic [NB_CORES-1:0] fetch_en_int; -logic s_rst_n; logic s_init_n; logic [NB_CORES-1:0][31:0] boot_addr; logic [NB_CORES-1:0] dbg_core_halt; @@ -271,7 +270,6 @@ logic s_hwpe_busy; hci_package::hci_interconnect_ctrl_t s_hci_ctrl; logic [NB_CORES-1:0] clk_core_en; -logic clk_cluster; // CLK reset, and other control signals @@ -325,8 +323,6 @@ logic s_decompr_done_evt; assign s_dma_fc_irq = s_decompr_done_evt; - - /* logarithmic and peripheral interconnect interfaces */ // ext -> log interconnect hci_core_intf #( @@ -334,7 +330,7 @@ hci_core_intf #( .AW ( ADDR_WIDTH ), .OW ( 1 ) ) s_hci_ext[NB_DMAS-1:0] ( - .clk ( clk_cluster ) + .clk ( clk_i ) ); // periph interconnect -> slave peripherals @@ -349,9 +345,9 @@ hci_core_intf #( .AW ( ADDR_WIDTH ), .OW ( 1 ) ) s_hci_dma[NB_DMAS-1:0] ( - .clk ( clk_cluster ) + .clk ( clk_i ) ); -XBAR_TCDM_BUS s_dma_plugin_xbar_bus[NB_DMAS-1:0](); +XBAR_TCDM_BUS s_dma_plugin_xbar_bus[NB_DMAS-1:0](); // ext -> xbar periphs FIXME XBAR_TCDM_BUS s_mperiph_xbar_bus[NB_MPERIPHS-1:0](); @@ -366,14 +362,14 @@ hci_core_intf #( .AW ( ADDR_WIDTH ), .OW ( 1 ) ) s_hci_hwpe [0:0] ( - .clk ( clk_cluster ) + .clk ( clk_i ) ); hci_core_intf #( .DW ( DATA_WIDTH ), .AW ( ADDR_WIDTH ), .OW ( 1 ) ) s_hci_core [NB_CORES-1:0] ( - .clk ( clk_cluster ) + .clk ( clk_i ) ); // cores -> periph interconnect @@ -392,7 +388,6 @@ XBAR_TCDM_BUS s_core_dmactrl_bus[NB_CORES-1:0](); // cores -> event unit ctrl XBAR_PERIPH_BUS s_core_euctrl_bus[NB_CORES-1:0](); - // apu-interconnect // handshake signals logic [NB_CORES-1:0] s_apu_master_req; @@ -426,7 +421,7 @@ hci_mem_intf #( .BW ( 8 ), .IW ( TCDM_ID_WIDTH ) ) s_tcdm_bus_sram[NB_TCDM_BANKS-1:0] ( - .clk ( clk_cluster ) + .clk ( clk_i ) ); //*************************************************** @@ -460,7 +455,6 @@ AXI_BUS #( .AXI_USER_WIDTH ( AXI_USER_WIDTH ) ) s_core_instr_bus(); - // ***********************************************************************************************+ // ***********************************************************************************************+ // ***********************************************************************************************+ @@ -503,15 +497,6 @@ AXI_BUS #( .AXI_USER_WIDTH ( AXI_USER_WIDTH ) ) s_ext_mperiph_bus(); -/* reset generator */ -rstgen rstgen_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .test_mode_i( test_mode_i ), - .rst_no ( s_rst_n ), - .init_no ( s_init_n ) -); - /* fetch & busy genertion */ assign s_cluster_int_busy = s_cluster_periphs_busy | s_per2axi_busy | s_axi2per_busy | s_axi2mem_busy | s_dmac_busy | s_hwpe_busy; assign busy_o = s_cluster_int_busy | (|core_busy); @@ -531,8 +516,8 @@ cluster_bus_wrap #( .AXI_ID_OUT_WIDTH ( AXI_ID_OUT_WIDTH ), .BaseAddr ( BaseAddr ) ) cluster_bus_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .test_en_i ( test_mode_i ), .cluster_id_i ( cluster_id_i ), .instr_slave ( s_core_instr_bus ), @@ -551,8 +536,8 @@ axi2mem_wrap #( .AXI_USER_WIDTH ( AXI_USER_WIDTH ), .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ) ) axi2mem_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .test_en_i ( test_mode_i ), .axi_slave ( s_ext_tcdm_bus ), .tcdm_master ( s_hci_ext ), @@ -565,8 +550,8 @@ axi2per_wrap #( .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ) ) axi2per_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .test_en_i ( test_mode_i ), .axi_slave ( s_ext_mperiph_bus ), .periph_master ( s_mperiph_bus ), @@ -577,8 +562,8 @@ per_demux_wrap #( .NB_MASTERS ( 2 ), .ADDR_OFFSET ( 20 ) ) per_demux_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .slave ( s_mperiph_bus ), .masters ( s_mperiph_demux_bus ) ); @@ -594,14 +579,13 @@ per2axi_wrap #( .AXI_USER_WIDTH ( AXI_USER_WIDTH ), .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ) ) per2axi_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .test_en_i ( test_mode_i ), .periph_slave ( s_xbar_speriph_bus[SPER_EXT_ID] ), .axi_master ( s_core_ext_bus ), .busy_o ( s_per2axi_busy ) ); - //*************************************************** /* cluster (log + periph) interconnect and attached peripherals */ @@ -629,8 +613,8 @@ cluster_interconnect_wrap #( .USE_HETEROGENEOUS_INTERCONNECT ( USE_HETEROGENEOUS_INTERCONNECT ) ) cluster_interconnect_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .core_tcdm_slave ( s_hci_core ), .hwpe_tcdm_slave ( s_hci_hwpe ), @@ -666,8 +650,8 @@ dmac_wrap #( .ADDR_WIDTH ( ADDR_WIDTH ), .BE_WIDTH ( BE_WIDTH ) ) dmac_wrap_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .test_mode_i ( test_mode_i ), .ctrl_slave ( s_core_dmactrl_bus ), .cl_ctrl_slave ( s_periph_dma_bus[0]), @@ -702,8 +686,8 @@ cluster_peripherals #( ) cluster_peripherals_i ( - .clk_i ( clk_cluster ), - .rst_ni ( s_rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .ref_clk_i ( ref_clk_i ), .test_mode_i ( test_mode_i ), .busy_o ( s_cluster_periphs_busy ), @@ -777,8 +761,8 @@ generate for (genvar i=0; i Date: Fri, 21 Apr 2023 15:45:05 +0200 Subject: [PATCH 010/207] Moved XBAR address map rule out of pulp_cluster_package to parametrize the address width. --- packages/pulp_cluster_package.sv | 8 -------- rtl/cluster_bus_wrap.sv | 11 ++++++++--- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 685a3bda..1fcd4be6 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -15,17 +15,9 @@ */ package pulp_cluster_package; - - typedef struct packed { - logic [31:0] idx; - logic [31:0] start_addr; - logic [31:0] end_addr; - } addr_map_rule_t; - parameter NB_SPERIPH_PLUGS_EU = 2; - // number of master and slave cluster periphs parameter NB_MPERIPHS = 1; parameter NB_SPERIPHS = 10; diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index cbf3a475..86aa30b7 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -20,10 +20,8 @@ `include "axi/assign.svh" `include "axi/typedef.svh" - module cluster_bus_wrap import axi_pkg::xbar_cfg_t; - import pulp_cluster_package::addr_map_rule_t; #( parameter int unsigned NB_MASTER = 3 , parameter int unsigned NB_SLAVE = 4 , @@ -92,11 +90,18 @@ module cluster_bus_wrap `AXI_ASSIGN(periph_master, axi_masters[1]) `AXI_ASSIGN(ext_master , axi_masters[2]) + // Address Map Rule + typedef struct packed { + logic [31:0] idx ; + logic [AXI_ADDR_WIDTH-1:0] start_addr; + logic [AXI_ADDR_WIDTH-1:0] end_addr ; + } addr_map_rule_t; + // address map logic [31:0] cluster_base_addr; assign cluster_base_addr = BaseAddr + ( cluster_id_i << 22); localparam int unsigned N_RULES = 3; - pulp_cluster_package::addr_map_rule_t [N_RULES-1:0] addr_map; + addr_map_rule_t [N_RULES-1:0] addr_map; assign addr_map[0] = '{ // TCDM From 11c1e5348d2e88a6d740afe1c9ed524582c5f291 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 24 Apr 2023 08:30:29 +0200 Subject: [PATCH 011/207] Unconnected signals. --- rtl/core_region.sv | 19 +++++++++++++++++++ rtl/pulp_cluster.sv | 8 ++++++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 60569dee..74bde915 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -146,6 +146,14 @@ module core_region logic core_mem_req; + // Shadow registers + logic core_shadow_req ; + logic core_shadow_we ; + logic [3:0] core_shadow_be ; + logic [31:0] core_shadow_addr ; + logic [31:0] core_shadow_wdata; + logic [5:0] core_data_atop ; + // clock gate of the core_region less the core itself cluster_clock_gating clock_gate_i ( .clk_i ( clk_i ), @@ -198,6 +206,16 @@ module core_region .data_addr_o ( s_core_bus.add ), .data_wdata_o ( s_core_bus.wdata ), .data_rdata_i ( s_core_bus.r_rdata ), + .shadow_req_o ( sadow_req ), + .shadow_gnt_i ( '0 ), + .shadow_rvalid_i ( '0 ), + .shadow_we_o ( core_shadow_we ), + .shadow_be_o ( core_shadow_be ), + .shadow_addr_o ( core_shadow_addr ), + .shadow_wdata_o ( core_shadow_wdata ), + .shadow_rdata_i ( '0 ), + // Atomic operation + .data_atop_o ( core_data_atop ), // apu-interconnect // Handshake .apu_req_o ( apu_master_req_o ), @@ -205,6 +223,7 @@ module core_region // Request Bus .apu_operands_o ( apu_master_operands_o ), .apu_op_o ( apu_master_op_o ), + .apu_type_o ( apu_master_type_o ), .apu_flags_o ( apu_master_flags_o ), // Response Bus .apu_rvalid_i ( apu_master_valid_i ), diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 17ba5a5e..d127ebaa 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -253,6 +253,8 @@ logic [NB_CORES-1:0][31:0] boot_addr; logic [NB_CORES-1:0] dbg_core_halt; logic [NB_CORES-1:0] dbg_core_resume; logic [NB_CORES-1:0] dbg_core_halted; +logic [NB_CORES-1:0] dbg_core_havereset; +logic [NB_CORES-1:0] dbg_core_running; logic [NB_CORES-1:0] s_dbg_irq; logic s_hwpe_en; @@ -812,8 +814,10 @@ generate .instr_r_valid_i ( instr_r_valid[i] ), //debug unit bind - .debug_req_i ( s_core_dbg_irq[i] ), - .debug_halted_o ( dbg_core_halted[i] ), + .debug_req_i ( s_core_dbg_irq[i] ), + .debug_halted_o ( dbg_core_halted[i] ), + .debug_havereset_o ( dbg_core_havereset[i] ), + .debug_running_o ( dbg_core_running[i] ), // .debug_resume_i ( dbg_core_resume[i] ), // Useful for HMR, consider keeping .tcdm_data_master ( s_hci_core[i] ), From 9376b77a353fa927b766d0e0a93788f43444193f Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 25 Apr 2023 21:07:17 +0200 Subject: [PATCH 012/207] Added AXI isolate. --- rtl/pulp_cluster.sv | 70 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 59 insertions(+), 11 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index d127ebaa..d5676e40 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -157,7 +157,9 @@ module pulp_cluster output logic eoc_o, output logic busy_o, - + + input logic axi_isolate_i, + output logic axi_isolated_o, input logic dma_pe_evt_ack_i, output logic dma_pe_evt_valid_o, @@ -1091,11 +1093,36 @@ tcdm_banks_wrap #( `AXI_TYPEDEF_REQ_T(c2s_req_t,c2s_aw_chan_t,c2s_w_chan_t,c2s_ar_chan_t) `AXI_TYPEDEF_RESP_T(c2s_resp_t,c2s_b_chan_t,c2s_r_chan_t) -c2s_req_t src_req ; -c2s_resp_t src_resp; +logic [1:0] axi_isolated; + +assign axi_isolated_o = |axi_isolated; + +c2s_req_t src_req, isolate_src_req ; +c2s_resp_t src_resp, isolate_src_rsp; -`AXI_ASSIGN_TO_REQ(src_req,s_data_master) -`AXI_ASSIGN_FROM_RESP(s_data_master,src_resp) +`AXI_ASSIGN_TO_REQ(isolate_src_req,s_data_master) +`AXI_ASSIGN_FROM_RESP(s_data_master,isolate_src_rsp) + +axi_isolate #( + .NumPending ( 8 ), + .TerminateTransaction ( 1 ), + .AtopSupport ( 1 ), + .AxiAddrWidth ( AXI_ADDR_WIDTH ), + .AxiDataWidth ( AXI_DATA_C2S_WIDTH ), + .AxiIdWidth ( AXI_ID_Out_WIDTH ), + .AxiUserWidth ( AXI_USER_WIDTH ), + .axi_req_t ( c2s_req_t ), + .axi_resp_t ( c2s_resp_t ) +) i_axi_master_isolate ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( isolate_src_req ), + .slv_resp_o ( isolate_src_resp ), + .mst_req_o ( src_req ), + .mst_resp_i ( src_rsp ), + .isolate_i ( axi_isolate_i ), + .isolated_o ( axi_isolated[1] ) +); axi_cdc_src #( .aw_chan_t ( c2s_aw_chan_t ), @@ -1138,12 +1165,12 @@ axi_cdc_src #( `AXI_TYPEDEF_REQ_T(s2c_req_t,s2c_aw_chan_t,s2c_w_chan_t,s2c_ar_chan_t) `AXI_TYPEDEF_RESP_T(s2c_resp_t,s2c_b_chan_t,s2c_r_chan_t) - s2c_req_t dst_req; - s2c_resp_t dst_resp; - -`AXI_ASSIGN_FROM_REQ(s_data_slave_32,dst_req) -`AXI_ASSIGN_TO_RESP(dst_resp,s_data_slave_32) + s2c_req_t dst_req , isolate_dst_req; + s2c_resp_t dst_resp, isolate_dst_rsp; +`AXI_ASSIGN_FROM_REQ(s_data_slave_32,isolate_dst_req) +`AXI_ASSIGN_TO_RESP(isolate_dst_rsp,s_data_slave_32) + axi_cdc_dst #( .aw_chan_t (s2c_aw_chan_t), .w_chan_t (s2c_w_chan_t ), @@ -1173,7 +1200,28 @@ axi_cdc_dst #( .async_data_slave_r_wptr_o ( async_data_slave_r_wptr_o ), .async_data_slave_r_rptr_i ( async_data_slave_r_rptr_i ), .async_data_slave_r_data_o ( async_data_slave_r_data_o ) -); +); + +axi_isolate #( + .NumPending ( 8 ), + .TerminateTransaction ( 1 ), + .AtopSupport ( 1 ), + .AxiAddrWidth ( AXI_ADDR_WIDTH ), + .AxiDataWidth ( AXI_DATA_C2S_WIDTH ), + .AxiIdWidth ( AXI_ID_IN_WIDTH ), + .AxiUserWidth ( AXI_USER_WIDTH ), + .axi_req_t ( s2c_req_t ), + .axi_resp_t ( s2c_resp_t ) +) i_axi_slave_isolate ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( dst_req ), + .slv_resp_o ( dst_resp ), + .mst_req_o ( isolate_dst_req ), + .mst_resp_i ( isolate_dst_rsp ), + .isolate_i ( axi_isolate_i ), + .isolated_o ( axi_isolated[0] ) +); axi_dw_converter_intf #( .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), From 65936b71dbed05d74a99059c8a0cfa28ff646c31 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Wed, 26 Apr 2023 09:48:18 +0200 Subject: [PATCH 013/207] rtl: Fix parameter name propagation --- rtl/pulp_cluster.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index d5676e40..2c33f467 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -1109,7 +1109,7 @@ axi_isolate #( .AtopSupport ( 1 ), .AxiAddrWidth ( AXI_ADDR_WIDTH ), .AxiDataWidth ( AXI_DATA_C2S_WIDTH ), - .AxiIdWidth ( AXI_ID_Out_WIDTH ), + .AxiIdWidth ( AXI_ID_OUT_WIDTH ), .AxiUserWidth ( AXI_USER_WIDTH ), .axi_req_t ( c2s_req_t ), .axi_resp_t ( c2s_resp_t ) From a7ced88c96660df69be9d9bf182577484a666d73 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 26 Apr 2023 12:26:41 +0200 Subject: [PATCH 014/207] Fixed typos in AXI buses. --- rtl/pulp_cluster.sv | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 2c33f467..4a9ff325 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -1098,10 +1098,10 @@ logic [1:0] axi_isolated; assign axi_isolated_o = |axi_isolated; c2s_req_t src_req, isolate_src_req ; -c2s_resp_t src_resp, isolate_src_rsp; +c2s_resp_t src_resp, isolate_src_resp; `AXI_ASSIGN_TO_REQ(isolate_src_req,s_data_master) -`AXI_ASSIGN_FROM_RESP(s_data_master,isolate_src_rsp) +`AXI_ASSIGN_FROM_RESP(s_data_master,isolate_src_resp) axi_isolate #( .NumPending ( 8 ), @@ -1119,7 +1119,7 @@ axi_isolate #( .slv_req_i ( isolate_src_req ), .slv_resp_o ( isolate_src_resp ), .mst_req_o ( src_req ), - .mst_resp_i ( src_rsp ), + .mst_resp_i ( src_resp ), .isolate_i ( axi_isolate_i ), .isolated_o ( axi_isolated[1] ) ); @@ -1166,10 +1166,10 @@ axi_cdc_src #( `AXI_TYPEDEF_RESP_T(s2c_resp_t,s2c_b_chan_t,s2c_r_chan_t) s2c_req_t dst_req , isolate_dst_req; - s2c_resp_t dst_resp, isolate_dst_rsp; + s2c_resp_t dst_resp, isolate_dst_resp; `AXI_ASSIGN_FROM_REQ(s_data_slave_32,isolate_dst_req) -`AXI_ASSIGN_TO_RESP(isolate_dst_rsp,s_data_slave_32) +`AXI_ASSIGN_TO_RESP(isolate_dst_resp,s_data_slave_32) axi_cdc_dst #( .aw_chan_t (s2c_aw_chan_t), @@ -1213,14 +1213,14 @@ axi_isolate #( .axi_req_t ( s2c_req_t ), .axi_resp_t ( s2c_resp_t ) ) i_axi_slave_isolate ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( dst_req ), - .slv_resp_o ( dst_resp ), - .mst_req_o ( isolate_dst_req ), - .mst_resp_i ( isolate_dst_rsp ), - .isolate_i ( axi_isolate_i ), - .isolated_o ( axi_isolated[0] ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( dst_req ), + .slv_resp_o ( dst_resp ), + .mst_req_o ( isolate_dst_req ), + .mst_resp_i ( isolate_dst_resp ), + .isolate_i ( axi_isolate_i ), + .isolated_o ( axi_isolated[0] ) ); axi_dw_converter_intf #( From f8a569797d1116be3117f3f84bab5477be744bc9 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 29 Apr 2023 09:10:53 +0200 Subject: [PATCH 015/207] Removed slave axi_isolate. --- rtl/pulp_cluster.sv | 33 ++++----------------------------- 1 file changed, 4 insertions(+), 29 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 4a9ff325..42bc776a 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -1093,10 +1093,6 @@ tcdm_banks_wrap #( `AXI_TYPEDEF_REQ_T(c2s_req_t,c2s_aw_chan_t,c2s_w_chan_t,c2s_ar_chan_t) `AXI_TYPEDEF_RESP_T(c2s_resp_t,c2s_b_chan_t,c2s_r_chan_t) -logic [1:0] axi_isolated; - -assign axi_isolated_o = |axi_isolated; - c2s_req_t src_req, isolate_src_req ; c2s_resp_t src_resp, isolate_src_resp; @@ -1121,7 +1117,7 @@ axi_isolate #( .mst_req_o ( src_req ), .mst_resp_i ( src_resp ), .isolate_i ( axi_isolate_i ), - .isolated_o ( axi_isolated[1] ) + .isolated_o ( axi_isolated_o ) ); axi_cdc_src #( @@ -1168,8 +1164,8 @@ axi_cdc_src #( s2c_req_t dst_req , isolate_dst_req; s2c_resp_t dst_resp, isolate_dst_resp; -`AXI_ASSIGN_FROM_REQ(s_data_slave_32,isolate_dst_req) -`AXI_ASSIGN_TO_RESP(isolate_dst_resp,s_data_slave_32) +`AXI_ASSIGN_FROM_REQ(s_data_slave_32,dst_req) +`AXI_ASSIGN_TO_RESP(dst_resp,s_data_slave_32) axi_cdc_dst #( .aw_chan_t (s2c_aw_chan_t), @@ -1179,7 +1175,7 @@ axi_cdc_dst #( .ar_chan_t (s2c_ar_chan_t), .axi_req_t (s2c_req_t ), .axi_resp_t(s2c_resp_t ), - .LogDepth ( LOG_DEPTH ) + .LogDepth ( LOG_DEPTH ) ) axi_slave_cdc_i ( .dst_rst_ni ( rst_ni ), .dst_clk_i ( clk_i ), @@ -1202,27 +1198,6 @@ axi_cdc_dst #( .async_data_slave_r_data_o ( async_data_slave_r_data_o ) ); -axi_isolate #( - .NumPending ( 8 ), - .TerminateTransaction ( 1 ), - .AtopSupport ( 1 ), - .AxiAddrWidth ( AXI_ADDR_WIDTH ), - .AxiDataWidth ( AXI_DATA_C2S_WIDTH ), - .AxiIdWidth ( AXI_ID_IN_WIDTH ), - .AxiUserWidth ( AXI_USER_WIDTH ), - .axi_req_t ( s2c_req_t ), - .axi_resp_t ( s2c_resp_t ) -) i_axi_slave_isolate ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( dst_req ), - .slv_resp_o ( dst_resp ), - .mst_req_o ( isolate_dst_req ), - .mst_resp_i ( isolate_dst_resp ), - .isolate_i ( axi_isolate_i ), - .isolated_o ( axi_isolated[0] ) -); - axi_dw_converter_intf #( .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), From 6c0b6b600d9285063bb88db9f78a08d33fde5482 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Tue, 9 May 2023 16:52:06 +0200 Subject: [PATCH 016/207] Bump FPU dependency to pulp-v0.1.1 --- Bender.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index 7bfc8efb..64789eed 100644 --- a/Bender.yml +++ b/Bender.yml @@ -26,7 +26,7 @@ dependencies: timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: "b26d1d6c5043bc6c535e23bf61b51313c802e44a" } # branch: michaero/safety-island-clic + cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: "f67ee07376845b8b8975f86c831c5d17cffcc5cb" } # branch: safety-island-clic ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", version: 1.1.0} hwpe-datamover-example: { git: "https://github.com/pulp-platform/hwpe-datamover-example.git", version: 1.0.1 } From 9445f35258ee9221586a26c40556b28b0f91822c Mon Sep 17 00:00:00 2001 From: aottaviano Date: Tue, 9 May 2023 17:00:28 +0200 Subject: [PATCH 017/207] Bump fpu_interco --- Bender.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index 64789eed..ec50a19a 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,7 +20,7 @@ dependencies: mchan: { git: "https://github.com/pulp-platform/mchan.git", version: 1.2.3 } hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "9e53e957f7e0fd88616a5f3fbcc2617fbc3c9d0d" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 } - fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "250b376bb68bd3b4b13c5b8f5ac2155e32152733" } # branch: yt/carfield + fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "e8195bb7b3f9fc2f7e968b4fcabf4a456afbe9d0" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0-beta.4 } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } From 3f420459b595d9847fa29705f44f9179173bf492 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Tue, 9 May 2023 17:11:33 +0200 Subject: [PATCH 018/207] Bump fpu_interco to FPU pulp-v0.1.1 --- Bender.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index ec50a19a..cf80f63e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,7 +20,7 @@ dependencies: mchan: { git: "https://github.com/pulp-platform/mchan.git", version: 1.2.3 } hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "9e53e957f7e0fd88616a5f3fbcc2617fbc3c9d0d" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 } - fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "e8195bb7b3f9fc2f7e968b4fcabf4a456afbe9d0" } # branch: yt/carfield + fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "bfee94c2f2222069a5dcc9759ddaa5da56cf94bc" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0-beta.4 } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } From f18f07d7c99dd3d97197636610112b359c14af3c Mon Sep 17 00:00:00 2001 From: aottaviano Date: Tue, 9 May 2023 17:22:02 +0200 Subject: [PATCH 019/207] Bump fpu_interco * Fix syntax error --- Bender.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index cf80f63e..d93f3f07 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,7 +20,7 @@ dependencies: mchan: { git: "https://github.com/pulp-platform/mchan.git", version: 1.2.3 } hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "9e53e957f7e0fd88616a5f3fbcc2617fbc3c9d0d" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 } - fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "bfee94c2f2222069a5dcc9759ddaa5da56cf94bc" } # branch: yt/carfield + fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "7a7899bfee33fcfe9d6166bd3d305cd1fb7118fc" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0-beta.4 } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } From 507ef1683e736d4aef7313f6c84c6854e49fa9c2 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 11 May 2023 19:38:27 +0200 Subject: [PATCH 020/207] Partial iDMA integration; bump mchan to fixed parametrization version; other general fixes. --- Bender.yml | 19 +- rtl/core_region.sv | 12 +- rtl/idma_wrap.sv | 467 ++++++++++++++++++++++++++++ rtl/{dmac_wrap.sv => mchan_wrap.sv} | 37 ++- rtl/pulp_cluster.sv | 125 +++++--- rtl/tcdm_banks_wrap.sv | 4 +- 6 files changed, 595 insertions(+), 69 deletions(-) create mode 100644 rtl/idma_wrap.sv rename rtl/{dmac_wrap.sv => mchan_wrap.sv} (96%) diff --git a/Bender.yml b/Bender.yml index d93f3f07..8242e4bf 100644 --- a/Bender.yml +++ b/Bender.yml @@ -15,10 +15,11 @@ dependencies: axi2mem: { git: "https://github.com/pulp-platform/axi2mem.git", rev: "6973e0434d26ba578cdb4aa69c26c1facd1a3f15" } # deprecated, replace with axi_to_mem in axi repo axi2per: { git: "https://github.com/pulp-platform/axi2per.git", version: 1.0.1 } per2axi: { git: "https://github.com/pulp-platform/per2axi.git", version: 1.0.4 } - cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", version: 1.1.1 } + cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: "1.4.1" } - mchan: { git: "https://github.com/pulp-platform/mchan.git", version: 1.2.3 } - hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "9e53e957f7e0fd88616a5f3fbcc2617fbc3c9d0d" } # branch: yt/carfield + mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization + idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master + hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a7e3f4e4c7fe607bcd6b9d94db77f612fd6ef6be" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 } fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "7a7899bfee33fcfe9d6166bd3d305cd1fb7118fc" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0-beta.4 } @@ -27,10 +28,11 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: "f67ee07376845b8b8975f86c831c5d17cffcc5cb" } # branch: safety-island-clic - ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } - scm: { git: "https://github.com/pulp-platform/scm.git", version: 1.1.0} + # ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } + scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating hwpe-datamover-example: { git: "https://github.com/pulp-platform/hwpe-datamover-example.git", version: 1.0.1 } hci: { git: "https://github.com/pulp-platform/hci.git", version: 1.0.8 } + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 50270f7f5b0ac512f8c35cfca15b7c70f74b4b0e } # branch: master export_include_dirs: - include @@ -47,7 +49,12 @@ sources: - rtl/cluster_clock_gate.sv - rtl/cluster_event_map.sv - rtl/cluster_timer_wrap.sv - - rtl/dmac_wrap.sv + - target: mchan + files: + - rtl/mchan_wrap.sv + - target: not(mchan) + files: + - rtl/idma_wrap.sv - rtl/hwpe_subsystem.sv - rtl/instr_width_converter.sv - rtl/per2axi_wrap.sv diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 74bde915..e2aee76c 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -93,7 +93,8 @@ module core_region // Interface for DEMUX to TCDM INTERCONNECT ,PERIPHERAL INTERCONNECT and DMA CONTROLLER hci_core_intf.master tcdm_data_master, - XBAR_TCDM_BUS.Master dma_ctrl_master, + // XBAR_TCDM_BUS.Master dma_ctrl_master, // FIXME: iDMA + hci_core_intf.master dma_ctrl_master, XBAR_PERIPH_BUS.Master eu_ctrl_master, XBAR_PERIPH_BUS.Master periph_data_master, @@ -455,6 +456,8 @@ module core_region assign tcdm_data_master.boffs = '0; assign tcdm_data_master.lrdy = '1; + assign periph_demux_bus.id = '0; + periph_demux periph_demux_i ( .clk ( clk_int ), .rst_ni ( rst_ni ), @@ -473,12 +476,12 @@ module core_region .data_req_o_MH ( dma_ctrl_master.req ), .data_add_o_MH ( dma_ctrl_master.add ), .data_wen_o_MH ( dma_ctrl_master.wen ), - .data_wdata_o_MH ( dma_ctrl_master.wdata ), + .data_wdata_o_MH ( dma_ctrl_master.data ), .data_be_o_MH ( dma_ctrl_master.be ), .data_gnt_i_MH ( dma_ctrl_master.gnt ), .data_r_valid_i_MH ( dma_ctrl_master.r_valid ), - .data_r_rdata_i_MH ( dma_ctrl_master.r_rdata ), + .data_r_rdata_i_MH ( dma_ctrl_master.r_data ), .data_r_opc_i_MH ( dma_ctrl_master.r_opc ), .data_req_o_EU ( eu_ctrl_master.req ), @@ -493,6 +496,9 @@ module core_region .data_r_opc_i_EU ( eu_ctrl_master.r_opc ) ); + assign dma_ctrl_master.boffs = '0; + assign dma_ctrl_master.lrdy = '1; + /* debug stuff */ //synopsys translate_off diff --git a/rtl/idma_wrap.sv b/rtl/idma_wrap.sv new file mode 100644 index 00000000..caec88b3 --- /dev/null +++ b/rtl/idma_wrap.sv @@ -0,0 +1,467 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +/* + * dmac_wrap.sv + * Thomas Benz + * Michael Rogenmoser + */ + +// DMA Core wrapper + +`include "axi/assign.svh" +`include "axi/typedef.svh" +`include "idma/typedef.svh" +`include "register_interface/typedef.svh" + +module dmac_wrap #( + parameter int unsigned NB_CORES = 4, + parameter int unsigned AXI_ADDR_WIDTH = 32, + parameter int unsigned AXI_DATA_WIDTH = 64, + parameter int unsigned AXI_USER_WIDTH = 6, + parameter int unsigned AXI_ID_WIDTH = 4, + parameter int unsigned PE_ID_WIDTH = 1, + parameter int unsigned NB_PE_PORTS = 1, + parameter int unsigned DATA_WIDTH = 32, + parameter int unsigned ADDR_WIDTH = 32, + parameter int unsigned BE_WIDTH = DATA_WIDTH/8, + parameter int unsigned NUM_STREAMS = 1, // Only 1 for now + parameter int unsigned TCDM_SIZE = 0, + parameter int unsigned TwoDMidend = 1, // Leave this on for now + parameter int unsigned NB_OUTSND_BURSTS = 8, + parameter int unsigned GLOBAL_QUEUE_DEPTH = 16, + parameter int unsigned BACKEND_QUEUE_DEPTH = 16, + parameter logic [AXI_ADDR_WIDTH-1:0] ClusterBaseAddr = 'h10000000 +) ( + input logic clk_i, + input logic rst_ni, + input logic test_mode_i, + XBAR_PERIPH_BUS.Slave pe_ctrl_slave[NB_PE_PORTS-1:0], + hci_core_intf.slave ctrl_slave[NB_CORES-1:0], + hci_core_intf.master tcdm_master[3:0], + AXI_BUS.Master ext_master, + output logic [NB_CORES-1:0] term_event_o, + output logic [NB_CORES-1:0] term_irq_o, + output logic [NB_PE_PORTS-1:0] term_event_pe_o, + output logic [NB_PE_PORTS-1:0] term_irq_pe_o, + output logic busy_o +); + + localparam int unsigned NumRegs = NB_CORES+NB_PE_PORTS; + localparam int unsigned MstIdxWidth = AXI_ID_WIDTH; + localparam int unsigned SlvIdxWidth = AXI_ID_WIDTH - $clog2(NUM_STREAMS); + + // CORE --> MCHAN CTRL INTERFACE BUS SIGNALS + logic [NumRegs-1:0][DATA_WIDTH-1:0] config_wdata; + logic [NumRegs-1:0][ADDR_WIDTH-1:0] config_add; + logic [NumRegs-1:0] config_req; + logic [NumRegs-1:0] config_wen; + logic [NumRegs-1:0][BE_WIDTH-1:0] config_be; + logic [NumRegs-1:0][PE_ID_WIDTH-1:0] config_id; + logic [NumRegs-1:0] config_gnt; + logic [NumRegs-1:0][DATA_WIDTH-1:0] config_r_rdata; + logic [NumRegs-1:0] config_r_valid; + logic [NumRegs-1:0] config_r_opc; + logic [NumRegs-1:0][PE_ID_WIDTH-1:0] config_r_id; + + // tie-off pe control ports + for (genvar i = 0; i < NB_CORES; i++) begin : gen_ctrl_registers + assign config_add[i] = ctrl_slave[i].add; + assign config_req[i] = ctrl_slave[i].req; + assign config_wdata[i] = ctrl_slave[i].data; + assign config_wen[i] = ctrl_slave[i].wen; + assign config_be[i] = ctrl_slave[i].be; + assign config_id[i] = '0; + assign ctrl_slave[i].gnt = config_gnt[i]; + assign ctrl_slave[i].r_opc = config_r_opc[i]; + assign ctrl_slave[i].r_valid = config_r_valid[i]; + assign ctrl_slave[i].r_data = config_r_rdata[i]; + end + + for (genvar i = 0; i < NB_PE_PORTS; i++) begin : gen_pe_ctrl_registers + assign config_add[NB_CORES+i] = pe_ctrl_slave[i].add; + assign config_req[NB_CORES+i] = pe_ctrl_slave[i].req; + assign config_wdata[NB_CORES+i] = pe_ctrl_slave[i].wdata; + assign config_wen[NB_CORES+i] = pe_ctrl_slave[i].wen; + assign config_be[NB_CORES+i] = pe_ctrl_slave[i].be; + assign config_id[NB_CORES+i] = pe_ctrl_slave[i].id; + assign pe_ctrl_slave[i].gnt = config_gnt[NB_CORES+i]; + assign pe_ctrl_slave[i].r_opc = config_r_opc[NB_CORES+i]; + assign pe_ctrl_slave[i].r_valid = config_r_valid[NB_CORES+i]; + assign pe_ctrl_slave[i].r_rdata = config_r_rdata[NB_CORES+i]; + assign pe_ctrl_slave[i].r_id = config_r_id[NB_CORES+i]; + end + + // AXI4+ATOP types + typedef logic [AXI_ADDR_WIDTH-1:0] addr_t; + typedef logic [ADDR_WIDTH-1:0] mem_addr_t; + typedef logic [AXI_DATA_WIDTH-1:0] data_t; + typedef logic [SlvIdxWidth-1:0] slv_id_t; + typedef logic [MstIdxWidth-1:0] mst_id_t; + typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t; + typedef logic [AXI_USER_WIDTH-1:0] user_t; + // AXI4+ATOP channels typedefs + `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(mem_aw_chan_t, mem_addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, slv_id_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, mst_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, slv_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(mem_ar_chan_t, mem_addr_t, mst_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, slv_id_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, mst_id_t, user_t) + `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) + `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) + `AXI_TYPEDEF_REQ_T(mem_req_t, mem_aw_chan_t, w_chan_t, mem_ar_chan_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) + // BUS definitions + mst_req_t tcdm_req, soc_req; + mem_req_t tcdm_mem_req; + mst_resp_t soc_rsp; + mst_resp_t tcdm_rsp; + slv_req_t [NUM_STREAMS-1:0] dma_req; + slv_resp_t [NUM_STREAMS-1:0] dma_rsp; + // interface to structs + `AXI_ASSIGN_FROM_REQ(ext_master, soc_req) + `AXI_ASSIGN_TO_RESP(soc_rsp, ext_master) + + // Register BUS definitions + `REG_BUS_TYPEDEF_ALL(dma_regs, logic[9:0], logic[31:0], logic[3:0]) + dma_regs_req_t [NumRegs-1:0] dma_regs_req; + dma_regs_rsp_t [NumRegs-1:0] dma_regs_rsp; + + // iDMA struct definitions + localparam int unsigned TFLenWidth = AXI_ADDR_WIDTH; + localparam int unsigned NumDim = 2; // Support 2D midend for 2D transfers + localparam int unsigned RepWidth = 32; + localparam int unsigned StrideWidth = 32; + typedef logic [TFLenWidth-1:0] tf_len_t; + typedef logic [RepWidth-1:0] reps_t; + typedef logic [StrideWidth-1:0] strides_t; + + // iDMA request / response types + `IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, slv_id_t, addr_t, tf_len_t) + `IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t) + + // iDMA ND request + `IDMA_TYPEDEF_FULL_ND_REQ_T(idma_nd_req_t, idma_req_t, reps_t, strides_t) + + idma_nd_req_t twod_req, twod_req_queue; + idma_req_t burst_req; + idma_rsp_t idma_rsp; + + logic fe_valid, twod_queue_valid, be_valid, be_rsp_valid; + logic fe_ready, twod_queue_ready, be_ready, be_rsp_ready; + logic trans_complete, midend_busy; + idma_pkg::idma_busy_t idma_busy; + + // ------------------------------------------------------ + // FRONTEND + // ------------------------------------------------------ + + for (genvar i = 0; i < NumRegs; i++) begin : gen_core_regs + periph_to_reg #( + .AW ( 10 ), + .DW ( 32 ), + .BW ( 8 ), + .IW ( PE_ID_WIDTH ), + .req_t ( dma_regs_req_t ), + .rsp_t ( dma_regs_rsp_t ) + ) i_pe_translate ( + .clk_i, + .rst_ni, + .req_i ( config_req [i] ), + .add_i ( config_add [i][9:0] ), + .wen_i ( config_wen [i] ), + .wdata_i ( config_wdata [i] ), + .be_i ( config_be [i] ), + .id_i ( config_id [i] ), + .gnt_o ( config_gnt [i] ), + .r_rdata_o ( config_r_rdata [i] ), + .r_opc_o ( config_r_opc [i] ), + .r_id_o ( config_r_id [i] ), + .r_valid_o ( config_r_valid [i] ), + .reg_req_o ( dma_regs_req [i] ), + .reg_rsp_i ( dma_regs_rsp [i] ) + ); + end + + idma_reg32_2d_frontend #( + .NumRegs ( NumRegs ), + .IdCounterWidth ( 28 ), + .dma_regs_req_t ( dma_regs_req_t ), + .dma_regs_rsp_t ( dma_regs_rsp_t ), + .burst_req_t ( idma_nd_req_t ) + ) i_idma_reg32_2d_frontend ( + .clk_i, + .rst_ni, + .dma_ctrl_req_i ( dma_regs_req ), + .dma_ctrl_rsp_o ( dma_regs_rsp ), + .burst_req_o ( twod_req ), + .valid_o ( fe_valid ), + .ready_i ( fe_ready ), + .backend_idle_i ( ~busy_o ), + .trans_complete_i ( trans_complete ) + ); + + // interrupts and events (currently broadcast tx_cplt event only) + assign term_event_pe_o = |trans_complete ? '1 : '0; + assign term_irq_pe_o = '0; + assign term_event_o = |trans_complete ? '1 : '0; + assign term_irq_o = '0; + + assign busy_o = midend_busy | |idma_busy; + + // ------------------------------------------------------ + // MIDEND + // ------------------------------------------------------ + + // global (2D) request FIFO + stream_fifo #( + .DEPTH ( GLOBAL_QUEUE_DEPTH ), + .T (idma_nd_req_t ) + ) i_2D_request_fifo ( + .clk_i, + .rst_ni, + .flush_i ( 1'b0 ), + .testmode_i ( test_mode_i ), + .usage_o (/*NOT CONNECTED*/), + + .data_i ( twod_req ), + .valid_i ( fe_valid ), + .ready_o ( fe_ready ), + + .data_o ( twod_req_queue ), + .valid_o ( twod_queue_valid ), + .ready_i ( twod_queue_ready ) + ); + + localparam logic [1:0][31:0] RepWidths = '{default: 32'd32}; + + idma_nd_midend #( + .NumDim ( NumDim ), + .addr_t ( addr_t ), + .idma_req_t ( idma_req_t ), + .idma_rsp_t ( idma_rsp_t ), + .idma_nd_req_t( idma_nd_req_t ), + .RepWidths ( RepWidths ) + ) i_idma_2D_midend ( + .clk_i, + .rst_ni, + + .nd_req_i ( twod_req_queue ), + .nd_req_valid_i ( twod_queue_valid ), + .nd_req_ready_o ( twod_queue_ready ), + + .nd_rsp_o (/*NOT CONNECTED*/ ), + .nd_rsp_valid_o ( trans_complete ), + .nd_rsp_ready_i ( 1'b1 ), // Always ready to accept completed transfers + + .burst_req_o ( burst_req ), + .burst_req_valid_o( be_valid ), + .burst_req_ready_i( be_ready ), + + .burst_rsp_i ( idma_rsp ), + .burst_rsp_valid_i( be_rsp_valid ), + .burst_rsp_ready_o( be_rsp_ready ), + + .busy_o ( midend_busy ) + ); + + // ------------------------------------------------------ + // BACKEND + // ------------------------------------------------------ + + idma_backend #( + .DataWidth ( AXI_DATA_WIDTH ), + .AddrWidth ( AXI_ADDR_WIDTH ), + .UserWidth ( AXI_USER_WIDTH ), + .AxiIdWidth ( AXI_ID_WIDTH ), + .NumAxInFlight ( NB_OUTSND_BURSTS ), + .BufferDepth ( 3 ), + .TFLenWidth ( TFLenWidth ), + .RAWCouplingAvail ( 1'b1 ), + .MemSysDepth ( 32'd0 ), + .MaskInvalidData ( 1'b1 ), + .HardwareLegalizer ( 1'b1 ), + .RejectZeroTransfers ( 1'b1 ), + .ErrorCap ( idma_pkg::NO_ERROR_HANDLING ), + .idma_req_t ( idma_req_t ), + .idma_rsp_t ( idma_rsp_t ), + .idma_eh_req_t ( idma_pkg::idma_eh_req_t ), + .idma_busy_t ( idma_pkg::idma_busy_t ), + .protocol_req_t ( slv_req_t ), + .protocol_rsp_t ( slv_resp_t ), + .aw_chan_t ( slv_aw_chan_t ), + .ar_chan_t ( slv_ar_chan_t ) + ) i_idma_backend ( + .clk_i, + .rst_ni, + .testmode_i ( test_mode_i ), + + .idma_req_i ( burst_req ), + .req_valid_i ( be_valid ), + .req_ready_o ( be_ready ), + + .idma_rsp_o ( idma_rsp ), + .rsp_valid_o ( be_rsp_valid ), + .rsp_ready_i ( be_rsp_ready ), + + .idma_eh_req_i ( '0 ), // No error handling + .eh_req_valid_i ( 1'b1 ), + .eh_req_ready_o (/*NOT CONNECTED*/), + + .protocol_req_o ( dma_req ), + .protocol_rsp_i ( dma_rsp ), + .busy_o ( idma_busy ) + ); + + // ------------------------------------------------------ + // AXI connection to EXT/TCDM + // ------------------------------------------------------ + + // xbar + localparam int unsigned NumRules = 3; + typedef struct packed { + int unsigned idx; + logic [AXI_ADDR_WIDTH-1:0] start_addr; + logic [AXI_ADDR_WIDTH-1:0] end_addr; + } xbar_rule_t; + xbar_rule_t [NumRules-1:0] addr_map; + logic [AXI_ADDR_WIDTH-1:0] cluster_base_addr; + assign cluster_base_addr = ClusterBaseAddr; /* + (cluster_id_i << 22);*/ + assign addr_map = '{ + '{ // SoC low + start_addr: '0, + end_addr: cluster_base_addr, + idx: 0 + }, + '{ // TCDM + start_addr: cluster_base_addr, + end_addr: cluster_base_addr + TCDM_SIZE, + idx: 1 + }, + '{ // SoC high + start_addr: cluster_base_addr + TCDM_SIZE, + end_addr: '1, + idx: 0 + } + }; + localparam int unsigned NumMstPorts = 2; + localparam int unsigned NumSlvPorts = NUM_STREAMS; + + /* verilator lint_off WIDTHCONCAT */ + localparam axi_pkg::xbar_cfg_t XbarCfg = '{ + NoSlvPorts: NumSlvPorts, + NoMstPorts: NumMstPorts, + MaxMstTrans: NB_OUTSND_BURSTS, + MaxSlvTrans: NB_OUTSND_BURSTS, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_PORTS, + PipelineStages: 0, + AxiIdWidthSlvPorts: SlvIdxWidth, + AxiIdUsedSlvPorts: SlvIdxWidth, + UniqueIds: 1'b0, + AxiAddrWidth: AXI_ADDR_WIDTH, + AxiDataWidth: AXI_DATA_WIDTH, + NoAddrRules: NumRules + }; + /* verilator lint_on WIDTHCONCAT */ + + axi_xbar #( + .Cfg ( XbarCfg ), + .slv_aw_chan_t( slv_aw_chan_t ), + .mst_aw_chan_t( mst_aw_chan_t ), + .w_chan_t ( w_chan_t ), + .slv_b_chan_t ( slv_b_chan_t ), + .mst_b_chan_t ( mst_b_chan_t ), + .slv_ar_chan_t( slv_ar_chan_t ), + .mst_ar_chan_t( mst_ar_chan_t ), + .slv_r_chan_t ( slv_r_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ), + .slv_req_t ( slv_req_t ), + .slv_resp_t ( slv_resp_t ), + .mst_req_t ( mst_req_t ), + .mst_resp_t ( mst_resp_t ), + .rule_t ( xbar_rule_t ) + ) i_dma_axi_xbar ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_i ( test_mode_i ), + .slv_ports_req_i ( dma_req ), + .slv_ports_resp_o ( dma_rsp ), + .mst_ports_req_o ( { tcdm_req, soc_req } ), + .mst_ports_resp_i ( { tcdm_rsp, soc_rsp } ), + .addr_map_i ( addr_map ), + .en_default_mst_port_i ( '0 ), + .default_mst_port_i ( '0 ) + ); + + localparam int unsigned TcdmFifoDepth = 1; + `AXI_ASSIGN_REQ_STRUCT(tcdm_mem_req, tcdm_req) + + axi_to_mem_split #( + .axi_req_t ( mem_req_t ), + .axi_resp_t ( mst_resp_t ), + .AddrWidth ( ADDR_WIDTH ), + .AxiDataWidth ( AXI_DATA_WIDTH ), + .IdWidth ( MstIdxWidth ), + .MemDataWidth ( DATA_WIDTH ), + .BufDepth ( TcdmFifoDepth ), + .HideStrb ( 1'b1 ) + ) i_axi_to_mem ( + .clk_i, + .rst_ni, + .busy_o (), + .axi_req_i ( tcdm_mem_req ), + .axi_resp_o ( tcdm_rsp ), + .mem_req_o ( { tcdm_master[0].req, tcdm_master[1].req, + tcdm_master[2].req, tcdm_master[3].req } ), + .mem_gnt_i ( { tcdm_master[0].gnt, tcdm_master[1].gnt, + tcdm_master[2].gnt, tcdm_master[3].gnt } ), + .mem_addr_o ( { tcdm_master[0].add, tcdm_master[1].add, + tcdm_master[2].add, tcdm_master[3].add } ), + .mem_wdata_o ( { tcdm_master[0].data, tcdm_master[1].data, + tcdm_master[2].data, tcdm_master[3].data } ), + .mem_strb_o ( { tcdm_master[0].be, tcdm_master[1].be, + tcdm_master[2].be, tcdm_master[3].be } ), + .mem_atop_o ( ), + .mem_we_o ( { tcdm_master_we_0, tcdm_master_we_1, + tcdm_master_we_2, tcdm_master_we_3 } ), + .mem_rvalid_i ( { tcdm_master[0].r_valid, tcdm_master[1].r_valid, + tcdm_master[2].r_valid, tcdm_master[3].r_valid } ), + .mem_rdata_i ( { tcdm_master[0].r_data, tcdm_master[1].r_data, + tcdm_master[2].r_data, tcdm_master[3].r_data } ) + ); + + // tie-off TCDM master port + // for (genvar i = 0; i < 4; i++) begin : gen_tie_off_unused_tcdm_master + // assign tcdm_master[i].r_opc = '0; + // end + + // flip we polarity + assign tcdm_master[0].wen = !tcdm_master_we_0; + assign tcdm_master[1].wen = !tcdm_master_we_1; + assign tcdm_master[2].wen = !tcdm_master_we_2; + assign tcdm_master[3].wen = !tcdm_master_we_3; + + assign tcdm_master[0].boffs = '0; + assign tcdm_master[1].boffs = '0; + assign tcdm_master[2].boffs = '0; + assign tcdm_master[3].boffs = '0; + + assign tcdm_master[0].lrdy = '1; + assign tcdm_master[1].lrdy = '1; + assign tcdm_master[2].lrdy = '1; + assign tcdm_master[3].lrdy = '1; + + assign tcdm_master[0].user = '0; + assign tcdm_master[1].user = '0; + assign tcdm_master[2].user = '0; + assign tcdm_master[3].user = '0; + +endmodule : dmac_wrap diff --git a/rtl/dmac_wrap.sv b/rtl/mchan_wrap.sv similarity index 96% rename from rtl/dmac_wrap.sv rename to rtl/mchan_wrap.sv index 916a7d4a..fdb5eeed 100644 --- a/rtl/dmac_wrap.sv +++ b/rtl/mchan_wrap.sv @@ -32,15 +32,16 @@ module dmac_wrap parameter ADDR_WIDTH = 32, parameter BE_WIDTH = DATA_WIDTH/8 ) -( +( input logic clk_i, input logic rst_ni, input logic test_mode_i, - - XBAR_TCDM_BUS.Slave ctrl_slave[NB_CORES-1:0], + //FIXME: iDMA + // XBAR_TCDM_BUS.Slave ctrl_slave[NB_CORES-1:0], + hci_core_intf.slave ctrl_slave[NB_CORES-1:0], XBAR_PERIPH_BUS.Slave cl_ctrl_slave, XBAR_PERIPH_BUS.Slave fc_ctrl_slave, - + hci_core_intf.master tcdm_master[3:0], AXI_BUS.Master ext_master, output logic term_event_cl_o, @@ -51,7 +52,7 @@ module dmac_wrap output logic [NB_CORES-1:0] term_irq_o, output logic busy_o ); - + // CORE --> MCHAN CTRL INTERFACE BUS SIGNALS logic [NB_CTRLS-1:0][DATA_WIDTH-1:0] s_ctrl_bus_wdata; logic [NB_CTRLS-1:0][ADDR_WIDTH-1:0] s_ctrl_bus_add; @@ -82,16 +83,16 @@ module dmac_wrap assign s_ctrl_bus_add[i] = ctrl_slave[i].add; assign s_ctrl_bus_req[i] = ctrl_slave[i].req; - assign s_ctrl_bus_wdata[i] = ctrl_slave[i].wdata; + assign s_ctrl_bus_wdata[i] = ctrl_slave[i].data; assign s_ctrl_bus_wen[i] = ctrl_slave[i].wen; assign s_ctrl_bus_be[i] = ctrl_slave[i].be; assign s_ctrl_bus_id[i] = i; - + assign ctrl_slave[i].gnt = s_ctrl_bus_gnt[i]; assign ctrl_slave[i].r_opc = s_ctrl_bus_r_opc[i]; assign ctrl_slave[i].r_valid = s_ctrl_bus_r_valid[i]; - assign ctrl_slave[i].r_rdata = s_ctrl_bus_r_rdata[i]; + assign ctrl_slave[i].r_data = s_ctrl_bus_r_rdata[i]; end // for (genvar i=0; i $1 - bender script $(VSIM) --vlog-arg="$(VLOG_ARGS)" $2 | grep -v "set ROOT" >> $1 + bender script vsim --vlog-arg="$(VLOG_ARGS)" $2 | grep -v "set ROOT" >> $1 echo >> $1 endef @@ -75,7 +85,7 @@ sim_clean: rm -rf work scripts/compile.tcl: | Bender.lock - $(call generate_vsim, $@, -t rtl -t test -t cluster_standalone,..) + $(call generate_vsim, $@, $(bender_defs) $(bender_targs),..) # compile the elfloader.cpp $(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr) @@ -86,19 +96,19 @@ $(dpi-library)/cl_dpi.so: $(dpi) $(CXX) -shared -m64 -o $(dpi-library)/cl_dpi.so $? -L$(RISCV)/lib -L$(SPIKE_ROOT)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_ROOT)/lib -lfesvr $(library): - vlib${questa_version} $(library) + $(QUESTA) vlib $(library) compile: $(library) $(dpi) $(dpi-library)/cl_dpi.so @test -f Bender.lock || { echo "ERROR: Bender.lock file does not exist. Did you run make checkout in bender mode?"; exit 1; } @test -f scripts/compile.tcl || { echo "ERROR: scripts/compile.tcl file does not exist. Did you run make scripts in bender mode?"; exit 1; } - vsim -c -do 'source scripts/compile.tcl; quit' + $(VSIM) -c -do 'source scripts/compile.tcl; quit' build: compile $(dpi) - vopt $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis + $(VOPT) $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis run: - vsim +permissive $(questa-flags) $(questa-cmd) -suppress 3053 -suppress 8885 -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) +APP=$(elf-bin) +notimingchecks +nospecify -t 1ps \ + $(VSIM) +permissive $(questa-flags) $(questa-cmd) -suppress 3053 -suppress 8885 -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) +APP=$(elf-bin) +notimingchecks +nospecify -t 1ps \ $(uvm-flags) $(QUESTASIM_FLAGS) -sv_lib $(dpi-library)/cl_dpi \ ${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) ++$(cl-bin) | tee sim.log diff --git a/README.md b/README.md index e124128e..0823b6d2 100644 --- a/README.md +++ b/README.md @@ -26,10 +26,11 @@ To simulate the cluster on its own, you can perform the following steps: RISCV GCC toolchain](https://github.com/pulp-platform/pulp-riscv-gcc) to use a pre-built release. -2. We need RV64 toolchain to compile DPI libraries. Export it to a `RISCV` env - variable. Please refer to [RISC-V GNU +2. We need RV64 toolchain to compile DPI libraries. To this purpose, export the + RV64 toolchain to a `RISCV` env variable and also export your questa + installation path to a `QUESTA_HOME` env variable. Please refer to [RISC-V GNU toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain/) to use a - pre-built release. + pre-built RV64 toolchain release. 3. Compile the hw: ``` @@ -38,17 +39,17 @@ To simulate the cluster on its own, you can perform the following steps: make build ``` -4. Source the environment: - ``` - source env/env.sh - ``` - -5. Download the sw stack and bare-metal tests: +4. Download the sw stack and bare-metal tests: ``` make pulp-runtime make regression-tests ``` +5. Source the environment: + ``` + source env/env.sh + ``` + 6. Run the tests. Choose any test among the `parallel_bare_tests` and the `mchan_tests`, move into the related folder and do: diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index 86aa30b7..b7150fa9 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -56,8 +56,8 @@ module cluster_bus_wrap else if (AXI_ID_OUT_WIDTH > AXI_ID_IN_WIDTH + $clog2(NB_SLAVE)) $warning("ID width of the AXI output port has the wrong length. It is larger than the required value. Trim it to the right length to get rid of this warning."); - if (AXI_ADDR_WIDTH != 48) - $fatal(1,"Address map is only defined for 48-bit addresses!"); + // if (AXI_ADDR_WIDTH != 48) + // $fatal(1,"Address map is only defined for 48-bit addresses!"); if (TCDM_SIZE == 0) $fatal(1,"TCDM size must be non-zero!"); if (TCDM_SIZE >2048*1024) // Periph start address is at offset 0x0020_0000, which actually allows for up to 2 MiB of TCDM, diff --git a/rtl/tcdm_banks_wrap.sv b/rtl/tcdm_banks_wrap.sv index b216cf15..0b856a42 100644 --- a/rtl/tcdm_banks_wrap.sv +++ b/rtl/tcdm_banks_wrap.sv @@ -54,12 +54,12 @@ module tcdm_banks_wrap #( .NumWords (BankSize ), // Number of Words in data array .DataWidth (DataWidth), // Data signal width .NumPorts (1 ), // Number of read and write ports - .Latency (1 ), // Latency when the read data is available `ifndef SYNTHESIS .ByteWidth (8 ), // Width of a data byte .SimInit ("ones" ), // Simulation initialization - .PrintSimCfg(0 ) // Print configuration + .PrintSimCfg(0 ), // Print configuration `endif + .Latency (1 ) // Latency when the read data is available ) i_bank ( .clk_i (clk_i ), // Clock .rst_ni (rst_ni ), // Asynchronous reset active low diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 0ed5c3e7..51b55f9b 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -296,6 +296,8 @@ module pulp_cluster_tb; .clk_i ( s_clk ), .rst_ni ( s_rstn ), .ref_clk_i ( s_clk ), + .axi_isolate_i ( '0 ), + .axi_isolated_o ( ), .pmu_mem_pwdn_i ( 1'b0 ), From d50efde86a76b7ed9fb7b2b5929f42f8cf7f6d70 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 15 May 2023 15:29:03 +0200 Subject: [PATCH 022/207] Bumped core and added setback signal. --- Bender.lock | 2 +- Bender.yml | 2 +- rtl/core_region.sv | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index e28c2733..5de862e1 100644 --- a/Bender.lock +++ b/Bender.lock @@ -74,7 +74,7 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cv32e40p: - revision: f67ee07376845b8b8975f86c831c5d17cffcc5cb + revision: 9b77611a1d0c681f4819798d95422b0b895528a2 version: null source: Git: https://github.com/pulp-platform/cv32e40p.git diff --git a/Bender.yml b/Bender.yml index b357be95..0bf1b99e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -27,7 +27,7 @@ dependencies: timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: "f67ee07376845b8b8975f86c831c5d17cffcc5cb" } # branch: safety-island-clic + cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "9b77611" } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating hwpe-datamover-example: { git: "https://github.com/pulp-platform/hwpe-datamover-example.git", version: 1.0.1 } diff --git a/rtl/core_region.sv b/rtl/core_region.sv index e2aee76c..9e9d203d 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -183,6 +183,7 @@ module core_region ) RISCV_CORE ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .setback_i ( '0 ), // Control Interface .pulp_clock_en_i ( clock_en_i ), .scan_cg_en_i ( test_mode_i ), From 2fe929632a95e27ebb3f135603835adb60b41fd2 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 15 May 2023 15:42:38 +0200 Subject: [PATCH 023/207] Bumped FPU interconnect. --- Bender.lock | 4 ++-- Bender.yml | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Bender.lock b/Bender.lock index 5de862e1..23a4eb68 100644 --- a/Bender.lock +++ b/Bender.lock @@ -105,10 +105,10 @@ packages: dependencies: - common_cells fpu_interco: - revision: 7a7899bfee33fcfe9d6166bd3d305cd1fb7118fc + revision: null version: null source: - Git: https://github.com/pulp-platform/fpu_interco.git + Path: working_dir/fpu_interco dependencies: - cv32e40p - fpnew diff --git a/Bender.yml b/Bender.yml index 0bf1b99e..d9dc3c36 100644 --- a/Bender.yml +++ b/Bender.yml @@ -21,7 +21,7 @@ dependencies: idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a7e3f4e4c7fe607bcd6b9d94db77f612fd6ef6be" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 } - fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "7a7899bfee33fcfe9d6166bd3d305cd1fb7118fc" } # branch: yt/carfield + fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "2c11ff8176a8b176f2bdd3fc019db2b7db44debf" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0-beta.4 } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } From 56d64633432a72de8da49c1f0418500a9c173ddb Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 16 May 2023 12:24:47 +0200 Subject: [PATCH 024/207] Updating FPU interconnect to align it with updated FPU. --- Bender.lock | 4 ++-- Bender.yml | 4 ++-- Makefile | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Bender.lock b/Bender.lock index 23a4eb68..2c7187d9 100644 --- a/Bender.lock +++ b/Bender.lock @@ -105,10 +105,10 @@ packages: dependencies: - common_cells fpu_interco: - revision: null + revision: 0769976fa51bdd820656a01161a4c46b88c59ac5 version: null source: - Path: working_dir/fpu_interco + Git: https://github.com/pulp-platform/fpu_interco.git dependencies: - cv32e40p - fpnew diff --git a/Bender.yml b/Bender.yml index d9dc3c36..057099e0 100644 --- a/Bender.yml +++ b/Bender.yml @@ -21,13 +21,13 @@ dependencies: idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a7e3f4e4c7fe607bcd6b9d94db77f612fd6ef6be" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 } - fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "2c11ff8176a8b176f2bdd3fc019db2b7db44debf" } # branch: yt/carfield + fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "0769976fa51bdd820656a01161a4c46b88c59ac5" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0-beta.4 } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "9b77611" } # `michaero/safety-island-clic` branch + cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: 9b77611a1d0c681f4819798d95422b0b895528a2 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating hwpe-datamover-example: { git: "https://github.com/pulp-platform/hwpe-datamover-example.git", version: 1.0.1 } diff --git a/Makefile b/Makefile index 1d25aa46..2657c26c 100644 --- a/Makefile +++ b/Makefile @@ -53,7 +53,7 @@ nonfree-init: # Dependencies # ################ -.PHONY: checkout +.PHONY: checkout scripts/compile.tcl ## Checkout/update dependencies using Bender checkout: bender checkout From 04350862b1edb8691588db772a363db62bf564e4 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 16 May 2023 19:12:07 +0200 Subject: [PATCH 025/207] First draft with power-rest and AXI isolate synchronization. --- Bender.yml | 1 + rtl/pulp_cluster.sv | 35 +++++++++++++++++++++++++---------- 2 files changed, 26 insertions(+), 10 deletions(-) diff --git a/Bender.yml b/Bender.yml index 057099e0..f1f8d1fc 100644 --- a/Bender.yml +++ b/Bender.yml @@ -33,6 +33,7 @@ dependencies: hwpe-datamover-example: { git: "https://github.com/pulp-platform/hwpe-datamover-example.git", version: 1.0.1 } hci: { git: "https://github.com/pulp-platform/hci.git", version: 1.0.8 } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 50270f7f5b0ac512f8c35cfca15b7c70f74b4b0e } # branch: master + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } export_include_dirs: - include diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 0d929b29..9e83f453 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -38,6 +38,8 @@ module pulp_cluster parameter CLUSTER_ALIAS = 1, parameter CLUSTER_ALIAS_BASE = 12'h000, + + parameter int unsigned SynchStages = 2, parameter TCDM_SIZE = 64*1024, // [B], must be 2**N parameter NB_TCDM_BANKS = 16, // must be 2**N @@ -141,6 +143,7 @@ module pulp_cluster input logic clk_i, input logic rst_ni, input logic ref_clk_i, + input logic pwr_on_rst_ni, input logic pmu_mem_pwdn_i, @@ -260,6 +263,8 @@ logic [NB_CORES-1:0] dbg_core_running; logic [NB_CORES-1:0] s_dbg_irq; logic s_hwpe_en; +logic axi_isolate_synch; + logic s_cluster_periphs_busy; logic s_axi2mem_busy; logic s_per2axi_busy; @@ -1140,6 +1145,16 @@ c2s_resp_t src_resp, isolate_src_resp; `AXI_ASSIGN_TO_REQ(isolate_src_req,s_data_master) `AXI_ASSIGN_FROM_RESP(s_data_master,isolate_src_resp) +sync #( + .STAGES ( SynchStages ), + .ResetValue ( 1'b0 ) +) i_isolate_synch ( + .clk_i ( clk_i ), + .rst_ni ( pwr_on_rst_ni ), + .serial_i ( axi_isolate_i ), + .serial_o ( axi_isolate_synch ) +); + axi_isolate #( .NumPending ( 8 ), .TerminateTransaction ( 1 ), @@ -1151,14 +1166,14 @@ axi_isolate #( .axi_req_t ( c2s_req_t ), .axi_resp_t ( c2s_resp_t ) ) i_axi_master_isolate ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( isolate_src_req ), - .slv_resp_o ( isolate_src_resp ), - .mst_req_o ( src_req ), - .mst_resp_i ( src_resp ), - .isolate_i ( axi_isolate_i ), - .isolated_o ( axi_isolated_o ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( isolate_src_req ), + .slv_resp_o ( isolate_src_resp ), + .mst_req_o ( src_req ), + .mst_resp_i ( src_resp ), + .isolate_i ( axi_isolate_synch ), + .isolated_o ( axi_isolated_o ) ); axi_cdc_src #( @@ -1171,7 +1186,7 @@ axi_cdc_src #( .axi_resp_t ( c2s_resp_t ), .LogDepth ( LOG_DEPTH ) ) axi_master_cdc_i ( - .src_rst_ni ( rst_ni ), + .src_rst_ni ( pwr_on_rst_ni ), .src_clk_i ( clk_i ), .src_req_i ( src_req ), .src_resp_o ( src_resp ), @@ -1218,7 +1233,7 @@ axi_cdc_dst #( .axi_resp_t(s2c_resp_t ), .LogDepth ( LOG_DEPTH ) ) axi_slave_cdc_i ( - .dst_rst_ni ( rst_ni ), + .dst_rst_ni ( pwr_on_rst_ni ), .dst_clk_i ( clk_i ), .dst_req_o ( dst_req ), .dst_resp_i ( dst_resp ), From 43bb73f5f239b6d9bade79ef4b5c62756bd58dc4 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 16 May 2023 19:39:15 +0200 Subject: [PATCH 026/207] Synchronized control signals and added mailbox interrupt. --- rtl/cluster_peripherals.sv | 3 +- rtl/pulp_cluster.sv | 58 ++++++++++++++++++++++++++++++++++---- 2 files changed, 54 insertions(+), 7 deletions(-) diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index c57c806a..af459850 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -56,6 +56,7 @@ module cluster_peripherals input logic [NB_CORES-1:0] dma_event_i, input logic [NB_CORES-1:0] dma_irq_i, + input logic mbox_irq_i, XBAR_PERIPH_BUS.Master dma_cfg_master[1:0], input logic dma_cl_event_i, @@ -134,7 +135,7 @@ module cluster_peripherals // decide between common or core-specific event sources generate for (genvar I=0; I Date: Tue, 16 May 2023 19:54:55 +0200 Subject: [PATCH 027/207] Connected `pwr_on_rst_ni` and `mbox_irq_i` in testbench. --- tb/pulp_cluster_tb.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 51b55f9b..4bf6d2c3 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -295,6 +295,7 @@ module pulp_cluster_tb; ) cluster_i ( .clk_i ( s_clk ), .rst_ni ( s_rstn ), + .pwr_on_rst_ni ( s_rstn ), .ref_clk_i ( s_clk ), .axi_isolate_i ( '0 ), .axi_isolated_o ( ), @@ -310,6 +311,7 @@ module pulp_cluster_tb; .dma_pe_irq_valid_o ( ), .dbg_irq_valid_i ( '0 ), + .mbox_irq_i ( '0 ), .pf_evt_ack_i ( 1'b1 ), .pf_evt_valid_o ( ), From 01c2d00e2bc9e79f180f7abc0dedcd114588b59c Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 19 May 2023 13:03:50 +0200 Subject: [PATCH 028/207] Making parallel matrix multiplication work --- Bender.local | 4 +++ Bender.lock | 10 +++--- Bender.yml | 6 ++-- Makefile | 4 +++ include/pulp_soc_defines.sv | 5 +++ rtl/core_demux.sv | 3 +- rtl/core_region.sv | 62 +++++++++++++++++++++++++++---------- rtl/pulp_cluster.sv | 33 ++++++++++---------- rtl/xbar_pe_wrap.sv | 2 +- tb/pulp_cluster_tb.sv | 1 + 10 files changed, 88 insertions(+), 42 deletions(-) create mode 100644 Bender.local diff --git a/Bender.local b/Bender.local new file mode 100644 index 00000000..723b1b0a --- /dev/null +++ b/Bender.local @@ -0,0 +1,4 @@ +overrides: + axi : { git: "https://github.com/pulp-platform/axi.git" , version: =0.39.0-beta.9 } + register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master + cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix diff --git a/Bender.lock b/Bender.lock index 2c7187d9..6e0f5d44 100644 --- a/Bender.lock +++ b/Bender.lock @@ -1,14 +1,14 @@ packages: apb: - revision: 56ca84b687c9f6dc650e2a7cb221cb2bd4b2a456 - version: 0.2.3 + revision: 77ddf073f194d44b9119949d2421be59789e69ae + version: 0.2.4 source: Git: https://github.com/pulp-platform/apb.git dependencies: - common_cells axi: - revision: fd60be8b51a4fa7476856be162ce3334474592ba - version: 0.39.0-beta.4 + revision: f24b1faf7bcf651f1aabdef5e8f99ce2fd817c2e + version: 0.39.0-beta.9 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -200,7 +200,7 @@ packages: dependencies: - axi_slice register_interface: - revision: 50270f7f5b0ac512f8c35cfca15b7c70f74b4b0e + revision: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 version: null source: Git: https://github.com/pulp-platform/register_interface.git diff --git a/Bender.yml b/Bender.yml index f1f8d1fc..d73c8c35 100644 --- a/Bender.yml +++ b/Bender.yml @@ -22,17 +22,17 @@ dependencies: hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a7e3f4e4c7fe607bcd6b9d94db77f612fd6ef6be" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 } fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "0769976fa51bdd820656a01161a4c46b88c59ac5" } # branch: yt/carfield - axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0-beta.4 } + axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0-beta.9 } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: 9b77611a1d0c681f4819798d95422b0b895528a2 } # `michaero/safety-island-clic` branch + cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "9b77611" } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating hwpe-datamover-example: { git: "https://github.com/pulp-platform/hwpe-datamover-example.git", version: 1.0.1 } hci: { git: "https://github.com/pulp-platform/hci.git", version: 1.0.8 } - register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 50270f7f5b0ac512f8c35cfca15b7c70f74b4b0e } # branch: master + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } export_include_dirs: diff --git a/Makefile b/Makefile index 2657c26c..51b50a5f 100644 --- a/Makefile +++ b/Makefile @@ -26,9 +26,13 @@ XVLOG_ARGS += -64bit -compile -vtimescale 1ns/1ns -quiet bender_defs += -D FEATURE_ICACHE_STAT bender_defs += -D PRIVATE_ICACHE bender_defs += -D HIERARCHY_ICACHE_32BIT +bender_defs += -D NO_FPU +bender_defs += -D TRACE_EXECUTION +bender_defs += -D CLUSTER_ALIAS bender_targs += -t rtl bender_targs += -t test +bender_targs += -t mchan bender_targs += -t cluster_standalone bender_targs += -t cv32e40p_use_ff_regfile diff --git a/include/pulp_soc_defines.sv b/include/pulp_soc_defines.sv index fd5d065e..5307196e 100644 --- a/include/pulp_soc_defines.sv +++ b/include/pulp_soc_defines.sv @@ -33,6 +33,11 @@ `define CLUST_FP_DIVSQRT 0 `define CLUST_SHARED_FP 0 `define CLUST_SHARED_FP_DIVSQRT 0 +`elsif NO_FPU + `define CLUST_FPU 0 + `define CLUST_FP_DIVSQRT 0 + `define CLUST_SHARED_FP 0 + `define CLUST_SHARED_FP_DIVSQRT 0 `else `define CLUST_FPU 1 `define CLUST_FP_DIVSQRT 1 diff --git a/rtl/core_demux.sv b/rtl/core_demux.sv index 0a9b864c..a7c347b3 100644 --- a/rtl/core_demux.sv +++ b/rtl/core_demux.sv @@ -21,6 +21,7 @@ module core_demux parameter DATA_WIDTH = 32, parameter BYTE_ENABLE_BIT = DATA_WIDTH/8, parameter REMAP_ADDRESS = 0, + parameter CLUSTER_ALIAS = 1, parameter CLUSTER_ALIAS_BASE = 12'h000 ) ( @@ -150,7 +151,7 @@ module core_demux assign data_add_int[27:0] = data_add_i[27:0]; -if (REMAP_ADDRESS) begin +if (REMAP_ADDRESS == 1) begin always_comb begin if(data_add_i[31:28] == base_addr_i) diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 9e9d203d..1d0c3714 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -35,6 +35,7 @@ module core_region parameter ADDR_WIDTH = 32, parameter DATA_WIDTH = 32, parameter INSTR_RDATA_WIDTH = 32, + parameter CLUSTER_ALIAS = 1, parameter CLUSTER_ALIAS_BASE = 12'h000, parameter REMAP_ADDRESS = 0, @@ -172,22 +173,33 @@ module core_region generate if ( CORE_TYPE_CL == 0 ) begin: CL_CORE assign boot_addr = boot_addr_i; - cv32e40p_core #( + cv32e40p_wrapper #( // .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), - .PULP_XPULP ( 0 ), // For now this is a no - .PULP_CLUSTER ( 1 ), - .FPU ( FPU ), + .PULP_XPULP ( 1 ), // For now this is a no + .PULP_CLUSTER ( 1 ), + .FPU ( FPU ), .NUM_EXTERNAL_PERF ( N_EXT_PERF_COUNTERS_ACTUAL ), + // .N_EXT_PERF_COUNTERS ( N_EXT_PERF_COUNTERS_ACTUAL ), .NUM_INTERRUPTS ( NUM_INTERRUPTS ), + // .PULP_OBI_INTF ( 1 ), + // .TRANS_STABLE ( 0 ), .PULP_ZFINX ( 0 ) + // .Zfinx ( 0 ), + // .WAPUTYPE ( WAPUTYPE ), + // .DM_HaltAddress ( DEBUG_START_ADDR + 16'h0800 ) ) RISCV_CORE ( - .clk_i ( clk_i ), + .clk_i ( clk_int ), .rst_ni ( rst_ni ), + // .clock_en_i ( clock_en_i ), + // .test_en_i ( test_mode_i ), .setback_i ( '0 ), // Control Interface .pulp_clock_en_i ( clock_en_i ), + // .fregfile_disable_i ( '1 ), .scan_cg_en_i ( test_mode_i ), .boot_addr_i ( boot_addr ), + // .core_id_i ( hart_id[3:0] ), + // .cluster_id_i ( cluster_id_i ), .mtvec_addr_i ( '0 ), .mtvt_addr_i ( '0 ), .dm_halt_addr_i ( DEBUG_START_ADDR + 16'h0800 ), @@ -208,6 +220,7 @@ module core_region .data_addr_o ( s_core_bus.add ), .data_wdata_o ( s_core_bus.wdata ), .data_rdata_i ( s_core_bus.r_rdata ), + // Shadow Memory Interface .shadow_req_o ( sadow_req ), .shadow_gnt_i ( '0 ), .shadow_rvalid_i ( '0 ), @@ -220,23 +233,37 @@ module core_region .data_atop_o ( core_data_atop ), // apu-interconnect // Handshake + // .apu_master_req_o ( apu_master_req_o ), + // .apu_master_ready_o ( apu_master_ready_o ), + // .apu_master_gnt_i ( apu_master_gnt_i ), .apu_req_o ( apu_master_req_o ), .apu_gnt_i ( apu_master_gnt_i ), // Request Bus + // .apu_master_operands_o ( apu_master_operands_o ), + // .apu_master_op_o ( apu_master_op_o ), + // .apu_master_type_o ( apu_master_type_o ), + // .apu_master_flags_o ( apu_master_flags_o ), .apu_operands_o ( apu_master_operands_o ), .apu_op_o ( apu_master_op_o ), .apu_type_o ( apu_master_type_o ), .apu_flags_o ( apu_master_flags_o ), // Response Bus + // .apu_master_valid_i ( apu_master_valid_i ), + // .apu_master_result_i ( apu_master_result_i ), + // .apu_master_flags_i ( apu_master_flags_i ), .apu_rvalid_i ( apu_master_valid_i ), .apu_result_i ( apu_master_result_i ), .apu_flags_i ( apu_master_flags_i ), // IRQ Interface + // .irq_i ( irq_req_i ), .irq_i ( core_irq_x ), + // .irq_id_i ( irq_id_i ), .irq_level_i ( '0 ), // CLIC interrupt level .irq_shv_i ( '0 ), // CLIC selective hardware vectoring .irq_ack_o ( irq_ack_o ), .irq_id_o ( irq_ack_id_o ), + // .irq_sec_i ( '0 ), + // .sec_lvl_o ( ), // Debug Interface .debug_req_i ( debug_req_i ), .debug_havereset_o ( debug_havereset_o ), @@ -244,12 +271,17 @@ module core_region .debug_halted_o ( debug_halted_o ), // Yet other control signals .fetch_enable_i ( fetch_en_i ), + // .core_busy_o ( core_busy_o ), .core_sleep_o ( core_sleep ), // External performance monitoring signals + // .ext_perf_counters_i ( perf_counters ) .external_perf_i ( perf_counters ) - ); + ); + assign core_busy_o = ~core_sleep; end else begin: CL_CORE assign boot_addr = boot_addr_i & 32'hFFFFFF00; // RI5CY expects 0x80 offset, Ibex expects 0x00 offset (adds reset offset 0x80 internally) + // Core busy + assign core_busy_o = ~core_sleep; if (INSTR_RDATA_WIDTH == 128) begin instr_width_converter ibex_width_converter ( @@ -366,17 +398,16 @@ module core_region .core_sleep_o ( core_sleep ) ); - // Ibex supports 32 additional fast interrupts and reads the interrupt lines directly. - // Convert ID back to interrupt lines - always_comb begin : gen_core_irq_x - core_irq_x = '0; - if (irq_req_i) begin - core_irq_x[irq_id_i] = 1'b1; - end - end end endgenerate + always_comb begin : gen_core_irq_x + core_irq_x = '0; + if (irq_req_i) begin + core_irq_x[irq_id_i] = 1'b1; + end + end + //assign debug_bus.r_opc = 1'b0; // Bind to 0 Unused Signals in CORE interface @@ -388,8 +419,6 @@ module core_region // Performance Counters assign perf_counters[4] = tcdm_data_master.req & (~tcdm_data_master.gnt); // Cycles lost due to contention - // Core busy - assign core_busy_o = ~core_sleep; //******************************************************** //****** DEMUX TO TCDM AND PERIPHERAL INTERCONNECT ******* @@ -401,6 +430,7 @@ module core_region .DATA_WIDTH ( 32 ), .BYTE_ENABLE_BIT ( DATA_WIDTH/8 ), .REMAP_ADDRESS ( REMAP_ADDRESS ), + .CLUSTER_ALIAS ( CLUSTER_ALIAS ), .CLUSTER_ALIAS_BASE ( CLUSTER_ALIAS_BASE ) ) core_demux_i ( .clk ( clk_int ), diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 25124fba..91cd7b80 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -144,6 +144,7 @@ module pulp_cluster input logic rst_ni, input logic ref_clk_i, input logic pwr_on_rst_ni, + input logic core_init_ni, input logic pmu_mem_pwdn_i, @@ -255,7 +256,6 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; logic [NB_CORES-1:0] fetch_enable_reg_int; logic [NB_CORES-1:0] fetch_en_int; -logic s_init_n; logic [NB_CORES-1:0][31:0] boot_addr; logic [NB_CORES-1:0] dbg_core_halt; logic [NB_CORES-1:0] dbg_core_resume; @@ -824,19 +824,20 @@ generate ); core_region #( - .CORE_TYPE_CL ( CORE_TYPE_CL ), - .CORE_ID ( i ), - .ADDR_WIDTH ( 32 ), - .DATA_WIDTH ( 32 ), - .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), - .CLUSTER_ALIAS_BASE ( CLUSTER_ALIAS_BASE ), - .REMAP_ADDRESS ( REMAP_ADDRESS ), - .APU_NARGS_CPU ( APU_NARGS_CPU ), //= 2, - .APU_WOP_CPU ( APU_WOP_CPU ), //= 1, - .WAPUTYPE ( WAPUTYPE ), //= 3, - .APU_NDSFLAGS_CPU ( APU_NDSFLAGS_CPU ), //= 3, - .APU_NUSFLAGS_CPU ( APU_NUSFLAGS_CPU ), //= 5, - .DEBUG_START_ADDR ( DEBUG_START_ADDR ), + .CORE_TYPE_CL ( CORE_TYPE_CL ), + .CORE_ID ( i ), + .ADDR_WIDTH ( 32 ), + .DATA_WIDTH ( 32 ), + .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), + .CLUSTER_ALIAS ( CLUSTER_ALIAS ), + .CLUSTER_ALIAS_BASE ( CLUSTER_ALIAS_BASE ), + .REMAP_ADDRESS ( REMAP_ADDRESS ), + .APU_NARGS_CPU ( APU_NARGS_CPU ), //= 2, + .APU_WOP_CPU ( APU_WOP_CPU ), //= 1, + .WAPUTYPE ( WAPUTYPE ), //= 3, + .APU_NDSFLAGS_CPU ( APU_NDSFLAGS_CPU ), //= 3, + .APU_NUSFLAGS_CPU ( APU_NUSFLAGS_CPU ), //= 5, + .DEBUG_START_ADDR ( DEBUG_START_ADDR ), .FPU ( CLUST_FPU ), .FP_DIVSQRT ( CLUST_FP_DIVSQRT ), .SHARED_FP ( CLUST_SHARED_FP ), @@ -846,7 +847,7 @@ generate .rst_ni ( rst_ni ), .base_addr_i ( base_addr_i ), - .init_ni ( s_init_n ), + .init_ni ( core_init_ni ), .cluster_id_i ( cluster_id_i ), .clock_en_i ( clk_core_en[i] ), .fetch_en_i ( fetch_en_int[i] ), @@ -1115,7 +1116,7 @@ icache_hier_top #( ); assign s_core_instr_bus.aw_atop = '0; - + /* TCDM banks */ tcdm_banks_wrap #( .BankSize (TCDM_NUM_ROWS), diff --git a/rtl/xbar_pe_wrap.sv b/rtl/xbar_pe_wrap.sv index 98887f60..6d09a02b 100644 --- a/rtl/xbar_pe_wrap.sv +++ b/rtl/xbar_pe_wrap.sv @@ -49,7 +49,7 @@ module xbar_pe_wrap logic cluster_alias; - assign cluster_alias = (CLUSTER_ALIAS) ? 1'b1 : 1'b0; + assign cluster_alias = (CLUSTER_ALIAS == 1) ? 1'b1 : 1'b0; localparam int unsigned PE_XBAR_N_INPS = NB_CORES + NB_MPERIPHS; localparam int unsigned PE_XBAR_N_OUPS = NB_SPERIPHS; diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 4bf6d2c3..d067fc40 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -296,6 +296,7 @@ module pulp_cluster_tb; .clk_i ( s_clk ), .rst_ni ( s_rstn ), .pwr_on_rst_ni ( s_rstn ), + .core_init_ni ( s_rstn ), .ref_clk_i ( s_clk ), .axi_isolate_i ( '0 ), .axi_isolated_o ( ), From 1cc996140cdb5b9d46e0f2e6364c45dd36675978 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 21 May 2023 00:31:39 +0200 Subject: [PATCH 029/207] Externalized core demultiplexers. --- Bender.yml | 3 +- rtl/core_demux_wrap.sv | 135 +++++++++++++ rtl/core_region.sv | 205 ++++---------------- rtl/{core_demux.sv => data_periph_demux.sv} | 5 +- rtl/pulp_cluster.sv | 68 +++++-- 5 files changed, 221 insertions(+), 195 deletions(-) create mode 100644 rtl/core_demux_wrap.sv rename rtl/{core_demux.sv => data_periph_demux.sv} (99%) diff --git a/Bender.yml b/Bender.yml index d73c8c35..3e377455 100644 --- a/Bender.yml +++ b/Bender.yml @@ -67,7 +67,8 @@ sources: # Level 1 - rtl/cluster_interconnect_wrap.sv - rtl/cluster_peripherals.sv - - rtl/core_demux.sv + - rtl/data_periph_demux.sv + - rtl/core_demux_wrap.sv # Level 2 - target: rtl defines: diff --git a/rtl/core_demux_wrap.sv b/rtl/core_demux_wrap.sv new file mode 100644 index 00000000..b11d3c00 --- /dev/null +++ b/rtl/core_demux_wrap.sv @@ -0,0 +1,135 @@ +module core_demux_wrap #( + parameter int unsigned AddrWidth = 32 , + parameter int unsigned DataWidth = 32 , + parameter int unsigned RemapAddress = 1 , + parameter int unsigned ClustAlias = 1 , + parameter int unsigned ClustAliasBase = 12'h000 , + parameter int unsigned NumExtPerf = 5 , + localparam int unsigned ByteEnable = DataWidth/8 +)( + input logic clk_i , + input logic rst_ni , + input logic test_en_i , + input logic clk_en_i , + input logic [3:0] base_addr_i , + input logic [5:0] cluster_id_i , + output logic [NumExtPerf-1:0] ext_perf_o , + hci_core_intf.slave core_bus_slv_i , + hci_core_intf.master tcdm_bus_mst_o , + hci_core_intf.master dma_ctrl_mst_o , + XBAR_PERIPH_BUS.Master eventunit_bus_mst_o , + XBAR_PERIPH_BUS.Master peripheral_bus_mst_o +); + +localparam N_EXT_PERF_COUNTERS_ACTUAL = 5; // Temporary + +logic clk_int; +logic [N_EXT_PERF_COUNTERS_ACTUAL-1:0] perf_counters; + +XBAR_PERIPH_BUS periph_demux_bus(); + +assign core_bus_slv_i.r_user = '0; + +assign tcdm_bus_mst_o.boffs = '0; +assign tcdm_bus_mst_o.lrdy = '1; + +data_periph_demux #( + .ADDR_WIDTH ( AddrWidth ), + .DATA_WIDTH ( DataWidth ), + .BYTE_ENABLE_BIT ( ByteEnable ), + .REMAP_ADDRESS ( RemapAddress ), + .CLUSTER_ALIAS ( ClustAlias ), + .CLUSTER_ALIAS_BASE ( ClustAliasBase ) +) data_periph_demux_i ( + .clk ( clk_i ), + .rst_ni ( rst_ni ), + .test_en_i ( test_en_i ), + .base_addr_i ( base_addr_i ), + .data_req_i ( core_bus_slv_i.req ), + .data_add_i ( core_bus_slv_i.add ), + .data_wen_i ( core_bus_slv_i.wen ), //inverted when using OR10N + .data_wdata_i ( core_bus_slv_i.data ), + .data_be_i ( core_bus_slv_i.be ), + .data_gnt_o ( core_bus_slv_i.gnt ), + .data_r_valid_o ( core_bus_slv_i.r_valid ), + .data_r_opc_o ( core_bus_slv_i.r_opc ), + .data_r_rdata_o ( core_bus_slv_i.r_data ), + + .data_req_o_SH ( tcdm_bus_mst_o.req ), + .data_add_o_SH ( tcdm_bus_mst_o.add ), + .data_wen_o_SH ( tcdm_bus_mst_o.wen ), + .data_wdata_o_SH ( tcdm_bus_mst_o.data ), + .data_be_o_SH ( tcdm_bus_mst_o.be ), + .data_gnt_i_SH ( tcdm_bus_mst_o.gnt ), + .data_r_valid_i_SH ( tcdm_bus_mst_o.r_valid ), + .data_r_rdata_i_SH ( tcdm_bus_mst_o.r_data ), + + .data_req_o_EXT ( periph_demux_bus.req ), + .data_add_o_EXT ( periph_demux_bus.add ), + .data_wen_o_EXT ( periph_demux_bus.wen ), + .data_wdata_o_EXT ( periph_demux_bus.wdata ), + .data_be_o_EXT ( periph_demux_bus.be ), + .data_gnt_i_EXT ( periph_demux_bus.gnt ), + .data_r_valid_i_EXT ( periph_demux_bus.r_valid ), + .data_r_rdata_i_EXT ( periph_demux_bus.r_rdata ), + .data_r_opc_i_EXT ( periph_demux_bus.r_opc ), + + .data_req_o_PE ( peripheral_bus_mst_o.req ), + .data_add_o_PE ( peripheral_bus_mst_o.add ), + .data_wen_o_PE ( peripheral_bus_mst_o.wen ), + .data_wdata_o_PE ( peripheral_bus_mst_o.wdata ), + .data_be_o_PE ( peripheral_bus_mst_o.be ), + .data_gnt_i_PE ( peripheral_bus_mst_o.gnt ), + .data_r_valid_i_PE ( peripheral_bus_mst_o.r_valid ), + .data_r_rdata_i_PE ( peripheral_bus_mst_o.r_rdata ), + .data_r_opc_i_PE ( peripheral_bus_mst_o.r_opc ), + + .perf_l2_ld_o ( ext_perf_o [0] ), + .perf_l2_st_o ( ext_perf_o [1] ), + .perf_l2_ld_cyc_o ( ext_perf_o [2] ), + .perf_l2_st_cyc_o ( ext_perf_o [3] ), + .CLUSTER_ID ( cluster_id_i ) +); + +assign periph_demux_bus.id = '0; + +assign dma_ctrl_mst_o.boffs = '0; +assign dma_ctrl_mst_o.lrdy = '1; + +periph_demux +periph_demux_i ( + .clk ( clk_i ), + .rst_ni ( rst_ni ), + + .data_req_i ( periph_demux_bus.req ), + .data_add_i ( periph_demux_bus.add ), + .data_wen_i ( periph_demux_bus.wen ), + .data_wdata_i ( periph_demux_bus.wdata ), + .data_be_i ( periph_demux_bus.be ), + .data_gnt_o ( periph_demux_bus.gnt ), + .data_r_valid_o ( periph_demux_bus.r_valid ), + .data_r_opc_o ( periph_demux_bus.r_opc ), + .data_r_rdata_o ( periph_demux_bus.r_rdata ), + + .data_req_o_MH ( dma_ctrl_mst_o.req ), + .data_add_o_MH ( dma_ctrl_mst_o.add ), + .data_wen_o_MH ( dma_ctrl_mst_o.wen ), + .data_wdata_o_MH ( dma_ctrl_mst_o.data ), + .data_be_o_MH ( dma_ctrl_mst_o.be ), + .data_gnt_i_MH ( dma_ctrl_mst_o.gnt ), + .data_r_valid_i_MH ( dma_ctrl_mst_o.r_valid ), + .data_r_rdata_i_MH ( dma_ctrl_mst_o.r_data ), + .data_r_opc_i_MH ( dma_ctrl_mst_o.r_opc ), + + .data_req_o_EU ( eventunit_bus_mst_o.req ), + .data_add_o_EU ( eventunit_bus_mst_o.add ), + .data_wen_o_EU ( eventunit_bus_mst_o.wen ), + .data_wdata_o_EU ( eventunit_bus_mst_o.wdata ), + .data_be_o_EU ( eventunit_bus_mst_o.be ), + .data_gnt_i_EU ( eventunit_bus_mst_o.gnt ), + .data_r_valid_i_EU ( eventunit_bus_mst_o.r_valid ), + .data_r_rdata_i_EU ( eventunit_bus_mst_o.r_rdata ), + .data_r_opc_i_EU ( eventunit_bus_mst_o.r_opc ) +); + +endmodule: core_demux_wrap diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 1d0c3714..0660711f 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -60,8 +60,6 @@ module core_region input logic rst_ni, input logic init_ni, - input logic [3:0] base_addr_i, // FOR CLUSTER VIRTUALIZATION - input logic [5:0] cluster_id_i, input logic irq_req_i, @@ -71,7 +69,6 @@ module core_region input logic clock_en_i, input logic fetch_en_i, - input logic fregfile_disable_i, input logic [31:0] boot_addr_i, @@ -90,14 +87,10 @@ module core_region output logic debug_havereset_o, output logic debug_running_o, output logic debug_halted_o, - // input logic debug_core_resume_i, // Useful for HMR, consider keeping - - // Interface for DEMUX to TCDM INTERCONNECT ,PERIPHERAL INTERCONNECT and DMA CONTROLLER - hci_core_intf.master tcdm_data_master, - // XBAR_TCDM_BUS.Master dma_ctrl_master, // FIXME: iDMA - hci_core_intf.master dma_ctrl_master, - XBAR_PERIPH_BUS.Master eu_ctrl_master, - XBAR_PERIPH_BUS.Master periph_data_master, + + input logic [N_EXT_PERF_COUNTERS-1:0] ext_perf_i, + + hci_core_intf.master core_bus_mst_o, output logic apu_master_req_o, input logic apu_master_gnt_i, @@ -129,12 +122,6 @@ module core_region //******************************************************** //***************** SIGNALS DECLARATION ****************** //******************************************************** - - XBAR_DEMUX_BUS s_core_bus(); // Internal interface between CORE <--> DEMUX - XBAR_PERIPH_BUS periph_demux_bus(); // Internal interface between CORE_DEMUX <--> PERIPHERAL DEMUX - - logic [N_EXT_PERF_COUNTERS_ACTUAL-1:0] perf_counters; - logic clk_int; logic [31:0] hart_id; logic core_sleep; logic [31:0] boot_addr; @@ -155,15 +142,11 @@ module core_region logic [31:0] core_shadow_addr ; logic [31:0] core_shadow_wdata; logic [5:0] core_data_atop ; + logic core_bus_must_we; - // clock gate of the core_region less the core itself - cluster_clock_gating clock_gate_i ( - .clk_i ( clk_i ), - .en_i ( clock_en_i ), - .test_en_i ( test_mode_i ), - .clk_o ( clk_int ) - ); - + assign core_bus_mst_o.wen = ~core_bus_must_we; + assign core_bus_mst_o.lrdy = '1; + assign core_bus_mst_o.user = '0; assign hart_id = {21'b0, cluster_id_i[5:0], 1'b0, CORE_ID[3:0]}; //******************************************************** @@ -178,7 +161,7 @@ module core_region .PULP_XPULP ( 1 ), // For now this is a no .PULP_CLUSTER ( 1 ), .FPU ( FPU ), - .NUM_EXTERNAL_PERF ( N_EXT_PERF_COUNTERS_ACTUAL ), + .NUM_EXTERNAL_PERF ( N_EXT_PERF_COUNTERS ), // .N_EXT_PERF_COUNTERS ( N_EXT_PERF_COUNTERS_ACTUAL ), .NUM_INTERRUPTS ( NUM_INTERRUPTS ), // .PULP_OBI_INTF ( 1 ), @@ -188,7 +171,7 @@ module core_region // .WAPUTYPE ( WAPUTYPE ), // .DM_HaltAddress ( DEBUG_START_ADDR + 16'h0800 ) ) RISCV_CORE ( - .clk_i ( clk_int ), + .clk_i ( clk_i ), .rst_ni ( rst_ni ), // .clock_en_i ( clock_en_i ), // .test_en_i ( test_mode_i ), @@ -212,14 +195,14 @@ module core_region .instr_addr_o ( instr_addr_o ), .instr_rdata_i ( instr_r_rdata_i ), // Data Interface - .data_req_o ( s_core_bus.req ), - .data_gnt_i ( s_core_bus.gnt ), - .data_rvalid_i ( s_core_bus.r_valid ), - .data_we_o ( s_core_bus.we ), - .data_be_o ( s_core_bus.be ), - .data_addr_o ( s_core_bus.add ), - .data_wdata_o ( s_core_bus.wdata ), - .data_rdata_i ( s_core_bus.r_rdata ), + .data_req_o ( core_bus_mst_o.req ), + .data_gnt_i ( core_bus_mst_o.gnt ), + .data_rvalid_i ( core_bus_mst_o.r_valid ), + .data_we_o ( core_bus_must_we ), + .data_be_o ( core_bus_mst_o.be ), + .data_addr_o ( core_bus_mst_o.add ), + .data_wdata_o ( core_bus_mst_o.data ), + .data_rdata_i ( core_bus_mst_o.r_data ), // Shadow Memory Interface .shadow_req_o ( sadow_req ), .shadow_gnt_i ( '0 ), @@ -275,7 +258,7 @@ module core_region .core_sleep_o ( core_sleep ), // External performance monitoring signals // .ext_perf_counters_i ( perf_counters ) - .external_perf_i ( perf_counters ) + .external_perf_i ( ext_perf_i ) ); assign core_busy_o = ~core_sleep; end else begin: CL_CORE @@ -319,9 +302,9 @@ module core_region .clk_i (clk_i ), .rst_ni (rst_ni ), .core_req_i (core_mem_req ), - .mem_req_o (s_core_bus.req ), - .mem_gnt_i (s_core_bus.gnt ), - .mem_rvalid_i(s_core_bus.r_valid) + .mem_req_o (core_bus_mst_o.req ), + .mem_gnt_i (core_bus_mst_o.gnt ), + .mem_rvalid_i(core_bus_mst_o.r_valid) ); `ifdef VERILATOR @@ -369,13 +352,13 @@ module core_region // Data memory interface: .data_req_o ( core_mem_req ), - .data_gnt_i ( s_core_bus.gnt ), - .data_rvalid_i ( s_core_bus.r_valid ), - .data_we_o ( s_core_bus.we ), - .data_be_o ( s_core_bus.be ), - .data_addr_o ( s_core_bus.add ), - .data_wdata_o ( s_core_bus.wdata ), - .data_rdata_i ( s_core_bus.r_rdata ), + .data_gnt_i ( core_bus_mst_o.gnt ), + .data_rvalid_i ( core_bus_mst_o.r_valid ), + .data_we_o ( ~core_bus_mst_o.we ), + .data_be_o ( core_bus_mst_o.be ), + .data_addr_o ( core_bus_mst_o.add ), + .data_wdata_o ( core_bus_mst_o.wdata ), + .data_rdata_i ( core_bus_mst_o.r_rdata ), .data_err_i ( 1'b0 ), .irq_software_i ( 1'b0 ), @@ -408,128 +391,6 @@ module core_region end end - //assign debug_bus.r_opc = 1'b0; - - // Bind to 0 Unused Signals in CORE interface - assign s_core_bus.r_gnt = 1'b0; - assign s_core_bus.barrier = 1'b0; - assign s_core_bus.exec_cancel = 1'b0; - assign s_core_bus.exec_stall = 1'b0; - - // Performance Counters - assign perf_counters[4] = tcdm_data_master.req & (~tcdm_data_master.gnt); // Cycles lost due to contention - - - //******************************************************** - //****** DEMUX TO TCDM AND PERIPHERAL INTERCONNECT ******* - //******************************************************** - - // demuxes to TCDM & memory hierarchy - core_demux #( - .ADDR_WIDTH ( 32 ), - .DATA_WIDTH ( 32 ), - .BYTE_ENABLE_BIT ( DATA_WIDTH/8 ), - .REMAP_ADDRESS ( REMAP_ADDRESS ), - .CLUSTER_ALIAS ( CLUSTER_ALIAS ), - .CLUSTER_ALIAS_BASE ( CLUSTER_ALIAS_BASE ) - ) core_demux_i ( - .clk ( clk_int ), - .rst_ni ( rst_ni ), - .test_en_i ( test_mode_i ), - .base_addr_i ( base_addr_i ), - .data_req_i ( s_core_bus.req ), - .data_add_i ( s_core_bus.add ), - .data_wen_i ( ~s_core_bus.we ), //inverted when using OR10N - .data_wdata_i ( s_core_bus.wdata ), - .data_be_i ( s_core_bus.be ), - .data_gnt_o ( s_core_bus.gnt ), - .data_r_gnt_i ( s_core_bus.r_gnt ), - .data_r_valid_o ( s_core_bus.r_valid ), - .data_r_opc_o ( ), - .data_r_rdata_o ( s_core_bus.r_rdata ), - - .data_req_o_SH ( tcdm_data_master.req ), - .data_add_o_SH ( tcdm_data_master.add ), - .data_wen_o_SH ( tcdm_data_master.wen ), - .data_wdata_o_SH ( tcdm_data_master.data ), - .data_be_o_SH ( tcdm_data_master.be ), - .data_gnt_i_SH ( tcdm_data_master.gnt ), - .data_r_valid_i_SH ( tcdm_data_master.r_valid ), - .data_r_rdata_i_SH ( tcdm_data_master.r_data ), - - .data_req_o_EXT ( periph_demux_bus.req ), - .data_add_o_EXT ( periph_demux_bus.add ), - .data_wen_o_EXT ( periph_demux_bus.wen ), - .data_wdata_o_EXT ( periph_demux_bus.wdata ), - .data_be_o_EXT ( periph_demux_bus.be ), - .data_gnt_i_EXT ( periph_demux_bus.gnt ), - .data_r_valid_i_EXT ( periph_demux_bus.r_valid ), - .data_r_rdata_i_EXT ( periph_demux_bus.r_rdata ), - .data_r_opc_i_EXT ( periph_demux_bus.r_opc ), - - .data_req_o_PE ( periph_data_master.req ), - .data_add_o_PE ( periph_data_master.add ), - .data_wen_o_PE ( periph_data_master.wen ), - .data_wdata_o_PE ( periph_data_master.wdata ), - .data_be_o_PE ( periph_data_master.be ), - .data_gnt_i_PE ( periph_data_master.gnt ), - .data_r_valid_i_PE ( periph_data_master.r_valid ), - .data_r_rdata_i_PE ( periph_data_master.r_rdata ), - .data_r_opc_i_PE ( periph_data_master.r_opc ), - - .perf_l2_ld_o ( perf_counters[0] ), - .perf_l2_st_o ( perf_counters[1] ), - .perf_l2_ld_cyc_o ( perf_counters[2] ), - .perf_l2_st_cyc_o ( perf_counters[3] ), - .CLUSTER_ID ( cluster_id_i ) - ); - - assign tcdm_data_master.boffs = '0; - assign tcdm_data_master.lrdy = '1; - - assign periph_demux_bus.id = '0; - - periph_demux periph_demux_i ( - .clk ( clk_int ), - .rst_ni ( rst_ni ), - - .data_req_i ( periph_demux_bus.req ), - .data_add_i ( periph_demux_bus.add ), - .data_wen_i ( periph_demux_bus.wen ), - .data_wdata_i ( periph_demux_bus.wdata ), - .data_be_i ( periph_demux_bus.be ), - .data_gnt_o ( periph_demux_bus.gnt ), - - .data_r_valid_o ( periph_demux_bus.r_valid ), - .data_r_opc_o ( periph_demux_bus.r_opc ), - .data_r_rdata_o ( periph_demux_bus.r_rdata ), - - .data_req_o_MH ( dma_ctrl_master.req ), - .data_add_o_MH ( dma_ctrl_master.add ), - .data_wen_o_MH ( dma_ctrl_master.wen ), - .data_wdata_o_MH ( dma_ctrl_master.data ), - .data_be_o_MH ( dma_ctrl_master.be ), - .data_gnt_i_MH ( dma_ctrl_master.gnt ), - - .data_r_valid_i_MH ( dma_ctrl_master.r_valid ), - .data_r_rdata_i_MH ( dma_ctrl_master.r_data ), - .data_r_opc_i_MH ( dma_ctrl_master.r_opc ), - - .data_req_o_EU ( eu_ctrl_master.req ), - .data_add_o_EU ( eu_ctrl_master.add ), - .data_wen_o_EU ( eu_ctrl_master.wen ), - .data_wdata_o_EU ( eu_ctrl_master.wdata ), - .data_be_o_EU ( eu_ctrl_master.be ), - .data_gnt_i_EU ( eu_ctrl_master.gnt ), - - .data_r_valid_i_EU ( eu_ctrl_master.r_valid ), - .data_r_rdata_i_EU ( eu_ctrl_master.r_rdata ), - .data_r_opc_i_EU ( eu_ctrl_master.r_opc ) - ); - - assign dma_ctrl_master.boffs = '0; - assign dma_ctrl_master.lrdy = '1; - /* debug stuff */ //synopsys translate_off @@ -537,12 +398,12 @@ module core_region always @(posedge clk_i) begin : CHECK_ASSERTIONS `ifndef CLUSTER_ALIAS - if ((s_core_bus.req == 1'b1) && (s_core_bus.add < 32'h1000_0000)) begin - $error("ERROR_1 (0x00000000 -> 0x10000000) : Data interface is making a request on unmapped region --> %8x\t at time %t [ns]" ,s_core_bus.add, $time()/1000 ); + if ((core_bus_mst_o.req == 1'b1) && (core_bus_mst_o.add < 32'h1000_0000)) begin + $error("ERROR_1 (0x00000000 -> 0x10000000) : Data interface is making a request on unmapped region --> %8x\t at time %t [ns]" ,core_bus_mst_o.add, $time()/1000 ); $finish(); end - if ((s_core_bus.req == 1'b1) && (s_core_bus.add >= 32'h1040_0000) && ((s_core_bus.add < 32'h1A00_0000))) begin - $error("ERROR_2 (0x10400000 -> 0x1A000000) : Data interface is making a request on unmapped region --> %8x\t at time %t [ns]" ,s_core_bus.add, $time()/1000 ); + if ((core_bus_mst_o.req == 1'b1) && (core_bus_mst_o.add >= 32'h1040_0000) && ((core_bus_mst_o.add < 32'h1A00_0000))) begin + $error("ERROR_2 (0x10400000 -> 0x1A000000) : Data interface is making a request on unmapped region --> %8x\t at time %t [ns]" ,core_bus_mst_o.add, $time()/1000 ); $finish(); end `endif diff --git a/rtl/core_demux.sv b/rtl/data_periph_demux.sv similarity index 99% rename from rtl/core_demux.sv rename to rtl/data_periph_demux.sv index a7c347b3..61dc2eb8 100644 --- a/rtl/core_demux.sv +++ b/rtl/data_periph_demux.sv @@ -15,7 +15,7 @@ */ -module core_demux +module data_periph_demux #( parameter ADDR_WIDTH = 32, parameter DATA_WIDTH = 32, @@ -38,7 +38,6 @@ module core_demux input logic [BYTE_ENABLE_BIT - 1:0] data_be_i, output logic data_gnt_o, - input logic data_r_gnt_i, // Data Response Grant (For LOAD/STORE commands) output logic data_r_valid_o, // Data Response Valid (For LOAD/STORE commands) output logic [DATA_WIDTH - 1:0] data_r_rdata_o, // Data Response DATA (For LOAD commands) output logic data_r_opc_o, // Data Response Error @@ -635,4 +634,4 @@ logic clear_regs, enable_regs; end `endif -endmodule +endmodule: data_periph_demux diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 91cd7b80..cfe062c1 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -813,6 +813,17 @@ cluster_peripherals #( //------------------------------------------------------// /* cluster cores + core-coupled accelerators / shared execution units */ +logic [NB_CORES-1:0] clk_core; +logic [NB_CORES-1:0][4:0] ext_perf; + +hci_core_intf #( + .DW ( DATA_WIDTH ), + .AW ( ADDR_WIDTH ), + .OW ( 1 ) +) core_bus_mst [NB_CORES-1:0] ( + .clk ( clk_i ) +); + generate for (genvar i=0; i Date: Sun, 21 May 2023 23:32:51 +0200 Subject: [PATCH 030/207] Added RI5CY selectable via parameter. --- Bender.lock | 8 ++++ Bender.yml | 1 + rtl/core_region.sv | 109 ++++++++++++++++++++++++++++++-------------- rtl/pulp_cluster.sv | 2 +- 4 files changed, 85 insertions(+), 35 deletions(-) diff --git a/Bender.lock b/Bender.lock index 6e0f5d44..63256d97 100644 --- a/Bender.lock +++ b/Bender.lock @@ -209,6 +209,14 @@ packages: - axi - common_cells - common_verification + riscv: + revision: 779b107a5968a2a7cb37bd8270b44c10a4187b6e + version: null + source: + Git: git@github.com:AlSaqr-platform/riscv_nn.git + dependencies: + - fpnew + - tech_cells_generic scm: revision: f7b51416f3c407e4c31e9c016616d57aae2687bd version: null diff --git a/Bender.yml b/Bender.yml index 3e377455..9ff8f414 100644 --- a/Bender.yml +++ b/Bender.yml @@ -27,6 +27,7 @@ dependencies: timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } + riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 779b107a5968a2a7cb37bd8270b44c10a4187b6e } # branch: yt/hmr cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "9b77611" } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 0660711f..e64d8413 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -26,7 +26,7 @@ module core_region #( // CORE PARAMETERS - parameter CORE_TYPE_CL = 0, // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) + parameter CORE_TYPE_CL = 0, // 0 for CV32, 1 RI5CY, 2 for IBEX RV32IMC // parameter USE_FPU = 1, // parameter USE_HWPE = 1, parameter N_EXT_PERF_COUNTERS = 1, @@ -154,35 +154,23 @@ module core_region //******************************************************** generate - if ( CORE_TYPE_CL == 0 ) begin: CL_CORE + if ( CORE_TYPE_CL == 0 ) begin: CV32_CORE assign boot_addr = boot_addr_i; cv32e40p_wrapper #( - // .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), .PULP_XPULP ( 1 ), // For now this is a no .PULP_CLUSTER ( 1 ), .FPU ( FPU ), .NUM_EXTERNAL_PERF ( N_EXT_PERF_COUNTERS ), - // .N_EXT_PERF_COUNTERS ( N_EXT_PERF_COUNTERS_ACTUAL ), - .NUM_INTERRUPTS ( NUM_INTERRUPTS ), - // .PULP_OBI_INTF ( 1 ), - // .TRANS_STABLE ( 0 ), - .PULP_ZFINX ( 0 ) - // .Zfinx ( 0 ), - // .WAPUTYPE ( WAPUTYPE ), - // .DM_HaltAddress ( DEBUG_START_ADDR + 16'h0800 ) - ) RISCV_CORE ( + .NUM_INTERRUPTS ( NUM_INTERRUPTS ), + .PULP_ZFINX ( 0 ) + ) CV32_CORE ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - // .clock_en_i ( clock_en_i ), - // .test_en_i ( test_mode_i ), .setback_i ( '0 ), // Control Interface .pulp_clock_en_i ( clock_en_i ), - // .fregfile_disable_i ( '1 ), .scan_cg_en_i ( test_mode_i ), .boot_addr_i ( boot_addr ), - // .core_id_i ( hart_id[3:0] ), - // .cluster_id_i ( cluster_id_i ), .mtvec_addr_i ( '0 ), .mtvt_addr_i ( '0 ), .dm_halt_addr_i ( DEBUG_START_ADDR + 16'h0800 ), @@ -216,37 +204,23 @@ module core_region .data_atop_o ( core_data_atop ), // apu-interconnect // Handshake - // .apu_master_req_o ( apu_master_req_o ), - // .apu_master_ready_o ( apu_master_ready_o ), - // .apu_master_gnt_i ( apu_master_gnt_i ), .apu_req_o ( apu_master_req_o ), .apu_gnt_i ( apu_master_gnt_i ), // Request Bus - // .apu_master_operands_o ( apu_master_operands_o ), - // .apu_master_op_o ( apu_master_op_o ), - // .apu_master_type_o ( apu_master_type_o ), - // .apu_master_flags_o ( apu_master_flags_o ), .apu_operands_o ( apu_master_operands_o ), .apu_op_o ( apu_master_op_o ), .apu_type_o ( apu_master_type_o ), .apu_flags_o ( apu_master_flags_o ), // Response Bus - // .apu_master_valid_i ( apu_master_valid_i ), - // .apu_master_result_i ( apu_master_result_i ), - // .apu_master_flags_i ( apu_master_flags_i ), .apu_rvalid_i ( apu_master_valid_i ), .apu_result_i ( apu_master_result_i ), .apu_flags_i ( apu_master_flags_i ), // IRQ Interface - // .irq_i ( irq_req_i ), .irq_i ( core_irq_x ), - // .irq_id_i ( irq_id_i ), .irq_level_i ( '0 ), // CLIC interrupt level .irq_shv_i ( '0 ), // CLIC selective hardware vectoring .irq_ack_o ( irq_ack_o ), .irq_id_o ( irq_ack_id_o ), - // .irq_sec_i ( '0 ), - // .sec_lvl_o ( ), // Debug Interface .debug_req_i ( debug_req_i ), .debug_havereset_o ( debug_havereset_o ), @@ -254,14 +228,81 @@ module core_region .debug_halted_o ( debug_halted_o ), // Yet other control signals .fetch_enable_i ( fetch_en_i ), - // .core_busy_o ( core_busy_o ), .core_sleep_o ( core_sleep ), // External performance monitoring signals - // .ext_perf_counters_i ( perf_counters ) .external_perf_i ( ext_perf_i ) ); assign core_busy_o = ~core_sleep; - end else begin: CL_CORE + end else if ( CORE_TYPE_CL == 1 ) begin: RI5CY_CORE + assign boot_addr = boot_addr_i; + riscv_core #( + .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), + .PULP_CLUSTER ( 1 ), + .FPU ( FPU ), + .N_EXT_PERF_COUNTERS ( N_EXT_PERF_COUNTERS_ACTUAL ), + .Zfinx ( 0 ), + .WAPUTYPE ( WAPUTYPE ), + .DM_HaltAddress ( DEBUG_START_ADDR + 16'h0800 ) + ) RI5CY_CORE ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clock_en_i ( clock_en_i ), + .test_en_i ( test_mode_i ), + // .setback_i ( '0 ), // Useful for HMR + // Control Interface + .fregfile_disable_i ( '1 ), + .boot_addr_i ( boot_addr ), + .core_id_i ( hart_id[3:0] ), + .cluster_id_i ( cluster_id_i ), + // Instruction Interface + .instr_req_o ( instr_req_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_r_valid_i ), + .instr_addr_o ( instr_addr_o ), + .instr_rdata_i ( instr_r_rdata_i ), + // Data Interface + .data_req_o ( core_bus_mst_o.req ), + .data_gnt_i ( core_bus_mst_o.gnt ), + .data_rvalid_i ( core_bus_mst_o.r_valid ), + .data_we_o ( core_bus_must_we ), + .data_be_o ( core_bus_mst_o.be ), + .data_addr_o ( core_bus_mst_o.add ), + .data_wdata_o ( core_bus_mst_o.data ), + .data_rdata_i ( core_bus_mst_o.r_data ), + .data_unaligned_o ( /* Unused */ ), + // apu-interconnect + // Handshake + .apu_master_req_o ( apu_master_req_o ), + .apu_master_ready_o ( apu_master_ready_o ), + .apu_master_gnt_i ( apu_master_gnt_i ), + // Request Bus + .apu_master_operands_o ( apu_master_operands_o ), + .apu_master_op_o ( apu_master_op_o ), + .apu_master_type_o ( apu_master_type_o ), + .apu_master_flags_o ( apu_master_flags_o ), + // Response Bus + .apu_master_valid_i ( apu_master_valid_i ), + .apu_master_result_i ( apu_master_result_i ), + .apu_master_flags_i ( apu_master_flags_i ), + // IRQ Interface + .irq_i ( irq_req_i ), + .irq_id_i ( irq_id_i ), + .irq_ack_o ( irq_ack_o ), + .irq_id_o ( irq_ack_id_o ), + .irq_sec_i ( '0 ), + .sec_lvl_o ( ), + // Debug Interface + .debug_req_i ( debug_req_i ), + // .debug_havereset_o ( debug_havereset_o ), // Useful for HMR + // .debug_running_o ( debug_running_o ), // Useful for HMR + // .debug_halted_o ( debug_halted_o ), // Useful for HMR + // Yet other control signals + .fetch_enable_i ( fetch_en_i ), + .core_busy_o ( core_busy_o ), + // External performance monitoring signals + .ext_perf_counters_i ( ext_perf_i ) + ); + end else begin: IBEX_CORE assign boot_addr = boot_addr_i & 32'hFFFFFF00; // RI5CY expects 0x80 offset, Ibex expects 0x00 offset (adds reset offset 0x80 internally) // Core busy assign core_busy_o = ~core_sleep; diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index cfe062c1..9f753256 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -27,7 +27,7 @@ module pulp_cluster import hci_package::*; #( // cluster parameters - parameter CORE_TYPE_CL = 0, // 0 for RISCY, 1 for IBEX RV32IMC (formerly ZERORISCY), 2 for IBEX RV32EC (formerly MICRORISCY) + parameter CORE_TYPE_CL = 1, // 0 for CV32, 1 for RI5CY, 2 for IBEX RV32IMC parameter NB_CORES = 8, parameter NB_HWPE_PORTS = 9, // number of DMA TCDM plugs, NOT number of DMA slave peripherals! From 4c5e6759d767d80d04562e2a76d72ed9bcd2b79a Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 31 May 2023 11:44:51 +0200 Subject: [PATCH 031/207] HMR integration. --- Bender.lock | 12 +- Bender.yml | 3 +- packages/pulp_cluster_package.sv | 49 +++++++- rtl/cluster_peripherals.sv | 21 +++- rtl/core_demux_wrap.sv | 47 ++++---- rtl/core_region.sv | 134 +++++++++++----------- rtl/pulp_cluster.sv | 191 +++++++++++++++++++++++++------ tb/pulp_cluster_tb.sv | 1 - 8 files changed, 322 insertions(+), 136 deletions(-) diff --git a/Bender.lock b/Bender.lock index 63256d97..9d98e8db 100644 --- a/Bender.lock +++ b/Bender.lock @@ -199,6 +199,16 @@ packages: Git: https://github.com/pulp-platform/per2axi.git dependencies: - axi_slice + redundancy_cells: + revision: 6e10650b50c7b40f7f81602acf61526330c4d69d + version: null + source: + Git: https://github.com/pulp-platform/redundancy_cells.git + dependencies: + - common_cells + - common_verification + - register_interface + - tech_cells_generic register_interface: revision: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 version: null @@ -210,7 +220,7 @@ packages: - common_cells - common_verification riscv: - revision: 779b107a5968a2a7cb37bd8270b44c10a4187b6e + revision: dbcf0bbf827e1ec323ca223883c92ebfe9347c67 version: null source: Git: git@github.com:AlSaqr-platform/riscv_nn.git diff --git a/Bender.yml b/Bender.yml index 9ff8f414..c93d5002 100644 --- a/Bender.yml +++ b/Bender.yml @@ -27,7 +27,7 @@ dependencies: timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 779b107a5968a2a7cb37bd8270b44c10a4187b6e } # branch: yt/hmr + riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: dbcf0bbf827e1ec323ca223883c92ebfe9347c67 } # branch: yt/hmr cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "9b77611" } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating @@ -35,6 +35,7 @@ dependencies: hci: { git: "https://github.com/pulp-platform/hci.git", version: 1.0.8 } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 6e10650b50c7b40f7f81602acf61526330c4d69d} # branch: yt/hmr export_include_dirs: - include diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 1fcd4be6..88484ccc 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -31,7 +31,7 @@ package pulp_cluster_package; parameter SPER_ICACHE_CTRL = 5; parameter SPER_DMA_CL_ID = 6; parameter SPER_DMA_FC_ID = 7; - parameter SPER_DECOMP_ID = 8; // Currently unused / grounded, available for specific designs + parameter SPER_HMR_UNIT_ID = 8; parameter SPER_EXT_ID = 9; parameter SPER_ERROR_ID = 10; @@ -48,4 +48,51 @@ package pulp_cluster_package; // // remember to change the defines in the pulp.h as well to be coherent with this approach // parameter DEM_PER_BEFORE_TCDM_TS = 0; + typedef struct packed { + logic gnt; + logic [31:0] r_data; + logic r_valid; + } core_data_rsp_t; + + typedef struct packed { + logic req; + logic [31:0] add; + logic wen; + logic [31:0] data; + logic [3:0] be; + } core_data_req_t; + + typedef struct packed { + logic clock_en; + logic [31:0] boot_addr; + logic [3:0] core_id; + logic [5:0] cluster_id; + logic instr_gnt; + logic instr_rvalid; + logic [31:0] instr_rdata; + logic data_gnt; + logic data_rvalid; + logic [31:0] data_rdata; + logic irq_req; + logic [4:0] irq_id; + logic debug_req; + // logic debug_resume; + } core_inputs_t; + + typedef struct packed { + logic instr_req; + logic [31:0] instr_addr; + logic data_req; + logic data_we; + logic [3:0] data_be; + logic [31:0] data_add; + logic [31:0] data_wdata; + logic irq_ack; + logic [4:0] irq_ack_id; + // logic debug_havereset; + // logic debug_running; + // logic debug_halted; + logic core_busy; + } core_outputs_t; + endpackage diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index af459850..ec64825a 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -89,6 +89,7 @@ module cluster_peripherals output logic [1:0] TCDM_arb_policy_o, XBAR_PERIPH_BUS.Master hwpe_cfg_master, + XBAR_PERIPH_BUS.Master hmr_cfg_master, input logic [NB_CORES-1:0][3:0] hwpe_events_i, output logic hwpe_en_o, output hci_package::hci_interconnect_ctrl_t hci_ctrl_o, @@ -331,12 +332,22 @@ module cluster_peripherals assign hwpe_cfg_master.be = speriph_slave[SPER_HWPE_ID].be; assign hwpe_cfg_master.id = speriph_slave[SPER_HWPE_ID].id; - assign speriph_slave[SPER_DECOMP_ID].gnt = '0; - assign speriph_slave[SPER_DECOMP_ID].r_rdata = '0; - assign speriph_slave[SPER_DECOMP_ID].r_opc = '0; - assign speriph_slave[SPER_DECOMP_ID].r_id = '0; - assign speriph_slave[SPER_DECOMP_ID].r_valid = '0; + //******************************************************** + //******************** HMR UNIT ************************** + //******************************************************** + assign speriph_slave[SPER_HMR_UNIT_ID].gnt = hmr_cfg_master.gnt; + assign speriph_slave[SPER_HMR_UNIT_ID].r_rdata = hmr_cfg_master.r_rdata; + assign speriph_slave[SPER_HMR_UNIT_ID].r_opc = hmr_cfg_master.r_opc; + assign speriph_slave[SPER_HMR_UNIT_ID].r_id = hmr_cfg_master.r_id; + assign speriph_slave[SPER_HMR_UNIT_ID].r_valid = hmr_cfg_master.r_valid; + + assign hmr_cfg_master.req = speriph_slave[SPER_HMR_UNIT_ID].req; + assign hmr_cfg_master.add = speriph_slave[SPER_HMR_UNIT_ID].add; + assign hmr_cfg_master.wen = speriph_slave[SPER_HMR_UNIT_ID].wen; + assign hmr_cfg_master.wdata = speriph_slave[SPER_HMR_UNIT_ID].wdata; + assign hmr_cfg_master.be = speriph_slave[SPER_HMR_UNIT_ID].be; + assign hmr_cfg_master.id = speriph_slave[SPER_HMR_UNIT_ID].id; generate if(FEATURE_DEMUX_MAPPED == 0) begin : eu_not_demux_mapped_gen diff --git a/rtl/core_demux_wrap.sv b/rtl/core_demux_wrap.sv index b11d3c00..e4446aba 100644 --- a/rtl/core_demux_wrap.sv +++ b/rtl/core_demux_wrap.sv @@ -1,11 +1,13 @@ module core_demux_wrap #( - parameter int unsigned AddrWidth = 32 , - parameter int unsigned DataWidth = 32 , - parameter int unsigned RemapAddress = 1 , - parameter int unsigned ClustAlias = 1 , - parameter int unsigned ClustAliasBase = 12'h000 , - parameter int unsigned NumExtPerf = 5 , - localparam int unsigned ByteEnable = DataWidth/8 + parameter int unsigned AddrWidth = 32 , + parameter int unsigned DataWidth = 32 , + parameter int unsigned RemapAddress = 1 , + parameter int unsigned ClustAlias = 1 , + parameter int unsigned ClustAliasBase = 12'h000 , + parameter int unsigned NumExtPerf = 5 , + parameter type core_data_req_t = logic , + parameter type core_data_rsp_t = logic , + localparam int unsigned ByteEnable = DataWidth/8 )( input logic clk_i , input logic rst_ni , @@ -14,24 +16,19 @@ module core_demux_wrap #( input logic [3:0] base_addr_i , input logic [5:0] cluster_id_i , output logic [NumExtPerf-1:0] ext_perf_o , - hci_core_intf.slave core_bus_slv_i , + input core_data_req_t core_data_req_i , + output core_data_rsp_t core_data_rsp_o , hci_core_intf.master tcdm_bus_mst_o , hci_core_intf.master dma_ctrl_mst_o , XBAR_PERIPH_BUS.Master eventunit_bus_mst_o , XBAR_PERIPH_BUS.Master peripheral_bus_mst_o ); -localparam N_EXT_PERF_COUNTERS_ACTUAL = 5; // Temporary - -logic clk_int; -logic [N_EXT_PERF_COUNTERS_ACTUAL-1:0] perf_counters; - XBAR_PERIPH_BUS periph_demux_bus(); -assign core_bus_slv_i.r_user = '0; - assign tcdm_bus_mst_o.boffs = '0; assign tcdm_bus_mst_o.lrdy = '1; +assign tcdm_bus_mst_o.user = '0; data_periph_demux #( .ADDR_WIDTH ( AddrWidth ), @@ -45,15 +42,15 @@ data_periph_demux #( .rst_ni ( rst_ni ), .test_en_i ( test_en_i ), .base_addr_i ( base_addr_i ), - .data_req_i ( core_bus_slv_i.req ), - .data_add_i ( core_bus_slv_i.add ), - .data_wen_i ( core_bus_slv_i.wen ), //inverted when using OR10N - .data_wdata_i ( core_bus_slv_i.data ), - .data_be_i ( core_bus_slv_i.be ), - .data_gnt_o ( core_bus_slv_i.gnt ), - .data_r_valid_o ( core_bus_slv_i.r_valid ), - .data_r_opc_o ( core_bus_slv_i.r_opc ), - .data_r_rdata_o ( core_bus_slv_i.r_data ), + .data_req_i ( core_data_req_i.req ), + .data_add_i ( core_data_req_i.add ), + .data_wen_i ( core_data_req_i.wen ), //inverted when using OR10N + .data_wdata_i ( core_data_req_i.data ), + .data_be_i ( core_data_req_i.be ), + .data_gnt_o ( core_data_rsp_o.gnt ), + .data_r_valid_o ( core_data_rsp_o.r_valid ), + .data_r_opc_o ( /* ucnconnected */ ), + .data_r_rdata_o ( core_data_rsp_o.r_data ), .data_req_o_SH ( tcdm_bus_mst_o.req ), .data_add_o_SH ( tcdm_bus_mst_o.add ), @@ -91,6 +88,8 @@ data_periph_demux #( .CLUSTER_ID ( cluster_id_i ) ); +assign ext_perf_o[4] = '0; + assign periph_demux_bus.id = '0; assign dma_ctrl_mst_o.boffs = '0; diff --git a/rtl/core_region.sv b/rtl/core_region.sv index e64d8413..cb08152d 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -26,39 +26,42 @@ module core_region #( // CORE PARAMETERS - parameter CORE_TYPE_CL = 0, // 0 for CV32, 1 RI5CY, 2 for IBEX RV32IMC - // parameter USE_FPU = 1, - // parameter USE_HWPE = 1, - parameter N_EXT_PERF_COUNTERS = 1, - parameter NUM_INTERRUPTS = 32, - parameter CORE_ID = 0, - parameter ADDR_WIDTH = 32, - parameter DATA_WIDTH = 32, - parameter INSTR_RDATA_WIDTH = 32, - parameter CLUSTER_ALIAS = 1, - parameter CLUSTER_ALIAS_BASE = 12'h000, - parameter REMAP_ADDRESS = 0, - - parameter APU_NARGS_CPU = 2, - parameter APU_WOP_CPU = 1, - parameter WAPUTYPE = 3, - parameter APU_NDSFLAGS_CPU = 3, - parameter APU_NUSFLAGS_CPU = 5, - - parameter FPU = 0, - parameter FP_DIVSQRT = 0, - parameter SHARED_FP = 0, - parameter SHARED_FP_DIVSQRT = 0, - - parameter DEBUG_START_ADDR = 32'h1A110000, - - parameter L2_SLM_FILE = "./slm_files/l2_stim.slm", - parameter ROM_SLM_FILE = "../sw/apps/boot/slm_files/l2_stim.slm" + parameter CORE_TYPE_CL = 0, // 0 for CV32, 1 RI5CY, 2 for IBEX RV32IMC + // parameter USE_FPU = 1, + // parameter USE_HWPE = 1, + parameter N_EXT_PERF_COUNTERS = 1, + parameter NUM_INTERRUPTS = 32, + parameter CORE_ID = 0, + parameter ADDR_WIDTH = 32, + parameter DATA_WIDTH = 32, + parameter INSTR_RDATA_WIDTH = 32, + parameter CLUSTER_ALIAS = 1, + parameter CLUSTER_ALIAS_BASE = 12'h000, + parameter REMAP_ADDRESS = 0, + + parameter APU_NARGS_CPU = 2, + parameter APU_WOP_CPU = 1, + parameter WAPUTYPE = 3, + parameter APU_NDSFLAGS_CPU = 3, + parameter APU_NUSFLAGS_CPU = 5, + + parameter FPU = 0, + parameter FP_DIVSQRT = 0, + parameter SHARED_FP = 0, + parameter SHARED_FP_DIVSQRT = 0, + + parameter DEBUG_START_ADDR = 32'h1A110000, + + parameter type core_data_req_t = logic, + parameter type core_data_rsp_t = logic, + + parameter L2_SLM_FILE = "./slm_files/l2_stim.slm", + parameter ROM_SLM_FILE = "../sw/apps/boot/slm_files/l2_stim.slm" ) ( input logic clk_i, input logic rst_ni, - input logic init_ni, + input logic setback_i, input logic [5:0] cluster_id_i, @@ -90,8 +93,8 @@ module core_region input logic [N_EXT_PERF_COUNTERS-1:0] ext_perf_i, - hci_core_intf.master core_bus_mst_o, - + output core_data_req_t core_data_req_o, + input core_data_rsp_t core_data_rsp_i, output logic apu_master_req_o, input logic apu_master_gnt_i, // request channel @@ -142,11 +145,9 @@ module core_region logic [31:0] core_shadow_addr ; logic [31:0] core_shadow_wdata; logic [5:0] core_data_atop ; - logic core_bus_must_we; + logic core_data_req_we ; - assign core_bus_mst_o.wen = ~core_bus_must_we; - assign core_bus_mst_o.lrdy = '1; - assign core_bus_mst_o.user = '0; + assign core_data_req_o.wen = ~core_data_req_we; assign hart_id = {21'b0, cluster_id_i[5:0], 1'b0, CORE_ID[3:0]}; //******************************************************** @@ -183,14 +184,14 @@ module core_region .instr_addr_o ( instr_addr_o ), .instr_rdata_i ( instr_r_rdata_i ), // Data Interface - .data_req_o ( core_bus_mst_o.req ), - .data_gnt_i ( core_bus_mst_o.gnt ), - .data_rvalid_i ( core_bus_mst_o.r_valid ), - .data_we_o ( core_bus_must_we ), - .data_be_o ( core_bus_mst_o.be ), - .data_addr_o ( core_bus_mst_o.add ), - .data_wdata_o ( core_bus_mst_o.data ), - .data_rdata_i ( core_bus_mst_o.r_data ), + .data_req_o ( core_data_req_o.req ), + .data_gnt_i ( core_data_rsp_i.gnt ), + .data_rvalid_i ( core_data_rsp_i.r_valid ), + .data_we_o ( core_data_req_we ), + .data_be_o ( core_data_req_o.be ), + .data_addr_o ( core_data_req_o.add ), + .data_wdata_o ( core_data_req_o.data ), + .data_rdata_i ( core_data_rsp_i.r_data ), // Shadow Memory Interface .shadow_req_o ( sadow_req ), .shadow_gnt_i ( '0 ), @@ -246,6 +247,7 @@ module core_region ) RI5CY_CORE ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .setback_i ( setback_i ), .clock_en_i ( clock_en_i ), .test_en_i ( test_mode_i ), // .setback_i ( '0 ), // Useful for HMR @@ -261,14 +263,14 @@ module core_region .instr_addr_o ( instr_addr_o ), .instr_rdata_i ( instr_r_rdata_i ), // Data Interface - .data_req_o ( core_bus_mst_o.req ), - .data_gnt_i ( core_bus_mst_o.gnt ), - .data_rvalid_i ( core_bus_mst_o.r_valid ), - .data_we_o ( core_bus_must_we ), - .data_be_o ( core_bus_mst_o.be ), - .data_addr_o ( core_bus_mst_o.add ), - .data_wdata_o ( core_bus_mst_o.data ), - .data_rdata_i ( core_bus_mst_o.r_data ), + .data_req_o ( core_data_req_o.req ), + .data_gnt_i ( core_data_rsp_i.gnt ), + .data_rvalid_i ( core_data_rsp_i.r_valid ), + .data_we_o ( core_data_req_we ), + .data_be_o ( core_data_req_o.be ), + .data_addr_o ( core_data_req_o.add ), + .data_wdata_o ( core_data_req_o.data ), + .data_rdata_i ( core_data_rsp_i.r_data ), .data_unaligned_o ( /* Unused */ ), // apu-interconnect // Handshake @@ -343,9 +345,9 @@ module core_region .clk_i (clk_i ), .rst_ni (rst_ni ), .core_req_i (core_mem_req ), - .mem_req_o (core_bus_mst_o.req ), - .mem_gnt_i (core_bus_mst_o.gnt ), - .mem_rvalid_i(core_bus_mst_o.r_valid) + .mem_req_o (core_data_req_o.req ), + .mem_gnt_i (core_data_rsp_i.gnt ), + .mem_rvalid_i(core_data_rsp_i.r_valid) ); `ifdef VERILATOR @@ -392,14 +394,14 @@ module core_region .instr_err_i ( 1'b0 ), // Data memory interface: - .data_req_o ( core_mem_req ), - .data_gnt_i ( core_bus_mst_o.gnt ), - .data_rvalid_i ( core_bus_mst_o.r_valid ), - .data_we_o ( ~core_bus_mst_o.we ), - .data_be_o ( core_bus_mst_o.be ), - .data_addr_o ( core_bus_mst_o.add ), - .data_wdata_o ( core_bus_mst_o.wdata ), - .data_rdata_i ( core_bus_mst_o.r_rdata ), + .data_req_o ( core_mem_req ), + .data_gnt_i ( core_data_rsp_i.gnt ), + .data_rvalid_i ( core_data_rsp_i.r_valid ), + .data_we_o ( core_data_req_we ), + .data_be_o ( core_data_req_o.be ), + .data_addr_o ( core_data_req_o.add ), + .data_wdata_o ( core_data_req_o.wdata ), + .data_rdata_i ( core_data_rsp_i.r_rdata ), .data_err_i ( 1'b0 ), .irq_software_i ( 1'b0 ), @@ -439,12 +441,12 @@ module core_region always @(posedge clk_i) begin : CHECK_ASSERTIONS `ifndef CLUSTER_ALIAS - if ((core_bus_mst_o.req == 1'b1) && (core_bus_mst_o.add < 32'h1000_0000)) begin - $error("ERROR_1 (0x00000000 -> 0x10000000) : Data interface is making a request on unmapped region --> %8x\t at time %t [ns]" ,core_bus_mst_o.add, $time()/1000 ); + if ((core_data_req_o.req == 1'b1) && (core_data_req_o.add < 32'h1000_0000)) begin + $error("ERROR_1 (0x00000000 -> 0x10000000) : Data interface is making a request on unmapped region --> %8x\t at time %t [ns]" ,core_data_req_o.add, $time()/1000 ); $finish(); end - if ((core_bus_mst_o.req == 1'b1) && (core_bus_mst_o.add >= 32'h1040_0000) && ((core_bus_mst_o.add < 32'h1A00_0000))) begin - $error("ERROR_2 (0x10400000 -> 0x1A000000) : Data interface is making a request on unmapped region --> %8x\t at time %t [ns]" ,core_bus_mst_o.add, $time()/1000 ); + if ((core_data_req_o.req == 1'b1) && (core_data_req_o.add >= 32'h1040_0000) && ((core_data_req_o.add < 32'h1A00_0000))) begin + $error("ERROR_2 (0x10400000 -> 0x1A000000) : Data interface is making a request on unmapped region --> %8x\t at time %t [ns]" ,core_data_req_o.add, $time()/1000 ); $finish(); end `endif diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 9f753256..32c992b3 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -21,6 +21,7 @@ `include "axi/assign.svh" `include "cluster_bus_defines.sv" `include "pulp_interfaces.sv" +`include "register_interface/typedef.svh" module pulp_cluster import pulp_cluster_package::*; @@ -144,7 +145,6 @@ module pulp_cluster input logic rst_ni, input logic ref_clk_i, input logic pwr_on_rst_ni, - input logic core_init_ni, input logic pmu_mem_pwdn_i, @@ -393,6 +393,9 @@ XBAR_PERIPH_BUS s_core_periph_bus[NB_CORES-1:0](); // periph interconnect -> DMA XBAR_PERIPH_BUS s_periph_dma_bus[1:0](); +// periph interconnect -> HMR unit +XBAR_PERIPH_BUS s_periph_hmr_bus (); + // debug XBAR_TCDM_BUS s_debug_bus[NB_CORES-1:0](); @@ -757,6 +760,7 @@ cluster_peripherals #( .core_eu_direct_link ( s_core_euctrl_bus ), .dma_cfg_master ( s_periph_dma_bus ), + .hmr_cfg_master ( s_periph_hmr_bus ), .dma_cl_event_i ( s_dma_cl_event ), .dma_cl_irq_i ( s_dma_cl_irq ), @@ -813,17 +817,43 @@ cluster_peripherals #( //------------------------------------------------------// /* cluster cores + core-coupled accelerators / shared execution units */ +`REG_BUS_TYPEDEF_ALL(hmr_reg, logic[31:0], logic[31:0], logic[3:0]) +hmr_reg_req_t hmr_reg_req; +hmr_reg_rsp_t hmr_reg_rsp; + +periph_to_reg #( + .AW ( ADDR_WIDTH ), + .DW ( DATA_WIDTH ), + .BW ( 8 ), + .IW ( NB_CORES + 1 ), + .req_t ( hmr_reg_req_t ), + .rsp_t ( hmr_reg_rsp_t ) +) i_periph_to_hmr ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( s_periph_hmr_bus.req ), + .add_i ( s_periph_hmr_bus.add ), + .wen_i ( s_periph_hmr_bus.wen ), + .wdata_i ( s_periph_hmr_bus.wdata ), + .be_i ( s_periph_hmr_bus.be ), + .id_i ( s_periph_hmr_bus.id ), + .gnt_o ( s_periph_hmr_bus.gnt ), + .r_rdata_o ( s_periph_hmr_bus.r_rdata ), + .r_opc_o ( s_periph_hmr_bus.r_opc ), + .r_id_o ( s_periph_hmr_bus.r_id ), + .r_valid_o ( s_periph_hmr_bus.r_valid ), + .reg_req_o ( hmr_reg_req ), + .reg_rsp_i ( hmr_reg_rsp ) +); + +core_data_req_t [NB_CORES-1:0] core_data_req, demux_data_req; +core_data_rsp_t [NB_CORES-1:0] core_data_rsp, demux_data_rsp; +core_inputs_t [NB_CORES-1:0] sys2hmr, hmr2core; +core_outputs_t [NB_CORES-1:0] hmr2sys, core2hmr; logic [NB_CORES-1:0] clk_core; +logic [NB_CORES-1:0] setback; logic [NB_CORES-1:0][4:0] ext_perf; -hci_core_intf #( - .DW ( DATA_WIDTH ), - .AW ( ADDR_WIDTH ), - .OW ( 1 ) -) core_bus_mst [NB_CORES-1:0] ( - .clk ( clk_i ) -); - generate for (genvar i=0; i Date: Wed, 31 May 2023 14:12:58 +0200 Subject: [PATCH 032/207] Fixed unconnected signals. --- Bender.lock | 2 +- Bender.yml | 2 +- rtl/core_region.sv | 3 +++ rtl/pulp_cluster.sv | 11 +++++------ 4 files changed, 10 insertions(+), 8 deletions(-) diff --git a/Bender.lock b/Bender.lock index 9d98e8db..2c9ac646 100644 --- a/Bender.lock +++ b/Bender.lock @@ -220,7 +220,7 @@ packages: - common_cells - common_verification riscv: - revision: dbcf0bbf827e1ec323ca223883c92ebfe9347c67 + revision: 4ceb402db8619718a9170058bb31f75fcdf7ed1c version: null source: Git: git@github.com:AlSaqr-platform/riscv_nn.git diff --git a/Bender.yml b/Bender.yml index c93d5002..20e8313f 100644 --- a/Bender.yml +++ b/Bender.yml @@ -27,7 +27,7 @@ dependencies: timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: dbcf0bbf827e1ec323ca223883c92ebfe9347c67 } # branch: yt/hmr + riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 4ceb402db8619718a9170058bb31f75fcdf7ed1c } # branch: yt/hmr cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "9b77611" } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating diff --git a/rtl/core_region.sv b/rtl/core_region.sv index cb08152d..95712f95 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -304,6 +304,9 @@ module core_region // External performance monitoring signals .ext_perf_counters_i ( ext_perf_i ) ); + assign debug_havereset_o = '0; + assign debug_running_o = '0; + assign debug_halted_o = '0; end else begin: IBEX_CORE assign boot_addr = boot_addr_i & 32'hFFFFFF00; // RI5CY expects 0x80 offset, Ibex expects 0x00 offset (adds reset offset 0x80 internally) // Core busy diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 32c992b3..9b780433 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -727,8 +727,7 @@ cluster_interconnect_wrap #( //*************************************************** //**************CLUSTER PERIPHERALS****************** -//*************************************************** - +//*************************************************** cluster_peripherals #( .NB_CORES ( NB_CORES ), .NB_MPERIPHS ( NB_MPERIPHS ), @@ -771,7 +770,7 @@ cluster_peripherals #( // NEW_SIGNALS .decompr_done_evt_i ( s_decompr_done_evt ), .dma_fc_event_i ( s_dma_fc_event ), - .dma_fc_irq_i ( ), + .dma_fc_irq_i ( '0 ), .soc_periph_evt_ready_o ( s_events_ready ), .soc_periph_evt_valid_i ( s_events_valid ), @@ -916,9 +915,9 @@ generate //debug unit bind .debug_req_i ( hmr2core[i].debug_req | s_core_dbg_irq[i] ), - // .debug_halted_o ( dbg_core_halted[i] ), - // .debug_havereset_o ( dbg_core_havereset[i] ), - // .debug_running_o ( dbg_core_running[i] ), + .debug_halted_o ( dbg_core_halted[i] ), + .debug_havereset_o ( dbg_core_havereset[i] ), + .debug_running_o ( dbg_core_running[i] ), .ext_perf_i ( ext_perf[i] ), .core_data_req_o ( core_data_req[i] ), .core_data_rsp_i ( core_data_rsp[i] ), From 9404fdb3b435c0760aead86a0d89e5ce0b4334fc Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 31 May 2023 15:34:17 +0200 Subject: [PATCH 033/207] Integrated RedMulE. --- Bender.local | 2 + Bender.lock | 17 +- Bender.yml | 3 +- rtl/hwpe_subsystem.sv | 46 +-- tb/pulp_cluster_tb.sv | 4 +- wave.do | 822 ++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 856 insertions(+), 38 deletions(-) create mode 100644 wave.do diff --git a/Bender.local b/Bender.local index 723b1b0a..949a509a 100644 --- a/Bender.local +++ b/Bender.local @@ -2,3 +2,5 @@ overrides: axi : { git: "https://github.com/pulp-platform/axi.git" , version: =0.39.0-beta.9 } register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix + cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: 9b77611a1d0c681f4819798d95422b0b895528a2 } # `michaero/safety-island-clic` branch + hci : { git: "https://github.com/pulp-platform/hci.git" , rev: bender-fix } \ No newline at end of file diff --git a/Bender.lock b/Bender.lock index 2c9ac646..9a9bf69e 100644 --- a/Bender.lock +++ b/Bender.lock @@ -113,8 +113,8 @@ packages: - cv32e40p - fpnew hci: - revision: 8fb848e8f6722c1c21b44533535f430960c31b0b - version: 1.0.8 + revision: b5c11e3645356ed6031d41c85becb7214598c59d + version: null source: Git: https://github.com/pulp-platform/hci.git dependencies: @@ -199,6 +199,19 @@ packages: Git: https://github.com/pulp-platform/per2axi.git dependencies: - axi_slice + redmule: + revision: c7478dafc96ccfef9dbb5f2b246371d42e9cae19 + version: null + source: + Git: https://github.com/pulp-platform/redmule.git + dependencies: + - common_cells + - cv32e40p + - fpnew + - hci + - hwpe-ctrl + - hwpe-stream + - tech_cells_generic redundancy_cells: revision: 6e10650b50c7b40f7f81602acf61526330c4d69d version: null diff --git a/Bender.yml b/Bender.yml index 20e8313f..8ec9a34c 100644 --- a/Bender.yml +++ b/Bender.yml @@ -28,7 +28,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 4ceb402db8619718a9170058bb31f75fcdf7ed1c } # branch: yt/hmr - cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "9b77611" } # `michaero/safety-island-clic` branch + cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: 9b77611a1d0c681f4819798d95422b0b895528a2 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating hwpe-datamover-example: { git: "https://github.com/pulp-platform/hwpe-datamover-example.git", version: 1.0.1 } @@ -36,6 +36,7 @@ dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 6e10650b50c7b40f7f81602acf61526330c4d69d} # branch: yt/hmr + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: c7478dafc96ccfef9dbb5f2b246371d42e9cae19 } # branch: power-management export_include_dirs: - include diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index e2e33063..8f5f6a16 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -40,39 +40,19 @@ module hwpe_subsystem .clk ( clk ) ); - generate - if(USE_RBE) begin : rbe_gen - rbe_top #( - .ID ( ID_WIDTH ), - .N_CORES ( N_CORES ), - .BW ( N_MASTER_PORT*32 ) - ) hwpe_top_wrap_i ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .test_mode_i ( test_mode ), - .evt_o ( evt_o ), - .tcdm ( hwpe_xbar_master ), - .hci_ctrl_o ( ), - .periph ( periph ) - ); - assign busy_o = 1'b1; - end - else begin : datamover_gen - datamover_top #( - .ID ( ID_WIDTH ), - .N_CORES ( N_CORES ), - .BW ( N_MASTER_PORT*32 ) - ) hwpe_top_wrap_i ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .test_mode_i ( test_mode ), - .evt_o ( evt_o ), - .tcdm ( hwpe_xbar_master ), - .periph ( periph ) - ); - assign busy_o = 1'b1; - end - endgenerate + redmule_top #( + .ID_WIDTH ( ID_WIDTH ), + .N_CORES ( N_CORES ), + .DW ( N_MASTER_PORT*32 ) + ) i_redmule ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_mode_i ( test_mode ), + .busy_o ( busy_o ), + .evt_o ( evt_o ), + .tcdm ( hwpe_xbar_master ), + .periph ( periph ) + ); always_comb begin diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 4bf6d2c3..91a19077 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -259,9 +259,9 @@ module pulp_cluster_tb; pulp_cluster #( .NB_CORES ( `NB_CORES ), - .NB_HWPE_PORTS ( 4 ), + .NB_HWPE_PORTS ( 9 ), .NB_DMAS ( `NB_DMAS ), - .HWPE_PRESENT ( 0 ), + .HWPE_PRESENT ( 1 ), .TCDM_SIZE ( 128*1024 ), .NB_TCDM_BANKS ( 16 ), .SET_ASSOCIATIVE ( 4 ), diff --git a/wave.do b/wave.do new file mode 100644 index 00000000..c54e4dca --- /dev/null +++ b/wave.do @@ -0,0 +1,822 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/clk_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/rst_ni +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/ref_clk_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/pwr_on_rst_ni +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/pmu_mem_pwdn_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/base_addr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/test_mode_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/en_sa_boot_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/cluster_id_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/fetch_en_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/eoc_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/busy_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/axi_isolate_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/axi_isolated_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dma_pe_evt_ack_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dma_pe_evt_valid_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dma_pe_irq_ack_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dma_pe_irq_valid_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/pf_evt_ack_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/pf_evt_valid_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dbg_irq_valid_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/mbox_irq_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_cluster_events_wptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_cluster_events_rptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_cluster_events_data_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_aw_wptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_aw_data_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_aw_rptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_ar_wptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_ar_data_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_ar_rptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_w_wptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_w_data_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_w_rptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_r_wptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_r_data_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_r_rptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_b_wptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_b_data_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_slave_b_rptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_aw_wptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_aw_data_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_aw_rptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_ar_wptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_ar_data_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_ar_rptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_w_wptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_w_data_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_w_rptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_r_wptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_r_data_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_r_rptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_b_wptr_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_b_data_i +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/async_data_master_b_rptr_o +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/fetch_enable_reg_int +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/fetch_en_int +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/boot_addr +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dbg_core_halt +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dbg_core_resume +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dbg_core_halted +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dbg_core_havereset +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dbg_core_running +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dbg_irq +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_hwpe_en +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/fetch_en_synch +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/en_sa_boot_synch +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/axi_isolate_synch +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/eoc_synch +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_cluster_periphs_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_axi2mem_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_per2axi_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_axi2per_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dmac_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_cluster_cg_en +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dma_event +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dma_irq +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_hwpe_remap_evt +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_hwpe_evt +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_hwpe_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_hci_ctrl +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/clk_core_en +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_cluster_int_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_fregfile_disable +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/core_busy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_incoming_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_isolate_cluster +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_events_async +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_events_valid +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_events_ready +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_events_data +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/instr_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/instr_addr +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/instr_gnt +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/instr_r_valid +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/instr_r_rdata +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_TCDM_arb_policy +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/tcdm_sleep +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/irq_id +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/irq_ack_id +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/irq_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/irq_ack +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_core_dbg_irq +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_rw_margin_L1 +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dma_cl_event +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dma_cl_irq +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dma_fc_event +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_dma_fc_irq +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_gnt +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_operands +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_op +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_type +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_flags +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_rready +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_rvalid +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_rdata +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu_master_rflags +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_special_core_icache_cfg +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_enable_l1_l15_prefetch +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/mbox_irq_synch +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/hmr_reg_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/hmr_reg_rsp +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/core_data_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/demux_data_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/core_data_rsp +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/demux_data_rsp +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/sys2hmr +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/hmr2core +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/hmr2sys +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/core2hmr +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/clk_core +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/setback +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/ext_perf +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu__operands +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu__op +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu__type +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu__flags +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/s_apu__rflags +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/src_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/isolate_src_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/src_resp +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/isolate_src_resp +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dst_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/isolate_dst_req +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dst_resp +add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/isolate_dst_resp +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/clk} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/rst_ni} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/test_en_i} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/base_addr_i} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_req_i} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_i} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wen_i} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wdata_i} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_be_i} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_gnt_o} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_valid_o} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_rdata_o} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_opc_o} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_req_o_SH} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_o_SH} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wen_o_SH} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wdata_o_SH} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_be_o_SH} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_gnt_i_SH} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_valid_i_SH} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_rdata_i_SH} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_req_o_EXT} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_o_EXT} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wen_o_EXT} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wdata_o_EXT} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_be_o_EXT} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_gnt_i_EXT} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_valid_i_EXT} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_rdata_i_EXT} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_opc_i_EXT} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_req_o_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_o_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wen_o_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wdata_o_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_be_o_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_gnt_i_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_valid_i_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_opc_i_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_rdata_i_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/perf_l2_ld_o} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/perf_l2_st_o} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/perf_l2_ld_cyc_o} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/perf_l2_st_cyc_o} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/CLUSTER_ID} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/CLUSTER_ALIAS_BASE_11} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/CLUSTER_ALIAS_BASE_12} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_req_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_gnt_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_r_data_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_r_valid_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_r_opc_PE} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_r_data_PE_0} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_r_valid_PE_0} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_r_opc_PE_0} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/CS} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/NS} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_req_to_L2} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_to_L2} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wen_to_L2} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wdata_to_L2} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_be_to_L2} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_gnt_from_L2} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/request_destination} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/destination} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_int} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_busy_PE_fifo} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_req_PE_fifo} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_PE_fifo} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wen_PE_fifo} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wdata_PE_fifo} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_be_PE_fifo} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_gnt_PE_fifo} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_valid_PE_fifo} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_opc_PE_fifo} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_rdata_PE_fifo} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/TCDM_RW} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/TCDM_TS} +add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/DEM_PER} +add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/clk_i} +add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/rst_ni} +add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/test_en_i} +add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/clk_en_i} +add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/base_addr_i} +add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/cluster_id_i} +add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/ext_perf_o} +add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/core_data_req_i} +add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/core_data_rsp_o} +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/clk_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/rst_ni +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/reg_request_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/reg_response_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_failure_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_error_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_resynch_req_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_sw_synch_req_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_cores_synch_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_failure_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_error_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_resynch_req_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_sw_synch_req_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_cores_synch_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/sys_inputs_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/sys_nominal_outputs_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/sys_bus_outputs_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/sys_fetch_en_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/enable_bus_vote_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_setback_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_inputs_o +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_nominal_outputs_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_bus_outputs_i +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_nominal_outputs +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_bus_outputs +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_nominal_outputs +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_bus_outputs +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_failure +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_failure_main +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_failure_data +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_error +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_error_main +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_error_data +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_single_mismatch +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_failure +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_failure_main +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_failure_data +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_en_as_master +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_in_independent +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_in_dmr +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_in_tmr +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_core_rapid_recovery_en +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_core_rapid_recovery_en +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_setback_q +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_grp_in_independent +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_rapid_recovery_en +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_setback_q +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_grp_in_independent +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_rapid_recovery_en +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/sp_store_is_zero +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/sp_store_will_be_zero +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/top_register_reqs +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/top_register_resps +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/hmr_hw2reg +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/hmr_reg2hw +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_register_reqs +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_register_resps +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_config_reg2hw +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_config_hw2reg +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_incr_mismatches +add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_incr_mismatches +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/clk_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/rst_ni} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/cluster_id_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_req_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_ack_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_id_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_ack_id_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/clock_en_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/fetch_en_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/boot_addr_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/test_mode_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_busy_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_req_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_addr_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_req_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_havereset_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_running_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_halted_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/ext_perf_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_req_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_rsp_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_req_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_type_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_operands_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_op_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_flags_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_ready_o} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_valid_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_result_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_flags_i} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/hart_id} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_sleep} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/boot_addr} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_irq_x} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_req} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_gnt} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_addr} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_r_valid} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_mem_req} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_req} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_we} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_be} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_addr} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_wdata} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_atop} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/FILE} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_L2} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/destination} +add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/reg_cache_refill} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/clk} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/rst_ni} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_req_i} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_add_i} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_wen_i} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_wdata_i} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_be_i} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_gnt_o} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_valid_o} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_rdata_o} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_opc_o} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_req_o_MH} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_add_o_MH} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_wen_o_MH} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_wdata_o_MH} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_be_o_MH} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_gnt_i_MH} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_valid_i_MH} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_rdata_i_MH} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_opc_i_MH} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_req_o_EU} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_add_o_EU} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_wen_o_EU} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_wdata_o_EU} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_be_o_EU} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_gnt_i_EU} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_valid_i_EU} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_rdata_i_EU} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_opc_i_EU} +add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/request_destination} +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/clk_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/rst_ni +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/ref_clk_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/test_mode_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/en_sa_boot_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/fetch_en_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/core_busy_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/core_clk_en_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/fregfile_disable_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/boot_addr_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_cg_en_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/busy_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dma_event_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dma_irq_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/mbox_irq_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dma_cl_event_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dma_cl_irq_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dma_fc_event_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dma_fc_irq_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/soc_periph_evt_ready_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/soc_periph_evt_valid_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/soc_periph_evt_data_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dbg_core_halted_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dbg_core_halt_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dbg_core_resume_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eoc_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/fetch_enable_reg_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/irq_id_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/irq_ack_id_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/irq_req_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/irq_ack_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dbg_req_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/dbg_req_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/TCDM_arb_policy_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/hwpe_events_i +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/hwpe_en_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/hci_ctrl_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/enable_l1_l15_prefetch_o +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_timer_out_lo_event +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_timer_out_hi_event +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_timer_in_lo_event +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_timer_in_hi_event +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_cluster_events +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_acc_events +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_timer_events +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_dma_events +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/s_fetch_en_cc +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eu_speriph_plug_req +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eu_speriph_plug_add +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eu_speriph_plug_wen +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eu_speriph_plug_wdata +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eu_speriph_plug_be +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/eu_speriph_plug_id +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/soc_periph_evt_valid +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/soc_periph_evt_ready +add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/soc_periph_evt_data +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/clk_i +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/rst_ni +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/en_sa_boot_i +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fetch_en_i +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/event_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/eoc_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/cluster_cg_en_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/hwpe_en_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/hci_ctrl_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fregfile_disable_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/core_halted_i +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/core_halt_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/core_resume_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fetch_enable_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/boot_addr_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/TCDM_arb_policy_o +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/rvalid_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/rvalid_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/id_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/id_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/rdata_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/rdata_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fetch_en_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fetch_en_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/dbg_halt_mask_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/dbg_halt_mask_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/core_halted_any_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/core_halted_any_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/eoc_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/event_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/hwpe_en_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/hci_ctrl_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/hci_ctrl_q +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fregfile_disable_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/boot_addr_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/fetch_en_sync +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/start_fetch +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/start_boot +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/cluster_cg_en_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/TCDM_arb_policy_n +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/core_halt_rising_edge +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/boot_cs +add wave -noupdate -group cluster_control_unit /pulp_cluster_tb/cluster_i/cluster_peripherals_i/cluster_control_unit_i/boot_ns +add wave -noupdate -group hwpe_subsystem /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/clk +add wave -noupdate -group hwpe_subsystem /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/rst_n +add wave -noupdate -group hwpe_subsystem /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/test_mode +add wave -noupdate -group hwpe_subsystem /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/evt_o +add wave -noupdate -group hwpe_subsystem /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/busy_o +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/clk_i +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/rst_ni +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/test_mode_i +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/busy_o +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/evt_o +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/fsm_z_clk_en +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/ctrl_z_clk_en +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/enable +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/clear +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/soft_clear +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/y_buffer_depth_count +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/y_buffer_load +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/z_buffer_fill +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/z_buffer_store +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_shift +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_load +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/reg_enable +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/gate_en +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_cols_lftovr +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/y_cols_lftovr +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_rows_lftovr +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/y_rows_lftovr +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/cntrl_streamer +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/flgs_streamer +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/cntrl_engine +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/x_buffer_ctrl +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/x_buffer_flgs +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_buffer_ctrl +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_buffer_flgs +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/z_buffer_ctrl +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/z_buffer_flgs +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/cntrl_scheduler +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/flgs_scheduler +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/reg_file +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_fifo_flgs +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/x_buffer_clk_en +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/x_buffer_clock +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/x_buffer_q +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/w_buffer_q +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/z_buffer_d +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/y_bias_q +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/ctrl_engine +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/flgs_engine +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/accumulate +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/engine_flush +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/fma_is_boxed +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/noncomp_is_boxed +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/stage1_rnd +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/stage2_rnd +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/op1 +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/op2 +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/op_mod +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/in_tag +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/in_aux +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/in_valid +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/in_ready +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/flush +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/status +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/extension_bit +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/class_mask +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/is_class +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/out_tag +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/out_aux +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/out_valid +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/out_ready +add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/busy +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {112525599521 ps} 0} {{Cursor 2} {67278742839 ps} 0} {{Cursor 3} {323044715583 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 211 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {339486 us} From ba8f3cc3c06433d710b70e6e663239ddfd33d50e Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 31 May 2023 18:59:55 +0200 Subject: [PATCH 034/207] Updated dependencies. --- Bender.local | 2 -- Bender.lock | 17 ++++------------- Bender.yml | 9 ++++----- 3 files changed, 8 insertions(+), 20 deletions(-) diff --git a/Bender.local b/Bender.local index 949a509a..723b1b0a 100644 --- a/Bender.local +++ b/Bender.local @@ -2,5 +2,3 @@ overrides: axi : { git: "https://github.com/pulp-platform/axi.git" , version: =0.39.0-beta.9 } register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix - cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: 9b77611a1d0c681f4819798d95422b0b895528a2 } # `michaero/safety-island-clic` branch - hci : { git: "https://github.com/pulp-platform/hci.git" , rev: bender-fix } \ No newline at end of file diff --git a/Bender.lock b/Bender.lock index 9a9bf69e..6c0fb30d 100644 --- a/Bender.lock +++ b/Bender.lock @@ -53,8 +53,8 @@ packages: dependencies: - common_cells cluster_peripherals: - revision: d388a790d9e1129e3ec57b2e0075ee21e454c3b1 - version: 2.1.0 + revision: a596f17fc77713909bceb7eecf3ea2c3cdfe707c + version: null source: Git: https://github.com/pulp-platform/cluster_peripherals.git dependencies: @@ -113,7 +113,7 @@ packages: - cv32e40p - fpnew hci: - revision: b5c11e3645356ed6031d41c85becb7214598c59d + revision: b2e6f391aa6c10c03f45b693d80a0aaddecf169b version: null source: Git: https://github.com/pulp-platform/hci.git @@ -140,15 +140,6 @@ packages: Git: https://github.com/pulp-platform/hwpe-ctrl.git dependencies: - tech_cells_generic - hwpe-datamover-example: - revision: 47e7fe8a38331b123d763ecab11be4058d425021 - version: 1.0.1 - source: - Git: https://github.com/pulp-platform/hwpe-datamover-example.git - dependencies: - - hci - - hwpe-ctrl - - hwpe-stream hwpe-stream: revision: ddc154424187dff42a8fcec946c768ceb13f13de version: 1.6.4 @@ -200,7 +191,7 @@ packages: dependencies: - axi_slice redmule: - revision: c7478dafc96ccfef9dbb5f2b246371d42e9cae19 + revision: 3797413e5f190c2a86185ab6d8b12af365051b1e version: null source: Git: https://github.com/pulp-platform/redmule.git diff --git a/Bender.yml b/Bender.yml index 8ec9a34c..ac9e7bcb 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,7 +20,7 @@ dependencies: mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a7e3f4e4c7fe607bcd6b9d94db77f612fd6ef6be" } # branch: yt/carfield - cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", version: 2.1.0 } + cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: a596f17fc77713909bceb7eecf3ea2c3cdfe707c } # branch: yt/bump-hci fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "0769976fa51bdd820656a01161a4c46b88c59ac5" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0-beta.9 } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) @@ -28,15 +28,14 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 4ceb402db8619718a9170058bb31f75fcdf7ed1c } # branch: yt/hmr - cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: 9b77611a1d0c681f4819798d95422b0b895528a2 } # `michaero/safety-island-clic` branch + cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: 9b77611 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating - hwpe-datamover-example: { git: "https://github.com/pulp-platform/hwpe-datamover-example.git", version: 1.0.1 } - hci: { git: "https://github.com/pulp-platform/hci.git", version: 1.0.8 } + hci: { git: "https://github.com/pulp-platform/hci.git", rev: b2e6f391aa6c10c03f45b693d80a0aaddecf169b } # branch: master register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 6e10650b50c7b40f7f81602acf61526330c4d69d} # branch: yt/hmr - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: c7478dafc96ccfef9dbb5f2b246371d42e9cae19 } # branch: power-management + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 3797413e5f190c2a86185ab6d8b12af365051b1e } # branch: carfield export_include_dirs: - include From 62ee8628cdc3371f70f78e3fd7abc83083745fcb Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 1 Jun 2023 20:14:19 +0200 Subject: [PATCH 035/207] Turning core_id from parameter to input. --- rtl/core_region.sv | 13 +++++-------- rtl/pulp_cluster.sv | 4 ++-- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 95712f95..7b2fb15e 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -27,11 +27,8 @@ module core_region #( // CORE PARAMETERS parameter CORE_TYPE_CL = 0, // 0 for CV32, 1 RI5CY, 2 for IBEX RV32IMC - // parameter USE_FPU = 1, - // parameter USE_HWPE = 1, parameter N_EXT_PERF_COUNTERS = 1, parameter NUM_INTERRUPTS = 32, - parameter CORE_ID = 0, parameter ADDR_WIDTH = 32, parameter DATA_WIDTH = 32, parameter INSTR_RDATA_WIDTH = 32, @@ -63,6 +60,7 @@ module core_region input logic rst_ni, input logic setback_i, + input logic [3:0] core_id_i, input logic [5:0] cluster_id_i, input logic irq_req_i, @@ -148,7 +146,7 @@ module core_region logic core_data_req_we ; assign core_data_req_o.wen = ~core_data_req_we; - assign hart_id = {21'b0, cluster_id_i[5:0], 1'b0, CORE_ID[3:0]}; + assign hart_id = {21'b0, cluster_id_i[5:0], 1'b0, core_id_i}; //******************************************************** //***************** PROCESSOR **************************** @@ -244,17 +242,16 @@ module core_region .Zfinx ( 0 ), .WAPUTYPE ( WAPUTYPE ), .DM_HaltAddress ( DEBUG_START_ADDR + 16'h0800 ) - ) RI5CY_CORE ( + ) RI5CY_CORE ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .setback_i ( setback_i ), .clock_en_i ( clock_en_i ), .test_en_i ( test_mode_i ), - // .setback_i ( '0 ), // Useful for HMR // Control Interface .fregfile_disable_i ( '1 ), .boot_addr_i ( boot_addr ), - .core_id_i ( hart_id[3:0] ), + .core_id_i ( core_id_i ), .cluster_id_i ( cluster_id_i ), // Instruction Interface .instr_req_o ( instr_req_o ), @@ -471,7 +468,7 @@ module core_region initial begin - FILE_ID.itoa(CORE_ID); + FILE_ID.itoa(core_id_i); FILENAME = {"FETCH_CORE_", FILE_ID, ".log" }; FILE=$fopen(FILENAME,"w"); end diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 9b780433..8e2d837e 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -873,7 +873,6 @@ generate core_region #( .CORE_TYPE_CL ( CORE_TYPE_CL ), .N_EXT_PERF_COUNTERS ( 5 ), - .CORE_ID ( i ), .ADDR_WIDTH ( 32 ), .DATA_WIDTH ( 32 ), .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), @@ -897,6 +896,7 @@ generate .rst_ni ( rst_ni ), .setback_i ( setback[i] ), .cluster_id_i ( hmr2core[i].cluster_id ), + .core_id_i ( hmr2core[i].core_id ), .clock_en_i ( hmr2core[i].clock_en ), .fetch_en_i ( fetch_en_int[i] ), .boot_addr_i ( hmr2core[i].boot_addr ), @@ -938,7 +938,7 @@ generate // Binding inputs/outputs from HMR to the system and vice versa assign sys2hmr[i].clock_en = clk_core_en[i]; assign sys2hmr[i].boot_addr = boot_addr; - assign sys2hmr[i].core_id = '0; // FIXME + assign sys2hmr[i].core_id = i[3:0]; assign sys2hmr[i].cluster_id = cluster_id_i; assign sys2hmr[i].instr_gnt = instr_gnt[i]; assign sys2hmr[i].instr_rvalid = instr_r_valid[i]; From bd8182aaa33f2b0ac7bf924621f094a382d8ab17 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 1 Jun 2023 20:34:09 +0200 Subject: [PATCH 036/207] Bumped number of cores to 12 and updated pulp-runtime commit. --- Makefile | 2 +- include/pulp_soc_defines.sv | 2 +- wave.do | 2801 +++++++++++++++++++++++++++++++---- 3 files changed, 2493 insertions(+), 312 deletions(-) diff --git a/Makefile b/Makefile index 51b50a5f..fa311c7d 100644 --- a/Makefile +++ b/Makefile @@ -74,7 +74,7 @@ Bender.lock: ## Clone pulp-runtime as SW stack pulp-runtime: - git clone https://github.com/pulp-platform/pulp-runtime.git -b lv/pulp_cluster $@ + git clone https://github.com/pulp-platform/pulp-runtime.git -b yt/carfield $@ ## Clone regression tests for bare-metal verification regression-tests: diff --git a/include/pulp_soc_defines.sv b/include/pulp_soc_defines.sv index 5307196e..54307677 100644 --- a/include/pulp_soc_defines.sv +++ b/include/pulp_soc_defines.sv @@ -47,7 +47,7 @@ //PARAMETRES `define NB_CLUSTERS 1 -`define NB_CORES 8 +`define NB_CORES 12 `define NB_DMAS 4 `define NB_MPERIPHS 1 `define NB_SPERIPHS 10 diff --git a/wave.do b/wave.do index c54e4dca..3e1541b4 100644 --- a/wave.do +++ b/wave.do @@ -295,313 +295,6 @@ add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_config_ add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_config_hw2reg add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_incr_mismatches add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_incr_mismatches -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/clk_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/rst_ni} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/cluster_id_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_req_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_ack_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_id_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_ack_id_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/clock_en_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/fetch_en_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/boot_addr_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/test_mode_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_busy_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_req_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_addr_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_req_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_havereset_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_running_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_halted_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/ext_perf_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_req_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_rsp_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_req_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_gnt_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_type_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_operands_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_op_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_flags_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_ready_o} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_valid_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_result_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_flags_i} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/hart_id} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_sleep} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/boot_addr} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_irq_x} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_req} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_gnt} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_addr} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_r_rdata} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_r_valid} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_mem_req} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_req} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_we} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_be} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_addr} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_wdata} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_atop} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/FILE} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_L2} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_ROM} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_ROM} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_ROM} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_L2} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_L2} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/destination} -add wave -noupdate -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/reg_cache_refill} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} -add wave -noupdate -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/clk} add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/rst_ni} add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_req_i} @@ -802,9 +495,2497 @@ add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/out_valid add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/out_ready add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/busy +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/clk_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/rst_ni} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/setback_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_id_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/cluster_id_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_req_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_ack_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_id_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_ack_id_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/clock_en_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/fetch_en_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/boot_addr_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/test_mode_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_busy_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_req_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_addr_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_req_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_havereset_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_running_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_halted_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/ext_perf_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_req_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_rsp_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_req_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_type_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_operands_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_op_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_flags_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_ready_o} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_valid_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_result_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_flags_i} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/hart_id} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_sleep} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/boot_addr} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_irq_x} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_req} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_gnt} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_addr} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_r_valid} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_mem_req} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_req} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_we} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_be} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_addr} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_wdata} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_atop} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_req_we} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/FILE} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_L2} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/destination} +add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/reg_cache_refill} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/clk_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/rst_ni} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/setback_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_id_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/cluster_id_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_req_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_ack_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_id_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_ack_id_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/clock_en_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/fetch_en_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/boot_addr_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/test_mode_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_busy_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_req_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_gnt_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_addr_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_valid_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_req_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_havereset_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_running_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_halted_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/ext_perf_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_req_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_rsp_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_req_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_type_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_operands_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_op_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_flags_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_ready_o} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_valid_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_result_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_flags_i} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/hart_id} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_sleep} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/boot_addr} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_irq_x} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_req} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_gnt} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_addr} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_r_valid} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_mem_req} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_shadow_req} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_shadow_we} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_shadow_be} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_shadow_addr} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_shadow_wdata} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_atop} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_req_we} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/FILE} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_gnt_L2} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/destination} +add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/reg_cache_refill} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/clk_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/rst_ni} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/setback_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_id_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/cluster_id_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_req_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_ack_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_id_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_ack_id_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/clock_en_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/fetch_en_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/boot_addr_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/test_mode_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_busy_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_req_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_gnt_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_addr_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_valid_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_req_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_havereset_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_running_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_halted_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/ext_perf_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_req_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_rsp_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_req_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_type_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_operands_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_op_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_flags_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_ready_o} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_valid_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_result_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_flags_i} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/hart_id} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_sleep} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/boot_addr} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_irq_x} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_req} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_gnt} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_addr} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_r_valid} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_mem_req} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_shadow_req} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_shadow_we} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_shadow_be} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_shadow_addr} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_shadow_wdata} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_atop} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_req_we} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/FILE} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_gnt_L2} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/destination} +add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/reg_cache_refill} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/clk_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/rst_ni} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/setback_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_id_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/cluster_id_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_req_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_ack_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_id_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_ack_id_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/clock_en_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/fetch_en_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/boot_addr_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/test_mode_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_busy_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_req_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_gnt_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_addr_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_valid_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_req_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_havereset_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_running_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_halted_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/ext_perf_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_req_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_rsp_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_req_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_type_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_operands_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_op_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_flags_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_ready_o} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_valid_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_result_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_flags_i} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/hart_id} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_sleep} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/boot_addr} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_irq_x} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_req} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_gnt} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_addr} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_r_valid} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_mem_req} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_shadow_req} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_shadow_we} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_shadow_be} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_shadow_addr} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_shadow_wdata} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_atop} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_req_we} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/FILE} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_gnt_L2} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/destination} +add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/reg_cache_refill} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/clk_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/rst_ni} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/setback_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_id_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/cluster_id_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/irq_req_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/irq_ack_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/irq_id_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/irq_ack_id_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/clock_en_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/fetch_en_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/boot_addr_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/test_mode_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_busy_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_req_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_gnt_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_addr_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_r_valid_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/debug_req_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/debug_havereset_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/debug_running_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/debug_halted_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/ext_perf_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_data_req_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_data_rsp_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_req_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_type_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_operands_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_op_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_flags_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_ready_o} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_valid_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_result_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_flags_i} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/hart_id} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_sleep} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/boot_addr} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_irq_x} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_instr_req} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_instr_gnt} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_instr_addr} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_instr_r_valid} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_mem_req} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_shadow_req} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_shadow_we} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_shadow_be} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_shadow_addr} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_shadow_wdata} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_data_atop} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_data_req_we} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/FILE} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_gnt_L2} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/destination} +add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/reg_cache_refill} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/clk_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/rst_ni} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/setback_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_id_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/cluster_id_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/irq_req_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/irq_ack_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/irq_id_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/irq_ack_id_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/clock_en_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/fetch_en_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/boot_addr_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/test_mode_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_busy_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_req_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_gnt_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_addr_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_r_valid_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/debug_req_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/debug_havereset_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/debug_running_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/debug_halted_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/ext_perf_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_data_req_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_data_rsp_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_req_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_type_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_operands_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_op_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_flags_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_ready_o} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_valid_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_result_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_flags_i} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/hart_id} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_sleep} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/boot_addr} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_irq_x} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_instr_req} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_instr_gnt} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_instr_addr} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_instr_r_valid} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_mem_req} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_shadow_req} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_shadow_we} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_shadow_be} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_shadow_addr} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_shadow_wdata} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_data_atop} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_data_req_we} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/FILE} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_gnt_L2} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/destination} +add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/reg_cache_refill} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/clk_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/rst_ni} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/setback_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_id_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/cluster_id_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/irq_req_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/irq_ack_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/irq_id_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/irq_ack_id_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/clock_en_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/fetch_en_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/boot_addr_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/test_mode_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_busy_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_req_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_gnt_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_addr_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_r_valid_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/debug_req_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/debug_havereset_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/debug_running_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/debug_halted_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/ext_perf_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_data_req_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_data_rsp_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_req_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_type_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_operands_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_op_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_flags_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_ready_o} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_valid_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_result_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_flags_i} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/hart_id} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_sleep} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/boot_addr} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_irq_x} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_instr_req} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_instr_gnt} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_instr_addr} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_instr_r_valid} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_mem_req} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_shadow_req} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_shadow_we} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_shadow_be} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_shadow_addr} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_shadow_wdata} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_data_atop} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_data_req_we} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/FILE} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_gnt_L2} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/destination} +add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/reg_cache_refill} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/clk_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/rst_ni} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/setback_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_id_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/cluster_id_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/irq_req_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/irq_ack_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/irq_id_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/irq_ack_id_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/clock_en_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/fetch_en_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/boot_addr_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/test_mode_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_busy_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_req_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_gnt_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_addr_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_r_valid_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/debug_req_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/debug_havereset_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/debug_running_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/debug_halted_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/ext_perf_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_data_req_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_data_rsp_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_req_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_type_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_operands_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_op_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_flags_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_ready_o} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_valid_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_result_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_flags_i} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/hart_id} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_sleep} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/boot_addr} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_irq_x} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_instr_req} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_instr_gnt} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_instr_addr} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_instr_r_valid} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_mem_req} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_shadow_req} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_shadow_we} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_shadow_be} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_shadow_addr} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_shadow_wdata} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_data_atop} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_data_req_we} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/FILE} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_gnt_L2} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/destination} +add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/reg_cache_refill} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {112525599521 ps} 0} {{Cursor 2} {67278742839 ps} 0} {{Cursor 3} {323044715583 ps} 0} -quietly wave cursor active 1 +WaveRestoreCursors {{Cursor 1} {112525599521 ps} 0} {{Cursor 2} {89136000000 ps} 0} {{Cursor 3} {222455730424 ps} 0} +quietly wave cursor active 3 configure wave -namecolwidth 211 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -819,4 +3000,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ps} {339486 us} +WaveRestoreZoom {305197047167 ps} {305528576465 ps} From 05da344fe540c2a4317f64ac1ad971c432bc3a6e Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 7 Jun 2023 11:41:38 +0200 Subject: [PATCH 037/207] Fixed unused and unconnected buses. --- rtl/core_region.sv | 51 +++++++++++++++++++-------------------------- rtl/pulp_cluster.sv | 10 ++++++++- 2 files changed, 31 insertions(+), 30 deletions(-) diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 7b2fb15e..8fccc549 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -136,13 +136,6 @@ module core_region logic core_mem_req; - // Shadow registers - logic core_shadow_req ; - logic core_shadow_we ; - logic [3:0] core_shadow_be ; - logic [31:0] core_shadow_addr ; - logic [31:0] core_shadow_wdata; - logic [5:0] core_data_atop ; logic core_data_req_we ; assign core_data_req_o.wen = ~core_data_req_we; @@ -182,25 +175,25 @@ module core_region .instr_addr_o ( instr_addr_o ), .instr_rdata_i ( instr_r_rdata_i ), // Data Interface - .data_req_o ( core_data_req_o.req ), - .data_gnt_i ( core_data_rsp_i.gnt ), - .data_rvalid_i ( core_data_rsp_i.r_valid ), - .data_we_o ( core_data_req_we ), - .data_be_o ( core_data_req_o.be ), - .data_addr_o ( core_data_req_o.add ), - .data_wdata_o ( core_data_req_o.data ), - .data_rdata_i ( core_data_rsp_i.r_data ), + .data_req_o ( core_data_req_o.req ), + .data_gnt_i ( core_data_rsp_i.gnt ), + .data_rvalid_i ( core_data_rsp_i.r_valid ), + .data_we_o ( core_data_req_we ), + .data_be_o ( core_data_req_o.be ), + .data_addr_o ( core_data_req_o.add ), + .data_wdata_o ( core_data_req_o.data ), + .data_rdata_i ( core_data_rsp_i.r_data ), // Shadow Memory Interface - .shadow_req_o ( sadow_req ), + .shadow_req_o ( /* Unconnected */ ), .shadow_gnt_i ( '0 ), .shadow_rvalid_i ( '0 ), - .shadow_we_o ( core_shadow_we ), - .shadow_be_o ( core_shadow_be ), - .shadow_addr_o ( core_shadow_addr ), - .shadow_wdata_o ( core_shadow_wdata ), + .shadow_we_o ( /* Unconnected */ ), + .shadow_be_o ( /* Unconnected */ ), + .shadow_addr_o ( /* Unconnected */ ), + .shadow_wdata_o ( /* Unconnected */ ), .shadow_rdata_i ( '0 ), // Atomic operation - .data_atop_o ( core_data_atop ), + .data_atop_o ( /* Unconnected */ ), // apu-interconnect // Handshake .apu_req_o ( apu_master_req_o ), @@ -260,14 +253,14 @@ module core_region .instr_addr_o ( instr_addr_o ), .instr_rdata_i ( instr_r_rdata_i ), // Data Interface - .data_req_o ( core_data_req_o.req ), - .data_gnt_i ( core_data_rsp_i.gnt ), - .data_rvalid_i ( core_data_rsp_i.r_valid ), - .data_we_o ( core_data_req_we ), - .data_be_o ( core_data_req_o.be ), - .data_addr_o ( core_data_req_o.add ), - .data_wdata_o ( core_data_req_o.data ), - .data_rdata_i ( core_data_rsp_i.r_data ), + .data_req_o ( core_data_req_o.req ), + .data_gnt_i ( core_data_rsp_i.gnt ), + .data_rvalid_i ( core_data_rsp_i.r_valid ), + .data_we_o ( core_data_req_we ), + .data_be_o ( core_data_req_o.be ), + .data_addr_o ( core_data_req_o.add ), + .data_wdata_o ( core_data_req_o.data ), + .data_rdata_i ( core_data_rsp_i.r_data ), .data_unaligned_o ( /* Unused */ ), // apu-interconnect // Handshake diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 8e2d837e..367d3238 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -369,7 +369,7 @@ XBAR_TCDM_BUS s_mperiph_xbar_bus[NB_MPERIPHS-1:0](); // periph demux XBAR_TCDM_BUS s_mperiph_bus(); -XBAR_TCDM_BUS s_mperiph_demux_bus[1:0](); +XBAR_TCDM_BUS s_mperiph_demux_bus[1:0](); // bus 1 is no longer in use. // cores & accelerators -> log interconnect hci_core_intf #( @@ -597,6 +597,12 @@ per_demux_wrap #( `TCDM_ASSIGN_MASTER (s_mperiph_xbar_bus[NB_MPERIPHS-1], s_mperiph_demux_bus[0]) +/* Binding of unused bus */ +assign s_mperiph_demux_bus[1].gnt = '0; +assign s_mperiph_demux_bus[1].r_rdata = '0; +assign s_mperiph_demux_bus[1].r_opc = '0; +assign s_mperiph_demux_bus[1].r_valid = '0; + per2axi_wrap #( .NB_CORES ( NB_CORES ), .PER_ADDR_WIDTH ( 32 ), @@ -1144,6 +1150,7 @@ generate assign s_hwpe_cfg_bus.gnt = '1; assign s_hwpe_cfg_bus.r_rdata = 32'hdeadbeef; assign s_hwpe_cfg_bus.r_id = '0; + assign s_hwpe_cfg_bus.r_opc = '0; assign s_hci_hwpe[0].req = 1'b0; assign s_hci_hwpe[0].add = '0; assign s_hci_hwpe[0].wen = '0; @@ -1151,6 +1158,7 @@ generate assign s_hci_hwpe[0].be = '0; assign s_hci_hwpe[0].boffs = '0; assign s_hci_hwpe[0].lrdy = '1; + assign s_hci_hwpe[0].user = '0; assign s_hwpe_busy = '0; assign s_hwpe_evt = '0; end From 9338c3722bb2dec4d9aa8e857def19f0a5aa7507 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 21 Jun 2023 23:49:38 +0200 Subject: [PATCH 038/207] Parametrized internal address map and propagated it to the XBAR PE. --- Bender.lock | 2 +- Bender.yml | 2 +- rtl/cluster_bus_wrap.sv | 30 +++++++------- rtl/cluster_interconnect_wrap.sv | 28 ++++++++----- rtl/core_region.sv | 2 +- rtl/pulp_cluster.sv | 67 ++++++++++++++++++-------------- rtl/xbar_pe_wrap.sv | 21 ++++++++-- 7 files changed, 93 insertions(+), 59 deletions(-) diff --git a/Bender.lock b/Bender.lock index 6c0fb30d..697d3558 100644 --- a/Bender.lock +++ b/Bender.lock @@ -224,7 +224,7 @@ packages: - common_cells - common_verification riscv: - revision: 4ceb402db8619718a9170058bb31f75fcdf7ed1c + revision: 4ef49607a0093378d3f6dccce2e673178d6481af version: null source: Git: git@github.com:AlSaqr-platform/riscv_nn.git diff --git a/Bender.yml b/Bender.yml index ac9e7bcb..fdf01a07 100644 --- a/Bender.yml +++ b/Bender.yml @@ -27,7 +27,7 @@ dependencies: timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 4ceb402db8619718a9170058bb31f75fcdf7ed1c } # branch: yt/hmr + riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 4ef49607a0093378d3f6dccce2e673178d6481af } # branch: yt/hmr cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: 9b77611 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index b7150fa9..0cafebda 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -23,17 +23,19 @@ module cluster_bus_wrap import axi_pkg::xbar_cfg_t; #( - parameter int unsigned NB_MASTER = 3 , - parameter int unsigned NB_SLAVE = 4 , - parameter int unsigned NB_CORES = 4 , - parameter int unsigned AXI_ADDR_WIDTH = 32, - parameter int unsigned AXI_DATA_WIDTH = 64, - parameter int unsigned AXI_ID_IN_WIDTH = 4 , - parameter int unsigned AXI_ID_OUT_WIDTH = 6 , - parameter int unsigned AXI_USER_WIDTH = 6 , - parameter int unsigned DMA_NB_OUTSND_BURSTS = 8 , - parameter int unsigned TCDM_SIZE = 0 , - parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h10000000 + parameter int unsigned NB_MASTER = 3 , + parameter int unsigned NB_SLAVE = 4 , + parameter int unsigned NB_CORES = 4 , + parameter int unsigned AXI_ADDR_WIDTH = 32 , + parameter int unsigned AXI_DATA_WIDTH = 64 , + parameter int unsigned AXI_ID_IN_WIDTH = 4 , + parameter int unsigned AXI_ID_OUT_WIDTH = 6 , + parameter int unsigned AXI_USER_WIDTH = 6 , + parameter int unsigned DMA_NB_OUTSND_BURSTS = 8 , + parameter int unsigned TCDM_SIZE = 0 , + parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h10000000, + parameter logic [AXI_ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, + parameter logic [AXI_ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000 )( input logic clk_i, input logic rst_ni, @@ -111,12 +113,12 @@ module cluster_bus_wrap }; assign addr_map[1] = '{ // Peripherals idx: 1, - start_addr: cluster_base_addr + 32'h0020_0000, - end_addr: cluster_base_addr + 32'h0040_0000 + start_addr: cluster_base_addr + ClusterPeripheralsOffs, + end_addr: cluster_base_addr + ClusterExternalOffs }; assign addr_map[2] = '{ // everything above cluster to ext_slave idx: 2, - start_addr: cluster_base_addr + 32'h0040_0000, + start_addr: cluster_base_addr + ClusterExternalOffs, end_addr: 32'hFFFF_FFFF }; diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index 07fd047c..5ad6a46c 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -30,6 +30,9 @@ module cluster_interconnect_wrap parameter DATA_WIDTH = 32, parameter ADDR_WIDTH = 32, parameter BE_WIDTH = DATA_WIDTH/8, + parameter logic [ADDR_WIDTH-1:0] ClusterBaseAddr = 'h10000000, + parameter logic [ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, + parameter logic [ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000, //TCDM PARAMETERS parameter TEST_SET_BIT = 20, @@ -45,6 +48,7 @@ module cluster_interconnect_wrap ( input logic clk_i, input logic rst_ni, + input logic [5:0] cluster_id_i, hci_core_intf.slave core_tcdm_slave [NB_CORES-1:0], hci_core_intf.slave hwpe_tcdm_slave [0:0], XBAR_PERIPH_BUS.Slave core_periph_slave[NB_CORES-1:0], @@ -165,21 +169,25 @@ module cluster_interconnect_wrap //******************************************************** xbar_pe_wrap #( - .NB_CORES ( NB_CORES ), - .NB_MPERIPHS ( NB_MPERIPHS ), - .NB_SPERIPHS ( NB_SPERIPHS ), - .ADDR_WIDTH ( ADDR_WIDTH ), - .DATA_WIDTH ( DATA_WIDTH ), - .BE_WIDTH ( BE_WIDTH ), - .PE_ROUTING_LSB ( PE_ROUTING_LSB ), - .PE_ROUTING_MSB ( PE_ROUTING_MSB ), - .CLUSTER_ALIAS ( CLUSTER_ALIAS ), - .CLUSTER_ALIAS_BASE ( CLUSTER_ALIAS_BASE ) + .NB_CORES ( NB_CORES ), + .NB_MPERIPHS ( NB_MPERIPHS ), + .NB_SPERIPHS ( NB_SPERIPHS ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .BE_WIDTH ( BE_WIDTH ), + .PE_ROUTING_LSB ( PE_ROUTING_LSB ), + .PE_ROUTING_MSB ( PE_ROUTING_MSB ), + .CLUSTER_ALIAS ( CLUSTER_ALIAS ), + .CLUSTER_ALIAS_BASE ( CLUSTER_ALIAS_BASE ), + .ClusterBaseAddr ( ClusterBaseAddr ), + .ClusterPeripheralsOffs ( ClusterPeripheralsOffs ), + .ClusterExternalOffs ( ClusterExternalOffs ) ) xbar_pe_inst ( .clk_i ( clk_i ), .rst_ni ( rst_ni), + .cluster_id_i ( cluster_id_i ), .core_periph_slave( core_periph_slave), .speriph_master ( speriph_master ), .mperiph_slave ( mperiph_slave ) diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 8fccc549..63365ef4 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -244,7 +244,7 @@ module core_region // Control Interface .fregfile_disable_i ( '1 ), .boot_addr_i ( boot_addr ), - .core_id_i ( core_id_i ), + .core_id_i ( hart_id ), .cluster_id_i ( cluster_id_i ), // Instruction Interface .instr_req_o ( instr_req_o ), diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 367d3238..0aadd2fe 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -87,6 +87,8 @@ module pulp_cluster parameter DC_SLICE_BUFFER_WIDTH = 8, parameter LOG_DEPTH = 3, parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h10000000, + parameter logic [AXI_ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, + parameter logic [AXI_ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000, // CLUSTER TO SOC CDC AXI PARAMETER localparam S2C_AW_WIDTH = axi_pkg::aw_width(AXI_ADDR_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), localparam S2C_W_WIDTH = axi_pkg::w_width(AXI_DATA_S2C_WIDTH,AXI_USER_WIDTH), @@ -149,6 +151,7 @@ module pulp_cluster input logic [3:0] base_addr_i, + input logic [31:0] boot_addr_i, input logic test_mode_i, @@ -531,17 +534,19 @@ assign fetch_en_int = fetch_enable_reg_int; /* cluster bus and attached peripherals */ cluster_bus_wrap #( - .NB_MASTER ( NumAxiMst ), - .NB_SLAVE ( NumAxiSlv ), - .NB_CORES ( NB_CORES ), - .DMA_NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), - .TCDM_SIZE ( TCDM_SIZE ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_IN_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_ID_OUT_WIDTH ( AXI_ID_OUT_WIDTH ), - .BaseAddr ( BaseAddr ) + .NB_MASTER ( NumAxiMst ), + .NB_SLAVE ( NumAxiSlv ), + .NB_CORES ( NB_CORES ), + .DMA_NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), + .TCDM_SIZE ( TCDM_SIZE ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_ID_IN_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_ID_OUT_WIDTH ( AXI_ID_OUT_WIDTH ), + .BaseAddr ( BaseAddr ), + .ClusterPeripheralsOffs ( ClusterPeripheralsOffs ), + .ClusterExternalOffs ( ClusterExternalOffs ) ) cluster_bus_wrap_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -625,29 +630,33 @@ per2axi_wrap #( //*************************************************** cluster_interconnect_wrap #( - .NB_CORES ( NB_CORES ), - .HWPE_PRESENT ( HWPE_PRESENT ), - .NB_HWPE_PORTS ( NB_HWPE_PORTS ), - .NB_DMAS ( NB_DMAS ), - .NB_MPERIPHS ( NB_MPERIPHS ), - .NB_TCDM_BANKS ( NB_TCDM_BANKS ), - .NB_SPERIPHS ( NB_SPERIPHS ), - - .DATA_WIDTH ( DATA_WIDTH ), - .ADDR_WIDTH ( ADDR_WIDTH ), - .BE_WIDTH ( BE_WIDTH ), - - .TEST_SET_BIT ( TEST_SET_BIT ), - .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH ), - - .LOG_CLUSTER ( LOG_CLUSTER ), - .PE_ROUTING_LSB ( PE_ROUTING_LSB ), - .CLUSTER_ALIAS ( CLUSTER_ALIAS ), + .NB_CORES ( NB_CORES ), + .HWPE_PRESENT ( HWPE_PRESENT ), + .NB_HWPE_PORTS ( NB_HWPE_PORTS ), + .NB_DMAS ( NB_DMAS ), + .NB_MPERIPHS ( NB_MPERIPHS ), + .NB_TCDM_BANKS ( NB_TCDM_BANKS ), + .NB_SPERIPHS ( NB_SPERIPHS ), + + .DATA_WIDTH ( DATA_WIDTH ), + .ADDR_WIDTH ( ADDR_WIDTH ), + .BE_WIDTH ( BE_WIDTH ), + .ClusterBaseAddr ( BaseAddr ), + .ClusterPeripheralsOffs ( ClusterPeripheralsOffs ), + .ClusterExternalOffs ( ClusterExternalOffs ), + + .TEST_SET_BIT ( TEST_SET_BIT ), + .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH ), + + .LOG_CLUSTER ( LOG_CLUSTER ), + .PE_ROUTING_LSB ( PE_ROUTING_LSB ), + .CLUSTER_ALIAS ( CLUSTER_ALIAS ), .USE_HETEROGENEOUS_INTERCONNECT ( USE_HETEROGENEOUS_INTERCONNECT ) ) cluster_interconnect_wrap_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), + .cluster_id_i ( cluster_id_i ), .core_tcdm_slave ( s_hci_core ), .hwpe_tcdm_slave ( s_hci_hwpe ), diff --git a/rtl/xbar_pe_wrap.sv b/rtl/xbar_pe_wrap.sv index 6d09a02b..445eb472 100644 --- a/rtl/xbar_pe_wrap.sv +++ b/rtl/xbar_pe_wrap.sv @@ -37,17 +37,28 @@ module xbar_pe_wrap parameter bit HWPE_PRESENT = 1'b1, parameter CLUSTER_ALIAS = 1, parameter CLUSTER_ALIAS_BASE = 12'h000, - parameter ADDREXT = 1'b0 + parameter ADDREXT = 1'b0, + parameter logic [ADDR_WIDTH-1:0] ClusterBaseAddr = 'h10000000, + parameter logic [ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, + parameter logic [ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000 ) ( input logic clk_i, input logic rst_ni, + input logic [5:0] cluster_id_i, XBAR_PERIPH_BUS.Slave core_periph_slave[NB_CORES-1:0], XBAR_PERIPH_BUS.Master speriph_master[NB_SPERIPHS-1:0], XBAR_TCDM_BUS.Slave mperiph_slave[NB_MPERIPHS-1:0] ); logic cluster_alias; + logic [ADDR_WIDTH-1:0] cluster_base_addr , + cluster_peripherals_base, + cluster_peripherals_end ; + + assign cluster_base_addr = ClusterBaseAddr + (cluster_id_i << 22); // same as in the cluster_bus_wrap + assign cluster_peripherals_base = cluster_base_addr + ClusterPeripheralsOffs; // same as in the cluster_bus_wrap + assign cluster_peripherals_end = cluster_base_addr + ClusterExternalOffs; // same as in the cluster_bus_wrap assign cluster_alias = (CLUSTER_ALIAS == 1) ? 1'b1 : 1'b0; @@ -88,11 +99,15 @@ module xbar_pe_wrap // if the access is to this cluster .. (addr[31:24] == 8'h10 || (cluster_alias && addr[31:24] == CLUSTER_ALIAS_BASE[11:4])) // .. and the peripherals - && (addr[23:20] >= 4'h2 && addr[23:20] <= 4'h3) + && (addr >= cluster_peripherals_base + && addr <= cluster_peripherals_end) ) begin // decode peripheral to access pe_idx = addr[PE_ROUTING_MSB:PE_ROUTING_LSB]; - if (addr[23:20] == 4'h2 && addr[19:PE_ROUTING_MSB+1] == '0 && pe_idx < NB_SPERIPHS) begin + if (addr[23:20] == cluster_peripherals_base && + addr[19:PE_ROUTING_MSB+1] == '0 && + pe_idx < NB_SPERIPHS) + begin if (pe_idx >= pulp_cluster_package::SPER_EVENT_U_ID && pe_idx < pulp_cluster_package::SPER_EVENT_U_ID + pulp_cluster_package::NB_SPERIPH_PLUGS_EU From 6542185b66a33817b94e5c4466a3e7aa882c12a1 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 23 Jun 2023 18:14:06 +0200 Subject: [PATCH 039/207] Fixed bug in XBAR PE. --- rtl/xbar_pe_wrap.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/xbar_pe_wrap.sv b/rtl/xbar_pe_wrap.sv index 445eb472..cf7f6c02 100644 --- a/rtl/xbar_pe_wrap.sv +++ b/rtl/xbar_pe_wrap.sv @@ -104,7 +104,7 @@ module xbar_pe_wrap ) begin // decode peripheral to access pe_idx = addr[PE_ROUTING_MSB:PE_ROUTING_LSB]; - if (addr[23:20] == cluster_peripherals_base && + if (addr[31:16] == cluster_peripherals_base[31:16] && addr[19:PE_ROUTING_MSB+1] == '0 && pe_idx < NB_SPERIPHS) begin From a746000f9dc9965e1351186905b59bca36edef57 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 26 Jun 2023 16:25:32 +0200 Subject: [PATCH 040/207] Bumped core, regression tests, runtime, and changed cluster ID. --- Bender.lock | 6 +- Bender.yml | 2 +- Makefile | 4 +- rtl/pulp_cluster.sv | 1 - rtl/xbar_pe_wrap.sv | 2 +- tb/pulp_cluster_tb.sv | 2 +- wave.do | 4181 ++++++++++++++++------------------------- 7 files changed, 1580 insertions(+), 2618 deletions(-) diff --git a/Bender.lock b/Bender.lock index 697d3558..19091dd7 100644 --- a/Bender.lock +++ b/Bender.lock @@ -60,8 +60,8 @@ packages: dependencies: - hci common_cells: - revision: 4ac82b420e46fd0005513ca2283cb3c905e7599a - version: 1.29.0 + revision: 0989ff73d0315922791bf42137c0ce0cbb4a76ca + version: 1.30.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -224,7 +224,7 @@ packages: - common_cells - common_verification riscv: - revision: 4ef49607a0093378d3f6dccce2e673178d6481af + revision: 4eac53237c6d0062715d17016fe95462eb81ebc3 version: null source: Git: git@github.com:AlSaqr-platform/riscv_nn.git diff --git a/Bender.yml b/Bender.yml index fdf01a07..94c05463 100644 --- a/Bender.yml +++ b/Bender.yml @@ -27,7 +27,7 @@ dependencies: timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 4ef49607a0093378d3f6dccce2e673178d6481af } # branch: yt/hmr + riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 4eac53237c6d0062715d17016fe95462eb81ebc3 } # branch: yt/hmr cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: 9b77611 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating diff --git a/Makefile b/Makefile index fa311c7d..9daa70aa 100644 --- a/Makefile +++ b/Makefile @@ -74,11 +74,11 @@ Bender.lock: ## Clone pulp-runtime as SW stack pulp-runtime: - git clone https://github.com/pulp-platform/pulp-runtime.git -b yt/carfield $@ + git clone git@github.com:pulp-platform/pulp-runtime.git -b yt/carfield $@ ## Clone regression tests for bare-metal verification regression-tests: - git clone https://github.com/pulp-platform/regression_tests $@ + git clone git@github.com:pulp-platform/regression_tests.git -b yt/carfield $@ ######################## # Build and simulation # diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 0aadd2fe..25e43a93 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -151,7 +151,6 @@ module pulp_cluster input logic [3:0] base_addr_i, - input logic [31:0] boot_addr_i, input logic test_mode_i, diff --git a/rtl/xbar_pe_wrap.sv b/rtl/xbar_pe_wrap.sv index cf7f6c02..89a9c4cd 100644 --- a/rtl/xbar_pe_wrap.sv +++ b/rtl/xbar_pe_wrap.sv @@ -104,7 +104,7 @@ module xbar_pe_wrap ) begin // decode peripheral to access pe_idx = addr[PE_ROUTING_MSB:PE_ROUTING_LSB]; - if (addr[31:16] == cluster_peripherals_base[31:16] && + if (addr[31:20] == cluster_peripherals_base[31:20] && addr[19:PE_ROUTING_MSB+1] == '0 && pe_idx < NB_SPERIPHS) begin diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 91a19077..4e251060 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -325,7 +325,7 @@ module pulp_cluster_tb; .fetch_en_i ( s_cluster_fetch_en ), .eoc_o ( s_cluster_eoc ), .busy_o ( s_cluster_busy ), - .cluster_id_i ( 6'b000000 ), + .cluster_id_i ( 6'b000001 ), .async_data_master_aw_wptr_o ( async_cluster_to_soc_axi_bus.aw_wptr ), .async_data_master_aw_rptr_i ( async_cluster_to_soc_axi_bus.aw_rptr ), diff --git a/wave.do b/wave.do index 3e1541b4..77679d61 100644 --- a/wave.do +++ b/wave.do @@ -147,93 +147,6 @@ add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dst_req add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/isolate_dst_req add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/dst_resp add wave -noupdate -group cluster /pulp_cluster_tb/cluster_i/isolate_dst_resp -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/clk} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/rst_ni} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/test_en_i} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/base_addr_i} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_req_i} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_i} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wen_i} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wdata_i} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_be_i} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_gnt_o} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_valid_o} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_rdata_o} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_opc_o} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_req_o_SH} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_o_SH} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wen_o_SH} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wdata_o_SH} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_be_o_SH} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_gnt_i_SH} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_valid_i_SH} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_rdata_i_SH} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_req_o_EXT} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_o_EXT} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wen_o_EXT} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wdata_o_EXT} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_be_o_EXT} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_gnt_i_EXT} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_valid_i_EXT} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_rdata_i_EXT} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_opc_i_EXT} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_req_o_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_o_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wen_o_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wdata_o_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_be_o_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_gnt_i_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_valid_i_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_opc_i_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_rdata_i_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/perf_l2_ld_o} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/perf_l2_st_o} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/perf_l2_ld_cyc_o} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/perf_l2_st_cyc_o} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/CLUSTER_ID} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/CLUSTER_ALIAS_BASE_11} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/CLUSTER_ALIAS_BASE_12} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_req_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_gnt_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_r_data_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_r_valid_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_r_opc_PE} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_r_data_PE_0} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_r_valid_PE_0} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/s_data_r_opc_PE_0} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/CS} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/NS} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_req_to_L2} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_to_L2} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wen_to_L2} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wdata_to_L2} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_be_to_L2} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_gnt_from_L2} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/request_destination} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/destination} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_int} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_busy_PE_fifo} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_req_PE_fifo} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_add_PE_fifo} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wen_PE_fifo} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_wdata_PE_fifo} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_be_PE_fifo} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_gnt_PE_fifo} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_valid_PE_fifo} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_opc_PE_fifo} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/data_r_rdata_PE_fifo} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/TCDM_RW} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/TCDM_TS} -add wave -noupdate -group data_periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/data_periph_demux_i/DEM_PER} -add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/clk_i} -add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/rst_ni} -add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/test_en_i} -add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/clk_en_i} -add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/base_addr_i} -add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/cluster_id_i} -add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/ext_perf_o} -add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/core_data_req_i} -add wave -noupdate -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/core_data_rsp_o} add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/clk_i add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/rst_ni add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/reg_request_i @@ -295,36 +208,6 @@ add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_config_ add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/core_config_hw2reg add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/tmr_incr_mismatches add wave -noupdate -group hmr /pulp_cluster_tb/cluster_i/i_hmr_unit/dmr_incr_mismatches -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/clk} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/rst_ni} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_req_i} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_add_i} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_wen_i} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_wdata_i} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_be_i} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_gnt_o} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_valid_o} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_rdata_o} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_opc_o} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_req_o_MH} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_add_o_MH} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_wen_o_MH} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_wdata_o_MH} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_be_o_MH} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_gnt_i_MH} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_valid_i_MH} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_rdata_i_MH} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_opc_i_MH} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_req_o_EU} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_add_o_EU} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_wen_o_EU} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_wdata_o_EU} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_be_o_EU} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_gnt_i_EU} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_valid_i_EU} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_rdata_i_EU} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/data_r_opc_i_EU} -add wave -noupdate -group periph_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/periph_demux_i/request_destination} add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/clk_i add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/rst_ni add wave -noupdate -group cluster_peripherals /pulp_cluster_tb/cluster_i/cluster_peripherals_i/ref_clk_i @@ -495,2498 +378,1578 @@ add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/out_valid add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/out_ready add wave -noupdate -group hwpe_subsystem -group redmule /pulp_cluster_tb/cluster_i/hwpe_gen/hwpe_subsystem_i/i_redmule/busy -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/clk_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/rst_ni} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/setback_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_id_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/cluster_id_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_req_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_ack_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_id_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_ack_id_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/clock_en_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/fetch_en_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/boot_addr_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/test_mode_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_busy_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_req_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_addr_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_req_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_havereset_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_running_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_halted_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/ext_perf_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_req_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_rsp_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_req_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_gnt_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_type_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_operands_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_op_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_flags_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_ready_o} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_valid_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_result_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_flags_i} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/hart_id} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_sleep} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/boot_addr} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_irq_x} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_req} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_gnt} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_addr} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_r_rdata} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_r_valid} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_mem_req} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_req} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_we} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_be} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_addr} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_shadow_wdata} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_atop} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_req_we} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/FILE} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_L2} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_ROM} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_ROM} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_ROM} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_L2} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_L2} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/destination} -add wave -noupdate -group core_region_0 {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/reg_cache_refill} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} -add wave -noupdate -group core_region_0 -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/clk_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/rst_ni} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/setback_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_id_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/cluster_id_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_req_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_ack_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_id_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_ack_id_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/clock_en_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/fetch_en_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/boot_addr_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/test_mode_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_busy_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_req_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_gnt_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_addr_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_rdata_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_valid_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_req_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_havereset_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_running_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_halted_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/ext_perf_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_req_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_rsp_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_req_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_gnt_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_type_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_operands_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_op_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_flags_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_ready_o} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_valid_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_result_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_flags_i} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/hart_id} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_sleep} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/boot_addr} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_irq_x} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_req} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_gnt} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_addr} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_r_rdata} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_r_valid} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_mem_req} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_shadow_req} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_shadow_we} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_shadow_be} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_shadow_addr} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_shadow_wdata} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_atop} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_req_we} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/FILE} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_gnt_L2} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_gnt_ROM} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_rdata_ROM} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_valid_ROM} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_rdata_L2} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_valid_L2} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/destination} -add wave -noupdate -group core_region_1 {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/reg_cache_refill} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} -add wave -noupdate -group core_region_1 -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/clk_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/rst_ni} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/setback_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_id_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/cluster_id_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_req_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_ack_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_id_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_ack_id_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/clock_en_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/fetch_en_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/boot_addr_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/test_mode_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_busy_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_req_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_gnt_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_addr_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_rdata_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_valid_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_req_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_havereset_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_running_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_halted_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/ext_perf_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_req_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_rsp_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_req_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_gnt_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_type_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_operands_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_op_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_flags_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_ready_o} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_valid_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_result_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_flags_i} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/hart_id} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_sleep} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/boot_addr} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_irq_x} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_req} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_gnt} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_addr} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_r_rdata} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_r_valid} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_mem_req} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_shadow_req} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_shadow_we} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_shadow_be} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_shadow_addr} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_shadow_wdata} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_atop} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_req_we} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/FILE} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_gnt_L2} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_gnt_ROM} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_rdata_ROM} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_valid_ROM} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_rdata_L2} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_valid_L2} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/destination} -add wave -noupdate -group core_region_2 {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/reg_cache_refill} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} -add wave -noupdate -group core_region_2 -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/clk_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/rst_ni} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/setback_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_id_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/cluster_id_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_req_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_ack_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_id_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_ack_id_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/clock_en_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/fetch_en_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/boot_addr_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/test_mode_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_busy_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_req_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_gnt_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_addr_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_rdata_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_valid_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_req_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_havereset_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_running_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_halted_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/ext_perf_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_req_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_rsp_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_req_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_gnt_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_type_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_operands_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_op_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_flags_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_ready_o} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_valid_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_result_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_flags_i} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/hart_id} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_sleep} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/boot_addr} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_irq_x} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_req} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_gnt} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_addr} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_r_rdata} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_r_valid} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_mem_req} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_shadow_req} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_shadow_we} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_shadow_be} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_shadow_addr} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_shadow_wdata} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_atop} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_req_we} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/FILE} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_gnt_L2} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_gnt_ROM} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_rdata_ROM} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_valid_ROM} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_rdata_L2} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_valid_L2} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/destination} -add wave -noupdate -group core_region_3 {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/reg_cache_refill} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} -add wave -noupdate -group core_region_3 -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/clk_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/rst_ni} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/setback_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_id_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/cluster_id_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/irq_req_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/irq_ack_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/irq_id_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/irq_ack_id_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/clock_en_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/fetch_en_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/boot_addr_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/test_mode_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_busy_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_req_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_gnt_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_addr_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_r_rdata_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_r_valid_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/debug_req_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/debug_havereset_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/debug_running_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/debug_halted_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/ext_perf_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_data_req_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_data_rsp_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_req_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_gnt_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_type_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_operands_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_op_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_flags_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_ready_o} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_valid_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_result_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/apu_master_flags_i} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/hart_id} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_sleep} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/boot_addr} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_irq_x} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_instr_req} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_instr_gnt} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_instr_addr} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_instr_r_rdata} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_instr_r_valid} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_mem_req} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_shadow_req} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_shadow_we} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_shadow_be} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_shadow_addr} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_shadow_wdata} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_data_atop} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/core_data_req_we} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/FILE} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_gnt_L2} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_gnt_ROM} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_r_rdata_ROM} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_r_valid_ROM} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_r_rdata_L2} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/instr_r_valid_L2} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/destination} -add wave -noupdate -group core_region_4 {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/reg_cache_refill} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} -add wave -noupdate -group core_region_4 -group core {/pulp_cluster_tb/cluster_i/CORE[4]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/clk_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/rst_ni} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/setback_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_id_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/cluster_id_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/irq_req_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/irq_ack_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/irq_id_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/irq_ack_id_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/clock_en_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/fetch_en_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/boot_addr_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/test_mode_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_busy_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_req_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_gnt_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_addr_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_r_rdata_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_r_valid_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/debug_req_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/debug_havereset_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/debug_running_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/debug_halted_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/ext_perf_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_data_req_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_data_rsp_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_req_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_gnt_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_type_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_operands_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_op_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_flags_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_ready_o} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_valid_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_result_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/apu_master_flags_i} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/hart_id} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_sleep} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/boot_addr} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_irq_x} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_instr_req} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_instr_gnt} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_instr_addr} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_instr_r_rdata} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_instr_r_valid} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_mem_req} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_shadow_req} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_shadow_we} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_shadow_be} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_shadow_addr} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_shadow_wdata} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_data_atop} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/core_data_req_we} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/FILE} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_gnt_L2} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_gnt_ROM} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_r_rdata_ROM} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_r_valid_ROM} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_r_rdata_L2} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/instr_r_valid_L2} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/destination} -add wave -noupdate -group core_region_5 {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/reg_cache_refill} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} -add wave -noupdate -group core_region_5 -group core {/pulp_cluster_tb/cluster_i/CORE[5]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/clk_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/rst_ni} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/setback_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_id_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/cluster_id_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/irq_req_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/irq_ack_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/irq_id_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/irq_ack_id_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/clock_en_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/fetch_en_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/boot_addr_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/test_mode_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_busy_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_req_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_gnt_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_addr_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_r_rdata_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_r_valid_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/debug_req_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/debug_havereset_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/debug_running_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/debug_halted_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/ext_perf_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_data_req_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_data_rsp_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_req_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_gnt_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_type_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_operands_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_op_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_flags_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_ready_o} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_valid_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_result_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/apu_master_flags_i} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/hart_id} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_sleep} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/boot_addr} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_irq_x} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_instr_req} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_instr_gnt} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_instr_addr} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_instr_r_rdata} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_instr_r_valid} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_mem_req} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_shadow_req} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_shadow_we} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_shadow_be} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_shadow_addr} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_shadow_wdata} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_data_atop} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/core_data_req_we} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/FILE} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_gnt_L2} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_gnt_ROM} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_r_rdata_ROM} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_r_valid_ROM} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_r_rdata_L2} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/instr_r_valid_L2} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/destination} -add wave -noupdate -group core_region_6 {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/reg_cache_refill} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} -add wave -noupdate -group core_region_6 -group core {/pulp_cluster_tb/cluster_i/CORE[6]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/clk_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/rst_ni} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/setback_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_id_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/cluster_id_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/irq_req_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/irq_ack_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/irq_id_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/irq_ack_id_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/clock_en_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/fetch_en_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/boot_addr_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/test_mode_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_busy_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_req_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_gnt_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_addr_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_r_rdata_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_r_valid_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/debug_req_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/debug_havereset_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/debug_running_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/debug_halted_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/ext_perf_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_data_req_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_data_rsp_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_req_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_gnt_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_type_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_operands_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_op_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_flags_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_ready_o} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_valid_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_result_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/apu_master_flags_i} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/hart_id} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_sleep} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/boot_addr} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_irq_x} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_instr_req} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_instr_gnt} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_instr_addr} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_instr_r_rdata} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_instr_r_valid} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_mem_req} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_shadow_req} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_shadow_we} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_shadow_be} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_shadow_addr} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_shadow_wdata} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_data_atop} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/core_data_req_we} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/FILE} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_gnt_L2} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_gnt_ROM} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_r_rdata_ROM} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_r_valid_ROM} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_r_rdata_L2} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/instr_r_valid_L2} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/destination} -add wave -noupdate -group core_region_7 {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/reg_cache_refill} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} -add wave -noupdate -group core_region_7 -group core {/pulp_cluster_tb/cluster_i/CORE[7]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/clk_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/rst_ni} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/setback_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_id_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/cluster_id_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_req_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_ack_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_id_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/irq_ack_id_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/clock_en_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/fetch_en_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/boot_addr_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/test_mode_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_busy_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_req_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_addr_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_req_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_havereset_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_running_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/debug_halted_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/ext_perf_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_req_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_rsp_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_req_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_type_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_operands_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_op_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_flags_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_ready_o} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_valid_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_result_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/apu_master_flags_i} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/hart_id} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_sleep} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/boot_addr} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_irq_x} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_req} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_gnt} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_addr} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_instr_r_valid} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_mem_req} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/core_data_req_we} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/FILE} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_L2} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/destination} +add wave -noupdate -group {Core[0]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/reg_cache_refill} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group {Core[0]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[0]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/clk_i} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/rst_ni} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/test_en_i} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/clk_en_i} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/base_addr_i} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/cluster_id_i} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/ext_perf_o} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/core_data_req_i} +add wave -noupdate -group {Core[0]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[0]/i_core_demux/core_data_rsp_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/clk_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/rst_ni} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/setback_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_id_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/cluster_id_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_req_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_ack_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_id_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/irq_ack_id_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/clock_en_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/fetch_en_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/boot_addr_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/test_mode_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_busy_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_req_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_gnt_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_addr_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_valid_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_req_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_havereset_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_running_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/debug_halted_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/ext_perf_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_req_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_rsp_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_req_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_type_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_operands_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_op_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_flags_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_ready_o} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_valid_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_result_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/apu_master_flags_i} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/hart_id} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_sleep} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/boot_addr} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_irq_x} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_req} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_gnt} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_addr} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_instr_r_valid} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_mem_req} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/core_data_req_we} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/FILE} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_gnt_L2} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/destination} +add wave -noupdate -group {Core[1]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/reg_cache_refill} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group {Core[1]} -group core_region -group core -radix unsigned {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group {Core[1]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[1]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/clk_i} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/rst_ni} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/test_en_i} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/clk_en_i} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/base_addr_i} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/cluster_id_i} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/ext_perf_o} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/core_data_req_i} +add wave -noupdate -group {Core[1]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[1]/i_core_demux/core_data_rsp_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/clk_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/rst_ni} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/setback_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_id_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/cluster_id_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_req_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_ack_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_id_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/irq_ack_id_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/clock_en_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/fetch_en_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/boot_addr_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/test_mode_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_busy_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_req_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_gnt_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_addr_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_valid_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_req_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_havereset_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_running_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/debug_halted_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/ext_perf_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_req_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_rsp_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_req_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_type_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_operands_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_op_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_flags_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_ready_o} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_valid_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_result_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/apu_master_flags_i} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/hart_id} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_sleep} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/boot_addr} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_irq_x} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_req} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_gnt} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_addr} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_instr_r_valid} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_mem_req} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/core_data_req_we} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/FILE} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_gnt_L2} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/destination} +add wave -noupdate -group {Core[2]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/reg_cache_refill} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group {Core[2]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[2]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/clk_i} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/rst_ni} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/test_en_i} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/clk_en_i} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/base_addr_i} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/cluster_id_i} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/ext_perf_o} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/core_data_req_i} +add wave -noupdate -group {Core[2]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[2]/i_core_demux/core_data_rsp_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/clk_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/rst_ni} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/setback_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_id_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/cluster_id_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_req_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_ack_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_id_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/irq_ack_id_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/clock_en_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/fetch_en_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/boot_addr_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/test_mode_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_busy_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_req_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_gnt_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_addr_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_valid_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_req_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_havereset_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_running_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/debug_halted_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/ext_perf_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_req_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_rsp_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_req_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_type_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_operands_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_op_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_flags_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_ready_o} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_valid_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_result_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/apu_master_flags_i} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/hart_id} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_sleep} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/boot_addr} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_irq_x} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_req} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_gnt} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_addr} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_instr_r_valid} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_mem_req} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/core_data_req_we} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/FILE} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_gnt_L2} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/destination} +add wave -noupdate -group {Core[3]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/reg_cache_refill} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group {Core[3]} -group core_region -group core {/pulp_cluster_tb/cluster_i/CORE[3]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/clk_i} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/rst_ni} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/test_en_i} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/clk_en_i} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/base_addr_i} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/cluster_id_i} +add wave -noupdate -group {Core[3]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[3]/i_core_demux/ext_perf_o} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/clk_i} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/rst_ni} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/test_en_i} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/clk_en_i} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/base_addr_i} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/cluster_id_i} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/ext_perf_o} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/core_data_req_i} +add wave -noupdate -group {Core[11]} -group core_demux {/pulp_cluster_tb/cluster_i/CORE[11]/i_core_demux/core_data_rsp_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/clk_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/rst_ni} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/setback_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_id_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/cluster_id_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/irq_req_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/irq_ack_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/irq_id_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/irq_ack_id_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/clock_en_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/fetch_en_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/boot_addr_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/test_mode_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_busy_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_req_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_gnt_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_addr_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_r_rdata_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_r_valid_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/debug_req_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/debug_havereset_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/debug_running_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/debug_halted_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/ext_perf_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_data_req_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_data_rsp_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_req_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_gnt_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_type_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_operands_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_op_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_flags_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_ready_o} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_valid_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_result_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/apu_master_flags_i} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/hart_id} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_sleep} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/boot_addr} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_irq_x} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_instr_req} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_instr_gnt} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_instr_addr} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_instr_r_rdata} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_instr_r_valid} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_mem_req} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/core_data_req_we} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/FILE} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_gnt_L2} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_gnt_ROM} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_r_rdata_ROM} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_r_valid_ROM} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_r_rdata_L2} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/instr_r_valid_L2} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/destination} +add wave -noupdate -group {Core[11]} -group core_region {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/reg_cache_refill} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/rst_ni} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/setback_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/test_en_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/fregfile_disable_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/boot_addr_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_id_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/cluster_id_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rvalid_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_be_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_wdata_o} +add wave -noupdate -group {Core[11]} -group core -radix unsigned {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rdata_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_unaligned_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_req_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_ready_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_gnt_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_operands_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_op_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_type_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_valid_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_result_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_master_flags_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_ack_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_id_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/irq_sec_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/sec_lvl_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_req_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/fetch_enable_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/ext_perf_counters_i} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_hwlp_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_dec_cnt_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_valid_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_rdata_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_compressed_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_fetch_failed_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/illegal_c_insn_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_if} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/clear_instr_valid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_set} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_mux_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_pc_mux_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/exc_cause} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/trap_addr_mux} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_load_err} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_store_err} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tosprw_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_tospra_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/dot_spr_operand_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_w_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/update_a_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_decoding} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/useincr_addr_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_multicycle} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/jump_target_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_in_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/branch_decision} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/ctrl_busy} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/if_busy} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_busy} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_busy} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pc_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_en_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operator_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_operand_c_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/bmask_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/imm_vec_ext_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_vec_mode_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_op_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_clpx_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_is_subrot_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/alu_clpx_shift_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operator_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_operand_c_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_en_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_sel_subword_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_signed_mode_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_imm_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_h_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_b_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_n_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_a_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_b_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_op_c_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_dot_signed_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex_o} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_shift_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_clpx_img_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/fprec_csr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/frm_csr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_csr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/fflags_we} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_en_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_type_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_flags_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_op_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_lat_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_operands_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_waddr_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_regs_valid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_read_dep} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_regs_valid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_write_dep} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_type} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_cont} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_dep} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_apu_wb} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_waddr_fw_wb} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_we_wb} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_wdata} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr2_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_waddr_fw} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_we_fw} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/regfile_alu_wdata_fw} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/ivec_fmt_csr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_csr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_cycle_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/skip_size_csr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/sb_legacy_mode} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mtvec} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/utvec} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_access} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_op} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_addr_int} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_rdata} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_wdata} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/current_priv_lvl} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_op} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_addr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_macl_wdata} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_address} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_address} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_stride} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_stride} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_rollback} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_rollback} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/a_skip} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/w_skip} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_a_rstn} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/macl_w_rstn} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/curr_cyc_sel} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_type_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_sign_ext_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_reg_offset_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_load_event_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_misaligned_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_rdata} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_rvalid_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/loadComputeVLIW_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/halt_if} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_ready} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_ready} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/id_valid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/ex_valid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/wb_valid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/lsu_ready_wb} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/apu_ready_wb} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_int} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/m_irq_enable} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/u_irq_enable} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_irq_sec} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mepc} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/uepc} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/depc} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_cause} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_if} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_save_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_cause} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_mret_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_uret_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_restore_dret_id} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_mode} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_cause} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_csr_save} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_single_step} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreakm} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/debug_ebreaku} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_start} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_end} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/hwlp_cnt} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_regid} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_we} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/csr_hwlp_data} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_imiss} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jump} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_jr_stall} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_ld_stall} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/perf_pipeline_stall} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_ctrl_firstfetch} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_int} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/core_busy_q} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_addr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/pmp_cfg} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_req_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_addr_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_we_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_gnt_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/data_err_ack} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_req_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_gnt_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_addr_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/instr_err_pmp} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mpc_next_cycle} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mux_sel_wcsr} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/is_interrupt} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/clk} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/clock_en} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/sleeping} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/mult_is_clpx_ex} +add wave -noupdate -group {Core[11]} -group core {/pulp_cluster_tb/cluster_i/CORE[11]/core_region_i/RI5CY_CORE/RI5CY_CORE/tracer_clk} TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {112525599521 ps} 0} {{Cursor 2} {89136000000 ps} 0} {{Cursor 3} {222455730424 ps} 0} -quietly wave cursor active 3 -configure wave -namecolwidth 211 +WaveRestoreCursors {{Cursor 1} {226440000000 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 184 configure wave -valuecolwidth 100 configure wave -justifyvalue left configure wave -signalnamewidth 1 @@ -3000,4 +1963,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {305197047167 ps} {305528576465 ps} +WaveRestoreZoom {225717754960 ps} {227423563880 ps} From b20f74bf7abc55dda34a5093934af0be2becf132 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 27 Jun 2023 14:50:55 +0200 Subject: [PATCH 041/207] Aligned testbench parameters to Carfield. --- tb/pulp_cluster_tb.sv | 75 +++++++++++++++++++++++-------------------- 1 file changed, 41 insertions(+), 34 deletions(-) diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 4e251060..4933bfbb 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -258,40 +258,47 @@ module pulp_cluster_tb; ); pulp_cluster #( - .NB_CORES ( `NB_CORES ), - .NB_HWPE_PORTS ( 9 ), - .NB_DMAS ( `NB_DMAS ), - .HWPE_PRESENT ( 1 ), - .TCDM_SIZE ( 128*1024 ), - .NB_TCDM_BANKS ( 16 ), - .SET_ASSOCIATIVE ( 4 ), - .CACHE_LINE ( 1 ), - .CACHE_SIZE ( 4096 ), - .ICACHE_DATA_WIDTH ( 128 ), - .L0_BUFFER_FEATURE ( "DISABLED" ), - .MULTICAST_FEATURE ( "DISABLED" ), - .SHARED_ICACHE ( "ENABLED" ), - .DIRECT_MAPPED_FEATURE ( "DISABLED" ), - .L2_SIZE ( 32'h10000 ), - .ROM_BOOT_ADDR ( 32'h1A000000 ), - .BOOT_ADDR ( 32'h1c008080 ), - .INSTR_RDATA_WIDTH ( 32 ), - .CLUST_FPU ( `CLUST_FPU ), - .CLUST_FP_DIVSQRT ( `CLUST_FP_DIVSQRT ), - .CLUST_SHARED_FP ( `CLUST_SHARED_FP ), - .CLUST_SHARED_FP_DIVSQRT ( `CLUST_SHARED_FP_DIVSQRT ), - .AXI_ADDR_WIDTH ( AxiAw ), - .AXI_DATA_S2C_WIDTH ( AxiDw ), - .AXI_DATA_C2S_WIDTH ( AxiDw ), - .AXI_USER_WIDTH ( AxiUw ), - .AXI_ID_IN_WIDTH ( AxiIw-2 ), - .AXI_ID_OUT_WIDTH ( AxiIw ), - .LOG_DEPTH ( 3 ), - .DATA_WIDTH ( 32 ), - .ADDR_WIDTH ( 32 ), - .LOG_CLUSTER ( 3 ), - .PE_ROUTING_LSB ( 10 ), - .EVNT_WIDTH ( 8 ) + .NB_CORES ( `NB_CORES ), + .NB_HWPE_PORTS ( 9 ), + .NB_DMAS ( `NB_DMAS ), + .NB_MPERIPHS ( 1 ), + .NB_SPERIPHS ( 10 ), + .CLUSTER_ALIAS ( 1 ), + .CLUSTER_ALIAS_BASE ( 12'h000 ), + .TCDM_SIZE ( 256*1024 ), + .NB_TCDM_BANKS ( 16 ), + .HWPE_PRESENT ( 1 ), + .USE_HETEROGENEOUS_INTERCONNECT ( 1 ), + .SET_ASSOCIATIVE ( 4 ), + .NB_CACHE_BANKS ( 2 ), + .CACHE_LINE ( 1 ), + .CACHE_SIZE ( 4*1024 ), + .ICACHE_DATA_WIDTH ( 128 ), + .L0_BUFFER_FEATURE ( "DISABLED" ), + .MULTICAST_FEATURE ( "DISABLED" ), + .SHARED_ICACHE ( "ENABLED" ), + .DIRECT_MAPPED_FEATURE ( "DISABLED" ), + .L2_SIZE ( 32'h10000 ), + .USE_REDUCED_TAG ( "TRUE" ), + .ROM_BOOT_ADDR ( 32'h1A000000 ), + .BOOT_ADDR ( 32'h1c008080 ), + .INSTR_RDATA_WIDTH ( 32 ), + .CLUST_FPU ( 0 ), + .CLUST_FP_DIVSQRT ( 0 ), + .CLUST_SHARED_FP ( 0 ), + .CLUST_SHARED_FP_DIVSQRT ( 0 ), + .AXI_ADDR_WIDTH ( AxiAw ), + .AXI_DATA_S2C_WIDTH ( AxiDw ), + .AXI_DATA_C2S_WIDTH ( AxiDw ), + .AXI_USER_WIDTH ( AxiUw ), + .AXI_ID_IN_WIDTH ( AxiIw-2 ), + .AXI_ID_OUT_WIDTH ( AxiIw ), + .LOG_DEPTH ( 3 ), + .DATA_WIDTH ( 32 ), + .ADDR_WIDTH ( 32 ), + .LOG_CLUSTER ( 3 ), + .PE_ROUTING_LSB ( 10 ), + .EVNT_WIDTH ( 8 ) ) cluster_i ( .clk_i ( s_clk ), .rst_ni ( s_rstn ), From 2c6ad3f823ee5f323062279c16af37a1180030be Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 7 Jul 2023 11:34:33 +0200 Subject: [PATCH 042/207] Fixed cluster base address bug in XBAR PE. --- rtl/xbar_pe_wrap.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/xbar_pe_wrap.sv b/rtl/xbar_pe_wrap.sv index 89a9c4cd..3b3d88bc 100644 --- a/rtl/xbar_pe_wrap.sv +++ b/rtl/xbar_pe_wrap.sv @@ -97,7 +97,7 @@ module xbar_pe_wrap end else begin if ( // if the access is to this cluster .. - (addr[31:24] == 8'h10 || (cluster_alias && addr[31:24] == CLUSTER_ALIAS_BASE[11:4])) + (addr[31:24] == cluster_base_addr[31:24] || (cluster_alias && addr[31:24] == CLUSTER_ALIAS_BASE[11:4])) // .. and the peripherals && (addr >= cluster_peripherals_base && addr <= cluster_peripherals_end) From e20498569e49cb8d1114cb985bb6d58f2b4479fc Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 11 Jul 2023 17:01:06 +0200 Subject: [PATCH 043/207] Aligned parameters to Carfield. --- tb/pulp_cluster_tb.sv | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 4933bfbb..c1c4a463 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -46,7 +46,7 @@ module pulp_cluster_tb; .rst_no ( s_rstn ) ); - localparam AxiAw = 32; + localparam AxiAw = 48; localparam AxiDw = 64; localparam AxiIw = 6; localparam NMst = 2; @@ -54,7 +54,7 @@ module pulp_cluster_tb; localparam AxiIwMst = AxiIw + $clog2(NMst); localparam AxiWideBeWidth = AxiDw/8; localparam AxiWideByteOffset = $clog2(AxiWideBeWidth); - localparam AxiUw = 1; + localparam AxiUw = 2; typedef logic [AxiAw-1:0] axi_addr_t; typedef logic [AxiDw-1:0] axi_data_t; @@ -261,8 +261,8 @@ module pulp_cluster_tb; .NB_CORES ( `NB_CORES ), .NB_HWPE_PORTS ( 9 ), .NB_DMAS ( `NB_DMAS ), - .NB_MPERIPHS ( 1 ), - .NB_SPERIPHS ( 10 ), + .NB_MPERIPHS ( `NB_MPERIPHS ), + .NB_SPERIPHS ( `NB_SPERIPHS ), .CLUSTER_ALIAS ( 1 ), .CLUSTER_ALIAS_BASE ( 12'h000 ), .TCDM_SIZE ( 256*1024 ), @@ -273,13 +273,7 @@ module pulp_cluster_tb; .NB_CACHE_BANKS ( 2 ), .CACHE_LINE ( 1 ), .CACHE_SIZE ( 4*1024 ), - .ICACHE_DATA_WIDTH ( 128 ), - .L0_BUFFER_FEATURE ( "DISABLED" ), - .MULTICAST_FEATURE ( "DISABLED" ), - .SHARED_ICACHE ( "ENABLED" ), - .DIRECT_MAPPED_FEATURE ( "DISABLED" ), - .L2_SIZE ( 32'h10000 ), - .USE_REDUCED_TAG ( "TRUE" ), + .L2_SIZE ( 32'h100000 ), .ROM_BOOT_ADDR ( 32'h1A000000 ), .BOOT_ADDR ( 32'h1c008080 ), .INSTR_RDATA_WIDTH ( 32 ), @@ -293,12 +287,7 @@ module pulp_cluster_tb; .AXI_USER_WIDTH ( AxiUw ), .AXI_ID_IN_WIDTH ( AxiIw-2 ), .AXI_ID_OUT_WIDTH ( AxiIw ), - .LOG_DEPTH ( 3 ), - .DATA_WIDTH ( 32 ), - .ADDR_WIDTH ( 32 ), - .LOG_CLUSTER ( 3 ), - .PE_ROUTING_LSB ( 10 ), - .EVNT_WIDTH ( 8 ) + .LOG_DEPTH ( 3 ) ) cluster_i ( .clk_i ( s_clk ), .rst_ni ( s_rstn ), From 08da2015fc27a95becef0564c398cdccf5e7c89b Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 11 Jul 2023 19:57:15 +0200 Subject: [PATCH 044/207] Added carfield environment and written cluster memory map in pulp_cluster_pkg.sv --- env/carfield-env.sh | 8 ++++++++ packages/pulp_cluster_package.sv | 20 ++++++++++---------- 2 files changed, 18 insertions(+), 10 deletions(-) create mode 100644 env/carfield-env.sh diff --git a/env/carfield-env.sh b/env/carfield-env.sh new file mode 100644 index 00000000..4426c8f9 --- /dev/null +++ b/env/carfield-env.sh @@ -0,0 +1,8 @@ +# Copyright 2023 ETH Zurich and University of Bologna +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# set up environment variables for rtl simulation, pulp-runtime and freertos +ROOTD=$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")/.." && pwd) +source "$ROOTD/pulp-runtime/configs/carfield-cluster.sh" +source "$ROOTD/scripts/vsim.sh" diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 88484ccc..974417d8 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -23,17 +23,17 @@ package pulp_cluster_package; parameter NB_SPERIPHS = 10; // position of peripherals on slave port of periph interconnect - parameter SPER_EOC_ID = 0; - parameter SPER_TIMER_ID = 1; - parameter SPER_EVENT_U_ID = 2; + parameter SPER_EOC_ID = 0; // 0x0000 - 0x0400 + parameter SPER_TIMER_ID = 1; // 0x0400 - 0x0800 + parameter SPER_EVENT_U_ID = 2; // 0x0800 - 0x1000 // 3 also used for Event Unit - parameter SPER_HWPE_ID = 4; - parameter SPER_ICACHE_CTRL = 5; - parameter SPER_DMA_CL_ID = 6; - parameter SPER_DMA_FC_ID = 7; - parameter SPER_HMR_UNIT_ID = 8; - parameter SPER_EXT_ID = 9; - parameter SPER_ERROR_ID = 10; + parameter SPER_HWPE_ID = 4; // 0x1000 - 0x1400 + parameter SPER_ICACHE_CTRL = 5; // 0x1400 - 0x1800 + parameter SPER_DMA_CL_ID = 6; // 0x1800 - 0x1C00 + parameter SPER_DMA_FC_ID = 7; // 0x1C00 - 0x2000 + parameter SPER_HMR_UNIT_ID = 8; // 0x2000 - 0x2400 + parameter SPER_EXT_ID = 9; // 0x2400 - 0x2800 + parameter SPER_ERROR_ID = 10; // 0x2800 - 0x2C00 // if set to 1, then instantiate APU in the cluster // parameter APU_CLUSTER = 0; From c7c044a0f6df167c6bb7b793a4ea48c4f2d0063c Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 1 Aug 2023 18:15:43 +0200 Subject: [PATCH 045/207] Added rapid recovery; propagated CDC synch stages; bumped dependencies. --- Bender.local | 2 +- Bender.lock | 20 +++--- Bender.yml | 10 +-- packages/pulp_cluster_package.sv | 8 ++- rtl/pulp_cluster.sv | 104 +++++++++++++++++++------------ tb/pulp_cluster_tb.sv | 11 ++-- 6 files changed, 90 insertions(+), 65 deletions(-) diff --git a/Bender.local b/Bender.local index 723b1b0a..2386c8ee 100644 --- a/Bender.local +++ b/Bender.local @@ -1,4 +1,4 @@ overrides: - axi : { git: "https://github.com/pulp-platform/axi.git" , version: =0.39.0-beta.9 } + axi : { git: "https://github.com/pulp-platform/axi.git" , version: =0.39.1-beta } register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix diff --git a/Bender.lock b/Bender.lock index 19091dd7..fab0542c 100644 --- a/Bender.lock +++ b/Bender.lock @@ -7,8 +7,8 @@ packages: dependencies: - common_cells axi: - revision: f24b1faf7bcf651f1aabdef5e8f99ce2fd817c2e - version: 0.39.0-beta.9 + revision: da423834b45f2e1878ecb28a11dc5b72b437f9c1 + version: 0.39.1-beta source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -105,13 +105,13 @@ packages: dependencies: - common_cells fpu_interco: - revision: 0769976fa51bdd820656a01161a4c46b88c59ac5 + revision: 4aec4b68424947b0c4cf25fd7c4b907cb9ec3dfa version: null source: Git: https://github.com/pulp-platform/fpu_interco.git dependencies: - - cv32e40p - fpnew + - riscv hci: revision: b2e6f391aa6c10c03f45b693d80a0aaddecf169b version: null @@ -134,8 +134,8 @@ packages: - scm - tech_cells_generic hwpe-ctrl: - revision: 4bf1487a463c262bf7d8ffee79d1cf392937daa2 - version: 1.7.1 + revision: 3d9b9bea7b98df24e6b235408364521a1a27d561 + version: 1.7.2 source: Git: https://github.com/pulp-platform/hwpe-ctrl.git dependencies: @@ -148,10 +148,10 @@ packages: dependencies: - tech_cells_generic ibex: - revision: 95b85ddd1c995ace9f89ee42530f9e24820c1051 + revision: b18f7ef178ed07f5085051f96042c670a919fd5c version: null source: - Git: https://github.com/lowRISC/ibex.git + Git: https://github.com/pulp-platform/ibex.git dependencies: - tech_cells_generic icache-intc: @@ -204,7 +204,7 @@ packages: - hwpe-stream - tech_cells_generic redundancy_cells: - revision: 6e10650b50c7b40f7f81602acf61526330c4d69d + revision: 482d2f5ed05f25c851f4048f1bd402cc0d2b58b6 version: null source: Git: https://github.com/pulp-platform/redundancy_cells.git @@ -224,7 +224,7 @@ packages: - common_cells - common_verification riscv: - revision: 4eac53237c6d0062715d17016fe95462eb81ebc3 + revision: dd086242d10f248b4051a1fc67ae2b35b989c29c version: null source: Git: git@github.com:AlSaqr-platform/riscv_nn.git diff --git a/Bender.yml b/Bender.yml index 94c05463..9ad63ac9 100644 --- a/Bender.yml +++ b/Bender.yml @@ -21,20 +21,20 @@ dependencies: idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a7e3f4e4c7fe607bcd6b9d94db77f612fd6ef6be" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: a596f17fc77713909bceb7eecf3ea2c3cdfe707c } # branch: yt/bump-hci - fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "0769976fa51bdd820656a01161a4c46b88c59ac5" } # branch: yt/carfield - axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.0-beta.9 } + fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "4aec4b68424947b0c4cf25fd7c4b907cb9ec3dfa" } # branch: yt/carfield + axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 4eac53237c6d0062715d17016fe95462eb81ebc3 } # branch: yt/hmr + riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: dd086242d10f248b4051a1fc67ae2b35b989c29c } # branch: yt/hmr cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: 9b77611 } # `michaero/safety-island-clic` branch - ibex: { git: "https://github.com/lowRISC/ibex.git", rev: "pulpissimo-v6.1.1" } + ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating hci: { git: "https://github.com/pulp-platform/hci.git", rev: b2e6f391aa6c10c03f45b693d80a0aaddecf169b } # branch: master register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } - redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 6e10650b50c7b40f7f81602acf61526330c4d69d} # branch: yt/hmr + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 482d2f5ed05f25c851f4048f1bd402cc0d2b58b6 } # branch: yt/rapidrecovery redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 3797413e5f190c2a86185ab6d8b12af365051b1e } # branch: carfield export_include_dirs: diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 974417d8..7bee53a5 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -16,6 +16,7 @@ package pulp_cluster_package; + import rapid_recovery_pkg::*; parameter NB_SPERIPH_PLUGS_EU = 2; // number of master and slave cluster periphs @@ -75,8 +76,6 @@ package pulp_cluster_package; logic [31:0] data_rdata; logic irq_req; logic [4:0] irq_id; - logic debug_req; - // logic debug_resume; } core_inputs_t; typedef struct packed { @@ -91,8 +90,11 @@ package pulp_cluster_package; logic [4:0] irq_ack_id; // logic debug_havereset; // logic debug_running; - // logic debug_halted; + logic debug_halted; logic core_busy; + rapid_recovery_pkg::regfile_write_t regfile_backup; + rapid_recovery_pkg::csrs_intf_t csr_backup; + rapid_recovery_pkg::pc_intf_t pc_backup; } core_outputs_t; endpackage diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 25e43a93..6f88b705 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -26,6 +26,7 @@ module pulp_cluster import pulp_cluster_package::*; import hci_package::*; + import rapid_recovery_pkg::*; #( // cluster parameters parameter CORE_TYPE_CL = 1, // 0 for CV32, 1 for RI5CY, 2 for IBEX RV32IMC @@ -86,6 +87,7 @@ module pulp_cluster parameter AXI_STRB_S2C_WIDTH = AXI_DATA_S2C_WIDTH/8, parameter DC_SLICE_BUFFER_WIDTH = 8, parameter LOG_DEPTH = 3, + parameter int unsigned CdcSynchStages = 3, parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h10000000, parameter logic [AXI_ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, parameter logic [AXI_ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000, @@ -863,6 +865,7 @@ core_data_req_t [NB_CORES-1:0] core_data_req, demux_data_req; core_data_rsp_t [NB_CORES-1:0] core_data_rsp, demux_data_rsp; core_inputs_t [NB_CORES-1:0] sys2hmr, hmr2core; core_outputs_t [NB_CORES-1:0] hmr2sys, core2hmr; +rapid_recovery_pkg::rapid_recovery_t [NB_CORES-1:0] recovery_bus; logic [NB_CORES-1:0] clk_core; logic [NB_CORES-1:0] setback; logic [NB_CORES-1:0][4:0] ext_perf; @@ -927,15 +930,24 @@ generate .instr_r_rdata_i ( hmr2core[i].instr_rdata ), .instr_r_valid_i ( hmr2core[i].instr_rvalid ), //debug unit bind - .debug_req_i ( hmr2core[i].debug_req | - s_core_dbg_irq[i] ), - .debug_halted_o ( dbg_core_halted[i] ), - .debug_havereset_o ( dbg_core_havereset[i] ), - .debug_running_o ( dbg_core_running[i] ), - .ext_perf_i ( ext_perf[i] ), - .core_data_req_o ( core_data_req[i] ), - .core_data_rsp_i ( core_data_rsp[i] ), - // .debug_resume_i ( dbg_core_resume[i] ), // Useful for HMR, consider keeping + .debug_req_i ( recovery_bus[i].debug_req | + s_core_dbg_irq[i] ), + // .debug_halted_o ( dbg_core_halted[i] ), + .debug_halted_o ( core2hmr[i].debug_halted ), + .debug_havereset_o ( dbg_core_havereset[i] ), + .debug_running_o ( dbg_core_running[i] ), + .ext_perf_i ( ext_perf[i] ), + .core_data_req_o ( core_data_req[i] ), + .core_data_rsp_i ( core_data_rsp[i] ), + // .debug_resume_i ( recovery_bus[i].debug_resume ), // Useful for HMR, consider keeping + //HMR Recovery Bus + // .csr_recovery_i ( recovery_bus[i].csr_recovery ), + // .pc_recovery_i ( recovery_bus[i].pc_recovery ), + // .instr_lock_i ( recovery_bus[i].instr_lock ), + // .pc_recovery_en ( recovery_bus[i].pc_recovery_en ), + // .rf_recovery_en ( recovery_bus[i].rf_recovery_en ), + // .rf_recovery_wdata ( recovery_bus[i].rf_recovery_wdata ), + // .rf_recovery_rdata ( recovery_bus[i].rf_recovery_rdata ), //apu interface .apu_master_req_o ( s_apu_master_req [i] ), .apu_master_gnt_i ( s_apu_master_gnt [i] ), @@ -949,6 +961,8 @@ generate .apu_master_flags_i ( s_apu_master_rflags [i] ) ); + assign dbg_core_halted[i] = core2hmr[i].debug_halted; + // Binding inputs/outputs from HMR to the system and vice versa assign sys2hmr[i].clock_en = clk_core_en[i]; assign sys2hmr[i].boot_addr = boot_addr; @@ -962,7 +976,6 @@ generate assign sys2hmr[i].data_rdata = demux_data_rsp[i].r_data; assign sys2hmr[i].irq_req = irq_req[i]; assign sys2hmr[i].irq_id = irq_id[i]; - assign sys2hmr[i].debug_req = '0; assign instr_req[i] = hmr2sys[i].instr_req; assign instr_addr[i] = hmr2sys[i].instr_addr; @@ -986,6 +999,10 @@ generate assign core2hmr[i].data_wdata = core_data_req[i].data; assign core2hmr[i].data_be = core_data_req[i].be; + assign core2hmr[i].regfile_backup = '0; + assign core2hmr[i].csr_backup = '0; + assign core2hmr[i].pc_backup = '0; + core_demux_wrap #( .AddrWidth ( ADDR_WIDTH ), .DataWidth ( DATA_WIDTH ), @@ -1014,19 +1031,20 @@ generate endgenerate hmr_unit #( - .NumCores ( NB_CORES ), - .DMRSupported ( 1 ), - .DMRFixed ( 0 ), - .TMRSupported ( 1 ), - .TMRFixed ( 0 ), - .InterleaveGrps ( 1 ), - .RapidRecovery ( 0 ), - .SeparateData ( 1 ), - .NumBusVoters ( 1 ), - .all_inputs_t ( core_inputs_t ), - .nominal_outputs_t ( core_outputs_t ), - .reg_req_t ( hmr_reg_req_t ), - .reg_rsp_t ( hmr_reg_rsp_t ) + .NumCores ( NB_CORES ), + .DMRSupported ( 1 ), + .DMRFixed ( 0 ), + .TMRSupported ( 1 ), + .TMRFixed ( 0 ), + .InterleaveGrps ( 1 ), + .RapidRecovery ( 1 ), + .SeparateData ( 1 ), + .NumBusVoters ( 1 ), + .all_inputs_t ( core_inputs_t ), + .nominal_outputs_t ( core_outputs_t ), + .reg_req_t ( hmr_reg_req_t ), + .reg_rsp_t ( hmr_reg_rsp_t ), + .rapid_recovery_t ( rapid_recovery_pkg::rapid_recovery_t ) ) i_hmr_unit ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -1045,6 +1063,8 @@ hmr_unit #( .dmr_resynch_req_o ( ), .dmr_sw_synch_req_o ( ), .dmr_cores_synch_i ( '0 ), + // Rapid recovery output bus + .rapid_recovery_o ( recovery_bus ), .sys_inputs_i ( sys2hmr ), .sys_nominal_outputs_o ( hmr2sys ), .sys_bus_outputs_o ( ), @@ -1385,15 +1405,16 @@ axi_isolate #( .isolated_o ( axi_isolated_o ) ); -axi_cdc_src #( - .aw_chan_t ( c2s_aw_chan_t ), - .w_chan_t ( c2s_w_chan_t ), - .b_chan_t ( c2s_b_chan_t ), - .r_chan_t ( c2s_r_chan_t ), - .ar_chan_t ( c2s_ar_chan_t ), - .axi_req_t ( c2s_req_t ), - .axi_resp_t ( c2s_resp_t ), - .LogDepth ( LOG_DEPTH ) +axi_cdc_src #( + .aw_chan_t ( c2s_aw_chan_t ), + .w_chan_t ( c2s_w_chan_t ), + .b_chan_t ( c2s_b_chan_t ), + .r_chan_t ( c2s_r_chan_t ), + .ar_chan_t ( c2s_ar_chan_t ), + .axi_req_t ( c2s_req_t ), + .axi_resp_t ( c2s_resp_t ), + .LogDepth ( LOG_DEPTH ), + .SyncStages ( CdcSynchStages ) ) axi_master_cdc_i ( .src_rst_ni ( pwr_on_rst_ni ), .src_clk_i ( clk_i ), @@ -1432,15 +1453,16 @@ axi_cdc_src #( `AXI_ASSIGN_FROM_REQ(s_data_slave_32,dst_req) `AXI_ASSIGN_TO_RESP(dst_resp,s_data_slave_32) -axi_cdc_dst #( - .aw_chan_t (s2c_aw_chan_t), - .w_chan_t (s2c_w_chan_t ), - .b_chan_t (s2c_b_chan_t ), - .r_chan_t (s2c_r_chan_t ), - .ar_chan_t (s2c_ar_chan_t), - .axi_req_t (s2c_req_t ), - .axi_resp_t(s2c_resp_t ), - .LogDepth ( LOG_DEPTH ) +axi_cdc_dst #( + .aw_chan_t ( s2c_aw_chan_t ), + .w_chan_t ( s2c_w_chan_t ), + .b_chan_t ( s2c_b_chan_t ), + .r_chan_t ( s2c_r_chan_t ), + .ar_chan_t ( s2c_ar_chan_t ), + .axi_req_t ( s2c_req_t ), + .axi_resp_t ( s2c_resp_t ), + .LogDepth ( LOG_DEPTH ), + .SyncStages ( CdcSynchStages ) ) axi_slave_cdc_i ( .dst_rst_ni ( pwr_on_rst_ni ), .dst_clk_i ( clk_i ), diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index c1c4a463..0c0626c2 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -287,7 +287,8 @@ module pulp_cluster_tb; .AXI_USER_WIDTH ( AxiUw ), .AXI_ID_IN_WIDTH ( AxiIw-2 ), .AXI_ID_OUT_WIDTH ( AxiIw ), - .LOG_DEPTH ( 3 ) + .LOG_DEPTH ( 3 ), + .CdcSynchStages ( 3 ) ) cluster_i ( .clk_i ( s_clk ), .rst_ni ( s_rstn ), @@ -467,7 +468,7 @@ module pulp_cluster_tb; assign s_cluster_fetch_en = 1'b1; ret_val = '0; - while(~ret_val[31]) begin + while(~s_cluster_eoc) begin ar_beat.ax_addr = 32'h1A10_40A0; ar_beat.ax_len = '0; @@ -477,7 +478,7 @@ module pulp_cluster_tb; axi_master_drv.send_ar(ar_beat); @(posedge s_clk); axi_master_drv.recv_r(r_beat); - ret_val = r_beat.r_data; + ret_val = r_beat.r_data; repeat(1000) @(posedge s_clk); @@ -492,7 +493,7 @@ module pulp_cluster_tb; $fatal(1,"[TB] Test not passed: ret_val!=0\n"); end - end // initial begin + end -endmodule // pulp_cluster_tb +endmodule : pulp_cluster_tb From 223805341b69123870c720b867aea1f3e1d2a194 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 2 Aug 2023 00:45:47 +0200 Subject: [PATCH 046/207] Aligned Testbench memory map to Carfield and PULP runtime ones. --- tb/pulp_cluster_tb.sv | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 0c0626c2..17a1aca0 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -55,6 +55,15 @@ module pulp_cluster_tb; localparam AxiWideBeWidth = AxiDw/8; localparam AxiWideByteOffset = $clog2(AxiWideBeWidth); localparam AxiUw = 2; + + localparam bit[AxiAw-1:0] ClustBase = 'h50000000; + localparam bit[AxiAw-1:0] ClustPeriphOffs = 'h00200000; + localparam bit[AxiAw-1:0] ClustExtOffs = 'h00400000; + localparam bit[ 5:0] ClustIdx = 'h1; + localparam bit[AxiAw-1:0] ClustBaseAddr = ClustBase - ClustIdx*ClustExtOffs; + localparam bit[AxiAw-1:0] L2BaseAddr = 'h78000000; + localparam bit[AxiAw-1:0] L2Size = 'h00100000; + localparam bit[AxiAw-1:0] BootAddr = L2BaseAddr + 'h8080; typedef logic [AxiAw-1:0] axi_addr_t; typedef logic [AxiDw-1:0] axi_data_t; @@ -173,13 +182,13 @@ module pulp_cluster_tb; }; assign addr_map[1] = '{ // 512KiB L2SPM idx: 1, - start_addr: 32'h1C00_0000, - end_addr: 32'h1C08_0000 + start_addr: L2BaseAddr, + end_addr: L2BaseAddr + L2Size }; assign addr_map[2] = '{ // Pulp Cluster idx: 2, - start_addr: 32'h1000_0000, - end_addr: 32'h1004_0000 + start_addr: ClustBaseAddr, + end_addr: ClustBaseAddr + ClustExtOffs }; assign addr_map[3] = '{ // Return address idx: 1, // Just put it in axi_sim_mem @@ -275,7 +284,7 @@ module pulp_cluster_tb; .CACHE_SIZE ( 4*1024 ), .L2_SIZE ( 32'h100000 ), .ROM_BOOT_ADDR ( 32'h1A000000 ), - .BOOT_ADDR ( 32'h1c008080 ), + .BOOT_ADDR ( BootAddr ), .INSTR_RDATA_WIDTH ( 32 ), .CLUST_FPU ( 0 ), .CLUST_FP_DIVSQRT ( 0 ), @@ -288,6 +297,9 @@ module pulp_cluster_tb; .AXI_ID_IN_WIDTH ( AxiIw-2 ), .AXI_ID_OUT_WIDTH ( AxiIw ), .LOG_DEPTH ( 3 ), + .BaseAddr ( ClustBaseAddr ), + .ClusterPeripheralsOffs ( ClustPeriphOffs ), + .ClusterExternalOffs ( ClustExtOffs ), .CdcSynchStages ( 3 ) ) cluster_i ( .clk_i ( s_clk ), From 201453dbcedc8f7235b2723363356ba5845e5120 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 2 Aug 2023 07:26:33 +0200 Subject: [PATCH 047/207] Sourcing correct config file during regression execution. --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 9daa70aa..3cd2701c 100644 --- a/Makefile +++ b/Makefile @@ -119,7 +119,7 @@ run: .PHONY: test-rt-par-bare ## Run only parallel tests on pulp-runtime test-rt-par-bare: pulp-runtime regression-tests - source env/env.sh; \ + source env/carfield-env.sh; \ cd regression-tests && $(bwruntest) --proc-verbose -v \ -t 3600 --yaml --max-procs 2 \ -o runtime-parallel.xml parallel-bare-tests.yaml @@ -128,7 +128,7 @@ test-rt-par-bare: pulp-runtime regression-tests .PHONY: test-rt-mchan ## Run mchan tests on pulp-runtime test-rt-mchan: pulp-runtime regression-tests - source env/env.sh; \ + source env/carfield-env.sh; \ cd regression-tests && $(bwruntest) --proc-verbose -v \ -t 3600 --yaml --max-procs 2 \ -o runtime-mchan.xml pulp_cluster-mchan-tests.yaml From 70ce347de85f14644782ead576212658e111abc8 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 11 Aug 2023 18:48:28 +0200 Subject: [PATCH 048/207] Fixed address issue. Data/Periph demux did not consider the cluster base address input for routing requests. Propagated cluster index only to cores. --- rtl/data_periph_demux.sv | 6 +++--- rtl/pulp_cluster.sv | 6 +++--- tb/pulp_cluster_tb.sv | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/rtl/data_periph_demux.sv b/rtl/data_periph_demux.sv index 61dc2eb8..aef48582 100644 --- a/rtl/data_periph_demux.sv +++ b/rtl/data_periph_demux.sv @@ -135,9 +135,9 @@ module data_periph_demux always_comb begin - TCDM_RW = 12'h100 + (CLUSTER_ID << 2) + 0; - TCDM_TS = 12'h100 + (CLUSTER_ID << 2) + 1; - DEM_PER = 12'h100 + (CLUSTER_ID << 2) + 2; + TCDM_RW = {base_addr_i, 8'h00} + (CLUSTER_ID << 2) + 0; + TCDM_TS = {base_addr_i, 8'h00} + (CLUSTER_ID << 2) + 1; + DEM_PER = {base_addr_i, 8'h00} + (CLUSTER_ID << 2) + 2; end diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 6f88b705..cbde3f0e 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -552,7 +552,7 @@ cluster_bus_wrap #( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .test_en_i ( test_mode_i ), - .cluster_id_i ( cluster_id_i ), + .cluster_id_i ( '0 ), .instr_slave ( s_core_instr_bus ), .data_slave ( s_core_ext_bus ), .dma_slave ( s_dma_ext_bus ), @@ -657,7 +657,7 @@ cluster_interconnect_wrap #( ) cluster_interconnect_wrap_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .cluster_id_i ( cluster_id_i ), + .cluster_id_i ( '0 ), .core_tcdm_slave ( s_hci_core ), .hwpe_tcdm_slave ( s_hci_hwpe ), @@ -1018,7 +1018,7 @@ generate .test_en_i ( test_mode_i ), .clk_en_i ( clk_core_en[i] ), .base_addr_i ( base_addr_i ), - .cluster_id_i ( cluster_id_i ), + .cluster_id_i ( '0 ), .ext_perf_o ( ext_perf[i] ), .core_data_req_i ( demux_data_req[i] ), .core_data_rsp_o ( demux_data_rsp[i] ), diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 17a1aca0..dc14e40d 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -60,7 +60,7 @@ module pulp_cluster_tb; localparam bit[AxiAw-1:0] ClustPeriphOffs = 'h00200000; localparam bit[AxiAw-1:0] ClustExtOffs = 'h00400000; localparam bit[ 5:0] ClustIdx = 'h1; - localparam bit[AxiAw-1:0] ClustBaseAddr = ClustBase - ClustIdx*ClustExtOffs; + localparam bit[AxiAw-1:0] ClustBaseAddr = ClustBase; localparam bit[AxiAw-1:0] L2BaseAddr = 'h78000000; localparam bit[AxiAw-1:0] L2Size = 'h00100000; localparam bit[AxiAw-1:0] BootAddr = L2BaseAddr + 'h8080; @@ -311,7 +311,7 @@ module pulp_cluster_tb; .pmu_mem_pwdn_i ( 1'b0 ), - .base_addr_i ( '0 ), + .base_addr_i ( 4'd5 ), .dma_pe_evt_ack_i ( '1 ), .dma_pe_evt_valid_o ( ), @@ -334,7 +334,7 @@ module pulp_cluster_tb; .fetch_en_i ( s_cluster_fetch_en ), .eoc_o ( s_cluster_eoc ), .busy_o ( s_cluster_busy ), - .cluster_id_i ( 6'b000001 ), + .cluster_id_i ( ClustIdx ), .async_data_master_aw_wptr_o ( async_cluster_to_soc_axi_bus.aw_wptr ), .async_data_master_aw_rptr_i ( async_cluster_to_soc_axi_bus.aw_rptr ), From 1f44700d64a54224e5001139990a2aaef5e33c2d Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 12 Aug 2023 12:05:43 +0200 Subject: [PATCH 049/207] Bumped hier-icache and enabled usage of FFs instead of SCMs. --- Bender.lock | 6 +++--- Bender.yml | 2 +- Makefile | 2 ++ 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/Bender.lock b/Bender.lock index fab0542c..550d68db 100644 --- a/Bender.lock +++ b/Bender.lock @@ -60,8 +60,8 @@ packages: dependencies: - hci common_cells: - revision: 0989ff73d0315922791bf42137c0ce0cbb4a76ca - version: 1.30.0 + revision: 53b0b58af2db5bd3c850a7038fae170ed78326bb + version: 1.31.1 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -122,7 +122,7 @@ packages: - hwpe-stream - l2_tcdm_hybrid_interco hier-icache: - revision: a7e3f4e4c7fe607bcd6b9d94db77f612fd6ef6be + revision: 9631f34f5d057f099808e2c93745e4fdf7f88dfe version: null source: Git: https://github.com/pulp-platform/hier-icache.git diff --git a/Bender.yml b/Bender.yml index 9ad63ac9..b52fb0d4 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,7 +19,7 @@ dependencies: event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: "1.4.1" } mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master - hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a7e3f4e4c7fe607bcd6b9d94db77f612fd6ef6be" } # branch: yt/carfield + hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "9631f34f5d057f099808e2c93745e4fdf7f88dfe" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: a596f17fc77713909bceb7eecf3ea2c3cdfe707c } # branch: yt/bump-hci fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "4aec4b68424947b0c4cf25fd7c4b907cb9ec3dfa" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } diff --git a/Makefile b/Makefile index 3cd2701c..2c75e3a8 100644 --- a/Makefile +++ b/Makefile @@ -26,6 +26,7 @@ XVLOG_ARGS += -64bit -compile -vtimescale 1ns/1ns -quiet bender_defs += -D FEATURE_ICACHE_STAT bender_defs += -D PRIVATE_ICACHE bender_defs += -D HIERARCHY_ICACHE_32BIT +bender_defs += -D ICAHE_USE_FF bender_defs += -D NO_FPU bender_defs += -D TRACE_EXECUTION bender_defs += -D CLUSTER_ALIAS @@ -34,6 +35,7 @@ bender_targs += -t rtl bender_targs += -t test bender_targs += -t mchan bender_targs += -t cluster_standalone +bender_targs += -t scm_use_fpga_scm bender_targs += -t cv32e40p_use_ff_regfile define generate_vsim From fa797ad057bfeefd34744d0310a501c216332263 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 13 Aug 2023 09:06:40 +0200 Subject: [PATCH 050/207] Make base_addr_i depend on base address parameter. --- tb/pulp_cluster_tb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index dc14e40d..78923f1c 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -311,7 +311,7 @@ module pulp_cluster_tb; .pmu_mem_pwdn_i ( 1'b0 ), - .base_addr_i ( 4'd5 ), + .base_addr_i ( ClustBase[31:28] ), .dma_pe_evt_ack_i ( '1 ), .dma_pe_evt_valid_o ( ), From 2fa998a201954945f58b914961eaa8cb26a86141 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 14 Aug 2023 11:09:50 +0200 Subject: [PATCH 051/207] Bumped RedMulE to ff-based regfile version. --- Bender.lock | 6 +++--- Bender.yml | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Bender.lock b/Bender.lock index 550d68db..f082ff83 100644 --- a/Bender.lock +++ b/Bender.lock @@ -134,8 +134,8 @@ packages: - scm - tech_cells_generic hwpe-ctrl: - revision: 3d9b9bea7b98df24e6b235408364521a1a27d561 - version: 1.7.2 + revision: b7857919ea14b586901ff4282ad7749a3d50501e + version: null source: Git: https://github.com/pulp-platform/hwpe-ctrl.git dependencies: @@ -191,7 +191,7 @@ packages: dependencies: - axi_slice redmule: - revision: 3797413e5f190c2a86185ab6d8b12af365051b1e + revision: 886ad5ecf5fd908e0c0b278c22914a76a704eda3 version: null source: Git: https://github.com/pulp-platform/redmule.git diff --git a/Bender.yml b/Bender.yml index b52fb0d4..1fbd6180 100644 --- a/Bender.yml +++ b/Bender.yml @@ -35,7 +35,7 @@ dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 482d2f5ed05f25c851f4048f1bd402cc0d2b58b6 } # branch: yt/rapidrecovery - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 3797413e5f190c2a86185ab6d8b12af365051b1e } # branch: carfield + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 886ad5ecf5fd908e0c0b278c22914a76a704eda3 } # branch: carfield export_include_dirs: - include From 9360945eba02e2fc586d3445dcb56939056f90c8 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 14 Aug 2023 15:26:49 +0200 Subject: [PATCH 052/207] Bumped icache. --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index f082ff83..738b662d 100644 --- a/Bender.lock +++ b/Bender.lock @@ -122,7 +122,7 @@ packages: - hwpe-stream - l2_tcdm_hybrid_interco hier-icache: - revision: 9631f34f5d057f099808e2c93745e4fdf7f88dfe + revision: 24643e55ef34f90427cf00b2da9a57ec064bb966 version: null source: Git: https://github.com/pulp-platform/hier-icache.git diff --git a/Bender.yml b/Bender.yml index 1fbd6180..2d68977b 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,7 +19,7 @@ dependencies: event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: "1.4.1" } mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master - hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "9631f34f5d057f099808e2c93745e4fdf7f88dfe" } # branch: yt/carfield + hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "24643e55ef34f90427cf00b2da9a57ec064bb966" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: a596f17fc77713909bceb7eecf3ea2c3cdfe707c } # branch: yt/bump-hci fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "4aec4b68424947b0c4cf25fd7c4b907cb9ec3dfa" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } From 78c7e4b188151c7790bb1422b9aeeb28f5e0b588 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 14 Aug 2023 16:01:38 +0200 Subject: [PATCH 053/207] Bumped icache and scm. --- Bender.lock | 4 ++-- Bender.yml | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Bender.lock b/Bender.lock index 738b662d..d78aa39f 100644 --- a/Bender.lock +++ b/Bender.lock @@ -122,7 +122,7 @@ packages: - hwpe-stream - l2_tcdm_hybrid_interco hier-icache: - revision: 24643e55ef34f90427cf00b2da9a57ec064bb966 + revision: fac03040e4901daad29c141fc481f7c5d3758e99 version: null source: Git: https://github.com/pulp-platform/hier-icache.git @@ -232,7 +232,7 @@ packages: - fpnew - tech_cells_generic scm: - revision: f7b51416f3c407e4c31e9c016616d57aae2687bd + revision: 74426dee36f28ae1c02f7635cf844a0156145320 version: null source: Git: https://github.com/pulp-platform/scm.git diff --git a/Bender.yml b/Bender.yml index 2d68977b..eaaa7a6a 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,7 +19,7 @@ dependencies: event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: "1.4.1" } mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master - hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "24643e55ef34f90427cf00b2da9a57ec064bb966" } # branch: yt/carfield + hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "fac03040e4901daad29c141fc481f7c5d3758e99" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: a596f17fc77713909bceb7eecf3ea2c3cdfe707c } # branch: yt/bump-hci fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "4aec4b68424947b0c4cf25fd7c4b907cb9ec3dfa" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } @@ -30,7 +30,7 @@ dependencies: riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: dd086242d10f248b4051a1fc67ae2b35b989c29c } # branch: yt/hmr cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: 9b77611 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } - scm: { git: "https://github.com/pulp-platform/scm.git", rev: f7b51416f3c407e4c31e9c016616d57aae2687bd } # branch: yt/bump-clkgating + scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating hci: { git: "https://github.com/pulp-platform/hci.git", rev: b2e6f391aa6c10c03f45b693d80a0aaddecf169b } # branch: master register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } From 3ef692aea035919933aceaa065c4d9a3753c8db6 Mon Sep 17 00:00:00 2001 From: Cyril Koenig Date: Thu, 31 Aug 2023 00:28:24 +0200 Subject: [PATCH 054/207] bender: Put TRACE_EXECUTION under target simulation --- Bender.yml | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/Bender.yml b/Bender.yml index eaaa7a6a..dfab2024 100644 --- a/Bender.yml +++ b/Bender.yml @@ -72,14 +72,11 @@ sources: - rtl/data_periph_demux.sv - rtl/core_demux_wrap.sv # Level 2 - - target: rtl + - rtl/core_region.sv + - target: simulation + files: defines: TRACE_EXECUTION: ~ - files: - - rtl/core_region.sv - - target: not(rtl) - files: - - rtl/core_region.sv # Level 3 - rtl/pulp_cluster.sv From 94450befd0927fc705ab3db49c0cd488ac69476e Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 9 Sep 2023 20:06:54 +0200 Subject: [PATCH 055/207] Added clock gating cell for HWPE Subsystem. --- rtl/hwpe_subsystem.sv | 14 ++++++++++++-- rtl/pulp_cluster.sv | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index 8f5f6a16..9c5cb717 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -26,6 +26,7 @@ module hwpe_subsystem input logic clk, input logic rst_n, input logic test_mode, + input logic hwpe_en_i, hci_core_intf.master hwpe_xbar_master, XBAR_PERIPH_BUS.Slave hwpe_cfg_slave, @@ -34,10 +35,19 @@ module hwpe_subsystem output logic busy_o ); + logic hwpe_clk; + + tc_clk_gating i_hwpe_clock_gate ( + .clk_i ( clk ), + .en_i ( hwpe_en_i ), + .test_en_i ( test_mode ), + .clk_o ( hwpe_clk ) + ); + hwpe_ctrl_intf_periph #( .ID_WIDTH ( ID_WIDTH ) ) periph ( - .clk ( clk ) + .clk ( hwpe_clk ) ); redmule_top #( @@ -45,7 +55,7 @@ module hwpe_subsystem .N_CORES ( N_CORES ), .DW ( N_MASTER_PORT*32 ) ) i_redmule ( - .clk_i ( clk ), + .clk_i ( hwpe_clk ), .rst_ni ( rst_n ), .test_mode_i ( test_mode ), .busy_o ( busy_o ), diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index cbde3f0e..751f5e13 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -1167,6 +1167,7 @@ generate .clk ( clk_i ), .rst_n ( rst_ni ), .test_mode ( test_mode_i ), + .hwpe_en_i ( s_hwpe_en ), .hwpe_xbar_master ( s_hci_hwpe [0] ), .hwpe_cfg_slave ( s_hwpe_cfg_bus ), .evt_o ( s_hwpe_evt ), From 35595ad0d44c43516cb0a1fe7c3e077140e20ced Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 9 Sep 2023 20:17:47 +0200 Subject: [PATCH 056/207] Parametrized AXI XBAR rule in tb. --- tb/pulp_cluster_tb.sv | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 78923f1c..ea0d8931 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -173,12 +173,19 @@ module pulp_cluster_tb; // XBAR localparam int unsigned NumRules = NSlv+1; - typedef axi_pkg::xbar_rule_32_t rule_t; + + typedef struct packed { + int unsigned idx; + logic [AxiAw-1:0] start_addr; + logic [AxiAw-1:0] end_addr; + } rule_t; + + // typedef axi_pkg::xbar_rule_32_t rule_t; rule_t [NumRules-1:0] addr_map; assign addr_map[0] = '{ // UART idx: 0, - start_addr: 32'h4000_0000, - end_addr: 32'h4000_ffff + start_addr: 'h4000_0000, + end_addr: 'h4000_ffff }; assign addr_map[1] = '{ // 512KiB L2SPM idx: 1, @@ -192,8 +199,8 @@ module pulp_cluster_tb; }; assign addr_map[3] = '{ // Return address idx: 1, // Just put it in axi_sim_mem - start_addr: 32'h1A10_4000, - end_addr: 32'h1A10_40F0 + start_addr: 'h1A10_4000, + end_addr: 'h1A10_40F0 }; // Crossbar Configuration and Instantiation localparam axi_pkg::xbar_cfg_t XbarCfg = '{ From d5e826107a72b13424976b2805ef93475606f39f Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 30 Sep 2023 11:11:56 +0200 Subject: [PATCH 057/207] Connected rapid recovery signals to core. --- packages/pulp_cluster_package.sv | 2 -- rtl/core_region.sv | 56 +++++++++++++++++++++++++++++--- rtl/pulp_cluster.sv | 17 +++------- 3 files changed, 55 insertions(+), 20 deletions(-) diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 7bee53a5..88207829 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -88,8 +88,6 @@ package pulp_cluster_package; logic [31:0] data_wdata; logic irq_ack; logic [4:0] irq_ack_id; - // logic debug_havereset; - // logic debug_running; logic debug_halted; logic core_busy; rapid_recovery_pkg::regfile_write_t regfile_backup; diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 63365ef4..c6524c36 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -24,6 +24,7 @@ //`define DUMP_INSTR_FETCH module core_region +import rapid_recovery_pkg::*; #( // CORE PARAMETERS parameter CORE_TYPE_CL = 0, // 0 for CV32, 1 RI5CY, 2 for IBEX RV32IMC @@ -88,6 +89,12 @@ module core_region output logic debug_havereset_o, output logic debug_running_o, output logic debug_halted_o, + // Recovery bus + input rapid_recovery_pkg::rapid_recovery_t recovery_bus_i, + // Backup bus + output rapid_recovery_pkg::regfile_write_t regfile_backup_o, + output rapid_recovery_pkg::pc_intf_t pc_backup_o, + output rapid_recovery_pkg::csrs_intf_t csr_backup_o, input logic [N_EXT_PERF_COUNTERS-1:0] ext_perf_i, @@ -285,18 +292,57 @@ module core_region .sec_lvl_o ( ), // Debug Interface .debug_req_i ( debug_req_i ), - // .debug_havereset_o ( debug_havereset_o ), // Useful for HMR - // .debug_running_o ( debug_running_o ), // Useful for HMR - // .debug_halted_o ( debug_halted_o ), // Useful for HMR + .debug_mode_o ( debug_halted_o ), // Yet other control signals .fetch_enable_i ( fetch_en_i ), .core_busy_o ( core_busy_o ), // External performance monitoring signals - .ext_perf_counters_i ( ext_perf_i ) + .ext_perf_counters_i ( ext_perf_i ), + // RF recovery ports + .recover_i ( recovery_bus_i.rf_recovery_en ), + // Write port A + .regfile_waddr_a_i ( recovery_bus_i.rf_recovery_wdata.waddr_a ), + .regfile_wdata_a_i ( recovery_bus_i.rf_recovery_wdata.wdata_a ), + .regfile_we_a_i ( recovery_bus_i.rf_recovery_wdata.we_a ), + // Write port B + .regfile_waddr_b_i ( recovery_bus_i.rf_recovery_wdata.waddr_b ), + .regfile_wdata_b_i ( recovery_bus_i.rf_recovery_wdata.wdata_b ), + .regfile_we_b_i ( recovery_bus_i.rf_recovery_wdata.we_b ), + // Outputs from RF + // Port A + .regfile_we_a_o ( regfile_backup_o.we_a ), + .regfile_waddr_a_o ( regfile_backup_o.waddr_a ), + .regfile_wdata_a_o ( regfile_backup_o.wdata_a ), + // Port B + .regfile_we_b_o ( regfile_backup_o.we_b ), + .regfile_waddr_b_o ( regfile_backup_o.waddr_b ), + .regfile_wdata_b_o ( regfile_backup_o.wdata_b ), + // Program Counter Backup + .backup_program_counter_o ( pc_backup_o.program_counter ), + .backup_branch_o ( pc_backup_o.is_branch ), + .backup_branch_addr_o ( pc_backup_o.branch_addr ), + // Program Counter Recovery + .pc_recover_i ( recovery_bus_i.pc_recovery_en ), + .recovery_program_counter_i ( recovery_bus_i.pc_recovery.program_counter ), + .recovery_branch_i ( recovery_bus_i.pc_recovery.is_branch ), + .recovery_branch_addr_i ( recovery_bus_i.pc_recovery.branch_addr ), + // CSRs Backup + .backup_mstatus_o ( csr_backup_o.csr_mstatus ), + .backup_mtvec_o ( csr_backup_o.csr_mtvec ), + .backup_mscratch_o ( csr_backup_o.csr_mscratch ), + .backup_mepc_o ( csr_backup_o.csr_mepc ), + .backup_mcause_o ( csr_backup_o.csr_mcause ), + // CSRs Recovery + .recovery_mstatus_i ( recovery_bus_i.csr_recovery.csr_mstatus ), + .recovery_mtvec_i ( recovery_bus_i.csr_recovery.csr_mtvec ), + .recovery_mscratch_i ( recovery_bus_i.csr_recovery.csr_mscratch ), + .recovery_mepc_i ( recovery_bus_i.csr_recovery.csr_mepc ), + .recovery_mcause_i ( recovery_bus_i.csr_recovery.csr_mcause ) ); assign debug_havereset_o = '0; assign debug_running_o = '0; - assign debug_halted_o = '0; + assign csr_backup_o.csr_mie = '0; + assign csr_backup_o.csr_mip = '0; end else begin: IBEX_CORE assign boot_addr = boot_addr_i & 32'hFFFFFF00; // RI5CY expects 0x80 offset, Ibex expects 0x00 offset (adds reset offset 0x80 internally) // Core busy diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 751f5e13..ce37847c 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -932,22 +932,17 @@ generate //debug unit bind .debug_req_i ( recovery_bus[i].debug_req | s_core_dbg_irq[i] ), - // .debug_halted_o ( dbg_core_halted[i] ), .debug_halted_o ( core2hmr[i].debug_halted ), .debug_havereset_o ( dbg_core_havereset[i] ), .debug_running_o ( dbg_core_running[i] ), .ext_perf_i ( ext_perf[i] ), .core_data_req_o ( core_data_req[i] ), .core_data_rsp_i ( core_data_rsp[i] ), - // .debug_resume_i ( recovery_bus[i].debug_resume ), // Useful for HMR, consider keeping //HMR Recovery Bus - // .csr_recovery_i ( recovery_bus[i].csr_recovery ), - // .pc_recovery_i ( recovery_bus[i].pc_recovery ), - // .instr_lock_i ( recovery_bus[i].instr_lock ), - // .pc_recovery_en ( recovery_bus[i].pc_recovery_en ), - // .rf_recovery_en ( recovery_bus[i].rf_recovery_en ), - // .rf_recovery_wdata ( recovery_bus[i].rf_recovery_wdata ), - // .rf_recovery_rdata ( recovery_bus[i].rf_recovery_rdata ), + .recovery_bus_i ( recovery_bus[i] ), + .regfile_backup_o ( core2hmr[i].regfile_backup ), + .pc_backup_o ( core2hmr[i].pc_backup ), + .csr_backup_o ( core2hmr[i].csr_backup ), //apu interface .apu_master_req_o ( s_apu_master_req [i] ), .apu_master_gnt_i ( s_apu_master_gnt [i] ), @@ -999,10 +994,6 @@ generate assign core2hmr[i].data_wdata = core_data_req[i].data; assign core2hmr[i].data_be = core_data_req[i].be; - assign core2hmr[i].regfile_backup = '0; - assign core2hmr[i].csr_backup = '0; - assign core2hmr[i].pc_backup = '0; - core_demux_wrap #( .AddrWidth ( ADDR_WIDTH ), .DataWidth ( DATA_WIDTH ), From e559028e72e9d41b6fba727843667d9d2ab8c3c6 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 30 Sep 2023 11:12:56 +0200 Subject: [PATCH 058/207] Bump IPs to align dependencies; adaptx TB XBAR rules to make printf work (to be fixed and aligned with Carfield memory map). --- Bender.lock | 20 ++++++-------------- Bender.yml | 8 ++++---- tb/pulp_cluster_tb.sv | 8 ++++---- 3 files changed, 14 insertions(+), 22 deletions(-) diff --git a/Bender.lock b/Bender.lock index d78aa39f..a4480a4c 100644 --- a/Bender.lock +++ b/Bender.lock @@ -60,8 +60,8 @@ packages: dependencies: - hci common_cells: - revision: 53b0b58af2db5bd3c850a7038fae170ed78326bb - version: 1.31.1 + revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f + version: 1.32.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -74,7 +74,7 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cv32e40p: - revision: 9b77611a1d0c681f4819798d95422b0b895528a2 + revision: e863f576699815b38cc9d80dbdede8ed5efd5991 version: null source: Git: https://github.com/pulp-platform/cv32e40p.git @@ -90,7 +90,7 @@ packages: dependencies: - common_cells fpnew: - revision: f231041c610f270ffc03cbdac38739ddb6426572 + revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 version: null source: Git: https://github.com/pulp-platform/cvfpu.git @@ -104,14 +104,6 @@ packages: Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git dependencies: - common_cells - fpu_interco: - revision: 4aec4b68424947b0c4cf25fd7c4b907cb9ec3dfa - version: null - source: - Git: https://github.com/pulp-platform/fpu_interco.git - dependencies: - - fpnew - - riscv hci: revision: b2e6f391aa6c10c03f45b693d80a0aaddecf169b version: null @@ -191,7 +183,7 @@ packages: dependencies: - axi_slice redmule: - revision: 886ad5ecf5fd908e0c0b278c22914a76a704eda3 + revision: 80a5acb543b1626c9627cf5e64e0d84bca1848ba version: null source: Git: https://github.com/pulp-platform/redmule.git @@ -224,7 +216,7 @@ packages: - common_cells - common_verification riscv: - revision: dd086242d10f248b4051a1fc67ae2b35b989c29c + revision: ae45f76e316f19782037b5629ab5f159fd1d0d4c version: null source: Git: git@github.com:AlSaqr-platform/riscv_nn.git diff --git a/Bender.yml b/Bender.yml index dfab2024..86903413 100644 --- a/Bender.yml +++ b/Bender.yml @@ -21,21 +21,21 @@ dependencies: idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "fac03040e4901daad29c141fc481f7c5d3758e99" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: a596f17fc77713909bceb7eecf3ea2c3cdfe707c } # branch: yt/bump-hci - fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "4aec4b68424947b0c4cf25fd7c4b907cb9ec3dfa" } # branch: yt/carfield + # fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "4aec4b68424947b0c4cf25fd7c4b907cb9ec3dfa" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: dd086242d10f248b4051a1fc67ae2b35b989c29c } # branch: yt/hmr - cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: 9b77611 } # `michaero/safety-island-clic` branch + riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: ae45f76e316f19782037b5629ab5f159fd1d0d4c } # branch: yt/hmr + cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating hci: { git: "https://github.com/pulp-platform/hci.git", rev: b2e6f391aa6c10c03f45b693d80a0aaddecf169b } # branch: master register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 482d2f5ed05f25c851f4048f1bd402cc0d2b58b6 } # branch: yt/rapidrecovery - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 886ad5ecf5fd908e0c0b278c22914a76a704eda3 } # branch: carfield + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 80a5acb543b1626c9627cf5e64e0d84bca1848ba } # branch: carfield export_include_dirs: - include diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index ea0d8931..cd575bc2 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -62,7 +62,7 @@ module pulp_cluster_tb; localparam bit[ 5:0] ClustIdx = 'h1; localparam bit[AxiAw-1:0] ClustBaseAddr = ClustBase; localparam bit[AxiAw-1:0] L2BaseAddr = 'h78000000; - localparam bit[AxiAw-1:0] L2Size = 'h00100000; + localparam bit[AxiAw-1:0] L2Size = 'h10000000; localparam bit[AxiAw-1:0] BootAddr = L2BaseAddr + 'h8080; typedef logic [AxiAw-1:0] axi_addr_t; @@ -184,8 +184,8 @@ module pulp_cluster_tb; rule_t [NumRules-1:0] addr_map; assign addr_map[0] = '{ // UART idx: 0, - start_addr: 'h4000_0000, - end_addr: 'h4000_ffff + start_addr: 'h6000_0000, // FIXME: Adjust with Carfield memory map + end_addr: 'h6000_ffff }; assign addr_map[1] = '{ // 512KiB L2SPM idx: 1, @@ -199,7 +199,7 @@ module pulp_cluster_tb; }; assign addr_map[3] = '{ // Return address idx: 1, // Just put it in axi_sim_mem - start_addr: 'h1A10_4000, + start_addr: 'h1A10_4000, // FIXME: Adjust with Carfield memory map end_addr: 'h1A10_40F0 }; // Crossbar Configuration and Instantiation From 53d4751499039a2de2d0a1b75b1bbc433f60c918 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 30 Sep 2023 11:25:41 +0200 Subject: [PATCH 059/207] Making ROM_BOOT_ADDR same as BOOT_ADDR. --- tb/pulp_cluster_tb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index cd575bc2..c0e77415 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -290,7 +290,7 @@ module pulp_cluster_tb; .CACHE_LINE ( 1 ), .CACHE_SIZE ( 4*1024 ), .L2_SIZE ( 32'h100000 ), - .ROM_BOOT_ADDR ( 32'h1A000000 ), + .ROM_BOOT_ADDR ( BootAddr ), .BOOT_ADDR ( BootAddr ), .INSTR_RDATA_WIDTH ( 32 ), .CLUST_FPU ( 0 ), From d2512d27c09862e83f7b1afffd4fe16ad3218992 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 30 Sep 2023 18:33:39 +0200 Subject: [PATCH 060/207] Bump core commit. --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index a4480a4c..b18f401b 100644 --- a/Bender.lock +++ b/Bender.lock @@ -216,7 +216,7 @@ packages: - common_cells - common_verification riscv: - revision: ae45f76e316f19782037b5629ab5f159fd1d0d4c + revision: f0565371c1ceeb3d5cf50098b227bf3333f5fbed version: null source: Git: git@github.com:AlSaqr-platform/riscv_nn.git diff --git a/Bender.yml b/Bender.yml index 86903413..fec1b3ae 100644 --- a/Bender.yml +++ b/Bender.yml @@ -27,7 +27,7 @@ dependencies: timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: ae45f76e316f19782037b5629ab5f159fd1d0d4c } # branch: yt/hmr + riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: f0565371c1ceeb3d5cf50098b227bf3333f5fbed } # branch: yt/hmr cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating From 5976664aea55e3f5191ab5b8565c3bbffebca076 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 1 Oct 2023 10:20:49 +0200 Subject: [PATCH 061/207] Bumped RedMulE commit. --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index b18f401b..2053ef21 100644 --- a/Bender.lock +++ b/Bender.lock @@ -183,7 +183,7 @@ packages: dependencies: - axi_slice redmule: - revision: 80a5acb543b1626c9627cf5e64e0d84bca1848ba + revision: 0fe14edd77e9a35d3d220bd78bd6b41a0e5935ea version: null source: Git: https://github.com/pulp-platform/redmule.git diff --git a/Bender.yml b/Bender.yml index fec1b3ae..ac2301c7 100644 --- a/Bender.yml +++ b/Bender.yml @@ -35,7 +35,7 @@ dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 482d2f5ed05f25c851f4048f1bd402cc0d2b58b6 } # branch: yt/rapidrecovery - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 80a5acb543b1626c9627cf5e64e0d84bca1848ba } # branch: carfield + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 0fe14edd77e9a35d3d220bd78bd6b41a0e5935ea } # branch: carfield export_include_dirs: - include From 360c120c50d88a7ec6f32d84b0d48815039584d1 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 2 Oct 2023 08:37:40 +0200 Subject: [PATCH 062/207] Bumped core commit. --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index 2053ef21..f22ed745 100644 --- a/Bender.lock +++ b/Bender.lock @@ -216,7 +216,7 @@ packages: - common_cells - common_verification riscv: - revision: f0565371c1ceeb3d5cf50098b227bf3333f5fbed + revision: 6c56a943f272e987968a53df6dca095f939c1915 version: null source: Git: git@github.com:AlSaqr-platform/riscv_nn.git diff --git a/Bender.yml b/Bender.yml index ac2301c7..f609dc0b 100644 --- a/Bender.yml +++ b/Bender.yml @@ -27,7 +27,7 @@ dependencies: timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: f0565371c1ceeb3d5cf50098b227bf3333f5fbed } # branch: yt/hmr + riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 6c56a943f272e987968a53df6dca095f939c1915 } # branch: yt/hmr cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating From 16839e27a7f4a0d96376f89ea97a5e19951e657f Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 3 Oct 2023 13:08:30 +0200 Subject: [PATCH 063/207] Allowed access to the entire external address space and aligned standard out with Carfield. --- rtl/cluster_bus_wrap.sv | 8 ++++++-- tb/pulp_cluster_tb.sv | 4 ++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index 0cafebda..bd03a31d 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -102,10 +102,9 @@ module cluster_bus_wrap // address map logic [31:0] cluster_base_addr; assign cluster_base_addr = BaseAddr + ( cluster_id_i << 22); - localparam int unsigned N_RULES = 3; + localparam int unsigned N_RULES = 4; addr_map_rule_t [N_RULES-1:0] addr_map; - assign addr_map[0] = '{ // TCDM idx: 0, start_addr: cluster_base_addr, @@ -121,6 +120,11 @@ module cluster_bus_wrap start_addr: cluster_base_addr + ClusterExternalOffs, end_addr: 32'hFFFF_FFFF }; + assign addr_map[3] = '{ // everything below cluster + idx: 2, + start_addr: 'h0, + end_addr: cluster_base_addr + }; localparam int unsigned MAX_TXNS_PER_SLV_PORT = (DMA_NB_OUTSND_BURSTS > NB_CORES) ? DMA_NB_OUTSND_BURSTS : NB_CORES; diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index c0e77415..897edcb0 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -184,8 +184,8 @@ module pulp_cluster_tb; rule_t [NumRules-1:0] addr_map; assign addr_map[0] = '{ // UART idx: 0, - start_addr: 'h6000_0000, // FIXME: Adjust with Carfield memory map - end_addr: 'h6000_ffff + start_addr: 'h03002000, + end_addr: 'h03003000 }; assign addr_map[1] = '{ // 512KiB L2SPM idx: 1, From 8356888056441d6cf5b94e348a0817264b9b1b8c Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 6 Oct 2023 16:27:04 +0200 Subject: [PATCH 064/207] Fixed connections to HMR unit and cluster peripherals. --- Bender.lock | 4 +-- Bender.yml | 4 +-- rtl/cluster_peripherals.sv | 15 ++++++++-- rtl/core_region.sv | 4 ++- rtl/pulp_cluster.sv | 60 +++++++++++++++++++++++++++++++------- 5 files changed, 69 insertions(+), 18 deletions(-) diff --git a/Bender.lock b/Bender.lock index f22ed745..9260fec1 100644 --- a/Bender.lock +++ b/Bender.lock @@ -83,7 +83,7 @@ packages: - fpnew - tech_cells_generic event_unit_flex: - revision: 53fb3a1093aaaedfe883739fd8a3155d601210bc + revision: 28e0499374117c7b0ef4c6ad81b60d7526af886f version: null source: Git: https://github.com/pulp-platform/event_unit_flex.git @@ -196,7 +196,7 @@ packages: - hwpe-stream - tech_cells_generic redundancy_cells: - revision: 482d2f5ed05f25c851f4048f1bd402cc0d2b58b6 + revision: f206f5ecbfaa028f9eae6f0efaed9e34631d9171 version: null source: Git: https://github.com/pulp-platform/redundancy_cells.git diff --git a/Bender.yml b/Bender.yml index f609dc0b..369a5205 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,7 +16,7 @@ dependencies: axi2per: { git: "https://github.com/pulp-platform/axi2per.git", version: 1.0.1 } per2axi: { git: "https://github.com/pulp-platform/per2axi.git", version: 1.0.4 } cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix - event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: "1.4.1" } + event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "fac03040e4901daad29c141fc481f7c5d3758e99" } # branch: yt/carfield @@ -34,7 +34,7 @@ dependencies: hci: { git: "https://github.com/pulp-platform/hci.git", rev: b2e6f391aa6c10c03f45b693d80a0aaddecf169b } # branch: master register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } - redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 482d2f5ed05f25c851f4048f1bd402cc0d2b58b6 } # branch: yt/rapidrecovery + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: f206f5ecbfaa028f9eae6f0efaed9e34631d9171 } # branch: yt/rapidrecovery redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 0fe14edd77e9a35d3d220bd78bd6b41a0e5935ea } # branch: carfield export_include_dirs: diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index ec64825a..d2d73c58 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -31,7 +31,8 @@ module cluster_peripherals parameter EVNT_WIDTH = 8, parameter FEATURE_DEMUX_MAPPED = 1, parameter int unsigned NB_L1_CUTS = 16, - parameter int unsigned RW_MARGIN_WIDTH = 4 + parameter int unsigned RW_MARGIN_WIDTH = 4, + parameter int unsigned NB_BARRIERS = NB_CORES ) ( input logic clk_i, @@ -84,6 +85,11 @@ module cluster_peripherals input logic [NB_CORES-1:0] dbg_req_i, output logic [NB_CORES-1:0] dbg_req_o, + output logic [NB_BARRIERS-1:0] barrier_matched_o, + + // HMR synch requests + input logic [NB_CORES-1:0] hmr_sw_resynch_req_i, + input logic [NB_CORES-1:0] hmr_sw_synch_req_i, // SRAM SPEED REGULATION --> TCDM output logic [1:0] TCDM_arb_policy_o, @@ -136,7 +142,10 @@ module cluster_peripherals // decide between common or core-specific event sources generate for (genvar I=0; I Date: Tue, 10 Oct 2023 09:27:11 +0200 Subject: [PATCH 065/207] Bump redundancy cells for FF-based recovery RF. --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index 9260fec1..f7000edf 100644 --- a/Bender.lock +++ b/Bender.lock @@ -196,7 +196,7 @@ packages: - hwpe-stream - tech_cells_generic redundancy_cells: - revision: f206f5ecbfaa028f9eae6f0efaed9e34631d9171 + revision: 257344b589b151844d85d04279a89f65183c7741 version: null source: Git: https://github.com/pulp-platform/redundancy_cells.git diff --git a/Bender.yml b/Bender.yml index 369a5205..f665bb71 100644 --- a/Bender.yml +++ b/Bender.yml @@ -34,7 +34,7 @@ dependencies: hci: { git: "https://github.com/pulp-platform/hci.git", rev: b2e6f391aa6c10c03f45b693d80a0aaddecf169b } # branch: master register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } - redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: f206f5ecbfaa028f9eae6f0efaed9e34631d9171 } # branch: yt/rapidrecovery + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 257344b589b151844d85d04279a89f65183c7741 } # branch: yt/rapidrecovery redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 0fe14edd77e9a35d3d220bd78bd6b41a0e5935ea } # branch: carfield export_include_dirs: From 188d6c1ba31a3ab7c1a52053a9126cbab9904142 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 11 Oct 2023 17:49:13 +0200 Subject: [PATCH 066/207] Making default parameters same as in carfield istance. --- rtl/cluster_bus_wrap.sv | 12 +-- rtl/pulp_cluster.sv | 42 +++++------ tb/pulp_cluster_tb.sv | 162 ++++++++++++++++++++++------------------ 3 files changed, 118 insertions(+), 98 deletions(-) diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index bd03a31d..f9c07db9 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -25,15 +25,15 @@ module cluster_bus_wrap #( parameter int unsigned NB_MASTER = 3 , parameter int unsigned NB_SLAVE = 4 , - parameter int unsigned NB_CORES = 4 , - parameter int unsigned AXI_ADDR_WIDTH = 32 , + parameter int unsigned NB_CORES = 12 , + parameter int unsigned AXI_ADDR_WIDTH = 48 , parameter int unsigned AXI_DATA_WIDTH = 64 , parameter int unsigned AXI_ID_IN_WIDTH = 4 , parameter int unsigned AXI_ID_OUT_WIDTH = 6 , - parameter int unsigned AXI_USER_WIDTH = 6 , + parameter int unsigned AXI_USER_WIDTH = 10 , parameter int unsigned DMA_NB_OUTSND_BURSTS = 8 , - parameter int unsigned TCDM_SIZE = 0 , - parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h10000000, + parameter int unsigned TCDM_SIZE = 256*1024 , + parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h50000000, parameter logic [AXI_ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, parameter logic [AXI_ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000 )( @@ -100,7 +100,7 @@ module cluster_bus_wrap } addr_map_rule_t; // address map - logic [31:0] cluster_base_addr; + logic [AXI_ADDR_WIDTH-1:0] cluster_base_addr; assign cluster_base_addr = BaseAddr + ( cluster_id_i << 22); localparam int unsigned N_RULES = 4; addr_map_rule_t [N_RULES-1:0] addr_map; diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index e5a6aef6..59b3cd8e 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -30,7 +30,7 @@ module pulp_cluster #( // cluster parameters parameter CORE_TYPE_CL = 1, // 0 for CV32, 1 for RI5CY, 2 for IBEX RV32IMC - parameter NB_CORES = 8, + parameter NB_CORES = 12, parameter NB_HWPE_PORTS = 9, // number of DMA TCDM plugs, NOT number of DMA slave peripherals! // Everything will go to hell if you change this! @@ -38,57 +38,57 @@ module pulp_cluster parameter NB_MPERIPHS = 1, parameter NB_SPERIPHS = 10, - parameter CLUSTER_ALIAS = 1, - parameter CLUSTER_ALIAS_BASE = 12'h000, + parameter CLUSTER_ALIAS = 1, // to be checked, we do not want it + parameter CLUSTER_ALIAS_BASE = 12'h000, // to be checked, we do not want it - parameter int unsigned SynchStages = 2, + parameter int unsigned SynchStages = 3, - parameter TCDM_SIZE = 64*1024, // [B], must be 2**N + parameter TCDM_SIZE = 256*1024, // [B], must be 2**N parameter NB_TCDM_BANKS = 16, // must be 2**N parameter TCDM_BANK_SIZE = TCDM_SIZE/NB_TCDM_BANKS, // [B] parameter TCDM_NUM_ROWS = TCDM_BANK_SIZE/4, // [words] - parameter HWPE_PRESENT = 0, // set to 1 if HW Processing Engines are present in the cluster + parameter HWPE_PRESENT = 1, // set to 1 if HW Processing Engines are present in the cluster parameter USE_HETEROGENEOUS_INTERCONNECT = 1, // set to 1 to connect HWPEs via heterogeneous interconnect; to 0 for larger LIC // I$ parameters parameter SET_ASSOCIATIVE = 4, parameter NB_CACHE_BANKS = 2, parameter CACHE_LINE = 1, - parameter CACHE_SIZE = 4096, + parameter CACHE_SIZE = 4*1024, parameter ICACHE_DATA_WIDTH = 128, parameter L0_BUFFER_FEATURE = "DISABLED", parameter MULTICAST_FEATURE = "DISABLED", parameter SHARED_ICACHE = "ENABLED", parameter DIRECT_MAPPED_FEATURE = "DISABLED", - parameter L2_SIZE = 512*1024, + parameter L2_SIZE = 2**20, parameter USE_REDUCED_TAG = "TRUE", // core parameters - parameter DEBUG_START_ADDR = 32'h1A110000, - parameter ROM_BOOT_ADDR = 32'h1A000000, - parameter BOOT_ADDR = 32'h1C000000, + parameter DEBUG_START_ADDR = 32'h60203000, + parameter ROM_BOOT_ADDR = 32'h78000000, + parameter BOOT_ADDR = 32'h78000000, parameter INSTR_RDATA_WIDTH = 32, - parameter CLUST_FPU = 1, - parameter CLUST_FP_DIVSQRT = 1, - parameter CLUST_SHARED_FP = 2, - parameter CLUST_SHARED_FP_DIVSQRT = 2, + parameter CLUST_FPU = 0, + parameter CLUST_FP_DIVSQRT = 0, + parameter CLUST_SHARED_FP = 0, + parameter CLUST_SHARED_FP_DIVSQRT = 0, // AXI parameters parameter int unsigned NumAxiMst = 3 , parameter int unsigned NumAxiSlv = 4 , - parameter AXI_ADDR_WIDTH = 32, + parameter AXI_ADDR_WIDTH = 48, parameter AXI_DATA_C2S_WIDTH = 64, - parameter AXI_DATA_S2C_WIDTH = 32, - parameter AXI_USER_WIDTH = 6, - parameter AXI_ID_IN_WIDTH = 5, - parameter AXI_ID_OUT_WIDTH = 7, + parameter AXI_DATA_S2C_WIDTH = 64, + parameter AXI_USER_WIDTH = 10, + parameter AXI_ID_IN_WIDTH = 4, + parameter AXI_ID_OUT_WIDTH = AXI_ID_IN_WIDTH + $clog2(NumAxiSlv), parameter AXI_STRB_C2S_WIDTH = AXI_DATA_C2S_WIDTH/8, parameter AXI_STRB_S2C_WIDTH = AXI_DATA_S2C_WIDTH/8, parameter DC_SLICE_BUFFER_WIDTH = 8, parameter LOG_DEPTH = 3, parameter int unsigned CdcSynchStages = 3, - parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h10000000, + parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h50000000, parameter logic [AXI_ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, parameter logic [AXI_ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000, // CLUSTER TO SOC CDC AXI PARAMETER diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 897edcb0..9b8681de 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -54,7 +54,7 @@ module pulp_cluster_tb; localparam AxiIwMst = AxiIw + $clog2(NMst); localparam AxiWideBeWidth = AxiDw/8; localparam AxiWideByteOffset = $clog2(AxiWideBeWidth); - localparam AxiUw = 2; + localparam AxiUw = 10; localparam bit[AxiAw-1:0] ClustBase = 'h50000000; localparam bit[AxiAw-1:0] ClustPeriphOffs = 'h00200000; @@ -273,7 +273,9 @@ module pulp_cluster_tb; .dst ( axi_slave[1] ) ); - pulp_cluster #( + pulp_cluster +`ifdef USE_PULP_PARAMETERS + #( .NB_CORES ( `NB_CORES ), .NB_HWPE_PORTS ( 9 ), .NB_DMAS ( `NB_DMAS ), @@ -308,73 +310,75 @@ module pulp_cluster_tb; .ClusterPeripheralsOffs ( ClustPeriphOffs ), .ClusterExternalOffs ( ClustExtOffs ), .CdcSynchStages ( 3 ) - ) cluster_i ( - .clk_i ( s_clk ), - .rst_ni ( s_rstn ), - .pwr_on_rst_ni ( s_rstn ), - .ref_clk_i ( s_clk ), - .axi_isolate_i ( '0 ), - .axi_isolated_o ( ), - - .pmu_mem_pwdn_i ( 1'b0 ), - - .base_addr_i ( ClustBase[31:28] ), - - .dma_pe_evt_ack_i ( '1 ), - .dma_pe_evt_valid_o ( ), - - .dma_pe_irq_ack_i ( 1'b1 ), - .dma_pe_irq_valid_o ( ), - - .dbg_irq_valid_i ( '0 ), - .mbox_irq_i ( '0 ), - - .pf_evt_ack_i ( 1'b1 ), - .pf_evt_valid_o ( ), - - .async_cluster_events_wptr_i ( '0 ), - .async_cluster_events_rptr_o ( ), - .async_cluster_events_data_i ( '0 ), - - .en_sa_boot_i ( s_cluster_en_sa_boot ), - .test_mode_i ( 1'b0 ), - .fetch_en_i ( s_cluster_fetch_en ), - .eoc_o ( s_cluster_eoc ), - .busy_o ( s_cluster_busy ), - .cluster_id_i ( ClustIdx ), - - .async_data_master_aw_wptr_o ( async_cluster_to_soc_axi_bus.aw_wptr ), - .async_data_master_aw_rptr_i ( async_cluster_to_soc_axi_bus.aw_rptr ), - .async_data_master_aw_data_o ( async_cluster_to_soc_axi_bus.aw_data ), - .async_data_master_ar_wptr_o ( async_cluster_to_soc_axi_bus.ar_wptr ), - .async_data_master_ar_rptr_i ( async_cluster_to_soc_axi_bus.ar_rptr ), - .async_data_master_ar_data_o ( async_cluster_to_soc_axi_bus.ar_data ), - .async_data_master_w_data_o ( async_cluster_to_soc_axi_bus.w_data ), - .async_data_master_w_wptr_o ( async_cluster_to_soc_axi_bus.w_wptr ), - .async_data_master_w_rptr_i ( async_cluster_to_soc_axi_bus.w_rptr ), - .async_data_master_r_wptr_i ( async_cluster_to_soc_axi_bus.r_wptr ), - .async_data_master_r_rptr_o ( async_cluster_to_soc_axi_bus.r_rptr ), - .async_data_master_r_data_i ( async_cluster_to_soc_axi_bus.r_data ), - .async_data_master_b_wptr_i ( async_cluster_to_soc_axi_bus.b_wptr ), - .async_data_master_b_rptr_o ( async_cluster_to_soc_axi_bus.b_rptr ), - .async_data_master_b_data_i ( async_cluster_to_soc_axi_bus.b_data ), - - .async_data_slave_aw_wptr_i ( async_soc_to_cluster_axi_bus.aw_wptr ), - .async_data_slave_aw_rptr_o ( async_soc_to_cluster_axi_bus.aw_rptr ), - .async_data_slave_aw_data_i ( async_soc_to_cluster_axi_bus.aw_data ), - .async_data_slave_ar_wptr_i ( async_soc_to_cluster_axi_bus.ar_wptr ), - .async_data_slave_ar_rptr_o ( async_soc_to_cluster_axi_bus.ar_rptr ), - .async_data_slave_ar_data_i ( async_soc_to_cluster_axi_bus.ar_data ), - .async_data_slave_w_data_i ( async_soc_to_cluster_axi_bus.w_data ), - .async_data_slave_w_wptr_i ( async_soc_to_cluster_axi_bus.w_wptr ), - .async_data_slave_w_rptr_o ( async_soc_to_cluster_axi_bus.w_rptr ), - .async_data_slave_r_wptr_o ( async_soc_to_cluster_axi_bus.r_wptr ), - .async_data_slave_r_rptr_i ( async_soc_to_cluster_axi_bus.r_rptr ), - .async_data_slave_r_data_o ( async_soc_to_cluster_axi_bus.r_data ), - .async_data_slave_b_wptr_o ( async_soc_to_cluster_axi_bus.b_wptr ), - .async_data_slave_b_rptr_i ( async_soc_to_cluster_axi_bus.b_rptr ), - .async_data_slave_b_data_o ( async_soc_to_cluster_axi_bus.b_data ) - ); + ) +`endif + cluster_i ( + .clk_i ( s_clk ), + .rst_ni ( s_rstn ), + .pwr_on_rst_ni ( s_rstn ), + .ref_clk_i ( s_clk ), + .axi_isolate_i ( '0 ), + .axi_isolated_o ( ), + + .pmu_mem_pwdn_i ( 1'b0 ), + + .base_addr_i ( ClustBase[31:28] ), + + .dma_pe_evt_ack_i ( '1 ), + .dma_pe_evt_valid_o ( ), + + .dma_pe_irq_ack_i ( 1'b1 ), + .dma_pe_irq_valid_o ( ), + + .dbg_irq_valid_i ( '0 ), + .mbox_irq_i ( '0 ), + + .pf_evt_ack_i ( 1'b1 ), + .pf_evt_valid_o ( ), + + .async_cluster_events_wptr_i ( '0 ), + .async_cluster_events_rptr_o ( ), + .async_cluster_events_data_i ( '0 ), + + .en_sa_boot_i ( s_cluster_en_sa_boot ), + .test_mode_i ( 1'b0 ), + .fetch_en_i ( s_cluster_fetch_en ), + .eoc_o ( s_cluster_eoc ), + .busy_o ( s_cluster_busy ), + .cluster_id_i ( ClustIdx ), + + .async_data_master_aw_wptr_o ( async_cluster_to_soc_axi_bus.aw_wptr ), + .async_data_master_aw_rptr_i ( async_cluster_to_soc_axi_bus.aw_rptr ), + .async_data_master_aw_data_o ( async_cluster_to_soc_axi_bus.aw_data ), + .async_data_master_ar_wptr_o ( async_cluster_to_soc_axi_bus.ar_wptr ), + .async_data_master_ar_rptr_i ( async_cluster_to_soc_axi_bus.ar_rptr ), + .async_data_master_ar_data_o ( async_cluster_to_soc_axi_bus.ar_data ), + .async_data_master_w_data_o ( async_cluster_to_soc_axi_bus.w_data ), + .async_data_master_w_wptr_o ( async_cluster_to_soc_axi_bus.w_wptr ), + .async_data_master_w_rptr_i ( async_cluster_to_soc_axi_bus.w_rptr ), + .async_data_master_r_wptr_i ( async_cluster_to_soc_axi_bus.r_wptr ), + .async_data_master_r_rptr_o ( async_cluster_to_soc_axi_bus.r_rptr ), + .async_data_master_r_data_i ( async_cluster_to_soc_axi_bus.r_data ), + .async_data_master_b_wptr_i ( async_cluster_to_soc_axi_bus.b_wptr ), + .async_data_master_b_rptr_o ( async_cluster_to_soc_axi_bus.b_rptr ), + .async_data_master_b_data_i ( async_cluster_to_soc_axi_bus.b_data ), + + .async_data_slave_aw_wptr_i ( async_soc_to_cluster_axi_bus.aw_wptr ), + .async_data_slave_aw_rptr_o ( async_soc_to_cluster_axi_bus.aw_rptr ), + .async_data_slave_aw_data_i ( async_soc_to_cluster_axi_bus.aw_data ), + .async_data_slave_ar_wptr_i ( async_soc_to_cluster_axi_bus.ar_wptr ), + .async_data_slave_ar_rptr_o ( async_soc_to_cluster_axi_bus.ar_rptr ), + .async_data_slave_ar_data_i ( async_soc_to_cluster_axi_bus.ar_data ), + .async_data_slave_w_data_i ( async_soc_to_cluster_axi_bus.w_data ), + .async_data_slave_w_wptr_i ( async_soc_to_cluster_axi_bus.w_wptr ), + .async_data_slave_w_rptr_o ( async_soc_to_cluster_axi_bus.w_rptr ), + .async_data_slave_r_wptr_o ( async_soc_to_cluster_axi_bus.r_wptr ), + .async_data_slave_r_rptr_i ( async_soc_to_cluster_axi_bus.r_rptr ), + .async_data_slave_r_data_o ( async_soc_to_cluster_axi_bus.r_data ), + .async_data_slave_b_wptr_o ( async_soc_to_cluster_axi_bus.b_wptr ), + .async_data_slave_b_rptr_i ( async_soc_to_cluster_axi_bus.b_rptr ), + .async_data_slave_b_data_o ( async_soc_to_cluster_axi_bus.b_data ) + ); // Load ELF binary file task load_binary; @@ -480,11 +484,27 @@ module pulp_cluster_tb; axi_master_drv.recv_b(b_beat); $display("[TB] Launch cluster\n"); - + + for (int i = 0; i < `NB_CORES; i++) begin + aw_beat.ax_addr = 32'h50200040 + i*4; + aw_beat.ax_len = '0; + aw_beat.ax_burst = axi_pkg::BURST_INCR; + aw_beat.ax_size = 4'h3; + + w_beat.w_data = 'h78008080; + w_beat.w_strb = 'h1; + w_beat.w_last = 'h1; + + axi_master_drv.send_aw(aw_beat); + axi_master_drv.send_w(w_beat); + @(posedge s_clk); + axi_master_drv.recv_b(b_beat); + end + @(negedge s_clk); assign s_cluster_en_sa_boot = 1'b1; @(negedge s_clk); - assign s_cluster_fetch_en = 1'b1; + assign s_cluster_fetch_en = 1'b1; ret_val = '0; while(~s_cluster_eoc) begin From 020860a5d3668e46d9d34709ff6087dc1953b3f1 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 11 Oct 2023 22:05:19 +0200 Subject: [PATCH 067/207] Align XBAR PE's and cluster interconnect's parameters to default. --- rtl/cluster_interconnect_wrap.sv | 28 +++++++++++++--------------- rtl/xbar_pe_wrap.sv | 17 ++++++++++------- 2 files changed, 23 insertions(+), 22 deletions(-) diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index 5ad6a46c..245f0dc8 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -19,18 +19,18 @@ import hci_package::*; module cluster_interconnect_wrap #( - parameter NB_CORES = 8, + parameter NB_CORES = 12, parameter HWPE_PRESENT = 1, - parameter NB_HWPE_PORTS = 4, + parameter NB_HWPE_PORTS = 9, parameter NB_DMAS = 4, parameter NB_MPERIPHS = 1, parameter NB_TCDM_BANKS = 16, - parameter NB_SPERIPHS = 8, //differ + parameter NB_SPERIPHS = 10, //differ parameter DATA_WIDTH = 32, parameter ADDR_WIDTH = 32, parameter BE_WIDTH = DATA_WIDTH/8, - parameter logic [ADDR_WIDTH-1:0] ClusterBaseAddr = 'h10000000, + parameter logic [ADDR_WIDTH-1:0] ClusterBaseAddr = 'h50000000, parameter logic [ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, parameter logic [ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000, @@ -38,7 +38,7 @@ module cluster_interconnect_wrap parameter TEST_SET_BIT = 20, parameter ADDR_MEM_WIDTH = 11, parameter LOG_CLUSTER = 5, - parameter PE_ROUTING_LSB = 16, + parameter PE_ROUTING_LSB = 10, parameter PE_ROUTING_MSB = PE_ROUTING_LSB+$clog2(NB_SPERIPHS)-1, //differ parameter CLUSTER_ALIAS = 1, parameter CLUSTER_ALIAS_BASE = 12'h000, @@ -182,16 +182,14 @@ module cluster_interconnect_wrap .ClusterBaseAddr ( ClusterBaseAddr ), .ClusterPeripheralsOffs ( ClusterPeripheralsOffs ), .ClusterExternalOffs ( ClusterExternalOffs ) - ) - xbar_pe_inst - ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni), - .cluster_id_i ( cluster_id_i ), - .core_periph_slave( core_periph_slave), - .speriph_master ( speriph_master ), - .mperiph_slave ( mperiph_slave ) - ); + ) xbar_pe_inst ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .cluster_id_i ( cluster_id_i ), + .core_periph_slave( core_periph_slave), + .speriph_master ( speriph_master ), + .mperiph_slave ( mperiph_slave ) + ); endmodule diff --git a/rtl/xbar_pe_wrap.sv b/rtl/xbar_pe_wrap.sv index 3b3d88bc..5e2fbb28 100644 --- a/rtl/xbar_pe_wrap.sv +++ b/rtl/xbar_pe_wrap.sv @@ -26,7 +26,7 @@ module xbar_pe_wrap import pulp_cluster_package::*; #( - parameter NB_CORES = 8, + parameter NB_CORES = 12, parameter NB_MPERIPHS = 1, parameter NB_SPERIPHS = 10, parameter ADDR_WIDTH = 32, @@ -38,7 +38,7 @@ module xbar_pe_wrap parameter CLUSTER_ALIAS = 1, parameter CLUSTER_ALIAS_BASE = 12'h000, parameter ADDREXT = 1'b0, - parameter logic [ADDR_WIDTH-1:0] ClusterBaseAddr = 'h10000000, + parameter logic [ADDR_WIDTH-1:0] ClusterBaseAddr = 'h50000000, parameter logic [ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, parameter logic [ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000 ) @@ -56,11 +56,14 @@ module xbar_pe_wrap cluster_peripherals_base, cluster_peripherals_end ; - assign cluster_base_addr = ClusterBaseAddr + (cluster_id_i << 22); // same as in the cluster_bus_wrap - assign cluster_peripherals_base = cluster_base_addr + ClusterPeripheralsOffs; // same as in the cluster_bus_wrap - assign cluster_peripherals_end = cluster_base_addr + ClusterExternalOffs; // same as in the cluster_bus_wrap - - assign cluster_alias = (CLUSTER_ALIAS == 1) ? 1'b1 : 1'b0; + assign cluster_base_addr = ClusterBaseAddr + (cluster_id_i << 22); // same as in the cluster_bus_wrap + assign cluster_peripherals_base = cluster_base_addr + ClusterPeripheralsOffs; // same as in the cluster_bus_wrap + assign cluster_peripherals_end = cluster_base_addr + ClusterExternalOffs; // same as in the cluster_bus_wrap + + if (CLUSTER_ALIAS == 1) + assign cluster_alias = 1'b1; + else + assign cluster_alias = 1'b0; localparam int unsigned PE_XBAR_N_INPS = NB_CORES + NB_MPERIPHS; localparam int unsigned PE_XBAR_N_OUPS = NB_SPERIPHS; From c7b9abe248a31b10daab601f42ed8d7ba4cbd7b2 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 11 Oct 2023 22:59:03 +0200 Subject: [PATCH 068/207] Use pipelined checker for cores' backup buses. --- Bender.lock | 2 +- Bender.yml | 2 +- packages/pulp_cluster_package.sv | 5 ++++- rtl/pulp_cluster.sv | 16 ++++++++++------ 4 files changed, 16 insertions(+), 9 deletions(-) diff --git a/Bender.lock b/Bender.lock index f7000edf..3dbb2e02 100644 --- a/Bender.lock +++ b/Bender.lock @@ -196,7 +196,7 @@ packages: - hwpe-stream - tech_cells_generic redundancy_cells: - revision: 257344b589b151844d85d04279a89f65183c7741 + revision: f3b1bc9b2e816fe1b51147ceafa8955326d1b466 version: null source: Git: https://github.com/pulp-platform/redundancy_cells.git diff --git a/Bender.yml b/Bender.yml index f665bb71..a61a2357 100644 --- a/Bender.yml +++ b/Bender.yml @@ -34,7 +34,7 @@ dependencies: hci: { git: "https://github.com/pulp-platform/hci.git", rev: b2e6f391aa6c10c03f45b693d80a0aaddecf169b } # branch: master register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } - redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 257344b589b151844d85d04279a89f65183c7741 } # branch: yt/rapidrecovery + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: f3b1bc9b2e816fe1b51147ceafa8955326d1b466 } # branch: yt/rapidrecovery redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 0fe14edd77e9a35d3d220bd78bd6b41a0e5935ea } # branch: carfield export_include_dirs: diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 88207829..5d0eae25 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -90,9 +90,12 @@ package pulp_cluster_package; logic [4:0] irq_ack_id; logic debug_halted; logic core_busy; + } core_outputs_t; + + typedef struct packed { rapid_recovery_pkg::regfile_write_t regfile_backup; rapid_recovery_pkg::csrs_intf_t csr_backup; rapid_recovery_pkg::pc_intf_t pc_backup; - } core_outputs_t; + } core_backup_t; endpackage diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 59b3cd8e..e32586c2 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -872,9 +872,11 @@ periph_to_reg #( core_data_req_t [NB_CORES-1:0] core_data_req, demux_data_req; core_data_rsp_t [NB_CORES-1:0] core_data_rsp, demux_data_rsp; -core_inputs_t [NB_CORES-1:0] sys2hmr, hmr2core; -core_outputs_t [NB_CORES-1:0] hmr2sys, core2hmr; +core_inputs_t [NB_CORES-1:0] sys2hmr, hmr2core; +core_outputs_t [NB_CORES-1:0] hmr2sys, core2hmr; +core_backup_t [NB_CORES-1:0] backup_bus; rapid_recovery_pkg::rapid_recovery_t [NB_CORES-1:0] recovery_bus; + logic [NB_CORES-1:0] clk_core; logic [NB_CORES-1:0] setback; logic [NB_CORES-1:0][4:0] ext_perf; @@ -947,10 +949,10 @@ generate .core_data_req_o ( core_data_req[i] ), .core_data_rsp_i ( core_data_rsp[i] ), //HMR Recovery Bus - .recovery_bus_i ( recovery_bus[i] ), - .regfile_backup_o ( core2hmr[i].regfile_backup ), - .pc_backup_o ( core2hmr[i].pc_backup ), - .csr_backup_o ( core2hmr[i].csr_backup ), + .recovery_bus_i ( recovery_bus[i] ), + .regfile_backup_o ( backup_bus[i].regfile_backup ), + .pc_backup_o ( backup_bus[i].pc_backup ), + .csr_backup_o ( backup_bus[i].csr_backup ), //apu interface .apu_master_req_o ( s_apu_master_req [i] ), .apu_master_gnt_i ( s_apu_master_gnt [i] ), @@ -1073,6 +1075,7 @@ hmr_unit #( .NumBusVoters ( 1 ), .all_inputs_t ( core_inputs_t ), .nominal_outputs_t ( core_outputs_t ), + .core_backup_t ( core_backup_t ), .reg_req_t ( hmr_reg_req_t ), .reg_rsp_t ( hmr_reg_rsp_t ), .rapid_recovery_t ( rapid_recovery_pkg::rapid_recovery_t ) @@ -1096,6 +1099,7 @@ hmr_unit #( .dmr_cores_synch_i ( hmr_barrier_matched[NB_CORES/2:1] ), // Rapid recovery output bus .rapid_recovery_o ( recovery_bus ), + .core_backup_i ( backup_bus ), .sys_inputs_i ( sys2hmr ), .sys_nominal_outputs_o ( hmr2sys ), .sys_bus_outputs_o ( ), From 4d1558ac660ad445f62ffe44415ca6efc4240cf6 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 12 Oct 2023 17:09:05 +0200 Subject: [PATCH 069/207] Switch to structures-based axi xbar. --- rtl/cluster_bus_wrap.sv | 172 ++++++++++++++++++++++++---------------- 1 file changed, 104 insertions(+), 68 deletions(-) diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index f9c07db9..e2722db2 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -23,19 +23,26 @@ module cluster_bus_wrap import axi_pkg::xbar_cfg_t; #( - parameter int unsigned NB_MASTER = 3 , - parameter int unsigned NB_SLAVE = 4 , - parameter int unsigned NB_CORES = 12 , - parameter int unsigned AXI_ADDR_WIDTH = 48 , - parameter int unsigned AXI_DATA_WIDTH = 64 , - parameter int unsigned AXI_ID_IN_WIDTH = 4 , - parameter int unsigned AXI_ID_OUT_WIDTH = 6 , - parameter int unsigned AXI_USER_WIDTH = 10 , - parameter int unsigned DMA_NB_OUTSND_BURSTS = 8 , - parameter int unsigned TCDM_SIZE = 256*1024 , - parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h50000000, - parameter logic [AXI_ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, - parameter logic [AXI_ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000 + parameter int unsigned NB_MASTER = 3 , + parameter int unsigned NB_SLAVE = 4 , + parameter int unsigned NB_CORES = 12 , + parameter int unsigned AXI_ADDR_WIDTH = 48 , + parameter int unsigned AXI_DATA_WIDTH = 64 , + parameter int unsigned AXI_ID_IN_WIDTH = 4 , + parameter int unsigned AXI_ID_OUT_WIDTH = 6 , + parameter int unsigned AXI_USER_WIDTH = 10 , + parameter int unsigned DMA_NB_OUTSND_BURSTS = 8 , + parameter int unsigned TCDM_SIZE = 256*1024 , + parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h50000000, + parameter logic [AXI_ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, + parameter logic [AXI_ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000, + localparam int unsigned STRB = AXI_DATA_WIDTH/8, + localparam type axi_aw_t = logic[AXI_ADDR_WIDTH-1:0], + localparam type axi_dw_t = logic[AXI_DATA_WIDTH-1:0], + localparam type axi_uw_t = logic[AXI_USER_WIDTH-1:0], + localparam type axi_slv_iw_t = logic[AXI_ID_IN_WIDTH-1:0], + localparam type axi_mst_iw_t = logic[AXI_ID_OUT_WIDTH-1:0], + localparam type axi_strbw_t = logic[STRB-1:0] )( input logic clk_i, input logic rst_ni, @@ -51,6 +58,8 @@ module cluster_bus_wrap AXI_BUS.Master ext_master ); + `AXI_TYPEDEF_ALL_CT(xbar_slv, xbar_slv_req_t, xbar_slv_rsp_t, axi_aw_t, axi_slv_iw_t, axi_dw_t, axi_strbw_t, axi_uw_t) + `AXI_TYPEDEF_ALL_CT(xbar_mst, xbar_mst_req_t, xbar_mst_rsp_t, axi_aw_t, axi_mst_iw_t, axi_dw_t, axi_strbw_t, axi_uw_t) //Ensure that AXI_ID out width has the correct size with an elaboration system task if (AXI_ID_OUT_WIDTH < AXI_ID_IN_WIDTH + $clog2(NB_SLAVE)) @@ -67,34 +76,49 @@ module cluster_bus_wrap $fatal(1,"TCDM size exceeds available address space in cluster bus!"); // Crossbar - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) axi_slaves [NB_SLAVE-1:0](); - - // assign here your axi slaves - `AXI_ASSIGN(axi_slaves[0] , data_slave ) - `AXI_ASSIGN(axi_slaves[1] , instr_slave) - `AXI_ASSIGN(axi_slaves[2] , dma_slave ) - `AXI_ASSIGN(axi_slaves[3] , ext_slave ) - - AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) - ) axi_masters [NB_MASTER-1:0](); - - // assign here your axi masters - `AXI_ASSIGN(tcdm_master , axi_masters[0]) - `AXI_ASSIGN(periph_master, axi_masters[1]) - `AXI_ASSIGN(ext_master , axi_masters[2]) + /***************/ + /* Slave buses */ + /***************/ + xbar_slv_req_t [NB_SLAVE-1:0] slave_req; + xbar_slv_rsp_t [NB_SLAVE-1:0] slave_rsp; + // data_slv -> slave_req[0] + // data_slv <- slave_rsp[0] + `AXI_ASSIGN_TO_REQ(slave_req[0], data_slave) + `AXI_ASSIGN_FROM_RESP(data_slave, slave_rsp[0]) + // instr_slv -> slave_req[1] + // instr_slv <- slave_rsp[1] + `AXI_ASSIGN_TO_REQ(slave_req[1], instr_slave) + `AXI_ASSIGN_FROM_RESP(instr_slave, slave_rsp[1]) + // dma_slv -> slave_req[2] + // dma_slv <- slave_rsp[2] + `AXI_ASSIGN_TO_REQ(slave_req[2], dma_slave) + `AXI_ASSIGN_FROM_RESP(dma_slave, slave_rsp[2]) + // ext_slv -> slave_req[3] + // ext_slv <- slave_rsp[3] + `AXI_ASSIGN_TO_REQ(slave_req[3], ext_slave) + `AXI_ASSIGN_FROM_RESP(ext_slave, slave_rsp[3]) + + /****************/ + /* Master buses */ + /****************/ + xbar_mst_req_t [NB_MASTER-1:0] master_req; + xbar_mst_rsp_t [NB_MASTER-1:0] master_rsp; + // tcdm_master <- master_req[0] + // tcdm_master -> master_rsp[0] + `AXI_ASSIGN_FROM_REQ(tcdm_master, master_req[0]) + `AXI_ASSIGN_TO_RESP(master_rsp[0], tcdm_master) + // periph_master <- master_req[1] + // periph_master -> master_rsp[1] + `AXI_ASSIGN_FROM_REQ(periph_master, master_req[1]) + `AXI_ASSIGN_TO_RESP(master_rsp[1], periph_master) + // ext_master <- master_req[2] + // ext_master -> master_rsp[2] + `AXI_ASSIGN_FROM_REQ(ext_master, master_req[2]) + `AXI_ASSIGN_TO_RESP(master_rsp[2], ext_master) // Address Map Rule typedef struct packed { - logic [31:0] idx ; + logic [AXI_ADDR_WIDTH-1:0] idx ; logic [AXI_ADDR_WIDTH-1:0] start_addr; logic [AXI_ADDR_WIDTH-1:0] end_addr ; } addr_map_rule_t; @@ -129,39 +153,51 @@ module cluster_bus_wrap localparam int unsigned MAX_TXNS_PER_SLV_PORT = (DMA_NB_OUTSND_BURSTS > NB_CORES) ? DMA_NB_OUTSND_BURSTS : NB_CORES; + localparam xbar_cfg_t AXI_XBAR_CFG = '{ + NoSlvPorts: NB_SLAVE, + NoMstPorts: NB_MASTER, + MaxMstTrans: MAX_TXNS_PER_SLV_PORT, //The TCDM ports do not support + //outstanding transactiions anyways + MaxSlvTrans: DMA_NB_OUTSND_BURSTS + NB_CORES, //Allow up to 4 in-flight transactions + //per slave port + FallThrough: 1'b0, //Use the reccomended default config + LatencyMode: axi_pkg::NO_LATENCY, // CUT_ALL_AX | axi_pkg::DemuxW, + PipelineStages: 0, + AxiIdWidthSlvPorts: AXI_ID_IN_WIDTH, + AxiIdUsedSlvPorts: AXI_ID_IN_WIDTH, + UniqueIds: 1'b0, + AxiAddrWidth: AXI_ADDR_WIDTH, + AxiDataWidth: AXI_DATA_WIDTH, + NoAddrRules: N_RULES + }; - localparam xbar_cfg_t AXI_XBAR_CFG = '{ - NoSlvPorts: NB_SLAVE, - NoMstPorts: NB_MASTER, - MaxMstTrans: MAX_TXNS_PER_SLV_PORT, //The TCDM ports do not support - //outstanding transactiions anyways - MaxSlvTrans: DMA_NB_OUTSND_BURSTS + NB_CORES, //Allow up to 4 in-flight transactions - //per slave port - FallThrough: 1'b0, //Use the reccomended default config - LatencyMode: axi_pkg::NO_LATENCY, // CUT_ALL_AX | axi_pkg::DemuxW, - PipelineStages: 0, - AxiIdWidthSlvPorts: AXI_ID_IN_WIDTH, - AxiIdUsedSlvPorts: AXI_ID_IN_WIDTH, - UniqueIds: 1'b0, - AxiAddrWidth: AXI_ADDR_WIDTH, - AxiDataWidth: AXI_DATA_WIDTH, - NoAddrRules: N_RULES - }; - - - axi_xbar_intf #( - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .Cfg ( AXI_XBAR_CFG ), - .rule_t ( addr_map_rule_t ) - ) i_xbar ( + axi_xbar #( + .Cfg ( AXI_XBAR_CFG ), + .slv_aw_chan_t ( xbar_slv_aw_chan_t ), + .mst_aw_chan_t ( xbar_mst_aw_chan_t ), + .w_chan_t ( xbar_mst_w_chan_t ), + .slv_b_chan_t ( xbar_slv_b_chan_t ), + .mst_b_chan_t ( xbar_mst_b_chan_t ), + .slv_ar_chan_t ( xbar_slv_ar_chan_t ), + .mst_ar_chan_t ( xbar_mst_ar_chan_t ), + .slv_r_chan_t ( xbar_slv_r_chan_t ), + .mst_r_chan_t ( xbar_mst_r_chan_t ), + .slv_req_t ( xbar_slv_req_t ), + .slv_resp_t ( xbar_slv_rsp_t ), + .mst_req_t ( xbar_mst_req_t ), + .mst_resp_t ( xbar_mst_rsp_t ), + .rule_t ( addr_map_rule_t ) + ) i_xbar ( .clk_i, .rst_ni, - .test_i (test_en_i), - .slv_ports (axi_slaves), - .mst_ports (axi_masters), - .addr_map_i (addr_map), - .en_default_mst_port_i ('0), // disable default master port for all slave ports - .default_mst_port_i ('0) + .test_i ( test_en_i ), + .slv_ports_req_i ( slave_req ), + .slv_ports_resp_o ( slave_rsp ), + .mst_ports_req_o ( master_req ), + .mst_ports_resp_i ( master_rsp ), + .addr_map_i ( addr_map ), + .en_default_mst_port_i ( '0 ), + .default_mst_port_i ( '0 ) ); endmodule From e363672d9913fa72bf6fe1e2fecc74049c107684 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 12 Oct 2023 22:19:48 +0200 Subject: [PATCH 070/207] Fix inconsistent code. --- rtl/pulp_cluster.sv | 83 ++++++++++++++++++++++++--------------------- 1 file changed, 44 insertions(+), 39 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index e32586c2..923d64ba 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -377,7 +377,6 @@ XBAR_TCDM_BUS s_mperiph_xbar_bus[NB_MPERIPHS-1:0](); // periph demux XBAR_TCDM_BUS s_mperiph_bus(); -XBAR_TCDM_BUS s_mperiph_demux_bus[1:0](); // bus 1 is no longer in use. // cores & accelerators -> log interconnect hci_core_intf #( @@ -467,14 +466,14 @@ AXI_BUS #( .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ) -) s_data_slave_64(); +) s_data_slave_int(); AXI_BUS #( .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), .AXI_USER_WIDTH ( AXI_USER_WIDTH ) -) s_data_slave_32(); +) s_data_slave_ext(); AXI_BUS #( .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), @@ -560,7 +559,7 @@ cluster_bus_wrap #( .instr_slave ( s_core_instr_bus ), .data_slave ( s_core_ext_bus ), .dma_slave ( s_dma_ext_bus ), - .ext_slave ( s_data_slave_64 ), + .ext_slave ( s_data_slave_int ), .tcdm_master ( s_ext_tcdm_bus ), .periph_master ( s_ext_mperiph_bus ), .ext_master ( s_data_master ) @@ -595,23 +594,24 @@ axi2per_wrap #( .busy_o ( s_axi2per_busy ) ); -per_demux_wrap #( - .NB_MASTERS ( 2 ), - .ADDR_OFFSET ( 20 ) -) per_demux_wrap_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slave ( s_mperiph_bus ), - .masters ( s_mperiph_demux_bus ) -); - -`TCDM_ASSIGN_MASTER (s_mperiph_xbar_bus[NB_MPERIPHS-1], s_mperiph_demux_bus[0]) +if (NB_MPERIPHS > 1) begin + XBAR_TCDM_BUS s_mperiph_demux_bus[NB_MPERIPHS-1:0](); + per_demux_wrap #( + .NB_MASTERS ( NB_MPERIPHS ), + .ADDR_OFFSET ( 20 ) + ) per_demux_wrap_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slave ( s_mperiph_bus ), + .masters ( s_mperiph_demux_bus ) + ); -/* Binding of unused bus */ -assign s_mperiph_demux_bus[1].gnt = '0; -assign s_mperiph_demux_bus[1].r_rdata = '0; -assign s_mperiph_demux_bus[1].r_opc = '0; -assign s_mperiph_demux_bus[1].r_valid = '0; + for (genvar i = 0; i < NB_MPERIPHS; i++) begin + `TCDM_ASSIGN_MASTER (s_mperiph_xbar_bus[i], s_mperiph_demux_bus[i]) + end +end else begin + `TCDM_ASSIGN_MASTER (s_mperiph_xbar_bus[0], s_mperiph_bus) +end per2axi_wrap #( .NB_CORES ( NB_CORES ), @@ -1483,11 +1483,8 @@ axi_cdc_src #( `AXI_TYPEDEF_REQ_T(s2c_req_t,s2c_aw_chan_t,s2c_w_chan_t,s2c_ar_chan_t) `AXI_TYPEDEF_RESP_T(s2c_resp_t,s2c_b_chan_t,s2c_r_chan_t) - s2c_req_t dst_req , isolate_dst_req; - s2c_resp_t dst_resp, isolate_dst_resp; - -`AXI_ASSIGN_FROM_REQ(s_data_slave_32,dst_req) -`AXI_ASSIGN_TO_RESP(dst_resp,s_data_slave_32) +s2c_req_t dst_req , isolate_dst_req; +s2c_resp_t dst_resp, isolate_dst_resp; axi_cdc_dst #( .aw_chan_t ( s2c_aw_chan_t ), @@ -1521,20 +1518,28 @@ axi_cdc_dst #( .async_data_slave_r_data_o ( async_data_slave_r_data_o ) ); -axi_dw_converter_intf #( - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_SLV_PORT_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), - .AXI_MST_PORT_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_MAX_READS ( 1 ) -) axi_dw_UPSIZE_32_64_wrap_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv ( s_data_slave_32 ), - .mst ( s_data_slave_64 ) -); - +if (AXI_DATA_S2C_WIDTH != AXI_DATA_C2S_WIDTH) begin + `AXI_ASSIGN_FROM_REQ(s_data_slave_ext,dst_req) + `AXI_ASSIGN_TO_RESP(dst_resp,s_data_slave_ext) + + axi_dw_converter_intf #( + .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), + .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), + .AXI_SLV_PORT_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), + .AXI_MST_PORT_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), + .AXI_USER_WIDTH ( AXI_USER_WIDTH ), + .AXI_MAX_READS ( 1 ) + ) axi_dw_UPSIZE_32_64_wrap_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv ( s_data_slave_ext ), + .mst ( s_data_slave_int ) + ); +end else begin + `AXI_ASSIGN_FROM_REQ(s_data_slave_int,dst_req) + `AXI_ASSIGN_TO_RESP(dst_resp,s_data_slave_int) +end + /* event synchronizers */ cdc_fifo_gray_dst #( .T(logic[EVNT_WIDTH-1:0]), From a94be90773ba2ef2259e4b324755ddc213c30efb Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 16 Oct 2023 17:09:30 +0200 Subject: [PATCH 071/207] Making iCache interface array consistent with the rest of the code. --- rtl/cluster_peripherals.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index d2d73c58..4c237590 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -101,8 +101,8 @@ module cluster_peripherals output hci_package::hci_interconnect_ctrl_t hci_ctrl_o, // Control ports - SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_main[NB_CACHE_BANKS], - PRI_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_pri[NB_CORES], + SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_main[NB_CACHE_BANKS-1:0], + PRI_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_pri[NB_CORES-1:0], output logic [NB_CORES-1:0] enable_l1_l15_prefetch_o ); From b38a18b1594f1aa4faf8b15e426a276be7ead3aa Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 16 Oct 2023 17:21:28 +0200 Subject: [PATCH 072/207] Bumping iCache for interfaces indexing consistency. --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index 3dbb2e02..29d4b91f 100644 --- a/Bender.lock +++ b/Bender.lock @@ -114,7 +114,7 @@ packages: - hwpe-stream - l2_tcdm_hybrid_interco hier-icache: - revision: fac03040e4901daad29c141fc481f7c5d3758e99 + revision: a971e364bf8090cf77fafad995b480c1ac7ea4e0 version: null source: Git: https://github.com/pulp-platform/hier-icache.git diff --git a/Bender.yml b/Bender.yml index a61a2357..4c2d149d 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,7 +19,7 @@ dependencies: event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master - hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "fac03040e4901daad29c141fc481f7c5d3758e99" } # branch: yt/carfield + hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a971e364bf8090cf77fafad995b480c1ac7ea4e0" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: a596f17fc77713909bceb7eecf3ea2c3cdfe707c } # branch: yt/bump-hci # fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "4aec4b68424947b0c4cf25fd7c4b907cb9ec3dfa" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } From d1475aebd9862bcf933871192f9d7572356e37f1 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 20 Oct 2023 00:22:21 +0200 Subject: [PATCH 073/207] Add return value register internal to PULP cluster. --- Bender.lock | 2 +- Bender.yml | 2 +- tb/pulp_cluster_tb.sv | 34 +++++++++++++++++----------------- 3 files changed, 19 insertions(+), 19 deletions(-) diff --git a/Bender.lock b/Bender.lock index 29d4b91f..cd9b00b5 100644 --- a/Bender.lock +++ b/Bender.lock @@ -53,7 +53,7 @@ packages: dependencies: - common_cells cluster_peripherals: - revision: a596f17fc77713909bceb7eecf3ea2c3cdfe707c + revision: c015839816938a790c8da5fd5829cfc536f1ca9c version: null source: Git: https://github.com/pulp-platform/cluster_peripherals.git diff --git a/Bender.yml b/Bender.yml index 4c2d149d..bb02e079 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,7 +20,7 @@ dependencies: mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a971e364bf8090cf77fafad995b480c1ac7ea4e0" } # branch: yt/carfield - cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: a596f17fc77713909bceb7eecf3ea2c3cdfe707c } # branch: yt/bump-hci + cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: c015839816938a790c8da5fd5829cfc536f1ca9c } # branch: yt/return-reg # fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "4aec4b68424947b0c4cf25fd7c4b907cb9ec3dfa" } # branch: yt/carfield axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 9b8681de..bf36d3f7 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -64,6 +64,7 @@ module pulp_cluster_tb; localparam bit[AxiAw-1:0] L2BaseAddr = 'h78000000; localparam bit[AxiAw-1:0] L2Size = 'h10000000; localparam bit[AxiAw-1:0] BootAddr = L2BaseAddr + 'h8080; + localparam bit[AxiAw-1:0] ClustReturnInt = 'h50200100; typedef logic [AxiAw-1:0] axi_addr_t; typedef logic [AxiDw-1:0] axi_data_t; @@ -502,27 +503,26 @@ module pulp_cluster_tb; end @(negedge s_clk); - assign s_cluster_en_sa_boot = 1'b1; + assign s_cluster_en_sa_boot = 1'b1; @(negedge s_clk); - assign s_cluster_fetch_en = 1'b1; + assign s_cluster_fetch_en = 1'b1; ret_val = '0; while(~s_cluster_eoc) begin - - ar_beat.ax_addr = 32'h1A10_40A0; - ar_beat.ax_len = '0; - ar_beat.ax_burst = axi_pkg::BURST_INCR; - ar_beat.ax_size = 4'h2; - - axi_master_drv.send_ar(ar_beat); - @(posedge s_clk); - axi_master_drv.recv_r(r_beat); - ret_val = r_beat.r_data; - repeat(1000) - @(posedge s_clk); - + repeat(1) + @(posedge s_clk); end - + + ar_beat.ax_addr = ClustReturnInt; + ar_beat.ax_len = '0; + ar_beat.ax_burst = axi_pkg::BURST_INCR; + ar_beat.ax_size = 4'h2; + + axi_master_drv.send_ar(ar_beat); + @(posedge s_clk); + axi_master_drv.recv_r(r_beat); + ret_val = r_beat.r_data; + $display("[TB] Received ret_val: %d\n", ret_val[30:0]); if(ret_val[30:0]==0) begin @@ -531,7 +531,7 @@ module pulp_cluster_tb; end else begin $fatal(1,"[TB] Test not passed: ret_val!=0\n"); end - + end From 009975a6efaced16b2d67bc6ba6f9a26532fcab4 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 25 Oct 2023 23:51:17 +0200 Subject: [PATCH 074/207] Update core commit. --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index cd9b00b5..242dde9a 100644 --- a/Bender.lock +++ b/Bender.lock @@ -216,7 +216,7 @@ packages: - common_cells - common_verification riscv: - revision: 6c56a943f272e987968a53df6dca095f939c1915 + revision: 8d1fac5542625f30551f3bfd44f512e83c6a6a50 version: null source: Git: git@github.com:AlSaqr-platform/riscv_nn.git diff --git a/Bender.yml b/Bender.yml index bb02e079..384652aa 100644 --- a/Bender.yml +++ b/Bender.yml @@ -27,7 +27,7 @@ dependencies: timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 6c56a943f272e987968a53df6dca095f939c1915 } # branch: yt/hmr + riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 8d1fac5542625f30551f3bfd44f512e83c6a6a50 } # branch: yt/hmr cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating From aa41a23d170d88261fb8ad6eb95c749753bab336 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 25 Oct 2023 23:51:44 +0200 Subject: [PATCH 075/207] Added local OBI adapter. --- Bender.yml | 1 + rtl/obi_pulp_adapter.sv | 65 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100644 rtl/obi_pulp_adapter.sv diff --git a/Bender.yml b/Bender.yml index 384652aa..75d2b785 100644 --- a/Bender.yml +++ b/Bender.yml @@ -52,6 +52,7 @@ sources: - rtl/cluster_clock_gate.sv - rtl/cluster_event_map.sv - rtl/cluster_timer_wrap.sv + - rtl/obi_pulp_adapter.sv - target: mchan files: - rtl/mchan_wrap.sv diff --git a/rtl/obi_pulp_adapter.sv b/rtl/obi_pulp_adapter.sv new file mode 100644 index 00000000..d41a4509 --- /dev/null +++ b/rtl/obi_pulp_adapter.sv @@ -0,0 +1,65 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Author: Matteo Perotti, mperotti@iis.ee.ethz.ch +// Description: Module to adapt CV32E40P to the PULP memory system. +// It blocks multiple outstanding requests to the memory until the first one is served. + +module obi_pulp_adapter ( + input logic rst_ni, + input logic clk_i, + input logic setback_i, + // Master (core) interface + input logic core_req_i, + // Slave (memory) interface + input logic mem_gnt_i, + input logic mem_rvalid_i, + output logic mem_req_o +); + +// CU states +typedef enum logic {WAIT_GNT, WAIT_VALID} state_t; +state_t ps, ns; + +// FSM next-state sequential process +always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + ps <= WAIT_GNT; + end else begin + if (setback_i) begin + ps <= WAIT_GNT; + end else begin + ps <= ns; + end + end +end + +// Block multiple requests, as the memory does not support them +// core_req_i is kept stable by cv32e40p (OBI compliant) +always_comb begin + case (ps) + WAIT_GNT: begin + // Idle state, the memory has not received any request yet + mem_req_o = core_req_i; + ns = (core_req_i && mem_gnt_i) ? WAIT_VALID : WAIT_GNT; + end + WAIT_VALID: begin + // The memory has received and granted a request. Filter the next request until the memory is ready to accept it. + mem_req_o = (core_req_i && mem_rvalid_i) ? 1'b1 : 1'b0; + ns = (mem_rvalid_i && !mem_gnt_i) ? WAIT_GNT : WAIT_VALID; + end + default: begin + mem_req_o = core_req_i; + ns = WAIT_GNT; + end + endcase +end + +endmodule From 450eb8780a3fe62cac6bcb0b34542ede2bc7c3c0 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 25 Oct 2023 23:52:04 +0200 Subject: [PATCH 076/207] Connecting correct buses from recovery RF. --- rtl/core_region.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rtl/core_region.sv b/rtl/core_region.sv index c9a6d653..1dcbd2b7 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -304,11 +304,11 @@ import rapid_recovery_pkg::*; .recover_i ( recovery_bus_i.rf_recovery_en ), // Write port A .regfile_waddr_a_i ( recovery_bus_i.rf_recovery_wdata.waddr_a ), - .regfile_wdata_a_i ( recovery_bus_i.rf_recovery_wdata.wdata_a ), + .regfile_wdata_a_i ( recovery_bus_i.rf_recovery_rdata.rdata_a ), .regfile_we_a_i ( recovery_bus_i.rf_recovery_wdata.we_a ), // Write port B .regfile_waddr_b_i ( recovery_bus_i.rf_recovery_wdata.waddr_b ), - .regfile_wdata_b_i ( recovery_bus_i.rf_recovery_wdata.wdata_b ), + .regfile_wdata_b_i ( recovery_bus_i.rf_recovery_rdata.rdata_b ), .regfile_we_b_i ( recovery_bus_i.rf_recovery_wdata.we_b ), // Outputs from RF // Port A From 86e67af40e98c983aa3cf1cf9d3258601185a02b Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 30 Oct 2023 22:24:35 +0100 Subject: [PATCH 077/207] Bump core and redundancy cells, add core PC IF backup. --- Bender.lock | 4 ++-- Bender.yml | 4 ++-- rtl/core_region.sv | 7 ++++--- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/Bender.lock b/Bender.lock index 242dde9a..959f34de 100644 --- a/Bender.lock +++ b/Bender.lock @@ -196,7 +196,7 @@ packages: - hwpe-stream - tech_cells_generic redundancy_cells: - revision: f3b1bc9b2e816fe1b51147ceafa8955326d1b466 + revision: 32023555679cfdb8a0a073ad4c17fc3a5d1ddea5 version: null source: Git: https://github.com/pulp-platform/redundancy_cells.git @@ -216,7 +216,7 @@ packages: - common_cells - common_verification riscv: - revision: 8d1fac5542625f30551f3bfd44f512e83c6a6a50 + revision: a1dcae35edae6092ddbf92c424690cb903b678d5 version: null source: Git: git@github.com:AlSaqr-platform/riscv_nn.git diff --git a/Bender.yml b/Bender.yml index 75d2b785..07560901 100644 --- a/Bender.yml +++ b/Bender.yml @@ -27,14 +27,14 @@ dependencies: timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: 8d1fac5542625f30551f3bfd44f512e83c6a6a50 } # branch: yt/hmr + riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: a1dcae35edae6092ddbf92c424690cb903b678d5 } # branch: yt/hmr cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating hci: { git: "https://github.com/pulp-platform/hci.git", rev: b2e6f391aa6c10c03f45b693d80a0aaddecf169b } # branch: master register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } - redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: f3b1bc9b2e816fe1b51147ceafa8955326d1b466 } # branch: yt/rapidrecovery + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 32023555679cfdb8a0a073ad4c17fc3a5d1ddea5 } # branch: yt/rapidrecovery redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 0fe14edd77e9a35d3d220bd78bd6b41a0e5935ea } # branch: carfield export_include_dirs: diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 1dcbd2b7..3690ec6e 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -320,9 +320,10 @@ import rapid_recovery_pkg::*; .regfile_waddr_b_o ( regfile_backup_o.waddr_b ), .regfile_wdata_b_o ( regfile_backup_o.wdata_b ), // Program Counter Backup - .backup_program_counter_o ( pc_backup_o.program_counter ), - .backup_branch_o ( pc_backup_o.is_branch ), - .backup_branch_addr_o ( pc_backup_o.branch_addr ), + .backup_program_counter_o ( pc_backup_o.program_counter ), + .backup_program_counter_if_o ( pc_backup_o.program_counter_if ), + .backup_branch_o ( pc_backup_o.is_branch ), + .backup_branch_addr_o ( pc_backup_o.branch_addr ), // Program Counter Recovery .pc_recover_i ( recovery_bus_i.pc_recovery_en ), .recovery_program_counter_i ( recovery_bus_i.pc_recovery.program_counter ), From de93f2001ee0a6fca1dc11f6dd95119d8e6aadfb Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 30 Oct 2023 22:32:30 +0100 Subject: [PATCH 078/207] Make rata_req.we propagation consistent. --- packages/pulp_cluster_package.sv | 2 +- rtl/core_demux_wrap.sv | 2 +- rtl/core_region.sv | 7 +++---- rtl/pulp_cluster.sv | 4 ++-- 4 files changed, 7 insertions(+), 8 deletions(-) diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 5d0eae25..eb06fae0 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -58,7 +58,7 @@ package pulp_cluster_package; typedef struct packed { logic req; logic [31:0] add; - logic wen; + logic we; logic [31:0] data; logic [3:0] be; } core_data_req_t; diff --git a/rtl/core_demux_wrap.sv b/rtl/core_demux_wrap.sv index e4446aba..bdc33068 100644 --- a/rtl/core_demux_wrap.sv +++ b/rtl/core_demux_wrap.sv @@ -44,7 +44,7 @@ data_periph_demux #( .base_addr_i ( base_addr_i ), .data_req_i ( core_data_req_i.req ), .data_add_i ( core_data_req_i.add ), - .data_wen_i ( core_data_req_i.wen ), //inverted when using OR10N + .data_wen_i ( ~core_data_req_i.we ), //inverted when using OR10N .data_wdata_i ( core_data_req_i.data ), .data_be_i ( core_data_req_i.be ), .data_gnt_o ( core_data_rsp_o.gnt ), diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 3690ec6e..485030de 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -145,7 +145,6 @@ import rapid_recovery_pkg::*; logic core_data_req_we ; - assign core_data_req_o.wen = ~core_data_req_we; assign hart_id = {21'b0, cluster_id_i[5:0], 1'b0, core_id_i}; //******************************************************** @@ -185,7 +184,7 @@ import rapid_recovery_pkg::*; .data_req_o ( core_data_req_o.req ), .data_gnt_i ( core_data_rsp_i.gnt ), .data_rvalid_i ( core_data_rsp_i.r_valid ), - .data_we_o ( core_data_req_we ), + .data_we_o ( core_data_req_o.we ), .data_be_o ( core_data_req_o.be ), .data_addr_o ( core_data_req_o.add ), .data_wdata_o ( core_data_req_o.data ), @@ -263,7 +262,7 @@ import rapid_recovery_pkg::*; .data_req_o ( core_data_req_o.req ), .data_gnt_i ( core_data_rsp_i.gnt ), .data_rvalid_i ( core_data_rsp_i.r_valid ), - .data_we_o ( core_data_req_we ), + .data_we_o ( core_data_req_o.we ), .data_be_o ( core_data_req_o.be ), .data_addr_o ( core_data_req_o.add ), .data_wdata_o ( core_data_req_o.data ), @@ -439,7 +438,7 @@ import rapid_recovery_pkg::*; .data_req_o ( core_mem_req ), .data_gnt_i ( core_data_rsp_i.gnt ), .data_rvalid_i ( core_data_rsp_i.r_valid ), - .data_we_o ( core_data_req_we ), + .data_we_o ( core_data_req_o.we ), .data_be_o ( core_data_req_o.be ), .data_addr_o ( core_data_req_o.add ), .data_wdata_o ( core_data_req_o.wdata ), diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 923d64ba..81db335b 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -985,7 +985,7 @@ generate assign instr_req[i] = hmr2sys[i].instr_req; assign instr_addr[i] = hmr2sys[i].instr_addr; assign demux_data_req[i].req = hmr2sys[i].data_req; - assign demux_data_req[i].wen = hmr2sys[i].data_we; // The protocol is handeled within the core + assign demux_data_req[i].we = hmr2sys[i].data_we; assign demux_data_req[i].be = hmr2sys[i].data_be; assign demux_data_req[i].add = hmr2sys[i].data_add; assign demux_data_req[i].data = hmr2sys[i].data_wdata; @@ -1000,7 +1000,7 @@ generate assign core2hmr[i].data_req = core_data_req[i].req; assign core2hmr[i].data_add = core_data_req[i].add; - assign core2hmr[i].data_we = core_data_req[i].wen; // The protocol is handeled within the core + assign core2hmr[i].data_we = core_data_req[i].we; assign core2hmr[i].data_wdata = core_data_req[i].data; assign core2hmr[i].data_be = core_data_req[i].be; From bd2cd62b66a06877dffc69f78ac5eed6b892127d Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 7 Jan 2024 21:45:44 +0100 Subject: [PATCH 079/207] Bump RedMulE commit to cut critical path. --- Bender.lock | 4 ++-- Bender.yml | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Bender.lock b/Bender.lock index 959f34de..c86f60bb 100644 --- a/Bender.lock +++ b/Bender.lock @@ -105,7 +105,7 @@ packages: dependencies: - common_cells hci: - revision: b2e6f391aa6c10c03f45b693d80a0aaddecf169b + revision: 78fb8fc8a6f2c376554562c47755b4d0febaba25 version: null source: Git: https://github.com/pulp-platform/hci.git @@ -183,7 +183,7 @@ packages: dependencies: - axi_slice redmule: - revision: 0fe14edd77e9a35d3d220bd78bd6b41a0e5935ea + revision: 532f9514ad5c7ee21dde9e3a84ae99d2a5760610 version: null source: Git: https://github.com/pulp-platform/redmule.git diff --git a/Bender.yml b/Bender.yml index 07560901..15d35abb 100644 --- a/Bender.yml +++ b/Bender.yml @@ -35,7 +35,7 @@ dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 32023555679cfdb8a0a073ad4c17fc3a5d1ddea5 } # branch: yt/rapidrecovery - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 0fe14edd77e9a35d3d220bd78bd6b41a0e5935ea } # branch: carfield + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 532f9514ad5c7ee21dde9e3a84ae99d2a5760610 } # branch: astral export_include_dirs: - include From 4fc2c92683ac0afbda687d7a3a8dc93220867dc6 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 24 Jan 2024 16:51:19 +0100 Subject: [PATCH 080/207] Allow questasim to return exit code in case of errors. --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 2c75e3a8..73b062ea 100644 --- a/Makefile +++ b/Makefile @@ -107,7 +107,7 @@ $(library): compile: $(library) $(dpi) $(dpi-library)/cl_dpi.so @test -f Bender.lock || { echo "ERROR: Bender.lock file does not exist. Did you run make checkout in bender mode?"; exit 1; } @test -f scripts/compile.tcl || { echo "ERROR: scripts/compile.tcl file does not exist. Did you run make scripts in bender mode?"; exit 1; } - $(VSIM) -c -do 'source scripts/compile.tcl; quit' + $(VSIM) -c -do 'quit -code [source scripts/compile.tcl]' build: compile $(dpi) $(VOPT) $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis From 578cb13b85f46487d9cf6ceb40275879628257ed Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 24 Jan 2024 16:51:56 +0100 Subject: [PATCH 081/207] Add FPU wrapper as a unit within PULP cluster. --- Bender.yml | 1 + rtl/fpu_wrap.sv | 114 +++++++++++++++++++++++ rtl/pulp_cluster.sv | 216 +++++++++++++++++++++++++------------------- 3 files changed, 237 insertions(+), 94 deletions(-) create mode 100644 rtl/fpu_wrap.sv diff --git a/Bender.yml b/Bender.yml index 15d35abb..e0c2c881 100644 --- a/Bender.yml +++ b/Bender.yml @@ -72,6 +72,7 @@ sources: - rtl/cluster_peripherals.sv - rtl/data_periph_demux.sv - rtl/core_demux_wrap.sv + - rtl/fpu_wrap.sv # Level 2 - rtl/core_region.sv - target: simulation diff --git a/rtl/fpu_wrap.sv b/rtl/fpu_wrap.sv new file mode 100644 index 00000000..5cba5e50 --- /dev/null +++ b/rtl/fpu_wrap.sv @@ -0,0 +1,114 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +module fpu_wrap + import riscv_defines::*; +#( + parameter int unsigned DataWidth = 32, + parameter int unsigned FpuNumOperands = 3, + parameter int unsigned FpuOpcodeWidth = 6, + parameter int unsigned FpuInFlagsWidth = 15, + parameter int unsigned FpuOutFlagsWidth = 5, + parameter int unsigned FpuFmtBits = fpnew_pkg::FP_FORMAT_BITS, + parameter int unsigned FpuIntFmtBits = fpnew_pkg::INT_FORMAT_BITS, + parameter int unsigned FpuRoundBits = 3, + parameter int unsigned FpuOpBits = fpnew_pkg::OP_BITS, + parameter int unsigned FpuDivSqrt = 0 +)( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + input logic [31:0] hart_id_i, + // APU Side: Master port + input logic fpu_req_i, + output logic fpu_gnt_o, + // request channel + input logic [FpuNumOperands-1:0][DataWidth-1:0] fpu_operands_i, + input logic [FpuOpcodeWidth-1:0] fpu_op_i, + input logic [FpuInFlagsWidth-1:0] fpu_flags_i, + // response channel + output logic fpu_valid_o, + output logic [DataWidth-1:0] fpu_result_o, + output logic [FpuOutFlagsWidth-1:0] fpu_flags_o +); + +localparam fpnew_pkg::unit_type_t C_DIV = FpuDivSqrt ? fpnew_pkg::MERGED : + fpnew_pkg::DISABLED; + +logic fpu_op_mod; +logic fpu_vec_op; +logic [FpuOpBits-1:0] fpu_op; + +logic [FpuFmtBits-1:0] dst_fmt; +logic [FpuFmtBits-1:0] src_fmt; +logic [FpuIntFmtBits-1:0] int_fmt; +logic [FpuRoundBits-1:0] fp_rnd_mode; + +assign {fpu_vec_op, fpu_op_mod, fpu_op} = fpu_op_i; +assign {int_fmt, src_fmt, dst_fmt, fp_rnd_mode} = fpu_flags_i; + +// ----------- +// FPU Config +// ----------- +// Features (enabled formats, vectors etc.) +localparam fpnew_pkg::fpu_features_t FpuFeatures = '{ + Width: C_FLEN, + EnableVectors: C_XFVEC, + EnableNanBox: 1'b0, + FpFmtMask: {C_RVF, C_RVD, C_XF16, C_XF8, C_XF16ALT, C_XF8ALT}, + IntFmtMask: {C_XFVEC && (C_XF8 || C_XF8ALT), + C_XFVEC && (C_XF16 || C_XF16ALT), 1'b1, 1'b0} +}; + +// Implementation (number of registers etc) +localparam fpnew_pkg::fpu_implementation_t FpuImplementation = '{ + PipeRegs: '{// FP32, FP64, FP16, FP8, FP16alt, FP8alt + '{C_LAT_FP32, C_LAT_FP64, + C_LAT_FP16, C_LAT_FP8 , + C_LAT_FP16ALT, C_LAT_FP8ALT}, // ADDMUL + '{default: C_LAT_DIVSQRT}, // DIVSQRT + '{default: C_LAT_NONCOMP}, // NONCOMP + '{default: C_LAT_CONV }, // CONV + '{default: C_LAT_DOTP }}, // SDOTP + UnitTypes: '{'{default: fpnew_pkg::MERGED}, // ADDMUL + '{default: C_DIV}, // DIVSQRT + '{default: fpnew_pkg::PARALLEL}, // NONCOMP + '{default: fpnew_pkg::MERGED}, // CONV + '{default: fpnew_pkg::DISABLED}}, // SDOTP + PipeConfig: fpnew_pkg::BEFORE +}; + +//--------------- +// FPU instance +//--------------- +fpnew_top #( + .Features ( FpuImplementation ), + .Implementation ( FpuFeatures ), + .TagType ( logic ) +) i_fpnew ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .hart_id_i ( hart_id_i ), + .operands_i ( fpu_operands_i ), + .rnd_mode_i ( fpnew_pkg::roundmode_e'(fp_rnd_mode) ), + .op_i ( fpnew_pkg::operation_e'(fpu_op) ), + .op_mod_i ( fpu_op_mod ), + .src_fmt_i ( fpnew_pkg::fp_format_e'(src_fmt) ), + .dst_fmt_i ( fpnew_pkg::fp_format_e'(dst_fmt) ), + .int_fmt_i ( fpnew_pkg::int_format_e'(int_fmt) ), + .vectorial_op_i ( fpu_vec_op ), + .tag_i ( '0 ), + .simd_mask_i ( '1 ), + .in_valid_i ( fpu_req_i ), + .in_ready_o ( fpu_gnt_o ), + .flush_i ( '0 ), + .result_o ( fpu_result_o ), + .status_o ( fpu_flags_o ), + .tag_o ( ), + .out_valid_o ( fpu_valid_o ), + .out_ready_i ( 1'b1 ), + .busy_o ( ) +); + +endmodule: fpu_wrap diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 81db335b..c31e6022 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -69,7 +69,8 @@ module pulp_cluster parameter BOOT_ADDR = 32'h78000000, parameter INSTR_RDATA_WIDTH = 32, - parameter CLUST_FPU = 0, + parameter bit CLUST_FPU = 1, + parameter int unsigned NumFpu = NB_CORES, parameter CLUST_FP_DIVSQRT = 0, parameter CLUST_SHARED_FP = 0, parameter CLUST_SHARED_FP_DIVSQRT = 0, @@ -424,18 +425,18 @@ XBAR_PERIPH_BUS s_core_euctrl_bus[NB_CORES-1:0](); // apu-interconnect // handshake signals -logic [NB_CORES-1:0] s_apu_master_req; -logic [NB_CORES-1:0] s_apu_master_gnt; +logic [NB_CORES-1:0] fpu_master_req; +logic [NB_CORES-1:0] fpu_master_gnt; // request channel -logic [NB_CORES-1:0][APU_NARGS_CPU-1:0][31:0] s_apu_master_operands; -logic [NB_CORES-1:0][APU_WOP_CPU-1:0] s_apu_master_op; -logic [NB_CORES-1:0][WAPUTYPE-1:0] s_apu_master_type; -logic [NB_CORES-1:0][APU_NDSFLAGS_CPU-1:0] s_apu_master_flags; +logic [NB_CORES-1:0][APU_NARGS_CPU-1:0][31:0] fpu_master_operands; +logic [NB_CORES-1:0][APU_WOP_CPU-1:0] fpu_master_op; +logic [NB_CORES-1:0][WAPUTYPE-1:0] fpu_master_type; +logic [NB_CORES-1:0][APU_NDSFLAGS_CPU-1:0] fpu_master_in_flags; // response channel -logic [NB_CORES-1:0] s_apu_master_rready; -logic [NB_CORES-1:0] s_apu_master_rvalid; -logic [NB_CORES-1:0][31:0] s_apu_master_rdata; -logic [NB_CORES-1:0][APU_NUSFLAGS_CPU-1:0] s_apu_master_rflags; +logic [NB_CORES-1:0] fpu_master_rready; +logic [NB_CORES-1:0] fpu_master_valid; +logic [NB_CORES-1:0][31:0] fpu_master_result; +logic [NB_CORES-1:0][APU_NUSFLAGS_CPU-1:0] fpu_master_out_flags; //----------------------------------------------------------------------// // Interfaces between ICache - L0 - Icache_Interco and Icache_ctrl_unit // @@ -954,18 +955,49 @@ generate .pc_backup_o ( backup_bus[i].pc_backup ), .csr_backup_o ( backup_bus[i].csr_backup ), //apu interface - .apu_master_req_o ( s_apu_master_req [i] ), - .apu_master_gnt_i ( s_apu_master_gnt [i] ), - .apu_master_type_o ( s_apu_master_type [i] ), - .apu_master_operands_o ( s_apu_master_operands[i] ), - .apu_master_op_o ( s_apu_master_op [i] ), - .apu_master_flags_o ( s_apu_master_flags [i] ), - .apu_master_valid_i ( s_apu_master_rvalid [i] ), - .apu_master_ready_o ( s_apu_master_rready [i] ), - .apu_master_result_i ( s_apu_master_rdata [i] ), - .apu_master_flags_i ( s_apu_master_rflags [i] ) + .apu_master_req_o ( fpu_master_req [i] ), + .apu_master_gnt_i ( fpu_master_gnt [i] ), + .apu_master_type_o ( fpu_master_type [i] ), + .apu_master_operands_o ( fpu_master_operands [i] ), + .apu_master_op_o ( fpu_master_op [i] ), + .apu_master_flags_o ( fpu_master_in_flags [i] ), + .apu_master_valid_i ( fpu_master_valid [i] ), + .apu_master_ready_o ( fpu_master_rready [i] ), + .apu_master_result_i ( fpu_master_result [i] ), + .apu_master_flags_i ( fpu_master_out_flags[i] ) ); + if (CLUST_FPU) begin: gen_fpu + fpu_wrap #( + .DataWidth ( 32 ), + .FpuNumOperands ( APU_NARGS_CPU ), + .FpuOpcodeWidth ( APU_WOP_CPU ), + .FpuInFlagsWidth ( APU_NDSFLAGS_CPU ), + .FpuOutFlagsWidth ( APU_NUSFLAGS_CPU ), + .FpuFmtBits ( fpnew_pkg::FP_FORMAT_BITS ), + .FpuIntFmtBits ( fpnew_pkg::INT_FORMAT_BITS ), + .FpuRoundBits ( 3 ), + .FpuOpBits ( fpnew_pkg::OP_BITS ), + .FpuDivSqrt ( CLUST_FP_DIVSQRT ) + ) i_fpu_wrap ( + .clk_i ( clk_core[i] ), + .rst_ni ( rst_ni ), + .hart_id_i ( i ), + .fpu_req_i ( fpu_master_req[i] ), + .fpu_gnt_o ( fpu_master_gnt[i] ), + .fpu_operands_i ( fpu_master_operands[i] ), + .fpu_op_i ( fpu_master_op[i] ), + .fpu_flags_i ( fpu_master_in_flags[i] ), + .fpu_valid_o ( fpu_master_valid[i] ), + .fpu_result_o ( fpu_master_result[i] ), + .fpu_flags_o ( fpu_master_out_flags[i] ) + ); + end else begin: gen_no_fpu + assign fpu_master_gnt[i] = '0; + assign fpu_master_valid[i] = '0; + assign fpu_master_result[i] = '0; + assign fpu_master_out_flags[i] = '0; + end assign dbg_core_halted[i] = core2hmr[i].debug_halted; // Binding inputs/outputs from HMR to the system and vice versa @@ -1114,80 +1146,76 @@ hmr_unit #( //**************************************************** //**** Shared FPU cluster - Shared execution units *** //**************************************************** -// request channel -logic [NB_CORES-1:0][2:0][31:0] s_apu__operands; -logic [NB_CORES-1:0][5:0] s_apu__op; -logic [NB_CORES-1:0][2:0] s_apu__type; -logic [NB_CORES-1:0][14:0] s_apu__flags; -// response channel -logic [NB_CORES-1:0][4:0] s_apu__rflags; - -genvar k; -for(k=0;k Date: Thu, 25 Jan 2024 16:05:33 +0100 Subject: [PATCH 082/207] Directly use Questa to compile DPIs. --- Makefile | 25 ++- scripts/start.tcl | 2 +- tb/dpi/elfloader.cc | 135 ---------------- tb/dpi/elfloader.cpp | 353 ++++++++++++++++++++++++++++++++++++++++++ tb/pulp_cluster_tb.sv | 5 +- 5 files changed, 365 insertions(+), 155 deletions(-) delete mode 100644 tb/dpi/elfloader.cc create mode 100644 tb/dpi/elfloader.cpp diff --git a/Makefile b/Makefile index 73b062ea..3a01df22 100644 --- a/Makefile +++ b/Makefile @@ -4,10 +4,11 @@ ROOT_DIR = $(strip $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) +QUESTA ?= questa-2022.3 GIT ?= git BENDER ?= bender -VSIM ?= vsim -VOPT ?= vopt +VSIM ?= $(QUESTA) vsim +VOPT ?= $(QUESTA) vopt top_level ?= pulp_cluster_tb dpi-library ?= work-dpi library ?= work @@ -76,7 +77,7 @@ Bender.lock: ## Clone pulp-runtime as SW stack pulp-runtime: - git clone git@github.com:pulp-platform/pulp-runtime.git -b yt/carfield $@ + git clone git@github.com:pulp-platform/pulp-runtime.git -b astral $@ ## Clone regression tests for bare-metal verification regression-tests: @@ -92,30 +93,22 @@ sim_clean: scripts/compile.tcl: | Bender.lock $(call generate_vsim, $@, $(bender_defs) $(bender_targs),..) - -# compile the elfloader.cpp -$(dpi-library)/%.o: tb/dpi/%.cc $(dpi_hdr) - mkdir -p $(dpi-library) - $(CXX) -shared -fPIC -std=c++0x -Bsymbolic $(CFLAGS) -c $< -o $@ - -$(dpi-library)/cl_dpi.so: $(dpi) - $(CXX) -shared -m64 -o $(dpi-library)/cl_dpi.so $? -L$(RISCV)/lib -L$(SPIKE_ROOT)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_ROOT)/lib -lfesvr + echo 'vlog "$(realpath $(ROOT_DIR))/tb/dpi/elfloader.cpp" -ccflags "-std=c++11"' >> $@ + echo 'vopt +permissive -suppress 3053 -suppress 8885 +UVM_NO_RELNOTES $(top_level) -o $(top_level)_optimized' $(library): $(QUESTA) vlib $(library) -compile: $(library) $(dpi) $(dpi-library)/cl_dpi.so +compile: $(library) @test -f Bender.lock || { echo "ERROR: Bender.lock file does not exist. Did you run make checkout in bender mode?"; exit 1; } @test -f scripts/compile.tcl || { echo "ERROR: scripts/compile.tcl file does not exist. Did you run make scripts in bender mode?"; exit 1; } $(VSIM) -c -do 'quit -code [source scripts/compile.tcl]' -build: compile $(dpi) +build: compile $(VOPT) $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis - run: - $(VSIM) +permissive $(questa-flags) $(questa-cmd) -suppress 3053 -suppress 8885 -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) +APP=$(elf-bin) +notimingchecks +nospecify -t 1ps \ - $(uvm-flags) $(QUESTASIM_FLAGS) -sv_lib $(dpi-library)/cl_dpi \ + $(VSIM) +permissive $(questa-flags) $(uvm-flags) $(QUESTASIM_FLAGS) $(questa-cmd) -suppress 3053 -suppress 8885 -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) +APP=$(elf-bin) +notimingchecks +nospecify -t 1ps \ ${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) ++$(cl-bin) | tee sim.log .PHONY: test-rt-par-bare diff --git a/scripts/start.tcl b/scripts/start.tcl index 9928618e..a9ebc7fa 100644 --- a/scripts/start.tcl +++ b/scripts/start.tcl @@ -3,7 +3,7 @@ if {![info exists VSIM_PATH ]} { set VSIM_PATH "" } -vsim +permissive -suppress 3053 -suppress 8885 -lib $VSIM_PATH/work +APP=./build/test/test +notimingchecks +nospecify -t 1ps -sv_lib $VSIM_PATH/work-dpi/cl_dpi pulp_cluster_tb_optimized +permissive-off ++./build/test/test +vsim +permissive -suppress 3053 -suppress 8885 +UVM_NO_RELNOTES -lib $VSIM_PATH/work +APP=./build/test/test +notimingchecks +nospecify -t 1ps pulp_cluster_tb_optimized +permissive-off ++./build/test/test add log -r /* run -all diff --git a/tb/dpi/elfloader.cc b/tb/dpi/elfloader.cc deleted file mode 100644 index 2aa1dfb1..00000000 --- a/tb/dpi/elfloader.cc +++ /dev/null @@ -1,135 +0,0 @@ -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SHT_PROGBITS 0x1 -#define SHT_GROUP 0x11 - -// address and size -std::vector> sections; -std::map symbols; -// memory based address and content -std::map> mems; -reg_t entry; -int section_index = 0; - -void write (uint64_t address, uint64_t len, uint8_t* buf) { - uint64_t datum; - std::vector mem; - for (int i = 0; i < len; i++) { - mem.push_back(buf[i]); - } - mems.insert(std::make_pair(address, mem)); -} - -// Communicate the section address and len -// Returns: -// 0 if there are no more sections -// 1 if there are more sections to load -extern "C" char get_section (long long* address, long long* len) { - if (section_index < sections.size()) { - *address = sections[section_index].first; - *len = sections[section_index].second; - section_index++; - return 1; - } else return 0; -} - -extern "C" char read_section (long long address, const svOpenArrayHandle buffer) { - // get actual poitner - void* buf = svGetArrayPtr(buffer); - // check that the address points to a section - assert(mems.count(address) > 0); - // copy array - int i = 0; - for (auto &datum : mems.find(address)->second) { - *((char *) buf + i) = datum; - i++; - } -} - -extern "C" void read_elf(const char* filename) { - int fd = open(filename, O_RDONLY); - struct stat s; - assert(fd != -1); - if (fstat(fd, &s) < 0) - abort(); - size_t size = s.st_size; - - char* buf = (char*)mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd, 0); - assert(buf != MAP_FAILED); - close(fd); - - assert(size >= sizeof(Elf64_Ehdr)); - const Elf64_Ehdr* eh64 = (const Elf64_Ehdr*)buf; - assert(IS_ELF32(*eh64) || IS_ELF64(*eh64)); - - - - std::vector zeros; - std::map symbols; - - #define LOAD_ELF(ehdr_t, phdr_t, shdr_t, sym_t) do { \ - ehdr_t* eh = (ehdr_t*)buf; \ - phdr_t* ph = (phdr_t*)(buf + eh->e_phoff); \ - entry = eh->e_entry; \ - assert(size >= eh->e_phoff + eh->e_phnum*sizeof(*ph)); \ - for (unsigned i = 0; i < eh->e_phnum; i++) { \ - if(ph[i].p_type == PT_LOAD && ph[i].p_memsz) { \ - if (ph[i].p_filesz) { \ - assert(size >= ph[i].p_offset + ph[i].p_filesz); \ - sections.push_back(std::make_pair(ph[i].p_paddr, ph[i].p_memsz)); \ - write(ph[i].p_paddr, ph[i].p_filesz, (uint8_t*)buf + ph[i].p_offset); \ - } \ - zeros.resize(ph[i].p_memsz - ph[i].p_filesz); \ - } \ - } \ - shdr_t* sh = (shdr_t*)(buf + eh->e_shoff); \ - assert(size >= eh->e_shoff + eh->e_shnum*sizeof(*sh)); \ - assert(eh->e_shstrndx < eh->e_shnum); \ - assert(size >= sh[eh->e_shstrndx].sh_offset + sh[eh->e_shstrndx].sh_size); \ - char *shstrtab = buf + sh[eh->e_shstrndx].sh_offset; \ - unsigned strtabidx = 0, symtabidx = 0; \ - for (unsigned i = 0; i < eh->e_shnum; i++) { \ - unsigned max_len = sh[eh->e_shstrndx].sh_size - sh[i].sh_name; \ - if ((sh[i].sh_type & SHT_GROUP) && strcmp(shstrtab + sh[i].sh_name, ".strtab") != 0 && strcmp(shstrtab + sh[i].sh_name, ".shstrtab") != 0) \ - assert(strnlen(shstrtab + sh[i].sh_name, max_len) < max_len); \ - if (sh[i].sh_type & SHT_PROGBITS) continue; \ - if (strcmp(shstrtab + sh[i].sh_name, ".strtab") == 0) \ - strtabidx = i; \ - if (strcmp(shstrtab + sh[i].sh_name, ".symtab") == 0) \ - symtabidx = i; \ - } \ - if (strtabidx && symtabidx) { \ - char* strtab = buf + sh[strtabidx].sh_offset; \ - sym_t* sym = (sym_t*)(buf + sh[symtabidx].sh_offset); \ - for (unsigned i = 0; i < sh[symtabidx].sh_size/sizeof(sym_t); i++) { \ - unsigned max_len = sh[strtabidx].sh_size - sym[i].st_name; \ - assert(sym[i].st_name < sh[strtabidx]. sh_size); \ - assert(strnlen(strtab + sym[i].st_name, max_len) < max_len); \ - symbols[strtab + sym[i].st_name] = sym[i].st_value; \ - } \ - } \ - } while(0) - - if (IS_ELF32(*eh64)) - LOAD_ELF(Elf32_Ehdr, Elf32_Phdr, Elf32_Shdr, Elf32_Sym); - else - LOAD_ELF(Elf64_Ehdr, Elf64_Phdr, Elf64_Shdr, Elf64_Sym); - - munmap(buf, size); -} diff --git a/tb/dpi/elfloader.cpp b/tb/dpi/elfloader.cpp new file mode 100644 index 00000000..4bb0fd62 --- /dev/null +++ b/tb/dpi/elfloader.cpp @@ -0,0 +1,353 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Modified version of the RISC-V Frontend Server +// (https://github.com/riscvarchive/riscv-fesvr, e41cfc3001293b5625c25412bd9b26e6e4ab8f7e) +// +// Nicole Narr +// Christopher Reinwardt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IS_ELF(hdr) \ + ((hdr).e_ident[0] == 0x7f && (hdr).e_ident[1] == 'E' && \ + (hdr).e_ident[2] == 'L' && (hdr).e_ident[3] == 'F') + +#define IS_ELF32(hdr) (IS_ELF(hdr) && (hdr).e_ident[4] == 1) +#define IS_ELF64(hdr) (IS_ELF(hdr) && (hdr).e_ident[4] == 2) + +#define PT_LOAD 1 +#define SHT_NOBITS 8 +#define SHT_PROGBITS 0x1 +#define SHT_GROUP 0x11 + +typedef struct { + uint8_t e_ident[16]; + uint16_t e_type; + uint16_t e_machine; + uint32_t e_version; + uint32_t e_entry; + uint32_t e_phoff; + uint32_t e_shoff; + uint32_t e_flags; + uint16_t e_ehsize; + uint16_t e_phentsize; + uint16_t e_phnum; + uint16_t e_shentsize; + uint16_t e_shnum; + uint16_t e_shstrndx; +} Elf32_Ehdr; + +typedef struct { + uint32_t sh_name; + uint32_t sh_type; + uint32_t sh_flags; + uint32_t sh_addr; + uint32_t sh_offset; + uint32_t sh_size; + uint32_t sh_link; + uint32_t sh_info; + uint32_t sh_addralign; + uint32_t sh_entsize; +} Elf32_Shdr; + +typedef struct +{ + uint32_t p_type; + uint32_t p_offset; + uint32_t p_vaddr; + uint32_t p_paddr; + uint32_t p_filesz; + uint32_t p_memsz; + uint32_t p_flags; + uint32_t p_align; +} Elf32_Phdr; + +typedef struct +{ + uint32_t st_name; + uint32_t st_value; + uint32_t st_size; + uint8_t st_info; + uint8_t st_other; + uint16_t st_shndx; +} Elf32_Sym; + +typedef struct { + uint8_t e_ident[16]; + uint16_t e_type; + uint16_t e_machine; + uint32_t e_version; + uint64_t e_entry; + uint64_t e_phoff; + uint64_t e_shoff; + uint32_t e_flags; + uint16_t e_ehsize; + uint16_t e_phentsize; + uint16_t e_phnum; + uint16_t e_shentsize; + uint16_t e_shnum; + uint16_t e_shstrndx; +} Elf64_Ehdr; + +typedef struct { + uint32_t sh_name; + uint32_t sh_type; + uint64_t sh_flags; + uint64_t sh_addr; + uint64_t sh_offset; + uint64_t sh_size; + uint32_t sh_link; + uint32_t sh_info; + uint64_t sh_addralign; + uint64_t sh_entsize; +} Elf64_Shdr; + +typedef struct { + uint32_t p_type; + uint32_t p_flags; + uint64_t p_offset; + uint64_t p_vaddr; + uint64_t p_paddr; + uint64_t p_filesz; + uint64_t p_memsz; + uint64_t p_align; +} Elf64_Phdr; + +typedef struct { + uint32_t st_name; + uint8_t st_info; + uint8_t st_other; + uint16_t st_shndx; + uint64_t st_value; + uint64_t st_size; +} Elf64_Sym; + +// address and size +std::vector> sections; + +// memory based address and content +std::map> mems; + +// Entrypoint +uint64_t entry = 0; +int section_index = 0; + +extern "C" { + char get_entry(long long *entry_ret); + char get_section(long long *address_ret, long long *len_ret); + char read_section(long long address, const svOpenArrayHandle buffer, long long len); + char read_elf(const char *filename); +} + +static void write (uint64_t address, uint64_t len, uint8_t *buf) +{ + std::vector mem; + for (int i = 0; i < len; i++) { + mem.push_back(buf[i]); + } + mems.insert(std::make_pair(address, mem)); +} + +// Return the entry point reported by the ELF file +// Must be called after reading the elf file obviously +extern "C" char get_entry(long long *entry_ret) +{ + *entry_ret = entry; + return 0; +} + +// Iterator over the section addresses and lengths +// Returns: +// 0 if there are no more sections +// 1 if there are more sections to load +extern "C" char get_section(long long *address_ret, long long *len_ret) +{ + if (section_index < sections.size()) { + *address_ret = sections[section_index].first; + *len_ret = sections[section_index].second; + section_index++; + return 1; + } else { + return 0; + } +} + +extern "C" char read_section(long long address, const svOpenArrayHandle buffer, long long len) +{ + // get actual pointer + char *buf = (char *) svGetArrayPtr(buffer); + + // check that the address points to a section + if (!mems.count(address)) { + printf("[ELF] ERROR: No section found for address %p\n", address); + return -1; + } + + // copy array + long long int len_tmp = len; + for (auto &datum : mems.find(address)->second) { + if(len_tmp-- == 0){ + printf("[ELF] ERROR: Copied 0x%lx bytes. Buffer is full but there is still data available.\n", len); + return -1; + } + + *buf++ = datum; + } + + return 0; +} + +template +static void load_elf(char *buf, size_t size) +{ + E *eh = (E *) buf; + P *ph = (P *) (buf + eh->e_phoff); + Sh *sh = (Sh *) (buf + eh->e_shoff); + + char *shstrtab = NULL; + + if(size < eh->e_phoff + (eh->e_phnum * sizeof(P))){ + printf("[ELF] ERROR: Filesize is smaller than advertised program headers (0x%lx vs 0x%lx)\n", size, eh->e_phoff + (eh->e_phnum * sizeof(P))); + return; + } + + entry = eh->e_entry; + printf("[ELF] INFO: Entrypoint at %p\n", entry); + + // Iterate over all program header entries + for (unsigned int i = 0; i < eh->e_phnum; i++) { + // Check whether the current program header entry contains a loadable section of nonzero size + if(ph[i].p_type == PT_LOAD && ph[i].p_memsz) { + // Is this section something else than zeros? + if (ph[i].p_filesz) { + assert(size >= ph[i].p_offset + ph[i].p_filesz); + sections.push_back(std::make_pair(ph[i].p_paddr, ph[i].p_memsz)); + write(ph[i].p_paddr, ph[i].p_filesz, (uint8_t*)buf + ph[i].p_offset); + } + + if(ph[i].p_memsz > ph[i].p_filesz){ + printf("[ELF] WARNING: The section starting @ %p contains 0x%lx zero bytes which will NOT be preloaded!\n", + ph[i].p_paddr, (ph[i].p_memsz - ph[i].p_filesz)); + } + } + } + + if(size < eh->e_shoff + (eh->e_shnum * sizeof(Sh))){ + printf("[ELF] ERROR: Filesize is smaller than advertised section headers (0x%lx vs 0x%lx)\n", + size, eh->e_shoff + (eh->e_shnum * sizeof(Sh))); + return; + } + + if(eh->e_shstrndx >= eh->e_shnum){ + printf("[ELF] ERROR: Malformed ELF file. The index of the section header strings is out of bounds (0x%lx vs max 0x%lx)", + eh->e_shstrndx, eh->e_shnum); + return; + } + + if(size < sh[eh->e_shstrndx].sh_offset + sh[eh->e_shstrndx].sh_size){ + printf("[ELF] ERROR: Filesize is smaller than advertised size of section name table (0x%lx vs 0x%lx)\n", + size, sh[eh->e_shstrndx].sh_offset + sh[eh->e_shstrndx].sh_size); + return; + } + + // Get a direct pointer to the section name section + shstrtab = buf + sh[eh->e_shstrndx].sh_offset; + unsigned int strtabidx = 0, symtabidx = 0; + + // Iterate over all section headers to find .strtab and .symtab + for (unsigned int i = 0; i < eh->e_shnum; i++) { + // Get an upper limit on how long the name can be (length of the section name section minus the offset of the name) + unsigned int max_len = sh[eh->e_shstrndx].sh_size - sh[i].sh_name; + + // Is this the string table? + if(strcmp(shstrtab + sh[i].sh_name, ".strtab") == 0){ + printf("[ELF] INFO: Found string table at offset 0x%lx\n", sh[i].sh_offset); + strtabidx = i; + continue; + } + + // Is this the symbol table? + if(strcmp(shstrtab + sh[i].sh_name, ".symtab") == 0){ + printf("[ELF] INFO: Found symbol table at offset 0x%lx\n", sh[i].sh_offset); + symtabidx = i; + continue; + } + } +} + +extern "C" char read_elf(const char *filename) +{ + char *buf = NULL; + Elf64_Ehdr* eh64 = NULL; + int fd = open(filename, O_RDONLY); + char retval = 0; + struct stat s; + size_t size = 0; + + if(fd == -1){ + printf("[ELF] ERROR: Unable to open file %s\n", filename); + retval = -1; + goto exit; + } + + if(fstat(fd, &s) < 0) { + printf("[ELF] ERROR: Unable to read stats for file %s\n", filename); + retval = -1; + goto exit_fd; + } + + size = s.st_size; + + if(size < sizeof(Elf64_Ehdr)){ + printf("[ELF] ERROR: File %s is too small to contain a valid ELF header (0x%lx vs 0x%lx)\n", filename, size, sizeof(Elf64_Ehdr)); + retval = -1; + goto exit_fd; + } + + buf = (char *) mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd, 0); + if(buf == MAP_FAILED){ + printf("[ELF] ERROR: Unable to memory map file %s\n", filename); + retval = -1; + goto exit_fd; + } + + printf("[ELF] INFO: File %s was memory mapped to %p\n", filename, buf); + + eh64 = (Elf64_Ehdr *) buf; + + if(!(IS_ELF32(*eh64) || IS_ELF64(*eh64))){ + printf("[ELF] ERROR: File %s does not contain a valid ELF signature\n", filename); + retval = -1; + goto exit_mmap; + } + + if (IS_ELF32(*eh64)){ + load_elf(buf, size); + } else { + load_elf(buf, size); + } + +exit_mmap: + munmap(buf, size); + +exit_fd: + close(fd); + +exit: + return retval; +} diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index bf36d3f7..2b8ec71e 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -17,13 +17,12 @@ `timescale 1ps/1ps `include "pulp_soc_defines.sv" -`include "uvm_macros.svh" `include "axi/assign.svh" `include "axi/typedef.svh" import "DPI-C" function read_elf(input string filename); import "DPI-C" function byte get_section(output longint address, output longint len); -import "DPI-C" context function byte read_section(input longint address, inout byte buffer[]); +import "DPI-C" context function byte read_section(input longint address, inout byte buffer[], input longint len); module pulp_cluster_tb; @@ -397,7 +396,7 @@ module pulp_cluster_tb; sections[section_addr >> AxiWideByteOffset] = num_words; buffer = new[num_words * AxiWideBeWidth]; - void'(read_section(section_addr, buffer)); + void'(read_section(section_addr, buffer, section_len)); for (int i = 0; i < num_words; i++) begin automatic logic [AxiWideBeWidth-1:0][7:0] word = '0; for (int j = 0; j < AxiWideBeWidth; j++) begin From 9bfeba948d0345a67baea95656b0511b198f5ab8 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 25 Jan 2024 22:56:24 +0100 Subject: [PATCH 083/207] Add private FPUs. --- Bender.local | 1 + Bender.lock | 14 +++++++++++--- Bender.yml | 4 ++-- rtl/pulp_cluster.sv | 38 ++++---------------------------------- 4 files changed, 18 insertions(+), 39 deletions(-) diff --git a/Bender.local b/Bender.local index 2386c8ee..c6274f27 100644 --- a/Bender.local +++ b/Bender.local @@ -1,4 +1,5 @@ overrides: + hci : { git: "https://github.com/pulp-platform/hci.git" , rev: 3cb3d99b2cebfeed55cb6ab9d98fce7b99e97cb9 } # branch: master axi : { git: "https://github.com/pulp-platform/axi.git" , version: =0.39.1-beta } register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix diff --git a/Bender.lock b/Bender.lock index c86f60bb..ceaaed57 100644 --- a/Bender.lock +++ b/Bender.lock @@ -104,8 +104,16 @@ packages: Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git dependencies: - common_cells + fpu_interco: + revision: b5f7a315929308823cacd81e1e4898f1eeecfc64 + version: null + source: + Git: https://github.com/pulp-platform/fpu_interco.git + dependencies: + - fpnew + - riscv hci: - revision: 78fb8fc8a6f2c376554562c47755b4d0febaba25 + revision: 3cb3d99b2cebfeed55cb6ab9d98fce7b99e97cb9 version: null source: Git: https://github.com/pulp-platform/hci.git @@ -133,8 +141,8 @@ packages: dependencies: - tech_cells_generic hwpe-stream: - revision: ddc154424187dff42a8fcec946c768ceb13f13de - version: 1.6.4 + revision: 389bd7fb1975d2df1546910c5f220c668122e646 + version: 1.6.5 source: Git: https://github.com/pulp-platform/hwpe-stream.git dependencies: diff --git a/Bender.yml b/Bender.yml index e0c2c881..7347953d 100644 --- a/Bender.yml +++ b/Bender.yml @@ -21,7 +21,7 @@ dependencies: idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a971e364bf8090cf77fafad995b480c1ac7ea4e0" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: c015839816938a790c8da5fd5829cfc536f1ca9c } # branch: yt/return-reg - # fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "4aec4b68424947b0c4cf25fd7c4b907cb9ec3dfa" } # branch: yt/carfield + fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "b5f7a315929308823cacd81e1e4898f1eeecfc64" } # branch: astral axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } @@ -31,7 +31,7 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: b2e6f391aa6c10c03f45b693d80a0aaddecf169b } # branch: master + hci: { git: "https://github.com/pulp-platform/hci.git", rev: 3cb3d99b2cebfeed55cb6ab9d98fce7b99e97cb9 } # branch: test_mode_fix register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 32023555679cfdb8a0a073ad4c17fc3a5d1ddea5 } # branch: yt/rapidrecovery diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index c31e6022..f3786487 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -27,6 +27,7 @@ module pulp_cluster import pulp_cluster_package::*; import hci_package::*; import rapid_recovery_pkg::*; + import fpnew_pkg::*; #( // cluster parameters parameter CORE_TYPE_CL = 1, // 0 for CV32, 1 for RI5CY, 2 for IBEX RV32IMC @@ -70,7 +71,7 @@ module pulp_cluster parameter INSTR_RDATA_WIDTH = 32, parameter bit CLUST_FPU = 1, - parameter int unsigned NumFpu = NB_CORES, + parameter int unsigned NumFpus = NB_CORES, parameter CLUST_FP_DIVSQRT = 0, parameter CLUST_SHARED_FP = 0, parameter CLUST_SHARED_FP_DIVSQRT = 0, @@ -967,37 +968,6 @@ generate .apu_master_flags_i ( fpu_master_out_flags[i] ) ); - if (CLUST_FPU) begin: gen_fpu - fpu_wrap #( - .DataWidth ( 32 ), - .FpuNumOperands ( APU_NARGS_CPU ), - .FpuOpcodeWidth ( APU_WOP_CPU ), - .FpuInFlagsWidth ( APU_NDSFLAGS_CPU ), - .FpuOutFlagsWidth ( APU_NUSFLAGS_CPU ), - .FpuFmtBits ( fpnew_pkg::FP_FORMAT_BITS ), - .FpuIntFmtBits ( fpnew_pkg::INT_FORMAT_BITS ), - .FpuRoundBits ( 3 ), - .FpuOpBits ( fpnew_pkg::OP_BITS ), - .FpuDivSqrt ( CLUST_FP_DIVSQRT ) - ) i_fpu_wrap ( - .clk_i ( clk_core[i] ), - .rst_ni ( rst_ni ), - .hart_id_i ( i ), - .fpu_req_i ( fpu_master_req[i] ), - .fpu_gnt_o ( fpu_master_gnt[i] ), - .fpu_operands_i ( fpu_master_operands[i] ), - .fpu_op_i ( fpu_master_op[i] ), - .fpu_flags_i ( fpu_master_in_flags[i] ), - .fpu_valid_o ( fpu_master_valid[i] ), - .fpu_result_o ( fpu_master_result[i] ), - .fpu_flags_o ( fpu_master_out_flags[i] ) - ); - end else begin: gen_no_fpu - assign fpu_master_gnt[i] = '0; - assign fpu_master_valid[i] = '0; - assign fpu_master_result[i] = '0; - assign fpu_master_out_flags[i] = '0; - end assign dbg_core_halted[i] = core2hmr[i].debug_halted; // Binding inputs/outputs from HMR to the system and vice versa @@ -1146,7 +1116,7 @@ hmr_unit #( //**************************************************** //**** Shared FPU cluster - Shared execution units *** //**************************************************** -if (CLUST_SHARED_FP) begin: gen_shared_fpu +if (CLUST_FPU) begin: gen_fpu_subsystem // request channel logic [NB_CORES-1:0][2:0][31:0] s_apu__operands; logic [NB_CORES-1:0][5:0] s_apu__op; @@ -1166,7 +1136,7 @@ if (CLUST_SHARED_FP) begin: gen_shared_fpu shared_fpu_cluster #( .NB_CORES ( NB_CORES ), .NB_APUS ( 1 ), - .NB_FPNEW ( 4 ), + .NB_FPNEW ( NumFpus ), .FP_TYPE_WIDTH ( 3 ), .NB_CORE_ARGS ( 3 ), From 3931d03a4599cc0a7b12ad351378fb6423893bfc Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 25 Jan 2024 23:07:43 +0100 Subject: [PATCH 084/207] Delete FPU wrapper. --- Bender.yml | 1 - rtl/fpu_wrap.sv | 114 ------------------------------------------------ 2 files changed, 115 deletions(-) delete mode 100644 rtl/fpu_wrap.sv diff --git a/Bender.yml b/Bender.yml index 7347953d..823bc714 100644 --- a/Bender.yml +++ b/Bender.yml @@ -72,7 +72,6 @@ sources: - rtl/cluster_peripherals.sv - rtl/data_periph_demux.sv - rtl/core_demux_wrap.sv - - rtl/fpu_wrap.sv # Level 2 - rtl/core_region.sv - target: simulation diff --git a/rtl/fpu_wrap.sv b/rtl/fpu_wrap.sv deleted file mode 100644 index 5cba5e50..00000000 --- a/rtl/fpu_wrap.sv +++ /dev/null @@ -1,114 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -module fpu_wrap - import riscv_defines::*; -#( - parameter int unsigned DataWidth = 32, - parameter int unsigned FpuNumOperands = 3, - parameter int unsigned FpuOpcodeWidth = 6, - parameter int unsigned FpuInFlagsWidth = 15, - parameter int unsigned FpuOutFlagsWidth = 5, - parameter int unsigned FpuFmtBits = fpnew_pkg::FP_FORMAT_BITS, - parameter int unsigned FpuIntFmtBits = fpnew_pkg::INT_FORMAT_BITS, - parameter int unsigned FpuRoundBits = 3, - parameter int unsigned FpuOpBits = fpnew_pkg::OP_BITS, - parameter int unsigned FpuDivSqrt = 0 -)( - // Clock and Reset - input logic clk_i, - input logic rst_ni, - input logic [31:0] hart_id_i, - // APU Side: Master port - input logic fpu_req_i, - output logic fpu_gnt_o, - // request channel - input logic [FpuNumOperands-1:0][DataWidth-1:0] fpu_operands_i, - input logic [FpuOpcodeWidth-1:0] fpu_op_i, - input logic [FpuInFlagsWidth-1:0] fpu_flags_i, - // response channel - output logic fpu_valid_o, - output logic [DataWidth-1:0] fpu_result_o, - output logic [FpuOutFlagsWidth-1:0] fpu_flags_o -); - -localparam fpnew_pkg::unit_type_t C_DIV = FpuDivSqrt ? fpnew_pkg::MERGED : - fpnew_pkg::DISABLED; - -logic fpu_op_mod; -logic fpu_vec_op; -logic [FpuOpBits-1:0] fpu_op; - -logic [FpuFmtBits-1:0] dst_fmt; -logic [FpuFmtBits-1:0] src_fmt; -logic [FpuIntFmtBits-1:0] int_fmt; -logic [FpuRoundBits-1:0] fp_rnd_mode; - -assign {fpu_vec_op, fpu_op_mod, fpu_op} = fpu_op_i; -assign {int_fmt, src_fmt, dst_fmt, fp_rnd_mode} = fpu_flags_i; - -// ----------- -// FPU Config -// ----------- -// Features (enabled formats, vectors etc.) -localparam fpnew_pkg::fpu_features_t FpuFeatures = '{ - Width: C_FLEN, - EnableVectors: C_XFVEC, - EnableNanBox: 1'b0, - FpFmtMask: {C_RVF, C_RVD, C_XF16, C_XF8, C_XF16ALT, C_XF8ALT}, - IntFmtMask: {C_XFVEC && (C_XF8 || C_XF8ALT), - C_XFVEC && (C_XF16 || C_XF16ALT), 1'b1, 1'b0} -}; - -// Implementation (number of registers etc) -localparam fpnew_pkg::fpu_implementation_t FpuImplementation = '{ - PipeRegs: '{// FP32, FP64, FP16, FP8, FP16alt, FP8alt - '{C_LAT_FP32, C_LAT_FP64, - C_LAT_FP16, C_LAT_FP8 , - C_LAT_FP16ALT, C_LAT_FP8ALT}, // ADDMUL - '{default: C_LAT_DIVSQRT}, // DIVSQRT - '{default: C_LAT_NONCOMP}, // NONCOMP - '{default: C_LAT_CONV }, // CONV - '{default: C_LAT_DOTP }}, // SDOTP - UnitTypes: '{'{default: fpnew_pkg::MERGED}, // ADDMUL - '{default: C_DIV}, // DIVSQRT - '{default: fpnew_pkg::PARALLEL}, // NONCOMP - '{default: fpnew_pkg::MERGED}, // CONV - '{default: fpnew_pkg::DISABLED}}, // SDOTP - PipeConfig: fpnew_pkg::BEFORE -}; - -//--------------- -// FPU instance -//--------------- -fpnew_top #( - .Features ( FpuImplementation ), - .Implementation ( FpuFeatures ), - .TagType ( logic ) -) i_fpnew ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .hart_id_i ( hart_id_i ), - .operands_i ( fpu_operands_i ), - .rnd_mode_i ( fpnew_pkg::roundmode_e'(fp_rnd_mode) ), - .op_i ( fpnew_pkg::operation_e'(fpu_op) ), - .op_mod_i ( fpu_op_mod ), - .src_fmt_i ( fpnew_pkg::fp_format_e'(src_fmt) ), - .dst_fmt_i ( fpnew_pkg::fp_format_e'(dst_fmt) ), - .int_fmt_i ( fpnew_pkg::int_format_e'(int_fmt) ), - .vectorial_op_i ( fpu_vec_op ), - .tag_i ( '0 ), - .simd_mask_i ( '1 ), - .in_valid_i ( fpu_req_i ), - .in_ready_o ( fpu_gnt_o ), - .flush_i ( '0 ), - .result_o ( fpu_result_o ), - .status_o ( fpu_flags_o ), - .tag_o ( ), - .out_valid_o ( fpu_valid_o ), - .out_ready_i ( 1'b1 ), - .busy_o ( ) -); - -endmodule: fpu_wrap From b373cb03192babb3d1dbcd726ad353bc721bac4c Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 27 Jan 2024 00:12:07 +0100 Subject: [PATCH 085/207] Rmove shared FPU and bump core. --- Bender.lock | 10 +--- Bender.yml | 3 +- rtl/core_region.sv | 2 +- rtl/pulp_cluster.sv | 109 ++++---------------------------------------- 4 files changed, 13 insertions(+), 111 deletions(-) diff --git a/Bender.lock b/Bender.lock index ceaaed57..f86b28ba 100644 --- a/Bender.lock +++ b/Bender.lock @@ -104,14 +104,6 @@ packages: Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git dependencies: - common_cells - fpu_interco: - revision: b5f7a315929308823cacd81e1e4898f1eeecfc64 - version: null - source: - Git: https://github.com/pulp-platform/fpu_interco.git - dependencies: - - fpnew - - riscv hci: revision: 3cb3d99b2cebfeed55cb6ab9d98fce7b99e97cb9 version: null @@ -224,7 +216,7 @@ packages: - common_cells - common_verification riscv: - revision: a1dcae35edae6092ddbf92c424690cb903b678d5 + revision: c760db14dbd6cc3ec3b8ae8274df2eac7225bcac version: null source: Git: git@github.com:AlSaqr-platform/riscv_nn.git diff --git a/Bender.yml b/Bender.yml index 823bc714..8b2df85e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -21,13 +21,12 @@ dependencies: idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a971e364bf8090cf77fafad995b480c1ac7ea4e0" } # branch: yt/carfield cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: c015839816938a790c8da5fd5829cfc536f1ca9c } # branch: yt/return-reg - fpu_interco: { git: "https://github.com/pulp-platform/fpu_interco.git", rev: "b5f7a315929308823cacd81e1e4898f1eeecfc64" } # branch: astral axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: a1dcae35edae6092ddbf92c424690cb903b678d5 } # branch: yt/hmr + riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: astral-v1.0 } cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 485030de..057c5ad8 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -238,7 +238,7 @@ import rapid_recovery_pkg::*; .PULP_CLUSTER ( 1 ), .FPU ( FPU ), .N_EXT_PERF_COUNTERS ( N_EXT_PERF_COUNTERS_ACTUAL ), - .Zfinx ( 0 ), + .Zfinx ( FPU ), .WAPUTYPE ( WAPUTYPE ), .DM_HaltAddress ( DEBUG_START_ADDR + 16'h0800 ) ) RI5CY_CORE ( diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index f3786487..e0f9ed98 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -424,21 +424,6 @@ hci_core_intf #( // cores -> event unit ctrl XBAR_PERIPH_BUS s_core_euctrl_bus[NB_CORES-1:0](); -// apu-interconnect -// handshake signals -logic [NB_CORES-1:0] fpu_master_req; -logic [NB_CORES-1:0] fpu_master_gnt; -// request channel -logic [NB_CORES-1:0][APU_NARGS_CPU-1:0][31:0] fpu_master_operands; -logic [NB_CORES-1:0][APU_WOP_CPU-1:0] fpu_master_op; -logic [NB_CORES-1:0][WAPUTYPE-1:0] fpu_master_type; -logic [NB_CORES-1:0][APU_NDSFLAGS_CPU-1:0] fpu_master_in_flags; -// response channel -logic [NB_CORES-1:0] fpu_master_rready; -logic [NB_CORES-1:0] fpu_master_valid; -logic [NB_CORES-1:0][31:0] fpu_master_result; -logic [NB_CORES-1:0][APU_NUSFLAGS_CPU-1:0] fpu_master_out_flags; - //----------------------------------------------------------------------// // Interfaces between ICache - L0 - Icache_Interco and Icache_ctrl_unit // // // @@ -956,16 +941,16 @@ generate .pc_backup_o ( backup_bus[i].pc_backup ), .csr_backup_o ( backup_bus[i].csr_backup ), //apu interface - .apu_master_req_o ( fpu_master_req [i] ), - .apu_master_gnt_i ( fpu_master_gnt [i] ), - .apu_master_type_o ( fpu_master_type [i] ), - .apu_master_operands_o ( fpu_master_operands [i] ), - .apu_master_op_o ( fpu_master_op [i] ), - .apu_master_flags_o ( fpu_master_in_flags [i] ), - .apu_master_valid_i ( fpu_master_valid [i] ), - .apu_master_ready_o ( fpu_master_rready [i] ), - .apu_master_result_i ( fpu_master_result [i] ), - .apu_master_flags_i ( fpu_master_out_flags[i] ) + .apu_master_req_o ( ), + .apu_master_gnt_i ( '0 ), + .apu_master_type_o ( ), + .apu_master_operands_o ( ), + .apu_master_op_o ( ), + .apu_master_flags_o ( ), + .apu_master_valid_i ( '0 ), + .apu_master_ready_o ( ), + .apu_master_result_i ( '0 ), + .apu_master_flags_i ( '0 ) ); assign dbg_core_halted[i] = core2hmr[i].debug_halted; @@ -1113,80 +1098,6 @@ hmr_unit #( .core_bus_outputs_i ( '0 ) ); -//**************************************************** -//**** Shared FPU cluster - Shared execution units *** -//**************************************************** -if (CLUST_FPU) begin: gen_fpu_subsystem - // request channel - logic [NB_CORES-1:0][2:0][31:0] s_apu__operands; - logic [NB_CORES-1:0][5:0] s_apu__op; - logic [NB_CORES-1:0][2:0] s_apu__type; - logic [NB_CORES-1:0][14:0] s_apu__flags; - // response channel - logic [NB_CORES-1:0][4:0] s_apu__rflags; - - for(genvar k=0; k< NB_CORES; k++) begin - assign s_apu__operands[k][2:0] = fpu_master_operands[k][2:0]; - assign s_apu__op[k][5:0] = fpu_master_op[k][5:0]; - assign s_apu__type[k][2:0] = fpu_master_type[k][2:0]; - assign s_apu__flags[k][14:0] = fpu_master_in_flags[k][14:0]; - assign fpu_master_out_flags[k][4:0] = s_apu__rflags[k][4:0]; - end - - shared_fpu_cluster #( - .NB_CORES ( NB_CORES ), - .NB_APUS ( 1 ), - .NB_FPNEW ( NumFpus ), - .FP_TYPE_WIDTH ( 3 ), - - .NB_CORE_ARGS ( 3 ), - .CORE_DATA_WIDTH ( 32 ), - .CORE_OPCODE_WIDTH ( 6 ), - .CORE_DSFLAGS_CPU ( 15 ), - .CORE_USFLAGS_CPU ( 5 ), - - .NB_APU_ARGS ( 2 ), - .APU_OPCODE_WIDTH ( 6 ), - .APU_DSFLAGS_CPU ( 15 ), - .APU_USFLAGS_CPU ( 5 ), - - .NB_FPNEW_ARGS ( 3 ), //= 3, - .FPNEW_OPCODE_WIDTH ( 6 ), //= 6, - .FPNEW_DSFLAGS_CPU ( 15 ), //= 15, - .FPNEW_USFLAGS_CPU ( 5 ), //= 5, - - .APUTYPE_ID ( 1 ), - .FPNEWTYPE_ID ( 0 ), - - .C_FPNEW_FMTBITS (fpnew_pkg::FP_FORMAT_BITS ), - .C_FPNEW_IFMTBITS (fpnew_pkg::INT_FORMAT_BITS ), - .C_ROUND_BITS (3 ), - .C_FPNEW_OPBITS (fpnew_pkg::OP_BITS ), - .USE_FPU_OPT_ALLOC ("FALSE"), - .USE_FPNEW_OPT_ALLOC ("TRUE"), - .FPNEW_INTECO_TYPE ("SINGLE_INTERCO") - ) i_shared_fpu_cluster ( - .clk ( clk_i ), - .rst_n ( rst_ni ), - .test_mode_i ( test_mode_i ), - .core_slave_req_i ( fpu_master_req ), - .core_slave_gnt_o ( fpu_master_gnt ), - .core_slave_type_i ( s_apu__type ), - .core_slave_operands_i ( s_apu__operands ), - .core_slave_op_i ( s_apu__op ), - .core_slave_flags_i ( s_apu__flags ), - .core_slave_rready_i ( fpu_master_rready ), - .core_slave_rvalid_o ( fpu_master_valid ), - .core_slave_rdata_o ( fpu_master_result ), - .core_slave_rflags_o ( s_apu__rflags ) - ); -end else begin: gen_no_shared_fpu - assign fpu_master_gnt = '0; - assign fpu_master_valid = '0; - assign fpu_master_result = '0; - assign fpu_master_out_flags = '0; -end - //************************************************************** //**** HW Processing Engines / Cluster-Coupled Accelerators **** //************************************************************** From 388261e1a8fb248e9dd25cf3dd63917cb14b6e2e Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 27 Jan 2024 00:15:55 +0100 Subject: [PATCH 086/207] Update regression-tests fetch branch. --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3a01df22..039e1c7e 100644 --- a/Makefile +++ b/Makefile @@ -81,7 +81,7 @@ pulp-runtime: ## Clone regression tests for bare-metal verification regression-tests: - git clone git@github.com:pulp-platform/regression_tests.git -b yt/carfield $@ + git clone git@github.com:pulp-platform/regression_tests.git -b astral $@ ######################## # Build and simulation # From a697a658cfeb08120eeb350a3be830b2a033d9bb Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 27 Jan 2024 01:03:17 +0100 Subject: [PATCH 087/207] Reduce number of cores. --- rtl/pulp_cluster.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index e0f9ed98..8bb71ea9 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -31,7 +31,7 @@ module pulp_cluster #( // cluster parameters parameter CORE_TYPE_CL = 1, // 0 for CV32, 1 for RI5CY, 2 for IBEX RV32IMC - parameter NB_CORES = 12, + parameter NB_CORES = 8, parameter NB_HWPE_PORTS = 9, // number of DMA TCDM plugs, NOT number of DMA slave peripherals! // Everything will go to hell if you change this! From 5b211bee65ff4054251029ae1df698043a822651 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 27 Jan 2024 02:06:03 +0100 Subject: [PATCH 088/207] Update number of cores in PULP SoC defines. --- include/pulp_soc_defines.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/pulp_soc_defines.sv b/include/pulp_soc_defines.sv index 54307677..5307196e 100644 --- a/include/pulp_soc_defines.sv +++ b/include/pulp_soc_defines.sv @@ -47,7 +47,7 @@ //PARAMETRES `define NB_CLUSTERS 1 -`define NB_CORES 12 +`define NB_CORES 8 `define NB_DMAS 4 `define NB_MPERIPHS 1 `define NB_SPERIPHS 10 From b45d55471f5d47d0aaa7cbb3389eb07411f33ee2 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 28 Jan 2024 10:20:50 +0100 Subject: [PATCH 089/207] Add ECC SRAMs. --- rtl/pulp_cluster.sv | 30 ++++++++---- rtl/tcdm_banks_wrap.sv | 105 ++++++++++++++++++++++++++++++----------- 2 files changed, 97 insertions(+), 38 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 8bb71ea9..c0637447 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -1246,17 +1246,27 @@ assign s_core_instr_bus.aw_atop = '0; /* TCDM banks */ tcdm_banks_wrap #( - .BankSize (TCDM_NUM_ROWS), - .NbBanks (NB_TCDM_BANKS), - .DataWidth(DATA_WIDTH ), - .AddrWidth(ADDR_WIDTH ), - .BeWidth (BE_WIDTH ), - .IdWidth (TCDM_ID_WIDTH) + .BankSize (TCDM_NUM_ROWS), + .NbBanks (NB_TCDM_BANKS), + .DataWidth (DATA_WIDTH ), + .AddrWidth (ADDR_WIDTH ), + .BeWidth (BE_WIDTH ), + .IdWidth (TCDM_ID_WIDTH), + .EnableEcc ( 1 ), + .EccInterco ( 0 ) // Not supported at the moment ) tcdm_banks_i ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .test_mode_i(test_mode_i ), - .tcdm_slave (s_tcdm_bus_sram) //PMU ?? + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_mode_i ( test_mode_i ), + // Scrubber + .scrub_trigger_i ( '0 ), // TODO: to be connected to a register + // in the cluster control unit. + .scrub_fix_o ( /* TODO: left pending */ ), + .scrub_uncorrectable_o ( /* TODO: left pending */ ), + // ECC + .ecc_single_error_o ( /* TODO: left pending */ ), + .ecc_multile_error_o ( /* TODO: left pending */ ), + .tcdm_slave ( s_tcdm_bus_sram ) //PMU ?? ); /* AXI interconnect infrastructure (slices, size conversion) */ diff --git a/rtl/tcdm_banks_wrap.sv b/rtl/tcdm_banks_wrap.sv index 0b856a42..84e48395 100644 --- a/rtl/tcdm_banks_wrap.sv +++ b/rtl/tcdm_banks_wrap.sv @@ -17,38 +17,89 @@ */ module tcdm_banks_wrap #( - parameter BankSize = 256, //- -> OVERRIDE - parameter NbBanks = 1, // --> OVERRIDE - parameter DataWidth = 32, - parameter AddrWidth = 32, - parameter BeWidth = DataWidth/8, - parameter IdWidth = 1 + parameter int unsigned BankSize = 256, //- -> OVERRIDE + parameter int unsigned NbBanks = 1, // --> OVERRIDE + parameter int unsigned DataWidth = 32, + parameter int unsigned AddrWidth = 32, + parameter int unsigned BeWidth = DataWidth/8, + parameter int unsigned IdWidth = 1, + parameter bit EnableEcc = 1, + parameter bit EccInterco = 0 ) ( - input logic clk_i, - input logic rst_ni, - input logic test_mode_i, - + input logic clk_i, + input logic rst_ni, + input logic test_mode_i, + // Scrubber + input logic scrub_trigger_i, + output logic scrub_fix_o, + output logic scrub_uncorrectable_o, + // ECC + output logic ecc_single_error_o, + output logic ecc_multile_error_o, hci_mem_intf.slave tcdm_slave[NbBanks-1:0] ); + +logic [NbBanks-1:0] ecc_single_error, ecc_multiple_error, + scrub_fix, scrub_uncorrectable; + +assign ecc_single_error_o = |ecc_single_error; +assign ecc_multiple_error_o = |ecc_multiple_error; +assign scrub_fix_o = |scrub_fix; +assign scrub_uncorrectable_o = |scrub_uncorrectable; - for(genvar i=0; i Don't know if this is needed, but OBI protocol requires it - logic [IdWidth-1:0] resp_id_d, resp_id_q; - assign resp_id_d = tcdm_slave[i].id; - assign tcdm_slave[i].r_id = resp_id_q; + // r_id is same as request id -> Don't know if this is needed, but OBI protocol requires it + logic [IdWidth-1:0] resp_id_d, resp_id_q; + assign resp_id_d = tcdm_slave[i].id; + assign tcdm_slave[i].r_id = resp_id_q; - always_ff @(posedge clk_i or negedge rst_ni) begin : proc_resp_id - if(~rst_ni) begin - resp_id_q <= '0; - end else begin - resp_id_q <= resp_id_d; - end + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_resp_id + if(~rst_ni) begin + resp_id_q <= '0; + end else begin + resp_id_q <= resp_id_d; end + end - assign tcdm_slave[i].gnt = 1'b1; - + if (EnableEcc) begin: gen_ecc_banks + if (EccInterco) begin: gen_ecc_banks_and_connection + /* TODO: blank for the moment */ + end else begin: gen_ecc_banks_only + ecc_sram_wrap #( + .BankSize ( BankSize ), + .InputECC ( EccInterco ), + .UnprotectedWidth ( 32 ), + .ProtectedWidth ( 39 ) + ) i_ecc_bank ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_enable_i ( test_mode_i ), + // Scrubber + .scrub_trigger_i ( scrub_trigger_i ), + .scrubber_fix_o ( scrub_fix[i] ), + .scrub_uncorrectable_o ( scrub_uncorrectable[i] ), + // TCDM interface + .tcdm_wdata_i ( tcdm_slave[i].data ), + .tcdm_add_i ( tcdm_slave[i].add ), + .tcdm_req_i ( tcdm_slave[i].req ), + .tcdm_wen_i ( tcdm_slave[i].wen ), + .tcdm_be_i ( tcdm_slave[i].be ), + .tcdm_rdata_o ( tcdm_slave[i].r_data ), + .tcdm_gnt_o ( tcdm_slave[i].gnt ), + // ECC + .single_error_o ( ecc_single_error[i] ), + .multi_error_o ( ecc_multiple_error[i] ), + .test_write_mask_ni ( '0 ) // TODO: needed? + ); + end + end else begin: gen_standard_banks + assign tcdm_slave[i].gnt = 1'b1; + assign ecc_single_error = 1'b0; + assign ecc_multiple_error = 1'b0; + assign scrub_fix = 1'b0; + assign scrub_uncorrectable = 1'b0; tc_sram #( .NumWords (BankSize ), // Number of Words in data array @@ -63,17 +114,15 @@ module tcdm_banks_wrap #( ) i_bank ( .clk_i (clk_i ), // Clock .rst_ni (rst_ni ), // Asynchronous reset active low - .req_i (tcdm_slave[i].req ), // request .we_i (~tcdm_slave[i].wen ), // write enable .addr_i (tcdm_slave[i].add[$clog2(BankSize)+2-1:2]), // request address .wdata_i(tcdm_slave[i].data ), // write data .be_i (tcdm_slave[i].be ), // write byte enable - .rdata_o(tcdm_slave[i].r_data ) // read data ); - - end -endmodule +end + +endmodule: tcdm_banks_wrap From ac0d053ba8fefc42351b887ef5f0189fe2a8d917 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 28 Jan 2024 11:24:36 +0100 Subject: [PATCH 090/207] Bump redundancy_cells for rebase. --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index f86b28ba..6329c92f 100644 --- a/Bender.lock +++ b/Bender.lock @@ -196,7 +196,7 @@ packages: - hwpe-stream - tech_cells_generic redundancy_cells: - revision: 32023555679cfdb8a0a073ad4c17fc3a5d1ddea5 + revision: 651441e4a6459f84f3dde4242cf34961925a2142 version: null source: Git: https://github.com/pulp-platform/redundancy_cells.git diff --git a/Bender.yml b/Bender.yml index 8b2df85e..ed720f84 100644 --- a/Bender.yml +++ b/Bender.yml @@ -33,7 +33,7 @@ dependencies: hci: { git: "https://github.com/pulp-platform/hci.git", rev: 3cb3d99b2cebfeed55cb6ab9d98fce7b99e97cb9 } # branch: test_mode_fix register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } - redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 32023555679cfdb8a0a073ad4c17fc3a5d1ddea5 } # branch: yt/rapidrecovery + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 651441e4a6459f84f3dde4242cf34961925a2142 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 532f9514ad5c7ee21dde9e3a84ae99d2a5760610 } # branch: astral export_include_dirs: From 2f07f0bb50096c56650f16c62733d859b68fc6bf Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 7 Feb 2024 22:44:00 +0100 Subject: [PATCH 091/207] Remove unneeded comments. --- packages/pulp_cluster_package.sv | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index eb06fae0..6700b5f7 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -35,19 +35,6 @@ package pulp_cluster_package; parameter SPER_HMR_UNIT_ID = 8; // 0x2000 - 0x2400 parameter SPER_EXT_ID = 9; // 0x2400 - 0x2800 parameter SPER_ERROR_ID = 10; // 0x2800 - 0x2C00 - - // if set to 1, then instantiate APU in the cluster - // parameter APU_CLUSTER = 0; - - // // if set to 1, the 0x0000_0000 to 0x0040_0000 is the alias of the current cluster address space (eg cluster 0 is from 0x1000_0000 to 0x1040_0000) - // parameter CLUSTER_ALIAS = 1; - - // // if set to 1, the DEMUX peripherals (EU, MCHAN) are placed right before the test and set region. - // // This will steal 16KB from the 1MB TCDM reegion. - // // EU is mapped from 0x10100000 - 0x400 - // // MCHAN regs are mapped from 0x10100000 - 0x800 - // // remember to change the defines in the pulp.h as well to be coherent with this approach - // parameter DEM_PER_BEFORE_TCDM_TS = 0; typedef struct packed { logic gnt; From 0827b51c95c55e2f54fd2cc46e118c0054d4d782 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 8 Feb 2024 13:42:03 +0100 Subject: [PATCH 092/207] Restore shared FPU cluster. --- rtl/pulp_cluster.sv | 113 ++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 103 insertions(+), 10 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index c0637447..1edd4be7 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -424,6 +424,21 @@ hci_core_intf #( // cores -> event unit ctrl XBAR_PERIPH_BUS s_core_euctrl_bus[NB_CORES-1:0](); +// apu-interconnect +// handshake signals +logic [NB_CORES-1:0] s_apu_master_req; +logic [NB_CORES-1:0] s_apu_master_gnt; +// request channel +logic [NB_CORES-1:0][APU_NARGS_CPU-1:0][31:0] s_apu_master_operands; +logic [NB_CORES-1:0][APU_WOP_CPU-1:0] s_apu_master_op; +logic [NB_CORES-1:0][WAPUTYPE-1:0] s_apu_master_type; +logic [NB_CORES-1:0][APU_NDSFLAGS_CPU-1:0] s_apu_master_flags; +// response channel +logic [NB_CORES-1:0] s_apu_master_rready; +logic [NB_CORES-1:0] s_apu_master_rvalid; +logic [NB_CORES-1:0][31:0] s_apu_master_rdata; +logic [NB_CORES-1:0][APU_NUSFLAGS_CPU-1:0] s_apu_master_rflags; + //----------------------------------------------------------------------// // Interfaces between ICache - L0 - Icache_Interco and Icache_ctrl_unit // // // @@ -941,16 +956,16 @@ generate .pc_backup_o ( backup_bus[i].pc_backup ), .csr_backup_o ( backup_bus[i].csr_backup ), //apu interface - .apu_master_req_o ( ), - .apu_master_gnt_i ( '0 ), - .apu_master_type_o ( ), - .apu_master_operands_o ( ), - .apu_master_op_o ( ), - .apu_master_flags_o ( ), - .apu_master_valid_i ( '0 ), - .apu_master_ready_o ( ), - .apu_master_result_i ( '0 ), - .apu_master_flags_i ( '0 ) + .apu_master_req_o ( s_apu_master_req [i] ), + .apu_master_gnt_i ( s_apu_master_gnt [i] ), + .apu_master_type_o ( s_apu_master_type [i] ), + .apu_master_operands_o ( s_apu_master_operands[i] ), + .apu_master_op_o ( s_apu_master_op [i] ), + .apu_master_flags_o ( s_apu_master_flags [i] ), + .apu_master_valid_i ( s_apu_master_rvalid [i] ), + .apu_master_ready_o ( s_apu_master_rready [i] ), + .apu_master_result_i ( s_apu_master_rdata [i] ), + .apu_master_flags_i ( s_apu_master_rflags [i] ) ); assign dbg_core_halted[i] = core2hmr[i].debug_halted; @@ -1098,6 +1113,84 @@ hmr_unit #( .core_bus_outputs_i ( '0 ) ); +//**************************************************** +//**** Shared FPU cluster - Shared execution units *** +//**************************************************** +// request channel +logic [NB_CORES-1:0][2:0][31:0] s_apu__operands; +logic [NB_CORES-1:0][5:0] s_apu__op; +logic [NB_CORES-1:0][2:0] s_apu__type; +logic [NB_CORES-1:0][14:0] s_apu__flags; +// response channel +logic [NB_CORES-1:0][4:0] s_apu__rflags; + +genvar k; +for(k=0;k Date: Thu, 8 Feb 2024 13:53:25 +0100 Subject: [PATCH 093/207] Add daft configuration. --- packages/pulp_cluster_package.sv | 116 +++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 6700b5f7..39b67009 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -17,6 +17,122 @@ package pulp_cluster_package; import rapid_recovery_pkg::*; + + typedef bit [ 7:0] byte_t; + typedef bit [31:0] word_t; + typedef bit [63:0] doub_t; + + // Core type + typedef enum logic[1:0] { + CV32, + RISCY, + IBEX + } core_type_e; + + // PULP cluster configuration + typedef struct packed { + // Type of core in the cluster + core_type_e CoreType; + // Number of cores in the cluster + byte_t NumCores; + // Number of DMA TCDM plugs + byte_t DmaNumPlugs; + // Number of DMA outstanding transactions + byte_t DmaNumOutstandingBursts; + // DMA burst length in bits + word_t DmaBurstLength; + // Number of masters in crossbar peripherals + byte_t NumMstPeriphs; + // Number of slaves in crossbar peripherals + byte_t NumSlvPeriphs; + // Enable cluster aliasing + bit ClusterAlias; + // Base of the cluster alias + byte_t ClusterAliasBase; + // Number of internal synchronization stages + byte_bt NumSyncStages; + // Enable HCI + bit UseHci; + // Size of the TCDM in bytes (power of two) + word_t TcdmSize; + // Number of TCDM banks (power of two) + byte_t TcdmNumBank, + // Enable HWPEs + bit HwpePresent; + // Number of memory ports available for HWPEs + byte_t HwpeNumPorts; + // I$ associativity + byte_t iCacheSetAssociative; + // Number if I$ banks + byte_t iCacheNumBanks; + // Number of I$ lines + byte_t iCacheNumLines; + // I$ size + word_t iCacheSize; + // Instruction read data width + byte_t InstructionReadDataWidth; + // Enable L0 buffer + bit EnableL0; + // Enable multicast + bit EnableMultiCast; + // Enable shared I$ + bit EnableSharediCache; + // Enable reduced tag + bit EnableReducedTag; + // Enable direct map + bit EnableDirectMap; + // L2 size + word_t L2Size; + // Debug module base address + doub_t DmBaseAddr; + // BootROM base address + doub_t BootRomBaseAddr; + // Cores boot address + doub_t BootAddr; + // Enable FPU + bit EnableFpu; + // Enable FP division/sqrt + bit EnableFpDivSqrt; + // Number of FPUs + bite_t NumFpu; + // Enable shared FPUs + bit EnableSharedFpu; + // Enable shared FP division/sqrt + bit EnableSharedFpDivSqrt; + byte_t FpuNumInput; + byte_t Fpu + // Number of AXI crossbar manager ports + byte_t NumAxiIn; + // AXI ID width of subordinate ports + byte_t NumAxiOut; + // Number of AXI crossbar subordinate ports + byte_t AxiIdInWidth; + // AXI ID width of subordinate ports + byte_t AxiIdOutWidth; + // AXI address width + byte_t AxiAddrWidth; + // AXI data width from external to cluster + byte_t AxiDatInWidth; + // AXI data width from cluster to external + byte_t AxiDatOutWidth;; + // AXI user width + byte_t AxiUserWidth; + // Log depth of AXI CDC FIFOs + byte_t AxiCdcLogDepth; + // Sinchronization stages of AXI CDC FIFOs + byte_t AxiCdcSyncStages; + // Cluster base address + doub_t ClusterBaseAddr; + // Cluster peripherals offset + doub_t ClusterPeriphOffs; + // Cluster base external offset + doub_t ClusterExternalOffs; + // Address remap for virtualization + bit EnableRemapAddress; + // LSB used as routing BIT in periph interco + byte_t PeRoutingLsb; + } pulp_cluster_cfg_t; + parameter NB_SPERIPH_PLUGS_EU = 2; // number of master and slave cluster periphs From a2b385d08049bb4ecfdf1c4925b64097d6d8472f Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 9 Feb 2024 16:39:25 +0100 Subject: [PATCH 094/207] Restore 12 cores for testing. --- include/pulp_soc_defines.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/pulp_soc_defines.sv b/include/pulp_soc_defines.sv index 5307196e..54307677 100644 --- a/include/pulp_soc_defines.sv +++ b/include/pulp_soc_defines.sv @@ -47,7 +47,7 @@ //PARAMETRES `define NB_CLUSTERS 1 -`define NB_CORES 8 +`define NB_CORES 12 `define NB_DMAS 4 `define NB_MPERIPHS 1 `define NB_SPERIPHS 10 From 2d06d13f608a7aec393b5c84a89bf078b0b65da2 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 9 Feb 2024 16:45:35 +0100 Subject: [PATCH 095/207] Add top-level configuration to PULP cluster. --- Makefile | 1 + packages/pulp_cluster_package.sv | 116 ++-- rtl/pulp_cluster.sv | 993 +++++++++++++++---------------- tb/pulp_cluster_tb.sv | 90 +-- 4 files changed, 607 insertions(+), 593 deletions(-) diff --git a/Makefile b/Makefile index 039e1c7e..b291539c 100644 --- a/Makefile +++ b/Makefile @@ -31,6 +31,7 @@ bender_defs += -D ICAHE_USE_FF bender_defs += -D NO_FPU bender_defs += -D TRACE_EXECUTION bender_defs += -D CLUSTER_ALIAS +bender_defs += -D USE_PULP_PARAMETERS bender_targs += -t rtl bender_targs += -t test diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 39b67009..6ebd33e8 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -19,6 +19,7 @@ package pulp_cluster_package; import rapid_recovery_pkg::*; typedef bit [ 7:0] byte_t; + typedef bit [12:0] alias_t; typedef bit [31:0] word_t; typedef bit [63:0] doub_t; @@ -48,39 +49,33 @@ package pulp_cluster_package; // Enable cluster aliasing bit ClusterAlias; // Base of the cluster alias - byte_t ClusterAliasBase; + alias_t ClusterAliasBase; // Number of internal synchronization stages - byte_bt NumSyncStages; + byte_t NumSyncStages; // Enable HCI bit UseHci; // Size of the TCDM in bytes (power of two) word_t TcdmSize; // Number of TCDM banks (power of two) - byte_t TcdmNumBank, + byte_t TcdmNumBank; // Enable HWPEs bit HwpePresent; // Number of memory ports available for HWPEs byte_t HwpeNumPorts; - // I$ associativity - byte_t iCacheSetAssociative; // Number if I$ banks byte_t iCacheNumBanks; // Number of I$ lines byte_t iCacheNumLines; - // I$ size - word_t iCacheSize; - // Instruction read data width - byte_t InstructionReadDataWidth; - // Enable L0 buffer - bit EnableL0; - // Enable multicast - bit EnableMultiCast; - // Enable shared I$ - bit EnableSharediCache; + // Number of I$ ways + byte_t iCacheNumWays; // default is 4 + // Shared I$ size in bytes + word_t iCacheSharedSize; // default is 4096 + // Private I$ size in bytes + word_t iCachePrivateSize; // default is 521 + // Private I$ data width + byte_t iCachePrivateDataWidth; // Enable reduced tag bit EnableReducedTag; - // Enable direct map - bit EnableDirectMap; // L2 size word_t L2Size; // Debug module base address @@ -89,38 +84,38 @@ package pulp_cluster_package; doub_t BootRomBaseAddr; // Cores boot address doub_t BootAddr; - // Enable FPU - bit EnableFpu; - // Enable FP division/sqrt - bit EnableFpDivSqrt; - // Number of FPUs - bite_t NumFpu; + // Enable private FPU + bit EnablePrivateFpu; + // Enable private FP division/sqrt + bit EnablePrivateFpDivSqrt; // Enable shared FPUs bit EnableSharedFpu; // Enable shared FP division/sqrt bit EnableSharedFpDivSqrt; - byte_t FpuNumInput; - byte_t Fpu - // Number of AXI crossbar manager ports + // Number of shared FPUs + byte_t NumSharedFpu; + // Number of AXI crossbar subordinate ports byte_t NumAxiIn; - // AXI ID width of subordinate ports + // Number of AXI crossbar manager ports byte_t NumAxiOut; - // Number of AXI crossbar subordinate ports + // AXI ID width of crossbar subordinate ports byte_t AxiIdInWidth; - // AXI ID width of subordinate ports + // AXI ID width of crossbar manager ports byte_t AxiIdOutWidth; // AXI address width byte_t AxiAddrWidth; // AXI data width from external to cluster - byte_t AxiDatInWidth; + byte_t AxiDataInWidth; // AXI data width from cluster to external - byte_t AxiDatOutWidth;; + byte_t AxiDataOutWidth; // AXI user width byte_t AxiUserWidth; // Log depth of AXI CDC FIFOs - byte_t AxiCdcLogDepth; + byte_t AxiCdcLogDepth; // old LOG_DEPTH // Sinchronization stages of AXI CDC FIFOs byte_t AxiCdcSyncStages; + // Input synchronization stages + byte_t SyncStages; // Cluster base address doub_t ClusterBaseAddr; // Cluster peripherals offset @@ -129,8 +124,6 @@ package pulp_cluster_package; doub_t ClusterExternalOffs; // Address remap for virtualization bit EnableRemapAddress; - // LSB used as routing BIT in periph interco - byte_t PeRoutingLsb; } pulp_cluster_cfg_t; parameter NB_SPERIPH_PLUGS_EU = 2; @@ -152,6 +145,61 @@ package pulp_cluster_package; parameter SPER_EXT_ID = 9; // 0x2400 - 0x2800 parameter SPER_ERROR_ID = 10; // 0x2800 - 0x2C00 + // The following parameters refer to the cluster AXI crossbar + localparam byte_t NumAxiSubordinatePorts = 4; + localparam byte_t NumAxiManagerPorts = 3; + localparam byte_t AxiSubordinateIdwidth = 4; + localparam byte_t AxiManagerIdwidth = AxiSubordinateIdwidth + $clog2(NumAxiSubordinatePorts); + + localparam pulp_cluster_cfg_t PulpClusterDefaultCfg = '{ + CoreType: CV32, + NumCores: 8, + DmaNumPlugs: 4, + DmaNumOutstandingBursts: 8, + DmaBurstLength: 256, + NumMstPeriphs: NB_MPERIPHS, + NumSlvPeriphs: NB_SPERIPHS, + ClusterAlias: 1, + ClusterAliasBase: 'h0, + NumSyncStages: 3, + UseHci: 1, + TcdmSize: 64*1024, + TcdmNumBank: 16, + HwpePresent: 0, + HwpeNumPorts: 0, + iCacheNumBanks: 2, + iCacheNumLines: 1, + iCacheNumWays: 4, + iCacheSharedSize: 4*1024, + iCachePrivateSize: 512, + iCachePrivateDataWidth: 32, + EnableReducedTag: 1, + L2Size: 1000*1024, + DmBaseAddr: 'h1A110000, + BootRomBaseAddr: 'h1A000000, + BootAddr: 'h1C000000, + EnablePrivateFpu: 1, + EnablePrivateFpDivSqrt: 0, + EnableSharedFpu: 0, + EnableSharedFpDivSqrt: 0, + NumSharedFpu: 0, + NumAxiIn: NumAxiSubordinatePorts, + NumAxiOut: NumAxiManagerPorts, + AxiIdInWidth: AxiSubordinateIdwidth, + AxiIdOutWidth:AxiManagerIdwidth, + AxiAddrWidth: 32, + AxiDataInWidth: 32, + AxiDataOutWidth: 32, + AxiUserWidth: 10, + AxiCdcLogDepth: 3, + AxiCdcSyncStages: 3, + ClusterBaseAddr: 'h10000000, + ClusterPeriphOffs: 'h00200000, + ClusterExternalOffs: 'h00400000, + EnableRemapAddress: 0, + default: '0 + }; + typedef struct packed { logic gnt; logic [31:0] r_data; diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 1edd4be7..d40aae16 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -29,124 +29,73 @@ module pulp_cluster import rapid_recovery_pkg::*; import fpnew_pkg::*; #( - // cluster parameters - parameter CORE_TYPE_CL = 1, // 0 for CV32, 1 for RI5CY, 2 for IBEX RV32IMC - parameter NB_CORES = 8, - parameter NB_HWPE_PORTS = 9, - // number of DMA TCDM plugs, NOT number of DMA slave peripherals! - // Everything will go to hell if you change this! - parameter NB_DMAS = 4, - parameter NB_MPERIPHS = 1, - parameter NB_SPERIPHS = 10, - - parameter CLUSTER_ALIAS = 1, // to be checked, we do not want it - parameter CLUSTER_ALIAS_BASE = 12'h000, // to be checked, we do not want it - - parameter int unsigned SynchStages = 3, - - parameter TCDM_SIZE = 256*1024, // [B], must be 2**N - parameter NB_TCDM_BANKS = 16, // must be 2**N - parameter TCDM_BANK_SIZE = TCDM_SIZE/NB_TCDM_BANKS, // [B] - parameter TCDM_NUM_ROWS = TCDM_BANK_SIZE/4, // [words] - parameter HWPE_PRESENT = 1, // set to 1 if HW Processing Engines are present in the cluster - parameter USE_HETEROGENEOUS_INTERCONNECT = 1, // set to 1 to connect HWPEs via heterogeneous interconnect; to 0 for larger LIC - - // I$ parameters - parameter SET_ASSOCIATIVE = 4, - parameter NB_CACHE_BANKS = 2, - parameter CACHE_LINE = 1, - parameter CACHE_SIZE = 4*1024, - parameter ICACHE_DATA_WIDTH = 128, - parameter L0_BUFFER_FEATURE = "DISABLED", - parameter MULTICAST_FEATURE = "DISABLED", - parameter SHARED_ICACHE = "ENABLED", - parameter DIRECT_MAPPED_FEATURE = "DISABLED", - parameter L2_SIZE = 2**20, - parameter USE_REDUCED_TAG = "TRUE", - - // core parameters - parameter DEBUG_START_ADDR = 32'h60203000, - parameter ROM_BOOT_ADDR = 32'h78000000, - parameter BOOT_ADDR = 32'h78000000, - parameter INSTR_RDATA_WIDTH = 32, - - parameter bit CLUST_FPU = 1, - parameter int unsigned NumFpus = NB_CORES, - parameter CLUST_FP_DIVSQRT = 0, - parameter CLUST_SHARED_FP = 0, - parameter CLUST_SHARED_FP_DIVSQRT = 0, - - // AXI parameters - parameter int unsigned NumAxiMst = 3 , - parameter int unsigned NumAxiSlv = 4 , - parameter AXI_ADDR_WIDTH = 48, - parameter AXI_DATA_C2S_WIDTH = 64, - parameter AXI_DATA_S2C_WIDTH = 64, - parameter AXI_USER_WIDTH = 10, - parameter AXI_ID_IN_WIDTH = 4, - parameter AXI_ID_OUT_WIDTH = AXI_ID_IN_WIDTH + $clog2(NumAxiSlv), - parameter AXI_STRB_C2S_WIDTH = AXI_DATA_C2S_WIDTH/8, - parameter AXI_STRB_S2C_WIDTH = AXI_DATA_S2C_WIDTH/8, - parameter DC_SLICE_BUFFER_WIDTH = 8, - parameter LOG_DEPTH = 3, - parameter int unsigned CdcSynchStages = 3, - parameter logic [AXI_ADDR_WIDTH-1:0] BaseAddr = 'h50000000, - parameter logic [AXI_ADDR_WIDTH-1:0] ClusterPeripheralsOffs = 'h00200000, - parameter logic [AXI_ADDR_WIDTH-1:0] ClusterExternalOffs = 'h00400000, - // CLUSTER TO SOC CDC AXI PARAMETER - localparam S2C_AW_WIDTH = axi_pkg::aw_width(AXI_ADDR_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), - localparam S2C_W_WIDTH = axi_pkg::w_width(AXI_DATA_S2C_WIDTH,AXI_USER_WIDTH), - localparam S2C_R_WIDTH = axi_pkg::r_width(AXI_DATA_S2C_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), - localparam S2C_B_WIDTH = axi_pkg::b_width(AXI_ID_IN_WIDTH,AXI_USER_WIDTH), - localparam S2C_AR_WIDTH = axi_pkg::ar_width(AXI_ADDR_WIDTH,AXI_ID_IN_WIDTH,AXI_USER_WIDTH), - // CLUSTER TO SOC CDC AXI PARAMETERS - localparam C2S_AW_WIDTH = axi_pkg::aw_width(AXI_ADDR_WIDTH,AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), - localparam C2S_W_WIDTH = axi_pkg::w_width(AXI_DATA_C2S_WIDTH,AXI_USER_WIDTH), - localparam C2S_R_WIDTH = axi_pkg::r_width(AXI_DATA_C2S_WIDTH,AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), - localparam C2S_B_WIDTH = axi_pkg::b_width(AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), - localparam C2S_AR_WIDTH = axi_pkg::ar_width(AXI_ADDR_WIDTH,AXI_ID_OUT_WIDTH,AXI_USER_WIDTH), - - localparam ASYNC_C2S_AW_DATA_WIDTH = (2**LOG_DEPTH)*C2S_AW_WIDTH, - localparam ASYNC_C2S_W_DATA_WIDTH = (2**LOG_DEPTH)*C2S_W_WIDTH, - localparam ASYNC_C2S_B_DATA_WIDTH = (2**LOG_DEPTH)*C2S_B_WIDTH, - localparam ASYNC_C2S_AR_DATA_WIDTH = (2**LOG_DEPTH)*C2S_AR_WIDTH, - localparam ASYNC_C2S_R_DATA_WIDTH = (2**LOG_DEPTH)*C2S_R_WIDTH, - - localparam ASYNC_S2C_AW_DATA_WIDTH = (2**LOG_DEPTH)*S2C_AW_WIDTH, - localparam ASYNC_S2C_W_DATA_WIDTH = (2**LOG_DEPTH)*S2C_W_WIDTH, - localparam ASYNC_S2C_B_DATA_WIDTH = (2**LOG_DEPTH)*S2C_B_WIDTH, - localparam ASYNC_S2C_AR_DATA_WIDTH = (2**LOG_DEPTH)*S2C_AR_WIDTH, - localparam ASYNC_S2C_R_DATA_WIDTH = (2**LOG_DEPTH)*S2C_R_WIDTH, - - // TCDM and log interconnect parameters - parameter DATA_WIDTH = 32, - parameter ADDR_WIDTH = 32, - parameter BE_WIDTH = DATA_WIDTH/8, - parameter TEST_SET_BIT = 20, // bit used to indicate a test-and-set operation during a load in TCDM - parameter ADDR_MEM_WIDTH = $clog2(TCDM_BANK_SIZE/4), // WORD address width per TCDM bank (the word width is 32 bits) - - // DMA parameters - parameter TCDM_ADD_WIDTH = ADDR_MEM_WIDTH + $clog2(NB_TCDM_BANKS) + 2, // BYTE address width TCDM - parameter NB_OUTSND_BURSTS = 8, - parameter MCHAN_BURST_LENGTH = 256, - - - // peripheral and periph interconnect parameters - parameter LOG_CLUSTER = 5, // unused - parameter PE_ROUTING_LSB = 10, // LSB used as routing BIT in periph interco - // parameter PE_ROUTING_MSB = 13, // MSB used as routing BIT in periph interco - parameter EVNT_WIDTH = 8, // size of the event bus - parameter REMAP_ADDRESS = 0, // for cluster virtualization - - localparam ASYNC_EVENT_DATA_WIDTH = (2**LOG_DEPTH)*EVNT_WIDTH, - // FPU PARAMETERS - parameter APU_NARGS_CPU = 3, - parameter APU_WOP_CPU = 6, - parameter WAPUTYPE = 3, - parameter APU_NDSFLAGS_CPU = 15, - parameter APU_NUSFLAGS_CPU = 5 -) -( + parameter pulp_cluster_package::pulp_cluster_cfg_t Cfg = pulp_cluster_package::PulpClusterDefaultCfg, + localparam int unsigned TcdmBankSize = Cfg.TcdmSize/Cfg.TcdmNumBank, + localparam int unsigned TcdmNumRows = TcdmBankSize/4, + // CDC AXI parameters (external to cluster) + localparam int unsigned AwInWidth = axi_pkg::aw_width(Cfg.AxiAddrWidth, + Cfg.AxiIdInWidth, + Cfg.AxiUserWidth), + localparam int unsigned WInWidth = axi_pkg::w_width(Cfg.AxiDataInWidth, + Cfg.AxiUserWidth), + localparam int unsigned BInWidth = axi_pkg::b_width(Cfg.AxiIdInWidth, + Cfg.AxiUserWidth), + localparam int unsigned ArInWidth = axi_pkg::ar_width(Cfg.AxiAddrWidth, + Cfg.AxiIdInWidth, + Cfg.AxiUserWidth), + localparam int unsigned RInWidth = axi_pkg::r_width(Cfg.AxiDataInWidth, + Cfg.AxiIdInWidth, + Cfg.AxiUserWidth), + localparam int unsigned AsyncInAwDatawidth = (2**Cfg.AxiCdcLogDepth)*AwInWidth, + localparam int unsigned AsyncInWDatawidth = (2**Cfg.AxiCdcLogDepth)*WInWidth, + localparam int unsigned AsyncInBDataWidth = (2**Cfg.AxiCdcLogDepth)*BInWidth, + localparam int unsigned AsyncInArDatawidth = (2**Cfg.AxiCdcLogDepth)*ArInWidth, + localparam int unsigned AsyncInRDataWidth = (2**Cfg.AxiCdcLogDepth)*RInWidth, + // CDC AXI parameters (cluster to external) + localparam int unsigned AwOutWidth = axi_pkg::aw_width(Cfg.AxiAddrWidth, + Cfg.AxiIdOutWidth, + Cfg.AxiUserWidth), + localparam int unsigned WOutWidth = axi_pkg::w_width(Cfg.AxiDataOutWidth, + Cfg.AxiUserWidth), + localparam int unsigned BOutWidth = axi_pkg::b_width(Cfg.AxiIdOutWidth, + Cfg.AxiUserWidth), + localparam int unsigned ArOutWidth = axi_pkg::ar_width(Cfg.AxiAddrWidth, + Cfg.AxiIdOutWidth, + Cfg.AxiUserWidth), + localparam int unsigned ROutWidth = axi_pkg::r_width(Cfg.AxiDataOutWidth, + Cfg.AxiIdOutWidth, + Cfg.AxiUserWidth), + localparam int unsigned AsyncOutAwDataWidth = (2**Cfg.AxiCdcLogDepth)*AwOutWidth, + localparam int unsigned AsyncOutWDataWidth = (2**Cfg.AxiCdcLogDepth)*WOutWidth, + localparam int unsigned AsyncOutBDataWidth = (2**Cfg.AxiCdcLogDepth)*BOutWidth, + localparam int unsigned AsyncOutArDataWidth = (2**Cfg.AxiCdcLogDepth)*ArOutWidth, + localparam int unsigned AsyncOutRDataWidth = (2**Cfg.AxiCdcLogDepth)*ROutWidth, + // Internal bus parameters + // TCDM data bus width (never changes) + localparam int unsigned DataWidth = 32, + // TCDM address bus width (never changes) + localparam int unsigned AddrWidth = 32, + // TCDM bank enable width (never changes) + localparam int unsigned BeWidth = DataWidth/8, + // Indicates a test-and-set operation during a load in TCDM + localparam int unsigned TestSetBit = 20, + // Word address width per TCDM bank + localparam int unsigned AddrMemWidth= $clog2(TcdmNumRows), + // Byte address width of TCDM + localparam int unsigned TcdmAddrWidth = AddrMemWidth + $clog2(Cfg.TcdmNumBank) + 2, + // Synchronous event bus size + localparam int unsigned EventWidth = 8, + // Asynchronous event bus size + localparam int unsigned AsyncEventDataWidth = (2**Cfg.AxiCdcLogDepth)*EventWidth, + // LSB used as routing BIT in periph interco + localparam int unsigned PeRoutingLsb = 10, + // FPU bus parameters + localparam int unsigned FpuNumArgs = 3, + localparam int unsigned FpuOpCodeWidth = 6, + localparam int unsigned FpuTypeWidth = 3, + localparam int unsigned FpuInFlagsWidth = 15, + localparam int unsigned FpuOutFlagsWidth = 5 +)( input logic clk_i, input logic rst_ni, input logic ref_clk_i, @@ -180,73 +129,72 @@ module pulp_cluster input logic pf_evt_ack_i, output logic pf_evt_valid_o, - input logic [NB_CORES-1:0] dbg_irq_valid_i, + input logic [Cfg.NumCores-1:0] dbg_irq_valid_i, input logic mbox_irq_i, - input logic [LOG_DEPTH:0] async_cluster_events_wptr_i, - output logic [LOG_DEPTH:0] async_cluster_events_rptr_o, - input logic [ASYNC_EVENT_DATA_WIDTH-1:0] async_cluster_events_data_i, + input logic [Cfg.AxiCdcLogDepth:0] async_cluster_events_wptr_i, + output logic [Cfg.AxiCdcLogDepth:0] async_cluster_events_rptr_o, + input logic [AsyncEventDataWidth-1:0] async_cluster_events_data_i, // AXI4 SLAVE //*************************************** // WRITE ADDRESS CHANNEL - input logic [LOG_DEPTH:0] async_data_slave_aw_wptr_i, - input logic [ASYNC_S2C_AW_DATA_WIDTH-1:0] async_data_slave_aw_data_i, - output logic [LOG_DEPTH:0] async_data_slave_aw_rptr_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_slave_aw_wptr_i, + input logic [AsyncInAwDatawidth-1:0] async_data_slave_aw_data_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_slave_aw_rptr_o, // READ ADDRESS CHANNEL - input logic [LOG_DEPTH:0] async_data_slave_ar_wptr_i, - input logic [ASYNC_S2C_AR_DATA_WIDTH-1:0] async_data_slave_ar_data_i, - output logic [LOG_DEPTH:0] async_data_slave_ar_rptr_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_slave_ar_wptr_i, + input logic [AsyncInArDatawidth-1:0] async_data_slave_ar_data_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_slave_ar_rptr_o, // WRITE DATA CHANNEL - input logic [LOG_DEPTH:0] async_data_slave_w_wptr_i, - input logic [ASYNC_S2C_W_DATA_WIDTH-1:0] async_data_slave_w_data_i, - output logic [LOG_DEPTH:0] async_data_slave_w_rptr_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_slave_w_wptr_i, + input logic [AsyncInWDatawidth-1:0] async_data_slave_w_data_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_slave_w_rptr_o, // READ DATA CHANNEL - output logic [LOG_DEPTH:0] async_data_slave_r_wptr_o, - output logic [ASYNC_S2C_R_DATA_WIDTH-1:0] async_data_slave_r_data_o, - input logic [LOG_DEPTH:0] async_data_slave_r_rptr_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_slave_r_wptr_o, + output logic [AsyncInRDataWidth-1:0] async_data_slave_r_data_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_slave_r_rptr_i, // WRITE RESPONSE CHANNEL - output logic [LOG_DEPTH:0] async_data_slave_b_wptr_o, - output logic [ASYNC_S2C_B_DATA_WIDTH-1:0] async_data_slave_b_data_o, - input logic [LOG_DEPTH:0] async_data_slave_b_rptr_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_slave_b_wptr_o, + output logic [AsyncInBDataWidth-1:0] async_data_slave_b_data_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_slave_b_rptr_i, // AXI4 MASTER //*************************************** // WRITE ADDRESS CHANNEL - output logic [LOG_DEPTH:0] async_data_master_aw_wptr_o, - output logic [ASYNC_C2S_AW_DATA_WIDTH-1:0] async_data_master_aw_data_o, - input logic [LOG_DEPTH:0] async_data_master_aw_rptr_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_master_aw_wptr_o, + output logic [AsyncOutAwDataWidth-1:0] async_data_master_aw_data_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_master_aw_rptr_i, // READ ADDRESS CHANNEL - output logic [LOG_DEPTH:0] async_data_master_ar_wptr_o, - output logic [ASYNC_C2S_AR_DATA_WIDTH-1:0] async_data_master_ar_data_o, - input logic [LOG_DEPTH:0] async_data_master_ar_rptr_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_master_ar_wptr_o, + output logic [AsyncOutArDataWidth-1:0] async_data_master_ar_data_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_master_ar_rptr_i, // WRITE DATA CHANNEL - output logic [LOG_DEPTH:0] async_data_master_w_wptr_o, - output logic [ASYNC_C2S_W_DATA_WIDTH-1:0] async_data_master_w_data_o, - input logic [LOG_DEPTH:0] async_data_master_w_rptr_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_master_w_wptr_o, + output logic [AsyncOutWDataWidth-1:0] async_data_master_w_data_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_master_w_rptr_i, // READ DATA CHANNEL - input logic [LOG_DEPTH:0] async_data_master_r_wptr_i, - input logic [ASYNC_C2S_R_DATA_WIDTH-1:0] async_data_master_r_data_i, - output logic [LOG_DEPTH:0] async_data_master_r_rptr_o, + input logic [Cfg.AxiCdcLogDepth:0] async_data_master_r_wptr_i, + input logic [AsyncOutRDataWidth-1:0] async_data_master_r_data_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_master_r_rptr_o, // WRITE RESPONSE CHANNEL - input logic [LOG_DEPTH:0] async_data_master_b_wptr_i, - input logic [ASYNC_C2S_B_DATA_WIDTH-1:0] async_data_master_b_data_i, - output logic [LOG_DEPTH:0] async_data_master_b_rptr_o - + input logic [Cfg.AxiCdcLogDepth:0] async_data_master_b_wptr_i, + input logic [AsyncOutBDataWidth-1:0] async_data_master_b_data_i, + output logic [Cfg.AxiCdcLogDepth:0] async_data_master_b_rptr_o ); //Ensure that the input AXI ID width is big enough to accomodate the accomodate the IDs of internal wiring -if (AXI_ID_IN_WIDTH < 1 + $clog2(NB_CACHE_BANKS)) - $error("AXI input ID width must be larger than 1+$clog2(NB_CACHE_BANKS) which is %d but was %d", 1 + $clog2(NB_CACHE_BANKS), AXI_ID_IN_WIDTH); +if (Cfg.AxiIdInWidth < 1 + $clog2(Cfg.iCacheNumBanks)) + $error("AXI input ID width must be larger than 1+$clog2(Cfg.iCacheNumBanks) which is %d but was %d", 1 + $clog2(Cfg.iCacheNumBanks), Cfg.AxiIdInWidth); localparam int unsigned NB_L1_CUTS = 16; localparam int unsigned RW_MARGIN_WIDTH = 4; @@ -260,15 +208,15 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; //***************** SIGNALS DECLARATION ****************** //******************************************************** -logic [NB_CORES-1:0] fetch_enable_reg_int; -logic [NB_CORES-1:0] fetch_en_int; -logic [NB_CORES-1:0][31:0] boot_addr; -logic [NB_CORES-1:0] dbg_core_halt; -logic [NB_CORES-1:0] dbg_core_resume; -logic [NB_CORES-1:0] dbg_core_halted; -logic [NB_CORES-1:0] dbg_core_havereset; -logic [NB_CORES-1:0] dbg_core_running; -logic [NB_CORES-1:0] s_dbg_irq; +logic [Cfg.NumCores-1:0] fetch_enable_reg_int; +logic [Cfg.NumCores-1:0] fetch_en_int; +logic [Cfg.NumCores-1:0][31:0] boot_addr; +logic [Cfg.NumCores-1:0] dbg_core_halt; +logic [Cfg.NumCores-1:0] dbg_core_resume; +logic [Cfg.NumCores-1:0] dbg_core_halted; +logic [Cfg.NumCores-1:0] dbg_core_havereset; +logic [Cfg.NumCores-1:0] dbg_core_running; +logic [Cfg.NumCores-1:0] s_dbg_irq; logic s_hwpe_en; logic fetch_en_synch; @@ -282,21 +230,21 @@ logic s_per2axi_busy; logic s_axi2per_busy; logic s_dmac_busy; logic s_cluster_cg_en; -logic [NB_CORES-1:0] s_dma_event; -logic [NB_CORES-1:0] s_dma_irq; -logic [NB_CORES-1:0][3:0] s_hwpe_remap_evt; -logic [NB_CORES-1:0][1:0] s_hwpe_evt; +logic [Cfg.NumCores-1:0] s_dma_event; +logic [Cfg.NumCores-1:0] s_dma_irq; +logic [Cfg.NumCores-1:0][3:0] s_hwpe_remap_evt; +logic [Cfg.NumCores-1:0][1:0] s_hwpe_evt; logic s_hwpe_busy; hci_package::hci_interconnect_ctrl_t s_hci_ctrl; -logic [NB_CORES-1:0] clk_core_en; +logic [Cfg.NumCores-1:0] clk_core_en; // CLK reset, and other control signals logic s_cluster_int_busy; logic s_fregfile_disable; -logic [NB_CORES-1:0] core_busy; +logic [Cfg.NumCores-1:0] core_busy; logic s_incoming_req; logic s_isolate_cluster; @@ -304,14 +252,14 @@ logic s_events_async; logic s_events_valid; logic s_events_ready; -logic [EVNT_WIDTH-1:0] s_events_data; +logic [EventWidth-1:0] s_events_data; // Signals Between CORE_ISLAND and INSTRUCTION CACHES -logic [NB_CORES-1:0] instr_req; -logic [NB_CORES-1:0][31:0] instr_addr; -logic [NB_CORES-1:0] instr_gnt; -logic [NB_CORES-1:0] instr_r_valid; -logic [NB_CORES-1:0][INSTR_RDATA_WIDTH-1:0] instr_r_rdata; +logic [Cfg.NumCores-1:0] instr_req; +logic [Cfg.NumCores-1:0][31:0] instr_addr; +logic [Cfg.NumCores-1:0] instr_gnt; +logic [Cfg.NumCores-1:0] instr_r_valid; +logic [Cfg.NumCores-1:0][Cfg.iCachePrivateDataWidth-1:0] instr_r_rdata; logic [1:0] s_TCDM_arb_policy; logic tcdm_sleep; @@ -321,12 +269,12 @@ logic tcdm_sleep; // logic s_dma_pe_irq; // logic s_pf_event; -logic[NB_CORES-1:0][4:0] irq_id; -logic[NB_CORES-1:0][4:0] irq_ack_id; -logic[NB_CORES-1:0] irq_req; -logic[NB_CORES-1:0] irq_ack; +logic[Cfg.NumCores-1:0][4:0] irq_id; +logic[Cfg.NumCores-1:0][4:0] irq_ack_id; +logic[Cfg.NumCores-1:0] irq_req; +logic[Cfg.NumCores-1:0] irq_ack; -logic [NB_CORES-1:0] s_core_dbg_irq; +logic [Cfg.NumCores-1:0] s_core_dbg_irq; logic [NB_L1_CUTS-1:0][RW_MARGIN_WIDTH-1:0] s_rw_margin_L1; @@ -336,9 +284,9 @@ logic s_dma_cl_irq; logic s_dma_fc_event; logic s_dma_fc_irq; -logic [NB_CORES-1:0] hmr_barrier_matched; -logic [NB_CORES-1:0] hmr_dmr_sw_resynch_req, hmr_tmr_sw_resynch_req; -logic [NB_CORES-1:0] hmr_dmr_sw_synch_req, hmr_tmr_sw_synch_req; +logic [Cfg.NumCores-1:0] hmr_barrier_matched; +logic [Cfg.NumCores-1:0] hmr_dmr_sw_resynch_req, hmr_tmr_sw_resynch_req; +logic [Cfg.NumCores-1:0] hmr_dmr_sw_synch_req, hmr_tmr_sw_synch_req; // FIXME: iDMA // logic s_dma_decompr_event; @@ -351,53 +299,53 @@ logic [NB_CORES-1:0] hmr_dmr_sw_synch_req, hmr_tmr_sw_synch_req; /* logarithmic and peripheral interconnect interfaces */ // ext -> log interconnect hci_core_intf #( - .DW ( DATA_WIDTH ), - .AW ( ADDR_WIDTH ), + .DW ( DataWidth ), + .AW ( AddrWidth ), .OW ( 1 ) -) s_hci_ext[NB_DMAS-1:0] ( +) s_hci_ext[Cfg.DmaNumPlugs-1:0] ( .clk ( clk_i ) ); // periph interconnect -> slave peripherals -XBAR_PERIPH_BUS s_xbar_speriph_bus[NB_SPERIPHS-1:0](); +XBAR_PERIPH_BUS s_xbar_speriph_bus[Cfg.NumSlvPeriphs-1:0](); // periph interconnect -> HWPE subsystem XBAR_PERIPH_BUS s_hwpe_cfg_bus(); // DMA -> log interconnect hci_core_intf #( - .DW ( DATA_WIDTH ), - .AW ( ADDR_WIDTH ), + .DW ( DataWidth ), + .AW ( AddrWidth ), .OW ( 1 ) -) s_hci_dma[NB_DMAS-1:0] ( +) s_hci_dma[Cfg.DmaNumPlugs-1:0] ( .clk ( clk_i ) ); -XBAR_TCDM_BUS s_dma_plugin_xbar_bus[NB_DMAS-1:0](); +XBAR_TCDM_BUS s_dma_plugin_xbar_bus[Cfg.DmaNumPlugs-1:0](); // ext -> xbar periphs FIXME -XBAR_TCDM_BUS s_mperiph_xbar_bus[NB_MPERIPHS-1:0](); +XBAR_TCDM_BUS s_mperiph_xbar_bus[Cfg.NumMstPeriphs-1:0](); // periph demux XBAR_TCDM_BUS s_mperiph_bus(); // cores & accelerators -> log interconnect hci_core_intf #( - .DW ( NB_HWPE_PORTS*DATA_WIDTH ), - .AW ( ADDR_WIDTH ), + .DW ( Cfg.HwpeNumPorts * DataWidth ), + .AW ( AddrWidth ), .OW ( 1 ) ) s_hci_hwpe [0:0] ( .clk ( clk_i ) ); hci_core_intf #( - .DW ( DATA_WIDTH ), - .AW ( ADDR_WIDTH ), + .DW ( DataWidth ), + .AW ( AddrWidth ), .OW ( 1 ) -) s_hci_core [NB_CORES-1:0] ( +) s_hci_core [Cfg.NumCores-1:0] ( .clk ( clk_i ) ); // cores -> periph interconnect -XBAR_PERIPH_BUS s_core_periph_bus[NB_CORES-1:0](); +XBAR_PERIPH_BUS s_core_periph_bus[Cfg.NumCores-1:0](); // periph interconnect -> DMA XBAR_PERIPH_BUS s_periph_dma_bus[1:0](); @@ -406,57 +354,57 @@ XBAR_PERIPH_BUS s_periph_dma_bus[1:0](); XBAR_PERIPH_BUS s_periph_hmr_bus (); // debug -XBAR_TCDM_BUS s_debug_bus[NB_CORES-1:0](); +XBAR_TCDM_BUS s_debug_bus[Cfg.NumCores-1:0](); /* other interfaces */ // cores -> DMA ctrl // FIXME: iDMA // XBAR_TCDM_BUS s_core_dmactrl_bus[NB_CORES-1:0](); hci_core_intf #( - .DW ( DATA_WIDTH ), - .AW ( ADDR_WIDTH ), + .DW ( DataWidth ), + .AW ( AddrWidth ), .OW ( 1 ), .UW ( 0 ) -) s_core_dmactrl_bus [NB_CORES-1:0] ( +) s_core_dmactrl_bus [Cfg.NumCores-1:0] ( .clk ( clk_i ) ); // cores -> event unit ctrl -XBAR_PERIPH_BUS s_core_euctrl_bus[NB_CORES-1:0](); +XBAR_PERIPH_BUS s_core_euctrl_bus[Cfg.NumCores-1:0](); // apu-interconnect // handshake signals -logic [NB_CORES-1:0] s_apu_master_req; -logic [NB_CORES-1:0] s_apu_master_gnt; +logic [Cfg.NumCores-1:0] s_apu_master_req; +logic [Cfg.NumCores-1:0] s_apu_master_gnt; // request channel -logic [NB_CORES-1:0][APU_NARGS_CPU-1:0][31:0] s_apu_master_operands; -logic [NB_CORES-1:0][APU_WOP_CPU-1:0] s_apu_master_op; -logic [NB_CORES-1:0][WAPUTYPE-1:0] s_apu_master_type; -logic [NB_CORES-1:0][APU_NDSFLAGS_CPU-1:0] s_apu_master_flags; +logic [Cfg.NumCores-1:0][FpuNumArgs-1:0][31:0] s_apu_master_operands; +logic [Cfg.NumCores-1:0][FpuOpCodeWidth-1:0] s_apu_master_op; +logic [Cfg.NumCores-1:0][FpuTypeWidth-1:0] s_apu_master_type; +logic [Cfg.NumCores-1:0][FpuInFlagsWidth-1:0] s_apu_master_flags; // response channel -logic [NB_CORES-1:0] s_apu_master_rready; -logic [NB_CORES-1:0] s_apu_master_rvalid; -logic [NB_CORES-1:0][31:0] s_apu_master_rdata; -logic [NB_CORES-1:0][APU_NUSFLAGS_CPU-1:0] s_apu_master_rflags; +logic [Cfg.NumCores-1:0] s_apu_master_rready; +logic [Cfg.NumCores-1:0] s_apu_master_rvalid; +logic [Cfg.NumCores-1:0][31:0] s_apu_master_rdata; +logic [Cfg.NumCores-1:0][FpuOutFlagsWidth-1:0] s_apu_master_rflags; //----------------------------------------------------------------------// // Interfaces between ICache - L0 - Icache_Interco and Icache_ctrl_unit // // // -SP_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_main[NB_CACHE_BANKS](); -PRI_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_pri[NB_CORES](); +SP_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_main[Cfg.iCacheNumBanks](); +PRI_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_pri[Cfg.NumCores](); logic s_special_core_icache_cfg; -logic[NB_CORES-1:0] s_enable_l1_l15_prefetch; +logic[Cfg.NumCores-1:0] s_enable_l1_l15_prefetch; //----------------------------------------------------------------------// -localparam TCDM_ID_WIDTH = NB_CORES+NB_DMAS+4+NB_HWPE_PORTS; +localparam TCDM_ID_WIDTH = Cfg.NumCores + Cfg.DmaNumPlugs + 4 + Cfg.HwpeNumPorts; // log interconnect -> TCDM memory banks (SRAM) hci_mem_intf #( - .AW (ADDR_WIDTH ), - .DW ( DATA_WIDTH ), + .AW ( AddrWidth ), + .DW ( DataWidth ), .BW ( 8 ), .IW ( TCDM_ID_WIDTH ) -) s_tcdm_bus_sram[NB_TCDM_BANKS-1:0] ( +) s_tcdm_bus_sram[Cfg.TcdmNumBank-1:0] ( .clk ( clk_i ) ); @@ -464,31 +412,31 @@ hci_mem_intf #( /* synchronous AXI interfaces at CLUSTER/SOC interface */ //*************************************************** AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_data_slave_int(); AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_S2C_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataInWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_data_slave_ext(); AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_data_master(); AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_core_instr_bus(); // ***********************************************************************************************+ @@ -503,34 +451,34 @@ AXI_BUS #( // core per2axi -> ext AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_core_ext_bus(); // DMA -> ext AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_dma_ext_bus(); // ext -> axi2mem AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_ext_tcdm_bus(); // cluster bus -> axi2per AXI_BUS #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_ext_mperiph_bus(); /* fetch & busy genertion */ @@ -540,19 +488,19 @@ assign fetch_en_int = fetch_enable_reg_int; /* cluster bus and attached peripherals */ cluster_bus_wrap #( - .NB_MASTER ( NumAxiMst ), - .NB_SLAVE ( NumAxiSlv ), - .NB_CORES ( NB_CORES ), - .DMA_NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), - .TCDM_SIZE ( TCDM_SIZE ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_IN_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_ID_OUT_WIDTH ( AXI_ID_OUT_WIDTH ), - .BaseAddr ( BaseAddr ), - .ClusterPeripheralsOffs ( ClusterPeripheralsOffs ), - .ClusterExternalOffs ( ClusterExternalOffs ) + .NB_MASTER ( Cfg.NumAxiOut ), + .NB_SLAVE ( Cfg.NumAxiIn ), + .NB_CORES ( Cfg.NumCores ), + .DMA_NB_OUTSND_BURSTS ( Cfg.DmaNumOutstandingBursts ), + .TCDM_SIZE ( Cfg.TcdmSize ), + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), + .AXI_ID_IN_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_ID_OUT_WIDTH ( Cfg.AxiIdOutWidth ), + .BaseAddr ( Cfg.ClusterBaseAddr ), + .ClusterPeripheralsOffs ( Cfg.ClusterPeriphOffs ), + .ClusterExternalOffs ( Cfg.ClusterExternalOffs ) ) cluster_bus_wrap_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -568,11 +516,11 @@ cluster_bus_wrap #( ); axi2mem_wrap #( - .NB_DMAS ( NB_DMAS ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ) + .NB_DMAS ( Cfg.DmaNumPlugs ), + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdOutWidth ) ) axi2mem_wrap_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -583,10 +531,10 @@ axi2mem_wrap #( ); axi2per_wrap #( - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_OUT_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ) + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) axi2per_wrap_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -596,10 +544,10 @@ axi2per_wrap #( .busy_o ( s_axi2per_busy ) ); -if (NB_MPERIPHS > 1) begin - XBAR_TCDM_BUS s_mperiph_demux_bus[NB_MPERIPHS-1:0](); +if (Cfg.NumMstPeriphs > 1) begin + XBAR_TCDM_BUS s_mperiph_demux_bus[Cfg.NumMstPeriphs-1:0](); per_demux_wrap #( - .NB_MASTERS ( NB_MPERIPHS ), + .NB_MASTERS ( Cfg.NumMstPeriphs ), .ADDR_OFFSET ( 20 ) ) per_demux_wrap_i ( .clk_i ( clk_i ), @@ -608,7 +556,7 @@ if (NB_MPERIPHS > 1) begin .masters ( s_mperiph_demux_bus ) ); - for (genvar i = 0; i < NB_MPERIPHS; i++) begin + for (genvar i = 0; i < Cfg.NumMstPeriphs; i++) begin `TCDM_ASSIGN_MASTER (s_mperiph_xbar_bus[i], s_mperiph_demux_bus[i]) end end else begin @@ -616,14 +564,14 @@ end else begin end per2axi_wrap #( - .NB_CORES ( NB_CORES ), - .PER_ADDR_WIDTH ( 32 ), - .PER_ID_WIDTH ( NB_CORES+NB_MPERIPHS ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ) -) per2axi_wrap_i ( + .NB_CORES ( Cfg.NumCores ), + .PER_ADDR_WIDTH ( 32 ), + .PER_ID_WIDTH ( Cfg.NumCores + Cfg.NumMstPeriphs ), + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ) +) per2axi_wrap_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .test_en_i ( test_mode_i ), @@ -637,47 +585,46 @@ per2axi_wrap #( //*************************************************** cluster_interconnect_wrap #( - .NB_CORES ( NB_CORES ), - .HWPE_PRESENT ( HWPE_PRESENT ), - .NB_HWPE_PORTS ( NB_HWPE_PORTS ), - .NB_DMAS ( NB_DMAS ), - .NB_MPERIPHS ( NB_MPERIPHS ), - .NB_TCDM_BANKS ( NB_TCDM_BANKS ), - .NB_SPERIPHS ( NB_SPERIPHS ), - - .DATA_WIDTH ( DATA_WIDTH ), - .ADDR_WIDTH ( ADDR_WIDTH ), - .BE_WIDTH ( BE_WIDTH ), - .ClusterBaseAddr ( BaseAddr ), - .ClusterPeripheralsOffs ( ClusterPeripheralsOffs ), - .ClusterExternalOffs ( ClusterExternalOffs ), - - .TEST_SET_BIT ( TEST_SET_BIT ), - .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH ), - - .LOG_CLUSTER ( LOG_CLUSTER ), - .PE_ROUTING_LSB ( PE_ROUTING_LSB ), - .CLUSTER_ALIAS ( CLUSTER_ALIAS ), - .USE_HETEROGENEOUS_INTERCONNECT ( USE_HETEROGENEOUS_INTERCONNECT ) + .NB_CORES ( Cfg.NumCores ), + .HWPE_PRESENT ( Cfg.HwpePresent ), + .NB_HWPE_PORTS ( Cfg.HwpeNumPorts ), + .NB_DMAS ( Cfg.DmaNumPlugs ), + .NB_MPERIPHS ( Cfg.NumMstPeriphs ), + .NB_TCDM_BANKS ( Cfg.TcdmNumBank ), + .NB_SPERIPHS ( Cfg.NumSlvPeriphs ), + + .DATA_WIDTH ( DataWidth ), + .ADDR_WIDTH ( AddrWidth ), + .BE_WIDTH ( BeWidth ), + .ClusterBaseAddr ( Cfg.ClusterBaseAddr ), + .ClusterPeripheralsOffs ( Cfg.ClusterPeriphOffs ), + .ClusterExternalOffs ( Cfg.ClusterExternalOffs), + + .TEST_SET_BIT ( TestSetBit ), + .ADDR_MEM_WIDTH ( AddrMemWidth ), + + .PE_ROUTING_LSB ( PeRoutingLsb ), + .CLUSTER_ALIAS ( Cfg.ClusterAlias ), + .USE_HETEROGENEOUS_INTERCONNECT ( Cfg.UseHci ) ) cluster_interconnect_wrap_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .cluster_id_i ( '0 ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .cluster_id_i ( '0 ), - .core_tcdm_slave ( s_hci_core ), - .hwpe_tcdm_slave ( s_hci_hwpe ), - .ext_slave ( s_hci_ext ), - .dma_slave ( s_hci_dma ), + .core_tcdm_slave ( s_hci_core ), + .hwpe_tcdm_slave ( s_hci_hwpe ), + .ext_slave ( s_hci_ext ), + .dma_slave ( s_hci_dma ), - .tcdm_sram_master ( s_tcdm_bus_sram ), + .tcdm_sram_master ( s_tcdm_bus_sram ), - .core_periph_slave ( s_core_periph_bus ), - .mperiph_slave ( s_mperiph_xbar_bus[NB_MPERIPHS-1:0] ), - .speriph_master ( s_xbar_speriph_bus ), + .core_periph_slave ( s_core_periph_bus ), + .mperiph_slave ( s_mperiph_xbar_bus[Cfg.NumMstPeriphs-1:0] ), + .speriph_master ( s_xbar_speriph_bus ), - .hci_ctrl_i ( s_hci_ctrl ), - .TCDM_arb_policy_i ( s_TCDM_arb_policy ) + .hci_ctrl_i ( s_hci_ctrl ), + .TCDM_arb_policy_i ( s_TCDM_arb_policy ) ); //*************************************************** @@ -685,19 +632,19 @@ cluster_interconnect_wrap #( //*************************************************** `ifdef TARGET_MCHAN dmac_wrap #( - .NB_CTRLS ( NB_CORES+2 ), - .NB_CORES ( NB_CORES ), - .NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), - .MCHAN_BURST_LENGTH ( MCHAN_BURST_LENGTH ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .PE_ID_WIDTH ( NB_CORES + 1 ), - .TCDM_ADD_WIDTH ( TCDM_ADD_WIDTH ), - .DATA_WIDTH ( DATA_WIDTH ), - .ADDR_WIDTH ( ADDR_WIDTH ), - .BE_WIDTH ( BE_WIDTH ) + .NB_CTRLS ( Cfg.NumCores + 2 ), + .NB_CORES ( Cfg.NumCores ), + .NB_OUTSND_BURSTS ( Cfg.DmaNumOutstandingBursts ), + .MCHAN_BURST_LENGTH ( Cfg.DmaBurstLength ), + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), + .PE_ID_WIDTH ( Cfg.NumCores + 1 ), + .TCDM_ADD_WIDTH ( TcdmAddrWidth ), + .DATA_WIDTH ( DataWidth ), + .ADDR_WIDTH ( AddrWidth ), + .BE_WIDTH ( BeWidth ) ) dmac_wrap_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -717,20 +664,20 @@ cluster_interconnect_wrap #( ); `else dmac_wrap #( - .NB_CORES ( NB_CORES ), - .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_C2S_WIDTH ), - .AXI_USER_WIDTH ( AXI_USER_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_IN_WIDTH ), - .PE_ID_WIDTH ( NB_CORES + 1 ), - .NB_PE_PORTS ( 2 ), - .DATA_WIDTH ( DATA_WIDTH ), - .ADDR_WIDTH ( ADDR_WIDTH ), - .BE_WIDTH ( BE_WIDTH ), - .NUM_STREAMS ( 4 ), - .TCDM_SIZE ( TCDM_SIZE ), - .NB_OUTSND_BURSTS ( NB_OUTSND_BURSTS ), - .ClusterBaseAddr ( BaseAddr ) + .NB_CORES ( Cfg.NumCores ), + .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), + .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .PE_ID_WIDTH ( Cfg.NumCores + 1 ), + .NB_PE_PORTS ( 2 ), + .DATA_WIDTH ( DataWidth ), + .ADDR_WIDTH ( AddrWidth ), + .BE_WIDTH ( BE_WIDTH ), + .NUM_STREAMS ( 4 ), + .TCDM_SIZE ( Cfg.TcdmSize ), + .NB_OUTSND_BURSTS ( Cfg.DmaNumOutstandingBursts ), + .ClusterBaseAddr ( Cfg.ClusterBaseAddr ) ) dmac_wrap_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -751,14 +698,14 @@ cluster_interconnect_wrap #( //**************CLUSTER PERIPHERALS****************** //*************************************************** cluster_peripherals #( - .NB_CORES ( NB_CORES ), - .NB_MPERIPHS ( NB_MPERIPHS ), - .NB_CACHE_BANKS ( NB_CACHE_BANKS ), - .NB_SPERIPHS ( NB_SPERIPHS ), - .NB_TCDM_BANKS ( NB_TCDM_BANKS ), - .ROM_BOOT_ADDR ( ROM_BOOT_ADDR ), - .BOOT_ADDR ( BOOT_ADDR ), - .EVNT_WIDTH ( EVNT_WIDTH ), + .NB_CORES ( Cfg.NumCores ), + .NB_MPERIPHS ( Cfg.NumMstPeriphs ), + .NB_CACHE_BANKS ( Cfg.iCacheNumBanks), + .NB_SPERIPHS ( Cfg.NumSlvPeriphs ), + .NB_TCDM_BANKS ( Cfg.TcdmNumBank ), + .ROM_BOOT_ADDR ( Cfg.BootRomBaseAddr), + .BOOT_ADDR ( Cfg.BootAddr ), + .EVNT_WIDTH ( EventWidth ), .NB_L1_CUTS ( NB_L1_CUTS ), .RW_MARGIN_WIDTH ( RW_MARGIN_WIDTH ) @@ -777,8 +724,8 @@ cluster_peripherals #( .core_busy_i ( core_busy ), .core_clk_en_o ( clk_core_en ), - .speriph_slave ( s_xbar_speriph_bus[NB_SPERIPHS-2:0]), - .core_eu_direct_link ( s_core_euctrl_bus ), + .speriph_slave ( s_xbar_speriph_bus[Cfg.NumSlvPeriphs-2:0] ), + .core_eu_direct_link ( s_core_euctrl_bus ), .dma_cfg_master ( s_periph_dma_bus ), .hmr_cfg_master ( s_periph_hmr_bus ), @@ -848,12 +795,12 @@ hmr_reg_req_t hmr_reg_req; hmr_reg_rsp_t hmr_reg_rsp; periph_to_reg #( - .AW ( ADDR_WIDTH ), - .DW ( DATA_WIDTH ), - .BW ( 8 ), - .IW ( NB_CORES + 1 ), - .req_t ( hmr_reg_req_t ), - .rsp_t ( hmr_reg_rsp_t ) + .AW ( AddrWidth ), + .DW ( DataWidth ), + .BW ( 8 ), + .IW ( Cfg.NumCores + 1 ), + .req_t ( hmr_reg_req_t ), + .rsp_t ( hmr_reg_rsp_t ) ) i_periph_to_hmr ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -872,19 +819,19 @@ periph_to_reg #( .reg_rsp_i ( hmr_reg_rsp ) ); -core_data_req_t [NB_CORES-1:0] core_data_req, demux_data_req; -core_data_rsp_t [NB_CORES-1:0] core_data_rsp, demux_data_rsp; -core_inputs_t [NB_CORES-1:0] sys2hmr, hmr2core; -core_outputs_t [NB_CORES-1:0] hmr2sys, core2hmr; -core_backup_t [NB_CORES-1:0] backup_bus; -rapid_recovery_pkg::rapid_recovery_t [NB_CORES-1:0] recovery_bus; +core_data_req_t [Cfg.NumCores-1:0] core_data_req, demux_data_req; +core_data_rsp_t [Cfg.NumCores-1:0] core_data_rsp, demux_data_rsp; +core_inputs_t [Cfg.NumCores-1:0] sys2hmr, hmr2core; +core_outputs_t [Cfg.NumCores-1:0] hmr2sys, core2hmr; +core_backup_t [Cfg.NumCores-1:0] backup_bus; +rapid_recovery_pkg::rapid_recovery_t [Cfg.NumCores-1:0] recovery_bus; -logic [NB_CORES-1:0] clk_core; -logic [NB_CORES-1:0] setback; -logic [NB_CORES-1:0][4:0] ext_perf; +logic [Cfg.NumCores-1:0] clk_core; +logic [Cfg.NumCores-1:0] setback; +logic [Cfg.NumCores-1:0][4:0] ext_perf; generate - for (genvar i=0; i Date: Fri, 9 Feb 2024 16:46:16 +0100 Subject: [PATCH 096/207] Properly drive ECC and scrubber signals when ECCs are not enabled. --- rtl/tcdm_banks_wrap.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/rtl/tcdm_banks_wrap.sv b/rtl/tcdm_banks_wrap.sv index 84e48395..758d2690 100644 --- a/rtl/tcdm_banks_wrap.sv +++ b/rtl/tcdm_banks_wrap.sv @@ -96,10 +96,10 @@ for(genvar i=0; i Date: Fri, 9 Feb 2024 18:50:34 +0100 Subject: [PATCH 097/207] Update RedMuE commit for bug fixing. --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index 6329c92f..24aaad01 100644 --- a/Bender.lock +++ b/Bender.lock @@ -183,7 +183,7 @@ packages: dependencies: - axi_slice redmule: - revision: 532f9514ad5c7ee21dde9e3a84ae99d2a5760610 + revision: afc6d5cfd5cf966e30e74837eefd441c6bfacec7 version: null source: Git: https://github.com/pulp-platform/redmule.git diff --git a/Bender.yml b/Bender.yml index ed720f84..3e5cbdee 100644 --- a/Bender.yml +++ b/Bender.yml @@ -34,7 +34,7 @@ dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 651441e4a6459f84f3dde4242cf34961925a2142 } # branch: astral_rebase - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 532f9514ad5c7ee21dde9e3a84ae99d2a5760610 } # branch: astral + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: afc6d5cfd5cf966e30e74837eefd441c6bfacec7 } # branch: carfield export_include_dirs: - include From 4f838bf830d57983cf9476d4325425e782c5e6f5 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 10 Feb 2024 12:14:59 +0100 Subject: [PATCH 098/207] Bump HCI, cluster peripherals, and RedMulE. --- Bender.local | 1 - Bender.lock | 6 +++--- Bender.yml | 6 +++--- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/Bender.local b/Bender.local index c6274f27..2386c8ee 100644 --- a/Bender.local +++ b/Bender.local @@ -1,5 +1,4 @@ overrides: - hci : { git: "https://github.com/pulp-platform/hci.git" , rev: 3cb3d99b2cebfeed55cb6ab9d98fce7b99e97cb9 } # branch: master axi : { git: "https://github.com/pulp-platform/axi.git" , version: =0.39.1-beta } register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix diff --git a/Bender.lock b/Bender.lock index 24aaad01..7db025a3 100644 --- a/Bender.lock +++ b/Bender.lock @@ -53,7 +53,7 @@ packages: dependencies: - common_cells cluster_peripherals: - revision: c015839816938a790c8da5fd5829cfc536f1ca9c + revision: c9defcfb4f4e8733383b28a451c430783c2febbd version: null source: Git: https://github.com/pulp-platform/cluster_peripherals.git @@ -105,7 +105,7 @@ packages: dependencies: - common_cells hci: - revision: 3cb3d99b2cebfeed55cb6ab9d98fce7b99e97cb9 + revision: 4823e503851eb7e8cc765a58621d767a01d6a77b version: null source: Git: https://github.com/pulp-platform/hci.git @@ -183,7 +183,7 @@ packages: dependencies: - axi_slice redmule: - revision: afc6d5cfd5cf966e30e74837eefd441c6bfacec7 + revision: 1b30b0b9a31afa702eb2d166d672ceda2f5d463a version: null source: Git: https://github.com/pulp-platform/redmule.git diff --git a/Bender.yml b/Bender.yml index 3e5cbdee..316fd835 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,7 +20,7 @@ dependencies: mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a971e364bf8090cf77fafad995b480c1ac7ea4e0" } # branch: yt/carfield - cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: c015839816938a790c8da5fd5829cfc536f1ca9c } # branch: yt/return-reg + cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: c9defcfb4f4e8733383b28a451c430783c2febbd } # branch: astral axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } @@ -30,11 +30,11 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: 3cb3d99b2cebfeed55cb6ab9d98fce7b99e97cb9 } # branch: test_mode_fix + hci: { git: "https://github.com/pulp-platform/hci.git", rev: v1.1 } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 651441e4a6459f84f3dde4242cf34961925a2142 } # branch: astral_rebase - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: afc6d5cfd5cf966e30e74837eefd441c6bfacec7 } # branch: carfield + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 1b30b0b9a31afa702eb2d166d672ceda2f5d463a } # branch: astral export_include_dirs: - include From 29db9a5d867aca217ec26587051cfe94c2b79139 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella <48508508+yvantor@users.noreply.github.com> Date: Sat, 10 Feb 2024 10:28:07 +0100 Subject: [PATCH 099/207] Cherry-pick CI fixes. * Add `run_and_exit.tcl`; use specific commits for regressions and runtime. * Update nonfree flow * Fix environment sourcing * Adapt run scripts to use VSIM. * Add error suppression for WLF logging. --------- Co-authored-by: Yvan Tortorella Co-authored-by: Michael Rogenmoser --- Makefile | 8 +++++--- scripts/run_and_exit.tcl | 23 +++++++++++++++++++++++ scripts/start.tcl | 6 +++++- 3 files changed, 33 insertions(+), 4 deletions(-) create mode 100644 scripts/run_and_exit.tcl diff --git a/Makefile b/Makefile index b291539c..6a7af560 100644 --- a/Makefile +++ b/Makefile @@ -51,7 +51,7 @@ endef ###################### NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git -NONFREE_COMMIT ?= e327fb9f8cb4a583d219862e81245405f22283bb +NONFREE_COMMIT ?= f069d0a234e5d33e6971d2fdd590b5df22ea6bd8 nonfree-init: git clone $(NONFREE_REMOTE) nonfree @@ -78,11 +78,13 @@ Bender.lock: ## Clone pulp-runtime as SW stack pulp-runtime: - git clone git@github.com:pulp-platform/pulp-runtime.git -b astral $@ + git clone https://github.com/pulp-platform/pulp-runtime.git $@ + cd $@; git checkout 38ae6be6e28ff39f79218d333c41632a935bd584; cd .. ## Clone regression tests for bare-metal verification regression-tests: - git clone git@github.com:pulp-platform/regression_tests.git -b astral $@ + git clone https://github.com/pulp-platform/regression_tests.git $@ + cd $@; git checkout 7343d39bb9d1137b6eb3f2561777df546cd1e421; cd .. ######################## # Build and simulation # diff --git a/scripts/run_and_exit.tcl b/scripts/run_and_exit.tcl new file mode 100644 index 00000000..242b667c --- /dev/null +++ b/scripts/run_and_exit.tcl @@ -0,0 +1,23 @@ +if {![info exists VSIM_PATH ]} { + return -code error -errorinfo "[ERRORINFO] You must set the \"VSIM_PATH\" variable before sourcing the start script." + set VSIM_PATH "" +} + +if {![info exists APP]} { + set APP "./build/test/test" +} + +if {![info exists VSIM]} { + set VSIM vsim +} + +$VSIM +permissive -suppress 3053 -suppress 8885 -suppress 12130 -lib $VSIM_PATH/work +APP=./build/test/test +notimingchecks +nospecify -t 1ps pulp_cluster_tb_optimized +permissive-off ++./build/test/test + +add log -r /* + +proc run_and_exit {} { + run -all + quit -code [examine -radix decimal sim:/pulp_cluster_tb/ret_val(30:0)] +} + +run_and_exit diff --git a/scripts/start.tcl b/scripts/start.tcl index a9ebc7fa..69413969 100644 --- a/scripts/start.tcl +++ b/scripts/start.tcl @@ -3,7 +3,11 @@ if {![info exists VSIM_PATH ]} { set VSIM_PATH "" } -vsim +permissive -suppress 3053 -suppress 8885 +UVM_NO_RELNOTES -lib $VSIM_PATH/work +APP=./build/test/test +notimingchecks +nospecify -t 1ps pulp_cluster_tb_optimized +permissive-off ++./build/test/test +if {![info exists VSIM]} { + set VSIM vsim +} + +$VSIM +permissive -suppress 3053 -suppress 8885 -suppress 12130 -lib $VSIM_PATH/work +APP=./build/test/test +notimingchecks +nospecify -t 1ps pulp_cluster_tb_optimized +permissive-off ++./build/test/test add log -r /* run -all From 242c9ff6b70abf0644061590dc34ab4d62174c22 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Wed, 7 Feb 2024 09:42:42 +0100 Subject: [PATCH 100/207] Set up questa version for IIS --- env/env.sh | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/env/env.sh b/env/env.sh index c53e25b0..80caa63b 100644 --- a/env/env.sh +++ b/env/env.sh @@ -4,5 +4,19 @@ # set up environment variables for rtl simulation, pulp-runtime and freertos ROOTD=$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")/.." && pwd) + +# If at IIS, set up appropriate questa version. +if test -f /etc/iis.version; then + export QUESTA=questa-2023.4-zr + export VLOG="$QUESTA vlog" + export VLIB="$QUESTA vlib" + export VMAP="$QUESTA vmap" + export VCOM="$QUESTA vcom" + export VOPT="$QUESTA vopt" + export VSIM="$QUESTA vsim" + export QUESTA_HOME=/usr/pack/${QUESTA}/questasim + export QUESTASIM_HOME=/usr/pack/${QUESTA}/questasim +fi + source "$ROOTD/pulp-runtime/configs/pulp_cluster.sh" source "$ROOTD/scripts/vsim.sh" From 13c6da8c788edae8f3c6ea6a1951ae92e9f8f697 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 10 Feb 2024 17:27:13 +0100 Subject: [PATCH 101/207] Make CI flow more reliable. --- Makefile | 19 +++++++++---------- env/carfield-env.sh | 15 +++++++++++++++ 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index 6a7af560..e9dfd298 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 -ROOT_DIR = $(strip $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) +ROOT_DIR = $(strip $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) QUESTA ?= questa-2022.3 GIT ?= git @@ -15,6 +15,8 @@ library ?= work elf-bin ?= stimuli.riscv bwruntest = $(ROOT_DIR)/pulp-runtime/scripts/bwruntests.py +REGRESSIONS := $(ROOT_DIR)/regression-tests + CFLAGS ?= -I$(QUESTASIM_HOME)/include \ -I$(RISCV)/include/ \ -I/include -std=c++11 -I../tb/dpi -O3 @@ -51,7 +53,7 @@ endef ###################### NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git -NONFREE_COMMIT ?= f069d0a234e5d33e6971d2fdd590b5df22ea6bd8 +NONFREE_COMMIT ?= bb64efc82c3cff99a5de9585c8963025078c16c2 nonfree-init: git clone $(NONFREE_REMOTE) nonfree @@ -79,12 +81,12 @@ Bender.lock: ## Clone pulp-runtime as SW stack pulp-runtime: git clone https://github.com/pulp-platform/pulp-runtime.git $@ - cd $@; git checkout 38ae6be6e28ff39f79218d333c41632a935bd584; cd .. + cd $@; git checkout 197d06b6ad1d8014cef73e0e87b59b5ebf66d019; cd $(ROOT_DIR) ## Clone regression tests for bare-metal verification regression-tests: git clone https://github.com/pulp-platform/regression_tests.git $@ - cd $@; git checkout 7343d39bb9d1137b6eb3f2561777df546cd1e421; cd .. + cd $@; git checkout b85310fd9ed068a0b310b67ed7b3aa46ec30c9bb; cd $(ROOT_DIR) ######################## # Build and simulation # @@ -117,16 +119,13 @@ run: .PHONY: test-rt-par-bare ## Run only parallel tests on pulp-runtime test-rt-par-bare: pulp-runtime regression-tests - source env/carfield-env.sh; \ - cd regression-tests && $(bwruntest) --proc-verbose -v \ + cd $(REGRESSIONS)/carfield && $(bwruntest) --proc-verbose -v \ -t 3600 --yaml --max-procs 2 \ - -o runtime-parallel.xml parallel-bare-tests.yaml - + -o $(REGRESSIONS)/carfield/runtime-parallel.xml $(REGRESSIONS)/carfield/parallel-bare-tests.yaml .PHONY: test-rt-mchan ## Run mchan tests on pulp-runtime test-rt-mchan: pulp-runtime regression-tests - source env/carfield-env.sh; \ cd regression-tests && $(bwruntest) --proc-verbose -v \ -t 3600 --yaml --max-procs 2 \ - -o runtime-mchan.xml pulp_cluster-mchan-tests.yaml + -o $(REGRESSIONS)/carfield/runtime-mchan.xml $(REGRESSIONS)/carfield/pulp_cluster-mchan-tests.yaml diff --git a/env/carfield-env.sh b/env/carfield-env.sh index 4426c8f9..90a85222 100644 --- a/env/carfield-env.sh +++ b/env/carfield-env.sh @@ -4,5 +4,20 @@ # set up environment variables for rtl simulation, pulp-runtime and freertos ROOTD=$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")/.." && pwd) + +# If at IIS, set up appropriate questa version. +if test -f /etc/iis.version; then + export QUESTA=questa-2023.4-zr + export VLOG="$QUESTA vlog" + export VLIB="$QUESTA vlib" + export VMAP="$QUESTA vmap" + export VCOM="$QUESTA vcom" + export VOPT="$QUESTA vopt" + export VSIM="$QUESTA vsim" + export QUESTA_HOME=/usr/pack/${QUESTA}/questasim + export QUESTASIM_HOME=/usr/pack/${QUESTA}/questasim + export PULP_RUNTIME_GCC_TOOLCHAIN=/usr/pack/riscv-1.0-kgf/pulp-gcc-1.0.16 +fi + source "$ROOTD/pulp-runtime/configs/carfield-cluster.sh" source "$ROOTD/scripts/vsim.sh" From 89dae226941ee479c00301035810ca29eeacb6e8 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 10 Feb 2024 23:10:30 +0100 Subject: [PATCH 102/207] Update nonfree to simplify CI extension. --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index e9dfd298..1cc2da6a 100644 --- a/Makefile +++ b/Makefile @@ -53,7 +53,7 @@ endef ###################### NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git -NONFREE_COMMIT ?= bb64efc82c3cff99a5de9585c8963025078c16c2 +NONFREE_COMMIT ?= 7bd4e0bab5282a20aebbe63de6bb94462bdc1231 nonfree-init: git clone $(NONFREE_REMOTE) nonfree @@ -86,7 +86,7 @@ pulp-runtime: ## Clone regression tests for bare-metal verification regression-tests: git clone https://github.com/pulp-platform/regression_tests.git $@ - cd $@; git checkout b85310fd9ed068a0b310b67ed7b3aa46ec30c9bb; cd $(ROOT_DIR) + cd $@; git checkout 8c9dc7e5a489cad272378c81a0058517f11d9adf; cd $(ROOT_DIR) ######################## # Build and simulation # From 67566fb7f63c4c3b7bc694d0813464c73323892f Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Mon, 12 Feb 2024 18:54:53 +0100 Subject: [PATCH 103/207] Update regression targets in Makefile --- Makefile | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 1cc2da6a..98b9a4d4 100644 --- a/Makefile +++ b/Makefile @@ -119,13 +119,20 @@ run: .PHONY: test-rt-par-bare ## Run only parallel tests on pulp-runtime test-rt-par-bare: pulp-runtime regression-tests - cd $(REGRESSIONS)/carfield && $(bwruntest) --proc-verbose -v \ + cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ -t 3600 --yaml --max-procs 2 \ - -o $(REGRESSIONS)/carfield/runtime-parallel.xml $(REGRESSIONS)/carfield/parallel-bare-tests.yaml + -o $(REGRESSIONS)/carfield/runtime-parallel.xml $(REGRESSIONS)/parallel-bare-tests.yaml .PHONY: test-rt-mchan ## Run mchan tests on pulp-runtime test-rt-mchan: pulp-runtime regression-tests - cd regression-tests && $(bwruntest) --proc-verbose -v \ + cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ -t 3600 --yaml --max-procs 2 \ - -o $(REGRESSIONS)/carfield/runtime-mchan.xml $(REGRESSIONS)/carfield/pulp_cluster-mchan-tests.yaml + -o $(REGRESSIONS)/carfield/runtime-mchan.xml $(REGRESSIONS)/pulp_cluster-mchan-tests.yaml + +.PHONY: test-rt-carfield +## Run Carfield tests on pulp-runtime +test-rt-carfield: pulp-runtime regression-tests + cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ + -t 3600 --yaml --max-procs 2 \ + -o $(REGRESSIONS)/carfield/runtime-mchan.xml $(REGRESSIONS)/carfield.yaml From 94f366ef36c4996b50b1e331c8f3430f67feb026 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Tue, 13 Feb 2024 08:46:41 +0100 Subject: [PATCH 104/207] Increase timeout for mchan tests --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 98b9a4d4..7b147a04 100644 --- a/Makefile +++ b/Makefile @@ -127,7 +127,7 @@ test-rt-par-bare: pulp-runtime regression-tests ## Run mchan tests on pulp-runtime test-rt-mchan: pulp-runtime regression-tests cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ - -t 3600 --yaml --max-procs 2 \ + -t 7200 --yaml --max-procs 2 \ -o $(REGRESSIONS)/carfield/runtime-mchan.xml $(REGRESSIONS)/pulp_cluster-mchan-tests.yaml .PHONY: test-rt-carfield From f2f3a39d44235d915ab25fae96dc4896644464f2 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Tue, 13 Feb 2024 10:00:54 +0100 Subject: [PATCH 105/207] Create a separate fragment for regression targets --- Makefile | 32 ++++++-------------------------- regression.mk | 25 +++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 26 deletions(-) create mode 100644 regression.mk diff --git a/Makefile b/Makefile index 7b147a04..995a729a 100644 --- a/Makefile +++ b/Makefile @@ -81,12 +81,7 @@ Bender.lock: ## Clone pulp-runtime as SW stack pulp-runtime: git clone https://github.com/pulp-platform/pulp-runtime.git $@ - cd $@; git checkout 197d06b6ad1d8014cef73e0e87b59b5ebf66d019; cd $(ROOT_DIR) - -## Clone regression tests for bare-metal verification -regression-tests: - git clone https://github.com/pulp-platform/regression_tests.git $@ - cd $@; git checkout 8c9dc7e5a489cad272378c81a0058517f11d9adf; cd $(ROOT_DIR) + cd $@; git checkout e90f6e53279248bf64d98a8247f79f0f13545c11; cd $(ROOT_DIR) ######################## # Build and simulation # @@ -116,23 +111,8 @@ run: $(VSIM) +permissive $(questa-flags) $(uvm-flags) $(QUESTASIM_FLAGS) $(questa-cmd) -suppress 3053 -suppress 8885 -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) +APP=$(elf-bin) +notimingchecks +nospecify -t 1ps \ ${top_level}_optimized +permissive-off ++$(elf-bin) ++$(target-options) ++$(cl-bin) | tee sim.log -.PHONY: test-rt-par-bare -## Run only parallel tests on pulp-runtime -test-rt-par-bare: pulp-runtime regression-tests - cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ - -t 3600 --yaml --max-procs 2 \ - -o $(REGRESSIONS)/carfield/runtime-parallel.xml $(REGRESSIONS)/parallel-bare-tests.yaml - -.PHONY: test-rt-mchan -## Run mchan tests on pulp-runtime -test-rt-mchan: pulp-runtime regression-tests - cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ - -t 7200 --yaml --max-procs 2 \ - -o $(REGRESSIONS)/carfield/runtime-mchan.xml $(REGRESSIONS)/pulp_cluster-mchan-tests.yaml - -.PHONY: test-rt-carfield -## Run Carfield tests on pulp-runtime -test-rt-carfield: pulp-runtime regression-tests - cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ - -t 3600 --yaml --max-procs 2 \ - -o $(REGRESSIONS)/carfield/runtime-mchan.xml $(REGRESSIONS)/carfield.yaml +#################### +# Regression tests # +#################### + +include regression.mk diff --git a/regression.mk b/regression.mk new file mode 100644 index 00000000..6457e4f9 --- /dev/null +++ b/regression.mk @@ -0,0 +1,25 @@ +## Clone regression tests for bare-metal verification +regression-tests: + git clone https://github.com/pulp-platform/regression_tests.git $@ + cd $@; git checkout 6d31694ab395aa7d35daaaea10a7bb66811118bf; cd $(ROOT_DIR) + +.PHONY: test-rt-par-bare +## Run only parallel tests on pulp-runtime +test-rt-par-bare: pulp-runtime regression-tests + cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ + -t 3600 --yaml --max-procs 2 \ + -o $(REGRESSIONS)/carfield/runtime-parallel.xml $(REGRESSIONS)/parallel-bare-tests.yaml + +.PHONY: test-rt-mchan +## Run mchan tests on pulp-runtime +test-rt-mchan: pulp-runtime regression-tests + cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ + -t 7200 --yaml --max-procs 2 \ + -o $(REGRESSIONS)/carfield/runtime-mchan.xml $(REGRESSIONS)/pulp_cluster-mchan-tests.yaml + +.PHONY: test-rt-carfield +## Run Carfield tests on pulp-runtime +test-rt-carfield: pulp-runtime regression-tests + cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ + -t 3600 --yaml --max-procs 2 \ + -o $(REGRESSIONS)/carfield/runtime-mchan.xml $(REGRESSIONS)/carfield.yaml From c59f3daabfe9d26fc15f890ef75e8c6bd1d6a7e8 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Tue, 13 Feb 2024 14:27:05 +0100 Subject: [PATCH 106/207] Bump `redundancy_cells` --- Bender.lock | 2 +- Bender.yml | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Bender.lock b/Bender.lock index 7db025a3..aa6eab1a 100644 --- a/Bender.lock +++ b/Bender.lock @@ -196,7 +196,7 @@ packages: - hwpe-stream - tech_cells_generic redundancy_cells: - revision: 651441e4a6459f84f3dde4242cf34961925a2142 + revision: c37bdb47339bf70e8323de8df14ea8bbeafb6583 version: null source: Git: https://github.com/pulp-platform/redundancy_cells.git diff --git a/Bender.yml b/Bender.yml index 316fd835..1cb94f7b 100644 --- a/Bender.yml +++ b/Bender.yml @@ -4,7 +4,7 @@ package: name: pulp_cluster - authors: + authors: - "Pirmin Vogel " - "Angelo Garofalo " - "Francesco Conti " @@ -33,7 +33,7 @@ dependencies: hci: { git: "https://github.com/pulp-platform/hci.git", rev: v1.1 } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } - redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 651441e4a6459f84f3dde4242cf34961925a2142 } # branch: astral_rebase + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 1b30b0b9a31afa702eb2d166d672ceda2f5d463a } # branch: astral export_include_dirs: @@ -79,7 +79,7 @@ sources: TRACE_EXECUTION: ~ # Level 3 - rtl/pulp_cluster.sv - + - target: test files: - tb/mock_uart.sv @@ -90,4 +90,4 @@ sources: - target: cluster_standalone files: - include/pulp_interfaces.sv - + From a47e90538a2907aac7cddea2726fc5a835aad847 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 20 Feb 2024 17:22:42 +0100 Subject: [PATCH 107/207] Remove deprecated dependencies. --- Bender.local | 2 +- Bender.lock | 23 +++++++---------------- Bender.yml | 3 +-- 3 files changed, 9 insertions(+), 19 deletions(-) diff --git a/Bender.local b/Bender.local index 2386c8ee..8ac1a168 100644 --- a/Bender.local +++ b/Bender.local @@ -1,4 +1,4 @@ overrides: - axi : { git: "https://github.com/pulp-platform/axi.git" , version: =0.39.1-beta } + axi : { git: "https://github.com/pulp-platform/axi.git" , version: =0.39.1 } register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix diff --git a/Bender.lock b/Bender.lock index aa6eab1a..01e1fbae 100644 --- a/Bender.lock +++ b/Bender.lock @@ -7,8 +7,8 @@ packages: dependencies: - common_cells axi: - revision: da423834b45f2e1878ecb28a11dc5b72b437f9c1 - version: 0.39.1-beta + revision: fccffb5953ec8564218ba05e20adbedec845e014 + version: 0.39.1 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -30,19 +30,11 @@ packages: Git: https://github.com/pulp-platform/axi2per.git dependencies: - axi_slice - axi_node: - revision: e2d038004c5b8cec9dd3bb9d23ad0bee72f9d908 - version: 1.1.4 - source: - Git: git@github.com:pulp-platform/axi_node.git - dependencies: - - axi - - common_cells axi_slice: revision: a4f72bc21ac4d7da631e8309d9f8d0c34b735c23 version: 1.1.4 source: - Git: https://github.com/pulp-platform/axi_slice.git + Git: git@github.com:pulp-platform/axi_slice.git dependencies: - common_cells cluster_interconnect: @@ -114,13 +106,12 @@ packages: - hwpe-stream - l2_tcdm_hybrid_interco hier-icache: - revision: a971e364bf8090cf77fafad995b480c1ac7ea4e0 + revision: 8e77bdc828c717299ac8572a1f9bf10144382105 version: null source: Git: https://github.com/pulp-platform/hier-icache.git dependencies: - - axi_node - - axi_slice + - axi - common_cells - icache-intc - scm @@ -133,8 +124,8 @@ packages: dependencies: - tech_cells_generic hwpe-stream: - revision: 389bd7fb1975d2df1546910c5f220c668122e646 - version: 1.6.5 + revision: 4c2ef8c33a6e2a8c88127e2153013d4f2dc3f448 + version: 1.7.0 source: Git: https://github.com/pulp-platform/hwpe-stream.git dependencies: diff --git a/Bender.yml b/Bender.yml index 1cb94f7b..3f83c9d6 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,10 +19,9 @@ dependencies: event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master - hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "a971e364bf8090cf77fafad995b480c1ac7ea4e0" } # branch: yt/carfield + hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "8e77bdc828c717299ac8572a1f9bf10144382105" } # branch: astral cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: c9defcfb4f4e8733383b28a451c430783c2febbd } # branch: astral axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } - axi_slice: { git: "https://github.com/pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo) timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } From 8b19b1ca49ccb490b48343e0b49f7402dc5edc59 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Tue, 20 Feb 2024 18:57:11 +0100 Subject: [PATCH 108/207] Use git submodules for `pulp-runtime` and `regression_tests` --- .gitmodules | 6 ++++++ Makefile | 3 +-- pulp-runtime | 1 + regression-tests | 1 + regression.mk | 3 +-- 5 files changed, 10 insertions(+), 4 deletions(-) create mode 100644 .gitmodules create mode 160000 pulp-runtime create mode 160000 regression-tests diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 00000000..2c0f881d --- /dev/null +++ b/.gitmodules @@ -0,0 +1,6 @@ +[submodule "pulp-runtime"] + path = pulp-runtime + url = https://github.com/pulp-platform/pulp-runtime.git +[submodule "regression-tests"] + path = regression-tests + url = https://github.com/pulp-platform/regression_tests.git diff --git a/Makefile b/Makefile index 995a729a..d5d3f294 100644 --- a/Makefile +++ b/Makefile @@ -80,8 +80,7 @@ Bender.lock: ## Clone pulp-runtime as SW stack pulp-runtime: - git clone https://github.com/pulp-platform/pulp-runtime.git $@ - cd $@; git checkout e90f6e53279248bf64d98a8247f79f0f13545c11; cd $(ROOT_DIR) + git submodule update --init --recursive $@ ######################## # Build and simulation # diff --git a/pulp-runtime b/pulp-runtime new file mode 160000 index 00000000..e90f6e53 --- /dev/null +++ b/pulp-runtime @@ -0,0 +1 @@ +Subproject commit e90f6e53279248bf64d98a8247f79f0f13545c11 diff --git a/regression-tests b/regression-tests new file mode 160000 index 00000000..6d31694a --- /dev/null +++ b/regression-tests @@ -0,0 +1 @@ +Subproject commit 6d31694ab395aa7d35daaaea10a7bb66811118bf diff --git a/regression.mk b/regression.mk index 6457e4f9..6364108f 100644 --- a/regression.mk +++ b/regression.mk @@ -1,7 +1,6 @@ ## Clone regression tests for bare-metal verification regression-tests: - git clone https://github.com/pulp-platform/regression_tests.git $@ - cd $@; git checkout 6d31694ab395aa7d35daaaea10a7bb66811118bf; cd $(ROOT_DIR) + git submodule update --init --recursive $@ .PHONY: test-rt-par-bare ## Run only parallel tests on pulp-runtime From 72fae340fd8f28b2f0afeda312149e2bf35c27fd Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Wed, 21 Feb 2024 11:34:19 +0100 Subject: [PATCH 109/207] Add explicit `init` target in `Makefile` --- Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Makefile b/Makefile index d5d3f294..e20ebc84 100644 --- a/Makefile +++ b/Makefile @@ -63,6 +63,10 @@ nonfree-init: # Dependencies # ################ +.PHONY: init + +init: checkout pulp-runtime regression-tests + .PHONY: checkout scripts/compile.tcl ## Checkout/update dependencies using Bender checkout: @@ -74,6 +78,7 @@ Bender.lock: bender checkout touch Bender.lock + ###### # SW # ###### From 828f69f727fa487809ee2bf6f55a244d2d66e9f5 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Tue, 27 Feb 2024 09:46:44 +0100 Subject: [PATCH 110/207] Add fault injection scripts to simulation flow --- .gitmodules | 4 +- Makefile | 4 + fault_injection_sim | 1 + .../pulp_extract_nets.tcl | 246 ++++++++++++++++++ .../pulp_inject_fault.tcl | 51 ++++ scripts/run_and_exit.tcl | 4 + scripts/start.tcl | 4 + 7 files changed, 313 insertions(+), 1 deletion(-) create mode 160000 fault_injection_sim create mode 100644 scripts/fault_injection_config/pulp_extract_nets.tcl create mode 100644 scripts/fault_injection_config/pulp_inject_fault.tcl diff --git a/.gitmodules b/.gitmodules index 1e861dcf..5e63128c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -5,4 +5,6 @@ [submodule "regression-tests"] path = regression-tests url = https://github.com/pulp-platform/regression_tests.git - branch = astral +[submodule "fault_injection_sim"] + path = fault_injection_sim + url = git@iis-git.ee.ethz.ch:michaero/fault_injection_sim.git diff --git a/Makefile b/Makefile index e20ebc84..26a0dc24 100644 --- a/Makefile +++ b/Makefile @@ -87,6 +87,10 @@ Bender.lock: pulp-runtime: git submodule update --init --recursive $@ +## Clone fault injection scripts +fault_injection_sim: + git submodule update --init --recursive $@ + ######################## # Build and simulation # ######################## diff --git a/fault_injection_sim b/fault_injection_sim new file mode 160000 index 00000000..84ddcff9 --- /dev/null +++ b/fault_injection_sim @@ -0,0 +1 @@ +Subproject commit 84ddcff943b7c2d63fb97fc9ff1864ccea398eef diff --git a/scripts/fault_injection_config/pulp_extract_nets.tcl b/scripts/fault_injection_config/pulp_extract_nets.tcl new file mode 100644 index 00000000..72e79cd6 --- /dev/null +++ b/scripts/fault_injection_config/pulp_extract_nets.tcl @@ -0,0 +1,246 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Author: Michael Rogenmoser (michaero@iis.ee.ethz.ch) +# Riccardo Tedeschi (riccardo.tedeschi6@unibo.it) + +# Description: This file is used to extract specific groups of nets from the +# PULP Cluster, so they can be used in the fault injection script + +# Source generic netlist extraction procs +source [file join $script_base_path extract_nets.tcl] + +# == Base Path of a Cluster Core == +proc base_path {core} {return "pulp_cluster_tb/cluster_i/CORE\[$core\]/core_region_i"} + +# nets that would crash the simulation if flipped +lappend core_netlist_ignore *clk_i +lappend core_netlist_ignore *Clk_CI +lappend core_netlist_ignore *clk +lappend core_netlist_ignore *clk_ungated_i +lappend core_netlist_ignore *rst_ni +lappend core_netlist_ignore *rst_i +lappend core_netlist_ignore *rst_n +lappend core_netlist_ignore *rst +lappend core_netlist_ignore *Rst_RBI +lappend core_netlist_ignore *scan_cg_en_i +lappend core_netlist_ignore *testmode_i +lappend core_netlist_ignore *i_fpnew_bulk* + +# registers/memories: +# lappend core_netlist_ignore *_q +# lappend core_netlist_ignore *obi_pulp_adapter/ps TODOs + +# debug +lappend core_netlist_ignore *tracer_i* + +###################### +# Core Output Nets # +###################### + +proc get_core_output_nets {core} { + set core_output_netlist [get_output_netlist [base_path $core]] + lappend core_output_netlist [base_path $core]/RI5CY_CORE/RI5CY_CORE/data_we_o + lappend core_output_netlist [base_path $core]/RI5CY_CORE/RI5CY_CORE/data_be_o + lappend core_output_netlist [base_path $core]/RI5CY_CORE/RI5CY_CORE/data_addr_o + lappend core_output_netlist [base_path $core]/RI5CY_CORE/RI5CY_CORE/data_wdata_o + return [concat $core_output_netlist] +} + +#################### +# State Netlists # +#################### +proc get_core_state_nets {core} { + set state_list {\ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/fifo_i/write_pointer_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/register_file_i/wdata_b_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/register_file_i/wdata_a_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/register_file_i/waddr_onehot_b_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/gen_apu/apu_disp_i/valid_waiting \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/gen_apu/apu_disp_i/valid_inflight \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/utvec_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/utvec_mode_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/uepc_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/ucause_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/prefetch_controller_i/trans_addr_q \ + [base_path $core]/RI5CY_CORE/riscv_tracer_i/trace_wb_is_null \ + [base_path $core]/RI5CY_CORE/riscv_tracer_i/trace_wb_delay_is_null \ + [base_path $core]/RI5CY_CORE/riscv_tracer_i/trace_ex_is_null \ + [base_path $core]/RI5CY_CORE/riscv_tracer_i/trace_ex_delay_is_null \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/gen_trigger_regs/tmatch_value_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/gen_trigger_regs/tmatch_control_exec_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/fifo_i/status_cnt_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/State_SP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/data_obi_i/state_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/instruction_obi_i/state_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/prefetch_controller_i/state_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/aligner_i/state \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/ResReg_DP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/ResInv_SP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/RemSel_SP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/regfile_we_lsu \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/regfile_we_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/regfile_waddr_lsu \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/regfile_waddr_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/regfile_alu_we_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/regfile_alu_waddr_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/fifo_i/read_pointer_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/rdata_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/rdata_offset_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/aligner_i/r_instr_h \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/priv_lvl_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/prepost_useincr_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/aligner_i/pc_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/pc_id_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/pc_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/sleep_unit_i/p_elw_busy_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/instruction_obi_i/gen_no_trans_stable/obi_we_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/instruction_obi_i/gen_no_trans_stable/obi_wdata_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/instruction_obi_i/gen_no_trans_stable/obi_be_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/instruction_obi_i/gen_no_trans_stable/obi_atop_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/instruction_obi_i/gen_no_trans_stable/obi_addr_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_signed_mode_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_sel_subword_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_operator_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_operand_c_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_operand_b_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_operand_a_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_is_clpx_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_imm_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_en_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_dot_signed_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_dot_op_c_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_dot_op_b_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_dot_op_a_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_clpx_shift_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mult_clpx_img_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/mult_i/mulh_CS \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/mult_i/mulh_carry_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mtvec_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mtvec_mode_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mstatus_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mscratch_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mie_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_store_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_pipe_stall_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_minstret_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_load_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_ld_stall_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_jump_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_jr_stall_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_imiss_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_compressed_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_branch_taken_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/mhpmevent_branch_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mhpmcounter_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mepc_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/fifo_i/mem_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mcountinhibit_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mcounteren_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/mcause_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/jump_done_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/is_fetch_failed_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/is_compressed_id_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/int_controller_i/irq_sec_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/int_controller_i/irq_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/instr_valid_id_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/instr_rdata_id_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/imm_vec_ext_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/illegal_insn_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/illegal_c_insn_id_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/id_valid_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/aligner_i/hwlp_update_pc_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/gen_hwloop_regs/hwloop_regs_i/hwlp_start_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/prefetch_controller_i/hwlp_flush_cnt_delayed_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/prefetch_controller_i/hwlp_flush_after_resp \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/gen_hwloop_regs/hwloop_regs_i/hwlp_end_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/hwlp_end_4_id_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/gen_hwloop_regs/hwloop_regs_i/hwlp_counter_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/aligner_i/hwlp_addr_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/frm_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/prefetch_controller_i/flush_cnt_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/fflags_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/sleep_unit_i/fetch_enable_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/dscratch1_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/dscratch0_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/depc_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/debug_req_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/debug_req_entry_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/debug_mode_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/debug_fsm_cs \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/debug_force_wakeup_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/cs_registers_i/dcsr_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/data_we_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_we_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/data_type_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_type_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/data_sign_ext_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_sign_ext_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_req_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_reg_offset_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_misaligned_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/data_load_event_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/data_load_event_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/data_err_q \ + [base_path $core]/RI5CY_CORE/riscv_tracer_i/cycles \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/controller_i/ctrl_fsm_cs \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/csr_op_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/csr_access_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/sleep_unit_i/core_busy_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/CompInv_SP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/prefetch_buffer_i/prefetch_controller_i/cnt_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/load_store_unit_i/cnt_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/Cnt_DP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/BReg_DP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/branch_in_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/bmask_b_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/bmask_a_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/atop_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/alu_i/alu_div_i/AReg_DP \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_waddr_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_operands_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_op_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_lat_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_lat \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/gen_apu/apu_disp_i/apu_lat \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_flags_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/apu_en_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_vec_mode_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_operator_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_operand_c_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_operand_b_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_operand_a_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_is_subrot_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_is_clpx_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_en_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/id_stage_i/alu_clpx_shift_ex_o \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/if_stage_i/aligner_i/aligner_ready_q \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/gen_apu/apu_disp_i/addr_waiting \ + [base_path $core]/RI5CY_CORE/RI5CY_CORE/ex_stage_i/gen_apu/apu_disp_i/addr_inflight \ + } + + return [extract_netlists [subst $state_list] 1] +} + +############################## +# Get all nets from a core # +############################## + +proc get_all_core_nets {core} { + set core_path [base_path $core] + # set core_netlist_ignore_full [concat $::core_netlist_ignore [get_core_state_nets $core]] + set all_signals [extract_all_nets_recursive_filtered $core_path $::core_netlist_ignore] + # set state_signals [get_core_state_nets $core] + # set netlist_filtered {} + # foreach signal $all_signals { + # set sig_unpacked [lindex $signal 0] + # # echo $sig_unpacked + # foreach state_sig $state_signals { + # if {[string first $state_sig $sig_unpacked] == -1} { + # lappend netlist_filtered $sig_unpacked + # } + # } + # } + return $all_signals +} \ No newline at end of file diff --git a/scripts/fault_injection_config/pulp_inject_fault.tcl b/scripts/fault_injection_config/pulp_inject_fault.tcl new file mode 100644 index 00000000..f8e7c9ed --- /dev/null +++ b/scripts/fault_injection_config/pulp_inject_fault.tcl @@ -0,0 +1,51 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Author: Michael Rogenmoser (michaero@iis.ee.ethz.ch) + +transcript quietly +if {! [info exists ::env(VSIM_PATH)]} {error "Define VSIM_PATH"} +set config_base_path [file join $::env(VSIM_PATH) scripts fault_injection_config] +set script_base_path [file join $::env(VSIM_PATH) fault_injection_sim scripts] + +set verbosity 2 +set log_injections 1 +# Easy way to generate a variable seed +# set seed [clock seconds] +# Default value +set seed 12345 +set print_statistics 1 + +set inject_start_time 250856000000ps +set inject_stop_time 413000000000ps +set injection_clock "pulp_cluster_tb/cluster_i/clk_i" +set injection_clock_trigger 0 +set fault_period 250 +set rand_initial_injection_phase 0 +# max_num set to 0 means until stop_time +set max_num_fault_inject 0 +set signal_fault_duration 20ns +set register_fault_duration 0ns + +set allow_multi_bit_upset 1 +set use_bitwidth_as_weight 0 +set check_core_output_modification 0 +set check_core_next_state_modification 0 +set reg_to_sig_ratio 1 + +source [file join $config_base_path pulp_extract_nets.tcl] + +set inject_signals_netlist [] +set inject_register_netlist [] +set output_netlist [] +set next_state_netlist [] +set assertion_disable_list [] + +for {set idx 0} {$idx < 12} {incr idx} { + set inject_signals_netlist [list {*}$inject_signals_netlist {*}[get_all_core_nets $idx]] + set output_netlist [list {*}$output_netlist {*}[get_core_output_nets $idx]] +} + +source [file join $script_base_path inject_fault.tcl] + diff --git a/scripts/run_and_exit.tcl b/scripts/run_and_exit.tcl index 242b667c..a0c09228 100644 --- a/scripts/run_and_exit.tcl +++ b/scripts/run_and_exit.tcl @@ -20,4 +20,8 @@ proc run_and_exit {} { quit -code [examine -radix decimal sim:/pulp_cluster_tb/ret_val(30:0)] } +if {[info exists ::env(FAULT_INJECTION)]} { + source [file join $::env(VSIM_PATH) scripts fault_injection_config pulp_inject_fault.tcl] +} + run_and_exit diff --git a/scripts/start.tcl b/scripts/start.tcl index 69413969..a6143fe7 100644 --- a/scripts/start.tcl +++ b/scripts/start.tcl @@ -9,5 +9,9 @@ if {![info exists VSIM]} { $VSIM +permissive -suppress 3053 -suppress 8885 -suppress 12130 -lib $VSIM_PATH/work +APP=./build/test/test +notimingchecks +nospecify -t 1ps pulp_cluster_tb_optimized +permissive-off ++./build/test/test +if {[info exists ::env(FAULT_INJECTION)]} { + source [file join $::env(VSIM_PATH) scripts fault_injection_config pulp_inject_fault.tcl] +} + add log -r /* run -all From 807c8e6964d00ddb1ba992b04e0fa337b6b99f98 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 28 Feb 2024 15:20:36 +0100 Subject: [PATCH 111/207] Added TCDM scrubber (ECC manager). --- include/pulp_soc_defines.sv | 2 +- packages/pulp_cluster_package.sv | 29 +++++----- pulp-runtime | 2 +- regression-tests | 2 +- rtl/cluster_peripherals.sv | 18 ++++++ rtl/pulp_cluster.sv | 98 ++++++++++++++++++++++++++------ rtl/tcdm_banks_wrap.sv | 71 +++++++++++------------ 7 files changed, 150 insertions(+), 72 deletions(-) diff --git a/include/pulp_soc_defines.sv b/include/pulp_soc_defines.sv index 54307677..512271e5 100644 --- a/include/pulp_soc_defines.sv +++ b/include/pulp_soc_defines.sv @@ -50,4 +50,4 @@ `define NB_CORES 12 `define NB_DMAS 4 `define NB_MPERIPHS 1 -`define NB_SPERIPHS 10 +`define NB_SPERIPHS 11 diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 6ebd33e8..ef0b6899 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -126,24 +126,25 @@ package pulp_cluster_package; bit EnableRemapAddress; } pulp_cluster_cfg_t; - parameter NB_SPERIPH_PLUGS_EU = 2; + parameter int unsigned NB_SPERIPH_PLUGS_EU = 2; // number of master and slave cluster periphs - parameter NB_MPERIPHS = 1; - parameter NB_SPERIPHS = 10; + parameter int unsigned NB_MPERIPHS = 1; + parameter int unsigned NB_SPERIPHS = 11; // position of peripherals on slave port of periph interconnect - parameter SPER_EOC_ID = 0; // 0x0000 - 0x0400 - parameter SPER_TIMER_ID = 1; // 0x0400 - 0x0800 - parameter SPER_EVENT_U_ID = 2; // 0x0800 - 0x1000 - // 3 also used for Event Unit - parameter SPER_HWPE_ID = 4; // 0x1000 - 0x1400 - parameter SPER_ICACHE_CTRL = 5; // 0x1400 - 0x1800 - parameter SPER_DMA_CL_ID = 6; // 0x1800 - 0x1C00 - parameter SPER_DMA_FC_ID = 7; // 0x1C00 - 0x2000 - parameter SPER_HMR_UNIT_ID = 8; // 0x2000 - 0x2400 - parameter SPER_EXT_ID = 9; // 0x2400 - 0x2800 - parameter SPER_ERROR_ID = 10; // 0x2800 - 0x2C00 + parameter int unsigned SPER_EOC_ID = 0; // 0x0000 - 0x0400 + parameter int unsigned SPER_TIMER_ID = 1; // 0x0400 - 0x0800 + parameter int unsigned SPER_EVENT_U_ID = 2; // 0x0800 - 0x1000 + // 3 also used for Event Unit + parameter int unsigned SPER_HWPE_ID = 4; // 0x1000 - 0x1400 + parameter int unsigned SPER_ICACHE_CTRL = 5; // 0x1400 - 0x1800 + parameter int unsigned SPER_DMA_CL_ID = 6; // 0x1800 - 0x1C00 + parameter int unsigned SPER_DMA_FC_ID = 7; // 0x1C00 - 0x2000 + parameter int unsigned SPER_HMR_UNIT_ID = 8; // 0x2000 - 0x2400 + parameter int unsigned SPER_TCDM_SCRUBBER_ID = 9; // 0x2400 - 0x2800 + parameter int unsigned SPER_EXT_ID = 10; // 0x2800 - 0x2C00 + parameter int unsigned SPER_ERROR_ID = 11; // 0x2C00 - 0x3000 // The following parameters refer to the cluster AXI crossbar localparam byte_t NumAxiSubordinatePorts = 4; diff --git a/pulp-runtime b/pulp-runtime index e90f6e53..1cbf59cb 160000 --- a/pulp-runtime +++ b/pulp-runtime @@ -1 +1 @@ -Subproject commit e90f6e53279248bf64d98a8247f79f0f13545c11 +Subproject commit 1cbf59cba81b02c989a55844f6958fc13e1e6c73 diff --git a/regression-tests b/regression-tests index 6d31694a..11479f8e 160000 --- a/regression-tests +++ b/regression-tests @@ -1 +1 @@ -Subproject commit 6d31694ab395aa7d35daaaea10a7bb66811118bf +Subproject commit 11479f8ef91663f97101f3f1b3bf55708332e166 diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index 4c237590..6bd45bde 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -96,6 +96,7 @@ module cluster_peripherals XBAR_PERIPH_BUS.Master hwpe_cfg_master, XBAR_PERIPH_BUS.Master hmr_cfg_master, + XBAR_PERIPH_BUS.Master tcdm_scrubber_cfg_master, input logic [NB_CORES-1:0][3:0] hwpe_events_i, output logic hwpe_en_o, output hci_package::hci_interconnect_ctrl_t hci_ctrl_o, @@ -358,6 +359,23 @@ module cluster_peripherals assign hmr_cfg_master.be = speriph_slave[SPER_HMR_UNIT_ID].be; assign hmr_cfg_master.id = speriph_slave[SPER_HMR_UNIT_ID].id; + //******************************************************** + //******************** TCDM Scrubber ********************* + //******************************************************** + + assign speriph_slave[SPER_TCDM_SCRUBBER_ID].gnt = tcdm_scrubber_cfg_master.gnt; + assign speriph_slave[SPER_TCDM_SCRUBBER_ID].r_rdata = tcdm_scrubber_cfg_master.r_rdata; + assign speriph_slave[SPER_TCDM_SCRUBBER_ID].r_opc = tcdm_scrubber_cfg_master.r_opc; + assign speriph_slave[SPER_TCDM_SCRUBBER_ID].r_id = tcdm_scrubber_cfg_master.r_id; + assign speriph_slave[SPER_TCDM_SCRUBBER_ID].r_valid = tcdm_scrubber_cfg_master.r_valid; + + assign tcdm_scrubber_cfg_master.req = speriph_slave[SPER_TCDM_SCRUBBER_ID].req; + assign tcdm_scrubber_cfg_master.add = speriph_slave[SPER_TCDM_SCRUBBER_ID].add; + assign tcdm_scrubber_cfg_master.wen = speriph_slave[SPER_TCDM_SCRUBBER_ID].wen; + assign tcdm_scrubber_cfg_master.wdata = speriph_slave[SPER_TCDM_SCRUBBER_ID].wdata; + assign tcdm_scrubber_cfg_master.be = speriph_slave[SPER_TCDM_SCRUBBER_ID].be; + assign tcdm_scrubber_cfg_master.id = speriph_slave[SPER_TCDM_SCRUBBER_ID].id; + generate if(FEATURE_DEMUX_MAPPED == 0) begin : eu_not_demux_mapped_gen for(genvar i=0;i< NB_CORES; i++) begin diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index d40aae16..836dbd64 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -94,7 +94,11 @@ module pulp_cluster localparam int unsigned FpuOpCodeWidth = 6, localparam int unsigned FpuTypeWidth = 3, localparam int unsigned FpuInFlagsWidth = 15, - localparam int unsigned FpuOutFlagsWidth = 5 + localparam int unsigned FpuOutFlagsWidth = 5, + // Number of parity bits for ECC in memory banks + localparam int unsigned ParityWidth = 7, + // TCDM banks data width extended with parity for ECCs + localparam int unsigned ProtectedTcdmWidth = DataWidth + ParityWidth )( input logic clk_i, input logic rst_ni, @@ -353,6 +357,9 @@ XBAR_PERIPH_BUS s_periph_dma_bus[1:0](); // periph interconnect -> HMR unit XBAR_PERIPH_BUS s_periph_hmr_bus (); +// periph interconnect -> TCDM scrubber +XBAR_PERIPH_BUS s_periph_tcdm_scrubber_bus (); + // debug XBAR_TCDM_BUS s_debug_bus[Cfg.NumCores-1:0](); @@ -729,6 +736,7 @@ cluster_peripherals #( .dma_cfg_master ( s_periph_dma_bus ), .hmr_cfg_master ( s_periph_hmr_bus ), + .tcdm_scrubber_cfg_master ( s_periph_tcdm_scrubber_bus ), .dma_cl_event_i ( s_dma_cl_event ), .dma_cl_irq_i ( s_dma_cl_irq ), @@ -1282,30 +1290,88 @@ icache_hier_top #( .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ) ); -assign s_core_instr_bus.aw_atop = '0; +assign s_core_instr_bus.aw_atop = '0; + +`REG_BUS_TYPEDEF_ALL(tcdm_scrubber_reg, logic[31:0], logic[31:0], logic[3:0]) + +tcdm_scrubber_reg_req_t tcdm_scrubber_reg_req; +tcdm_scrubber_reg_rsp_t tcdm_scrubber_reg_rsp; + +periph_to_reg #( + .AW ( AddrWidth ), + .DW ( DataWidth ), + .BW ( 8 ), + .IW ( Cfg.NumCores + 1 ), + .req_t ( tcdm_scrubber_reg_req_t ), + .rsp_t ( tcdm_scrubber_reg_rsp_t ) +) i_periph_to_tcdm_scrubber ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .req_i ( s_periph_tcdm_scrubber_bus.req ), + .add_i ( s_periph_tcdm_scrubber_bus.add ), + .wen_i ( s_periph_tcdm_scrubber_bus.wen ), + .wdata_i ( s_periph_tcdm_scrubber_bus.wdata ), + .be_i ( s_periph_tcdm_scrubber_bus.be ), + .id_i ( s_periph_tcdm_scrubber_bus.id ), + .gnt_o ( s_periph_tcdm_scrubber_bus.gnt ), + .r_rdata_o ( s_periph_tcdm_scrubber_bus.r_rdata ), + .r_opc_o ( s_periph_tcdm_scrubber_bus.r_opc ), + .r_id_o ( s_periph_tcdm_scrubber_bus.r_id ), + .r_valid_o ( s_periph_tcdm_scrubber_bus.r_valid ), + .reg_req_o ( tcdm_scrubber_reg_req ), + .reg_rsp_i ( tcdm_scrubber_reg_rsp ) +); + +logic [Cfg.TcdmNumBank] bank_faults; +logic [Cfg.TcdmNumBank] ecc_single_error; +logic [Cfg.TcdmNumBank] ecc_multiple_error; +logic [Cfg.TcdmNumBank] scrubber_fix; +logic [Cfg.TcdmNumBank] scrubber_uncorrectable; +logic [Cfg.TcdmNumBank] scrubber_trigger; +logic [Cfg.TcdmNumBank][ProtectedTcdmWidth-1:0] test_write_mask_n; + +assign bank_faults = ecc_single_error | ecc_multiple_error; // TODO: check + +ecc_manager #( + .NumBanks ( Cfg.TcdmNumBank ), + .ecc_mgr_req_t ( tcdm_scrubber_reg_req_t ), + .ecc_mgr_rsp_t ( tcdm_scrubber_reg_rsp_t ) +) i_tcdm_scrubber ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .ecc_mgr_req_i ( tcdm_scrubber_reg_req ), + .ecc_mgr_rsp_o ( tcdm_scrubber_reg_rsp ), + .bank_faults_i ( bank_faults ), + .scrub_fix_i ( scrubber_fix ), + .scrub_uncorrectable_i( scrubber_uncorrectable ), + .scrub_trigger_o ( scrubber_trigger ), + .test_write_mask_no ( test_write_mask_n ) +); /* TCDM banks */ -tcdm_banks_wrap #( - .BankSize ( TcdmNumRows ), - .NbBanks ( Cfg.TcdmNumBank ), - .DataWidth ( DataWidth ), - .AddrWidth ( AddrWidth ), - .BeWidth ( BeWidth ), - .IdWidth ( TCDM_ID_WIDTH ), - .EnableEcc ( 1 ), - .EccInterco ( 0 ) // Not supported at the moment +tcdm_banks_wrap #( + .BankSize ( TcdmNumRows ), + .NbBanks ( Cfg.TcdmNumBank ), + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .BeWidth ( BeWidth ), + .IdWidth ( TCDM_ID_WIDTH ), + .EnableEcc ( 1 ), + .EccInterco ( 0 ), // Not supported at the moment + .ProtectedWidth ( ProtectedTcdmWidth ) ) tcdm_banks_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .test_mode_i ( test_mode_i ), // Scrubber - .scrub_trigger_i ( '0 ), // TODO: to be connected to a register + .scrub_trigger_i ( scrubber_trigger ), // in the cluster control unit. - .scrub_fix_o ( /* TODO: left pending */ ), - .scrub_uncorrectable_o ( /* TODO: left pending */ ), + .scrub_fix_o ( scrubber_fix ), + .scrub_uncorrectable_o ( scrubber_uncorrectable ), // ECC - .ecc_single_error_o ( /* TODO: left pending */ ), - .ecc_multile_error_o ( /* TODO: left pending */ ), + .ecc_single_error_o ( ecc_single_error ), + .ecc_multiple_error_o ( ecc_multiple_error ), + .test_write_mask_ni ( test_write_mask_n ), .tcdm_slave ( s_tcdm_bus_sram ) //PMU ?? ); diff --git a/rtl/tcdm_banks_wrap.sv b/rtl/tcdm_banks_wrap.sv index 758d2690..7619de44 100644 --- a/rtl/tcdm_banks_wrap.sv +++ b/rtl/tcdm_banks_wrap.sv @@ -17,35 +17,29 @@ */ module tcdm_banks_wrap #( - parameter int unsigned BankSize = 256, //- -> OVERRIDE - parameter int unsigned NbBanks = 1, // --> OVERRIDE - parameter int unsigned DataWidth = 32, - parameter int unsigned AddrWidth = 32, - parameter int unsigned BeWidth = DataWidth/8, - parameter int unsigned IdWidth = 1, - parameter bit EnableEcc = 1, - parameter bit EccInterco = 0 + parameter int unsigned BankSize = 256, //- -> OVERRIDE + parameter int unsigned NbBanks = 1, // --> OVERRIDE + parameter int unsigned DataWidth = 32, + parameter int unsigned AddrWidth = 32, + parameter int unsigned BeWidth = DataWidth/8, + parameter int unsigned IdWidth = 1, + parameter bit EnableEcc = 1, + parameter bit EccInterco = 0, + parameter int unsigned ProtectedWidth = DataWidth + 7 ) ( - input logic clk_i, - input logic rst_ni, - input logic test_mode_i, + input logic clk_i, + input logic rst_ni, + input logic test_mode_i, // Scrubber - input logic scrub_trigger_i, - output logic scrub_fix_o, - output logic scrub_uncorrectable_o, + input logic [NbBanks-1:0] scrub_trigger_i, + output logic [NbBanks-1:0] scrub_fix_o, + output logic [NbBanks-1:0] scrub_uncorrectable_o, // ECC - output logic ecc_single_error_o, - output logic ecc_multile_error_o, + output logic [NbBanks-1:0] ecc_single_error_o, + output logic [NbBanks-1:0] ecc_multiple_error_o, + input logic [NbBanks-1:0][ProtectedWidth-1:0] test_write_mask_ni, hci_mem_intf.slave tcdm_slave[NbBanks-1:0] ); - -logic [NbBanks-1:0] ecc_single_error, ecc_multiple_error, - scrub_fix, scrub_uncorrectable; - -assign ecc_single_error_o = |ecc_single_error; -assign ecc_multiple_error_o = |ecc_multiple_error; -assign scrub_fix_o = |scrub_fix; -assign scrub_uncorrectable_o = |scrub_uncorrectable; for(genvar i=0; i Date: Wed, 28 Feb 2024 15:49:17 +0100 Subject: [PATCH 112/207] Update submodules. --- .gitmodules | 2 ++ regression-tests | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index 2c0f881d..ea8c7efb 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,8 @@ [submodule "pulp-runtime"] path = pulp-runtime url = https://github.com/pulp-platform/pulp-runtime.git + branch = yt/tcdm-scrubber [submodule "regression-tests"] path = regression-tests url = https://github.com/pulp-platform/regression_tests.git + branch = yt/tcdm-scrubber diff --git a/regression-tests b/regression-tests index 11479f8e..460e60dc 160000 --- a/regression-tests +++ b/regression-tests @@ -1 +1 @@ -Subproject commit 11479f8ef91663f97101f3f1b3bf55708332e166 +Subproject commit 460e60dc848af5eac80993f49c5a8fdbde7479a8 From eb63d1ea7d4b217c8d5203ece5ecfee5a5193a67 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 28 Feb 2024 16:23:50 +0100 Subject: [PATCH 113/207] Remove test write mask connection. --- rtl/pulp_cluster.sv | 4 +--- rtl/tcdm_banks_wrap.sv | 3 +-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 836dbd64..ab09b0d3 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -1328,7 +1328,6 @@ logic [Cfg.TcdmNumBank] ecc_multiple_error; logic [Cfg.TcdmNumBank] scrubber_fix; logic [Cfg.TcdmNumBank] scrubber_uncorrectable; logic [Cfg.TcdmNumBank] scrubber_trigger; -logic [Cfg.TcdmNumBank][ProtectedTcdmWidth-1:0] test_write_mask_n; assign bank_faults = ecc_single_error | ecc_multiple_error; // TODO: check @@ -1345,7 +1344,7 @@ ecc_manager #( .scrub_fix_i ( scrubber_fix ), .scrub_uncorrectable_i( scrubber_uncorrectable ), .scrub_trigger_o ( scrubber_trigger ), - .test_write_mask_no ( test_write_mask_n ) + .test_write_mask_no ( /* not used */ ) ); /* TCDM banks */ @@ -1371,7 +1370,6 @@ tcdm_banks_wrap #( // ECC .ecc_single_error_o ( ecc_single_error ), .ecc_multiple_error_o ( ecc_multiple_error ), - .test_write_mask_ni ( test_write_mask_n ), .tcdm_slave ( s_tcdm_bus_sram ) //PMU ?? ); diff --git a/rtl/tcdm_banks_wrap.sv b/rtl/tcdm_banks_wrap.sv index 7619de44..333324f9 100644 --- a/rtl/tcdm_banks_wrap.sv +++ b/rtl/tcdm_banks_wrap.sv @@ -37,7 +37,6 @@ module tcdm_banks_wrap #( // ECC output logic [NbBanks-1:0] ecc_single_error_o, output logic [NbBanks-1:0] ecc_multiple_error_o, - input logic [NbBanks-1:0][ProtectedWidth-1:0] test_write_mask_ni, hci_mem_intf.slave tcdm_slave[NbBanks-1:0] ); @@ -84,7 +83,7 @@ for(genvar i=0; i Date: Wed, 28 Feb 2024 16:26:50 +0100 Subject: [PATCH 114/207] Restore gnt connection when using regular TCDM banks. --- rtl/tcdm_banks_wrap.sv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/rtl/tcdm_banks_wrap.sv b/rtl/tcdm_banks_wrap.sv index 333324f9..aa429d15 100644 --- a/rtl/tcdm_banks_wrap.sv +++ b/rtl/tcdm_banks_wrap.sv @@ -93,6 +93,9 @@ for(genvar i=0; i Date: Wed, 28 Feb 2024 17:57:27 +0100 Subject: [PATCH 115/207] Rework and polish the fault injection flow --- .gitmodules | 2 + fault_injection_sim | 2 +- regression-tests | 2 +- scripts/compile.tcl | 2339 +++++++++++++++++ .../pulp_inject_fault.tcl | 51 - .../pulp_extract_nets.tcl | 30 +- scripts/run_and_exit.tcl | 5 +- scripts/start.tcl | 5 +- 8 files changed, 2380 insertions(+), 56 deletions(-) create mode 100644 scripts/compile.tcl delete mode 100644 scripts/fault_injection_config/pulp_inject_fault.tcl rename scripts/{fault_injection_config => fault_injection_utils}/pulp_extract_nets.tcl (94%) diff --git a/.gitmodules b/.gitmodules index 5e63128c..07a9d481 100644 --- a/.gitmodules +++ b/.gitmodules @@ -8,3 +8,5 @@ [submodule "fault_injection_sim"] path = fault_injection_sim url = git@iis-git.ee.ethz.ch:michaero/fault_injection_sim.git +[submodule "fault_injection_sim/"] + url = https://github.com/pulp-platform/InjectaFault.git diff --git a/fault_injection_sim b/fault_injection_sim index 84ddcff9..ecc354f1 160000 --- a/fault_injection_sim +++ b/fault_injection_sim @@ -1 +1 @@ -Subproject commit 84ddcff943b7c2d63fb97fc9ff1864ccea398eef +Subproject commit ecc354f1bd18481a553de103bcbda26f248831ba diff --git a/regression-tests b/regression-tests index 60fc494a..28823bcc 160000 --- a/regression-tests +++ b/regression-tests @@ -1 +1 @@ -Subproject commit 60fc494a18694aada4b0a4ed6f933782570d22aa +Subproject commit 28823bcc69cfb3a994cedc5045c15844ee0a9794 diff --git a/scripts/compile.tcl b/scripts/compile.tcl new file mode 100644 index 00000000..b99d8bbc --- /dev/null +++ b/scripts/compile.tcl @@ -0,0 +1,2339 @@ +set ROOT [file normalize [file dirname [info script]]/..] +# This script was generated automatically by bender. + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/clk_rst_gen.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/rand_id_queue.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/rand_stream_mst.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/rand_synch_holdable_driver.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/rand_verif_pkg.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/signal_highlighter.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/sim_timeout.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/stream_watchdog.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/rand_synch_driver.sv" \ + "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/rand_stream_slv.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/test/tb_clk_rst_gen.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/rtl/tc_sram.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/rtl/tc_sram_impl.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/rtl/tc_clk.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/cluster_pwr_cells.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/generic_memory.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/generic_rom.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/pad_functional.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/pulp_buffer.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/pulp_pwr_cells.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/tc_pwr.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/test/tb_tc_sram.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/pulp_clock_gating_async.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/cluster_clk_cells.sv" \ + "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/pulp_clk_cells.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/binary_to_gray.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cb_filter_pkg.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cc_onehot.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_reset_ctrlr_pkg.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cf_math_pkg.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/clk_int_div.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/delta_counter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/ecc_pkg.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/edge_propagator_tx.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/exp_backoff.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/fifo_v3.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/gray_to_binary.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/isochronous_4phase_handshake.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/isochronous_spill_register.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/lfsr.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/lfsr_16bit.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/lfsr_8bit.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/lossy_valid_to_stream.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/mv_filter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/onehot_to_bin.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/plru_tree.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/popcount.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/rr_arb_tree.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/rstgen_bypass.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/serial_deglitch.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/shift_reg.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/shift_reg_gated.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/spill_register_flushable.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_demux.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_filter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_fork.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_intf.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_join_dynamic.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_mux.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_throttle.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/sub_per_hash.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/sync.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/sync_wedge.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/unread.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/read.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/addr_decode_dync.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_2phase.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_4phase.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/clk_int_div_static.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/addr_decode.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/addr_decode_napot.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/multiaddr_decode.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cb_filter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_fifo_2phase.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/clk_mux_glitch_free.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/counter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/ecc_decode.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/ecc_encode.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/edge_detect.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/lzc.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/max_counter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/rstgen.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/spill_register.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_delay.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_fifo.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_fork_dynamic.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_join.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_reset_ctrlr.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_fifo_gray.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/fall_through_register.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/id_queue.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_to_mem.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_arbiter_flushable.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_fifo_optimal_wrap.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_register.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_xbar.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_fifo_gray_clearable.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_2phase_clearable.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/mem_to_banks_detailed.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_arbiter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_omega_net.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/mem_to_banks.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/sram.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/addr_decode_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/cb_filter_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/cdc_2phase_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/cdc_2phase_clearable_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/cdc_fifo_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/cdc_fifo_clearable_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/fifo_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/graycode_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/id_queue_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/popcount_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/rr_arb_tree_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/stream_test.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/stream_register_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/stream_to_mem_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/sub_per_hash_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/isochronous_crossing_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/stream_omega_net_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/stream_xbar_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/clk_int_div_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/clk_int_div_static_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/clk_mux_glitch_free_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/lossy_valid_to_stream_tb.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/clock_divider_counter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/clk_div.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/find_first_one.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/generic_LFSR_8bit.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/generic_fifo.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/prioarbiter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/pulp_sync.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/pulp_sync_wedge.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/rrarbiter.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/clock_divider.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/fifo_v2.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/fifo_v1.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/edge_propagator_ack.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/edge_propagator.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/edge_propagator_rx.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/defs_div_sqrt_mvp.sv" \ + "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/iteration_div_sqrt_mvp.sv" \ + "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/control_mvp.sv" \ + "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/norm_div_sqrt_mvp.sv" \ + "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/preprocess_mvp.sv" \ + "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/nrbd_nrsc_mvp.sv" \ + "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/div_sqrt_top_mvp.sv" \ + "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/div_sqrt_mvp_wrapper.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_pkg.sv" \ + "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_intf.sv" \ + "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_err_slv.sv" \ + "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_regs.sv" \ + "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_cdc.sv" \ + "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_demux.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_test.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/test/tb_apb_regs.sv" \ + "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/test/tb_apb_cdc.sv" \ + "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/test/tb_apb_demux.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_pkg.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_intf.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_atop_filter.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_burst_splitter.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_bus_compare.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_cdc_dst.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_cdc_src.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_cut.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_delayer.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_demux_simple.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_dw_downsizer.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_dw_upsizer.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_fifo.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_id_remap.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_id_prepend.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_isolate.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_join.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_demux.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_dw_converter.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_from_mem.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_join.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_lfsr.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_mailbox.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_mux.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_regs.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_to_apb.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_to_axi.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_modify_address.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_mux.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_rw_join.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_rw_split.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_serializer.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_slave_compare.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_throttle.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_to_detailed_mem.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_cdc.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_demux.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_err_slv.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_dw_converter.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_from_mem.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_id_serialize.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lfsr.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_multicut.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_to_axi_lite.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_to_mem.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_iw_converter.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_xbar.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_xbar.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_to_mem_banked.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_to_mem_interleaved.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_to_mem_split.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_xp.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_chan_compare.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_dumper.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_sim_mem.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_test.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_dw_pkg.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_xbar_pkg.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_addr_test.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_atop_filter.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_bus_compare.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_cdc.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_delayer.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_dw_downsizer.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_dw_upsizer.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_fifo.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_isolate.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_lite_dw_converter.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_lite_mailbox.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_lite_regs.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_iw_converter.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_lite_to_apb.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_lite_to_axi.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_lite_xbar.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_modify_address.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_serializer.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_sim_mem.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_slave_compare.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_to_axi_lite.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_to_mem_banked.sv" \ + "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_xbar.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/addr_dec_resp_mux.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/amo_shim.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/variable_latency_interconnect/addr_decoder.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/xbar.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/variable_latency_interconnect/simplex_xbar.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/clos_net.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/bfly_net.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/variable_latency_interconnect/full_duplex_xbar.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/tcdm_interconnect.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/variable_latency_interconnect/variable_latency_bfly_net.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/variable_latency_interconnect/variable_latency_interconnect.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/FanInPrimitive_Req.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/ArbitrationTree.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/MUX2_REQ.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/AddressDecoder_Resp.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/TestAndSet.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/RequestBlock2CH.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/RequestBlock1CH.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/FanInPrimitive_Resp.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/ResponseTree.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/ResponseBlock.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/AddressDecoder_Req.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/XBAR_TCDM.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/XBAR_TCDM_WRAPPER.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/TCDM_PIPE_REQ.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/TCDM_PIPE_RESP.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/grant_mask.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/priority_Flag_Req.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/AddressDecoder_PE_Req.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/AddressDecoder_Resp_PE.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/ArbitrationTree_PE.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/FanInPrimitive_Req_PE.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/RR_Flag_Req_PE.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/MUX2_REQ_PE.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/FanInPrimitive_PE_Resp.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/RequestBlock1CH_PE.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/RequestBlock2CH_PE.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/ResponseBlock_PE.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/ResponseTree_PE.sv" \ + "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/XBAR_PE.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_pkg.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_cast_multi.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_classifier.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ctrl.v" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ff1.v" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_pack_single.v" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_round_single.v" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_special.v" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_srt_single.v" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_top.v" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_dp.v" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_frbus.v" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_src_type.v" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_divsqrt_th_32.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_divsqrt_multi.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_fma.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_fma_multi.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_sdotp_multi.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_sdotp_multi_wrapper.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_noncomp.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_opgroup_block.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_opgroup_fmt_slice.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_opgroup_multifmt_slice.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_rounding.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/lfsr_sr.sv" \ + "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_top.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/hwpe_stream_interfaces.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/hwpe_stream_package.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_assign.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_buffer.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_demux_static.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_deserialize.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_fence.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_merge.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_mux_static.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_serialize.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_split.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_ctrl.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_scm.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_addressgen.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_addressgen_v2.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_addressgen_v3.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_sink_realign.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_source_realign.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_strbgen.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_streamer_queue.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_assign.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_mux.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_mux_static.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_reorder.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_reorder_static.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_earlystall.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_earlystall_sidech.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_scm_test_wrap.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_sidech.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_fifo_load_sidech.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_passthrough.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_source.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_fifo.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_fifo_load.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_fifo_store.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_sink.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/verif/hwpe_stream_traffic_gen.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/verif/hwpe_stream_traffic_recv.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/verif/tb_fifo.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/l2_tcdm_demux.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/lint_2_apb.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/lint_2_axi.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/axi_2_lint/axi64_2_lint32.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/axi_2_lint/axi_read_ctrl.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/axi_2_lint/axi_write_ctrl.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/axi_2_lint/lint64_to_32.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/AddressDecoder_Req_L2.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/AddressDecoder_Resp_L2.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/ArbitrationTree_L2.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/FanInPrimitive_Req_L2.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/FanInPrimitive_Resp_L2.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/MUX2_REQ_L2.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/RequestBlock_L2_1CH.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/RequestBlock_L2_2CH.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/ResponseBlock_L2.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/ResponseTree_L2.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/RR_Flag_Req_L2.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/XBAR_L2.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/AddressDecoder_Req_BRIDGE.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/AddressDecoder_Resp_BRIDGE.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/ArbitrationTree_BRIDGE.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/FanInPrimitive_Req_BRIDGE.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/FanInPrimitive_Resp_BRIDGE.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/MUX2_REQ_BRIDGE.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/RequestBlock1CH_BRIDGE.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/RequestBlock2CH_BRIDGE.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/ResponseBlock_BRIDGE.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/ResponseTree_BRIDGE.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/RR_Flag_Req_BRIDGE.sv" \ + "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/XBAR_BRIDGE.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_single_slice.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_ar_buffer.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_aw_buffer.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_b_buffer.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_r_buffer.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_slice.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_w_buffer.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_slice_wrap.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/bhv" \ + "+incdir+$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/include" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/include/cv32e40p_apu_core_pkg.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/include/cv32e40p_pkg.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_pulp_clock_gate.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_alu.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_alu_div.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_aligner.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_compressed_decoder.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_controller.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_shadow_controller.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_cs_registers.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_decoder.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_int_controller.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_ex_stage.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_fifo.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_hwloop_regs.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_id_stage.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_if_stage.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_load_store_unit.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_mult.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_prefetch_buffer.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_prefetch_controller.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_obi_interface.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_core.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_apu_disp.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_popcnt.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_ff_one.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_sleep_unit.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/bhv" \ + "+incdir+$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/include" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_register_file_ff.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+CV32E40P_TRACE_EXECUTION \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/bhv" \ + "+incdir+$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/include" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/bhv/include/cv32e40p_tracer_pkg.sv" \ + "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/bhv/cv32e40p_wrapper.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/common/hci_package.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/common/hci_interfaces.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_assign.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_cmd_queue.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_fifo.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_memmap_demux_interl.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_memmap_filter.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_mux_dynamic.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_mux_static.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_mux_ooo.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_r_valid_filter.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_r_user_filter.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_source.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_split.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_log_interconnect.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_log_interconnect_l2.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_new_log_interconnect.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_shallow_interconnect.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/mem/hci_mem_assign.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_hwpe_reorder.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_sink.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_hwpe_interconnect.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/hci_interconnect.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl" \ + "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_interfaces.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_package.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_regfile_ff.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_regfile_latch.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_seq_mult.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_uloop.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_regfile_latch_test_wrap.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_regfile.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_slave.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/Req_Arb_Node_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/Resp_Arb_Node_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/lint_mux.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/DistributedArbitrationNetwork_Req_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/DistributedArbitrationNetwork_Resp_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/RoutingBlock_Req_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/RoutingBlock_2ch_Req_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/RoutingBlock_Resp_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/icache_intc.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/include" \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_intf.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/vendor/lowrisc_opentitan/src/prim_subreg_arb.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/vendor/lowrisc_opentitan/src/prim_subreg_ext.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/apb_to_reg.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/axi_to_reg.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/periph_to_reg.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_cdc.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_demux.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_err_slv.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_filter_empty_writes.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_mux.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_to_apb.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_to_mem.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_uniform.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_to_tlul.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/vendor/lowrisc_opentitan/src/prim_subreg_shadow.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/vendor/lowrisc_opentitan/src/prim_subreg.sv" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/axi_lite_to_reg.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/include" \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_test.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1r_1w_all.sv" \ + "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1r_1w_be.sv" \ + "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1r_1w.sv" \ + "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1r_1w_1row.sv" \ + "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1r_1w_raw.sv" \ + "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1w_multi_port_read.sv" \ + "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1w_64b_multi_port_read_32b.sv" \ + "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1w_64b_1r_32b.sv" \ + "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_2r_1w_asymm.sv" \ + "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_2r_1w_asymm_test_wrap.sv" \ + "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_2r_2w.sv" \ + "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_3r_2w.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_busy_unit.sv" \ + "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_rd_channel.sv" \ + "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem.sv" \ + "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_tcdm_rd_if.sv" \ + "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_tcdm_synch.sv" \ + "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_tcdm_unit.sv" \ + "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_tcdm_wr_if.sv" \ + "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_trans_unit.sv" \ + "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_wr_channel.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/axi2per-70eb6ef4b0b0efca/axi2per_req_channel.sv" \ + "$ROOT/.bender/git/checkouts/axi2per-70eb6ef4b0b0efca/axi2per_res_channel.sv" \ + "$ROOT/.bender/git/checkouts/axi2per-70eb6ef4b0b0efca/axi2per.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/cluster_control_unit/cluster_control_unit.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/include" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/HW_barrier_logic.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/event_unit_arbiter.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/event_unit_mux.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/event_unit_sm.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/interrupt_mask.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/HW_barrier.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/event_unit_input.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/event_unit.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/icache_ctrl_unit/icache_ctrl_unit.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/icache_ctrl_unit/mp_icache_ctrl_unit.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/icache_ctrl_unit/mp_pf_icache_ctrl_unit.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/icache_ctrl_unit/new_icache_ctrl_unit.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/icache_ctrl_unit/pri_icache_ctrl_unit.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/icache_ctrl_unit/sp_icache_ctrl_unit.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/mmu_config_unit/mmu_config_unit.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/perf_counters_unit/perf_counters_unit.sv" \ + "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/tcdm_pipe_unit/tcdm_pipe_unit.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl" \ + "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/event_unit_core.sv" \ + "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/hw_barrier_unit.sv" \ + "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/hw_dispatch.sv" \ + "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/hw_mutex_unit.sv" \ + "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/interc_sw_evt_trig.sv" \ + "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/periph_FIFO_id.sv" \ + "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/soc_periph_fifo.sv" \ + "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/event_unit_interface_mux.sv" \ + "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/event_unit_top.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/CTRL_UNIT/hier_icache_ctrl_unit.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/ram_ws_rs_data_scm.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/ram_ws_rs_tag_scm.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/RefillTracker_4.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/REP_buffer_4.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1_CACHE/pri_icache_controller.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1_CACHE/refill_arbiter.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/CTRL_UNIT/hier_icache_ctrl_unit_wrap.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/AXI4_REFILL_Resp_Deserializer.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/share_icache_controller.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1_CACHE/register_file_1w_multi_port_read_test_wrap.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/share_icache.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1_CACHE/pri_icache.sv" \ + "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/TOP/icache_hier_top.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_register_file_latch.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_register_file_ff.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_register_file_fpga.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+RVFI=true \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl" \ + "+incdir+$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/vendor/lowrisc_ip/ip/prim/rtl" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_pkg.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_register_file_ff.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_alu.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_compressed_decoder.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_controller.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_counter.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_csr.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_decoder.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_fetch_fifo.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_load_store_unit.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_multdiv_fast.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_multdiv_slow.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_pmp.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_tracer_pkg.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_wb_stage.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_cs_registers.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_ex_block.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_id_stage.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_prefetch_buffer.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_tracer.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_if_stage.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_core.sv" \ + "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_core_tracing.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/idma_transfer_id_gen.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_pkg.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_stream_fifo.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_buffer.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_error_handler.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_channel_coupler.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_axi_transport_layer.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_axi_lite_transport_layer.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_obi_transport_layer.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_legalizer.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_backend.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/legacy/axi_dma_backend.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/legacy/midends/idma_2D_midend.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/midends/idma_nd_midend.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_pkg.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_top.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/register_32bit_2d/idma_reg32_2d_frontend.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/register_64bit/idma_reg64_frontend_reg_pkg.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/register_64bit/idma_reg64_frontend_reg_top.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/register_64bit/idma_reg64_frontend.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/desc64/idma_desc64_reg_pkg.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/desc64/idma_desc64_reg_top.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/desc64/idma_desc64_shared_counter.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/desc64/idma_desc64_reg_wrapper.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/desc64/idma_desc64_top.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_SIMULATION \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ + "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/idma_intf.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/idma_tb_per2axi.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/idma_obi_asserter.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/idma_test.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/idma_obi2axi_bridge.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/tb_idma_backend.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/tb_idma_lite_backend.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/tb_idma_obi_backend.sv" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/tb_idma_nd_backend.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/frontends/tb_idma_desc64_top.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/include" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/misc/mchan_arbiter.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/misc/mchan_arb_primitive.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/misc/mchan_rr_flag_req.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/ctrl_fsm.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/ctrl_if.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/ctrl_unit.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/synch_unit.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/trans_allocator.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/trans_queue.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/trans_arbiter_wrap.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/trans_unpack.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/twd_trans_queue.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/twd_trans_splitter.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_ar_buffer.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_aw_buffer.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_b_buffer.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_buffer.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_opc_buf.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_r_buffer.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_rx_if.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_tid_gen.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_tx_if.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_unit.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_w_buffer.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/tcdm_unit/tcdm_cmd_unpack.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/tcdm_unit/tcdm_rx_if.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/tcdm_unit/tcdm_synch.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/tcdm_unit/tcdm_tx_if.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/tcdm_unit/tcdm_unit.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/trans_unit/trans_aligner.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/trans_unit/trans_buffers.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/trans_unit/trans_unit.sv" \ + "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/top/mchan.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/per2axi-60b4d6ef3b53fc48/src/per2axi_busy_unit.sv" \ + "$ROOT/.bender/git/checkouts/per2axi-60b4d6ef3b53fc48/src/per2axi_req_channel.sv" \ + "$ROOT/.bender/git/checkouts/per2axi-60b4d6ef3b53fc48/src/per2axi_res_channel.sv" \ + "$ROOT/.bender/git/checkouts/per2axi-60b4d6ef3b53fc48/src/per2axi.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_ctrl.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_scheduler.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_castin.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_castout.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_streamer.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_x_buffer.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_w_buffer.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_z_buffer.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_fma.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_noncomp.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_ce.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_row.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_engine.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_top.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_wrap.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ODRG_unit/odrg_manager_reg_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ecc_wrap/ecc_manager_reg_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/pulpissimo_tcls/tcls_manager_reg_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_13_8_cor.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_13_8_dec.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_13_8_enc.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_22_16_cor.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_22_16_dec.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_22_16_enc.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_39_32_cor.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_39_32_dec.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_39_32_enc.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_72_64_cor.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_72_64_dec.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_72_64_enc.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ODRG_unit/triple_core_barrier.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/hsiao_ecc/hsiao_ecc_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/hsiao_ecc/hsiao_ecc_enc.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/hsiao_ecc/hsiao_ecc_dec.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/hsiao_ecc/hsiao_ecc_cor.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/TMR_voter.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/TMR_word_voter.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/resp_suppress.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ODRG_unit/odrg_manager_reg_top.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ecc_wrap/ecc_manager_reg_top.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/pulpissimo_tcls/tcls_manager_reg_top.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ecc_wrap/ecc_scrubber.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ecc_concat_32_64.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_13_8_cor.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_13_8_dec.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_13_8_enc.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_22_16_cor.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_22_16_dec.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_22_16_enc.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_39_32_cor.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_39_32_dec.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_39_32_enc.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_72_64_cor.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_72_64_dec.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_72_64_enc.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/TMR_voter_detect.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/bitwise_TMR_voter.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ecc_wrap/ecc_manager.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ecc_wrap/ecc_sram_wrap.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ODRG_unit" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ODRG_unit/ODRG_unit.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/pulpissimo_tcls" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/pulpissimo_tcls/TCLS_unit.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_ecc_scrubber.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_ecc_secded.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_ecc_sram.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_tmr_voter.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_tmr_voter_detect.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_tmr_word_voter.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_bitwise_tmr_voter.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/rapid_recovery_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/recovery_csr.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/recovery_pc.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/recovery_rf.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/rapid_recovery_unit.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/DMR_checker.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/DMR_CSR_checker.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/DMR_address_generator.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_rapid_recovery_ctrl.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_registers_reg_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_core_regs_reg_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_dmr_regs_reg_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_tmr_regs_reg_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_registers_reg_top.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_core_regs_reg_top.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_dmr_regs_reg_top.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_dmr_ctrl.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_tmr_regs_reg_top.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_tmr_ctrl.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/HMR_wrap.sv" \ + "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_unit.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include/apu_core_package.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include/riscv_defines.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include/riscv_tracer_defines.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/macload_controller.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/mixed_precision_controller.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_alu.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_alu_basic.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_alu_div.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_compressed_decoder.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_controller.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_cs_registers.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_decoder.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_int_controller.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_ex_stage.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_hwloop_controller.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_hwloop_regs.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/register_file_test_wrap.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_id_stage.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_if_stage.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_load_store_unit.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_mult.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_prefetch_buffer.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_prefetch_L0_buffer.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_core.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_apu_disp.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_fetch_fifo.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_L0_buffer.sv" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_pmp.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_register_file.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include" \ + "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_tracer.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "$ROOT/.bender/git/checkouts/timer_unit-beb608985450c057/rtl/timer_unit_counter.sv" \ + "$ROOT/.bender/git/checkouts/timer_unit-beb608985450c057/rtl/timer_unit_counter_presc.sv" \ + "$ROOT/.bender/git/checkouts/timer_unit-beb608985450c057/rtl/apb_timer_unit.sv" \ + "$ROOT/.bender/git/checkouts/timer_unit-beb608985450c057/rtl/timer_unit.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/packages/pulp_cluster_package.sv" \ + "$ROOT/rtl/axi2mem_wrap.sv" \ + "$ROOT/rtl/axi2per_wrap.sv" \ + "$ROOT/rtl/cluster_bus_wrap.sv" \ + "$ROOT/rtl/cluster_clock_gate.sv" \ + "$ROOT/rtl/cluster_event_map.sv" \ + "$ROOT/rtl/cluster_timer_wrap.sv" \ + "$ROOT/rtl/obi_pulp_adapter.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/rtl/mchan_wrap.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/rtl/hwpe_subsystem.sv" \ + "$ROOT/rtl/instr_width_converter.sv" \ + "$ROOT/rtl/per2axi_wrap.sv" \ + "$ROOT/rtl/periph_demux.sv" \ + "$ROOT/rtl/per_demux_wrap.sv" \ + "$ROOT/rtl/periph_FIFO.sv" \ + "$ROOT/rtl/tcdm_banks_wrap.sv" \ + "$ROOT/rtl/xbar_pe_wrap.sv" \ + "$ROOT/rtl/cluster_interconnect_wrap.sv" \ + "$ROOT/rtl/cluster_peripherals.sv" \ + "$ROOT/rtl/data_periph_demux.sv" \ + "$ROOT/rtl/core_demux_wrap.sv" \ + "$ROOT/rtl/core_region.sv" \ + "$ROOT/rtl/pulp_cluster.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/tb/mock_uart.sv" \ + "$ROOT/tb/axi2apb_64_32.sv" \ + "$ROOT/tb/mock_uart_axi.sv" \ + "$ROOT/tb/pulp_cluster_tb.sv" \ +}]} {return 1} + +if {[catch { vlog -incr -sv \ + -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ + +define+TARGET_CLUSTER_STANDALONE \ + +define+TARGET_CV32E40P_USE_FF_REGFILE \ + +define+TARGET_MCHAN \ + +define+TARGET_RTL \ + +define+TARGET_SCM_USE_FPGA_SCM \ + +define+TARGET_SIMULATION \ + +define+TARGET_TEST \ + +define+TARGET_VSIM \ + +define+FEATURE_ICACHE_STAT \ + +define+PRIVATE_ICACHE \ + +define+HIERARCHY_ICACHE_32BIT \ + +define+ICAHE_USE_FF \ + +define+NO_FPU \ + +define+TRACE_EXECUTION \ + +define+CLUSTER_ALIAS \ + +define+USE_PULP_PARAMETERS \ + "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ + "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ + "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ + "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ + "+incdir+$ROOT/include" \ + "$ROOT/include/pulp_interfaces.sv" \ +}]} {return 1} + + +vlog "/scratch2/rtedeschi/astral/scrubber/tb/dpi/elfloader.cpp" -ccflags "-std=c++11" diff --git a/scripts/fault_injection_config/pulp_inject_fault.tcl b/scripts/fault_injection_config/pulp_inject_fault.tcl deleted file mode 100644 index f8e7c9ed..00000000 --- a/scripts/fault_injection_config/pulp_inject_fault.tcl +++ /dev/null @@ -1,51 +0,0 @@ -# Copyright 2023 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Author: Michael Rogenmoser (michaero@iis.ee.ethz.ch) - -transcript quietly -if {! [info exists ::env(VSIM_PATH)]} {error "Define VSIM_PATH"} -set config_base_path [file join $::env(VSIM_PATH) scripts fault_injection_config] -set script_base_path [file join $::env(VSIM_PATH) fault_injection_sim scripts] - -set verbosity 2 -set log_injections 1 -# Easy way to generate a variable seed -# set seed [clock seconds] -# Default value -set seed 12345 -set print_statistics 1 - -set inject_start_time 250856000000ps -set inject_stop_time 413000000000ps -set injection_clock "pulp_cluster_tb/cluster_i/clk_i" -set injection_clock_trigger 0 -set fault_period 250 -set rand_initial_injection_phase 0 -# max_num set to 0 means until stop_time -set max_num_fault_inject 0 -set signal_fault_duration 20ns -set register_fault_duration 0ns - -set allow_multi_bit_upset 1 -set use_bitwidth_as_weight 0 -set check_core_output_modification 0 -set check_core_next_state_modification 0 -set reg_to_sig_ratio 1 - -source [file join $config_base_path pulp_extract_nets.tcl] - -set inject_signals_netlist [] -set inject_register_netlist [] -set output_netlist [] -set next_state_netlist [] -set assertion_disable_list [] - -for {set idx 0} {$idx < 12} {incr idx} { - set inject_signals_netlist [list {*}$inject_signals_netlist {*}[get_all_core_nets $idx]] - set output_netlist [list {*}$output_netlist {*}[get_core_output_nets $idx]] -} - -source [file join $script_base_path inject_fault.tcl] - diff --git a/scripts/fault_injection_config/pulp_extract_nets.tcl b/scripts/fault_injection_utils/pulp_extract_nets.tcl similarity index 94% rename from scripts/fault_injection_config/pulp_extract_nets.tcl rename to scripts/fault_injection_utils/pulp_extract_nets.tcl index 72e79cd6..5e375e72 100644 --- a/scripts/fault_injection_config/pulp_extract_nets.tcl +++ b/scripts/fault_injection_utils/pulp_extract_nets.tcl @@ -243,4 +243,32 @@ proc get_all_core_nets {core} { # } # } return $all_signals -} \ No newline at end of file +} + +################## +# Memory signals # +################## + +# <------ banks ------> +# b1 b2 b3 b4 +# +----+----+----+----+ ^ +# | | | | | 3 | +# +----+----+----+----+ | +# | | | | | 2 | +# +----+----+----+----+ | words +# | | | | | 1 | +# +----+----+----+----+ | +# | | | | | 0 | +# +----+----+----+----+ v + +# == Path to a word in sram signal in tc_sram == +proc get_memory_word {bank word} {return "/pulp_cluster_tb/cluster_i/tcdm_banks_i/banks_gen\[$bank\]/gen_ecc_banks/gen_ecc_banks_only/i_ecc_bank/i_bank/sram($word)"} + +proc get_memory_slice {bank_range word_range} { + set mem_slice [list] + for {set i [lindex $bank_range 0]} {$i < [lindex $bank_range end]} {incr i} { + for {set j [lindex $word_range 0]} {$j < [lindex $word_range end]} {incr j} { + lappend mem_slice [get_memory_word $i $j]} + } + return $mem_slice +} diff --git a/scripts/run_and_exit.tcl b/scripts/run_and_exit.tcl index a0c09228..5443a739 100644 --- a/scripts/run_and_exit.tcl +++ b/scripts/run_and_exit.tcl @@ -21,7 +21,10 @@ proc run_and_exit {} { } if {[info exists ::env(FAULT_INJECTION)]} { - source [file join $::env(VSIM_PATH) scripts fault_injection_config pulp_inject_fault.tcl] + if {![info exists ::env(FAULT_INJECTION_SCRIPT)]} { + error "Error: Missing FAULT_INJECTION_SCRIPT to source!" + } + source $::env(FAULT_INJECTION_SCRIPT) } run_and_exit diff --git a/scripts/start.tcl b/scripts/start.tcl index a6143fe7..e1792a42 100644 --- a/scripts/start.tcl +++ b/scripts/start.tcl @@ -10,7 +10,10 @@ if {![info exists VSIM]} { $VSIM +permissive -suppress 3053 -suppress 8885 -suppress 12130 -lib $VSIM_PATH/work +APP=./build/test/test +notimingchecks +nospecify -t 1ps pulp_cluster_tb_optimized +permissive-off ++./build/test/test if {[info exists ::env(FAULT_INJECTION)]} { - source [file join $::env(VSIM_PATH) scripts fault_injection_config pulp_inject_fault.tcl] + if {![info exists ::env(FAULT_INJECTION_SCRIPT)]} { + error "Error: Missing FAULT_INJECTION_SCRIPT to source!" + } + source $::env(FAULT_INJECTION_SCRIPT) } add log -r /* From 54be025defe308c640b5a757331ebf8075922f65 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Wed, 28 Feb 2024 18:08:01 +0100 Subject: [PATCH 116/207] Fix submodules --- .gitmodules | 7 +++---- fault_injection_sim | 2 +- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/.gitmodules b/.gitmodules index 07a9d481..2765f2ae 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,12 +1,11 @@ [submodule "pulp-runtime"] path = pulp-runtime url = https://github.com/pulp-platform/pulp-runtime.git - branch = astral + branch = astral [submodule "regression-tests"] path = regression-tests url = https://github.com/pulp-platform/regression_tests.git + branch = astral [submodule "fault_injection_sim"] path = fault_injection_sim - url = git@iis-git.ee.ethz.ch:michaero/fault_injection_sim.git -[submodule "fault_injection_sim/"] - url = https://github.com/pulp-platform/InjectaFault.git + url = https://github.com/pulp-platform/InjectaFault.git \ No newline at end of file diff --git a/fault_injection_sim b/fault_injection_sim index ecc354f1..84ddcff9 160000 --- a/fault_injection_sim +++ b/fault_injection_sim @@ -1 +1 @@ -Subproject commit ecc354f1bd18481a553de103bcbda26f248831ba +Subproject commit 84ddcff943b7c2d63fb97fc9ff1864ccea398eef From a39aaafed5896098c13ba3345403e1795d82474c Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 28 Feb 2024 21:37:03 +0100 Subject: [PATCH 117/207] Clarify that slave periph EXT and ERROR IDs both redirect to errors. --- packages/pulp_cluster_package.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index ef0b6899..0a73b01d 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -143,8 +143,8 @@ package pulp_cluster_package; parameter int unsigned SPER_DMA_FC_ID = 7; // 0x1C00 - 0x2000 parameter int unsigned SPER_HMR_UNIT_ID = 8; // 0x2000 - 0x2400 parameter int unsigned SPER_TCDM_SCRUBBER_ID = 9; // 0x2400 - 0x2800 - parameter int unsigned SPER_EXT_ID = 10; // 0x2800 - 0x2C00 - parameter int unsigned SPER_ERROR_ID = 11; // 0x2C00 - 0x3000 + parameter int unsigned SPER_EXT_ID = 10; // -> unmapped, directed to error + parameter int unsigned SPER_ERROR_ID = 11; // -> unmapped, directed to error // The following parameters refer to the cluster AXI crossbar localparam byte_t NumAxiSubordinatePorts = 4; From d6cda0879ea8e59a8e27e3adfea1c2ad035b5a6a Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 28 Feb 2024 21:44:09 +0100 Subject: [PATCH 118/207] Update submodules. --- .gitmodules | 4 ++-- pulp-runtime | 2 +- regression-tests | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.gitmodules b/.gitmodules index ea8c7efb..1e861dcf 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,8 +1,8 @@ [submodule "pulp-runtime"] path = pulp-runtime url = https://github.com/pulp-platform/pulp-runtime.git - branch = yt/tcdm-scrubber + branch = astral [submodule "regression-tests"] path = regression-tests url = https://github.com/pulp-platform/regression_tests.git - branch = yt/tcdm-scrubber + branch = astral diff --git a/pulp-runtime b/pulp-runtime index 1cbf59cb..7c791d05 160000 --- a/pulp-runtime +++ b/pulp-runtime @@ -1 +1 @@ -Subproject commit 1cbf59cba81b02c989a55844f6958fc13e1e6c73 +Subproject commit 7c791d0568e4cb8c8d64b1cf59f5822c0f910145 diff --git a/regression-tests b/regression-tests index 460e60dc..60fc494a 160000 --- a/regression-tests +++ b/regression-tests @@ -1 +1 @@ -Subproject commit 460e60dc848af5eac80993f49c5a8fdbde7479a8 +Subproject commit 60fc494a18694aada4b0a4ed6f933782570d22aa From 80fabc2c13fab91420bfb4fc1af9726126da0bab Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 29 Feb 2024 17:26:32 +0100 Subject: [PATCH 119/207] Bump dependencies to avoid using SSH links. --- Bender.lock | 19 ++++++++++--------- Bender.yml | 10 +++++----- 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/Bender.lock b/Bender.lock index 01e1fbae..5e1166de 100644 --- a/Bender.lock +++ b/Bender.lock @@ -16,7 +16,7 @@ packages: - common_verification - tech_cells_generic axi2mem: - revision: 6973e0434d26ba578cdb4aa69c26c1facd1a3f15 + revision: b0e963433b2f6a61262b1448031e74eaec57c203 version: null source: Git: https://github.com/pulp-platform/axi2mem.git @@ -24,8 +24,8 @@ packages: - axi_slice - common_cells axi2per: - revision: a99ef2fac9f3b087671109a27c766f25e8e0f115 - version: 1.0.1 + revision: 4932bd2b88a1c7b5f0bf95411fc512905ed32439 + version: null source: Git: https://github.com/pulp-platform/axi2per.git dependencies: @@ -34,7 +34,7 @@ packages: revision: a4f72bc21ac4d7da631e8309d9f8d0c34b735c23 version: 1.1.4 source: - Git: git@github.com:pulp-platform/axi_slice.git + Git: https://github.com/pulp-platform/axi_slice.git dependencies: - common_cells cluster_interconnect: @@ -106,12 +106,13 @@ packages: - hwpe-stream - l2_tcdm_hybrid_interco hier-icache: - revision: 8e77bdc828c717299ac8572a1f9bf10144382105 + revision: 2886cb2a46cea3e2bd2d979b505d88fadfbe150c version: null source: Git: https://github.com/pulp-platform/hier-icache.git dependencies: - axi + - axi_slice - common_cells - icache-intc - scm @@ -141,7 +142,7 @@ packages: revision: 663c3b6d3c2bf63ff25cda46f33c799c647b3985 version: 1.0.1 source: - Git: git@github.com:pulp-platform/icache-intc.git + Git: https://github.com/pulp-platform/icache-intc.git dependencies: [] idma: revision: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 @@ -167,8 +168,8 @@ packages: dependencies: - common_cells per2axi: - revision: 892fcad60b6374fe558cbde76f4a529d473ba5ca - version: 1.0.4 + revision: 95bf23119b47fc171d9ed3734c431f71cffd9350 + version: null source: Git: https://github.com/pulp-platform/per2axi.git dependencies: @@ -210,7 +211,7 @@ packages: revision: c760db14dbd6cc3ec3b8ae8274df2eac7225bcac version: null source: - Git: git@github.com:AlSaqr-platform/riscv_nn.git + Git: https://github.com/AlSaqr-platform/riscv_nn.git dependencies: - fpnew - tech_cells_generic diff --git a/Bender.yml b/Bender.yml index 3f83c9d6..002af572 100644 --- a/Bender.yml +++ b/Bender.yml @@ -12,20 +12,20 @@ package: - "Michael Rogenmoser " dependencies: - axi2mem: { git: "https://github.com/pulp-platform/axi2mem.git", rev: "6973e0434d26ba578cdb4aa69c26c1facd1a3f15" } # deprecated, replace with axi_to_mem in axi repo - axi2per: { git: "https://github.com/pulp-platform/axi2per.git", version: 1.0.1 } - per2axi: { git: "https://github.com/pulp-platform/per2axi.git", version: 1.0.4 } + axi2mem: { git: "https://github.com/pulp-platform/axi2mem.git", rev: "b0e963433b2f6a61262b1448031e74eaec57c203" } # branch: yt/astral + axi2per: { git: "https://github.com/pulp-platform/axi2per.git", rev: "4932bd2b88a1c7b5f0bf95411fc512905ed32439" } # branch: yt/astral + per2axi: { git: "https://github.com/pulp-platform/per2axi.git", rev: "95bf23119b47fc171d9ed3734c431f71cffd9350" } # branch: yt/astral cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master - hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "8e77bdc828c717299ac8572a1f9bf10144382105" } # branch: astral + hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "2886cb2a46cea3e2bd2d979b505d88fadfbe150c" } # branch: astral cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: c9defcfb4f4e8733383b28a451c430783c2febbd } # branch: astral axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } - riscv: { git: "git@github.com:AlSaqr-platform/riscv_nn.git", rev: astral-v1.0 } + riscv: { git: "https://github.com/AlSaqr-platform/riscv_nn.git", rev: astral-v1.0 } cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating From 1091cf790c25640b782926704741fe9b0212e731 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Wed, 6 Mar 2024 17:00:35 +0100 Subject: [PATCH 120/207] Update submodules --- pulp-runtime | 2 +- regression-tests | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pulp-runtime b/pulp-runtime index 7c791d05..8b508dca 160000 --- a/pulp-runtime +++ b/pulp-runtime @@ -1 +1 @@ -Subproject commit 7c791d0568e4cb8c8d64b1cf59f5822c0f910145 +Subproject commit 8b508dca78ee778e5def6ee6a3529b9877358bb7 diff --git a/regression-tests b/regression-tests index 28823bcc..1563f088 160000 --- a/regression-tests +++ b/regression-tests @@ -1 +1 @@ -Subproject commit 28823bcc69cfb3a994cedc5045c15844ee0a9794 +Subproject commit 1563f0882242d30c7c6661525c917fc33ba42347 From 65490ce7945fa7a809ee2cdf9f93dc3f37507f46 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi <58978462+ricted98@users.noreply.github.com> Date: Fri, 8 Mar 2024 09:41:32 +0100 Subject: [PATCH 121/207] Delete scripts/compile.tcl --- scripts/compile.tcl | 2339 ------------------------------------------- 1 file changed, 2339 deletions(-) delete mode 100644 scripts/compile.tcl diff --git a/scripts/compile.tcl b/scripts/compile.tcl deleted file mode 100644 index b99d8bbc..00000000 --- a/scripts/compile.tcl +++ /dev/null @@ -1,2339 +0,0 @@ -set ROOT [file normalize [file dirname [info script]]/..] -# This script was generated automatically by bender. - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/clk_rst_gen.sv" \ - "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/rand_id_queue.sv" \ - "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/rand_stream_mst.sv" \ - "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/rand_synch_holdable_driver.sv" \ - "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/rand_verif_pkg.sv" \ - "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/signal_highlighter.sv" \ - "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/sim_timeout.sv" \ - "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/stream_watchdog.sv" \ - "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/rand_synch_driver.sv" \ - "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/src/rand_stream_slv.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/common_verification-cc1bf617dee837ac/test/tb_clk_rst_gen.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/rtl/tc_sram.sv" \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/rtl/tc_sram_impl.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/rtl/tc_clk.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/cluster_pwr_cells.sv" \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/generic_memory.sv" \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/generic_rom.sv" \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/pad_functional.sv" \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/pulp_buffer.sv" \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/pulp_pwr_cells.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/tc_pwr.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/test/tb_tc_sram.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/pulp_clock_gating_async.sv" \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/cluster_clk_cells.sv" \ - "$ROOT/.bender/git/checkouts/tech_cells_generic-a2219ab85e824aa9/src/deprecated/pulp_clk_cells.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/binary_to_gray.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cb_filter_pkg.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cc_onehot.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_reset_ctrlr_pkg.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cf_math_pkg.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/clk_int_div.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/delta_counter.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/ecc_pkg.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/edge_propagator_tx.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/exp_backoff.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/fifo_v3.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/gray_to_binary.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/isochronous_4phase_handshake.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/isochronous_spill_register.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/lfsr.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/lfsr_16bit.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/lfsr_8bit.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/lossy_valid_to_stream.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/mv_filter.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/onehot_to_bin.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/plru_tree.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/popcount.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/rr_arb_tree.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/rstgen_bypass.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/serial_deglitch.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/shift_reg.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/shift_reg_gated.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/spill_register_flushable.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_demux.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_filter.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_fork.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_intf.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_join_dynamic.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_mux.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_throttle.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/sub_per_hash.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/sync.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/sync_wedge.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/unread.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/read.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/addr_decode_dync.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_2phase.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_4phase.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/clk_int_div_static.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/addr_decode.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/addr_decode_napot.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/multiaddr_decode.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cb_filter.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_fifo_2phase.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/clk_mux_glitch_free.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/counter.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/ecc_decode.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/ecc_encode.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/edge_detect.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/lzc.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/max_counter.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/rstgen.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/spill_register.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_delay.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_fifo.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_fork_dynamic.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_join.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_reset_ctrlr.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_fifo_gray.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/fall_through_register.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/id_queue.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_to_mem.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_arbiter_flushable.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_fifo_optimal_wrap.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_register.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_xbar.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_fifo_gray_clearable.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/cdc_2phase_clearable.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/mem_to_banks_detailed.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_arbiter.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/stream_omega_net.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/mem_to_banks.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/sram.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/addr_decode_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/cb_filter_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/cdc_2phase_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/cdc_2phase_clearable_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/cdc_fifo_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/cdc_fifo_clearable_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/fifo_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/graycode_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/id_queue_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/popcount_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/rr_arb_tree_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/stream_test.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/stream_register_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/stream_to_mem_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/sub_per_hash_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/isochronous_crossing_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/stream_omega_net_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/stream_xbar_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/clk_int_div_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/clk_int_div_static_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/clk_mux_glitch_free_tb.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/lossy_valid_to_stream_tb.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/clock_divider_counter.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/clk_div.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/find_first_one.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/generic_LFSR_8bit.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/generic_fifo.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/prioarbiter.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/pulp_sync.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/pulp_sync_wedge.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/rrarbiter.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/clock_divider.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/fifo_v2.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/deprecated/fifo_v1.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/edge_propagator_ack.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/edge_propagator.sv" \ - "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/edge_propagator_rx.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/defs_div_sqrt_mvp.sv" \ - "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/iteration_div_sqrt_mvp.sv" \ - "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/control_mvp.sv" \ - "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/norm_div_sqrt_mvp.sv" \ - "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/preprocess_mvp.sv" \ - "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/nrbd_nrsc_mvp.sv" \ - "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/div_sqrt_top_mvp.sv" \ - "$ROOT/.bender/git/checkouts/fpu_div_sqrt_mvp-63417eb299582dbb/hdl/div_sqrt_mvp_wrapper.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_pkg.sv" \ - "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_intf.sv" \ - "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_err_slv.sv" \ - "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_regs.sv" \ - "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_cdc.sv" \ - "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_demux.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/src/apb_test.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/test/tb_apb_regs.sv" \ - "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/test/tb_apb_cdc.sv" \ - "$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/test/tb_apb_demux.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_pkg.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_intf.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_atop_filter.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_burst_splitter.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_bus_compare.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_cdc_dst.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_cdc_src.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_cut.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_delayer.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_demux_simple.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_dw_downsizer.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_dw_upsizer.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_fifo.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_id_remap.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_id_prepend.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_isolate.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_join.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_demux.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_dw_converter.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_from_mem.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_join.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_lfsr.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_mailbox.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_mux.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_regs.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_to_apb.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_to_axi.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_modify_address.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_mux.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_rw_join.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_rw_split.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_serializer.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_slave_compare.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_throttle.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_to_detailed_mem.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_cdc.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_demux.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_err_slv.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_dw_converter.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_from_mem.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_id_serialize.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lfsr.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_multicut.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_to_axi_lite.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_to_mem.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_iw_converter.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_lite_xbar.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_xbar.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_to_mem_banked.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_to_mem_interleaved.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_to_mem_split.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_xp.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_chan_compare.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_dumper.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_sim_mem.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/src/axi_test.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_dw_pkg.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_xbar_pkg.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_addr_test.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_atop_filter.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_bus_compare.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_cdc.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_delayer.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_dw_downsizer.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_dw_upsizer.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_fifo.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_isolate.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_lite_dw_converter.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_lite_mailbox.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_lite_regs.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_iw_converter.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_lite_to_apb.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_lite_to_axi.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_lite_xbar.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_modify_address.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_serializer.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_sim_mem.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_slave_compare.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_to_axi_lite.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_to_mem_banked.sv" \ - "$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/test/tb_axi_xbar.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/addr_dec_resp_mux.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/amo_shim.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/variable_latency_interconnect/addr_decoder.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/xbar.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/variable_latency_interconnect/simplex_xbar.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/clos_net.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/bfly_net.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/variable_latency_interconnect/full_duplex_xbar.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/tcdm_interconnect/tcdm_interconnect.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/variable_latency_interconnect/variable_latency_bfly_net.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/variable_latency_interconnect/variable_latency_interconnect.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/FanInPrimitive_Req.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/ArbitrationTree.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/MUX2_REQ.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/AddressDecoder_Resp.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/TestAndSet.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/RequestBlock2CH.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/RequestBlock1CH.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/FanInPrimitive_Resp.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/ResponseTree.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/ResponseBlock.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/AddressDecoder_Req.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/XBAR_TCDM.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/XBAR_TCDM_WRAPPER.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/TCDM_PIPE_REQ.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/TCDM_PIPE_RESP.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/grant_mask.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco/priority_Flag_Req.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/AddressDecoder_PE_Req.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/AddressDecoder_Resp_PE.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/ArbitrationTree_PE.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/FanInPrimitive_Req_PE.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/RR_Flag_Req_PE.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/MUX2_REQ_PE.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/FanInPrimitive_PE_Resp.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/RequestBlock1CH_PE.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/RequestBlock2CH_PE.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/ResponseBlock_PE.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/ResponseTree_PE.sv" \ - "$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco/XBAR_PE.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_pkg.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_cast_multi.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_classifier.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/clk/rtl/gated_clk_cell.v" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ctrl.v" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_ff1.v" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_pack_single.v" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_prepare.v" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_round_single.v" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_special.v" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_srt_single.v" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fdsu/rtl/pa_fdsu_top.v" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_dp.v" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_frbus.v" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/vendor/opene906/E906_RTL_FACTORY/gen_rtl/fpu/rtl/pa_fpu_src_type.v" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_divsqrt_th_32.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_divsqrt_multi.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_fma.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_fma_multi.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_sdotp_multi.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_sdotp_multi_wrapper.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_noncomp.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_opgroup_block.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_opgroup_fmt_slice.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_opgroup_multifmt_slice.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_rounding.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/lfsr_sr.sv" \ - "$ROOT/.bender/git/checkouts/fpnew-9db08a877f46b059/src/fpnew_top.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/hwpe_stream_interfaces.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/hwpe_stream_package.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_assign.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_buffer.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_demux_static.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_deserialize.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_fence.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_merge.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_mux_static.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_serialize.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_split.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_ctrl.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_scm.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_addressgen.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_addressgen_v2.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_addressgen_v3.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_sink_realign.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_source_realign.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_strbgen.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_streamer_queue.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_assign.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_mux.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_mux_static.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_reorder.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_reorder_static.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_earlystall.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_earlystall_sidech.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_scm_test_wrap.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_sidech.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_fifo_load_sidech.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_passthrough.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_source.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_fifo.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_fifo_load.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_fifo_store.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_sink.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/verif/hwpe_stream_traffic_gen.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/verif/hwpe_stream_traffic_recv.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/verif/tb_fifo.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/l2_tcdm_demux.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/lint_2_apb.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/lint_2_axi.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/axi_2_lint/axi64_2_lint32.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/axi_2_lint/axi_read_ctrl.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/axi_2_lint/axi_write_ctrl.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/axi_2_lint/lint64_to_32.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/AddressDecoder_Req_L2.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/AddressDecoder_Resp_L2.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/ArbitrationTree_L2.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/FanInPrimitive_Req_L2.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/FanInPrimitive_Resp_L2.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/MUX2_REQ_L2.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/RequestBlock_L2_1CH.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/RequestBlock_L2_2CH.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/ResponseBlock_L2.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/ResponseTree_L2.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/RR_Flag_Req_L2.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_L2/XBAR_L2.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/AddressDecoder_Req_BRIDGE.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/AddressDecoder_Resp_BRIDGE.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/ArbitrationTree_BRIDGE.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/FanInPrimitive_Req_BRIDGE.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/FanInPrimitive_Resp_BRIDGE.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/MUX2_REQ_BRIDGE.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/RequestBlock1CH_BRIDGE.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/RequestBlock2CH_BRIDGE.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/ResponseBlock_BRIDGE.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/ResponseTree_BRIDGE.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/RR_Flag_Req_BRIDGE.sv" \ - "$ROOT/.bender/git/checkouts/l2_tcdm_hybrid_interco-1269e18c44c5aa21/RTL/XBAR_BRIDGE/XBAR_BRIDGE.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_single_slice.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_ar_buffer.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_aw_buffer.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_b_buffer.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_r_buffer.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_slice.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_w_buffer.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_slice_wrap.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/bhv" \ - "+incdir+$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/include" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/include/cv32e40p_apu_core_pkg.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/include/cv32e40p_pkg.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_pulp_clock_gate.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_alu.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_alu_div.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_aligner.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_compressed_decoder.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_controller.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_shadow_controller.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_cs_registers.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_decoder.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_int_controller.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_ex_stage.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_fifo.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_hwloop_regs.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_id_stage.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_if_stage.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_load_store_unit.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_mult.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_prefetch_buffer.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_prefetch_controller.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_obi_interface.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_core.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_apu_disp.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_popcnt.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_ff_one.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_sleep_unit.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/bhv" \ - "+incdir+$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/include" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/cv32e40p_register_file_ff.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+CV32E40P_TRACE_EXECUTION \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/bhv" \ - "+incdir+$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/rtl/include" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/bhv/include/cv32e40p_tracer_pkg.sv" \ - "$ROOT/.bender/git/checkouts/cv32e40p-35b87d405a0b7598/bhv/cv32e40p_wrapper.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/common/hci_package.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/common/hci_interfaces.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_assign.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_cmd_queue.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_fifo.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_memmap_demux_interl.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_memmap_filter.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_mux_dynamic.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_mux_static.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_mux_ooo.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_r_valid_filter.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_r_user_filter.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_source.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_split.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_log_interconnect.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_log_interconnect_l2.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_new_log_interconnect.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_shallow_interconnect.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/mem/hci_mem_assign.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_hwpe_reorder.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_sink.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_hwpe_interconnect.sv" \ - "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/hci_interconnect.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl" \ - "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_interfaces.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_package.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_regfile_ff.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_regfile_latch.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_seq_mult.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_uloop.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_regfile_latch_test_wrap.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_regfile.sv" \ - "$ROOT/.bender/git/checkouts/hwpe-ctrl-f0ffa31ac61ad2d6/rtl/hwpe_ctrl_slave.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/Req_Arb_Node_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/Resp_Arb_Node_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/lint_mux.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/DistributedArbitrationNetwork_Req_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/DistributedArbitrationNetwork_Resp_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/RoutingBlock_Req_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/RoutingBlock_2ch_Req_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/RoutingBlock_Resp_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/icache_intc.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/include" \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_intf.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/vendor/lowrisc_opentitan/src/prim_subreg_arb.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/vendor/lowrisc_opentitan/src/prim_subreg_ext.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/apb_to_reg.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/axi_to_reg.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/periph_to_reg.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_cdc.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_demux.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_err_slv.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_filter_empty_writes.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_mux.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_to_apb.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_to_mem.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_uniform.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_to_tlul.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/vendor/lowrisc_opentitan/src/prim_subreg_shadow.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/vendor/lowrisc_opentitan/src/prim_subreg.sv" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/axi_lite_to_reg.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/apb-a9fe5d9ed5687f05/include" \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/src/reg_test.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1r_1w_all.sv" \ - "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1r_1w_be.sv" \ - "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1r_1w.sv" \ - "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1r_1w_1row.sv" \ - "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1r_1w_raw.sv" \ - "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1w_multi_port_read.sv" \ - "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1w_64b_multi_port_read_32b.sv" \ - "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_1w_64b_1r_32b.sv" \ - "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_2r_1w_asymm.sv" \ - "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_2r_1w_asymm_test_wrap.sv" \ - "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_2r_2w.sv" \ - "$ROOT/.bender/git/checkouts/scm-b5c3b6e26a3cbb29/fpga_scm/register_file_3r_2w.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_busy_unit.sv" \ - "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_rd_channel.sv" \ - "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem.sv" \ - "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_tcdm_rd_if.sv" \ - "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_tcdm_synch.sv" \ - "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_tcdm_unit.sv" \ - "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_tcdm_wr_if.sv" \ - "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_trans_unit.sv" \ - "$ROOT/.bender/git/checkouts/axi2mem-72695b5154370c02/axi2mem_wr_channel.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/axi2per-70eb6ef4b0b0efca/axi2per_req_channel.sv" \ - "$ROOT/.bender/git/checkouts/axi2per-70eb6ef4b0b0efca/axi2per_res_channel.sv" \ - "$ROOT/.bender/git/checkouts/axi2per-70eb6ef4b0b0efca/axi2per.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/cluster_control_unit/cluster_control_unit.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/include" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/HW_barrier_logic.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/event_unit_arbiter.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/event_unit_mux.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/event_unit_sm.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/interrupt_mask.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/HW_barrier.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/event_unit_input.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/event_unit/event_unit.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/icache_ctrl_unit/icache_ctrl_unit.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/icache_ctrl_unit/mp_icache_ctrl_unit.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/icache_ctrl_unit/mp_pf_icache_ctrl_unit.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/icache_ctrl_unit/new_icache_ctrl_unit.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/icache_ctrl_unit/pri_icache_ctrl_unit.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/icache_ctrl_unit/sp_icache_ctrl_unit.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/mmu_config_unit/mmu_config_unit.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/perf_counters_unit/perf_counters_unit.sv" \ - "$ROOT/.bender/git/checkouts/cluster_peripherals-45e4f8f679514447/tcdm_pipe_unit/tcdm_pipe_unit.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl" \ - "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/event_unit_core.sv" \ - "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/hw_barrier_unit.sv" \ - "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/hw_dispatch.sv" \ - "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/hw_mutex_unit.sv" \ - "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/interc_sw_evt_trig.sv" \ - "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/periph_FIFO_id.sv" \ - "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/soc_periph_fifo.sv" \ - "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/event_unit_interface_mux.sv" \ - "$ROOT/.bender/git/checkouts/event_unit_flex-915b40dfa1db7f9f/rtl/event_unit_top.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/CTRL_UNIT/hier_icache_ctrl_unit.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/ram_ws_rs_data_scm.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/ram_ws_rs_tag_scm.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/RefillTracker_4.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/REP_buffer_4.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1_CACHE/pri_icache_controller.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1_CACHE/refill_arbiter.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/CTRL_UNIT/hier_icache_ctrl_unit_wrap.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/AXI4_REFILL_Resp_Deserializer.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/share_icache_controller.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1_CACHE/register_file_1w_multi_port_read_test_wrap.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1.5_CACHE/share_icache.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/L1_CACHE/pri_icache.sv" \ - "$ROOT/.bender/git/checkouts/hier-icache-71ffd6f896cfd54b/RTL/TOP/icache_hier_top.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_register_file_latch.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_register_file_ff.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_register_file_fpga.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+RVFI=true \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl" \ - "+incdir+$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/vendor/lowrisc_ip/ip/prim/rtl" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_pkg.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_register_file_ff.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/vendor/lowrisc_ip/ip/prim/rtl/prim_assert.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_alu.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_compressed_decoder.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_controller.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_counter.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_csr.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_decoder.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_fetch_fifo.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_load_store_unit.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_multdiv_fast.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_multdiv_slow.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_pmp.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_tracer_pkg.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_wb_stage.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_cs_registers.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_ex_block.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_id_stage.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_prefetch_buffer.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_tracer.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_if_stage.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_core.sv" \ - "$ROOT/.bender/git/checkouts/ibex-ea88d7e2212bdc23/rtl/ibex_core_tracing.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/idma_transfer_id_gen.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_pkg.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_stream_fifo.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_buffer.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_error_handler.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_channel_coupler.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_axi_transport_layer.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_axi_lite_transport_layer.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_obi_transport_layer.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_legalizer.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/idma_backend.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/legacy/axi_dma_backend.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/legacy/midends/idma_2D_midend.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/midends/idma_nd_midend.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_pkg.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/register_32bit_2d/idma_reg32_2d_frontend_reg_top.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/register_32bit_2d/idma_reg32_2d_frontend.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/register_64bit/idma_reg64_frontend_reg_pkg.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/register_64bit/idma_reg64_frontend_reg_top.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/register_64bit/idma_reg64_frontend.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/desc64/idma_desc64_reg_pkg.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/desc64/idma_desc64_reg_top.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/desc64/idma_desc64_shared_counter.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/desc64/idma_desc64_reg_wrapper.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/frontends/desc64/idma_desc64_top.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_SIMULATION \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ - "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/idma_intf.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/idma_tb_per2axi.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/idma_obi_asserter.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/idma_test.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/idma_obi2axi_bridge.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/tb_idma_backend.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/tb_idma_lite_backend.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/tb_idma_obi_backend.sv" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/tb_idma_nd_backend.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/test/frontends/tb_idma_desc64_top.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/include" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/misc/mchan_arbiter.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/misc/mchan_arb_primitive.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/misc/mchan_rr_flag_req.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/ctrl_fsm.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/ctrl_if.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/ctrl_unit.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/synch_unit.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/trans_allocator.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/trans_queue.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/trans_arbiter_wrap.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/trans_unpack.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/twd_trans_queue.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ctrl_unit/twd_trans_splitter.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_ar_buffer.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_aw_buffer.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_b_buffer.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_buffer.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_opc_buf.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_r_buffer.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_rx_if.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_tid_gen.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_tx_if.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_unit.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/ext_unit/ext_w_buffer.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/tcdm_unit/tcdm_cmd_unpack.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/tcdm_unit/tcdm_rx_if.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/tcdm_unit/tcdm_synch.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/tcdm_unit/tcdm_tx_if.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/tcdm_unit/tcdm_unit.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/trans_unit/trans_aligner.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/trans_unit/trans_buffers.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/trans_unit/trans_unit.sv" \ - "$ROOT/.bender/git/checkouts/mchan-9c1d6ff87a51f443/rtl/top/mchan.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/per2axi-60b4d6ef3b53fc48/src/per2axi_busy_unit.sv" \ - "$ROOT/.bender/git/checkouts/per2axi-60b4d6ef3b53fc48/src/per2axi_req_channel.sv" \ - "$ROOT/.bender/git/checkouts/per2axi-60b4d6ef3b53fc48/src/per2axi_res_channel.sv" \ - "$ROOT/.bender/git/checkouts/per2axi-60b4d6ef3b53fc48/src/per2axi.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_pkg.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_ctrl.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_scheduler.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_castin.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_castout.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_streamer.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_x_buffer.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_w_buffer.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_z_buffer.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_fma.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_noncomp.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_ce.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_row.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_engine.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_top.sv" \ - "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_wrap.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ODRG_unit/odrg_manager_reg_pkg.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ecc_wrap/ecc_manager_reg_pkg.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/pulpissimo_tcls/tcls_manager_reg_pkg.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_13_8_cor.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_13_8_dec.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_13_8_enc.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_22_16_cor.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_22_16_dec.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_22_16_enc.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_39_32_cor.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_39_32_dec.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_39_32_enc.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_72_64_cor.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_72_64_dec.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_72_64_enc.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_pkg.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ODRG_unit/triple_core_barrier.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/hsiao_ecc/hsiao_ecc_pkg.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/hsiao_ecc/hsiao_ecc_enc.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/hsiao_ecc/hsiao_ecc_dec.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/hsiao_ecc/hsiao_ecc_cor.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/TMR_voter.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/TMR_word_voter.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/resp_suppress.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ODRG_unit/odrg_manager_reg_top.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ecc_wrap/ecc_manager_reg_top.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/pulpissimo_tcls/tcls_manager_reg_top.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ecc_wrap/ecc_scrubber.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ecc_concat_32_64.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_pkg.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_13_8_cor.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_13_8_dec.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_13_8_enc.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_22_16_cor.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_22_16_dec.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_22_16_enc.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_39_32_cor.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_39_32_dec.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_39_32_enc.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_72_64_cor.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_72_64_dec.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/lowrisc_ecc/prim_secded_72_64_enc.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/TMR_voter_detect.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/bitwise_TMR_voter.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ecc_wrap/ecc_manager.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ecc_wrap/ecc_sram_wrap.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ODRG_unit" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/ODRG_unit/ODRG_unit.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/pulpissimo_tcls" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/pulpissimo_tcls/TCLS_unit.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_ecc_scrubber.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_ecc_secded.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_ecc_sram.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_tmr_voter.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_tmr_voter_detect.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_tmr_word_voter.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/test/tb_bitwise_tmr_voter.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/rapid_recovery_pkg.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/recovery_csr.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/recovery_pc.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/recovery_rf.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/rapid_recovery_unit.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/DMR_checker.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/DMR_CSR_checker.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/DMR_address_generator.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_rapid_recovery_ctrl.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_registers_reg_pkg.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_core_regs_reg_pkg.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_dmr_regs_reg_pkg.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_tmr_regs_reg_pkg.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_registers_reg_top.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_core_regs_reg_top.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_dmr_regs_reg_top.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_dmr_ctrl.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_tmr_regs_reg_top.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_tmr_ctrl.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/HMR_wrap.sv" \ - "$ROOT/.bender/git/checkouts/redundancy_cells-5efefdcf7db23b80/rtl/HMR/hmr_unit.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include/apu_core_package.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include/riscv_defines.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include/riscv_tracer_defines.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/macload_controller.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/mixed_precision_controller.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_alu.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_alu_basic.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_alu_div.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_compressed_decoder.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_controller.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_cs_registers.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_decoder.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_int_controller.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_ex_stage.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_hwloop_controller.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_hwloop_regs.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/register_file_test_wrap.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_id_stage.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_if_stage.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_load_store_unit.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_mult.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_prefetch_buffer.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_prefetch_L0_buffer.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_core.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_apu_disp.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_fetch_fifo.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_L0_buffer.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_pmp.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_register_file.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_tracer.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/timer_unit-beb608985450c057/rtl/timer_unit_counter.sv" \ - "$ROOT/.bender/git/checkouts/timer_unit-beb608985450c057/rtl/timer_unit_counter_presc.sv" \ - "$ROOT/.bender/git/checkouts/timer_unit-beb608985450c057/rtl/apb_timer_unit.sv" \ - "$ROOT/.bender/git/checkouts/timer_unit-beb608985450c057/rtl/timer_unit.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "+incdir+$ROOT/include" \ - "$ROOT/packages/pulp_cluster_package.sv" \ - "$ROOT/rtl/axi2mem_wrap.sv" \ - "$ROOT/rtl/axi2per_wrap.sv" \ - "$ROOT/rtl/cluster_bus_wrap.sv" \ - "$ROOT/rtl/cluster_clock_gate.sv" \ - "$ROOT/rtl/cluster_event_map.sv" \ - "$ROOT/rtl/cluster_timer_wrap.sv" \ - "$ROOT/rtl/obi_pulp_adapter.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "+incdir+$ROOT/include" \ - "$ROOT/rtl/mchan_wrap.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "+incdir+$ROOT/include" \ - "$ROOT/rtl/hwpe_subsystem.sv" \ - "$ROOT/rtl/instr_width_converter.sv" \ - "$ROOT/rtl/per2axi_wrap.sv" \ - "$ROOT/rtl/periph_demux.sv" \ - "$ROOT/rtl/per_demux_wrap.sv" \ - "$ROOT/rtl/periph_FIFO.sv" \ - "$ROOT/rtl/tcdm_banks_wrap.sv" \ - "$ROOT/rtl/xbar_pe_wrap.sv" \ - "$ROOT/rtl/cluster_interconnect_wrap.sv" \ - "$ROOT/rtl/cluster_peripherals.sv" \ - "$ROOT/rtl/data_periph_demux.sv" \ - "$ROOT/rtl/core_demux_wrap.sv" \ - "$ROOT/rtl/core_region.sv" \ - "$ROOT/rtl/pulp_cluster.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "+incdir+$ROOT/include" \ - "$ROOT/tb/mock_uart.sv" \ - "$ROOT/tb/axi2apb_64_32.sv" \ - "$ROOT/tb/mock_uart_axi.sv" \ - "$ROOT/tb/pulp_cluster_tb.sv" \ -}]} {return 1} - -if {[catch { vlog -incr -sv \ - -suppress vlog-2583 -suppress vlog-13314 -suppress vlog-13233 -timescale "1 ns / 1 ps" "+incdir+/scratch2/rtedeschi/astral/scrubber/include" \ - +define+TARGET_CLUSTER_STANDALONE \ - +define+TARGET_CV32E40P_USE_FF_REGFILE \ - +define+TARGET_MCHAN \ - +define+TARGET_RTL \ - +define+TARGET_SCM_USE_FPGA_SCM \ - +define+TARGET_SIMULATION \ - +define+TARGET_TEST \ - +define+TARGET_VSIM \ - +define+FEATURE_ICACHE_STAT \ - +define+PRIVATE_ICACHE \ - +define+HIERARCHY_ICACHE_32BIT \ - +define+ICAHE_USE_FF \ - +define+NO_FPU \ - +define+TRACE_EXECUTION \ - +define+CLUSTER_ALIAS \ - +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/axi-f34f593106290a7f/include" \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ - "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "+incdir+$ROOT/.bender/git/checkouts/idma-56b9ad1d44bf0812/src/include" \ - "+incdir+$ROOT/.bender/git/checkouts/register_interface-96e1aa763449594f/include" \ - "+incdir+$ROOT/include" \ - "$ROOT/include/pulp_interfaces.sv" \ -}]} {return 1} - - -vlog "/scratch2/rtedeschi/astral/scrubber/tb/dpi/elfloader.cpp" -ccflags "-std=c++11" From 1d6b1fe8a4153c5059207ca69ba011033bc74c3c Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Mon, 11 Mar 2024 13:23:09 +0100 Subject: [PATCH 122/207] Bump SW and CI deps --- Makefile | 2 +- regression-tests | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 26a0dc24..a208087f 100644 --- a/Makefile +++ b/Makefile @@ -53,7 +53,7 @@ endef ###################### NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git -NONFREE_COMMIT ?= 7bd4e0bab5282a20aebbe63de6bb94462bdc1231 +NONFREE_COMMIT ?= 99ab7cf5e5c69e134ef84ad3304138f6fa105dd8 nonfree-init: git clone $(NONFREE_REMOTE) nonfree diff --git a/regression-tests b/regression-tests index 1563f088..ad3aeeff 160000 --- a/regression-tests +++ b/regression-tests @@ -1 +1 @@ -Subproject commit 1563f0882242d30c7c6661525c917fc33ba42347 +Subproject commit ad3aeeff90e4b754805a14230a5c39157cc14f96 From 83e790749908d2771461616a72937bcfec29063e Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 18 Mar 2024 22:46:49 +0100 Subject: [PATCH 123/207] Integrate AXI ID remappers. --- packages/pulp_cluster_package.sv | 6 ++ rtl/pulp_cluster.sv | 133 ++++++++++++++++++++++++------- tb/pulp_cluster_tb.sv | 2 + 3 files changed, 113 insertions(+), 28 deletions(-) diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 0a73b01d..78662fea 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -110,6 +110,10 @@ package pulp_cluster_package; byte_t AxiDataOutWidth; // AXI user width byte_t AxiUserWidth; + // AXI maximum subordinate transaction per ID + byte_t AxiMaxInTrans; + // AXI maximum manager transaction per ID + byte_t AxiMaxOutTrans; // Log depth of AXI CDC FIFOs byte_t AxiCdcLogDepth; // old LOG_DEPTH // Sinchronization stages of AXI CDC FIFOs @@ -192,6 +196,8 @@ package pulp_cluster_package; AxiDataInWidth: 32, AxiDataOutWidth: 32, AxiUserWidth: 10, + AxiMaxInTrans: 64, + AxiMaxOutTrans: 64, AxiCdcLogDepth: 3, AxiCdcSyncStages: 3, ClusterBaseAddr: 'h10000000, diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index ab09b0d3..3eac9831 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -32,6 +32,9 @@ module pulp_cluster parameter pulp_cluster_package::pulp_cluster_cfg_t Cfg = pulp_cluster_package::PulpClusterDefaultCfg, localparam int unsigned TcdmBankSize = Cfg.TcdmSize/Cfg.TcdmNumBank, localparam int unsigned TcdmNumRows = TcdmBankSize/4, + localparam int unsigned MaxUniqId = 1, + localparam int unsigned AxiIdInWidth = pulp_cluster_package::AxiSubordinateIdwidth, + localparam int unsigned AxiIdOutWidth = pulp_cluster_package::AxiManagerIdwidth, // CDC AXI parameters (external to cluster) localparam int unsigned AwInWidth = axi_pkg::aw_width(Cfg.AxiAddrWidth, Cfg.AxiIdInWidth, @@ -198,7 +201,7 @@ module pulp_cluster //Ensure that the input AXI ID width is big enough to accomodate the accomodate the IDs of internal wiring if (Cfg.AxiIdInWidth < 1 + $clog2(Cfg.iCacheNumBanks)) - $error("AXI input ID width must be larger than 1+$clog2(Cfg.iCacheNumBanks) which is %d but was %d", 1 + $clog2(Cfg.iCacheNumBanks), Cfg.AxiIdInWidth); + $info("AXI input ID width must be larger than 1+$clog2(Cfg.iCacheNumBanks) which is %d but was %d", 1 + $clog2(Cfg.iCacheNumBanks), Cfg.AxiIdInWidth); localparam int unsigned NB_L1_CUTS = 16; localparam int unsigned RW_MARGIN_WIDTH = 4; @@ -421,28 +424,28 @@ hci_mem_intf #( AXI_BUS #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_ID_WIDTH ( AxiIdInWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_data_slave_int(); AXI_BUS #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataInWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_ID_WIDTH ( AxiIdInWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_data_slave_ext(); AXI_BUS #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdOutWidth ), + .AXI_ID_WIDTH ( AxiIdOutWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_data_master(); AXI_BUS #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_ID_WIDTH ( AxiIdInWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_core_instr_bus(); @@ -460,7 +463,7 @@ AXI_BUS #( AXI_BUS #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_ID_WIDTH ( AxiIdInWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_core_ext_bus(); @@ -468,7 +471,7 @@ AXI_BUS #( AXI_BUS #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_ID_WIDTH ( AxiIdInWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_dma_ext_bus(); @@ -476,7 +479,7 @@ AXI_BUS #( AXI_BUS #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdOutWidth ), + .AXI_ID_WIDTH ( AxiIdOutWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_ext_tcdm_bus(); @@ -484,7 +487,7 @@ AXI_BUS #( AXI_BUS #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdOutWidth ), + .AXI_ID_WIDTH ( AxiIdOutWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_ext_mperiph_bus(); @@ -503,8 +506,8 @@ cluster_bus_wrap #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), - .AXI_ID_IN_WIDTH ( Cfg.AxiIdInWidth ), - .AXI_ID_OUT_WIDTH ( Cfg.AxiIdOutWidth ), + .AXI_ID_IN_WIDTH ( AxiIdInWidth ), + .AXI_ID_OUT_WIDTH ( AxiIdOutWidth ), .BaseAddr ( Cfg.ClusterBaseAddr ), .ClusterPeripheralsOffs ( Cfg.ClusterPeriphOffs ), .ClusterExternalOffs ( Cfg.ClusterExternalOffs ) @@ -527,7 +530,7 @@ axi2mem_wrap #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdOutWidth ) + .AXI_ID_WIDTH ( AxiIdOutWidth ) ) axi2mem_wrap_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -540,7 +543,7 @@ axi2mem_wrap #( axi2per_wrap #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdOutWidth ), + .AXI_ID_WIDTH ( AxiIdOutWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) axi2per_wrap_i ( .clk_i ( clk_i ), @@ -577,7 +580,7 @@ per2axi_wrap #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ) + .AXI_ID_WIDTH ( AxiIdInWidth ) ) per2axi_wrap_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -645,7 +648,7 @@ cluster_interconnect_wrap #( .MCHAN_BURST_LENGTH ( Cfg.DmaBurstLength ), .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_ID_WIDTH ( AxiIdInWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), .PE_ID_WIDTH ( Cfg.NumCores + 1 ), .TCDM_ADD_WIDTH ( TcdmAddrWidth ), @@ -675,7 +678,7 @@ cluster_interconnect_wrap #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ), - .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_ID_WIDTH ( AxiIdInWidth ), .PE_ID_WIDTH ( Cfg.NumCores + 1 ), .NB_PE_PORTS ( 2 ), .DATA_WIDTH ( DataWidth ), @@ -1208,7 +1211,7 @@ icache_hier_top #( .PRI_CACHE_SIZE ( Cfg.iCachePrivateSize), //= 512, // in Byte .PRI_CACHE_LINE ( Cfg.iCacheNumLines ), //= 1, // in word of [PRI_FETCH_DATA_WIDTH] - .AXI_ID ( Cfg.AxiIdInWidth ), //= 6, + .AXI_ID ( AxiIdInWidth ), //= 6, .AXI_ADDR ( Cfg.AxiAddrWidth ), //= 32, .AXI_USER ( Cfg.AxiUserWidth ), //= 6, .AXI_DATA ( Cfg.AxiDataOutWidth ), //= 64, @@ -1383,15 +1386,12 @@ tcdm_banks_wrap #( `AXI_TYPEDEF_B_CHAN_T(c2s_b_chan_t,logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) `AXI_TYPEDEF_AR_CHAN_T(c2s_ar_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) `AXI_TYPEDEF_R_CHAN_T(c2s_r_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[Cfg.AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) - + `AXI_TYPEDEF_REQ_T(c2s_req_t,c2s_aw_chan_t,c2s_w_chan_t,c2s_ar_chan_t) `AXI_TYPEDEF_RESP_T(c2s_resp_t,c2s_b_chan_t,c2s_r_chan_t) c2s_req_t src_req, isolate_src_req ; c2s_resp_t src_resp, isolate_src_resp; - -`AXI_ASSIGN_TO_REQ(isolate_src_req,s_data_master) -`AXI_ASSIGN_FROM_RESP(s_data_master,isolate_src_resp) sync #( .STAGES ( Cfg.SyncStages ), @@ -1443,6 +1443,44 @@ sync #( .serial_o ( mbox_irq_synch ) ); +`AXI_TYPEDEF_AW_CHAN_T(c2s_remap_aw_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) +`AXI_TYPEDEF_W_CHAN_T(c2s_remap_w_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[Cfg.AxiDataOutWidth/8-1:0],logic[Cfg.AxiUserWidth-1:0]) +`AXI_TYPEDEF_B_CHAN_T(c2s_remap_b_chan_t,logic[AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) +`AXI_TYPEDEF_AR_CHAN_T(c2s_remap_ar_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) +`AXI_TYPEDEF_R_CHAN_T(c2s_remap_r_chan_t,logic[Cfg.AxiDataOutWidth-1:0],logic[AxiIdOutWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) + +`AXI_TYPEDEF_REQ_T(c2s_remap_req_t,c2s_remap_aw_chan_t,c2s_remap_w_chan_t,c2s_remap_ar_chan_t) +`AXI_TYPEDEF_RESP_T(c2s_remap_resp_t,c2s_remap_b_chan_t,c2s_remap_r_chan_t) + +c2s_remap_req_t src_remap_req; +c2s_remap_resp_t src_remap_resp; + +`AXI_ASSIGN_TO_REQ(src_remap_req,s_data_master) +`AXI_ASSIGN_FROM_RESP(s_data_master,src_remap_resp) + +if (Cfg.AxiIdOutWidth != AxiIdOutWidth) begin : gen_c2s_idwremap + axi_id_remap #( + .AxiSlvPortIdWidth ( AxiIdOutWidth ), + .AxiSlvPortMaxUniqIds ( MaxUniqId ), + .AxiMaxTxnsPerId ( Cfg.AxiMaxOutTrans ), + .AxiMstPortIdWidth ( Cfg.AxiIdOutWidth ), + .slv_req_t ( c2s_remap_req_t ), + .slv_resp_t ( c2s_remap_resp_t ), + .mst_req_t ( c2s_req_t ), + .mst_resp_t ( c2s_resp_t ) + ) i_axi_out_id_remap ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( src_remap_req ), + .slv_resp_o ( src_remap_resp ), + .mst_req_o ( isolate_src_req ), + .mst_resp_i ( isolate_src_resp ) + ); +end else begin : gen_no_c2s_idwremap + assign isolate_src_req = src_remap_req; + assign src_remap_resp = isolate_src_resp; +end + axi_isolate #( .NumPending ( 8 ), .TerminateTransaction ( 1 ), @@ -1506,8 +1544,8 @@ axi_cdc_src #( `AXI_TYPEDEF_REQ_T(s2c_req_t,s2c_aw_chan_t,s2c_w_chan_t,s2c_ar_chan_t) `AXI_TYPEDEF_RESP_T(s2c_resp_t,s2c_b_chan_t,s2c_r_chan_t) -s2c_req_t dst_req , isolate_dst_req; -s2c_resp_t dst_resp, isolate_dst_resp; +s2c_req_t dst_req; +s2c_resp_t dst_resp; axi_cdc_dst #( .aw_chan_t ( s2c_aw_chan_t ), @@ -1541,12 +1579,51 @@ axi_cdc_dst #( .async_data_slave_r_data_o ( async_data_slave_r_data_o ) ); +// If the AXI ID width of the subordinate port does not match the one required, we interpose +// an AXI ID remapper. Otherwise the busses are simply assigned. +`AXI_TYPEDEF_AW_CHAN_T(s2c_remap_aw_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) +`AXI_TYPEDEF_W_CHAN_T(s2c_remap_w_chan_t,logic[Cfg.AxiDataInWidth-1:0],logic[Cfg.AxiDataInWidth/8-1:0],logic[Cfg.AxiUserWidth-1:0]) +`AXI_TYPEDEF_B_CHAN_T(s2c_remap_b_chan_t,logic[AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) +`AXI_TYPEDEF_AR_CHAN_T(s2c_remap_ar_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) +`AXI_TYPEDEF_R_CHAN_T(s2c_remap_r_chan_t,logic[Cfg.AxiDataInWidth-1:0],logic[AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) + +`AXI_TYPEDEF_REQ_T(s2c_remap_req_t,s2c_remap_aw_chan_t,s2c_remap_w_chan_t,s2c_remap_ar_chan_t) +`AXI_TYPEDEF_RESP_T(s2c_remap_resp_t,s2c_remap_b_chan_t,s2c_remap_r_chan_t) + +s2c_remap_req_t dst_remap_req; +s2c_remap_resp_t dst_remap_resp; + +if (Cfg.AxiIdInWidth != AxiIdInWidth) begin : gen_s2c_idwremap + axi_id_remap #( + .AxiSlvPortIdWidth ( Cfg.AxiIdInWidth ), + .AxiSlvPortMaxUniqIds ( MaxUniqId ), + .AxiMaxTxnsPerId ( Cfg.AxiMaxInTrans ), + .AxiMstPortIdWidth ( AxiIdInWidth ), + .slv_req_t ( s2c_req_t ), + .slv_resp_t ( s2c_resp_t ), + .mst_req_t ( s2c_remap_req_t ), + .mst_resp_t ( s2c_remap_resp_t ) + ) i_axi_in_id_remap ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( dst_req ), + .slv_resp_o ( dst_resp ), + .mst_req_o ( dst_remap_req ), + .mst_resp_i ( dst_remap_resp ) + ); +end else begin : gen_no_s2c_idwremap + assign dst_remap_req = dst_req; + assign dst_resp = dst_remap_resp; +end + +// If the external and internal data widths do not match, we interpose an AXI +// data width converter, otherwise the buses are simply assigned. if (Cfg.AxiDataInWidth != Cfg.AxiDataOutWidth) begin - `AXI_ASSIGN_FROM_REQ(s_data_slave_ext,dst_req) - `AXI_ASSIGN_TO_RESP(dst_resp,s_data_slave_ext) + `AXI_ASSIGN_FROM_REQ(s_data_slave_ext,dst_remap_req) + `AXI_ASSIGN_TO_RESP(dst_remap_resp,s_data_slave_ext) axi_dw_converter_intf #( - .AXI_ID_WIDTH ( Cfg.AxiIdInWidth ), + .AXI_ID_WIDTH ( pulp_cluster_package::AxiSubordinateIdwidth ), .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_SLV_PORT_DATA_WIDTH ( Cfg.AxiDataInWidth ), .AXI_MST_PORT_DATA_WIDTH ( Cfg.AxiDataOutWidth), @@ -1559,8 +1636,8 @@ if (Cfg.AxiDataInWidth != Cfg.AxiDataOutWidth) begin .mst ( s_data_slave_int ) ); end else begin - `AXI_ASSIGN_FROM_REQ(s_data_slave_int,dst_req) - `AXI_ASSIGN_TO_RESP(dst_resp,s_data_slave_int) + `AXI_ASSIGN_FROM_REQ(s_data_slave_int,dst_remap_req) + `AXI_ASSIGN_TO_RESP(dst_remap_resp,s_data_slave_int) end /* event synchronizers */ diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 7f5853d7..19fb6c86 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -314,6 +314,8 @@ module pulp_cluster_tb; AxiDataInWidth: AxiDw, AxiDataOutWidth: AxiDw, AxiUserWidth: AxiUw, + AxiMaxInTrans: 64, + AxiMaxOutTrans: 64, AxiCdcLogDepth: 3, AxiCdcSyncStages: 3, SyncStages: 3, From bb8a855740cf52fa9f5a8c0e0a43ead62cb8a121 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 19 Mar 2024 14:59:06 +0100 Subject: [PATCH 124/207] Various fixes and parameters alignment. --- rtl/pulp_cluster.sv | 110 ++++++++++++++++++++++---------------------- 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 3eac9831..1887a00b 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -217,7 +217,7 @@ localparam int unsigned RW_MARGIN_WIDTH = 4; logic [Cfg.NumCores-1:0] fetch_enable_reg_int; logic [Cfg.NumCores-1:0] fetch_en_int; -logic [Cfg.NumCores-1:0][31:0] boot_addr; +logic [Cfg.NumCores-1:0][AddrWidth-1:0] boot_addr; logic [Cfg.NumCores-1:0] dbg_core_halt; logic [Cfg.NumCores-1:0] dbg_core_resume; logic [Cfg.NumCores-1:0] dbg_core_halted; @@ -251,7 +251,7 @@ logic [Cfg.NumCores-1:0] clk_core_en; logic s_cluster_int_busy; logic s_fregfile_disable; -logic [Cfg.NumCores-1:0] core_busy; +logic [Cfg.NumCores-1:0] core_busy; logic s_incoming_req; logic s_isolate_cluster; @@ -263,7 +263,7 @@ logic [EventWidth-1:0] s_events_data; // Signals Between CORE_ISLAND and INSTRUCTION CACHES logic [Cfg.NumCores-1:0] instr_req; -logic [Cfg.NumCores-1:0][31:0] instr_addr; +logic [Cfg.NumCores-1:0][AddrWidth-1:0] instr_addr; logic [Cfg.NumCores-1:0] instr_gnt; logic [Cfg.NumCores-1:0] instr_r_valid; logic [Cfg.NumCores-1:0][Cfg.iCachePrivateDataWidth-1:0] instr_r_rdata; @@ -575,7 +575,7 @@ end per2axi_wrap #( .NB_CORES ( Cfg.NumCores ), - .PER_ADDR_WIDTH ( 32 ), + .PER_ADDR_WIDTH ( AddrWidth ), .PER_ID_WIDTH ( Cfg.NumCores + Cfg.NumMstPeriphs ), .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), @@ -801,7 +801,7 @@ cluster_peripherals #( //------------------------------------------------------// /* cluster cores + core-coupled accelerators / shared execution units */ -`REG_BUS_TYPEDEF_ALL(hmr_reg, logic[31:0], logic[31:0], logic[3:0]) +`REG_BUS_TYPEDEF_ALL(hmr_reg, logic[AddrWidth-1:0], logic[DataWidth-1:0], logic[BeWidth-1:0]) hmr_reg_req_t hmr_reg_req; hmr_reg_rsp_t hmr_reg_rsp; @@ -861,8 +861,8 @@ generate core_region #( .CORE_TYPE_CL ( Cfg.CoreType ), .N_EXT_PERF_COUNTERS ( 5 ), - .ADDR_WIDTH ( 32 ), - .DATA_WIDTH ( 32 ), + .ADDR_WIDTH ( AddrWidth ), + .DATA_WIDTH ( DataWidth ), .INSTR_RDATA_WIDTH ( Cfg.iCachePrivateDataWidth ), .CLUSTER_ALIAS ( Cfg.ClusterAlias ), .CLUSTER_ALIAS_BASE ( Cfg.ClusterAliasBase ), @@ -1101,7 +1101,7 @@ generate .FP_TYPE_WIDTH ( FpuTypeWidth ), .NB_CORE_ARGS ( FpuNumArgs ), - .CORE_DATA_WIDTH ( 32 ), + .CORE_DATA_WIDTH ( DataWidth ), .CORE_OPCODE_WIDTH ( FpuOpCodeWidth ), .CORE_DSFLAGS_CPU ( FpuInFlagsWidth ), .CORE_USFLAGS_CPU ( FpuOutFlagsWidth ), @@ -1196,7 +1196,7 @@ generate endgenerate icache_hier_top #( - .FETCH_ADDR_WIDTH ( 32 ), //= 32, + .FETCH_ADDR_WIDTH ( AddrWidth ), //= 32, .PRI_FETCH_DATA_WIDTH ( Cfg.iCachePrivateDataWidth ), //= 128, // Tested for 32 and 128 .SH_FETCH_DATA_WIDTH ( 128 ), //= 128, @@ -1295,7 +1295,7 @@ icache_hier_top #( assign s_core_instr_bus.aw_atop = '0; -`REG_BUS_TYPEDEF_ALL(tcdm_scrubber_reg, logic[31:0], logic[31:0], logic[3:0]) +`REG_BUS_TYPEDEF_ALL(tcdm_scrubber_reg, logic[AddrWidth-1:0], logic[DataWidth-1:0], logic[BeWidth-1:0]) tcdm_scrubber_reg_req_t tcdm_scrubber_reg_req; tcdm_scrubber_reg_rsp_t tcdm_scrubber_reg_rsp; @@ -1325,12 +1325,12 @@ periph_to_reg #( .reg_rsp_i ( tcdm_scrubber_reg_rsp ) ); -logic [Cfg.TcdmNumBank] bank_faults; -logic [Cfg.TcdmNumBank] ecc_single_error; -logic [Cfg.TcdmNumBank] ecc_multiple_error; -logic [Cfg.TcdmNumBank] scrubber_fix; -logic [Cfg.TcdmNumBank] scrubber_uncorrectable; -logic [Cfg.TcdmNumBank] scrubber_trigger; +logic [Cfg.TcdmNumBank-1:0] bank_faults; +logic [Cfg.TcdmNumBank-1:0] ecc_single_error; +logic [Cfg.TcdmNumBank-1:0] ecc_multiple_error; +logic [Cfg.TcdmNumBank-1:0] scrubber_fix; +logic [Cfg.TcdmNumBank-1:0] scrubber_uncorrectable; +logic [Cfg.TcdmNumBank-1:0] scrubber_trigger; assign bank_faults = ecc_single_error | ecc_multiple_error; // TODO: check @@ -1513,25 +1513,25 @@ axi_cdc_src #( .LogDepth ( Cfg.AxiCdcLogDepth ), .SyncStages ( Cfg.AxiCdcSyncStages ) ) axi_master_cdc_i ( - .src_rst_ni ( pwr_on_rst_ni ), - .src_clk_i ( clk_i ), - .src_req_i ( src_req ), - .src_resp_o ( src_resp ), - .async_data_master_aw_wptr_o ( async_data_master_aw_wptr_o ), - .async_data_master_aw_rptr_i ( async_data_master_aw_rptr_i ), - .async_data_master_aw_data_o ( async_data_master_aw_data_o ), - .async_data_master_w_wptr_o ( async_data_master_w_wptr_o ), - .async_data_master_w_rptr_i ( async_data_master_w_rptr_i ), - .async_data_master_w_data_o ( async_data_master_w_data_o ), - .async_data_master_ar_wptr_o ( async_data_master_ar_wptr_o ), - .async_data_master_ar_rptr_i ( async_data_master_ar_rptr_i ), - .async_data_master_ar_data_o ( async_data_master_ar_data_o ), - .async_data_master_b_wptr_i ( async_data_master_b_wptr_i ), - .async_data_master_b_rptr_o ( async_data_master_b_rptr_o ), - .async_data_master_b_data_i ( async_data_master_b_data_i ), - .async_data_master_r_wptr_i ( async_data_master_r_wptr_i ), - .async_data_master_r_rptr_o ( async_data_master_r_rptr_o ), - .async_data_master_r_data_i ( async_data_master_r_data_i ) + .src_rst_ni ( pwr_on_rst_ni ), + .src_clk_i ( clk_i ), + .src_req_i ( src_req ), + .src_resp_o ( src_resp ), + .async_data_master_aw_wptr_o ( async_data_master_aw_wptr_o ), + .async_data_master_aw_rptr_i ( async_data_master_aw_rptr_i ), + .async_data_master_aw_data_o ( async_data_master_aw_data_o ), + .async_data_master_w_wptr_o ( async_data_master_w_wptr_o ), + .async_data_master_w_rptr_i ( async_data_master_w_rptr_i ), + .async_data_master_w_data_o ( async_data_master_w_data_o ), + .async_data_master_ar_wptr_o ( async_data_master_ar_wptr_o ), + .async_data_master_ar_rptr_i ( async_data_master_ar_rptr_i ), + .async_data_master_ar_data_o ( async_data_master_ar_data_o ), + .async_data_master_b_wptr_i ( async_data_master_b_wptr_i ), + .async_data_master_b_rptr_o ( async_data_master_b_rptr_o ), + .async_data_master_b_data_i ( async_data_master_b_data_i ), + .async_data_master_r_wptr_i ( async_data_master_r_wptr_i ), + .async_data_master_r_rptr_o ( async_data_master_r_rptr_o ), + .async_data_master_r_data_i ( async_data_master_r_data_i ) ); // SOC TO CLUSTER @@ -1558,25 +1558,25 @@ axi_cdc_dst #( .LogDepth ( Cfg.AxiCdcLogDepth ), .SyncStages ( Cfg.AxiCdcSyncStages ) ) axi_slave_cdc_i ( - .dst_rst_ni ( pwr_on_rst_ni ), - .dst_clk_i ( clk_i ), - .dst_req_o ( dst_req ), - .dst_resp_i ( dst_resp ), - .async_data_slave_aw_wptr_i ( async_data_slave_aw_wptr_i ), - .async_data_slave_aw_rptr_o ( async_data_slave_aw_rptr_o ), - .async_data_slave_aw_data_i ( async_data_slave_aw_data_i ), - .async_data_slave_w_wptr_i ( async_data_slave_w_wptr_i ), - .async_data_slave_w_rptr_o ( async_data_slave_w_rptr_o ), - .async_data_slave_w_data_i ( async_data_slave_w_data_i ), - .async_data_slave_ar_wptr_i ( async_data_slave_ar_wptr_i ), - .async_data_slave_ar_rptr_o ( async_data_slave_ar_rptr_o ), - .async_data_slave_ar_data_i ( async_data_slave_ar_data_i ), - .async_data_slave_b_wptr_o ( async_data_slave_b_wptr_o ), - .async_data_slave_b_rptr_i ( async_data_slave_b_rptr_i ), - .async_data_slave_b_data_o ( async_data_slave_b_data_o ), - .async_data_slave_r_wptr_o ( async_data_slave_r_wptr_o ), - .async_data_slave_r_rptr_i ( async_data_slave_r_rptr_i ), - .async_data_slave_r_data_o ( async_data_slave_r_data_o ) + .dst_rst_ni ( pwr_on_rst_ni ), + .dst_clk_i ( clk_i ), + .dst_req_o ( dst_req ), + .dst_resp_i ( dst_resp ), + .async_data_slave_aw_wptr_i ( async_data_slave_aw_wptr_i ), + .async_data_slave_aw_rptr_o ( async_data_slave_aw_rptr_o ), + .async_data_slave_aw_data_i ( async_data_slave_aw_data_i ), + .async_data_slave_w_wptr_i ( async_data_slave_w_wptr_i ), + .async_data_slave_w_rptr_o ( async_data_slave_w_rptr_o ), + .async_data_slave_w_data_i ( async_data_slave_w_data_i ), + .async_data_slave_ar_wptr_i ( async_data_slave_ar_wptr_i ), + .async_data_slave_ar_rptr_o ( async_data_slave_ar_rptr_o ), + .async_data_slave_ar_data_i ( async_data_slave_ar_data_i ), + .async_data_slave_b_wptr_o ( async_data_slave_b_wptr_o ), + .async_data_slave_b_rptr_i ( async_data_slave_b_rptr_i ), + .async_data_slave_b_data_o ( async_data_slave_b_data_o ), + .async_data_slave_r_wptr_o ( async_data_slave_r_wptr_o ), + .async_data_slave_r_rptr_i ( async_data_slave_r_rptr_i ), + .async_data_slave_r_data_o ( async_data_slave_r_data_o ) ); // If the AXI ID width of the subordinate port does not match the one required, we interpose @@ -1623,7 +1623,7 @@ if (Cfg.AxiDataInWidth != Cfg.AxiDataOutWidth) begin `AXI_ASSIGN_TO_RESP(dst_remap_resp,s_data_slave_ext) axi_dw_converter_intf #( - .AXI_ID_WIDTH ( pulp_cluster_package::AxiSubordinateIdwidth ), + .AXI_ID_WIDTH ( AxiIdInWidth ), .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_SLV_PORT_DATA_WIDTH ( Cfg.AxiDataInWidth ), .AXI_MST_PORT_DATA_WIDTH ( Cfg.AxiDataOutWidth), From 3f3eb2e7a558b1b4acc0cc8dd011a5d19f753d9c Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Mon, 12 Feb 2024 12:07:32 +0100 Subject: [PATCH 125/207] Add NEureka dependency --- Bender.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/Bender.yml b/Bender.yml index 002af572..a0d7e3f2 100644 --- a/Bender.yml +++ b/Bender.yml @@ -34,6 +34,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 1b30b0b9a31afa702eb2d166d672ceda2f5d463a } # branch: astral + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: d9e4c3c38aa28b3149444840297100f7355ddc22 } # branch: astral export_include_dirs: - include From 525613200d626b2dcfe4f773beda11f01f63c698 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Mon, 12 Feb 2024 12:09:04 +0100 Subject: [PATCH 126/207] Add `cv32e40p` override to `Bender.local` --- Bender.local | 1 + 1 file changed, 1 insertion(+) diff --git a/Bender.local b/Bender.local index 8ac1a168..5c808517 100644 --- a/Bender.local +++ b/Bender.local @@ -2,3 +2,4 @@ overrides: axi : { git: "https://github.com/pulp-platform/axi.git" , version: =0.39.1 } register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix + cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic From a271fef383d7ec55ffdf79f7243813b4eb2d1547 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Mon, 12 Feb 2024 17:01:19 +0100 Subject: [PATCH 127/207] Integrate NEureka in HWPE subsystem with RedMulE * `hwpe_sel` is used to statically choose the HWPE * `hwpe_sel` is memory-mapped in the control unit * NEureka `tcdm_weight` port is not used * Additional tweaks are likely needed --- rtl/cluster_peripherals.sv | 4 +- rtl/hwpe_subsystem.sv | 183 +++++++++++++++++++++++++++++++------ rtl/pulp_cluster.sv | 11 ++- 3 files changed, 167 insertions(+), 31 deletions(-) diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index 6bd45bde..943426dd 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -93,12 +93,13 @@ module cluster_peripherals // SRAM SPEED REGULATION --> TCDM output logic [1:0] TCDM_arb_policy_o, - + XBAR_PERIPH_BUS.Master hwpe_cfg_master, XBAR_PERIPH_BUS.Master hmr_cfg_master, XBAR_PERIPH_BUS.Master tcdm_scrubber_cfg_master, input logic [NB_CORES-1:0][3:0] hwpe_events_i, output logic hwpe_en_o, + output logic hwpe_sel_o, output hci_package::hci_interconnect_ctrl_t hci_ctrl_o, // Control ports @@ -182,6 +183,7 @@ module cluster_peripherals // SRAM SPEED REGULATION --> TCDM .hwpe_en_o ( hwpe_en_o ), + .hwpe_sel_o ( hwpe_sel_o ), .hci_ctrl_o ( hci_ctrl_o ), .fregfile_disable_o ( fregfile_disable_o ), diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index 9c5cb717..39da2e34 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -18,23 +18,31 @@ import hci_package::*; module hwpe_subsystem #( parameter N_CORES = 8, + parameter N_HWPES = 1, parameter N_MASTER_PORT = 9, parameter ID_WIDTH = 8, - parameter USE_RBE = 0 + parameter USE_RBE = 0, + parameter DW = DEFAULT_DW, + parameter AW = DEFAULT_AW, + parameter OW = AW ) ( - input logic clk, - input logic rst_n, - input logic test_mode, - input logic hwpe_en_i, - - hci_core_intf.master hwpe_xbar_master, - XBAR_PERIPH_BUS.Slave hwpe_cfg_slave, - - output logic [N_CORES-1:0][1:0] evt_o, - output logic busy_o + input logic clk, + input logic rst_n, + input logic test_mode, + input logic hwpe_en_i, + input logic [$clog2(N_HWPES)-1:0] hwpe_sel_i, + + hci_core_intf.master hwpe_xbar_master, + XBAR_PERIPH_BUS.Slave hwpe_cfg_slave, + + output logic [N_CORES-1:0][1:0] evt_o, + output logic busy_o ); + logic [N_HWPES-1:0] busy; + logic [N_HWPES-1:0][N_CORES-1:0][1:0] evt; + logic hwpe_clk; tc_clk_gating i_hwpe_clock_gate ( @@ -46,10 +54,22 @@ module hwpe_subsystem hwpe_ctrl_intf_periph #( .ID_WIDTH ( ID_WIDTH ) - ) periph ( + ) periph [N_HWPES-1:0] ( .clk ( hwpe_clk ) ); + hci_core_intf #( + .DW ( DW ), + .AW ( AW ), + .OW ( OW ) + ) tcdm [N_HWPES-1:0] ( + .clk ( clk_i ) + ); + + ///////////// + // REDMULE // + ///////////// + redmule_top #( .ID_WIDTH ( ID_WIDTH ), .N_CORES ( N_CORES ), @@ -58,24 +78,131 @@ module hwpe_subsystem .clk_i ( hwpe_clk ), .rst_ni ( rst_n ), .test_mode_i ( test_mode ), - .busy_o ( busy_o ), - .evt_o ( evt_o ), - .tcdm ( hwpe_xbar_master ), - .periph ( periph ) + .busy_o ( busy[0] ), + .evt_o ( evt[0] ), + .tcdm ( tcdm[0] ), + .periph ( periph[0] ) + ); + + ///////////// + // NEUREKA // + ///////////// + + hci_core_intf #( + .DW ( DW ), + .AW ( AW ), + .OW ( OW ) + ) unused_tcdm ( + .clk ( clk_i ) + ); + + // TODO: specify params in package + neureka_top #( + .ID ( ID_WIDTH ), + .BW ( N_MASTER_PORT*32 ), + .N_CORES ( N_CORES ) + ) i_neureka ( + // global signals + .clk_i ( hwpe_clk ), + .rst_ni ( rst_n ), + .test_mode_i ( test_mode ), + // events + .evt_o ( evt[1] ), + .busy_o ( busy[1] ), + // tcdm master ports + .tcdm ( tcdm[1] ), + .tcdm_weight ( unused_tcdm ), + // periph slave port + .periph ( periph[1] ) ); - always_comb - begin - periph.req = hwpe_cfg_slave.req; - periph.add = hwpe_cfg_slave.add; - periph.wen = hwpe_cfg_slave.wen; - periph.be = hwpe_cfg_slave.be; - periph.data = hwpe_cfg_slave.wdata; - periph.id = hwpe_cfg_slave.id; + // Bind unused target signals of tcdm_weight port + assign unused_tcdm.gnt = 1'b1; // To be sure that unwanted reqs get granted nevertheless + assign unused_tcdm.r_data = '0; + assign unused_tcdm.r_valid = '0; + assign unused_tcdm.r_opc = '0; + assign unused_tcdm.r_user = '0; + + ////////////////// + // HWPE CFG BUS // + ////////////////// + + // Initiator signals decoded according to `hwpe_sel_i` + for (genvar i = 0; i < N_HWPES; i++) begin + always_comb begin + periph[i].req = (hwpe_sel_i == i) ? hwpe_cfg_slave.req : '0; + periph[i].add = (hwpe_sel_i == i) ? hwpe_cfg_slave.add : '0; + periph[i].wen = (hwpe_sel_i == i) ? hwpe_cfg_slave.wen : '0; + periph[i].be = (hwpe_sel_i == i) ? hwpe_cfg_slave.be : '0; + periph[i].data = (hwpe_sel_i == i) ? hwpe_cfg_slave.wdata : '0; + periph[i].id = (hwpe_sel_i == i) ? hwpe_cfg_slave.id : '0; + end + end + + // Target signals muxed according to `hwpe_sel_i` + logic [N_HWPES-1:0] periph_gnt; + logic [N_HWPES-1:0][31:0] periph_r_rdata; + logic [N_HWPES-1:0] periph_r_valid; + logic [N_HWPES-1:0][ID_WIDTH-1:0] periph_r_id; + + for (genvar i = 0; i < N_HWPES; i++) begin + assign periph_gnt [i] = periph[i].gnt; + assign periph_r_rdata [i] = periph[i].r_data; + assign periph_r_valid [i] = periph[i].r_valid; + assign periph_r_id [i] = periph[i].r_id; + end + + always_comb begin + hwpe_cfg_slave.gnt = periph_gnt [0]; + hwpe_cfg_slave.r_rdata = periph_r_rdata [0]; + hwpe_cfg_slave.r_valid = periph_r_valid [0]; + hwpe_cfg_slave.r_id = periph_r_id [0]; + for (int i = 1; i < N_HWPES; i++) begin + if (hwpe_sel_i == i) begin + hwpe_cfg_slave.gnt = periph_gnt [i]; + hwpe_cfg_slave.r_rdata = periph_r_rdata [i]; + hwpe_cfg_slave.r_valid = periph_r_valid [i]; + hwpe_cfg_slave.r_id = periph_r_id [i]; + end + end + end + + ////////////////////// + // HWPE XBAR MASTER // + ////////////////////// + + hci_core_mux_static #( + .NB_CHAN ( N_HWPES ), + .DW ( DW ), + .AW ( AW ), + .OW ( OW ) + ) i_hwpe_hci_mux ( + + /* Internally unused */ + .clk_i ( hwpe_clk ), + .rst_ni ( rst_n ), + .clear_i ( '0 ), + /*********************/ + + .sel_i ( hwpe_sel_i ), + + .in ( tcdm ), + .out ( hwpe_xbar_master ) +); + +////////////////// +// EVT AND BUSY // +////////////////// + +always_comb begin + evt_o = evt[0]; + busy_o = busy[0]; + for (int i = 1; i < N_HWPES; i++) begin + if (hwpe_sel_i == i) begin + evt_o = evt[i]; + busy_o = busy[i]; + end end - assign hwpe_cfg_slave.gnt = periph.gnt; - assign hwpe_cfg_slave.r_rdata = periph.r_data; - assign hwpe_cfg_slave.r_valid = periph.r_valid; - assign hwpe_cfg_slave.r_id = periph.r_id; +end endmodule diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 1887a00b..d10ed9ce 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -224,7 +224,8 @@ logic [Cfg.NumCores-1:0] dbg_core_halted; logic [Cfg.NumCores-1:0] dbg_core_havereset; logic [Cfg.NumCores-1:0] dbg_core_running; logic [Cfg.NumCores-1:0] s_dbg_irq; -logic s_hwpe_en; +logic s_hwpe_en; +logic s_hwpe_sel; logic fetch_en_synch; logic en_sa_boot_synch; @@ -782,6 +783,7 @@ cluster_peripherals #( .hwpe_cfg_master ( s_hwpe_cfg_bus ), .hwpe_events_i ( s_hwpe_remap_evt ), .hwpe_en_o ( s_hwpe_en ), + .hwpe_sel_o ( s_hwpe_sel ), .hci_ctrl_o ( s_hci_ctrl ), .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), @@ -1156,13 +1158,18 @@ generate if(Cfg.HwpePresent) begin: hwpe_gen hwpe_subsystem #( .N_CORES ( Cfg.NumCores ), + .N_HWPES ( 2 ), .N_MASTER_PORT ( Cfg.HwpeNumPorts ), - .ID_WIDTH ( Cfg.NumCores + Cfg.NumMstPeriphs ) + .ID_WIDTH ( Cfg.NumCores + Cfg.NumMstPeriphs ), + .DW ( Cfg.HwpeNumPorts * DataWidth ), + .AW ( AddrWidth ), + .OW ( 1 ) ) hwpe_subsystem_i ( .clk ( clk_i ), .rst_n ( rst_ni ), .test_mode ( test_mode_i ), .hwpe_en_i ( s_hwpe_en ), + .hwpe_sel_i ( s_hwpe_sel ), .hwpe_xbar_master ( s_hci_hwpe [0] ), .hwpe_cfg_slave ( s_hwpe_cfg_bus ), .evt_o ( s_hwpe_evt ), From e55a642d6a6f1ac80b1bd4edeb003c6e32ec4d6d Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Mon, 12 Feb 2024 17:40:52 +0100 Subject: [PATCH 128/207] Update dependencies to integrate NEureka * Update NEureka in `Bender.yml` * Development branches are included in `Bender.local` --- Bender.local | 3 +++ Bender.lock | 22 +++++++++++++++++++--- Bender.yml | 2 +- 3 files changed, 23 insertions(+), 4 deletions(-) diff --git a/Bender.local b/Bender.local index 5c808517..25b9b48c 100644 --- a/Bender.local +++ b/Bender.local @@ -3,3 +3,6 @@ overrides: register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic + cluster_peripherals : { git: "https://github.com/pulp-platform/cluster_peripherals.git" , rev: ab82a2c3e10b87b677932e0fa46fd93e6e5df547 } # branch: rt/neureka-redmule-integration + hwpe-ctrl : { git: "https://github.com/pulp-platform/hwpe-ctrl.git" , rev: a5966201aeeb988d607accdc55da933a53c6a56e } # branch: master + redmule : { git: "https://github.com/pulp-platform/redmule.git" , rev: 10363c973f987963f27227332c6c6638289f3f9c } # branch: rt/neureka-redmule-integration \ No newline at end of file diff --git a/Bender.lock b/Bender.lock index 5e1166de..7e491bea 100644 --- a/Bender.lock +++ b/Bender.lock @@ -45,7 +45,7 @@ packages: dependencies: - common_cells cluster_peripherals: - revision: c9defcfb4f4e8733383b28a451c430783c2febbd + revision: ab82a2c3e10b87b677932e0fa46fd93e6e5df547 version: null source: Git: https://github.com/pulp-platform/cluster_peripherals.git @@ -118,7 +118,7 @@ packages: - scm - tech_cells_generic hwpe-ctrl: - revision: b7857919ea14b586901ff4282ad7749a3d50501e + revision: a5966201aeeb988d607accdc55da933a53c6a56e version: null source: Git: https://github.com/pulp-platform/hwpe-ctrl.git @@ -167,6 +167,16 @@ packages: Git: https://github.com/pulp-platform/mchan.git dependencies: - common_cells + neureka: + revision: d9e4c3c38aa28b3149444840297100f7355ddc22 + version: null + source: + Git: https://github.com/pulp-platform/neureka.git + dependencies: + - hci + - hwpe-ctrl + - hwpe-stream + - zeroriscy per2axi: revision: 95bf23119b47fc171d9ed3734c431f71cffd9350 version: null @@ -175,7 +185,7 @@ packages: dependencies: - axi_slice redmule: - revision: 1b30b0b9a31afa702eb2d166d672ceda2f5d463a + revision: 10363c973f987963f27227332c6c6638289f3f9c version: null source: Git: https://github.com/pulp-platform/redmule.git @@ -235,3 +245,9 @@ packages: source: Git: https://github.com/pulp-platform/timer_unit.git dependencies: [] + zeroriscy: + revision: 8a6c00e899cb6c715dcd5a3a1a92263994fb634b + version: null + source: + Git: git@github.com:yvantor/ibex.git + dependencies: [] diff --git a/Bender.yml b/Bender.yml index a0d7e3f2..2d2e3c6b 100644 --- a/Bender.yml +++ b/Bender.yml @@ -34,7 +34,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 1b30b0b9a31afa702eb2d166d672ceda2f5d463a } # branch: astral - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: d9e4c3c38aa28b3149444840297100f7355ddc22 } # branch: astral + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: a002f52587418844fff60a2472bd834ffcd6af29 } # branch: astral export_include_dirs: - include From 4f0f4c75393979c0b55f9433bae6fd3669e3e41b Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Mon, 12 Feb 2024 19:25:00 +0100 Subject: [PATCH 129/207] Fix clock signal passed to HWPE tcdm interfaces --- rtl/hwpe_subsystem.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index 39da2e34..b5bbb1f7 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -63,7 +63,7 @@ module hwpe_subsystem .AW ( AW ), .OW ( OW ) ) tcdm [N_HWPES-1:0] ( - .clk ( clk_i ) + .clk ( hwpe_clk ) ); ///////////// From 8bf87479602dce5aabd7c904c3210aff2ac6225a Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Tue, 13 Feb 2024 10:21:10 +0100 Subject: [PATCH 130/207] Bump deps --- Bender.local | 2 -- Bender.lock | 4 ++-- Bender.yml | 2 +- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/Bender.local b/Bender.local index 25b9b48c..4802448f 100644 --- a/Bender.local +++ b/Bender.local @@ -4,5 +4,3 @@ overrides: cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic cluster_peripherals : { git: "https://github.com/pulp-platform/cluster_peripherals.git" , rev: ab82a2c3e10b87b677932e0fa46fd93e6e5df547 } # branch: rt/neureka-redmule-integration - hwpe-ctrl : { git: "https://github.com/pulp-platform/hwpe-ctrl.git" , rev: a5966201aeeb988d607accdc55da933a53c6a56e } # branch: master - redmule : { git: "https://github.com/pulp-platform/redmule.git" , rev: 10363c973f987963f27227332c6c6638289f3f9c } # branch: rt/neureka-redmule-integration \ No newline at end of file diff --git a/Bender.lock b/Bender.lock index 7e491bea..e40491d8 100644 --- a/Bender.lock +++ b/Bender.lock @@ -168,7 +168,7 @@ packages: dependencies: - common_cells neureka: - revision: d9e4c3c38aa28b3149444840297100f7355ddc22 + revision: a002f52587418844fff60a2472bd834ffcd6af29 version: null source: Git: https://github.com/pulp-platform/neureka.git @@ -185,7 +185,7 @@ packages: dependencies: - axi_slice redmule: - revision: 10363c973f987963f27227332c6c6638289f3f9c + revision: 68999ccc922b10a5043bb98f67aaf3d8d8d59f3f version: null source: Git: https://github.com/pulp-platform/redmule.git diff --git a/Bender.yml b/Bender.yml index 2d2e3c6b..8899e022 100644 --- a/Bender.yml +++ b/Bender.yml @@ -33,7 +33,7 @@ dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 1b30b0b9a31afa702eb2d166d672ceda2f5d463a } # branch: astral + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 68999ccc922b10a5043bb98f67aaf3d8d8d59f3f } # branch: astral neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: a002f52587418844fff60a2472bd834ffcd6af29 } # branch: astral export_include_dirs: From 7c56ddb96205709c4ccb217a7946057d5ac2db9f Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Wed, 14 Feb 2024 16:53:53 +0100 Subject: [PATCH 131/207] Add clock gating cells for each HWPE --- rtl/hwpe_subsystem.sv | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index b5bbb1f7..fef84ec7 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -43,28 +43,33 @@ module hwpe_subsystem logic [N_HWPES-1:0] busy; logic [N_HWPES-1:0][N_CORES-1:0][1:0] evt; - logic hwpe_clk; - - tc_clk_gating i_hwpe_clock_gate ( - .clk_i ( clk ), - .en_i ( hwpe_en_i ), - .test_en_i ( test_mode ), - .clk_o ( hwpe_clk ) - ); + logic [N_HWPES-1:0] hwpe_clk; + logic [N_HWPES-1:0] hwpe_en_int; hwpe_ctrl_intf_periph #( .ID_WIDTH ( ID_WIDTH ) - ) periph [N_HWPES-1:0] ( - .clk ( hwpe_clk ) - ); + ) periph [N_HWPES-1:0] (.clk()); hci_core_intf #( .DW ( DW ), .AW ( AW ), .OW ( OW ) - ) tcdm [N_HWPES-1:0] ( - .clk ( hwpe_clk ) - ); + ) tcdm [N_HWPES-1:0] (.clk()); + + for (genvar i = 0; i < N_HWPES; i++) begin + // HWPE specific enable + assign hwpe_en_int[i] = hwpe_en_i && (hwpe_sel_i == i); + // Clock gating cell + tc_clk_gating i_hwpe_clock_gate ( + .clk_i ( clk ), + .en_i ( hwpe_en_int[i] ), + .test_en_i ( test_mode ), + .clk_o ( hwpe_clk[i] ) + ); + // Interface clocks + assign periph[i].clk = hwpe_clk[i]; + assign tcdm[i].clk = hwpe_clk[i]; + end ///////////// // REDMULE // @@ -75,7 +80,7 @@ module hwpe_subsystem .N_CORES ( N_CORES ), .DW ( N_MASTER_PORT*32 ) ) i_redmule ( - .clk_i ( hwpe_clk ), + .clk_i ( hwpe_clk[0] ), .rst_ni ( rst_n ), .test_mode_i ( test_mode ), .busy_o ( busy[0] ), @@ -93,7 +98,7 @@ module hwpe_subsystem .AW ( AW ), .OW ( OW ) ) unused_tcdm ( - .clk ( clk_i ) + .clk ( hwpe_clk[1] ) ); // TODO: specify params in package @@ -103,7 +108,7 @@ module hwpe_subsystem .N_CORES ( N_CORES ) ) i_neureka ( // global signals - .clk_i ( hwpe_clk ), + .clk_i ( hwpe_clk[1] ), .rst_ni ( rst_n ), .test_mode_i ( test_mode ), // events @@ -179,7 +184,7 @@ module hwpe_subsystem ) i_hwpe_hci_mux ( /* Internally unused */ - .clk_i ( hwpe_clk ), + .clk_i ( clk ), .rst_ni ( rst_n ), .clear_i ( '0 ), /*********************/ From 678117ad44a4a9579d2c9075e96704c81c8fbfcb Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Wed, 28 Feb 2024 10:44:50 +0100 Subject: [PATCH 132/207] Align to latests changes in NEureka * Remove weight port * Bump WIP IPs version in the `Bender.local` --- Bender.local | 2 ++ Bender.lock | 4 ++-- rtl/hwpe_subsystem.sv | 28 +++++----------------------- 3 files changed, 9 insertions(+), 25 deletions(-) diff --git a/Bender.local b/Bender.local index 4802448f..e245c7d4 100644 --- a/Bender.local +++ b/Bender.local @@ -4,3 +4,5 @@ overrides: cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic cluster_peripherals : { git: "https://github.com/pulp-platform/cluster_peripherals.git" , rev: ab82a2c3e10b87b677932e0fa46fd93e6e5df547 } # branch: rt/neureka-redmule-integration + neureka : { git: "https://github.com/pulp-platform/neureka.git" , rev: 3131e87c40118f75e11a1ff9bae60fe764336a19 } # branch: astral-4x4 + hci : { git: "https://github.com/pulp-platform/hci.git" , rev: 9d266f61deff39e99d87350e671ace8909e696f4 } # branch: add-passthrough diff --git a/Bender.lock b/Bender.lock index e40491d8..1d97b7d5 100644 --- a/Bender.lock +++ b/Bender.lock @@ -97,7 +97,7 @@ packages: dependencies: - common_cells hci: - revision: 4823e503851eb7e8cc765a58621d767a01d6a77b + revision: 9d266f61deff39e99d87350e671ace8909e696f4 version: null source: Git: https://github.com/pulp-platform/hci.git @@ -168,7 +168,7 @@ packages: dependencies: - common_cells neureka: - revision: a002f52587418844fff60a2472bd834ffcd6af29 + revision: 3131e87c40118f75e11a1ff9bae60fe764336a19 version: null source: Git: https://github.com/pulp-platform/neureka.git diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index fef84ec7..bda7d20b 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -48,13 +48,13 @@ module hwpe_subsystem hwpe_ctrl_intf_periph #( .ID_WIDTH ( ID_WIDTH ) - ) periph [N_HWPES-1:0] (.clk()); + ) periph [N_HWPES-1:0] (.clk(clk)); hci_core_intf #( .DW ( DW ), .AW ( AW ), .OW ( OW ) - ) tcdm [N_HWPES-1:0] (.clk()); + ) tcdm [N_HWPES-1:0] (.clk(clk)); for (genvar i = 0; i < N_HWPES; i++) begin // HWPE specific enable @@ -66,9 +66,6 @@ module hwpe_subsystem .test_en_i ( test_mode ), .clk_o ( hwpe_clk[i] ) ); - // Interface clocks - assign periph[i].clk = hwpe_clk[i]; - assign tcdm[i].clk = hwpe_clk[i]; end ///////////// @@ -93,19 +90,12 @@ module hwpe_subsystem // NEUREKA // ///////////// - hci_core_intf #( - .DW ( DW ), - .AW ( AW ), - .OW ( OW ) - ) unused_tcdm ( - .clk ( hwpe_clk[1] ) - ); - // TODO: specify params in package neureka_top #( + .PE_H ( 4 ), + .PE_W ( 4 ), .ID ( ID_WIDTH ), - .BW ( N_MASTER_PORT*32 ), - .N_CORES ( N_CORES ) + .N_CORES ( N_CORES ) ) i_neureka ( // global signals .clk_i ( hwpe_clk[1] ), @@ -116,18 +106,10 @@ module hwpe_subsystem .busy_o ( busy[1] ), // tcdm master ports .tcdm ( tcdm[1] ), - .tcdm_weight ( unused_tcdm ), // periph slave port .periph ( periph[1] ) ); - // Bind unused target signals of tcdm_weight port - assign unused_tcdm.gnt = 1'b1; // To be sure that unwanted reqs get granted nevertheless - assign unused_tcdm.r_data = '0; - assign unused_tcdm.r_valid = '0; - assign unused_tcdm.r_opc = '0; - assign unused_tcdm.r_user = '0; - ////////////////// // HWPE CFG BUS // ////////////////// From 99ff7ac7b61303b54d6baa335607333cda38cc4c Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Wed, 28 Feb 2024 12:23:18 +0100 Subject: [PATCH 133/207] Remove unnecessary decoding of incoming HWPE signals --- rtl/hwpe_subsystem.sv | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index bda7d20b..9bcd4c42 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -114,15 +114,16 @@ module hwpe_subsystem // HWPE CFG BUS // ////////////////// - // Initiator signals decoded according to `hwpe_sel_i` for (genvar i = 0; i < N_HWPES; i++) begin always_comb begin - periph[i].req = (hwpe_sel_i == i) ? hwpe_cfg_slave.req : '0; - periph[i].add = (hwpe_sel_i == i) ? hwpe_cfg_slave.add : '0; - periph[i].wen = (hwpe_sel_i == i) ? hwpe_cfg_slave.wen : '0; - periph[i].be = (hwpe_sel_i == i) ? hwpe_cfg_slave.be : '0; - periph[i].data = (hwpe_sel_i == i) ? hwpe_cfg_slave.wdata : '0; - periph[i].id = (hwpe_sel_i == i) ? hwpe_cfg_slave.id : '0; + // Initiator signals decoded according to `hwpe_sel_i` + periph[i].req = (hwpe_sel_i == i) ? hwpe_cfg_slave.req : '0; + // No muxing needed + periph[i].add = hwpe_cfg_slave.add; + periph[i].wen = hwpe_cfg_slave.wen; + periph[i].be = hwpe_cfg_slave.be; + periph[i].data = hwpe_cfg_slave.wdata; + periph[i].id = hwpe_cfg_slave.id; end end From f968a7d0c08987a357db16c775faccd2e3a5206d Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Fri, 1 Mar 2024 09:54:41 +0100 Subject: [PATCH 134/207] Clean up and refactor code --- rtl/hwpe_subsystem.sv | 48 +++++++++++++++++-------------------------- 1 file changed, 19 insertions(+), 29 deletions(-) diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index 9bcd4c42..3d350f9d 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -90,7 +90,6 @@ module hwpe_subsystem // NEUREKA // ///////////// - // TODO: specify params in package neureka_top #( .PE_H ( 4 ), .PE_W ( 4 ), @@ -114,6 +113,12 @@ module hwpe_subsystem // HWPE CFG BUS // ////////////////// + // Target signals muxed according to `hwpe_sel_i` + logic [N_HWPES-1:0] periph_gnt; + logic [N_HWPES-1:0][31:0] periph_r_rdata; + logic [N_HWPES-1:0] periph_r_valid; + logic [N_HWPES-1:0][ID_WIDTH-1:0] periph_r_id; + for (genvar i = 0; i < N_HWPES; i++) begin always_comb begin // Initiator signals decoded according to `hwpe_sel_i` @@ -124,33 +129,33 @@ module hwpe_subsystem periph[i].be = hwpe_cfg_slave.be; periph[i].data = hwpe_cfg_slave.wdata; periph[i].id = hwpe_cfg_slave.id; + // Split interface signals into packed vectors + periph_gnt [i] = periph[i].gnt; + periph_r_rdata [i] = periph[i].r_data; + periph_r_valid [i] = periph[i].r_valid; + periph_r_id [i] = periph[i].r_id; end end - // Target signals muxed according to `hwpe_sel_i` - logic [N_HWPES-1:0] periph_gnt; - logic [N_HWPES-1:0][31:0] periph_r_rdata; - logic [N_HWPES-1:0] periph_r_valid; - logic [N_HWPES-1:0][ID_WIDTH-1:0] periph_r_id; - - for (genvar i = 0; i < N_HWPES; i++) begin - assign periph_gnt [i] = periph[i].gnt; - assign periph_r_rdata [i] = periph[i].r_data; - assign periph_r_valid [i] = periph[i].r_valid; - assign periph_r_id [i] = periph[i].r_id; - end - always_comb begin + // Config bus hwpe_cfg_slave.gnt = periph_gnt [0]; hwpe_cfg_slave.r_rdata = periph_r_rdata [0]; hwpe_cfg_slave.r_valid = periph_r_valid [0]; hwpe_cfg_slave.r_id = periph_r_id [0]; + // evt and busy + evt_o = evt[0]; + busy_o = busy[0]; for (int i = 1; i < N_HWPES; i++) begin if (hwpe_sel_i == i) begin + // Config bus hwpe_cfg_slave.gnt = periph_gnt [i]; hwpe_cfg_slave.r_rdata = periph_r_rdata [i]; hwpe_cfg_slave.r_valid = periph_r_valid [i]; hwpe_cfg_slave.r_id = periph_r_id [i]; + // evt and busy + evt_o = evt[i]; + busy_o = busy[i]; end end end @@ -178,19 +183,4 @@ module hwpe_subsystem .out ( hwpe_xbar_master ) ); -////////////////// -// EVT AND BUSY // -////////////////// - -always_comb begin - evt_o = evt[0]; - busy_o = busy[0]; - for (int i = 1; i < N_HWPES; i++) begin - if (hwpe_sel_i == i) begin - evt_o = evt[i]; - busy_o = busy[i]; - end - end -end - endmodule From e3cfd5669bf500b2e890942ab55d44c6a10d0b22 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Fri, 1 Mar 2024 12:05:25 +0100 Subject: [PATCH 135/207] Define parameter types in `hwpe_subsystem` --- rtl/hwpe_subsystem.sv | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index 3d350f9d..b777d08d 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -17,14 +17,13 @@ import hci_package::*; module hwpe_subsystem #( - parameter N_CORES = 8, - parameter N_HWPES = 1, - parameter N_MASTER_PORT = 9, - parameter ID_WIDTH = 8, - parameter USE_RBE = 0, - parameter DW = DEFAULT_DW, - parameter AW = DEFAULT_AW, - parameter OW = AW + parameter int unsigned N_CORES = 8, + parameter int unsigned N_HWPES = 1, + parameter int unsigned N_MASTER_PORT = 9, + parameter int unsigned ID_WIDTH = 8, + parameter int unsigned DW = DEFAULT_DW, + parameter int unsigned AW = DEFAULT_AW, + parameter int unsigned OW = AW ) ( input logic clk, From 8a6cf80d61628cdfd83daf9ebcf34cead8587441 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Mon, 4 Mar 2024 15:54:50 +0100 Subject: [PATCH 136/207] Make the `hwpe_subsystem` more customizable `HwpeCfg` is added to the `pulp_cluster_package` and a list of HWPEs can be passed to instantiate them. The corresponding selection ID is simply the position inside the list. `MAX_NUM_HWPES` sets an upper limit to the number of HWPEs to comply with the packed nature of the `Cfg` data structure. --- Bender.local | 6 +- Bender.lock | 8 +- packages/pulp_cluster_package.sv | 16 ++++ rtl/cluster_peripherals.sv | 4 +- rtl/hwpe_subsystem.sv | 144 +++++++++++++++++-------------- rtl/pulp_cluster.sv | 5 +- tb/pulp_cluster_tb.sv | 1 + 7 files changed, 111 insertions(+), 73 deletions(-) diff --git a/Bender.local b/Bender.local index e245c7d4..b52bb8e8 100644 --- a/Bender.local +++ b/Bender.local @@ -3,6 +3,8 @@ overrides: register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic - cluster_peripherals : { git: "https://github.com/pulp-platform/cluster_peripherals.git" , rev: ab82a2c3e10b87b677932e0fa46fd93e6e5df547 } # branch: rt/neureka-redmule-integration + # WIPs, to be removed + cluster_peripherals : { git: "https://github.com/pulp-platform/cluster_peripherals.git" , rev: 8a9f62dafb5ec23c6cd361847ff0047e12befca4 } # branch: rt/neureka-redmule-integration neureka : { git: "https://github.com/pulp-platform/neureka.git" , rev: 3131e87c40118f75e11a1ff9bae60fe764336a19 } # branch: astral-4x4 - hci : { git: "https://github.com/pulp-platform/hci.git" , rev: 9d266f61deff39e99d87350e671ace8909e696f4 } # branch: add-passthrough + hci : { git: "https://github.com/pulp-platform/hci.git" , rev: e47627c20b33bcaf4842c1add81fb888b4f12a9d } # branch: master + hwpe-stream : { git: "https://github.com/pulp-platform/hwpe-stream.git" , rev: bcb4435f802add732f557dc7fa1c6b5dd8854458 } # branch: master \ No newline at end of file diff --git a/Bender.lock b/Bender.lock index 1d97b7d5..ac6827bd 100644 --- a/Bender.lock +++ b/Bender.lock @@ -45,7 +45,7 @@ packages: dependencies: - common_cells cluster_peripherals: - revision: ab82a2c3e10b87b677932e0fa46fd93e6e5df547 + revision: 8a9f62dafb5ec23c6cd361847ff0047e12befca4 version: null source: Git: https://github.com/pulp-platform/cluster_peripherals.git @@ -97,7 +97,7 @@ packages: dependencies: - common_cells hci: - revision: 9d266f61deff39e99d87350e671ace8909e696f4 + revision: e47627c20b33bcaf4842c1add81fb888b4f12a9d version: null source: Git: https://github.com/pulp-platform/hci.git @@ -125,8 +125,8 @@ packages: dependencies: - tech_cells_generic hwpe-stream: - revision: 4c2ef8c33a6e2a8c88127e2153013d4f2dc3f448 - version: 1.7.0 + revision: bcb4435f802add732f557dc7fa1c6b5dd8854458 + version: null source: Git: https://github.com/pulp-platform/hwpe-stream.git dependencies: diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 78662fea..d5f39097 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -30,6 +30,19 @@ package pulp_cluster_package; IBEX } core_type_e; + // HWPE type + typedef enum byte_t { + REDMULE, + NEUREKA + } hwpe_type_e; + + parameter MAX_NUM_HWPES = 8; + + typedef struct packed { + hwpe_type_e [MAX_NUM_HWPES-1:0] HwpeList; + byte_t NumHwpes; + } hwpe_subsystem_cfg_t; + // PULP cluster configuration typedef struct packed { // Type of core in the cluster @@ -60,6 +73,8 @@ package pulp_cluster_package; byte_t TcdmNumBank; // Enable HWPEs bit HwpePresent; + // HWPEs selection and ID map + hwpe_subsystem_cfg_t HwpeCfg; // Number of memory ports available for HWPEs byte_t HwpeNumPorts; // Number if I$ banks @@ -171,6 +186,7 @@ package pulp_cluster_package; TcdmSize: 64*1024, TcdmNumBank: 16, HwpePresent: 0, + HwpeCfg: '0, HwpeNumPorts: 0, iCacheNumBanks: 2, iCacheNumLines: 1, diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index 943426dd..0873c343 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -22,6 +22,7 @@ import pulp_cluster_package::*; module cluster_peripherals #( parameter NB_CORES = 8, + parameter NB_HWPES = 8, parameter NB_MPERIPHS = 1, parameter NB_CACHE_BANKS = 4, parameter NB_SPERIPHS = 8, @@ -99,7 +100,7 @@ module cluster_peripherals XBAR_PERIPH_BUS.Master tcdm_scrubber_cfg_master, input logic [NB_CORES-1:0][3:0] hwpe_events_i, output logic hwpe_en_o, - output logic hwpe_sel_o, + output logic [$clog2(NB_HWPES)-1:0] hwpe_sel_o, output hci_package::hci_interconnect_ctrl_t hci_ctrl_o, // Control ports @@ -163,6 +164,7 @@ module cluster_peripherals cluster_control_unit #( .PER_ID_WIDTH ( NB_CORES+NB_MPERIPHS ), .NB_CORES ( NB_CORES ), + .NB_HWPES ( NB_HWPES ), .ROM_BOOT_ADDR ( ROM_BOOT_ADDR ), .BOOT_ADDR ( BOOT_ADDR ) //.NB_L1_CUTS ( NB_L1_CUTS ), diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index b777d08d..24e8db01 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -14,37 +14,44 @@ */ import hci_package::*; +import pulp_cluster_package::*; module hwpe_subsystem #( - parameter int unsigned N_CORES = 8, - parameter int unsigned N_HWPES = 1, - parameter int unsigned N_MASTER_PORT = 9, - parameter int unsigned ID_WIDTH = 8, - parameter int unsigned DW = DEFAULT_DW, - parameter int unsigned AW = DEFAULT_AW, - parameter int unsigned OW = AW + parameter hwpe_subsystem_cfg_t HWPE_CFG = '0, + parameter int unsigned N_CORES = 8, + parameter int unsigned N_MASTER_PORT = 9, + parameter int unsigned ID_WIDTH = 8, + parameter int unsigned DW = DEFAULT_DW, + parameter int unsigned AW = DEFAULT_AW, + parameter int unsigned OW = AW ) ( - input logic clk, - input logic rst_n, - input logic test_mode, - input logic hwpe_en_i, - input logic [$clog2(N_HWPES)-1:0] hwpe_sel_i, + input logic clk, + input logic rst_n, + input logic test_mode, + input logic hwpe_en_i, + input logic [$clog2(MAX_NUM_HWPES)-1:0] hwpe_sel_i, - hci_core_intf.master hwpe_xbar_master, - XBAR_PERIPH_BUS.Slave hwpe_cfg_slave, + hci_core_intf.master hwpe_xbar_master, + XBAR_PERIPH_BUS.Slave hwpe_cfg_slave, - output logic [N_CORES-1:0][1:0] evt_o, - output logic busy_o + output logic [N_CORES-1:0][1:0] evt_o, + output logic busy_o ); + localparam int unsigned N_HWPES = HWPE_CFG.NumHwpes; + logic [N_HWPES-1:0] busy; logic [N_HWPES-1:0][N_CORES-1:0][1:0] evt; logic [N_HWPES-1:0] hwpe_clk; logic [N_HWPES-1:0] hwpe_en_int; + logic [$clog2(N_HWPES)-1:0] hwpe_sel_int; + + assign hwpe_sel_int = hwpe_sel_i[0+:$clog2(N_HWPES)]; + hwpe_ctrl_intf_periph #( .ID_WIDTH ( ID_WIDTH ) ) periph [N_HWPES-1:0] (.clk(clk)); @@ -55,9 +62,11 @@ module hwpe_subsystem .OW ( OW ) ) tcdm [N_HWPES-1:0] (.clk(clk)); - for (genvar i = 0; i < N_HWPES; i++) begin + for (genvar i = 0; i < N_HWPES; i++) begin : gen_hwpe + // HWPE specific enable - assign hwpe_en_int[i] = hwpe_en_i && (hwpe_sel_i == i); + assign hwpe_en_int[i] = hwpe_en_i && (hwpe_sel_int == i); + // Clock gating cell tc_clk_gating i_hwpe_clock_gate ( .clk_i ( clk ), @@ -65,54 +74,61 @@ module hwpe_subsystem .test_en_i ( test_mode ), .clk_o ( hwpe_clk[i] ) ); - end - ///////////// - // REDMULE // - ///////////// - - redmule_top #( - .ID_WIDTH ( ID_WIDTH ), - .N_CORES ( N_CORES ), - .DW ( N_MASTER_PORT*32 ) - ) i_redmule ( - .clk_i ( hwpe_clk[0] ), - .rst_ni ( rst_n ), - .test_mode_i ( test_mode ), - .busy_o ( busy[0] ), - .evt_o ( evt[0] ), - .tcdm ( tcdm[0] ), - .periph ( periph[0] ) - ); - - ///////////// - // NEUREKA // - ///////////// - - neureka_top #( - .PE_H ( 4 ), - .PE_W ( 4 ), - .ID ( ID_WIDTH ), - .N_CORES ( N_CORES ) - ) i_neureka ( - // global signals - .clk_i ( hwpe_clk[1] ), - .rst_ni ( rst_n ), - .test_mode_i ( test_mode ), - // events - .evt_o ( evt[1] ), - .busy_o ( busy[1] ), - // tcdm master ports - .tcdm ( tcdm[1] ), - // periph slave port - .periph ( periph[1] ) - ); + // Generate desired HWPEs + if (HWPE_CFG.HwpeList[i] == REDMULE) begin : gen_redmule + + ///////////// + // REDMULE // + ///////////// + + redmule_top #( + .ID_WIDTH ( ID_WIDTH ), + .N_CORES ( N_CORES ), + .DW ( N_MASTER_PORT*32 ) + ) i_redmule ( + .clk_i ( hwpe_clk[i] ), + .rst_ni ( rst_n ), + .test_mode_i ( test_mode ), + .busy_o ( busy[i] ), + .evt_o ( evt[i] ), + .tcdm ( tcdm[i] ), + .periph ( periph[i] ) + ); + + end else if (HWPE_CFG.HwpeList[i] == NEUREKA) begin : gen_neureka + + ///////////// + // NEUREKA // + ///////////// + + neureka_top #( + .PE_H ( 4 ), + .PE_W ( 4 ), + .ID ( ID_WIDTH ), + .N_CORES ( N_CORES ) + ) i_neureka ( + // global signals + .clk_i ( hwpe_clk[i] ), + .rst_ni ( rst_n ), + .test_mode_i ( test_mode ), + // events + .evt_o ( evt[i] ), + .busy_o ( busy[i] ), + // tcdm master ports + .tcdm ( tcdm[i] ), + // periph slave port + .periph ( periph[i] ) + ); + + end + end ////////////////// // HWPE CFG BUS // ////////////////// - // Target signals muxed according to `hwpe_sel_i` + // Target signals muxed according to `hwpe_sel_int` logic [N_HWPES-1:0] periph_gnt; logic [N_HWPES-1:0][31:0] periph_r_rdata; logic [N_HWPES-1:0] periph_r_valid; @@ -120,8 +136,8 @@ module hwpe_subsystem for (genvar i = 0; i < N_HWPES; i++) begin always_comb begin - // Initiator signals decoded according to `hwpe_sel_i` - periph[i].req = (hwpe_sel_i == i) ? hwpe_cfg_slave.req : '0; + // Initiator signals decoded according to `hwpe_sel_int` + periph[i].req = (hwpe_sel_int == i) ? hwpe_cfg_slave.req : '0; // No muxing needed periph[i].add = hwpe_cfg_slave.add; periph[i].wen = hwpe_cfg_slave.wen; @@ -146,7 +162,7 @@ module hwpe_subsystem evt_o = evt[0]; busy_o = busy[0]; for (int i = 1; i < N_HWPES; i++) begin - if (hwpe_sel_i == i) begin + if (hwpe_sel_int == i) begin // Config bus hwpe_cfg_slave.gnt = periph_gnt [i]; hwpe_cfg_slave.r_rdata = periph_r_rdata [i]; @@ -176,7 +192,7 @@ module hwpe_subsystem .clear_i ( '0 ), /*********************/ - .sel_i ( hwpe_sel_i ), + .sel_i ( hwpe_sel_int ), .in ( tcdm ), .out ( hwpe_xbar_master ) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index d10ed9ce..a9567b43 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -225,7 +225,7 @@ logic [Cfg.NumCores-1:0] dbg_core_havereset; logic [Cfg.NumCores-1:0] dbg_core_running; logic [Cfg.NumCores-1:0] s_dbg_irq; logic s_hwpe_en; -logic s_hwpe_sel; +logic [$clog2(MAX_NUM_HWPES)-1:0] s_hwpe_sel; logic fetch_en_synch; logic en_sa_boot_synch; @@ -710,6 +710,7 @@ cluster_interconnect_wrap #( //*************************************************** cluster_peripherals #( .NB_CORES ( Cfg.NumCores ), + .NB_HWPES ( MAX_NUM_HWPES ), .NB_MPERIPHS ( Cfg.NumMstPeriphs ), .NB_CACHE_BANKS ( Cfg.iCacheNumBanks), .NB_SPERIPHS ( Cfg.NumSlvPeriphs ), @@ -1157,8 +1158,8 @@ endgenerate generate if(Cfg.HwpePresent) begin: hwpe_gen hwpe_subsystem #( + .HWPE_CFG ( Cfg.HwpeCfg ), .N_CORES ( Cfg.NumCores ), - .N_HWPES ( 2 ), .N_MASTER_PORT ( Cfg.HwpeNumPorts ), .ID_WIDTH ( Cfg.NumCores + Cfg.NumMstPeriphs ), .DW ( Cfg.HwpeNumPorts * DataWidth ), diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 19fb6c86..3f28caaa 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -289,6 +289,7 @@ module pulp_cluster_tb; TcdmSize: 256*1024, TcdmNumBank: 16, HwpePresent: 1, + HwpeCfg: '{NumHwpes: 2, HwpeList: {NEUREKA, REDMULE}}, HwpeNumPorts: 9, iCacheNumBanks: 2, iCacheNumLines: 1, From 434b3ac46c0c6647fc78904e633c57a6d5f63f78 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Mon, 4 Mar 2024 16:00:00 +0100 Subject: [PATCH 137/207] Clean up whitespaces --- rtl/cluster_peripherals.sv | 44 +++++----- rtl/pulp_cluster.sv | 164 ++++++++++++++++++------------------- tb/pulp_cluster_tb.sv | 58 ++++++------- 3 files changed, 133 insertions(+), 133 deletions(-) diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index 0873c343..bed5b72d 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -53,7 +53,7 @@ module cluster_peripherals output logic busy_o, - XBAR_PERIPH_BUS.Slave speriph_slave[NB_SPERIPHS-2:0], // SPER_EXT_ID NOT PLUGGED HERE + XBAR_PERIPH_BUS.Slave speriph_slave[NB_SPERIPHS-2:0], // SPER_EXT_ID NOT PLUGGED HERE XBAR_PERIPH_BUS.Slave core_eu_direct_link[NB_CORES-1:0], input logic [NB_CORES-1:0] dma_event_i, @@ -63,14 +63,14 @@ module cluster_peripherals XBAR_PERIPH_BUS.Master dma_cfg_master[1:0], input logic dma_cl_event_i, input logic dma_cl_irq_i, - + input logic dma_fc_event_i, input logic dma_fc_irq_i, - + output logic soc_periph_evt_ready_o, input logic soc_periph_evt_valid_i, input logic [EVNT_WIDTH-1:0] soc_periph_evt_data_i, - + input logic [NB_CORES-1:0] dbg_core_halted_i, output logic [NB_CORES-1:0] dbg_core_halt_o, @@ -108,20 +108,20 @@ module cluster_peripherals PRI_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_pri[NB_CORES-1:0], output logic [NB_CORES-1:0] enable_l1_l15_prefetch_o ); - + logic s_timer_out_lo_event; logic s_timer_out_hi_event; logic s_timer_in_lo_event; logic s_timer_in_hi_event; - + logic [NB_CORES-1:0][31:0] s_cluster_events; logic [NB_CORES-1:0][3:0] s_acc_events; logic [NB_CORES-1:0][1:0] s_timer_events; logic [NB_CORES-1:0][1:0] s_dma_events; - + logic [NB_CORES-1:0] s_fetch_en_cc; - MESSAGE_BUS eu_message_master(); + MESSAGE_BUS eu_message_master(); logic [NB_SPERIPH_PLUGS_EU-1:0] eu_speriph_plug_req; logic [NB_SPERIPH_PLUGS_EU-1:0][31:0] eu_speriph_plug_add; @@ -132,7 +132,7 @@ module cluster_peripherals logic soc_periph_evt_valid, soc_periph_evt_ready; logic [7:0] soc_periph_evt_data; - + // internal speriph bus to combine multiple plugs to new event unit XBAR_PERIPH_BUS speriph_slave_eu_comb(); @@ -141,7 +141,7 @@ module cluster_peripherals `else localparam bit FEATURE_STAT = 1'b0; `endif - + // decide between common or core-specific event sources generate for (genvar I=0; I ext AXI_BUS #( @@ -466,7 +466,7 @@ AXI_BUS #( .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), .AXI_ID_WIDTH ( AxiIdInWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) -) s_core_ext_bus(); +) s_core_ext_bus(); // DMA -> ext AXI_BUS #( @@ -474,7 +474,7 @@ AXI_BUS #( .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), .AXI_ID_WIDTH ( AxiIdInWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) -) s_dma_ext_bus(); +) s_dma_ext_bus(); // ext -> axi2mem AXI_BUS #( @@ -482,9 +482,9 @@ AXI_BUS #( .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), .AXI_ID_WIDTH ( AxiIdOutWidth ), .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) -) s_ext_tcdm_bus(); +) s_ext_tcdm_bus(); -// cluster bus -> axi2per +// cluster bus -> axi2per AXI_BUS #( .AXI_ADDR_WIDTH ( Cfg.AxiAddrWidth ), .AXI_DATA_WIDTH ( Cfg.AxiDataOutWidth ), @@ -593,7 +593,7 @@ per2axi_wrap #( //*************************************************** /* cluster (log + periph) interconnect and attached peripherals */ -//*************************************************** +//*************************************************** cluster_interconnect_wrap #( .NB_CORES ( Cfg.NumCores ), @@ -640,7 +640,7 @@ cluster_interconnect_wrap #( //*************************************************** //*********************DMAC WRAP********************* -//*************************************************** +//*************************************************** `ifdef TARGET_MCHAN dmac_wrap #( .NB_CTRLS ( Cfg.NumCores + 2 ), @@ -777,10 +777,10 @@ cluster_peripherals #( .hmr_sw_resynch_req_i ( hmr_dmr_sw_resynch_req | hmr_tmr_sw_resynch_req ), .hmr_sw_synch_req_i ( hmr_dmr_sw_synch_req | hmr_tmr_sw_synch_req ), - .fregfile_disable_o ( s_fregfile_disable ), - + .fregfile_disable_o ( s_fregfile_disable ), + .TCDM_arb_policy_o ( s_TCDM_arb_policy ), - + .hwpe_cfg_master ( s_hwpe_cfg_bus ), .hwpe_events_i ( s_hwpe_remap_evt ), .hwpe_en_o ( s_hwpe_en ), @@ -897,7 +897,7 @@ generate .irq_ack_o ( core2hmr[i].irq_ack ), .test_mode_i ( test_mode_i ), .core_busy_o ( core2hmr[i].core_busy ), - //instruction cache bind + //instruction cache bind .instr_req_o ( core2hmr[i].instr_req ), .instr_gnt_i ( hmr2core[i].instr_gnt ), .instr_addr_o ( core2hmr[i].instr_addr ), @@ -1384,7 +1384,7 @@ tcdm_banks_wrap #( .tcdm_slave ( s_tcdm_bus_sram ) //PMU ?? ); -/* AXI interconnect infrastructure (slices, size conversion) */ +/* AXI interconnect infrastructure (slices, size conversion) */ //******************************************************** //**************** AXI REGISTER SLICES ******************* //******************************************************** @@ -1521,34 +1521,34 @@ axi_cdc_src #( .LogDepth ( Cfg.AxiCdcLogDepth ), .SyncStages ( Cfg.AxiCdcSyncStages ) ) axi_master_cdc_i ( - .src_rst_ni ( pwr_on_rst_ni ), - .src_clk_i ( clk_i ), - .src_req_i ( src_req ), - .src_resp_o ( src_resp ), - .async_data_master_aw_wptr_o ( async_data_master_aw_wptr_o ), - .async_data_master_aw_rptr_i ( async_data_master_aw_rptr_i ), - .async_data_master_aw_data_o ( async_data_master_aw_data_o ), - .async_data_master_w_wptr_o ( async_data_master_w_wptr_o ), - .async_data_master_w_rptr_i ( async_data_master_w_rptr_i ), - .async_data_master_w_data_o ( async_data_master_w_data_o ), - .async_data_master_ar_wptr_o ( async_data_master_ar_wptr_o ), - .async_data_master_ar_rptr_i ( async_data_master_ar_rptr_i ), - .async_data_master_ar_data_o ( async_data_master_ar_data_o ), - .async_data_master_b_wptr_i ( async_data_master_b_wptr_i ), - .async_data_master_b_rptr_o ( async_data_master_b_rptr_o ), - .async_data_master_b_data_i ( async_data_master_b_data_i ), - .async_data_master_r_wptr_i ( async_data_master_r_wptr_i ), - .async_data_master_r_rptr_o ( async_data_master_r_rptr_o ), - .async_data_master_r_data_i ( async_data_master_r_data_i ) + .src_rst_ni ( pwr_on_rst_ni ), + .src_clk_i ( clk_i ), + .src_req_i ( src_req ), + .src_resp_o ( src_resp ), + .async_data_master_aw_wptr_o ( async_data_master_aw_wptr_o ), + .async_data_master_aw_rptr_i ( async_data_master_aw_rptr_i ), + .async_data_master_aw_data_o ( async_data_master_aw_data_o ), + .async_data_master_w_wptr_o ( async_data_master_w_wptr_o ), + .async_data_master_w_rptr_i ( async_data_master_w_rptr_i ), + .async_data_master_w_data_o ( async_data_master_w_data_o ), + .async_data_master_ar_wptr_o ( async_data_master_ar_wptr_o ), + .async_data_master_ar_rptr_i ( async_data_master_ar_rptr_i ), + .async_data_master_ar_data_o ( async_data_master_ar_data_o ), + .async_data_master_b_wptr_i ( async_data_master_b_wptr_i ), + .async_data_master_b_rptr_o ( async_data_master_b_rptr_o ), + .async_data_master_b_data_i ( async_data_master_b_data_i ), + .async_data_master_r_wptr_i ( async_data_master_r_wptr_i ), + .async_data_master_r_rptr_o ( async_data_master_r_rptr_o ), + .async_data_master_r_data_i ( async_data_master_r_data_i ) ); - + // SOC TO CLUSTER `AXI_TYPEDEF_AW_CHAN_T(s2c_aw_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) `AXI_TYPEDEF_W_CHAN_T(s2c_w_chan_t,logic[Cfg.AxiDataInWidth-1:0],logic[Cfg.AxiDataInWidth/8-1:0],logic[Cfg.AxiUserWidth-1:0]) `AXI_TYPEDEF_B_CHAN_T(s2c_b_chan_t,logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) `AXI_TYPEDEF_AR_CHAN_T(s2c_ar_chan_t,logic[Cfg.AxiAddrWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) `AXI_TYPEDEF_R_CHAN_T(s2c_r_chan_t,logic[Cfg.AxiDataInWidth-1:0],logic[Cfg.AxiIdInWidth-1:0],logic[Cfg.AxiUserWidth-1:0]) - + `AXI_TYPEDEF_REQ_T(s2c_req_t,s2c_aw_chan_t,s2c_w_chan_t,s2c_ar_chan_t) `AXI_TYPEDEF_RESP_T(s2c_resp_t,s2c_b_chan_t,s2c_r_chan_t) @@ -1566,25 +1566,25 @@ axi_cdc_dst #( .LogDepth ( Cfg.AxiCdcLogDepth ), .SyncStages ( Cfg.AxiCdcSyncStages ) ) axi_slave_cdc_i ( - .dst_rst_ni ( pwr_on_rst_ni ), - .dst_clk_i ( clk_i ), - .dst_req_o ( dst_req ), - .dst_resp_i ( dst_resp ), - .async_data_slave_aw_wptr_i ( async_data_slave_aw_wptr_i ), - .async_data_slave_aw_rptr_o ( async_data_slave_aw_rptr_o ), - .async_data_slave_aw_data_i ( async_data_slave_aw_data_i ), - .async_data_slave_w_wptr_i ( async_data_slave_w_wptr_i ), - .async_data_slave_w_rptr_o ( async_data_slave_w_rptr_o ), - .async_data_slave_w_data_i ( async_data_slave_w_data_i ), - .async_data_slave_ar_wptr_i ( async_data_slave_ar_wptr_i ), - .async_data_slave_ar_rptr_o ( async_data_slave_ar_rptr_o ), - .async_data_slave_ar_data_i ( async_data_slave_ar_data_i ), - .async_data_slave_b_wptr_o ( async_data_slave_b_wptr_o ), - .async_data_slave_b_rptr_i ( async_data_slave_b_rptr_i ), - .async_data_slave_b_data_o ( async_data_slave_b_data_o ), - .async_data_slave_r_wptr_o ( async_data_slave_r_wptr_o ), - .async_data_slave_r_rptr_i ( async_data_slave_r_rptr_i ), - .async_data_slave_r_data_o ( async_data_slave_r_data_o ) + .dst_rst_ni ( pwr_on_rst_ni ), + .dst_clk_i ( clk_i ), + .dst_req_o ( dst_req ), + .dst_resp_i ( dst_resp ), + .async_data_slave_aw_wptr_i ( async_data_slave_aw_wptr_i ), + .async_data_slave_aw_rptr_o ( async_data_slave_aw_rptr_o ), + .async_data_slave_aw_data_i ( async_data_slave_aw_data_i ), + .async_data_slave_w_wptr_i ( async_data_slave_w_wptr_i ), + .async_data_slave_w_rptr_o ( async_data_slave_w_rptr_o ), + .async_data_slave_w_data_i ( async_data_slave_w_data_i ), + .async_data_slave_ar_wptr_i ( async_data_slave_ar_wptr_i ), + .async_data_slave_ar_rptr_o ( async_data_slave_ar_rptr_o ), + .async_data_slave_ar_data_i ( async_data_slave_ar_data_i ), + .async_data_slave_b_wptr_o ( async_data_slave_b_wptr_o ), + .async_data_slave_b_rptr_i ( async_data_slave_b_rptr_i ), + .async_data_slave_b_data_o ( async_data_slave_b_data_o ), + .async_data_slave_r_wptr_o ( async_data_slave_r_wptr_o ), + .async_data_slave_r_rptr_i ( async_data_slave_r_rptr_i ), + .async_data_slave_r_data_o ( async_data_slave_r_data_o ) ); // If the AXI ID width of the subordinate port does not match the one required, we interpose @@ -1662,9 +1662,9 @@ cdc_fifo_gray_dst #( (* async *) .async_data_i ( async_cluster_events_data_i ), (* async *) .async_wptr_i ( async_cluster_events_wptr_i ), (* async *) .async_rptr_o ( async_cluster_events_rptr_o ) -); +); assign s_events_async = s_events_valid; - + edge_propagator_tx ep_dma_pe_evt_i ( .clk_i ( clk_i ), .rstn_i ( rst_ni ), @@ -1672,7 +1672,7 @@ edge_propagator_tx ep_dma_pe_evt_i ( .ack_i ( dma_pe_evt_ack_i ), .valid_o ( dma_pe_evt_valid_o ) ); - + edge_propagator_tx ep_dma_pe_irq_i ( .clk_i ( clk_i ), .rstn_i ( rst_ni ), diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 3f28caaa..f2bea30c 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -33,7 +33,7 @@ module pulp_cluster_tb; logic s_clk; logic s_rstn; logic s_rstn_cl; - + localparam time SYS_TCK = 8ns; localparam time SYS_TA = 2ns; localparam time SYS_TT = SYS_TCK - 2ns; @@ -45,7 +45,7 @@ module pulp_cluster_tb; .clk_o ( s_clk ), .rst_no ( s_rstn ) ); - + localparam AxiAw = 48; localparam AxiDw = 64; localparam AxiIw = 6; @@ -65,7 +65,7 @@ module pulp_cluster_tb; localparam bit[AxiAw-1:0] L2Size = 'h10000000; localparam bit[AxiAw-1:0] BootAddr = L2BaseAddr + 'h8080; localparam bit[AxiAw-1:0] ClustReturnInt = 'h50200100; - + typedef logic [AxiAw-1:0] axi_addr_t; typedef logic [AxiDw-1:0] axi_data_t; typedef logic [AxiDw/8-1:0] axi_strb_t; @@ -86,20 +86,20 @@ module pulp_cluster_tb; `AXI_TYPEDEF_AR_CHAN_T(ar_m_chan_t, axi_addr_t, axi_m_id_t, axi_user_t) `AXI_TYPEDEF_R_CHAN_T(r_m_chan_t, axi_data_t, axi_m_id_t, axi_user_t) `AXI_TYPEDEF_REQ_T(axi_m_req_t, aw_m_chan_t, w_chan_t, ar_m_chan_t) - `AXI_TYPEDEF_RESP_T(axi_m_resp_t, b_m_chan_t, r_m_chan_t) + `AXI_TYPEDEF_RESP_T(axi_m_resp_t, b_m_chan_t, r_m_chan_t) typedef logic [AxiAw-1:0] addr_t; - typedef logic [AxiDw-1:0] data_t; + typedef logic [AxiDw-1:0] data_t; data_t memory [bit [31:0]]; int sections [bit [31:0]]; - + string binary ; - + logic s_cluster_en_sa_boot ; logic s_cluster_fetch_en ; logic s_cluster_eoc ; logic s_cluster_busy ; - + AXI_BUS #( .AXI_ADDR_WIDTH( AxiAw ), .AXI_DATA_WIDTH( AxiDw ), @@ -140,10 +140,10 @@ module pulp_cluster_tb; // Behavioural slaves axi_m_req_t axi_memreq; axi_m_resp_t axi_memrsp; - + `AXI_ASSIGN_TO_REQ(axi_memreq, axi_master[1]) `AXI_ASSIGN_FROM_RESP(axi_master[1], axi_memrsp) - + axi_sim_mem #( .AddrWidth ( AxiAw ), .DataWidth ( AxiDw ), @@ -152,7 +152,7 @@ module pulp_cluster_tb; .axi_req_t ( axi_m_req_t ), .axi_rsp_t ( axi_m_resp_t ), .ApplDelay ( SYS_TA ), - .AcqDelay ( SYS_TT ) + .AcqDelay ( SYS_TT ) ) sim_mem ( .clk_i ( s_clk ), .rst_ni ( s_rstn ), @@ -171,7 +171,7 @@ module pulp_cluster_tb; .test_i ( '0 ), .uart ( axi_master[0] ) ); - + // XBAR localparam int unsigned NumRules = NSlv+1; @@ -247,7 +247,7 @@ module pulp_cluster_tb; .slv ( axi_master[2] ), .mst ( soc_to_cluster_axi_bus ) ); - + axi_cdc_src_intf #( .AXI_ADDR_WIDTH ( AxiAw ), .AXI_DATA_WIDTH ( AxiDw ), @@ -260,7 +260,7 @@ module pulp_cluster_tb; .src ( soc_to_cluster_axi_bus ), .dst ( async_soc_to_cluster_axi_bus ) ); - + axi_cdc_dst_intf #( .AXI_ADDR_WIDTH ( AxiAw ), .AXI_DATA_WIDTH ( AxiDw ), @@ -347,7 +347,7 @@ module pulp_cluster_tb; .dma_pe_evt_ack_i ( '1 ), .dma_pe_evt_valid_o ( ), - + .dma_pe_irq_ack_i ( 1'b1 ), .dma_pe_irq_valid_o ( ), @@ -454,10 +454,10 @@ module pulp_cluster_tb; initial begin assign s_cluster_en_sa_boot = 1'b0; - assign s_cluster_fetch_en = 1'b0; + assign s_cluster_fetch_en = 1'b0; axi_master_drv.reset_master(); axi_master_drv.reset_slave(); - + @(posedge s_rstn); @(posedge s_clk); @@ -465,40 +465,40 @@ module pulp_cluster_tb; $display("[TB] Testing %s", binary); load_binary(binary); - + foreach (sections[addr]) begin $display("[TB] Writing %h with %0d words", addr << 3, sections[addr]); // word = 8 bytes here for (int i = 0; i < sections[addr]; i++) begin - + aw_beat.ax_addr = ( addr << 3 ) + ( i * 8 ); aw_beat.ax_len = '0; aw_beat.ax_burst = axi_pkg::BURST_INCR; aw_beat.ax_size = 4'h3; - + w_beat.w_data = memory[addr + i][63:0]; w_beat.w_strb = '1; w_beat.w_last = '1; - + axi_master_drv.send_aw(aw_beat); axi_master_drv.send_w(w_beat); @(posedge s_clk); axi_master_drv.recv_b(b_beat); end // for (int i = 0; i < sections[addr]; i++) - $display("[TB] Completed\n"); - end + $display("[TB] Completed\n"); + end $display("[TB] Initialize ret_val\n"); - + aw_beat.ax_addr = 32'h1A10_40A0; aw_beat.ax_len = '0; aw_beat.ax_burst = axi_pkg::BURST_INCR; aw_beat.ax_size = 4'h3; - + w_beat.w_data = '0; w_beat.w_strb = '1; w_beat.w_last = '1; - + axi_master_drv.send_aw(aw_beat); axi_master_drv.send_w(w_beat); @(posedge s_clk); @@ -544,7 +544,7 @@ module pulp_cluster_tb; ret_val = r_beat.r_data; $display("[TB] Received ret_val: %d\n", ret_val[30:0]); - + if(ret_val[30:0]==0) begin $display("[TB] Test passed\n"); $finish; @@ -553,6 +553,6 @@ module pulp_cluster_tb; end end - - + + endmodule : pulp_cluster_tb From 98b390571b04f694a003e4205f6abc0954c6c33b Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Wed, 27 Mar 2024 11:27:52 +0100 Subject: [PATCH 138/207] Bump deps --- Bender.local | 9 ++++----- Bender.lock | 8 ++++---- Bender.yml | 6 +++--- 3 files changed, 11 insertions(+), 12 deletions(-) diff --git a/Bender.local b/Bender.local index b52bb8e8..ff73c9f0 100644 --- a/Bender.local +++ b/Bender.local @@ -3,8 +3,7 @@ overrides: register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic - # WIPs, to be removed - cluster_peripherals : { git: "https://github.com/pulp-platform/cluster_peripherals.git" , rev: 8a9f62dafb5ec23c6cd361847ff0047e12befca4 } # branch: rt/neureka-redmule-integration - neureka : { git: "https://github.com/pulp-platform/neureka.git" , rev: 3131e87c40118f75e11a1ff9bae60fe764336a19 } # branch: astral-4x4 - hci : { git: "https://github.com/pulp-platform/hci.git" , rev: e47627c20b33bcaf4842c1add81fb888b4f12a9d } # branch: master - hwpe-stream : { git: "https://github.com/pulp-platform/hwpe-stream.git" , rev: bcb4435f802add732f557dc7fa1c6b5dd8854458 } # branch: master \ No newline at end of file + + # Temporarily left here to avoid conflicts + hwpe-stream : { git: "https://github.com/pulp-platform/hwpe-stream.git" , rev: 65c99a4a2f37a79acee800ab0151f67dfb1edef1 } # branch: master + hci : { git: "https://github.com/pulp-platform/hci.git", rev: e47627c20b33bcaf4842c1add81fb888b4f12a9d } diff --git a/Bender.lock b/Bender.lock index ac6827bd..ce81efc2 100644 --- a/Bender.lock +++ b/Bender.lock @@ -52,8 +52,8 @@ packages: dependencies: - hci common_cells: - revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f - version: 1.32.0 + revision: ad22699793d98ef714f120c6268fe92d096a61e1 + version: 1.33.1 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -125,8 +125,8 @@ packages: dependencies: - tech_cells_generic hwpe-stream: - revision: bcb4435f802add732f557dc7fa1c6b5dd8854458 - version: null + revision: 65c99a4a2f37a79acee800ab0151f67dfb1edef1 + version: 1.8.0 source: Git: https://github.com/pulp-platform/hwpe-stream.git dependencies: diff --git a/Bender.yml b/Bender.yml index 8899e022..72cffa32 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,7 +20,7 @@ dependencies: mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "2886cb2a46cea3e2bd2d979b505d88fadfbe150c" } # branch: astral - cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: c9defcfb4f4e8733383b28a451c430783c2febbd } # branch: astral + cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 8a9f62dafb5ec23c6cd361847ff0047e12befca4 } # branch: astral axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } @@ -29,12 +29,12 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: v1.1 } + hci: { git: "https://github.com/pulp-platform/hci.git", rev: e47627c20b33bcaf4842c1add81fb888b4f12a9d } register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 68999ccc922b10a5043bb98f67aaf3d8d8d59f3f } # branch: astral - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: a002f52587418844fff60a2472bd834ffcd6af29 } # branch: astral + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 3131e87c40118f75e11a1ff9bae60fe764336a19 } # branch: astral-4x4 export_include_dirs: - include From bf404ab5a5598343d0541d5313ffc658d1e39d82 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Wed, 27 Mar 2024 12:34:29 +0100 Subject: [PATCH 139/207] Update init target in Makefile --- Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a208087f..2e11d6b4 100644 --- a/Makefile +++ b/Makefile @@ -65,7 +65,8 @@ nonfree-init: .PHONY: init -init: checkout pulp-runtime regression-tests +init: checkout + git submodule update --init --recursive .PHONY: checkout scripts/compile.tcl ## Checkout/update dependencies using Bender From 6520e2cbe26af78f81dac24f41259005234c79c3 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Wed, 27 Mar 2024 12:55:21 +0100 Subject: [PATCH 140/207] Add neureka test to regression suite and CI --- Bender.lock | 7 ------- Makefile | 2 +- regression-tests | 2 +- 3 files changed, 2 insertions(+), 9 deletions(-) diff --git a/Bender.lock b/Bender.lock index ce81efc2..f3b9085f 100644 --- a/Bender.lock +++ b/Bender.lock @@ -176,7 +176,6 @@ packages: - hci - hwpe-ctrl - hwpe-stream - - zeroriscy per2axi: revision: 95bf23119b47fc171d9ed3734c431f71cffd9350 version: null @@ -245,9 +244,3 @@ packages: source: Git: https://github.com/pulp-platform/timer_unit.git dependencies: [] - zeroriscy: - revision: 8a6c00e899cb6c715dcd5a3a1a92263994fb634b - version: null - source: - Git: git@github.com:yvantor/ibex.git - dependencies: [] diff --git a/Makefile b/Makefile index 2e11d6b4..4e313741 100644 --- a/Makefile +++ b/Makefile @@ -53,7 +53,7 @@ endef ###################### NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git -NONFREE_COMMIT ?= 99ab7cf5e5c69e134ef84ad3304138f6fa105dd8 +NONFREE_COMMIT ?= fe360697bcfab4caba3ad463b42d4d27ff618c5a nonfree-init: git clone $(NONFREE_REMOTE) nonfree diff --git a/regression-tests b/regression-tests index ad3aeeff..1601f569 160000 --- a/regression-tests +++ b/regression-tests @@ -1 +1 @@ -Subproject commit ad3aeeff90e4b754805a14230a5c39157cc14f96 +Subproject commit 1601f5698d6255b7dfcde9e9ebf475cd259daf07 From 54120f47b2988a385f3f5ab544ac02ea3775eb5f Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Wed, 27 Mar 2024 15:04:30 +0100 Subject: [PATCH 141/207] Bump `register_interface` --- Bender.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index 72cffa32..ac4938ee 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating hci: { git: "https://github.com/pulp-platform/hci.git", rev: e47627c20b33bcaf4842c1add81fb888b4f12a9d } - register_interface: { git: "https://github.com/pulp-platform/register_interface.git", rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 68999ccc922b10a5043bb98f67aaf3d8d8d59f3f } # branch: astral From 9e73e9bfd6d9a16f7f92d81477d57cc8cfbe4fcf Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 23 Mar 2024 20:20:36 +0100 Subject: [PATCH 142/207] Add astral config. --- Makefile | 2 +- env/astral-env.sh | 23 +++++++++++++++++++++++ pulp-runtime | 2 +- regression-tests | 2 +- regression.mk | 10 ++++++---- tb/pulp_cluster_tb.sv | 6 +++--- 6 files changed, 35 insertions(+), 10 deletions(-) create mode 100644 env/astral-env.sh diff --git a/Makefile b/Makefile index 4e313741..295ff1e7 100644 --- a/Makefile +++ b/Makefile @@ -53,7 +53,7 @@ endef ###################### NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git -NONFREE_COMMIT ?= fe360697bcfab4caba3ad463b42d4d27ff618c5a +NONFREE_COMMIT ?= f7cf9949eae7cb7f7e3b3c30863996b67497bf17 nonfree-init: git clone $(NONFREE_REMOTE) nonfree diff --git a/env/astral-env.sh b/env/astral-env.sh new file mode 100644 index 00000000..411f39e4 --- /dev/null +++ b/env/astral-env.sh @@ -0,0 +1,23 @@ +# Copyright 2023 ETH Zurich and University of Bologna +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# set up environment variables for rtl simulation, pulp-runtime and freertos +ROOTD=$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")/.." && pwd) + +# If at IIS, set up appropriate questa version. +if test -f /etc/iis.version; then + export QUESTA=questa-2023.4-zr + export VLOG="$QUESTA vlog" + export VLIB="$QUESTA vlib" + export VMAP="$QUESTA vmap" + export VCOM="$QUESTA vcom" + export VOPT="$QUESTA vopt" + export VSIM="$QUESTA vsim" + export QUESTA_HOME=/usr/pack/${QUESTA}/questasim + export QUESTASIM_HOME=/usr/pack/${QUESTA}/questasim + export PULP_RUNTIME_GCC_TOOLCHAIN=/usr/pack/riscv-1.0-kgf/pulp-gcc-1.0.16 +fi + +source "$ROOTD/pulp-runtime/configs/astral-cluster.sh" +source "$ROOTD/scripts/vsim.sh" diff --git a/pulp-runtime b/pulp-runtime index 8b508dca..54a233a8 160000 --- a/pulp-runtime +++ b/pulp-runtime @@ -1 +1 @@ -Subproject commit 8b508dca78ee778e5def6ee6a3529b9877358bb7 +Subproject commit 54a233a83566a68436d0d68159d680277c2292a8 diff --git a/regression-tests b/regression-tests index 1601f569..126a1c56 160000 --- a/regression-tests +++ b/regression-tests @@ -1 +1 @@ -Subproject commit 1601f5698d6255b7dfcde9e9ebf475cd259daf07 +Subproject commit 126a1c56a6774d235f52b05ea1e3d5566606effd diff --git a/regression.mk b/regression.mk index 6364108f..2be2a08c 100644 --- a/regression.mk +++ b/regression.mk @@ -1,4 +1,6 @@ ## Clone regression tests for bare-metal verification +TARGET ?= astral + regression-tests: git submodule update --init --recursive $@ @@ -7,18 +9,18 @@ regression-tests: test-rt-par-bare: pulp-runtime regression-tests cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ -t 3600 --yaml --max-procs 2 \ - -o $(REGRESSIONS)/carfield/runtime-parallel.xml $(REGRESSIONS)/parallel-bare-tests.yaml + -o $(REGRESSIONS)/$(TARGET)/runtime-parallel.xml $(REGRESSIONS)/parallel-bare-tests.yaml .PHONY: test-rt-mchan ## Run mchan tests on pulp-runtime test-rt-mchan: pulp-runtime regression-tests cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ -t 7200 --yaml --max-procs 2 \ - -o $(REGRESSIONS)/carfield/runtime-mchan.xml $(REGRESSIONS)/pulp_cluster-mchan-tests.yaml + -o $(REGRESSIONS)/$(TARGET)/runtime-mchan.xml $(REGRESSIONS)/pulp_cluster-mchan-tests.yaml -.PHONY: test-rt-carfield +.PHONY: test-rt-$(TARGET) ## Run Carfield tests on pulp-runtime test-rt-carfield: pulp-runtime regression-tests cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ -t 3600 --yaml --max-procs 2 \ - -o $(REGRESSIONS)/carfield/runtime-mchan.xml $(REGRESSIONS)/carfield.yaml + -o $(REGRESSIONS)/$(TARGET)/runtime-mchan.xml $(REGRESSIONS)/$(TARGET).yaml diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index f2bea30c..2b36d699 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -61,7 +61,7 @@ module pulp_cluster_tb; localparam bit[AxiAw-1:0] ClustExtOffs = 'h00400000; localparam bit[ 5:0] ClustIdx = 'h1; localparam bit[AxiAw-1:0] ClustBaseAddr = ClustBase; - localparam bit[AxiAw-1:0] L2BaseAddr = 'h78000000; + localparam bit[AxiAw-1:0] L2BaseAddr = 'h10000000; localparam bit[AxiAw-1:0] L2Size = 'h10000000; localparam bit[AxiAw-1:0] BootAddr = L2BaseAddr + 'h8080; localparam bit[AxiAw-1:0] ClustReturnInt = 'h50200100; @@ -507,12 +507,12 @@ module pulp_cluster_tb; $display("[TB] Launch cluster\n"); for (int i = 0; i < `NB_CORES; i++) begin - aw_beat.ax_addr = 32'h50200040 + i*4; + aw_beat.ax_addr = ClustBase + ClustPeriphOffs + 'h40 + i*4; aw_beat.ax_len = '0; aw_beat.ax_burst = axi_pkg::BURST_INCR; aw_beat.ax_size = 4'h3; - w_beat.w_data = 'h78008080; + w_beat.w_data = BootAddr; w_beat.w_strb = 'h1; w_beat.w_last = 'h1; From 4306ca498f9d1595f3bf895bffa13a3add0111eb Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 8 Apr 2024 17:13:30 +0200 Subject: [PATCH 143/207] Bump nonfree. --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 295ff1e7..9e0899f9 100644 --- a/Makefile +++ b/Makefile @@ -53,7 +53,7 @@ endef ###################### NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git -NONFREE_COMMIT ?= f7cf9949eae7cb7f7e3b3c30863996b67497bf17 +NONFREE_COMMIT ?= df4dba5d7c494d2842c2461c1996fa7b4eafff57 nonfree-init: git clone $(NONFREE_REMOTE) nonfree From 932c4f9f15c6253351ba238cfbccf79d50143c62 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 8 Apr 2024 17:28:18 +0200 Subject: [PATCH 144/207] Update regression tests. --- regression-tests | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/regression-tests b/regression-tests index 126a1c56..f2206791 160000 --- a/regression-tests +++ b/regression-tests @@ -1 +1 @@ -Subproject commit 126a1c56a6774d235f52b05ea1e3d5566606effd +Subproject commit f220679120dc6c4ccb82c5f4292d3add8cd134e4 From 504b83d1d3c7aae5706b882af1f06a54800c97ce Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Fri, 29 Mar 2024 11:08:59 +0100 Subject: [PATCH 145/207] Reduce number of cores --- include/pulp_soc_defines.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/pulp_soc_defines.sv b/include/pulp_soc_defines.sv index 512271e5..a5c33c41 100644 --- a/include/pulp_soc_defines.sv +++ b/include/pulp_soc_defines.sv @@ -47,7 +47,7 @@ //PARAMETRES `define NB_CLUSTERS 1 -`define NB_CORES 12 +`define NB_CORES 8 `define NB_DMAS 4 `define NB_MPERIPHS 1 `define NB_SPERIPHS 11 From eb54fbebc4abcc763d87a42698900197287aa2f8 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Fri, 29 Mar 2024 11:10:33 +0100 Subject: [PATCH 146/207] Reduce TCDM size --- tb/pulp_cluster_tb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 2b36d699..fc9f6053 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -286,7 +286,7 @@ module pulp_cluster_tb; ClusterAliasBase: 'h0, NumSyncStages: 3, UseHci: 1, - TcdmSize: 256*1024, + TcdmSize: 128*1024, TcdmNumBank: 16, HwpePresent: 1, HwpeCfg: '{NumHwpes: 2, HwpeList: {NEUREKA, REDMULE}}, From ccf7518d262486ad7ffea079a78abf18cb4652ed Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Fri, 29 Mar 2024 12:29:11 +0100 Subject: [PATCH 147/207] Fix regression target in Makefile --- regression.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/regression.mk b/regression.mk index 2be2a08c..c5fbbe6a 100644 --- a/regression.mk +++ b/regression.mk @@ -20,7 +20,7 @@ test-rt-mchan: pulp-runtime regression-tests .PHONY: test-rt-$(TARGET) ## Run Carfield tests on pulp-runtime -test-rt-carfield: pulp-runtime regression-tests +test-rt-$(TARGET): pulp-runtime regression-tests cd $(REGRESSIONS) && $(bwruntest) --proc-verbose -v \ -t 3600 --yaml --max-procs 2 \ -o $(REGRESSIONS)/$(TARGET)/runtime-mchan.xml $(REGRESSIONS)/$(TARGET).yaml From cc223283e5f34c6bef96c31972363fc645d59805 Mon Sep 17 00:00:00 2001 From: Riccardo Tedeschi Date: Mon, 8 Apr 2024 17:34:36 +0200 Subject: [PATCH 148/207] Bump pulp-runtime --- pulp-runtime | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pulp-runtime b/pulp-runtime index 54a233a8..f208e9f3 160000 --- a/pulp-runtime +++ b/pulp-runtime @@ -1 +1 @@ -Subproject commit 54a233a83566a68436d0d68159d680277c2292a8 +Subproject commit f208e9f30426a9980446800087b7ac9b59fbb979 From d23b83217e38a6b26d8b57170a9d35dff28e4fb9 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Thu, 7 Mar 2024 00:01:06 +0000 Subject: [PATCH 149/207] Adapt Astral PULP cluster to HCI-v2 --- Makefile | 15 +- pulp-runtime | 2 +- rtl/axi2mem_wrap.sv | 20 +- rtl/cluster_interconnect_wrap.sv | 27 +- rtl/core_demux_wrap.sv | 59 +- rtl/hwpe_subsystem.sv | 20 +- rtl/idma_wrap.sv | 30 +- rtl/mchan_wrap.sv | 11 +- rtl/pulp_cluster.sv | 39 +- rtl/tcdm_banks_wrap.sv | 20 +- scripts/compile.tcl | 2440 ++++++++++++++++++++++++++++++ scripts/start.tcl | 2 +- 12 files changed, 2577 insertions(+), 108 deletions(-) create mode 100644 scripts/compile.tcl diff --git a/Makefile b/Makefile index 9e0899f9..d66f5f45 100644 --- a/Makefile +++ b/Makefile @@ -4,9 +4,9 @@ ROOT_DIR = $(strip $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) -QUESTA ?= questa-2022.3 +QUESTA ?= GIT ?= git -BENDER ?= bender +BENDER ?= ./bender VSIM ?= $(QUESTA) vsim VOPT ?= $(QUESTA) vopt top_level ?= pulp_cluster_tb @@ -44,7 +44,7 @@ bender_targs += -t cv32e40p_use_ff_regfile define generate_vsim echo 'set ROOT [file normalize [file dirname [info script]]/$3]' > $1 - bender script vsim --vlog-arg="$(VLOG_ARGS)" $2 | grep -v "set ROOT" >> $1 + $(BENDER) script vsim --vlog-arg="$(VLOG_ARGS)" $2 | grep -v "set ROOT" >> $1 echo >> $1 endef @@ -71,12 +71,12 @@ init: checkout .PHONY: checkout scripts/compile.tcl ## Checkout/update dependencies using Bender checkout: - bender checkout + $(BENDER) checkout touch Bender.lock make scripts/compile.tcl Bender.lock: - bender checkout + $(BENDER) checkout touch Bender.lock @@ -96,6 +96,11 @@ fault_injection_sim: # Build and simulation # ######################## +$(BENDER): + curl --proto '=https' \ + --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh -s -- 0.24.0 + mv bender $(BENDER) + sim_clean: rm -rf scripts/compile.tcl rm -rf work diff --git a/pulp-runtime b/pulp-runtime index f208e9f3..ed59950a 160000 --- a/pulp-runtime +++ b/pulp-runtime @@ -1 +1 @@ -Subproject commit f208e9f30426a9980446800087b7ac9b59fbb979 +Subproject commit ed59950ab7e1bd7cec2d199748352b1a2a668de5 diff --git a/rtl/axi2mem_wrap.sv b/rtl/axi2mem_wrap.sv index fe0bcf11..1e2268e0 100644 --- a/rtl/axi2mem_wrap.sv +++ b/rtl/axi2mem_wrap.sv @@ -25,12 +25,12 @@ module axi2mem_wrap parameter AXI_ID_WIDTH = 6 ) ( - input logic clk_i, - input logic rst_ni, - input logic test_en_i, - AXI_BUS.Slave axi_slave, - hci_core_intf.master tcdm_master[NB_DMAS-1:0], - output logic busy_o + input logic clk_i, + input logic rst_ni, + input logic test_en_i, + AXI_BUS.Slave axi_slave, + hci_core_intf.initiator tcdm_master[0:NB_DMAS-1], + output logic busy_o ); logic [NB_DMAS-1:0][31:0] s_tcdm_bus_wdata; @@ -49,8 +49,12 @@ module axi2mem_wrap assign tcdm_master[i].data = s_tcdm_bus_wdata[i]; assign tcdm_master[i].wen = s_tcdm_bus_wen[i]; assign tcdm_master[i].be = s_tcdm_bus_be[i]; - assign tcdm_master[i].boffs = '0; - assign tcdm_master[i].lrdy = '1; + assign tcdm_master[i].r_ready = '1; + assign tcdm_master[i].user = '0; + assign tcdm_master[i].ecc = '0; + assign tcdm_master[i].id = '0; + assign tcdm_master[i].ereq = '0; + assign tcdm_master[i].r_eready = '1; assign s_tcdm_bus_gnt[i] = tcdm_master[i].gnt; assign s_tcdm_bus_r_valid[i] = tcdm_master[i].r_valid; diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index 245f0dc8..ed69f586 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -49,14 +49,14 @@ module cluster_interconnect_wrap input logic clk_i, input logic rst_ni, input logic [5:0] cluster_id_i, - hci_core_intf.slave core_tcdm_slave [NB_CORES-1:0], - hci_core_intf.slave hwpe_tcdm_slave [0:0], - XBAR_PERIPH_BUS.Slave core_periph_slave[NB_CORES-1:0], - hci_core_intf.slave ext_slave [3:0], - hci_core_intf.slave dma_slave [NB_DMAS-1:0], //FIXME IGOR --> check NB_CORES depend ASK DAVIDE - XBAR_TCDM_BUS.Slave mperiph_slave[NB_MPERIPHS-1:0], - hci_mem_intf.master tcdm_sram_master[NB_TCDM_BANKS-1:0], - XBAR_PERIPH_BUS.Master speriph_master[NB_SPERIPHS-1:0], + hci_core_intf.target core_tcdm_slave [0 : NB_CORES-1 ], + hci_core_intf.target hwpe_tcdm_slave [0 : 0 ], + XBAR_PERIPH_BUS.Slave core_periph_slave [NB_CORES-1 : 0 ], + hci_core_intf.target ext_slave [0 : 3 ], + hci_core_intf.target dma_slave [0 : NB_DMAS-1 ], + XBAR_TCDM_BUS.Slave mperiph_slave [NB_MPERIPHS-1 : 0 ], + hci_core_intf.initiator tcdm_sram_master [0 : NB_TCDM_BANKS-1], + XBAR_PERIPH_BUS.Master speriph_master [NB_SPERIPHS-1 : 0 ], input hci_interconnect_ctrl_t hci_ctrl_i, input logic [1:0] TCDM_arb_policy_i ); @@ -84,7 +84,6 @@ module cluster_interconnect_wrap .TS_BIT ( TEST_SET_BIT ), .AWH ( ADDR_WIDTH ), .DWH ( NB_HWPE_PORTS*DATA_WIDTH ), - .OWH ( 1 ), .AWM ( ADDR_MEM_WIDTH+2 ) ) i_hci_interconnect ( .clk_i ( clk_i ), @@ -102,16 +101,14 @@ module cluster_interconnect_wrap hci_core_intf #( .DW ( 32 ), - .AW ( 32 ), - .OW ( 1 ) - ) core_hwpe_tcdm_slave [NB_CORES+NB_HWPE_PORTS-1:0] ( + .AW ( 32 ) + ) core_hwpe_tcdm_slave [0:NB_CORES+NB_HWPE_PORTS-1] ( .clk ( clk_i ) ); hci_core_intf #( .DW ( NB_HWPE_PORTS*32 ), - .AW ( 32 ), - .OW ( 1 ) + .AW ( 32 ) ) null_hwpe_tcdm_slave ( .clk ( clk_i ) ); @@ -124,7 +121,7 @@ module cluster_interconnect_wrap .rst_ni ( rst_ni ), .clear_i ( clear_i ), .tcdm_slave ( hwpe_tcdm_slave[0] ), - .tcdm_master ( core_hwpe_tcdm_slave[NB_CORES+NB_HWPE_PORTS-1:NB_CORES] ) + .tcdm_master ( core_hwpe_tcdm_slave[NB_CORES:NB_CORES+NB_HWPE_PORTS-1] ) ); for(genvar ii=0; ii log interconnect hci_core_intf #( .DW ( DataWidth ), - .AW ( AddrWidth ), - .OW ( 1 ) -) s_hci_ext[Cfg.DmaNumPlugs-1:0] ( + .AW ( AddrWidth ) +) s_hci_ext[0:Cfg.DmaNumPlugs-1] ( .clk ( clk_i ) ); @@ -323,9 +322,8 @@ XBAR_PERIPH_BUS s_hwpe_cfg_bus(); // DMA -> log interconnect hci_core_intf #( .DW ( DataWidth ), - .AW ( AddrWidth ), - .OW ( 1 ) -) s_hci_dma[Cfg.DmaNumPlugs-1:0] ( + .AW ( AddrWidth ) +) s_hci_dma[0:Cfg.DmaNumPlugs-1] ( .clk ( clk_i ) ); XBAR_TCDM_BUS s_dma_plugin_xbar_bus[Cfg.DmaNumPlugs-1:0](); @@ -339,16 +337,14 @@ XBAR_TCDM_BUS s_mperiph_bus(); // cores & accelerators -> log interconnect hci_core_intf #( .DW ( Cfg.HwpeNumPorts * DataWidth ), - .AW ( AddrWidth ), - .OW ( 1 ) + .AW ( AddrWidth ) ) s_hci_hwpe [0:0] ( .clk ( clk_i ) ); hci_core_intf #( .DW ( DataWidth ), - .AW ( AddrWidth ), - .OW ( 1 ) -) s_hci_core [Cfg.NumCores-1:0] ( + .AW ( AddrWidth ) +) s_hci_core [0:Cfg.NumCores-1] ( .clk ( clk_i ) ); @@ -370,13 +366,11 @@ XBAR_TCDM_BUS s_debug_bus[Cfg.NumCores-1:0](); /* other interfaces */ // cores -> DMA ctrl // FIXME: iDMA -// XBAR_TCDM_BUS s_core_dmactrl_bus[NB_CORES-1:0](); hci_core_intf #( .DW ( DataWidth ), .AW ( AddrWidth ), - .OW ( 1 ), .UW ( 0 ) -) s_core_dmactrl_bus [Cfg.NumCores-1:0] ( +) s_core_dmactrl_bus [0:Cfg.NumCores-1] ( .clk ( clk_i ) ); @@ -410,12 +404,12 @@ logic[Cfg.NumCores-1:0] s_enable_l1_l15_prefetch; localparam TCDM_ID_WIDTH = Cfg.NumCores + Cfg.DmaNumPlugs + 4 + Cfg.HwpeNumPorts; // log interconnect -> TCDM memory banks (SRAM) -hci_mem_intf #( - .AW ( AddrWidth ), - .DW ( DataWidth ), - .BW ( 8 ), - .IW ( TCDM_ID_WIDTH ) -) s_tcdm_bus_sram[Cfg.TcdmNumBank-1:0] ( +hci_core_intf #( + .AW ( AddrMemWidth+2 ), // AddrMemWidth is word-wise, +2 for byte-wise + .DW ( DataWidth ), + .BW ( 8 ), + .IW ( TCDM_ID_WIDTH ) +) s_tcdm_bus_sram[0:Cfg.TcdmNumBank-1] ( .clk ( clk_i ) ); @@ -1161,10 +1155,7 @@ generate .HWPE_CFG ( Cfg.HwpeCfg ), .N_CORES ( Cfg.NumCores ), .N_MASTER_PORT ( Cfg.HwpeNumPorts ), - .ID_WIDTH ( Cfg.NumCores + Cfg.NumMstPeriphs ), - .DW ( Cfg.HwpeNumPorts * DataWidth ), - .AW ( AddrWidth ), - .OW ( 1 ) + .ID_WIDTH ( Cfg.NumCores + Cfg.NumMstPeriphs ) ) hwpe_subsystem_i ( .clk ( clk_i ), .rst_n ( rst_ni ), diff --git a/rtl/tcdm_banks_wrap.sv b/rtl/tcdm_banks_wrap.sv index aa429d15..85a345e1 100644 --- a/rtl/tcdm_banks_wrap.sv +++ b/rtl/tcdm_banks_wrap.sv @@ -37,11 +37,22 @@ module tcdm_banks_wrap #( // ECC output logic [NbBanks-1:0] ecc_single_error_o, output logic [NbBanks-1:0] ecc_multiple_error_o, - hci_mem_intf.slave tcdm_slave[NbBanks-1:0] + hci_core_intf.target tcdm_slave[NbBanks-1:0] ); for(genvar i=0; i Date: Tue, 26 Mar 2024 20:49:56 +0000 Subject: [PATCH 150/207] Align versions for HCIv2 Update submodules Adapt Makefile to work both in IIS and non-IIS settings More scary Bender black magic. But to me it looks like the Bender.lock is still wrong. Scariest Benderonomicon of them all Makefile fix for IIS Use correct nonfree-commit for CI Fix nonfree commit Update regression-tests --- Bender.local | 4 - Bender.lock | 10 +- Bender.yml | 8 +- Makefile | 11 +- rtl/cluster_interconnect_wrap.sv | 8 +- scripts/compile.tcl | 306 ++++++++++++++++--------------- 6 files changed, 172 insertions(+), 175 deletions(-) diff --git a/Bender.local b/Bender.local index ff73c9f0..5c808517 100644 --- a/Bender.local +++ b/Bender.local @@ -3,7 +3,3 @@ overrides: register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic - - # Temporarily left here to avoid conflicts - hwpe-stream : { git: "https://github.com/pulp-platform/hwpe-stream.git" , rev: 65c99a4a2f37a79acee800ab0151f67dfb1edef1 } # branch: master - hci : { git: "https://github.com/pulp-platform/hci.git", rev: e47627c20b33bcaf4842c1add81fb888b4f12a9d } diff --git a/Bender.lock b/Bender.lock index f3b9085f..bdcec4f4 100644 --- a/Bender.lock +++ b/Bender.lock @@ -45,7 +45,7 @@ packages: dependencies: - common_cells cluster_peripherals: - revision: 8a9f62dafb5ec23c6cd361847ff0047e12befca4 + revision: 0b8e8ab9e6be3a5030a18256bb7e75cf6b6f6cac version: null source: Git: https://github.com/pulp-platform/cluster_peripherals.git @@ -97,8 +97,8 @@ packages: dependencies: - common_cells hci: - revision: e47627c20b33bcaf4842c1add81fb888b4f12a9d - version: null + revision: 33bd45771ad2e2690140cb29cafe0e753065d7aa + version: 2.0.0-rc1 source: Git: https://github.com/pulp-platform/hci.git dependencies: @@ -168,7 +168,7 @@ packages: dependencies: - common_cells neureka: - revision: 3131e87c40118f75e11a1ff9bae60fe764336a19 + revision: 60c51c0a5f6b30140ca99cc546ddcfde00af0044 version: null source: Git: https://github.com/pulp-platform/neureka.git @@ -184,7 +184,7 @@ packages: dependencies: - axi_slice redmule: - revision: 68999ccc922b10a5043bb98f67aaf3d8d8d59f3f + revision: 7abb25690090c7f5548a8aa905c7bf0440d4ba6b version: null source: Git: https://github.com/pulp-platform/redmule.git diff --git a/Bender.yml b/Bender.yml index ac4938ee..0b170b7e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,7 +20,7 @@ dependencies: mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "2886cb2a46cea3e2bd2d979b505d88fadfbe150c" } # branch: astral - cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 8a9f62dafb5ec23c6cd361847ff0047e12befca4 } # branch: astral + cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2 axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } @@ -29,12 +29,12 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: e47627c20b33bcaf4842c1add81fb888b4f12a9d } + hci: { git: "https://github.com/pulp-platform/hci.git", rev: "v2.0.0-rc1" } # branch: breaking-names register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 68999ccc922b10a5043bb98f67aaf3d8d8d59f3f } # branch: astral - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 3131e87c40118f75e11a1ff9bae60fe764336a19 } # branch: astral-4x4 + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 7abb256 } # branch: fc/hci-v2 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 60c51c0 } # branch: hci-v2 export_include_dirs: - include diff --git a/Makefile b/Makefile index d66f5f45..f95992e3 100644 --- a/Makefile +++ b/Makefile @@ -4,9 +4,14 @@ ROOT_DIR = $(strip $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) -QUESTA ?= +ifneq (,$(wildcard /etc/iis.version)) + QUESTA ?= questa-2022.3 + BENDER ?= bender +else + QUESTA ?= + BENDER ?= ./bender +endif GIT ?= git -BENDER ?= ./bender VSIM ?= $(QUESTA) vsim VOPT ?= $(QUESTA) vopt top_level ?= pulp_cluster_tb @@ -53,7 +58,7 @@ endef ###################### NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git -NONFREE_COMMIT ?= df4dba5d7c494d2842c2461c1996fa7b4eafff57 +NONFREE_COMMIT ?= ad58d90 nonfree-init: git clone $(NONFREE_REMOTE) nonfree diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index ed69f586..aea18d4e 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -78,13 +78,7 @@ module cluster_interconnect_wrap .N_EXT ( 4 ), .N_MEM ( NB_TCDM_BANKS ), .IW ( TCDM_ID_WIDTH ), - .AWC ( ADDR_WIDTH ), - .DW_LIC ( DATA_WIDTH ), - .DW_SIC ( NB_HWPE_PORTS*DATA_WIDTH ), - .TS_BIT ( TEST_SET_BIT ), - .AWH ( ADDR_WIDTH ), - .DWH ( NB_HWPE_PORTS*DATA_WIDTH ), - .AWM ( ADDR_MEM_WIDTH+2 ) + .TS_BIT ( TEST_SET_BIT ) ) i_hci_interconnect ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/scripts/compile.tcl b/scripts/compile.tcl index abeeca9d..e51c1a6f 100644 --- a/scripts/compile.tcl +++ b/scripts/compile.tcl @@ -247,6 +247,7 @@ if {[catch { vlog -incr -sv \ "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/mv_filter.sv" \ "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/onehot_to_bin.sv" \ "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/plru_tree.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/passthrough_stream_fifo.sv" \ "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/popcount.sv" \ "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/rr_arb_tree.sv" \ "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/src/rstgen_bypass.sv" \ @@ -376,6 +377,7 @@ if {[catch { vlog -incr -sv \ "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/fifo_tb.sv" \ "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/graycode_tb.sv" \ "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/id_queue_tb.sv" \ + "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/passthrough_stream_fifo_tb.sv" \ "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/popcount_tb.sv" \ "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/rr_arb_tree_tb.sv" \ "$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/test/stream_test.sv" \ @@ -810,44 +812,44 @@ if {[catch { vlog -incr -sv \ +define+TRACE_EXECUTION \ +define+CLUSTER_ALIAS \ +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/working_dir/hwpe-stream/rtl" \ - "$ROOT/working_dir/hwpe-stream/rtl/hwpe_stream_interfaces.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/hwpe_stream_package.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/basic/hwpe_stream_assign.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/basic/hwpe_stream_buffer.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/basic/hwpe_stream_demux_static.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/basic/hwpe_stream_deserialize.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/basic/hwpe_stream_fence.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/basic/hwpe_stream_merge.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/basic/hwpe_stream_mux_static.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/basic/hwpe_stream_serialize.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/basic/hwpe_stream_split.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/fifo/hwpe_stream_fifo_ctrl.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/fifo/hwpe_stream_fifo_scm.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/streamer/hwpe_stream_addressgen.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/streamer/hwpe_stream_addressgen_v2.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/streamer/hwpe_stream_addressgen_v3.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/streamer/hwpe_stream_sink_realign.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/streamer/hwpe_stream_source_realign.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/streamer/hwpe_stream_strbgen.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/streamer/hwpe_stream_streamer_queue.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/tcdm/hwpe_stream_tcdm_assign.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/tcdm/hwpe_stream_tcdm_mux.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/tcdm/hwpe_stream_tcdm_mux_static.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/tcdm/hwpe_stream_tcdm_reorder.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/tcdm/hwpe_stream_tcdm_reorder_static.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/fifo/hwpe_stream_fifo_earlystall.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/fifo/hwpe_stream_fifo_earlystall_sidech.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/fifo/hwpe_stream_fifo_scm_test_wrap.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/fifo/hwpe_stream_fifo_sidech.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/fifo/hwpe_stream_fifo.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/tcdm/hwpe_stream_tcdm_fifo_load_sidech.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/fifo/hwpe_stream_fifo_passthrough.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/streamer/hwpe_stream_source.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/tcdm/hwpe_stream_tcdm_fifo.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/tcdm/hwpe_stream_tcdm_fifo_load.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/tcdm/hwpe_stream_tcdm_fifo_store.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/streamer/hwpe_stream_sink.sv" \ + "+incdir+$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/hwpe_stream_interfaces.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/hwpe_stream_package.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_assign.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_buffer.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_demux_static.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_deserialize.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_fence.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_merge.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_mux_static.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_serialize.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/basic/hwpe_stream_split.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_ctrl.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_scm.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_addressgen.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_addressgen_v2.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_addressgen_v3.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_sink_realign.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_source_realign.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_strbgen.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_streamer_queue.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_assign.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_mux.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_mux_static.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_reorder.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_reorder_static.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_earlystall.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_earlystall_sidech.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_scm_test_wrap.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_sidech.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_fifo_load_sidech.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/fifo/hwpe_stream_fifo_passthrough.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_source.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_fifo.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_fifo_load.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/tcdm/hwpe_stream_tcdm_fifo_store.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/streamer/hwpe_stream_sink.sv" \ }]} {return 1} if {[catch { vlog -incr -sv \ @@ -868,10 +870,10 @@ if {[catch { vlog -incr -sv \ +define+TRACE_EXECUTION \ +define+CLUSTER_ALIAS \ +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/working_dir/hwpe-stream/rtl" \ - "$ROOT/working_dir/hwpe-stream/rtl/verif/hwpe_stream_traffic_gen.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/verif/hwpe_stream_traffic_recv.sv" \ - "$ROOT/working_dir/hwpe-stream/rtl/verif/tb_fifo.sv" \ + "+incdir+$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/verif/hwpe_stream_traffic_gen.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/verif/hwpe_stream_traffic_recv.sv" \ + "$ROOT/.bender/git/checkouts/hwpe-stream-bc1f2d87c271f75a/rtl/verif/tb_fifo.sv" \ }]} {return 1} if {[catch { vlog -incr -sv \ @@ -944,14 +946,14 @@ if {[catch { vlog -incr -sv \ +define+CLUSTER_ALIAS \ +define+USE_PULP_PARAMETERS \ "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_single_slice.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_ar_buffer.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_aw_buffer.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_b_buffer.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_r_buffer.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_slice.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_w_buffer.sv" \ - "$ROOT/.bender/git/checkouts/axi_slice-097f179baf7559d9/src/axi_slice_wrap.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-daa15d3f50dbd970/src/axi_single_slice.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-daa15d3f50dbd970/src/axi_ar_buffer.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-daa15d3f50dbd970/src/axi_aw_buffer.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-daa15d3f50dbd970/src/axi_b_buffer.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-daa15d3f50dbd970/src/axi_r_buffer.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-daa15d3f50dbd970/src/axi_slice.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-daa15d3f50dbd970/src/axi_w_buffer.sv" \ + "$ROOT/.bender/git/checkouts/axi_slice-daa15d3f50dbd970/src/axi_slice_wrap.sv" \ }]} {return 1} if {[catch { vlog -incr -sv \ @@ -1074,26 +1076,26 @@ if {[catch { vlog -incr -sv \ +define+USE_PULP_PARAMETERS \ "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/low_latency_interco" \ "+incdir+$ROOT/.bender/git/checkouts/cluster_interconnect-9a146c2c6998a1b5/rtl/peripheral_interco" \ - "+incdir+$ROOT/working_dir/hci/rtl" \ - "$ROOT/working_dir/hci/rtl/common/hci_package.sv" \ - "$ROOT/working_dir/hci/rtl/common/hci_interfaces.sv" \ - "$ROOT/working_dir/hci/rtl/core/hci_core_assign.sv" \ - "$ROOT/working_dir/hci/rtl/core/hci_core_fifo.sv" \ - "$ROOT/working_dir/hci/rtl/core/hci_core_mux_dynamic.sv" \ - "$ROOT/working_dir/hci/rtl/core/hci_core_mux_static.sv" \ - "$ROOT/working_dir/hci/rtl/core/hci_core_mux_ooo.sv" \ - "$ROOT/working_dir/hci/rtl/core/hci_core_r_valid_filter.sv" \ - "$ROOT/working_dir/hci/rtl/core/hci_core_r_id_filter.sv" \ - "$ROOT/working_dir/hci/rtl/core/hci_core_source.sv" \ - "$ROOT/working_dir/hci/rtl/core/hci_core_split.sv" \ - "$ROOT/working_dir/hci/rtl/interco/hci_log_interconnect.sv" \ - "$ROOT/working_dir/hci/rtl/interco/hci_log_interconnect_l2.sv" \ - "$ROOT/working_dir/hci/rtl/interco/hci_new_log_interconnect.sv" \ - "$ROOT/working_dir/hci/rtl/interco/hci_arbiter.sv" \ - "$ROOT/working_dir/hci/rtl/interco/hci_router_reorder.sv" \ - "$ROOT/working_dir/hci/rtl/core/hci_core_sink.sv" \ - "$ROOT/working_dir/hci/rtl/interco/hci_router.sv" \ - "$ROOT/working_dir/hci/rtl/hci_interconnect.sv" \ + "+incdir+$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/common" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/common/hci_package.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/common/hci_interfaces.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_assign.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_fifo.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_mux_dynamic.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_mux_static.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_mux_ooo.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_r_valid_filter.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_r_id_filter.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_source.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_split.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_log_interconnect.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_log_interconnect_l2.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_new_log_interconnect.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_arbiter.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_router_reorder.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/core/hci_core_sink.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/interco/hci_router.sv" \ + "$ROOT/.bender/git/checkouts/hci-f956ddaaacdaf461/rtl/hci_interconnect.sv" \ }]} {return 1} if {[catch { vlog -incr -sv \ @@ -1144,15 +1146,15 @@ if {[catch { vlog -incr -sv \ +define+TRACE_EXECUTION \ +define+CLUSTER_ALIAS \ +define+USE_PULP_PARAMETERS \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/Req_Arb_Node_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/Resp_Arb_Node_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/lint_mux.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/DistributedArbitrationNetwork_Req_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/DistributedArbitrationNetwork_Resp_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/RoutingBlock_Req_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/RoutingBlock_2ch_Req_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/RoutingBlock_Resp_icache_intc.sv" \ - "$ROOT/.bender/git/checkouts/icache-intc-02d7b8b93cfd008b/icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-a10f772797fa0be4/Req_Arb_Node_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-a10f772797fa0be4/Resp_Arb_Node_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-a10f772797fa0be4/lint_mux.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-a10f772797fa0be4/DistributedArbitrationNetwork_Req_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-a10f772797fa0be4/DistributedArbitrationNetwork_Resp_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-a10f772797fa0be4/RoutingBlock_Req_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-a10f772797fa0be4/RoutingBlock_2ch_Req_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-a10f772797fa0be4/RoutingBlock_Resp_icache_intc.sv" \ + "$ROOT/.bender/git/checkouts/icache-intc-a10f772797fa0be4/icache_intc.sv" \ }]} {return 1} if {[catch { vlog -incr -sv \ @@ -1817,28 +1819,28 @@ if {[catch { vlog -incr -sv \ +define+TRACE_EXECUTION \ +define+CLUSTER_ALIAS \ +define+USE_PULP_PARAMETERS \ - "$ROOT/working_dir/neureka/rtl/neureka_package.sv" \ - "$ROOT/working_dir/neureka/rtl/accumulator/neureka_normquant.sv" \ - "$ROOT/working_dir/neureka/rtl/accumulator/neureka_normquant_shifter.sv" \ - "$ROOT/working_dir/neureka/rtl/accumulator/neureka_normquant_bias.sv" \ - "$ROOT/working_dir/neureka/rtl/accumulator/neureka_accumulator_adder.sv" \ - "$ROOT/working_dir/neureka/rtl/accumulator/neureka_normquant_multiplier.sv" \ - "$ROOT/working_dir/neureka/rtl/accumulator/neureka_accumulator_buffer.sv" \ - "$ROOT/working_dir/neureka/rtl/accumulator/neureka_accumulator_normquant.sv" \ - "$ROOT/working_dir/neureka/rtl/input_buffer/neureka_input_buffer_scm.sv" \ - "$ROOT/working_dir/neureka/rtl/input_buffer/neureka_input_buffer_scm_test_wrap.sv" \ - "$ROOT/working_dir/neureka/rtl/input_buffer/neureka_input_buffer.sv" \ - "$ROOT/working_dir/neureka/rtl/input_buffer/neureka_double_input_buffer.sv" \ - "$ROOT/working_dir/neureka/rtl/array/neureka_scale.sv" \ - "$ROOT/working_dir/neureka/rtl/array/neureka_binconv_col.sv" \ - "$ROOT/working_dir/neureka/rtl/array/neureka_binconv_pe.sv" \ - "$ROOT/working_dir/neureka/rtl/array/neureka_binconv_array.sv" \ - "$ROOT/working_dir/neureka/rtl/ctrl/neureka_ctrl_fsm.sv" \ - "$ROOT/working_dir/neureka/rtl/ctrl/neureka_ctrl.sv" \ - "$ROOT/working_dir/neureka/rtl/neureka_engine.sv" \ - "$ROOT/working_dir/neureka/rtl/neureka_streamer.sv" \ - "$ROOT/working_dir/neureka/rtl/neureka_top.sv" \ - "$ROOT/working_dir/neureka/rtl/neureka_top_wrap.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/neureka_package.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/accumulator/neureka_normquant.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/accumulator/neureka_normquant_shifter.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/accumulator/neureka_normquant_bias.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/accumulator/neureka_accumulator_adder.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/accumulator/neureka_normquant_multiplier.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/accumulator/neureka_accumulator_buffer.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/accumulator/neureka_accumulator_normquant.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/input_buffer/neureka_input_buffer_scm.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/input_buffer/neureka_input_buffer_scm_test_wrap.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/input_buffer/neureka_input_buffer.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/input_buffer/neureka_double_input_buffer.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/array/neureka_scale.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/array/neureka_binconv_col.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/array/neureka_binconv_pe.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/array/neureka_binconv_array.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/ctrl/neureka_ctrl_fsm.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/ctrl/neureka_ctrl.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/neureka_engine.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/neureka_streamer.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/neureka_top.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/neureka_top_wrap.sv" \ }]} {return 1} if {[catch { vlog -incr -sv \ @@ -1859,8 +1861,8 @@ if {[catch { vlog -incr -sv \ +define+TRACE_EXECUTION \ +define+CLUSTER_ALIAS \ +define+USE_PULP_PARAMETERS \ - "$ROOT/working_dir/neureka/rtl/verif/tb_dummy_memory.sv" \ - "$ROOT/working_dir/neureka/rtl/verif/tb_neureka.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/verif/tb_dummy_memory.sv" \ + "$ROOT/.bender/git/checkouts/neureka-9d242f85cecf0969/rtl/verif/tb_neureka.sv" \ }]} {return 1} if {[catch { vlog -incr -sv \ @@ -1906,22 +1908,22 @@ if {[catch { vlog -incr -sv \ +define+CLUSTER_ALIAS \ +define+USE_PULP_PARAMETERS \ "+incdir+$ROOT/.bender/git/checkouts/common_cells-5a98055a67ec8079/include" \ - "$ROOT/working_dir/redmule/rtl/redmule_pkg.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_ctrl.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_scheduler.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_castin.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_castout.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_streamer.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_x_buffer.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_w_buffer.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_z_buffer.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_fma.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_noncomp.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_ce.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_row.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_engine.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_top.sv" \ - "$ROOT/working_dir/redmule/rtl/redmule_wrap.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_pkg.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_ctrl.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_scheduler.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_castin.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_castout.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_streamer.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_x_buffer.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_w_buffer.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_z_buffer.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_fma.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_noncomp.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_ce.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_row.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_engine.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_top.sv" \ + "$ROOT/.bender/git/checkouts/redmule-8ba8e6c90026f85e/rtl/redmule_wrap.sv" \ }]} {return 1} if {[catch { vlog -incr -sv \ @@ -2174,35 +2176,35 @@ if {[catch { vlog -incr -sv \ +define+TRACE_EXECUTION \ +define+CLUSTER_ALIAS \ +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include/apu_core_package.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include/riscv_defines.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include/riscv_tracer_defines.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/macload_controller.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/mixed_precision_controller.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_alu.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_alu_basic.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_alu_div.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_compressed_decoder.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_controller.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_cs_registers.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_decoder.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_int_controller.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_ex_stage.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_hwloop_controller.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_hwloop_regs.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/register_file_test_wrap.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_id_stage.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_if_stage.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_load_store_unit.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_mult.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_prefetch_buffer.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_prefetch_L0_buffer.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_core.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_apu_disp.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_fetch_fifo.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_L0_buffer.sv" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_pmp.sv" \ + "+incdir+$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/include" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/include/apu_core_package.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/include/riscv_defines.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/include/riscv_tracer_defines.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/macload_controller.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/mixed_precision_controller.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_alu.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_alu_basic.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_alu_div.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_compressed_decoder.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_controller.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_cs_registers.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_decoder.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_int_controller.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_ex_stage.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_hwloop_controller.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_hwloop_regs.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/register_file_test_wrap.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_id_stage.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_if_stage.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_load_store_unit.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_mult.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_prefetch_buffer.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_prefetch_L0_buffer.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_core.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_apu_disp.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_fetch_fifo.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_L0_buffer.sv" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_pmp.sv" \ }]} {return 1} if {[catch { vlog -incr -sv \ @@ -2223,8 +2225,8 @@ if {[catch { vlog -incr -sv \ +define+TRACE_EXECUTION \ +define+CLUSTER_ALIAS \ +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_register_file.sv" \ + "+incdir+$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/include" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_register_file.sv" \ }]} {return 1} if {[catch { vlog -incr -sv \ @@ -2245,8 +2247,8 @@ if {[catch { vlog -incr -sv \ +define+TRACE_EXECUTION \ +define+CLUSTER_ALIAS \ +define+USE_PULP_PARAMETERS \ - "+incdir+$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/include" \ - "$ROOT/.bender/git/checkouts/riscv-fa10b6376f1fd1ee/rtl/riscv_tracer.sv" \ + "+incdir+$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/include" \ + "$ROOT/.bender/git/checkouts/riscv-61599a4c0726f240/rtl/riscv_tracer.sv" \ }]} {return 1} if {[catch { vlog -incr -sv \ From db00b21b7eaff0e0303c8132aa4ca1e417e64103 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Mon, 8 Apr 2024 08:05:35 +0000 Subject: [PATCH 151/207] address review comments --- .gitignore | 1 + Makefile | 4 +- rtl/tcdm_banks_wrap.sv | 2 +- scripts/compile.tcl | 2442 ---------------------------------------- 4 files changed, 4 insertions(+), 2445 deletions(-) create mode 100644 .gitignore delete mode 100644 scripts/compile.tcl diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..50c6844c --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +scripts/compile.tcl diff --git a/Makefile b/Makefile index f95992e3..9ba4d606 100644 --- a/Makefile +++ b/Makefile @@ -5,10 +5,10 @@ ROOT_DIR = $(strip $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))) ifneq (,$(wildcard /etc/iis.version)) - QUESTA ?= questa-2022.3 + QUESTA ?= questa-2022.3 BENDER ?= bender else - QUESTA ?= + QUESTA ?= BENDER ?= ./bender endif GIT ?= git diff --git a/rtl/tcdm_banks_wrap.sv b/rtl/tcdm_banks_wrap.sv index 85a345e1..e3f2fba5 100644 --- a/rtl/tcdm_banks_wrap.sv +++ b/rtl/tcdm_banks_wrap.sv @@ -37,7 +37,7 @@ module tcdm_banks_wrap #( // ECC output logic [NbBanks-1:0] ecc_single_error_o, output logic [NbBanks-1:0] ecc_multiple_error_o, - hci_core_intf.target tcdm_slave[NbBanks-1:0] + hci_core_intf.target tcdm_slave[0:NbBanks-1] ); for(genvar i=0; i Date: Tue, 16 Apr 2024 08:15:09 +0000 Subject: [PATCH 152/207] Use HCIv2 --- Bender.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index 0b170b7e..16c2f9de 100644 --- a/Bender.yml +++ b/Bender.yml @@ -29,7 +29,7 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: "v2.0.0-rc1" } # branch: breaking-names + hci: { git: "https://github.com/pulp-platform/hci.git", version: 2.0 } # branch: breaking-names register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase From e1866eff758469fecacbda1cb611bad157767396 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Tue, 16 Apr 2024 10:30:59 +0000 Subject: [PATCH 153/207] Update pulp-runtime to align with carfield-cluster --- pulp-runtime | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pulp-runtime b/pulp-runtime index ed59950a..0782b2fe 160000 --- a/pulp-runtime +++ b/pulp-runtime @@ -1 +1 @@ -Subproject commit ed59950ab7e1bd7cec2d199748352b1a2a668de5 +Subproject commit 0782b2fee078fc9c974ba112216aa4c72b872091 From 97fd41e239e25e317cdf86d2856ed422a239c7b3 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 23 Apr 2024 14:00:24 +0200 Subject: [PATCH 154/207] Adapt L2 address in runtime and testbench. --- pulp-runtime | 2 +- tb/pulp_cluster_tb.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pulp-runtime b/pulp-runtime index 0782b2fe..d8972b0f 160000 --- a/pulp-runtime +++ b/pulp-runtime @@ -1 +1 @@ -Subproject commit 0782b2fee078fc9c974ba112216aa4c72b872091 +Subproject commit d8972b0f0cac72ba8889fe09aa9a319fee0a1519 diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index fc9f6053..4951203d 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -61,7 +61,7 @@ module pulp_cluster_tb; localparam bit[AxiAw-1:0] ClustExtOffs = 'h00400000; localparam bit[ 5:0] ClustIdx = 'h1; localparam bit[AxiAw-1:0] ClustBaseAddr = ClustBase; - localparam bit[AxiAw-1:0] L2BaseAddr = 'h10000000; + localparam bit[AxiAw-1:0] L2BaseAddr = 'h78000000; localparam bit[AxiAw-1:0] L2Size = 'h10000000; localparam bit[AxiAw-1:0] BootAddr = L2BaseAddr + 'h8080; localparam bit[AxiAw-1:0] ClustReturnInt = 'h50200100; From 9a69d99db30c8ef1f47416e058b0f31445cbcf6b Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 23 Apr 2024 14:08:53 +0200 Subject: [PATCH 155/207] Bump pulp-runtime. --- pulp-runtime | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pulp-runtime b/pulp-runtime index d8972b0f..f3e685f3 160000 --- a/pulp-runtime +++ b/pulp-runtime @@ -1 +1 @@ -Subproject commit d8972b0f0cac72ba8889fe09aa9a319fee0a1519 +Subproject commit f3e685f38e5f07fa98ff26b8ab875c063feccfca From 34ead2a7b41945b46f34e8180b34b9b46bb6f379 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 10 May 2024 20:02:49 +0200 Subject: [PATCH 156/207] Align to HCIv2.1, without automatic parameter prop --- Bender.yml | 4 ++-- rtl/cluster_interconnect_wrap.sv | 35 +++++++++++++++++++---------- rtl/hwpe_subsystem.sv | 15 ++++++++----- rtl/pulp_cluster.sv | 38 ++++++++++++++++++++++++++++---- 4 files changed, 69 insertions(+), 23 deletions(-) diff --git a/Bender.yml b/Bender.yml index 16c2f9de..a91ae85f 100644 --- a/Bender.yml +++ b/Bender.yml @@ -33,8 +33,8 @@ dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 7abb256 } # branch: fc/hci-v2 - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 60c51c0 } # branch: hci-v2 + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: e1858900ed32702862cd1fdfc8957f5566f61ce1 } # branch: fc/hci-v2.1 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 7a63088004aa5528bd715731702e5faf255aafaa } # branch: fc/hci-v2.1 export_include_dirs: - include diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index aea18d4e..e415f28c 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -14,6 +14,7 @@ * University of Bologna. */ +`include "hci_helpers.svh" import hci_package::*; @@ -43,7 +44,10 @@ module cluster_interconnect_wrap parameter CLUSTER_ALIAS = 1, parameter CLUSTER_ALIAS_BASE = 12'h000, - parameter USE_HETEROGENEOUS_INTERCONNECT = 1 + parameter USE_HETEROGENEOUS_INTERCONNECT = 1, + parameter hci_package::hci_size_parameter_t HCI_CORE_SIZE = '0, + parameter hci_package::hci_size_parameter_t HCI_HWPE_SIZE = '0, + parameter hci_package::hci_size_parameter_t HCI_MEM_SIZE = '0, ) ( input logic clk_i, @@ -78,7 +82,10 @@ module cluster_interconnect_wrap .N_EXT ( 4 ), .N_MEM ( NB_TCDM_BANKS ), .IW ( TCDM_ID_WIDTH ), - .TS_BIT ( TEST_SET_BIT ) + .TS_BIT ( TEST_SET_BIT ), + .`HCI_SIZE_PARAM(cores) ( HCI_CORE_SIZE ), + .`HCI_SIZE_PARAM(mems) ( HCI_MEM_SIZE ), + .`HCI_SIZE_PARAM(hwpe) ( HCI_HWPE_SIZE ) ) i_hci_interconnect ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -108,20 +115,21 @@ module cluster_interconnect_wrap ); hci_core_split #( - .DW ( NB_HWPE_PORTS*32 ), - .NB_OUT_CHAN ( NB_HWPE_PORTS ) + .DW ( NB_HWPE_PORTS*32 ), + .NB_OUT_CHAN ( NB_HWPE_PORTS ), + .`HCI_SIZE_PARAM(tcdm_target) ( HCI_HWPE_SIZE ) ) i_hwpe_tcdm_splitter ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clear_i ( clear_i ), - .tcdm_slave ( hwpe_tcdm_slave[0] ), - .tcdm_master ( core_hwpe_tcdm_slave[NB_CORES:NB_CORES+NB_HWPE_PORTS-1] ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( clear_i ), + .tcdm_target ( hwpe_tcdm_slave[0] ), + .tcdm_initiator ( core_hwpe_tcdm_slave[NB_CORES:NB_CORES+NB_HWPE_PORTS-1] ) ); for(genvar ii=0; ii */ +`include "hci_helpers.svh" + import hci_package::*; import pulp_cluster_package::*; @@ -21,7 +23,8 @@ module hwpe_subsystem parameter hwpe_subsystem_cfg_t HWPE_CFG = '0, parameter int unsigned N_CORES = 8, parameter int unsigned N_MASTER_PORT = 9, - parameter int unsigned ID_WIDTH = 8 + parameter int unsigned ID_WIDTH = 8, + parameter hci_package::hci_size_parameter_t HCI_HWPE_SIZE = '0 ) ( input logic clk, @@ -37,8 +40,8 @@ module hwpe_subsystem output logic busy_o ); - localparam int unsigned DW = hwpe_xbar_master.DW; - localparam int unsigned AW = hwpe_xbar_master.AW; + localparam int unsigned DW = HCI_HWPE_SIZE.DW; + localparam int unsigned AW = HCI_HWPE_SIZE.AW; localparam int unsigned N_HWPES = HWPE_CFG.NumHwpes; @@ -105,7 +108,8 @@ module hwpe_subsystem .PE_H ( 4 ), .PE_W ( 4 ), .ID ( ID_WIDTH ), - .N_CORES ( N_CORES ) + .N_CORES ( N_CORES ), + .`HCI_SIZE_PARAM(tcdm) ( HCI_HWPE_SIZE ) ) i_neureka ( // global signals .clk_i ( hwpe_clk[i] ), @@ -179,7 +183,8 @@ module hwpe_subsystem ////////////////////// hci_core_mux_static #( - .NB_CHAN ( N_HWPES ) + .NB_CHAN ( N_HWPES ), + .`HCI_SIZE_PARAM(in) ( HCI_HWPE_SIZE ) ) i_hwpe_hci_mux ( /* Internally unused */ diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index a3d16333..4aece35b 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -304,6 +304,24 @@ logic [Cfg.NumCores-1:0] hmr_dmr_sw_synch_req, hmr_tmr_sw_synch_req; // assign s_dma_fc_irq = s_decompr_done_evt; +localparam hci_package::hci_size_parameter_t HciCoreSizeParam = '{ + DW: DataWidth, + AW: AddrWidth, + BW: DEFAULT_BW, + UW: DEFAULT_UW, + IW: DEFAULT_IW, + EW: DEFAULT_EW, + EHW: DEFAULT_EHW +}; +localparam hci_package::hci_size_parameter_t HciHwpeSizeParam = '{ + DW: Cfg.HwpeNumPorts * DataWidth, + AW: AddrWidth, + BW: DEFAULT_BW, + UW: DEFAULT_UW, + IW: DEFAULT_IW, + EW: DEFAULT_EW, + EHW: DEFAULT_EHW +}; /* logarithmic and peripheral interconnect interfaces */ // ext -> log interconnect hci_core_intf #( @@ -368,8 +386,7 @@ XBAR_TCDM_BUS s_debug_bus[Cfg.NumCores-1:0](); // FIXME: iDMA hci_core_intf #( .DW ( DataWidth ), - .AW ( AddrWidth ), - .UW ( 0 ) + .AW ( AddrWidth ) ) s_core_dmactrl_bus [0:Cfg.NumCores-1] ( .clk ( clk_i ) ); @@ -402,6 +419,15 @@ logic[Cfg.NumCores-1:0] s_enable_l1_l15_prefetch; //----------------------------------------------------------------------// localparam TCDM_ID_WIDTH = Cfg.NumCores + Cfg.DmaNumPlugs + 4 + Cfg.HwpeNumPorts; +localparam hci_package::hci_size_parameter_t HciMemSizeParam = '{ + DW: DataWidth, + AW: AddrMemWidth+2, + BW: 8, + UW: DEFAULT_UW, + IW: TCDM_ID_WIDTH, + EW: DEFAULT_EW, + EHW: DEFAULT_EHW +}; // log interconnect -> TCDM memory banks (SRAM) hci_core_intf #( @@ -610,7 +636,10 @@ cluster_interconnect_wrap #( .PE_ROUTING_LSB ( PeRoutingLsb ), .CLUSTER_ALIAS ( Cfg.ClusterAlias ), - .USE_HETEROGENEOUS_INTERCONNECT ( Cfg.UseHci ) + .USE_HETEROGENEOUS_INTERCONNECT ( Cfg.UseHci ), + .HCI_CORE_SIZE ( HciCoreSizeParam ), + .HCI_HWPE_SIZE ( HciHwpeSizeParam ), + .HCI_MEM_SIZE ( HciMemSizeParam ) ) cluster_interconnect_wrap_i ( .clk_i ( clk_i ), @@ -1155,7 +1184,8 @@ generate .HWPE_CFG ( Cfg.HwpeCfg ), .N_CORES ( Cfg.NumCores ), .N_MASTER_PORT ( Cfg.HwpeNumPorts ), - .ID_WIDTH ( Cfg.NumCores + Cfg.NumMstPeriphs ) + .ID_WIDTH ( Cfg.NumCores + Cfg.NumMstPeriphs ), + .HCI_HWPE_SIZE ( HciHwpeSizeParam ) ) hwpe_subsystem_i ( .clk ( clk_i ), .rst_n ( rst_ni ), From aa92d23245d2d3096519e7e16c1fb2e514b22211 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 10 May 2024 21:24:58 +0200 Subject: [PATCH 157/207] Update Bender.yml with new hci --- Bender.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Bender.yml b/Bender.yml index a91ae85f..d0f1b16d 100644 --- a/Bender.yml +++ b/Bender.yml @@ -29,12 +29,12 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", version: 2.0 } # branch: breaking-names + hci: { git: "https://github.com/pulp-platform/hci.git", rev: d8df176b6aeb83a96465dcde2c1466575411a8c8 } # branch: remove-automatic-parameter-prop register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: e1858900ed32702862cd1fdfc8957f5566f61ce1 } # branch: fc/hci-v2.1 - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 7a63088004aa5528bd715731702e5faf255aafaa } # branch: fc/hci-v2.1 + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 64c4b0e919ccd66d42689a7dc40942150fe9c6f2 } # branch: fc/hci-v2.1 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 2dfde5070accb32aa4aa94b026fdb07488ae430c } # branch: fc/hci-v2.1 export_include_dirs: - include From a65dbcd9ef40d6f073fd0085c5f835035f8b909a Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 10 May 2024 21:44:47 +0200 Subject: [PATCH 158/207] Update Bender.lock --- Bender.lock | 50 +++++++++++++++++++++++++++++++++++++------------- 1 file changed, 37 insertions(+), 13 deletions(-) diff --git a/Bender.lock b/Bender.lock index bdcec4f4..12f43752 100644 --- a/Bender.lock +++ b/Bender.lock @@ -7,8 +7,8 @@ packages: dependencies: - common_cells axi: - revision: fccffb5953ec8564218ba05e20adbedec845e014 - version: 0.39.1 + revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6 + version: 0.39.3 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -37,6 +37,13 @@ packages: Git: https://github.com/pulp-platform/axi_slice.git dependencies: - common_cells + axi_stream: + revision: 54891ff40455ca94a37641b9da4604647878cc07 + version: 0.1.1 + source: + Git: https://github.com/pulp-platform/axi_stream.git + dependencies: + - common_cells cluster_interconnect: revision: 89e1019d64a86425211be6200770576cbdf3e8b3 version: null @@ -52,8 +59,8 @@ packages: dependencies: - hci common_cells: - revision: ad22699793d98ef714f120c6268fe92d096a61e1 - version: 1.33.1 + revision: 0d67563b6b592549542544f1abc0f43e5d4ee8b4 + version: 1.35.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -97,8 +104,8 @@ packages: dependencies: - common_cells hci: - revision: 33bd45771ad2e2690140cb29cafe0e753065d7aa - version: 2.0.0-rc1 + revision: d8df176b6aeb83a96465dcde2c1466575411a8c8 + version: null source: Git: https://github.com/pulp-platform/hci.git dependencies: @@ -145,14 +152,16 @@ packages: Git: https://github.com/pulp-platform/icache-intc.git dependencies: [] idma: - revision: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 - version: null + revision: 95f366e56f7e772c283fb3c8b343afc4a3978375 + version: 0.6.2 source: - Git: https://github.com/pulp-platform/iDMA.git + Git: https://github.com/pulp-platform/idma.git dependencies: - axi + - axi_stream - common_cells - common_verification + - obi - register_interface l2_tcdm_hybrid_interco: revision: fa55e72859dcfb117a2788a77352193bef94ff2b @@ -168,7 +177,7 @@ packages: dependencies: - common_cells neureka: - revision: 60c51c0a5f6b30140ca99cc546ddcfde00af0044 + revision: 2dfde5070accb32aa4aa94b026fdb07488ae430c version: null source: Git: https://github.com/pulp-platform/neureka.git @@ -176,6 +185,15 @@ packages: - hci - hwpe-ctrl - hwpe-stream + - zeroriscy + obi: + revision: 1aa411df145c4ebdd61f8fed4d003c33f7b20636 + version: 0.1.2 + source: + Git: https://github.com/pulp-platform/obi.git + dependencies: + - common_cells + - common_verification per2axi: revision: 95bf23119b47fc171d9ed3734c431f71cffd9350 version: null @@ -184,7 +202,7 @@ packages: dependencies: - axi_slice redmule: - revision: 7abb25690090c7f5548a8aa905c7bf0440d4ba6b + revision: 64c4b0e919ccd66d42689a7dc40942150fe9c6f2 version: null source: Git: https://github.com/pulp-platform/redmule.git @@ -232,8 +250,8 @@ packages: dependencies: - tech_cells_generic tech_cells_generic: - revision: a9cae21902e75b1434328ecf36f85327ba5717de - version: 0.2.11 + revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf + version: 0.2.13 source: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: @@ -244,3 +262,9 @@ packages: source: Git: https://github.com/pulp-platform/timer_unit.git dependencies: [] + zeroriscy: + revision: cc4068a0ccb7691cd062b809c34b2304e7fbfa36 + version: null + source: + Git: git@github.com:yvantor/ibex.git + dependencies: [] From 103a9f45919b13c3d8fe8b8c6890a3aa46aca896 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 10 May 2024 22:06:43 +0200 Subject: [PATCH 159/207] Revert wrongly committed changes to Bender.lock Due to a Bender.local override in an upward folder --- Bender.lock | 31 +++++++------------------------ 1 file changed, 7 insertions(+), 24 deletions(-) diff --git a/Bender.lock b/Bender.lock index 12f43752..28ed757c 100644 --- a/Bender.lock +++ b/Bender.lock @@ -7,8 +7,8 @@ packages: dependencies: - common_cells axi: - revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6 - version: 0.39.3 + revision: fccffb5953ec8564218ba05e20adbedec845e014 + version: 0.39.1 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -37,13 +37,6 @@ packages: Git: https://github.com/pulp-platform/axi_slice.git dependencies: - common_cells - axi_stream: - revision: 54891ff40455ca94a37641b9da4604647878cc07 - version: 0.1.1 - source: - Git: https://github.com/pulp-platform/axi_stream.git - dependencies: - - common_cells cluster_interconnect: revision: 89e1019d64a86425211be6200770576cbdf3e8b3 version: null @@ -152,16 +145,14 @@ packages: Git: https://github.com/pulp-platform/icache-intc.git dependencies: [] idma: - revision: 95f366e56f7e772c283fb3c8b343afc4a3978375 - version: 0.6.2 + revision: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 + version: null source: - Git: https://github.com/pulp-platform/idma.git + Git: https://github.com/pulp-platform/iDMA.git dependencies: - axi - - axi_stream - common_cells - common_verification - - obi - register_interface l2_tcdm_hybrid_interco: revision: fa55e72859dcfb117a2788a77352193bef94ff2b @@ -186,14 +177,6 @@ packages: - hwpe-ctrl - hwpe-stream - zeroriscy - obi: - revision: 1aa411df145c4ebdd61f8fed4d003c33f7b20636 - version: 0.1.2 - source: - Git: https://github.com/pulp-platform/obi.git - dependencies: - - common_cells - - common_verification per2axi: revision: 95bf23119b47fc171d9ed3734c431f71cffd9350 version: null @@ -250,8 +233,8 @@ packages: dependencies: - tech_cells_generic tech_cells_generic: - revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf - version: 0.2.13 + revision: a9cae21902e75b1434328ecf36f85327ba5717de + version: 0.2.11 source: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: From 3a1ded191a970255a5ba9be614ceea9c5a4e9191 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 10 May 2024 22:18:22 +0200 Subject: [PATCH 160/207] Fix a few issues and update Bender.lock and Bender.yml --- Bender.lock | 2 +- Bender.yml | 2 +- rtl/cluster_interconnect_wrap.sv | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Bender.lock b/Bender.lock index 28ed757c..914f79bb 100644 --- a/Bender.lock +++ b/Bender.lock @@ -168,7 +168,7 @@ packages: dependencies: - common_cells neureka: - revision: 2dfde5070accb32aa4aa94b026fdb07488ae430c + revision: 9d61b67c02e262c272cd434a3982b5bbd8660afd version: null source: Git: https://github.com/pulp-platform/neureka.git diff --git a/Bender.yml b/Bender.yml index d0f1b16d..d4a3cea3 100644 --- a/Bender.yml +++ b/Bender.yml @@ -34,7 +34,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 64c4b0e919ccd66d42689a7dc40942150fe9c6f2 } # branch: fc/hci-v2.1 - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 2dfde5070accb32aa4aa94b026fdb07488ae430c } # branch: fc/hci-v2.1 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 9d61b67c02e262c272cd434a3982b5bbd8660afd } # branch: fc/hci-v2.1 export_include_dirs: - include diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index e415f28c..3662c799 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -47,7 +47,7 @@ module cluster_interconnect_wrap parameter USE_HETEROGENEOUS_INTERCONNECT = 1, parameter hci_package::hci_size_parameter_t HCI_CORE_SIZE = '0, parameter hci_package::hci_size_parameter_t HCI_HWPE_SIZE = '0, - parameter hci_package::hci_size_parameter_t HCI_MEM_SIZE = '0, + parameter hci_package::hci_size_parameter_t HCI_MEM_SIZE = '0 ) ( input logic clk_i, From 8e62a44acca5d32b65301b9878428c82b474bc94 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 10 May 2024 22:31:52 +0200 Subject: [PATCH 161/207] Update neureka to avoid assertion error --- Bender.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index d4a3cea3..ff8dc10c 100644 --- a/Bender.yml +++ b/Bender.yml @@ -34,7 +34,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 64c4b0e919ccd66d42689a7dc40942150fe9c6f2 } # branch: fc/hci-v2.1 - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 9d61b67c02e262c272cd434a3982b5bbd8660afd } # branch: fc/hci-v2.1 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 4aec41a64f70ff4ce568deb7f44b72f5e33b46d3 } # branch: fc/hci-v2.1 export_include_dirs: - include From 00685e1d905d909936236c9ad132b44d0884bce3 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 10 May 2024 22:44:07 +0200 Subject: [PATCH 162/207] Add waivers to avoid obnoxious asserts from HCI Unfortunately, on the memory side we are very much not following the HCI specs :D --- Bender.lock | 6 +++--- Bender.yml | 6 +++--- rtl/cluster_interconnect_wrap.sv | 10 ++++++++++ rtl/pulp_cluster.sv | 5 +++++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/Bender.lock b/Bender.lock index 914f79bb..afaef2a6 100644 --- a/Bender.lock +++ b/Bender.lock @@ -97,7 +97,7 @@ packages: dependencies: - common_cells hci: - revision: d8df176b6aeb83a96465dcde2c1466575411a8c8 + revision: 54cf241c99015a515ad3235fc00abeba832f29fd version: null source: Git: https://github.com/pulp-platform/hci.git @@ -168,7 +168,7 @@ packages: dependencies: - common_cells neureka: - revision: 9d61b67c02e262c272cd434a3982b5bbd8660afd + revision: dd1a82c78a4da0d9b5bb95e23a0edfe95a071de5 version: null source: Git: https://github.com/pulp-platform/neureka.git @@ -185,7 +185,7 @@ packages: dependencies: - axi_slice redmule: - revision: 64c4b0e919ccd66d42689a7dc40942150fe9c6f2 + revision: aa9f84aa7703802cf5e2549a4af6410a8c9e22bd version: null source: Git: https://github.com/pulp-platform/redmule.git diff --git a/Bender.yml b/Bender.yml index ff8dc10c..75f26b7a 100644 --- a/Bender.yml +++ b/Bender.yml @@ -29,12 +29,12 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: d8df176b6aeb83a96465dcde2c1466575411a8c8 } # branch: remove-automatic-parameter-prop + hci: { git: "https://github.com/pulp-platform/hci.git", rev: 54cf241c99015a515ad3235fc00abeba832f29fd } # branch: remove-automatic-parameter-prop register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 64c4b0e919ccd66d42689a7dc40942150fe9c6f2 } # branch: fc/hci-v2.1 - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 4aec41a64f70ff4ce568deb7f44b72f5e33b46d3 } # branch: fc/hci-v2.1 + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: aa9f84aa7703802cf5e2549a4af6410a8c9e22bd } # branch: fc/hci-v2.1 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: dd1a82c78a4da0d9b5bb95e23a0edfe95a071de5 } # branch: fc/hci-v2.1 export_include_dirs: - include diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index 3662c799..e54d3f2d 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -86,6 +86,11 @@ module cluster_interconnect_wrap .`HCI_SIZE_PARAM(cores) ( HCI_CORE_SIZE ), .`HCI_SIZE_PARAM(mems) ( HCI_MEM_SIZE ), .`HCI_SIZE_PARAM(hwpe) ( HCI_HWPE_SIZE ) +`ifndef SYNTHESIS + , + .WAIVE_RSP3_ASSERT ( 1'b1 ), + .WAIVE_RSP5_ASSERT ( 1'b1 ) +`endif ) i_hci_interconnect ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -151,6 +156,11 @@ module cluster_interconnect_wrap .`HCI_SIZE_PARAM(cores) ( HCI_CORE_SIZE ), .`HCI_SIZE_PARAM(mems) ( HCI_MEM_SIZE ), .`HCI_SIZE_PARAM(hwpe) ( HCI_HWPE_SIZE ) +`ifndef SYNTHESIS + , + .WAIVE_RSP3_ASSERT ( 1'b1 ), + .WAIVE_RSP5_ASSERT ( 1'b1 ) +`endif ) i_hci_interconnect ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 4aece35b..18862511 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -435,6 +435,11 @@ hci_core_intf #( .DW ( DataWidth ), .BW ( 8 ), .IW ( TCDM_ID_WIDTH ) +`ifndef SYNTHESIS + , + .WAIVE_RSP3_ASSERT ( 1'b1 ), + .WAIVE_RSP5_ASSERT ( 1'b1 ) +`endif ) s_tcdm_bus_sram[0:Cfg.TcdmNumBank-1] ( .clk ( clk_i ) ); From e02c85d91fc8b9bde7df9372b95e70389a612e8c Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 10 May 2024 22:56:30 +0200 Subject: [PATCH 163/207] Add more waivers in HCI and pulp_cluster --- Bender.yml | 6 +++--- rtl/cluster_interconnect_wrap.sv | 4 ++++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/Bender.yml b/Bender.yml index 75f26b7a..a060f321 100644 --- a/Bender.yml +++ b/Bender.yml @@ -29,12 +29,12 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: 54cf241c99015a515ad3235fc00abeba832f29fd } # branch: remove-automatic-parameter-prop + hci: { git: "https://github.com/pulp-platform/hci.git", rev: eaf82507bfdea772cd91b320eb2cc997d6909a7f } # branch: remove-automatic-parameter-prop register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: aa9f84aa7703802cf5e2549a4af6410a8c9e22bd } # branch: fc/hci-v2.1 - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: dd1a82c78a4da0d9b5bb95e23a0edfe95a071de5 } # branch: fc/hci-v2.1 + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: e0c39f5c13220474dafb29794b9e66fc94139727 } # branch: fc/hci-v2.1 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 4e82661acfeec8a4adac2ff49f23b6173f24e486 } # branch: fc/hci-v2.1 export_include_dirs: - include diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index e54d3f2d..5fa063c5 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -88,6 +88,8 @@ module cluster_interconnect_wrap .`HCI_SIZE_PARAM(hwpe) ( HCI_HWPE_SIZE ) `ifndef SYNTHESIS , + .WAIVE_RQ3_ASSERT ( 1'b1 ), + .WAIVE_RQ4_ASSERT ( 1'b1 ), .WAIVE_RSP3_ASSERT ( 1'b1 ), .WAIVE_RSP5_ASSERT ( 1'b1 ) `endif @@ -158,6 +160,8 @@ module cluster_interconnect_wrap .`HCI_SIZE_PARAM(hwpe) ( HCI_HWPE_SIZE ) `ifndef SYNTHESIS , + .WAIVE_RQ3_ASSERT ( 1'b1 ), + .WAIVE_RQ4_ASSERT ( 1'b1 ), .WAIVE_RSP3_ASSERT ( 1'b1 ), .WAIVE_RSP5_ASSERT ( 1'b1 ) `endif From 4d96fa80d47010574ddcd0389df4d2525147f49a Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sat, 11 May 2024 00:47:04 +0200 Subject: [PATCH 164/207] Update HCI to (finally) correct simulation? --- Bender.local | 2 ++ Bender.lock | 8 ++++---- Bender.yml | 6 +++--- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/Bender.local b/Bender.local index 5c808517..d3cce56c 100644 --- a/Bender.local +++ b/Bender.local @@ -3,3 +3,5 @@ overrides: register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic + hci: { path: "../hci" } + diff --git a/Bender.lock b/Bender.lock index afaef2a6..28ff431b 100644 --- a/Bender.lock +++ b/Bender.lock @@ -97,10 +97,10 @@ packages: dependencies: - common_cells hci: - revision: 54cf241c99015a515ad3235fc00abeba832f29fd + revision: null version: null source: - Git: https://github.com/pulp-platform/hci.git + Path: ../hci dependencies: - cluster_interconnect - hwpe-stream @@ -168,7 +168,7 @@ packages: dependencies: - common_cells neureka: - revision: dd1a82c78a4da0d9b5bb95e23a0edfe95a071de5 + revision: 0bcfdf8493e00382553ca738f4d560691d101548 version: null source: Git: https://github.com/pulp-platform/neureka.git @@ -185,7 +185,7 @@ packages: dependencies: - axi_slice redmule: - revision: aa9f84aa7703802cf5e2549a4af6410a8c9e22bd + revision: 0d6e423778928c6038728cda33e5ab93170081d0 version: null source: Git: https://github.com/pulp-platform/redmule.git diff --git a/Bender.yml b/Bender.yml index a060f321..c35dc122 100644 --- a/Bender.yml +++ b/Bender.yml @@ -29,12 +29,12 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: eaf82507bfdea772cd91b320eb2cc997d6909a7f } # branch: remove-automatic-parameter-prop + hci: { git: "https://github.com/pulp-platform/hci.git", rev: 1d533faa9028b32d7981300c516e488132d35455 } # branch: remove-automatic-parameter-prop register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: e0c39f5c13220474dafb29794b9e66fc94139727 } # branch: fc/hci-v2.1 - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 4e82661acfeec8a4adac2ff49f23b6173f24e486 } # branch: fc/hci-v2.1 + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: eec8a76f7370d32a8d092fe581579980bb3c8f35 } # branch: fc/hci-v2.1 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 702dfd8e92e4b1ca00b23209fc6be78fe60f85e0 } # branch: fc/hci-v2.1 export_include_dirs: - include From dbb1fd039daf7941295f38567a0d848bd9275caf Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sat, 11 May 2024 00:51:03 +0200 Subject: [PATCH 165/207] Use typo-fixed HCI --- Bender.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Bender.yml b/Bender.yml index c35dc122..c400b3fa 100644 --- a/Bender.yml +++ b/Bender.yml @@ -29,12 +29,12 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: 1d533faa9028b32d7981300c516e488132d35455 } # branch: remove-automatic-parameter-prop + hci: { git: "https://github.com/pulp-platform/hci.git", rev: d31af36ebcaf2196fb51676b40782aa8cbd9cc69 } # branch: remove-automatic-parameter-prop register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: eec8a76f7370d32a8d092fe581579980bb3c8f35 } # branch: fc/hci-v2.1 - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 702dfd8e92e4b1ca00b23209fc6be78fe60f85e0 } # branch: fc/hci-v2.1 + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 } # branch: fc/hci-v2.1 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 14ca68d480350dd53a4b6b601db5eb54954de266 } # branch: fc/hci-v2.1 export_include_dirs: - include From 5dfa471f96cc6d413d2b5ac33d1e9ae05a467677 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sat, 11 May 2024 00:56:23 +0200 Subject: [PATCH 166/207] Update Bender.loc{k,al} --- Bender.local | 1 - Bender.lock | 8 ++++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/Bender.local b/Bender.local index d3cce56c..ebbaaf28 100644 --- a/Bender.local +++ b/Bender.local @@ -3,5 +3,4 @@ overrides: register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic - hci: { path: "../hci" } diff --git a/Bender.lock b/Bender.lock index 28ff431b..1814a950 100644 --- a/Bender.lock +++ b/Bender.lock @@ -97,10 +97,10 @@ packages: dependencies: - common_cells hci: - revision: null + revision: d31af36ebcaf2196fb51676b40782aa8cbd9cc69 version: null source: - Path: ../hci + Git: https://github.com/pulp-platform/hci.git dependencies: - cluster_interconnect - hwpe-stream @@ -168,7 +168,7 @@ packages: dependencies: - common_cells neureka: - revision: 0bcfdf8493e00382553ca738f4d560691d101548 + revision: 14ca68d480350dd53a4b6b601db5eb54954de266 version: null source: Git: https://github.com/pulp-platform/neureka.git @@ -185,7 +185,7 @@ packages: dependencies: - axi_slice redmule: - revision: 0d6e423778928c6038728cda33e5ab93170081d0 + revision: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 version: null source: Git: https://github.com/pulp-platform/redmule.git From 4b0d9b556a1233dc71382b95367abb4dd1a01577 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Sat, 11 May 2024 01:31:04 +0200 Subject: [PATCH 167/207] Update NEUREKA to remove parasitic latches in accum. controller --- Bender.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index c400b3fa..88bf31cf 100644 --- a/Bender.yml +++ b/Bender.yml @@ -34,7 +34,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 } # branch: fc/hci-v2.1 - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 14ca68d480350dd53a4b6b601db5eb54954de266 } # branch: fc/hci-v2.1 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 4f201c238c7dd0c1f84306f40d66ebdaa8589307 } # branch: fc/hci-v2.1 export_include_dirs: - include From 0c46c6f89884dd754d6e6e487d1c47a465ad7ac3 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 11 May 2024 01:42:12 +0200 Subject: [PATCH 168/207] Fix zeroriscy URL in Bender.lock --- Bender.local | 1 - Bender.lock | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/Bender.local b/Bender.local index ebbaaf28..5c808517 100644 --- a/Bender.local +++ b/Bender.local @@ -3,4 +3,3 @@ overrides: register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic - diff --git a/Bender.lock b/Bender.lock index 1814a950..fc5b2e13 100644 --- a/Bender.lock +++ b/Bender.lock @@ -249,5 +249,5 @@ packages: revision: cc4068a0ccb7691cd062b809c34b2304e7fbfa36 version: null source: - Git: git@github.com:yvantor/ibex.git + Git: https://github.com/yvantor/ibex.git dependencies: [] From c9c12296719be0699c25e313e994f4835c4ce943 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 15 May 2024 18:33:45 +0200 Subject: [PATCH 169/207] Bump regression-tests. --- regression-tests | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/regression-tests b/regression-tests index f2206791..9fe04d0d 160000 --- a/regression-tests +++ b/regression-tests @@ -1 +1 @@ -Subproject commit f220679120dc6c4ccb82c5f4292d3add8cd134e4 +Subproject commit 9fe04d0d984a01cf0dcccc248483bb2b152912fe From 6417d215fdca9a91935998c5623e212e8d29723c Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Wed, 15 May 2024 19:39:16 +0200 Subject: [PATCH 170/207] Bump neureka. --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index fc5b2e13..9e46cbc9 100644 --- a/Bender.lock +++ b/Bender.lock @@ -168,7 +168,7 @@ packages: dependencies: - common_cells neureka: - revision: 14ca68d480350dd53a4b6b601db5eb54954de266 + revision: 6221fd4d17809166333ace71aec37b58ac28ce72 version: null source: Git: https://github.com/pulp-platform/neureka.git diff --git a/Bender.yml b/Bender.yml index 88bf31cf..8dbb9050 100644 --- a/Bender.yml +++ b/Bender.yml @@ -34,7 +34,7 @@ dependencies: common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 } # branch: fc/hci-v2.1 - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 4f201c238c7dd0c1f84306f40d66ebdaa8589307 } # branch: fc/hci-v2.1 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 6221fd4d17809166333ace71aec37b58ac28ce72 } # branch: hci-v2 export_include_dirs: - include From b0ed8519aeaa179e0b1ce7d493866b98ba7d921e Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Sat, 18 May 2024 14:59:47 +0200 Subject: [PATCH 171/207] replace hier-icache with cluster-icache Update hier-icache to a new icache originally from the snitch cluster --- Bender.lock | 28 +++----- Bender.yml | 2 +- rtl/cluster_peripherals.sv | 38 ++++++---- rtl/pulp_cluster.sv | 142 ++++++++++++------------------------- 4 files changed, 80 insertions(+), 130 deletions(-) diff --git a/Bender.lock b/Bender.lock index 9e46cbc9..0014f0c1 100644 --- a/Bender.lock +++ b/Bender.lock @@ -37,6 +37,16 @@ packages: Git: https://github.com/pulp-platform/axi_slice.git dependencies: - common_cells + cluster_icache: + revision: 229ed4ff412024a8c41cc8817e532f92beeb2c4a + version: null + source: + Git: https://github.com/pulp-platform/cluster_icache.git + dependencies: + - axi + - common_cells + - scm + - tech_cells_generic cluster_interconnect: revision: 89e1019d64a86425211be6200770576cbdf3e8b3 version: null @@ -105,18 +115,6 @@ packages: - cluster_interconnect - hwpe-stream - l2_tcdm_hybrid_interco - hier-icache: - revision: 2886cb2a46cea3e2bd2d979b505d88fadfbe150c - version: null - source: - Git: https://github.com/pulp-platform/hier-icache.git - dependencies: - - axi - - axi_slice - - common_cells - - icache-intc - - scm - - tech_cells_generic hwpe-ctrl: revision: a5966201aeeb988d607accdc55da933a53c6a56e version: null @@ -138,12 +136,6 @@ packages: Git: https://github.com/pulp-platform/ibex.git dependencies: - tech_cells_generic - icache-intc: - revision: 663c3b6d3c2bf63ff25cda46f33c799c647b3985 - version: 1.0.1 - source: - Git: https://github.com/pulp-platform/icache-intc.git - dependencies: [] idma: revision: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 version: null diff --git a/Bender.yml b/Bender.yml index 8dbb9050..2bf5e4e5 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,7 +19,7 @@ dependencies: event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master - hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "2886cb2a46cea3e2bd2d979b505d88fadfbe150c" } # branch: astral + cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "229ed4ff412024a8c41cc8817e532f92beeb2c4a" } cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2 axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index bed5b72d..92078edd 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -18,6 +18,7 @@ import pulp_cluster_package::*; +`include "common_cells/registers.svh" module cluster_peripherals #( @@ -280,20 +281,29 @@ module cluster_peripherals //******************************************************** //******************** icache_ctrl_unit ****************** //******************************************************** - - hier_icache_ctrl_unit_wrap #( - .NB_CACHE_BANKS ( NB_CACHE_BANKS ), - .NB_CORES ( NB_CORES ), - .ID_WIDTH ( NB_CORES+NB_MPERIPHS ) - ) icache_ctrl_unit_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .speriph_slave ( speriph_slave[SPER_ICACHE_CTRL] ), - .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), - .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), - .enable_l1_l15_prefetch_o ( enable_l1_l15_prefetch_o ) - ); + + assign enable_l1_l15_prefetch_o = '1; + assign speriph_slave[SPER_ICACHE_CTRL].gnt = '1; + assign speriph_slave[SPER_ICACHE_CTRL].r_rdata = '0; + assign speriph_slave[SPER_ICACHE_CTRL].r_opc = '0; + + `FF(speriph_slave[SPER_ICACHE_CTRL].r_valid, speriph_slave[SPER_ICACHE_CTRL].req, '0); + `FF(speriph_slave[SPER_ICACHE_CTRL].r_id, speriph_slave[SPER_ICACHE_CTRL].id, '0); + + + // hier_icache_ctrl_unit_wrap #( + // .NB_CACHE_BANKS ( NB_CACHE_BANKS ), + // .NB_CORES ( NB_CORES ), + // .ID_WIDTH ( NB_CORES+NB_MPERIPHS ) + // ) icache_ctrl_unit_i ( + // .clk_i ( clk_i ), + // .rst_ni ( rst_ni ), + + // .speriph_slave ( speriph_slave[SPER_ICACHE_CTRL] ), + // .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), + // .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), + // .enable_l1_l15_prefetch_o ( enable_l1_l15_prefetch_o ) + // ); //******************************************************** //******************** DMA CL CONFIG PORT **************** diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 18862511..3522a3e3 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -475,6 +475,18 @@ AXI_BUS #( .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) s_core_instr_bus(); +`AXI_TYPEDEF_ALL(instr_axi, logic[AddrWidth-1:0], logic[AxiIdInWidth-1:0], logic[Cfg.AxiDataOutWidth-1:0], logic[Cfg.AxiDataOutWidth/8-1:0], logic[Cfg.AxiUserWidth-1:0]) + +instr_axi_req_t s_core_instr_bus_req; +instr_axi_resp_t s_core_instr_bus_resp; + +always_comb begin + s_core_instr_bus.aw_addr = '0; + s_core_instr_bus.ar_addr = '0; + `AXI_SET_FROM_REQ(s_core_instr_bus, s_core_instr_bus_req) +end +`AXI_ASSIGN_TO_RESP(s_core_instr_bus_resp, s_core_instr_bus) + // ***********************************************************************************************+ // ***********************************************************************************************+ // ***********************************************************************************************+ @@ -1229,106 +1241,42 @@ generate end endgenerate -icache_hier_top #( - .FETCH_ADDR_WIDTH ( AddrWidth ), //= 32, - .PRI_FETCH_DATA_WIDTH ( Cfg.iCachePrivateDataWidth ), //= 128, // Tested for 32 and 128 - .SH_FETCH_DATA_WIDTH ( 128 ), //= 128, - - .NB_CORES ( Cfg.NumCores ), //= 8, - - .SH_NB_BANKS ( Cfg.iCacheNumBanks ), //= 1, - .SH_NB_WAYS ( Cfg.iCacheNumWays ), //= 4, - .SH_CACHE_SIZE ( Cfg.iCacheSharedSize), //= 4*1024, // in Byte - .SH_CACHE_LINE ( Cfg.iCacheNumLines ), //= 1, // in word of [SH_FETCH_DATA_WIDTH] - - .PRI_NB_WAYS ( Cfg.iCacheNumWays ), //= 4, - .PRI_CACHE_SIZE ( Cfg.iCachePrivateSize), //= 512, // in Byte - .PRI_CACHE_LINE ( Cfg.iCacheNumLines ), //= 1, // in word of [PRI_FETCH_DATA_WIDTH] - - .AXI_ID ( AxiIdInWidth ), //= 6, - .AXI_ADDR ( Cfg.AxiAddrWidth ), //= 32, - .AXI_USER ( Cfg.AxiUserWidth ), //= 6, - .AXI_DATA ( Cfg.AxiDataOutWidth ), //= 64, - - .USE_REDUCED_TAG ( Cfg.EnableReducedTag ), //= "TRUE", // TRUE | FALSE - .L2_SIZE ( Cfg.L2Size ) //= 512*1024 // Size of max(L2 ,ROM) program memory in Byte +pulp_icache_wrap #( + .NumFetchPorts ( Cfg.NumCores ), + .L0_LINE_COUNT ( 16 ), + .LINE_WIDTH ( 256 ), + .LINE_COUNT ( 32 ), + .SET_COUNT ( 4 ), + .FetchAddrWidth ( AddrWidth ), + .FetchDataWidth ( DataWidth ), + .AxiAddrWidth ( AddrWidth ), + .AxiDataWidth ( Cfg.AxiDataOutWidth ), + .axi_req_t ( instr_axi_req_t ), + .axi_rsp_t ( instr_axi_resp_t ) ) icache_top_i ( - .clk ( clk_i ), - .rst_n ( rst_ni ), - .test_en_i ( test_mode_i ), - - .fetch_req_i ( instr_req ), - .fetch_addr_i ( instr_addr ), - .fetch_gnt_o ( instr_gnt ), - - .fetch_rvalid_o ( instr_r_valid ), - .fetch_rdata_o ( instr_r_rdata ), - - .enable_l1_l15_prefetch_i ( s_enable_l1_l15_prefetch ), // set it to 1 to use prefetch feature - - //AXI read address bus ------------------------------------------- - .axi_master_arid_o ( s_core_instr_bus.ar_id ), - .axi_master_araddr_o ( s_core_instr_bus.ar_addr ), - .axi_master_arlen_o ( s_core_instr_bus.ar_len ), //burst length - 1 to 16 - .axi_master_arsize_o ( s_core_instr_bus.ar_size ), //size of each transfer in burst - .axi_master_arburst_o ( s_core_instr_bus.ar_burst ), //accept only incr burst=01 - .axi_master_arlock_o ( s_core_instr_bus.ar_lock ), //only normal access supported axs_awlock=00 - .axi_master_arcache_o ( s_core_instr_bus.ar_cache ), - .axi_master_arprot_o ( s_core_instr_bus.ar_prot ), - .axi_master_arregion_o ( s_core_instr_bus.ar_region ), // - .axi_master_aruser_o ( s_core_instr_bus.ar_user ), // - .axi_master_arqos_o ( s_core_instr_bus.ar_qos ), // - .axi_master_arvalid_o ( s_core_instr_bus.ar_valid ), //master addr valid - .axi_master_arready_i ( s_core_instr_bus.ar_ready ), //slave ready to accept - // --------------------------------------------------------------- - - //AXI BACKWARD read data bus ---------------------------------------------- - .axi_master_rid_i ( s_core_instr_bus.r_id ), - .axi_master_rdata_i ( s_core_instr_bus.r_data ), - .axi_master_rresp_i ( s_core_instr_bus.r_resp ), - .axi_master_rlast_i ( s_core_instr_bus.r_last ), //last transfer in burst - .axi_master_ruser_i ( s_core_instr_bus.r_user ), - .axi_master_rvalid_i ( s_core_instr_bus.r_valid ), //slave data valid - .axi_master_rready_o ( s_core_instr_bus.r_ready ), //master ready to accept - - // NOT USED ---------------------------------------------- - .axi_master_awid_o ( s_core_instr_bus.aw_id ), - .axi_master_awaddr_o ( s_core_instr_bus.aw_addr ), - .axi_master_awlen_o ( s_core_instr_bus.aw_len ), - .axi_master_awsize_o ( s_core_instr_bus.aw_size ), - .axi_master_awburst_o ( s_core_instr_bus.aw_burst ), - .axi_master_awlock_o ( s_core_instr_bus.aw_lock ), - .axi_master_awcache_o ( s_core_instr_bus.aw_cache ), - .axi_master_awprot_o ( s_core_instr_bus.aw_prot ), - .axi_master_awregion_o ( s_core_instr_bus.aw_region ), - .axi_master_awuser_o ( s_core_instr_bus.aw_user ), - .axi_master_awqos_o ( s_core_instr_bus.aw_qos ), - .axi_master_awvalid_o ( s_core_instr_bus.aw_valid ), - .axi_master_awready_i ( s_core_instr_bus.aw_ready ), - - // NOT USED ---------------------------------------------- - .axi_master_wdata_o ( s_core_instr_bus.w_data ), - .axi_master_wstrb_o ( s_core_instr_bus.w_strb ), - .axi_master_wlast_o ( s_core_instr_bus.w_last ), - .axi_master_wuser_o ( s_core_instr_bus.w_user ), - .axi_master_wvalid_o ( s_core_instr_bus.w_valid ), - .axi_master_wready_i ( s_core_instr_bus.w_ready ), - // --------------------------------------------------------------- - - // NOT USED ---------------------------------------------- - .axi_master_bid_i ( s_core_instr_bus.b_id ), - .axi_master_bresp_i ( s_core_instr_bus.b_resp ), - .axi_master_buser_i ( s_core_instr_bus.b_user ), - .axi_master_bvalid_i ( s_core_instr_bus.b_valid ), - .axi_master_bready_o ( s_core_instr_bus.b_ready ), - // --------------------------------------------------------------- - - .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), - .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .fetch_req_i ( instr_req ), + .fetch_addr_i ( instr_addr ), + .fetch_gnt_o ( instr_gnt ), + .fetch_rvalid_o ( instr_r_valid ), + .fetch_rdata_o ( instr_r_rdata ), + .fetch_rerror_o (), + + .enable_prefetching_i ( s_enable_l1_l15_prefetch[0] ), + .icache_l0_events_o (), + .icache_l1_events_o (), + .flush_valid_i ('0), + .flush_ready_o (), + + .sram_cfg_data_i ('0), + .sram_cfg_tag_i ('0), + + .axi_req_o ( s_core_instr_bus_req ), + .axi_rsp_i ( s_core_instr_bus_resp ) ); -assign s_core_instr_bus.aw_atop = '0; - `REG_BUS_TYPEDEF_ALL(tcdm_scrubber_reg, logic[AddrWidth-1:0], logic[DataWidth-1:0], logic[BeWidth-1:0]) tcdm_scrubber_reg_req_t tcdm_scrubber_reg_req; From a1066860f09f71e7dcca16f79e60739ad42fb90c Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 26 Mar 2024 17:38:38 +0100 Subject: [PATCH 172/207] Fix mock UART for correct last signal on AXI burst --- Bender.yml | 1 - tb/axi2apb_64_32.sv | 745 -------------------------------------------- tb/mock_uart_axi.sv | 138 ++++---- 3 files changed, 72 insertions(+), 812 deletions(-) delete mode 100644 tb/axi2apb_64_32.sv diff --git a/Bender.yml b/Bender.yml index 2bf5e4e5..f8b83e1c 100644 --- a/Bender.yml +++ b/Bender.yml @@ -83,7 +83,6 @@ sources: - target: test files: - tb/mock_uart.sv - - tb/axi2apb_64_32.sv - tb/mock_uart_axi.sv - tb/pulp_cluster_tb.sv diff --git a/tb/axi2apb_64_32.sv b/tb/axi2apb_64_32.sv deleted file mode 100644 index c98b1798..00000000 --- a/tb/axi2apb_64_32.sv +++ /dev/null @@ -1,745 +0,0 @@ -// Copyright 2014-2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the “License”); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// -// Igor Loi -// Davide Rossi -// Florian Zaruba - -`define OKAY 2'b00 -`define EXOKAY 2'b01 -`define SLVERR 2'b10 -`define DECERR 2'b11 - -module axi2apb_64_32 #( - parameter int unsigned AXI4_ADDRESS_WIDTH = 32, - parameter int unsigned AXI4_RDATA_WIDTH = 64, - parameter int unsigned AXI4_WDATA_WIDTH = 64, - parameter int unsigned AXI4_ID_WIDTH = 16, - parameter int unsigned AXI4_USER_WIDTH = 10, - parameter int unsigned AXI_NUMBYTES = AXI4_WDATA_WIDTH/8, - - parameter int unsigned BUFF_DEPTH_SLAVE = 4, - parameter int unsigned APB_NUM_SLAVES = 8, - parameter int unsigned APB_ADDR_WIDTH = 12 -) -( - input logic ACLK, - input logic ARESETn, - input logic test_en_i, - // --------------------------------------------------------- - // AXI TARG Port Declarations ------------------------------ - // --------------------------------------------------------- - //AXI write address bus -------------- // USED// ----------- - input logic [AXI4_ID_WIDTH-1:0] AWID_i , - input logic [AXI4_ADDRESS_WIDTH-1:0] AWADDR_i , - input logic [ 7:0] AWLEN_i , - input logic [ 2:0] AWSIZE_i , - input logic [ 1:0] AWBURST_i , - input logic AWLOCK_i , - input logic [ 3:0] AWCACHE_i , - input logic [ 2:0] AWPROT_i , - input logic [ 3:0] AWREGION_i , - input logic [ AXI4_USER_WIDTH-1:0] AWUSER_i , - input logic [ 3:0] AWQOS_i , - input logic AWVALID_i , - output logic AWREADY_o , - // --------------------------------------------------------- - - //AXI write data bus -------------- // USED// -------------- - input logic [AXI_NUMBYTES-1:0][7:0] WDATA_i , - input logic [AXI_NUMBYTES-1:0] WSTRB_i , - input logic WLAST_i , - input logic [AXI4_USER_WIDTH-1:0] WUSER_i , - input logic WVALID_i , - output logic WREADY_o , - // --------------------------------------------------------- - - //AXI write response bus -------------- // USED// ---------- - output logic [AXI4_ID_WIDTH-1:0] BID_o , - output logic [ 1:0] BRESP_o , - output logic BVALID_o , - output logic [AXI4_USER_WIDTH-1:0] BUSER_o , - input logic BREADY_i , - // --------------------------------------------------------- - - //AXI read address bus ------------------------------------- - input logic [AXI4_ID_WIDTH-1:0] ARID_i , - input logic [AXI4_ADDRESS_WIDTH-1:0] ARADDR_i , - input logic [ 7:0] ARLEN_i , - input logic [ 2:0] ARSIZE_i , - input logic [ 1:0] ARBURST_i , - input logic ARLOCK_i , - input logic [ 3:0] ARCACHE_i , - input logic [ 2:0] ARPROT_i , - input logic [ 3:0] ARREGION_i , - input logic [ AXI4_USER_WIDTH-1:0] ARUSER_i , - input logic [ 3:0] ARQOS_i , - input logic ARVALID_i , - output logic ARREADY_o , - // --------------------------------------------------------- - - //AXI read data bus ---------------------------------------- - output logic [AXI4_ID_WIDTH-1:0] RID_o , - output logic [AXI4_RDATA_WIDTH-1:0] RDATA_o , - output logic [ 1:0] RRESP_o , - output logic RLAST_o , - output logic [AXI4_USER_WIDTH-1:0] RUSER_o , - output logic RVALID_o , - input logic RREADY_i , - // --------------------------------------------------------- - - output logic PENABLE , - output logic PWRITE , - output logic [APB_ADDR_WIDTH-1:0] PADDR , - output logic PSEL , - output logic [31:0] PWDATA , - input logic [31:0] PRDATA , - input logic PREADY , - input logic PSLVERR -); - - // -------------------- - // AXI write address bus - // -------------------- - logic [AXI4_ID_WIDTH-1:0] AWID; - logic [AXI4_ADDRESS_WIDTH-1:0] AWADDR; - logic [ 7:0] AWLEN; - logic [ 2:0] AWSIZE; - logic [ 1:0] AWBURST; - logic AWLOCK; - logic [ 3:0] AWCACHE; - logic [ 2:0] AWPROT; - logic [ 3:0] AWREGION; - logic [ AXI4_USER_WIDTH-1:0] AWUSER; - logic [ 3:0] AWQOS; - logic AWVALID; - logic AWREADY; - // -------------------- - // AXI write data bus - // -------------------- - logic [1:0][31:0] WDATA; // from FIFO - logic [AXI_NUMBYTES-1:0] WSTRB; // from FIFO - logic WLAST; // from FIFO - logic [AXI4_USER_WIDTH-1:0] WUSER; // from FIFO - logic WVALID; // from FIFO - logic WREADY; // TO FIFO - // -------------------- - // AXI write response bus - // -------------------- - logic [AXI4_ID_WIDTH-1:0] BID; - logic [ 1:0] BRESP; - logic BVALID; - logic [AXI4_USER_WIDTH-1:0] BUSER; - logic BREADY; - // -------------------- - // AXI read address bus - // -------------------- - logic [AXI4_ID_WIDTH-1:0] ARID; - logic [AXI4_ADDRESS_WIDTH-1:0] ARADDR; - logic [ 7:0] ARLEN; - logic [ 2:0] ARSIZE; - logic [ 1:0] ARBURST; - logic ARLOCK; - logic [ 3:0] ARCACHE; - logic [ 2:0] ARPROT; - logic [ 3:0] ARREGION; - logic [ AXI4_USER_WIDTH-1:0] ARUSER; - logic [ 3:0] ARQOS; - logic ARVALID; - logic ARREADY; - // -------------------- - // AXI read data bus - // -------------------- - logic [AXI4_ID_WIDTH-1:0] RID; - logic [1:0][31:0] RDATA; - logic [ 1:0] RRESP; - logic RLAST; - logic [AXI4_USER_WIDTH-1:0] RUSER; - logic RVALID; - logic RREADY; - - enum logic [3:0] { IDLE, - SINGLE_RD, SINGLE_RD_64, - BURST_RD_1, BURST_RD, BURST_RD_64, - BURST_WR, BURST_WR_64, - SINGLE_WR,SINGLE_WR_64, - WAIT_R_PREADY, WAIT_W_PREADY - } CS, NS; - - logic W_word_sel; - - logic [APB_ADDR_WIDTH-1:0] address; - - logic read_req; - logic write_req; - - logic sample_AR; - logic [8:0] ARLEN_Q; - logic decr_ARLEN; - - logic sample_AW; - logic [8:0] AWLEN_Q; - logic decr_AWLEN; - - logic [AXI4_ADDRESS_WIDTH-1:0] ARADDR_Q; - logic incr_ARADDR; - - logic [AXI4_ADDRESS_WIDTH-1:0] AWADDR_Q; - logic incr_AWADDR; - - logic sample_RDATA_0; // sample the first 32 bit chunk to be aggregated in 64 bit rdata - logic sample_RDATA_1; // sample the second 32 bit chunk to be aggregated in 64 bit rdata - logic [31:0] RDATA_Q_0; - logic [31:0] RDATA_Q_1; - - assign PENABLE = write_req | read_req; - assign PWRITE = write_req; - assign PADDR = address[APB_ADDR_WIDTH-1:0]; - - assign PWDATA = WDATA[W_word_sel]; - assign PSEL = 1'b1; - - // AXI WRITE ADDRESS CHANNEL BUFFER - axi_aw_buffer #( - .ID_WIDTH ( AXI4_ID_WIDTH ), - .ADDR_WIDTH ( AXI4_ADDRESS_WIDTH ), - .USER_WIDTH ( AXI4_USER_WIDTH ), - .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) - ) slave_aw_buffer_i ( - .clk_i ( ACLK ), - .rst_ni ( ARESETn ), - .test_en_i ( test_en_i ), - .slave_valid_i ( AWVALID_i ), - .slave_addr_i ( AWADDR_i ), - .slave_prot_i ( AWPROT_i ), - .slave_region_i ( AWREGION_i ), - .slave_len_i ( AWLEN_i ), - .slave_size_i ( AWSIZE_i ), - .slave_burst_i ( AWBURST_i ), - .slave_lock_i ( AWLOCK_i ), - .slave_cache_i ( AWCACHE_i ), - .slave_qos_i ( AWQOS_i ), - .slave_id_i ( AWID_i ), - .slave_user_i ( AWUSER_i ), - .slave_ready_o ( AWREADY_o ), - .master_valid_o ( AWVALID ), - .master_addr_o ( AWADDR ), - .master_prot_o ( AWPROT ), - .master_region_o ( AWREGION ), - .master_len_o ( AWLEN ), - .master_size_o ( AWSIZE ), - .master_burst_o ( AWBURST ), - .master_lock_o ( AWLOCK ), - .master_cache_o ( AWCACHE ), - .master_qos_o ( AWQOS ), - .master_id_o ( AWID ), - .master_user_o ( AWUSER ), - .master_ready_i ( AWREADY ) - ); - // AXI WRITE ADDRESS CHANNEL BUFFER - axi_ar_buffer #( - .ID_WIDTH ( AXI4_ID_WIDTH ), - .ADDR_WIDTH ( AXI4_ADDRESS_WIDTH ), - .USER_WIDTH ( AXI4_USER_WIDTH ), - .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) - ) slave_ar_buffer_i ( - .clk_i ( ACLK ), - .rst_ni ( ARESETn ), - .test_en_i ( test_en_i ), - .slave_valid_i ( ARVALID_i ), - .slave_addr_i ( ARADDR_i ), - .slave_prot_i ( ARPROT_i ), - .slave_region_i ( ARREGION_i ), - .slave_len_i ( ARLEN_i ), - .slave_size_i ( ARSIZE_i ), - .slave_burst_i ( ARBURST_i ), - .slave_lock_i ( ARLOCK_i ), - .slave_cache_i ( ARCACHE_i ), - .slave_qos_i ( ARQOS_i ), - .slave_id_i ( ARID_i ), - .slave_user_i ( ARUSER_i ), - .slave_ready_o ( ARREADY_o ), - .master_valid_o ( ARVALID ), - .master_addr_o ( ARADDR ), - .master_prot_o ( ARPROT ), - .master_region_o ( ARREGION ), - .master_len_o ( ARLEN ), - .master_size_o ( ARSIZE ), - .master_burst_o ( ARBURST ), - .master_lock_o ( ARLOCK ), - .master_cache_o ( ARCACHE ), - .master_qos_o ( ARQOS ), - .master_id_o ( ARID ), - .master_user_o ( ARUSER ), - .master_ready_i ( ARREADY ) - ); - axi_w_buffer #( - .DATA_WIDTH ( AXI4_WDATA_WIDTH ), - .USER_WIDTH ( AXI4_USER_WIDTH ), - .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) - ) slave_w_buffer_i ( - .clk_i ( ACLK ), - .rst_ni ( ARESETn ), - .test_en_i ( test_en_i ), - .slave_valid_i ( WVALID_i ), - .slave_data_i ( WDATA_i ), - .slave_strb_i ( WSTRB_i ), - .slave_user_i ( WUSER_i ), - .slave_last_i ( WLAST_i ), - .slave_ready_o ( WREADY_o ), - .master_valid_o ( WVALID ), - .master_data_o ( WDATA ), - .master_strb_o ( WSTRB ), - .master_user_o ( WUSER ), - .master_last_o ( WLAST ), - .master_ready_i ( WREADY ) - ); - axi_r_buffer #( - .ID_WIDTH ( AXI4_ID_WIDTH ), - .DATA_WIDTH ( AXI4_RDATA_WIDTH ), - .USER_WIDTH ( AXI4_USER_WIDTH ), - .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) - ) slave_r_buffer_i ( - .clk_i ( ACLK ), - .rst_ni ( ARESETn ), - .test_en_i ( test_en_i ), - .slave_valid_i ( RVALID ), - .slave_data_i ( RDATA ), - .slave_resp_i ( RRESP ), - .slave_user_i ( RUSER ), - .slave_id_i ( RID ), - .slave_last_i ( RLAST ), - .slave_ready_o ( RREADY ), - .master_valid_o ( RVALID_o ), - .master_data_o ( RDATA_o ), - .master_resp_o ( RRESP_o ), - .master_user_o ( RUSER_o ), - .master_id_o ( RID_o ), - .master_last_o ( RLAST_o ), - .master_ready_i ( RREADY_i ) - ); - - axi_b_buffer #( - .ID_WIDTH ( AXI4_ID_WIDTH ), - .USER_WIDTH ( AXI4_USER_WIDTH ), - .BUFFER_DEPTH ( BUFF_DEPTH_SLAVE ) - ) slave_b_buffer_i ( - .clk_i ( ACLK ), - .rst_ni ( ARESETn ), - .test_en_i ( test_en_i ), - - .slave_valid_i ( BVALID ), - .slave_resp_i ( BRESP ), - .slave_id_i ( BID ), - .slave_user_i ( BUSER ), - .slave_ready_o ( BREADY ), - - .master_valid_o ( BVALID_o ), - .master_resp_o ( BRESP_o ), - .master_id_o ( BID_o ), - .master_user_o ( BUSER_o ), - .master_ready_i ( BREADY_i ) - ); - - always_comb begin - read_req = 1'b0; - write_req = 1'b0; - W_word_sel = 1'b0; // Write Word Selector - - sample_AW = 1'b0; - decr_AWLEN = 1'b0; - sample_AR = 1'b0; - decr_ARLEN = 1'b0; - - incr_AWADDR = 1'b0; - incr_ARADDR = 1'b0; - - sample_RDATA_0 = 1'b0; - sample_RDATA_1 = 1'b0; - - ARREADY = 1'b0; - AWREADY = 1'b0; - WREADY = 1'b0; - RDATA = '0; - - BVALID = 1'b0; - BRESP = `OKAY; - BID = AWID; - BUSER = AWUSER; - - RVALID = 1'b0; - RLAST = 1'b0; - RID = ARID; - RUSER = ARUSER; - RRESP = `OKAY; - - case(CS) - - WAIT_R_PREADY: begin - sample_AR = 1'b0; - read_req = 1'b1; - address = ARADDR; - - if (PREADY == 1'b1) begin// APB is READY --> RDATA is AVAILABLE - if (ARLEN == 0) begin - case (ARSIZE) - 3'h3: begin - NS = SINGLE_RD_64; - if (ARADDR[2:0] == 3'h4) - sample_RDATA_1 = 1'b1; - else sample_RDATA_0 = 1'b1; - end - - default: begin - NS = SINGLE_RD; - if (ARADDR[2:0] == 3'h4) - sample_RDATA_1 = 1'b1; - else - sample_RDATA_0 = 1'b1; - end - endcase - end else begin // ARLEN > 0 --> BURST - NS = BURST_RD_64; - sample_RDATA_0 = 1'b1; - decr_ARLEN = 1'b1; - incr_ARADDR = 1'b1; - end - end else begin // APB not ready - NS = WAIT_R_PREADY; - end - end - - WAIT_W_PREADY: begin - address = AWADDR; - write_req = 1'b1; - - if (AWADDR[2:0] == 3'h4) - W_word_sel = 1'b1; - else - W_word_sel = 1'b0; - - // There is a Pending WRITE!! - if (PREADY == 1'b1) begin // APB is READY --> WDATA is LAtched - if (AWLEN == 0) begin // single write - case (AWSIZE) - 3'h3: NS = SINGLE_WR_64; - default: NS = SINGLE_WR; - endcase - end else begin // BURST WRITE - sample_AW = 1'b1; - NS = BURST_WR_64; - end - end else begin // APB not READY - NS = WAIT_W_PREADY; - end - end - - IDLE: begin - if (ARVALID == 1'b1) begin - sample_AR = 1'b1; - read_req = 1'b1; - address = ARADDR; - - if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE - if (ARLEN == 0) begin - case (ARSIZE) - 3'h3: begin - NS = SINGLE_RD_64; - if (ARADDR[2:0] == 4) - sample_RDATA_1 = 1'b1; - else - sample_RDATA_0 = 1'b1; - end - default: begin - NS = SINGLE_RD; - if (ARADDR[2:0] == 4) - sample_RDATA_1 = 1'b1; - else - sample_RDATA_0 = 1'b1; - end - endcase end else begin //ARLEN > 0 --> BURST - NS = BURST_RD_64; - sample_RDATA_0 = 1'b1; - end - end else begin // APB not ready - NS = WAIT_R_PREADY; - end - end else begin - - if (AWVALID) begin //: _VALID_AW_REQ_ - if (WVALID) begin // : _VALID_W_REQ_ - write_req = 1'b1; - address = AWADDR; - - if (AWADDR[2:0] == 3'h4) - W_word_sel = 1'b1; - else - W_word_sel = 1'b0; - - // There is a Pending WRITE!! - if (PREADY == 1'b1) begin// APB is READY --> WDATA is LAtched _APB_SLAVE_READY_ - if(AWLEN == 0) begin //: _SINGLE_WRITE_ - case(AWSIZE) - 3'h3: NS = SINGLE_WR_64; - default: NS = SINGLE_WR; - endcase - end else begin // BURST WRITE - sample_AW = 1'b1; - if ((AWADDR[2:0] == 3'h4) && (WSTRB[7:4] == 0)) - incr_AWADDR = 1'b0; - else - incr_AWADDR = 1'b1; - NS = BURST_WR_64; - end - end else begin// APB not READY - NS = WAIT_W_PREADY; - end - end else begin // GOT ADDRESS WRITE, not DATA - write_req = 1'b0; - address = '0; - NS = IDLE; - end - end else begin// No requests - NS = IDLE; - address = '0; - end - end - end - - SINGLE_WR_64: begin - address = AWADDR + 4; - W_word_sel = 1'b1; // write the Second data chunk - write_req = WVALID; - if (WVALID) begin - if (PREADY == 1'b1) - NS = SINGLE_WR; - else - NS = SINGLE_WR_64; - end else begin - NS = SINGLE_WR_64; - end - end - - SINGLE_WR: begin - BVALID = 1'b1; - address = '0; - if (BREADY) begin - NS = IDLE; - AWREADY = 1'b1; - WREADY = 1'b1; - end else begin - NS = SINGLE_WR; - end - end - - BURST_WR_64: begin - W_word_sel = 1'b1; // write the Second data chunk first - write_req = WVALID & (|WSTRB[7:4]); - address = AWADDR_Q; // second Chunk, Fixzed Burst - - if (WVALID) begin - if (&WSTRB[7:4]) begin - if(PREADY == 1'b1) begin - NS = BURST_WR; - WREADY = 1'b1; // pop onother data from the WDATA fifo - decr_AWLEN = 1'b1; // decrement the remaining BURST beat - incr_AWADDR = 1'b1; // increment address - end else begin - NS = BURST_WR_64; - end - end else begin - NS = BURST_WR; - WREADY = 1'b1; // pop onother data from the WDATA fifo - decr_AWLEN = 1'b1; // decrement the remaining BURST beat - incr_AWADDR = 1'b1; // increment address - end - end else begin - NS = BURST_WR_64; - end - end - - BURST_WR: begin - address = AWADDR_Q; // second Chunk, Fixzed Burst - if (AWLEN_Q == 0) begin // last : _BURST_COMPLETED_ - BVALID = 1'b1; - if (BREADY) begin - NS = IDLE; - AWREADY = 1'b1; - end else - NS = BURST_WR; - end else begin //: _BUSRST_NOT_COMPLETED_ - W_word_sel = 1'b0; // write the Second data chunk first - write_req = WVALID & (&WSTRB[3:0]); - if (WVALID) begin - if (PREADY == 1'b1) begin - NS = BURST_WR_64; - incr_AWADDR = 1'b1; - decr_AWLEN = 1'b1; //decrement the remaining BURST beat - end else - NS = BURST_WR; - end else begin - NS = BURST_WR_64; - end - end - end - - BURST_RD_64: begin - read_req = 1'b1; - address = ARADDR_Q; - - if (ARLEN_Q == 0) begin // burst completed - NS = IDLE; - ARREADY = 1'b1; - end else begin - if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE - decr_ARLEN = 1'b1; - sample_RDATA_1 = 1'b1; - NS = BURST_RD; - - if (ARADDR_Q[2:0] == 3'h4) - incr_ARADDR = 1'b1; - else - incr_ARADDR = 1'b0; - end - else begin - NS = BURST_RD_64; - end - end - end - - BURST_RD: begin - RVALID = 1'b1; - RDATA[0] = RDATA_Q_0; - RDATA[1] = RDATA_Q_1; - RLAST = (ARLEN_Q == 0) ? 1'b1 : 1'b0; - address = ARADDR_Q; - - if (RREADY) begin // ready to send back the rdata - if (ARLEN_Q == 0) begin // burst completed - NS = IDLE; - ARREADY = 1'b1; - end else begin //: _READ_BUSRST_NOT_COMPLETED_ - read_req = 1'b1; - if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE - sample_RDATA_0 = 1'b1; - NS = BURST_RD_64; - incr_ARADDR = 1'b1; - decr_ARLEN = 1'b1; - end else begin - NS = BURST_RD_1; - end - end - end else begin // NOT ready to send back the rdata - NS = BURST_RD; - end - end - - BURST_RD_1: begin - read_req = 1'b1; - address = ARADDR_Q; - - if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE - sample_RDATA_0 = 1'b1; - NS = BURST_RD_64; - incr_ARADDR = 1'b1; - decr_ARLEN = 1'b1; - end else begin - NS = BURST_RD_1; - end - end - - SINGLE_RD: begin - RVALID = 1'b1; - RDATA[0] = RDATA_Q_0; - RDATA[1] = RDATA_Q_1; - RLAST = 1; - address = '0; - - if (RREADY) begin // ready to send back the rdata - NS = IDLE; - ARREADY = 1'b1; - end else begin // NOT ready to send back the rdata - NS = SINGLE_RD; - end - end - - SINGLE_RD_64: begin - read_req = 1'b1; - address = ARADDR + 4; - if (PREADY == 1'b1) begin // APB is READY --> RDATA is AVAILABLE - NS = SINGLE_RD; - if(ARADDR[2:0] == 3'h4) - sample_RDATA_0 = 1'b1; - else - sample_RDATA_1 = 1'b1; - end else begin - NS = SINGLE_RD_64; - end - end - - default: begin - NS = IDLE; - address = '0; - end - endcase - end - - // ----------- - // Registers - // ----------- - always_ff @(posedge ACLK, negedge ARESETn) begin - if (ARESETn == 1'b0) begin - CS <= IDLE; - //Read Channel - ARLEN_Q <= '0; - AWADDR_Q <= '0; - //Write Channel - AWLEN_Q <= '0; - RDATA_Q_0 <= '0; - RDATA_Q_1 <= '0; - ARADDR_Q <= '0; - end else begin - CS <= NS; - - if (sample_AR) begin - ARLEN_Q <= {ARLEN,1'b0} + 2; - end else if (decr_ARLEN) begin - ARLEN_Q <= ARLEN_Q - 1; - end - - if (sample_RDATA_0) - RDATA_Q_0 <= PRDATA; - - if (sample_RDATA_1) - RDATA_Q_1 <= PRDATA; - - case ({sample_AW, decr_AWLEN}) - 2'b00: AWLEN_Q <= AWLEN_Q; - 2'b01: AWLEN_Q <= AWLEN_Q - 1; - 2'b10: AWLEN_Q <= {AWLEN, 1'b0} + 1; - 2'b11: AWLEN_Q <= {AWLEN, 1'b0}; - endcase - - case ({sample_AW, incr_AWADDR}) - 2'b00: AWADDR_Q <= AWADDR_Q; - 2'b01: AWADDR_Q <= AWADDR_Q + 4; - 2'b10: AWADDR_Q <= {AWADDR[AXI4_ADDRESS_WIDTH-1:3], 3'b000}; - 2'b11: AWADDR_Q <= {AWADDR[AXI4_ADDRESS_WIDTH-1:3], 3'b000} + 4; - endcase - - case({sample_AR, incr_ARADDR}) - 2'b00: ARADDR_Q <= ARADDR_Q; - 2'b01: ARADDR_Q <= ARADDR_Q + 4; - 2'b10: ARADDR_Q <= {ARADDR[AXI4_ADDRESS_WIDTH-1:3], 3'b000}; - 2'b11: ARADDR_Q <= {ARADDR[AXI4_ADDRESS_WIDTH-1:3], 3'b000} + 4; - endcase - end - end -endmodule diff --git a/tb/mock_uart_axi.sv b/tb/mock_uart_axi.sv index 46049d23..80406a87 100644 --- a/tb/mock_uart_axi.sv +++ b/tb/mock_uart_axi.sv @@ -26,77 +26,83 @@ module mock_uart_axi #( logic uart_penable; logic uart_pwrite; - logic [31:0] uart_paddr; + logic [AxiAw-1:0] uart_paddr; logic uart_psel; logic [31:0] uart_pwdata; logic [31:0] uart_prdata; logic uart_pready; logic uart_pslverr; - axi2apb_64_32 #( - .AXI4_ADDRESS_WIDTH ( AxiAw ), - .AXI4_RDATA_WIDTH ( AxiDw ), - .AXI4_WDATA_WIDTH ( AxiDw ), - .AXI4_ID_WIDTH ( AxiIw ), - .AXI4_USER_WIDTH ( AxiUw ), - .BUFF_DEPTH_SLAVE ( 2 ), - .APB_ADDR_WIDTH ( 32 ) - ) i_axi2apb_64_32_uart ( - .ACLK ( clk_i ), - .ARESETn ( rst_ni ), - .test_en_i ( 1'b0 ), - .AWID_i ( uart.aw_id ), - .AWADDR_i ( uart.aw_addr ), - .AWLEN_i ( uart.aw_len ), - .AWSIZE_i ( uart.aw_size ), - .AWBURST_i ( uart.aw_burst ), - .AWLOCK_i ( uart.aw_lock ), - .AWCACHE_i ( uart.aw_cache ), - .AWPROT_i ( uart.aw_prot ), - .AWREGION_i( uart.aw_region ), - .AWUSER_i ( uart.aw_user ), - .AWQOS_i ( uart.aw_qos ), - .AWVALID_i ( uart.aw_valid ), - .AWREADY_o ( uart.aw_ready ), - .WDATA_i ( uart.w_data ), - .WSTRB_i ( uart.w_strb ), - .WLAST_i ( uart.w_last ), - .WUSER_i ( uart.w_user ), - .WVALID_i ( uart.w_valid ), - .WREADY_o ( uart.w_ready ), - .BID_o ( uart.b_id ), - .BRESP_o ( uart.b_resp ), - .BVALID_o ( uart.b_valid ), - .BUSER_o ( uart.b_user ), - .BREADY_i ( uart.b_ready ), - .ARID_i ( uart.ar_id ), - .ARADDR_i ( uart.ar_addr ), - .ARLEN_i ( uart.ar_len ), - .ARSIZE_i ( uart.ar_size ), - .ARBURST_i ( uart.ar_burst ), - .ARLOCK_i ( uart.ar_lock ), - .ARCACHE_i ( uart.ar_cache ), - .ARPROT_i ( uart.ar_prot ), - .ARREGION_i( uart.ar_region ), - .ARUSER_i ( uart.ar_user ), - .ARQOS_i ( uart.ar_qos ), - .ARVALID_i ( uart.ar_valid ), - .ARREADY_o ( uart.ar_ready ), - .RID_o ( uart.r_id ), - .RDATA_o ( uart.r_data ), - .RRESP_o ( uart.r_resp ), - .RLAST_o ( uart.r_last ), - .RUSER_o ( uart.r_user ), - .RVALID_o ( uart.r_valid ), - .RREADY_i ( uart.r_ready ), - .PENABLE ( uart_penable ), - .PWRITE ( uart_pwrite ), - .PADDR ( uart_paddr ), - .PSEL ( uart_psel ), - .PWDATA ( uart_pwdata ), - .PRDATA ( uart_prdata ), - .PREADY ( uart_pready ), - .PSLVERR ( uart_pslverr ) + AXI_LITE #( + .AXI_DATA_WIDTH(AxiDw), + .AXI_ADDR_WIDTH(AxiAw) + ) uart_lite_wide(); + + AXI_LITE #( + .AXI_DATA_WIDTH(32), + .AXI_ADDR_WIDTH(AxiAw) + ) uart_lite(); + + axi_to_axi_lite_intf #( + .AXI_ADDR_WIDTH ( AxiAw ), + .AXI_DATA_WIDTH ( AxiDw ), + .AXI_ID_WIDTH ( AxiIw ), + .AXI_USER_WIDTH ( AxiUw ), + .AXI_MAX_WRITE_TXNS(1), + .AXI_MAX_READ_TXNS (1), + .FALL_THROUGH (1'b1), + .FULL_BW (1'b1) + ) i_axi_to_axi_lite_intf ( + .clk_i, + .rst_ni, + .testmode_i(test_i), + .slv (uart), + .mst (uart_lite_wide) + ); + + axi_lite_dw_converter_intf #( + .AXI_ADDR_WIDTH (AxiAw), + .AXI_SLV_PORT_DATA_WIDTH(AxiDw), + .AXI_MST_PORT_DATA_WIDTH(32) + ) i_axi_lite_dw_converter_intf ( + .clk_i ( clk_i ), + .rst_ni( rst_ni ), + .slv ( uart_lite_wide ), + .mst ( uart_lite ) + ); + + typedef struct packed { + int unsigned idx; + logic [AxiAw-1:0] start_addr; + logic [AxiAw-1:0] end_addr; + } rule_t; + + rule_t [0:0] rule; + assign rule[0] = '{0, '0, '1}; + + axi_lite_to_apb_intf #( + .NoApbSlaves (1), + .NoRules (1), + .AddrWidth (AxiAw), + .DataWidth (32), + .PipelineRequest (1'b0), + .PipelineResponse(1'b0), + .rule_t (rule_t) + ) i_axi_lite_to_apb_intf ( + .clk_i, + .rst_ni, + .slv ( uart_lite ), + .paddr_o ( uart_paddr ), + .pprot_o ( ), + .pselx_o ( uart_psel ), + .penable_o ( uart_penable ), + .pwrite_o ( uart_pwrite ), + .pwdata_o ( uart_pwdata ), + .pstrb_o ( ), + .pready_i ( uart_pready ), + .prdata_i ( uart_prdata ), + .pslverr_i ( uart_pslverr ), + .addr_map_i(rule) ); /* pragma translate_off */ @@ -105,7 +111,7 @@ module mock_uart_axi #( .rst_ni ( rst_ni ), .penable_i ( uart_penable ), .pwrite_i ( uart_pwrite ), - .paddr_i ( uart_paddr ), + .paddr_i ( uart_paddr[31:0] ), .psel_i ( uart_psel ), .pwdata_i ( uart_pwdata ), .prdata_o ( uart_prdata ), From bd08235679b0f16ddf27f7543c29c38367de1222 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Thu, 25 Apr 2024 15:47:31 +0200 Subject: [PATCH 173/207] Update icache parameters --- rtl/pulp_cluster.sv | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 3522a3e3..e7647a0a 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -1242,26 +1242,26 @@ generate endgenerate pulp_icache_wrap #( - .NumFetchPorts ( Cfg.NumCores ), - .L0_LINE_COUNT ( 16 ), - .LINE_WIDTH ( 256 ), - .LINE_COUNT ( 32 ), - .SET_COUNT ( 4 ), - .FetchAddrWidth ( AddrWidth ), - .FetchDataWidth ( DataWidth ), - .AxiAddrWidth ( AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataOutWidth ), - .axi_req_t ( instr_axi_req_t ), - .axi_rsp_t ( instr_axi_resp_t ) + .NumFetchPorts ( Cfg.NumCores ), + .L0_LINE_COUNT ( Cfg.iCachePrivateSize*8/256 ), + .LINE_WIDTH ( 256 ), // Ideally 32*NumCores + .LINE_COUNT ( Cfg.iCacheSharedSize*8/256/Cfg.iCacheNumWays ), + .SET_COUNT ( Cfg.iCacheNumWays ), + .FetchAddrWidth ( AddrWidth ), + .FetchDataWidth ( Cfg.iCachePrivateDataWidth ), + .AxiAddrWidth ( AddrWidth ), + .AxiDataWidth ( Cfg.AxiDataOutWidth ), + .axi_req_t ( instr_axi_req_t ), + .axi_rsp_t ( instr_axi_resp_t ) ) icache_top_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .fetch_req_i ( instr_req ), - .fetch_addr_i ( instr_addr ), - .fetch_gnt_o ( instr_gnt ), - .fetch_rvalid_o ( instr_r_valid ), - .fetch_rdata_o ( instr_r_rdata ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .fetch_req_i ( instr_req ), + .fetch_addr_i ( instr_addr ), + .fetch_gnt_o ( instr_gnt ), + .fetch_rvalid_o ( instr_r_valid ), + .fetch_rdata_o ( instr_r_rdata ), .fetch_rerror_o (), .enable_prefetching_i ( s_enable_l1_l15_prefetch[0] ), From fff4f6b419ddb975ad2173546d949a1d133e810e Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 30 Apr 2024 14:18:00 +0200 Subject: [PATCH 174/207] Minor fixes --- Makefile | 2 +- rtl/cluster_peripherals.sv | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 9ba4d606..12893585 100644 --- a/Makefile +++ b/Makefile @@ -124,7 +124,7 @@ compile: $(library) $(VSIM) -c -do 'quit -code [source scripts/compile.tcl]' build: compile - $(VOPT) $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis + $(VOPT) $(compile_flag) -suppress 3053 -suppress 8885 -work $(library) $(top_level) -o $(top_level)_optimized +acc run: $(VSIM) +permissive $(questa-flags) $(uvm-flags) $(QUESTASIM_FLAGS) $(questa-cmd) -suppress 3053 -suppress 8885 -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) +APP=$(elf-bin) +notimingchecks +nospecify -t 1ps \ diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index 92078edd..c2b32b1b 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -16,11 +16,10 @@ * Francesco Conti */ -import pulp_cluster_package::*; - `include "common_cells/registers.svh" -module cluster_peripherals +module cluster_peripherals + import pulp_cluster_package::*; #( parameter NB_CORES = 8, parameter NB_HWPES = 8, From 084029a2e5da493129d4109dc8ead9229f4d5bfd Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 30 Apr 2024 14:28:59 +0200 Subject: [PATCH 175/207] cleanup common_cells dependency --- Bender.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Bender.yml b/Bender.yml index f8b83e1c..d01c8b0e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -23,7 +23,7 @@ dependencies: cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2 axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.35.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } riscv: { git: "https://github.com/AlSaqr-platform/riscv_nn.git", rev: astral-v1.0 } cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch @@ -31,7 +31,6 @@ dependencies: scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating hci: { git: "https://github.com/pulp-platform/hci.git", rev: d31af36ebcaf2196fb51676b40782aa8cbd9cc69 } # branch: remove-automatic-parameter-prop register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 } # branch: fc/hci-v2.1 neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 6221fd4d17809166333ace71aec37b58ac28ce72 } # branch: hci-v2 From 18a8d60bae32a04c957498c496d9843dfc0ffcd0 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Sat, 18 May 2024 15:01:28 +0200 Subject: [PATCH 176/207] Bump AXI for uninitialized simulation memory --- Bender.local | 1 - Bender.lock | 4 ++-- Bender.yml | 2 +- tb/pulp_cluster_tb.sv | 1 + 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Bender.local b/Bender.local index 5c808517..7d3b0a61 100644 --- a/Bender.local +++ b/Bender.local @@ -1,5 +1,4 @@ overrides: - axi : { git: "https://github.com/pulp-platform/axi.git" , version: =0.39.1 } register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic diff --git a/Bender.lock b/Bender.lock index 0014f0c1..439c995d 100644 --- a/Bender.lock +++ b/Bender.lock @@ -7,8 +7,8 @@ packages: dependencies: - common_cells axi: - revision: fccffb5953ec8564218ba05e20adbedec845e014 - version: 0.39.1 + revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6 + version: 0.39.3 source: Git: https://github.com/pulp-platform/axi.git dependencies: diff --git a/Bender.yml b/Bender.yml index d01c8b0e..b9f194b8 100644 --- a/Bender.yml +++ b/Bender.yml @@ -21,7 +21,7 @@ dependencies: idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "229ed4ff412024a8c41cc8817e532f92beeb2c4a" } cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2 - axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta } + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3 } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.35.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 } diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index 4951203d..d73abf77 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -151,6 +151,7 @@ module pulp_cluster_tb; .UserWidth ( AxiUw ), .axi_req_t ( axi_m_req_t ), .axi_rsp_t ( axi_m_resp_t ), + .UninitializedData ( "random" ), .ApplDelay ( SYS_TA ), .AcqDelay ( SYS_TT ) ) sim_mem ( From 4b035381507f566425059b2bca2e62ac75507758 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Sat, 18 May 2024 15:02:35 +0200 Subject: [PATCH 177/207] Bump icache, add control registers, add L1 redundancy --- Bender.local | 1 - Bender.lock | 7 ++-- Bender.yml | 2 +- rtl/cluster_peripherals.sv | 82 ++++++++++++++++++++++++++------------ rtl/pulp_cluster.sv | 27 +++++++------ 5 files changed, 76 insertions(+), 43 deletions(-) diff --git a/Bender.local b/Bender.local index 7d3b0a61..75fd5f90 100644 --- a/Bender.local +++ b/Bender.local @@ -1,4 +1,3 @@ overrides: - register_interface : { git: "https://github.com/pulp-platform/register_interface.git" , rev: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 } # branch: master cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic diff --git a/Bender.lock b/Bender.lock index 439c995d..706d8973 100644 --- a/Bender.lock +++ b/Bender.lock @@ -38,13 +38,14 @@ packages: dependencies: - common_cells cluster_icache: - revision: 229ed4ff412024a8c41cc8817e532f92beeb2c4a + revision: 269f6fd23aeaeb9cd18f16377ca1095688aa337d version: null source: Git: https://github.com/pulp-platform/cluster_icache.git dependencies: - axi - common_cells + - register_interface - scm - tech_cells_generic cluster_interconnect: @@ -200,8 +201,8 @@ packages: - register_interface - tech_cells_generic register_interface: - revision: 19163bb5191d2669a8cbc267cdd4ce8e60f20746 - version: null + revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d + version: 0.4.4 source: Git: https://github.com/pulp-platform/register_interface.git dependencies: diff --git a/Bender.yml b/Bender.yml index b9f194b8..1e5a447d 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,7 +19,7 @@ dependencies: event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master - cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "229ed4ff412024a8c41cc8817e532f92beeb2c4a" } + cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "269f6fd23aeaeb9cd18f16377ca1095688aa337d" } cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2 axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3 } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index c2b32b1b..57ce3d02 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -16,6 +16,7 @@ * Francesco Conti */ +`include "register_interface/typedef.svh" `include "common_cells/registers.svh" module cluster_peripherals @@ -104,9 +105,11 @@ module cluster_peripherals output hci_package::hci_interconnect_ctrl_t hci_ctrl_o, // Control ports - SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_main[NB_CACHE_BANKS-1:0], - PRI_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_pri[NB_CORES-1:0], - output logic [NB_CORES-1:0] enable_l1_l15_prefetch_o + output logic enable_l1_l15_prefetch_o, + output logic [NB_CORES-1:0] flush_valid_o, + input logic [NB_CORES-1:0] flush_ready_i, + input snitch_icache_pkg::icache_l0_events_t [NB_CORES-1:0] l0_events_i, + input snitch_icache_pkg::icache_l1_events_t l1_events_i ); logic s_timer_out_lo_event; @@ -280,29 +283,56 @@ module cluster_peripherals //******************************************************** //******************** icache_ctrl_unit ****************** //******************************************************** - - assign enable_l1_l15_prefetch_o = '1; - assign speriph_slave[SPER_ICACHE_CTRL].gnt = '1; - assign speriph_slave[SPER_ICACHE_CTRL].r_rdata = '0; - assign speriph_slave[SPER_ICACHE_CTRL].r_opc = '0; - - `FF(speriph_slave[SPER_ICACHE_CTRL].r_valid, speriph_slave[SPER_ICACHE_CTRL].req, '0); - `FF(speriph_slave[SPER_ICACHE_CTRL].r_id, speriph_slave[SPER_ICACHE_CTRL].id, '0); - - - // hier_icache_ctrl_unit_wrap #( - // .NB_CACHE_BANKS ( NB_CACHE_BANKS ), - // .NB_CORES ( NB_CORES ), - // .ID_WIDTH ( NB_CORES+NB_MPERIPHS ) - // ) icache_ctrl_unit_i ( - // .clk_i ( clk_i ), - // .rst_ni ( rst_ni ), - - // .speriph_slave ( speriph_slave[SPER_ICACHE_CTRL] ), - // .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), - // .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), - // .enable_l1_l15_prefetch_o ( enable_l1_l15_prefetch_o ) - // ); + + `REG_BUS_TYPEDEF_ALL(icache, logic[31:0], logic[31:0], logic[3:0]) + icache_req_t icache_req; + icache_rsp_t icache_rsp; + + periph_to_reg #( + .AW ( 32 ), + .DW ( 32 ), + .BW ( 8 ), + .IW ( NB_CORES+1 ), + .req_t ( icache_req_t ), + .rsp_t ( icache_rsp_t ) + ) i_icache_bus_converter ( + .clk_i, + .rst_ni, + + .req_i ( speriph_slave[SPER_ICACHE_CTRL].req ), + .add_i ( speriph_slave[SPER_ICACHE_CTRL].add ), + .wen_i ( speriph_slave[SPER_ICACHE_CTRL].wen ), + .wdata_i ( speriph_slave[SPER_ICACHE_CTRL].wdata ), + .be_i ( speriph_slave[SPER_ICACHE_CTRL].be ), + .id_i ( speriph_slave[SPER_ICACHE_CTRL].id ), + .gnt_o ( speriph_slave[SPER_ICACHE_CTRL].gnt ), + .r_rdata_o ( speriph_slave[SPER_ICACHE_CTRL].r_rdata ), + .r_opc_o ( speriph_slave[SPER_ICACHE_CTRL].r_opc ), + .r_id_o ( speriph_slave[SPER_ICACHE_CTRL].r_id ), + .r_valid_o ( speriph_slave[SPER_ICACHE_CTRL].r_valid ), + + .reg_req_o ( icache_req ), + .reg_rsp_i ( icache_rsp ) + ); + + cluster_icache_ctrl_unit #( + .NR_FETCH_PORTS ( NB_CORES ), + .reg_req_t ( icache_req_t ), + .reg_rsp_t ( icache_rsp_t ) + ) i_icache_ctrl_unit ( + .clk_i, + .rst_ni, + + .reg_req_i ( icache_req ), + .reg_rsp_o ( icache_rsp ), + + .enable_prefetching_o ( enable_l1_l15_prefetch_o), + .flush_valid_o, + .flush_ready_i, + + .l0_events_i, + .l1_events_i + ); //******************************************************** //******************** DMA CL CONFIG PORT **************** diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index e7647a0a..d835d19b 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -412,10 +412,10 @@ logic [Cfg.NumCores-1:0][FpuOutFlagsWidth-1:0] s_apu_master_rflags; //----------------------------------------------------------------------// // Interfaces between ICache - L0 - Icache_Interco and Icache_ctrl_unit // // // -SP_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_main[Cfg.iCacheNumBanks](); -PRI_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_pri[Cfg.NumCores](); -logic s_special_core_icache_cfg; -logic[Cfg.NumCores-1:0] s_enable_l1_l15_prefetch; +logic s_enable_l1_l15_prefetch; +logic [Cfg.NumCores-1:0] s_icache_flush_valid, s_icache_flush_ready; +snitch_icache_pkg::icache_l0_events_t [Cfg.NumCores-1:0] s_icache_l0_events; +snitch_icache_pkg::icache_l1_events_t s_icache_l1_events; //----------------------------------------------------------------------// localparam TCDM_ID_WIDTH = Cfg.NumCores + Cfg.DmaNumPlugs + 4 + Cfg.HwpeNumPorts; @@ -826,9 +826,11 @@ cluster_peripherals #( .hwpe_en_o ( s_hwpe_en ), .hwpe_sel_o ( s_hwpe_sel ), .hci_ctrl_o ( s_hci_ctrl ), - .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), - .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), - .enable_l1_l15_prefetch_o ( s_enable_l1_l15_prefetch ) + .enable_l1_l15_prefetch_o ( s_enable_l1_l15_prefetch ), + .flush_valid_o ( s_icache_flush_valid ), + .flush_ready_i ( s_icache_flush_ready ), + .l0_events_i ( s_icache_l0_events ), + .l1_events_i ( s_icache_l1_events ) ); //******************************************************** @@ -1247,6 +1249,7 @@ pulp_icache_wrap #( .LINE_WIDTH ( 256 ), // Ideally 32*NumCores .LINE_COUNT ( Cfg.iCacheSharedSize*8/256/Cfg.iCacheNumWays ), .SET_COUNT ( Cfg.iCacheNumWays ), + .L1DataParityWidth ( 8 ), .FetchAddrWidth ( AddrWidth ), .FetchDataWidth ( Cfg.iCachePrivateDataWidth ), .AxiAddrWidth ( AddrWidth ), @@ -1264,11 +1267,11 @@ pulp_icache_wrap #( .fetch_rdata_o ( instr_r_rdata ), .fetch_rerror_o (), - .enable_prefetching_i ( s_enable_l1_l15_prefetch[0] ), - .icache_l0_events_o (), - .icache_l1_events_o (), - .flush_valid_i ('0), - .flush_ready_o (), + .enable_prefetching_i ( s_enable_l1_l15_prefetch ), + .icache_l0_events_o ( s_icache_l0_events ), + .icache_l1_events_o ( s_icache_l1_events ), + .flush_valid_i ( s_icache_flush_valid ), + .flush_ready_o ( s_icache_flush_ready ), .sram_cfg_data_i ('0), .sram_cfg_tag_i ('0), From 155ac11a39dfcfe133e050716e269668e99420cb Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 30 Apr 2024 17:46:08 +0200 Subject: [PATCH 178/207] Update hci interconnect --- Bender.local | 1 - Bender.lock | 2 +- Bender.yml | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/Bender.local b/Bender.local index 75fd5f90..13c00451 100644 --- a/Bender.local +++ b/Bender.local @@ -1,3 +1,2 @@ overrides: - cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix cv32e40p : { git: "https://github.com/pulp-platform/cv32e40p.git" , rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # branch: michaero/safety-island-clic diff --git a/Bender.lock b/Bender.lock index 706d8973..6e6e3629 100644 --- a/Bender.lock +++ b/Bender.lock @@ -49,7 +49,7 @@ packages: - scm - tech_cells_generic cluster_interconnect: - revision: 89e1019d64a86425211be6200770576cbdf3e8b3 + revision: 1284def6c0b7f7e9355eb093d00883ad9dead1b7 version: null source: Git: https://github.com/pulp-platform/cluster_interconnect.git diff --git a/Bender.yml b/Bender.yml index 1e5a447d..d2004b7e 100644 --- a/Bender.yml +++ b/Bender.yml @@ -15,7 +15,7 @@ dependencies: axi2mem: { git: "https://github.com/pulp-platform/axi2mem.git", rev: "b0e963433b2f6a61262b1448031e74eaec57c203" } # branch: yt/astral axi2per: { git: "https://github.com/pulp-platform/axi2per.git", rev: "4932bd2b88a1c7b5f0bf95411fc512905ed32439" } # branch: yt/astral per2axi: { git: "https://github.com/pulp-platform/per2axi.git", rev: "95bf23119b47fc171d9ed3734c431f71cffd9350" } # branch: yt/astral - cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 89e1019d64a86425211be6200770576cbdf3e8b3 } # branch: assertion-fix + cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", rev: 1284def6c0b7f7e9355eb093d00883ad9dead1b7 } # branch: michaero/hci-fix event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master From 7e6febca28c7c7b2090dabbf29a9b48319230ecd Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Fri, 10 May 2024 18:03:01 +0200 Subject: [PATCH 179/207] Move L0 I$ statistics to performance counters --- Bender.lock | 2 +- Bender.yml | 2 +- rtl/cluster_peripherals.sv | 6 +++--- rtl/core_region.sv | 6 +++--- rtl/pulp_cluster.sv | 6 +++--- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/Bender.lock b/Bender.lock index 6e6e3629..fa418e05 100644 --- a/Bender.lock +++ b/Bender.lock @@ -38,7 +38,7 @@ packages: dependencies: - common_cells cluster_icache: - revision: 269f6fd23aeaeb9cd18f16377ca1095688aa337d + revision: b3b0c474eb5baa2fdeece65369805206398ab63b version: null source: Git: https://github.com/pulp-platform/cluster_icache.git diff --git a/Bender.yml b/Bender.yml index d2004b7e..551e38c5 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,7 +19,7 @@ dependencies: event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master - cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "269f6fd23aeaeb9cd18f16377ca1095688aa337d" } + cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "b3b0c474eb5baa2fdeece65369805206398ab63b" } cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2 axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3 } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index 57ce3d02..39912cce 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -108,7 +108,7 @@ module cluster_peripherals output logic enable_l1_l15_prefetch_o, output logic [NB_CORES-1:0] flush_valid_o, input logic [NB_CORES-1:0] flush_ready_i, - input snitch_icache_pkg::icache_l0_events_t [NB_CORES-1:0] l0_events_i, + // input snitch_icache_pkg::icache_l0_events_t [NB_CORES-1:0] l0_events_i, input snitch_icache_pkg::icache_l1_events_t l1_events_i ); @@ -315,7 +315,7 @@ module cluster_peripherals .reg_rsp_i ( icache_rsp ) ); - cluster_icache_ctrl_unit #( + cluster_icache_ctrl_perfctr_unit #( .NR_FETCH_PORTS ( NB_CORES ), .reg_req_t ( icache_req_t ), .reg_rsp_t ( icache_rsp_t ) @@ -330,7 +330,7 @@ module cluster_peripherals .flush_valid_o, .flush_ready_i, - .l0_events_i, + // .l0_events_i, .l1_events_i ); diff --git a/rtl/core_region.sv b/rtl/core_region.sv index 057c5ad8..87d6669c 100644 --- a/rtl/core_region.sv +++ b/rtl/core_region.sv @@ -114,7 +114,7 @@ import rapid_recovery_pkg::*; input logic [APU_NUSFLAGS_CPU-1:0] apu_master_flags_i ); - localparam N_EXT_PERF_COUNTERS_ACTUAL = 5; + // localparam N_EXT_PERF_COUNTERS_ACTUAL = 5; localparam USE_IBEX = CORE_TYPE_CL == 1 || CORE_TYPE_CL == 2; localparam IBEX_RV32M = CORE_TYPE_CL == 1 ? ibex_pkg::RV32MSingleCycle : ibex_pkg::RV32MNone; localparam IBEX_RV32E = CORE_TYPE_CL == 2; @@ -237,7 +237,7 @@ import rapid_recovery_pkg::*; .INSTR_RDATA_WIDTH ( INSTR_RDATA_WIDTH ), .PULP_CLUSTER ( 1 ), .FPU ( FPU ), - .N_EXT_PERF_COUNTERS ( N_EXT_PERF_COUNTERS_ACTUAL ), + .N_EXT_PERF_COUNTERS ( N_EXT_PERF_COUNTERS ), .Zfinx ( FPU ), .WAPUTYPE ( WAPUTYPE ), .DM_HaltAddress ( DEBUG_START_ADDR + 16'h0800 ) @@ -455,7 +455,7 @@ import rapid_recovery_pkg::*; .irq_x_ack_o ( irq_ack_o ), .irq_x_ack_id_o ( irq_ack_id_o ), - .external_perf_i ( {{{16- N_EXT_PERF_COUNTERS_ACTUAL}{'0}}, perf_counters} ), + .external_perf_i ( {{{16- N_EXT_PERF_COUNTERS}{'0}}, ext_perf_i} ), .debug_req_i ( debug_req_i ), diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index d835d19b..4852db9a 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -829,7 +829,7 @@ cluster_peripherals #( .enable_l1_l15_prefetch_o ( s_enable_l1_l15_prefetch ), .flush_valid_o ( s_icache_flush_valid ), .flush_ready_i ( s_icache_flush_ready ), - .l0_events_i ( s_icache_l0_events ), + // .l0_events_i ( s_icache_l0_events ), .l1_events_i ( s_icache_l1_events ) ); @@ -905,7 +905,7 @@ generate core_region #( .CORE_TYPE_CL ( Cfg.CoreType ), - .N_EXT_PERF_COUNTERS ( 5 ), + .N_EXT_PERF_COUNTERS ( 5 + $bits(snitch_icache_pkg::icache_l0_events_t ) ), .ADDR_WIDTH ( AddrWidth ), .DATA_WIDTH ( DataWidth ), .INSTR_RDATA_WIDTH ( Cfg.iCachePrivateDataWidth ), @@ -950,7 +950,7 @@ generate .debug_halted_o ( core2hmr[i].debug_halted ), .debug_havereset_o ( dbg_core_havereset[i] ), .debug_running_o ( dbg_core_running[i] ), - .ext_perf_i ( ext_perf[i] ), + .ext_perf_i ( {s_icache_l0_events[i], ext_perf[i]} ), .core_data_req_o ( core_data_req[i] ), .core_data_rsp_i ( core_data_rsp[i] ), //HMR Recovery Bus From 25cd063691a9279c647f3bc4a4f9ab86171ec599 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Sat, 18 May 2024 15:22:22 +0200 Subject: [PATCH 180/207] Fix for rebase --- Bender.lock | 2 +- Bender.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index fa418e05..44a24e60 100644 --- a/Bender.lock +++ b/Bender.lock @@ -108,7 +108,7 @@ packages: dependencies: - common_cells hci: - revision: d31af36ebcaf2196fb51676b40782aa8cbd9cc69 + revision: 4ea0f83a0657fa24514b7fc8981cfb4acf2ccb3b version: null source: Git: https://github.com/pulp-platform/hci.git diff --git a/Bender.yml b/Bender.yml index 551e38c5..a00a9396 100644 --- a/Bender.yml +++ b/Bender.yml @@ -29,7 +29,7 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: d31af36ebcaf2196fb51676b40782aa8cbd9cc69 } # branch: remove-automatic-parameter-prop + hci: { git: "https://github.com/pulp-platform/hci.git", rev: 4ea0f83a0657fa24514b7fc8981cfb4acf2ccb3b } # branch: fix on top of remove-automatic-parameter-prop register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 } # branch: fc/hci-v2.1 From 9eea76e1eeed95b7a7a5f751dc2eaf6b5756f05f Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 31 May 2024 16:33:07 +0200 Subject: [PATCH 181/207] Update NEureka. --- Bender.lock | 4 ++-- Bender.yml | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Bender.lock b/Bender.lock index 44a24e60..332645bf 100644 --- a/Bender.lock +++ b/Bender.lock @@ -161,8 +161,8 @@ packages: dependencies: - common_cells neureka: - revision: 6221fd4d17809166333ace71aec37b58ac28ce72 - version: null + revision: b6141132d915b3fa5c1db712b730ac463a949a34 + version: 1.0.0 source: Git: https://github.com/pulp-platform/neureka.git dependencies: diff --git a/Bender.yml b/Bender.yml index a00a9396..41da2384 100644 --- a/Bender.yml +++ b/Bender.yml @@ -33,7 +33,7 @@ dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 } # branch: fc/hci-v2.1 - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 6221fd4d17809166333ace71aec37b58ac28ce72 } # branch: hci-v2 + neureka: { git: "https://github.com/pulp-platform/neureka.git", version: 1.0.0 } export_include_dirs: - include From c0b47736369229679fe9283c15c059e6a5d4a3bc Mon Sep 17 00:00:00 2001 From: Andrea Belano Date: Fri, 10 May 2024 10:02:25 +0200 Subject: [PATCH 182/207] Fixed sysnthesis error --- rtl/hwpe_subsystem.sv | 5 +++-- rtl/pulp_cluster.sv | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index 244207b1..7f952dc1 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -60,8 +60,9 @@ module hwpe_subsystem ) periph [N_HWPES-1:0] (.clk(clk)); hci_core_intf #( - .DW ( DW ), - .AW ( AW ) + .DW ( DW ), + .AW ( AW ), + .EHW ( 0 ) ) tcdm [0:N_HWPES-1] (.clk(clk)); for (genvar i = 0; i < N_HWPES; i++) begin : gen_hwpe diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 4852db9a..d9aff6bd 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -354,8 +354,9 @@ XBAR_TCDM_BUS s_mperiph_bus(); // cores & accelerators -> log interconnect hci_core_intf #( - .DW ( Cfg.HwpeNumPorts * DataWidth ), - .AW ( AddrWidth ) + .DW ( Cfg.HwpeNumPorts * DataWidth ), + .AW ( AddrWidth ), + .EHW ( 0 ) ) s_hci_hwpe [0:0] ( .clk ( clk_i ) ); From d8a23513156e17578a04ee73e5a29ca8b6835332 Mon Sep 17 00:00:00 2001 From: Andrea Belano Date: Fri, 31 May 2024 16:22:10 +0200 Subject: [PATCH 183/207] Updated Bender.lock --- Bender.lock | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/Bender.lock b/Bender.lock index 332645bf..453cc530 100644 --- a/Bender.lock +++ b/Bender.lock @@ -63,8 +63,8 @@ packages: dependencies: - hci common_cells: - revision: 0d67563b6b592549542544f1abc0f43e5d4ee8b4 - version: 1.35.0 + revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f + version: 1.32.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -178,7 +178,7 @@ packages: dependencies: - axi_slice redmule: - revision: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 + revision: 7abb25690090c7f5548a8aa905c7bf0440d4ba6b version: null source: Git: https://github.com/pulp-platform/redmule.git @@ -225,6 +225,18 @@ packages: Git: https://github.com/pulp-platform/scm.git dependencies: - tech_cells_generic + softex: + revision: 0fe8b1349ce6f4f05aa63ce65961a87b9c133ae5 + version: null + source: + Git: https://github.com/belanoa/softex.git + dependencies: + - common_cells + - fpnew + - hci + - hwpe-ctrl + - hwpe-stream + - ibex tech_cells_generic: revision: a9cae21902e75b1434328ecf36f85327ba5717de version: 0.2.11 @@ -242,5 +254,5 @@ packages: revision: cc4068a0ccb7691cd062b809c34b2304e7fbfa36 version: null source: - Git: https://github.com/yvantor/ibex.git + Git: git@github.com:yvantor/ibex.git dependencies: [] From 3122cb39fc628afad14b615a5dee98434325a5db Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 31 May 2024 17:10:13 +0200 Subject: [PATCH 184/207] Fix zeroriscy dependency.. --- Bender.lock | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) diff --git a/Bender.lock b/Bender.lock index 453cc530..332645bf 100644 --- a/Bender.lock +++ b/Bender.lock @@ -63,8 +63,8 @@ packages: dependencies: - hci common_cells: - revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f - version: 1.32.0 + revision: 0d67563b6b592549542544f1abc0f43e5d4ee8b4 + version: 1.35.0 source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -178,7 +178,7 @@ packages: dependencies: - axi_slice redmule: - revision: 7abb25690090c7f5548a8aa905c7bf0440d4ba6b + revision: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 version: null source: Git: https://github.com/pulp-platform/redmule.git @@ -225,18 +225,6 @@ packages: Git: https://github.com/pulp-platform/scm.git dependencies: - tech_cells_generic - softex: - revision: 0fe8b1349ce6f4f05aa63ce65961a87b9c133ae5 - version: null - source: - Git: https://github.com/belanoa/softex.git - dependencies: - - common_cells - - fpnew - - hci - - hwpe-ctrl - - hwpe-stream - - ibex tech_cells_generic: revision: a9cae21902e75b1434328ecf36f85327ba5717de version: 0.2.11 @@ -254,5 +242,5 @@ packages: revision: cc4068a0ccb7691cd062b809c34b2304e7fbfa36 version: null source: - Git: git@github.com:yvantor/ibex.git + Git: https://github.com/yvantor/ibex.git dependencies: [] From 8689e429d97a399bd699d544fde08a55ca843952 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Fri, 31 May 2024 18:01:12 +0200 Subject: [PATCH 185/207] Fix parameter errors. --- rtl/hwpe_subsystem.sv | 3 ++- rtl/pulp_cluster.sv | 22 +++++++++++----------- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index 7f952dc1..aad613d6 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -42,6 +42,7 @@ module hwpe_subsystem localparam int unsigned DW = HCI_HWPE_SIZE.DW; localparam int unsigned AW = HCI_HWPE_SIZE.AW; + localparam int unsigned EHW = HCI_HWPE_SIZE.EHW; localparam int unsigned N_HWPES = HWPE_CFG.NumHwpes; @@ -62,7 +63,7 @@ module hwpe_subsystem hci_core_intf #( .DW ( DW ), .AW ( AW ), - .EHW ( 0 ) + .EHW ( EHW ) ) tcdm [0:N_HWPES-1] (.clk(clk)); for (genvar i = 0; i < N_HWPES; i++) begin : gen_hwpe diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index d9aff6bd..b87b87fd 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -325,8 +325,8 @@ localparam hci_package::hci_size_parameter_t HciHwpeSizeParam = '{ /* logarithmic and peripheral interconnect interfaces */ // ext -> log interconnect hci_core_intf #( - .DW ( DataWidth ), - .AW ( AddrWidth ) + .DW ( HciCoreSizeParam.DW ), + .AW ( HciCoreSizeParam.AW ) ) s_hci_ext[0:Cfg.DmaNumPlugs-1] ( .clk ( clk_i ) ); @@ -339,8 +339,8 @@ XBAR_PERIPH_BUS s_hwpe_cfg_bus(); // DMA -> log interconnect hci_core_intf #( - .DW ( DataWidth ), - .AW ( AddrWidth ) + .DW ( HciCoreSizeParam.DW ), + .AW ( HciCoreSizeParam.AW ) ) s_hci_dma[0:Cfg.DmaNumPlugs-1] ( .clk ( clk_i ) ); @@ -354,15 +354,15 @@ XBAR_TCDM_BUS s_mperiph_bus(); // cores & accelerators -> log interconnect hci_core_intf #( - .DW ( Cfg.HwpeNumPorts * DataWidth ), - .AW ( AddrWidth ), - .EHW ( 0 ) + .DW ( HciHwpeSizeParam.DW ), + .AW ( HciHwpeSizeParam.AW ), + .EHW ( HciHwpeSizeParam.EHW ) ) s_hci_hwpe [0:0] ( .clk ( clk_i ) ); hci_core_intf #( - .DW ( DataWidth ), - .AW ( AddrWidth ) + .DW ( HciCoreSizeParam.DW ), + .AW ( HciCoreSizeParam.AW ) ) s_hci_core [0:Cfg.NumCores-1] ( .clk ( clk_i ) ); @@ -386,8 +386,8 @@ XBAR_TCDM_BUS s_debug_bus[Cfg.NumCores-1:0](); // cores -> DMA ctrl // FIXME: iDMA hci_core_intf #( - .DW ( DataWidth ), - .AW ( AddrWidth ) + .DW ( HciCoreSizeParam.DW ), + .AW ( HciCoreSizeParam.AW ) ) s_core_dmactrl_bus [0:Cfg.NumCores-1] ( .clk ( clk_i ) ); From 76d1a6d106664eb8b43ac0e7d4a7ff2bf0b40e17 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella <48508508+yvantor@users.noreply.github.com> Date: Sun, 2 Jun 2024 23:33:35 +0200 Subject: [PATCH 186/207] Integrate SoftEx HWPE. (#75) * Integrate SoftEx to v1.0.0. * Bump HCI. --------- Co-authored-by: Andrea Belano Co-authored-by: Yvan Tortorella --- Bender.lock | 14 +++++++++++++- Bender.yml | 5 +++-- Makefile | 2 +- packages/pulp_cluster_package.sv | 3 ++- regression-tests | 2 +- rtl/hwpe_subsystem.sv | 18 ++++++++++++++++++ tb/pulp_cluster_tb.sv | 2 +- 7 files changed, 39 insertions(+), 7 deletions(-) diff --git a/Bender.lock b/Bender.lock index 332645bf..28879c3f 100644 --- a/Bender.lock +++ b/Bender.lock @@ -108,7 +108,7 @@ packages: dependencies: - common_cells hci: - revision: 4ea0f83a0657fa24514b7fc8981cfb4acf2ccb3b + revision: afe0220f9a2f132dc8655c48da05aae5121a570b version: null source: Git: https://github.com/pulp-platform/hci.git @@ -225,6 +225,18 @@ packages: Git: https://github.com/pulp-platform/scm.git dependencies: - tech_cells_generic + softex: + revision: 23faeccaf204817bc9e6649e469072e5726be561 + version: 1.0.0 + source: + Git: https://github.com/belanoa/softex.git + dependencies: + - common_cells + - fpnew + - hci + - hwpe-ctrl + - hwpe-stream + - ibex tech_cells_generic: revision: a9cae21902e75b1434328ecf36f85327ba5717de version: 0.2.11 diff --git a/Bender.yml b/Bender.yml index 41da2384..2f3bd5ad 100644 --- a/Bender.yml +++ b/Bender.yml @@ -29,11 +29,12 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: 4ea0f83a0657fa24514b7fc8981cfb4acf2ccb3b } # branch: fix on top of remove-automatic-parameter-prop - register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } # branch: master + hci: { git: "https://github.com/pulp-platform/hci.git", rev: afe0220 } # branch: master + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 } # branch: fc/hci-v2.1 neureka: { git: "https://github.com/pulp-platform/neureka.git", version: 1.0.0 } + softex: { git: "https://github.com/belanoa/softex.git" , version: 1.0.0 } export_include_dirs: - include diff --git a/Makefile b/Makefile index 12893585..0764afd2 100644 --- a/Makefile +++ b/Makefile @@ -113,7 +113,7 @@ sim_clean: scripts/compile.tcl: | Bender.lock $(call generate_vsim, $@, $(bender_defs) $(bender_targs),..) echo 'vlog "$(realpath $(ROOT_DIR))/tb/dpi/elfloader.cpp" -ccflags "-std=c++11"' >> $@ - echo 'vopt +permissive -suppress 3053 -suppress 8885 +UVM_NO_RELNOTES $(top_level) -o $(top_level)_optimized' + echo 'vopt +permissive -suppress 3053 -suppress 8885 +UVM_NO_RELNOTES $(top_level) -o $(top_level)_optimized' >> $@ $(library): $(QUESTA) vlib $(library) diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index d5f39097..2553d549 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -33,7 +33,8 @@ package pulp_cluster_package; // HWPE type typedef enum byte_t { REDMULE, - NEUREKA + NEUREKA, + SOFTEX } hwpe_type_e; parameter MAX_NUM_HWPES = 8; diff --git a/regression-tests b/regression-tests index 9fe04d0d..979c0b22 160000 --- a/regression-tests +++ b/regression-tests @@ -1 +1 @@ -Subproject commit 9fe04d0d984a01cf0dcccc248483bb2b152912fe +Subproject commit 979c0b221ea6b65eb6fc67d515f98a593efb3975 diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index aad613d6..6fb56e9a 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -126,6 +126,24 @@ module hwpe_subsystem .periph ( periph[i] ) ); + end else if (HWPE_CFG.HwpeList[i] == SOFTEX) begin : gen_softex + + //////////// + // SOFTEX // + //////////// + + softex_top #( + .N_CORES ( N_CORES ), + .`HCI_SIZE_PARAM(Tcdm) ( HCI_HWPE_SIZE ) + ) i_softex ( + .clk_i ( hwpe_clk[i] ), + .rst_ni ( rst_n ), + .busy_o ( busy[i] ), + .evt_o ( evt[i] ), + .tcdm ( tcdm[i] ), + .periph ( periph[i] ) + ); + end end diff --git a/tb/pulp_cluster_tb.sv b/tb/pulp_cluster_tb.sv index d73abf77..4b7976c6 100644 --- a/tb/pulp_cluster_tb.sv +++ b/tb/pulp_cluster_tb.sv @@ -290,7 +290,7 @@ module pulp_cluster_tb; TcdmSize: 128*1024, TcdmNumBank: 16, HwpePresent: 1, - HwpeCfg: '{NumHwpes: 2, HwpeList: {NEUREKA, REDMULE}}, + HwpeCfg: '{NumHwpes: 3, HwpeList: {SOFTEX, NEUREKA, REDMULE}}, HwpeNumPorts: 9, iCacheNumBanks: 2, iCacheNumLines: 1, From 41ba385cd8c1fd7bef151c3bafc0bdb3f67f3c64 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 9 Jun 2024 12:52:27 +0200 Subject: [PATCH 187/207] Bump redundancy cells updating SRAMs and HMR unit. --- Bender.lock | 6 +++--- Bender.yml | 2 +- rtl/pulp_cluster.sv | 4 +++- rtl/tcdm_banks_wrap.sv | 26 ++++++++++---------------- 4 files changed, 17 insertions(+), 21 deletions(-) diff --git a/Bender.lock b/Bender.lock index 28879c3f..4490f535 100644 --- a/Bender.lock +++ b/Bender.lock @@ -191,7 +191,7 @@ packages: - hwpe-stream - tech_cells_generic redundancy_cells: - revision: c37bdb47339bf70e8323de8df14ea8bbeafb6583 + revision: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc version: null source: Git: https://github.com/pulp-platform/redundancy_cells.git @@ -238,8 +238,8 @@ packages: - hwpe-stream - ibex tech_cells_generic: - revision: a9cae21902e75b1434328ecf36f85327ba5717de - version: 0.2.11 + revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf + version: 0.2.13 source: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: diff --git a/Bender.yml b/Bender.yml index 2f3bd5ad..a800a8de 100644 --- a/Bender.yml +++ b/Bender.yml @@ -31,7 +31,7 @@ dependencies: scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating hci: { git: "https://github.com/pulp-platform/hci.git", rev: afe0220 } # branch: master register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } - redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc } # branch: astral-v0 redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 } # branch: fc/hci-v2.1 neureka: { git: "https://github.com/pulp-platform/neureka.git", version: 1.0.0 } softex: { git: "https://github.com/belanoa/softex.git" , version: 1.0.0 } diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index b87b87fd..3b0f56a1 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -1078,6 +1078,7 @@ hmr_unit #( .InterleaveGrps ( 1 ), .RapidRecovery ( 1 ), .SeparateData ( 1 ), + .SeparateAxiBus ( 0 ), .NumBusVoters ( 1 ), .all_inputs_t ( core_inputs_t ), .nominal_outputs_t ( core_outputs_t ), @@ -1114,7 +1115,8 @@ hmr_unit #( .core_setback_o ( setback ), .core_inputs_o ( hmr2core ), .core_nominal_outputs_i ( core2hmr ), - .core_bus_outputs_i ( '0 ) + .core_bus_outputs_i ( '0 ), + .core_axi_outputs_i ( '0 ) ); //**************************************************** diff --git a/rtl/tcdm_banks_wrap.sv b/rtl/tcdm_banks_wrap.sv index e3f2fba5..4bfe6541 100644 --- a/rtl/tcdm_banks_wrap.sv +++ b/rtl/tcdm_banks_wrap.sv @@ -71,35 +71,29 @@ for(genvar i=0; i Date: Sun, 9 Jun 2024 15:08:58 +0200 Subject: [PATCH 188/207] Bump cluster iCache to fix missing reset connection. --- Bender.lock | 9 ++++----- Bender.yml | 2 +- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/Bender.lock b/Bender.lock index 4490f535..475c2f12 100644 --- a/Bender.lock +++ b/Bender.lock @@ -38,7 +38,7 @@ packages: dependencies: - common_cells cluster_icache: - revision: b3b0c474eb5baa2fdeece65369805206398ab63b + revision: 4cffcf37724704ab27d483338804a1981f5c4497 version: null source: Git: https://github.com/pulp-platform/cluster_icache.git @@ -219,12 +219,11 @@ packages: - fpnew - tech_cells_generic scm: - revision: 74426dee36f28ae1c02f7635cf844a0156145320 - version: null + revision: 998466d2a3c2d7d572e43d2666d93c4f767d8d60 + version: 1.1.1 source: Git: https://github.com/pulp-platform/scm.git - dependencies: - - tech_cells_generic + dependencies: [] softex: revision: 23faeccaf204817bc9e6649e469072e5726be561 version: 1.0.0 diff --git a/Bender.yml b/Bender.yml index a800a8de..976d8cca 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,7 +19,7 @@ dependencies: event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master - cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "b3b0c474eb5baa2fdeece65369805206398ab63b" } + cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "4cffcf37724704ab27d483338804a1981f5c4497" } # branch: astral-synth cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2 axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3 } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } From 320d8cb2ead8943ba91e06b9a6b749e19e450d3f Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 9 Jun 2024 17:22:29 +0200 Subject: [PATCH 189/207] Reintroduce hierarchical cache selectable with Bender define. --- Bender.lock | 18 +++ Bender.yml | 1 + rtl/cluster_peripherals.sv | 49 +++++++- rtl/pulp_cluster.sv | 229 +++++++++++++++++++++++++++++-------- 4 files changed, 248 insertions(+), 49 deletions(-) diff --git a/Bender.lock b/Bender.lock index 475c2f12..bb0ff630 100644 --- a/Bender.lock +++ b/Bender.lock @@ -116,6 +116,18 @@ packages: - cluster_interconnect - hwpe-stream - l2_tcdm_hybrid_interco + hier-icache: + revision: 2886cb2a46cea3e2bd2d979b505d88fadfbe150c + version: null + source: + Git: https://github.com/pulp-platform/hier-icache.git + dependencies: + - axi + - axi_slice + - common_cells + - icache-intc + - scm + - tech_cells_generic hwpe-ctrl: revision: a5966201aeeb988d607accdc55da933a53c6a56e version: null @@ -137,6 +149,12 @@ packages: Git: https://github.com/pulp-platform/ibex.git dependencies: - tech_cells_generic + icache-intc: + revision: 663c3b6d3c2bf63ff25cda46f33c799c647b3985 + version: 1.0.1 + source: + Git: https://github.com/pulp-platform/icache-intc.git + dependencies: [] idma: revision: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 version: null diff --git a/Bender.yml b/Bender.yml index 976d8cca..f1141f94 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,6 +20,7 @@ dependencies: mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "4cffcf37724704ab27d483338804a1981f5c4497" } # branch: astral-synth + hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "2886cb2a46cea3e2bd2d979b505d88fadfbe150c" } # branch: astral cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2 axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3 } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index 39912cce..d3645714 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -105,7 +105,9 @@ module cluster_peripherals output hci_package::hci_interconnect_ctrl_t hci_ctrl_o, // Control ports - output logic enable_l1_l15_prefetch_o, + SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_main[NB_CACHE_BANKS-1:0], + PRI_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_pri[NB_CORES-1:0], + output logic [NB_CORES-1:0] enable_l1_l15_prefetch_o, output logic [NB_CORES-1:0] flush_valid_o, input logic [NB_CORES-1:0] flush_ready_i, // input snitch_icache_pkg::icache_l0_events_t [NB_CORES-1:0] l0_events_i, @@ -284,6 +286,7 @@ module cluster_peripherals //******************** icache_ctrl_unit ****************** //******************************************************** +`ifdef SNITCH_ICACHE `REG_BUS_TYPEDEF_ALL(icache, logic[31:0], logic[31:0], logic[3:0]) icache_req_t icache_req; icache_rsp_t icache_rsp; @@ -326,7 +329,7 @@ module cluster_peripherals .reg_req_i ( icache_req ), .reg_rsp_o ( icache_rsp ), - .enable_prefetching_o ( enable_l1_l15_prefetch_o), + .enable_prefetching_o ( enable_l1_l15_prefetch_o[0]), .flush_valid_o, .flush_ready_i, @@ -334,6 +337,48 @@ module cluster_peripherals .l1_events_i ); + assign enable_l1_l15_prefetch_o[NB_CORES:1] = '0; + + for (genvar i = 0; i < NB_CORES; i++) begin + assign IC_ctrl_unit_bus_pri[i].bypass_req = '0; + assign IC_ctrl_unit_bus_pri[i].flush_req = '0; + assign IC_ctrl_unit_bus_pri[i].sel_flush_req = '0; + assign IC_ctrl_unit_bus_pri[i].sel_flush_addr = '0; + `ifdef FEATURE_ICACHE_STAT + assign IC_ctrl_unit_bus_pri[i].ctrl_clear_regs = '0; + assign IC_ctrl_unit_bus_pri[i].ctrl_enable_regs = '0; + `endif + end + + for (genvar i = 0; i < NB_CACHE_BANKS; i++) begin + assign IC_ctrl_unit_bus_main[i].ctrl_req_enable = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_req_disable = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_flush_req = '0; + assign IC_ctrl_unit_bus_main[i].icache_is_private = '0; + assign IC_ctrl_unit_bus_main[i].sel_flush_req = '0; + assign IC_ctrl_unit_bus_main[i].sel_flush_addr = '0; + `ifdef FEATURE_ICACHE_STAT + assign IC_ctrl_unit_bus_main[i].ctrl_clear_regs = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_enable_regs = '0; + `endif + end +`else + assign flush_valid_o = '0; + hier_icache_ctrl_unit_wrap #( + .NB_CACHE_BANKS ( NB_CACHE_BANKS ), + .NB_CORES ( NB_CORES ), + .ID_WIDTH ( NB_CORES+NB_MPERIPHS ) + ) icache_ctrl_unit_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .speriph_slave ( speriph_slave[SPER_ICACHE_CTRL] ), + .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), + .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), + .enable_l1_l15_prefetch_o ( enable_l1_l15_prefetch_o ) + ); +`endif + //******************************************************** //******************** DMA CL CONFIG PORT **************** //******************************************************** diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 3b0f56a1..a4220904 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -413,7 +413,9 @@ logic [Cfg.NumCores-1:0][FpuOutFlagsWidth-1:0] s_apu_master_rflags; //----------------------------------------------------------------------// // Interfaces between ICache - L0 - Icache_Interco and Icache_ctrl_unit // // // -logic s_enable_l1_l15_prefetch; +SP_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_main[Cfg.iCacheNumBanks](); +PRI_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_pri[Cfg.NumCores]();; +logic [Cfg.NumCores-1:0] s_enable_l1_l15_prefetch; logic [Cfg.NumCores-1:0] s_icache_flush_valid, s_icache_flush_ready; snitch_icache_pkg::icache_l0_events_t [Cfg.NumCores-1:0] s_icache_l0_events; snitch_icache_pkg::icache_l1_events_t s_icache_l1_events; @@ -478,16 +480,6 @@ AXI_BUS #( `AXI_TYPEDEF_ALL(instr_axi, logic[AddrWidth-1:0], logic[AxiIdInWidth-1:0], logic[Cfg.AxiDataOutWidth-1:0], logic[Cfg.AxiDataOutWidth/8-1:0], logic[Cfg.AxiUserWidth-1:0]) -instr_axi_req_t s_core_instr_bus_req; -instr_axi_resp_t s_core_instr_bus_resp; - -always_comb begin - s_core_instr_bus.aw_addr = '0; - s_core_instr_bus.ar_addr = '0; - `AXI_SET_FROM_REQ(s_core_instr_bus, s_core_instr_bus_req) -end -`AXI_ASSIGN_TO_RESP(s_core_instr_bus_resp, s_core_instr_bus) - // ***********************************************************************************************+ // ***********************************************************************************************+ // ***********************************************************************************************+ @@ -830,6 +822,8 @@ cluster_peripherals #( .enable_l1_l15_prefetch_o ( s_enable_l1_l15_prefetch ), .flush_valid_o ( s_icache_flush_valid ), .flush_ready_i ( s_icache_flush_ready ), + .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), + .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), // .l0_events_i ( s_icache_l0_events ), .l1_events_i ( s_icache_l1_events ) ); @@ -1246,42 +1240,183 @@ generate end endgenerate -pulp_icache_wrap #( - .NumFetchPorts ( Cfg.NumCores ), - .L0_LINE_COUNT ( Cfg.iCachePrivateSize*8/256 ), - .LINE_WIDTH ( 256 ), // Ideally 32*NumCores - .LINE_COUNT ( Cfg.iCacheSharedSize*8/256/Cfg.iCacheNumWays ), - .SET_COUNT ( Cfg.iCacheNumWays ), - .L1DataParityWidth ( 8 ), - .FetchAddrWidth ( AddrWidth ), - .FetchDataWidth ( Cfg.iCachePrivateDataWidth ), - .AxiAddrWidth ( AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataOutWidth ), - .axi_req_t ( instr_axi_req_t ), - .axi_rsp_t ( instr_axi_resp_t ) -) icache_top_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .fetch_req_i ( instr_req ), - .fetch_addr_i ( instr_addr ), - .fetch_gnt_o ( instr_gnt ), - .fetch_rvalid_o ( instr_r_valid ), - .fetch_rdata_o ( instr_r_rdata ), - .fetch_rerror_o (), - - .enable_prefetching_i ( s_enable_l1_l15_prefetch ), - .icache_l0_events_o ( s_icache_l0_events ), - .icache_l1_events_o ( s_icache_l1_events ), - .flush_valid_i ( s_icache_flush_valid ), - .flush_ready_o ( s_icache_flush_ready ), - - .sram_cfg_data_i ('0), - .sram_cfg_tag_i ('0), - - .axi_req_o ( s_core_instr_bus_req ), - .axi_rsp_i ( s_core_instr_bus_resp ) -); +`ifdef SNITCH_ICACHE + instr_axi_req_t s_core_instr_bus_req; + instr_axi_resp_t s_core_instr_bus_resp; + + always_comb begin + s_core_instr_bus.aw_addr = '0; + s_core_instr_bus.ar_addr = '0; + `AXI_SET_FROM_REQ(s_core_instr_bus, s_core_instr_bus_req) + end + `AXI_ASSIGN_TO_RESP(s_core_instr_bus_resp, s_core_instr_bus) + + pulp_icache_wrap #( + .NumFetchPorts ( Cfg.NumCores ), + .L0_LINE_COUNT ( Cfg.iCachePrivateSize*8/256 ), + .LINE_WIDTH ( 256 ), // Ideally 32*NumCores + .LINE_COUNT ( Cfg.iCacheSharedSize*8/256/Cfg.iCacheNumWays ), + .SET_COUNT ( Cfg.iCacheNumWays ), + .L1DataParityWidth ( 8 ), + .FetchAddrWidth ( AddrWidth ), + .FetchDataWidth ( Cfg.iCachePrivateDataWidth ), + .AxiAddrWidth ( AddrWidth ), + .AxiDataWidth ( Cfg.AxiDataOutWidth ), + .axi_req_t ( instr_axi_req_t ), + .axi_rsp_t ( instr_axi_resp_t ) + ) icache_top_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .fetch_req_i ( instr_req ), + .fetch_addr_i ( instr_addr ), + .fetch_gnt_o ( instr_gnt ), + .fetch_rvalid_o ( instr_r_valid ), + .fetch_rdata_o ( instr_r_rdata ), + .fetch_rerror_o (), + + .enable_prefetching_i ( s_enable_l1_l15_prefetch[0] ), + .icache_l0_events_o ( s_icache_l0_events ), + .icache_l1_events_o ( s_icache_l1_events ), + .flush_valid_i ( s_icache_flush_valid ), + .flush_ready_o ( s_icache_flush_ready ), + + .sram_cfg_data_i ('0), + .sram_cfg_tag_i ('0), + + .axi_req_o ( s_core_instr_bus_req ), + .axi_rsp_i ( s_core_instr_bus_resp ) + ); + + for (genvar i = 0; i < Cfg.NumCores; i++) begin + assign IC_ctrl_unit_bus_pri[i].bypass_ack = '0; + assign IC_ctrl_unit_bus_pri[i].flush_ack = '0; + assign IC_ctrl_unit_bus_pri[i].sel_flush_ack = '0; + `ifdef FEATURE_ICACHE_STAT + assign IC_ctrl_unit_bus_pri[i].ctrl_hit_count = '0; + assign IC_ctrl_unit_bus_pri[i].ctrl_trans_count = '0; + assign IC_ctrl_unit_bus_pri[i].ctrl_miss_count = '0; + assign IC_ctrl_unit_bus_pri[i].ctrl_cong_count = '0; + `endif + end + + for (genvar i = 0; i < Cfg.iCacheNumBanks; i++) begin + assign IC_ctrl_unit_bus_main[i].ctrl_flush_ack = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_ack_enable = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_ack_disable = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_pending_trans = '0; + assign IC_ctrl_unit_bus_main[i].sel_flush_ack = '0; + `ifdef FEATURE_ICACHE_STAT + assign IC_ctrl_unit_bus_main[i].ctrl_hit_count = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_trans_count = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_miss_count = '0; + `endif + end +`else + assign s_icache_flush_ready = '0; + assign s_icache_l0_events = '0; + assign s_icache_l1_events = '0; + + icache_hier_top #( + .FETCH_ADDR_WIDTH ( AddrWidth ), //= 32, + .PRI_FETCH_DATA_WIDTH ( Cfg.iCachePrivateDataWidth ), //= 128, // Tested for 32 and 128 + .SH_FETCH_DATA_WIDTH ( 128 ), //= 128, + + .NB_CORES ( Cfg.NumCores ), //= 8, + + .SH_NB_BANKS ( Cfg.iCacheNumBanks ), //= 1, + .SH_NB_WAYS ( Cfg.iCacheNumWays ), //= 4, + .SH_CACHE_SIZE ( Cfg.iCacheSharedSize), //= 4*1024, // in Byte + .SH_CACHE_LINE ( Cfg.iCacheNumLines ), //= 1, // in word of [SH_FETCH_DATA_WIDTH] + + .PRI_NB_WAYS ( Cfg.iCacheNumWays ), //= 4, + .PRI_CACHE_SIZE ( Cfg.iCachePrivateSize), //= 512, // in Byte + .PRI_CACHE_LINE ( Cfg.iCacheNumLines ), //= 1, // in word of [PRI_FETCH_DATA_WIDTH] + + .AXI_ID ( AxiIdInWidth ), //= 6, + .AXI_ADDR ( Cfg.AxiAddrWidth ), //= 32, + .AXI_USER ( Cfg.AxiUserWidth ), //= 6, + .AXI_DATA ( Cfg.AxiDataOutWidth ), //= 64, + + .USE_REDUCED_TAG ( Cfg.EnableReducedTag ), //= "TRUE", // TRUE | FALSE + .L2_SIZE ( Cfg.L2Size ) //= 512*1024 // Size of max(L2 ,ROM) program memory in Byte + ) icache_top_i ( + .clk ( clk_i ), + .rst_n ( rst_ni ), + .test_en_i ( test_mode_i ), + + .fetch_req_i ( instr_req ), + .fetch_addr_i ( instr_addr ), + .fetch_gnt_o ( instr_gnt ), + + .fetch_rvalid_o ( instr_r_valid ), + .fetch_rdata_o ( instr_r_rdata ), + + .enable_l1_l15_prefetch_i ( s_enable_l1_l15_prefetch ), // set it to 1 to use prefetch feature + + //AXI read address bus ------------------------------------------- + .axi_master_arid_o ( s_core_instr_bus.ar_id ), + .axi_master_araddr_o ( s_core_instr_bus.ar_addr ), + .axi_master_arlen_o ( s_core_instr_bus.ar_len ), //burst length - 1 to 16 + .axi_master_arsize_o ( s_core_instr_bus.ar_size ), //size of each transfer in burst + .axi_master_arburst_o ( s_core_instr_bus.ar_burst ), //accept only incr burst=01 + .axi_master_arlock_o ( s_core_instr_bus.ar_lock ), //only normal access supported axs_awlock=00 + .axi_master_arcache_o ( s_core_instr_bus.ar_cache ), + .axi_master_arprot_o ( s_core_instr_bus.ar_prot ), + .axi_master_arregion_o ( s_core_instr_bus.ar_region ), // + .axi_master_aruser_o ( s_core_instr_bus.ar_user ), // + .axi_master_arqos_o ( s_core_instr_bus.ar_qos ), // + .axi_master_arvalid_o ( s_core_instr_bus.ar_valid ), //master addr valid + .axi_master_arready_i ( s_core_instr_bus.ar_ready ), //slave ready to accept + // --------------------------------------------------------------- + + //AXI BACKWARD read data bus ---------------------------------------------- + .axi_master_rid_i ( s_core_instr_bus.r_id ), + .axi_master_rdata_i ( s_core_instr_bus.r_data ), + .axi_master_rresp_i ( s_core_instr_bus.r_resp ), + .axi_master_rlast_i ( s_core_instr_bus.r_last ), //last transfer in burst + .axi_master_ruser_i ( s_core_instr_bus.r_user ), + .axi_master_rvalid_i ( s_core_instr_bus.r_valid ), //slave data valid + .axi_master_rready_o ( s_core_instr_bus.r_ready ), //master ready to accept + + // NOT USED ---------------------------------------------- + .axi_master_awid_o ( s_core_instr_bus.aw_id ), + .axi_master_awaddr_o ( s_core_instr_bus.aw_addr ), + .axi_master_awlen_o ( s_core_instr_bus.aw_len ), + .axi_master_awsize_o ( s_core_instr_bus.aw_size ), + .axi_master_awburst_o ( s_core_instr_bus.aw_burst ), + .axi_master_awlock_o ( s_core_instr_bus.aw_lock ), + .axi_master_awcache_o ( s_core_instr_bus.aw_cache ), + .axi_master_awprot_o ( s_core_instr_bus.aw_prot ), + .axi_master_awregion_o ( s_core_instr_bus.aw_region ), + .axi_master_awuser_o ( s_core_instr_bus.aw_user ), + .axi_master_awqos_o ( s_core_instr_bus.aw_qos ), + .axi_master_awvalid_o ( s_core_instr_bus.aw_valid ), + .axi_master_awready_i ( s_core_instr_bus.aw_ready ), + + // NOT USED ---------------------------------------------- + .axi_master_wdata_o ( s_core_instr_bus.w_data ), + .axi_master_wstrb_o ( s_core_instr_bus.w_strb ), + .axi_master_wlast_o ( s_core_instr_bus.w_last ), + .axi_master_wuser_o ( s_core_instr_bus.w_user ), + .axi_master_wvalid_o ( s_core_instr_bus.w_valid ), + .axi_master_wready_i ( s_core_instr_bus.w_ready ), + // --------------------------------------------------------------- + + // NOT USED ---------------------------------------------- + .axi_master_bid_i ( s_core_instr_bus.b_id ), + .axi_master_bresp_i ( s_core_instr_bus.b_resp ), + .axi_master_buser_i ( s_core_instr_bus.b_user ), + .axi_master_bvalid_i ( s_core_instr_bus.b_valid ), + .axi_master_bready_o ( s_core_instr_bus.b_ready ), + // --------------------------------------------------------------- + + .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), + .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ) + ); + + assign s_core_instr_bus.aw_atop = '0; +`endif `REG_BUS_TYPEDEF_ALL(tcdm_scrubber_reg, logic[AddrWidth-1:0], logic[DataWidth-1:0], logic[BeWidth-1:0]) From d14f7c8e6d697d62619c15428f891fe4a0bef377 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 9 Jun 2024 17:23:16 +0200 Subject: [PATCH 190/207] Set define in to use snitch cache. --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index 0764afd2..84c5428e 100644 --- a/Makefile +++ b/Makefile @@ -39,6 +39,7 @@ bender_defs += -D NO_FPU bender_defs += -D TRACE_EXECUTION bender_defs += -D CLUSTER_ALIAS bender_defs += -D USE_PULP_PARAMETERS +bender_defs += -D SNITCH_ICACHE bender_targs += -t rtl bender_targs += -t test From 4e2eb72624884ed343a2be187912219a0a03857f Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 10 Jun 2024 10:52:28 +0200 Subject: [PATCH 191/207] Add AXI cut between snitch cache and cluster bus wrap. --- rtl/pulp_cluster.sv | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index a4220904..bbf5d624 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -1241,8 +1241,8 @@ generate endgenerate `ifdef SNITCH_ICACHE - instr_axi_req_t s_core_instr_bus_req; - instr_axi_resp_t s_core_instr_bus_resp; + instr_axi_req_t s_core_instr_bus_req, s_core_instr_bus_req_cut; + instr_axi_resp_t s_core_instr_bus_resp, s_core_instr_bus_resp_cut; always_comb begin s_core_instr_bus.aw_addr = '0; @@ -1284,8 +1284,26 @@ endgenerate .sram_cfg_data_i ('0), .sram_cfg_tag_i ('0), - .axi_req_o ( s_core_instr_bus_req ), - .axi_rsp_i ( s_core_instr_bus_resp ) + .axi_req_o ( s_core_instr_bus_req_cut ), + .axi_rsp_i ( s_core_instr_bus_resp_cut ) + ); + + axi_cut #( + .Bypass (0), + .aw_chan_t (instr_axi_aw_chan_t), + .w_chan_t (instr_axi_w_chan_t), + .b_chan_t (instr_axi_b_chan_t), + .ar_chan_t (instr_axi_ar_chan_t), + .r_chan_t (instr_axi_r_chan_t), + .axi_req_t (instr_axi_req_t), + .axi_resp_t (instr_axi_resp_t) + ) icache_cut_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .slv_req_i ( s_core_instr_bus_req_cut ), + .slv_resp_o ( s_core_instr_bus_resp_cut ), + .mst_req_o ( s_core_instr_bus_req ), + .mst_resp_i ( s_core_instr_bus_resp ) ); for (genvar i = 0; i < Cfg.NumCores; i++) begin From 2e17c8f0661d731a9ad081b80c3ef00c2010e3b8 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 17 Jun 2024 22:07:44 +0200 Subject: [PATCH 192/207] Fix `enable_l1_l15_prefetch` bus range in cluster peripherals. --- rtl/cluster_peripherals.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index d3645714..5ee663b1 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -337,7 +337,7 @@ module cluster_peripherals .l1_events_i ); - assign enable_l1_l15_prefetch_o[NB_CORES:1] = '0; + assign enable_l1_l15_prefetch_o[NB_CORES-1:1] = '0; for (genvar i = 0; i < NB_CORES; i++) begin assign IC_ctrl_unit_bus_pri[i].bypass_req = '0; From 6d5f0d940f623dbd4c25db1765bfec84d835f628 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 17 Jun 2024 22:10:22 +0200 Subject: [PATCH 193/207] Remove iCache AXI cut. --- rtl/pulp_cluster.sv | 26 ++++---------------------- 1 file changed, 4 insertions(+), 22 deletions(-) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index bbf5d624..a4220904 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -1241,8 +1241,8 @@ generate endgenerate `ifdef SNITCH_ICACHE - instr_axi_req_t s_core_instr_bus_req, s_core_instr_bus_req_cut; - instr_axi_resp_t s_core_instr_bus_resp, s_core_instr_bus_resp_cut; + instr_axi_req_t s_core_instr_bus_req; + instr_axi_resp_t s_core_instr_bus_resp; always_comb begin s_core_instr_bus.aw_addr = '0; @@ -1284,26 +1284,8 @@ endgenerate .sram_cfg_data_i ('0), .sram_cfg_tag_i ('0), - .axi_req_o ( s_core_instr_bus_req_cut ), - .axi_rsp_i ( s_core_instr_bus_resp_cut ) - ); - - axi_cut #( - .Bypass (0), - .aw_chan_t (instr_axi_aw_chan_t), - .w_chan_t (instr_axi_w_chan_t), - .b_chan_t (instr_axi_b_chan_t), - .ar_chan_t (instr_axi_ar_chan_t), - .r_chan_t (instr_axi_r_chan_t), - .axi_req_t (instr_axi_req_t), - .axi_resp_t (instr_axi_resp_t) - ) icache_cut_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .slv_req_i ( s_core_instr_bus_req_cut ), - .slv_resp_o ( s_core_instr_bus_resp_cut ), - .mst_req_o ( s_core_instr_bus_req ), - .mst_resp_i ( s_core_instr_bus_resp ) + .axi_req_o ( s_core_instr_bus_req ), + .axi_rsp_i ( s_core_instr_bus_resp ) ); for (genvar i = 0; i < Cfg.NumCores; i++) begin From e2c039ebdd94c792217f0dd2c0a549968b6e36f0 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Mon, 17 Jun 2024 22:10:42 +0200 Subject: [PATCH 194/207] Add AX latency in XBAR master ports. --- rtl/cluster_bus_wrap.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index e2722db2..846acbc8 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -161,7 +161,7 @@ module cluster_bus_wrap MaxSlvTrans: DMA_NB_OUTSND_BURSTS + NB_CORES, //Allow up to 4 in-flight transactions //per slave port FallThrough: 1'b0, //Use the reccomended default config - LatencyMode: axi_pkg::NO_LATENCY, // CUT_ALL_AX | axi_pkg::DemuxW, + LatencyMode: axi_pkg::CUT_MST_AX, // axi_pkg::CUT_ALL_AX | axi_pkg::DemuxW, PipelineStages: 0, AxiIdWidthSlvPorts: AXI_ID_IN_WIDTH, AxiIdUsedSlvPorts: AXI_ID_IN_WIDTH, From 98f536bdc74e78fba7dcc72d73d944e6f470012c Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Tue, 18 Jun 2024 13:56:41 +0200 Subject: [PATCH 195/207] Cut all AX ports in XBAR. --- rtl/cluster_bus_wrap.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index 846acbc8..93576b7e 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -161,7 +161,7 @@ module cluster_bus_wrap MaxSlvTrans: DMA_NB_OUTSND_BURSTS + NB_CORES, //Allow up to 4 in-flight transactions //per slave port FallThrough: 1'b0, //Use the reccomended default config - LatencyMode: axi_pkg::CUT_MST_AX, // axi_pkg::CUT_ALL_AX | axi_pkg::DemuxW, + LatencyMode: axi_pkg::CUT_ALL_AX, // CUT_ALL_AX | axi_pkg::DemuxW, PipelineStages: 0, AxiIdWidthSlvPorts: AXI_ID_IN_WIDTH, AxiIdUsedSlvPorts: AXI_ID_IN_WIDTH, From e9c2b218d467e9b3d07def7a4135c941d1281cff Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Wed, 19 Jun 2024 18:10:29 +0200 Subject: [PATCH 196/207] Add reliability to icache L0 --- Bender.lock | 2 +- Bender.yml | 1 - rtl/pulp_cluster.sv | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Bender.lock b/Bender.lock index bb0ff630..91a9ec18 100644 --- a/Bender.lock +++ b/Bender.lock @@ -38,7 +38,7 @@ packages: dependencies: - common_cells cluster_icache: - revision: 4cffcf37724704ab27d483338804a1981f5c4497 + revision: 8114ab36fd446f76cd1e9f139f12a62ab1fb9a6a version: null source: Git: https://github.com/pulp-platform/cluster_icache.git diff --git a/Bender.yml b/Bender.yml index f1141f94..8f1a98a1 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,7 +19,6 @@ dependencies: event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master - cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "4cffcf37724704ab27d483338804a1981f5c4497" } # branch: astral-synth hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "2886cb2a46cea3e2bd2d979b505d88fadfbe150c" } # branch: astral cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2 axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3 } diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index a4220904..2270df01 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -1258,6 +1258,7 @@ endgenerate .LINE_COUNT ( Cfg.iCacheSharedSize*8/256/Cfg.iCacheNumWays ), .SET_COUNT ( Cfg.iCacheNumWays ), .L1DataParityWidth ( 8 ), + .L0DataParityWidth ( 8 ), .FetchAddrWidth ( AddrWidth ), .FetchDataWidth ( Cfg.iCachePrivateDataWidth ), .AxiAddrWidth ( AddrWidth ), From ef16ba66bd1dc1f20b23013ac65968d1d936474b Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 27 Jun 2024 23:00:16 +0200 Subject: [PATCH 197/207] [PATCH]: Reintroduce cluster_icache dependency. --- Bender.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/Bender.yml b/Bender.yml index 8f1a98a1..8c82db3b 100644 --- a/Bender.yml +++ b/Bender.yml @@ -20,6 +20,7 @@ dependencies: mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "2886cb2a46cea3e2bd2d979b505d88fadfbe150c" } # branch: astral + cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "8114ab36fd446f76cd1e9f139f12a62ab1fb9a6a" } # michaero/branch: astral_cut_path cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2 axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3 } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } From 2cd26c4923570ae81297c06078a0cfcded1e761c Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 29 Jun 2024 10:40:37 +0200 Subject: [PATCH 198/207] Assign generic AXI request struct to HMR unit to prevent complains about undeclared (and unused) buses. --- rtl/pulp_cluster.sv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 2270df01..b8eb0521 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -1079,6 +1079,9 @@ hmr_unit #( .core_backup_t ( core_backup_t ), .reg_req_t ( hmr_reg_req_t ), .reg_rsp_t ( hmr_reg_rsp_t ), + // We use any axi_req_t to just let the unit not complain about + // undeclared r_ready and b_ready signals. + .axi_req_t ( instr_axi_req_t ), .rapid_recovery_t ( rapid_recovery_pkg::rapid_recovery_t ) ) i_hmr_unit ( .clk_i ( clk_i ), From 63f7c02cc50c275a9d4094daf1ed5b75a44b559a Mon Sep 17 00:00:00 2001 From: Luigi Ghionda Date: Thu, 27 Jun 2024 11:28:35 +0200 Subject: [PATCH 199/207] Add HCI with ECC (HWPE branch only) --- Bender.lock | 9 +++++---- Bender.yml | 6 +++--- rtl/cluster_interconnect_wrap.sv | 2 +- rtl/hwpe_subsystem.sv | 31 +++++++++++++++++++++++++++---- rtl/pulp_cluster.sv | 7 +++++-- 5 files changed, 41 insertions(+), 14 deletions(-) diff --git a/Bender.lock b/Bender.lock index 91a9ec18..b8b7e95e 100644 --- a/Bender.lock +++ b/Bender.lock @@ -108,7 +108,7 @@ packages: dependencies: - common_cells hci: - revision: afe0220f9a2f132dc8655c48da05aae5121a570b + revision: 95636da243bc7a7d4777db8ea537899445145788 version: null source: Git: https://github.com/pulp-platform/hci.git @@ -116,6 +116,7 @@ packages: - cluster_interconnect - hwpe-stream - l2_tcdm_hybrid_interco + - redundancy_cells hier-icache: revision: 2886cb2a46cea3e2bd2d979b505d88fadfbe150c version: null @@ -179,8 +180,8 @@ packages: dependencies: - common_cells neureka: - revision: b6141132d915b3fa5c1db712b730ac463a949a34 - version: 1.0.0 + revision: 793a33ee1a83e6686550c4cf665797467cb1c4b7 + version: null source: Git: https://github.com/pulp-platform/neureka.git dependencies: @@ -196,7 +197,7 @@ packages: dependencies: - axi_slice redmule: - revision: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 + revision: 831b31d55b2953f86a68c77012759d4f2913e5cb version: null source: Git: https://github.com/pulp-platform/redmule.git diff --git a/Bender.yml b/Bender.yml index 8c82db3b..54e4d448 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,11 +30,11 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: afe0220 } # branch: master + hci: { git: "https://github.com/pulp-platform/hci.git", rev: 95636da } # branch: lg/ecc_to_mem_rebase register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc } # branch: astral-v0 - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 } # branch: fc/hci-v2.1 - neureka: { git: "https://github.com/pulp-platform/neureka.git", version: 1.0.0 } + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 831b31d } # branch: lg/hci-v2.1-ecc + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 793a33e } # branch: lg/hci-ecc-rebase softex: { git: "https://github.com/belanoa/softex.git" , version: 1.0.0 } export_include_dirs: diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index 5fa063c5..161a2b7e 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -75,7 +75,7 @@ module cluster_interconnect_wrap generate if( USE_HETEROGENEOUS_INTERCONNECT || !HWPE_PRESENT ) begin : hci_gen - hci_interconnect #( + hci_ecc_interconnect #( .N_HWPE ( HWPE_PRESENT ), .N_CORE ( NB_CORES ), .N_DMA ( NB_DMAS ), diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index 6fb56e9a..eb9c62df 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -42,8 +42,21 @@ module hwpe_subsystem localparam int unsigned DW = HCI_HWPE_SIZE.DW; localparam int unsigned AW = HCI_HWPE_SIZE.AW; + localparam int unsigned EW = HCI_HWPE_SIZE.EW; localparam int unsigned EHW = HCI_HWPE_SIZE.EHW; + // TEMP: localparam used by softex since it doesn't support yet ECC-HCI interface + localparam hci_package::hci_size_parameter_t `HCI_SIZE_PARAM(tcdm_softex) = '{ + DW: DW, + AW: AW, + BW: DEFAULT_BW, + UW: DEFAULT_UW, + IW: DEFAULT_IW, + EW: DEFAULT_EW, + EHW: DEFAULT_EHW + }; + `HCI_INTF(tcdm_softex, clk); + localparam int unsigned N_HWPES = HWPE_CFG.NumHwpes; logic [N_HWPES-1:0] busy; @@ -63,6 +76,7 @@ module hwpe_subsystem hci_core_intf #( .DW ( DW ), .AW ( AW ), + .EW ( EW ), .EHW ( EHW ) ) tcdm [0:N_HWPES-1] (.clk(clk)); @@ -89,7 +103,8 @@ module hwpe_subsystem redmule_top #( .ID_WIDTH ( ID_WIDTH ), .N_CORES ( N_CORES ), - .DW ( N_MASTER_PORT*32 ) + .DW ( N_MASTER_PORT*32 ), + .`HCI_SIZE_PARAM(tcdm) ( HCI_HWPE_SIZE ) ) i_redmule ( .clk_i ( hwpe_clk[i] ), .rst_ni ( rst_n ), @@ -134,16 +149,24 @@ module hwpe_subsystem softex_top #( .N_CORES ( N_CORES ), - .`HCI_SIZE_PARAM(Tcdm) ( HCI_HWPE_SIZE ) - ) i_softex ( + .`HCI_SIZE_PARAM(Tcdm) ( `HCI_SIZE_PARAM(tcdm_softex) ) + ) i_softex ( .clk_i ( hwpe_clk[i] ), .rst_ni ( rst_n ), .busy_o ( busy[i] ), .evt_o ( evt[i] ), - .tcdm ( tcdm[i] ), + .tcdm ( tcdm_softex ), .periph ( periph[i] ) ); + // TEMP: softex doesn't yet support ECC-HCI internally + hci_ecc_enc #( + .`HCI_SIZE_PARAM(tcdm_target) ( `HCI_SIZE_PARAM(tcdm_softex) ) + ) i_ecc_softex_enc ( + .tcdm_target ( tcdm_softex ), + .tcdm_initiator ( tcdm[i] ) + ); + end end diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index b8eb0521..be91a984 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -101,7 +101,9 @@ module pulp_cluster // Number of parity bits for ECC in memory banks localparam int unsigned ParityWidth = 7, // TCDM banks data width extended with parity for ECCs - localparam int unsigned ProtectedTcdmWidth = DataWidth + ParityWidth + localparam int unsigned ProtectedTcdmWidth = DataWidth + ParityWidth, + // Number of parity bits for ECC in HCI HWPE branch + localparam int unsigned HWPEParityWidth = ($clog2(DataWidth)+2)*Cfg.HwpeNumPorts + ($clog2(AddrWidth+(Cfg.HwpeNumPorts*DataWidth)/8+1)+2) )( input logic clk_i, input logic rst_ni, @@ -319,7 +321,7 @@ localparam hci_package::hci_size_parameter_t HciHwpeSizeParam = '{ BW: DEFAULT_BW, UW: DEFAULT_UW, IW: DEFAULT_IW, - EW: DEFAULT_EW, + EW: HWPEParityWidth, EHW: DEFAULT_EHW }; /* logarithmic and peripheral interconnect interfaces */ @@ -356,6 +358,7 @@ XBAR_TCDM_BUS s_mperiph_bus(); hci_core_intf #( .DW ( HciHwpeSizeParam.DW ), .AW ( HciHwpeSizeParam.AW ), + .EW ( HciHwpeSizeParam.EW ), .EHW ( HciHwpeSizeParam.EHW ) ) s_hci_hwpe [0:0] ( .clk ( clk_i ) From e95d155caa795a9d73185a18aee9fbcf483d3b2a Mon Sep 17 00:00:00 2001 From: Luigi Ghionda Date: Thu, 27 Jun 2024 12:08:58 +0200 Subject: [PATCH 200/207] Add memory-mapped registers to store number of detected errors on ECC-extended HCI --- Bender.lock | 4 +++- Bender.yml | 2 +- include/pulp_soc_defines.sv | 2 +- packages/pulp_cluster_package.sv | 7 ++++--- pulp-runtime | 2 +- rtl/cluster_interconnect_wrap.sv | 20 +++++++++++--------- rtl/cluster_peripherals.sv | 18 ++++++++++++++++++ rtl/pulp_cluster.sv | 6 ++++++ 8 files changed, 45 insertions(+), 16 deletions(-) diff --git a/Bender.lock b/Bender.lock index b8b7e95e..e7682489 100644 --- a/Bender.lock +++ b/Bender.lock @@ -108,15 +108,17 @@ packages: dependencies: - common_cells hci: - revision: 95636da243bc7a7d4777db8ea537899445145788 + revision: e04701b05305cfdfa8a2fcac51c820c14bcfa07b version: null source: Git: https://github.com/pulp-platform/hci.git dependencies: - cluster_interconnect + - common_cells - hwpe-stream - l2_tcdm_hybrid_interco - redundancy_cells + - register_interface hier-icache: revision: 2886cb2a46cea3e2bd2d979b505d88fadfbe150c version: null diff --git a/Bender.yml b/Bender.yml index 54e4d448..bb55fd73 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: 95636da } # branch: lg/ecc_to_mem_rebase + hci: { git: "https://github.com/pulp-platform/hci.git", rev: e04701b } # branch: lg/ecc_to_mem_rebase register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc } # branch: astral-v0 redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 831b31d } # branch: lg/hci-v2.1-ecc diff --git a/include/pulp_soc_defines.sv b/include/pulp_soc_defines.sv index a5c33c41..965fef4a 100644 --- a/include/pulp_soc_defines.sv +++ b/include/pulp_soc_defines.sv @@ -50,4 +50,4 @@ `define NB_CORES 8 `define NB_DMAS 4 `define NB_MPERIPHS 1 -`define NB_SPERIPHS 11 +`define NB_SPERIPHS 12 diff --git a/packages/pulp_cluster_package.sv b/packages/pulp_cluster_package.sv index 2553d549..45954893 100644 --- a/packages/pulp_cluster_package.sv +++ b/packages/pulp_cluster_package.sv @@ -150,7 +150,7 @@ package pulp_cluster_package; // number of master and slave cluster periphs parameter int unsigned NB_MPERIPHS = 1; - parameter int unsigned NB_SPERIPHS = 11; + parameter int unsigned NB_SPERIPHS = 12; // position of peripherals on slave port of periph interconnect parameter int unsigned SPER_EOC_ID = 0; // 0x0000 - 0x0400 @@ -163,8 +163,9 @@ package pulp_cluster_package; parameter int unsigned SPER_DMA_FC_ID = 7; // 0x1C00 - 0x2000 parameter int unsigned SPER_HMR_UNIT_ID = 8; // 0x2000 - 0x2400 parameter int unsigned SPER_TCDM_SCRUBBER_ID = 9; // 0x2400 - 0x2800 - parameter int unsigned SPER_EXT_ID = 10; // -> unmapped, directed to error - parameter int unsigned SPER_ERROR_ID = 11; // -> unmapped, directed to error + parameter int unsigned SPER_HWPE_HCI_ECC_ID = 10; // 0x2800 - 0x3200 + parameter int unsigned SPER_EXT_ID = 11; // -> unmapped, directed to error + parameter int unsigned SPER_ERROR_ID = 12; // -> unmapped, directed to error // The following parameters refer to the cluster AXI crossbar localparam byte_t NumAxiSubordinatePorts = 4; diff --git a/pulp-runtime b/pulp-runtime index f3e685f3..3ba9a349 160000 --- a/pulp-runtime +++ b/pulp-runtime @@ -1 +1 @@ -Subproject commit f3e685f38e5f07fa98ff26b8ab875c063feccfca +Subproject commit 3ba9a349664047c292d10640309a67a63bddd0c7 diff --git a/rtl/cluster_interconnect_wrap.sv b/rtl/cluster_interconnect_wrap.sv index 161a2b7e..015e9dfc 100644 --- a/rtl/cluster_interconnect_wrap.sv +++ b/rtl/cluster_interconnect_wrap.sv @@ -53,6 +53,7 @@ module cluster_interconnect_wrap input logic clk_i, input logic rst_ni, input logic [5:0] cluster_id_i, + XBAR_PERIPH_BUS.Slave hci_ecc_periph_slave, hci_core_intf.target core_tcdm_slave [0 : NB_CORES-1 ], hci_core_intf.target hwpe_tcdm_slave [0 : 0 ], XBAR_PERIPH_BUS.Slave core_periph_slave [NB_CORES-1 : 0 ], @@ -94,15 +95,16 @@ module cluster_interconnect_wrap .WAIVE_RSP5_ASSERT ( 1'b1 ) `endif ) i_hci_interconnect ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .clear_i( 1'b0 ), - .ctrl_i ( hci_ctrl_i ), - .cores ( core_tcdm_slave ), - .hwpe ( hwpe_tcdm_slave [0] ), - .dma ( dma_slave ), - .ext ( ext_slave ), - .mems ( tcdm_sram_master ) + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clear_i ( 1'b0 ), + .ctrl_i ( hci_ctrl_i ), + .periph_hci_ecc ( hci_ecc_periph_slave ), + .cores ( core_tcdm_slave ), + .hwpe ( hwpe_tcdm_slave [0] ), + .dma ( dma_slave ), + .ext ( ext_slave ), + .mems ( tcdm_sram_master ) ); end else begin : no_hci_gen diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index 5ee663b1..dee36d9d 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -99,6 +99,7 @@ module cluster_peripherals XBAR_PERIPH_BUS.Master hwpe_cfg_master, XBAR_PERIPH_BUS.Master hmr_cfg_master, XBAR_PERIPH_BUS.Master tcdm_scrubber_cfg_master, + XBAR_PERIPH_BUS.Master hwpe_hci_ecc_cfg_master, input logic [NB_CORES-1:0][3:0] hwpe_events_i, output logic hwpe_en_o, output logic [$clog2(NB_HWPES)-1:0] hwpe_sel_o, @@ -464,6 +465,23 @@ module cluster_peripherals assign tcdm_scrubber_cfg_master.be = speriph_slave[SPER_TCDM_SCRUBBER_ID].be; assign tcdm_scrubber_cfg_master.id = speriph_slave[SPER_TCDM_SCRUBBER_ID].id; + //******************************************************** + //******************** HWPE HCI with ECC ********************* + //******************************************************** + + assign speriph_slave[SPER_HWPE_HCI_ECC_ID].gnt = hwpe_hci_ecc_cfg_master.gnt; + assign speriph_slave[SPER_HWPE_HCI_ECC_ID].r_rdata = hwpe_hci_ecc_cfg_master.r_rdata; + assign speriph_slave[SPER_HWPE_HCI_ECC_ID].r_opc = hwpe_hci_ecc_cfg_master.r_opc; + assign speriph_slave[SPER_HWPE_HCI_ECC_ID].r_id = hwpe_hci_ecc_cfg_master.r_id; + assign speriph_slave[SPER_HWPE_HCI_ECC_ID].r_valid = hwpe_hci_ecc_cfg_master.r_valid; + + assign hwpe_hci_ecc_cfg_master.req = speriph_slave[SPER_HWPE_HCI_ECC_ID].req; + assign hwpe_hci_ecc_cfg_master.add = speriph_slave[SPER_HWPE_HCI_ECC_ID].add; + assign hwpe_hci_ecc_cfg_master.wen = speriph_slave[SPER_HWPE_HCI_ECC_ID].wen; + assign hwpe_hci_ecc_cfg_master.wdata = speriph_slave[SPER_HWPE_HCI_ECC_ID].wdata; + assign hwpe_hci_ecc_cfg_master.be = speriph_slave[SPER_HWPE_HCI_ECC_ID].be; + assign hwpe_hci_ecc_cfg_master.id = speriph_slave[SPER_HWPE_HCI_ECC_ID].id; + generate if(FEATURE_DEMUX_MAPPED == 0) begin : eu_not_demux_mapped_gen for(genvar i=0;i< NB_CORES; i++) begin diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index be91a984..57a47962 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -382,6 +382,9 @@ XBAR_PERIPH_BUS s_periph_hmr_bus (); // periph interconnect -> TCDM scrubber XBAR_PERIPH_BUS s_periph_tcdm_scrubber_bus (); +// periph interconnect -> HCI with ECC +XBAR_PERIPH_BUS s_periph_hwpe_hci_ecc_bus (); + // debug XBAR_TCDM_BUS s_debug_bus[Cfg.NumCores-1:0](); @@ -659,6 +662,8 @@ cluster_interconnect_wrap #( .rst_ni ( rst_ni ), .cluster_id_i ( '0 ), + .hci_ecc_periph_slave ( s_periph_hwpe_hci_ecc_bus ), + .core_tcdm_slave ( s_hci_core ), .hwpe_tcdm_slave ( s_hci_hwpe ), .ext_slave ( s_hci_ext ), @@ -778,6 +783,7 @@ cluster_peripherals #( .dma_cfg_master ( s_periph_dma_bus ), .hmr_cfg_master ( s_periph_hmr_bus ), .tcdm_scrubber_cfg_master ( s_periph_tcdm_scrubber_bus ), + .hwpe_hci_ecc_cfg_master ( s_periph_hwpe_hci_ecc_bus ), .dma_cl_event_i ( s_dma_cl_event ), .dma_cl_irq_i ( s_dma_cl_irq ), From f5480b9086ec0d5ace89bd196a831d308a846680 Mon Sep 17 00:00:00 2001 From: Luigi Ghionda Date: Thu, 27 Jun 2024 16:09:46 +0200 Subject: [PATCH 201/207] Add support to ECC-extended Interco up to TCDM banks --- Bender.lock | 2 +- Bender.yml | 2 +- rtl/hwpe_subsystem.sv | 8 +- rtl/pulp_cluster.sv | 14 ++- rtl/tcdm_banks_wrap.sv | 106 +++++++++++++++--- .../pulp_extract_nets.tcl | 2 +- 6 files changed, 109 insertions(+), 25 deletions(-) diff --git a/Bender.lock b/Bender.lock index e7682489..c84f8890 100644 --- a/Bender.lock +++ b/Bender.lock @@ -108,7 +108,7 @@ packages: dependencies: - common_cells hci: - revision: e04701b05305cfdfa8a2fcac51c820c14bcfa07b + revision: 246934b14432d6b1132ef838d59fc999eb788f18 version: null source: Git: https://github.com/pulp-platform/hci.git diff --git a/Bender.yml b/Bender.yml index bb55fd73..af029995 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: e04701b } # branch: lg/ecc_to_mem_rebase + hci: { git: "https://github.com/pulp-platform/hci.git", rev: 246934b } # branch: lg/ecc_to_mem_rebase register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc } # branch: astral-v0 redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 831b31d } # branch: lg/hci-v2.1-ecc diff --git a/rtl/hwpe_subsystem.sv b/rtl/hwpe_subsystem.sv index eb9c62df..01263b5b 100644 --- a/rtl/hwpe_subsystem.sv +++ b/rtl/hwpe_subsystem.sv @@ -161,8 +161,14 @@ module hwpe_subsystem // TEMP: softex doesn't yet support ECC-HCI internally hci_ecc_enc #( - .`HCI_SIZE_PARAM(tcdm_target) ( `HCI_SIZE_PARAM(tcdm_softex) ) + .DW ( DW ), + .`HCI_SIZE_PARAM(tcdm_target) ( `HCI_SIZE_PARAM(tcdm_softex) ), + .`HCI_SIZE_PARAM(tcdm_initiator) ( HCI_HWPE_SIZE ) ) i_ecc_softex_enc ( + .r_data_single_err_o ( ), + .r_data_multi_err_o ( ), + .r_meta_single_err_o ( ), + .r_meta_multi_err_o ( ), .tcdm_target ( tcdm_softex ), .tcdm_initiator ( tcdm[i] ) ); diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index 57a47962..f20ff077 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -100,9 +100,11 @@ module pulp_cluster localparam int unsigned FpuOutFlagsWidth = 5, // Number of parity bits for ECC in memory banks localparam int unsigned ParityWidth = 7, + // Number of parity bits for metadata in ECC-extended HCI + localparam int unsigned MetaParityWidth = $clog2( AddrMemWidth+2 + BeWidth +1 ) + 2, // TCDM banks data width extended with parity for ECCs localparam int unsigned ProtectedTcdmWidth = DataWidth + ParityWidth, - // Number of parity bits for ECC in HCI HWPE branch + // Number of parity bits for ECC-extended HCI HWPE branch localparam int unsigned HWPEParityWidth = ($clog2(DataWidth)+2)*Cfg.HwpeNumPorts + ($clog2(AddrWidth+(Cfg.HwpeNumPorts*DataWidth)/8+1)+2) )( input logic clk_i, @@ -434,7 +436,7 @@ localparam hci_package::hci_size_parameter_t HciMemSizeParam = '{ BW: 8, UW: DEFAULT_UW, IW: TCDM_ID_WIDTH, - EW: DEFAULT_EW, + EW: ParityWidth+MetaParityWidth, EHW: DEFAULT_EHW }; @@ -443,7 +445,8 @@ hci_core_intf #( .AW ( AddrMemWidth+2 ), // AddrMemWidth is word-wise, +2 for byte-wise .DW ( DataWidth ), .BW ( 8 ), - .IW ( TCDM_ID_WIDTH ) + .IW ( TCDM_ID_WIDTH ), + .EW ( ParityWidth+MetaParityWidth ) `ifndef SYNTHESIS , .WAIVE_RSP3_ASSERT ( 1'b1 ), @@ -1495,8 +1498,9 @@ tcdm_banks_wrap #( .BeWidth ( BeWidth ), .IdWidth ( TCDM_ID_WIDTH ), .EnableEcc ( 1 ), - .EccInterco ( 0 ), // Not supported at the moment - .ProtectedWidth ( ProtectedTcdmWidth ) + .EccInterco ( 1 ), + .ProtectedWidth ( ProtectedTcdmWidth ), + .HCI_MEM_SIZE ( HciMemSizeParam ) ) tcdm_banks_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/rtl/tcdm_banks_wrap.sv b/rtl/tcdm_banks_wrap.sv index 4bfe6541..1d367ffc 100644 --- a/rtl/tcdm_banks_wrap.sv +++ b/rtl/tcdm_banks_wrap.sv @@ -16,6 +16,8 @@ * Francesco Conti */ +`include "hci_helpers.svh" + module tcdm_banks_wrap #( parameter int unsigned BankSize = 256, //- -> OVERRIDE parameter int unsigned NbBanks = 1, // --> OVERRIDE @@ -25,7 +27,8 @@ module tcdm_banks_wrap #( parameter int unsigned IdWidth = 1, parameter bit EnableEcc = 1, parameter bit EccInterco = 0, - parameter int unsigned ProtectedWidth = DataWidth + 7 + parameter int unsigned ProtectedWidth = DataWidth + 7, + parameter hci_package::hci_size_parameter_t HCI_MEM_SIZE = '0 ) ( input logic clk_i, input logic rst_ni, @@ -42,21 +45,7 @@ module tcdm_banks_wrap #( for(genvar i=0; i Date: Thu, 11 Jul 2024 07:06:02 +0200 Subject: [PATCH 204/207] Bump non-free to add softex regression. --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 9018b463..52d4b753 100644 --- a/Makefile +++ b/Makefile @@ -59,7 +59,7 @@ endef ###################### NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/pulp-cluster-nonfree.git -NONFREE_COMMIT ?= 06cb2203 +NONFREE_COMMIT ?= ef45d63e nonfree-init: git clone $(NONFREE_REMOTE) nonfree From f7c4fd75aacb8b4a233cc6a2a9c0f3766c5d004f Mon Sep 17 00:00:00 2001 From: Luigi Ghionda Date: Sat, 17 Aug 2024 16:14:19 +0200 Subject: [PATCH 205/207] Bump HWPEs. --- Bender.lock | 6 +++--- Bender.yml | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Bender.lock b/Bender.lock index 714f94b7..48b38821 100644 --- a/Bender.lock +++ b/Bender.lock @@ -108,7 +108,7 @@ packages: dependencies: - common_cells hci: - revision: 33e95cb7f8ce98587e06ce74a3914d1ec09aee52 + revision: 38fc2a7eea7978df52434e66ee04a40788fd86b7 version: null source: Git: https://github.com/pulp-platform/hci.git @@ -182,7 +182,7 @@ packages: dependencies: - common_cells neureka: - revision: 7f991e5b792872c8d7892a49050b8c58804f94f4 + revision: f23d22a2d630cf8e4d524c919bfd943ab9e4998d version: null source: Git: https://github.com/pulp-platform/neureka.git @@ -200,7 +200,7 @@ packages: dependencies: - axi_slice redmule: - revision: 41150b9251207bb1e0e76544aa5915042e26834c + revision: 9223ccc932e21d0667e9c2d30831db41eec9299e version: null source: Git: https://github.com/pulp-platform/redmule.git diff --git a/Bender.yml b/Bender.yml index e29fcdde..4d0bb01b 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,11 +30,11 @@ dependencies: cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: e863f576699815b38cc9d80dbdede8ed5efd5991 } # `michaero/safety-island-clic` branch ibex: { git: "https://github.com/pulp-platform/ibex.git", rev: "pulpissimo-v6.1.2" } scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating - hci: { git: "https://github.com/pulp-platform/hci.git", rev: 33e95cb } # branch: lg/ecc_rebase_v2.1.1 + hci: { git: "https://github.com/pulp-platform/hci.git", rev: 38fc2a7 } # branch: lg/ecc_rebase_v2.1.1 register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc } # branch: astral-v0 - redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 41150b9 } # branch: lg/hci-v2.1-ecc-regs - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 7f991e5 } # branch: lg/hci-ecc-rebase-v1 + redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 9223ccc } # branch: astral-hci-v2.1 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: f23d22a } # branch: astral-v1.0 softex: { git: "https://github.com/belanoa/softex.git" , version: 1.0.0 } export_include_dirs: From 2714339a5f65b22227480f099bb37f193ceb6324 Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 23 Aug 2024 23:06:41 +0200 Subject: [PATCH 206/207] Bump NEUREKA to version rebased on main --- Bender.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index 4d0bb01b..ff0fe717 100644 --- a/Bender.yml +++ b/Bender.yml @@ -34,7 +34,7 @@ dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc } # branch: astral-v0 redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 9223ccc } # branch: astral-hci-v2.1 - neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: f23d22a } # branch: astral-v1.0 + neureka: { git: "https://github.com/pulp-platform/neureka.git", rev: 94528df } # branch: fc/astral-v1.0-rebased softex: { git: "https://github.com/belanoa/softex.git" , version: 1.0.0 } export_include_dirs: From 07988cd01c359a81804820135927bc04da3c25cd Mon Sep 17 00:00:00 2001 From: Francesco Conti Date: Fri, 23 Aug 2024 23:29:50 +0200 Subject: [PATCH 207/207] fix Bender.lock --- Bender.lock | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Bender.lock b/Bender.lock index 48b38821..b88d0385 100644 --- a/Bender.lock +++ b/Bender.lock @@ -182,7 +182,7 @@ packages: dependencies: - common_cells neureka: - revision: f23d22a2d630cf8e4d524c919bfd943ab9e4998d + revision: 94528df2bc6d5eedc0439bd403c2ad005f0a7519 version: null source: Git: https://github.com/pulp-platform/neureka.git