diff --git a/Bender.lock b/Bender.lock index 28879c3..bb0ff63 100644 --- a/Bender.lock +++ b/Bender.lock @@ -38,7 +38,7 @@ packages: dependencies: - common_cells cluster_icache: - revision: b3b0c474eb5baa2fdeece65369805206398ab63b + revision: 4cffcf37724704ab27d483338804a1981f5c4497 version: null source: Git: https://github.com/pulp-platform/cluster_icache.git @@ -116,6 +116,18 @@ packages: - cluster_interconnect - hwpe-stream - l2_tcdm_hybrid_interco + hier-icache: + revision: 2886cb2a46cea3e2bd2d979b505d88fadfbe150c + version: null + source: + Git: https://github.com/pulp-platform/hier-icache.git + dependencies: + - axi + - axi_slice + - common_cells + - icache-intc + - scm + - tech_cells_generic hwpe-ctrl: revision: a5966201aeeb988d607accdc55da933a53c6a56e version: null @@ -137,6 +149,12 @@ packages: Git: https://github.com/pulp-platform/ibex.git dependencies: - tech_cells_generic + icache-intc: + revision: 663c3b6d3c2bf63ff25cda46f33c799c647b3985 + version: 1.0.1 + source: + Git: https://github.com/pulp-platform/icache-intc.git + dependencies: [] idma: revision: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 version: null @@ -191,7 +209,7 @@ packages: - hwpe-stream - tech_cells_generic redundancy_cells: - revision: c37bdb47339bf70e8323de8df14ea8bbeafb6583 + revision: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc version: null source: Git: https://github.com/pulp-platform/redundancy_cells.git @@ -219,12 +237,11 @@ packages: - fpnew - tech_cells_generic scm: - revision: 74426dee36f28ae1c02f7635cf844a0156145320 - version: null + revision: 998466d2a3c2d7d572e43d2666d93c4f767d8d60 + version: 1.1.1 source: Git: https://github.com/pulp-platform/scm.git - dependencies: - - tech_cells_generic + dependencies: [] softex: revision: 23faeccaf204817bc9e6649e469072e5726be561 version: 1.0.0 @@ -238,8 +255,8 @@ packages: - hwpe-stream - ibex tech_cells_generic: - revision: a9cae21902e75b1434328ecf36f85327ba5717de - version: 0.2.11 + revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf + version: 0.2.13 source: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: diff --git a/Bender.yml b/Bender.yml index 2f3bd5a..f1141f9 100644 --- a/Bender.yml +++ b/Bender.yml @@ -19,7 +19,8 @@ dependencies: event_unit_flex: { git: "https://github.com/pulp-platform/event_unit_flex.git", rev: 28e0499374117c7b0ef4c6ad81b60d7526af886f } # branch: michaero/hmr mchan: { git: "https://github.com/pulp-platform/mchan.git", rev: 7f064f205a3e0203e959b14773c4afecf56681ab } # branch: yt/fix-parametrization idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 437ffa9dac5dea0daccfd3e8ae604d4f6ae2cdf1 } # branch: master - cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "b3b0c474eb5baa2fdeece65369805206398ab63b" } + cluster_icache: { git: "https://github.com/pulp-platform/cluster_icache.git", rev: "4cffcf37724704ab27d483338804a1981f5c4497" } # branch: astral-synth + hier-icache: { git: "https://github.com/pulp-platform/hier-icache.git", rev: "2886cb2a46cea3e2bd2d979b505d88fadfbe150c" } # branch: astral cluster_peripherals: { git: "https://github.com/pulp-platform/cluster_peripherals.git", rev: 0b8e8ab } # branch: fc/hci-v2 axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3 } timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 } @@ -31,7 +32,7 @@ dependencies: scm: { git: "https://github.com/pulp-platform/scm.git", rev: 74426dee36f28ae1c02f7635cf844a0156145320 } # branch: yt/bump-clkgating hci: { git: "https://github.com/pulp-platform/hci.git", rev: afe0220 } # branch: master register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 } - redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: c37bdb47339bf70e8323de8df14ea8bbeafb6583 } # branch: astral_rebase + redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 49e714b97a19a7aaddf064ae2757c8f02d1f62dc } # branch: astral-v0 redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: 60ba008c339ec70b5ffa7120bec2cbf5a8f53c99 } # branch: fc/hci-v2.1 neureka: { git: "https://github.com/pulp-platform/neureka.git", version: 1.0.0 } softex: { git: "https://github.com/belanoa/softex.git" , version: 1.0.0 } diff --git a/Makefile b/Makefile index 0764afd..84c5428 100644 --- a/Makefile +++ b/Makefile @@ -39,6 +39,7 @@ bender_defs += -D NO_FPU bender_defs += -D TRACE_EXECUTION bender_defs += -D CLUSTER_ALIAS bender_defs += -D USE_PULP_PARAMETERS +bender_defs += -D SNITCH_ICACHE bender_targs += -t rtl bender_targs += -t test diff --git a/rtl/cluster_bus_wrap.sv b/rtl/cluster_bus_wrap.sv index e2722db..93576b7 100644 --- a/rtl/cluster_bus_wrap.sv +++ b/rtl/cluster_bus_wrap.sv @@ -161,7 +161,7 @@ module cluster_bus_wrap MaxSlvTrans: DMA_NB_OUTSND_BURSTS + NB_CORES, //Allow up to 4 in-flight transactions //per slave port FallThrough: 1'b0, //Use the reccomended default config - LatencyMode: axi_pkg::NO_LATENCY, // CUT_ALL_AX | axi_pkg::DemuxW, + LatencyMode: axi_pkg::CUT_ALL_AX, // CUT_ALL_AX | axi_pkg::DemuxW, PipelineStages: 0, AxiIdWidthSlvPorts: AXI_ID_IN_WIDTH, AxiIdUsedSlvPorts: AXI_ID_IN_WIDTH, diff --git a/rtl/cluster_peripherals.sv b/rtl/cluster_peripherals.sv index 39912cc..5ee663b 100644 --- a/rtl/cluster_peripherals.sv +++ b/rtl/cluster_peripherals.sv @@ -105,7 +105,9 @@ module cluster_peripherals output hci_package::hci_interconnect_ctrl_t hci_ctrl_o, // Control ports - output logic enable_l1_l15_prefetch_o, + SP_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_main[NB_CACHE_BANKS-1:0], + PRI_ICACHE_CTRL_UNIT_BUS.Master IC_ctrl_unit_bus_pri[NB_CORES-1:0], + output logic [NB_CORES-1:0] enable_l1_l15_prefetch_o, output logic [NB_CORES-1:0] flush_valid_o, input logic [NB_CORES-1:0] flush_ready_i, // input snitch_icache_pkg::icache_l0_events_t [NB_CORES-1:0] l0_events_i, @@ -284,6 +286,7 @@ module cluster_peripherals //******************** icache_ctrl_unit ****************** //******************************************************** +`ifdef SNITCH_ICACHE `REG_BUS_TYPEDEF_ALL(icache, logic[31:0], logic[31:0], logic[3:0]) icache_req_t icache_req; icache_rsp_t icache_rsp; @@ -326,7 +329,7 @@ module cluster_peripherals .reg_req_i ( icache_req ), .reg_rsp_o ( icache_rsp ), - .enable_prefetching_o ( enable_l1_l15_prefetch_o), + .enable_prefetching_o ( enable_l1_l15_prefetch_o[0]), .flush_valid_o, .flush_ready_i, @@ -334,6 +337,48 @@ module cluster_peripherals .l1_events_i ); + assign enable_l1_l15_prefetch_o[NB_CORES-1:1] = '0; + + for (genvar i = 0; i < NB_CORES; i++) begin + assign IC_ctrl_unit_bus_pri[i].bypass_req = '0; + assign IC_ctrl_unit_bus_pri[i].flush_req = '0; + assign IC_ctrl_unit_bus_pri[i].sel_flush_req = '0; + assign IC_ctrl_unit_bus_pri[i].sel_flush_addr = '0; + `ifdef FEATURE_ICACHE_STAT + assign IC_ctrl_unit_bus_pri[i].ctrl_clear_regs = '0; + assign IC_ctrl_unit_bus_pri[i].ctrl_enable_regs = '0; + `endif + end + + for (genvar i = 0; i < NB_CACHE_BANKS; i++) begin + assign IC_ctrl_unit_bus_main[i].ctrl_req_enable = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_req_disable = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_flush_req = '0; + assign IC_ctrl_unit_bus_main[i].icache_is_private = '0; + assign IC_ctrl_unit_bus_main[i].sel_flush_req = '0; + assign IC_ctrl_unit_bus_main[i].sel_flush_addr = '0; + `ifdef FEATURE_ICACHE_STAT + assign IC_ctrl_unit_bus_main[i].ctrl_clear_regs = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_enable_regs = '0; + `endif + end +`else + assign flush_valid_o = '0; + hier_icache_ctrl_unit_wrap #( + .NB_CACHE_BANKS ( NB_CACHE_BANKS ), + .NB_CORES ( NB_CORES ), + .ID_WIDTH ( NB_CORES+NB_MPERIPHS ) + ) icache_ctrl_unit_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .speriph_slave ( speriph_slave[SPER_ICACHE_CTRL] ), + .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), + .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), + .enable_l1_l15_prefetch_o ( enable_l1_l15_prefetch_o ) + ); +`endif + //******************************************************** //******************** DMA CL CONFIG PORT **************** //******************************************************** diff --git a/rtl/pulp_cluster.sv b/rtl/pulp_cluster.sv index b87b87f..a422090 100644 --- a/rtl/pulp_cluster.sv +++ b/rtl/pulp_cluster.sv @@ -413,7 +413,9 @@ logic [Cfg.NumCores-1:0][FpuOutFlagsWidth-1:0] s_apu_master_rflags; //----------------------------------------------------------------------// // Interfaces between ICache - L0 - Icache_Interco and Icache_ctrl_unit // // // -logic s_enable_l1_l15_prefetch; +SP_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_main[Cfg.iCacheNumBanks](); +PRI_ICACHE_CTRL_UNIT_BUS IC_ctrl_unit_bus_pri[Cfg.NumCores]();; +logic [Cfg.NumCores-1:0] s_enable_l1_l15_prefetch; logic [Cfg.NumCores-1:0] s_icache_flush_valid, s_icache_flush_ready; snitch_icache_pkg::icache_l0_events_t [Cfg.NumCores-1:0] s_icache_l0_events; snitch_icache_pkg::icache_l1_events_t s_icache_l1_events; @@ -478,16 +480,6 @@ AXI_BUS #( `AXI_TYPEDEF_ALL(instr_axi, logic[AddrWidth-1:0], logic[AxiIdInWidth-1:0], logic[Cfg.AxiDataOutWidth-1:0], logic[Cfg.AxiDataOutWidth/8-1:0], logic[Cfg.AxiUserWidth-1:0]) -instr_axi_req_t s_core_instr_bus_req; -instr_axi_resp_t s_core_instr_bus_resp; - -always_comb begin - s_core_instr_bus.aw_addr = '0; - s_core_instr_bus.ar_addr = '0; - `AXI_SET_FROM_REQ(s_core_instr_bus, s_core_instr_bus_req) -end -`AXI_ASSIGN_TO_RESP(s_core_instr_bus_resp, s_core_instr_bus) - // ***********************************************************************************************+ // ***********************************************************************************************+ // ***********************************************************************************************+ @@ -830,6 +822,8 @@ cluster_peripherals #( .enable_l1_l15_prefetch_o ( s_enable_l1_l15_prefetch ), .flush_valid_o ( s_icache_flush_valid ), .flush_ready_i ( s_icache_flush_ready ), + .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ), + .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), // .l0_events_i ( s_icache_l0_events ), .l1_events_i ( s_icache_l1_events ) ); @@ -1078,6 +1072,7 @@ hmr_unit #( .InterleaveGrps ( 1 ), .RapidRecovery ( 1 ), .SeparateData ( 1 ), + .SeparateAxiBus ( 0 ), .NumBusVoters ( 1 ), .all_inputs_t ( core_inputs_t ), .nominal_outputs_t ( core_outputs_t ), @@ -1114,7 +1109,8 @@ hmr_unit #( .core_setback_o ( setback ), .core_inputs_o ( hmr2core ), .core_nominal_outputs_i ( core2hmr ), - .core_bus_outputs_i ( '0 ) + .core_bus_outputs_i ( '0 ), + .core_axi_outputs_i ( '0 ) ); //**************************************************** @@ -1244,42 +1240,183 @@ generate end endgenerate -pulp_icache_wrap #( - .NumFetchPorts ( Cfg.NumCores ), - .L0_LINE_COUNT ( Cfg.iCachePrivateSize*8/256 ), - .LINE_WIDTH ( 256 ), // Ideally 32*NumCores - .LINE_COUNT ( Cfg.iCacheSharedSize*8/256/Cfg.iCacheNumWays ), - .SET_COUNT ( Cfg.iCacheNumWays ), - .L1DataParityWidth ( 8 ), - .FetchAddrWidth ( AddrWidth ), - .FetchDataWidth ( Cfg.iCachePrivateDataWidth ), - .AxiAddrWidth ( AddrWidth ), - .AxiDataWidth ( Cfg.AxiDataOutWidth ), - .axi_req_t ( instr_axi_req_t ), - .axi_rsp_t ( instr_axi_resp_t ) -) icache_top_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .fetch_req_i ( instr_req ), - .fetch_addr_i ( instr_addr ), - .fetch_gnt_o ( instr_gnt ), - .fetch_rvalid_o ( instr_r_valid ), - .fetch_rdata_o ( instr_r_rdata ), - .fetch_rerror_o (), - - .enable_prefetching_i ( s_enable_l1_l15_prefetch ), - .icache_l0_events_o ( s_icache_l0_events ), - .icache_l1_events_o ( s_icache_l1_events ), - .flush_valid_i ( s_icache_flush_valid ), - .flush_ready_o ( s_icache_flush_ready ), - - .sram_cfg_data_i ('0), - .sram_cfg_tag_i ('0), - - .axi_req_o ( s_core_instr_bus_req ), - .axi_rsp_i ( s_core_instr_bus_resp ) -); +`ifdef SNITCH_ICACHE + instr_axi_req_t s_core_instr_bus_req; + instr_axi_resp_t s_core_instr_bus_resp; + + always_comb begin + s_core_instr_bus.aw_addr = '0; + s_core_instr_bus.ar_addr = '0; + `AXI_SET_FROM_REQ(s_core_instr_bus, s_core_instr_bus_req) + end + `AXI_ASSIGN_TO_RESP(s_core_instr_bus_resp, s_core_instr_bus) + + pulp_icache_wrap #( + .NumFetchPorts ( Cfg.NumCores ), + .L0_LINE_COUNT ( Cfg.iCachePrivateSize*8/256 ), + .LINE_WIDTH ( 256 ), // Ideally 32*NumCores + .LINE_COUNT ( Cfg.iCacheSharedSize*8/256/Cfg.iCacheNumWays ), + .SET_COUNT ( Cfg.iCacheNumWays ), + .L1DataParityWidth ( 8 ), + .FetchAddrWidth ( AddrWidth ), + .FetchDataWidth ( Cfg.iCachePrivateDataWidth ), + .AxiAddrWidth ( AddrWidth ), + .AxiDataWidth ( Cfg.AxiDataOutWidth ), + .axi_req_t ( instr_axi_req_t ), + .axi_rsp_t ( instr_axi_resp_t ) + ) icache_top_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .fetch_req_i ( instr_req ), + .fetch_addr_i ( instr_addr ), + .fetch_gnt_o ( instr_gnt ), + .fetch_rvalid_o ( instr_r_valid ), + .fetch_rdata_o ( instr_r_rdata ), + .fetch_rerror_o (), + + .enable_prefetching_i ( s_enable_l1_l15_prefetch[0] ), + .icache_l0_events_o ( s_icache_l0_events ), + .icache_l1_events_o ( s_icache_l1_events ), + .flush_valid_i ( s_icache_flush_valid ), + .flush_ready_o ( s_icache_flush_ready ), + + .sram_cfg_data_i ('0), + .sram_cfg_tag_i ('0), + + .axi_req_o ( s_core_instr_bus_req ), + .axi_rsp_i ( s_core_instr_bus_resp ) + ); + + for (genvar i = 0; i < Cfg.NumCores; i++) begin + assign IC_ctrl_unit_bus_pri[i].bypass_ack = '0; + assign IC_ctrl_unit_bus_pri[i].flush_ack = '0; + assign IC_ctrl_unit_bus_pri[i].sel_flush_ack = '0; + `ifdef FEATURE_ICACHE_STAT + assign IC_ctrl_unit_bus_pri[i].ctrl_hit_count = '0; + assign IC_ctrl_unit_bus_pri[i].ctrl_trans_count = '0; + assign IC_ctrl_unit_bus_pri[i].ctrl_miss_count = '0; + assign IC_ctrl_unit_bus_pri[i].ctrl_cong_count = '0; + `endif + end + + for (genvar i = 0; i < Cfg.iCacheNumBanks; i++) begin + assign IC_ctrl_unit_bus_main[i].ctrl_flush_ack = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_ack_enable = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_ack_disable = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_pending_trans = '0; + assign IC_ctrl_unit_bus_main[i].sel_flush_ack = '0; + `ifdef FEATURE_ICACHE_STAT + assign IC_ctrl_unit_bus_main[i].ctrl_hit_count = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_trans_count = '0; + assign IC_ctrl_unit_bus_main[i].ctrl_miss_count = '0; + `endif + end +`else + assign s_icache_flush_ready = '0; + assign s_icache_l0_events = '0; + assign s_icache_l1_events = '0; + + icache_hier_top #( + .FETCH_ADDR_WIDTH ( AddrWidth ), //= 32, + .PRI_FETCH_DATA_WIDTH ( Cfg.iCachePrivateDataWidth ), //= 128, // Tested for 32 and 128 + .SH_FETCH_DATA_WIDTH ( 128 ), //= 128, + + .NB_CORES ( Cfg.NumCores ), //= 8, + + .SH_NB_BANKS ( Cfg.iCacheNumBanks ), //= 1, + .SH_NB_WAYS ( Cfg.iCacheNumWays ), //= 4, + .SH_CACHE_SIZE ( Cfg.iCacheSharedSize), //= 4*1024, // in Byte + .SH_CACHE_LINE ( Cfg.iCacheNumLines ), //= 1, // in word of [SH_FETCH_DATA_WIDTH] + + .PRI_NB_WAYS ( Cfg.iCacheNumWays ), //= 4, + .PRI_CACHE_SIZE ( Cfg.iCachePrivateSize), //= 512, // in Byte + .PRI_CACHE_LINE ( Cfg.iCacheNumLines ), //= 1, // in word of [PRI_FETCH_DATA_WIDTH] + + .AXI_ID ( AxiIdInWidth ), //= 6, + .AXI_ADDR ( Cfg.AxiAddrWidth ), //= 32, + .AXI_USER ( Cfg.AxiUserWidth ), //= 6, + .AXI_DATA ( Cfg.AxiDataOutWidth ), //= 64, + + .USE_REDUCED_TAG ( Cfg.EnableReducedTag ), //= "TRUE", // TRUE | FALSE + .L2_SIZE ( Cfg.L2Size ) //= 512*1024 // Size of max(L2 ,ROM) program memory in Byte + ) icache_top_i ( + .clk ( clk_i ), + .rst_n ( rst_ni ), + .test_en_i ( test_mode_i ), + + .fetch_req_i ( instr_req ), + .fetch_addr_i ( instr_addr ), + .fetch_gnt_o ( instr_gnt ), + + .fetch_rvalid_o ( instr_r_valid ), + .fetch_rdata_o ( instr_r_rdata ), + + .enable_l1_l15_prefetch_i ( s_enable_l1_l15_prefetch ), // set it to 1 to use prefetch feature + + //AXI read address bus ------------------------------------------- + .axi_master_arid_o ( s_core_instr_bus.ar_id ), + .axi_master_araddr_o ( s_core_instr_bus.ar_addr ), + .axi_master_arlen_o ( s_core_instr_bus.ar_len ), //burst length - 1 to 16 + .axi_master_arsize_o ( s_core_instr_bus.ar_size ), //size of each transfer in burst + .axi_master_arburst_o ( s_core_instr_bus.ar_burst ), //accept only incr burst=01 + .axi_master_arlock_o ( s_core_instr_bus.ar_lock ), //only normal access supported axs_awlock=00 + .axi_master_arcache_o ( s_core_instr_bus.ar_cache ), + .axi_master_arprot_o ( s_core_instr_bus.ar_prot ), + .axi_master_arregion_o ( s_core_instr_bus.ar_region ), // + .axi_master_aruser_o ( s_core_instr_bus.ar_user ), // + .axi_master_arqos_o ( s_core_instr_bus.ar_qos ), // + .axi_master_arvalid_o ( s_core_instr_bus.ar_valid ), //master addr valid + .axi_master_arready_i ( s_core_instr_bus.ar_ready ), //slave ready to accept + // --------------------------------------------------------------- + + //AXI BACKWARD read data bus ---------------------------------------------- + .axi_master_rid_i ( s_core_instr_bus.r_id ), + .axi_master_rdata_i ( s_core_instr_bus.r_data ), + .axi_master_rresp_i ( s_core_instr_bus.r_resp ), + .axi_master_rlast_i ( s_core_instr_bus.r_last ), //last transfer in burst + .axi_master_ruser_i ( s_core_instr_bus.r_user ), + .axi_master_rvalid_i ( s_core_instr_bus.r_valid ), //slave data valid + .axi_master_rready_o ( s_core_instr_bus.r_ready ), //master ready to accept + + // NOT USED ---------------------------------------------- + .axi_master_awid_o ( s_core_instr_bus.aw_id ), + .axi_master_awaddr_o ( s_core_instr_bus.aw_addr ), + .axi_master_awlen_o ( s_core_instr_bus.aw_len ), + .axi_master_awsize_o ( s_core_instr_bus.aw_size ), + .axi_master_awburst_o ( s_core_instr_bus.aw_burst ), + .axi_master_awlock_o ( s_core_instr_bus.aw_lock ), + .axi_master_awcache_o ( s_core_instr_bus.aw_cache ), + .axi_master_awprot_o ( s_core_instr_bus.aw_prot ), + .axi_master_awregion_o ( s_core_instr_bus.aw_region ), + .axi_master_awuser_o ( s_core_instr_bus.aw_user ), + .axi_master_awqos_o ( s_core_instr_bus.aw_qos ), + .axi_master_awvalid_o ( s_core_instr_bus.aw_valid ), + .axi_master_awready_i ( s_core_instr_bus.aw_ready ), + + // NOT USED ---------------------------------------------- + .axi_master_wdata_o ( s_core_instr_bus.w_data ), + .axi_master_wstrb_o ( s_core_instr_bus.w_strb ), + .axi_master_wlast_o ( s_core_instr_bus.w_last ), + .axi_master_wuser_o ( s_core_instr_bus.w_user ), + .axi_master_wvalid_o ( s_core_instr_bus.w_valid ), + .axi_master_wready_i ( s_core_instr_bus.w_ready ), + // --------------------------------------------------------------- + + // NOT USED ---------------------------------------------- + .axi_master_bid_i ( s_core_instr_bus.b_id ), + .axi_master_bresp_i ( s_core_instr_bus.b_resp ), + .axi_master_buser_i ( s_core_instr_bus.b_user ), + .axi_master_bvalid_i ( s_core_instr_bus.b_valid ), + .axi_master_bready_o ( s_core_instr_bus.b_ready ), + // --------------------------------------------------------------- + + .IC_ctrl_unit_bus_pri ( IC_ctrl_unit_bus_pri ), + .IC_ctrl_unit_bus_main ( IC_ctrl_unit_bus_main ) + ); + + assign s_core_instr_bus.aw_atop = '0; +`endif `REG_BUS_TYPEDEF_ALL(tcdm_scrubber_reg, logic[AddrWidth-1:0], logic[DataWidth-1:0], logic[BeWidth-1:0]) diff --git a/rtl/tcdm_banks_wrap.sv b/rtl/tcdm_banks_wrap.sv index e3f2fba..4bfe654 100644 --- a/rtl/tcdm_banks_wrap.sv +++ b/rtl/tcdm_banks_wrap.sv @@ -71,35 +71,29 @@ for(genvar i=0; i