From 7f064f205a3e0203e959b14773c4afecf56681ab Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Thu, 11 May 2023 19:22:16 +0200 Subject: [PATCH] Fixing parametrization. --- rtl/ctrl_unit/ctrl_fsm.sv | 2 +- rtl/ext_unit/ext_rx_if.sv | 6 +++++- rtl/ext_unit/ext_tx_if.sv | 6 +++++- rtl/ext_unit/ext_unit.sv | 11 +++++++++-- 4 files changed, 20 insertions(+), 5 deletions(-) diff --git a/rtl/ctrl_unit/ctrl_fsm.sv b/rtl/ctrl_unit/ctrl_fsm.sv index 54a0d73..db2f83b 100755 --- a/rtl/ctrl_unit/ctrl_fsm.sv +++ b/rtl/ctrl_unit/ctrl_fsm.sv @@ -1025,7 +1025,7 @@ module ctrl_fsm assign cmd_sid_o = s_trans_sid; assign tcdm_add_o = ctrl_targ_data_i[TCDM_ADD_WIDTH-1:0]; - assign ext_add_o = ctrl_targ_data_i[EXT_ADD_WIDTH-1:0]; + assign ext_add_o = {{(EXT_ADD_WIDTH-32){1'b0}}, ctrl_targ_data_i}; assign twd_ext_queue_count_o = s_twd_ext_count[TWD_COUNT_WIDTH:0]-1; assign twd_ext_queue_stride_o = ctrl_targ_data_i[TWD_STRIDE_WIDTH:0]-1; diff --git a/rtl/ext_unit/ext_rx_if.sv b/rtl/ext_unit/ext_rx_if.sv index 31e671e..849bdd7 100755 --- a/rtl/ext_unit/ext_rx_if.sv +++ b/rtl/ext_unit/ext_rx_if.sv @@ -83,6 +83,10 @@ module ext_rx_if output logic axi_master_r_ready_o ); + + localparam int unsigned ID_WIDTH_DIFF = (AXI_ID_WIDTH > EXT_TID_WIDTH) ? + (AXI_ID_WIDTH - EXT_TID_WIDTH) : + (EXT_TID_WIDTH - AXI_ID_WIDTH) ; enum `ifdef SYNTHESIS logic [1:0] `endif { TRANS_IDLE, TRANS_STALLED, TRANS_RUN } CS, NS; logic [AXI_ID_WIDTH+4-1:0] s_axi_master_ar_id; @@ -246,6 +250,6 @@ module ext_rx_if assign axi_master_ar_id_o = s_axi_master_ar_id[AXI_ID_WIDTH-1:0]; assign rx_data_dat_o = axi_master_r_data_i; - assign res_tid_o = axi_master_r_id_i[EXT_TID_WIDTH-1:0]; + assign res_tid_o = {{ID_WIDTH_DIFF{1'b0}}, axi_master_r_id_i}; endmodule diff --git a/rtl/ext_unit/ext_tx_if.sv b/rtl/ext_unit/ext_tx_if.sv index 642c113..7560f05 100755 --- a/rtl/ext_unit/ext_tx_if.sv +++ b/rtl/ext_unit/ext_tx_if.sv @@ -84,6 +84,10 @@ module ext_tx_if output logic axi_master_b_ready_o ); + + localparam int unsigned ID_WIDTH_DIFF = (AXI_ID_WIDTH > EXT_TID_WIDTH) ? + (AXI_ID_WIDTH - EXT_TID_WIDTH) : + (EXT_TID_WIDTH - AXI_ID_WIDTH) ; // FSM STATES SIGNALS enum `ifdef SYNTHESIS logic [1:0] `endif { TRANS_IDLE, TRANS_ACK, TRANS_RUN } CS, NS; @@ -304,7 +308,7 @@ module ext_tx_if assign axi_master_b_ready_o = 1'b1; assign release_tid_o = axi_master_b_valid_i; - assign res_tid_o = axi_master_b_id_i[EXT_TID_WIDTH-1:0]; + assign res_tid_o = {{ID_WIDTH_DIFF{1'b0}}, axi_master_b_id_i}; assign synch_req_o = release_tid_o; diff --git a/rtl/ext_unit/ext_unit.sv b/rtl/ext_unit/ext_unit.sv index 6fd9116..6db2603 100755 --- a/rtl/ext_unit/ext_unit.sv +++ b/rtl/ext_unit/ext_unit.sv @@ -215,6 +215,13 @@ module ext_unit //********************************************************** //*************** TX COMMAND QUEUE ************************* //********************************************************** + localparam int unsigned ID_WIDTH_DIFF = (AXI_ID_WIDTH > EXT_TID_WIDTH) ? + (AXI_ID_WIDTH - EXT_TID_WIDTH) : + (EXT_TID_WIDTH - AXI_ID_WIDTH) ; + + logic [EXT_TID_WIDTH-1:0] s_r_ext_id, s_b_ext_id; + assign s_r_ext_id = {{ID_WIDTH_DIFF{1'b0}}, s_r_id}; + assign s_b_ext_id = {{ID_WIDTH_DIFF{1'b0}}, s_b_id}; generic_fifo #( @@ -480,7 +487,7 @@ module ext_unit .r_add_i(s_rx_r_add), .sid_i(s_rx_sid), - .r_tid_i(s_r_id[EXT_TID_WIDTH-1:0]), + .r_tid_i(s_r_ext_id), .tcdm_opc_o(tcdm_rx_opc_o), .tcdm_len_o(tcdm_rx_len_o), @@ -517,7 +524,7 @@ module ext_unit .r_add_i('0), .sid_i(s_tx_sid), - .r_tid_i(s_b_id[EXT_TID_WIDTH-1:0]), + .r_tid_i(s_b_ext_id), .tcdm_opc_o(), .tcdm_len_o(),