-
Notifications
You must be signed in to change notification settings - Fork 272
/
axi_demux.sv
302 lines (281 loc) · 10.8 KB
/
axi_demux.sv
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
// Copyright (c) 2019 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Authors:
// - Michael Rogenmoser <michaero@iis.ee.ethz.ch>
// - Wolfgang Roenninger <wroennin@iis.ee.ethz.ch>
// - Thomas Benz <tbenz@iis.ee.ethz.ch>
// - Andreas Kurth <akurth@iis.ee.ethz.ch>
`include "common_cells/assertions.svh"
`include "common_cells/registers.svh"
`ifdef QUESTA
// Derive `TARGET_VSIM`, which is used for tool-specific workarounds in this file, from `QUESTA`,
// which is automatically set in Questa.
`define TARGET_VSIM
`endif
/// Demultiplex one AXI4+ATOP slave port to multiple AXI4+ATOP master ports.
///
/// The AW and AR slave channels each have a `select` input to determine to which master port the
/// current request is sent. The `select` can, for example, be driven by an address decoding module
/// to map address ranges to different AXI slaves.
///
/// ## Design overview
///
/// 
///
/// Beats on the W channel are routed by demultiplexer according to the selection for the
/// corresponding AW beat. This relies on the AXI property that W bursts must be sent in the same
/// order as AW beats and beats from different W bursts may not be interleaved.
///
/// Beats on the B and R channel are multiplexed from the master ports to the slave port with
/// a round-robin arbitration tree.
module axi_demux #(
parameter int unsigned AxiIdWidth = 32'd0,
parameter bit AtopSupport = 1'b1,
parameter type aw_chan_t = logic,
parameter type w_chan_t = logic,
parameter type b_chan_t = logic,
parameter type ar_chan_t = logic,
parameter type r_chan_t = logic,
parameter type axi_req_t = logic,
parameter type axi_resp_t = logic,
parameter int unsigned NoMstPorts = 32'd0,
parameter int unsigned MaxTrans = 32'd8,
parameter int unsigned AxiLookBits = 32'd3,
parameter bit UniqueIds = 1'b0,
parameter bit SpillAw = 1'b1,
parameter bit SpillW = 1'b0,
parameter bit SpillB = 1'b0,
parameter bit SpillAr = 1'b1,
parameter bit SpillR = 1'b0,
// Dependent parameters, DO NOT OVERRIDE!
parameter int unsigned SelectWidth = (NoMstPorts > 32'd1) ? $clog2(NoMstPorts) : 32'd1,
parameter type select_t = logic [SelectWidth-1:0]
) (
input logic clk_i,
input logic rst_ni,
input logic test_i,
// Slave Port
input axi_req_t slv_req_i,
input select_t slv_aw_select_i,
input select_t slv_ar_select_i,
output axi_resp_t slv_resp_o,
// Master Ports
output axi_req_t [NoMstPorts-1:0] mst_reqs_o,
input axi_resp_t [NoMstPorts-1:0] mst_resps_i
);
axi_req_t slv_req_cut;
axi_resp_t slv_resp_cut;
logic slv_aw_ready_chan, slv_aw_ready_sel;
logic slv_aw_valid_chan, slv_aw_valid_sel;
logic slv_ar_ready_chan, slv_ar_ready_sel;
logic slv_ar_valid_chan, slv_ar_valid_sel;
select_t slv_aw_select, slv_ar_select;
spill_register #(
.T ( aw_chan_t ),
.Bypass ( ~SpillAw )
) i_aw_spill_reg (
.clk_i,
.rst_ni,
.valid_i ( slv_req_i.aw_valid ),
.ready_o ( slv_aw_ready_chan ),
.data_i ( slv_req_i.aw ),
.valid_o ( slv_aw_valid_chan ),
.ready_i ( slv_resp_cut.aw_ready ),
.data_o ( slv_req_cut.aw )
);
spill_register #(
.T ( select_t ),
.Bypass ( ~SpillAw )
) i_aw_select_spill_reg (
.clk_i,
.rst_ni,
.valid_i ( slv_req_i.aw_valid ),
.ready_o ( slv_aw_ready_sel ),
.data_i ( slv_aw_select_i ),
.valid_o ( slv_aw_valid_sel ),
.ready_i ( slv_resp_cut.aw_ready ),
.data_o ( slv_aw_select )
);
assign slv_resp_o.aw_ready = slv_aw_ready_chan & slv_aw_ready_sel;
assign slv_req_cut.aw_valid = slv_aw_valid_chan & slv_aw_valid_sel;
spill_register #(
.T ( w_chan_t ),
.Bypass ( ~SpillW )
) i_w_spill_reg (
.clk_i,
.rst_ni,
.valid_i ( slv_req_i.w_valid ),
.ready_o ( slv_resp_o.w_ready ),
.data_i ( slv_req_i.w ),
.valid_o ( slv_req_cut.w_valid ),
.ready_i ( slv_resp_cut.w_ready ),
.data_o ( slv_req_cut.w )
);
spill_register #(
.T ( ar_chan_t ),
.Bypass ( ~SpillAr )
) i_ar_spill_reg (
.clk_i,
.rst_ni,
.valid_i ( slv_req_i.ar_valid ),
.ready_o ( slv_ar_ready_chan ),
.data_i ( slv_req_i.ar ),
.valid_o ( slv_ar_valid_chan ),
.ready_i ( slv_resp_cut.ar_ready ),
.data_o ( slv_req_cut.ar )
);
spill_register #(
.T ( select_t ),
.Bypass ( ~SpillAr )
) i_ar_sel_spill_reg (
.clk_i,
.rst_ni,
.valid_i ( slv_req_i.ar_valid ),
.ready_o ( slv_ar_ready_sel ),
.data_i ( slv_ar_select_i ),
.valid_o ( slv_ar_valid_sel ),
.ready_i ( slv_resp_cut.ar_ready ),
.data_o ( slv_ar_select )
);
assign slv_resp_o.ar_ready = slv_ar_ready_chan & slv_ar_ready_sel;
assign slv_req_cut.ar_valid = slv_ar_valid_chan & slv_ar_valid_sel;
spill_register #(
.T ( b_chan_t ),
.Bypass ( ~SpillB )
) i_b_spill_reg (
.clk_i,
.rst_ni,
.valid_i ( slv_resp_cut.b_valid ),
.ready_o ( slv_req_cut.b_ready ),
.data_i ( slv_resp_cut.b ),
.valid_o ( slv_resp_o.b_valid ),
.ready_i ( slv_req_i.b_ready ),
.data_o ( slv_resp_o.b )
);
spill_register #(
.T ( r_chan_t ),
.Bypass ( ~SpillR )
) i_r_spill_reg (
.clk_i,
.rst_ni,
.valid_i ( slv_resp_cut.r_valid ),
.ready_o ( slv_req_cut.r_ready ),
.data_i ( slv_resp_cut.r ),
.valid_o ( slv_resp_o.r_valid ),
.ready_i ( slv_req_i.r_ready ),
.data_o ( slv_resp_o.r )
);
axi_demux_simple #(
.AxiIdWidth ( AxiIdWidth ),
.AtopSupport( AtopSupport ),
.axi_req_t ( axi_req_t ),
.axi_resp_t ( axi_resp_t ),
.NoMstPorts ( NoMstPorts ),
.MaxTrans ( MaxTrans ),
.AxiLookBits( AxiLookBits ),
.UniqueIds ( UniqueIds )
) i_demux_simple (
.clk_i,
.rst_ni,
.test_i,
.slv_req_i ( slv_req_cut ),
.slv_aw_select_i ( slv_aw_select ),
.slv_ar_select_i ( slv_ar_select ),
.slv_resp_o ( slv_resp_cut ),
.mst_reqs_o ( mst_reqs_o ),
.mst_resps_i ( mst_resps_i )
);
endmodule
// interface wrapper
`include "axi/assign.svh"
`include "axi/typedef.svh"
module axi_demux_intf #(
parameter int unsigned AXI_ID_WIDTH = 32'd0, // Synopsys DC requires default value for params
parameter bit ATOP_SUPPORT = 1'b1,
parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
parameter int unsigned AXI_DATA_WIDTH = 32'd0,
parameter int unsigned AXI_USER_WIDTH = 32'd0,
parameter int unsigned NO_MST_PORTS = 32'd3,
parameter int unsigned MAX_TRANS = 32'd8,
parameter int unsigned AXI_LOOK_BITS = 32'd3,
parameter bit UNIQUE_IDS = 1'b0,
parameter bit SPILL_AW = 1'b1,
parameter bit SPILL_W = 1'b0,
parameter bit SPILL_B = 1'b0,
parameter bit SPILL_AR = 1'b1,
parameter bit SPILL_R = 1'b0,
// Dependent parameters, DO NOT OVERRIDE!
parameter int unsigned SELECT_WIDTH = (NO_MST_PORTS > 32'd1) ? $clog2(NO_MST_PORTS) : 32'd1,
parameter type select_t = logic [SELECT_WIDTH-1:0] // MST port select type
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic test_i, // Testmode enable
input select_t slv_aw_select_i, // has to be stable, when aw_valid
input select_t slv_ar_select_i, // has to be stable, when ar_valid
AXI_BUS.Slave slv, // slave port
AXI_BUS.Master mst [NO_MST_PORTS-1:0] // master ports
);
typedef logic [AXI_ID_WIDTH-1:0] id_t;
typedef logic [AXI_ADDR_WIDTH-1:0] addr_t;
typedef logic [AXI_DATA_WIDTH-1:0] data_t;
typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
typedef logic [AXI_USER_WIDTH-1:0] user_t;
`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
`AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
axi_req_t slv_req;
axi_resp_t slv_resp;
axi_req_t [NO_MST_PORTS-1:0] mst_req;
axi_resp_t [NO_MST_PORTS-1:0] mst_resp;
`AXI_ASSIGN_TO_REQ(slv_req, slv)
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)
for (genvar i = 0; i < NO_MST_PORTS; i++) begin : gen_assign_mst_ports
`AXI_ASSIGN_FROM_REQ(mst[i], mst_req[i])
`AXI_ASSIGN_TO_RESP(mst_resp[i], mst[i])
end
axi_demux #(
.AxiIdWidth ( AXI_ID_WIDTH ), // ID Width
.AtopSupport ( ATOP_SUPPORT ),
.aw_chan_t ( aw_chan_t ), // AW Channel Type
.w_chan_t ( w_chan_t ), // W Channel Type
.b_chan_t ( b_chan_t ), // B Channel Type
.ar_chan_t ( ar_chan_t ), // AR Channel Type
.r_chan_t ( r_chan_t ), // R Channel Type
.axi_req_t ( axi_req_t ),
.axi_resp_t ( axi_resp_t ),
.NoMstPorts ( NO_MST_PORTS ),
.MaxTrans ( MAX_TRANS ),
.AxiLookBits ( AXI_LOOK_BITS ),
.UniqueIds ( UNIQUE_IDS ),
.SpillAw ( SPILL_AW ),
.SpillW ( SPILL_W ),
.SpillB ( SPILL_B ),
.SpillAr ( SPILL_AR ),
.SpillR ( SPILL_R )
) i_axi_demux (
.clk_i, // Clock
.rst_ni, // Asynchronous reset active low
.test_i, // Testmode enable
// slave port
.slv_req_i ( slv_req ),
.slv_aw_select_i ( slv_aw_select_i ),
.slv_ar_select_i ( slv_ar_select_i ),
.slv_resp_o ( slv_resp ),
// master port
.mst_reqs_o ( mst_req ),
.mst_resps_i ( mst_resp )
);
endmodule