From 18764fbef1f1f90bc696fe35d059685b2b37f149 Mon Sep 17 00:00:00 2001
From: "Barbieri, Kealan" <kealan.barbieri@intel.com>
Date: Tue, 20 Sep 2022 16:44:38 -0700
Subject: [PATCH] src: gpu: jit: conv: allow non-trivial m dim tg for int8

---
 src/gpu/jit/conv/config.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gpu/jit/conv/config.cpp b/src/gpu/jit/conv/config.cpp
index 7a0a2aac36a..6ef86f0338f 100644
--- a/src/gpu/jit/conv/config.cpp
+++ b/src/gpu/jit/conv/config.cpp
@@ -177,7 +177,8 @@ status_t conv_config_t::init_fwd(convolution_pd_t *conv_pd) {
         if (is_dw) bh->set_pref_tg_block(osp_name);
         bh->allow_split({osp_name, "mb"});
         bh->reorder({osp_name, "mb"});
-        if (!fuse_spatial && mb < 16 && iw % 8 != 0 && !is_dw) {
+        if (!is_int8_dst() && !fuse_spatial && mb < 16 && iw % 8 != 0
+                && !is_dw) {
             bh->set_max_m_tg_dim(1);
         }
     } else {