Add language support for VHDL

[BHatGuy]

Adds support for VHDL (#490). Sadly VHDL has no official logo, so I just used the name.

[spenserblack]

Thank you! Very nice 3D effect with the ASCII.

Sadly VHDL has no official logo

It's definitely hard to make an ASCII logo with no official logo for reference 😢
How did you decide on green for the color? What do you think about making the letters different colors to make the ASCII more eye-catching?

[o2sh]

What about using a micro chip as an illustration? similarly to what we did for SQL and Fortran:

        |  |  |  |
       ------------
    --|    ----    |--
    --|   |    |   |--
    --|   |    |   |--
    --|    ----    |--
       ------------
        |  |  |  |

__     ___   _ ____  _
\ \   / / | | |  _ \| |
 \ \ / /| |_| | | | | |
  \ V / |  _  | |_| | |___
   \_/  |_| |_|____/|_____|

[BHatGuy]

Yes, this looks nice

[spenserblack]

Could you resolve the conflict? #630 introduced a new field when defining language support.

[spenserblack]

Thank you!

Just curious: how did you decide on the colors Cyan and Yellow?

[BHatGuy]

I don't really know. I think it looks nice

[spenserblack]

I think it looks nice

Agreed 🙂

Although I wonder if green and yellow would better represent a microchip. @o2sh What do you think?

[o2sh]

Option 1:

Option 2 (as suggested by @spenserblack):

I personally lean toward Option 2 🤔

Code for Option 2:

{0}         |  |  |  |
{0}        {1}------------
{0}     --{1}|    {2}----    {1}|{0}--
{0}     --{1}|   {2}|    |   {1}|{0}--
{0}     --{1}|   {2}|    |   {1}|{0}--
{0}     --{1}|    {2}----    {1}|{0}--
{0}        {1}------------
{0}         |  |  |  |

{2} __     ___   _ ____  _
{2} \ \   / / | | |  _ \| |
{2}  \ \ / /| |_| | | | | |
{2}   \ V / |  _  | |_| | |___
{2}    \_/  |_| |_|____/|_____|

{ Vhdl, Programming, "vhdl.ascii", define_colors!([Yellow, Green, White]), Rgb(173, 178, 203) },