From d2903a38678dcd985c04e7eca3be60292c346ac6 Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 16:40:48 -0500 Subject: [PATCH 01/80] fixing the parsing and constraint generation for sbtype instructions --- .../src/interpreters/riscv32im/interpreter.rs | 65 ++++++++++++++----- 1 file changed, 50 insertions(+), 15 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 3ae830de49..04d50853f2 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2066,9 +2066,11 @@ pub fn interpret_stype(env: &mut Env, instr: SInstruction) /// Following the documentation found /// [here](https://www.cs.cornell.edu/courses/cs3410/2024fa/assignments/cpusim/riscv-instructions.pdf) pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction) { + /* fetch instruction pointer from the program state */ let instruction_pointer = env.get_instruction_pointer(); + /* compute the next instruction ptr and add one, as well record raml lookup */ let _next_instruction_pointer = env.get_next_instruction_pointer(); - + /* read instruction from ip address */ let instruction = { let v0 = env.read_memory(&instruction_pointer); let v1 = env.read_memory(&(instruction_pointer.clone() + Env::constant(1))); @@ -2079,20 +2081,15 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction + (v1 * Env::constant(1 << 8)) + v0 }; + /* fetch opcode from instruction bit 0 - 6 for a total len of 7 */ let opcode = { let pos = env.alloc_scratch(); unsafe { env.bitmask(&instruction, 7, 0, pos) } }; + /* verify opcode is 7 bits */ env.range_check8(&opcode, 7); - // FIXME: trickier - let imm1 = { - let pos = env.alloc_scratch(); - unsafe { env.bitmask(&instruction, 12, 7, pos) } - }; - env.range_check8(&imm1, 5); - let funct3 = { let pos = env.alloc_scratch(); unsafe { env.bitmask(&instruction, 15, 12, pos) } @@ -2111,14 +2108,52 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction }; env.range_check8(&rs2, 5); - // FIXME: trickier - let imm2 = { - let pos = env.alloc_scratch(); - unsafe { env.bitmask(&instruction, 32, 25, pos) } - }; - env.range_check16(&imm2, 12); + let imm0_12 = { + let imm11 = { + let pos = env.alloc_scratch(); + unsafe { env.bitmask(&instruction, 8, 7, pos) } + }; - // FIXME: check correctness of decomposition + env.range_check8(&imm11, 1); + + let imm1_4 = { + let pos = env.alloc_scratch(); + unsafe { env.bitmask(&instruction, 12, 8, pos) } + }; + env.range_check8(&imm1_4, 4); + + let imm5_10 = { + let pos = env.alloc_scratch(); + unsafe { env.bitmask(&instruction, 31, 25, pos) } + }; + env.range_check8(&imm5_10, 6); + + let imm12 = { + let pos = env.alloc_scratch(); + unsafe { env.bitmask(&instruction, 32, 31, pos) } + }; + env.range_check8(&imm12, 1); + + // check correctness of decomposition of SB type function + env.add_constraint( + instruction.clone() + - (opcode * Env::constant(1 << 0)) // opcode at bits 0-7 + - (imm11.clone() * Env::constant(1 << 7)) // imm11 at bits 8 + - (imm1_4.clone() * Env::constant(1 << 8)) // imm1_4 at bits 9-11 + - (funct3 * Env::constant(1 << 11)) // funct3 at bits 11-14 + - (rs1 * Env::constant(1 << 14)) // rs1 at bits 15-20 + - (rs2 * Env::constant(1 << 19)) // rs2 at bits 20-24 + - (imm5_10.clone() * Env::constant(1 << 24)) // imm5_10 at bits 25-30 + - (imm12.clone() * Env::constant(1 << 31)), // imm12 at bits 31 + ); + + (imm12 * Env::constant(1 << 12)) + + (imm11 * Env::constant(1 << 11)) + + (imm5_10 * Env::constant(1 << 5)) + + (imm1_4 * Env::constant(1 << 1)) + }; + // extra bit is because the 0th bit in the immediate is always 0 i.e you cannot jump to an odd address + let _imm0_12 = env.sign_extend(&imm0_12, 13); match instr { SBInstruction::BranchEq => { From 1e6efe5abce3cc03028332838a4050c5b2f88147 Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 16:50:05 -0500 Subject: [PATCH 02/80] implementation for branch not equal instruction --- .../src/interpreters/riscv32im/interpreter.rs | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 04d50853f2..462ded8981 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2141,8 +2141,8 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction - (imm11.clone() * Env::constant(1 << 7)) // imm11 at bits 8 - (imm1_4.clone() * Env::constant(1 << 8)) // imm1_4 at bits 9-11 - (funct3 * Env::constant(1 << 11)) // funct3 at bits 11-14 - - (rs1 * Env::constant(1 << 14)) // rs1 at bits 15-20 - - (rs2 * Env::constant(1 << 19)) // rs2 at bits 20-24 + - (rs1.clone() * Env::constant(1 << 14)) // rs1 at bits 15-20 + - (rs2.clone() * Env::constant(1 << 19)) // rs2 at bits 20-24 - (imm5_10.clone() * Env::constant(1 << 24)) // imm5_10 at bits 25-30 - (imm12.clone() * Env::constant(1 << 31)), // imm12 at bits 31 ); @@ -2153,14 +2153,35 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction + (imm1_4 * Env::constant(1 << 1)) }; // extra bit is because the 0th bit in the immediate is always 0 i.e you cannot jump to an odd address - let _imm0_12 = env.sign_extend(&imm0_12, 13); + let imm0_12 = env.sign_extend(&imm0_12, 13); match instr { SBInstruction::BranchEq => { unimplemented!("BranchEq") } SBInstruction::BranchNeq => { - unimplemented!("BranchNeq") + // bne: if (x[rs1] != x[rs2]) pc += sext(offset) + let local_rs1 = env.read_register(&rs1); + let local_rs2 = env.read_register(&rs2); + + let equals = env.equal(&local_rs1, &local_rs2); + let offset = equals.clone() * Env::constant(4) + (Env::constant(1) - equals) * imm0_12; + let addr = { + let res_scratch = env.alloc_scratch(); + let overflow_scratch = env.alloc_scratch(); + let (res, _overflow) = unsafe { + env.add_witness( + &next_instruction_pointer, + &offset, + res_scratch, + overflow_scratch, + ) + }; + // FIXME: Requires a range check + res + }; + env.set_instruction_pointer(next_instruction_pointer); + env.set_next_instruction_pointer(addr); } SBInstruction::BranchLessThan => { unimplemented!("BranchLessThan") From 6393f638266f621ba173918c38e07598076b5538 Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 16:52:03 -0500 Subject: [PATCH 03/80] branch equal instruction implementation --- .../src/interpreters/riscv32im/interpreter.rs | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 462ded8981..904dbf67c9 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2069,7 +2069,7 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction /* fetch instruction pointer from the program state */ let instruction_pointer = env.get_instruction_pointer(); /* compute the next instruction ptr and add one, as well record raml lookup */ - let _next_instruction_pointer = env.get_next_instruction_pointer(); + let next_instruction_pointer = env.get_next_instruction_pointer(); /* read instruction from ip address */ let instruction = { let v0 = env.read_memory(&instruction_pointer); @@ -2157,7 +2157,29 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction match instr { SBInstruction::BranchEq => { - unimplemented!("BranchEq") + // beq: if (x[rs1] == x[rs2]) pc += sext(offset) + let local_rs1 = env.read_register(&rs1); + let local_rs2 = env.read_register(&rs2); + + let equals = env.equal(&local_rs1, &local_rs2); + let offset = (Env::constant(1) - equals.clone()) * Env::constant(4) + equals * imm0_12; + let offset = env.sign_extend(&offset, 12); + let addr = { + let res_scratch = env.alloc_scratch(); + let overflow_scratch = env.alloc_scratch(); + let (res, _overflow) = unsafe { + env.add_witness( + &next_instruction_pointer, + &offset, + res_scratch, + overflow_scratch, + ) + }; + // FIXME: Requires a range check + res + }; + env.set_instruction_pointer(next_instruction_pointer); + env.set_next_instruction_pointer(addr); } SBInstruction::BranchNeq => { // bne: if (x[rs1] != x[rs2]) pc += sext(offset) From 4ff26e35bf28a36294f9d23f2debcc1a4a6b75f3 Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 16:55:52 -0500 Subject: [PATCH 04/80] adding instruction for branch lt --- .../src/interpreters/riscv32im/interpreter.rs | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 904dbf67c9..319bc73fc1 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2206,7 +2206,33 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction env.set_next_instruction_pointer(addr); } SBInstruction::BranchLessThan => { - unimplemented!("BranchLessThan") + // blt: if (x[rs1] < x[rs2]) pc += sext(offset) + let local_rs1 = env.read_register(&rs1); + let local_rs2 = env.read_register(&rs2); + + let rd_scratch = env.alloc_scratch(); + + let less_than = + unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) }; + let offset = (less_than.clone()) * imm0_12 + + (Env::constant(1) - less_than.clone()) * Env::constant(4); + + let addr = { + let res_scratch = env.alloc_scratch(); + let overflow_scratch = env.alloc_scratch(); + let (res, _overflow) = unsafe { + env.add_witness( + &next_instruction_pointer, + &offset, + res_scratch, + overflow_scratch, + ) + }; + // FIXME: Requires a range check + res + }; + env.set_instruction_pointer(next_instruction_pointer); + env.set_next_instruction_pointer(addr); } SBInstruction::BranchGreaterThanEqual => { unimplemented!("BranchGreaterThanEqual") From 7d07938f122e5ff449ffc0600298f832d077a993 Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 16:56:13 -0500 Subject: [PATCH 05/80] lint and format --- .../src/interpreters/riscv32im/interpreter.rs | 54 +++++++++---------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 319bc73fc1..88aa412f97 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2206,33 +2206,33 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction env.set_next_instruction_pointer(addr); } SBInstruction::BranchLessThan => { - // blt: if (x[rs1] < x[rs2]) pc += sext(offset) - let local_rs1 = env.read_register(&rs1); - let local_rs2 = env.read_register(&rs2); - - let rd_scratch = env.alloc_scratch(); - - let less_than = - unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) }; - let offset = (less_than.clone()) * imm0_12 - + (Env::constant(1) - less_than.clone()) * Env::constant(4); - - let addr = { - let res_scratch = env.alloc_scratch(); - let overflow_scratch = env.alloc_scratch(); - let (res, _overflow) = unsafe { - env.add_witness( - &next_instruction_pointer, - &offset, - res_scratch, - overflow_scratch, - ) - }; - // FIXME: Requires a range check - res - }; - env.set_instruction_pointer(next_instruction_pointer); - env.set_next_instruction_pointer(addr); + // blt: if (x[rs1] < x[rs2]) pc += sext(offset) + let local_rs1 = env.read_register(&rs1); + let local_rs2 = env.read_register(&rs2); + + let rd_scratch = env.alloc_scratch(); + + let less_than = + unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) }; + let offset = (less_than.clone()) * imm0_12 + + (Env::constant(1) - less_than.clone()) * Env::constant(4); + + let addr = { + let res_scratch = env.alloc_scratch(); + let overflow_scratch = env.alloc_scratch(); + let (res, _overflow) = unsafe { + env.add_witness( + &next_instruction_pointer, + &offset, + res_scratch, + overflow_scratch, + ) + }; + // FIXME: Requires a range check + res + }; + env.set_instruction_pointer(next_instruction_pointer); + env.set_next_instruction_pointer(addr); } SBInstruction::BranchGreaterThanEqual => { unimplemented!("BranchGreaterThanEqual") From 16f66ac9a1b0bc182ac9831f820d8498df32081c Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 17:00:07 -0500 Subject: [PATCH 06/80] implementation for branch greater than or equal --- .../src/interpreters/riscv32im/interpreter.rs | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 88aa412f97..a16cc82418 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2235,7 +2235,34 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction env.set_next_instruction_pointer(addr); } SBInstruction::BranchGreaterThanEqual => { - unimplemented!("BranchGreaterThanEqual") + // bge: if (x[rs1] >= x[rs2]) pc += sext(offset) + let local_rs1 = env.read_register(&rs1); + let local_rs2 = env.read_register(&rs2); + + let rd_scratch = env.alloc_scratch(); + + let less_than = + unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) }; + + let offset = + less_than.clone() * Env::constant(4) + (Env::constant(1) - less_than) * imm0_12; + // greater than equal is the negation of less than + let addr = { + let res_scratch = env.alloc_scratch(); + let overflow_scratch = env.alloc_scratch(); + let (res, _overflow) = unsafe { + env.add_witness( + &next_instruction_pointer, + &offset, + res_scratch, + overflow_scratch, + ) + }; + // FIXME: Requires a range check + res + }; + env.set_instruction_pointer(next_instruction_pointer); + env.set_next_instruction_pointer(addr); } SBInstruction::BranchLessThanUnsigned => { unimplemented!("BranchLessThanUnsigned") From 2c71aa2583a27da88c78cb202346c70693ec0c6f Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 17:03:33 -0500 Subject: [PATCH 07/80] branch less than unsigned --- .../src/interpreters/riscv32im/interpreter.rs | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index a16cc82418..0f87fc448e 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2265,7 +2265,28 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction env.set_next_instruction_pointer(addr); } SBInstruction::BranchLessThanUnsigned => { - unimplemented!("BranchLessThanUnsigned") + // bltu: if (x[rs1] { unimplemented!("BranchGreaterThanEqualUnsigned") From c281b7eee2d6ee1bf62230e0affe47bb8c7b365b Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 17:30:17 -0500 Subject: [PATCH 08/80] fixing unused variable naming to fix CI --- o1vm/src/interpreters/riscv32im/interpreter.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 462ded8981..b379c5b290 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2069,7 +2069,7 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction /* fetch instruction pointer from the program state */ let instruction_pointer = env.get_instruction_pointer(); /* compute the next instruction ptr and add one, as well record raml lookup */ - let _next_instruction_pointer = env.get_next_instruction_pointer(); + let next_instruction_pointer = env.get_next_instruction_pointer(); /* read instruction from ip address */ let instruction = { let v0 = env.read_memory(&instruction_pointer); From 7a13dc7a5907230f05ca6edd00113d277ed1f7f4 Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 17:32:40 -0500 Subject: [PATCH 09/80] implementation for branch greater than equal unsigned --- .../src/interpreters/riscv32im/interpreter.rs | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 0f87fc448e..63b2269eaa 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2289,7 +2289,27 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction env.set_next_instruction_pointer(addr); } SBInstruction::BranchGreaterThanEqualUnsigned => { - unimplemented!("BranchGreaterThanEqualUnsigned") + // bgeu: if (x[rs1] >=u x[rs2]) pc += sext(offset) + let local_rs1 = env.read_register(&rs1); + let local_rs2 = env.read_register(&rs2); + + let rd_scratch = env.alloc_scratch(); + let less_than = unsafe { env.test_less_than(&local_rs1, &local_rs2, rd_scratch) }; + let offset = + less_than.clone() * Env::constant(4) + (Env::constant(1) - less_than) * imm0_12; + + // greater than equal is the negation of less than + let addr = { + let res_scratch = env.alloc_scratch(); + let overflow_scratch = env.alloc_scratch(); + let (res, _overflow) = unsafe { + env.add_witness(&instruction_pointer, &offset, res_scratch, overflow_scratch) + }; + res + }; + + env.set_instruction_pointer(next_instruction_pointer); + env.set_next_instruction_pointer(addr); } }; } From 4a3ed8b3ceddccc61c558ee03157f4c5c691f9ad Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 17:35:48 -0500 Subject: [PATCH 10/80] removing ignore pragma for successfully passing fibb 7 test --- o1vm/tests/test_riscv_elf.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 7b278a3a8e..2ecda3d173 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -52,7 +52,6 @@ fn test_no_action() { // FIXME: stop ignoring when all the instructions are implemented. #[test] -#[ignore] fn test_fibonacci_7() { let curr_dir = std::env::current_dir().unwrap(); let path = curr_dir.join(std::path::PathBuf::from( From 72b6d4d8fca064efa9fe444d1c0ac9ce2bab5899 Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 17:59:10 -0500 Subject: [PATCH 11/80] removing FIXME comment --- o1vm/tests/test_riscv_elf.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 2ecda3d173..cae094a530 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -50,7 +50,6 @@ fn test_no_action() { assert_eq!(witness.registers.general_purpose[17], 42); } -// FIXME: stop ignoring when all the instructions are implemented. #[test] fn test_fibonacci_7() { let curr_dir = std::env::current_dir().unwrap(); From 4a3161db65117500e14de45a7dc39c2a0402928b Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Sun, 22 Dec 2024 14:46:29 +0100 Subject: [PATCH 12/80] o1vm/riscv32: add alias for registers --- o1vm/src/interpreters/riscv32im/registers.rs | 99 ++++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 14 +++ 2 files changed, 113 insertions(+) diff --git a/o1vm/src/interpreters/riscv32im/registers.rs b/o1vm/src/interpreters/riscv32im/registers.rs index ca5906bd54..6a73eca625 100644 --- a/o1vm/src/interpreters/riscv32im/registers.rs +++ b/o1vm/src/interpreters/riscv32im/registers.rs @@ -64,3 +64,102 @@ impl IndexMut for Registers { } } } + +/// This enum provides aliases for the registers. +/// This is useful for debugging and for providing a more readable interface. +/// It can be used to index the registers in the witness. +pub enum RegisterAlias { + Zero, + /// Return address + Ra, + /// Stack pointer + Sp, + /// Global pointer + Gp, + /// Thread pointer + Tp, + /// Temporary/alternate register + T0, + /// Temporaries + T1, + T2, + /// Frame pointer/saved register. This is the same register. + Fp, + S0, + /// Saved registers + S1, + /// Function arguments/results + A0, + A1, + A2, + A3, + A4, + A5, + A6, + A7, + S2, + S3, + S4, + S5, + S6, + S7, + S8, + S9, + S10, + S11, + T3, + T4, + T5, + T6, + /// Current instruction pointer + Ip, + /// Next instruction pointer + NextIp, + HeapPointer, +} + +impl Index for Registers { + type Output = T; + + fn index(&self, index: RegisterAlias) -> &Self::Output { + match index { + RegisterAlias::Zero => &self.general_purpose[0], + RegisterAlias::Ra => &self.general_purpose[1], + RegisterAlias::Sp => &self.general_purpose[2], + RegisterAlias::Gp => &self.general_purpose[3], + RegisterAlias::Tp => &self.general_purpose[4], + RegisterAlias::T0 => &self.general_purpose[5], + RegisterAlias::T1 => &self.general_purpose[6], + RegisterAlias::T2 => &self.general_purpose[7], + // Frame pointer and first saved register are the same register. + RegisterAlias::Fp => &self.general_purpose[8], + RegisterAlias::S0 => &self.general_purpose[8], + RegisterAlias::S1 => &self.general_purpose[9], + RegisterAlias::A0 => &self.general_purpose[10], + RegisterAlias::A1 => &self.general_purpose[11], + RegisterAlias::A2 => &self.general_purpose[12], + RegisterAlias::A3 => &self.general_purpose[13], + RegisterAlias::A4 => &self.general_purpose[14], + RegisterAlias::A5 => &self.general_purpose[15], + RegisterAlias::A6 => &self.general_purpose[16], + RegisterAlias::A7 => &self.general_purpose[17], + RegisterAlias::S2 => &self.general_purpose[18], + RegisterAlias::S3 => &self.general_purpose[19], + RegisterAlias::S4 => &self.general_purpose[20], + RegisterAlias::S5 => &self.general_purpose[21], + RegisterAlias::S6 => &self.general_purpose[22], + RegisterAlias::S7 => &self.general_purpose[23], + RegisterAlias::S8 => &self.general_purpose[24], + RegisterAlias::S9 => &self.general_purpose[25], + RegisterAlias::S10 => &self.general_purpose[26], + RegisterAlias::S11 => &self.general_purpose[27], + RegisterAlias::T3 => &self.general_purpose[28], + RegisterAlias::T4 => &self.general_purpose[29], + RegisterAlias::T5 => &self.general_purpose[30], + RegisterAlias::T6 => &self.general_purpose[31], + RegisterAlias::Ip => &self.current_instruction_pointer, + RegisterAlias::NextIp => &self.next_instruction_pointer, + RegisterAlias::HeapPointer => &self.heap_pointer, + } + } +} diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 4152a5d4bc..8aba68fd3f 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -1,10 +1,24 @@ use mina_curves::pasta::Fp; use o1vm::interpreters::riscv32im::{ interpreter::{IInstruction, Instruction, RInstruction}, + registers::RegisterAlias::*, witness::Env, PAGE_SIZE, }; +#[test] +fn test_registers_indexed_by_alias() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/sll", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + assert_eq!(witness.registers[Ip], 65688); + assert_eq!(witness.registers[NextIp], 65692); +} + #[test] // Checking an instruction can be converted into a string. // It is mostly because we would want to use it to debug or write better error From a709048a0ebe43cdfa8e85d08a3bb787c8ece956 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Sun, 22 Dec 2024 15:29:57 +0100 Subject: [PATCH 13/80] o1vm/mips: use u64 to avoid overflow when bitlength is 0 When bitlength = 0 and when compiling with `-Coverflow-checks=y`, the runtime alerts us that there is an overflow while shifting. Lifting the type to u64 and cast the value as u32 when the computation is done. --- o1vm/src/interpreters/mips/interpreter.rs | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/o1vm/src/interpreters/mips/interpreter.rs b/o1vm/src/interpreters/mips/interpreter.rs index 0ea55c67ea..5ba96d9885 100644 --- a/o1vm/src/interpreters/mips/interpreter.rs +++ b/o1vm/src/interpreters/mips/interpreter.rs @@ -934,7 +934,13 @@ pub trait InterpreterEnv { let pos = self.alloc_scratch(); unsafe { self.bitmask(x, bitlength, bitlength - 1, pos) } }; - high_bit * Self::constant(((1 << (32 - bitlength)) - 1) << bitlength) + x.clone() + // Casting in u64 for special case of bitlength = 0 to avoid overflow. + // No condition for constant time execution. + // Decomposing the steps for readability. + let v: u64 = (1u64 << (32 - bitlength)) - 1; + let v: u64 = v << bitlength; + let v: u32 = v as u32; + high_bit * Self::constant(v) + x.clone() } fn report_exit(&mut self, exit_code: &Self::Variable); From 3ed7c54772609e45ea8fc42de2afd3a453465551 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Sun, 22 Dec 2024 15:24:51 +0100 Subject: [PATCH 14/80] o1vm/riscv32im: add runtime assertion for input invariants --- o1vm/src/interpreters/riscv32im/witness.rs | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/o1vm/src/interpreters/riscv32im/witness.rs b/o1vm/src/interpreters/riscv32im/witness.rs index c02b240bb4..011185339b 100644 --- a/o1vm/src/interpreters/riscv32im/witness.rs +++ b/o1vm/src/interpreters/riscv32im/witness.rs @@ -214,6 +214,14 @@ impl InterpreterEnv for Env { lowest_bit: u32, position: Self::Position, ) -> Self::Variable { + assert!( + lowest_bit < highest_bit, + "The lowest bit must be strictly lower than the highest bit" + ); + assert!( + highest_bit <= 32, + "The interpreter is for a 32bits architecture" + ); let x: u32 = (*x).try_into().unwrap(); let res = (x >> lowest_bit) & ((1 << (highest_bit - lowest_bit)) - 1); let res = res as u64; From e2b64e30fb06e4c7d8df5b2543a6922007d6aa6d Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Sun, 22 Dec 2024 15:25:27 +0100 Subject: [PATCH 15/80] o1vm/riscv32: sign_extend - add runtime assert for input invariants --- o1vm/src/interpreters/riscv32im/interpreter.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index f27d89ec4e..6338616219 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -1388,6 +1388,7 @@ pub trait InterpreterEnv { /// Given a variable `x`, this function extends it to a signed integer of /// `bitlength` bits. fn sign_extend(&mut self, x: &Self::Variable, bitlength: u32) -> Self::Variable { + assert!(bitlength <= 32); // FIXME: Constrain `high_bit` let high_bit = { let pos = self.alloc_scratch(); From 921811bd41c0ce1b786712ebe307ce1198bfb017 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Sun, 22 Dec 2024 15:25:58 +0100 Subject: [PATCH 16/80] o1vm/riscv32im: sign_extend - make it friendly with overflow checks When bitlength = 0 and when compiling with `-Coverflow-checks=y`, the runtime alerts us that there is an overflow while shifting. Lifting the type to u64 and cast the value as u32 when the computation is done. --- o1vm/src/interpreters/riscv32im/interpreter.rs | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 6338616219..e960a93fb4 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -1394,7 +1394,13 @@ pub trait InterpreterEnv { let pos = self.alloc_scratch(); unsafe { self.bitmask(x, bitlength, bitlength - 1, pos) } }; - high_bit * Self::constant(((1 << (32 - bitlength)) - 1) << bitlength) + x.clone() + // Casting in u64 for special case of bitlength = 0 to avoid overflow. + // No condition for constant time execution. + // Decomposing the steps for readability. + let v: u64 = (1u64 << (32 - bitlength)) - 1; + let v: u64 = v << bitlength; + let v: u32 = v as u32; + high_bit * Self::constant(v) + x.clone() } fn report_exit(&mut self, exit_code: &Self::Variable); From 177a9d5d245d1e438d2be6b279e343b575c39d00 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Sun, 22 Dec 2024 14:00:22 +0100 Subject: [PATCH 17/80] o1vm/riscv: sll tests - inline exit_success --- o1vm/resources/programs/riscv32im/src/sll.S | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/o1vm/resources/programs/riscv32im/src/sll.S b/o1vm/resources/programs/riscv32im/src/sll.S index 0f8cedd065..daf76f7fb8 100644 --- a/o1vm/resources/programs/riscv32im/src/sll.S +++ b/o1vm/resources/programs/riscv32im/src/sll.S @@ -1,6 +1,8 @@ .global _start -exit_success: +_start: + lui t0, 0x42 + sll t0, t0, 2 li a0, 0 li a1, 0 li a2, 0 @@ -10,8 +12,3 @@ exit_success: li a6, 0 li a7, 42 ecall - -_start: - lui t0, 0x42 - sll t0, t0, 2 - jal exit_success From d2d8d97309c6b9bd3843afaef6c6c0e3d57ecd4b Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Sun, 22 Dec 2024 14:00:46 +0100 Subject: [PATCH 18/80] o1vm/riscv32: run build-riscv32-programs --- o1vm/resources/programs/riscv32im/bin/sll | Bin 456 -> 452 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/o1vm/resources/programs/riscv32im/bin/sll b/o1vm/resources/programs/riscv32im/bin/sll index f5a7fc75b1f62ac9d2aebd97981d7a0843554b68..a6fbe52b56bbec3057643a92f1fd6c6ed9c74f29 100755 GIT binary patch delta 91 zcmX@Xe1v&|1ZN2YBZCP81B1#$MRCRj6D_sH7XW!6%nHN|0t^h>l~@=iPg0s#tU7VY d0Y;t4sf@~u3nq6ms!RL_Do_Tgf&xY;4FGX*5QhK& delta 86 zcmX@Ye1ds`1m_F}Mg|iG1_q6ZisFn*CR%FqF9GsEm=%Z_1Q;e(tMY7DVqus(Nr~b8 lhxoq}7aU+Tn4HL{%nDKzKY1gg@Z>p+0!++|lh-kd0RVou72E&- From 763521614321f795e5e1a5d44db4f684c493fa20 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Sun, 22 Dec 2024 14:01:19 +0100 Subject: [PATCH 19/80] o1vm/riscv32: stop ignoring sll.S test --- o1vm/tests/test_riscv_elf.rs | 3 --- 1 file changed, 3 deletions(-) diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 8aba68fd3f..343cbfb73c 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -88,10 +88,7 @@ fn test_fibonacci_7() { } } -// FIXME: stop ignore when all the instructions necessary for running this -// program are implemented. #[test] -#[ignore] fn test_sll() { let curr_dir = std::env::current_dir().unwrap(); let path = curr_dir.join(std::path::PathBuf::from( From ae5870f163a5da2bc398674ae280f6d1883cd91e Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Sun, 22 Dec 2024 14:01:52 +0100 Subject: [PATCH 20/80] Ignore object files from o1vm programs --- .gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 67a6dff458..c6f644327e 100644 --- a/.gitignore +++ b/.gitignore @@ -41,4 +41,5 @@ meta.json state.json # Directory for the RISC-V 32bits toolchain -_riscv32-gnu-toolchain \ No newline at end of file +_riscv32-gnu-toolchain +o1vm/resources/programs/riscv32im/bin/*.o \ No newline at end of file From 5dc6d5759b45ead66c2d033793bf738387ae97dc Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Sun, 22 Dec 2024 14:14:07 +0100 Subject: [PATCH 21/80] o1vm/riscv32: update sll program to get a more predictable input --- o1vm/resources/programs/riscv32im/src/sll.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/o1vm/resources/programs/riscv32im/src/sll.S b/o1vm/resources/programs/riscv32im/src/sll.S index daf76f7fb8..e343543e81 100644 --- a/o1vm/resources/programs/riscv32im/src/sll.S +++ b/o1vm/resources/programs/riscv32im/src/sll.S @@ -1,7 +1,9 @@ .global _start _start: - lui t0, 0x42 + # Load 2^12 in the register t0 + lui t0, 0b1 + # Multiply by 4 sll t0, t0, 2 li a0, 0 li a1, 0 From e267608fc3df2db7602b9eb2c0a91c01b7561826 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Sun, 22 Dec 2024 14:14:32 +0100 Subject: [PATCH 22/80] o1vm/riscv32: run make build-riscv32im-programs --- o1vm/resources/programs/riscv32im/bin/sll | Bin 452 -> 452 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/o1vm/resources/programs/riscv32im/bin/sll b/o1vm/resources/programs/riscv32im/bin/sll index a6fbe52b56bbec3057643a92f1fd6c6ed9c74f29..14d0b82f86ad9a542d07cfc83ab024dc1483e35a 100755 GIT binary patch delta 13 UcmX@Ye1v&IDU%Sx#&Taq03f9V9smFU delta 13 UcmX@Ye1v&IDU%Y*#&Taq03jI!G5`Po From 1c0c81ec13214b69c3027852a7ba45b021de5843 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Sun, 22 Dec 2024 14:14:47 +0100 Subject: [PATCH 23/80] o1vm/riscv32: update with expected output --- o1vm/tests/test_riscv_elf.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 343cbfb73c..287e91d9b2 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -101,5 +101,6 @@ fn test_sll() { witness.step(); } - // FIXME: check the state of the registers after the program has run. + // Expected output of the program + assert_eq!(witness.registers.general_purpose[5], 1 << 14) } From 826c154c1b3a36a95c86439b71ca549109a23162 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 15:18:53 +0100 Subject: [PATCH 24/80] o1vm/riscv32im: update IP for sll As the program changed, the initial IP also changed. --- o1vm/tests/test_riscv_elf.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 287e91d9b2..c2925b7b10 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -15,8 +15,8 @@ fn test_registers_indexed_by_alias() { let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); let witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); - assert_eq!(witness.registers[Ip], 65688); - assert_eq!(witness.registers[NextIp], 65692); + assert_eq!(witness.registers[Ip], 65652); + assert_eq!(witness.registers[NextIp], 65656); } #[test] From 1c9586156a7f7c2179c588fab28e7c921750a141 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 13:40:20 +0100 Subject: [PATCH 25/80] o1vm/riscv32im: add example and test for addi --- o1vm/resources/programs/riscv32im/bin/addi | Bin 0 -> 452 bytes o1vm/resources/programs/riscv32im/src/addi.S | 20 +++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 16 +++++++++++++++ 3 files changed, 36 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/addi create mode 100644 o1vm/resources/programs/riscv32im/src/addi.S diff --git a/o1vm/resources/programs/riscv32im/bin/addi b/o1vm/resources/programs/riscv32im/bin/addi new file mode 100755 index 0000000000000000000000000000000000000000..4ad4f72babb9e2542acaa7a09fb1b83828c1b2ef GIT binary patch literal 452 zcma)2K~BRk5S#=GmAHWN0VFtZKoK?l00%g6LY#@*kP1r;ME15qy&&<0e87L?0Wh23 za%HU9nO#j3dp~aP@3JgILXIzJC#-YoIh%dz9H+=}LBGd?E^?Mo{Tj{bx5^P?7uhH$ zB#wbTkLW)iP;k(b#Q~Kp4yj}@rA}iW7{7U9@h;RGWRJ8HzqvNfbhD~8-Bo4PElp>t zXDwS-2e0$3TQ;wC!ytXzu2(ZP*0yh>S@}@Y0cCgz;>9jdO7ku#hkun;#Jj~>8ok4R ram1j$m`@q@C)7(aLHDCLA$5mC!xG7~L!G7lsWP|2H{IE;`^)_RiD5f$ literal 0 HcmV?d00001 diff --git a/o1vm/resources/programs/riscv32im/src/addi.S b/o1vm/resources/programs/riscv32im/src/addi.S new file mode 100644 index 0000000000..f4e50282bf --- /dev/null +++ b/o1vm/resources/programs/riscv32im/src/addi.S @@ -0,0 +1,20 @@ +.section .text +.globl _start + +_start: + # Initialize register + li t0, 10 # Load immediate value 10 into t0 + + # Perform addition + addi t0, t0, 5 # Add 5 to the value in t0 and store the result back in t0 + + # Custom exit syscall + li a0, 0 # Set a0 to 0 + li a1, 0 # Set a1 to 0 + li a2, 0 # Set a2 to 0 + li a3, 0 # Set a3 to 0 + li a4, 0 # Set a4 to 0 + li a5, 0 # Set a5 to 0 + li a6, 0 # Set a6 to 0 + li a7, 42 # Set a7 to 42 (custom ecall number) + ecall diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index c2925b7b10..444249b11b 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -104,3 +104,19 @@ fn test_sll() { // Expected output of the program assert_eq!(witness.registers.general_purpose[5], 1 << 14) } + +#[test] +fn test_addi() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/addi", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T0], 15); +} From a7849d839fe2dc8fb08898c8834050f681009ebf Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 13:53:49 +0100 Subject: [PATCH 26/80] o1vm/riscv32im: simple example with multiple add calls --- o1vm/resources/programs/riscv32im/bin/add_1 | Bin 0 -> 488 bytes o1vm/resources/programs/riscv32im/src/add_1.S | 29 ++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 16 ++++++++++ 3 files changed, 45 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/add_1 create mode 100644 o1vm/resources/programs/riscv32im/src/add_1.S diff --git a/o1vm/resources/programs/riscv32im/bin/add_1 b/o1vm/resources/programs/riscv32im/bin/add_1 new file mode 100755 index 0000000000000000000000000000000000000000..6fc6fe9837f2bc1c9cc707dc662a75eab8cd0ea2 GIT binary patch literal 488 zcma)2!A-+J5S+6KL_!Kd*FdCvcv*=_0q_9v;E@M!EZaE3QViDJB|`Zir3E)Y59t6= z0VU7^4KQnS;mcaHGrO8Q+w*#Ld##j$uK?eW$+6GKHyjSgGmH@6j5_3l`okX}C%;;J za#qk)H;Gr!ljRU-0zijDG~oz(FhMi8fIgXHx6KGcysO>zllW4ahZ;g3k_ml8CUl?N ze+w+Hyu4>KrOnq+ca%M|K99?|o+edXPm)yBBCg})LE5Iwt&#nvTog}vK_hilt(H>} zX<9vZVrgtn1w{7II^)s|kt<#tqV`=;>YORFl`G^M{#(a1N-F%7He*Mg6TT!vsZ&C7 YZU;8W&*v;VpRq7~`x::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T0], 15); +} From 8a260b3b38428b04ff7244f078294ed222346879 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 14:00:09 +0100 Subject: [PATCH 27/80] o1vm/riscv32im: tests for add, a bit more complicated --- o1vm/resources/programs/riscv32im/bin/add_2 | Bin 0 -> 476 bytes o1vm/resources/programs/riscv32im/src/add_2.S | 32 ++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 22 ++++++++++++ 3 files changed, 54 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/add_2 create mode 100644 o1vm/resources/programs/riscv32im/src/add_2.S diff --git a/o1vm/resources/programs/riscv32im/bin/add_2 b/o1vm/resources/programs/riscv32im/bin/add_2 new file mode 100755 index 0000000000000000000000000000000000000000..6a35810533d1bec5a325af15ca95b9ddcef7fe6e GIT binary patch literal 476 zcma)2F;2rk5M0}YL_!LnD`+T?Xs9fFPDz6VR4FK^vChU3C&gghT_ThMcmXN=0iJ;5 zhX3#cKESNag_gBuXLdDrw&&$?dKCl#`3mWqcyj0y@EL|J@Pv*iq!Z`}57nRk066>A z?BlbHzWRy1i~%qAh??+YD5BTHCb~}2x18GXGo@=o?e165uE!)`Yyhzh2E-5yh!J@7 z9$H*;ev4+bEtVAAKn~0@m0H$GR>}G_Q>Odl~e4>Cr5Gju2?x|biQyUf5U%k2S!c;ztZLEz!!io&W&py;B31A WjWhGv^3LbV4Bw^>usGgKf4(0-&q5sl literal 0 HcmV?d00001 diff --git a/o1vm/resources/programs/riscv32im/src/add_2.S b/o1vm/resources/programs/riscv32im/src/add_2.S new file mode 100644 index 0000000000..83f4063ef1 --- /dev/null +++ b/o1vm/resources/programs/riscv32im/src/add_2.S @@ -0,0 +1,32 @@ +.section .text +.globl _start + +_start: + # Initialize registers with some numbers + li t0, 123 # First number + li t1, 456 # Second number + li t2, 789 # Third number + + # Perform first addition + add t3, t0, t1 # t3 = t0 + t1 (123 + 456 = 579) + + # Perform second addition + add t4, t3, t2 # t4 = t3 + t2 (579 + 789 = 1368) + + # Add all numbers in a more complex way for redundancy + add t5, t0, t2 # t5 = t0 + t2 (123 + 789 = 912) + add t6, t1, t5 # t6 = t1 + t5 (456 + 912 = 1368) + + # Ensure final result matches expectations + add t6, t4, x0 # t6 = t4 + x0 (Copy t4 to t6 for validation) + + # Custom exit syscall + li a0, 0 # Set a0 to 0 + li a1, 0 # Set a1 to 0 + li a2, 0 # Set a2 to 0 + li a3, 0 # Set a3 to 0 + li a4, 0 # Set a4 to 0 + li a5, 0 # Set a5 to 0 + li a6, 0 # Set a6 to 0 + li a7, 42 # Set a7 to 42 (custom ecall number) + ecall # Trigger syscall diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index ba3940ef4a..de5709fc23 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -136,3 +136,25 @@ fn test_add_1() { assert_eq!(witness.registers[T0], 15); } + +#[test] +fn test_add_2() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/add_2", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T0], 123); // First number + assert_eq!(witness.registers[T1], 456); // Second number + assert_eq!(witness.registers[T2], 789); // Third number + assert_eq!(witness.registers[T3], 579); // t3 = t0 + t1 + assert_eq!(witness.registers[T4], 1368); // t4 = t3 + t2 + assert_eq!(witness.registers[T5], 912); // t5 = t0 + t2 + assert_eq!(witness.registers[T6], 1368); // t6 = t4 + x0 (Copy t4 to t6) +} From 83e516ca4d0aad9e55b3457068817da64a555a00 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 15:07:02 +0100 Subject: [PATCH 28/80] o1vm/riscv32im: add tests for add with overflows --- .../programs/riscv32im/bin/add_overflow | Bin 0 -> 468 bytes .../programs/riscv32im/src/add_overflow.S | 31 ++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 20 +++++++++++ 3 files changed, 51 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/add_overflow create mode 100644 o1vm/resources/programs/riscv32im/src/add_overflow.S diff --git a/o1vm/resources/programs/riscv32im/bin/add_overflow b/o1vm/resources/programs/riscv32im/bin/add_overflow new file mode 100755 index 0000000000000000000000000000000000000000..0af6dd1bcc4eec53b8f47e2c125f106151701e74 GIT binary patch literal 468 zcma)2F;2rk5L`P1A|ZvK`v4LRl|_z}G!#%#Qe&MRN1PM~>+TYvG$43FKEM-@Qt&MV z4+t|hPFmKQo!Ql_Y|r!c?M)O#(pD@#!YQDSz#|NMWI2&o&Y(MZr21$N!0Df+kGDiq z%|tKJ<#HhM8OzJ+^?Rc_16jXiqWWK(b$=!bh83Xp!GJmd1F8q^y~iHsSNCYn`g|eL z9c0%nF0|FvFfDa;o*Jr&u5>zPTiV<^?w58_%<=+8=(3zohZM$?kByi*pF@cx{=o+q zOeRSvo`NLxyAl(Ev)Mcp{D%M5A&g7_zf$KJz?VQ<%!_plFw=TKV^(dZ+_ia<;oH^` K7N^^3=lcaNdO?5y literal 0 HcmV?d00001 diff --git a/o1vm/resources/programs/riscv32im/src/add_overflow.S b/o1vm/resources/programs/riscv32im/src/add_overflow.S new file mode 100644 index 0000000000..1d3616f36b --- /dev/null +++ b/o1vm/resources/programs/riscv32im/src/add_overflow.S @@ -0,0 +1,31 @@ +# The addition performed by `add` is simply a bit-wise addition +# The lowest 32 bits are kept, and no overflow bit is kept. +.section .text +.globl _start + +_start: + # Large positive values + # It is equal to + # 0b01111111111111111111111111111111 + + # 0b00000000000000000000000000000001 = + # 0b10000000000000000000000000000000 = + li t0, 2147483647 # t0 = 2147483647 (Max 32-bit signed int) + li t1, 1 # t1 = 1 + add t2, t0, t1 # t2 = t0 + t1 + + # 0b11111111111111111111111111111111 + + # 0b00000000000000000000000000000001 = + # 0b00000000000000000000000000000000 = + li t3, 0b11111111111111111111111111111111 + add t4, t3, t1 # t4 = t3 + t1 (Expected: overflow, wrap around) + + # Custom exit syscall + li a0, 0 + li a1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 42 + ecall diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index de5709fc23..7d3d7be7d2 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -158,3 +158,23 @@ fn test_add_2() { assert_eq!(witness.registers[T5], 912); // t5 = t0 + t2 assert_eq!(witness.registers[T6], 1368); // t6 = t4 + x0 (Copy t4 to t6) } + +#[test] +fn test_add_overflow() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/add_overflow", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T0], 0b01111111111111111111111111111111); + assert_eq!(witness.registers[T1], 0b00000000000000000000000000000001); + assert_eq!(witness.registers[T2], 0b10000000000000000000000000000000); + assert_eq!(witness.registers[T3], 0b11111111111111111111111111111111); + assert_eq!(witness.registers[T4], 0b00000000000000000000000000000000); +} From 911df441c2b861026c5f3935a6e258be367ca203 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 15:13:19 +0100 Subject: [PATCH 29/80] o1vm/riscv32im: add tests for addi with negative values --- .../programs/riscv32im/bin/addi_negative | Bin 0 -> 456 bytes .../programs/riscv32im/src/addi_negative.S | 22 ++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 18 ++++++++++++++ 3 files changed, 40 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/addi_negative create mode 100644 o1vm/resources/programs/riscv32im/src/addi_negative.S diff --git a/o1vm/resources/programs/riscv32im/bin/addi_negative b/o1vm/resources/programs/riscv32im/bin/addi_negative new file mode 100755 index 0000000000000000000000000000000000000000..f610f7df86b0c65ba290b0ec29a2b2bf9aab3055 GIT binary patch literal 456 zcma)2F;2rk5M0|yh(rUr4V>+_vN_pn2^yVO=! z^Q_d>EHiW~UFqzRgfGkOW=>;F`P`a~^EsSI>eoKFV3v}GVjm=J z?n+Gv&Mvp1;6MBqrx@suXR0L2wOm=SRfGRLMtVLn}soOKyevDYKPVA6Mgdq::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T0], 100); + assert_eq!(witness.registers[T1], 50); + assert_eq!(witness.registers[T2], (-50_i32) as u32); +} From 5c77396e7a1cf47a52a48b28ffeec62051ac7822 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 15:24:49 +0100 Subject: [PATCH 30/80] o1vm/riscv32im: implement swap using add and sub --- .../programs/riscv32im/bin/add_sub_swap | Bin 0 -> 464 bytes .../programs/riscv32im/src/add_sub_swap.S | 22 ++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 17 ++++++++++++++ 3 files changed, 39 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/add_sub_swap create mode 100644 o1vm/resources/programs/riscv32im/src/add_sub_swap.S diff --git a/o1vm/resources/programs/riscv32im/bin/add_sub_swap b/o1vm/resources/programs/riscv32im/bin/add_sub_swap new file mode 100755 index 0000000000000000000000000000000000000000..292b82f40de05a9e031e83ecadc2da92ef6ece25 GIT binary patch literal 464 zcma)2F;2rk5L`P1BBcTO14uMfR&q%}849Q^*Q$U}BM;MO4Q#qGZE}?sPr1^>mz{Rhok7tRl zx`|$*&*iDeHocdux0C&*l>O(!Y_c)43@^7pb_@ox6EKhsz=K`tarF8L%~@|&k~~88 z-D;w&YQ{yano*&t=BiP}Guzr4@3>#vdG%^47@_NWxfoMuUB7i=;k::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T0], 10); + assert_eq!(witness.registers[T1], 5); +} From f89c47e54f16359006c33bc15bc48e4b71907e80 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 15:43:53 +0100 Subject: [PATCH 31/80] o1vm/riscv32im: test for addi with overflow --- .../programs/riscv32im/bin/addi_overflow | Bin 0 -> 476 bytes .../programs/riscv32im/src/addi_overflow.S | 23 ++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 18 ++++++++++++++ 3 files changed, 41 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/addi_overflow create mode 100644 o1vm/resources/programs/riscv32im/src/addi_overflow.S diff --git a/o1vm/resources/programs/riscv32im/bin/addi_overflow b/o1vm/resources/programs/riscv32im/bin/addi_overflow new file mode 100755 index 0000000000000000000000000000000000000000..d6df4b003cf2fae4971a200ab5abc1f71a7ad5be GIT binary patch literal 476 zcma)2F;2rk5L`QiL_$Kq6|_h+sjTEkNrMDbliT6ViFcyH=2Lqx721Fa& z{s=9uxf-GwZId|#1IVVCUq~(UUYyCi8!J|0nalWr+d?PS@P47k>0^?@2%TlKX^(|c z*;6g1#wJiik)2p)oElN&(q~6e^{z-cXY^?1QvQZr>i|Yh0>4t_>cH24FV2nY7~pKH X0gW^B+49ck$_(GOPO&)OPXE4Nx)(+# literal 0 HcmV?d00001 diff --git a/o1vm/resources/programs/riscv32im/src/addi_overflow.S b/o1vm/resources/programs/riscv32im/src/addi_overflow.S new file mode 100644 index 0000000000..c1539b05a4 --- /dev/null +++ b/o1vm/resources/programs/riscv32im/src/addi_overflow.S @@ -0,0 +1,23 @@ +.section .text +.globl _start + +_start: + li t0, 2147483647 # t0 = 2147483647 (Max 32-bit signed int) + addi t1, t0, 1 # t1 = t0 + 1 (Expected: overflow to -2147483648) + + li t2, -2147483648 # t2 = -2147483648 (Min 32-bit signed int) + addi t3, t2, -1 # t3 = t2 + (-1) (Expected: overflow to 2147483647) + + li t4, 123456789 # t4 = 123456789 + addi t5, t4, 0 # t5 = t4 + 0 (Expected: t4 = 123456789) + + # Custom exit syscall + li a0, 0 + li a1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 42 + ecall diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index a4ab2e526e..077b634270 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -213,3 +213,21 @@ fn test_add_sub_swap() { assert_eq!(witness.registers[T0], 10); assert_eq!(witness.registers[T1], 5); } + +#[test] +fn test_addi_overflow() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/addi_overflow", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T1], (-2147483648_i32) as u32); + assert_eq!(witness.registers[T3], 2147483647); + assert_eq!(witness.registers[T5], 123456789); +} From aab22df80355abeef058bda6b76276b49cf2ab50 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 15:45:54 +0100 Subject: [PATCH 32/80] o1vm/riscv32im: add one test for addi with negative values only --- .../programs/riscv32im/bin/addi_negative | Bin 456 -> 464 bytes .../programs/riscv32im/src/addi_negative.S | 3 +++ o1vm/tests/test_riscv_elf.rs | 1 + 3 files changed, 4 insertions(+) diff --git a/o1vm/resources/programs/riscv32im/bin/addi_negative b/o1vm/resources/programs/riscv32im/bin/addi_negative index f610f7df86b0c65ba290b0ec29a2b2bf9aab3055..5d3eca47c23f70baa3e0637bc42f8f15ed60a395 100755 GIT binary patch delta 74 zcmX@Xe1Um_0;9o1MRCS86D_q>)-W(IfG{f%GYBv+OlERm6K;O=XEO8QpTc|%2PgBL cdoZ!#38Tg2R7PdSHIq9T)fu@bZ)6k)01f~aaR2}S delta 85 zcmcb>e1ds`0;9%6MRCR@6D_r6mM}0dfG{f%GYBv+OlERm6K;O=XEO8QpA$QtFd9tG aWmINdGI=7Sx&$*L1A{V19TWh$U;qG Date: Mon, 23 Dec 2024 15:50:47 +0100 Subject: [PATCH 33/80] o1vm/riscv32im: add unit tests for addi with boundary values --- .../riscv32im/bin/addi_boundary_immediate | Bin 0 -> 460 bytes .../riscv32im/src/addi_boundary_immediate.S | 20 ++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 17 +++++++++++++++ 3 files changed, 37 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/addi_boundary_immediate create mode 100644 o1vm/resources/programs/riscv32im/src/addi_boundary_immediate.S diff --git a/o1vm/resources/programs/riscv32im/bin/addi_boundary_immediate b/o1vm/resources/programs/riscv32im/bin/addi_boundary_immediate new file mode 100755 index 0000000000000000000000000000000000000000..65f5381c3c72e9cf59f00da22af000379ec124f8 GIT binary patch literal 460 zcma)2yH3ME5M0~jA<=;D2asqekVTHv2nwhusj)7`5hul9-CZJ-CXwiA`~#GHAN&9_ zb}qE6H9NEGIoUUx+xxpDNhDS(Kf)=XPr>IH4!~16kyOs0Gd$9K#RK4Cr|IKaqOX3U zml$w)B+{nWL-qc>X|wH>`pC8lFIqqi!GIcp0W}7XKU0rmH;-t}`f?@71LVN1F16Lo zq^NasQ5dSZZgla)wzj2r+^_AtdMPUyq3e3Nm{1r~zxHC`d::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T1], 2147); + assert_eq!(witness.registers[T3], (-1048_i32) as u32); +} From b7e0aa999668d0c0dc5a795085768168750a84cd Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 16:01:10 +0100 Subject: [PATCH 34/80] o1vm/riscv32im: add tests for sub --- o1vm/resources/programs/riscv32im/bin/sub | Bin 0 -> 468 bytes o1vm/resources/programs/riscv32im/bin/sub_2 | Bin 0 -> 468 bytes o1vm/resources/programs/riscv32im/bin/sub_3 | Bin 0 -> 468 bytes o1vm/resources/programs/riscv32im/src/sub.S | 25 +++++++++ o1vm/resources/programs/riscv32im/src/sub_2.S | 25 +++++++++ o1vm/resources/programs/riscv32im/src/sub_3.S | 22 ++++++++ o1vm/tests/test_riscv_elf.rs | 51 ++++++++++++++++++ 7 files changed, 123 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/sub create mode 100755 o1vm/resources/programs/riscv32im/bin/sub_2 create mode 100755 o1vm/resources/programs/riscv32im/bin/sub_3 create mode 100644 o1vm/resources/programs/riscv32im/src/sub.S create mode 100644 o1vm/resources/programs/riscv32im/src/sub_2.S create mode 100644 o1vm/resources/programs/riscv32im/src/sub_3.S diff --git a/o1vm/resources/programs/riscv32im/bin/sub b/o1vm/resources/programs/riscv32im/bin/sub new file mode 100755 index 0000000000000000000000000000000000000000..49411f110d305c1486004c84feabbfce83d50791 GIT binary patch literal 468 zcma)2!AiqG6nsf-EeNf$AE4mHQ?O}|BI!X-9z7d2F~x;O!|t|7FA9D_f51-={2zb9 zA8;md>(v+L&Ai7vlFZB1&2_5<1Nuu zH_=Pqbp1maPyAtiaHO0zT{D%M50gOxlztZOE!52U%=EXV!m}xtpF{_X%cOg$Qe7hQB Jak`uSd_U_%K1~1s literal 0 HcmV?d00001 diff --git a/o1vm/resources/programs/riscv32im/bin/sub_2 b/o1vm/resources/programs/riscv32im/bin/sub_2 new file mode 100755 index 0000000000000000000000000000000000000000..964e9c737a574da228dd409d1f067131750e10d6 GIT binary patch literal 468 zcma)2F;2rk5L`PXL_$h{djLo@R2FekQaA-vl+;*f(dYMc{4rNB)PNd*0ksPT)DS#;2_4SoH)z(l zd@aE>WZ$l*v5BimTE^8`s;L%n6{ojs8Lo1fn(6o$2el87_8k*gwlYNp2ip82uKth zfD0kz0Aa?CL(8+~&Ag|1vOO;sSC>H$NK>J#gp)@ff`=G($kLTideALAQhYQA;CQ3y z<1JBFJ<&_FxjYgn!|wH9d2{~NlGk#%TC0Pf_2=97NWoA7Y8MQsJusj;;LdyKa6Y<2 zv&N-!32q_Vc0SNX7yUTb#c7;SO?08-d$xs1o#lRECfQ?}!3dq_vuU3qN%E&!Osz|y zL?ZX#y!FXgBA-2biK=%+iTBowXFlUM{I~XDWCHk=Do+nS1Dax9tYd(gRs$NdYBJ@n Q$&(D(^b literal 0 HcmV?d00001 diff --git a/o1vm/resources/programs/riscv32im/src/sub.S b/o1vm/resources/programs/riscv32im/src/sub.S new file mode 100644 index 0000000000..53abe9bd17 --- /dev/null +++ b/o1vm/resources/programs/riscv32im/src/sub.S @@ -0,0 +1,25 @@ +.section .text +.globl _start + +_start: + + # Test 1: Simple subtraction + li t0, 1000 # t0 = 1000 + li t1, 500 # t1 = 500 + sub t2, t0, t1 # t2 = t0 - t1 (Expected: t2 = 500) + + # Test 2: Subtracting from zero + li t3, 0 # t3 = 0 + li t4, 100 # t4 = 100 + sub t5, t3, t4 # t5 = t3 - t4 (Expected: t5 = -100) + + # Custom exit syscall + li a0, 0 + li a1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 42 + ecall diff --git a/o1vm/resources/programs/riscv32im/src/sub_2.S b/o1vm/resources/programs/riscv32im/src/sub_2.S new file mode 100644 index 0000000000..8ccadb14ba --- /dev/null +++ b/o1vm/resources/programs/riscv32im/src/sub_2.S @@ -0,0 +1,25 @@ +.section .text +.globl _start + +_start: + + # Test 3: Subtracting a larger value (result negative) + li t0, 300 # t0 = 300 + li t1, 500 # t1 = 500 + sub t2, t0, t1 # t2 = t0 - t1 (Expected: t2 = -200) + + # Test 4: Subtracting negative values (result positive) + li t3, 100 # t3 = 100 + li t4, -50 # t4 = -50 + sub t5, t3, t4 # t5 = t3 - t4 (Expected: t5 = 150) + + # Custom exit syscall + li a0, 0 + li a1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 42 + ecall diff --git a/o1vm/resources/programs/riscv32im/src/sub_3.S b/o1vm/resources/programs/riscv32im/src/sub_3.S new file mode 100644 index 0000000000..78e90cc011 --- /dev/null +++ b/o1vm/resources/programs/riscv32im/src/sub_3.S @@ -0,0 +1,22 @@ +.section .text +.globl _start + +_start: + # Test 5: Result of subtracting from a register (using same value) + li t0, 1234 # t0 = 1234 + sub t1, t0, t0 # t1 = t0 - t0 (Expected: t1 = 0) + + # Test 6: Handling overflow (large subtraction result) + li t2, 2147483647 # t2 = 2147483647 (max positive signed 32-bit) + li t3, -1 # t3 = -1 + sub t4, t2, t3 # t4 = t2 - t3 (Expected: t0 = 2147483648, wraparound to -2147483648) + # Custom exit syscall + li a0, 0 + li a1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 42 + ecall diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 70db24b670..2c896e5d39 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -249,3 +249,54 @@ fn test_addi_boundary_immediate() { assert_eq!(witness.registers[T1], 2147); assert_eq!(witness.registers[T3], (-1048_i32) as u32); } + +#[test] +fn test_sub() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/sub", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T2], 500); + assert_eq!(witness.registers[T5], (-100_i32) as u32); +} + +#[test] +fn test_sub_2() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/sub_2", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T2], -200_i32 as u32); + assert_eq!(witness.registers[T5], 150); +} + +#[test] +fn test_sub_3() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/sub_3", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T1], 0); + assert_eq!(witness.registers[T4], -2147483648_i32 as u32); +} From 5a6e53b6e6e3675350b1402a6f4c5df0febbc548 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 16:08:39 +0100 Subject: [PATCH 35/80] o1vm/riscv32im: add tests for XOR --- o1vm/resources/programs/riscv32im/bin/xor | Bin 0 -> 480 bytes o1vm/resources/programs/riscv32im/src/xor.S | 30 ++++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 18 ++++++++++++ 3 files changed, 48 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/xor create mode 100644 o1vm/resources/programs/riscv32im/src/xor.S diff --git a/o1vm/resources/programs/riscv32im/bin/xor b/o1vm/resources/programs/riscv32im/bin/xor new file mode 100755 index 0000000000000000000000000000000000000000..2a9f659899027a72af0500893945a842b8b65dc4 GIT binary patch literal 480 zcma)2J5Iwu6r6PkL_!LnEoqQws4QaV08oG^kZ7o}*2WQ*Vz72M5lX`$d;#BqmI5jF z;0%$t0P}1dTAnp;<~`5)GjCV7*Geh$72q2(dG;y!g2N7ZiW3AlqaN@=_0b<7C%;;J za#qk)H;Gp;l;t5%2cOV`2Jh<>dfcEM1M%ILst-22w?Vv4plPlNy-Oza9+}W1@~8::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T2], 0b0110); // Result: t2 = 0b0110 + assert_eq!(witness.registers[T5], 0b1010); // Result: t5 = 0b1010 + assert_eq!(witness.registers[T1], 0); // Result: t1 = 0 +} From b12342663807c612fb5002a7913b01c16313656e Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 16:11:10 +0100 Subject: [PATCH 36/80] o1vm/riscv32im: add tests for AND --- o1vm/resources/programs/riscv32im/bin/and | Bin 0 -> 480 bytes o1vm/resources/programs/riscv32im/src/and.S | 30 ++++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 18 ++++++++++++ 3 files changed, 48 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/and create mode 100644 o1vm/resources/programs/riscv32im/src/and.S diff --git a/o1vm/resources/programs/riscv32im/bin/and b/o1vm/resources/programs/riscv32im/bin/and new file mode 100755 index 0000000000000000000000000000000000000000..4b645914a8b530f554043e7a6a1bed3593dd8e9c GIT binary patch literal 480 zcma)2J5Iwu6dXGQA|VCPmNZB-R2Et108oG^D5+W5#u1icuy!{QN|QtQ0=@$+1t;MQ zNWK8`Y#dsiHE-rU&-ydloBP`!2ryKL7BYGEIr)mi9(j&4gt(v{@j~@693Y!tEj~Fb z=&PT^D;Uf27^uTfs8NIWHiepgqn-ls_A9858s2LVw+4#lno#>>LLHC^H6c%$(D6~% zk8HMZ*&4wE<=C!cUFd3NN?l!=MASl8+B`|y6q&QK-xQ1dCCh1~F3Z(&CL&47*Iq2G z%cy|JJv(oGk|Of?n@7~WD@we#MY{62e8Ye1kVZ*^ztUyv$#=w1lAY8EA^CO#o8&g+ TE4v|EVfuD;%EkF^`t$t&+QUQY literal 0 HcmV?d00001 diff --git a/o1vm/resources/programs/riscv32im/src/and.S b/o1vm/resources/programs/riscv32im/src/and.S new file mode 100644 index 0000000000..4bab937b9b --- /dev/null +++ b/o1vm/resources/programs/riscv32im/src/and.S @@ -0,0 +1,30 @@ +.section .text +.globl _start + +_start: + + # Simple AND + li t0, 0b1100 # t0 = 0b1100 + li t1, 0b1010 # t1 = 0b1010 + and t2, t0, t1 # t2 = t0 & t1 (Expected: t2 = 0b1000) + + # AND with zero (result always zero) + li t3, 0b1111 # t3 = 0b1111 + li t4, 0 # t4 = 0 + and t5, t3, t4 # t5 = t3 & t4 (Expected: t5 = 0) + + # AND of identical values (result same value) + li t6, 0b1010 # t6 = 0b1010 + li t0, 0b1010 # t0 = 0b1010 + and t1, t6, t0 # t1 = t6 & t0 (Expected: t1 = 0b1010) + + # Custom exit syscall + li a0, 0 + li a1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 42 + ecall diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 80f00f9169..6646c5b734 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -318,3 +318,21 @@ fn test_xor() { assert_eq!(witness.registers[T5], 0b1010); // Result: t5 = 0b1010 assert_eq!(witness.registers[T1], 0); // Result: t1 = 0 } + +#[test] +fn test_and() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/and", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T2], 0b1000); + assert_eq!(witness.registers[T5], 0); + assert_eq!(witness.registers[T1], 0b1010); +} From 755b08551aa243911cc0967eb6875e93e650fd70 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 16:14:36 +0100 Subject: [PATCH 37/80] o1vm/riscv32im: add tests for SLT --- o1vm/resources/programs/riscv32im/bin/slt | Bin 0 -> 480 bytes o1vm/resources/programs/riscv32im/src/slt.S | 30 ++++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 18 ++++++++++++ 3 files changed, 48 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/slt create mode 100644 o1vm/resources/programs/riscv32im/src/slt.S diff --git a/o1vm/resources/programs/riscv32im/bin/slt b/o1vm/resources/programs/riscv32im/bin/slt new file mode 100755 index 0000000000000000000000000000000000000000..4f8906dd863ce9992d71d18526f3b9741822a4c3 GIT binary patch literal 480 zcma)2J5Iwu6nwiTKM_U1mNZB-REBJFfKY%aC{yFu#t|#UVC`-ql!n~F7eL|w6lp0q z376mk%(HQ5dDgs{_cXh<=jH15S_nZ+N%|(9Jo*?s!LSD&(+NpBgAVXe@zERrN57hV ze3nsHJ+YV3;^hHRDJN|eZ2H@`gw){ks2ptiqw_CO%2`hZv)=X{dzec=wZVYufC1G7 zcVDH$RhM^Y*0^*;7 literal 0 HcmV?d00001 diff --git a/o1vm/resources/programs/riscv32im/src/slt.S b/o1vm/resources/programs/riscv32im/src/slt.S new file mode 100644 index 0000000000..42ff3e513e --- /dev/null +++ b/o1vm/resources/programs/riscv32im/src/slt.S @@ -0,0 +1,30 @@ +.section .text +.globl _start + +_start: + + # SLT with t0 < t1 (Expected: 1) + li t0, 100 # t0 = 100 + li t1, 200 # t1 = 200 + slt t2, t0, t1 # t2 = (t0 < t1) ? 1 : 0 (Expected: t2 = 1) + + # SLT with t3 > t4 (Expected: 0) + li t3, 300 # t3 = 300 + li t4, 200 # t4 = 200 + slt t5, t3, t4 # t5 = (t3 < t4) ? 1 : 0 (Expected: t5 = 0) + + # SLT with t0 == t1 (Expected: 0) + li t0, 150 # t6 = 150 + li t1, 150 # t7 = 150 + slt t6, t0, t1 # t6 = (t0 < t1) ? 1 : 0 (Expected: t6 = 0) + + # Custom exit syscall + li a0, 0 + li a1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 42 + ecall diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 6646c5b734..be690f54b2 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -336,3 +336,21 @@ fn test_and() { assert_eq!(witness.registers[T5], 0); assert_eq!(witness.registers[T1], 0b1010); } + +#[test] +fn test_slt() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/slt", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T2], 1); + assert_eq!(witness.registers[T5], 0); + assert_eq!(witness.registers[T6], 0); +} From b32afd03e52be0b1ce4775dc2e56ca60aa6f55ac Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 16:23:40 +0100 Subject: [PATCH 38/80] o1vm/riscv32im: additional documentation when dividing by zero --- o1vm/src/interpreters/riscv32im/interpreter.rs | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index e960a93fb4..f2cb725bc9 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -1286,6 +1286,10 @@ pub trait InterpreterEnv { /// There are no constraints on the returned values; callers must manually add constraints to /// ensure that the pair of returned values correspond to the given values `x` and `y`, and /// that they fall within the desired range. + /// + /// Division by zero will create a panic! exception. The RISC-V + /// specification leaves the case unspecified, and therefore we prefer to + /// forbid this case while building the witness. unsafe fn div_signed( &mut self, x: &Self::Variable, @@ -1314,6 +1318,10 @@ pub trait InterpreterEnv { /// There are no constraints on the returned values; callers must manually add constraints to /// ensure that the pair of returned values correspond to the given values `x` and `y`, and /// that they fall within the desired range. + /// + /// Division by zero will create a panic! exception. The RISC-V + /// specification leaves the case unspecified, and therefore we prefer to + /// forbid this case while building the witness. unsafe fn div( &mut self, x: &Self::Variable, From 27a0dd4865fb24815c8b8c8e64d7e590a9ff2da4 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 16:23:57 +0100 Subject: [PATCH 39/80] o1vm/riscv32im: test dividing by zero --- .../programs/riscv32im/bin/div_by_zero | Bin 0 -> 456 bytes .../programs/riscv32im/bin/divu_by_zero | Bin 0 -> 456 bytes .../programs/riscv32im/src/div_by_zero.S | 19 +++++++++++ .../programs/riscv32im/src/divu_by_zero.S | 19 +++++++++++ o1vm/tests/test_riscv_elf.rs | 30 ++++++++++++++++++ 5 files changed, 68 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/div_by_zero create mode 100755 o1vm/resources/programs/riscv32im/bin/divu_by_zero create mode 100644 o1vm/resources/programs/riscv32im/src/div_by_zero.S create mode 100644 o1vm/resources/programs/riscv32im/src/divu_by_zero.S diff --git a/o1vm/resources/programs/riscv32im/bin/div_by_zero b/o1vm/resources/programs/riscv32im/bin/div_by_zero new file mode 100755 index 0000000000000000000000000000000000000000..57cd40f70db51171753060c0f6f10029cba63f67 GIT binary patch literal 456 zcma)2F;2rk5L{mfM4|!R2asq|S>(tED4?RG#yT5EoD_p~w~0_19+3~E;0HW`C-DJh zY;0P_nw{Cz?wxPnZ}0E2ERz97zJ-}0E}?TIN6@8Qh>`BSH+R+Di5SJB{0G7hJn28rNPG zo^It@S3EK7LX{%xyRfQXsv3>(O|w}qXuNM;d$W$If)mNpbJD23lw9jKmAtzv_o^|J w8?E^d|HUa9`D#3++o3{n#R%?*I0w1ME(tED4?RG#yT5EoD_p~w~0_19+3~E;0HW~r|`BSH+R+Di5SJB{0G7hJn28rNPG zo^It@S3EK7LX{%xyRfQXsv3>(O|w}qXuNM;d$W$If)mNpbJD23lw9jKmAtzv_o^|J w8?E^d|HUa9`D#3++o3{n#R%?*I0w1ME::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } +} + +#[test] +#[should_panic] +fn test_divu_by_zero() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/divu_by_zero", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } +} From 603969ccbd2f0d55e13feac0f5909689a1f440fe Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 16:31:03 +0100 Subject: [PATCH 40/80] o1vm/riscv32im: rem and remu by zero --- .../programs/riscv32im/bin/rem_by_zero | Bin 0 -> 456 bytes .../programs/riscv32im/bin/remu_by_zero | Bin 0 -> 456 bytes .../programs/riscv32im/src/rem_by_zero.S | 19 +++++++++++ .../programs/riscv32im/src/remu_by_zero.S | 19 +++++++++++ o1vm/tests/test_riscv_elf.rs | 30 ++++++++++++++++++ 5 files changed, 68 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/rem_by_zero create mode 100755 o1vm/resources/programs/riscv32im/bin/remu_by_zero create mode 100644 o1vm/resources/programs/riscv32im/src/rem_by_zero.S create mode 100644 o1vm/resources/programs/riscv32im/src/remu_by_zero.S diff --git a/o1vm/resources/programs/riscv32im/bin/rem_by_zero b/o1vm/resources/programs/riscv32im/bin/rem_by_zero new file mode 100755 index 0000000000000000000000000000000000000000..293f8dd5a281ea99783a4de3fb3fbb83220ed0f1 GIT binary patch literal 456 zcma)2F;2rk5L{mfM4|!R2asq|S>(tED4?RG#yT5EoD_p~w~0_19+3~E;0HX3C-4Dg zY;0P_nw{Cz?wxPnZ}0E2ERz97zJ-}0E}?TIN6@8Qh>`BSH+R+Di5SJB{0G7hJn28rNPG zo^It@S3EK7LX{%xyRfQXsv3>(O|w}qXuNM;d$W$If)mNpbJD23lw9jKmAtzv_o^|J w8?E^d|HUa9`D#3++o3{n#R%?*I0w1ME(tED4?RG#yT5EoD_p~w~0_19+3~E;0HV{A7IAD zre&YT+SQPi5J%xhy3<}yAbapTaBX`dTF{ElM*%RzEZf{+1?V@O0dsBG2 zm1|w`!mtZfimdO#s(!0#G{QH{X1$>CzIpG>I;ILvBu}qNqxw>Etv^)q?ylUc#!zmw u=0E%w=V;`s@sw_d3dI#8xFg~c::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } +} + +#[test] +#[should_panic] +fn test_remu_by_zero() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/remu_by_zero", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } +} From 54c8053dcb73198f525ce9c7263e3fdb5966c387 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 16:54:07 +0100 Subject: [PATCH 41/80] o1vm/riscv32im: test overflow for MUL --- .../programs/riscv32im/bin/mul_overflow | Bin 0 -> 464 bytes .../programs/riscv32im/src/mul_overflow.S | 18 ++++++++++++++++++ o1vm/tests/test_riscv_elf.rs | 16 ++++++++++++++++ 3 files changed, 34 insertions(+) create mode 100755 o1vm/resources/programs/riscv32im/bin/mul_overflow create mode 100644 o1vm/resources/programs/riscv32im/src/mul_overflow.S diff --git a/o1vm/resources/programs/riscv32im/bin/mul_overflow b/o1vm/resources/programs/riscv32im/bin/mul_overflow new file mode 100755 index 0000000000000000000000000000000000000000..3dd27cf465d9ec9a6aa096fbfc28d04b38e0f533 GIT binary patch literal 464 zcma)2F;2rk5L}-LL`nm?4^sCuapi z4U>2UBUv62eZ6g|dr|dywJycj$YoOc^AqxCAW|x zzdke0w6nZ1?KHQd7N#}%y|j%hgO~lrEvkpIf)ToDR?C?PYn#VGEPW`Uh_X-z_G}Bv zxO!sB`fp{H*}G!JmHfkhYXYO(9#`qJWbg$LOR|zW0wm9VK$Dzep0bNs3d6Un2^J^2 H>Cg8A$e}+4 literal 0 HcmV?d00001 diff --git a/o1vm/resources/programs/riscv32im/src/mul_overflow.S b/o1vm/resources/programs/riscv32im/src/mul_overflow.S new file mode 100644 index 0000000000..c7cced4253 --- /dev/null +++ b/o1vm/resources/programs/riscv32im/src/mul_overflow.S @@ -0,0 +1,18 @@ +.section .text +.globl _start + +_start: + li t0, 10000000 # Large number + li t1, 10000000 # Another large number + mul t2, t0, t1 # Test large multiplication (Expected overflow) + + # Custom exit syscall + li a0, 0 + li a1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 42 + ecall diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 5d191951de..792e383b66 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -414,3 +414,19 @@ fn test_remu_by_zero() { witness.step(); } } + +#[test] +fn test_mul_overflow() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/mul_overflow", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T2], 276447232); +} From 84989741c03571fc6c1f0c2a4b17cab8465d2702 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 19:26:13 +0100 Subject: [PATCH 42/80] o1vm/riscv32im: check T2 reg state in add-sub-swap --- o1vm/tests/test_riscv_elf.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index a4ab2e526e..05acfeef76 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -212,4 +212,5 @@ fn test_add_sub_swap() { assert_eq!(witness.registers[T0], 10); assert_eq!(witness.registers[T1], 5); + assert_eq!(witness.registers[T2], 15); } From 2c55e6ba2a31c62e6e6f4c2edabd2134550be340 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 19:29:29 +0100 Subject: [PATCH 43/80] o1vm/riscv32im: check T3 register state for addi --- o1vm/tests/test_riscv_elf.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 09a0b068dd..8c65ba25fb 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -195,6 +195,7 @@ fn test_addi_negative() { assert_eq!(witness.registers[T0], 100); assert_eq!(witness.registers[T1], 50); assert_eq!(witness.registers[T2], (-50_i32) as u32); + assert_eq!(witness.registers[T3], (-1000_i32) as u32); assert_eq!(witness.registers[T4], (-1500_i32) as u32); } From 909e6cb5609b7dfa8acae616b680b46142157a0f Mon Sep 17 00:00:00 2001 From: "fuder.eth" <139509124+vtjl10@users.noreply.github.com> Date: Mon, 23 Dec 2024 20:56:27 +0100 Subject: [PATCH 44/80] Update README-optimism.md --- o1vm/README-optimism.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/o1vm/README-optimism.md b/o1vm/README-optimism.md index 740d495a34..4ce5014df5 100644 --- a/o1vm/README-optimism.md +++ b/o1vm/README-optimism.md @@ -3,7 +3,7 @@ Install the first dependencies: ``` sudo apt update -# chrony will ensure the system clock is open to date +# chrony will ensure the system clock is up to date sudo apt install build-essential git vim chrony ufw -y ``` From 767719a0ce0afb214ab8a8b065f80278dbe7bfa5 Mon Sep 17 00:00:00 2001 From: svv232 Date: Mon, 23 Dec 2024 15:04:17 -0500 Subject: [PATCH 45/80] removing comments for instruction parsing, as these are now clarified by the tests --- o1vm/src/interpreters/riscv32im/interpreter.rs | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 04d50853f2..5da6951177 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2066,9 +2066,7 @@ pub fn interpret_stype(env: &mut Env, instr: SInstruction) /// Following the documentation found /// [here](https://www.cs.cornell.edu/courses/cs3410/2024fa/assignments/cpusim/riscv-instructions.pdf) pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction) { - /* fetch instruction pointer from the program state */ let instruction_pointer = env.get_instruction_pointer(); - /* compute the next instruction ptr and add one, as well record raml lookup */ let _next_instruction_pointer = env.get_next_instruction_pointer(); /* read instruction from ip address */ let instruction = { @@ -2081,13 +2079,11 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction + (v1 * Env::constant(1 << 8)) + v0 }; - /* fetch opcode from instruction bit 0 - 6 for a total len of 7 */ - let opcode = { let pos = env.alloc_scratch(); unsafe { env.bitmask(&instruction, 7, 0, pos) } }; - /* verify opcode is 7 bits */ + env.range_check8(&opcode, 7); let funct3 = { From 758fb1ef50ef62c673d34afe08b1938bc0af49be Mon Sep 17 00:00:00 2001 From: svv232 Date: Mon, 23 Dec 2024 15:16:13 -0500 Subject: [PATCH 46/80] replace range check 8 for size one with assert_boolean --- o1vm/src/interpreters/riscv32im/interpreter.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 5da6951177..2d8c51ebd2 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2110,7 +2110,7 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction unsafe { env.bitmask(&instruction, 8, 7, pos) } }; - env.range_check8(&imm11, 1); + env.assert_boolean(&imm11); let imm1_4 = { let pos = env.alloc_scratch(); @@ -2128,7 +2128,7 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction let pos = env.alloc_scratch(); unsafe { env.bitmask(&instruction, 32, 31, pos) } }; - env.range_check8(&imm12, 1); + env.assert_boolean(&imm12); // check correctness of decomposition of SB type function env.add_constraint( From badda6b6983717089fed748a82571a2d3922feec Mon Sep 17 00:00:00 2001 From: svv232 Date: Mon, 23 Dec 2024 15:21:54 -0500 Subject: [PATCH 47/80] moving scratch into less-than-variable scope --- o1vm/src/interpreters/riscv32im/interpreter.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 88aa412f97..db64d96152 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2210,10 +2210,10 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let rd_scratch = env.alloc_scratch(); - - let less_than = - unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) }; + let less_than = { + let rd_scratch = env.alloc_scratch(); + unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) } + }; let offset = (less_than.clone()) * imm0_12 + (Env::constant(1) - less_than.clone()) * Env::constant(4); From f43e34d1eb9edf219c1eb58d7d9b28b40f8a190a Mon Sep 17 00:00:00 2001 From: "fuder.eth" <139509124+vtjl10@users.noreply.github.com> Date: Mon, 23 Dec 2024 21:23:43 +0100 Subject: [PATCH 48/80] Update zkpm.md --- book/src/plonk/zkpm.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/book/src/plonk/zkpm.md b/book/src/plonk/zkpm.md index 4820a55095..e35dcff645 100644 --- a/book/src/plonk/zkpm.md +++ b/book/src/plonk/zkpm.md @@ -58,7 +58,7 @@ $$ = Z(\omega h)[(a(h) + \beta S_{\sigma1}(h) + \gamma)(b(h) + \beta S_{\sigma2}(h) + \gamma)(c(h) + \beta S_{\sigma3}(h) + \gamma)]$$ -The modified permuation checks that ensures that the check is performed only on all the values except the last $k$ elements in the witness polynomials are as follows. +The modified permutation checks that ensures that the check is performed only on all the values except the last $k$ elements in the witness polynomials are as follows. * For all $h \in H$, $L_1(h)(Z(h) - 1) = 0$ * For all $h \in \blue{H\setminus \{h_{n-k}, \ldots, h_n\}}$, $$\begin{aligned} & Z(h)[(a(h) + \beta h + \gamma)(b(h) + \beta k_1 h + \gamma)(c(h) + \beta k_2 h + \gamma)] \\ From 76ba34a2166694c403c084d35993bf0187ad3f7f Mon Sep 17 00:00:00 2001 From: svv232 Date: Mon, 23 Dec 2024 15:24:23 -0500 Subject: [PATCH 49/80] move position of less than variable into local scope --- o1vm/src/interpreters/riscv32im/interpreter.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 3801a63b0d..207a63a3ff 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2239,10 +2239,10 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let rd_scratch = env.alloc_scratch(); - - let less_than = - unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) }; + let less_than = { + let rd_scratch = env.alloc_scratch(); + unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) } + }; let offset = less_than.clone() * Env::constant(4) + (Env::constant(1) - less_than) * imm0_12; From b7849aa50f06e68c4494d302e484e3289e8e056b Mon Sep 17 00:00:00 2001 From: "fuder.eth" <139509124+vtjl10@users.noreply.github.com> Date: Mon, 23 Dec 2024 21:27:35 +0100 Subject: [PATCH 50/80] Update SUMMARY.md --- book/src/SUMMARY.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/book/src/SUMMARY.md b/book/src/SUMMARY.md index be318bb0a6..5c70bf9b8c 100644 --- a/book/src/SUMMARY.md +++ b/book/src/SUMMARY.md @@ -17,7 +17,7 @@ - [Commitments](./fundamentals/zkbook_commitment.md) - [Polynomial Commitments](./plonk/polynomial_commitments.md) - [Inner Product Argument](./plonk/inner_product.md) - - [Different Functionnalities](./plonk/inner_product_api.md) + - [Different Functionalities](./plonk/inner_product_api.md) - [Two Party Computation](./fundamentals/zkbook_2pc/overview.md) - [Garbled Circuits](./fundamentals/zkbook_2pc/gc.md) - [Basics](./fundamentals/zkbook_2pc/basics.md) From 037f60ade8101ba5d72324cd982b843f802eed5a Mon Sep 17 00:00:00 2001 From: svv232 Date: Mon, 23 Dec 2024 15:33:41 -0500 Subject: [PATCH 51/80] passing in reference to assert_boolean --- o1vm/src/interpreters/riscv32im/interpreter.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 2d8c51ebd2..702e7ba2ab 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -594,9 +594,9 @@ pub trait InterpreterEnv { fn check_boolean(x: &Self::Variable); /// Assert that the value `x` is boolean, and add a constraint in the proof system. - fn assert_boolean(&mut self, x: Self::Variable) { - Self::check_boolean(&x); - self.add_constraint(x.clone() * x.clone() - x); + fn assert_boolean(&mut self, x: &Self::Variable) { + Self::check_boolean(x); + self.add_constraint(x.clone() * x.clone() - x.clone()); } fn add_lookup(&mut self, lookup: Lookup); From fe0276fe9b66e1d3a75cf0fc185faddc090d7241 Mon Sep 17 00:00:00 2001 From: svv232 Date: Mon, 23 Dec 2024 15:49:52 -0500 Subject: [PATCH 52/80] remove comment and modifying scope of pos --- o1vm/src/interpreters/riscv32im/interpreter.rs | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 5f373ce068..f17e636bc0 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2269,9 +2269,11 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let rd_scratch = env.alloc_scratch(); - let less_than = unsafe { env.test_less_than(&local_rs1, &local_rs2, rd_scratch) }; - // debug!("less_than: {:?}", less_than); + let less_than = { + let rd_scratch = env.alloc_scratch(); + unsafe { env.test_less_than(&local_rs1, &local_rs2, rd_scratch) } + }; + let offset = (Env::constant(1) - less_than.clone()) * Env::constant(4) + less_than.clone() * imm0_12; From a0177abcc829fa1e3ceda8d740e4ca10a23af10c Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 21:22:37 +0100 Subject: [PATCH 53/80] o1vm/riscv32im: simplify assert_boolean --- o1vm/src/interpreters/riscv32im/constraints.rs | 4 ++-- o1vm/src/interpreters/riscv32im/interpreter.rs | 8 +------- o1vm/src/interpreters/riscv32im/witness.rs | 4 ++-- 3 files changed, 5 insertions(+), 11 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/constraints.rs b/o1vm/src/interpreters/riscv32im/constraints.rs index ba1633e1a7..e45099490e 100644 --- a/o1vm/src/interpreters/riscv32im/constraints.rs +++ b/o1vm/src/interpreters/riscv32im/constraints.rs @@ -77,8 +77,8 @@ impl InterpreterEnv for Env { // No-op, witness only } - fn check_boolean(_x: &Self::Variable) { - // No-op, witness only + fn assert_boolean(&mut self, x: &Self::Variable) { + self.add_constraint(x.clone() * x.clone() - x.clone()); } fn add_lookup(&mut self, lookup: Lookup) { diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 8a3e02d022..0b0adab521 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -598,14 +598,8 @@ pub trait InterpreterEnv { self.add_constraint(x - y); } - /// Check that the witness value `x` is a boolean (`0` or `1`); otherwise abort. - fn check_boolean(x: &Self::Variable); - /// Assert that the value `x` is boolean, and add a constraint in the proof system. - fn assert_boolean(&mut self, x: &Self::Variable) { - Self::check_boolean(x); - self.add_constraint(x.clone() * x.clone() - x.clone()); - } + fn assert_boolean(&mut self, x: &Self::Variable); fn add_lookup(&mut self, lookup: Lookup); diff --git a/o1vm/src/interpreters/riscv32im/witness.rs b/o1vm/src/interpreters/riscv32im/witness.rs index 011185339b..256de81687 100644 --- a/o1vm/src/interpreters/riscv32im/witness.rs +++ b/o1vm/src/interpreters/riscv32im/witness.rs @@ -88,8 +88,8 @@ impl InterpreterEnv for Env { assert_eq!(*x, *y); } - fn check_boolean(x: &Self::Variable) { - if !(*x == 0 || *x == 1) { + fn assert_boolean(&mut self, x: &Self::Variable) { + if *x != 0 && *x != 1 { panic!("The value {} is not a boolean", *x); } } From 84ffa12e2e5808febd780fca0e5522bbc2a726b8 Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 16:55:52 -0500 Subject: [PATCH 54/80] adding instruction for branch lt --- .../src/interpreters/riscv32im/interpreter.rs | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 0c9207c21e..ca486910cd 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2267,7 +2267,33 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction env.set_next_instruction_pointer(addr); } SBInstruction::BranchLessThan => { - unimplemented!("BranchLessThan") + // blt: if (x[rs1] < x[rs2]) pc += sext(offset) + let local_rs1 = env.read_register(&rs1); + let local_rs2 = env.read_register(&rs2); + + let rd_scratch = env.alloc_scratch(); + + let less_than = + unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) }; + let offset = (less_than.clone()) * imm0_12 + + (Env::constant(1) - less_than.clone()) * Env::constant(4); + + let addr = { + let res_scratch = env.alloc_scratch(); + let overflow_scratch = env.alloc_scratch(); + let (res, _overflow) = unsafe { + env.add_witness( + &next_instruction_pointer, + &offset, + res_scratch, + overflow_scratch, + ) + }; + // FIXME: Requires a range check + res + }; + env.set_instruction_pointer(next_instruction_pointer); + env.set_next_instruction_pointer(addr); } SBInstruction::BranchGreaterThanEqual => { unimplemented!("BranchGreaterThanEqual") From fa494c39ba0a252ae00c4d4a8ad9cb6b2eb076cf Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 16:56:13 -0500 Subject: [PATCH 55/80] lint and format --- .../src/interpreters/riscv32im/interpreter.rs | 54 +++++++++---------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index ca486910cd..c5f8d2739d 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2267,33 +2267,33 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction env.set_next_instruction_pointer(addr); } SBInstruction::BranchLessThan => { - // blt: if (x[rs1] < x[rs2]) pc += sext(offset) - let local_rs1 = env.read_register(&rs1); - let local_rs2 = env.read_register(&rs2); - - let rd_scratch = env.alloc_scratch(); - - let less_than = - unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) }; - let offset = (less_than.clone()) * imm0_12 - + (Env::constant(1) - less_than.clone()) * Env::constant(4); - - let addr = { - let res_scratch = env.alloc_scratch(); - let overflow_scratch = env.alloc_scratch(); - let (res, _overflow) = unsafe { - env.add_witness( - &next_instruction_pointer, - &offset, - res_scratch, - overflow_scratch, - ) - }; - // FIXME: Requires a range check - res - }; - env.set_instruction_pointer(next_instruction_pointer); - env.set_next_instruction_pointer(addr); + // blt: if (x[rs1] < x[rs2]) pc += sext(offset) + let local_rs1 = env.read_register(&rs1); + let local_rs2 = env.read_register(&rs2); + + let rd_scratch = env.alloc_scratch(); + + let less_than = + unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) }; + let offset = (less_than.clone()) * imm0_12 + + (Env::constant(1) - less_than.clone()) * Env::constant(4); + + let addr = { + let res_scratch = env.alloc_scratch(); + let overflow_scratch = env.alloc_scratch(); + let (res, _overflow) = unsafe { + env.add_witness( + &next_instruction_pointer, + &offset, + res_scratch, + overflow_scratch, + ) + }; + // FIXME: Requires a range check + res + }; + env.set_instruction_pointer(next_instruction_pointer); + env.set_next_instruction_pointer(addr); } SBInstruction::BranchGreaterThanEqual => { unimplemented!("BranchGreaterThanEqual") From 7751170407b97b09f0ce65e6225eb66a315e329a Mon Sep 17 00:00:00 2001 From: svv232 Date: Mon, 23 Dec 2024 15:21:54 -0500 Subject: [PATCH 56/80] moving scratch into less-than-variable scope --- o1vm/src/interpreters/riscv32im/interpreter.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index c5f8d2739d..1d98141a92 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2271,10 +2271,10 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let rd_scratch = env.alloc_scratch(); - - let less_than = - unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) }; + let less_than = { + let rd_scratch = env.alloc_scratch(); + unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) } + }; let offset = (less_than.clone()) * imm0_12 + (Env::constant(1) - less_than.clone()) * Env::constant(4); From 4b7b1aecc645b10cf69f053f31b62961f417d5a8 Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 17:00:07 -0500 Subject: [PATCH 57/80] implementation for branch greater than or equal --- .../src/interpreters/riscv32im/interpreter.rs | 29 ++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 1d98141a92..dbfb74274a 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2296,7 +2296,34 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction env.set_next_instruction_pointer(addr); } SBInstruction::BranchGreaterThanEqual => { - unimplemented!("BranchGreaterThanEqual") + // bge: if (x[rs1] >= x[rs2]) pc += sext(offset) + let local_rs1 = env.read_register(&rs1); + let local_rs2 = env.read_register(&rs2); + + let rd_scratch = env.alloc_scratch(); + + let less_than = + unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) }; + + let offset = + less_than.clone() * Env::constant(4) + (Env::constant(1) - less_than) * imm0_12; + // greater than equal is the negation of less than + let addr = { + let res_scratch = env.alloc_scratch(); + let overflow_scratch = env.alloc_scratch(); + let (res, _overflow) = unsafe { + env.add_witness( + &next_instruction_pointer, + &offset, + res_scratch, + overflow_scratch, + ) + }; + // FIXME: Requires a range check + res + }; + env.set_instruction_pointer(next_instruction_pointer); + env.set_next_instruction_pointer(addr); } SBInstruction::BranchLessThanUnsigned => { unimplemented!("BranchLessThanUnsigned") From 5efc2f8fa5014fc4c70b1ce659c9f1aa992c65c1 Mon Sep 17 00:00:00 2001 From: svv232 Date: Mon, 23 Dec 2024 15:24:23 -0500 Subject: [PATCH 58/80] move position of less than variable into local scope --- o1vm/src/interpreters/riscv32im/interpreter.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index dbfb74274a..8435aca06f 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2300,10 +2300,10 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let rd_scratch = env.alloc_scratch(); - - let less_than = - unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) }; + let less_than = { + let rd_scratch = env.alloc_scratch(); + unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) } + }; let offset = less_than.clone() * Env::constant(4) + (Env::constant(1) - less_than) * imm0_12; From 41e439739a2940f13c82653a0a2070ad26f92865 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Thu, 26 Dec 2024 11:33:21 +0100 Subject: [PATCH 59/80] o1vm/lookup: enforce 80 limits characters --- o1vm/src/lookups.rs | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/o1vm/src/lookups.rs b/o1vm/src/lookups.rs index eff69771f3..5085e0dae8 100644 --- a/o1vm/src/lookups.rs +++ b/o1vm/src/lookups.rs @@ -25,23 +25,29 @@ pub(crate) type LookupTable = LogupTable; /// All of the possible lookup table IDs used in the zkVM #[derive(Copy, Clone, Debug, Eq, PartialEq, Hash, Ord, PartialOrd)] pub enum LookupTableIDs { - // PadLookup ID is 0 because this is the only fixed table whose first entry is not 0. - // This way, it is guaranteed that the 0 value is not always in the tables after the - // randomization with the joint combiner is applied. - /// All [1..136] values of possible padding lengths, the value 2^len, and the 5 corresponding pad suffixes with the 10*1 rule + // PadLookup ID is 0 because this is the only fixed table whose first entry + // is not 0. This way, it is guaranteed that the 0 value is not always in + // the tables after the randomization with the joint combiner is applied. + /// All [1..136] values of possible padding lengths, the value 2^len, and + /// the 5 corresponding pad suffixes with the 10*1 rule PadLookup = 0, - /// 24-row table with all possible values for round and their round constant in expanded form (in big endian) [0..=23] + /// 24-row table with all possible values for round and their round constant + /// in expanded form (in big endian) [0..=23] RoundConstantsLookup = 1, /// Values from 0 to 4 to check the number of bytes read from syscalls AtMost4Lookup = 2, - /// All values that can be stored in a byte (amortized table, better than model as RangeCheck16 (x and scaled x) + /// All values that can be stored in a byte (amortized table, better than + /// model as RangeCheck16 (x and scaled x) ByteLookup = 3, - // Read tables come first to allow indexing with the table ID for the multiplicities + // Read tables come first to allow indexing with the table ID for the + // multiplicities /// Single-column table of all values in the range [0, 2^16) RangeCheck16Lookup = 4, - /// Single-column table of 2^16 entries with the sparse representation of all values + /// Single-column table of 2^16 entries with the sparse representation of + /// all values SparseLookup = 5, - /// Dual-column table of all values in the range [0, 2^16) and their sparse representation + /// Dual-column table of all values in the range [0, 2^16) and their sparse + /// representation ResetLookup = 6, // RAM Tables @@ -123,7 +129,8 @@ impl LookupTableID for LookupTableIDs { /// Trait that creates all the fixed lookup tables used in the VM pub(crate) trait FixedLookupTables { - /// Checks whether a value is in a table and returns the position if it is or None otherwise. + /// Checks whether a value is in a table and returns the position if it is + /// or None otherwise. fn is_in_table(table: &LookupTable, value: Vec) -> Option; /// Returns the pad table fn table_pad() -> LookupTable; @@ -144,7 +151,8 @@ pub(crate) trait FixedLookupTables { impl FixedLookupTables for LookupTable { fn is_in_table(table: &LookupTable, value: Vec) -> Option { let id = table.table_id; - // In these tables, the first value of the vector is related to the index within the table. + // In these tables, the first value of the vector is related to the + // index within the table. let idx = value[0] .to_bytes() .iter() From 2aeb0fd5a3d1b07bc28f3b14b39452c25e8b5cc7 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Thu, 26 Dec 2024 11:44:09 +0100 Subject: [PATCH 60/80] o1vm/riscv32im: being strict on scope It is mostly to simplify formal verification tools generating Coq/Lean from Rust code --- .../src/interpreters/riscv32im/interpreter.rs | 39 ++++++++++++------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index e51d7574d4..bab2dcd7cf 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -1523,9 +1523,9 @@ pub fn interpret_rtype(env: &mut Env, instr: RInstruction) /* sub: x[rd] = x[rs1] - x[rs2] */ let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let underflow_scratch = env.alloc_scratch(); - let rd_scratch = env.alloc_scratch(); let local_rd = unsafe { + let underflow_scratch = env.alloc_scratch(); + let rd_scratch = env.alloc_scratch(); let (local_rd, _underflow) = env.sub_witness(&local_rs1, &local_rs2, rd_scratch, underflow_scratch); local_rd @@ -1895,11 +1895,12 @@ pub fn interpret_itype(env: &mut Env, instr: IInstruction) // addi: x[rd] = x[rs1] + sext(immediate) let local_rs1 = env.read_register(&(rs1.clone())); let local_imm = env.sign_extend(&imm, 12); - let overflow_scratch = env.alloc_scratch(); - let rd_scratch = env.alloc_scratch(); - let local_rd = unsafe { - let (local_rd, _overflow) = - env.add_witness(&local_rs1, &local_imm, rd_scratch, overflow_scratch); + let local_rd = { + let overflow_scratch = env.alloc_scratch(); + let rd_scratch = env.alloc_scratch(); + let (local_rd, _overflow) = unsafe { + env.add_witness(&local_rs1, &local_imm, rd_scratch, overflow_scratch) + }; local_rd }; env.write_register(&rd, local_rd); @@ -1910,8 +1911,10 @@ pub fn interpret_itype(env: &mut Env, instr: IInstruction) // xori: x[rd] = x[rs1] ^ sext(immediate) let local_rs1 = env.read_register(&rs1); let local_imm = env.sign_extend(&imm, 12); - let rd_scratch = env.alloc_scratch(); - let local_rd = unsafe { env.xor_witness(&local_rs1, &local_imm, rd_scratch) }; + let local_rd = { + let rd_scratch = env.alloc_scratch(); + unsafe { env.xor_witness(&local_rs1, &local_imm, rd_scratch) } + }; env.write_register(&rd, local_rd); env.set_instruction_pointer(next_instruction_pointer.clone()); env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32)); @@ -1920,8 +1923,10 @@ pub fn interpret_itype(env: &mut Env, instr: IInstruction) // ori: x[rd] = x[rs1] | sext(immediate) let local_rs1 = env.read_register(&rs1); let local_imm = env.sign_extend(&imm, 12); - let rd_scratch = env.alloc_scratch(); - let local_rd = unsafe { env.or_witness(&local_rs1, &local_imm, rd_scratch) }; + let local_rd = { + let rd_scratch = env.alloc_scratch(); + unsafe { env.or_witness(&local_rs1, &local_imm, rd_scratch) } + }; env.write_register(&rd, local_rd); env.set_instruction_pointer(next_instruction_pointer.clone()); env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32)); @@ -1930,8 +1935,10 @@ pub fn interpret_itype(env: &mut Env, instr: IInstruction) // andi: x[rd] = x[rs1] & sext(immediate) let local_rs1 = env.read_register(&rs1); let local_imm = env.sign_extend(&imm, 12); - let rd_scratch = env.alloc_scratch(); - let local_rd = unsafe { env.and_witness(&local_rs1, &local_imm, rd_scratch) }; + let local_rd = { + let rd_scratch = env.alloc_scratch(); + unsafe { env.and_witness(&local_rs1, &local_imm, rd_scratch) } + }; env.write_register(&rd, local_rd); env.set_instruction_pointer(next_instruction_pointer.clone()); env.set_next_instruction_pointer(next_instruction_pointer + Env::constant(4u32)); @@ -2438,8 +2445,10 @@ pub fn interpret_utype(env: &mut Env, instr: UInstruction) UInstruction::LoadUpperImmediate => { // lui: x[rd] = sext(immediate[31:12] << 12) let local_imm = { - let pos = env.alloc_scratch(); - let shifted_imm = unsafe { env.shift_left(&imm, &Env::constant(12), pos) }; + let shifted_imm = { + let pos = env.alloc_scratch(); + unsafe { env.shift_left(&imm, &Env::constant(12), pos) } + }; env.sign_extend(&shifted_imm, 32) }; env.write_register(&rd, local_imm); From ff890834f5d004c2f158d89abdcf3f4955a31d42 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Thu, 26 Dec 2024 11:50:04 +0100 Subject: [PATCH 61/80] o1vm/riscv32im: place correctly the unsafe keyword --- .../src/interpreters/riscv32im/interpreter.rs | 50 ++++++++++--------- 1 file changed, 26 insertions(+), 24 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index bab2dcd7cf..ad029b0a81 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -1507,11 +1507,12 @@ pub fn interpret_rtype(env: &mut Env, instr: RInstruction) // add: x[rd] = x[rs1] + x[rs2] let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let overflow_scratch = env.alloc_scratch(); - let rd_scratch = env.alloc_scratch(); - let local_rd = unsafe { - let (local_rd, _overflow) = - env.add_witness(&local_rs1, &local_rs2, rd_scratch, overflow_scratch); + let local_rd = { + let overflow_scratch = env.alloc_scratch(); + let rd_scratch = env.alloc_scratch(); + let (local_rd, _overflow) = unsafe { + env.add_witness(&local_rs1, &local_rs2, rd_scratch, overflow_scratch) + }; local_rd }; env.write_register(&rd, local_rd); @@ -1523,11 +1524,12 @@ pub fn interpret_rtype(env: &mut Env, instr: RInstruction) /* sub: x[rd] = x[rs1] - x[rs2] */ let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let local_rd = unsafe { + let local_rd = { let underflow_scratch = env.alloc_scratch(); let rd_scratch = env.alloc_scratch(); - let (local_rd, _underflow) = - env.sub_witness(&local_rs1, &local_rs2, rd_scratch, underflow_scratch); + let (local_rd, _underflow) = unsafe { + env.sub_witness(&local_rs1, &local_rs2, rd_scratch, underflow_scratch) + }; local_rd }; env.write_register(&rd, local_rd); @@ -1539,9 +1541,9 @@ pub fn interpret_rtype(env: &mut Env, instr: RInstruction) /* sll: x[rd] = x[rs1] << x[rs2] */ let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let local_rd = unsafe { + let local_rd = { let rd_scratch = env.alloc_scratch(); - env.shift_left(&local_rs1, &local_rs2, rd_scratch) + unsafe { env.shift_left(&local_rs1, &local_rs2, rd_scratch) } }; env.write_register(&rd, local_rd); @@ -1552,9 +1554,9 @@ pub fn interpret_rtype(env: &mut Env, instr: RInstruction) /* slt: x[rd] = (x[rs1] < x[rs2]) ? 1 : 0 */ let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let local_rd = unsafe { + let local_rd = { let rd_scratch = env.alloc_scratch(); - env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) + unsafe { env.test_less_than_signed(&local_rs1, &local_rs2, rd_scratch) } }; env.write_register(&rd, local_rd); @@ -1565,9 +1567,9 @@ pub fn interpret_rtype(env: &mut Env, instr: RInstruction) /* sltu: x[rd] = (x[rs1] < (u)x[rs2]) ? 1 : 0 */ let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let local_rd = unsafe { + let local_rd = { let pos = env.alloc_scratch(); - env.test_less_than(&local_rs1, &local_rs2, pos) + unsafe { env.test_less_than(&local_rs1, &local_rs2, pos) } }; env.write_register(&rd, local_rd); @@ -1578,9 +1580,9 @@ pub fn interpret_rtype(env: &mut Env, instr: RInstruction) /* xor: x[rd] = x[rs1] ^ x[rs2] */ let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let local_rd = unsafe { + let local_rd = { let pos = env.alloc_scratch(); - env.xor_witness(&local_rs1, &local_rs2, pos) + unsafe { env.xor_witness(&local_rs1, &local_rs2, pos) } }; env.write_register(&rd, local_rd); @@ -1591,9 +1593,9 @@ pub fn interpret_rtype(env: &mut Env, instr: RInstruction) /* srl: x[rd] = x[rs1] >> x[rs2] */ let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let local_rd = unsafe { + let local_rd = { let pos = env.alloc_scratch(); - env.shift_right(&local_rs1, &local_rs2, pos) + unsafe { env.shift_right(&local_rs1, &local_rs2, pos) } }; env.write_register(&rd, local_rd); @@ -1604,9 +1606,9 @@ pub fn interpret_rtype(env: &mut Env, instr: RInstruction) /* sra: x[rd] = x[rs1] >> x[rs2] */ let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let local_rd = unsafe { + let local_rd = { let pos = env.alloc_scratch(); - env.shift_right_arithmetic(&local_rs1, &local_rs2, pos) + unsafe { env.shift_right_arithmetic(&local_rs1, &local_rs2, pos) } }; env.write_register(&rd, local_rd); @@ -1617,9 +1619,9 @@ pub fn interpret_rtype(env: &mut Env, instr: RInstruction) /* or: x[rd] = x[rs1] | x[rs2] */ let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let local_rd = unsafe { + let local_rd = { let pos = env.alloc_scratch(); - env.or_witness(&local_rs1, &local_rs2, pos) + unsafe { env.or_witness(&local_rs1, &local_rs2, pos) } }; env.write_register(&rd, local_rd); @@ -1630,9 +1632,9 @@ pub fn interpret_rtype(env: &mut Env, instr: RInstruction) /* and: x[rd] = x[rs1] & x[rs2] */ let local_rs1 = env.read_register(&rs1); let local_rs2 = env.read_register(&rs2); - let local_rd = unsafe { + let local_rd = { let pos = env.alloc_scratch(); - env.and_witness(&local_rs1, &local_rs2, pos) + unsafe { env.and_witness(&local_rs1, &local_rs2, pos) } }; env.write_register(&rd, local_rd); From 51d6d2a85fd11c20887ac67a4dab1bec9a1b70ca Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Thu, 26 Dec 2024 12:01:07 +0100 Subject: [PATCH 62/80] o1vm/riscv32im: decrease the number of required columns Try with 38, and fibonacci will fail. It might need to be increased in the future if you see that the current testsuite doesn't cover the whole instruction set. --- o1vm/src/interpreters/riscv32im/mod.rs | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/mod.rs b/o1vm/src/interpreters/riscv32im/mod.rs index 59c855694b..ed6dd1b38a 100644 --- a/o1vm/src/interpreters/riscv32im/mod.rs +++ b/o1vm/src/interpreters/riscv32im/mod.rs @@ -1,7 +1,5 @@ /// The minimal number of columns required for the VM -// FIXME: the value will be updated when the interpreter is fully -// implemented. Using a small value for now. -pub const SCRATCH_SIZE: usize = 80; +pub const SCRATCH_SIZE: usize = 39; /// Number of instructions in the ISA pub const INSTRUCTION_SET_SIZE: usize = 48; From 43c4dfa3075b7fa3d88fb5e0d811ae83d0223426 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Fri, 27 Dec 2024 13:01:56 +0100 Subject: [PATCH 63/80] o1vm/riscv32im: implement jal --- o1vm/resources/programs/riscv32im/bin/jal | Bin 0 -> 464 bytes o1vm/resources/programs/riscv32im/src/jal.S | 25 +++++++ .../src/interpreters/riscv32im/interpreter.rs | 69 ++++++++++++++++-- o1vm/tests/test_riscv_elf.rs | 17 +++++ 4 files changed, 103 insertions(+), 8 deletions(-) create mode 100755 o1vm/resources/programs/riscv32im/bin/jal create mode 100644 o1vm/resources/programs/riscv32im/src/jal.S diff --git a/o1vm/resources/programs/riscv32im/bin/jal b/o1vm/resources/programs/riscv32im/bin/jal new file mode 100755 index 0000000000000000000000000000000000000000..4b662e82bf985d6fc7771dad29581bc0af8c1734 GIT binary patch literal 464 zcma)2F;2rk5F9&%L`nm?2Y^IFWhF-nS_-HrD5$Y)$AOb#INe<$6d{55LO#F)=y(`N zJRr=*Txc0pI--S#g{8m?NUkAqmrsm?Z2g-N6&6poblBH$u(`) zEl#x2c9b{T4)a3XR9l@-q%2M4oy?bJTHjYSgY-=^pN+&6Mf1>_ne!DLkoh|wTqsIp zp?(a=Hs8vM5S%IJp_YI6F9rCeNy(hX;@@Wai21ayA)+^ivb5m I+wL#-1Jcw#761SM literal 0 HcmV?d00001 diff --git a/o1vm/resources/programs/riscv32im/src/jal.S b/o1vm/resources/programs/riscv32im/src/jal.S new file mode 100644 index 0000000000..191cdfbb3e --- /dev/null +++ b/o1vm/resources/programs/riscv32im/src/jal.S @@ -0,0 +1,25 @@ +.section .text +.global _start + +# t0 <- t0 + t1 +add_t0_t1: + add t0, t0, t1 + ret + +_start: + li t0, 5 + li t1, 7 + # Could be jalr + # jal without offset + jal ra, add_t0_t1 + + # exit + li a0, 0 + li a1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 42 + ecall diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index ad029b0a81..91f100e911 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2482,14 +2482,30 @@ pub fn interpret_utype(env: &mut Env, instr: UInstruction) /// Interpret an UJ-type instruction. /// The encoding of an UJ-type instruction is as follows: /// ```text -/// | 31 12 | 11 7 | 6 0 | -/// | immediate | rd | opcode | +/// | 31 12 | 11 7 | 6 0 | +/// | imm[20|10:1|11|19:12] | rd | opcode | /// ``` /// Following the documentation found /// [here](https://www.cs.cornell.edu/courses/cs3410/2024fa/assignments/cpusim/riscv-instructions.pdf) +/// +/// The interpretation of the immediate is as follow: +/// ```text +/// imm_20 = instruction[31] +/// imm_10_1 = instruction[30..21] +/// imm_11 = instruction[20] +/// imm_19_12 = instruction[19..12] +/// +/// imm = imm_20 << 19 + +/// imm_19_12 << 11 + +/// imm_11 << 10 + +/// imm_10_1 +/// +/// # The immediate is then sign-extended. The sign-extension is in the bit imm20 +/// imm = imm << 1 +/// ``` pub fn interpret_ujtype(env: &mut Env, instr: UJInstruction) { let instruction_pointer = env.get_instruction_pointer(); - let _next_instruction_pointer = env.get_next_instruction_pointer(); + let next_instruction_pointer = env.get_next_instruction_pointer(); let instruction = { let v0 = env.read_memory(&instruction_pointer); @@ -2514,18 +2530,55 @@ pub fn interpret_ujtype(env: &mut Env, instr: UJInstruction }; env.range_check8(&rd, 5); - // FIXME: trickier - let _imm = { + let imm20 = { let pos = env.alloc_scratch(); - unsafe { env.bitmask(&instruction, 32, 12, pos) } + unsafe { env.bitmask(&instruction, 32, 31, pos) } + }; + env.assert_boolean(&imm20); + + let imm10_1 = { + let pos = env.alloc_scratch(); + unsafe { env.bitmask(&instruction, 31, 21, pos) } + }; + env.range_check16(&imm10_1, 10); + + let imm11 = { + let pos = env.alloc_scratch(); + unsafe { env.bitmask(&instruction, 21, 20, pos) } + }; + env.assert_boolean(&imm11); + + let imm19_12 = { + let pos = env.alloc_scratch(); + unsafe { env.bitmask(&instruction, 20, 12, pos) } + }; + env.range_check8(&imm19_12, 8); + + let offset = { + imm10_1.clone() * Env::constant(1 << 1) + + imm11.clone() * Env::constant(1 << 11) + + imm19_12.clone() * Env::constant(1 << 12) + + imm20.clone() * Env::constant(1 << 20) }; // FIXME: check correctness of decomposition + match instr { UJInstruction::JumpAndLink => { - unimplemented!("JumpAndLink") + let offset = env.sign_extend(&offset, 21); + let new_addr = { + let res_scratch = env.alloc_scratch(); + let overflow_scratch = env.alloc_scratch(); + let (res, _overflow) = unsafe { + env.add_witness(&instruction_pointer, &offset, res_scratch, overflow_scratch) + }; + res + }; + env.write_register(&rd, next_instruction_pointer.clone()); + env.set_instruction_pointer(new_addr.clone()); + env.set_next_instruction_pointer(new_addr + Env::constant(4u32)); } - }; + } } pub fn interpret_syscall(env: &mut Env, _instr: SyscallInstruction) { diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 1046d2198b..d73e008b8e 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -430,3 +430,20 @@ fn test_mul_overflow() { assert_eq!(witness.registers[T2], 276447232); } + +#[test] +fn test_jal() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/jal", + )); + let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + while !witness.halt { + witness.step(); + } + + assert_eq!(witness.registers[T0], 12); + assert_eq!(witness.registers[T1], 7); +} From 5a9e9af8283ffadb11cefc10cb389f2afc74f8d6 Mon Sep 17 00:00:00 2001 From: oliveredget <188809800+oliveredget@users.noreply.github.com> Date: Tue, 31 Dec 2024 08:22:02 +0800 Subject: [PATCH 64/80] Fix typo book/src/pickles/diagrams.md --- book/src/pickles/diagrams.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/book/src/pickles/diagrams.md b/book/src/pickles/diagrams.md index 63783603a6..a2728c7c10 100644 --- a/book/src/pickles/diagrams.md +++ b/book/src/pickles/diagrams.md @@ -7,7 +7,7 @@ The legend of the diagrams is quite straightforward: - `MFNStep`/`MFNWrap` is an abbreviation from `MessagesForNextStep` and `MessagesForNextWrap` that is used for brevity. Most other datatypes are exactly the same as in the codebase. - The blue boxes are computations. Sometimes, when the computation is trivial or only vaguely indicated, it is denoted as a text sign directly on an arrow. - Arrows are blue by default and denote moving a piece of data from one place to another with no (or very little) change. Light blue arrows are denoting witness query that is implemented through the `handler` mechanism. The "chicken foot" connector means that this arrow accesses just one field in an array: such an arrow could connect e.g. a input field of type `old_a: A` in a structure `Vec<(A,B)>` to an output `new_a: A`, which just means that we are inside a `for` loop and this computation is done for all the elemnts in the vector/array. -- Colour of the field is sometimes introduced and denotes how many steps ago was this piece of data created. The absense of the colour means either that (1) the data structure contains different subfields of different origin, or that (2) it was not coloured but it could be. The colours are assigned according to the following convention: +- Colour of the field is sometimes introduced and denotes how many steps ago was this piece of data created. The absence of the colour means either that (1) the data structure contains different subfields of different origin, or that (2) it was not coloured but it could be. The colours are assigned according to the following convention: ![](./pickles_structure_legend_1.svg) From 33094e9858d6f39ecaeb3df520bd6eba41e91561 Mon Sep 17 00:00:00 2001 From: oliveredget <188809800+oliveredget@users.noreply.github.com> Date: Tue, 31 Dec 2024 08:22:08 +0800 Subject: [PATCH 65/80] Fix typo book/src/pickles/overview.md --- book/src/pickles/overview.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/book/src/pickles/overview.md b/book/src/pickles/overview.md index 7d2d8bdb7a..7ec7f1b98a 100644 --- a/book/src/pickles/overview.md +++ b/book/src/pickles/overview.md @@ -27,4 +27,4 @@ We note that the Step circuit may repeat items 2-3 to handle the following case: The accumulator is an abstraction introduced for the purpose of this diagram. In practice, each kimchi proof consists of (1) commitments to polynomials, (2) evaluations of them, (3) and the opening proof. What we refer to as accumulator here is actually the commitment inside the opening proof. It is called `sg` in the implementation and is semantically a polynomial commitment to `h(X)` (`b_poly` in the code) --- the poly-sized polynomial that is built from IPA challenges. It's a very important polynomial -- it can be evaluated in log time, but the commitment verification takes poly time, so the fact that `sg` is a commitment to `h(X)` is never proven inside the circuit. For more details, see [Proof-Carrying Data from Accumulation Schemes](https://eprint.iacr.org/2020/499.pdf), Appendix A.2, where `sg` is called `U`. -In pickles, what we do is that we "absorb" this commitment `sg` from the previous step while creating a new proof. That is, for example, Step 1 will produce this commitment that is denoted as `acc1` on the diagram, as part of its opening proof, and Step 2 will absorb this commitment. And this "absorbtion" is what Wrap 2 will prove (and, partially, Step 3 will also refer to the challenges used to build `acc1`, but this detail is completely avoided in this overview). In the end, `acc2` will be the result of Step 2, so in a way `acc2` "aggregates" `acc1` which somewhat justifies the language used. +In pickles, what we do is that we "absorb" this commitment `sg` from the previous step while creating a new proof. That is, for example, Step 1 will produce this commitment that is denoted as `acc1` on the diagram, as part of its opening proof, and Step 2 will absorb this commitment. And this "absorption" is what Wrap 2 will prove (and, partially, Step 3 will also refer to the challenges used to build `acc1`, but this detail is completely avoided in this overview). In the end, `acc2` will be the result of Step 2, so in a way `acc2` "aggregates" `acc1` which somewhat justifies the language used. From a1e6103cdb7d35336b3ec2f36f538014be89667f Mon Sep 17 00:00:00 2001 From: oliveredget <188809800+oliveredget@users.noreply.github.com> Date: Tue, 31 Dec 2024 08:22:14 +0800 Subject: [PATCH 66/80] Fix typo book/src/snarky/kimchi-backend.md --- book/src/snarky/kimchi-backend.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/book/src/snarky/kimchi-backend.md b/book/src/snarky/kimchi-backend.md index 7ab2e38bb6..5035dc8dec 100644 --- a/book/src/snarky/kimchi-backend.md +++ b/book/src/snarky/kimchi-backend.md @@ -107,7 +107,7 @@ It is the role of the `add_constrain` logic to enforce that at this point consta This is done by adding enough generic gates (using the `reduce_lincom()` or `reduce_to_var()` functions). ```admonish -This is a remnant of an optimization targetting R1CS (in which additions are for free). +This is a remnant of an optimization targeting R1CS (in which additions are for free). An issue with this approach is the following: imagine that two circuit variables are created from the same circuit variable, imagine also that the original circuit variable contained a long AST, then both variables might end up creating the same constraints to convert that AST. Currently, snarkyjs and pickles expose a `seal()` function that allows you to reduce this issue, at the cost of some manual work and mental tracking on the developer. We should probably get rid of this, while making sure that we can continue to optimize generic gates @@ -142,7 +142,7 @@ The `finalization()` function of the kimchi backend does the following: * add as many generic rows as there are public inputs. * construct the permutation -* computes a cache of the circuit (TODO: this is so unecessary) +* computes a cache of the circuit (TODO: this is so unnecessary) * and other things that are not that important ## Witness generation From 2a6085dfd3f52855d4c117435eebab0ff09dba63 Mon Sep 17 00:00:00 2001 From: oliveredget <188809800+oliveredget@users.noreply.github.com> Date: Tue, 31 Dec 2024 08:22:20 +0800 Subject: [PATCH 67/80] Fix typo book/src/snarky/snarky-wrapper.md --- book/src/snarky/snarky-wrapper.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/book/src/snarky/snarky-wrapper.md b/book/src/snarky/snarky-wrapper.md index 9f652da76b..4a52fbaeb2 100644 --- a/book/src/snarky/snarky-wrapper.md +++ b/book/src/snarky/snarky-wrapper.md @@ -48,7 +48,7 @@ The wrapper is designed to be used in different ways, depending on the fields se ```admonish Ideally, we would like to only run this once and obtain a result that's an immutable compiled artifact. -Currently, `public_input`, `private_input`, `eval_constriants`, `next_var`, and `mode` all need to be mutable. +Currently, `public_input`, `private_input`, `eval_constraints`, `next_var`, and `mode` all need to be mutable. In the future these should be passed as arguments to functions, and should not exist in the state. ``` From 8b4a231f17b0d11e8942306a8da6c8536a50af3e Mon Sep 17 00:00:00 2001 From: oliveredget <188809800+oliveredget@users.noreply.github.com> Date: Tue, 31 Dec 2024 08:22:26 +0800 Subject: [PATCH 68/80] Fix typo book/src/snarky/vars.md --- book/src/snarky/vars.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/book/src/snarky/vars.md b/book/src/snarky/vars.md index 41fabe82fd..69dced8d78 100644 --- a/book/src/snarky/vars.md +++ b/book/src/snarky/vars.md @@ -18,7 +18,7 @@ where /// A constant. Constant(F), - /// A variable that can be refered to via a `usize`. + /// A variable that can be referred to via a `usize`. Var(usize), /// The addition of two other [FieldVar]s. @@ -65,7 +65,7 @@ In some situations, we might not want to constrain the In general, a circuit variable only gets constrained by an assertion call like `assert` or `assert_equals`. When variables are added together, or scaled, they do not directly get constrained. -This is due to optimizations targetting R1CS (which we don't support anymore) that were implemented in the original snarky library, and that we have kept in snarky-rs. +This is due to optimizations targeting R1CS (which we don't support anymore) that were implemented in the original snarky library, and that we have kept in snarky-rs. Imagine the following example: From fc5755dabe92873ab1e73aff41755e8886187eaf Mon Sep 17 00:00:00 2001 From: oliveredget <188809800+oliveredget@users.noreply.github.com> Date: Tue, 31 Dec 2024 08:22:32 +0800 Subject: [PATCH 69/80] Fix typo o1vm/README.md --- o1vm/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/o1vm/README.md b/o1vm/README.md index d8dbd5d3d0..9e728c4ad9 100644 --- a/o1vm/README.md +++ b/o1vm/README.md @@ -55,7 +55,7 @@ gvm use go1.21s ``` You also will need to install the [Foundry](https://getfoundry.sh/) toolkit -in order to utilize applicaitons like `cast`. +in order to utilize applications like `cast`. ```shell foundryup From 9b73da792263362fdc63b2523e439967f0a6e039 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Thu, 19 Dec 2024 19:13:15 +0100 Subject: [PATCH 70/80] gitignore: start ignoring temporary obj files for o1vm --- .gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index c6f644327e..75a56fa0f0 100644 --- a/.gitignore +++ b/.gitignore @@ -42,4 +42,5 @@ state.json # Directory for the RISC-V 32bits toolchain _riscv32-gnu-toolchain -o1vm/resources/programs/riscv32im/bin/*.o \ No newline at end of file +o1vm/resources/programs/riscv32im/bin/*.o +o1vm/resources/programs/mips/bin/*.o From 5f773593d01d3108f16717763f57b54b1082642d Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 18:45:24 +0100 Subject: [PATCH 71/80] Makefile: add target to build all MIPS programs from Optimism And change the section .test into .text --- Makefile | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index c86e935ea1..41a35df28a 100644 --- a/Makefile +++ b/Makefile @@ -18,6 +18,13 @@ O1VM_RISCV32IM_BIN_DIR = ${O1VM_RESOURCES_PATH}/riscv32im/bin O1VM_RISCV32IM_BIN_FILES = $(patsubst ${O1VM_RISCV32IM_SOURCE_DIR}/%.S,${O1VM_RISCV32IM_BIN_DIR}/%.o,${O1VM_RISCV32IM_SOURCE_FILES}) RISCV32_AS_FLAGS = --warn --fatal-warnings +OPTIMISM_MIPS_SOURCE_DIR = $(shell pwd)/o1vm/ethereum-optimism/cannon/mipsevm/open_mips_tests/test +OPTIMISM_MIPS_SOURCE_FILES = $(wildcard ${OPTIMISM_MIPS_SOURCE_DIR}/*.asm) +O1VM_MIPS_SOURCE_DIR = ${O1VM_RESOURCES_PATH}/mips/src +O1VM_MIPS_SOURCE_FILES = $(patsubst ${OPTIMISM_MIPS_SOURCE_DIR}/%.asm,${O1VM_MIPS_SOURCE_DIR}/%.asm,${OPTIMISM_MIPS_SOURCE_FILES}) +O1VM_MIPS_BIN_DIR = ${O1VM_RESOURCES_PATH}/mips/bin +O1VM_MIPS_BIN_FILES = $(patsubst ${O1VM_MIPS_SOURCE_DIR}/%.asm,${O1VM_MIPS_BIN_DIR}/%.o,${O1VM_MIPS_SOURCE_FILES}) + # Default target all: release @@ -166,7 +173,31 @@ ${O1VM_RISCV32IM_BIN_DIR}/%.o: ${O1VM_RISCV32IM_SOURCE_DIR}/%.S ${RISCV32_TOOLCHAIN_PATH}/build/bin/riscv32-unknown-elf-ld -s -o $(basename $@) $@ @echo "" +build-mips-programs: ${O1VM_MIPS_SOURCE_FILES} ${O1VM_MIPS_BIN_FILES} ## Build all MIPS programs written for the o1vm + +${O1VM_MIPS_SOURCE_DIR}/%.asm: ${OPTIMISM_MIPS_SOURCE_DIR}/%.asm + @mkdir -p ${O1VM_MIPS_SOURCE_DIR} + @echo "Transforming $< to $@, making it compatible for o1vm" + @sed \ + -e '/\.balign 4/d' \ + -e '/\.set\s*noreorder/d' \ + -e '/\.ent\s*test/d' \ + -e '/\.end test/d' \ + -e 's/\.section .test, "x"/.section .text/' \ + -e 's/\s*\.section .text/.section .text/' \ + -e 's/\.global test/.global __start/' \ + -e "s/^\s*\.global __start/.global __start/" \ + -e "s/test\:/__start:/" \ + -e "/\.global __start/a\\" \ + $< > $@ + +${O1VM_MIPS_BIN_DIR}/%.o: ${O1VM_MIPS_SOURCE_DIR}/%.asm + @echo "Building the MIPS binary: $(basename $@) using $<" + @mkdir -p ${O1VM_MIPS_BIN_DIR} + @mips-linux-gnu-as -defsym big_endian=1 -march=mips32r2 -o $@ $< + @mips-linux-gnu-ld -s -o $(basename $@) $@ + fclean: clean ## Clean the tooling artefacts in addition to running clean rm -rf ${RISCV32_TOOLCHAIN_PATH} -.PHONY: all setup install-test-deps clean build release test-doc test-doc-with-coverage test test-with-coverage test-heavy test-heavy-with-coverage test-all test-all-with-coverage nextest nextest-with-coverage nextest-heavy nextest-heavy-with-coverage nextest-all nextest-all-with-coverage format lint generate-test-coverage-report generate-doc setup-riscv32-toolchain help fclean build-riscv32-programs +.PHONY: all setup install-test-deps clean build release test-doc test-doc-with-coverage test test-with-coverage test-heavy test-heavy-with-coverage test-all test-all-with-coverage nextest nextest-with-coverage nextest-heavy nextest-heavy-with-coverage nextest-all nextest-all-with-coverage format lint generate-test-coverage-report generate-doc setup-riscv32-toolchain help fclean build-riscv32-programs build-mips-programs From 2637499c5d915f383e2dc186a71b7e9a489ee36e Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 19:13:26 +0100 Subject: [PATCH 72/80] Makefile: clean MIPS bin dir when clean called --- Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 41a35df28a..43f57c5021 100644 --- a/Makefile +++ b/Makefile @@ -54,8 +54,9 @@ install-test-deps: ## Install test dependencies clean: ## Clean the project - cargo clean - rm -rf $(O1VM_RISCV32IM_BIN_FILES) + @cargo clean + @rm -rf $(O1VM_RISCV32IM_BIN_FILES) + @rm -rf $(O1VM_MIPS_BIN_DIR) build: ## Build the project From 22649ee9bb547e77c135d2cbee3cb99558b963b2 Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Thu, 2 Jan 2025 11:51:44 +0100 Subject: [PATCH 73/80] o1vm/riscv32im: start checking the nb of csts per instruction --- o1vm/src/interpreters/riscv32im/tests.rs | 185 ++++++++++++++++++++++- 1 file changed, 182 insertions(+), 3 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/tests.rs b/o1vm/src/interpreters/riscv32im/tests.rs index fcb923ed90..08c1634c5b 100644 --- a/o1vm/src/interpreters/riscv32im/tests.rs +++ b/o1vm/src/interpreters/riscv32im/tests.rs @@ -2,14 +2,14 @@ use super::{registers::Registers, witness::Env, INSTRUCTION_SET_SIZE, PAGE_SIZE, use crate::interpreters::riscv32im::{ constraints, interpreter::{ - IInstruction, Instruction, InterpreterEnv, MInstruction, RInstruction, SBInstruction, - SInstruction, SyscallInstruction, UInstruction, UJInstruction, + interpret_instruction, IInstruction, Instruction, InterpreterEnv, MInstruction, + RInstruction, SBInstruction, SInstruction, SyscallInstruction, UInstruction, UJInstruction, }, }; use ark_ff::Zero; use mina_curves::pasta::Fp; use rand::{CryptoRng, Rng, RngCore}; -use strum::EnumCount; +use strum::{EnumCount, IntoEnumIterator}; // Sanity check that we have as many selector as we have instructions #[test] @@ -735,3 +735,182 @@ pub fn test_instruction_decoding_remu() { let (opcode, _instruction) = env.decode_instruction(); assert_eq!(opcode, Instruction::MType(MInstruction::Remu)); } + +#[test] +fn test_regression_number_of_constraints_per_instruction() { + let mut env = constraints::Env::::default(); + let unimplemented_instructions = [ + Instruction::RType(RInstruction::Fence), + Instruction::RType(RInstruction::FenceI), + ]; + let instructions = Instruction::iter() + .flat_map(|x| x.into_iter()) + .filter(|x| !unimplemented_instructions.contains(x)); + for instruction in instructions { + interpret_instruction(&mut env, instruction); + println!("{:?}", instruction); + match instruction { + Instruction::RType(rtype) => match rtype { + RInstruction::Add => { + assert_eq!(env.constraints.len(), 4); + } + RInstruction::Sub => { + assert_eq!(env.constraints.len(), 4); + } + RInstruction::ShiftLeftLogical => { + assert_eq!(env.constraints.len(), 4); + } + RInstruction::SetLessThan => { + assert_eq!(env.constraints.len(), 4); + } + RInstruction::SetLessThanUnsigned => { + assert_eq!(env.constraints.len(), 4); + } + RInstruction::Xor => { + assert_eq!(env.constraints.len(), 4); + } + RInstruction::ShiftRightLogical => { + assert_eq!(env.constraints.len(), 4); + } + RInstruction::ShiftRightArithmetic => { + assert_eq!(env.constraints.len(), 4); + } + RInstruction::Or => { + assert_eq!(env.constraints.len(), 4); + } + RInstruction::And => { + assert_eq!(env.constraints.len(), 4); + } + RInstruction::Fence => { + unimplemented!("Fence should not be implemented"); + } + RInstruction::FenceI => { + unimplemented!("FenceI should not be implemented"); + } + }, + Instruction::IType(itype) => match itype { + IInstruction::LoadByte => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::LoadHalf => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::LoadWord => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::LoadByteUnsigned => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::LoadHalfUnsigned => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::AddImmediate => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::SetLessThanImmediate => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::SetLessThanImmediateUnsigned => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::XorImmediate => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::OrImmediate => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::AndImmediate => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::ShiftLeftLogicalImmediate => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::ShiftRightLogicalImmediate => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::ShiftRightArithmeticImmediate => { + assert_eq!(env.constraints.len(), 5); + } + IInstruction::JumpAndLinkRegister => { + assert_eq!(env.constraints.len(), 5); + } + }, + Instruction::SType(stype) => match stype { + SInstruction::StoreByte => { + assert_eq!(env.constraints.len(), 1); + } + SInstruction::StoreHalf => { + assert_eq!(env.constraints.len(), 1); + } + SInstruction::StoreWord => { + assert_eq!(env.constraints.len(), 1); + } + }, + Instruction::SBType(sbtype) => match sbtype { + SBInstruction::BranchEq => { + assert_eq!(env.constraints.len(), 5); + } + SBInstruction::BranchNeq => { + assert_eq!(env.constraints.len(), 5); + } + SBInstruction::BranchLessThan => { + assert_eq!(env.constraints.len(), 3); + } + SBInstruction::BranchLessThanUnsigned => { + assert_eq!(env.constraints.len(), 3); + } + SBInstruction::BranchGreaterThanEqual => { + assert_eq!(env.constraints.len(), 3); + } + SBInstruction::BranchGreaterThanEqualUnsigned => { + assert_eq!(env.constraints.len(), 3); + } + }, + Instruction::UType(utype) => match utype { + UInstruction::LoadUpperImmediate => { + assert_eq!(env.constraints.len(), 4); + } + UInstruction::AddUpperImmediate => { + assert_eq!(env.constraints.len(), 4); + } + }, + Instruction::UJType(ujtype) => match ujtype { + UJInstruction::JumpAndLink => { + assert_eq!(env.constraints.len(), 5); + } + }, + Instruction::SyscallType(syscall) => match syscall { + SyscallInstruction::SyscallSuccess => { + assert_eq!(env.constraints.len(), 0); + } + }, + Instruction::MType(mtype) => match mtype { + MInstruction::Mul => { + assert_eq!(env.constraints.len(), 4); + } + MInstruction::Mulh => { + assert_eq!(env.constraints.len(), 4); + } + MInstruction::Mulhsu => { + assert_eq!(env.constraints.len(), 4); + } + MInstruction::Mulhu => { + assert_eq!(env.constraints.len(), 4); + } + MInstruction::Div => { + assert_eq!(env.constraints.len(), 4); + } + MInstruction::Divu => { + assert_eq!(env.constraints.len(), 4); + } + MInstruction::Rem => { + assert_eq!(env.constraints.len(), 4); + } + MInstruction::Remu => { + assert_eq!(env.constraints.len(), 4); + } + }, + } + env.reset() + } +} From f3737a67b383e324c3b9f50cf4d3db215c2dd96e Mon Sep 17 00:00:00 2001 From: Danny Willems Date: Mon, 23 Dec 2024 18:46:20 +0100 Subject: [PATCH 74/80] Run make build-mips-programs --- o1vm/resources/programs/mips/bin/add | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/addi | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/addiu | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/addu | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/and | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/andi | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/beq | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/bgez | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/bgtz | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/blez | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/bltz | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/bne | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/brk | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/clo | Bin 0 -> 668 bytes o1vm/resources/programs/mips/bin/clone | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/clz | Bin 0 -> 668 bytes o1vm/resources/programs/mips/bin/div | Bin 0 -> 668 bytes o1vm/resources/programs/mips/bin/divu | Bin 0 -> 636 bytes o1vm/resources/programs/mips/bin/exit_group | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/fcntl | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/j | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/jal | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/jalr | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/jr | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/lb | Bin 0 -> 780 bytes o1vm/resources/programs/mips/bin/lbu | Bin 0 -> 652 bytes o1vm/resources/programs/mips/bin/lh | Bin 0 -> 684 bytes o1vm/resources/programs/mips/bin/lhu | Bin 0 -> 668 bytes o1vm/resources/programs/mips/bin/lui | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/lw | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/lwl | Bin 0 -> 700 bytes o1vm/resources/programs/mips/bin/lwr | Bin 0 -> 700 bytes o1vm/resources/programs/mips/bin/mfthi | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/mftlo | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/mmap | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/movn | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/movz | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/mul | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/mult | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/multu | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/nor | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/oracle | Bin 0 -> 860 bytes o1vm/resources/programs/mips/bin/oracle_kzg | Bin 0 -> 828 bytes .../programs/mips/bin/oracle_unaligned_read | Bin 0 -> 956 bytes .../programs/mips/bin/oracle_unaligned_write | Bin 0 -> 924 bytes o1vm/resources/programs/mips/bin/ori | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/sb | Bin 0 -> 620 bytes o1vm/resources/programs/mips/bin/sh | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/sll | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/sllv | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/slt | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/slti | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/sltiu | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/sltu | Bin 0 -> 572 bytes o1vm/resources/programs/mips/bin/sra | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/srav | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/srl | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/srlv | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/sub | Bin 0 -> 588 bytes o1vm/resources/programs/mips/bin/subu | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/swl | Bin 0 -> 716 bytes o1vm/resources/programs/mips/bin/swr | Bin 0 -> 716 bytes o1vm/resources/programs/mips/bin/xor | Bin 0 -> 604 bytes o1vm/resources/programs/mips/bin/xori | Bin 0 -> 588 bytes o1vm/resources/programs/mips/src/add.asm | 38 +++++ o1vm/resources/programs/mips/src/addi.asm | 38 +++++ o1vm/resources/programs/mips/src/addiu.asm | 38 +++++ o1vm/resources/programs/mips/src/addu.asm | 38 +++++ o1vm/resources/programs/mips/src/and.asm | 42 ++++++ o1vm/resources/programs/mips/src/andi.asm | 37 +++++ o1vm/resources/programs/mips/src/beq.asm | 50 +++++++ o1vm/resources/programs/mips/src/bgez.asm | 48 +++++++ o1vm/resources/programs/mips/src/bgtz.asm | 49 +++++++ o1vm/resources/programs/mips/src/blez.asm | 48 +++++++ o1vm/resources/programs/mips/src/bltz.asm | 50 +++++++ o1vm/resources/programs/mips/src/bne.asm | 50 +++++++ o1vm/resources/programs/mips/src/brk.asm | 22 +++ o1vm/resources/programs/mips/src/clo.asm | 59 ++++++++ o1vm/resources/programs/mips/src/clone.asm | 22 +++ o1vm/resources/programs/mips/src/clz.asm | 58 ++++++++ o1vm/resources/programs/mips/src/div.asm | 49 +++++++ o1vm/resources/programs/mips/src/divu.asm | 49 +++++++ .../programs/mips/src/exit_group.asm | 25 ++++ o1vm/resources/programs/mips/src/fcntl.asm | 23 +++ o1vm/resources/programs/mips/src/j.asm | 41 ++++++ o1vm/resources/programs/mips/src/jal.asm | 43 ++++++ o1vm/resources/programs/mips/src/jalr.asm | 44 ++++++ o1vm/resources/programs/mips/src/jr.asm | 42 ++++++ o1vm/resources/programs/mips/src/lb.asm | 112 +++++++++++++++ o1vm/resources/programs/mips/src/lbu.asm | 64 +++++++++ o1vm/resources/programs/mips/src/lh.asm | 80 +++++++++++ o1vm/resources/programs/mips/src/lhu.asm | 72 ++++++++++ o1vm/resources/programs/mips/src/lui.asm | 34 +++++ o1vm/resources/programs/mips/src/lw.asm | 39 +++++ o1vm/resources/programs/mips/src/lwl.asm | 78 ++++++++++ o1vm/resources/programs/mips/src/lwr.asm | 78 ++++++++++ o1vm/resources/programs/mips/src/mfthi.asm | 39 +++++ o1vm/resources/programs/mips/src/mftlo.asm | 39 +++++ o1vm/resources/programs/mips/src/mmap.asm | 24 ++++ o1vm/resources/programs/mips/src/movn.asm | 42 ++++++ o1vm/resources/programs/mips/src/movz.asm | 42 ++++++ o1vm/resources/programs/mips/src/mul.asm | 42 ++++++ o1vm/resources/programs/mips/src/mult.asm | 49 +++++++ o1vm/resources/programs/mips/src/multu.asm | 49 +++++++ o1vm/resources/programs/mips/src/nor.asm | 41 ++++++ o1vm/resources/programs/mips/src/oracle.asm | 102 ++++++++++++++ .../programs/mips/src/oracle_kzg.asm | 98 +++++++++++++ .../mips/src/oracle_unaligned_read.asm | 133 ++++++++++++++++++ .../mips/src/oracle_unaligned_write.asm | 123 ++++++++++++++++ o1vm/resources/programs/mips/src/ori.asm | 34 +++++ o1vm/resources/programs/mips/src/sb.asm | 54 +++++++ o1vm/resources/programs/mips/src/sh.asm | 50 +++++++ o1vm/resources/programs/mips/src/sll.asm | 40 ++++++ o1vm/resources/programs/mips/src/sllv.asm | 41 ++++++ o1vm/resources/programs/mips/src/slt.asm | 36 +++++ o1vm/resources/programs/mips/src/slti.asm | 37 +++++ o1vm/resources/programs/mips/src/sltiu.asm | 37 +++++ o1vm/resources/programs/mips/src/sltu.asm | 36 +++++ o1vm/resources/programs/mips/src/sra.asm | 40 ++++++ o1vm/resources/programs/mips/src/srav.asm | 41 ++++++ o1vm/resources/programs/mips/src/srl.asm | 40 ++++++ o1vm/resources/programs/mips/src/srlv.asm | 41 ++++++ o1vm/resources/programs/mips/src/sub.asm | 40 ++++++ o1vm/resources/programs/mips/src/subu.asm | 42 ++++++ o1vm/resources/programs/mips/src/swl.asm | 81 +++++++++++ o1vm/resources/programs/mips/src/swr.asm | 81 +++++++++++ o1vm/resources/programs/mips/src/xor.asm | 43 ++++++ o1vm/resources/programs/mips/src/xori.asm | 38 +++++ 128 files changed, 3235 insertions(+) create mode 100755 o1vm/resources/programs/mips/bin/add create mode 100755 o1vm/resources/programs/mips/bin/addi create mode 100755 o1vm/resources/programs/mips/bin/addiu create mode 100755 o1vm/resources/programs/mips/bin/addu create mode 100755 o1vm/resources/programs/mips/bin/and create mode 100755 o1vm/resources/programs/mips/bin/andi create mode 100755 o1vm/resources/programs/mips/bin/beq create mode 100755 o1vm/resources/programs/mips/bin/bgez create mode 100755 o1vm/resources/programs/mips/bin/bgtz create mode 100755 o1vm/resources/programs/mips/bin/blez create mode 100755 o1vm/resources/programs/mips/bin/bltz create mode 100755 o1vm/resources/programs/mips/bin/bne create mode 100755 o1vm/resources/programs/mips/bin/brk create mode 100755 o1vm/resources/programs/mips/bin/clo create mode 100755 o1vm/resources/programs/mips/bin/clone create mode 100755 o1vm/resources/programs/mips/bin/clz create mode 100755 o1vm/resources/programs/mips/bin/div create mode 100755 o1vm/resources/programs/mips/bin/divu create mode 100755 o1vm/resources/programs/mips/bin/exit_group create mode 100755 o1vm/resources/programs/mips/bin/fcntl create mode 100755 o1vm/resources/programs/mips/bin/j create mode 100755 o1vm/resources/programs/mips/bin/jal create mode 100755 o1vm/resources/programs/mips/bin/jalr create mode 100755 o1vm/resources/programs/mips/bin/jr create mode 100755 o1vm/resources/programs/mips/bin/lb create mode 100755 o1vm/resources/programs/mips/bin/lbu create mode 100755 o1vm/resources/programs/mips/bin/lh create mode 100755 o1vm/resources/programs/mips/bin/lhu create mode 100755 o1vm/resources/programs/mips/bin/lui create mode 100755 o1vm/resources/programs/mips/bin/lw create mode 100755 o1vm/resources/programs/mips/bin/lwl create mode 100755 o1vm/resources/programs/mips/bin/lwr create mode 100755 o1vm/resources/programs/mips/bin/mfthi create mode 100755 o1vm/resources/programs/mips/bin/mftlo create mode 100755 o1vm/resources/programs/mips/bin/mmap create mode 100755 o1vm/resources/programs/mips/bin/movn create mode 100755 o1vm/resources/programs/mips/bin/movz create mode 100755 o1vm/resources/programs/mips/bin/mul create mode 100755 o1vm/resources/programs/mips/bin/mult create mode 100755 o1vm/resources/programs/mips/bin/multu create mode 100755 o1vm/resources/programs/mips/bin/nor create mode 100755 o1vm/resources/programs/mips/bin/oracle create mode 100755 o1vm/resources/programs/mips/bin/oracle_kzg create mode 100755 o1vm/resources/programs/mips/bin/oracle_unaligned_read create mode 100755 o1vm/resources/programs/mips/bin/oracle_unaligned_write create mode 100755 o1vm/resources/programs/mips/bin/ori create mode 100755 o1vm/resources/programs/mips/bin/sb create mode 100755 o1vm/resources/programs/mips/bin/sh create mode 100755 o1vm/resources/programs/mips/bin/sll create mode 100755 o1vm/resources/programs/mips/bin/sllv create mode 100755 o1vm/resources/programs/mips/bin/slt create mode 100755 o1vm/resources/programs/mips/bin/slti create mode 100755 o1vm/resources/programs/mips/bin/sltiu create mode 100755 o1vm/resources/programs/mips/bin/sltu create mode 100755 o1vm/resources/programs/mips/bin/sra create mode 100755 o1vm/resources/programs/mips/bin/srav create mode 100755 o1vm/resources/programs/mips/bin/srl create mode 100755 o1vm/resources/programs/mips/bin/srlv create mode 100755 o1vm/resources/programs/mips/bin/sub create mode 100755 o1vm/resources/programs/mips/bin/subu create mode 100755 o1vm/resources/programs/mips/bin/swl create mode 100755 o1vm/resources/programs/mips/bin/swr create mode 100755 o1vm/resources/programs/mips/bin/xor create mode 100755 o1vm/resources/programs/mips/bin/xori create mode 100644 o1vm/resources/programs/mips/src/add.asm create mode 100644 o1vm/resources/programs/mips/src/addi.asm create mode 100644 o1vm/resources/programs/mips/src/addiu.asm create mode 100644 o1vm/resources/programs/mips/src/addu.asm create mode 100644 o1vm/resources/programs/mips/src/and.asm create mode 100644 o1vm/resources/programs/mips/src/andi.asm create mode 100644 o1vm/resources/programs/mips/src/beq.asm create mode 100644 o1vm/resources/programs/mips/src/bgez.asm create mode 100644 o1vm/resources/programs/mips/src/bgtz.asm create mode 100644 o1vm/resources/programs/mips/src/blez.asm create mode 100644 o1vm/resources/programs/mips/src/bltz.asm create mode 100644 o1vm/resources/programs/mips/src/bne.asm create mode 100644 o1vm/resources/programs/mips/src/brk.asm create mode 100644 o1vm/resources/programs/mips/src/clo.asm create mode 100644 o1vm/resources/programs/mips/src/clone.asm create mode 100644 o1vm/resources/programs/mips/src/clz.asm create mode 100644 o1vm/resources/programs/mips/src/div.asm create mode 100644 o1vm/resources/programs/mips/src/divu.asm create mode 100644 o1vm/resources/programs/mips/src/exit_group.asm create mode 100644 o1vm/resources/programs/mips/src/fcntl.asm create mode 100644 o1vm/resources/programs/mips/src/j.asm create mode 100644 o1vm/resources/programs/mips/src/jal.asm create mode 100644 o1vm/resources/programs/mips/src/jalr.asm create mode 100644 o1vm/resources/programs/mips/src/jr.asm create mode 100644 o1vm/resources/programs/mips/src/lb.asm create mode 100644 o1vm/resources/programs/mips/src/lbu.asm create mode 100644 o1vm/resources/programs/mips/src/lh.asm create mode 100644 o1vm/resources/programs/mips/src/lhu.asm create mode 100644 o1vm/resources/programs/mips/src/lui.asm create mode 100644 o1vm/resources/programs/mips/src/lw.asm create mode 100644 o1vm/resources/programs/mips/src/lwl.asm create mode 100644 o1vm/resources/programs/mips/src/lwr.asm create mode 100644 o1vm/resources/programs/mips/src/mfthi.asm create mode 100644 o1vm/resources/programs/mips/src/mftlo.asm create mode 100644 o1vm/resources/programs/mips/src/mmap.asm create mode 100644 o1vm/resources/programs/mips/src/movn.asm create mode 100644 o1vm/resources/programs/mips/src/movz.asm create mode 100644 o1vm/resources/programs/mips/src/mul.asm create mode 100644 o1vm/resources/programs/mips/src/mult.asm create mode 100644 o1vm/resources/programs/mips/src/multu.asm create mode 100644 o1vm/resources/programs/mips/src/nor.asm create mode 100644 o1vm/resources/programs/mips/src/oracle.asm create mode 100644 o1vm/resources/programs/mips/src/oracle_kzg.asm create mode 100644 o1vm/resources/programs/mips/src/oracle_unaligned_read.asm create mode 100644 o1vm/resources/programs/mips/src/oracle_unaligned_write.asm create mode 100644 o1vm/resources/programs/mips/src/ori.asm create mode 100644 o1vm/resources/programs/mips/src/sb.asm create mode 100644 o1vm/resources/programs/mips/src/sh.asm create mode 100644 o1vm/resources/programs/mips/src/sll.asm create mode 100644 o1vm/resources/programs/mips/src/sllv.asm create mode 100644 o1vm/resources/programs/mips/src/slt.asm create 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+############################################################################### +# File : add.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'add' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff # A = 0xfffffffd (-3) + ori $t0, 0xfffd + ori $t1, $0, 0x3 # B = 0x3 + add $t2, $t0, $t1 # C = A + B = 0 + sltiu $v0, $t2, 1 # D = 1 if C == 0 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/addi.asm b/o1vm/resources/programs/mips/src/addi.asm new file mode 100644 index 0000000000..6981d134fd --- /dev/null +++ b/o1vm/resources/programs/mips/src/addi.asm @@ -0,0 +1,38 @@ +############################################################################### +# File : addi.asm +# Project : MIPS32 MUX +# Author : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'addi' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff # A = 0xfffffffd (-3) + ori $t0, 0xfffd + addi $t1, $t0, 5 # B = A + 5 = 2 + addi $t2, $t1, 0xfffe # C = B + -2 = 0 + sltiu $v0, $t2, 1 # D = 1 if C == 0 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/addiu.asm b/o1vm/resources/programs/mips/src/addiu.asm new file mode 100644 index 0000000000..116ce36145 --- /dev/null +++ b/o1vm/resources/programs/mips/src/addiu.asm @@ -0,0 +1,38 @@ +############################################################################### +# File : addiu.asm +# Project : MIPS32 MUX +# Author : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'addiu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff # A = 0xfffffffd (-3) + ori $t0, 0xfffd + addiu $t1, $t0, 5 # B = A + 5 = 2 + addiu $t2, $t1, 0xfffe # C = B + -2 = 0 + sltiu $v0, $t2, 1 # D = 1 if C == 0 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/addu.asm b/o1vm/resources/programs/mips/src/addu.asm new file mode 100644 index 0000000000..328143dbc6 --- /dev/null +++ b/o1vm/resources/programs/mips/src/addu.asm @@ -0,0 +1,38 @@ +############################################################################### +# File : addu.asm +# Project : MIPS32 MUX +# Author : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'addu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff # A = 0xfffffffd (-3) + ori $t0, 0xfffd + ori $t1, $0, 0x3 # B = 0x3 + addu $t2, $t0, $t1 # C = A + B = 0 + sltiu $v0, $t2, 1 # D = 1 if C == 0 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/and.asm b/o1vm/resources/programs/mips/src/and.asm new file mode 100644 index 0000000000..19d40b99cc --- /dev/null +++ b/o1vm/resources/programs/mips/src/and.asm @@ -0,0 +1,42 @@ +############################################################################### +# File : and.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'and' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + lui $t1, 0xaaaa # B = 0xaaaaaaaa + lui $t2, 0x5555 # C = 0x55555555 + ori $t0, 0xbeef + ori $t1, 0xaaaa + ori $t2, 0x5555 + and $t3, $t0, $t1 # D = A & B = 0x8aaaaaaa + and $t4, $t2, $t3 # E = B & D = 0 + sltiu $v0, $t4, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/andi.asm b/o1vm/resources/programs/mips/src/andi.asm new file mode 100644 index 0000000000..78939b5d45 --- /dev/null +++ b/o1vm/resources/programs/mips/src/andi.asm @@ -0,0 +1,37 @@ +############################################################################### +# File : andi.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'andi' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $t0, $0, 0xcafe # A = 0xcafe + andi $t1, $t0, 0xaaaa # B = A & 0xaaaa = 0x8aaa + andi $t2, $t1, 0x5555 # C = B & 0x5555 = 0 + sltiu $v0, $t2, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/beq.asm b/o1vm/resources/programs/mips/src/beq.asm new file mode 100644 index 0000000000..a0733b62c8 --- /dev/null +++ b/o1vm/resources/programs/mips/src/beq.asm @@ -0,0 +1,50 @@ +############################################################################### +# File : beq.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'beq' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $t0, $0, 0xcafe + ori $t1, $0, 0xcafe + ori $v0, $0, 0 # The test result starts as a failure + beq $t0, $v0, $finish # No branch + nop + beq $t0, $t1, $target + nop + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + +$done: + jr $ra + nop + j $finish # Early-by-1 branch detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + beq $0, $0, $finish # Late-by-1 branch detection (result not stored) + nop + j $finish + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/bgez.asm b/o1vm/resources/programs/mips/src/bgez.asm new file mode 100644 index 0000000000..be7d41eb1a --- /dev/null +++ b/o1vm/resources/programs/mips/src/bgez.asm @@ -0,0 +1,48 @@ +############################################################################### +# File : bgez.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'bgez' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff + bgez $t0, $finish # No branch + nop + bgez $s1, $target + nop + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + +$done: + jr $ra + nop + j $finish # Early-by-1 branch detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + bgez $0, $finish # Late-by-1 branch detection (result not stored) + nop + j $finish # Broken branch recovery + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/bgtz.asm b/o1vm/resources/programs/mips/src/bgtz.asm new file mode 100644 index 0000000000..27b0199b88 --- /dev/null +++ b/o1vm/resources/programs/mips/src/bgtz.asm @@ -0,0 +1,49 @@ +############################################################################### +# File : bgtz.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'bgtz' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v0, $0, 0 # The test result starts as a failure + lui $t0, 0xffff + bgtz $t0, $finish # No branch + nop + bgtz $s1, $target + nop + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + +$done: + jr $ra + nop + j $finish # Early-by-1 branch detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + bgtz $s1, $finish # Late-by-1 branch detection (result not stored) + nop + j $finish # Broken branch recovery + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/blez.asm b/o1vm/resources/programs/mips/src/blez.asm new file mode 100644 index 0000000000..56c11338f7 --- /dev/null +++ b/o1vm/resources/programs/mips/src/blez.asm @@ -0,0 +1,48 @@ +############################################################################### +# File : blez.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'blez' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v0, $0, 0 # The test result starts as a failure + blez $s1, $finish # No branch + lui $t0, 0xffff + blez $t0, $target + nop + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + +$done: + jr $ra + nop + j $finish # Early-by-1 branch detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + blez $0, $finish # Late-by-1 branch detection (result not stored) + nop + j $finish + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/bltz.asm b/o1vm/resources/programs/mips/src/bltz.asm new file mode 100644 index 0000000000..27264f7251 --- /dev/null +++ b/o1vm/resources/programs/mips/src/bltz.asm @@ -0,0 +1,50 @@ +############################################################################### +# File : bltz.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'bltz' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v0, $0, 0 # The test result starts as a failure + bltz $0, $finish # No branch + nop + bltz $s1, $finish # No branch + lui $t0, 0xffff + bltz $t0, $target + nop + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + +$done: + jr $ra + nop + j $finish # Early-by-1 branch detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + bltz $t0, $finish # Late-by-1 branch detection (result not stored) + nop + j $finish # Broken branch recovery + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/bne.asm b/o1vm/resources/programs/mips/src/bne.asm new file mode 100644 index 0000000000..427ba8b941 --- /dev/null +++ b/o1vm/resources/programs/mips/src/bne.asm @@ -0,0 +1,50 @@ +############################################################################### +# File : bne.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'bne' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $t0, $0, 0xcafe + ori $t1, $0, 0xcafe + ori $v0, $0, 0 # The test result starts as a failure + bne $t0, $t1, $finish # No branch + nop + bne $t0, $v0, $target + nop + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + +$done: + jr $ra + nop + j $finish # Early-by-1 branch detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + bne $t0, $0, $finish # Late-by-1 branch detection (result not stored) + nop + j $finish + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/brk.asm b/o1vm/resources/programs/mips/src/brk.asm new file mode 100644 index 0000000000..cf4ace06f3 --- /dev/null +++ b/o1vm/resources/programs/mips/src/brk.asm @@ -0,0 +1,22 @@ +.section .text +.global __start + +__start: + li $v0, 4045 + syscall + lui $t0, 0x4000 + subu $v0, $v0, $t0 + sltiu $v0, $v0, 1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/clo.asm b/o1vm/resources/programs/mips/src/clo.asm new file mode 100644 index 0000000000..374d3fa15e --- /dev/null +++ b/o1vm/resources/programs/mips/src/clo.asm @@ -0,0 +1,59 @@ +############################################################################### +# File : clo.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'clo' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t2, 0xffff # 32 + ori $t2, 0xffff + lui $t3, 0xffff # 18 + ori $t3, 0xc000 + lui $t4, 0xf800 # 5 + lui $t5, 0xf000 # 4 + lui $t6, 0x7fff # 0 + ori $t7, $0, 0 # 0 + clo $s2, $t2 + clo $s3, $t3 + clo $s4, $t4 + clo $s5, $t5 + clo $s6, $t6 + clo $s7, $t7 + addiu $s2, -32 + addiu $s3, -18 + addiu $s4, -5 + addiu $s5, -4 + addiu $s6, 0 + addiu $s7, 0 + or $v1, $s2, $s3 + or $v1, $v1, $s4 + or $v1, $v1, $s5 + or $v1, $v1, $s6 + or $v1, $v1, $s7 + sltiu $v0, $v1, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/clone.asm b/o1vm/resources/programs/mips/src/clone.asm new file mode 100644 index 0000000000..5bf53581d2 --- /dev/null +++ b/o1vm/resources/programs/mips/src/clone.asm @@ -0,0 +1,22 @@ +.section .text +.global __start + +__start: + li $v0, 4120 + syscall + li $t0, 0x1 + subu $v0, $v0, $t0 + sltiu $v0, $v0, 1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/clz.asm b/o1vm/resources/programs/mips/src/clz.asm new file mode 100644 index 0000000000..dd33c0daa2 --- /dev/null +++ b/o1vm/resources/programs/mips/src/clz.asm @@ -0,0 +1,58 @@ +############################################################################### +# File : clz.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'clz' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t2, 0xffff # 0 + ori $t2, 0xffff + ori $t3, $0, 0x0100 # 23 + lui $t4, 0x0700 # 5 + lui $t5, 0x0f00 # 4 + lui $t6, 0x7fff # 1 + ori $t7, $0, 0 # 32 + clz $s2, $t2 + clz $s3, $t3 + clz $s4, $t4 + clz $s5, $t5 + clz $s6, $t6 + clz $s7, $t7 + addiu $s2, 0 + addiu $s3, -23 + addiu $s4, -5 + addiu $s5, -4 + addiu $s6, -1 + addiu $s7, -32 + or $v1, $s2, $s3 + or $v1, $v1, $s4 + or $v1, $v1, $s5 + or $v1, $v1, $s6 + or $v1, $v1, $s7 + sltiu $v0, $v1, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/div.asm b/o1vm/resources/programs/mips/src/div.asm new file mode 100644 index 0000000000..ae4f26ffeb --- /dev/null +++ b/o1vm/resources/programs/mips/src/div.asm @@ -0,0 +1,49 @@ +############################################################################### +# File : div.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'div' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x1234 + ori $t0, 0x5678 + lui $t1, 0xc001 + ori $t1, 0xcafe + div $t1, $t0 # 0xfffffffd (q), 0xf69ece66 (r) + mfhi $t2 + mflo $t3 + lui $t4, 0xf69e + ori $t4, 0xce66 + lui $t5, 0xffff + ori $t5, 0xfffd + subu $t6, $t2, $t4 + subu $t7, $t3, $t5 + sltiu $v0, $t6, 1 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/divu.asm b/o1vm/resources/programs/mips/src/divu.asm new file mode 100644 index 0000000000..825fac128c --- /dev/null +++ b/o1vm/resources/programs/mips/src/divu.asm @@ -0,0 +1,49 @@ +############################################################################### +# File : divu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'divu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x1234 + ori $t0, 0x5678 + lui $t1, 0xc001 + ori $t1, 0xcafe + divu $t1, $t0 # 0xa (q), 0x09f66a4e (r) + mfhi $t2 + mflo $t3 + lui $t4, 0x09f6 + ori $t4, 0x6a4e + lui $t5, 0x0000 + ori $t5, 0x000a + subu $t6, $t2, $t4 + subu $t7, $t3, $t5 + sltiu $v0, $t6, 1 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/exit_group.asm b/o1vm/resources/programs/mips/src/exit_group.asm new file mode 100644 index 0000000000..058f08f494 --- /dev/null +++ b/o1vm/resources/programs/mips/src/exit_group.asm @@ -0,0 +1,25 @@ +.section .text +.global __start + +__start: + li $a0, 1 + li $v0, 4246 + syscall + + # Unreachable .... + # set test result to fail. + # Test runner should short-circuit before reaching this point. + li $v0, 0 + + # save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/fcntl.asm b/o1vm/resources/programs/mips/src/fcntl.asm new file mode 100644 index 0000000000..b199dae3ed --- /dev/null +++ b/o1vm/resources/programs/mips/src/fcntl.asm @@ -0,0 +1,23 @@ +.section .text +.global __start + +__start: + # fnctl(0, 3) + li $v0, 4055 + li $a0, 0x0 + li $a1, 0x3 + syscall + sltiu $v0, $v0, 1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/j.asm b/o1vm/resources/programs/mips/src/j.asm new file mode 100644 index 0000000000..3932995c82 --- /dev/null +++ b/o1vm/resources/programs/mips/src/j.asm @@ -0,0 +1,41 @@ +############################################################################### +# File : j.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'j' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + j $target + ori $v0, $0, 0 # The test result starts as a failure + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + jr $ra + nop + j $finish # Early-by-1 detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + j $finish # Late-by 1 detection (result not written) + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/jal.asm b/o1vm/resources/programs/mips/src/jal.asm new file mode 100644 index 0000000000..cf8abb5c66 --- /dev/null +++ b/o1vm/resources/programs/mips/src/jal.asm @@ -0,0 +1,43 @@ +############################################################################### +# File : jal.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'jal' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v1, $ra, 0 # Save $ra + jal $target + ori $v0, $0, 0 # The test result starts as a failure + +$finish: + sw $v0, 8($s0) + ori $ra, $v1, 0 # Restore $ra + sw $s1, 4($s0) + jr $ra + nop + j $finish # Early-by-1 detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + jr $ra + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/jalr.asm b/o1vm/resources/programs/mips/src/jalr.asm new file mode 100644 index 0000000000..1a8805435a --- /dev/null +++ b/o1vm/resources/programs/mips/src/jalr.asm @@ -0,0 +1,44 @@ +############################################################################### +# File : jalr.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'jalr' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v1, $ra, 0 # Save $ra + la $t0, $target + jalr $t0 + ori $v0, $0, 0 # The test result starts as a failure + +$finish: + sw $v0, 8($s0) + ori $ra, $v1, 0 # Restore $ra + sw $s1, 4($s0) + jr $ra + nop + j $finish # Early-by-1 detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + jr $ra + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/jr.asm b/o1vm/resources/programs/mips/src/jr.asm new file mode 100644 index 0000000000..7fd6b34e9e --- /dev/null +++ b/o1vm/resources/programs/mips/src/jr.asm @@ -0,0 +1,42 @@ +############################################################################### +# File : jr.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'jr' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + la $t0, $target + jr $t0 + ori $v0, $0, 0 # The test result starts as a failure + +$finish: + sw $v0, 8($s0) + sw $s1, 4($s0) + jr $ra + nop + j $finish # Early-by-1 detection + +$target: + nop + ori $v0, $0, 1 # Set the result to pass + j $finish + nop + + #### Test code end #### + diff --git a/o1vm/resources/programs/mips/src/lb.asm b/o1vm/resources/programs/mips/src/lb.asm new file mode 100644 index 0000000000..8ae2bdb177 --- /dev/null +++ b/o1vm/resources/programs/mips/src/lb.asm @@ -0,0 +1,112 @@ +############################################################################### +# File : lb.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lb' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + lui $t1, 0xc001 + ori $t1, 0x7afe + sw $t1, 0($t0) + lb $t2, 0($t0) + lb $t3, 1($t0) + lb $t4, 2($t0) + lb $t5, 3($t0) + .ifdef big_endian + lui $t6, 0xffff + ori $t6, 0xffc0 + lui $t7, 0x0000 + ori $t7, 0x0001 + lui $t8, 0x0000 + ori $t8, 0x007a + lui $t9, 0xffff + ori $t9, 0xfffe + .else + lui $t6, 0xffff + ori $t6, 0xfffe + lui $t7, 0x0000 + ori $t7, 0x007a + lui $t8, 0x0000 + ori $t8, 0x0001 + lui $t9, 0xffff + ori $t9, 0xffc0 + .endif + subu $v1, $t2, $t6 + sltiu $v0, $v1, 1 + subu $v1, $t3, $t7 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t4, $t8 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t5, $t9 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + # Repeat with halves swapped (sign extension corner cases) + lui $t1, 0x7afe + ori $t1, 0xc001 + sw $t1, 0($t0) + lb $t2, 0($t0) + lb $t3, 1($t0) + lb $t4, 2($t0) + lb $t5, 3($t0) + .ifdef big_endian + lui $t6, 0x0000 + ori $t6, 0x007a + lui $t7, 0xffff + ori $t7, 0xfffe + lui $t8, 0xffff + ori $t8, 0xffc0 + lui $t9, 0x0000 + ori $t9, 0x0001 + .else + lui $t6, 0x0000 + ori $t6, 0x0001 + lui $t7, 0xffff + ori $t7, 0xffc0 + lui $t8, 0xffff + ori $t8, 0xfffe + lui $t9, 0x0000 + ori $t9, 0x007a + .endif + subu $v1, $t2, $t6 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t3, $t7 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t4, $t8 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t5, $t9 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lbu.asm b/o1vm/resources/programs/mips/src/lbu.asm new file mode 100644 index 0000000000..9473a3b2fb --- /dev/null +++ b/o1vm/resources/programs/mips/src/lbu.asm @@ -0,0 +1,64 @@ +############################################################################### +# File : lbu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lbu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + lui $t1, 0xc001 + ori $t1, 0x7afe + sw $t1, 0($t0) + lbu $t2, 0($t0) + lbu $t3, 1($t0) + lbu $t4, 2($t0) + lbu $t5, 3($t0) + .ifdef big_endian + ori $t6, $0, 0x00c0 + ori $t7, $0, 0x0001 + ori $t8, $0, 0x007a + ori $t9, $0, 0x00fe + .else + ori $t6, $0, 0x00fe + ori $t7, $0, 0x007a + ori $t8, $0, 0x0001 + ori $t9, $0, 0x00c0 + .endif + subu $v1, $t2, $t6 + sltiu $v0, $v1, 1 + subu $v1, $t3, $t7 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t4, $t8 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t5, $t9 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lh.asm b/o1vm/resources/programs/mips/src/lh.asm new file mode 100644 index 0000000000..bbf3d072c3 --- /dev/null +++ b/o1vm/resources/programs/mips/src/lh.asm @@ -0,0 +1,80 @@ +############################################################################### +# File : lh.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lh' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + lui $t1, 0x7001 + ori $t1, 0xcafe + sw $t1, 0($t0) + lh $t2, 0($t0) + lh $t3, 2($t0) + .ifdef big_endian + lui $t4, 0x0000 + ori $t4, 0x7001 + lui $t5, 0xffff + ori $t5, 0xcafe + .else + lui $t4, 0xffff + ori $t4, 0xcafe + lui $t5, 0x0000 + ori $t5, 0x7001 + .endif + subu $v1, $t2, $t4 + sltiu $v0, $v1, 1 + subu $v1, $t3, $t5 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + # Repeat with halves swapped (sign extension corner cases) + lui $t1, 0xcafe + ori $t1, 0x7001 + sw $t1, 0($t0) + lh $t2, 0($t0) + lh $t3, 2($t0) + .ifdef big_endian + lui $t4, 0xffff + ori $t4, 0xcafe + lui $t5, 0x0000 + ori $t5, 0x7001 + .else + lui $t4, 0x0000 + ori $t4, 0x7001 + lui $t5, 0xffff + ori $t5, 0xcafe + .endif + subu $v1, $t2, $t4 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t3, $t5 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lhu.asm b/o1vm/resources/programs/mips/src/lhu.asm new file mode 100644 index 0000000000..17399ce929 --- /dev/null +++ b/o1vm/resources/programs/mips/src/lhu.asm @@ -0,0 +1,72 @@ +############################################################################### +# File : lhu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lhu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + lui $t1, 0x7001 + ori $t1, 0xcafe + sw $t1, 0($t0) + lhu $t2, 0($t0) + lhu $t3, 2($t0) + .ifdef big_endian + ori $t4, $0, 0x7001 + ori $t5, $0, 0xcafe + .else + ori $t4, $0, 0xcafe + ori $t5, $0, 0x7001 + .endif + subu $v1, $t2, $t4 + sltiu $v0, $v1, 1 + subu $v1, $t3, $t5 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + # Repeat with halves swapped (sign extension corner cases) + lui $t1, 0xcafe + ori $t1, 0x7001 + sw $t1, 0($t0) + lhu $t2, 0($t0) + lhu $t3, 2($t0) + .ifdef big_endian + ori $t4, $0, 0xcafe + ori $t5, $0, 0x7001 + .else + ori $t4, $0, 0x7001 + ori $t5, $0, 0xcafe + .endif + subu $v1, $t2, $t4 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + subu $v1, $t3, $t5 + sltiu $v1, $v1, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lui.asm b/o1vm/resources/programs/mips/src/lui.asm new file mode 100644 index 0000000000..1b08d1b1c4 --- /dev/null +++ b/o1vm/resources/programs/mips/src/lui.asm @@ -0,0 +1,34 @@ +############################################################################### +# File : lui.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lui' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v0, $0, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lw.asm b/o1vm/resources/programs/mips/src/lw.asm new file mode 100644 index 0000000000..57eaa15dba --- /dev/null +++ b/o1vm/resources/programs/mips/src/lw.asm @@ -0,0 +1,39 @@ +############################################################################### +# File : lw.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lw' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load a valid address (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + sw $0, 0($t0) + ori $t1, $0, 1 + sw $t1, 0($t0) + lw $v0, 0($t0) + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lwl.asm b/o1vm/resources/programs/mips/src/lwl.asm new file mode 100644 index 0000000000..8b0aa87f17 --- /dev/null +++ b/o1vm/resources/programs/mips/src/lwl.asm @@ -0,0 +1,78 @@ +############################################################################### +# File : lwl.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lwl' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + lui $t1, 0xc001 # Memory word is 0xc001cafe + ori $t1, 0xcafe + sw $t1, 0($t0) + lui $t2, 0xdeaf # Register word is 0xdeafbeef + ori $t2, 0xbeef + or $t3, $0, $t2 + or $t4, $0, $t2 + or $t5, $0, $t2 + or $t6, $0, $t2 + lwl $t3, 0($t0) + lwl $t4, 1($t0) + lwl $t5, 2($t0) + lwl $t6, 3($t0) + .ifdef big_endian + lui $s3, 0xc001 # 0xc001cafe + ori $s3, 0xcafe + lui $s4, 0x01ca # 0x01cafeef + ori $s4, 0xfeef + lui $s5, 0xcafe # 0xcafebeef + ori $s5, 0xbeef + lui $s6, 0xfeaf # 0xfeafbeef + ori $s6, 0xbeef + .else + lui $s3, 0xfeaf # 0xfeafbeef + ori $s3, 0xbeef + lui $s4, 0xcafe # 0xcafebeef + ori $s4, 0xbeef + lui $s5, 0x01ca # 0x01cafeef + ori $s5, 0xfeef + lui $s6, 0xc001 # 0xc001cafe + ori $s6, 0xcafe + .endif + subu $s2, $t3, $s3 + sltiu $v0, $s2, 1 + subu $s2, $t4, $s4 + sltiu $v1, $s2, 1 + and $v0, $v0, $v1 + subu $s2, $t5, $s5 + sltiu $v1, $s2, 1 + and $v0, $v0, $v1 + subu $s2, $t6, $s6 + sltiu $v1, $s2, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/lwr.asm b/o1vm/resources/programs/mips/src/lwr.asm new file mode 100644 index 0000000000..5561a18d5e --- /dev/null +++ b/o1vm/resources/programs/mips/src/lwr.asm @@ -0,0 +1,78 @@ +############################################################################### +# File : lwr.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'lwr' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + lui $t1, 0xc001 # Memory word is 0xc001cafe + ori $t1, 0xcafe + sw $t1, 0($t0) + lui $t2, 0xdeaf # Register word is 0xdeafbeef + ori $t2, 0xbeef + or $t3, $0, $t2 + or $t4, $0, $t2 + or $t5, $0, $t2 + or $t6, $0, $t2 + lwr $t3, 0($t0) + lwr $t4, 1($t0) + lwr $t5, 2($t0) + lwr $t6, 3($t0) + .ifdef big_endian + lui $s3, 0xdeaf # 0xdeafbec0 + ori $s3, 0xbec0 + lui $s4, 0xdeaf # 0xdeafc001 + ori $s4, 0xc001 + lui $s5, 0xdec0 # 0xdec001ca + ori $s5, 0x01ca + lui $s6, 0xc001 # 0xc001cafe + ori $s6, 0xcafe + .else + lui $s3, 0xc001 # 0xc001cafe + ori $s3, 0xcafe + lui $s4, 0xdec0 # 0xdec001ca + ori $s4, 0x01ca + lui $s5, 0xdeaf # 0xdeafc001 + ori $s5, 0xc001 + lui $s6, 0xdeaf # 0xdeafbec0 + ori $s6, 0xbec0 + .endif + subu $s2, $t3, $s3 + sltiu $v0, $s2, 1 + subu $s2, $t4, $s4 + sltiu $v1, $s2, 1 + and $v0, $v0, $v1 + subu $s2, $t5, $s5 + sltiu $v1, $s2, 1 + and $v0, $v0, $v1 + subu $s2, $t6, $s6 + sltiu $v1, $s2, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/mfthi.asm b/o1vm/resources/programs/mips/src/mfthi.asm new file mode 100644 index 0000000000..ad7654b6ab --- /dev/null +++ b/o1vm/resources/programs/mips/src/mfthi.asm @@ -0,0 +1,39 @@ +############################################################################### +# File : mfthi.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'mthi' and 'mfhi' instructions. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf + ori $t0, 0xbeef + mthi $t0 + mfhi $t1 + subu $v1, $t0, $t1 + sltiu $v0, $v1, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/mftlo.asm b/o1vm/resources/programs/mips/src/mftlo.asm new file mode 100644 index 0000000000..e43da205ed --- /dev/null +++ b/o1vm/resources/programs/mips/src/mftlo.asm @@ -0,0 +1,39 @@ +############################################################################### +# File : mftlo.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'mtlo' and 'mflo' instructions. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf + ori $t0, 0xbeef + mtlo $t0 + mflo $t1 + subu $v1, $t0, $t1 + sltiu $v0, $v1, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/mmap.asm b/o1vm/resources/programs/mips/src/mmap.asm new file mode 100644 index 0000000000..8de6fad851 --- /dev/null +++ b/o1vm/resources/programs/mips/src/mmap.asm @@ -0,0 +1,24 @@ +.section .text +.global __start + +__start: + li $v0, 4090 + lui $a0, 0x3000 + li $a1, 4096 + syscall + lui $t0, 0x3000 + subu $v0, $v0, $t0 + sltiu $v0, $v0, 1 + + # save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/movn.asm b/o1vm/resources/programs/mips/src/movn.asm new file mode 100644 index 0000000000..53b9580817 --- /dev/null +++ b/o1vm/resources/programs/mips/src/movn.asm @@ -0,0 +1,42 @@ +############################################################################### +# File : movn.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'movn' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf + ori $t0, $t0, 0xbeef + ori $t1, $0, 0 + movn $t2, $t0, $s1 # $t2 gets 0xdeafbeef + movn $t1, $t0, $0 # $t1 remains 0 + subu $t3, $t2, $t0 + sltiu $v0, $t3, 1 + sltiu $v1, $t1, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/movz.asm b/o1vm/resources/programs/mips/src/movz.asm new file mode 100644 index 0000000000..74e78eacb5 --- /dev/null +++ b/o1vm/resources/programs/mips/src/movz.asm @@ -0,0 +1,42 @@ +############################################################################### +# File : movz.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'movz' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf + ori $t0, $t0, 0xbeef + ori $t2, $0, 0 + movz $t2, $t0, $s0 # $t2 remains 0 + movz $t1, $t0, $0 # $t1 gets 0xdeafbeef + subu $t3, $t1, $t0 + sltiu $v0, $t3, 1 + sltiu $v1, $t2, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/mul.asm b/o1vm/resources/programs/mips/src/mul.asm new file mode 100644 index 0000000000..2474b18357 --- /dev/null +++ b/o1vm/resources/programs/mips/src/mul.asm @@ -0,0 +1,42 @@ +############################################################################### +# File : mul.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'mul' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x1234 + ori $t0, 0x5678 + lui $t1, 0xc001 + ori $t1, 0xcafe + mul $t2, $t0, $t1 # 0xb2a07b10 + lui $t3, 0xb2a0 + ori $t3, 0x7b10 + subu $t4, $t2, $t3 + sltiu $v0, $t4, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/mult.asm b/o1vm/resources/programs/mips/src/mult.asm new file mode 100644 index 0000000000..19650b33df --- /dev/null +++ b/o1vm/resources/programs/mips/src/mult.asm @@ -0,0 +1,49 @@ +############################################################################### +# File : mult.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'mult' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x1234 + ori $t0, 0x5678 + lui $t1, 0xc001 + ori $t1, 0xcafe + mult $t0, $t1 # 0xfb730b05b2a07b10 + mfhi $t2 + mflo $t3 + lui $t4, 0xfb73 + ori $t4, 0x0b05 + lui $t5, 0xb2a0 + ori $t5, 0x7b10 + subu $t6, $t2, $t4 + subu $t7, $t3, $t5 + sltiu $v0, $t6, 1 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/multu.asm b/o1vm/resources/programs/mips/src/multu.asm new file mode 100644 index 0000000000..7ecc099961 --- /dev/null +++ b/o1vm/resources/programs/mips/src/multu.asm @@ -0,0 +1,49 @@ +############################################################################### +# File : multu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'multu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x1234 + ori $t0, 0x5678 + lui $t1, 0xc001 + ori $t1, 0xcafe + multu $t0, $t1 # 0x0da7617db2a07b10 + mfhi $t2 + mflo $t3 + lui $t4, 0x0da7 + ori $t4, 0x617d + lui $t5, 0xb2a0 + ori $t5, 0x7b10 + subu $t6, $t2, $t4 + subu $t7, $t3, $t5 + sltiu $v0, $t6, 1 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/nor.asm b/o1vm/resources/programs/mips/src/nor.asm new file mode 100644 index 0000000000..01b6799195 --- /dev/null +++ b/o1vm/resources/programs/mips/src/nor.asm @@ -0,0 +1,41 @@ +############################################################################### +# File : nor.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'nor' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, $t0, 0xbeef + lui $t1, 0x3141 # B = 0x31415926 + ori $t1, $t1, 0x5926 + lui $t2, 0xffff # C = 0xfffffffe + ori $t2, $t2, 0xfffe + nor $t3, $t0, $t1 # D = nor(A,B) = 0x00100010 + nor $v0, $t2, $t3 # E = nor(C,D) = 0x1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/oracle.asm b/o1vm/resources/programs/mips/src/oracle.asm new file mode 100644 index 0000000000..87759ab131 --- /dev/null +++ b/o1vm/resources/programs/mips/src/oracle.asm @@ -0,0 +1,102 @@ +.section .text +.global __start + +# load hash at 0x30001000 +# 0x47173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world") +# 0x02173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world").key +__start: + lui $s0, 0x3000 + ori $s0, 0x1000 + + lui $t0, 0x0217 + ori $t0, 0x3285 + sw $t0, 0($s0) + lui $t0, 0xa8d7 + ori $t0, 0x341e + sw $t0, 4($s0) + lui $t0, 0x5e97 + ori $t0, 0x2fc6 + sw $t0, 8($s0) + lui $t0, 0x7728 + ori $t0, 0x6384 + sw $t0, 0xc($s0) + lui $t0, 0xf802 + ori $t0, 0xf8ef + sw $t0, 0x10($s0) + lui $t0, 0x42a5 + ori $t0, 0xec5f + sw $t0, 0x14($s0) + lui $t0, 0x03bb + ori $t0, 0xfa25 + sw $t0, 0x18($s0) + lui $t0, 0x4cb0 + ori $t0, 0x1fad + sw $t0, 0x1c($s0) + +# preimage request - write(fdPreimageWrite, preimageData, 32) + li $a0, 6 + li $a1, 0x30001000 + li $t0, 8 + li $a2, 4 +$writeloop: + li $v0, 4004 + syscall + addiu $a1, $a1, 4 + addiu $t0, $t0, -1 + bnez $t0, $writeloop + nop + +# preimage response to 0x30002000 - read(fdPreimageRead, addr, count) +# read preimage length + li $a0, 5 + li $a1, 0x31000000 + li $a2, 4 + li $v0, 4003 + syscall + li $a1, 0x31000004 + li $v0, 4003 + syscall +# read the preimage data + li $a1, 0x31000008 + li $t0, 3 +$readloop: + li $v0, 4003 + syscall + addiu $a1, $a1, 4 + addiu $t0, $t0, -1 + bnez $t0, $readloop + nop + +# length at 0x31000000. We also check that the lower 32 bits are zero + lui $s1, 0x3100 + lw $t0, 0($s1) + sltiu $t6, $t0, 1 + li $s1, 0x31000004 + lw $t0, 0($s1) +# should be len("hello world") == 11 + li $t4, 11 + subu $t5, $t0, $t4 + sltiu $v0, $t5, 1 + and $v0, $v0, $t6 + +# data at 0x31000008 + lw $t0, 4($s1) + lui $t4, 0x6865 + ori $t4, 0x6c6c + subu $t5, $t0, $t4 + sltiu $v1, $t5, 1 + + and $v0, $v0, $v1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/oracle_kzg.asm b/o1vm/resources/programs/mips/src/oracle_kzg.asm new file mode 100644 index 0000000000..544737e2da --- /dev/null +++ b/o1vm/resources/programs/mips/src/oracle_kzg.asm @@ -0,0 +1,98 @@ +.section .text +.global __start + +# load hash at 0x30001000 +# point evaluation precompile input - 01e798154708fe7789429634053cbf9f99b619f9f084048927333fce637f549b564c0a11a0f704f4fc3e8acfe0f8245f0ad1347b378fbf96e206da11a5d3630624d25032e67a7e6a4910df5834b8fe70e6bcfeeac0352434196bdf4b2485d5a18f59a8d2a1a625a17f3fea0fe5eb8c896db3764f3185481bc22f91b4aaffcca25f26936857bc3a7c2539ea8ec3a952b7873033e038326e87ed3e1276fd140253fa08e9fc25fb2d9a98527fc22a2c9612fbeafdad446cbc7bcdbdcd780af2c16a +# 0x0a44472c cb798bc5 954fc466 e6ee2c31 e1ca8a87 d000966c 629d679a 4a29921f = keccak(address(0xa) ++ precompile_input) +# 0x0644472c cb798bc5 954fc466 e6ee2c31 e1ca8a87 d000966c 629d679a 4a29921f = keccak(address(0xa) ++ precompile_input).key (precompile) +__start: + lui $s0, 0x3000 + ori $s0, 0x1000 + + lui $t0, 0x0644 + ori $t0, 0x472c + sw $t0, 0($s0) + lui $t0, 0xcb79 + ori $t0, 0x8bc5 + sw $t0, 4($s0) + lui $t0, 0x954f + ori $t0, 0xc466 + sw $t0, 8($s0) + lui $t0, 0xe6ee + ori $t0, 0x2c31 + sw $t0, 0xc($s0) + lui $t0, 0xe1ca + ori $t0, 0x8a87 + sw $t0, 0x10($s0) + lui $t0, 0xd000 + ori $t0, 0x966c + sw $t0, 0x14($s0) + lui $t0, 0x629d + ori $t0, 0x679a + sw $t0, 0x18($s0) + lui $t0, 0x4a29 + ori $t0, 0x921f + sw $t0, 0x1c($s0) + +# preimage request - write(fdPreimageWrite, preimageData, 32) + li $a0, 6 + li $a1, 0x30001000 + li $t0, 8 + li $a2, 4 +$writeloop: + li $v0, 4004 + syscall + addiu $a1, $a1, 4 + addiu $t0, $t0, -1 + bnez $t0, $writeloop + nop + +# preimage response to 0x30002000 - read(fdPreimageRead, addr, count) +# read preimage length + li $a0, 5 + li $a1, 0x31000000 + li $a2, 4 + li $v0, 4003 + syscall + li $a1, 0x31000004 + li $v0, 4003 + syscall +# read the 1 byte precompile status and 3 bytes of return data + li $a1, 0x31000008 + li $v0, 4003 + syscall + nop + +# length at 0x31000000. We also check that the lower 32 bits are zero + lui $s1, 0x3100 + lw $t0, 0($s1) + sltiu $t6, $t0, 1 + li $s1, 0x31000004 + lw $t0, 0($s1) +# should be 1 + len(blobPrecompileReturnValue) = 65 + li $t4, 65 + subu $t5, $t0, $t4 + sltiu $v0, $t5, 1 + and $v0, $v0, $t6 + +# data at 0x31000008 +# first byte is 01 status. Next 3 bytes are 0 + lw $t0, 4($s1) + lui $t4, 0x0100 + ori $t4, 0x0000 + subu $t5, $t0, $t4 + sltiu $v1, $t5, 1 + and $v0, $v0, $v1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/oracle_unaligned_read.asm b/o1vm/resources/programs/mips/src/oracle_unaligned_read.asm new file mode 100644 index 0000000000..2ee7128ba4 --- /dev/null +++ b/o1vm/resources/programs/mips/src/oracle_unaligned_read.asm @@ -0,0 +1,133 @@ +.section .text +.global __start + +# load hash at 0x30001000 +# 0x47173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world") +# 0x02173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world").key +__start: + lui $s0, 0x3000 + ori $s0, 0x1000 + + lui $t0, 0x0217 + ori $t0, 0x3285 + sw $t0, 0($s0) + lui $t0, 0xa8d7 + ori $t0, 0x341e + sw $t0, 4($s0) + lui $t0, 0x5e97 + ori $t0, 0x2fc6 + sw $t0, 8($s0) + lui $t0, 0x7728 + ori $t0, 0x6384 + sw $t0, 0xc($s0) + lui $t0, 0xf802 + ori $t0, 0xf8ef + sw $t0, 0x10($s0) + lui $t0, 0x42a5 + ori $t0, 0xec5f + sw $t0, 0x14($s0) + lui $t0, 0x03bb + ori $t0, 0xfa25 + sw $t0, 0x18($s0) + lui $t0, 0x4cb0 + ori $t0, 0x1fad + sw $t0, 0x1c($s0) + +# preimage request - write(fdPreimageWrite, preimageData, 32) + li $a0, 6 + li $a1, 0x30001000 + li $t0, 8 + li $a2, 4 +$writeloop: + li $v0, 4004 + syscall + addiu $a1, $a1, 4 + addiu $t0, $t0, -1 + bnez $t0, $writeloop + nop + +# preimage response to 0x30002000 - read(fdPreimageRead, addr, count) +# read preimage length to unaligned addr. This will read only up to the nearest aligned byte so we have to read again. + li $a0, 5 + li $a1, 0x31000001 + li $a2, 4 + li $v0, 4003 + syscall + li $a1, 0x31000004 + li $v0, 4003 + syscall + li $a1, 0x31000008 + li $a2, 1 + li $v0, 4003 + syscall +# read the preimage data + li $a1, 0x31000009 + li $t0, 11 +$readloop: + li $v0, 4003 + li $a2, 4 + syscall + addu $a1, $a1, $v0 + subu $t0, $t0, $v0 + bnez $t0, $readloop + nop + +# length at 0x31000001. We also check that the lower 32 bits are zero + li $s1, 0x31000001 + lb $t0, 0($s1) + lb $t2, 1($s1) + sll $t2, $t2, 8 + or $t0, $t0, $t2 + lb $t2, 2($s1) + sll $t2, $t2, 16 + or $t0, $t0, $t2 +# assert len[0:3] == 0 + sltiu $v0, $t0, 1 + +# assert len[4:8] == 0 + addiu $s1, $s1, 3 + lw $t1, 0($s1) + sltiu $v1, $t1, 1 + and $v0, $v0, $v1 + +# assert len[8:9] == 11 + addiu $s1, $s1, 4 + lb $t2, 0($s1) + li $t4, 11 + subu $t5, $t2, $t4 + sltiu $v1, $t5, 1 + and $v0, $v0, $v1 + +# data at 0x31000009 + addiu $s1, $s1, 1 + lb $t0, 0($s1) + lb $t2, 1($s1) + sll $t0, $t0, 8 + or $t0, $t0, $t2 + lb $t2, 2($s1) + sll $t0, $t0, 8 + or $t0, $t0, $t2 + lb $t2, 3($s1) + sll $t0, $t0, 8 + or $t0, $t0, $t2 + + #lw $t0, 0($s1) + lui $t4, 0x6865 + ori $t4, 0x6c6c + subu $t5, $t0, $t4 + sltiu $v1, $t5, 1 + + and $v0, $v0, $v1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/oracle_unaligned_write.asm b/o1vm/resources/programs/mips/src/oracle_unaligned_write.asm new file mode 100644 index 0000000000..ca242f3490 --- /dev/null +++ b/o1vm/resources/programs/mips/src/oracle_unaligned_write.asm @@ -0,0 +1,123 @@ +.section .text +.global __start + +# load hash at 0x30001000 +# 0x47173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world") +# 0x02173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world").key +__start: + lui $s0, 0x3000 + ori $s0, 0x1000 + + lui $t0, 0x0217 + ori $t0, 0x3285 + sw $t0, 0($s0) + lui $t0, 0xa8d7 + ori $t0, 0x341e + sw $t0, 4($s0) + lui $t0, 0x5e97 + ori $t0, 0x2fc6 + sw $t0, 8($s0) + lui $t0, 0x7728 + ori $t0, 0x6384 + sw $t0, 0xc($s0) + lui $t0, 0xf802 + ori $t0, 0xf8ef + sw $t0, 0x10($s0) + lui $t0, 0x42a5 + ori $t0, 0xec5f + sw $t0, 0x14($s0) + lui $t0, 0x03bb + ori $t0, 0xfa25 + sw $t0, 0x18($s0) + lui $t0, 0x4cb0 + ori $t0, 0x1fad + sw $t0, 0x1c($s0) + +# preimage request - write(fdPreimageWrite, preimageData, 32) +# create stuffed buffer containing the first byte of the hash - [garbage, hash[0], garbage] + lui $s1, 0x3200 + ori $s1, 0x0000 + lui $t0, 0xFFFF + ori $t0, 0x02FF + sw $t0, 0($s1) + +# initial unaligned write for stuffed buffer + li $a0, 6 + li $a1, 0x32000002 + li $a2, 1 + li $v0, 4004 + syscall + +# write 3 bytes for realignment + li $a0, 6 + li $a1, 0x30001001 + li $a2, 3 + li $v0, 4004 + syscall + + li $a0, 6 + li $a1, 0x30001004 + li $t0, 7 + li $a2, 4 +$writeloop: + li $v0, 4004 + syscall + addiu $a1, $a1, 4 + addiu $t0, $t0, -1 + bnez $t0, $writeloop + nop + +# preimage response to 0x30002000 - read(fdPreimageRead, addr, count) +# read preimage length + li $a0, 5 + li $a1, 0x31000000 + li $a2, 4 + li $v0, 4003 + syscall + li $a1, 0x31000004 + li $v0, 4003 + syscall +# read the preimage data + li $a1, 0x31000008 + li $t0, 3 +$readloop: + li $v0, 4003 + syscall + addiu $a1, $a1, 4 + addiu $t0, $t0, -1 + bnez $t0, $readloop + nop + +# length at 0x31000000. We also check that the lower 32 bits are zero + lui $s1, 0x3100 + lw $t0, 0($s1) + sltiu $t6, $t0, 1 + li $s1, 0x31000004 + lw $t0, 0($s1) +# should be len("hello world") == 11 + li $t4, 11 + subu $t5, $t0, $t4 + sltiu $v0, $t5, 1 + and $v0, $v0, $t6 + +# data at 0x31000008 + lw $t0, 4($s1) + lui $t4, 0x6865 + ori $t4, 0x6c6c + subu $t5, $t0, $t4 + sltiu $v1, $t5, 1 + + and $v0, $v0, $v1 + +# save results + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/ori.asm b/o1vm/resources/programs/mips/src/ori.asm new file mode 100644 index 0000000000..d985d60ed5 --- /dev/null +++ b/o1vm/resources/programs/mips/src/ori.asm @@ -0,0 +1,34 @@ +############################################################################### +# File : ori.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'ori' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $v0, $s1, 0 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sb.asm b/o1vm/resources/programs/mips/src/sb.asm new file mode 100644 index 0000000000..d05d344420 --- /dev/null +++ b/o1vm/resources/programs/mips/src/sb.asm @@ -0,0 +1,54 @@ +############################################################################### +# File : sb.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sb' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + sw $0, 0($t0) + ori $t1, $0, 0xc0 + ori $t2, $0, 0x01 + ori $t3, $0, 0xca + ori $t4, $0, 0xfe + sb $t1, 0($t0) + sb $t2, 1($t0) + sb $t3, 2($t0) + sb $t4, 3($t0) + lw $t5, 0($t0) + .ifdef big_endian + lui $t6, 0xc001 + ori $t6, 0xcafe + .else + lui $t6, 0xfeca + ori $t6, 0x01c0 + .endif + subu $t7, $t5, $t6 + sltiu $v0, $t7, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sh.asm b/o1vm/resources/programs/mips/src/sh.asm new file mode 100644 index 0000000000..c4a0e81494 --- /dev/null +++ b/o1vm/resources/programs/mips/src/sh.asm @@ -0,0 +1,50 @@ +############################################################################### +# File : sh.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sh' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting + ori $t0, 0x07fc # from 0xbfc00000) + sw $0, 0($t0) + ori $t1, $0, 0xc001 + ori $t2, $0, 0xcafe + sh $t1, 0($t0) + sh $t2, 2($t0) + lw $t3, 0($t0) + .ifdef big_endian + lui $t4, 0xc001 + ori $t4, 0xcafe + .else + lui $t4, 0xcafe + ori $t4, 0xc001 + .endif + subu $t5, $t3, $t4 + sltiu $v0, $t5, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sll.asm b/o1vm/resources/programs/mips/src/sll.asm new file mode 100644 index 0000000000..8483593f96 --- /dev/null +++ b/o1vm/resources/programs/mips/src/sll.asm @@ -0,0 +1,40 @@ +############################################################################### +# File : sll.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sll' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + sll $t1, $t0, 4 # B = 0xdeafbeef << 4 = 0xeafbeef0 + lui $t2, 0xeafb # C = 0xeafbeef0 + ori $t2, 0xeef0 + subu $t3, $t1, $t2 + sltiu $v0, $t3, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sllv.asm b/o1vm/resources/programs/mips/src/sllv.asm new file mode 100644 index 0000000000..c6af8848e8 --- /dev/null +++ b/o1vm/resources/programs/mips/src/sllv.asm @@ -0,0 +1,41 @@ +############################################################################### +# File : sllv.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sllv' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + ori $t1, $0, 12 + sllv $t2, $t0, $t1 # B = 0xdeafbeef << 12 = 0xfbeef000 + lui $t3, 0xfbee + ori $t3, 0xf000 + subu $t4, $t2, $t3 + sltiu $v0, $t4, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/slt.asm b/o1vm/resources/programs/mips/src/slt.asm new file mode 100644 index 0000000000..d0a233a4a1 --- /dev/null +++ b/o1vm/resources/programs/mips/src/slt.asm @@ -0,0 +1,36 @@ +############################################################################### +# File : slt.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'slt' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff + ori $t0, 0xffff + slt $v0, $t0, $s1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/slti.asm b/o1vm/resources/programs/mips/src/slti.asm new file mode 100644 index 0000000000..6a40b9f5ad --- /dev/null +++ b/o1vm/resources/programs/mips/src/slti.asm @@ -0,0 +1,37 @@ +############################################################################### +# File : slti.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'slti' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x8000 + slti $v0, $t0, 0xffff + slti $v1, $t0, 0 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sltiu.asm b/o1vm/resources/programs/mips/src/sltiu.asm new file mode 100644 index 0000000000..3789706ecd --- /dev/null +++ b/o1vm/resources/programs/mips/src/sltiu.asm @@ -0,0 +1,37 @@ +############################################################################### +# File : sltiu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sltiu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0x8000 + sltiu $v0, $t0, 0xffff + sltiu $v1, $0, 0xffff + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sltu.asm b/o1vm/resources/programs/mips/src/sltu.asm new file mode 100644 index 0000000000..878be3ea84 --- /dev/null +++ b/o1vm/resources/programs/mips/src/sltu.asm @@ -0,0 +1,36 @@ +############################################################################### +# File : sltu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sltu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff + ori $t0, 0xffff + sltu $v0, $s1, $t0 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sra.asm b/o1vm/resources/programs/mips/src/sra.asm new file mode 100644 index 0000000000..96961d50fa --- /dev/null +++ b/o1vm/resources/programs/mips/src/sra.asm @@ -0,0 +1,40 @@ +############################################################################### +# File : sra.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sra' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + sra $t1, $t0, 4 # B = 0xdeafbeef >> 4 = 0xfdeafbee + lui $t2, 0xfdea # C = 0xfdeafbee + ori $t2, 0xfbee + subu $t3, $t1, $t2 # D = B - C = 0 + sltiu $v0, $t3, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/srav.asm b/o1vm/resources/programs/mips/src/srav.asm new file mode 100644 index 0000000000..163a4240c8 --- /dev/null +++ b/o1vm/resources/programs/mips/src/srav.asm @@ -0,0 +1,41 @@ +############################################################################### +# File : srav.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'srav' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + ori $t1, $0, 12 + srav $t2, $t0, $t1 # B = 0xdeafbeef >> 12 = 0xfffdeafb + lui $t3, 0xfffd + ori $t3, 0xeafb + subu $t4, $t2, $t3 + sltiu $v0, $t4, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/srl.asm b/o1vm/resources/programs/mips/src/srl.asm new file mode 100644 index 0000000000..66f6027ea6 --- /dev/null +++ b/o1vm/resources/programs/mips/src/srl.asm @@ -0,0 +1,40 @@ +############################################################################### +# File : srl.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'srl' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + srl $t1, $t0, 4 # B = 0xdeafbeef >> 4 = 0x0deafbee + lui $t2, 0x0dea + ori $t2, 0xfbee + subu $t3, $t1, $t2 # D = B - C = 0 + sltiu $v0, $t3, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/srlv.asm b/o1vm/resources/programs/mips/src/srlv.asm new file mode 100644 index 0000000000..96ee97fd75 --- /dev/null +++ b/o1vm/resources/programs/mips/src/srlv.asm @@ -0,0 +1,41 @@ +############################################################################### +# File : srlv.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'srlv' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + ori $t1, $0, 12 + srlv $t2, $t0, $t1 # B = 0xdeafbeef >> 12 = 0x000deafb + lui $t3, 0x000d + ori $t3, 0xeafb + subu $t4, $t2, $t3 + sltiu $v0, $t4, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/sub.asm b/o1vm/resources/programs/mips/src/sub.asm new file mode 100644 index 0000000000..26da5a19f5 --- /dev/null +++ b/o1vm/resources/programs/mips/src/sub.asm @@ -0,0 +1,40 @@ +############################################################################### +# File : sub.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'sub' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff # A = 0xfffffffd (-3) + ori $t0, 0xfffd + sub $t1, $t0, $t0 # B = A - A = 0 + sub $t2, $t1, $t0 # C = B - A = 0 - A = 3 + ori $t3, $0, 3 # D = 2 + sub $t4, $t2, $t3 # E = C - D = C - 2 = 0 + sltiu $v0, $t4, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/subu.asm b/o1vm/resources/programs/mips/src/subu.asm new file mode 100644 index 0000000000..0d9ab23154 --- /dev/null +++ b/o1vm/resources/programs/mips/src/subu.asm @@ -0,0 +1,42 @@ +############################################################################### +# File : subu.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'subu' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xffff # A = 0xfffffffd (-3) + ori $t0, 0xfffd + ori $t1, $0, 4 # B = 4 + subu $t2, $t0, $t1 # C = A - B = 0xfffffff9 (-7) + lui $t3, 0xffff # D = 0xfffffff8 (like -8 mod 2^32) + ori $t3, 0xfff8 + subu $t4, $t2, $t3 # F = C - D = 1 + subu $t5, $t4, $s1 # G = F - 1 = 0 + sltiu $v0, $t5, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/swl.asm b/o1vm/resources/programs/mips/src/swl.asm new file mode 100644 index 0000000000..354dadf567 --- /dev/null +++ b/o1vm/resources/programs/mips/src/swl.asm @@ -0,0 +1,81 @@ +############################################################################### +# File : swl.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'swl' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007ec (last four words in 2KB starting + ori $t0, 0x07ec # from 0xbfc00000) + lui $t1, 0xc001 # Memory word is 0xc001cafe + ori $t1, 0xcafe + sw $t1, 0($t0) + sw $t1, 4($t0) + sw $t1, 8($t0) + sw $t1, 12($t0) + lui $t2, 0xdeaf # Register word is 0xdeafbeef + ori $t2, 0xbeef + swl $t2, 0($t0) + swl $t2, 5($t0) + swl $t2, 10($t0) + swl $t2, 15($t0) + lw $s2, 0($t0) + lw $s3, 4($t0) + lw $s4, 8($t0) + lw $s5, 12($t0) + .ifdef big_endian + lui $t3, 0xdeaf # 0xdeafbeef + ori $t3, 0xbeef + lui $t4, 0xc0de # 0xc0deafbe + ori $t4, 0xafbe + lui $t5, 0xc001 # 0xc001deaf + ori $t5, 0xdeaf + lui $t6, 0xc001 # 0xc001cade + ori $t6, 0xcade + .else + lui $t3, 0xc001 # 0xc001cade + ori $t3, 0xcade + lui $t4, 0xc001 # 0xc001deaf + ori $t4, 0xdeaf + lui $t5, 0xc0de # 0xc0deafbe + ori $t5, 0xafbe + lui $t6, 0xdeaf # 0xdeafbeef + ori $t6, 0xbeef + .endif + subu $t7, $s2, $t3 + sltiu $v0, $t7, 1 + subu $t7, $s3, $t4 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + subu $t7, $s4, $t5 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + subu $t7, $s5, $t6 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/swr.asm b/o1vm/resources/programs/mips/src/swr.asm new file mode 100644 index 0000000000..2a4301cca7 --- /dev/null +++ b/o1vm/resources/programs/mips/src/swr.asm @@ -0,0 +1,81 @@ +############################################################################### +# File : swr.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'swr' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xbfc0 # Load address 0xbfc007ec (last four words in 2KB starting + ori $t0, 0x07ec # from 0xbfc00000) + lui $t1, 0xc001 # Memory words are 0xc001cafe + ori $t1, 0xcafe + sw $t1, 0($t0) + sw $t1, 4($t0) + sw $t1, 8($t0) + sw $t1, 12($t0) + lui $t2, 0xdeaf # Register word is 0xdeafbeef + ori $t2, 0xbeef + swr $t2, 0($t0) + swr $t2, 5($t0) + swr $t2, 10($t0) + swr $t2, 15($t0) + lw $s2, 0($t0) + lw $s3, 4($t0) + lw $s4, 8($t0) + lw $s5, 12($t0) + .ifdef big_endian + lui $t3, 0xef01 # 0xef01cafe + ori $t3, 0xcafe + lui $t4, 0xbeef # 0xbeefcafe + ori $t4, 0xcafe + lui $t5, 0xafbe # 0xafbeeffe + ori $t5, 0xeffe + lui $t6, 0xdeaf # 0xdeafbeef + ori $t6, 0xbeef + .else + lui $t3, 0xdeaf # 0xdeafbeef + ori $t3, 0xbeef + lui $t4, 0xafbe # 0xafbeeffe + ori $t4, 0xeffe + lui $t5, 0xbeef # 0xbeefcafe + ori $t5, 0xcafe + lui $t6, 0xef01 # 0xef01cafe + ori $t6, 0xcafe + .endif + subu $t7, $s2, $t3 + sltiu $v0, $t7, 1 + subu $t7, $s3, $t4 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + subu $t7, $s4, $t5 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + subu $t7, $s5, $t6 + sltiu $v1, $t7, 1 + and $v0, $v0, $v1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/xor.asm b/o1vm/resources/programs/mips/src/xor.asm new file mode 100644 index 0000000000..56770a0e93 --- /dev/null +++ b/o1vm/resources/programs/mips/src/xor.asm @@ -0,0 +1,43 @@ +############################################################################### +# File : xor.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'xor' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + lui $t0, 0xdeaf # A = 0xdeafbeef + ori $t0, 0xbeef + lui $t1, 0x3141 # B = 0x31415926 + ori $t1, 0x5926 + lui $t2, 0xefee # C = 0xefeee7c8 + ori $t2, 0xe7c8 + xor $t3, $t0, $t1 # D = xor(A,B) = 0xefeee7c8 + xor $t4, $t2, $t3 # E = xor(C,D) = 0x1 + xor $t5, $t4, $s1 # F = xor(E,1) = 0 + sltiu $v0, $t5, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + diff --git a/o1vm/resources/programs/mips/src/xori.asm b/o1vm/resources/programs/mips/src/xori.asm new file mode 100644 index 0000000000..491e3ba11b --- /dev/null +++ b/o1vm/resources/programs/mips/src/xori.asm @@ -0,0 +1,38 @@ +############################################################################### +# File : xori.asm +# Project : MIPS32 MUX +# Author: : Grant Ayers (ayers@cs.stanford.edu) +# +# Standards/Formatting: +# MIPS gas, soft tab, 80 column +# +# Description: +# Test the functionality of the 'xori' instruction. +# +############################################################################### + + +.section .text +.global __start +__start: + lui $s0, 0xbfff # Load the base address 0xbffffff0 + ori $s0, 0xfff0 + ori $s1, $0, 1 # Prepare the 'done' status + + #### Test code start #### + + ori $t0, $0, 0xdeaf # A = 0xdeaf + xori $t1, $t0, 0x3141 # B = xor(A, 0x3141) = 0xefee + xori $t2, $t1, 0xefef # C = xor(B, 0xefef) = 0x1 + xori $t3, $t2, 1 # D = xor(C, 1) = 0 + sltiu $v0, $t3, 1 + + #### Test code end #### + + sw $v0, 8($s0) # Set the test result + sw $s1, 4($s0) # Set 'done' + +$done: + jr $ra + nop + From ed8f4602a5e7263a0e1d45f1ba8a964e7f409026 Mon Sep 17 00:00:00 2001 From: martyall Date: Tue, 24 Dec 2024 11:02:33 -0800 Subject: [PATCH 75/80] ignore mips/bin --- .gitignore | 2 +- o1vm/resources/programs/mips/bin/add | Bin 588 -> 0 bytes o1vm/resources/programs/mips/bin/addi | Bin 588 -> 0 bytes o1vm/resources/programs/mips/bin/addiu | Bin 588 -> 0 bytes o1vm/resources/programs/mips/bin/addu | Bin 588 -> 0 bytes o1vm/resources/programs/mips/bin/and | Bin 604 -> 0 bytes o1vm/resources/programs/mips/bin/andi | Bin 572 -> 0 bytes o1vm/resources/programs/mips/bin/beq | Bin 620 -> 0 bytes o1vm/resources/programs/mips/bin/bgez | Bin 620 -> 0 bytes o1vm/resources/programs/mips/bin/bgtz | Bin 620 -> 0 bytes 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delete mode 100755 o1vm/resources/programs/mips/bin/lwl delete mode 100755 o1vm/resources/programs/mips/bin/lwr delete mode 100755 o1vm/resources/programs/mips/bin/mfthi delete mode 100755 o1vm/resources/programs/mips/bin/mftlo delete mode 100755 o1vm/resources/programs/mips/bin/mmap delete mode 100755 o1vm/resources/programs/mips/bin/movn delete mode 100755 o1vm/resources/programs/mips/bin/movz delete mode 100755 o1vm/resources/programs/mips/bin/mul delete mode 100755 o1vm/resources/programs/mips/bin/mult delete mode 100755 o1vm/resources/programs/mips/bin/multu delete mode 100755 o1vm/resources/programs/mips/bin/nor delete mode 100755 o1vm/resources/programs/mips/bin/oracle delete mode 100755 o1vm/resources/programs/mips/bin/oracle_kzg delete mode 100755 o1vm/resources/programs/mips/bin/oracle_unaligned_read delete mode 100755 o1vm/resources/programs/mips/bin/oracle_unaligned_write delete mode 100755 o1vm/resources/programs/mips/bin/ori delete mode 100755 o1vm/resources/programs/mips/bin/sb delete mode 100755 o1vm/resources/programs/mips/bin/sh delete mode 100755 o1vm/resources/programs/mips/bin/sll delete mode 100755 o1vm/resources/programs/mips/bin/sllv delete mode 100755 o1vm/resources/programs/mips/bin/slt delete mode 100755 o1vm/resources/programs/mips/bin/slti delete mode 100755 o1vm/resources/programs/mips/bin/sltiu delete mode 100755 o1vm/resources/programs/mips/bin/sltu delete mode 100755 o1vm/resources/programs/mips/bin/sra delete mode 100755 o1vm/resources/programs/mips/bin/srav delete mode 100755 o1vm/resources/programs/mips/bin/srl delete mode 100755 o1vm/resources/programs/mips/bin/srlv delete mode 100755 o1vm/resources/programs/mips/bin/sub delete mode 100755 o1vm/resources/programs/mips/bin/subu delete mode 100755 o1vm/resources/programs/mips/bin/swl delete mode 100755 o1vm/resources/programs/mips/bin/swr delete mode 100755 o1vm/resources/programs/mips/bin/xor delete mode 100755 o1vm/resources/programs/mips/bin/xori diff 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We should return a state depending on the -// architecture. In the meantime, we can have parse_riscv32i and parse_mips. -// FIXME: for now, we return a State structure, either for RISC-V 32i or MIPS. -// We should return a structure specifically built for the o1vm, and not tight -// to Cannon. It will be done in a future PR to avoid breaking the current code -// and have a huge diff. -pub fn parse_riscv32(path: &Path) -> Result { - debug!("Start parsing the ELF file to load a RISC-V 32i compatible state"); - let file_data = std::fs::read(path).expect("Could not read file."); - let slice = file_data.as_slice(); - let file = ElfBytes::::minimal_parse(slice).expect("Open ELF file failed."); +pub enum Architecture { + Mips, + RiscV, +} +pub fn make_state(file: ElfBytes) -> Result { // Checking it is RISC-V - assert_eq!(file.ehdr.e_machine, 243); let (shdrs_opt, strtab_opt) = file .section_headers_with_strtab() @@ -51,9 +46,11 @@ pub fn parse_riscv32(path: &Path) -> Result { .section_data(text_section) .expect("Failed to read data from .text section"); + // address of starting instruction in code section let code_section_starting_address = text_section.sh_addr as usize; let code_section_size = text_section.sh_size as usize; - let code_section_end_address = code_section_starting_address + code_section_size; + // address of last instruction in code section + let code_section_end_address = code_section_starting_address + code_section_size - 1; debug!( "The executable code starts at address {}, has size {} bytes, and ends at address {}.", code_section_starting_address, code_section_size, code_section_end_address @@ -64,17 +61,22 @@ pub fn parse_riscv32(path: &Path) -> Result { let page_size_usize: usize = PAGE_SIZE.try_into().unwrap(); // Padding to get the right number of pages. We suppose that the memory // index starts at 0. + + // the address that the first page starts on let start_page_address: usize = (code_section_starting_address / page_size_usize) * page_size_usize; - let end_page_address = - (code_section_end_address / (page_size_usize - 1)) * page_size_usize + page_size_usize; + + // the address that the last page starts on + let end_page_address = (code_section_end_address / page_size_usize) * page_size_usize; let first_page_index = start_page_address / page_size_usize; - let last_page_index = (end_page_address - 1) / page_size_usize; + + let last_page_index = end_page_address / page_size_usize; + let mut data_offset = 0; (first_page_index..=last_page_index).for_each(|page_index| { let mut data = vec![0; page_size_usize]; - // Special case of only one page + // Special case where all code fits in one page if first_page_index == last_page_index { let data_length = code_section_end_address - code_section_starting_address; let page_offset = code_section_starting_address - start_page_address; @@ -82,18 +84,25 @@ pub fn parse_riscv32(path: &Path) -> Result { .copy_from_slice(&text_section_data[0..data_length]); data_offset += data_length; } else { - let data_length = if page_index == last_page_index { - code_section_end_address - (page_index * page_size_usize) - } else { - page_size_usize - }; let page_offset = if page_index == first_page_index { code_section_starting_address - start_page_address } else { 0 }; - data[page_offset..] + let data_length = if page_index == last_page_index { + let data_length = code_section_end_address - end_page_address; + // for the last page, we might need to pad with zeros if the text_section_data is not + // a multiple of the page size. + if page_size_usize > data_length { + data[page_offset + data_length..page_offset + page_size_usize].fill(0); + } + data_length + } else { + page_size_usize + }; + data[page_offset..page_offset + data_length] .copy_from_slice(&text_section_data[data_offset..data_offset + data_length]); + data_offset += data_length; } let page = Page { @@ -115,7 +124,7 @@ pub fn parse_riscv32(path: &Path) -> Result { // Entry point of the program let pc: u32 = file.ehdr.e_entry as u32; - assert!(pc != 0, "Entry point is 0. The documentation of the ELF library says that it means the ELF doesn't have an entry point. This is not supported. This can happen if the binary given is an object file and not an executable file. You might need to call the linker (ld) before running the binary."); + assert!(pc != 0, "Entry point is 0. The documentation of the ELF library says that it means the ELF doesn't have an entry point. This is not supported."); let next_pc: u32 = pc + 4u32; let state = State { @@ -143,3 +152,22 @@ pub fn parse_riscv32(path: &Path) -> Result { Ok(state) } + +pub fn parse_elf(arch: Architecture, path: &Path) -> Result { + debug!("Start parsing the ELF file to load a compatible state"); + let file_data = std::fs::read(path).expect("Could not read file."); + let slice = file_data.as_slice(); + match arch { + Architecture::Mips => { + let file = ElfBytes::::minimal_parse(slice).expect("Open ELF file failed."); + assert_eq!(file.ehdr.e_machine, 8); + make_state(file) + } + Architecture::RiscV => { + let file = + ElfBytes::::minimal_parse(slice).expect("Open ELF file failed."); + assert_eq!(file.ehdr.e_machine, 243); + make_state(file) + } + } +} diff --git a/o1vm/src/interpreters/mips/witness.rs b/o1vm/src/interpreters/mips/witness.rs index 991b946c8d..b5fa8161a0 100644 --- a/o1vm/src/interpreters/mips/witness.rs +++ b/o1vm/src/interpreters/mips/witness.rs @@ -1143,7 +1143,7 @@ impl Env { pub fn step( &mut self, config: &VmConfiguration, - metadata: &Meta, + metadata: &Option, start: &Start, ) -> Instruction { self.reset_scratch_state(); @@ -1267,7 +1267,7 @@ impl Env { } } - fn pp_info(&mut self, at: &StepFrequency, meta: &Meta, start: &Start) { + fn pp_info(&mut self, at: &StepFrequency, meta: &Option, start: &Start) { if self.should_trigger_at(at) { let elapsed = start.time.elapsed(); // Compute the step number removing the MAX_ACC factor @@ -1286,8 +1286,9 @@ impl Env { let mem = self.memory_usage(); let name = meta - .find_address_symbol(pc) - .unwrap_or_else(|| "n/a".to_string()); + .as_ref() + .and_then(|m| m.find_address_symbol(pc)) + .unwrap_or("n/a".to_string()); info!( "processing step={} pc={:010x} insn={:010x} ips={:.2} pages={} mem={} name={}", diff --git a/o1vm/src/legacy/main.rs b/o1vm/src/legacy/main.rs index ade183ede2..e49de199a0 100644 --- a/o1vm/src/legacy/main.rs +++ b/o1vm/src/legacy/main.rs @@ -5,8 +5,8 @@ use kimchi::o1_utils; use kimchi_msm::{proof::ProofInputs, prover::prove, verifier::verify, witness::Witness}; use log::debug; use o1vm::{ - cannon::{self, Meta, Start, State}, - cli, + cannon::{self, Start, State}, + cli, elf_loader, interpreters::{ keccak::{ column::{Steps, N_ZKVM_KECCAK_COLS, N_ZKVM_KECCAK_REL_COLS, N_ZKVM_KECCAK_SEL_COLS}, @@ -33,7 +33,9 @@ use o1vm::{ test_preimage_read, }; use poly_commitment::SRS as _; -use std::{cmp::Ordering, collections::HashMap, fs::File, io::BufReader, process::ExitCode}; +use std::{ + cmp::Ordering, collections::HashMap, fs::File, io::BufReader, path::Path, process::ExitCode, +}; use strum::IntoEnumIterator; /// Domain size shared by the Keccak evaluations, MIPS evaluation and main @@ -50,18 +52,11 @@ pub fn cannon_main(args: cli::cannon::RunArgs) { // Read the JSON contents of the file as an instance of `State`. let state: State = serde_json::from_reader(reader).expect("Error reading input state file"); - let meta_file = File::open(&configuration.metadata_file).unwrap_or_else(|_| { - panic!( - "Could not open metadata file {}", - &configuration.metadata_file - ) - }); - - let meta: Meta = serde_json::from_reader(BufReader::new(meta_file)).unwrap_or_else(|_| { - panic!( - "Error deserializing metadata file {}", - &configuration.metadata_file - ) + let meta = &configuration.metadata_file.as_ref().map(|f| { + let meta_file = + File::open(f).unwrap_or_else(|_| panic!("Could not open metadata file {}", f)); + serde_json::from_reader(BufReader::new(meta_file)) + .unwrap_or_else(|_| panic!("Error deserializing metadata file {}", f)) }); let mut po = PreImageOracle::create(&configuration.host); @@ -124,7 +119,7 @@ pub fn cannon_main(args: cli::cannon::RunArgs) { } while !mips_wit_env.halt { - let instr = mips_wit_env.step(&configuration, &meta, &start); + let instr = mips_wit_env.step(&configuration, meta, &start); if let Some(ref mut keccak_env) = mips_wit_env.keccak_env { // Run all steps of hash @@ -327,6 +322,14 @@ pub fn cannon_main(args: cli::cannon::RunArgs) { // TODO: Logic } +fn gen_state_json(arg: cli::cannon::GenStateJsonArgs) -> Result<(), String> { + let path = Path::new(&arg.input); + let state = elf_loader::parse_elf(elf_loader::Architecture::Mips, path)?; + let file = File::create(&arg.output).expect("Error creating output state file"); + serde_json::to_writer_pretty(file, &state).expect("Error writing output state file"); + Ok(()) +} + pub fn main() -> ExitCode { env_logger::Builder::from_env(env_logger::Env::default().default_filter_or("info")).init(); let args = cli::Commands::parse(); @@ -338,6 +341,9 @@ pub fn main() -> ExitCode { cli::cannon::Cannon::TestPreimageRead(args) => { test_preimage_read::main(args); } + cli::cannon::Cannon::GenStateJson(args) => { + gen_state_json(args).expect("Error generating state.json"); + } }, } ExitCode::SUCCESS diff --git a/o1vm/src/pickles/main.rs b/o1vm/src/pickles/main.rs index 03ce2c7fa8..696dad2d68 100644 --- a/o1vm/src/pickles/main.rs +++ b/o1vm/src/pickles/main.rs @@ -9,8 +9,8 @@ use mina_poseidon::{ sponge::{DefaultFqSponge, DefaultFrSponge}, }; use o1vm::{ - cannon::{self, Meta, Start, State}, - cli, + cannon::{self, Start, State}, + cli, elf_loader, interpreters::mips::{ column::N_MIPS_REL_COLS, constraints as mips_constraints, @@ -23,7 +23,7 @@ use o1vm::{ test_preimage_read, }; use poly_commitment::{ipa::SRS, SRS as _}; -use std::{fs::File, io::BufReader, process::ExitCode, time::Instant}; +use std::{fs::File, io::BufReader, path::Path, process::ExitCode, time::Instant}; use strum::IntoEnumIterator; pub const DOMAIN_SIZE: usize = 1 << 15; @@ -40,18 +40,11 @@ pub fn cannon_main(args: cli::cannon::RunArgs) { // Read the JSON contents of the file as an instance of `State`. let state: State = serde_json::from_reader(reader).expect("Error reading input state file"); - let meta_file = File::open(&configuration.metadata_file).unwrap_or_else(|_| { - panic!( - "Could not open metadata file {}", - &configuration.metadata_file - ) - }); - - let meta: Meta = serde_json::from_reader(BufReader::new(meta_file)).unwrap_or_else(|_| { - panic!( - "Error deserializing metadata file {}", - &configuration.metadata_file - ) + let meta = &configuration.metadata_file.as_ref().map(|f| { + let meta_file = + File::open(f).unwrap_or_else(|_| panic!("Could not open metadata file {}", f)); + serde_json::from_reader(BufReader::new(meta_file)) + .unwrap_or_else(|_| panic!("Error deserializing metadata file {}", f)) }); let mut po = PreImageOracle::create(&configuration.host); @@ -93,7 +86,7 @@ pub fn cannon_main(args: cli::cannon::RunArgs) { let mut curr_proof_inputs: ProofInputs = ProofInputs::new(DOMAIN_SIZE); while !mips_wit_env.halt { - let _instr: Instruction = mips_wit_env.step(&configuration, &meta, &start); + let _instr: Instruction = mips_wit_env.step(&configuration, meta, &start); for (scratch, scratch_chunk) in mips_wit_env .scratch_state .iter() @@ -156,6 +149,14 @@ pub fn cannon_main(args: cli::cannon::RunArgs) { } } +fn gen_state_json(arg: cli::cannon::GenStateJsonArgs) -> Result<(), String> { + let path = Path::new(&arg.input); + let state = elf_loader::parse_elf(elf_loader::Architecture::Mips, path)?; + let file = File::create(&arg.output).expect("Error creating output state file"); + serde_json::to_writer_pretty(file, &state).expect("Error writing output state file"); + Ok(()) +} + pub fn main() -> ExitCode { env_logger::Builder::from_env(env_logger::Env::default().default_filter_or("info")).init(); let args = cli::Commands::parse(); @@ -167,6 +168,9 @@ pub fn main() -> ExitCode { cli::cannon::Cannon::TestPreimageRead(args) => { test_preimage_read::main(args); } + cli::cannon::Cannon::GenStateJson(args) => { + gen_state_json(args).expect("Error generating state.json"); + } }, } ExitCode::SUCCESS diff --git a/o1vm/test-gen-state-json.sh b/o1vm/test-gen-state-json.sh new file mode 100755 index 0000000000..61a4387c7c --- /dev/null +++ b/o1vm/test-gen-state-json.sh @@ -0,0 +1,14 @@ +#!/bin/bash + +BIN_DIR=${1:-${BIN_DIR:-o1vm/resources/programs/mips/bin}} + +# Ensure the directory exists +if [[ ! -d "$BIN_DIR" ]]; then + echo "Error: Directory '$BIN_DIR' does not exist." + exit 1 +fi + +find "$BIN_DIR" -type f ! -name "*.o" | while read -r file; do + echo "Processing: $file" + cargo run --bin pickles_o1vm -- cannon gen-state-json -i "$file" +done diff --git a/o1vm/tests/test_elf_loader.rs b/o1vm/tests/test_elf_loader.rs index e473c38ccb..695ea48f78 100644 --- a/o1vm/tests/test_elf_loader.rs +++ b/o1vm/tests/test_elf_loader.rs @@ -1,3 +1,5 @@ +use o1vm::elf_loader::Architecture; + #[test] // This test is used to check that the elf loader is working correctly. // We must export the code used in this test in a function that can be called by @@ -7,7 +9,7 @@ fn test_correctly_parsing_elf() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/fibonacci", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); // This is the output we get by running objdump -d fibonacci assert_eq!(state.pc, 69932); diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index d73e008b8e..35955da91d 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -1,24 +1,14 @@ use mina_curves::pasta::Fp; -use o1vm::interpreters::riscv32im::{ - interpreter::{IInstruction, Instruction, RInstruction}, - registers::RegisterAlias::*, - witness::Env, - PAGE_SIZE, +use o1vm::{ + elf_loader::Architecture, + interpreters::riscv32im::{ + interpreter::{IInstruction, Instruction, RInstruction}, + registers::RegisterAlias::{T0, T1, T2, T3, T4, T5, T6}, + witness::Env, + PAGE_SIZE, + }, }; -#[test] -fn test_registers_indexed_by_alias() { - let curr_dir = std::env::current_dir().unwrap(); - let path = curr_dir.join(std::path::PathBuf::from( - "resources/programs/riscv32im/bin/sll", - )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); - let witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); - - assert_eq!(witness.registers[Ip], 65652); - assert_eq!(witness.registers[NextIp], 65656); -} - #[test] // Checking an instruction can be converted into a string. // It is mostly because we would want to use it to debug or write better error @@ -43,7 +33,7 @@ fn test_no_action() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/no-action", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); // This is the output we get by running objdump -d no-action assert_eq!(witness.registers.current_instruction_pointer, 69844); @@ -70,7 +60,7 @@ fn test_fibonacci_7() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/fibonacci-7", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); // This is the output we get by running objdump -d fibonacci-7 assert_eq!(witness.registers.current_instruction_pointer, 69932); @@ -86,13 +76,16 @@ fn test_fibonacci_7() { } } +// FIXME: stop ignore when all the instructions necessary for running this +// program are implemented. #[test] +#[ignore] fn test_sll() { let curr_dir = std::env::current_dir().unwrap(); let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/sll", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -109,7 +102,7 @@ fn test_addi() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/addi", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -125,7 +118,7 @@ fn test_add_1() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/add_1", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -141,7 +134,7 @@ fn test_add_2() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/add_2", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -163,7 +156,7 @@ fn test_add_overflow() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/add_overflow", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -183,7 +176,7 @@ fn test_addi_negative() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/addi_negative", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -203,7 +196,7 @@ fn test_add_sub_swap() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/add_sub_swap", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -221,7 +214,7 @@ fn test_addi_overflow() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/addi_overflow", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -239,7 +232,7 @@ fn test_addi_boundary_immediate() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/addi_boundary_immediate", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -256,7 +249,7 @@ fn test_sub() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/sub", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -273,7 +266,7 @@ fn test_sub_2() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/sub_2", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -290,7 +283,7 @@ fn test_sub_3() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/sub_3", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -307,7 +300,7 @@ fn test_xor() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/xor", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -325,7 +318,7 @@ fn test_and() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/and", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -343,7 +336,7 @@ fn test_slt() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/slt", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -362,7 +355,7 @@ fn test_div_by_zero() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/div_by_zero", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -377,7 +370,7 @@ fn test_divu_by_zero() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/divu_by_zero", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -392,7 +385,7 @@ fn test_rem_by_zero() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/rem_by_zero", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -407,7 +400,7 @@ fn test_remu_by_zero() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/remu_by_zero", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -421,7 +414,7 @@ fn test_mul_overflow() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/mul_overflow", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -437,7 +430,7 @@ fn test_jal() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/jal", )); - let state = o1vm::elf_loader::parse_riscv32(&path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { From b81e92d952004d4d21fcd00eca09667c13f7ccb4 Mon Sep 17 00:00:00 2001 From: martyall Date: Thu, 26 Dec 2024 15:30:26 -0800 Subject: [PATCH 77/80] add mips-build job, remove dead coe in elf_loader --- .github/workflows/mips-build.yml | 55 ++++++++++++++++++++++++++++++++ o1vm/meta_test.json | 37 +++++++++++++++++++++ o1vm/src/elf_loader.rs | 18 ++++------- o1vm/tests/test_riscv_elf.rs | 18 ++++++++--- 4 files changed, 112 insertions(+), 16 deletions(-) create mode 100644 .github/workflows/mips-build.yml create mode 100644 o1vm/meta_test.json diff --git a/.github/workflows/mips-build.yml b/.github/workflows/mips-build.yml new file mode 100644 index 0000000000..181ae83104 --- /dev/null +++ b/.github/workflows/mips-build.yml @@ -0,0 +1,55 @@ +name: MIPS Build and Package + +on: + workflow_dispatch: + push: + paths: + - 'o1vm/resources/programs/mips/**' + - 'Makefile' + +jobs: + build: + runs-on: ubuntu-latest + strategy: + matrix: + rust_toolchain_version: ["1.74"] + + steps: + - uses: actions/checkout@v4 + with: + submodules: 'recursive' + + - name: Cache apt packages + id: apt-cache + uses: actions/cache@v4 + with: + path: | + /var/cache/apt/archives/*.deb + key: ${{ runner.os }}-apt-${{ hashFiles('.github/workflows/mips-build.yml') }} + + - name: Install MIPS tools + run: | + sudo apt-get update + sudo apt-get install -y binutils-mips-linux-gnu + + - name: Build MIPS programs + run: make build-mips-programs + + - name: Use shared Rust toolchain setting up steps + uses: ./.github/actions/toolchain-shared + with: + rust_toolchain_version: ${{ matrix.rust_toolchain_version }} + + - name: Test elf_loader against mips programs + run: ./o1vm/test-gen-state-json.sh + + - name: Create tar archive + run: | + cd o1vm/resources/programs/mips + tar -czf mips-binaries.tar.gz bin/ + + - name: Upload artifacts + uses: actions/upload-artifact@v4 + with: + name: mips-binaries + path: o1vm/resources/programs/mips/mips-binaries.tar.gz diff --git a/o1vm/meta_test.json b/o1vm/meta_test.json new file mode 100644 index 0000000000..ab21ff5093 --- /dev/null +++ b/o1vm/meta_test.json @@ -0,0 +1,37 @@ +{ + "symbols": [ + { + "name": "go.go", + "start": 0, + "size": 0 + }, + { + "name": "internal/cpu.processOptions", + "start": 69632, + "size": 1872 + }, + { + "name": "runtime.text", + "start": 69632, + "size": 0 + }, + { + "name": "runtime/internal/atomic.(*Uint8).Load", + "start": 71504, + "size": 28 + }, + { + "name": "runtime/internal/atomic.(*Uint8).Store", + "start": 71532, + "size": 28 + }, + { + "name": "runtime/internal/atomic.(*Uint8).And", + "start": 71560, + "size": 88 + }, + { + "name": "runtime/internal/atomic.(*Uint8).Or", + "start": 71648, + "size": 72 + }]} \ No newline at end of file diff --git a/o1vm/src/elf_loader.rs b/o1vm/src/elf_loader.rs index 46270a2d45..89e698f2ff 100644 --- a/o1vm/src/elf_loader.rs +++ b/o1vm/src/elf_loader.rs @@ -84,22 +84,16 @@ pub fn make_state(file: ElfBytes) -> Result { .copy_from_slice(&text_section_data[0..data_length]); data_offset += data_length; } else { + let data_length = if page_index == last_page_index { + code_section_end_address - end_page_address + } else { + page_size_usize + }; let page_offset = if page_index == first_page_index { code_section_starting_address - start_page_address } else { 0 }; - let data_length = if page_index == last_page_index { - let data_length = code_section_end_address - end_page_address; - // for the last page, we might need to pad with zeros if the text_section_data is not - // a multiple of the page size. - if page_size_usize > data_length { - data[page_offset + data_length..page_offset + page_size_usize].fill(0); - } - data_length - } else { - page_size_usize - }; data[page_offset..page_offset + data_length] .copy_from_slice(&text_section_data[data_offset..data_offset + data_length]); @@ -124,7 +118,7 @@ pub fn make_state(file: ElfBytes) -> Result { // Entry point of the program let pc: u32 = file.ehdr.e_entry as u32; - assert!(pc != 0, "Entry point is 0. The documentation of the ELF library says that it means the ELF doesn't have an entry point. This is not supported."); + assert!(pc != 0, "Entry point is 0. The documentation of the ELF library says that it means the ELF doesn't have an entry point. This is not supported. This can happen if the binary given is an object file and not an executable file. You might need to call the linker (ld) before running the binary."); let next_pc: u32 = pc + 4u32; let state = State { diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index 35955da91d..bedaed0047 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -3,12 +3,25 @@ use o1vm::{ elf_loader::Architecture, interpreters::riscv32im::{ interpreter::{IInstruction, Instruction, RInstruction}, - registers::RegisterAlias::{T0, T1, T2, T3, T4, T5, T6}, + registers::RegisterAlias::*, witness::Env, PAGE_SIZE, }, }; +#[test] +fn test_registers_indexed_by_alias() { + let curr_dir = std::env::current_dir().unwrap(); + let path = curr_dir.join(std::path::PathBuf::from( + "resources/programs/riscv32im/bin/sll", + )); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); + + assert_eq!(witness.registers[Ip], 65652); + assert_eq!(witness.registers[NextIp], 65656); +} + #[test] // Checking an instruction can be converted into a string. // It is mostly because we would want to use it to debug or write better error @@ -76,10 +89,7 @@ fn test_fibonacci_7() { } } -// FIXME: stop ignore when all the instructions necessary for running this -// program are implemented. #[test] -#[ignore] fn test_sll() { let curr_dir = std::env::current_dir().unwrap(); let path = curr_dir.join(std::path::PathBuf::from( From 57c7ec1808600115ad7c7dbaff6a2bd7ce706578 Mon Sep 17 00:00:00 2001 From: martyall Date: Thu, 2 Jan 2025 08:30:25 -0800 Subject: [PATCH 78/80] danny pr review comments --- README.md | 2 ++ o1vm/meta_test.json | 37 --------------------------- o1vm/src/elf_loader.rs | 4 +-- o1vm/tests/test_elf_loader.rs | 2 +- o1vm/tests/test_riscv_elf.rs | 48 +++++++++++++++++------------------ 5 files changed, 29 insertions(+), 64 deletions(-) delete mode 100644 o1vm/meta_test.json diff --git a/README.md b/README.md index 68f0191f5f..8f6b42bb21 100644 --- a/README.md +++ b/README.md @@ -88,6 +88,8 @@ You can visualize the documentation by opening the file `target/doc/index.html`. This workflow runs benchmarks when a pull request is labeled with "benchmark." It sets up the Rust and OCaml environments, installs necessary tools, and executes cargo criterion benchmarks on the kimchi crate. The benchmark results are then posted as a comment on the pull request for review. - [Deploy Specifications & Docs to GitHub Pages](.github/workflows/gh-page.yml). When CI passes on master, the documentation built from the rust code will be available by this [link](https://o1-labs.github.io/proof-systems/rustdoc) and the book will be available by this [link](https://o1-labs.github.io/proof-systems). +- [MIPS Build and Package](.github/workflows/mips-build.yml) + This workflow runs the assembler and linker on the programs from the OpenMips test suite, and provides a link where you can download the artifacts (recommended if you don't have / can't install the required MIPS tooling). This workflow also runs the o1vm ELF parser on the artifacts to check that our parsing is working. Currently it is run via manual trigger only -- you can find the trigger in the [GitHub actions tab](https://github.com/o1-labs/proof-systems/actions/workflows/mips-build.yml) and the link to the artifacts will appear in logs of the `Upload Artifacts` stage. ## Nix for Dependencies (WIP) diff --git a/o1vm/meta_test.json b/o1vm/meta_test.json deleted file mode 100644 index ab21ff5093..0000000000 --- a/o1vm/meta_test.json +++ /dev/null @@ -1,37 +0,0 @@ -{ - "symbols": [ - { - "name": "go.go", - "start": 0, - "size": 0 - }, - { - "name": "internal/cpu.processOptions", - "start": 69632, - "size": 1872 - }, - { - "name": "runtime.text", - "start": 69632, - "size": 0 - }, - { - "name": "runtime/internal/atomic.(*Uint8).Load", - "start": 71504, - "size": 28 - }, - { - "name": "runtime/internal/atomic.(*Uint8).Store", - "start": 71532, - "size": 28 - }, - { - "name": "runtime/internal/atomic.(*Uint8).And", - "start": 71560, - "size": 88 - }, - { - "name": "runtime/internal/atomic.(*Uint8).Or", - "start": 71648, - "size": 72 - }]} \ No newline at end of file diff --git a/o1vm/src/elf_loader.rs b/o1vm/src/elf_loader.rs index 89e698f2ff..b2e0e1009f 100644 --- a/o1vm/src/elf_loader.rs +++ b/o1vm/src/elf_loader.rs @@ -9,7 +9,7 @@ use std::{collections::HashMap, path::Path}; pub enum Architecture { Mips, - RiscV, + RiscV32, } pub fn make_state(file: ElfBytes) -> Result { @@ -157,7 +157,7 @@ pub fn parse_elf(arch: Architecture, path: &Path) -> Result { assert_eq!(file.ehdr.e_machine, 8); make_state(file) } - Architecture::RiscV => { + Architecture::RiscV32 => { let file = ElfBytes::::minimal_parse(slice).expect("Open ELF file failed."); assert_eq!(file.ehdr.e_machine, 243); diff --git a/o1vm/tests/test_elf_loader.rs b/o1vm/tests/test_elf_loader.rs index 695ea48f78..b248f8e79a 100644 --- a/o1vm/tests/test_elf_loader.rs +++ b/o1vm/tests/test_elf_loader.rs @@ -9,7 +9,7 @@ fn test_correctly_parsing_elf() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/fibonacci", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); // This is the output we get by running objdump -d fibonacci assert_eq!(state.pc, 69932); diff --git a/o1vm/tests/test_riscv_elf.rs b/o1vm/tests/test_riscv_elf.rs index bedaed0047..556f01b708 100644 --- a/o1vm/tests/test_riscv_elf.rs +++ b/o1vm/tests/test_riscv_elf.rs @@ -15,7 +15,7 @@ fn test_registers_indexed_by_alias() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/sll", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); assert_eq!(witness.registers[Ip], 65652); @@ -46,7 +46,7 @@ fn test_no_action() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/no-action", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); // This is the output we get by running objdump -d no-action assert_eq!(witness.registers.current_instruction_pointer, 69844); @@ -73,7 +73,7 @@ fn test_fibonacci_7() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/fibonacci-7", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); // This is the output we get by running objdump -d fibonacci-7 assert_eq!(witness.registers.current_instruction_pointer, 69932); @@ -95,7 +95,7 @@ fn test_sll() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/sll", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -112,7 +112,7 @@ fn test_addi() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/addi", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -128,7 +128,7 @@ fn test_add_1() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/add_1", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -144,7 +144,7 @@ fn test_add_2() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/add_2", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -166,7 +166,7 @@ fn test_add_overflow() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/add_overflow", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -186,7 +186,7 @@ fn test_addi_negative() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/addi_negative", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -206,7 +206,7 @@ fn test_add_sub_swap() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/add_sub_swap", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -224,7 +224,7 @@ fn test_addi_overflow() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/addi_overflow", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -242,7 +242,7 @@ fn test_addi_boundary_immediate() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/addi_boundary_immediate", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -259,7 +259,7 @@ fn test_sub() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/sub", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -276,7 +276,7 @@ fn test_sub_2() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/sub_2", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -293,7 +293,7 @@ fn test_sub_3() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/sub_3", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -310,7 +310,7 @@ fn test_xor() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/xor", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -328,7 +328,7 @@ fn test_and() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/and", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -346,7 +346,7 @@ fn test_slt() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/slt", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -365,7 +365,7 @@ fn test_div_by_zero() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/div_by_zero", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -380,7 +380,7 @@ fn test_divu_by_zero() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/divu_by_zero", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -395,7 +395,7 @@ fn test_rem_by_zero() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/rem_by_zero", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -410,7 +410,7 @@ fn test_remu_by_zero() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/remu_by_zero", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -424,7 +424,7 @@ fn test_mul_overflow() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/mul_overflow", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { @@ -440,7 +440,7 @@ fn test_jal() { let path = curr_dir.join(std::path::PathBuf::from( "resources/programs/riscv32im/bin/jal", )); - let state = o1vm::elf_loader::parse_elf(Architecture::RiscV, &path).unwrap(); + let state = o1vm::elf_loader::parse_elf(Architecture::RiscV32, &path).unwrap(); let mut witness = Env::::create(PAGE_SIZE.try_into().unwrap(), state); while !witness.halt { From f9c28ca2c465f65e11d307bd69715ff79faddc8f Mon Sep 17 00:00:00 2001 From: martyall Date: Thu, 2 Jan 2025 09:15:16 -0800 Subject: [PATCH 79/80] ignore generated assembly files --- .gitignore | 4 + o1vm/resources/programs/mips/src/add.asm | 38 ----- o1vm/resources/programs/mips/src/addi.asm | 38 ----- o1vm/resources/programs/mips/src/addiu.asm | 38 ----- o1vm/resources/programs/mips/src/addu.asm | 38 ----- o1vm/resources/programs/mips/src/and.asm | 42 ------ o1vm/resources/programs/mips/src/andi.asm | 37 ----- o1vm/resources/programs/mips/src/beq.asm | 50 ------- o1vm/resources/programs/mips/src/bgez.asm | 48 ------- o1vm/resources/programs/mips/src/bgtz.asm | 49 ------- o1vm/resources/programs/mips/src/blez.asm | 48 ------- o1vm/resources/programs/mips/src/bltz.asm | 50 ------- o1vm/resources/programs/mips/src/bne.asm | 50 ------- o1vm/resources/programs/mips/src/brk.asm | 22 --- o1vm/resources/programs/mips/src/clo.asm | 59 -------- o1vm/resources/programs/mips/src/clone.asm | 22 --- o1vm/resources/programs/mips/src/clz.asm | 58 -------- o1vm/resources/programs/mips/src/div.asm | 49 ------- o1vm/resources/programs/mips/src/divu.asm | 49 ------- .../programs/mips/src/exit_group.asm | 25 ---- o1vm/resources/programs/mips/src/fcntl.asm | 23 --- o1vm/resources/programs/mips/src/j.asm | 41 ------ o1vm/resources/programs/mips/src/jal.asm | 43 ------ o1vm/resources/programs/mips/src/jalr.asm | 44 ------ o1vm/resources/programs/mips/src/jr.asm | 42 ------ o1vm/resources/programs/mips/src/lb.asm | 112 --------------- o1vm/resources/programs/mips/src/lbu.asm | 64 --------- o1vm/resources/programs/mips/src/lh.asm | 80 ----------- o1vm/resources/programs/mips/src/lhu.asm | 72 ---------- o1vm/resources/programs/mips/src/lui.asm | 34 ----- o1vm/resources/programs/mips/src/lw.asm | 39 ----- o1vm/resources/programs/mips/src/lwl.asm | 78 ---------- o1vm/resources/programs/mips/src/lwr.asm | 78 ---------- o1vm/resources/programs/mips/src/mfthi.asm | 39 ----- o1vm/resources/programs/mips/src/mftlo.asm | 39 ----- o1vm/resources/programs/mips/src/mmap.asm | 24 ---- o1vm/resources/programs/mips/src/movn.asm | 42 ------ o1vm/resources/programs/mips/src/movz.asm | 42 ------ o1vm/resources/programs/mips/src/mul.asm | 42 ------ o1vm/resources/programs/mips/src/mult.asm | 49 ------- o1vm/resources/programs/mips/src/multu.asm | 49 ------- o1vm/resources/programs/mips/src/nor.asm | 41 ------ o1vm/resources/programs/mips/src/oracle.asm | 102 -------------- .../programs/mips/src/oracle_kzg.asm | 98 ------------- .../mips/src/oracle_unaligned_read.asm | 133 ------------------ .../mips/src/oracle_unaligned_write.asm | 123 ---------------- o1vm/resources/programs/mips/src/ori.asm | 34 ----- o1vm/resources/programs/mips/src/sb.asm | 54 ------- o1vm/resources/programs/mips/src/sh.asm | 50 ------- o1vm/resources/programs/mips/src/sll.asm | 40 ------ o1vm/resources/programs/mips/src/sllv.asm | 41 ------ o1vm/resources/programs/mips/src/slt.asm | 36 ----- o1vm/resources/programs/mips/src/slti.asm | 37 ----- o1vm/resources/programs/mips/src/sltiu.asm | 37 ----- o1vm/resources/programs/mips/src/sltu.asm | 36 ----- o1vm/resources/programs/mips/src/sra.asm | 40 ------ o1vm/resources/programs/mips/src/srav.asm | 41 ------ o1vm/resources/programs/mips/src/srl.asm | 40 ------ o1vm/resources/programs/mips/src/srlv.asm | 41 ------ o1vm/resources/programs/mips/src/sub.asm | 40 ------ o1vm/resources/programs/mips/src/subu.asm | 42 ------ o1vm/resources/programs/mips/src/swl.asm | 81 ----------- o1vm/resources/programs/mips/src/swr.asm | 81 ----------- o1vm/resources/programs/mips/src/xor.asm | 43 ------ o1vm/resources/programs/mips/src/xori.asm | 38 ----- 65 files changed, 4 insertions(+), 3235 deletions(-) delete mode 100644 o1vm/resources/programs/mips/src/add.asm delete mode 100644 o1vm/resources/programs/mips/src/addi.asm delete mode 100644 o1vm/resources/programs/mips/src/addiu.asm delete mode 100644 o1vm/resources/programs/mips/src/addu.asm delete mode 100644 o1vm/resources/programs/mips/src/and.asm delete mode 100644 o1vm/resources/programs/mips/src/andi.asm delete mode 100644 o1vm/resources/programs/mips/src/beq.asm delete mode 100644 o1vm/resources/programs/mips/src/bgez.asm delete mode 100644 o1vm/resources/programs/mips/src/bgtz.asm delete mode 100644 o1vm/resources/programs/mips/src/blez.asm delete mode 100644 o1vm/resources/programs/mips/src/bltz.asm delete mode 100644 o1vm/resources/programs/mips/src/bne.asm delete mode 100644 o1vm/resources/programs/mips/src/brk.asm delete mode 100644 o1vm/resources/programs/mips/src/clo.asm delete mode 100644 o1vm/resources/programs/mips/src/clone.asm delete mode 100644 o1vm/resources/programs/mips/src/clz.asm delete mode 100644 o1vm/resources/programs/mips/src/div.asm delete mode 100644 o1vm/resources/programs/mips/src/divu.asm delete mode 100644 o1vm/resources/programs/mips/src/exit_group.asm delete mode 100644 o1vm/resources/programs/mips/src/fcntl.asm delete mode 100644 o1vm/resources/programs/mips/src/j.asm delete mode 100644 o1vm/resources/programs/mips/src/jal.asm delete mode 100644 o1vm/resources/programs/mips/src/jalr.asm delete mode 100644 o1vm/resources/programs/mips/src/jr.asm delete mode 100644 o1vm/resources/programs/mips/src/lb.asm delete mode 100644 o1vm/resources/programs/mips/src/lbu.asm delete mode 100644 o1vm/resources/programs/mips/src/lh.asm delete mode 100644 o1vm/resources/programs/mips/src/lhu.asm delete mode 100644 o1vm/resources/programs/mips/src/lui.asm delete mode 100644 o1vm/resources/programs/mips/src/lw.asm delete mode 100644 o1vm/resources/programs/mips/src/lwl.asm delete mode 100644 o1vm/resources/programs/mips/src/lwr.asm delete mode 100644 o1vm/resources/programs/mips/src/mfthi.asm delete mode 100644 o1vm/resources/programs/mips/src/mftlo.asm delete mode 100644 o1vm/resources/programs/mips/src/mmap.asm delete mode 100644 o1vm/resources/programs/mips/src/movn.asm delete mode 100644 o1vm/resources/programs/mips/src/movz.asm delete mode 100644 o1vm/resources/programs/mips/src/mul.asm delete mode 100644 o1vm/resources/programs/mips/src/mult.asm delete mode 100644 o1vm/resources/programs/mips/src/multu.asm delete mode 100644 o1vm/resources/programs/mips/src/nor.asm delete mode 100644 o1vm/resources/programs/mips/src/oracle.asm delete mode 100644 o1vm/resources/programs/mips/src/oracle_kzg.asm delete mode 100644 o1vm/resources/programs/mips/src/oracle_unaligned_read.asm delete mode 100644 o1vm/resources/programs/mips/src/oracle_unaligned_write.asm delete mode 100644 o1vm/resources/programs/mips/src/ori.asm delete mode 100644 o1vm/resources/programs/mips/src/sb.asm delete mode 100644 o1vm/resources/programs/mips/src/sh.asm delete mode 100644 o1vm/resources/programs/mips/src/sll.asm delete mode 100644 o1vm/resources/programs/mips/src/sllv.asm delete mode 100644 o1vm/resources/programs/mips/src/slt.asm delete mode 100644 o1vm/resources/programs/mips/src/slti.asm delete mode 100644 o1vm/resources/programs/mips/src/sltiu.asm delete mode 100644 o1vm/resources/programs/mips/src/sltu.asm delete mode 100644 o1vm/resources/programs/mips/src/sra.asm delete mode 100644 o1vm/resources/programs/mips/src/srav.asm delete mode 100644 o1vm/resources/programs/mips/src/srl.asm delete mode 100644 o1vm/resources/programs/mips/src/srlv.asm delete mode 100644 o1vm/resources/programs/mips/src/sub.asm delete mode 100644 o1vm/resources/programs/mips/src/subu.asm delete mode 100644 o1vm/resources/programs/mips/src/swl.asm delete mode 100644 o1vm/resources/programs/mips/src/swr.asm delete mode 100644 o1vm/resources/programs/mips/src/xor.asm delete mode 100644 o1vm/resources/programs/mips/src/xori.asm diff --git a/.gitignore b/.gitignore index 2bf0a61158..4cdc7c90ff 100644 --- a/.gitignore +++ b/.gitignore @@ -44,4 +44,8 @@ o1vm/meta_test.json # Directory for the RISC-V 32bits toolchain _riscv32-gnu-toolchain o1vm/resources/programs/riscv32im/bin/*.o + +# modified assembly files generated from cannon's open mips tests +o1vm/resources/programs/mips/src +# mips binary files for open mips tests o1vm/resources/programs/mips/bin diff --git a/o1vm/resources/programs/mips/src/add.asm b/o1vm/resources/programs/mips/src/add.asm deleted file mode 100644 index 76df311e58..0000000000 --- a/o1vm/resources/programs/mips/src/add.asm +++ /dev/null @@ -1,38 +0,0 @@ -############################################################################### -# File : add.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'add' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xffff # A = 0xfffffffd (-3) - ori $t0, 0xfffd - ori $t1, $0, 0x3 # B = 0x3 - add $t2, $t0, $t1 # C = A + B = 0 - sltiu $v0, $t2, 1 # D = 1 if C == 0 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/addi.asm b/o1vm/resources/programs/mips/src/addi.asm deleted file mode 100644 index 6981d134fd..0000000000 --- a/o1vm/resources/programs/mips/src/addi.asm +++ /dev/null @@ -1,38 +0,0 @@ -############################################################################### -# File : addi.asm -# Project : MIPS32 MUX -# Author : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'addi' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xffff # A = 0xfffffffd (-3) - ori $t0, 0xfffd - addi $t1, $t0, 5 # B = A + 5 = 2 - addi $t2, $t1, 0xfffe # C = B + -2 = 0 - sltiu $v0, $t2, 1 # D = 1 if C == 0 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/addiu.asm b/o1vm/resources/programs/mips/src/addiu.asm deleted file mode 100644 index 116ce36145..0000000000 --- a/o1vm/resources/programs/mips/src/addiu.asm +++ /dev/null @@ -1,38 +0,0 @@ -############################################################################### -# File : addiu.asm -# Project : MIPS32 MUX -# Author : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'addiu' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xffff # A = 0xfffffffd (-3) - ori $t0, 0xfffd - addiu $t1, $t0, 5 # B = A + 5 = 2 - addiu $t2, $t1, 0xfffe # C = B + -2 = 0 - sltiu $v0, $t2, 1 # D = 1 if C == 0 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/addu.asm b/o1vm/resources/programs/mips/src/addu.asm deleted file mode 100644 index 328143dbc6..0000000000 --- a/o1vm/resources/programs/mips/src/addu.asm +++ /dev/null @@ -1,38 +0,0 @@ -############################################################################### -# File : addu.asm -# Project : MIPS32 MUX -# Author : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'addu' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xffff # A = 0xfffffffd (-3) - ori $t0, 0xfffd - ori $t1, $0, 0x3 # B = 0x3 - addu $t2, $t0, $t1 # C = A + B = 0 - sltiu $v0, $t2, 1 # D = 1 if C == 0 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/and.asm b/o1vm/resources/programs/mips/src/and.asm deleted file mode 100644 index 19d40b99cc..0000000000 --- a/o1vm/resources/programs/mips/src/and.asm +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################### -# File : and.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'and' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf # A = 0xdeafbeef - lui $t1, 0xaaaa # B = 0xaaaaaaaa - lui $t2, 0x5555 # C = 0x55555555 - ori $t0, 0xbeef - ori $t1, 0xaaaa - ori $t2, 0x5555 - and $t3, $t0, $t1 # D = A & B = 0x8aaaaaaa - and $t4, $t2, $t3 # E = B & D = 0 - sltiu $v0, $t4, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/andi.asm b/o1vm/resources/programs/mips/src/andi.asm deleted file mode 100644 index 78939b5d45..0000000000 --- a/o1vm/resources/programs/mips/src/andi.asm +++ /dev/null @@ -1,37 +0,0 @@ -############################################################################### -# File : andi.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'andi' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - ori $t0, $0, 0xcafe # A = 0xcafe - andi $t1, $t0, 0xaaaa # B = A & 0xaaaa = 0x8aaa - andi $t2, $t1, 0x5555 # C = B & 0x5555 = 0 - sltiu $v0, $t2, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/beq.asm b/o1vm/resources/programs/mips/src/beq.asm deleted file mode 100644 index a0733b62c8..0000000000 --- a/o1vm/resources/programs/mips/src/beq.asm +++ /dev/null @@ -1,50 +0,0 @@ -############################################################################### -# File : beq.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'beq' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - ori $t0, $0, 0xcafe - ori $t1, $0, 0xcafe - ori $v0, $0, 0 # The test result starts as a failure - beq $t0, $v0, $finish # No branch - nop - beq $t0, $t1, $target - nop - -$finish: - sw $v0, 8($s0) - sw $s1, 4($s0) - -$done: - jr $ra - nop - j $finish # Early-by-1 branch detection - -$target: - nop - ori $v0, $0, 1 # Set the result to pass - beq $0, $0, $finish # Late-by-1 branch detection (result not stored) - nop - j $finish - nop - - #### Test code end #### - diff --git a/o1vm/resources/programs/mips/src/bgez.asm b/o1vm/resources/programs/mips/src/bgez.asm deleted file mode 100644 index be7d41eb1a..0000000000 --- a/o1vm/resources/programs/mips/src/bgez.asm +++ /dev/null @@ -1,48 +0,0 @@ -############################################################################### -# File : bgez.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'bgez' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xffff - bgez $t0, $finish # No branch - nop - bgez $s1, $target - nop - -$finish: - sw $v0, 8($s0) - sw $s1, 4($s0) - -$done: - jr $ra - nop - j $finish # Early-by-1 branch detection - -$target: - nop - ori $v0, $0, 1 # Set the result to pass - bgez $0, $finish # Late-by-1 branch detection (result not stored) - nop - j $finish # Broken branch recovery - nop - - #### Test code end #### - diff --git a/o1vm/resources/programs/mips/src/bgtz.asm b/o1vm/resources/programs/mips/src/bgtz.asm deleted file mode 100644 index 27b0199b88..0000000000 --- a/o1vm/resources/programs/mips/src/bgtz.asm +++ /dev/null @@ -1,49 +0,0 @@ -############################################################################### -# File : bgtz.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'bgtz' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - ori $v0, $0, 0 # The test result starts as a failure - lui $t0, 0xffff - bgtz $t0, $finish # No branch - nop - bgtz $s1, $target - nop - -$finish: - sw $v0, 8($s0) - sw $s1, 4($s0) - -$done: - jr $ra - nop - j $finish # Early-by-1 branch detection - -$target: - nop - ori $v0, $0, 1 # Set the result to pass - bgtz $s1, $finish # Late-by-1 branch detection (result not stored) - nop - j $finish # Broken branch recovery - nop - - #### Test code end #### - diff --git a/o1vm/resources/programs/mips/src/blez.asm b/o1vm/resources/programs/mips/src/blez.asm deleted file mode 100644 index 56c11338f7..0000000000 --- a/o1vm/resources/programs/mips/src/blez.asm +++ /dev/null @@ -1,48 +0,0 @@ -############################################################################### -# File : blez.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'blez' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - ori $v0, $0, 0 # The test result starts as a failure - blez $s1, $finish # No branch - lui $t0, 0xffff - blez $t0, $target - nop - -$finish: - sw $v0, 8($s0) - sw $s1, 4($s0) - -$done: - jr $ra - nop - j $finish # Early-by-1 branch detection - -$target: - nop - ori $v0, $0, 1 # Set the result to pass - blez $0, $finish # Late-by-1 branch detection (result not stored) - nop - j $finish - nop - - #### Test code end #### - diff --git a/o1vm/resources/programs/mips/src/bltz.asm b/o1vm/resources/programs/mips/src/bltz.asm deleted file mode 100644 index 27264f7251..0000000000 --- a/o1vm/resources/programs/mips/src/bltz.asm +++ /dev/null @@ -1,50 +0,0 @@ -############################################################################### -# File : bltz.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'bltz' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - ori $v0, $0, 0 # The test result starts as a failure - bltz $0, $finish # No branch - nop - bltz $s1, $finish # No branch - lui $t0, 0xffff - bltz $t0, $target - nop - -$finish: - sw $v0, 8($s0) - sw $s1, 4($s0) - -$done: - jr $ra - nop - j $finish # Early-by-1 branch detection - -$target: - nop - ori $v0, $0, 1 # Set the result to pass - bltz $t0, $finish # Late-by-1 branch detection (result not stored) - nop - j $finish # Broken branch recovery - nop - - #### Test code end #### - diff --git a/o1vm/resources/programs/mips/src/bne.asm b/o1vm/resources/programs/mips/src/bne.asm deleted file mode 100644 index 427ba8b941..0000000000 --- a/o1vm/resources/programs/mips/src/bne.asm +++ /dev/null @@ -1,50 +0,0 @@ -############################################################################### -# File : bne.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'bne' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - ori $t0, $0, 0xcafe - ori $t1, $0, 0xcafe - ori $v0, $0, 0 # The test result starts as a failure - bne $t0, $t1, $finish # No branch - nop - bne $t0, $v0, $target - nop - -$finish: - sw $v0, 8($s0) - sw $s1, 4($s0) - -$done: - jr $ra - nop - j $finish # Early-by-1 branch detection - -$target: - nop - ori $v0, $0, 1 # Set the result to pass - bne $t0, $0, $finish # Late-by-1 branch detection (result not stored) - nop - j $finish - nop - - #### Test code end #### - diff --git a/o1vm/resources/programs/mips/src/brk.asm b/o1vm/resources/programs/mips/src/brk.asm deleted file mode 100644 index cf4ace06f3..0000000000 --- a/o1vm/resources/programs/mips/src/brk.asm +++ /dev/null @@ -1,22 +0,0 @@ -.section .text -.global __start - -__start: - li $v0, 4045 - syscall - lui $t0, 0x4000 - subu $v0, $v0, $t0 - sltiu $v0, $v0, 1 - -# save results - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/clo.asm b/o1vm/resources/programs/mips/src/clo.asm deleted file mode 100644 index 374d3fa15e..0000000000 --- a/o1vm/resources/programs/mips/src/clo.asm +++ /dev/null @@ -1,59 +0,0 @@ -############################################################################### -# File : clo.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'clo' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t2, 0xffff # 32 - ori $t2, 0xffff - lui $t3, 0xffff # 18 - ori $t3, 0xc000 - lui $t4, 0xf800 # 5 - lui $t5, 0xf000 # 4 - lui $t6, 0x7fff # 0 - ori $t7, $0, 0 # 0 - clo $s2, $t2 - clo $s3, $t3 - clo $s4, $t4 - clo $s5, $t5 - clo $s6, $t6 - clo $s7, $t7 - addiu $s2, -32 - addiu $s3, -18 - addiu $s4, -5 - addiu $s5, -4 - addiu $s6, 0 - addiu $s7, 0 - or $v1, $s2, $s3 - or $v1, $v1, $s4 - or $v1, $v1, $s5 - or $v1, $v1, $s6 - or $v1, $v1, $s7 - sltiu $v0, $v1, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/clone.asm b/o1vm/resources/programs/mips/src/clone.asm deleted file mode 100644 index 5bf53581d2..0000000000 --- a/o1vm/resources/programs/mips/src/clone.asm +++ /dev/null @@ -1,22 +0,0 @@ -.section .text -.global __start - -__start: - li $v0, 4120 - syscall - li $t0, 0x1 - subu $v0, $v0, $t0 - sltiu $v0, $v0, 1 - -# save results - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/clz.asm b/o1vm/resources/programs/mips/src/clz.asm deleted file mode 100644 index dd33c0daa2..0000000000 --- a/o1vm/resources/programs/mips/src/clz.asm +++ /dev/null @@ -1,58 +0,0 @@ -############################################################################### -# File : clz.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'clz' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t2, 0xffff # 0 - ori $t2, 0xffff - ori $t3, $0, 0x0100 # 23 - lui $t4, 0x0700 # 5 - lui $t5, 0x0f00 # 4 - lui $t6, 0x7fff # 1 - ori $t7, $0, 0 # 32 - clz $s2, $t2 - clz $s3, $t3 - clz $s4, $t4 - clz $s5, $t5 - clz $s6, $t6 - clz $s7, $t7 - addiu $s2, 0 - addiu $s3, -23 - addiu $s4, -5 - addiu $s5, -4 - addiu $s6, -1 - addiu $s7, -32 - or $v1, $s2, $s3 - or $v1, $v1, $s4 - or $v1, $v1, $s5 - or $v1, $v1, $s6 - or $v1, $v1, $s7 - sltiu $v0, $v1, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/div.asm b/o1vm/resources/programs/mips/src/div.asm deleted file mode 100644 index ae4f26ffeb..0000000000 --- a/o1vm/resources/programs/mips/src/div.asm +++ /dev/null @@ -1,49 +0,0 @@ -############################################################################### -# File : div.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'div' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0x1234 - ori $t0, 0x5678 - lui $t1, 0xc001 - ori $t1, 0xcafe - div $t1, $t0 # 0xfffffffd (q), 0xf69ece66 (r) - mfhi $t2 - mflo $t3 - lui $t4, 0xf69e - ori $t4, 0xce66 - lui $t5, 0xffff - ori $t5, 0xfffd - subu $t6, $t2, $t4 - subu $t7, $t3, $t5 - sltiu $v0, $t6, 1 - sltiu $v1, $t7, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/divu.asm b/o1vm/resources/programs/mips/src/divu.asm deleted file mode 100644 index 825fac128c..0000000000 --- a/o1vm/resources/programs/mips/src/divu.asm +++ /dev/null @@ -1,49 +0,0 @@ -############################################################################### -# File : divu.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'divu' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0x1234 - ori $t0, 0x5678 - lui $t1, 0xc001 - ori $t1, 0xcafe - divu $t1, $t0 # 0xa (q), 0x09f66a4e (r) - mfhi $t2 - mflo $t3 - lui $t4, 0x09f6 - ori $t4, 0x6a4e - lui $t5, 0x0000 - ori $t5, 0x000a - subu $t6, $t2, $t4 - subu $t7, $t3, $t5 - sltiu $v0, $t6, 1 - sltiu $v1, $t7, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/exit_group.asm b/o1vm/resources/programs/mips/src/exit_group.asm deleted file mode 100644 index 058f08f494..0000000000 --- a/o1vm/resources/programs/mips/src/exit_group.asm +++ /dev/null @@ -1,25 +0,0 @@ -.section .text -.global __start - -__start: - li $a0, 1 - li $v0, 4246 - syscall - - # Unreachable .... - # set test result to fail. - # Test runner should short-circuit before reaching this point. - li $v0, 0 - - # save results - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/fcntl.asm b/o1vm/resources/programs/mips/src/fcntl.asm deleted file mode 100644 index b199dae3ed..0000000000 --- a/o1vm/resources/programs/mips/src/fcntl.asm +++ /dev/null @@ -1,23 +0,0 @@ -.section .text -.global __start - -__start: - # fnctl(0, 3) - li $v0, 4055 - li $a0, 0x0 - li $a1, 0x3 - syscall - sltiu $v0, $v0, 1 - -# save results - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/j.asm b/o1vm/resources/programs/mips/src/j.asm deleted file mode 100644 index 3932995c82..0000000000 --- a/o1vm/resources/programs/mips/src/j.asm +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################### -# File : j.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'j' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - j $target - ori $v0, $0, 0 # The test result starts as a failure - -$finish: - sw $v0, 8($s0) - sw $s1, 4($s0) - jr $ra - nop - j $finish # Early-by-1 detection - -$target: - nop - ori $v0, $0, 1 # Set the result to pass - j $finish # Late-by 1 detection (result not written) - nop - - #### Test code end #### - diff --git a/o1vm/resources/programs/mips/src/jal.asm b/o1vm/resources/programs/mips/src/jal.asm deleted file mode 100644 index cf8abb5c66..0000000000 --- a/o1vm/resources/programs/mips/src/jal.asm +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################### -# File : jal.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'jal' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - ori $v1, $ra, 0 # Save $ra - jal $target - ori $v0, $0, 0 # The test result starts as a failure - -$finish: - sw $v0, 8($s0) - ori $ra, $v1, 0 # Restore $ra - sw $s1, 4($s0) - jr $ra - nop - j $finish # Early-by-1 detection - -$target: - nop - ori $v0, $0, 1 # Set the result to pass - jr $ra - nop - - #### Test code end #### - diff --git a/o1vm/resources/programs/mips/src/jalr.asm b/o1vm/resources/programs/mips/src/jalr.asm deleted file mode 100644 index 1a8805435a..0000000000 --- a/o1vm/resources/programs/mips/src/jalr.asm +++ /dev/null @@ -1,44 +0,0 @@ -############################################################################### -# File : jalr.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'jalr' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - ori $v1, $ra, 0 # Save $ra - la $t0, $target - jalr $t0 - ori $v0, $0, 0 # The test result starts as a failure - -$finish: - sw $v0, 8($s0) - ori $ra, $v1, 0 # Restore $ra - sw $s1, 4($s0) - jr $ra - nop - j $finish # Early-by-1 detection - -$target: - nop - ori $v0, $0, 1 # Set the result to pass - jr $ra - nop - - #### Test code end #### - diff --git a/o1vm/resources/programs/mips/src/jr.asm b/o1vm/resources/programs/mips/src/jr.asm deleted file mode 100644 index 7fd6b34e9e..0000000000 --- a/o1vm/resources/programs/mips/src/jr.asm +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################### -# File : jr.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'jr' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - la $t0, $target - jr $t0 - ori $v0, $0, 0 # The test result starts as a failure - -$finish: - sw $v0, 8($s0) - sw $s1, 4($s0) - jr $ra - nop - j $finish # Early-by-1 detection - -$target: - nop - ori $v0, $0, 1 # Set the result to pass - j $finish - nop - - #### Test code end #### - diff --git a/o1vm/resources/programs/mips/src/lb.asm b/o1vm/resources/programs/mips/src/lb.asm deleted file mode 100644 index 8ae2bdb177..0000000000 --- a/o1vm/resources/programs/mips/src/lb.asm +++ /dev/null @@ -1,112 +0,0 @@ -############################################################################### -# File : lb.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'lb' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting - ori $t0, 0x07fc # from 0xbfc00000) - lui $t1, 0xc001 - ori $t1, 0x7afe - sw $t1, 0($t0) - lb $t2, 0($t0) - lb $t3, 1($t0) - lb $t4, 2($t0) - lb $t5, 3($t0) - .ifdef big_endian - lui $t6, 0xffff - ori $t6, 0xffc0 - lui $t7, 0x0000 - ori $t7, 0x0001 - lui $t8, 0x0000 - ori $t8, 0x007a - lui $t9, 0xffff - ori $t9, 0xfffe - .else - lui $t6, 0xffff - ori $t6, 0xfffe - lui $t7, 0x0000 - ori $t7, 0x007a - lui $t8, 0x0000 - ori $t8, 0x0001 - lui $t9, 0xffff - ori $t9, 0xffc0 - .endif - subu $v1, $t2, $t6 - sltiu $v0, $v1, 1 - subu $v1, $t3, $t7 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - subu $v1, $t4, $t8 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - subu $v1, $t5, $t9 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - - # Repeat with halves swapped (sign extension corner cases) - lui $t1, 0x7afe - ori $t1, 0xc001 - sw $t1, 0($t0) - lb $t2, 0($t0) - lb $t3, 1($t0) - lb $t4, 2($t0) - lb $t5, 3($t0) - .ifdef big_endian - lui $t6, 0x0000 - ori $t6, 0x007a - lui $t7, 0xffff - ori $t7, 0xfffe - lui $t8, 0xffff - ori $t8, 0xffc0 - lui $t9, 0x0000 - ori $t9, 0x0001 - .else - lui $t6, 0x0000 - ori $t6, 0x0001 - lui $t7, 0xffff - ori $t7, 0xffc0 - lui $t8, 0xffff - ori $t8, 0xfffe - lui $t9, 0x0000 - ori $t9, 0x007a - .endif - subu $v1, $t2, $t6 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - subu $v1, $t3, $t7 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - subu $v1, $t4, $t8 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - subu $v1, $t5, $t9 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/lbu.asm b/o1vm/resources/programs/mips/src/lbu.asm deleted file mode 100644 index 9473a3b2fb..0000000000 --- a/o1vm/resources/programs/mips/src/lbu.asm +++ /dev/null @@ -1,64 +0,0 @@ -############################################################################### -# File : lbu.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'lbu' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting - ori $t0, 0x07fc # from 0xbfc00000) - lui $t1, 0xc001 - ori $t1, 0x7afe - sw $t1, 0($t0) - lbu $t2, 0($t0) - lbu $t3, 1($t0) - lbu $t4, 2($t0) - lbu $t5, 3($t0) - .ifdef big_endian - ori $t6, $0, 0x00c0 - ori $t7, $0, 0x0001 - ori $t8, $0, 0x007a - ori $t9, $0, 0x00fe - .else - ori $t6, $0, 0x00fe - ori $t7, $0, 0x007a - ori $t8, $0, 0x0001 - ori $t9, $0, 0x00c0 - .endif - subu $v1, $t2, $t6 - sltiu $v0, $v1, 1 - subu $v1, $t3, $t7 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - subu $v1, $t4, $t8 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - subu $v1, $t5, $t9 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/lh.asm b/o1vm/resources/programs/mips/src/lh.asm deleted file mode 100644 index bbf3d072c3..0000000000 --- a/o1vm/resources/programs/mips/src/lh.asm +++ /dev/null @@ -1,80 +0,0 @@ -############################################################################### -# File : lh.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'lh' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting - ori $t0, 0x07fc # from 0xbfc00000) - lui $t1, 0x7001 - ori $t1, 0xcafe - sw $t1, 0($t0) - lh $t2, 0($t0) - lh $t3, 2($t0) - .ifdef big_endian - lui $t4, 0x0000 - ori $t4, 0x7001 - lui $t5, 0xffff - ori $t5, 0xcafe - .else - lui $t4, 0xffff - ori $t4, 0xcafe - lui $t5, 0x0000 - ori $t5, 0x7001 - .endif - subu $v1, $t2, $t4 - sltiu $v0, $v1, 1 - subu $v1, $t3, $t5 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - - # Repeat with halves swapped (sign extension corner cases) - lui $t1, 0xcafe - ori $t1, 0x7001 - sw $t1, 0($t0) - lh $t2, 0($t0) - lh $t3, 2($t0) - .ifdef big_endian - lui $t4, 0xffff - ori $t4, 0xcafe - lui $t5, 0x0000 - ori $t5, 0x7001 - .else - lui $t4, 0x0000 - ori $t4, 0x7001 - lui $t5, 0xffff - ori $t5, 0xcafe - .endif - subu $v1, $t2, $t4 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - subu $v1, $t3, $t5 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/lhu.asm b/o1vm/resources/programs/mips/src/lhu.asm deleted file mode 100644 index 17399ce929..0000000000 --- a/o1vm/resources/programs/mips/src/lhu.asm +++ /dev/null @@ -1,72 +0,0 @@ -############################################################################### -# File : lhu.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'lhu' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting - ori $t0, 0x07fc # from 0xbfc00000) - lui $t1, 0x7001 - ori $t1, 0xcafe - sw $t1, 0($t0) - lhu $t2, 0($t0) - lhu $t3, 2($t0) - .ifdef big_endian - ori $t4, $0, 0x7001 - ori $t5, $0, 0xcafe - .else - ori $t4, $0, 0xcafe - ori $t5, $0, 0x7001 - .endif - subu $v1, $t2, $t4 - sltiu $v0, $v1, 1 - subu $v1, $t3, $t5 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - - # Repeat with halves swapped (sign extension corner cases) - lui $t1, 0xcafe - ori $t1, 0x7001 - sw $t1, 0($t0) - lhu $t2, 0($t0) - lhu $t3, 2($t0) - .ifdef big_endian - ori $t4, $0, 0xcafe - ori $t5, $0, 0x7001 - .else - ori $t4, $0, 0x7001 - ori $t5, $0, 0xcafe - .endif - subu $v1, $t2, $t4 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - subu $v1, $t3, $t5 - sltiu $v1, $v1, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/lui.asm b/o1vm/resources/programs/mips/src/lui.asm deleted file mode 100644 index 1b08d1b1c4..0000000000 --- a/o1vm/resources/programs/mips/src/lui.asm +++ /dev/null @@ -1,34 +0,0 @@ -############################################################################### -# File : lui.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'lui' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - ori $v0, $0, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/lw.asm b/o1vm/resources/programs/mips/src/lw.asm deleted file mode 100644 index 57eaa15dba..0000000000 --- a/o1vm/resources/programs/mips/src/lw.asm +++ /dev/null @@ -1,39 +0,0 @@ -############################################################################### -# File : lw.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'lw' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xbfc0 # Load a valid address (last word in 2KB starting - ori $t0, 0x07fc # from 0xbfc00000) - sw $0, 0($t0) - ori $t1, $0, 1 - sw $t1, 0($t0) - lw $v0, 0($t0) - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/lwl.asm b/o1vm/resources/programs/mips/src/lwl.asm deleted file mode 100644 index 8b0aa87f17..0000000000 --- a/o1vm/resources/programs/mips/src/lwl.asm +++ /dev/null @@ -1,78 +0,0 @@ -############################################################################### -# File : lwl.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'lwl' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting - ori $t0, 0x07fc # from 0xbfc00000) - lui $t1, 0xc001 # Memory word is 0xc001cafe - ori $t1, 0xcafe - sw $t1, 0($t0) - lui $t2, 0xdeaf # Register word is 0xdeafbeef - ori $t2, 0xbeef - or $t3, $0, $t2 - or $t4, $0, $t2 - or $t5, $0, $t2 - or $t6, $0, $t2 - lwl $t3, 0($t0) - lwl $t4, 1($t0) - lwl $t5, 2($t0) - lwl $t6, 3($t0) - .ifdef big_endian - lui $s3, 0xc001 # 0xc001cafe - ori $s3, 0xcafe - lui $s4, 0x01ca # 0x01cafeef - ori $s4, 0xfeef - lui $s5, 0xcafe # 0xcafebeef - ori $s5, 0xbeef - lui $s6, 0xfeaf # 0xfeafbeef - ori $s6, 0xbeef - .else - lui $s3, 0xfeaf # 0xfeafbeef - ori $s3, 0xbeef - lui $s4, 0xcafe # 0xcafebeef - ori $s4, 0xbeef - lui $s5, 0x01ca # 0x01cafeef - ori $s5, 0xfeef - lui $s6, 0xc001 # 0xc001cafe - ori $s6, 0xcafe - .endif - subu $s2, $t3, $s3 - sltiu $v0, $s2, 1 - subu $s2, $t4, $s4 - sltiu $v1, $s2, 1 - and $v0, $v0, $v1 - subu $s2, $t5, $s5 - sltiu $v1, $s2, 1 - and $v0, $v0, $v1 - subu $s2, $t6, $s6 - sltiu $v1, $s2, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/lwr.asm b/o1vm/resources/programs/mips/src/lwr.asm deleted file mode 100644 index 5561a18d5e..0000000000 --- a/o1vm/resources/programs/mips/src/lwr.asm +++ /dev/null @@ -1,78 +0,0 @@ -############################################################################### -# File : lwr.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'lwr' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting - ori $t0, 0x07fc # from 0xbfc00000) - lui $t1, 0xc001 # Memory word is 0xc001cafe - ori $t1, 0xcafe - sw $t1, 0($t0) - lui $t2, 0xdeaf # Register word is 0xdeafbeef - ori $t2, 0xbeef - or $t3, $0, $t2 - or $t4, $0, $t2 - or $t5, $0, $t2 - or $t6, $0, $t2 - lwr $t3, 0($t0) - lwr $t4, 1($t0) - lwr $t5, 2($t0) - lwr $t6, 3($t0) - .ifdef big_endian - lui $s3, 0xdeaf # 0xdeafbec0 - ori $s3, 0xbec0 - lui $s4, 0xdeaf # 0xdeafc001 - ori $s4, 0xc001 - lui $s5, 0xdec0 # 0xdec001ca - ori $s5, 0x01ca - lui $s6, 0xc001 # 0xc001cafe - ori $s6, 0xcafe - .else - lui $s3, 0xc001 # 0xc001cafe - ori $s3, 0xcafe - lui $s4, 0xdec0 # 0xdec001ca - ori $s4, 0x01ca - lui $s5, 0xdeaf # 0xdeafc001 - ori $s5, 0xc001 - lui $s6, 0xdeaf # 0xdeafbec0 - ori $s6, 0xbec0 - .endif - subu $s2, $t3, $s3 - sltiu $v0, $s2, 1 - subu $s2, $t4, $s4 - sltiu $v1, $s2, 1 - and $v0, $v0, $v1 - subu $s2, $t5, $s5 - sltiu $v1, $s2, 1 - and $v0, $v0, $v1 - subu $s2, $t6, $s6 - sltiu $v1, $s2, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/mfthi.asm b/o1vm/resources/programs/mips/src/mfthi.asm deleted file mode 100644 index ad7654b6ab..0000000000 --- a/o1vm/resources/programs/mips/src/mfthi.asm +++ /dev/null @@ -1,39 +0,0 @@ -############################################################################### -# File : mfthi.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'mthi' and 'mfhi' instructions. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf - ori $t0, 0xbeef - mthi $t0 - mfhi $t1 - subu $v1, $t0, $t1 - sltiu $v0, $v1, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/mftlo.asm b/o1vm/resources/programs/mips/src/mftlo.asm deleted file mode 100644 index e43da205ed..0000000000 --- a/o1vm/resources/programs/mips/src/mftlo.asm +++ /dev/null @@ -1,39 +0,0 @@ -############################################################################### -# File : mftlo.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'mtlo' and 'mflo' instructions. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf - ori $t0, 0xbeef - mtlo $t0 - mflo $t1 - subu $v1, $t0, $t1 - sltiu $v0, $v1, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/mmap.asm b/o1vm/resources/programs/mips/src/mmap.asm deleted file mode 100644 index 8de6fad851..0000000000 --- a/o1vm/resources/programs/mips/src/mmap.asm +++ /dev/null @@ -1,24 +0,0 @@ -.section .text -.global __start - -__start: - li $v0, 4090 - lui $a0, 0x3000 - li $a1, 4096 - syscall - lui $t0, 0x3000 - subu $v0, $v0, $t0 - sltiu $v0, $v0, 1 - - # save results - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/movn.asm b/o1vm/resources/programs/mips/src/movn.asm deleted file mode 100644 index 53b9580817..0000000000 --- a/o1vm/resources/programs/mips/src/movn.asm +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################### -# File : movn.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'movn' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf - ori $t0, $t0, 0xbeef - ori $t1, $0, 0 - movn $t2, $t0, $s1 # $t2 gets 0xdeafbeef - movn $t1, $t0, $0 # $t1 remains 0 - subu $t3, $t2, $t0 - sltiu $v0, $t3, 1 - sltiu $v1, $t1, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/movz.asm b/o1vm/resources/programs/mips/src/movz.asm deleted file mode 100644 index 74e78eacb5..0000000000 --- a/o1vm/resources/programs/mips/src/movz.asm +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################### -# File : movz.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'movz' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf - ori $t0, $t0, 0xbeef - ori $t2, $0, 0 - movz $t2, $t0, $s0 # $t2 remains 0 - movz $t1, $t0, $0 # $t1 gets 0xdeafbeef - subu $t3, $t1, $t0 - sltiu $v0, $t3, 1 - sltiu $v1, $t2, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/mul.asm b/o1vm/resources/programs/mips/src/mul.asm deleted file mode 100644 index 2474b18357..0000000000 --- a/o1vm/resources/programs/mips/src/mul.asm +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################### -# File : mul.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'mul' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0x1234 - ori $t0, 0x5678 - lui $t1, 0xc001 - ori $t1, 0xcafe - mul $t2, $t0, $t1 # 0xb2a07b10 - lui $t3, 0xb2a0 - ori $t3, 0x7b10 - subu $t4, $t2, $t3 - sltiu $v0, $t4, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/mult.asm b/o1vm/resources/programs/mips/src/mult.asm deleted file mode 100644 index 19650b33df..0000000000 --- a/o1vm/resources/programs/mips/src/mult.asm +++ /dev/null @@ -1,49 +0,0 @@ -############################################################################### -# File : mult.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'mult' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0x1234 - ori $t0, 0x5678 - lui $t1, 0xc001 - ori $t1, 0xcafe - mult $t0, $t1 # 0xfb730b05b2a07b10 - mfhi $t2 - mflo $t3 - lui $t4, 0xfb73 - ori $t4, 0x0b05 - lui $t5, 0xb2a0 - ori $t5, 0x7b10 - subu $t6, $t2, $t4 - subu $t7, $t3, $t5 - sltiu $v0, $t6, 1 - sltiu $v1, $t7, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/multu.asm b/o1vm/resources/programs/mips/src/multu.asm deleted file mode 100644 index 7ecc099961..0000000000 --- a/o1vm/resources/programs/mips/src/multu.asm +++ /dev/null @@ -1,49 +0,0 @@ -############################################################################### -# File : multu.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'multu' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0x1234 - ori $t0, 0x5678 - lui $t1, 0xc001 - ori $t1, 0xcafe - multu $t0, $t1 # 0x0da7617db2a07b10 - mfhi $t2 - mflo $t3 - lui $t4, 0x0da7 - ori $t4, 0x617d - lui $t5, 0xb2a0 - ori $t5, 0x7b10 - subu $t6, $t2, $t4 - subu $t7, $t3, $t5 - sltiu $v0, $t6, 1 - sltiu $v1, $t7, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/nor.asm b/o1vm/resources/programs/mips/src/nor.asm deleted file mode 100644 index 01b6799195..0000000000 --- a/o1vm/resources/programs/mips/src/nor.asm +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################### -# File : nor.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'nor' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf # A = 0xdeafbeef - ori $t0, $t0, 0xbeef - lui $t1, 0x3141 # B = 0x31415926 - ori $t1, $t1, 0x5926 - lui $t2, 0xffff # C = 0xfffffffe - ori $t2, $t2, 0xfffe - nor $t3, $t0, $t1 # D = nor(A,B) = 0x00100010 - nor $v0, $t2, $t3 # E = nor(C,D) = 0x1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/oracle.asm b/o1vm/resources/programs/mips/src/oracle.asm deleted file mode 100644 index 87759ab131..0000000000 --- a/o1vm/resources/programs/mips/src/oracle.asm +++ /dev/null @@ -1,102 +0,0 @@ -.section .text -.global __start - -# load hash at 0x30001000 -# 0x47173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world") -# 0x02173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world").key -__start: - lui $s0, 0x3000 - ori $s0, 0x1000 - - lui $t0, 0x0217 - ori $t0, 0x3285 - sw $t0, 0($s0) - lui $t0, 0xa8d7 - ori $t0, 0x341e - sw $t0, 4($s0) - lui $t0, 0x5e97 - ori $t0, 0x2fc6 - sw $t0, 8($s0) - lui $t0, 0x7728 - ori $t0, 0x6384 - sw $t0, 0xc($s0) - lui $t0, 0xf802 - ori $t0, 0xf8ef - sw $t0, 0x10($s0) - lui $t0, 0x42a5 - ori $t0, 0xec5f - sw $t0, 0x14($s0) - lui $t0, 0x03bb - ori $t0, 0xfa25 - sw $t0, 0x18($s0) - lui $t0, 0x4cb0 - ori $t0, 0x1fad - sw $t0, 0x1c($s0) - -# preimage request - write(fdPreimageWrite, preimageData, 32) - li $a0, 6 - li $a1, 0x30001000 - li $t0, 8 - li $a2, 4 -$writeloop: - li $v0, 4004 - syscall - addiu $a1, $a1, 4 - addiu $t0, $t0, -1 - bnez $t0, $writeloop - nop - -# preimage response to 0x30002000 - read(fdPreimageRead, addr, count) -# read preimage length - li $a0, 5 - li $a1, 0x31000000 - li $a2, 4 - li $v0, 4003 - syscall - li $a1, 0x31000004 - li $v0, 4003 - syscall -# read the preimage data - li $a1, 0x31000008 - li $t0, 3 -$readloop: - li $v0, 4003 - syscall - addiu $a1, $a1, 4 - addiu $t0, $t0, -1 - bnez $t0, $readloop - nop - -# length at 0x31000000. We also check that the lower 32 bits are zero - lui $s1, 0x3100 - lw $t0, 0($s1) - sltiu $t6, $t0, 1 - li $s1, 0x31000004 - lw $t0, 0($s1) -# should be len("hello world") == 11 - li $t4, 11 - subu $t5, $t0, $t4 - sltiu $v0, $t5, 1 - and $v0, $v0, $t6 - -# data at 0x31000008 - lw $t0, 4($s1) - lui $t4, 0x6865 - ori $t4, 0x6c6c - subu $t5, $t0, $t4 - sltiu $v1, $t5, 1 - - and $v0, $v0, $v1 - -# save results - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/oracle_kzg.asm b/o1vm/resources/programs/mips/src/oracle_kzg.asm deleted file mode 100644 index 544737e2da..0000000000 --- a/o1vm/resources/programs/mips/src/oracle_kzg.asm +++ /dev/null @@ -1,98 +0,0 @@ -.section .text -.global __start - -# load hash at 0x30001000 -# point evaluation precompile input - 01e798154708fe7789429634053cbf9f99b619f9f084048927333fce637f549b564c0a11a0f704f4fc3e8acfe0f8245f0ad1347b378fbf96e206da11a5d3630624d25032e67a7e6a4910df5834b8fe70e6bcfeeac0352434196bdf4b2485d5a18f59a8d2a1a625a17f3fea0fe5eb8c896db3764f3185481bc22f91b4aaffcca25f26936857bc3a7c2539ea8ec3a952b7873033e038326e87ed3e1276fd140253fa08e9fc25fb2d9a98527fc22a2c9612fbeafdad446cbc7bcdbdcd780af2c16a -# 0x0a44472c cb798bc5 954fc466 e6ee2c31 e1ca8a87 d000966c 629d679a 4a29921f = keccak(address(0xa) ++ precompile_input) -# 0x0644472c cb798bc5 954fc466 e6ee2c31 e1ca8a87 d000966c 629d679a 4a29921f = keccak(address(0xa) ++ precompile_input).key (precompile) -__start: - lui $s0, 0x3000 - ori $s0, 0x1000 - - lui $t0, 0x0644 - ori $t0, 0x472c - sw $t0, 0($s0) - lui $t0, 0xcb79 - ori $t0, 0x8bc5 - sw $t0, 4($s0) - lui $t0, 0x954f - ori $t0, 0xc466 - sw $t0, 8($s0) - lui $t0, 0xe6ee - ori $t0, 0x2c31 - sw $t0, 0xc($s0) - lui $t0, 0xe1ca - ori $t0, 0x8a87 - sw $t0, 0x10($s0) - lui $t0, 0xd000 - ori $t0, 0x966c - sw $t0, 0x14($s0) - lui $t0, 0x629d - ori $t0, 0x679a - sw $t0, 0x18($s0) - lui $t0, 0x4a29 - ori $t0, 0x921f - sw $t0, 0x1c($s0) - -# preimage request - write(fdPreimageWrite, preimageData, 32) - li $a0, 6 - li $a1, 0x30001000 - li $t0, 8 - li $a2, 4 -$writeloop: - li $v0, 4004 - syscall - addiu $a1, $a1, 4 - addiu $t0, $t0, -1 - bnez $t0, $writeloop - nop - -# preimage response to 0x30002000 - read(fdPreimageRead, addr, count) -# read preimage length - li $a0, 5 - li $a1, 0x31000000 - li $a2, 4 - li $v0, 4003 - syscall - li $a1, 0x31000004 - li $v0, 4003 - syscall -# read the 1 byte precompile status and 3 bytes of return data - li $a1, 0x31000008 - li $v0, 4003 - syscall - nop - -# length at 0x31000000. We also check that the lower 32 bits are zero - lui $s1, 0x3100 - lw $t0, 0($s1) - sltiu $t6, $t0, 1 - li $s1, 0x31000004 - lw $t0, 0($s1) -# should be 1 + len(blobPrecompileReturnValue) = 65 - li $t4, 65 - subu $t5, $t0, $t4 - sltiu $v0, $t5, 1 - and $v0, $v0, $t6 - -# data at 0x31000008 -# first byte is 01 status. Next 3 bytes are 0 - lw $t0, 4($s1) - lui $t4, 0x0100 - ori $t4, 0x0000 - subu $t5, $t0, $t4 - sltiu $v1, $t5, 1 - and $v0, $v0, $v1 - -# save results - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/oracle_unaligned_read.asm b/o1vm/resources/programs/mips/src/oracle_unaligned_read.asm deleted file mode 100644 index 2ee7128ba4..0000000000 --- a/o1vm/resources/programs/mips/src/oracle_unaligned_read.asm +++ /dev/null @@ -1,133 +0,0 @@ -.section .text -.global __start - -# load hash at 0x30001000 -# 0x47173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world") -# 0x02173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world").key -__start: - lui $s0, 0x3000 - ori $s0, 0x1000 - - lui $t0, 0x0217 - ori $t0, 0x3285 - sw $t0, 0($s0) - lui $t0, 0xa8d7 - ori $t0, 0x341e - sw $t0, 4($s0) - lui $t0, 0x5e97 - ori $t0, 0x2fc6 - sw $t0, 8($s0) - lui $t0, 0x7728 - ori $t0, 0x6384 - sw $t0, 0xc($s0) - lui $t0, 0xf802 - ori $t0, 0xf8ef - sw $t0, 0x10($s0) - lui $t0, 0x42a5 - ori $t0, 0xec5f - sw $t0, 0x14($s0) - lui $t0, 0x03bb - ori $t0, 0xfa25 - sw $t0, 0x18($s0) - lui $t0, 0x4cb0 - ori $t0, 0x1fad - sw $t0, 0x1c($s0) - -# preimage request - write(fdPreimageWrite, preimageData, 32) - li $a0, 6 - li $a1, 0x30001000 - li $t0, 8 - li $a2, 4 -$writeloop: - li $v0, 4004 - syscall - addiu $a1, $a1, 4 - addiu $t0, $t0, -1 - bnez $t0, $writeloop - nop - -# preimage response to 0x30002000 - read(fdPreimageRead, addr, count) -# read preimage length to unaligned addr. This will read only up to the nearest aligned byte so we have to read again. - li $a0, 5 - li $a1, 0x31000001 - li $a2, 4 - li $v0, 4003 - syscall - li $a1, 0x31000004 - li $v0, 4003 - syscall - li $a1, 0x31000008 - li $a2, 1 - li $v0, 4003 - syscall -# read the preimage data - li $a1, 0x31000009 - li $t0, 11 -$readloop: - li $v0, 4003 - li $a2, 4 - syscall - addu $a1, $a1, $v0 - subu $t0, $t0, $v0 - bnez $t0, $readloop - nop - -# length at 0x31000001. We also check that the lower 32 bits are zero - li $s1, 0x31000001 - lb $t0, 0($s1) - lb $t2, 1($s1) - sll $t2, $t2, 8 - or $t0, $t0, $t2 - lb $t2, 2($s1) - sll $t2, $t2, 16 - or $t0, $t0, $t2 -# assert len[0:3] == 0 - sltiu $v0, $t0, 1 - -# assert len[4:8] == 0 - addiu $s1, $s1, 3 - lw $t1, 0($s1) - sltiu $v1, $t1, 1 - and $v0, $v0, $v1 - -# assert len[8:9] == 11 - addiu $s1, $s1, 4 - lb $t2, 0($s1) - li $t4, 11 - subu $t5, $t2, $t4 - sltiu $v1, $t5, 1 - and $v0, $v0, $v1 - -# data at 0x31000009 - addiu $s1, $s1, 1 - lb $t0, 0($s1) - lb $t2, 1($s1) - sll $t0, $t0, 8 - or $t0, $t0, $t2 - lb $t2, 2($s1) - sll $t0, $t0, 8 - or $t0, $t0, $t2 - lb $t2, 3($s1) - sll $t0, $t0, 8 - or $t0, $t0, $t2 - - #lw $t0, 0($s1) - lui $t4, 0x6865 - ori $t4, 0x6c6c - subu $t5, $t0, $t4 - sltiu $v1, $t5, 1 - - and $v0, $v0, $v1 - -# save results - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/oracle_unaligned_write.asm b/o1vm/resources/programs/mips/src/oracle_unaligned_write.asm deleted file mode 100644 index ca242f3490..0000000000 --- a/o1vm/resources/programs/mips/src/oracle_unaligned_write.asm +++ /dev/null @@ -1,123 +0,0 @@ -.section .text -.global __start - -# load hash at 0x30001000 -# 0x47173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world") -# 0x02173285 a8d7341e 5e972fc6 77286384 f802f8ef 42a5ec5f 03bbfa25 4cb01fad = keccak("hello world").key -__start: - lui $s0, 0x3000 - ori $s0, 0x1000 - - lui $t0, 0x0217 - ori $t0, 0x3285 - sw $t0, 0($s0) - lui $t0, 0xa8d7 - ori $t0, 0x341e - sw $t0, 4($s0) - lui $t0, 0x5e97 - ori $t0, 0x2fc6 - sw $t0, 8($s0) - lui $t0, 0x7728 - ori $t0, 0x6384 - sw $t0, 0xc($s0) - lui $t0, 0xf802 - ori $t0, 0xf8ef - sw $t0, 0x10($s0) - lui $t0, 0x42a5 - ori $t0, 0xec5f - sw $t0, 0x14($s0) - lui $t0, 0x03bb - ori $t0, 0xfa25 - sw $t0, 0x18($s0) - lui $t0, 0x4cb0 - ori $t0, 0x1fad - sw $t0, 0x1c($s0) - -# preimage request - write(fdPreimageWrite, preimageData, 32) -# create stuffed buffer containing the first byte of the hash - [garbage, hash[0], garbage] - lui $s1, 0x3200 - ori $s1, 0x0000 - lui $t0, 0xFFFF - ori $t0, 0x02FF - sw $t0, 0($s1) - -# initial unaligned write for stuffed buffer - li $a0, 6 - li $a1, 0x32000002 - li $a2, 1 - li $v0, 4004 - syscall - -# write 3 bytes for realignment - li $a0, 6 - li $a1, 0x30001001 - li $a2, 3 - li $v0, 4004 - syscall - - li $a0, 6 - li $a1, 0x30001004 - li $t0, 7 - li $a2, 4 -$writeloop: - li $v0, 4004 - syscall - addiu $a1, $a1, 4 - addiu $t0, $t0, -1 - bnez $t0, $writeloop - nop - -# preimage response to 0x30002000 - read(fdPreimageRead, addr, count) -# read preimage length - li $a0, 5 - li $a1, 0x31000000 - li $a2, 4 - li $v0, 4003 - syscall - li $a1, 0x31000004 - li $v0, 4003 - syscall -# read the preimage data - li $a1, 0x31000008 - li $t0, 3 -$readloop: - li $v0, 4003 - syscall - addiu $a1, $a1, 4 - addiu $t0, $t0, -1 - bnez $t0, $readloop - nop - -# length at 0x31000000. We also check that the lower 32 bits are zero - lui $s1, 0x3100 - lw $t0, 0($s1) - sltiu $t6, $t0, 1 - li $s1, 0x31000004 - lw $t0, 0($s1) -# should be len("hello world") == 11 - li $t4, 11 - subu $t5, $t0, $t4 - sltiu $v0, $t5, 1 - and $v0, $v0, $t6 - -# data at 0x31000008 - lw $t0, 4($s1) - lui $t4, 0x6865 - ori $t4, 0x6c6c - subu $t5, $t0, $t4 - sltiu $v1, $t5, 1 - - and $v0, $v0, $v1 - -# save results - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/ori.asm b/o1vm/resources/programs/mips/src/ori.asm deleted file mode 100644 index d985d60ed5..0000000000 --- a/o1vm/resources/programs/mips/src/ori.asm +++ /dev/null @@ -1,34 +0,0 @@ -############################################################################### -# File : ori.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'ori' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - ori $v0, $s1, 0 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/sb.asm b/o1vm/resources/programs/mips/src/sb.asm deleted file mode 100644 index d05d344420..0000000000 --- a/o1vm/resources/programs/mips/src/sb.asm +++ /dev/null @@ -1,54 +0,0 @@ -############################################################################### -# File : sb.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'sb' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting - ori $t0, 0x07fc # from 0xbfc00000) - sw $0, 0($t0) - ori $t1, $0, 0xc0 - ori $t2, $0, 0x01 - ori $t3, $0, 0xca - ori $t4, $0, 0xfe - sb $t1, 0($t0) - sb $t2, 1($t0) - sb $t3, 2($t0) - sb $t4, 3($t0) - lw $t5, 0($t0) - .ifdef big_endian - lui $t6, 0xc001 - ori $t6, 0xcafe - .else - lui $t6, 0xfeca - ori $t6, 0x01c0 - .endif - subu $t7, $t5, $t6 - sltiu $v0, $t7, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/sh.asm b/o1vm/resources/programs/mips/src/sh.asm deleted file mode 100644 index c4a0e81494..0000000000 --- a/o1vm/resources/programs/mips/src/sh.asm +++ /dev/null @@ -1,50 +0,0 @@ -############################################################################### -# File : sh.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'sh' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xbfc0 # Load address 0xbfc007fc (last word in 2KB starting - ori $t0, 0x07fc # from 0xbfc00000) - sw $0, 0($t0) - ori $t1, $0, 0xc001 - ori $t2, $0, 0xcafe - sh $t1, 0($t0) - sh $t2, 2($t0) - lw $t3, 0($t0) - .ifdef big_endian - lui $t4, 0xc001 - ori $t4, 0xcafe - .else - lui $t4, 0xcafe - ori $t4, 0xc001 - .endif - subu $t5, $t3, $t4 - sltiu $v0, $t5, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/sll.asm b/o1vm/resources/programs/mips/src/sll.asm deleted file mode 100644 index 8483593f96..0000000000 --- a/o1vm/resources/programs/mips/src/sll.asm +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################### -# File : sll.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'sll' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf # A = 0xdeafbeef - ori $t0, 0xbeef - sll $t1, $t0, 4 # B = 0xdeafbeef << 4 = 0xeafbeef0 - lui $t2, 0xeafb # C = 0xeafbeef0 - ori $t2, 0xeef0 - subu $t3, $t1, $t2 - sltiu $v0, $t3, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/sllv.asm b/o1vm/resources/programs/mips/src/sllv.asm deleted file mode 100644 index c6af8848e8..0000000000 --- a/o1vm/resources/programs/mips/src/sllv.asm +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################### -# File : sllv.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'sllv' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf # A = 0xdeafbeef - ori $t0, 0xbeef - ori $t1, $0, 12 - sllv $t2, $t0, $t1 # B = 0xdeafbeef << 12 = 0xfbeef000 - lui $t3, 0xfbee - ori $t3, 0xf000 - subu $t4, $t2, $t3 - sltiu $v0, $t4, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/slt.asm b/o1vm/resources/programs/mips/src/slt.asm deleted file mode 100644 index d0a233a4a1..0000000000 --- a/o1vm/resources/programs/mips/src/slt.asm +++ /dev/null @@ -1,36 +0,0 @@ -############################################################################### -# File : slt.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'slt' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xffff - ori $t0, 0xffff - slt $v0, $t0, $s1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/slti.asm b/o1vm/resources/programs/mips/src/slti.asm deleted file mode 100644 index 6a40b9f5ad..0000000000 --- a/o1vm/resources/programs/mips/src/slti.asm +++ /dev/null @@ -1,37 +0,0 @@ -############################################################################### -# File : slti.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'slti' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0x8000 - slti $v0, $t0, 0xffff - slti $v1, $t0, 0 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/sltiu.asm b/o1vm/resources/programs/mips/src/sltiu.asm deleted file mode 100644 index 3789706ecd..0000000000 --- a/o1vm/resources/programs/mips/src/sltiu.asm +++ /dev/null @@ -1,37 +0,0 @@ -############################################################################### -# File : sltiu.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'sltiu' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0x8000 - sltiu $v0, $t0, 0xffff - sltiu $v1, $0, 0xffff - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/sltu.asm b/o1vm/resources/programs/mips/src/sltu.asm deleted file mode 100644 index 878be3ea84..0000000000 --- a/o1vm/resources/programs/mips/src/sltu.asm +++ /dev/null @@ -1,36 +0,0 @@ -############################################################################### -# File : sltu.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'sltu' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xffff - ori $t0, 0xffff - sltu $v0, $s1, $t0 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/sra.asm b/o1vm/resources/programs/mips/src/sra.asm deleted file mode 100644 index 96961d50fa..0000000000 --- a/o1vm/resources/programs/mips/src/sra.asm +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################### -# File : sra.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'sra' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf # A = 0xdeafbeef - ori $t0, 0xbeef - sra $t1, $t0, 4 # B = 0xdeafbeef >> 4 = 0xfdeafbee - lui $t2, 0xfdea # C = 0xfdeafbee - ori $t2, 0xfbee - subu $t3, $t1, $t2 # D = B - C = 0 - sltiu $v0, $t3, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/srav.asm b/o1vm/resources/programs/mips/src/srav.asm deleted file mode 100644 index 163a4240c8..0000000000 --- a/o1vm/resources/programs/mips/src/srav.asm +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################### -# File : srav.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'srav' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf # A = 0xdeafbeef - ori $t0, 0xbeef - ori $t1, $0, 12 - srav $t2, $t0, $t1 # B = 0xdeafbeef >> 12 = 0xfffdeafb - lui $t3, 0xfffd - ori $t3, 0xeafb - subu $t4, $t2, $t3 - sltiu $v0, $t4, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/srl.asm b/o1vm/resources/programs/mips/src/srl.asm deleted file mode 100644 index 66f6027ea6..0000000000 --- a/o1vm/resources/programs/mips/src/srl.asm +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################### -# File : srl.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'srl' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf # A = 0xdeafbeef - ori $t0, 0xbeef - srl $t1, $t0, 4 # B = 0xdeafbeef >> 4 = 0x0deafbee - lui $t2, 0x0dea - ori $t2, 0xfbee - subu $t3, $t1, $t2 # D = B - C = 0 - sltiu $v0, $t3, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/srlv.asm b/o1vm/resources/programs/mips/src/srlv.asm deleted file mode 100644 index 96ee97fd75..0000000000 --- a/o1vm/resources/programs/mips/src/srlv.asm +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################### -# File : srlv.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'srlv' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf # A = 0xdeafbeef - ori $t0, 0xbeef - ori $t1, $0, 12 - srlv $t2, $t0, $t1 # B = 0xdeafbeef >> 12 = 0x000deafb - lui $t3, 0x000d - ori $t3, 0xeafb - subu $t4, $t2, $t3 - sltiu $v0, $t4, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/sub.asm b/o1vm/resources/programs/mips/src/sub.asm deleted file mode 100644 index 26da5a19f5..0000000000 --- a/o1vm/resources/programs/mips/src/sub.asm +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################### -# File : sub.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'sub' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xffff # A = 0xfffffffd (-3) - ori $t0, 0xfffd - sub $t1, $t0, $t0 # B = A - A = 0 - sub $t2, $t1, $t0 # C = B - A = 0 - A = 3 - ori $t3, $0, 3 # D = 2 - sub $t4, $t2, $t3 # E = C - D = C - 2 = 0 - sltiu $v0, $t4, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/subu.asm b/o1vm/resources/programs/mips/src/subu.asm deleted file mode 100644 index 0d9ab23154..0000000000 --- a/o1vm/resources/programs/mips/src/subu.asm +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################### -# File : subu.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'subu' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xffff # A = 0xfffffffd (-3) - ori $t0, 0xfffd - ori $t1, $0, 4 # B = 4 - subu $t2, $t0, $t1 # C = A - B = 0xfffffff9 (-7) - lui $t3, 0xffff # D = 0xfffffff8 (like -8 mod 2^32) - ori $t3, 0xfff8 - subu $t4, $t2, $t3 # F = C - D = 1 - subu $t5, $t4, $s1 # G = F - 1 = 0 - sltiu $v0, $t5, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/swl.asm b/o1vm/resources/programs/mips/src/swl.asm deleted file mode 100644 index 354dadf567..0000000000 --- a/o1vm/resources/programs/mips/src/swl.asm +++ /dev/null @@ -1,81 +0,0 @@ -############################################################################### -# File : swl.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'swl' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xbfc0 # Load address 0xbfc007ec (last four words in 2KB starting - ori $t0, 0x07ec # from 0xbfc00000) - lui $t1, 0xc001 # Memory word is 0xc001cafe - ori $t1, 0xcafe - sw $t1, 0($t0) - sw $t1, 4($t0) - sw $t1, 8($t0) - sw $t1, 12($t0) - lui $t2, 0xdeaf # Register word is 0xdeafbeef - ori $t2, 0xbeef - swl $t2, 0($t0) - swl $t2, 5($t0) - swl $t2, 10($t0) - swl $t2, 15($t0) - lw $s2, 0($t0) - lw $s3, 4($t0) - lw $s4, 8($t0) - lw $s5, 12($t0) - .ifdef big_endian - lui $t3, 0xdeaf # 0xdeafbeef - ori $t3, 0xbeef - lui $t4, 0xc0de # 0xc0deafbe - ori $t4, 0xafbe - lui $t5, 0xc001 # 0xc001deaf - ori $t5, 0xdeaf - lui $t6, 0xc001 # 0xc001cade - ori $t6, 0xcade - .else - lui $t3, 0xc001 # 0xc001cade - ori $t3, 0xcade - lui $t4, 0xc001 # 0xc001deaf - ori $t4, 0xdeaf - lui $t5, 0xc0de # 0xc0deafbe - ori $t5, 0xafbe - lui $t6, 0xdeaf # 0xdeafbeef - ori $t6, 0xbeef - .endif - subu $t7, $s2, $t3 - sltiu $v0, $t7, 1 - subu $t7, $s3, $t4 - sltiu $v1, $t7, 1 - and $v0, $v0, $v1 - subu $t7, $s4, $t5 - sltiu $v1, $t7, 1 - and $v0, $v0, $v1 - subu $t7, $s5, $t6 - sltiu $v1, $t7, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/swr.asm b/o1vm/resources/programs/mips/src/swr.asm deleted file mode 100644 index 2a4301cca7..0000000000 --- a/o1vm/resources/programs/mips/src/swr.asm +++ /dev/null @@ -1,81 +0,0 @@ -############################################################################### -# File : swr.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'swr' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xbfc0 # Load address 0xbfc007ec (last four words in 2KB starting - ori $t0, 0x07ec # from 0xbfc00000) - lui $t1, 0xc001 # Memory words are 0xc001cafe - ori $t1, 0xcafe - sw $t1, 0($t0) - sw $t1, 4($t0) - sw $t1, 8($t0) - sw $t1, 12($t0) - lui $t2, 0xdeaf # Register word is 0xdeafbeef - ori $t2, 0xbeef - swr $t2, 0($t0) - swr $t2, 5($t0) - swr $t2, 10($t0) - swr $t2, 15($t0) - lw $s2, 0($t0) - lw $s3, 4($t0) - lw $s4, 8($t0) - lw $s5, 12($t0) - .ifdef big_endian - lui $t3, 0xef01 # 0xef01cafe - ori $t3, 0xcafe - lui $t4, 0xbeef # 0xbeefcafe - ori $t4, 0xcafe - lui $t5, 0xafbe # 0xafbeeffe - ori $t5, 0xeffe - lui $t6, 0xdeaf # 0xdeafbeef - ori $t6, 0xbeef - .else - lui $t3, 0xdeaf # 0xdeafbeef - ori $t3, 0xbeef - lui $t4, 0xafbe # 0xafbeeffe - ori $t4, 0xeffe - lui $t5, 0xbeef # 0xbeefcafe - ori $t5, 0xcafe - lui $t6, 0xef01 # 0xef01cafe - ori $t6, 0xcafe - .endif - subu $t7, $s2, $t3 - sltiu $v0, $t7, 1 - subu $t7, $s3, $t4 - sltiu $v1, $t7, 1 - and $v0, $v0, $v1 - subu $t7, $s4, $t5 - sltiu $v1, $t7, 1 - and $v0, $v0, $v1 - subu $t7, $s5, $t6 - sltiu $v1, $t7, 1 - and $v0, $v0, $v1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/xor.asm b/o1vm/resources/programs/mips/src/xor.asm deleted file mode 100644 index 56770a0e93..0000000000 --- a/o1vm/resources/programs/mips/src/xor.asm +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################### -# File : xor.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'xor' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - lui $t0, 0xdeaf # A = 0xdeafbeef - ori $t0, 0xbeef - lui $t1, 0x3141 # B = 0x31415926 - ori $t1, 0x5926 - lui $t2, 0xefee # C = 0xefeee7c8 - ori $t2, 0xe7c8 - xor $t3, $t0, $t1 # D = xor(A,B) = 0xefeee7c8 - xor $t4, $t2, $t3 # E = xor(C,D) = 0x1 - xor $t5, $t4, $s1 # F = xor(E,1) = 0 - sltiu $v0, $t5, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - diff --git a/o1vm/resources/programs/mips/src/xori.asm b/o1vm/resources/programs/mips/src/xori.asm deleted file mode 100644 index 491e3ba11b..0000000000 --- a/o1vm/resources/programs/mips/src/xori.asm +++ /dev/null @@ -1,38 +0,0 @@ -############################################################################### -# File : xori.asm -# Project : MIPS32 MUX -# Author: : Grant Ayers (ayers@cs.stanford.edu) -# -# Standards/Formatting: -# MIPS gas, soft tab, 80 column -# -# Description: -# Test the functionality of the 'xori' instruction. -# -############################################################################### - - -.section .text -.global __start -__start: - lui $s0, 0xbfff # Load the base address 0xbffffff0 - ori $s0, 0xfff0 - ori $s1, $0, 1 # Prepare the 'done' status - - #### Test code start #### - - ori $t0, $0, 0xdeaf # A = 0xdeaf - xori $t1, $t0, 0x3141 # B = xor(A, 0x3141) = 0xefee - xori $t2, $t1, 0xefef # C = xor(B, 0xefef) = 0x1 - xori $t3, $t2, 1 # D = xor(C, 1) = 0 - sltiu $v0, $t3, 1 - - #### Test code end #### - - sw $v0, 8($s0) # Set the test result - sw $s1, 4($s0) # Set 'done' - -$done: - jr $ra - nop - From 84c110374367105c18bab79b2a26c471b5f0e6ac Mon Sep 17 00:00:00 2001 From: martyall Date: Thu, 2 Jan 2025 09:24:43 -0800 Subject: [PATCH 80/80] no path dependent worfklow trigger --- .github/workflows/mips-build.yml | 4 ---- 1 file changed, 4 deletions(-) diff --git a/.github/workflows/mips-build.yml b/.github/workflows/mips-build.yml index 181ae83104..264a485ee4 100644 --- a/.github/workflows/mips-build.yml +++ b/.github/workflows/mips-build.yml @@ -2,10 +2,6 @@ name: MIPS Build and Package on: workflow_dispatch: - push: - paths: - - 'o1vm/resources/programs/mips/**' - - 'Makefile' jobs: build: