From e05aa78afefd9f0c8a3f65adf273e6e66463ef08 Mon Sep 17 00:00:00 2001 From: makslevental Date: Thu, 13 Jun 2024 19:08:46 -0500 Subject: [PATCH] port all the pieces of target model into iree_aie_runtime --- .../plugins/target/AMD-AIE/aie/AIEPass.cpp | 392 +- .../target/AMD-AIE/aie/AIEPathFinder.h | 257 +- .../target/AMD-AIE/aie/AIETargetCDODirect.cpp | 155 +- .../plugins/target/AMD-AIE/aie/CMakeLists.txt | 2 +- compiler/plugins/target/AMD-AIE/aie/Passes.h | 8 +- .../aie/aie_passes/AIE2_cyclostatic_dma.mlir | 48 +- .../aie/aie_passes/AIE2_cyclostatic_l1.mlir | 4 +- .../aie/aie_passes/AIE2_cyclostatic_l2.mlir | 50 +- .../aie/aie_passes/AIE2_delayed_release.mlir | 4 +- .../aie/aie_passes/AIE2_static_l1.mlir | 4 +- .../AMD-AIE/aie/aie_passes/CMakeLists.txt | 16 + .../aie/aie_passes/DeviceModelTest.cpp | 222 + .../aie/aie_passes/allocation_info_test.mlir | 4 +- .../aie/aie_passes/assign-lockIDs.mlir | 12 +- .../aie/aie_passes/base_test_AIE2.mlir | 4 +- .../target/AMD-AIE/aie/aie_passes/basic.mlir | 4 +- .../basic_alloc_memtile_simple.mlir | 4 +- .../aie/aie_passes/basic_alloc_simple.mlir | 12 +- .../cyclostatic_AIE2_sharedMem.mlir | 4 +- .../aie/aie_passes/link_test_AIE2.mlir | 4 +- .../aie/aie_passes/link_test_DDR_to_L1.mlir | 4 +- .../aie/aie_passes/link_test_L1_to_DDR.mlir | 4 +- .../aie/aie_passes/link_test_broadcast.mlir | 4 +- .../aie/aie_passes/link_test_distribute.mlir | 4 +- .../aie/aie_passes/link_test_join.mlir | 4 +- .../target/AMD-AIE/aie/aie_passes/locks1.mlir | 65 +- .../AMD-AIE/aie/aie_passes/lower_buffer.mlir | 16 +- .../AMD-AIE/aie/aie_passes/matmul_test.mlir | 4 +- .../AMD-AIE/aie/aie_passes/memTile_test.mlir | 4 +- .../aie/aie_passes/nd_dma_base_AIE2.mlir | 4 +- .../aie_passes/nd_dma_distribute_AIE2.mlir | 4 +- .../nd_dma_multiple_consumers_AIE2.mlir | 4 +- .../aie_passes/non_adjacency_test_AIE2.mlir | 4 +- .../same_core_producer_consumer_test.mlir | 4 +- .../aie/aie_passes/shim_AIE2_test.mlir | 4 +- .../aie/aie_passes/shim_broadcast_test.mlir | 4 +- .../aie/aie_passes/unit_broadcast.mlir | 248 +- .../aie_passes/unit_fixed_connections.mlir | 227 +- .../aie/aie_passes/unit_flow_test_1.mlir | 437 -- .../aie/aie_passes/unit_flow_test_2.mlir | 248 +- .../aie/aie_passes/unit_flow_test_3.mlir | 478 -- .../aie/aie_passes/unit_many_flows.mlir | 322 +- .../aie/aie_passes/unit_many_flows2.mlir | 292 +- .../AMD-AIE/aie/aie_passes/unit_memtile.mlir | 64 +- .../unit_memtile_routing_constraints.mlir | 8 +- .../AMD-AIE/aie/aie_passes/unit_mmult.mlir | 644 --- .../aie/aie_passes/unit_more_flows_shim.mlir | 121 - .../aie/aie_passes/unit_over_flows.mlir | 199 - .../aie/aie_passes/unit_routed_herd_3x1.mlir | 814 ---- .../aie/aie_passes/unit_routed_herd_3x2.mlir | 1009 ----- .../AMD-AIE/aie/aie_passes/unit_simple.mlir | 44 - .../AMD-AIE/aie/aie_passes/unit_simple2.mlir | 8 +- .../aie/aie_passes/unit_simple_flows.mlir | 20 +- .../aie/aie_passes/unit_simple_flows2.mlir | 60 +- .../aie_passes/unit_simple_flows_shim.mlir | 95 +- .../aie/aie_passes/unit_vecmul_4x4.mlir | 3855 ----------------- .../AMD-AIE/aie/aie_passes/user_assigned.mlir | 4 +- .../AMD-AIE/aie/aie_passes/via_DMA_test.mlir | 4 +- .../src/iree-amd-aie/runtime/CMakeLists.txt | 2 +- .../iree-amd-aie/runtime/iree_aie_runtime.cc | 334 ++ .../iree-amd-aie/runtime/iree_aie_runtime.h | 188 +- tests/aie_runtime/utest.cxx | 8 +- 62 files changed, 1836 insertions(+), 9244 deletions(-) create mode 100644 compiler/plugins/target/AMD-AIE/aie/aie_passes/DeviceModelTest.cpp delete mode 100644 compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_1.mlir delete mode 100644 compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_3.mlir delete mode 100644 compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_mmult.mlir delete mode 100644 compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_more_flows_shim.mlir delete mode 100644 compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_over_flows.mlir delete mode 100644 compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x1.mlir delete mode 100644 compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x2.mlir delete mode 100644 compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple.mlir delete mode 100644 compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_vecmul_4x4.mlir diff --git a/compiler/plugins/target/AMD-AIE/aie/AIEPass.cpp b/compiler/plugins/target/AMD-AIE/aie/AIEPass.cpp index 8dcbfc79e..e3abd7699 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AIEPass.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AIEPass.cpp @@ -49,6 +49,43 @@ using namespace mlir; using namespace xilinx; using namespace xilinx::AIE; +const std::map + _WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE = { + {xilinx::AIE::WireBundle::Core, StrmSwPortType::CORE}, + {xilinx::AIE::WireBundle::DMA, StrmSwPortType::DMA}, + {xilinx::AIE::WireBundle::Ctrl, StrmSwPortType::CTRL}, + {xilinx::AIE::WireBundle::FIFO, StrmSwPortType::FIFO}, + {xilinx::AIE::WireBundle::South, StrmSwPortType::SOUTH}, + {xilinx::AIE::WireBundle::West, StrmSwPortType::WEST}, + {xilinx::AIE::WireBundle::North, StrmSwPortType::NORTH}, + {xilinx::AIE::WireBundle::East, StrmSwPortType::EAST}, + // missing PLIO from WireBundle + // missing NOC from WireBundle + {xilinx::AIE::WireBundle::Trace, StrmSwPortType::TRACE}, +}; + +const std::map + _STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE = { + {StrmSwPortType::CORE, xilinx::AIE::WireBundle::Core}, + {StrmSwPortType::DMA, xilinx::AIE::WireBundle::DMA}, + {StrmSwPortType::CTRL, xilinx::AIE::WireBundle::Ctrl}, + {StrmSwPortType::FIFO, xilinx::AIE::WireBundle::FIFO}, + {StrmSwPortType::SOUTH, xilinx::AIE::WireBundle::South}, + {StrmSwPortType::WEST, xilinx::AIE::WireBundle::West}, + {StrmSwPortType::NORTH, xilinx::AIE::WireBundle::North}, + {StrmSwPortType::EAST, xilinx::AIE::WireBundle::East}, + {StrmSwPortType::TRACE, xilinx::AIE::WireBundle::Trace}, +}; + +inline StrmSwPortType WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE( + xilinx::AIE::WireBundle w) { + return _WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE.at(w); +} + +xilinx::AIE::WireBundle STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType s) { + return _STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE.at(s); +} + template class AIEAssignBufferAddressesPassBasicBase : public ::mlir::OperationPass { @@ -129,13 +166,18 @@ struct AIEAssignBufferAddressesPassBasic } }); + AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); for (auto tile : device.getOps()) { - const auto &targetModel = getTargetModel(tile); int maxDataMemorySize = 0; - if (tile.isMemTile()) - maxDataMemorySize = targetModel.getMemTileSize(); + if (tile.isShimTile()) + continue; + else if (tile.isMemTile()) + maxDataMemorySize = + targetModel.getMemTileSize(tile.colIndex(), tile.rowIndex()); else - maxDataMemorySize = targetModel.getLocalMemorySize(); + maxDataMemorySize = + targetModel.getLocalMemorySize(tile.colIndex(), tile.rowIndex()); SmallVector buffers; // Collect all the buffers for this tile. device.walk([&](BufferOp buffer) { @@ -215,7 +257,7 @@ void xilinx::AIE::registerAIEAssignBufferAddressesBasic() { #define ODD_BD_ID_START 24 struct BdIdGenerator { - BdIdGenerator(int col, int row, AMDAIENPUTargetModel targetModel) + BdIdGenerator(int col, int row, AMDAIENPUDeviceModel targetModel) : col(col), row(row), isMemTile(targetModel.isMemTile(col, row)) {} int32_t nextBdId(int channelIndex) { @@ -246,7 +288,8 @@ struct AIEAssignBufferDescriptorIDsPass AIEAssignBufferDescriptorIDsPass> { void runOnOperation() override { DeviceOp targetOp = getOperation(); - AMDAIENPUTargetModel targetModel = targetOp.getTargetModel(); + const AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); auto memOps = llvm::to_vector_of(targetOp.getOps()); llvm::append_range(memOps, targetOp.getOps()); @@ -321,8 +364,9 @@ struct AIEAssignBufferDescriptorIDsPass std::unique_ptr> AIE::createAIEAssignBufferDescriptorIDsPass() { return std::make_unique(); -} //===- AIEAssignLockIDs.cpp -------------------------------------*- C++ - //-*-===// +} + +//===- AIEAssignLockIDs.cpp -------------------------------------*- C++ // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -531,7 +575,8 @@ struct AIEPutStreamToStdLowering : OpConversionPattern { PutStreamOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { auto device = op->getParentOfType(); - const auto &targetModel = device.getTargetModel(); + AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); std::string funcName; funcName = "llvm.aie2.put."; @@ -569,7 +614,8 @@ struct AIEGetStreamToStdLowering : OpConversionPattern { GetStreamOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { auto device = op->getParentOfType(); - const auto &targetModel = device.getTargetModel(); + AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); std::string funcName; funcName = "llvm.aie2.get."; @@ -605,7 +651,8 @@ struct AIEPutCascadeToStdLowering : OpConversionPattern { PutCascadeOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { auto device = op->getParentOfType(); - const auto &targetModel = device.getTargetModel(); + AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); std::string funcName; funcName = "llvm.aie2.mcd.write.vec"; auto putMCDFunc = module.lookupSymbol(funcName); @@ -636,7 +683,8 @@ struct AIEGetCascadeToStdLowering : OpConversionPattern { GetCascadeOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { auto device = op->getParentOfType(); - const auto &targetModel = device.getTargetModel(); + AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); std::string funcName; funcName = "llvm.aie2.scd.read.vec"; auto getSCDFunc = module.lookupSymbol(funcName); @@ -670,7 +718,8 @@ struct AIEUseLockToStdLowering : OpConversionPattern { if (!device) { return module.emitOpError("Device Not found!"); } - const auto &targetModel = device.getTargetModel(); + AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); // Generate the intrinsic name std::string funcName; @@ -857,13 +906,13 @@ struct AIECoreToStandardPass return signalPassFailure(); } DeviceOp device = *m.getOps().begin(); - const auto &targetModel = device.getTargetModel(); + AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); // Ensure that we don't have an incorrect target triple. This may override // some bogus target triple in the original mlir. m->setAttr(LLVM::LLVMDialect::getTargetTripleAttrName(), - builder.getStringAttr( - getArchIntrinsicString(targetModel.getTargetArch()))); + builder.getStringAttr(getArchIntrinsicString(AIEArch::AIE2))); DenseMap> tileToBuffers; @@ -872,7 +921,7 @@ struct AIECoreToStandardPass // peano/llvm-project/llvm/lib/Target/AIE/AIEInstrInfo.td Also take a look // at the tests: peano/llvm-project/llvm/test/CodeGen/AIE builder.setInsertionPointToStart(m.getBody()); - declareAIEIntrinsics(targetModel.getTargetArch(), builder); + declareAIEIntrinsics(AIEArch::AIE2, builder); IRMapping mapper; ConversionTarget target(getContext()); @@ -924,6 +973,7 @@ struct AIECoreToStandardPass std::unique_ptr> AIE::createAIECoreToStandardPass() { return std::make_unique(); } + //===- AIECreatePathfindFlows.cpp -------------------------------*- C++ -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. @@ -950,22 +1000,24 @@ struct ConvertFlowsToInterconnect : OpConversionPattern { void addConnection(ConversionPatternRewriter &rewriter, // could be a shim-mux or a switchbox. - Interconnect op, FlowOp flowOp, WireBundle inBundle, - int inIndex, WireBundle outBundle, int outIndex) const { + Interconnect op, FlowOp flowOp, StrmSwPortType inBundle, + int inIndex, StrmSwPortType outBundle, + int outIndex) const { Region &r = op.getConnections(); Block &b = r.front(); auto point = rewriter.saveInsertionPoint(); rewriter.setInsertionPoint(b.getTerminator()); - rewriter.create(rewriter.getUnknownLoc(), inBundle, inIndex, - outBundle, outIndex); + rewriter.create( + rewriter.getUnknownLoc(), STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(inBundle), + inIndex, STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(outBundle), outIndex); rewriter.restoreInsertionPoint(point); LLVM_DEBUG(llvm::dbgs() << "\t\taddConnection() (" << op.colIndex() << "," - << op.rowIndex() << ") " << stringifyWireBundle(inBundle) - << inIndex << " -> " << stringifyWireBundle(outBundle) + << op.rowIndex() << ") " << stringifyStrmSwPortType(inBundle) + << inIndex << " -> " << stringifyStrmSwPortType(outBundle) << outIndex << "\n"); } @@ -974,22 +1026,22 @@ struct ConvertFlowsToInterconnect : OpConversionPattern { Operation *Op = flowOp.getOperation(); auto srcTile = cast(flowOp.getSource().getDefiningOp()); - TileID srcCoords = {srcTile.colIndex(), srcTile.rowIndex()}; - auto srcBundle = flowOp.getSourceBundle(); + TileLoc srcCoords = {srcTile.colIndex(), srcTile.rowIndex()}; + auto srcBundle = WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(flowOp.getSourceBundle()); auto srcChannel = flowOp.getSourceChannel(); - Port srcPort = {srcBundle, srcChannel}; + ::Port srcPort = {srcBundle, srcChannel}; #ifndef NDEBUG auto dstTile = cast(flowOp.getDest().getDefiningOp()); - TileID dstCoords = {dstTile.colIndex(), dstTile.rowIndex()}; - auto dstBundle = flowOp.getDestBundle(); + TileLoc dstCoords = {dstTile.colIndex(), dstTile.rowIndex()}; + auto dstBundle = WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(flowOp.getDestBundle()); auto dstChannel = flowOp.getDestChannel(); LLVM_DEBUG(llvm::dbgs() << "\n\t---Begin rewrite() for flowOp: (" << srcCoords.col - << ", " << srcCoords.row << ")" << stringifyWireBundle(srcBundle) - << srcChannel << " -> (" << dstCoords.col << ", " - << dstCoords.row << ")" << stringifyWireBundle(dstBundle) - << dstChannel << "\n\t"); + << ", " << srcCoords.row << ")" + << stringifyStrmSwPortType(srcBundle) << srcChannel << " -> (" + << dstCoords.col << ", " << dstCoords.row << ")" + << stringifyStrmSwPortType(dstBundle) << dstChannel << "\n\t"); #endif // if the flow (aka "net") for this FlowOp hasn't been processed yet, @@ -1006,31 +1058,14 @@ struct ConvertFlowsToInterconnect : OpConversionPattern { if (curr == srcSB && analyzer.getTile(rewriter, srcSB.col, srcSB.row).isShimNOCTile()) { // shim DMAs at start of flows - if (srcBundle == WireBundle::DMA) { + if (srcBundle == StrmSwPortType::DMA) { shimCh = srcChannel == 0 ? 3 : 7; // must be either DMA0 -> N3 or DMA1 -> N7 ShimMuxOp shimMuxOp = analyzer.getShimMux(rewriter, srcSB.col); addConnection(rewriter, cast(shimMuxOp.getOperation()), flowOp, - srcBundle, srcChannel, WireBundle::North, shimCh); - } else if (srcBundle == - WireBundle::NOC) { // must be NOC0/NOC1 -> N2/N3 or - // NOC2/NOC3 -> N6/N7 - shimCh = srcChannel >= 2 ? srcChannel + 4 : srcChannel + 2; - ShimMuxOp shimMuxOp = analyzer.getShimMux(rewriter, srcSB.col); - addConnection(rewriter, - cast(shimMuxOp.getOperation()), flowOp, - srcBundle, srcChannel, WireBundle::North, shimCh); - } else if (srcBundle == - WireBundle::PLIO) { // PLIO at start of flows with mux - if (srcChannel == 2 || srcChannel == 3 || srcChannel == 6 || - srcChannel == 7) { // Only some PLIO requrie mux - ShimMuxOp shimMuxOp = analyzer.getShimMux(rewriter, srcSB.col); - addConnection( - rewriter, cast(shimMuxOp.getOperation()), - flowOp, srcBundle, srcChannel, WireBundle::North, shimCh); - } + srcBundle, srcChannel, StrmSwPortType::NORTH, shimCh); } } for (const auto &[bundle, channel] : setting.dsts) { @@ -1038,40 +1073,34 @@ struct ConvertFlowsToInterconnect : OpConversionPattern { if (curr == srcSB && analyzer.getTile(rewriter, srcSB.col, srcSB.row) .isShimNOCorPLTile()) { addConnection(rewriter, cast(swOp.getOperation()), - flowOp, WireBundle::South, shimCh, bundle, channel); + flowOp, StrmSwPortType::SOUTH, shimCh, bundle, + channel); } else if (analyzer.getTile(rewriter, curr.col, curr.row) .isShimNOCorPLTile() && - (bundle == WireBundle::DMA || bundle == WireBundle::PLIO || - bundle == WireBundle::NOC)) { + (bundle == StrmSwPortType::DMA)) { shimCh = channel; if (analyzer.getTile(rewriter, curr.col, curr.row) .isShimNOCTile()) { // shim DMAs at end of flows - if (bundle == WireBundle::DMA) { + if (bundle == StrmSwPortType::DMA) { shimCh = channel == 0 ? 2 : 3; // must be either N2 -> DMA0 or N3 -> DMA1 ShimMuxOp shimMuxOp = analyzer.getShimMux(rewriter, curr.col); addConnection( rewriter, cast(shimMuxOp.getOperation()), - flowOp, WireBundle::North, shimCh, bundle, channel); - } else if (bundle == WireBundle::NOC) { - shimCh = channel + 2; // must be either N2/3/4/5 -> NOC0/1/2/3 - ShimMuxOp shimMuxOp = analyzer.getShimMux(rewriter, curr.col); - addConnection( - rewriter, cast(shimMuxOp.getOperation()), - flowOp, WireBundle::North, shimCh, bundle, channel); + flowOp, StrmSwPortType::NORTH, shimCh, bundle, channel); } else if (channel >= 2) { // must be PLIO...only PLIO >= 2 require mux ShimMuxOp shimMuxOp = analyzer.getShimMux(rewriter, curr.col); addConnection( rewriter, cast(shimMuxOp.getOperation()), - flowOp, WireBundle::North, shimCh, bundle, channel); + flowOp, StrmSwPortType::NORTH, shimCh, bundle, channel); } } addConnection(rewriter, cast(swOp.getOperation()), flowOp, setting.src.bundle, setting.src.channel, - WireBundle::South, shimCh); + StrmSwPortType::SOUTH, shimCh); } else { // otherwise, regular switchbox connection addConnection(rewriter, cast(swOp.getOperation()), @@ -1137,23 +1166,31 @@ void AIEPathfinderPass::runOnOperation() { // connections east-west between stream switches if (analyzer.coordToSwitchbox.count({col - 1, row})) { auto westsw = analyzer.coordToSwitchbox[{col - 1, row}]; - builder.create(builder.getUnknownLoc(), westsw, - WireBundle::East, sw, WireBundle::West); + builder.create( + builder.getUnknownLoc(), westsw, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::EAST), sw, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::WEST)); } } if (row > 0) { // connections between abstract 'core' of tile - builder.create(builder.getUnknownLoc(), tile, WireBundle::Core, - sw, WireBundle::Core); + builder.create( + builder.getUnknownLoc(), tile, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::CORE), sw, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::CORE)); // connections between abstract 'dma' of tile - builder.create(builder.getUnknownLoc(), tile, WireBundle::DMA, - sw, WireBundle::DMA); + builder.create( + builder.getUnknownLoc(), tile, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::DMA), sw, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::DMA)); // connections north-south inside array ( including connection to shim // row) if (analyzer.coordToSwitchbox.count({col, row - 1})) { auto southsw = analyzer.coordToSwitchbox[{col, row - 1}]; - builder.create(builder.getUnknownLoc(), southsw, - WireBundle::North, sw, WireBundle::South); + builder.create( + builder.getUnknownLoc(), southsw, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::NORTH), sw, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::SOUTH)); } } else if (row == 0) { if (tile.isShimNOCTile()) { @@ -1161,27 +1198,35 @@ void AIEPathfinderPass::runOnOperation() { auto shimsw = analyzer.coordToShimMux[{col, 0}]; builder.create( builder.getUnknownLoc(), shimsw, - WireBundle::North, // Changed to connect into the north - sw, WireBundle::South); + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE( + StrmSwPortType::NORTH), // Changed to connect into the + // north + sw, STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::SOUTH)); // PLIO is attached to shim mux if (analyzer.coordToPLIO.count(col)) { auto plio = analyzer.coordToPLIO[col]; - builder.create(builder.getUnknownLoc(), plio, - WireBundle::North, shimsw, - WireBundle::South); + builder.create( + builder.getUnknownLoc(), plio, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::NORTH), + shimsw, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::SOUTH)); } // abstract 'DMA' connection on tile is attached to shim mux ( in // row 0 ) - builder.create(builder.getUnknownLoc(), tile, - WireBundle::DMA, shimsw, WireBundle::DMA); + builder.create( + builder.getUnknownLoc(), tile, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::DMA), shimsw, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::DMA)); } } else if (tile.isShimPLTile()) { // PLIO is attached directly to switch if (analyzer.coordToPLIO.count(col)) { auto plio = analyzer.coordToPLIO[col]; - builder.create(builder.getUnknownLoc(), plio, - WireBundle::North, sw, WireBundle::South); + builder.create( + builder.getUnknownLoc(), plio, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::NORTH), sw, + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::SOUTH)); } } } @@ -1190,7 +1235,8 @@ void AIEPathfinderPass::runOnOperation() { // If the routing violates architecture-specific routing constraints, then // attempt to partially reroute. - const auto &targetModel = d.getTargetModel(); + AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); std::vector problemConnects; d.walk([&](ConnectOp connect) { if (auto sw = connect->getParentOfType()) { @@ -1198,8 +1244,11 @@ void AIEPathfinderPass::runOnOperation() { if (auto tile = sw.getTileOp(); tile.isMemTile() && !targetModel.isLegalMemtileConnection( - connect.getSourceBundle(), connect.getSourceChannel(), - connect.getDestBundle(), connect.getDestChannel())) { + tile.colIndex(), tile.rowIndex(), + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connect.getSourceBundle()), + connect.getSourceChannel(), + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connect.getDestBundle()), + connect.getDestChannel())) { problemConnects.push_back(connect); } } @@ -1220,36 +1269,40 @@ bool AIEPathfinderPass::attemptFixupMemTileRouting(const OpBuilder &builder, SwitchboxOp southSwOp, ConnectOp &problemConnect) { int problemNorthChannel; - if (problemConnect.getSourceBundle() == WireBundle::North) { + if (WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(problemConnect.getSourceBundle()) == + StrmSwPortType::NORTH) { problemNorthChannel = problemConnect.getSourceChannel(); - } else if (problemConnect.getDestBundle() == WireBundle::North) { + } else if (WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(problemConnect.getDestBundle()) == + StrmSwPortType::NORTH) { problemNorthChannel = problemConnect.getDestChannel(); } else return false; // Problem is not about n-s routing int problemSouthChannel; - if (problemConnect.getSourceBundle() == WireBundle::South) { + if (WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(problemConnect.getSourceBundle()) == + StrmSwPortType::SOUTH) { problemSouthChannel = problemConnect.getSourceChannel(); - } else if (problemConnect.getDestBundle() == WireBundle::South) { + } else if (WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(problemConnect.getDestBundle()) == + StrmSwPortType::SOUTH) { problemSouthChannel = problemConnect.getDestChannel(); } else return false; // Problem is not about n-s routing // Attempt to reroute northern neighbouring sw if (reconnectConnectOps(builder, northSwOp, problemConnect, true, - WireBundle::South, problemNorthChannel, + StrmSwPortType::SOUTH, problemNorthChannel, problemSouthChannel)) return true; if (reconnectConnectOps(builder, northSwOp, problemConnect, false, - WireBundle::South, problemNorthChannel, + StrmSwPortType::SOUTH, problemNorthChannel, problemSouthChannel)) return true; // Otherwise, attempt to reroute southern neighbouring sw if (reconnectConnectOps(builder, southSwOp, problemConnect, true, - WireBundle::North, problemSouthChannel, + StrmSwPortType::NORTH, problemSouthChannel, problemNorthChannel)) return true; if (reconnectConnectOps(builder, southSwOp, problemConnect, false, - WireBundle::North, problemSouthChannel, + StrmSwPortType::NORTH, problemSouthChannel, problemNorthChannel)) return true; return false; @@ -1259,40 +1312,44 @@ bool AIEPathfinderPass::reconnectConnectOps(const OpBuilder &builder, SwitchboxOp sw, ConnectOp problemConnect, bool isIncomingToSW, - WireBundle problemBundle, + StrmSwPortType problemBundle, int problemChan, int emptyChan) { bool hasEmptyChannelSlot = true; bool foundCandidateForFixup = false; ConnectOp candidate; if (isIncomingToSW) { for (ConnectOp connect : sw.getOps()) { - if (connect.getDestBundle() == problemBundle && + if (WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connect.getDestBundle()) == + problemBundle && connect.getDestChannel() == problemChan) { candidate = connect; foundCandidateForFixup = true; } - if (connect.getDestBundle() == problemBundle && + if (WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connect.getDestBundle()) == + problemBundle && connect.getDestChannel() == emptyChan) { hasEmptyChannelSlot = false; } } } else { for (ConnectOp connect : sw.getOps()) { - if (connect.getSourceBundle() == problemBundle && + if (WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connect.getSourceBundle()) == + problemBundle && connect.getSourceChannel() == problemChan) { candidate = connect; foundCandidateForFixup = true; } - if (connect.getSourceBundle() == problemBundle && + if (WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connect.getSourceBundle()) == + problemBundle && connect.getSourceChannel() == emptyChan) { hasEmptyChannelSlot = false; } } } if (foundCandidateForFixup && hasEmptyChannelSlot) { - WireBundle problemBundleOpposite = problemBundle == WireBundle::North - ? WireBundle::South - : WireBundle::North; + StrmSwPortType problemBundleOpposite = + problemBundle == StrmSwPortType::NORTH ? StrmSwPortType::SOUTH + : StrmSwPortType::NORTH; // Found empty channel slot, perform reroute if (isIncomingToSW) { replaceConnectOpWithNewDest(builder, candidate, problemBundle, emptyChan); @@ -1310,25 +1367,24 @@ bool AIEPathfinderPass::reconnectConnectOps(const OpBuilder &builder, } // Replace connect op -ConnectOp AIEPathfinderPass::replaceConnectOpWithNewDest(OpBuilder builder, - ConnectOp connect, - WireBundle newBundle, - int newChannel) { +ConnectOp AIEPathfinderPass::replaceConnectOpWithNewDest( + OpBuilder builder, ConnectOp connect, StrmSwPortType newBundle, + int newChannel) { builder.setInsertionPoint(connect); auto newOp = builder.create( builder.getUnknownLoc(), connect.getSourceBundle(), - connect.getSourceChannel(), newBundle, newChannel); + connect.getSourceChannel(), STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(newBundle), + newChannel); connect.erase(); return newOp; } -ConnectOp AIEPathfinderPass::replaceConnectOpWithNewSource(OpBuilder builder, - ConnectOp connect, - WireBundle newBundle, - int newChannel) { +ConnectOp AIEPathfinderPass::replaceConnectOpWithNewSource( + OpBuilder builder, ConnectOp connect, StrmSwPortType newBundle, + int newChannel) { builder.setInsertionPoint(connect); - auto newOp = builder.create(builder.getUnknownLoc(), newBundle, - newChannel, connect.getDestBundle(), - connect.getDestChannel()); + auto newOp = builder.create( + builder.getUnknownLoc(), STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(newBundle), + newChannel, connect.getDestBundle(), connect.getDestChannel()); connect.erase(); return newOp; } @@ -1348,6 +1404,7 @@ std::unique_ptr> createAIEPathfinderPass() { } } // namespace xilinx::AIE + //===- AIELocalizeLocks.cpp ---------------------------------------*- C++ //-*-===// // @@ -1369,7 +1426,8 @@ struct AIELocalizeLocksPass for (auto coreOp : deviceOp.getOps()) { // Collect the locks used in this core. - const auto &targetModel = getTargetModel(coreOp); + AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); auto thisTile = dyn_cast(coreOp.getTile().getDefiningOp()); int col = thisTile.colIndex(); @@ -1379,7 +1437,7 @@ struct AIELocalizeLocksPass SmallVector accessibleTiles; for (auto tile : deviceOp.getOps()) if (int dstRow = tile.rowIndex(); - targetModel.isLegalMemAffinity(col, row, tile.colIndex(), dstRow)) + targetModel.hasLegalMemAffinity(col, row, tile.colIndex(), dstRow)) accessibleTiles.push_back(tile); for (auto tile : accessibleTiles) { @@ -1387,17 +1445,16 @@ struct AIELocalizeLocksPass int dstRow = tile.rowIndex(); int cardinalMemOffset = 0; - const auto &targetModel = getTargetModel(tile); int numLocks = targetModel.getNumLocks(dstCol, dstRow); for (auto user : tile.getResult().getUsers()) if (auto lock = dyn_cast(user)) { - if (targetModel.isMemSouth(col, row, dstCol, dstRow)) + if (targetModel.hasMemSouth(col, row, dstCol, dstRow)) cardinalMemOffset = 0; - else if (targetModel.isMemWest(col, row, dstCol, dstRow)) + else if (targetModel.hasMemWest(col, row, dstCol, dstRow)) cardinalMemOffset = numLocks; - else if (targetModel.isMemNorth(col, row, dstCol, dstRow)) + else if (targetModel.hasMemNorth(col, row, dstCol, dstRow)) cardinalMemOffset = 2 * numLocks; - else if (targetModel.isMemEast(col, row, dstCol, dstRow)) + else if (targetModel.hasMemEast(col, row, dstCol, dstRow)) cardinalMemOffset = 3 * numLocks; else llvm_unreachable("Found illegal lock user!"); @@ -1421,8 +1478,10 @@ struct AIELocalizeLocksPass std::unique_ptr> AIE::createAIELocalizeLocksPass() { return std::make_unique(); -} //===- AIEObjectFifoStatefulTransform.cpp ----------------------*- MLIR - //-*-===// +} + +//===- AIEObjectFifoStatefulTransform.cpp ----------------------*- MLIR +//-*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -1458,7 +1517,8 @@ class LockAnalysis { /// Given a tile, returns next usable lockID for that tile. int getLockID(TileOp &tileOp) { - const auto &targetModel = getTargetModel(tileOp); + AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); for (unsigned i = 0; i < targetModel.getNumLocks(tileOp.getCol(), tileOp.getRow()); i++) if (int usageCnt = locksPerTile[{tileOp, i}]; usageCnt == 0) { @@ -1543,7 +1603,8 @@ struct AIEObjectFifoStatefulTransformPass /// * 1 if it is that of the second input tile, /// * 0 is no memory module is shared. bool isSharedMemory(TileOp a, TileOp b, int *share_direction) { - const auto &targetModel = getTargetModel(a.getOperation()); + AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); if ((a.isShimTile() && !b.isShimTile()) || (!a.isShimTile() && b.isShimTile())) { @@ -1557,10 +1618,10 @@ struct AIEObjectFifoStatefulTransformPass *share_direction = 0; return false; } - bool rightShared = targetModel.isLegalMemAffinity( + bool rightShared = targetModel.hasLegalMemAffinity( a.colIndex(), a.rowIndex(), b.colIndex(), b.rowIndex()); - bool leftShared = targetModel.isLegalMemAffinity( + bool leftShared = targetModel.hasLegalMemAffinity( b.colIndex(), b.rowIndex(), a.colIndex(), a.rowIndex()); if (leftShared) @@ -2480,10 +2541,12 @@ struct AIEObjectFifoStatefulTransformPass // create flow builder.setInsertionPointAfter(producer); - builder.create(builder.getUnknownLoc(), - producer.getProducerTile(), WireBundle::DMA, - producerChan.channel, consumer.getProducerTile(), - WireBundle::DMA, consumerChan.channel); + builder.create( + builder.getUnknownLoc(), producer.getProducerTile(), + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::DMA), + producerChan.channel, consumer.getProducerTile(), + STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType::DMA), + consumerChan.channel); } } @@ -2775,23 +2838,21 @@ LogicalResult DynamicTileAnalysis::runAnalysis(DeviceOp &device) { maxRow = std::max(maxRow, tileOp.rowIndex()); } - pathfinder->initialize(maxCol, maxRow, device.getTargetModel()); + pathfinder->initialize(maxCol, maxRow, + mlir::iree_compiler::AMDAIE::getDeviceModel()); // for each flow in the device, add it to pathfinder // each source can map to multiple different destinations (fanout) for (FlowOp flowOp : device.getOps()) { TileOp srcTile = cast(flowOp.getSource().getDefiningOp()); TileOp dstTile = cast(flowOp.getDest().getDefiningOp()); - TileID srcCoords = {srcTile.colIndex(), srcTile.rowIndex()}; - TileID dstCoords = {dstTile.colIndex(), dstTile.rowIndex()}; - Port srcPort = {flowOp.getSourceBundle(), flowOp.getSourceChannel()}; - Port dstPort = {flowOp.getDestBundle(), flowOp.getDestChannel()}; - LLVM_DEBUG(llvm::dbgs() - << "\tAdding Flow: (" << srcCoords.col << ", " << srcCoords.row - << ")" << stringifyWireBundle(srcPort.bundle) << srcPort.channel - << " -> (" << dstCoords.col << ", " << dstCoords.row << ")" - << stringifyWireBundle(dstPort.bundle) << dstPort.channel - << "\n"); + TileLoc srcCoords = {srcTile.colIndex(), srcTile.rowIndex()}; + TileLoc dstCoords = {dstTile.colIndex(), dstTile.rowIndex()}; + ::Port srcPort = { + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(flowOp.getSourceBundle()), + flowOp.getSourceChannel()}; + ::Port dstPort = {WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(flowOp.getDestBundle()), + flowOp.getDestChannel()}; pathfinder->addFlow(srcCoords, srcPort, dstCoords, dstPort); } @@ -2893,7 +2954,7 @@ ShimMuxOp DynamicTileAnalysis::getShimMux(OpBuilder &builder, int col) { } void Pathfinder::initialize(int maxCol, int maxRow, - AMDAIENPUTargetModel targetModel) { + AMDAIENPUDeviceModel targetModel) { // make grid of switchboxes int id = 0; for (int row = 0; row <= maxRow; row++) { @@ -2906,8 +2967,8 @@ void Pathfinder::initialize(int maxCol, int maxRow, // get the number of outgoing connections on the south side - outgoing // because these correspond to rhs of a connect op if (uint32_t maxCapacity = targetModel.getNumDestSwitchboxConnections( - col, row, WireBundle::South)) { - edges.emplace_back(thisNode, southernNeighbor, WireBundle::South, + col, row, StrmSwPortType::SOUTH)) { + edges.emplace_back(thisNode, southernNeighbor, StrmSwPortType::SOUTH, maxCapacity); (void)graph.connect(thisNode, southernNeighbor, edges.back()); } @@ -2916,8 +2977,8 @@ void Pathfinder::initialize(int maxCol, int maxRow, // routed using internal connect ops through the switchbox (i.e., lhs of // connect ops) if (uint32_t maxCapacity = targetModel.getNumSourceSwitchboxConnections( - col, row, WireBundle::South)) { - edges.emplace_back(southernNeighbor, thisNode, WireBundle::North, + col, row, StrmSwPortType::SOUTH)) { + edges.emplace_back(southernNeighbor, thisNode, StrmSwPortType::NORTH, maxCapacity); (void)graph.connect(southernNeighbor, thisNode, edges.back()); } @@ -2926,14 +2987,14 @@ void Pathfinder::initialize(int maxCol, int maxRow, if (col > 0) { // if not in col 0 add channel to East/West SwitchboxNode &westernNeighbor = grid.at({col - 1, row}); if (uint32_t maxCapacity = targetModel.getNumDestSwitchboxConnections( - col, row, WireBundle::West)) { - edges.emplace_back(thisNode, westernNeighbor, WireBundle::West, + col, row, StrmSwPortType::WEST)) { + edges.emplace_back(thisNode, westernNeighbor, StrmSwPortType::WEST, maxCapacity); (void)graph.connect(thisNode, westernNeighbor, edges.back()); } if (uint32_t maxCapacity = targetModel.getNumSourceSwitchboxConnections( - col, row, WireBundle::West)) { - edges.emplace_back(westernNeighbor, thisNode, WireBundle::East, + col, row, StrmSwPortType::WEST)) { + edges.emplace_back(westernNeighbor, thisNode, StrmSwPortType::EAST, maxCapacity); (void)graph.connect(westernNeighbor, thisNode, edges.back()); } @@ -2944,15 +3005,15 @@ void Pathfinder::initialize(int maxCol, int maxRow, // Add a flow from src to dst can have an arbitrary number of dst locations due // to fanout. -void Pathfinder::addFlow(TileID srcCoords, Port srcPort, TileID dstCoords, - Port dstPort) { +void Pathfinder::addFlow(TileLoc srcCoords, ::Port srcPort, TileLoc dstCoords, + ::Port dstPort) { // check if a flow with this source already exists for (auto &[src, dsts] : flows) { SwitchboxNode *existingSrc = src.sb; assert(existingSrc && "nullptr flow source"); - if (Port existingPort = src.port; existingSrc->col == srcCoords.col && - existingSrc->row == srcCoords.row && - existingPort == srcPort) { + if (::Port existingPort = src.port; existingSrc->col == srcCoords.col && + existingSrc->row == srcCoords.row && + existingPort == srcPort) { // find the vertex corresponding to the destination auto *matchingSb = std::find_if( graph.begin(), graph.end(), [&](const SwitchboxNode *sb) { @@ -2986,15 +3047,18 @@ bool Pathfinder::addFixedConnection(ConnectOp connectOp) { // TODO: keep track of capacity? if (sb.getTileOp().isShimNOCTile()) return true; - TileID sbTile = sb.getTileID(); - WireBundle sourceBundle = connectOp.getSourceBundle(); - WireBundle destBundle = connectOp.getDestBundle(); + TileLoc sbTile = {sb.colIndex(), sb.rowIndex()}; + StrmSwPortType sourceBundle = + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connectOp.getSourceBundle()); + StrmSwPortType destBundle = + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connectOp.getDestBundle()); // find the correct Channel and indicate the fixed direction // outgoing connection auto matchingCh = std::find_if(edges.begin(), edges.end(), [&](ChannelEdge &ch) { - return static_cast(ch.src) == sbTile && ch.bundle == destBundle; + return static_cast(ch.src) == sbTile && + ch.bundle == destBundle; }); if (matchingCh != edges.end()) return matchingCh->fixedCapacity.insert(connectOp.getDestChannel()) @@ -3003,8 +3067,8 @@ bool Pathfinder::addFixedConnection(ConnectOp connectOp) { // incoming connection matchingCh = std::find_if(edges.begin(), edges.end(), [&](ChannelEdge &ch) { - return static_cast(ch.target) == sbTile && - ch.bundle == getConnectingBundle(sourceBundle); + return static_cast(ch.target) == sbTile && + ch.bundle == getConnectingStrmSwPortType(sourceBundle); }); if (matchingCh != edges.end()) return matchingCh->fixedCapacity.insert(connectOp.getSourceChannel()) @@ -3094,8 +3158,9 @@ std::optional> Pathfinder::findPaths( LLVM_DEBUG(llvm::dbgs() << "Too much capacity on Edge (" << e.getTargetNode().col << ", " << e.getTargetNode().row << ") . " - << stringifyWireBundle(e.bundle) << "\t: used_capacity = " - << e.usedCapacity << "\t: Demand = " << e.demand << "\n"); + << stringifyStrmSwPortType(e.bundle) + << "\t: used_capacity = " << e.usedCapacity + << "\t: Demand = " << e.demand << "\n"); e.overCapacityCount++; LLVM_DEBUG(llvm::dbgs() << "over_capacity_count = " << e.overCapacityCount << "\n"); @@ -3174,7 +3239,7 @@ std::optional> Pathfinder::findPaths( while (ch->fixedCapacity.count(ch->usedCapacity)) ch->usedCapacity++; // add the entrance port for this Switchbox - switchSettings[*curr].src = {getConnectingBundle(ch->bundle), + switchSettings[*curr].src = {getConnectingStrmSwPortType(ch->bundle), ch->usedCapacity}; // add the current Switchbox to the map of the predecessor switchSettings[*preds[curr]].dsts.insert( @@ -3199,6 +3264,7 @@ std::optional> Pathfinder::findPaths( return routingSolution; } + //===- AIEXToStandard.cpp ---------------------------------------*- C++ -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. diff --git a/compiler/plugins/target/AMD-AIE/aie/AIEPathFinder.h b/compiler/plugins/target/AMD-AIE/aie/AIEPathFinder.h index 9dbc28ddb..50bca8212 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AIEPathFinder.h +++ b/compiler/plugins/target/AMD-AIE/aie/AIEPathFinder.h @@ -21,12 +21,44 @@ #include "llvm/ADT/DirectedGraph.h" #include "llvm/ADT/GraphTraits.h" -namespace xilinx::AIE { +namespace llvm { +template <> +struct DenseMapInfo { + using FirstInfo = DenseMapInfo; + using SecondInfo = DenseMapInfo; + + static TileLoc getEmptyKey() { + return {FirstInfo::getEmptyKey(), SecondInfo::getEmptyKey()}; + } + + static TileLoc getTombstoneKey() { + return {FirstInfo::getTombstoneKey(), SecondInfo::getTombstoneKey()}; + } + + static unsigned getHashValue(const TileLoc &t) { + return detail::combineHashValue(FirstInfo::getHashValue(t.col), + SecondInfo::getHashValue(t.row)); + } + + static bool isEqual(const TileLoc &lhs, const TileLoc &rhs) { + return lhs == rhs; + } +}; +} // namespace llvm + +template <> +struct std::hash { + std::size_t operator()(const TileLoc &s) const noexcept { + std::size_t h1 = std::hash{}(s.col); + std::size_t h2 = std::hash{}(s.row); + return h1 ^ (h2 << 1); + } +}; -using Switchbox = struct Switchbox : TileID { +using Switchbox = struct Switchbox : TileLoc { // Necessary for initializer construction? - Switchbox(TileID t) : TileID(t) {} - Switchbox(int col, int row) : TileID{col, row} {} + Switchbox(TileLoc t) : TileLoc(t) {} + Switchbox(int col, int row) : TileLoc{col, row} {} friend std::ostream &operator<<(std::ostream &os, const Switchbox &s) { os << "Switchbox(" << s.col << ", " << s.row << ")"; return os; @@ -35,12 +67,13 @@ using Switchbox = struct Switchbox : TileID { GENERATE_TO_STRING(Switchbox); bool operator==(const Switchbox &rhs) const { - return static_cast(*this) == rhs; + return static_cast(*this) == rhs; } }; using Channel = struct Channel { - Channel(Switchbox &src, Switchbox &target, WireBundle bundle, int maxCapacity) + Channel(Switchbox &src, Switchbox &target, StrmSwPortType bundle, + int maxCapacity) : src(src), target(target), bundle(bundle), maxCapacity(maxCapacity) {} friend std::ostream &operator<<(std::ostream &os, const Channel &c) { @@ -58,7 +91,7 @@ using Channel = struct Channel { Switchbox &src; Switchbox ⌖ - WireBundle bundle; + StrmSwPortType bundle; int maxCapacity = 0; // maximum number of routing resources double demand = 0.0; // indicates how many flows want to use this Channel int usedCapacity = 0; // how many flows are actually using this Channel @@ -66,6 +99,73 @@ using Channel = struct Channel { int overCapacityCount = 0; // history of Channel being over capacity }; +#define GENERATE_TO_STRING(TYPE_WITH_INSERTION_OP) \ + friend std::string to_string(const TYPE_WITH_INSERTION_OP &s) { \ + std::ostringstream ss; \ + ss << s; \ + return ss.str(); \ + } + +typedef struct Port { + StrmSwPortType bundle; + int channel; + + bool operator==(const Port &rhs) const { + return std::tie(bundle, channel) == std::tie(rhs.bundle, rhs.channel); + } + + bool operator!=(const Port &rhs) const { return !(*this == rhs); } + + bool operator<(const Port &rhs) const { + return std::tie(bundle, channel) < std::tie(rhs.bundle, rhs.channel); + } + + friend std::ostream &operator<<(std::ostream &os, const Port &port) { + os << "("; + switch (port.bundle) { + case StrmSwPortType::CORE: + os << "Core"; + break; + case StrmSwPortType::DMA: + os << "DMA"; + break; + case StrmSwPortType::NORTH: + os << "N"; + break; + case StrmSwPortType::EAST: + os << "E"; + break; + case StrmSwPortType::SOUTH: + os << "S"; + break; + case StrmSwPortType::WEST: + os << "W"; + break; + default: + os << "X"; + break; + } + os << ": " << std::to_string(port.channel) << ")"; + return os; + } + + GENERATE_TO_STRING(Port) + + friend llvm::raw_ostream &operator<<(llvm::raw_ostream &os, + const Port &port) { + os << to_string(port); + return os; + } + +} Port; + +template <> +struct std::less { + bool operator()(const Port &a, const Port &b) const { + return a.bundle == b.bundle ? a.channel < b.channel : a.bundle < b.bundle; + } +}; + struct SwitchboxNode; struct ChannelEdge; using SwitchboxNodeBase = llvm::DGNode; @@ -78,13 +178,11 @@ using SwitchboxNode = struct SwitchboxNode : SwitchboxNodeBase, Switchbox { int id; }; -// warning: 'xilinx::AIE::ChannelEdge::src' will be initialized after -// SwitchboxNode &src; [-Wreorder] using ChannelEdge = struct ChannelEdge : ChannelEdgeBase, Channel { using Channel::Channel; explicit ChannelEdge(SwitchboxNode &target) = delete; - ChannelEdge(SwitchboxNode &src, SwitchboxNode &target, WireBundle bundle, + ChannelEdge(SwitchboxNode &src, SwitchboxNode &target, StrmSwPortType bundle, int maxCapacity) : ChannelEdgeBase(target), Channel(src, target, bundle, maxCapacity), @@ -193,27 +291,27 @@ class Router { // https://lld.llvm.org/missingkeyfunction virtual ~Router() = default; virtual void initialize(int maxCol, int maxRow, - AMDAIENPUTargetModel targetModel) = 0; - virtual void addFlow(TileID srcCoords, Port srcPort, TileID dstCoords, + AMDAIENPUDeviceModel targetModel) = 0; + virtual void addFlow(TileLoc srcCoords, Port srcPort, TileLoc dstCoords, Port dstPort) = 0; - virtual bool addFixedConnection(ConnectOp connectOp) = 0; + virtual bool addFixedConnection(xilinx::AIE::ConnectOp connectOp) = 0; virtual std::optional> findPaths( int maxIterations) = 0; - virtual Switchbox *getSwitchbox(TileID coords) = 0; + virtual Switchbox *getSwitchbox(TileLoc coords) = 0; }; class Pathfinder : public Router { public: Pathfinder() = default; void initialize(int maxCol, int maxRow, - AMDAIENPUTargetModel targetModel) override; - void addFlow(TileID srcCoords, Port srcPort, TileID dstCoords, + AMDAIENPUDeviceModel targetModel) override; + void addFlow(TileLoc srcCoords, Port srcPort, TileLoc dstCoords, Port dstPort) override; - bool addFixedConnection(ConnectOp connectOp) override; + bool addFixedConnection(xilinx::AIE::ConnectOp connectOp) override; std::optional> findPaths( int maxIterations) override; - Switchbox *getSwitchbox(TileID coords) override { + Switchbox *getSwitchbox(TileLoc coords) override { auto *sb = std::find_if(graph.begin(), graph.end(), [&](SwitchboxNode *sb) { return sb->col == coords.col && sb->row == coords.row; }); @@ -224,7 +322,7 @@ class Pathfinder : public Router { private: SwitchboxGraph graph; std::vector flows; - std::map grid; + std::map grid; // Use a list instead of a vector because nodes have an edge list of raw // pointers to edges (so growing a vector would invalidate the pointers). std::list edges; @@ -241,30 +339,29 @@ class DynamicTileAnalysis { std::map flowSolutions; std::map processedFlows; - llvm::DenseMap coordToTile; - llvm::DenseMap coordToSwitchbox; - llvm::DenseMap coordToShimMux; - llvm::DenseMap coordToPLIO; + llvm::DenseMap coordToTile; + llvm::DenseMap coordToSwitchbox; + llvm::DenseMap coordToShimMux; + llvm::DenseMap coordToPLIO; const int maxIterations = 1000; // how long until declared unroutable DynamicTileAnalysis() : pathfinder(std::make_shared()) {} DynamicTileAnalysis(std::shared_ptr p) : pathfinder(std::move(p)) {} - mlir::LogicalResult runAnalysis(DeviceOp &device); + mlir::LogicalResult runAnalysis(xilinx::AIE::DeviceOp &device); int getMaxCol() const { return maxCol; } int getMaxRow() const { return maxRow; } - TileOp getTile(mlir::OpBuilder &builder, int col, int row); + xilinx::AIE::TileOp getTile(mlir::OpBuilder &builder, int col, int row); - SwitchboxOp getSwitchbox(mlir::OpBuilder &builder, int col, int row); + xilinx::AIE::SwitchboxOp getSwitchbox(mlir::OpBuilder &builder, int col, + int row); - ShimMuxOp getShimMux(mlir::OpBuilder &builder, int col); + xilinx::AIE::ShimMuxOp getShimMux(mlir::OpBuilder &builder, int col); }; -} // namespace xilinx::AIE - // For some mysterious reason, the only way to get the priorityQueue(cmp) // comparison in dijkstraShortestPaths to work correctly is to define // this template specialization for the pointers. Overloading operator @@ -275,9 +372,8 @@ class DynamicTileAnalysis { // (try moving this below the llvm namespace...) namespace std { template <> -struct less { - bool operator()(const xilinx::AIE::Switchbox *a, - const xilinx::AIE::Switchbox *b) const { +struct less { + bool operator()(const Switchbox *a, const Switchbox *b) const { return *a < *b; } }; @@ -286,20 +382,20 @@ struct less { namespace llvm { template <> -struct GraphTraits { - using NodeRef = xilinx::AIE::SwitchboxNode *; +struct GraphTraits { + using NodeRef = SwitchboxNode *; - static xilinx::AIE::SwitchboxNode *SwitchboxGraphGetSwitchbox( - DGEdge *P) { + static SwitchboxNode *SwitchboxGraphGetSwitchbox( + DGEdge *P) { return &P->getTargetNode(); } // Provide a mapped iterator so that the GraphTrait-based implementations can // find the target nodes without having to explicitly go through the edges. using ChildIteratorType = - mapped_iterator; - using ChildEdgeIteratorType = xilinx::AIE::SwitchboxNode::iterator; + using ChildEdgeIteratorType = SwitchboxNode::iterator; static NodeRef getEntryNode(NodeRef N) { return N; } static ChildIteratorType child_begin(NodeRef N) { @@ -316,22 +412,14 @@ struct GraphTraits { }; template <> -struct GraphTraits - : GraphTraits { - using nodes_iterator = xilinx::AIE::SwitchboxGraph::iterator; - static NodeRef getEntryNode(xilinx::AIE::SwitchboxGraph *DG) { - return *DG->begin(); - } - static nodes_iterator nodes_begin(xilinx::AIE::SwitchboxGraph *DG) { - return DG->begin(); - } - static nodes_iterator nodes_end(xilinx::AIE::SwitchboxGraph *DG) { - return DG->end(); - } +struct GraphTraits : GraphTraits { + using nodes_iterator = SwitchboxGraph::iterator; + static NodeRef getEntryNode(SwitchboxGraph *DG) { return *DG->begin(); } + static nodes_iterator nodes_begin(SwitchboxGraph *DG) { return DG->begin(); } + static nodes_iterator nodes_end(SwitchboxGraph *DG) { return DG->end(); } }; -inline raw_ostream &operator<<(raw_ostream &os, - const xilinx::AIE::SwitchSettings &ss) { +inline raw_ostream &operator<<(raw_ostream &os, const SwitchSettings &ss) { std::stringstream s; s << "\tSwitchSettings: "; for (const auto &[sb, setting] : ss) { @@ -342,20 +430,71 @@ inline raw_ostream &operator<<(raw_ostream &os, return os; } +template <> +struct DenseMapInfo { + using StorageInfo = ::llvm::DenseMapInfo; + + static inline StrmSwPortType getEmptyKey() { + return static_cast(StorageInfo::getEmptyKey()); + } + + static inline StrmSwPortType getTombstoneKey() { + return static_cast(StorageInfo::getTombstoneKey()); + } + + static unsigned getHashValue(const StrmSwPortType &val) { + return StorageInfo::getHashValue(static_cast(val)); + } + + static bool isEqual(const StrmSwPortType &lhs, const StrmSwPortType &rhs) { + return lhs == rhs; + } +}; + +template <> +struct DenseMapInfo { + using FirstInfo = DenseMapInfo; + using SecondInfo = DenseMapInfo; + + static Port getEmptyKey() { + return {FirstInfo::getEmptyKey(), SecondInfo::getEmptyKey()}; + } + + static Port getTombstoneKey() { + return {FirstInfo::getTombstoneKey(), SecondInfo::getTombstoneKey()}; + } + + static unsigned getHashValue(const Port &d) { + return detail::combineHashValue(FirstInfo::getHashValue(d.bundle), + SecondInfo::getHashValue(d.channel)); + } + + static bool isEqual(const Port &lhs, const Port &rhs) { return lhs == rhs; } +}; + } // namespace llvm template <> -struct std::hash { - std::size_t operator()(const xilinx::AIE::Switchbox &s) const noexcept { - return std::hash{}(s); +struct std::hash { + std::size_t operator()(const Port &p) const noexcept { + std::size_t h1 = std::hash{}(p.bundle); + std::size_t h2 = std::hash{}(p.channel); + return h1 ^ h2 << 1; + } +}; + +template <> +struct std::hash { + std::size_t operator()(const Switchbox &s) const noexcept { + return std::hash{}(s); } }; template <> -struct std::hash { - std::size_t operator()(const xilinx::AIE::PathEndPoint &pe) const noexcept { - std::size_t h1 = std::hash{}(pe.port); - std::size_t h2 = std::hash{}(pe.sb); +struct std::hash { + std::size_t operator()(const PathEndPoint &pe) const noexcept { + std::size_t h1 = std::hash{}(pe.port); + std::size_t h2 = std::hash{}(pe.sb); return h1 ^ (h2 << 1); } }; diff --git a/compiler/plugins/target/AMD-AIE/aie/AIETargetCDODirect.cpp b/compiler/plugins/target/AMD-AIE/aie/AIETargetCDODirect.cpp index cc332a7d8..37bcbbcf9 100644 --- a/compiler/plugins/target/AMD-AIE/aie/AIETargetCDODirect.cpp +++ b/compiler/plugins/target/AMD-AIE/aie/AIETargetCDODirect.cpp @@ -56,108 +56,32 @@ using namespace mlir; using namespace xilinx; using namespace xilinx::AIE; -#define AIERC_STR(x) x, #x -static const std::map AIERCTOSTR = { - {AIERC_STR(XAIE_OK)}, - {AIERC_STR(XAIE_ERR)}, - {AIERC_STR(XAIE_INVALID_DEVICE)}, - {AIERC_STR(XAIE_INVALID_RANGE)}, - {AIERC_STR(XAIE_INVALID_ARGS)}, - {AIERC_STR(XAIE_INVALID_TILE)}, - {AIERC_STR(XAIE_ERR_STREAM_PORT)}, - {AIERC_STR(XAIE_INVALID_DMA_TILE)}, - {AIERC_STR(XAIE_INVALID_BD_NUM)}, - {AIERC_STR(XAIE_ERR_OUTOFBOUND)}, - {AIERC_STR(XAIE_INVALID_DATA_MEM_ADDR)}, - {AIERC_STR(XAIE_INVALID_ELF)}, - {AIERC_STR(XAIE_CORE_STATUS_TIMEOUT)}, - {AIERC_STR(XAIE_INVALID_CHANNEL_NUM)}, - {AIERC_STR(XAIE_INVALID_LOCK)}, - {AIERC_STR(XAIE_INVALID_DMA_DIRECTION)}, - {AIERC_STR(XAIE_INVALID_PLIF_WIDTH)}, - {AIERC_STR(XAIE_INVALID_LOCK_ID)}, - {AIERC_STR(XAIE_INVALID_LOCK_VALUE)}, - {AIERC_STR(XAIE_LOCK_RESULT_FAILED)}, - {AIERC_STR(XAIE_INVALID_DMA_DESC)}, - {AIERC_STR(XAIE_INVALID_ADDRESS)}, - {AIERC_STR(XAIE_FEATURE_NOT_SUPPORTED)}, - {AIERC_STR(XAIE_INVALID_BURST_LENGTH)}, - {AIERC_STR(XAIE_INVALID_BACKEND)}, - {AIERC_STR(XAIE_INSUFFICIENT_BUFFER_SIZE)}, - {AIERC_STR(XAIE_ERR_MAX)}}; -#undef AIERC_STR - -static const std::map - WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE = { - {WireBundle::Core, StrmSwPortType::CORE}, - {WireBundle::DMA, StrmSwPortType::DMA}, - {WireBundle::Ctrl, StrmSwPortType::CTRL}, - {WireBundle::FIFO, StrmSwPortType::FIFO}, - {WireBundle::South, StrmSwPortType::SOUTH}, - {WireBundle::West, StrmSwPortType::WEST}, - {WireBundle::North, StrmSwPortType::NORTH}, - {WireBundle::East, StrmSwPortType::EAST}, - // missing PLIO from WireBundle - // missing NOC from WireBundle - {WireBundle::Trace, StrmSwPortType::TRACE}, +const std::map _WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE = { + {WireBundle::Core, StrmSwPortType::CORE}, + {WireBundle::DMA, StrmSwPortType::DMA}, + {WireBundle::Ctrl, StrmSwPortType::CTRL}, + {WireBundle::FIFO, StrmSwPortType::FIFO}, + {WireBundle::South, StrmSwPortType::SOUTH}, + {WireBundle::West, StrmSwPortType::WEST}, + {WireBundle::North, StrmSwPortType::NORTH}, + {WireBundle::East, StrmSwPortType::EAST}, + // missing PLIO from WireBundle + // missing NOC from WireBundle + {WireBundle::Trace, StrmSwPortType::TRACE}, }; -// https://stackoverflow.com/a/32230306 -template -raw_ostream &showArgs(raw_ostream &out, const char *label, H1 &&value) { - return out << label << "=" << std::forward

(value); +inline StrmSwPortType WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE( + xilinx::AIE::WireBundle w) { + return _WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE.at(w); } -template -raw_ostream &showArgs(raw_ostream &out, const char *label, H1 &&value, - T &&...rest) { - const char *pcomma = strchr(label, ','); - return showArgs(out.write(label, pcomma - label) - << "=" << std::forward

(value) << ',', - pcomma + 1, std::forward(rest)...); -} - -#define SHOW_ARGS(os, ...) showArgs(os, #__VA_ARGS__, __VA_ARGS__) - -raw_ostream &operator<<(raw_ostream &os, const XAie_LocType &loc) { - os << "XAie_LocType(col: " << std::to_string(loc.Col) - << ", row: " << std::to_string(loc.Row) << ")"; - return os; -} - -raw_ostream &operator<<(raw_ostream &os, const XAie_Lock &lock) { - os << "XAie_Lock(id: " << std::to_string(lock.LockId) - << ", val: " << std::to_string(lock.LockVal) << ")"; - return os; -} - -raw_ostream &operator<<(raw_ostream &os, const XAie_Packet &packet) { - os << "XAie_Packet(id: " << std::to_string(packet.PktId) - << ", type: " << std::to_string(packet.PktType) << ")"; - return os; -} - -// So that we can use the pattern if(auto r = TRY_XAIE_API...) { // r is nonzero -// } -static_assert(XAIE_OK == 0); - -#define TRY_XAIE_API_FATAL_ERROR(API, ...) \ - do { \ - LLVM_DEBUG(llvm::dbgs() << "trying XAIE API: " << #API << " with args: "); \ - LLVM_DEBUG(SHOW_ARGS(llvm::dbgs(), __VA_ARGS__)); \ - LLVM_DEBUG(llvm::dbgs() << "\n"); \ - if (auto r = API(__VA_ARGS__)) \ - llvm::report_fatal_error(llvm::Twine(#API " failed with ") + \ - AIERCTOSTR.at(r)); \ - } while (0) - -#define TRY_XAIE_API_EMIT_ERROR(OP, API, ...) \ - do { \ - LLVM_DEBUG(llvm::dbgs() << "trying XAIE API: " << #API << " with args: "); \ - LLVM_DEBUG(SHOW_ARGS(llvm::dbgs(), __VA_ARGS__)); \ - LLVM_DEBUG(llvm::dbgs() << "\n"); \ - if (auto r = API(__VA_ARGS__)) \ - return OP.emitOpError() << #API " failed with " << AIERCTOSTR.at(r); \ +#define TRY_XAIE_API_EMIT_ERROR(OP, API, ...) \ + do { \ + LLVM_DEBUG(llvm::dbgs() << "XAIE API: " << #API << " with args: "); \ + LLVM_DEBUG(SHOW_ARGS(llvm::dbgs(), __VA_ARGS__)); \ + LLVM_DEBUG(llvm::dbgs() << "\n"); \ + if (auto r = API(__VA_ARGS__)) \ + return OP.emitOpError() << #API " failed with " << AIERCTOSTR(r); \ } while (0) #define TRY_XAIE_API_LOGICAL_RESULT(API, ...) \ @@ -166,7 +90,7 @@ static_assert(XAIE_OK == 0); LLVM_DEBUG(SHOW_ARGS(llvm::dbgs(), __VA_ARGS__)); \ LLVM_DEBUG(llvm::dbgs() << "\n"); \ if (auto r = API(__VA_ARGS__)) { \ - llvm::errs() << #API " failed with " << AIERCTOSTR.at(r); \ + llvm::errs() << #API " failed with " << AIERCTOSTR(r); \ return failure(); \ } \ } while (0) @@ -182,15 +106,13 @@ auto ps = std::filesystem::path::preferred_separator; #define NPI_ADDR 0x0 #define NUM_LOCKS 16 -#define EVEN_BD_NUM_START 0 -#define ODD_BD_NUM_START 24 #define MEM_TILE_LOCK_ID_INCR 64 #define BASE_ADDR_A_INCR 0x80000 namespace xilinx::AIE { LogicalResult configureLocksInBdBlock(XAie_DmaDesc &dmaTileBd, Block &block, - AMDAIENPUTargetModel targetModel, + AMDAIENPUDeviceModel targetModel, XAie_LocType &tileLoc) { LLVM_DEBUG(llvm::dbgs() << "\nstart configuring bds\n"); std::optional acqValue, relValue, acqLockId, relLockId; @@ -236,7 +158,7 @@ LogicalResult configureLocksInBdBlock(XAie_DmaDesc &dmaTileBd, Block &block, } LogicalResult configureBdInBlock(XAie_DevInst &devInst, XAie_DmaDesc &dmaTileBd, - Block &block, AMDAIENPUTargetModel targetModel, + Block &block, AMDAIENPUDeviceModel targetModel, XAie_LocType &tileLoc, int bdId, std::optional nextBdId) { std::optional packetType; @@ -360,7 +282,7 @@ LogicalResult pushToBdQueueAndEnable(XAie_DevInst &devInst, Operation &op, LogicalResult configureLocksAndBd(XAie_DevInst &devInst, Block &block, XAie_LocType tileLoc, - AMDAIENPUTargetModel targetModel) { + AMDAIENPUDeviceModel targetModel) { DMABDOp bd = *block.getOps().begin(); assert(bd.getBdId().has_value() && "DMABDOp must have assigned bd_id; did you forget to run " @@ -382,7 +304,7 @@ struct AIEControl { XAie_DevInst devInst; AIEControl(size_t partitionStartCol, bool aieSim, bool xaieDebug, - AMDAIENPUTargetModel tm) { + const AMDAIENPUDeviceModel &tm) { size_t partitionNumCols = tm.columns(); size_t deviceRows = tm.rows(); size_t deviceCols = tm.columns() + partitionStartCol; @@ -489,7 +411,8 @@ struct AIEControl { << "lock op missing either id or init" << lockOp << "\n"); }); - AMDAIENPUTargetModel targetModel = targetOp.getTargetModel(); + AMDAIENPUDeviceModel &targetModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); auto memOps = llvm::to_vector_of(targetOp.getOps()); llvm::append_range(memOps, targetOp.getOps()); @@ -539,9 +462,9 @@ struct AIEControl { for (auto connectOp : b.getOps()) TRY_XAIE_API_EMIT_ERROR( switchboxOp, XAie_StrmConnCctEnable, &devInst, tileLoc, - WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE.at(connectOp.getSourceBundle()), + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connectOp.getSourceBundle()), connectOp.sourceIndex(), - WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE.at(connectOp.getDestBundle()), + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connectOp.getDestBundle()), connectOp.destIndex()); for (auto connectOp : b.getOps()) { @@ -566,7 +489,7 @@ struct AIEControl { isdma ? XAIE_SS_PKT_DROP_HEADER : XAIE_SS_PKT_DONOT_DROP_HEADER; TRY_XAIE_API_EMIT_ERROR( connectOp, XAie_StrmPktSwMstrPortEnable, &devInst, tileLoc, - WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE.at(connectOp.getDestBundle()), + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connectOp.getDestBundle()), connectOp.destIndex(), dropHeader, arbiter, mask); } @@ -579,13 +502,13 @@ struct AIEControl { int msel = amselOp.getMselValue(); TRY_XAIE_API_EMIT_ERROR( connectOp, XAie_StrmPktSwSlavePortEnable, &devInst, tileLoc, - WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE.at(connectOp.getSourceBundle()), + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connectOp.getSourceBundle()), connectOp.sourceIndex()); auto packetInit = XAie_PacketInit(slotOp.valueInt(), /*PktType*/ 0); // TODO Need to better define packet id,type used here TRY_XAIE_API_EMIT_ERROR( connectOp, XAie_StrmPktSwSlaveSlotEnable, &devInst, tileLoc, - WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE.at(connectOp.getSourceBundle()), + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connectOp.getSourceBundle()), connectOp.sourceIndex(), slot, packetInit, slotOp.maskInt(), msel, arbiter); slot++; @@ -617,9 +540,9 @@ struct AIEControl { for (auto connectOp : b.getOps()) TRY_XAIE_API_EMIT_ERROR( switchboxOp, XAie_StrmConnCctEnable, &devInst, tileLoc, - WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE.at(connectOp.getSourceBundle()), + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connectOp.getSourceBundle()), connectOp.sourceIndex(), - WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE.at(connectOp.getDestBundle()), + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE(connectOp.getDestBundle()), connectOp.destIndex()); } @@ -629,9 +552,9 @@ struct AIEControl { auto tileLoc = XAie_TileLoc(tile.getCol(), tile.getRow()); TRY_XAIE_API_EMIT_ERROR( targetOp, XAie_CoreConfigAccumulatorControl, &devInst, tileLoc, - WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE.at( + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE( static_cast(configOp.getInputDir())), - WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE.at( + WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE( static_cast(configOp.getOutputDir()))); } @@ -733,7 +656,7 @@ LogicalResult AIETranslateToCDODirect(ModuleOp m, llvm::StringRef workDirPath, "only exactly 1 device op supported."); DeviceOp targetOp = *devOps.begin(); AIEControl ctl(partitionStartCol, aieSim, xaieDebug, - targetOp.getTargetModel()); + mlir::iree_compiler::AMDAIE::getDeviceModel()); initializeCDOGenerator(endianness, cdoDebug); if (emitUnified) return generateCDOUnified(ctl, workDirPath, targetOp, aieSim, enableCores); diff --git a/compiler/plugins/target/AMD-AIE/aie/CMakeLists.txt b/compiler/plugins/target/AMD-AIE/aie/CMakeLists.txt index d9f121325..3a034c193 100644 --- a/compiler/plugins/target/AMD-AIE/aie/CMakeLists.txt +++ b/compiler/plugins/target/AMD-AIE/aie/CMakeLists.txt @@ -26,6 +26,7 @@ iree_cc_library( AIEDialectIR SRCS ${IREE_MLIR_AIE_SOURCE_DIR}/lib/Dialect/AIE/IR/AIEDialect.cpp + ${IREE_MLIR_AIE_SOURCE_DIR}/lib/Dialect/AIE/IR/AIETargetModel.cpp DEPS ::defs ::AIEAttrsGen @@ -342,7 +343,6 @@ iree_cc_library( "AIETargets.cpp" "AIETargetCDODirect.cpp" DEPS - ::AIEDialectIR ::AIEDialectIR ::AIEPass ::AIEVecDialectIR diff --git a/compiler/plugins/target/AMD-AIE/aie/Passes.h b/compiler/plugins/target/AMD-AIE/aie/Passes.h index 11f9b026a..fa1f291c9 100644 --- a/compiler/plugins/target/AMD-AIE/aie/Passes.h +++ b/compiler/plugins/target/AMD-AIE/aie/Passes.h @@ -94,15 +94,17 @@ struct AIEPathfinderPass bool reconnectConnectOps(const mlir::OpBuilder &builder, SwitchboxOp sw, ConnectOp problemConnect, bool isIncomingToSW, - WireBundle problemBundle, int problemChan, + StrmSwPortType problemBundle, int problemChan, int emptyChan); ConnectOp replaceConnectOpWithNewDest(mlir::OpBuilder builder, - ConnectOp connect, WireBundle newBundle, + ConnectOp connect, + StrmSwPortType newBundle, int newChannel); ConnectOp replaceConnectOpWithNewSource(mlir::OpBuilder builder, ConnectOp connect, - WireBundle newBundle, int newChannel); + StrmSwPortType newBundle, + int newChannel); SwitchboxOp getSwitchbox(DeviceOp &d, int col, int row); }; diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_dma.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_dma.mlir index e1d59ef9b..41eb29700 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_dma.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_dma.mlir @@ -1,22 +1,22 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @fifo_cons : memref // CHECK: memref.global "public" @fifo : memref // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) -// CHECK: %[[FIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_0"} : memref -// CHECK: %[[FIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_1"} : memref -// CHECK: %[[FIFO_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_2"} : memref -// CHECK: %[[FIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 0) {init = 3 : i32, sym_name = "fifo_cons_prod_lock"} -// CHECK: %[[FIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 1) {init = 0 : i32, sym_name = "fifo_cons_cons_lock"} +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[FIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "fifo_cons_buff_0"} : memref +// CHECK: %[[FIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "fifo_cons_buff_1"} : memref +// CHECK: %[[FIFO_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "fifo_cons_buff_2"} : memref +// CHECK: %[[FIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 3 : i32, sym_name = "fifo_cons_prod_lock"} +// CHECK: %[[FIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "fifo_cons_cons_lock"} // CHECK: %[[FIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_0"} : memref // CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref // CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "fifo_prod_lock"} // CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} -// CHECK: %[[BUF83:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf83"} : memref<4xi32> -// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_8_3]], DMA : 0) +// CHECK: %[[BUF33:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "buf33"} : memref<4xi32> +// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { // CHECK: %[[C55_I32:.*]] = arith.constant 55 : i32 // CHECK: %[[C66_I32:.*]] = arith.constant 66 : i32 @@ -36,24 +36,24 @@ // CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) // CHECK: aie.end // CHECK: } -// CHECK: %[[CORE_8_3:.*]] = aie.core(%[[TILE_8_3]]) { +// CHECK: %[[CORE_3_3:.*]] = aie.core(%[[TILE_3_3]]) { // CHECK: %[[C0:.*]] = arith.constant 0 : index // CHECK: %[[C1:.*]] = arith.constant 1 : index // CHECK: %[[C2:.*]] = arith.constant 2 : index // CHECK: %[[C3:.*]] = arith.constant 3 : index // CHECK: aie.use_lock(%[[FIFO_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) // CHECK: %[[VAL_0:.*]] = memref.load %[[FIFO_CONS_BUFF_0]][] : memref -// CHECK: memref.store %[[VAL_0]], %[[BUF83]]{{\[}}%[[C0]]] : memref<4xi32> +// CHECK: memref.store %[[VAL_0]], %[[BUF33]]{{\[}}%[[C0]]] : memref<4xi32> // CHECK: aie.use_lock(%[[FIFO_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.use_lock(%[[FIFO_CONS_CONS_LOCK]], AcquireGreaterEqual, 2) // CHECK: %[[VAL_1:.*]] = memref.load %[[FIFO_CONS_BUFF_1]][] : memref // CHECK: %[[VAL_2:.*]] = memref.load %[[FIFO_CONS_BUFF_2]][] : memref -// CHECK: memref.store %[[VAL_1]], %[[BUF83]]{{\[}}%[[C1]]] : memref<4xi32> -// CHECK: memref.store %[[VAL_2]], %[[BUF83]]{{\[}}%[[C2]]] : memref<4xi32> +// CHECK: memref.store %[[VAL_1]], %[[BUF33]]{{\[}}%[[C1]]] : memref<4xi32> +// CHECK: memref.store %[[VAL_2]], %[[BUF33]]{{\[}}%[[C2]]] : memref<4xi32> // CHECK: aie.use_lock(%[[FIFO_CONS_PROD_LOCK]], Release, 2) // CHECK: aie.use_lock(%[[FIFO_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) // CHECK: %[[VAL_3:.*]] = memref.load %[[FIFO_CONS_BUFF_0]][] : memref -// CHECK: memref.store %[[VAL_3]], %[[BUF83]]{{\[}}%[[C3]]] : memref<4xi32> +// CHECK: memref.store %[[VAL_3]], %[[BUF33]]{{\[}}%[[C3]]] : memref<4xi32> // CHECK: aie.use_lock(%[[FIFO_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.end // CHECK: } @@ -72,7 +72,7 @@ // CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[MEM_8_3:.*]] = aie.mem(%[[TILE_8_3]]) { +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { // CHECK: %[[VAL_5:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[FIFO_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) @@ -95,13 +95,13 @@ // CHECK: } module @aie2_cyclostatic_dma { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile22 = aie.tile(2, 2) // producer tile - %tile83 = aie.tile(8, 3) // consumer tile - %buf83 = aie.buffer(%tile83) {sym_name = "buf83"} : memref<4xi32> + %tile33 = aie.tile(3, 3) // consumer tile + %buf33 = aie.buffer(%tile33) {sym_name = "buf33"} : memref<4xi32> // ObjectFifo that can hold 4 memrefs, populated by tile22 and // consumed by tile23 - aie.objectfifo @fifo (%tile22, {%tile83}, 4 : i32) : !aie.objectfifo> + aie.objectfifo @fifo (%tile22, {%tile33}, 4 : i32) : !aie.objectfifo> // Producer core %core22 = aie.core(%tile22) { %c55 = arith.constant 55 : i32 @@ -131,7 +131,7 @@ module @aie2_cyclostatic_dma { aie.end } // Consumer core - %core28 = aie.core(%tile83) { + %core28 = aie.core(%tile33) { // Consumer pattern: {1, 2, 1} %i0 = arith.constant 0 : index %i1 = arith.constant 1 : index @@ -141,7 +141,7 @@ module @aie2_cyclostatic_dma { %subview0 = aie.objectfifo.acquire @fifo (Consume, 1) : !aie.objectfifosubview> %subview0_obj = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref %v55 = memref.load %subview0_obj[] : memref - memref.store %v55, %buf83[%i0] : memref<4xi32> + memref.store %v55, %buf33[%i0] : memref<4xi32> aie.objectfifo.release @fifo (Consume, 1) // Pop 2 objects off queue %subview1 = aie.objectfifo.acquire @fifo (Consume, 2) : !aie.objectfifosubview> @@ -149,14 +149,14 @@ module @aie2_cyclostatic_dma { %subview1_obj1 = aie.objectfifo.subview.access %subview1[1] : !aie.objectfifosubview> -> memref %v66 = memref.load %subview1_obj0[] : memref %v77 = memref.load %subview1_obj1[] : memref - memref.store %v66, %buf83[%i1] : memref<4xi32> - memref.store %v77, %buf83[%i2] : memref<4xi32> + memref.store %v66, %buf33[%i1] : memref<4xi32> + memref.store %v77, %buf33[%i2] : memref<4xi32> aie.objectfifo.release @fifo (Consume, 2) // Pop 1 object off queue %subview2 = aie.objectfifo.acquire @fifo (Consume, 1) : !aie.objectfifosubview> %subview2_obj = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref %v88 = memref.load %subview2_obj[] : memref - memref.store %v88, %buf83[%i3] : memref<4xi32> + memref.store %v88, %buf33[%i3] : memref<4xi32> aie.objectfifo.release @fifo (Consume, 1) aie.end } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l1.mlir index 36d4c46bb..3fab6dbab 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l1.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @fifo : memref // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) @@ -55,7 +55,7 @@ // CHECK: } module @aie2_cyclostatic_l1 { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile22 = aie.tile(2, 2) // producer tile %tile23 = aie.tile(2, 3) // consumer tile %buf23 = aie.buffer(%tile23) {sym_name = "buf23"} : memref<4xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l2.mlir index ecea483a6..5a661ee15 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l2.mlir @@ -1,20 +1,20 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @fifo1_cons : memref<1xi32> // CHECK: memref.global "public" @fifo1 : memref<1xi32> // CHECK: memref.global "public" @fifo0_cons : memref<1xi32> // CHECK: memref.global "public" @fifo0 : memref<1xi32> // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) -// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) -// CHECK: %[[FIFO1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_0"} : memref<1xi32> -// CHECK: %[[FIFO1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_1"} : memref<1xi32> -// CHECK: %[[FIFO1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_2"} : memref<1xi32> -// CHECK: %[[FIFO1_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_3"} : memref<1xi32> -// CHECK: %[[FIFO1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 0) {init = 4 : i32, sym_name = "fifo1_cons_prod_lock"} -// CHECK: %[[FIFO1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 1) {init = 0 : i32, sym_name = "fifo1_cons_cons_lock"} +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[FIFO1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "fifo1_cons_buff_0"} : memref<1xi32> +// CHECK: %[[FIFO1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "fifo1_cons_buff_1"} : memref<1xi32> +// CHECK: %[[FIFO1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "fifo1_cons_buff_2"} : memref<1xi32> +// CHECK: %[[FIFO1_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "fifo1_cons_buff_3"} : memref<1xi32> +// CHECK: %[[FIFO1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 4 : i32, sym_name = "fifo1_cons_prod_lock"} +// CHECK: %[[FIFO1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "fifo1_cons_cons_lock"} // CHECK: %[[FIFO0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_0"} : memref<1xi32> // CHECK: %[[FIFO0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_1"} : memref<1xi32> // CHECK: %[[FIFO0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_2"} : memref<1xi32> @@ -25,9 +25,9 @@ // CHECK: %[[FIFO0_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo0_buff_1"} : memref<1xi32> // CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "fifo0_prod_lock"} // CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "fifo0_cons_lock"} -// CHECK: %[[BUF83:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf83"} : memref<1xi32> +// CHECK: %[[BUF33:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "buf33"} : memref<1xi32> // CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_1]], DMA : 0) -// CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_8_3]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_3_3]], DMA : 0) // CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { // CHECK: %[[C0:.*]] = arith.constant 0 : index // CHECK: %[[C55_I32:.*]] = arith.constant 55 : i32 @@ -48,24 +48,24 @@ // CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], Release, 1) // CHECK: aie.end // CHECK: } -// CHECK: %[[CORE_8_3:.*]] = aie.core(%[[TILE_8_3]]) { +// CHECK: %[[CORE_3_3:.*]] = aie.core(%[[TILE_3_3]]) { // CHECK: %[[C0:.*]] = arith.constant 0 : index // CHECK: %[[C1:.*]] = arith.constant 1 : index // CHECK: %[[C2:.*]] = arith.constant 2 : index // CHECK: %[[C3:.*]] = arith.constant 3 : index // CHECK: aie.use_lock(%[[FIFO1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) // CHECK: %[[VAL_0:.*]] = memref.load %[[FIFO1_CONS_BUFF_0]]{{\[}}%[[C0]]] : memref<1xi32> -// CHECK: memref.store %[[VAL_0]], %[[BUF83]]{{\[}}%[[C0]]] : memref<1xi32> +// CHECK: memref.store %[[VAL_0]], %[[BUF33]]{{\[}}%[[C0]]] : memref<1xi32> // CHECK: aie.use_lock(%[[FIFO1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.use_lock(%[[FIFO1_CONS_CONS_LOCK]], AcquireGreaterEqual, 2) // CHECK: %[[VAL_1:.*]] = memref.load %[[FIFO1_CONS_BUFF_1]]{{\[}}%[[C0]]] : memref<1xi32> // CHECK: %[[VAL_2:.*]] = memref.load %[[FIFO1_CONS_BUFF_2]]{{\[}}%[[C0]]] : memref<1xi32> -// CHECK: memref.store %[[VAL_1]], %[[BUF83]]{{\[}}%[[C1]]] : memref<1xi32> -// CHECK: memref.store %[[VAL_2]], %[[BUF83]]{{\[}}%[[C2]]] : memref<1xi32> +// CHECK: memref.store %[[VAL_1]], %[[BUF33]]{{\[}}%[[C1]]] : memref<1xi32> +// CHECK: memref.store %[[VAL_2]], %[[BUF33]]{{\[}}%[[C2]]] : memref<1xi32> // CHECK: aie.use_lock(%[[FIFO1_CONS_PROD_LOCK]], Release, 2) // CHECK: aie.use_lock(%[[FIFO1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) // CHECK: %[[VAL_3:.*]] = memref.load %[[FIFO1_CONS_BUFF_3]]{{\[}}%[[C0]]] : memref<1xi32> -// CHECK: memref.store %[[VAL_3]], %[[BUF83]]{{\[}}%[[C3]]] : memref<1xi32> +// CHECK: memref.store %[[VAL_3]], %[[BUF33]]{{\[}}%[[C3]]] : memref<1xi32> // CHECK: aie.use_lock(%[[FIFO1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.end // CHECK: } @@ -131,7 +131,7 @@ // CHECK: ^bb10: // CHECK: aie.end // CHECK: } -// CHECK: %[[MEM_8_3:.*]] = aie.mem(%[[TILE_8_3]]) { +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { // CHECK: %[[VAL_7:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: // CHECK: aie.use_lock(%[[FIFO1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) @@ -159,15 +159,15 @@ // CHECK: } module @aie2_cyclostatic_l2 { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile22 = aie.tile(2, 2) // producer tile %memtile = aie.tile(2, 1) // mem tile - %tile83 = aie.tile(8, 3) // consumer tile - %buf83 = aie.buffer(%tile83) {sym_name = "buf83"} : memref<1xi32> + %tile33 = aie.tile(3, 3) // consumer tile + %buf33 = aie.buffer(%tile33) {sym_name = "buf33"} : memref<1xi32> // ObjectFifo that can hold 4 memref<1xi32>s, populated by tile22 and // consumed by tile23 aie.objectfifo @fifo0 (%tile22, {%memtile}, 4 : i32) : !aie.objectfifo> - aie.objectfifo @fifo1 (%memtile, {%tile83}, [4, 4]) : !aie.objectfifo> + aie.objectfifo @fifo1 (%memtile, {%tile33}, [4, 4]) : !aie.objectfifo> aie.objectfifo.link [@fifo0] -> [@fifo1] () // Producer core %core22 = aie.core(%tile22) { @@ -199,7 +199,7 @@ module @aie2_cyclostatic_l2 { aie.end } // Consumer core - %core28 = aie.core(%tile83) { + %core28 = aie.core(%tile33) { // Consumer pattern: {1, 2, 1} %i0 = arith.constant 0 : index %i1 = arith.constant 1 : index @@ -209,7 +209,7 @@ module @aie2_cyclostatic_l2 { %subview0 = aie.objectfifo.acquire @fifo1 (Consume, 1) : !aie.objectfifosubview> %subview0_obj = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref<1xi32> %v55 = memref.load %subview0_obj[%i0] : memref<1xi32> - memref.store %v55, %buf83[%i0] : memref<1xi32> + memref.store %v55, %buf33[%i0] : memref<1xi32> aie.objectfifo.release @fifo1 (Consume, 1) // Pop 2 objects off queue %subview1 = aie.objectfifo.acquire @fifo1 (Consume, 2) : !aie.objectfifosubview> @@ -217,14 +217,14 @@ module @aie2_cyclostatic_l2 { %subview1_obj1 = aie.objectfifo.subview.access %subview1[1] : !aie.objectfifosubview> -> memref<1xi32> %v66 = memref.load %subview1_obj0[%i0] : memref<1xi32> %v77 = memref.load %subview1_obj1[%i0] : memref<1xi32> - memref.store %v66, %buf83[%i1] : memref<1xi32> - memref.store %v77, %buf83[%i2] : memref<1xi32> + memref.store %v66, %buf33[%i1] : memref<1xi32> + memref.store %v77, %buf33[%i2] : memref<1xi32> aie.objectfifo.release @fifo1 (Consume, 2) // Pop 1 object off queue %subview2 = aie.objectfifo.acquire @fifo1 (Consume, 1) : !aie.objectfifosubview> %subview2_obj = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref<1xi32> %v88 = memref.load %subview2_obj[%i0] : memref<1xi32> - memref.store %v88, %buf83[%i3] : memref<1xi32> + memref.store %v88, %buf33[%i3] : memref<1xi32> aie.objectfifo.release @fifo1 (Consume, 1) aie.end } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_delayed_release.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_delayed_release.mlir index 44082c4dd..08d6dfef2 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_delayed_release.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_delayed_release.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @fifo : memref // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) @@ -53,7 +53,7 @@ // CHECK: } module @AIE2_delayed_release { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile22 = aie.tile(2, 2) %tile23 = aie.tile(2, 3) %buf23 = aie.buffer(%tile23) {sym_name = "buf23"} : memref<4xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_static_l1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_static_l1.mlir index d08ee86f7..c64f1ad0b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_static_l1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_static_l1.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @fifo : memref // CHECK: %[[C0:.*]] = arith.constant 0 : index // CHECK: %[[C1:.*]] = arith.constant 1 : index @@ -97,7 +97,7 @@ // CHECK: } module @aie2_static_l1 { - aie.device(xcve2302) { + aie.device(npu1_4col) { %i_c0 = arith.constant 0 : index %i_c1 = arith.constant 1 : index %i_c2 = arith.constant 2 : index diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/CMakeLists.txt b/compiler/plugins/target/AMD-AIE/aie/aie_passes/CMakeLists.txt index 9560a848f..2d98e2715 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/CMakeLists.txt +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/CMakeLists.txt @@ -13,3 +13,19 @@ iree_lit_test_suite( LABELS "hostonly" ) + +iree_cc_test( + NAME + DeviceModelTestCppTest + SRCS + "DeviceModelTest.cpp" + DEPS + gtest + iree::target::amd-aie::aie::AIEDialectIR + iree-amd-aie::runtime::iree_aie_runtime_static + MLIRViewLikeInterface + MLIRDataLayoutInterfaces + MLIRMemRefDialect + MLIRArithDialect + MLIRFuncDialect +) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/DeviceModelTest.cpp b/compiler/plugins/target/AMD-AIE/aie/aie_passes/DeviceModelTest.cpp new file mode 100644 index 000000000..a00a9a16e --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/DeviceModelTest.cpp @@ -0,0 +1,222 @@ +#include "aie/Dialect/AIE/IR/AIEDialect.h" +#include "aie/Dialect/AIE/IR/AIETargetModel.h" +#include "gtest/gtest-spi.h" +#include "gtest/gtest.h" +#include "iree-amd-aie/Transforms/AMDAIEUtils.h" +#include "iree-amd-aie/runtime/iree_aie_runtime.h" + +namespace { + +using namespace mlir::iree_compiler::AMDAIE; + +const std::map + _WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE = { + {xilinx::AIE::WireBundle::Core, StrmSwPortType::CORE}, + {xilinx::AIE::WireBundle::DMA, StrmSwPortType::DMA}, + {xilinx::AIE::WireBundle::Ctrl, StrmSwPortType::CTRL}, + {xilinx::AIE::WireBundle::FIFO, StrmSwPortType::FIFO}, + {xilinx::AIE::WireBundle::South, StrmSwPortType::SOUTH}, + {xilinx::AIE::WireBundle::West, StrmSwPortType::WEST}, + {xilinx::AIE::WireBundle::North, StrmSwPortType::NORTH}, + {xilinx::AIE::WireBundle::East, StrmSwPortType::EAST}, + // missing PLIO from WireBundle + // missing NOC from WireBundle + {xilinx::AIE::WireBundle::Trace, StrmSwPortType::TRACE}, +}; + +const std::map + _STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE = { + {StrmSwPortType::CORE, xilinx::AIE::WireBundle::Core}, + {StrmSwPortType::DMA, xilinx::AIE::WireBundle::DMA}, + {StrmSwPortType::CTRL, xilinx::AIE::WireBundle::Ctrl}, + {StrmSwPortType::FIFO, xilinx::AIE::WireBundle::FIFO}, + {StrmSwPortType::SOUTH, xilinx::AIE::WireBundle::South}, + {StrmSwPortType::WEST, xilinx::AIE::WireBundle::West}, + {StrmSwPortType::NORTH, xilinx::AIE::WireBundle::North}, + {StrmSwPortType::EAST, xilinx::AIE::WireBundle::East}, + {StrmSwPortType::TRACE, xilinx::AIE::WireBundle::Trace}, +}; + +inline StrmSwPortType WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE( + xilinx::AIE::WireBundle w) { + return _WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE.at(w); +} + +xilinx::AIE::WireBundle STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(StrmSwPortType s) { + return _STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE.at(s); +} + +TEST(EverythingExceptLegalMemConnection, Test0) { + AMDAIENPUDeviceModel &deviceModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); + const xilinx::AIE::AIETargetModel &targetModel = + xilinx::AIE::getTargetModel(xilinx::AIE::AIEDevice::npu1); + + EXPECT_EQ(deviceModel.rows(), targetModel.rows()); + EXPECT_EQ(deviceModel.columns(), targetModel.columns()); + + EXPECT_NONFATAL_FAILURE(EXPECT_EQ(deviceModel.isShimNOCTile(0, 0), + targetModel.isShimNOCTile(0, 0)), + "Expected equality of these values"); + + EXPECT_NONFATAL_FAILURE( + EXPECT_EQ(deviceModel.isShimPLTile(0, 0), targetModel.isShimPLTile(0, 0)), + "Expected equality of these values"); + + for (int c = 0; c < deviceModel.columns(); ++c) { + for (int r = 0; r < deviceModel.rows(); ++r) { + std::cout << "testing " + << " c, r " << c << ", " << r << "\n"; + + EXPECT_EQ(deviceModel.isCoreTile(c, r), targetModel.isCoreTile(c, r)) + << "Core tile disagree"; + EXPECT_EQ(deviceModel.isMemTile(c, r), targetModel.isMemTile(c, r)) + << "Mem tile disagree"; + if (c > 0 || r > 0) { + EXPECT_EQ(deviceModel.isShimNOCTile(c, r), + targetModel.isShimNOCTile(c, r)) + << "ShimNOC tile disagree"; + EXPECT_EQ(deviceModel.isShimPLTile(c, r), + targetModel.isShimPLTile(c, r)) + << "ShimPL tile disagree"; + } + + if (deviceModel.isCoreTile(c, r)) { + EXPECT_EQ(deviceModel.getLocalMemorySize(c, r), + targetModel.getLocalMemorySize()) + << "local size don't agree"; + } else if (deviceModel.isMemTile(c, r)) { + EXPECT_EQ(deviceModel.getMemTileSize(c, r), + targetModel.getMemTileSize()) + << "memtile memory size don't agree"; + } + + EXPECT_EQ(deviceModel.getNumLocks(c, r), targetModel.getNumLocks(c, r)) + << "Locks disagree"; + EXPECT_EQ(deviceModel.getNumBDs(c, r), targetModel.getNumBDs(c, r)) + << "BDs disagree"; + + TileLoc dloc = {c, r}; + xilinx::AIE::TileID tloc = {c, r}; + + auto d = deviceModel.getMemWest(dloc); + auto t = targetModel.getMemWest(tloc); + EXPECT_EQ(d.has_value(), t.has_value()) << "MemWest disagree on exist"; + if (d.has_value()) { + EXPECT_EQ(d->col, t->col) << "MemWest disagree on col"; + EXPECT_EQ(d->row, t->row) << "MemWest disagree on row"; + } + + d = deviceModel.getMemEast(dloc); + t = targetModel.getMemEast(tloc); + EXPECT_EQ(d.has_value(), t.has_value()) << "MemEast disagree on exist"; + if (d.has_value()) { + EXPECT_EQ(d->col, t->col) << "MemEast disagree on col"; + EXPECT_EQ(d->row, t->row) << "MemEast disagree on row"; + } + + d = deviceModel.getMemNorth(dloc); + t = targetModel.getMemNorth(tloc); + EXPECT_EQ(d.has_value(), t.has_value()) << "MemNorth disagree on exist"; + if (d.has_value()) { + EXPECT_EQ(d->col, t->col) << "MemNorth disagree on col"; + EXPECT_EQ(d->row, t->row) << "MemNorth disagree on row"; + } + + d = deviceModel.getMemSouth(dloc); + t = targetModel.getMemSouth(tloc); + EXPECT_EQ(d.has_value(), t.has_value()) << "MemSouth disagree on exist"; + if (d.has_value()) { + EXPECT_EQ(d->col, t->col) << "MemSouth disagree on col"; + EXPECT_EQ(d->row, t->row) << "MemSouth disagree on row"; + } + + for (int cc = 0; cc < deviceModel.columns(); ++cc) { + for (int rr = 0; rr < deviceModel.rows(); ++rr) { + EXPECT_EQ(deviceModel.hasMemWest(c, r, cc, rr), + targetModel.isMemWest(c, r, cc, rr)) + << "hasMemWest disagree"; + EXPECT_EQ(deviceModel.hasMemEast(c, r, cc, rr), + targetModel.isMemEast(c, r, cc, rr)) + << "hasMemEast disagree"; + EXPECT_EQ(deviceModel.hasMemNorth(c, r, cc, rr), + targetModel.isMemNorth(c, r, cc, rr)) + << "hasMemNorth disagree"; + EXPECT_EQ(deviceModel.hasMemSouth(c, r, cc, rr), + targetModel.isMemSouth(c, r, cc, rr)) + << "hasMemSouth disagree"; + EXPECT_EQ(deviceModel.hasLegalMemAffinity(c, r, cc, rr), + targetModel.isLegalMemAffinity(c, r, cc, rr)) + << "hasLegalMemAffinity disagree"; + } + } + } + } +} + +TEST(LegalMemConnection, Test0) { + AMDAIENPUDeviceModel &deviceModel = + mlir::iree_compiler::AMDAIE::getDeviceModel(); + const xilinx::AIE::AIETargetModel &targetModel = + xilinx::AIE::getTargetModel(xilinx::AIE::AIEDevice::npu1); + + EXPECT_EQ(deviceModel.rows(), targetModel.rows()); + EXPECT_EQ(deviceModel.columns(), targetModel.columns()); + + for (int c = 0; c < deviceModel.columns(); ++c) { + for (int r = 0; r < deviceModel.rows(); ++r) { + std::cout << "testing " + << " c, r " << c << ", " << r << "\n"; + for (int strmSwPortType = 0; strmSwPortType < SS_PORT_TYPE_MAX; + ++strmSwPortType) { + auto srcSw = static_cast(strmSwPortType); + auto wireB = STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(srcSw); + auto dNumSrc = + deviceModel.getNumSourceSwitchboxConnections(c, r, srcSw); + auto tNumSrc = + targetModel.getNumSourceSwitchboxConnections(c, r, wireB); + EXPECT_EQ(dNumSrc, tNumSrc) + << "diff src for typ: " << stringifyStrmSwPortType(srcSw) << "\n"; + + auto dNumDst = deviceModel.getNumDestSwitchboxConnections(c, r, srcSw); + auto tNumDst = targetModel.getNumDestSwitchboxConnections(c, r, wireB); + EXPECT_EQ(dNumDst, tNumDst) + << "diff dest for typ: " << stringifyStrmSwPortType(srcSw) << "\n"; + + if (deviceModel.isMemTile(c, r)) { + for (int destStrmSwPortType = 0; + destStrmSwPortType < SS_PORT_TYPE_MAX; ++destStrmSwPortType) { + auto destSw = static_cast(destStrmSwPortType); + auto destWireb = STRM_SW_PORT_TYPE_TO_WIRE_BUNDLE(destSw); + auto dNumDst = + deviceModel.getNumDestSwitchboxConnections(c, r, destSw); + for (int srcChan = 0; srcChan < dNumSrc; ++srcChan) { + for (int dstChan = 0; dstChan < dNumDst; ++dstChan) { + auto disLegal = deviceModel.isLegalMemtileConnection( + c, r, srcSw, srcChan, destSw, dstChan); + auto tisLegal = targetModel.isLegalMemtileConnection( + wireB, srcChan, destWireb, dstChan); + if (disLegal != tisLegal) { + std::cout << "isLegalMemtileConnection wrong (reports true " + "when false): " + << "src: " << stringifyStrmSwPortType(srcSw) + << (int)srcChan + << ", dst: " << stringifyStrmSwPortType(destSw) + << (int)dstChan << "\n"; + } + EXPECT_EQ(disLegal, tisLegal); + } + } + } + } + } + } + } +} + +} // namespace + +int main(int argc, char **argv) { + ::testing::InitGoogleTest(&argc, argv); + return RUN_ALL_TESTS(); +} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/allocation_info_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/allocation_info_test.mlir index c7efee118..09266ba67 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/allocation_info_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/allocation_info_test.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @of_out_1_cons : memref<64xi16> // CHECK: memref.global "public" @of_out_1 : memref<64xi16> // CHECK: memref.global "public" @of_in_1_cons : memref<64xi16> @@ -102,7 +102,7 @@ // CHECK: } module @alloc { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile20 = aie.tile(2, 0) %tile22 = aie.tile(2, 2) %tile23 = aie.tile(2, 3) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/assign-lockIDs.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/assign-lockIDs.mlir index 18da25850..8f294c90d 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/assign-lockIDs.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/assign-lockIDs.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-assign-lock-ids --split-input-file %s | FileCheck %s -// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) @@ -33,12 +33,10 @@ // CHECK: %[[LOCK_3_4_20:.*]] = aie.lock(%[[TILE_3_4]], 1) // CHECK: %[[LOCK_3_4_21:.*]] = aie.lock(%[[TILE_3_4]], 2) // CHECK: %[[LOCK_3_4_22:.*]] = aie.lock(%[[TILE_3_4]], 3) -// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) -// CHECK: %[[LOCK_6_0:.*]] = aie.lock(%[[TILE_6_0]], 0) // CHECK: } module @test_assign_lockIDs { - aie.device(xcvc1902) { + aie.device(npu1_4col) { %t22 = aie.tile(2, 2) %t23 = aie.tile(2, 3) %t33 = aie.tile(3, 3) @@ -70,14 +68,12 @@ module @test_assign_lockIDs { %l34_1 = aie.lock(%t34) %l34_2 = aie.lock(%t34) %l34_3 = aie.lock(%t34) - %t60 = aie.tile(6, 0) - %l60 = aie.lock(%t60) } } // ----- -// CHECK-LABEL: aie.device(xcve2802) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) // CHECK: %[[LOCK_1_1:.*]] = aie.lock(%[[TILE_1_1]], 1) // CHECK: %[[LOCK_1_1_0:.*]] = aie.lock(%[[TILE_1_1]], 0) @@ -102,7 +98,7 @@ module @test_assign_lockIDs { // CHECK: } module @memTileTest { - aie.device(xcve2802) { + aie.device(npu1_4col) { // Memory tiles on xcve have 64 locks. %tmemtile = aie.tile(1,1) %l0 = aie.lock(%tmemtile, 1) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/base_test_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/base_test_AIE2.mlir index 27c147164..7c240ea32 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/base_test_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/base_test_AIE2.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @of1_cons : memref<16xi32> // CHECK: memref.global "public" @of1 : memref<16xi32> // CHECK: memref.global "public" @of0 : memref<16xi32> @@ -56,7 +56,7 @@ // CHECK: } module @elementGenerationAIE2 { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile12 = aie.tile(1, 2) %tile13 = aie.tile(1, 3) %tile33 = aie.tile(3, 3) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic.mlir index ac8edc0d8..b543b11a4 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-assign-bd-ids %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[IN:.*]] = aie.buffer(%[[TILE_2_1]]) {address = 8192 : i32, sym_name = "in"} : memref<16xi32> // CHECK: %[[OUT:.*]] = aie.buffer(%[[TILE_2_1]]) {address = 1824 : i32, sym_name = "out"} : memref<16xi32> @@ -43,7 +43,7 @@ // CHECK: } module @aie_module { - aie.device(xcve2302) { + aie.device(npu1_4col) { %t01 = aie.tile(2, 1) %buf01_0 = aie.buffer(%t01) { address = 8192 : i32, sym_name = "in" } : memref<16xi32> %buf01_1 = aie.buffer(%t01) { address = 1824 : i32, sym_name = "out" } : memref<16xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_memtile_simple.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_memtile_simple.mlir index 6a94a8060..10bbf8b04 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_memtile_simple.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_memtile_simple.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-assign-buffer-addresses-basic %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) // CHECK: %[[A:.*]] = aie.buffer(%[[TILE_3_1]]) {address = 0 : i32, sym_name = "a"} : memref<65536xi32> // CHECK: %[[MEMTILE_DMA_3_1:.*]] = aie.memtile_dma(%[[TILE_3_1]]) { @@ -10,7 +10,7 @@ // CHECK: } module @test { - aie.device(xcve2302) { + aie.device(npu1_4col) { %0 = aie.tile(3, 1) %b1 = aie.buffer(%0) { sym_name = "a" } : memref<65536xi32> aie.memtile_dma(%0) { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_simple.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_simple.mlir index f700fae4b..84231ee0b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_simple.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_simple.mlir @@ -1,28 +1,28 @@ // RUN: iree-opt --aie-assign-buffer-addresses-basic %s | FileCheck %s -// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[A:.*]] = aie.buffer(%[[TILE_3_3]]) {address = 3104 : i32, sym_name = "a"} : memref<16xi8> // CHECK: %[[B:.*]] = aie.buffer(%[[TILE_3_3]]) {address = 1024 : i32, sym_name = "b"} : memref<512xi32> // CHECK: %[[C:.*]] = aie.buffer(%[[TILE_3_3]]) {address = 3072 : i32, sym_name = "c"} : memref<16xi16> -// CHECK: %[[TILE_4_4:.*]] = aie.tile(4, 4) -// CHECK: %[[VAL_0:.*]] = aie.buffer(%[[TILE_4_4]]) {address = 1024 : i32, sym_name = "_anonymous0"} : memref<500xi32> +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[VAL_0:.*]] = aie.buffer(%[[TILE_2_2]]) {address = 1024 : i32, sym_name = "_anonymous0"} : memref<500xi32> // CHECK: %[[CORE_3_3:.*]] = aie.core(%[[TILE_3_3]]) { // CHECK: aie.end // CHECK: } -// CHECK: %[[CORE_4_4:.*]] = aie.core(%[[TILE_4_4]]) { +// CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { // CHECK: aie.end // CHECK: } // CHECK: } module @test { - aie.device(xcvc1902) { + aie.device(npu1_4col) { %0 = aie.tile(3, 3) %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> %1 = aie.buffer(%0) { sym_name = "b" } : memref<512xi32> %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> - %3 = aie.tile(4, 4) + %3 = aie.tile(2, 2) %4 = aie.buffer(%3) : memref<500xi32> aie.core(%0) { aie.end diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/cyclostatic_AIE2_sharedMem.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/cyclostatic_AIE2_sharedMem.mlir index 11be73c1d..9a56d9522 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/cyclostatic_AIE2_sharedMem.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/cyclostatic_AIE2_sharedMem.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @fifo0 : memref<16xi32> // CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) @@ -81,7 +81,7 @@ // CHECK: } module @cyclostatic { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile12 = aie.tile(1, 2) %tile23 = aie.tile(2, 2) aie.objectfifo @fifo0 (%tile12, {%tile23}, 4 : i32) : !aie.objectfifo> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_AIE2.mlir index b161ac334..1267ac8e2 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_AIE2.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @mem_out_cons : memref<3000xi32> // CHECK: memref.global "public" @mem_out : memref<3000xi32> // CHECK: memref.global "public" @mem_in_0_cons : memref<3000xi32> @@ -170,7 +170,7 @@ // CHECK: } module @link_AIE2 { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile00 = aie.tile(0, 0) %tile01 = aie.tile(0, 1) %tile02 = aie.tile(0, 2) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_DDR_to_L1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_DDR_to_L1.mlir index 2c79e6644..77d7d09c6 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_DDR_to_L1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_DDR_to_L1.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @from_memTile_cons : memref<16xi32> // CHECK: memref.global "public" @from_memTile : memref<16xi32> // CHECK: memref.global "public" @to_memTile_cons : memref<16xi32> @@ -78,7 +78,7 @@ // CHECK: } module @link_DDR_L1 { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile20 = aie.tile(2, 0) %tile21 = aie.tile(2, 1) %tile22 = aie.tile(2, 2) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_L1_to_DDR.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_L1_to_DDR.mlir index 47c7127f7..29cc24e4e 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_L1_to_DDR.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_L1_to_DDR.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @from_memTile_cons : memref<48xi32> // CHECK: memref.global "public" @from_memTile : memref<48xi32> // CHECK: memref.global "public" @to_memTile_cons : memref<16xi32> @@ -78,7 +78,7 @@ // CHECK: } module @link_L1_DDR { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile20 = aie.tile(2, 0) %tile21 = aie.tile(2, 1) %tile22 = aie.tile(2, 2) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_broadcast.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_broadcast.mlir index 80b0fb5cd..971624350 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_broadcast.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_broadcast.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @skip_connection_cons : memref<16xi32> // CHECK: memref.global "public" @skip_connection : memref<16xi32> // CHECK: memref.global "public" @link2_0_cons : memref<16xi32> @@ -130,7 +130,7 @@ // CHECK: } module @link_broadcast { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile20 = aie.tile(2, 0) %tile21 = aie.tile(2, 1) %tile22 = aie.tile(2, 2) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_distribute.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_distribute.mlir index b051eca67..eaf14b918 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_distribute.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_distribute.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @link4_cons : memref<12xi32> // CHECK: memref.global "public" @link4 : memref<12xi32> // CHECK: memref.global "public" @link3_cons : memref<20xi32> @@ -148,7 +148,7 @@ // CHECK: } module @link_distribute { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile20 = aie.tile(2, 0) %tile21 = aie.tile(2, 1) %tile22 = aie.tile(2, 2) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_join.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_join.mlir index f417f8ab9..96de77ed1 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_join.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_join.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @link5_cons : memref<512xi8> // CHECK: memref.global "public" @link5 : memref<512xi8> // CHECK: memref.global "public" @link4_cons : memref<128xi8> @@ -183,7 +183,7 @@ // CHECK: } module @link_join { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile20 = aie.tile(2, 0) %tile21 = aie.tile(2, 1) %tile12 = aie.tile(1, 2) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/locks1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/locks1.mlir index 6c9f6376e..8aec73564 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/locks1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/locks1.mlir @@ -1,40 +1,41 @@ // RUN: iree-opt --aie-localize-locks %s | FileCheck %s -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) -// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) -// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_2_4:.*]] = aie.tile(2, 4) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) -// CHECK: %[[LOCK_1_1:.*]] = aie.lock(%[[TILE_1_1]], 0) +// CHECK: %[[LOCK_1_2:.*]] = aie.lock(%[[TILE_1_2]], 0) +// CHECK: %[[LOCK_2_3:.*]] = aie.lock(%[[TILE_2_3]], 8) // CHECK: %[[LOCK_3_3:.*]] = aie.lock(%[[TILE_3_3]], 8) -// CHECK: %[[LOCK_4_3:.*]] = aie.lock(%[[TILE_4_3]], 8) -// CHECK: %[[CORE_1_1:.*]] = aie.core(%[[TILE_1_1]]) { +// CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { // CHECK: %[[C48:.*]] = arith.constant 48 : index // CHECK: aie.use_lock(%[[C48]], Acquire, 0) // CHECK: aie.use_lock(%[[C48]], Release, 1) // CHECK: aie.end // CHECK: } -// CHECK: %[[CORE_3_4:.*]] = aie.core(%[[TILE_3_4]]) { +// CHECK: %[[CORE_2_4:.*]] = aie.core(%[[TILE_2_4]]) { // CHECK: %[[C8:.*]] = arith.constant 8 : index // CHECK: aie.use_lock(%[[C8]], Acquire, 0) // CHECK: aie.use_lock(%[[C8]], Release, 1) // CHECK: aie.end // CHECK: } -// CHECK: %[[CORE_3_2:.*]] = aie.core(%[[TILE_3_2]]) { +// CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { // CHECK: %[[C40:.*]] = arith.constant 40 : index +// CHECK: %[[C16:.*]] = arith.constant 16 : index // CHECK: aie.use_lock(%[[C40]], Acquire, 0) // CHECK: aie.use_lock(%[[C40]], Release, 1) // CHECK: aie.end // CHECK: } -// CHECK: %[[CORE_3_3:.*]] = aie.core(%[[TILE_3_3]]) { +// CHECK: %[[CORE_2_3:.*]] = aie.core(%[[TILE_2_3]]) { // CHECK: %[[C56:.*]] = arith.constant 56 : index // CHECK: aie.use_lock(%[[C56]], Acquire, 0) // CHECK: aie.use_lock(%[[C56]], Release, 1) // CHECK: aie.end // CHECK: } -// CHECK: %[[CORE_4_3:.*]] = aie.core(%[[TILE_4_3]]) { +// CHECK: %[[CORE_3_3:.*]] = aie.core(%[[TILE_3_3]]) { // CHECK: %[[C56:.*]] = arith.constant 56 : index // CHECK: %[[C24:.*]] = arith.constant 24 : index // CHECK: aie.use_lock(%[[C24]], Acquire, 0) @@ -46,40 +47,40 @@ // CHECK: } module @test_xaie0 { - aie.device(xcvc1902) { - %t11 = aie.tile(1, 1) - %t34 = aie.tile(3, 4) - %t32 = aie.tile(3, 2) + aie.device(npu1_4col) { + %t12 = aie.tile(1, 2) + %t24 = aie.tile(2, 4) + %t22 = aie.tile(2, 2) + %t23 = aie.tile(2, 3) %t33 = aie.tile(3, 3) - %t43 = aie.tile(4, 3) - %l11_8 = aie.lock(%t11, 0) + %l11_8 = aie.lock(%t12, 0) + %l23_8 = aie.lock(%t23, 8) %l33_8 = aie.lock(%t33, 8) - %l43_8 = aie.lock(%t43, 8) - aie.core(%t11) { + aie.core(%t12) { aie.use_lock(%l11_8, Acquire, 0) aie.use_lock(%l11_8, Release, 1) aie.end } - aie.core(%t34) { - aie.use_lock(%l33_8, Acquire, 0) - aie.use_lock(%l33_8, Release, 1) + aie.core(%t24) { + aie.use_lock(%l23_8, Acquire, 0) + aie.use_lock(%l23_8, Release, 1) aie.end } - aie.core(%t32) { - aie.use_lock(%l33_8, Acquire, 0) - aie.use_lock(%l33_8, Release, 1) + aie.core(%t22) { + aie.use_lock(%l23_8, Acquire, 0) + aie.use_lock(%l23_8, Release, 1) aie.end } - aie.core(%t33) { - aie.use_lock(%l33_8, Acquire, 0) - aie.use_lock(%l33_8, Release, 1) + aie.core(%t23) { + aie.use_lock(%l23_8, Acquire, 0) + aie.use_lock(%l23_8, Release, 1) aie.end } - aie.core(%t43) { + aie.core(%t33) { + aie.use_lock(%l23_8, Acquire, 0) + aie.use_lock(%l23_8, Release, 1) aie.use_lock(%l33_8, Acquire, 0) aie.use_lock(%l33_8, Release, 1) - aie.use_lock(%l43_8, Acquire, 0) - aie.use_lock(%l43_8, Release, 1) aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_buffer.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_buffer.mlir index ac75b7513..0947437de 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_buffer.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_buffer.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-standard-lowering %s | FileCheck %s // CHECK: memref.global "public" @a : memref<4xi32> -// CHECK-LABEL: func.func @core_4_3() { +// CHECK-LABEL: func.func @core_3_3() { // CHECK: %[[C0:.*]] = arith.constant 0 : index // CHECK: %[[VAL_0:.*]] = memref.get_global @a : memref<4xi32> // CHECK: memref.assume_alignment %[[VAL_0]], 32 : memref<4xi32> @@ -9,7 +9,7 @@ // CHECK: return // CHECK: } -// CHECK-LABEL: func.func @core_3_3() { +// CHECK-LABEL: func.func @core_2_3() { // CHECK: %[[C0:.*]] = arith.constant 0 : index // CHECK: %[[C377_I32:.*]] = arith.constant 377 : i32 // CHECK: %[[VAL_0:.*]] = memref.get_global @a : memref<4xi32> @@ -19,18 +19,18 @@ // CHECK: } module @codegen1 { - aie.device(xcvc1902) { - %t33 = aie.tile(3, 3) - %a = aie.buffer(%t33) { sym_name = "a" } : memref<4xi32> - %core33 = aie.core(%t33) { + aie.device(npu1_4col) { + %t23 = aie.tile(2, 3) + %a = aie.buffer(%t23) { sym_name = "a" } : memref<4xi32> + %core23 = aie.core(%t23) { %0 = arith.constant 0 : index %377 = arith.constant 377 : i32 memref.store %377, %a[%0] : memref<4xi32> aie.end } - %t34 = aie.tile(4, 3) + %t33 = aie.tile(3, 3) - %core34 = aie.core(%t34) { + %core33 = aie.core(%t33) { %0 = arith.constant 0 : index %1 = memref.load %a[%0] : memref<4xi32> aie.end diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/matmul_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/matmul_test.mlir index 35386a828..d8052865b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/matmul_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/matmul_test.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @outC_cons : memref<16x16xi16> // CHECK: memref.global "public" @outC : memref<16x16xi16> // CHECK: memref.global "public" @inB_cons : memref<8x16xi16> @@ -126,7 +126,7 @@ // CHECK: } module @matmul { - aie.device(xcve2302) { + aie.device(npu1_4col) { %t00 = aie.tile(0, 0) %t02 = aie.tile(0, 2) aie.objectfifo @inA (%t00, { %t02 }, 2 : i32) : !aie.objectfifo> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/memTile_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/memTile_test.mlir index c86482a82..9d1982652 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/memTile_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/memTile_test.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @of_cons : memref<16xi32> // CHECK: memref.global "public" @of : memref<16xi32> // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) @@ -48,7 +48,7 @@ // CHECK: } module @memTile { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile11 = aie.tile(2, 1) %tile12 = aie.tile(2, 2) aie.objectfifo @of (%tile11, {%tile12}, 2 : i32) : !aie.objectfifo> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_base_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_base_AIE2.mlir index cf2890344..6989eda56 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_base_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_base_AIE2.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @of1_cons : memref<256xi32> // CHECK: memref.global "public" @of1 : memref<256xi32> // CHECK: memref.global "public" @of0_cons : memref<256xi32> @@ -111,7 +111,7 @@ // CHECK: } module @ndDMAObjFifoAIE2 { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile12 = aie.tile(1, 2) %tile13 = aie.tile(1, 3) %tile33 = aie.tile(3, 3) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_AIE2.mlir index cf52624ab..24322cbf3 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_AIE2.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @of2_cons : memref<128xi32> // CHECK: memref.global "public" @of2 : memref<128xi32> // CHECK: memref.global "public" @of1_cons : memref<128xi32> @@ -102,7 +102,7 @@ // CHECK: } module @ndDMAObjFifoAIE2 { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile10 = aie.tile(1, 0) %tile11 = aie.tile(1, 1) %tile22 = aie.tile(2, 2) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_multiple_consumers_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_multiple_consumers_AIE2.mlir index 6d7050116..06f03c40b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_multiple_consumers_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_multiple_consumers_AIE2.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @of3_cons : memref<256xi32> // CHECK: memref.global "public" @of3 : memref<256xi32> // CHECK: memref.global "public" @of1_cons : memref<256xi32> @@ -184,7 +184,7 @@ // CHECK: } module @ndDMAObjFifoAIE2 { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile12 = aie.tile(1, 2) %tile13 = aie.tile(1, 3) %tile33 = aie.tile(3, 3) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_AIE2.mlir index 07aaba180..fb4ad7baf 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_AIE2.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @of_cons : memref<16xi32> // CHECK: memref.global "public" @of : memref<16xi32> // CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) @@ -81,7 +81,7 @@ // CHECK: } module @non_adjacency_AIE2 { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile12 = aie.tile(1, 2) %tile33 = aie.tile(3, 3) aie.objectfifo @of (%tile12, {%tile33}, 2 : i32) : !aie.objectfifo> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/same_core_producer_consumer_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/same_core_producer_consumer_test.mlir index 5ad514d11..ebefdf0f0 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/same_core_producer_consumer_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/same_core_producer_consumer_test.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @of : memref<16xi32> // CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) // CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> @@ -30,7 +30,7 @@ // CHECK: } module @same_core { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile12 = aie.tile(1, 2) aie.objectfifo @of (%tile12, {%tile12}, 3 : i32) : !aie.objectfifo> func.func @some_work(%line_in:memref<16xi32>) -> () { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_AIE2_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_AIE2_test.mlir index 3c8397557..ca8e5004b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_AIE2_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_AIE2_test.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @of_out_cons : memref<16xi32> // CHECK: memref.global "public" @of_out : memref<16xi32> // CHECK: memref.global "public" @of_in_cons : memref<16xi32> @@ -73,7 +73,7 @@ // CHECK: } module @shim_AIE2 { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile22 = aie.tile(2, 2) %tile20 = aie.tile(2, 0) aie.objectfifo @of_in (%tile20, {%tile22}, 2 : i32) : !aie.objectfifo> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_broadcast_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_broadcast_test.mlir index 57b4cd3ca..a5ac79bcc 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_broadcast_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_broadcast_test.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @of_in_0_cons : memref<16xi32> // CHECK: memref.global "public" @of_in_1_cons : memref<16xi32> // CHECK: memref.global "public" @of_in_2_cons : memref<16xi32> @@ -87,7 +87,7 @@ // CHECK: } module @shim_broadcast { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile20 = aie.tile(2, 0) %tile22 = aie.tile(2, 2) %tile23 = aie.tile(2, 3) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_broadcast.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_broadcast.mlir index afd7c6a54..cf50d8c42 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_broadcast.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_broadcast.mlir @@ -1,238 +1,134 @@ // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) // CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) -// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_1_4:.*]] = aie.tile(1, 4) // CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) -// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) -// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) -// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) // CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) -// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) -// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) -// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) -// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) -// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) -// CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) -// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) -// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) -// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[SWITCHBOX_0_0:.*]] = aie.switchbox(%[[TILE_0_0]]) { +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) -// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { // CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) -// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) -// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) -// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK: aie.connect +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) -// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { +// CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) -// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { +// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { +// CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect -// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) -// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { +// CHECK: aie.connect // CHECK: } // CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) -// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) -// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) -// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) // CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_0:.*]] : North, %[[SWITCHBOX_0_1]] : South) // CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) // CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) +// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_0]] : East, %[[SWITCHBOX_1_0:.*]] : West) // CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) // CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) // CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) -// CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3:.*]] : Core) +// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : North, %[[SWITCHBOX_1_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) +// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) // CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) -// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) -// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : North, %[[SWITCHBOX_1_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : East, %[[SWITCHBOX_2_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2]] : Core) // CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) // CHECK: aie.wire(%[[SWITCHBOX_1_3]] : East, %[[SWITCHBOX_2_3:.*]] : West) // CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3]] : Core) // CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) // CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1:.*]] : Core) // CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) // CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) // CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) // CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) -// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : North, %[[SWITCHBOX_4_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) -// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : East, %[[SWITCHBOX_5_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) -// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : North, %[[SWITCHBOX_5_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) -// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) -// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) -// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) -// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) -// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) -// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) -// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) -// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) // CHECK: } module { - aie.device(xcvc1902) { - %t03 = aie.tile(0, 3) + aie.device(npu1_4col) { + %t01 = aie.tile(0, 1) + %t11 = aie.tile(1, 1) %t02 = aie.tile(0, 2) - %t00 = aie.tile(0, 0) + %t03 = aie.tile(0, 3) + %t14 = aie.tile(1, 4) %t13 = aie.tile(1, 3) - %t11 = aie.tile(1, 1) - %t10 = aie.tile(1, 0) - %t20 = aie.tile(2, 0) - %t30 = aie.tile(3, 0) %t22 = aie.tile(2, 2) + %t23 = aie.tile(2, 3) + %t30 = aie.tile(3, 0) %t31 = aie.tile(3, 1) - %t60 = aie.tile(6, 0) - %t70 = aie.tile(7, 0) - %t71 = aie.tile(7, 1) - %t72 = aie.tile(7, 2) - %t73 = aie.tile(7, 3) - %t80 = aie.tile(8, 0) - %t82 = aie.tile(8, 2) - %t83 = aie.tile(8, 3) - aie.flow(%t20, DMA : 0, %t13, DMA : 0) - aie.flow(%t20, DMA : 0, %t31, DMA : 0) - aie.flow(%t20, DMA : 0, %t71, DMA : 0) - aie.flow(%t20, DMA : 0, %t82, DMA : 0) - aie.flow(%t60, DMA : 0, %t02, DMA : 1) - aie.flow(%t60, DMA : 0, %t83, DMA : 1) - aie.flow(%t60, DMA : 0, %t22, DMA : 1) - aie.flow(%t60, DMA : 0, %t31, DMA : 1) + aie.flow(%t01, DMA : 0, %t13, DMA : 0) + aie.flow(%t01, DMA : 0, %t31, DMA : 0) + aie.flow(%t01, DMA : 0, %t22, DMA : 0) + aie.flow(%t01, DMA : 0, %t03, DMA : 0) + aie.flow(%t11, DMA : 0, %t02, DMA : 1) + aie.flow(%t11, DMA : 0, %t23, DMA : 1) + aie.flow(%t11, DMA : 0, %t22, DMA : 1) + aie.flow(%t11, DMA : 0, %t31, DMA : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_fixed_connections.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_fixed_connections.mlir index aad54dea2..105664bc6 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_fixed_connections.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_fixed_connections.mlir @@ -1,11 +1,11 @@ // RUN: iree-opt --aie-create-pathfinder-flows --split-input-file %s | FileCheck %s -// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) // CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) -// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) -// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect @@ -14,24 +14,25 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { +// CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { +// CHECK: %[[SWITCHBOX_0_0:.*]] = aie.switchbox(%[[TILE_0_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[SWITCHBOX_2_0:.*]] : East, %[[SWITCHBOX_3_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_6_0:.*]] : East, %[[SWITCHBOX_7_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_0_0:.*]] : East, %[[SWITCHBOX_1_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : East, %[[SWITCHBOX_2_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) // CHECK: } module { - aie.device(xcvc1902) { + aie.device(npu1_4col) { %tile_2_0 = aie.tile(2, 0) %tile_3_0 = aie.tile(3, 0) - %tile_6_0 = aie.tile(6, 0) - %tile_7_0 = aie.tile(7, 0) + %tile_1_0 = aie.tile(1, 0) + %tile_0_0 = aie.tile(0, 0) %switchbox_2_0 = aie.switchbox(%tile_2_0) { aie.connect aie.connect @@ -40,215 +41,13 @@ module { aie.connect aie.connect } - %switchbox_6_0 = aie.switchbox(%tile_6_0) { + %switchbox_6_0 = aie.switchbox(%tile_1_0) { aie.connect aie.connect } - %switchbox_7_0 = aie.switchbox(%tile_7_0) { + %switchbox_7_0 = aie.switchbox(%tile_0_0) { aie.connect aie.connect } } } - -// ----- - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) -// CHECK: %[[TILE_1_4:.*]] = aie.tile(1, 4) -// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) -// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) -// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) -// CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) -// CHECK: %[[TILE_9_2:.*]] = aie.tile(9, 2) -// CHECK: %[[TILE_10_2:.*]] = aie.tile(10, 2) -// CHECK: %[[TILE_11_3:.*]] = aie.tile(11, 3) -// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_9_2:.*]] = aie.switchbox(%[[TILE_9_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_2:.*]] = aie.switchbox(%[[TILE_10_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_11_3:.*]] = aie.switchbox(%[[TILE_11_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) -// CHECK: aie.wire(%[[TILE_1_4]] : Core, %[[SWITCHBOX_1_4:.*]] : Core) -// CHECK: aie.wire(%[[TILE_1_4]] : DMA, %[[SWITCHBOX_1_4]] : DMA) -// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) -// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) -// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) -// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) -// CHECK: aie.wire(%[[TILE_7_4]] : Core, %[[SWITCHBOX_7_4:.*]] : Core) -// CHECK: aie.wire(%[[TILE_7_4]] : DMA, %[[SWITCHBOX_7_4]] : DMA) -// CHECK: aie.wire(%[[TILE_9_2]] : Core, %[[SWITCHBOX_9_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_9_2]] : DMA, %[[SWITCHBOX_9_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : East, %[[SWITCHBOX_10_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_2]] : Core, %[[SWITCHBOX_10_2]] : Core) -// CHECK: aie.wire(%[[TILE_10_2]] : DMA, %[[SWITCHBOX_10_2]] : DMA) -// CHECK: aie.wire(%[[TILE_11_3]] : Core, %[[SWITCHBOX_11_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_11_3]] : DMA, %[[SWITCHBOX_11_3]] : DMA) -// CHECK: } - -module { - aie.device(xcvc1902) { - %tile_0_3 = aie.tile(0, 3) - %tile_1_4 = aie.tile(1, 4) - %tile_3_3 = aie.tile(3, 3) - %tile_4_2 = aie.tile(4, 2) - %tile_5_3 = aie.tile(5, 3) - %tile_6_3 = aie.tile(6, 3) - %tile_7_4 = aie.tile(7, 4) - %tile_9_2 = aie.tile(9, 2) - %tile_10_2 = aie.tile(10, 2) - %tile_11_3 = aie.tile(11, 3) - %switchbox_0_3 = aie.switchbox(%tile_0_3) { - aie.connect - aie.connect - } - %switchbox_1_4 = aie.switchbox(%tile_1_4) { - aie.connect - } - %switchbox_3_3 = aie.switchbox(%tile_3_3) { - aie.connect - } - %switchbox_4_2 = aie.switchbox(%tile_4_2) { - aie.connect - } - %switchbox_5_3 = aie.switchbox(%tile_5_3) { - aie.connect - } - %switchbox_6_3 = aie.switchbox(%tile_6_3) { - aie.connect - aie.connect - } - %switchbox_7_4 = aie.switchbox(%tile_7_4) { - aie.connect - aie.connect - } - %switchbox_9_2 = aie.switchbox(%tile_9_2) { - aie.connect - } - %switchbox_10_2 = aie.switchbox(%tile_10_2) { - aie.connect - } - %switchbox_11_3 = aie.switchbox(%tile_11_3) { - aie.connect - aie.connect - } - } -} - -// ----- - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_2_5:.*]] = aie.tile(2, 5) -// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) -// CHECK: %[[TILE_6_6:.*]] = aie.tile(6, 6) -// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) -// CHECK: %[[TILE_12_5:.*]] = aie.tile(12, 5) -// CHECK: %[[TILE_13_3:.*]] = aie.tile(13, 3) -// CHECK: %[[SWITCHBOX_2_5:.*]] = aie.switchbox(%[[TILE_2_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_6:.*]] = aie.switchbox(%[[TILE_6_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_12_5:.*]] = aie.switchbox(%[[TILE_12_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_13_3:.*]] = aie.switchbox(%[[TILE_13_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[TILE_2_5]] : Core, %[[SWITCHBOX_2_5:.*]] : Core) -// CHECK: aie.wire(%[[TILE_2_5]] : DMA, %[[SWITCHBOX_2_5]] : DMA) -// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) -// CHECK: aie.wire(%[[TILE_6_6]] : Core, %[[SWITCHBOX_6_6:.*]] : Core) -// CHECK: aie.wire(%[[TILE_6_6]] : DMA, %[[SWITCHBOX_6_6]] : DMA) -// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) -// CHECK: aie.wire(%[[TILE_12_5]] : Core, %[[SWITCHBOX_12_5:.*]] : Core) -// CHECK: aie.wire(%[[TILE_12_5]] : DMA, %[[SWITCHBOX_12_5]] : DMA) -// CHECK: aie.wire(%[[TILE_13_3]] : Core, %[[SWITCHBOX_13_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_13_3]] : DMA, %[[SWITCHBOX_13_3]] : DMA) -// CHECK: } - -module { - aie.device(xcvc1902) { - %tile_2_5 = aie.tile(2, 5) - %tile_3_1 = aie.tile(3, 1) - %tile_6_6 = aie.tile(6, 6) - %tile_7_3 = aie.tile(7, 3) - %tile_12_5 = aie.tile(12, 5) - %tile_13_3 = aie.tile(13, 3) - %switchbox_2_5 = aie.switchbox(%tile_2_5) { - aie.connect - aie.connect - } - %switchbox_3_1 = aie.switchbox(%tile_3_1) { - aie.connect - aie.connect - } - %switchbox_6_6 = aie.switchbox(%tile_6_6) { - aie.connect - aie.connect - } - %switchbox_7_3 = aie.switchbox(%tile_7_3) { - aie.connect - aie.connect - } - %switchbox_12_5 = aie.switchbox(%tile_12_5) { - aie.connect - aie.connect - } - %switchbox_13_3 = aie.switchbox(%tile_13_3) { - aie.connect - aie.connect - } - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_1.mlir deleted file mode 100644 index f94d1995f..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_1.mlir +++ /dev/null @@ -1,437 +0,0 @@ - -// RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) -// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) -// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) -// CHECK: %[[TILE_4_4:.*]] = aie.tile(4, 4) -// CHECK: %[[TILE_5_4:.*]] = aie.tile(5, 4) -// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) -// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) -// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) -// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) -// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) -// CHECK: %[[TILE_8_4:.*]] = aie.tile(8, 4) -// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) -// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) -// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) -// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) -// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) -// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) -// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) -// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) -// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) -// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) -// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) -// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_5_4:.*]] = aie.switchbox(%[[TILE_5_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_4_4:.*]] = aie.switchbox(%[[TILE_4_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_4:.*]] = aie.tile(6, 4) -// CHECK: %[[SWITCHBOX_6_4:.*]] = aie.switchbox(%[[TILE_6_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) -// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) -// CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) -// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) -// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) -// CHECK: %[[SWITCHBOX_8_0:.*]] = aie.switchbox(%[[TILE_8_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_8_1:.*]] = aie.tile(8, 1) -// CHECK: %[[SWITCHBOX_8_1:.*]] = aie.switchbox(%[[TILE_8_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) -// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) -// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) -// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) -// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) -// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) -// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) -// CHECK: aie.wire(%[[TILE_3_4]] : Core, %[[SWITCHBOX_3_4:.*]] : Core) -// CHECK: aie.wire(%[[TILE_3_4]] : DMA, %[[SWITCHBOX_3_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : North, %[[SWITCHBOX_3_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) -// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : North, %[[SWITCHBOX_4_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) -// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) -// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : North, %[[SWITCHBOX_4_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_4]] : East, %[[SWITCHBOX_4_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_4]] : Core, %[[SWITCHBOX_4_4]] : Core) -// CHECK: aie.wire(%[[TILE_4_4]] : DMA, %[[SWITCHBOX_4_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : North, %[[SWITCHBOX_4_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : East, %[[SWITCHBOX_5_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) -// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : North, %[[SWITCHBOX_5_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) -// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) -// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_4]] : East, %[[SWITCHBOX_5_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_4]] : Core, %[[SWITCHBOX_5_4]] : Core) -// CHECK: aie.wire(%[[TILE_5_4]] : DMA, %[[SWITCHBOX_5_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : North, %[[SWITCHBOX_5_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) -// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) -// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) -// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) -// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_4]] : East, %[[SWITCHBOX_6_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_4]] : Core, %[[SWITCHBOX_6_4]] : Core) -// CHECK: aie.wire(%[[TILE_6_4]] : DMA, %[[SWITCHBOX_6_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : North, %[[SWITCHBOX_6_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) -// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) -// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) -// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) -// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_4]] : East, %[[SWITCHBOX_7_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_4]] : Core, %[[SWITCHBOX_7_4]] : Core) -// CHECK: aie.wire(%[[TILE_7_4]] : DMA, %[[SWITCHBOX_7_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : North, %[[SWITCHBOX_7_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : East, %[[SWITCHBOX_8_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : East, %[[SWITCHBOX_8_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_1]] : Core, %[[SWITCHBOX_8_1]] : Core) -// CHECK: aie.wire(%[[TILE_8_1]] : DMA, %[[SWITCHBOX_8_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_0]] : North, %[[SWITCHBOX_8_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) -// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : North, %[[SWITCHBOX_8_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) -// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : East, %[[SWITCHBOX_8_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_4]] : Core, %[[SWITCHBOX_8_4]] : Core) -// CHECK: aie.wire(%[[TILE_8_4]] : DMA, %[[SWITCHBOX_8_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : North, %[[SWITCHBOX_8_4]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t20 = aie.tile(2, 0) - %t30 = aie.tile(3, 0) - %t34 = aie.tile(3, 4) - %t43 = aie.tile(4, 3) - %t44 = aie.tile(4, 4) - %t54 = aie.tile(5, 4) - %t60 = aie.tile(6, 0) - %t63 = aie.tile(6, 3) - %t70 = aie.tile(7, 0) - %t72 = aie.tile(7, 2) - %t83 = aie.tile(8, 3) - %t84 = aie.tile(8, 4) - aie.flow(%t20, DMA : 0, %t63, DMA : 0) - aie.flow(%t20, DMA : 1, %t83, DMA : 0) - aie.flow(%t30, DMA : 0, %t72, DMA : 0) - aie.flow(%t30, DMA : 1, %t54, DMA : 0) - aie.flow(%t34, Core : 0, %t63, Core : 1) - aie.flow(%t34, DMA : 1, %t70, DMA : 0) - aie.flow(%t43, Core : 0, %t84, Core : 1) - aie.flow(%t43, DMA : 1, %t60, DMA : 1) - aie.flow(%t44, Core : 0, %t54, Core : 1) - aie.flow(%t44, DMA : 1, %t60, DMA : 0) - aie.flow(%t54, Core : 0, %t43, Core : 1) - aie.flow(%t54, DMA : 1, %t30, DMA : 1) - aie.flow(%t60, DMA : 0, %t44, DMA : 0) - aie.flow(%t60, DMA : 1, %t43, DMA : 0) - aie.flow(%t63, Core : 0, %t34, Core : 1) - aie.flow(%t63, DMA : 1, %t20, DMA : 1) - aie.flow(%t70, DMA : 0, %t34, DMA : 0) - aie.flow(%t70, DMA : 1, %t84, DMA : 0) - aie.flow(%t72, Core : 0, %t83, Core : 1) - aie.flow(%t72, DMA : 1, %t30, DMA : 0) - aie.flow(%t83, Core : 0, %t44, Core : 1) - aie.flow(%t83, DMA : 1, %t20, DMA : 0) - aie.flow(%t84, Core : 0, %t72, Core : 1) - aie.flow(%t84, DMA : 1, %t70, DMA : 1) - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_2.mlir index 9b42d358f..fa815ae42 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_2.mlir @@ -1,42 +1,35 @@ // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) // CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) // CHECK: %[[TILE_0_4:.*]] = aie.tile(0, 4) -// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_0_5:.*]] = aie.tile(0, 5) // CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) // CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) // CHECK: %[[TILE_1_4:.*]] = aie.tile(1, 4) +// CHECK: %[[TILE_1_5:.*]] = aie.tile(1, 5) // CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[TILE_2_4:.*]] = aie.tile(2, 4) +// CHECK: %[[TILE_2_5:.*]] = aie.tile(2, 5) // CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) -// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) // CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) // CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) -// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) -// CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK: aie.connect +// CHECK: %[[TILE_3_5:.*]] = aie.tile(3, 5) +// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { +// CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect @@ -44,73 +37,74 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { +// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { +// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_1_5:.*]] = aie.switchbox(%[[TILE_1_5]]) { +// CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { +// CHECK: aie.connect // CHECK: aie.connect +// CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_0_5:.*]] = aie.switchbox(%[[TILE_0_5]]) { // CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { // CHECK: aie.connect @@ -118,51 +112,50 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { +// CHECK: %[[SWITCHBOX_3_5:.*]] = aie.switchbox(%[[TILE_3_5]]) { // CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect // CHECK: } +// CHECK: %[[SWITCHBOX_2_5:.*]] = aie.switchbox(%[[TILE_2_5]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) // CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect // CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) // CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) // CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) // CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) // CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) // CHECK: aie.wire(%[[TILE_0_4]] : Core, %[[SWITCHBOX_0_4:.*]] : Core) // CHECK: aie.wire(%[[TILE_0_4]] : DMA, %[[SWITCHBOX_0_4]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_0_3]] : North, %[[SWITCHBOX_0_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) -// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_0:.*]] : North, %[[SWITCHBOX_1_1]] : South) +// CHECK: aie.wire(%[[TILE_0_5]] : Core, %[[SWITCHBOX_0_5:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_5]] : DMA, %[[SWITCHBOX_0_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_4]] : North, %[[SWITCHBOX_0_5]] : South) // CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) // CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) // CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) // CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) // CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) // CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) @@ -171,11 +164,13 @@ // CHECK: aie.wire(%[[TILE_1_4]] : Core, %[[SWITCHBOX_1_4]] : Core) // CHECK: aie.wire(%[[TILE_1_4]] : DMA, %[[SWITCHBOX_1_4]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_1_3]] : North, %[[SWITCHBOX_1_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : East, %[[SWITCHBOX_2_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_5]] : East, %[[SWITCHBOX_1_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_5]] : Core, %[[SWITCHBOX_1_5]] : Core) +// CHECK: aie.wire(%[[TILE_1_5]] : DMA, %[[SWITCHBOX_1_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_4]] : North, %[[SWITCHBOX_1_5]] : South) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) // CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) // CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) // CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) @@ -190,6 +185,10 @@ // CHECK: aie.wire(%[[TILE_2_4]] : Core, %[[SWITCHBOX_2_4]] : Core) // CHECK: aie.wire(%[[TILE_2_4]] : DMA, %[[SWITCHBOX_2_4]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_2_3]] : North, %[[SWITCHBOX_2_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_5]] : East, %[[SWITCHBOX_2_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_5]] : Core, %[[SWITCHBOX_2_5]] : Core) +// CHECK: aie.wire(%[[TILE_2_5]] : DMA, %[[SWITCHBOX_2_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_4]] : North, %[[SWITCHBOX_2_5]] : South) // CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) // CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) // CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) @@ -209,54 +208,53 @@ // CHECK: aie.wire(%[[TILE_3_4]] : Core, %[[SWITCHBOX_3_4]] : Core) // CHECK: aie.wire(%[[TILE_3_4]] : DMA, %[[SWITCHBOX_3_4]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_3_3]] : North, %[[SWITCHBOX_3_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_5]] : East, %[[SWITCHBOX_3_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_5]] : Core, %[[SWITCHBOX_3_5]] : Core) +// CHECK: aie.wire(%[[TILE_3_5]] : DMA, %[[SWITCHBOX_3_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_4]] : North, %[[SWITCHBOX_3_5]] : South) // CHECK: } module { - aie.device(xcvc1902) { - %t01 = aie.tile(0, 1) - %t02 = aie.tile(0, 2) - %t03 = aie.tile(0, 3) - %t04 = aie.tile(0, 4) - %t11 = aie.tile(1, 1) - %t12 = aie.tile(1, 2) - %t13 = aie.tile(1, 3) - %t14 = aie.tile(1, 4) - %t20 = aie.tile(2, 0) - %t21 = aie.tile(2, 1) - %t22 = aie.tile(2, 2) - %t23 = aie.tile(2, 3) - %t24 = aie.tile(2, 4) - %t30 = aie.tile(3, 0) - %t31 = aie.tile(3, 1) - %t32 = aie.tile(3, 2) - %t33 = aie.tile(3, 3) - %t34 = aie.tile(3, 4) + aie.device(npu1_4col) { + %tile_0_2 = aie.tile(0, 2) + %tile_0_3 = aie.tile(0, 3) + %tile_0_4 = aie.tile(0, 4) + %tile_0_5 = aie.tile(0, 5) + %tile_1_2 = aie.tile(1, 2) + %tile_1_3 = aie.tile(1, 3) + %tile_1_4 = aie.tile(1, 4) + %tile_1_5 = aie.tile(1, 5) + %tile_2_0 = aie.tile(2, 0) + %tile_2_2 = aie.tile(2, 2) + %tile_2_3 = aie.tile(2, 3) + %tile_2_4 = aie.tile(2, 4) + %tile_2_5 = aie.tile(2, 5) + %tile_3_0 = aie.tile(3, 0) + %tile_3_2 = aie.tile(3, 2) + %tile_3_3 = aie.tile(3, 3) + %tile_3_4 = aie.tile(3, 4) + %tile_3_5 = aie.tile(3, 5) //TASK 1 - aie.flow(%t20, DMA : 0, %t11, DMA : 0) - aie.flow(%t11, Core : 0, %t01, Core : 0) - aie.flow(%t01, Core : 0, %t12, Core : 0) - aie.flow(%t12, Core : 0, %t02, Core : 0) - aie.flow(%t02, DMA : 0, %t20, DMA : 0) + aie.flow(%tile_2_0, DMA : 0, %tile_1_2, DMA : 0) + aie.flow(%tile_1_2, Core : 0, %tile_0_2, Core : 0) + aie.flow(%tile_0_2, Core : 0, %tile_1_3, Core : 0) + aie.flow(%tile_1_3, Core : 0, %tile_0_3, Core : 0) + aie.flow(%tile_0_3, DMA : 0, %tile_2_0, DMA : 0) //TASK 2 - aie.flow(%t20, DMA : 1, %t14, DMA : 0) - aie.flow(%t14, Core : 0, %t04, Core : 0) - aie.flow(%t04, Core : 0, %t13, Core : 0) - aie.flow(%t13, DMA : 0, %t20, DMA : 1) + aie.flow(%tile_2_0, DMA : 1, %tile_1_5, DMA : 0) + aie.flow(%tile_1_5, Core : 0, %tile_0_5, Core : 0) + aie.flow(%tile_0_5, Core : 0, %tile_1_4, Core : 0) + aie.flow(%tile_1_4, DMA : 0, %tile_2_0, DMA : 1) //TASK 3 - aie.flow(%t30, DMA : 0, %t21, DMA : 0) - aie.flow(%t21, Core : 0, %t33, Core : 0) - aie.flow(%t33, Core : 0, %t22, Core : 0) - aie.flow(%t22, Core : 0, %t34, Core : 0) - aie.flow(%t34, Core : 0, %t24, Core : 0) - aie.flow(%t24, Core : 0, %t23, Core : 0) - aie.flow(%t23, DMA : 0, %t30, DMA : 0) + aie.flow(%tile_3_0, DMA : 0, %tile_2_2, DMA : 0) + aie.flow(%tile_2_2, Core : 0, %tile_3_4, Core : 0) + aie.flow(%tile_3_4, Core : 0, %tile_2_3, Core : 0) + aie.flow(%tile_2_3, Core : 0, %tile_3_5, Core : 0) + aie.flow(%tile_3_5, Core : 0, %tile_2_5, Core : 0) + aie.flow(%tile_2_5, Core : 0, %tile_2_4, Core : 0) + aie.flow(%tile_2_4, DMA : 0, %tile_3_0, DMA : 0) //TASK 4 - aie.flow(%t30, DMA : 1, %t31, DMA : 1) - aie.flow(%t31, Core : 1, %t23, Core : 1) - aie.flow(%t23, Core : 1, %t34, Core : 1) - aie.flow(%t34, Core : 1, %t24, Core : 1) - aie.flow(%t24, Core : 1, %t33, Core : 1) - aie.flow(%t33, Core : 1, %t32, Core : 1) - aie.flow(%t32, DMA : 1, %t30, DMA : 1) + aie.flow(%tile_3_0, DMA : 1, %tile_3_3, DMA : 1) + aie.flow(%tile_3_3, DMA : 1, %tile_3_0, DMA : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_3.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_3.mlir deleted file mode 100644 index 2e162549d..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_3.mlir +++ /dev/null @@ -1,478 +0,0 @@ - -// RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) -// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) -// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) -// CHECK: %[[TILE_0_4:.*]] = aie.tile(0, 4) -// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) -// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) -// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) -// CHECK: %[[TILE_1_4:.*]] = aie.tile(1, 4) -// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) -// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) -// CHECK: %[[TILE_2_4:.*]] = aie.tile(2, 4) -// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) -// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) -// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) -// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) -// CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) -// CHECK: %[[TILE_8_1:.*]] = aie.tile(8, 1) -// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) -// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) -// CHECK: %[[TILE_8_4:.*]] = aie.tile(8, 4) -// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) -// CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) -// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) -// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) -// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) -// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) -// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) -// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_4:.*]] = aie.tile(4, 4) -// CHECK: %[[SWITCHBOX_4_4:.*]] = aie.switchbox(%[[TILE_4_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_4:.*]] = aie.tile(5, 4) -// CHECK: %[[SWITCHBOX_5_4:.*]] = aie.switchbox(%[[TILE_5_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_4:.*]] = aie.tile(6, 4) -// CHECK: %[[SWITCHBOX_6_4:.*]] = aie.switchbox(%[[TILE_6_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) -// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) -// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) -// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) -// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) -// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) -// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) -// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) -// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) -// CHECK: aie.wire(%[[TILE_0_4]] : Core, %[[SWITCHBOX_0_4:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_4]] : DMA, %[[SWITCHBOX_0_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : North, %[[SWITCHBOX_0_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) -// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_0:.*]] : North, %[[SWITCHBOX_1_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) -// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) -// CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : North, %[[SWITCHBOX_1_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_4]] : East, %[[SWITCHBOX_1_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_4]] : Core, %[[SWITCHBOX_1_4]] : Core) -// CHECK: aie.wire(%[[TILE_1_4]] : DMA, %[[SWITCHBOX_1_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : North, %[[SWITCHBOX_1_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : East, %[[SWITCHBOX_2_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0]] : South) -// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) -// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2]] : Core) -// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : East, %[[SWITCHBOX_2_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3]] : Core) -// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_4]] : East, %[[SWITCHBOX_2_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_4]] : Core, %[[SWITCHBOX_2_4]] : Core) -// CHECK: aie.wire(%[[TILE_2_4]] : DMA, %[[SWITCHBOX_2_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : North, %[[SWITCHBOX_2_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) -// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) -// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) -// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : East, %[[SWITCHBOX_3_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3]] : Core) -// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_4]] : East, %[[SWITCHBOX_3_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_4]] : Core, %[[SWITCHBOX_3_4]] : Core) -// CHECK: aie.wire(%[[TILE_3_4]] : DMA, %[[SWITCHBOX_3_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : North, %[[SWITCHBOX_3_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) -// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) -// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) -// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : North, %[[SWITCHBOX_4_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_4]] : East, %[[SWITCHBOX_4_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_4]] : Core, %[[SWITCHBOX_4_4]] : Core) -// CHECK: aie.wire(%[[TILE_4_4]] : DMA, %[[SWITCHBOX_4_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : North, %[[SWITCHBOX_4_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) -// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) -// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) -// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_4]] : East, %[[SWITCHBOX_5_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_4]] : Core, %[[SWITCHBOX_5_4]] : Core) -// CHECK: aie.wire(%[[TILE_5_4]] : DMA, %[[SWITCHBOX_5_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : North, %[[SWITCHBOX_5_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) -// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) -// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) -// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_4]] : East, %[[SWITCHBOX_6_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_4]] : Core, %[[SWITCHBOX_6_4]] : Core) -// CHECK: aie.wire(%[[TILE_6_4]] : DMA, %[[SWITCHBOX_6_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : North, %[[SWITCHBOX_6_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) -// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) -// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) -// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_4]] : East, %[[SWITCHBOX_7_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_4]] : Core, %[[SWITCHBOX_7_4]] : Core) -// CHECK: aie.wire(%[[TILE_7_4]] : DMA, %[[SWITCHBOX_7_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : North, %[[SWITCHBOX_7_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) -// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) -// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : East, %[[SWITCHBOX_8_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_4]] : Core, %[[SWITCHBOX_8_4]] : Core) -// CHECK: aie.wire(%[[TILE_8_4]] : DMA, %[[SWITCHBOX_8_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : North, %[[SWITCHBOX_8_4]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t01 = aie.tile(0, 1) - %t02 = aie.tile(0, 2) - %t03 = aie.tile(0, 3) - %t04 = aie.tile(0, 4) - %t11 = aie.tile(1, 1) - %t12 = aie.tile(1, 2) - %t13 = aie.tile(1, 3) - %t14 = aie.tile(1, 4) - %t20 = aie.tile(2, 0) - %t21 = aie.tile(2, 1) - %t22 = aie.tile(2, 2) - %t23 = aie.tile(2, 3) - %t24 = aie.tile(2, 4) - %t30 = aie.tile(3, 0) - %t71 = aie.tile(7, 1) - %t72 = aie.tile(7, 2) - %t73 = aie.tile(7, 3) - %t74 = aie.tile(7, 4) - %t81 = aie.tile(8, 1) - %t82 = aie.tile(8, 2) - %t83 = aie.tile(8, 3) - %t84 = aie.tile(8, 4) - //TASK 1 - aie.flow(%t20, DMA : 0, %t03, DMA : 0) - aie.flow(%t03, Core : 0, %t71, Core : 0) - aie.flow(%t71, Core : 0, %t84, Core : 0) - aie.flow(%t84, Core : 0, %t11, Core : 0) - aie.flow(%t11, Core : 0, %t24, Core : 0) - aie.flow(%t24, DMA : 0, %t20, DMA : 0) - //TASK 2 - aie.flow(%t30, DMA : 0, %t14, DMA : 0) - aie.flow(%t14, Core : 0, %t01, Core : 0) - aie.flow(%t01, Core : 0, %t83, Core : 0) - aie.flow(%t83, Core : 0, %t21, Core : 0) - aie.flow(%t21, Core : 0, %t73, Core : 0) - aie.flow(%t73, Core : 0, %t82, Core : 0) - aie.flow(%t82, DMA : 0, %t30, DMA : 0) - //TASK 3 - aie.flow(%t20, DMA : 1, %t83, DMA : 1) - aie.flow(%t83, Core : 1, %t01, Core : 1) - aie.flow(%t01, Core : 1, %t72, Core : 1) - aie.flow(%t72, Core : 1, %t02, Core : 1) - aie.flow(%t02, Core : 1, %t24, Core : 1) - aie.flow(%t24, Core : 1, %t71, Core : 1) - aie.flow(%t71, Core : 1, %t84, Core : 1) - aie.flow(%t84, DMA : 1, %t20, DMA : 1) - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows.mlir index ec30373ad..b971b3db6 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) // CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) // CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) @@ -10,212 +10,106 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) // CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) -// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) -// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) -// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) -// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) // CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) -// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) -// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) -// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) -// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) -// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) // CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) -// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) -// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) -// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) -// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) -// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) -// CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) -// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) -// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { // CHECK: aie.connect // CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) -// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) -// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) -// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { +// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } // CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) // CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) // CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) // CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) -// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_0:.*]] : North, %[[SWITCHBOX_1_1]] : South) // CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) // CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) // CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) // CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) // CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) // CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_1_2]] : North, %[[SWITCHBOX_1_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : East, %[[SWITCHBOX_2_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0]] : South) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) // CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) // CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) // CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) @@ -241,85 +135,37 @@ // CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3]] : Core) // CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) -// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : North, %[[SWITCHBOX_4_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) -// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) -// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : North, %[[SWITCHBOX_4_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : East, %[[SWITCHBOX_5_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) -// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : North, %[[SWITCHBOX_5_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) -// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) -// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) -// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) -// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) -// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) -// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) -// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) -// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) -// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) +// CHECK: aie.wire(%[[TILE_3_4]] : Core, %[[SWITCHBOX_3_4:.*]] : Core) +// CHECK: aie.wire(%[[TILE_3_4]] : DMA, %[[SWITCHBOX_3_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : North, %[[SWITCHBOX_3_4]] : South) // CHECK: } module { - aie.device(xcvc1902) { - %t02 = aie.tile(0, 2) - %t03 = aie.tile(0, 3) - %t11 = aie.tile(1, 1) - %t13 = aie.tile(1, 3) - %t20 = aie.tile(2, 0) - %t22 = aie.tile(2, 2) - %t30 = aie.tile(3, 0) - %t31 = aie.tile(3, 1) - %t60 = aie.tile(6, 0) - %t70 = aie.tile(7, 0) - %t73 = aie.tile(7, 3) - aie.flow(%t03, DMA : 0, %t70, DMA : 0) - aie.flow(%t13, DMA : 0, %t70, DMA : 1) - aie.flow(%t02, DMA : 0, %t60, DMA : 0) - aie.flow(%t22, DMA : 0, %t60, DMA : 1) - aie.flow(%t03, Core : 0, %t13, Core : 0) - aie.flow(%t03, Core : 1, %t02, Core : 0) - aie.flow(%t13, Core : 1, %t22, Core : 0) - aie.flow(%t02, Core : 1, %t22, Core : 1) - aie.flow(%t73, DMA : 0, %t20, DMA : 0) - aie.flow(%t73, DMA : 1, %t30, DMA : 0) - aie.flow(%t31, DMA : 0, %t20, DMA : 1) - aie.flow(%t31, DMA : 1, %t30, DMA : 1) - aie.flow(%t73, Core : 0, %t31, Core : 0) - aie.flow(%t73, Core : 1, %t31, Core : 1) + aie.device(npu1_4col) { + %tile_0_2 = aie.tile(0, 2) + %tile_0_3 = aie.tile(0, 3) + %tile_1_1 = aie.tile(1, 1) + %tile_1_3 = aie.tile(1, 3) + %tile_2_0 = aie.tile(2, 0) + %tile_2_2 = aie.tile(2, 2) + %tile_3_0 = aie.tile(3, 0) + %tile_3_1 = aie.tile(3, 1) + %tile_3_2 = aie.tile(3, 2) + %tile_3_3 = aie.tile(3, 3) + %tile_3_4 = aie.tile(3, 4) + aie.flow(%tile_0_3, DMA : 0, %tile_3_3, DMA : 0) + aie.flow(%tile_1_3, DMA : 0, %tile_3_3, DMA : 1) + aie.flow(%tile_0_2, DMA : 0, %tile_3_2, DMA : 0) + aie.flow(%tile_2_2, DMA : 0, %tile_3_2, DMA : 1) + aie.flow(%tile_0_3, Core : 0, %tile_1_3, Core : 0) + aie.flow(%tile_0_3, Core : 0, %tile_0_2, Core : 0) + aie.flow(%tile_1_3, Core : 0, %tile_2_2, Core : 0) + aie.flow(%tile_0_2, Core : 0, %tile_3_2, Core : 0) + aie.flow(%tile_3_4, DMA : 0, %tile_2_0, DMA : 0) + aie.flow(%tile_3_4, DMA : 1, %tile_3_0, DMA : 0) + aie.flow(%tile_3_1, DMA : 0, %tile_2_0, DMA : 1) + aie.flow(%tile_3_1, DMA : 1, %tile_3_0, DMA : 1) + aie.flow(%tile_3_4, Core : 0, %tile_3_1, DMA : 0) + aie.flow(%tile_3_4, Core : 0, %tile_3_1, DMA : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows2.mlir index ab6ac0aa0..14b08294e 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows2.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) // CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) // CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) @@ -10,52 +10,46 @@ // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) // CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) -// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) -// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) -// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) -// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) // CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) -// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { +// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { // CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect -// CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: } +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect -// CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } @@ -63,143 +57,58 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) -// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) -// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) -// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) -// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) -// CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) -// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) -// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) -// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) -// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) -// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) -// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { +// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { // CHECK: aie.connect -// CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) -// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) -// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) -// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) -// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) // CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) // CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) // CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) // CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) -// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_0:.*]] : North, %[[SWITCHBOX_1_1]] : South) // CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) // CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) // CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) // CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) // CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) // CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_1_2]] : North, %[[SWITCHBOX_1_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : East, %[[SWITCHBOX_2_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0]] : South) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) // CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) // CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) // CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) @@ -217,87 +126,44 @@ // CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) // CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) // CHECK: aie.wire(%[[SWITCHBOX_2_3]] : East, %[[SWITCHBOX_3_3:.*]] : West) // CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3]] : Core) // CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) -// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : North, %[[SWITCHBOX_4_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) -// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : East, %[[SWITCHBOX_5_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) -// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : North, %[[SWITCHBOX_5_1]] : South) -// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) -// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) -// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) -// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) -// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) -// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) -// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) -// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) -// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) -// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) +// CHECK: aie.wire(%[[TILE_3_4]] : Core, %[[SWITCHBOX_3_4:.*]] : Core) +// CHECK: aie.wire(%[[TILE_3_4]] : DMA, %[[SWITCHBOX_3_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : North, %[[SWITCHBOX_3_4]] : South) // CHECK: } module { - aie.device(xcvc1902) { - %t02 = aie.tile(0, 2) - %t03 = aie.tile(0, 3) - %t11 = aie.tile(1, 1) - %t13 = aie.tile(1, 3) - %t20 = aie.tile(2, 0) - %t22 = aie.tile(2, 2) - %t30 = aie.tile(3, 0) - %t31 = aie.tile(3, 1) - %t60 = aie.tile(6, 0) - %t70 = aie.tile(7, 0) - %t73 = aie.tile(7, 3) - aie.flow(%t03, DMA : 0, %t30, DMA : 0) - aie.flow(%t03, DMA : 1, %t70, DMA : 1) - aie.flow(%t02, DMA : 0, %t60, DMA : 0) - aie.flow(%t22, DMA : 0, %t20, DMA : 0) - aie.flow(%t22, Core : 0, %t13, Core : 0) - aie.flow(%t03, Core : 1, %t02, Core : 0) - aie.flow(%t73, Core : 0, %t31, Core : 0) - aie.flow(%t73, Core : 1, %t22, Core : 1) - aie.flow(%t73, DMA : 0, %t60, DMA : 1) - aie.flow(%t73, DMA : 1, %t70, DMA : 0) - aie.flow(%t31, DMA : 0, %t20, DMA : 1) - aie.flow(%t31, DMA : 1, %t30, DMA : 1) - aie.flow(%t03, Core : 0, %t02, Core : 1) - aie.flow(%t13, Core : 1, %t31, Core : 1) + aie.device(npu1_4col) { + %tile_0_2 = aie.tile(0, 2) + %tile_0_3 = aie.tile(0, 3) + %tile_1_1 = aie.tile(1, 1) + %tile_1_3 = aie.tile(1, 3) + %tile_2_0 = aie.tile(2, 0) + %tile_2_2 = aie.tile(2, 2) + %tile_3_0 = aie.tile(3, 0) + %tile_3_1 = aie.tile(3, 1) + %tile_3_2 = aie.tile(3, 2) + %tile_3_3 = aie.tile(3, 3) + %tile_3_4 = aie.tile(3, 4) + aie.flow(%tile_0_3, DMA : 0, %tile_3_0, DMA : 0) + aie.flow(%tile_0_3, DMA : 1, %tile_3_3, DMA : 1) + aie.flow(%tile_0_2, DMA : 0, %tile_3_2, DMA : 0) + aie.flow(%tile_2_2, DMA : 0, %tile_2_0, DMA : 0) + aie.flow(%tile_2_2, Core : 0, %tile_1_3, Core : 0) + aie.flow(%tile_0_3, DMA : 1, %tile_0_2, Core : 0) + aie.flow(%tile_3_4, Core : 0, %tile_3_1, DMA : 0) + aie.flow(%tile_3_4, DMA : 0, %tile_3_2, DMA : 1) + aie.flow(%tile_3_4, DMA : 1, %tile_3_3, DMA : 0) + aie.flow(%tile_3_1, DMA : 0, %tile_2_0, DMA : 1) + aie.flow(%tile_3_1, DMA : 1, %tile_3_0, DMA : 1) + aie.flow(%tile_0_3, Core : 0, %tile_0_2, DMA : 1) + aie.flow(%tile_1_3, DMA : 1, %tile_3_1, DMA : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile.mlir index 3af08e130..e3ae2846d 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile.mlir @@ -1,18 +1,24 @@ // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2802) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_0_4:.*]] = aie.tile(0, 4) // CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) -// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) // CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) -// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[SWITCHBOX_0_0:.*]] = aie.switchbox(%[[TILE_0_0]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { +// CHECK: %[[SHIM_MUX_0_0:.*]] = aie.shim_mux(%[[TILE_0_0]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -26,6 +32,17 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } // CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { // CHECK: aie.connect // CHECK: aie.connect @@ -42,8 +59,11 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } +// CHECK: aie.wire(%[[SHIM_MUX_0_0:.*]] : North, %[[SWITCHBOX_0_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_0_0]] : DMA, %[[SHIM_MUX_0_0]] : DMA) // CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) // CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_0]] : North, %[[SWITCHBOX_0_1]] : South) // CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) // CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) // CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) @@ -56,22 +76,22 @@ // CHECK: } module { - aie.device(xcve2802) { + aie.device(npu1_4col) { %t04 = aie.tile(0, 4) %t03 = aie.tile(0, 3) - %t02 = aie.tile(0, 2) %t01 = aie.tile(0, 1) - aie.flow(%t01, DMA : 0, %t02, DMA : 0) - aie.flow(%t01, DMA : 1, %t02, DMA : 1) - aie.flow(%t02, DMA : 0, %t01, DMA : 0) - aie.flow(%t02, DMA : 1, %t01, DMA : 1) - aie.flow(%t02, DMA : 2, %t03, DMA : 0) - aie.flow(%t02, DMA : 3, %t03, DMA : 1) - aie.flow(%t03, DMA : 0, %t02, DMA : 2) - aie.flow(%t03, DMA : 1, %t02, DMA : 3) - aie.flow(%t02, DMA : 4, %t04, DMA : 0) - aie.flow(%t02, DMA : 5, %t04, DMA : 1) - aie.flow(%t04, DMA : 0, %t02, DMA : 4) - aie.flow(%t04, DMA : 1, %t02, DMA : 5) + %t00 = aie.tile(0, 0) + aie.flow(%t00, DMA : 0, %t01, DMA : 0) + aie.flow(%t00, DMA : 1, %t01, DMA : 1) + aie.flow(%t01, DMA : 0, %t00, DMA : 0) + aie.flow(%t01, DMA : 1, %t00, DMA : 1) + aie.flow(%t01, DMA : 2, %t03, DMA : 0) + aie.flow(%t01, DMA : 3, %t03, DMA : 1) + aie.flow(%t03, DMA : 0, %t01, DMA : 2) + aie.flow(%t03, DMA : 1, %t01, DMA : 3) + aie.flow(%t01, DMA : 4, %t04, DMA : 0) + aie.flow(%t01, DMA : 5, %t04, DMA : 1) + aie.flow(%t04, DMA : 0, %t01, DMA : 4) + aie.flow(%t04, DMA : 1, %t01, DMA : 5) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile_routing_constraints.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile_routing_constraints.mlir index 76d4286a5..404c9d9fd 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile_routing_constraints.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile_routing_constraints.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2802) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) @@ -12,7 +12,7 @@ // CHECK: } // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect @@ -21,7 +21,7 @@ // CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) // CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) @@ -37,7 +37,7 @@ // CHECK: } module { - aie.device(xcve2802) { + aie.device(npu1_4col) { %tile_2_0 = aie.tile(2, 0) %tile_2_1 = aie.tile(2, 1) %tile_2_2 = aie.tile(2, 2) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_mmult.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_mmult.mlir deleted file mode 100644 index e226f36fb..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_mmult.mlir +++ /dev/null @@ -1,644 +0,0 @@ - -// RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) -// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) -// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) -// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) -// CHECK: %[[LOCK_8_3:.*]] = aie.lock(%[[TILE_8_3]], 1) -// CHECK: %[[LOCK_8_3_0:.*]] = aie.lock(%[[TILE_8_3]], 3) -// CHECK: %[[BUF11:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf11"} : memref<16x16xf32, 2> -// CHECK: %[[LOCK_8_3_1:.*]] = aie.lock(%[[TILE_8_3]], 2) -// CHECK: %[[BUF10:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf10"} : memref<16x16xf32, 2> -// CHECK: %[[LOCK_8_3_2:.*]] = aie.lock(%[[TILE_8_3]], 0) -// CHECK: %[[BUF9:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf9"} : memref<16x16xf32, 2> -// CHECK: %[[MEM_8_3:.*]] = aie.mem(%[[TILE_8_3]]) { -// CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_8_3_2]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF9]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_8_3_2]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_8_3]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF11]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_8_3]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: -// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) -// CHECK: ^bb4: -// CHECK: aie.use_lock(%[[LOCK_8_3_1]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF10]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_8_3_1]], Release, 1) -// CHECK: aie.next_bd ^bb4 -// CHECK: ^bb5: -// CHECK: %[[VAL_2:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) -// CHECK: ^bb6: -// CHECK: aie.use_lock(%[[LOCK_8_3_0]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF11]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_8_3_0]], Release, 0) -// CHECK: aie.next_bd ^bb6 -// CHECK: ^bb7: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) -// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) -// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) -// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) -// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) -// CHECK: %[[LOCK_7_3:.*]] = aie.lock(%[[TILE_7_3]], 1) -// CHECK: %[[LOCK_7_3_3:.*]] = aie.lock(%[[TILE_7_3]], 3) -// CHECK: %[[BUF8:.*]] = aie.buffer(%[[TILE_7_3]]) {sym_name = "buf8"} : memref<16x16xf32, 2> -// CHECK: %[[LOCK_7_3_4:.*]] = aie.lock(%[[TILE_7_3]], 2) -// CHECK: %[[BUF7:.*]] = aie.buffer(%[[TILE_7_3]]) {sym_name = "buf7"} : memref<16x16xf32, 2> -// CHECK: %[[LOCK_7_3_5:.*]] = aie.lock(%[[TILE_7_3]], 0) -// CHECK: %[[BUF6:.*]] = aie.buffer(%[[TILE_7_3]]) {sym_name = "buf6"} : memref<16x16xf32, 2> -// CHECK: %[[MEM_7_3:.*]] = aie.mem(%[[TILE_7_3]]) { -// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_7_3_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF6]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_7_3_5]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_7_3]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF8]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_7_3]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: -// CHECK: %[[VAL_4:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) -// CHECK: ^bb4: -// CHECK: aie.use_lock(%[[LOCK_7_3_4]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF7]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_7_3_4]], Release, 1) -// CHECK: aie.next_bd ^bb4 -// CHECK: ^bb5: -// CHECK: %[[VAL_5:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) -// CHECK: ^bb6: -// CHECK: aie.use_lock(%[[LOCK_7_3_3]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF8]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_7_3_3]], Release, 0) -// CHECK: aie.next_bd ^bb6 -// CHECK: ^bb7: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) -// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) -// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) -// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) -// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) -// CHECK: %[[LOCK_8_2:.*]] = aie.lock(%[[TILE_8_2]], 1) -// CHECK: %[[LOCK_8_2_6:.*]] = aie.lock(%[[TILE_8_2]], 3) -// CHECK: %[[BUF5:.*]] = aie.buffer(%[[TILE_8_2]]) {sym_name = "buf5"} : memref<16x16xf32, 2> -// CHECK: %[[LOCK_8_2_7:.*]] = aie.lock(%[[TILE_8_2]], 2) -// CHECK: %[[BUF4:.*]] = aie.buffer(%[[TILE_8_2]]) {sym_name = "buf4"} : memref<16x16xf32, 2> -// CHECK: %[[LOCK_8_2_8:.*]] = aie.lock(%[[TILE_8_2]], 0) -// CHECK: %[[BUF3:.*]] = aie.buffer(%[[TILE_8_2]]) {sym_name = "buf3"} : memref<16x16xf32, 2> -// CHECK: %[[MEM_8_2:.*]] = aie.mem(%[[TILE_8_2]]) { -// CHECK: %[[VAL_6:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_8_2_8]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF3]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_8_2_8]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_8_2]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF5]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_8_2]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: -// CHECK: %[[VAL_7:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) -// CHECK: ^bb4: -// CHECK: aie.use_lock(%[[LOCK_8_2_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF4]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_8_2_7]], Release, 1) -// CHECK: aie.next_bd ^bb4 -// CHECK: ^bb5: -// CHECK: %[[VAL_8:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) -// CHECK: ^bb6: -// CHECK: aie.use_lock(%[[LOCK_8_2_6]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF5]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_8_2_6]], Release, 0) -// CHECK: aie.next_bd ^bb6 -// CHECK: ^bb7: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) -// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) -// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) -// CHECK: %[[LOCK_7_2:.*]] = aie.lock(%[[TILE_7_2]], 1) -// CHECK: %[[LOCK_7_2_9:.*]] = aie.lock(%[[TILE_7_2]], 3) -// CHECK: %[[BUF2:.*]] = aie.buffer(%[[TILE_7_2]]) {sym_name = "buf2"} : memref<16x16xf32, 2> -// CHECK: %[[LOCK_7_2_10:.*]] = aie.lock(%[[TILE_7_2]], 2) -// CHECK: %[[BUF1:.*]] = aie.buffer(%[[TILE_7_2]]) {sym_name = "buf1"} : memref<16x16xf32, 2> -// CHECK: %[[LOCK_7_2_11:.*]] = aie.lock(%[[TILE_7_2]], 0) -// CHECK: %[[BUF0:.*]] = aie.buffer(%[[TILE_7_2]]) {sym_name = "buf0"} : memref<16x16xf32, 2> -// CHECK: %[[MEM_7_2:.*]] = aie.mem(%[[TILE_7_2]]) { -// CHECK: %[[VAL_9:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_7_2_11]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF0]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_7_2_11]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_7_2]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF2]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_7_2]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: -// CHECK: %[[VAL_10:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) -// CHECK: ^bb4: -// CHECK: aie.use_lock(%[[LOCK_7_2_10]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF1]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_7_2_10]], Release, 1) -// CHECK: aie.next_bd ^bb4 -// CHECK: ^bb5: -// CHECK: %[[VAL_11:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) -// CHECK: ^bb6: -// CHECK: aie.use_lock(%[[LOCK_7_2_9]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF2]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[LOCK_7_2_9]], Release, 0) -// CHECK: aie.next_bd ^bb6 -// CHECK: ^bb7: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) -// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) -// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) -// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) -// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) -// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) -// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) -// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) -// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) -// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) -// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) -// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) -// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) -// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) -// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) -// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : North, %[[SWITCHBOX_4_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) -// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) -// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) -// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) -// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) -// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) -// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) -// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) -// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) -// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) -// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) -// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) -// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) -// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) -// CHECK: } - -module @aie.herd_0 { - aie.device(xcvc1902) { - %tile_7_1 = aie.tile(7, 1) - %tile_7_0 = aie.tile(7, 0) - %tile_1_1 = aie.tile(1, 1) - %tile_8_3 = aie.tile(8, 3) - %lock_8_3 = aie.lock(%tile_8_3, 1) - %lock_8_3_0 = aie.lock(%tile_8_3, 3) - %buffer_8_3 = aie.buffer(%tile_8_3) {sym_name = "buf11"} : memref<16x16xf32, 2> - %lock_8_3_1 = aie.lock(%tile_8_3, 2) - %buffer_8_3_2 = aie.buffer(%tile_8_3) {sym_name = "buf10"} : memref<16x16xf32, 2> - %lock_8_3_3 = aie.lock(%tile_8_3, 0) - %buffer_8_3_4 = aie.buffer(%tile_8_3) {sym_name = "buf9"} : memref<16x16xf32, 2> - %mem_8_3 = aie.mem(%tile_8_3) { - %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) - ^bb1: // 2 preds: ^bb0, ^bb2 - aie.use_lock(%lock_8_3_3, Acquire, 0) - aie.dma_bd(%buffer_8_3_4 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_3_3, Release, 1) - aie.next_bd ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%lock_8_3, Acquire, 0) - aie.dma_bd(%buffer_8_3 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_3, Release, 1) - aie.next_bd ^bb1 - ^bb3: // pred: ^bb5 - %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) - ^bb4: // 2 preds: ^bb3, ^bb4 - aie.use_lock(%lock_8_3_1, Acquire, 0) - aie.dma_bd(%buffer_8_3_2 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_3_1, Release, 1) - aie.next_bd ^bb4 - ^bb5: // pred: ^bb0 - %2 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) - ^bb6: // 2 preds: ^bb5, ^bb6 - aie.use_lock(%lock_8_3_0, Acquire, 1) - aie.dma_bd(%buffer_8_3 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_3_0, Release, 0) - aie.next_bd ^bb6 - ^bb7: // pred: ^bb3 - aie.end - } - %tile_6_2 = aie.tile(6, 2) - %tile_6_1 = aie.tile(6, 1) - %tile_6_0 = aie.tile(6, 0) - %tile_0_1 = aie.tile(0, 1) - %tile_7_3 = aie.tile(7, 3) - %lock_7_3 = aie.lock(%tile_7_3, 1) - %lock_7_3_5 = aie.lock(%tile_7_3, 3) - %buffer_7_3 = aie.buffer(%tile_7_3) {sym_name = "buf8"} : memref<16x16xf32, 2> - %lock_7_3_6 = aie.lock(%tile_7_3, 2) - %buffer_7_3_7 = aie.buffer(%tile_7_3) {sym_name = "buf7"} : memref<16x16xf32, 2> - %lock_7_3_8 = aie.lock(%tile_7_3, 0) - %buffer_7_3_9 = aie.buffer(%tile_7_3) {sym_name = "buf6"} : memref<16x16xf32, 2> - %mem_7_3 = aie.mem(%tile_7_3) { - %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) - ^bb1: // 2 preds: ^bb0, ^bb2 - aie.use_lock(%lock_7_3_8, Acquire, 0) - aie.dma_bd(%buffer_7_3_9 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_3_8, Release, 1) - aie.next_bd ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%lock_7_3, Acquire, 0) - aie.dma_bd(%buffer_7_3 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_3, Release, 1) - aie.next_bd ^bb1 - ^bb3: // pred: ^bb5 - %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) - ^bb4: // 2 preds: ^bb3, ^bb4 - aie.use_lock(%lock_7_3_6, Acquire, 0) - aie.dma_bd(%buffer_7_3_7 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_3_6, Release, 1) - aie.next_bd ^bb4 - ^bb5: // pred: ^bb0 - %2 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) - ^bb6: // 2 preds: ^bb5, ^bb6 - aie.use_lock(%lock_7_3_5, Acquire, 1) - aie.dma_bd(%buffer_7_3 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_3_5, Release, 0) - aie.next_bd ^bb6 - ^bb7: // pred: ^bb3 - aie.end - } - %tile_3_2 = aie.tile(3, 2) - %tile_3_1 = aie.tile(3, 1) - %tile_3_0 = aie.tile(3, 0) - %tile_1_0 = aie.tile(1, 0) - %tile_8_2 = aie.tile(8, 2) - %lock_8_2 = aie.lock(%tile_8_2, 1) - %lock_8_2_10 = aie.lock(%tile_8_2, 3) - %buffer_8_2 = aie.buffer(%tile_8_2) {sym_name = "buf5"} : memref<16x16xf32, 2> - %lock_8_2_11 = aie.lock(%tile_8_2, 2) - %buffer_8_2_12 = aie.buffer(%tile_8_2) {sym_name = "buf4"} : memref<16x16xf32, 2> - %lock_8_2_13 = aie.lock(%tile_8_2, 0) - %buffer_8_2_14 = aie.buffer(%tile_8_2) {sym_name = "buf3"} : memref<16x16xf32, 2> - %mem_8_2 = aie.mem(%tile_8_2) { - %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) - ^bb1: // 2 preds: ^bb0, ^bb2 - aie.use_lock(%lock_8_2_13, Acquire, 0) - aie.dma_bd(%buffer_8_2_14 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_2_13, Release, 1) - aie.next_bd ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%lock_8_2, Acquire, 0) - aie.dma_bd(%buffer_8_2 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_2, Release, 1) - aie.next_bd ^bb1 - ^bb3: // pred: ^bb5 - %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) - ^bb4: // 2 preds: ^bb3, ^bb4 - aie.use_lock(%lock_8_2_11, Acquire, 0) - aie.dma_bd(%buffer_8_2_12 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_2_11, Release, 1) - aie.next_bd ^bb4 - ^bb5: // pred: ^bb0 - %2 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) - ^bb6: // 2 preds: ^bb5, ^bb6 - aie.use_lock(%lock_8_2_10, Acquire, 1) - aie.dma_bd(%buffer_8_2 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_8_2_10, Release, 0) - aie.next_bd ^bb6 - ^bb7: // pred: ^bb3 - aie.end - } - %tile_2_2 = aie.tile(2, 2) - %tile_2_1 = aie.tile(2, 1) - %tile_2_0 = aie.tile(2, 0) - %tile_0_0 = aie.tile(0, 0) - %tile_7_2 = aie.tile(7, 2) - %lock_7_2 = aie.lock(%tile_7_2, 1) - %lock_7_2_15 = aie.lock(%tile_7_2, 3) - %buffer_7_2 = aie.buffer(%tile_7_2) {sym_name = "buf2"} : memref<16x16xf32, 2> - %lock_7_2_16 = aie.lock(%tile_7_2, 2) - %buffer_7_2_17 = aie.buffer(%tile_7_2) {sym_name = "buf1"} : memref<16x16xf32, 2> - %lock_7_2_18 = aie.lock(%tile_7_2, 0) - %buffer_7_2_19 = aie.buffer(%tile_7_2) {sym_name = "buf0"} : memref<16x16xf32, 2> - %mem_7_2 = aie.mem(%tile_7_2) { - %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb5) - ^bb1: // 2 preds: ^bb0, ^bb2 - aie.use_lock(%lock_7_2_18, Acquire, 0) - aie.dma_bd(%buffer_7_2_19 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_2_18, Release, 1) - aie.next_bd ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%lock_7_2, Acquire, 0) - aie.dma_bd(%buffer_7_2 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_2, Release, 1) - aie.next_bd ^bb1 - ^bb3: // pred: ^bb5 - %1 = aie.dma_start(S2MM, 1, ^bb4, ^bb7) - ^bb4: // 2 preds: ^bb3, ^bb4 - aie.use_lock(%lock_7_2_16, Acquire, 0) - aie.dma_bd(%buffer_7_2_17 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_2_16, Release, 1) - aie.next_bd ^bb4 - ^bb5: // pred: ^bb0 - %2 = aie.dma_start(MM2S, 0, ^bb6, ^bb3) - ^bb6: // 2 preds: ^bb5, ^bb6 - aie.use_lock(%lock_7_2_15, Acquire, 1) - aie.dma_bd(%buffer_7_2 : memref<16x16xf32, 2>, 0, 256) - aie.use_lock(%lock_7_2_15, Release, 0) - aie.next_bd ^bb6 - ^bb7: // pred: ^bb3 - aie.end - } - %switchbox_2_0 = aie.switchbox(%tile_2_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - aie.flow(%tile_2_1, South : 0, %tile_7_2, DMA : 0) - aie.flow(%tile_2_1, South : 1, %tile_7_2, DMA : 1) - aie.flow(%tile_7_2, DMA : 0, %tile_2_1, South : 0) - %switchbox_3_0 = aie.switchbox(%tile_3_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - aie.flow(%tile_3_1, South : 0, %tile_8_2, DMA : 0) - aie.flow(%tile_3_1, South : 1, %tile_8_2, DMA : 1) - aie.flow(%tile_8_2, DMA : 0, %tile_2_1, South : 1) - %switchbox_6_0 = aie.switchbox(%tile_6_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - aie.flow(%tile_6_1, South : 0, %tile_7_3, DMA : 0) - aie.flow(%tile_6_1, South : 1, %tile_7_3, DMA : 1) - aie.flow(%tile_7_3, DMA : 0, %tile_3_1, South : 0) - %switchbox_7_0 = aie.switchbox(%tile_7_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - aie.flow(%tile_7_1, South : 0, %tile_8_3, DMA : 0) - aie.flow(%tile_7_1, South : 1, %tile_8_3, DMA : 1) - aie.flow(%tile_8_3, DMA : 0, %tile_3_1, South : 1) - %shimmux_2_0 = aie.shim_mux(%tile_2_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - %shimmux_3_0 = aie.shim_mux(%tile_3_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - %shimmux_6_0 = aie.shim_mux(%tile_6_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - %shimmux_7_0 = aie.shim_mux(%tile_7_0) { - aie.connect - aie.connect - aie.connect - aie.connect - } - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_more_flows_shim.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_more_flows_shim.mlir deleted file mode 100644 index 3e87bc19f..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_more_flows_shim.mlir +++ /dev/null @@ -1,121 +0,0 @@ - -// RUN: iree-opt --split-input-file --aie-create-pathfinder-flows -split-input-file %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) -// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) -// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) -// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) -// CHECK: } - -// Tile 7,0 is a shim NoC tile that has a ShimMux. -// The ShimMux must be configured for streams to PLIO 2,3,4,5 -module @test70 { - aie.device(xcvc1902) { - %t70 = aie.tile(7, 0) - %t71 = aie.tile(7, 1) - aie.flow(%t71, North : 0, %t70, PLIO : 2) - } -} - -// ----- - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) -// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) -// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) -// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) -// CHECK: } - -// Tile 6,0 is a shim NoC tile that has a ShimMux. -// The ShimMux must be configured for streams from PLIO 2,3,6,7 -module @test60 { - aie.device(xcvc1902) { - %t60 = aie.tile(6, 0) - %t61 = aie.tile(6, 1) - aie.flow(%t60, PLIO : 6, %t61, DMA : 1) - } -} - -// ----- - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) -// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) -// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_0:.*]] : North, %[[SWITCHBOX_4_1]] : South) -// CHECK: } - -// Tile 4,0 is a shim PL tile and does not contain a ShimMux. -module @test40 { - aie.device(xcvc1902) { - %t40 = aie.tile(4, 0) - %t41 = aie.tile(4, 1) - aie.flow(%t41, North : 0, %t40, PLIO : 3) - aie.flow(%t40, PLIO : 4, %t41, North : 0) - } -} - -// ----- - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_10_0:.*]] = aie.tile(10, 0) -// CHECK: %[[TILE_10_1:.*]] = aie.tile(10, 1) -// CHECK: %[[SWITCHBOX_10_0:.*]] = aie.switchbox(%[[TILE_10_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_10_0:.*]] = aie.shim_mux(%[[TILE_10_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_1:.*]] = aie.switchbox(%[[TILE_10_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[SHIM_MUX_10_0:.*]] : North, %[[SWITCHBOX_10_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_10_0]] : DMA, %[[SHIM_MUX_10_0]] : DMA) -// CHECK: aie.wire(%[[TILE_10_1]] : Core, %[[SWITCHBOX_10_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_10_1]] : DMA, %[[SWITCHBOX_10_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : North, %[[SWITCHBOX_10_1]] : South) -// CHECK: } - -// Tile 10,0 is a shim NoC tile that has a ShimMux. -// The ShimMux must be configured for streams to NOC 0,1,2,3 -module @test100 { - aie.device(xcvc1902) { - %t100 = aie.tile(10, 0) - %t101 = aie.tile(10, 1) - aie.flow(%t101, North : 0, %t100, NOC : 2) - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_over_flows.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_over_flows.mlir deleted file mode 100644 index 4c63f1dc3..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_over_flows.mlir +++ /dev/null @@ -1,199 +0,0 @@ - -// RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) -// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) -// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) -// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) -// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) -// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) -// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) -// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) -// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) -// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) -// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) -// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) -// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) -// CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) -// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) -// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) -// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) -// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) -// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) -// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) -// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) -// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) -// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) -// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) -// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : North, %[[SWITCHBOX_4_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) -// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) -// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) -// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) -// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) -// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) -// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) -// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) -// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) -// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) -// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t03 = aie.tile(0, 3) - %t02 = aie.tile(0, 2) - %t00 = aie.tile(0, 0) - %t13 = aie.tile(1, 3) - %t11 = aie.tile(1, 1) - %t10 = aie.tile(1, 0) - %t20 = aie.tile(2, 0) - %t30 = aie.tile(3, 0) - %t22 = aie.tile(2, 2) - %t31 = aie.tile(3, 1) - %t60 = aie.tile(6, 0) - %t70 = aie.tile(7, 0) - %t71 = aie.tile(7, 1) - %t72 = aie.tile(7, 2) - %t73 = aie.tile(7, 3) - %t80 = aie.tile(8, 0) - %t82 = aie.tile(8, 2) - %t83 = aie.tile(8, 3) - aie.flow(%t71, DMA : 0, %t20, DMA : 0) - aie.flow(%t71, DMA : 1, %t20, DMA : 1) - aie.flow(%t72, DMA : 0, %t60, DMA : 0) - aie.flow(%t72, DMA : 1, %t60, DMA : 1) - aie.flow(%t73, DMA : 0, %t70, DMA : 0) - aie.flow(%t73, DMA : 1, %t70, DMA : 1) - aie.flow(%t83, DMA : 0, %t30, DMA : 0) - aie.flow(%t83, DMA : 1, %t30, DMA : 1) - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x1.mlir deleted file mode 100644 index 329bc2078..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x1.mlir +++ /dev/null @@ -1,814 +0,0 @@ - -// RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) -// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) -// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) -// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) -// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) -// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) -// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) -// CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) -// CHECK: %[[TILE_9_0:.*]] = aie.tile(9, 0) -// CHECK: %[[TILE_10_0:.*]] = aie.tile(10, 0) -// CHECK: %[[TILE_11_0:.*]] = aie.tile(11, 0) -// CHECK: %[[TILE_18_0:.*]] = aie.tile(18, 0) -// CHECK: %[[TILE_19_0:.*]] = aie.tile(19, 0) -// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) -// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) -// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) -// CHECK: %[[TILE_0_4:.*]] = aie.tile(0, 4) -// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) -// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) -// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) -// CHECK: %[[TILE_1_4:.*]] = aie.tile(1, 4) -// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) -// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) -// CHECK: %[[TILE_2_4:.*]] = aie.tile(2, 4) -// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) -// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) -// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) -// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) -// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) -// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) -// CHECK: %[[TILE_4_4:.*]] = aie.tile(4, 4) -// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) -// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) -// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) -// CHECK: %[[TILE_5_4:.*]] = aie.tile(5, 4) -// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) -// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) -// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) -// CHECK: %[[TILE_6_4:.*]] = aie.tile(6, 4) -// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) -// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) -// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) -// CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) -// CHECK: %[[TILE_8_1:.*]] = aie.tile(8, 1) -// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) -// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) -// CHECK: %[[TILE_8_4:.*]] = aie.tile(8, 4) -// CHECK: %[[TILE_9_1:.*]] = aie.tile(9, 1) -// CHECK: %[[TILE_9_2:.*]] = aie.tile(9, 2) -// CHECK: %[[TILE_9_3:.*]] = aie.tile(9, 3) -// CHECK: %[[TILE_9_4:.*]] = aie.tile(9, 4) -// CHECK: %[[TILE_10_1:.*]] = aie.tile(10, 1) -// CHECK: %[[TILE_10_2:.*]] = aie.tile(10, 2) -// CHECK: %[[TILE_10_3:.*]] = aie.tile(10, 3) -// CHECK: %[[TILE_10_4:.*]] = aie.tile(10, 4) -// CHECK: %[[TILE_11_1:.*]] = aie.tile(11, 1) -// CHECK: %[[TILE_11_2:.*]] = aie.tile(11, 2) -// CHECK: %[[TILE_11_3:.*]] = aie.tile(11, 3) -// CHECK: %[[TILE_11_4:.*]] = aie.tile(11, 4) -// CHECK: %[[TILE_12_1:.*]] = aie.tile(12, 1) -// CHECK: %[[TILE_12_2:.*]] = aie.tile(12, 2) -// CHECK: %[[TILE_12_3:.*]] = aie.tile(12, 3) -// CHECK: %[[TILE_12_4:.*]] = aie.tile(12, 4) -// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_4_4:.*]] = aie.switchbox(%[[TILE_4_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_5_4:.*]] = aie.switchbox(%[[TILE_5_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_4:.*]] = aie.switchbox(%[[TILE_6_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_1:.*]] = aie.switchbox(%[[TILE_8_1]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_9_1:.*]] = aie.switchbox(%[[TILE_9_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_9_2:.*]] = aie.switchbox(%[[TILE_9_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_9_3:.*]] = aie.switchbox(%[[TILE_9_3]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_9_4:.*]] = aie.switchbox(%[[TILE_9_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_10_1:.*]] = aie.switchbox(%[[TILE_10_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_2:.*]] = aie.switchbox(%[[TILE_10_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_3:.*]] = aie.switchbox(%[[TILE_10_3]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_10_4:.*]] = aie.switchbox(%[[TILE_10_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_11_1:.*]] = aie.switchbox(%[[TILE_11_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_11_2:.*]] = aie.switchbox(%[[TILE_11_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_11_3:.*]] = aie.switchbox(%[[TILE_11_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_11_4:.*]] = aie.switchbox(%[[TILE_11_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_0_0:.*]] = aie.switchbox(%[[TILE_0_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_0:.*]] = aie.switchbox(%[[TILE_10_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_10_0:.*]] = aie.shim_mux(%[[TILE_10_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_11_0:.*]] = aie.switchbox(%[[TILE_11_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_11_0:.*]] = aie.shim_mux(%[[TILE_11_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_0:.*]] = aie.switchbox(%[[TILE_8_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_9_0:.*]] = aie.switchbox(%[[TILE_9_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_12_0:.*]] = aie.tile(12, 0) -// CHECK: %[[SWITCHBOX_12_0:.*]] = aie.switchbox(%[[TILE_12_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_13_0:.*]] = aie.tile(13, 0) -// CHECK: %[[SWITCHBOX_13_0:.*]] = aie.switchbox(%[[TILE_13_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_14_0:.*]] = aie.tile(14, 0) -// CHECK: %[[SWITCHBOX_14_0:.*]] = aie.switchbox(%[[TILE_14_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_15_0:.*]] = aie.tile(15, 0) -// CHECK: %[[SWITCHBOX_15_0:.*]] = aie.switchbox(%[[TILE_15_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_16_0:.*]] = aie.tile(16, 0) -// CHECK: %[[SWITCHBOX_16_0:.*]] = aie.switchbox(%[[TILE_16_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_17_0:.*]] = aie.tile(17, 0) -// CHECK: %[[SWITCHBOX_17_0:.*]] = aie.switchbox(%[[TILE_17_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_18_0:.*]] = aie.switchbox(%[[TILE_18_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_18_0:.*]] = aie.shim_mux(%[[TILE_18_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_19_0:.*]] = aie.switchbox(%[[TILE_19_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_19_0:.*]] = aie.shim_mux(%[[TILE_19_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_0:.*]] : North, %[[SWITCHBOX_0_1]] : South) -// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) -// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) -// CHECK: aie.wire(%[[TILE_0_4]] : Core, %[[SWITCHBOX_0_4:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_4]] : DMA, %[[SWITCHBOX_0_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : North, %[[SWITCHBOX_0_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_0]] : East, %[[SWITCHBOX_1_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) -// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : North, %[[SWITCHBOX_1_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) -// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) -// CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : North, %[[SWITCHBOX_1_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_4]] : East, %[[SWITCHBOX_1_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_4]] : Core, %[[SWITCHBOX_1_4]] : Core) -// CHECK: aie.wire(%[[TILE_1_4]] : DMA, %[[SWITCHBOX_1_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : North, %[[SWITCHBOX_1_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : East, %[[SWITCHBOX_2_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0]] : South) -// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) -// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2]] : Core) -// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : East, %[[SWITCHBOX_2_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3]] : Core) -// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_4]] : East, %[[SWITCHBOX_2_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_4]] : Core, %[[SWITCHBOX_2_4]] : Core) -// CHECK: aie.wire(%[[TILE_2_4]] : DMA, %[[SWITCHBOX_2_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : North, %[[SWITCHBOX_2_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) -// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) -// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) -// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : East, %[[SWITCHBOX_3_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3]] : Core) -// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_4]] : East, %[[SWITCHBOX_3_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_4]] : Core, %[[SWITCHBOX_3_4]] : Core) -// CHECK: aie.wire(%[[TILE_3_4]] : DMA, %[[SWITCHBOX_3_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : North, %[[SWITCHBOX_3_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) -// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : North, %[[SWITCHBOX_4_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) -// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) -// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : North, %[[SWITCHBOX_4_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_4]] : East, %[[SWITCHBOX_4_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_4]] : Core, %[[SWITCHBOX_4_4]] : Core) -// CHECK: aie.wire(%[[TILE_4_4]] : DMA, %[[SWITCHBOX_4_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : North, %[[SWITCHBOX_4_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : East, %[[SWITCHBOX_5_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) -// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : North, %[[SWITCHBOX_5_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) -// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) -// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_4]] : East, %[[SWITCHBOX_5_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_4]] : Core, %[[SWITCHBOX_5_4]] : Core) -// CHECK: aie.wire(%[[TILE_5_4]] : DMA, %[[SWITCHBOX_5_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : North, %[[SWITCHBOX_5_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) -// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) -// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) -// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) -// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_4]] : East, %[[SWITCHBOX_6_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_4]] : Core, %[[SWITCHBOX_6_4]] : Core) -// CHECK: aie.wire(%[[TILE_6_4]] : DMA, %[[SWITCHBOX_6_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : North, %[[SWITCHBOX_6_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) -// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) -// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) -// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) -// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_4]] : East, %[[SWITCHBOX_7_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_4]] : Core, %[[SWITCHBOX_7_4]] : Core) -// CHECK: aie.wire(%[[TILE_7_4]] : DMA, %[[SWITCHBOX_7_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : North, %[[SWITCHBOX_7_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : East, %[[SWITCHBOX_8_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : East, %[[SWITCHBOX_8_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_1]] : Core, %[[SWITCHBOX_8_1]] : Core) -// CHECK: aie.wire(%[[TILE_8_1]] : DMA, %[[SWITCHBOX_8_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_0]] : North, %[[SWITCHBOX_8_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) -// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : North, %[[SWITCHBOX_8_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) -// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : East, %[[SWITCHBOX_8_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_4]] : Core, %[[SWITCHBOX_8_4]] : Core) -// CHECK: aie.wire(%[[TILE_8_4]] : DMA, %[[SWITCHBOX_8_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : North, %[[SWITCHBOX_8_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_8_0]] : East, %[[SWITCHBOX_9_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : East, %[[SWITCHBOX_9_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_1]] : Core, %[[SWITCHBOX_9_1]] : Core) -// CHECK: aie.wire(%[[TILE_9_1]] : DMA, %[[SWITCHBOX_9_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_0]] : North, %[[SWITCHBOX_9_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : East, %[[SWITCHBOX_9_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_2]] : Core, %[[SWITCHBOX_9_2]] : Core) -// CHECK: aie.wire(%[[TILE_9_2]] : DMA, %[[SWITCHBOX_9_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_1]] : North, %[[SWITCHBOX_9_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : East, %[[SWITCHBOX_9_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_3]] : Core, %[[SWITCHBOX_9_3]] : Core) -// CHECK: aie.wire(%[[TILE_9_3]] : DMA, %[[SWITCHBOX_9_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : North, %[[SWITCHBOX_9_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_8_4]] : East, %[[SWITCHBOX_9_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_4]] : Core, %[[SWITCHBOX_9_4]] : Core) -// CHECK: aie.wire(%[[TILE_9_4]] : DMA, %[[SWITCHBOX_9_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_3]] : North, %[[SWITCHBOX_9_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_9_0]] : East, %[[SWITCHBOX_10_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_10_0:.*]] : North, %[[SWITCHBOX_10_0]] : South) -// CHECK: aie.wire(%[[TILE_10_0]] : DMA, %[[SHIM_MUX_10_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_1]] : East, %[[SWITCHBOX_10_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_1]] : Core, %[[SWITCHBOX_10_1]] : Core) -// CHECK: aie.wire(%[[TILE_10_1]] : DMA, %[[SWITCHBOX_10_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : North, %[[SWITCHBOX_10_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : East, %[[SWITCHBOX_10_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_2]] : Core, %[[SWITCHBOX_10_2]] : Core) -// CHECK: aie.wire(%[[TILE_10_2]] : DMA, %[[SWITCHBOX_10_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_1]] : North, %[[SWITCHBOX_10_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_9_3]] : East, %[[SWITCHBOX_10_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_3]] : Core, %[[SWITCHBOX_10_3]] : Core) -// CHECK: aie.wire(%[[TILE_10_3]] : DMA, %[[SWITCHBOX_10_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_2]] : North, %[[SWITCHBOX_10_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_9_4]] : East, %[[SWITCHBOX_10_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_4]] : Core, %[[SWITCHBOX_10_4]] : Core) -// CHECK: aie.wire(%[[TILE_10_4]] : DMA, %[[SWITCHBOX_10_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_3]] : North, %[[SWITCHBOX_10_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : East, %[[SWITCHBOX_11_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_11_0:.*]] : North, %[[SWITCHBOX_11_0]] : South) -// CHECK: aie.wire(%[[TILE_11_0]] : DMA, %[[SHIM_MUX_11_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_1]] : East, %[[SWITCHBOX_11_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_1]] : Core, %[[SWITCHBOX_11_1]] : Core) -// CHECK: aie.wire(%[[TILE_11_1]] : DMA, %[[SWITCHBOX_11_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_0]] : North, %[[SWITCHBOX_11_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_2]] : East, %[[SWITCHBOX_11_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_2]] : Core, %[[SWITCHBOX_11_2]] : Core) -// CHECK: aie.wire(%[[TILE_11_2]] : DMA, %[[SWITCHBOX_11_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_1]] : North, %[[SWITCHBOX_11_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_3]] : East, %[[SWITCHBOX_11_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_3]] : Core, %[[SWITCHBOX_11_3]] : Core) -// CHECK: aie.wire(%[[TILE_11_3]] : DMA, %[[SWITCHBOX_11_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_2]] : North, %[[SWITCHBOX_11_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_4]] : East, %[[SWITCHBOX_11_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_4]] : Core, %[[SWITCHBOX_11_4]] : Core) -// CHECK: aie.wire(%[[TILE_11_4]] : DMA, %[[SWITCHBOX_11_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_3]] : North, %[[SWITCHBOX_11_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_11_0]] : East, %[[SWITCHBOX_12_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_12_0]] : East, %[[SWITCHBOX_13_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_13_0]] : East, %[[SWITCHBOX_14_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_14_0]] : East, %[[SWITCHBOX_15_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_15_0]] : East, %[[SWITCHBOX_16_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_16_0]] : East, %[[SWITCHBOX_17_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_17_0]] : East, %[[SWITCHBOX_18_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_18_0:.*]] : North, %[[SWITCHBOX_18_0]] : South) -// CHECK: aie.wire(%[[TILE_18_0]] : DMA, %[[SHIM_MUX_18_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_18_0]] : East, %[[SWITCHBOX_19_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_19_0:.*]] : North, %[[SWITCHBOX_19_0]] : South) -// CHECK: aie.wire(%[[TILE_19_0]] : DMA, %[[SHIM_MUX_19_0]] : DMA) -// CHECK: } - -module { - aie.device(xcvc1902) { - %tile_0_0 = aie.tile(0, 0) - %tile_1_0 = aie.tile(1, 0) - %tile_2_0 = aie.tile(2, 0) - %tile_3_0 = aie.tile(3, 0) - %tile_4_0 = aie.tile(4, 0) - %tile_5_0 = aie.tile(5, 0) - %tile_6_0 = aie.tile(6, 0) - %tile_7_0 = aie.tile(7, 0) - %tile_8_0 = aie.tile(8, 0) - %tile_9_0 = aie.tile(9, 0) - %tile_10_0 = aie.tile(10, 0) - %tile_11_0 = aie.tile(11, 0) - %tile_18_0 = aie.tile(18, 0) - %tile_19_0 = aie.tile(19, 0) - %tile_0_1 = aie.tile(0, 1) - %tile_0_2 = aie.tile(0, 2) - %tile_0_3 = aie.tile(0, 3) - %tile_0_4 = aie.tile(0, 4) - %tile_1_1 = aie.tile(1, 1) - %tile_1_2 = aie.tile(1, 2) - %tile_1_3 = aie.tile(1, 3) - %tile_1_4 = aie.tile(1, 4) - %tile_2_1 = aie.tile(2, 1) - %tile_2_2 = aie.tile(2, 2) - %tile_2_3 = aie.tile(2, 3) - %tile_2_4 = aie.tile(2, 4) - %tile_3_1 = aie.tile(3, 1) - %tile_3_2 = aie.tile(3, 2) - %tile_3_3 = aie.tile(3, 3) - %tile_3_4 = aie.tile(3, 4) - %tile_4_1 = aie.tile(4, 1) - %tile_4_2 = aie.tile(4, 2) - %tile_4_3 = aie.tile(4, 3) - %tile_4_4 = aie.tile(4, 4) - %tile_5_1 = aie.tile(5, 1) - %tile_5_2 = aie.tile(5, 2) - %tile_5_3 = aie.tile(5, 3) - %tile_5_4 = aie.tile(5, 4) - %tile_6_1 = aie.tile(6, 1) - %tile_6_2 = aie.tile(6, 2) - %tile_6_3 = aie.tile(6, 3) - %tile_6_4 = aie.tile(6, 4) - %tile_7_1 = aie.tile(7, 1) - %tile_7_2 = aie.tile(7, 2) - %tile_7_3 = aie.tile(7, 3) - %tile_7_4 = aie.tile(7, 4) - %tile_8_1 = aie.tile(8, 1) - %tile_8_2 = aie.tile(8, 2) - %tile_8_3 = aie.tile(8, 3) - %tile_8_4 = aie.tile(8, 4) - %tile_9_1 = aie.tile(9, 1) - %tile_9_2 = aie.tile(9, 2) - %tile_9_3 = aie.tile(9, 3) - %tile_9_4 = aie.tile(9, 4) - %tile_10_1 = aie.tile(10, 1) - %tile_10_2 = aie.tile(10, 2) - %tile_10_3 = aie.tile(10, 3) - %tile_10_4 = aie.tile(10, 4) - %tile_11_1 = aie.tile(11, 1) - %tile_11_2 = aie.tile(11, 2) - %tile_11_3 = aie.tile(11, 3) - %tile_11_4 = aie.tile(11, 4) - %tile_12_1 = aie.tile(12, 1) - %tile_12_2 = aie.tile(12, 2) - %tile_12_3 = aie.tile(12, 3) - %tile_12_4 = aie.tile(12, 4) - %switchbox_0_1 = aie.switchbox(%tile_0_1) { - aie.connect - } - %switchbox_0_2 = aie.switchbox(%tile_0_2) { - aie.connect - } - %switchbox_0_3 = aie.switchbox(%tile_0_3) { - aie.connect - aie.connect - } - %switchbox_0_4 = aie.switchbox(%tile_0_4) { - } - %switchbox_1_1 = aie.switchbox(%tile_1_1) { - aie.connect - } - %switchbox_1_2 = aie.switchbox(%tile_1_2) { - aie.connect - } - %switchbox_1_3 = aie.switchbox(%tile_1_3) { - aie.connect - } - %switchbox_1_4 = aie.switchbox(%tile_1_4) { - aie.connect - } - %switchbox_2_1 = aie.switchbox(%tile_2_1) { - aie.connect - } - %switchbox_2_2 = aie.switchbox(%tile_2_2) { - aie.connect - } - %switchbox_2_3 = aie.switchbox(%tile_2_3) { - aie.connect - } - %switchbox_2_4 = aie.switchbox(%tile_2_4) { - aie.connect - } - %switchbox_3_1 = aie.switchbox(%tile_3_1) { - aie.connect - } - %switchbox_3_2 = aie.switchbox(%tile_3_2) { - aie.connect - } - %switchbox_3_3 = aie.switchbox(%tile_3_3) { - aie.connect - } - %switchbox_3_4 = aie.switchbox(%tile_3_4) { - } - %switchbox_4_1 = aie.switchbox(%tile_4_1) { - aie.connect - } - %switchbox_4_2 = aie.switchbox(%tile_4_2) { - aie.connect - } - %switchbox_4_3 = aie.switchbox(%tile_4_3) { - } - %switchbox_4_4 = aie.switchbox(%tile_4_4) { - } - %switchbox_5_1 = aie.switchbox(%tile_5_1) { - aie.connect - } - %switchbox_5_2 = aie.switchbox(%tile_5_2) { - aie.connect - } - %switchbox_5_3 = aie.switchbox(%tile_5_3) { - aie.connect - } - %switchbox_5_4 = aie.switchbox(%tile_5_4) { - } - %switchbox_6_1 = aie.switchbox(%tile_6_1) { - aie.connect - aie.connect - } - %switchbox_6_2 = aie.switchbox(%tile_6_2) { - aie.connect - aie.connect - } - %switchbox_6_3 = aie.switchbox(%tile_6_3) { - aie.connect - aie.connect - } - %switchbox_6_4 = aie.switchbox(%tile_6_4) { - } - %switchbox_7_1 = aie.switchbox(%tile_7_1) { - aie.connect - aie.connect - } - %switchbox_7_2 = aie.switchbox(%tile_7_2) { - aie.connect - aie.connect - } - %switchbox_7_3 = aie.switchbox(%tile_7_3) { - aie.connect - aie.connect - } - %switchbox_7_4 = aie.switchbox(%tile_7_4) { - aie.connect - aie.connect - } - %switchbox_8_1 = aie.switchbox(%tile_8_1) { - } - %switchbox_8_2 = aie.switchbox(%tile_8_2) { - } - %switchbox_8_3 = aie.switchbox(%tile_8_3) { - } - %switchbox_8_4 = aie.switchbox(%tile_8_4) { - } - %switchbox_9_1 = aie.switchbox(%tile_9_1) { - aie.connect - } - %switchbox_9_2 = aie.switchbox(%tile_9_2) { - aie.connect - } - %switchbox_9_3 = aie.switchbox(%tile_9_3) { - } - %switchbox_9_4 = aie.switchbox(%tile_9_4) { - } - %switchbox_10_1 = aie.switchbox(%tile_10_1) { - aie.connect - } - %switchbox_10_2 = aie.switchbox(%tile_10_2) { - aie.connect - } - %switchbox_10_3 = aie.switchbox(%tile_10_3) { - } - %switchbox_10_4 = aie.switchbox(%tile_10_4) { - } - %switchbox_11_1 = aie.switchbox(%tile_11_1) { - aie.connect - aie.connect - } - %switchbox_11_2 = aie.switchbox(%tile_11_2) { - aie.connect - aie.connect - } - %switchbox_11_3 = aie.switchbox(%tile_11_3) { - aie.connect - aie.connect - } - %switchbox_11_4 = aie.switchbox(%tile_11_4) { - } - aie.flow(%tile_2_0, DMA : 0, %tile_2_0, North : 0) - aie.flow(%tile_2_0, DMA : 1, %tile_6_0, North : 1) - aie.flow(%tile_3_0, DMA : 0, %tile_3_0, North : 0) - aie.flow(%tile_3_0, DMA : 1, %tile_7_0, North : 1) - aie.flow(%tile_6_0, DMA : 0, %tile_0_0, North : 0) - aie.flow(%tile_6_0, DMA : 1, %tile_4_0, North : 0) - aie.flow(%tile_7_0, DMA : 0, %tile_1_0, North : 0) - aie.flow(%tile_7_0, DMA : 1, %tile_5_0, North : 0) - aie.flow(%tile_10_0, DMA : 0, %tile_10_0, North : 0) - aie.flow(%tile_11_0, DMA : 0, %tile_11_0, North : 0) - aie.flow(%tile_18_0, DMA : 0, %tile_6_0, North : 0) - aie.flow(%tile_18_0, DMA : 1, %tile_9_0, North : 0) - aie.flow(%tile_19_0, DMA : 0, %tile_7_0, North : 0) - aie.flow(%tile_19_0, DMA : 1, %tile_11_0, North : 1) - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x2.mlir deleted file mode 100644 index 5fe7af528..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x2.mlir +++ /dev/null @@ -1,1009 +0,0 @@ - -// RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) -// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) -// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) -// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) -// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) -// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) -// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) -// CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) -// CHECK: %[[TILE_9_0:.*]] = aie.tile(9, 0) -// CHECK: %[[TILE_10_0:.*]] = aie.tile(10, 0) -// CHECK: %[[TILE_11_0:.*]] = aie.tile(11, 0) -// CHECK: %[[TILE_18_0:.*]] = aie.tile(18, 0) -// CHECK: %[[TILE_19_0:.*]] = aie.tile(19, 0) -// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) -// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) -// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) -// CHECK: %[[TILE_0_4:.*]] = aie.tile(0, 4) -// CHECK: %[[TILE_0_5:.*]] = aie.tile(0, 5) -// CHECK: %[[TILE_0_6:.*]] = aie.tile(0, 6) -// CHECK: %[[TILE_0_7:.*]] = aie.tile(0, 7) -// CHECK: %[[TILE_0_8:.*]] = aie.tile(0, 8) -// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) -// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) -// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) -// CHECK: %[[TILE_1_4:.*]] = aie.tile(1, 4) -// CHECK: %[[TILE_1_5:.*]] = aie.tile(1, 5) -// CHECK: %[[TILE_1_6:.*]] = aie.tile(1, 6) -// CHECK: %[[TILE_1_7:.*]] = aie.tile(1, 7) -// CHECK: %[[TILE_1_8:.*]] = aie.tile(1, 8) -// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) -// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) -// CHECK: %[[TILE_2_4:.*]] = aie.tile(2, 4) -// CHECK: %[[TILE_2_5:.*]] = aie.tile(2, 5) -// CHECK: %[[TILE_2_6:.*]] = aie.tile(2, 6) -// CHECK: %[[TILE_2_7:.*]] = aie.tile(2, 7) -// CHECK: %[[TILE_2_8:.*]] = aie.tile(2, 8) -// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) -// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) -// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) -// CHECK: %[[TILE_3_5:.*]] = aie.tile(3, 5) -// CHECK: %[[TILE_3_6:.*]] = aie.tile(3, 6) -// CHECK: %[[TILE_3_7:.*]] = aie.tile(3, 7) -// CHECK: %[[TILE_3_8:.*]] = aie.tile(3, 8) -// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) -// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) -// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) -// CHECK: %[[TILE_4_4:.*]] = aie.tile(4, 4) -// CHECK: %[[TILE_4_5:.*]] = aie.tile(4, 5) -// CHECK: %[[TILE_4_6:.*]] = aie.tile(4, 6) -// CHECK: %[[TILE_4_7:.*]] = aie.tile(4, 7) -// CHECK: %[[TILE_4_8:.*]] = aie.tile(4, 8) -// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) -// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) -// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) -// CHECK: %[[TILE_5_4:.*]] = aie.tile(5, 4) -// CHECK: %[[TILE_5_5:.*]] = aie.tile(5, 5) -// CHECK: %[[TILE_5_6:.*]] = aie.tile(5, 6) -// CHECK: %[[TILE_5_7:.*]] = aie.tile(5, 7) -// CHECK: %[[TILE_5_8:.*]] = aie.tile(5, 8) -// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) -// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) -// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) -// CHECK: %[[TILE_6_4:.*]] = aie.tile(6, 4) -// CHECK: %[[TILE_6_5:.*]] = aie.tile(6, 5) -// CHECK: %[[TILE_6_6:.*]] = aie.tile(6, 6) -// CHECK: %[[TILE_6_7:.*]] = aie.tile(6, 7) -// CHECK: %[[TILE_6_8:.*]] = aie.tile(6, 8) -// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) -// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) -// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) -// CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) -// CHECK: %[[TILE_7_5:.*]] = aie.tile(7, 5) -// CHECK: %[[TILE_7_6:.*]] = aie.tile(7, 6) -// CHECK: %[[TILE_7_7:.*]] = aie.tile(7, 7) -// CHECK: %[[TILE_7_8:.*]] = aie.tile(7, 8) -// CHECK: %[[TILE_8_1:.*]] = aie.tile(8, 1) -// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) -// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) -// CHECK: %[[TILE_8_4:.*]] = aie.tile(8, 4) -// CHECK: %[[TILE_8_5:.*]] = aie.tile(8, 5) -// CHECK: %[[TILE_8_6:.*]] = aie.tile(8, 6) -// CHECK: %[[TILE_8_7:.*]] = aie.tile(8, 7) -// CHECK: %[[TILE_8_8:.*]] = aie.tile(8, 8) -// CHECK: %[[TILE_9_1:.*]] = aie.tile(9, 1) -// CHECK: %[[TILE_9_2:.*]] = aie.tile(9, 2) -// CHECK: %[[TILE_9_3:.*]] = aie.tile(9, 3) -// CHECK: %[[TILE_9_4:.*]] = aie.tile(9, 4) -// CHECK: %[[TILE_9_5:.*]] = aie.tile(9, 5) -// CHECK: %[[TILE_9_6:.*]] = aie.tile(9, 6) -// CHECK: %[[TILE_9_7:.*]] = aie.tile(9, 7) -// CHECK: %[[TILE_9_8:.*]] = aie.tile(9, 8) -// CHECK: %[[TILE_10_1:.*]] = aie.tile(10, 1) -// CHECK: %[[TILE_10_2:.*]] = aie.tile(10, 2) -// CHECK: %[[TILE_10_3:.*]] = aie.tile(10, 3) -// CHECK: %[[TILE_10_4:.*]] = aie.tile(10, 4) -// CHECK: %[[TILE_10_5:.*]] = aie.tile(10, 5) -// CHECK: %[[TILE_10_6:.*]] = aie.tile(10, 6) -// CHECK: %[[TILE_10_7:.*]] = aie.tile(10, 7) -// CHECK: %[[TILE_10_8:.*]] = aie.tile(10, 8) -// CHECK: %[[TILE_11_1:.*]] = aie.tile(11, 1) -// CHECK: %[[TILE_11_2:.*]] = aie.tile(11, 2) -// CHECK: %[[TILE_11_3:.*]] = aie.tile(11, 3) -// CHECK: %[[TILE_11_4:.*]] = aie.tile(11, 4) -// CHECK: %[[TILE_11_5:.*]] = aie.tile(11, 5) -// CHECK: %[[TILE_11_6:.*]] = aie.tile(11, 6) -// CHECK: %[[TILE_11_7:.*]] = aie.tile(11, 7) -// CHECK: %[[TILE_11_8:.*]] = aie.tile(11, 8) -// CHECK: %[[TILE_12_1:.*]] = aie.tile(12, 1) -// CHECK: %[[TILE_12_2:.*]] = aie.tile(12, 2) -// CHECK: %[[TILE_12_3:.*]] = aie.tile(12, 3) -// CHECK: %[[TILE_12_4:.*]] = aie.tile(12, 4) -// CHECK: %[[TILE_12_5:.*]] = aie.tile(12, 5) -// CHECK: %[[TILE_12_6:.*]] = aie.tile(12, 6) -// CHECK: %[[TILE_12_7:.*]] = aie.tile(12, 7) -// CHECK: %[[TILE_12_8:.*]] = aie.tile(12, 8) -// CHECK: %[[TILE_13_0:.*]] = aie.tile(13, 0) -// CHECK: %[[TILE_13_1:.*]] = aie.tile(13, 1) -// CHECK: %[[TILE_13_2:.*]] = aie.tile(13, 2) -// CHECK: %[[TILE_13_3:.*]] = aie.tile(13, 3) -// CHECK: %[[TILE_13_4:.*]] = aie.tile(13, 4) -// CHECK: %[[TILE_13_5:.*]] = aie.tile(13, 5) -// CHECK: %[[TILE_13_6:.*]] = aie.tile(13, 6) -// CHECK: %[[TILE_13_7:.*]] = aie.tile(13, 7) -// CHECK: %[[TILE_13_8:.*]] = aie.tile(13, 8) -// CHECK: %[[TILE_14_1:.*]] = aie.tile(14, 1) -// CHECK: %[[TILE_14_2:.*]] = aie.tile(14, 2) -// CHECK: %[[TILE_14_3:.*]] = aie.tile(14, 3) -// CHECK: %[[TILE_14_4:.*]] = aie.tile(14, 4) -// CHECK: %[[TILE_14_5:.*]] = aie.tile(14, 5) -// CHECK: %[[TILE_14_6:.*]] = aie.tile(14, 6) -// CHECK: %[[TILE_14_7:.*]] = aie.tile(14, 7) -// CHECK: %[[TILE_14_8:.*]] = aie.tile(14, 8) -// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_5:.*]] = aie.switchbox(%[[TILE_2_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_5:.*]] = aie.switchbox(%[[TILE_3_5]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_4_4:.*]] = aie.switchbox(%[[TILE_4_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_5_4:.*]] = aie.switchbox(%[[TILE_5_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_5_5:.*]] = aie.switchbox(%[[TILE_5_5]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_5_6:.*]] = aie.switchbox(%[[TILE_5_6]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_6_4:.*]] = aie.switchbox(%[[TILE_6_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_6_5:.*]] = aie.switchbox(%[[TILE_6_5]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_6_6:.*]] = aie.switchbox(%[[TILE_6_6]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_5:.*]] = aie.switchbox(%[[TILE_7_5]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_6:.*]] = aie.switchbox(%[[TILE_7_6]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_1:.*]] = aie.switchbox(%[[TILE_8_1]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_9_1:.*]] = aie.switchbox(%[[TILE_9_1]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_9_2:.*]] = aie.switchbox(%[[TILE_9_2]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_9_3:.*]] = aie.switchbox(%[[TILE_9_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_9_4:.*]] = aie.switchbox(%[[TILE_9_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_10_1:.*]] = aie.switchbox(%[[TILE_10_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_2:.*]] = aie.switchbox(%[[TILE_10_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_3:.*]] = aie.switchbox(%[[TILE_10_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_4:.*]] = aie.switchbox(%[[TILE_10_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_11_1:.*]] = aie.switchbox(%[[TILE_11_1]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_11_2:.*]] = aie.switchbox(%[[TILE_11_2]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_11_3:.*]] = aie.switchbox(%[[TILE_11_3]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_11_4:.*]] = aie.switchbox(%[[TILE_11_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_12_1:.*]] = aie.switchbox(%[[TILE_12_1]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_12_2:.*]] = aie.switchbox(%[[TILE_12_2]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_12_3:.*]] = aie.switchbox(%[[TILE_12_3]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_12_4:.*]] = aie.switchbox(%[[TILE_12_4]]) { -// CHECK: } -// CHECK: %[[SWITCHBOX_12_5:.*]] = aie.switchbox(%[[TILE_12_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_13_1:.*]] = aie.switchbox(%[[TILE_13_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_13_2:.*]] = aie.switchbox(%[[TILE_13_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_13_3:.*]] = aie.switchbox(%[[TILE_13_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_13_4:.*]] = aie.switchbox(%[[TILE_13_4]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_13_5:.*]] = aie.switchbox(%[[TILE_13_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_4_5:.*]] = aie.switchbox(%[[TILE_4_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_0:.*]] = aie.switchbox(%[[TILE_10_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_10_0:.*]] = aie.shim_mux(%[[TILE_10_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_4_6:.*]] = aie.switchbox(%[[TILE_4_6]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_11_0:.*]] = aie.switchbox(%[[TILE_11_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_11_0:.*]] = aie.shim_mux(%[[TILE_11_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_12_0:.*]] = aie.tile(12, 0) -// CHECK: %[[SWITCHBOX_12_0:.*]] = aie.switchbox(%[[TILE_12_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_13_0:.*]] = aie.switchbox(%[[TILE_13_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_14_2:.*]] = aie.switchbox(%[[TILE_14_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_14_3:.*]] = aie.switchbox(%[[TILE_14_3]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_14_4:.*]] = aie.switchbox(%[[TILE_14_4]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_14_5:.*]] = aie.switchbox(%[[TILE_14_5]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_15_2:.*]] = aie.tile(15, 2) -// CHECK: %[[SWITCHBOX_15_2:.*]] = aie.switchbox(%[[TILE_15_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_16_2:.*]] = aie.tile(16, 2) -// CHECK: %[[SWITCHBOX_16_2:.*]] = aie.switchbox(%[[TILE_16_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_17_0:.*]] = aie.tile(17, 0) -// CHECK: %[[SWITCHBOX_17_0:.*]] = aie.switchbox(%[[TILE_17_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_17_1:.*]] = aie.tile(17, 1) -// CHECK: %[[SWITCHBOX_17_1:.*]] = aie.switchbox(%[[TILE_17_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_17_2:.*]] = aie.tile(17, 2) -// CHECK: %[[SWITCHBOX_17_2:.*]] = aie.switchbox(%[[TILE_17_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_18_0:.*]] = aie.switchbox(%[[TILE_18_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_18_0:.*]] = aie.shim_mux(%[[TILE_18_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) -// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) -// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) -// CHECK: aie.wire(%[[TILE_0_4]] : Core, %[[SWITCHBOX_0_4:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_4]] : DMA, %[[SWITCHBOX_0_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : North, %[[SWITCHBOX_0_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) -// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) -// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) -// CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : North, %[[SWITCHBOX_1_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_4]] : East, %[[SWITCHBOX_1_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_4]] : Core, %[[SWITCHBOX_1_4]] : Core) -// CHECK: aie.wire(%[[TILE_1_4]] : DMA, %[[SWITCHBOX_1_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : North, %[[SWITCHBOX_1_4]] : South) -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) -// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2]] : Core) -// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : East, %[[SWITCHBOX_2_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3]] : Core) -// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_1_4]] : East, %[[SWITCHBOX_2_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_4]] : Core, %[[SWITCHBOX_2_4]] : Core) -// CHECK: aie.wire(%[[TILE_2_4]] : DMA, %[[SWITCHBOX_2_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : North, %[[SWITCHBOX_2_4]] : South) -// CHECK: aie.wire(%[[TILE_2_5]] : Core, %[[SWITCHBOX_2_5:.*]] : Core) -// CHECK: aie.wire(%[[TILE_2_5]] : DMA, %[[SWITCHBOX_2_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_4]] : North, %[[SWITCHBOX_2_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) -// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) -// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) -// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : East, %[[SWITCHBOX_3_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3]] : Core) -// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_4]] : East, %[[SWITCHBOX_3_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_4]] : Core, %[[SWITCHBOX_3_4]] : Core) -// CHECK: aie.wire(%[[TILE_3_4]] : DMA, %[[SWITCHBOX_3_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : North, %[[SWITCHBOX_3_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_5]] : East, %[[SWITCHBOX_3_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_5]] : Core, %[[SWITCHBOX_3_5]] : Core) -// CHECK: aie.wire(%[[TILE_3_5]] : DMA, %[[SWITCHBOX_3_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_4]] : North, %[[SWITCHBOX_3_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) -// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) -// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) -// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : North, %[[SWITCHBOX_4_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_4]] : East, %[[SWITCHBOX_4_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_4]] : Core, %[[SWITCHBOX_4_4]] : Core) -// CHECK: aie.wire(%[[TILE_4_4]] : DMA, %[[SWITCHBOX_4_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : North, %[[SWITCHBOX_4_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_5]] : East, %[[SWITCHBOX_4_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_5]] : Core, %[[SWITCHBOX_4_5]] : Core) -// CHECK: aie.wire(%[[TILE_4_5]] : DMA, %[[SWITCHBOX_4_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_4]] : North, %[[SWITCHBOX_4_5]] : South) -// CHECK: aie.wire(%[[TILE_4_6]] : Core, %[[SWITCHBOX_4_6:.*]] : Core) -// CHECK: aie.wire(%[[TILE_4_6]] : DMA, %[[SWITCHBOX_4_6]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_5]] : North, %[[SWITCHBOX_4_6]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) -// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_0:.*]] : North, %[[SWITCHBOX_5_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) -// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) -// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_4]] : East, %[[SWITCHBOX_5_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_4]] : Core, %[[SWITCHBOX_5_4]] : Core) -// CHECK: aie.wire(%[[TILE_5_4]] : DMA, %[[SWITCHBOX_5_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : North, %[[SWITCHBOX_5_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_5]] : East, %[[SWITCHBOX_5_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_5]] : Core, %[[SWITCHBOX_5_5]] : Core) -// CHECK: aie.wire(%[[TILE_5_5]] : DMA, %[[SWITCHBOX_5_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_4]] : North, %[[SWITCHBOX_5_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_4_6]] : East, %[[SWITCHBOX_5_6:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_6]] : Core, %[[SWITCHBOX_5_6]] : Core) -// CHECK: aie.wire(%[[TILE_5_6]] : DMA, %[[SWITCHBOX_5_6]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_5]] : North, %[[SWITCHBOX_5_6]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) -// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) -// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) -// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) -// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_4]] : East, %[[SWITCHBOX_6_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_4]] : Core, %[[SWITCHBOX_6_4]] : Core) -// CHECK: aie.wire(%[[TILE_6_4]] : DMA, %[[SWITCHBOX_6_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : North, %[[SWITCHBOX_6_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_5]] : East, %[[SWITCHBOX_6_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_5]] : Core, %[[SWITCHBOX_6_5]] : Core) -// CHECK: aie.wire(%[[TILE_6_5]] : DMA, %[[SWITCHBOX_6_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_4]] : North, %[[SWITCHBOX_6_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_6]] : East, %[[SWITCHBOX_6_6:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_6]] : Core, %[[SWITCHBOX_6_6]] : Core) -// CHECK: aie.wire(%[[TILE_6_6]] : DMA, %[[SWITCHBOX_6_6]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_5]] : North, %[[SWITCHBOX_6_6]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) -// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) -// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) -// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_4]] : East, %[[SWITCHBOX_7_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_4]] : Core, %[[SWITCHBOX_7_4]] : Core) -// CHECK: aie.wire(%[[TILE_7_4]] : DMA, %[[SWITCHBOX_7_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : North, %[[SWITCHBOX_7_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_5]] : East, %[[SWITCHBOX_7_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_5]] : Core, %[[SWITCHBOX_7_5]] : Core) -// CHECK: aie.wire(%[[TILE_7_5]] : DMA, %[[SWITCHBOX_7_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : North, %[[SWITCHBOX_7_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_6]] : East, %[[SWITCHBOX_7_6:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_6]] : Core, %[[SWITCHBOX_7_6]] : Core) -// CHECK: aie.wire(%[[TILE_7_6]] : DMA, %[[SWITCHBOX_7_6]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_5]] : North, %[[SWITCHBOX_7_6]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : East, %[[SWITCHBOX_8_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_1]] : Core, %[[SWITCHBOX_8_1]] : Core) -// CHECK: aie.wire(%[[TILE_8_1]] : DMA, %[[SWITCHBOX_8_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) -// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : North, %[[SWITCHBOX_8_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) -// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : East, %[[SWITCHBOX_8_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_4]] : Core, %[[SWITCHBOX_8_4]] : Core) -// CHECK: aie.wire(%[[TILE_8_4]] : DMA, %[[SWITCHBOX_8_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : North, %[[SWITCHBOX_8_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : East, %[[SWITCHBOX_9_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_1]] : Core, %[[SWITCHBOX_9_1]] : Core) -// CHECK: aie.wire(%[[TILE_9_1]] : DMA, %[[SWITCHBOX_9_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : East, %[[SWITCHBOX_9_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_2]] : Core, %[[SWITCHBOX_9_2]] : Core) -// CHECK: aie.wire(%[[TILE_9_2]] : DMA, %[[SWITCHBOX_9_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_1]] : North, %[[SWITCHBOX_9_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : East, %[[SWITCHBOX_9_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_3]] : Core, %[[SWITCHBOX_9_3]] : Core) -// CHECK: aie.wire(%[[TILE_9_3]] : DMA, %[[SWITCHBOX_9_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : North, %[[SWITCHBOX_9_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_8_4]] : East, %[[SWITCHBOX_9_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_4]] : Core, %[[SWITCHBOX_9_4]] : Core) -// CHECK: aie.wire(%[[TILE_9_4]] : DMA, %[[SWITCHBOX_9_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_3]] : North, %[[SWITCHBOX_9_4]] : South) -// CHECK: aie.wire(%[[SHIM_MUX_10_0:.*]] : North, %[[SWITCHBOX_10_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_10_0]] : DMA, %[[SHIM_MUX_10_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_1]] : East, %[[SWITCHBOX_10_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_1]] : Core, %[[SWITCHBOX_10_1]] : Core) -// CHECK: aie.wire(%[[TILE_10_1]] : DMA, %[[SWITCHBOX_10_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : North, %[[SWITCHBOX_10_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : East, %[[SWITCHBOX_10_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_2]] : Core, %[[SWITCHBOX_10_2]] : Core) -// CHECK: aie.wire(%[[TILE_10_2]] : DMA, %[[SWITCHBOX_10_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_1]] : North, %[[SWITCHBOX_10_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_9_3]] : East, %[[SWITCHBOX_10_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_3]] : Core, %[[SWITCHBOX_10_3]] : Core) -// CHECK: aie.wire(%[[TILE_10_3]] : DMA, %[[SWITCHBOX_10_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_2]] : North, %[[SWITCHBOX_10_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_9_4]] : East, %[[SWITCHBOX_10_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_4]] : Core, %[[SWITCHBOX_10_4]] : Core) -// CHECK: aie.wire(%[[TILE_10_4]] : DMA, %[[SWITCHBOX_10_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_3]] : North, %[[SWITCHBOX_10_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : East, %[[SWITCHBOX_11_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_11_0:.*]] : North, %[[SWITCHBOX_11_0]] : South) -// CHECK: aie.wire(%[[TILE_11_0]] : DMA, %[[SHIM_MUX_11_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_1]] : East, %[[SWITCHBOX_11_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_1]] : Core, %[[SWITCHBOX_11_1]] : Core) -// CHECK: aie.wire(%[[TILE_11_1]] : DMA, %[[SWITCHBOX_11_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_0]] : North, %[[SWITCHBOX_11_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_2]] : East, %[[SWITCHBOX_11_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_2]] : Core, %[[SWITCHBOX_11_2]] : Core) -// CHECK: aie.wire(%[[TILE_11_2]] : DMA, %[[SWITCHBOX_11_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_1]] : North, %[[SWITCHBOX_11_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_3]] : East, %[[SWITCHBOX_11_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_3]] : Core, %[[SWITCHBOX_11_3]] : Core) -// CHECK: aie.wire(%[[TILE_11_3]] : DMA, %[[SWITCHBOX_11_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_2]] : North, %[[SWITCHBOX_11_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_4]] : East, %[[SWITCHBOX_11_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_4]] : Core, %[[SWITCHBOX_11_4]] : Core) -// CHECK: aie.wire(%[[TILE_11_4]] : DMA, %[[SWITCHBOX_11_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_3]] : North, %[[SWITCHBOX_11_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_11_0]] : East, %[[SWITCHBOX_12_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_11_1]] : East, %[[SWITCHBOX_12_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_12_1]] : Core, %[[SWITCHBOX_12_1]] : Core) -// CHECK: aie.wire(%[[TILE_12_1]] : DMA, %[[SWITCHBOX_12_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_12_0]] : North, %[[SWITCHBOX_12_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_11_2]] : East, %[[SWITCHBOX_12_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_12_2]] : Core, %[[SWITCHBOX_12_2]] : Core) -// CHECK: aie.wire(%[[TILE_12_2]] : DMA, %[[SWITCHBOX_12_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_12_1]] : North, %[[SWITCHBOX_12_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_11_3]] : East, %[[SWITCHBOX_12_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_12_3]] : Core, %[[SWITCHBOX_12_3]] : Core) -// CHECK: aie.wire(%[[TILE_12_3]] : DMA, %[[SWITCHBOX_12_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_12_2]] : North, %[[SWITCHBOX_12_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_11_4]] : East, %[[SWITCHBOX_12_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_12_4]] : Core, %[[SWITCHBOX_12_4]] : Core) -// CHECK: aie.wire(%[[TILE_12_4]] : DMA, %[[SWITCHBOX_12_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_12_3]] : North, %[[SWITCHBOX_12_4]] : South) -// CHECK: aie.wire(%[[TILE_12_5]] : Core, %[[SWITCHBOX_12_5:.*]] : Core) -// CHECK: aie.wire(%[[TILE_12_5]] : DMA, %[[SWITCHBOX_12_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_12_4]] : North, %[[SWITCHBOX_12_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_12_0]] : East, %[[SWITCHBOX_13_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_12_1]] : East, %[[SWITCHBOX_13_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_13_1]] : Core, %[[SWITCHBOX_13_1]] : Core) -// CHECK: aie.wire(%[[TILE_13_1]] : DMA, %[[SWITCHBOX_13_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_13_0]] : North, %[[SWITCHBOX_13_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_12_2]] : East, %[[SWITCHBOX_13_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_13_2]] : Core, %[[SWITCHBOX_13_2]] : Core) -// CHECK: aie.wire(%[[TILE_13_2]] : DMA, %[[SWITCHBOX_13_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_13_1]] : North, %[[SWITCHBOX_13_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_12_3]] : East, %[[SWITCHBOX_13_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_13_3]] : Core, %[[SWITCHBOX_13_3]] : Core) -// CHECK: aie.wire(%[[TILE_13_3]] : DMA, %[[SWITCHBOX_13_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_13_2]] : North, %[[SWITCHBOX_13_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_12_4]] : East, %[[SWITCHBOX_13_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_13_4]] : Core, %[[SWITCHBOX_13_4]] : Core) -// CHECK: aie.wire(%[[TILE_13_4]] : DMA, %[[SWITCHBOX_13_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_13_3]] : North, %[[SWITCHBOX_13_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_12_5]] : East, %[[SWITCHBOX_13_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_13_5]] : Core, %[[SWITCHBOX_13_5]] : Core) -// CHECK: aie.wire(%[[TILE_13_5]] : DMA, %[[SWITCHBOX_13_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_13_4]] : North, %[[SWITCHBOX_13_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_13_2]] : East, %[[SWITCHBOX_14_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_14_2]] : Core, %[[SWITCHBOX_14_2]] : Core) -// CHECK: aie.wire(%[[TILE_14_2]] : DMA, %[[SWITCHBOX_14_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_13_3]] : East, %[[SWITCHBOX_14_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_14_3]] : Core, %[[SWITCHBOX_14_3]] : Core) -// CHECK: aie.wire(%[[TILE_14_3]] : DMA, %[[SWITCHBOX_14_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_14_2]] : North, %[[SWITCHBOX_14_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_13_4]] : East, %[[SWITCHBOX_14_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_14_4]] : Core, %[[SWITCHBOX_14_4]] : Core) -// CHECK: aie.wire(%[[TILE_14_4]] : DMA, %[[SWITCHBOX_14_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_14_3]] : North, %[[SWITCHBOX_14_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_13_5]] : East, %[[SWITCHBOX_14_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_14_5]] : Core, %[[SWITCHBOX_14_5]] : Core) -// CHECK: aie.wire(%[[TILE_14_5]] : DMA, %[[SWITCHBOX_14_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_14_4]] : North, %[[SWITCHBOX_14_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_14_2]] : East, %[[SWITCHBOX_15_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_15_2]] : Core, %[[SWITCHBOX_15_2]] : Core) -// CHECK: aie.wire(%[[TILE_15_2]] : DMA, %[[SWITCHBOX_15_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_15_2]] : East, %[[SWITCHBOX_16_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_16_2]] : Core, %[[SWITCHBOX_16_2]] : Core) -// CHECK: aie.wire(%[[TILE_16_2]] : DMA, %[[SWITCHBOX_16_2]] : DMA) -// CHECK: aie.wire(%[[TILE_17_1]] : Core, %[[SWITCHBOX_17_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_17_1]] : DMA, %[[SWITCHBOX_17_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_17_0:.*]] : North, %[[SWITCHBOX_17_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_16_2]] : East, %[[SWITCHBOX_17_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_17_2]] : Core, %[[SWITCHBOX_17_2]] : Core) -// CHECK: aie.wire(%[[TILE_17_2]] : DMA, %[[SWITCHBOX_17_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_17_1]] : North, %[[SWITCHBOX_17_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_17_0]] : East, %[[SWITCHBOX_18_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_18_0:.*]] : North, %[[SWITCHBOX_18_0]] : South) -// CHECK: aie.wire(%[[TILE_18_0]] : DMA, %[[SHIM_MUX_18_0]] : DMA) -// CHECK: } - -module { - aie.device(xcvc1902) { - %tile_0_0 = aie.tile(0, 0) - %tile_1_0 = aie.tile(1, 0) - %tile_2_0 = aie.tile(2, 0) - %tile_3_0 = aie.tile(3, 0) - %tile_4_0 = aie.tile(4, 0) - %tile_5_0 = aie.tile(5, 0) - %tile_6_0 = aie.tile(6, 0) - %tile_7_0 = aie.tile(7, 0) - %tile_8_0 = aie.tile(8, 0) - %tile_9_0 = aie.tile(9, 0) - %tile_10_0 = aie.tile(10, 0) - %tile_11_0 = aie.tile(11, 0) - %tile_18_0 = aie.tile(18, 0) - %tile_19_0 = aie.tile(19, 0) - %tile_0_1 = aie.tile(0, 1) - %tile_0_2 = aie.tile(0, 2) - %tile_0_3 = aie.tile(0, 3) - %tile_0_4 = aie.tile(0, 4) - %tile_0_5 = aie.tile(0, 5) - %tile_0_6 = aie.tile(0, 6) - %tile_0_7 = aie.tile(0, 7) - %tile_0_8 = aie.tile(0, 8) - %tile_1_1 = aie.tile(1, 1) - %tile_1_2 = aie.tile(1, 2) - %tile_1_3 = aie.tile(1, 3) - %tile_1_4 = aie.tile(1, 4) - %tile_1_5 = aie.tile(1, 5) - %tile_1_6 = aie.tile(1, 6) - %tile_1_7 = aie.tile(1, 7) - %tile_1_8 = aie.tile(1, 8) - %tile_2_1 = aie.tile(2, 1) - %tile_2_2 = aie.tile(2, 2) - %tile_2_3 = aie.tile(2, 3) - %tile_2_4 = aie.tile(2, 4) - %tile_2_5 = aie.tile(2, 5) - %tile_2_6 = aie.tile(2, 6) - %tile_2_7 = aie.tile(2, 7) - %tile_2_8 = aie.tile(2, 8) - %tile_3_1 = aie.tile(3, 1) - %tile_3_2 = aie.tile(3, 2) - %tile_3_3 = aie.tile(3, 3) - %tile_3_4 = aie.tile(3, 4) - %tile_3_5 = aie.tile(3, 5) - %tile_3_6 = aie.tile(3, 6) - %tile_3_7 = aie.tile(3, 7) - %tile_3_8 = aie.tile(3, 8) - %tile_4_1 = aie.tile(4, 1) - %tile_4_2 = aie.tile(4, 2) - %tile_4_3 = aie.tile(4, 3) - %tile_4_4 = aie.tile(4, 4) - %tile_4_5 = aie.tile(4, 5) - %tile_4_6 = aie.tile(4, 6) - %tile_4_7 = aie.tile(4, 7) - %tile_4_8 = aie.tile(4, 8) - %tile_5_1 = aie.tile(5, 1) - %tile_5_2 = aie.tile(5, 2) - %tile_5_3 = aie.tile(5, 3) - %tile_5_4 = aie.tile(5, 4) - %tile_5_5 = aie.tile(5, 5) - %tile_5_6 = aie.tile(5, 6) - %tile_5_7 = aie.tile(5, 7) - %tile_5_8 = aie.tile(5, 8) - %tile_6_1 = aie.tile(6, 1) - %tile_6_2 = aie.tile(6, 2) - %tile_6_3 = aie.tile(6, 3) - %tile_6_4 = aie.tile(6, 4) - %tile_6_5 = aie.tile(6, 5) - %tile_6_6 = aie.tile(6, 6) - %tile_6_7 = aie.tile(6, 7) - %tile_6_8 = aie.tile(6, 8) - %tile_7_1 = aie.tile(7, 1) - %tile_7_2 = aie.tile(7, 2) - %tile_7_3 = aie.tile(7, 3) - %tile_7_4 = aie.tile(7, 4) - %tile_7_5 = aie.tile(7, 5) - %tile_7_6 = aie.tile(7, 6) - %tile_7_7 = aie.tile(7, 7) - %tile_7_8 = aie.tile(7, 8) - %tile_8_1 = aie.tile(8, 1) - %tile_8_2 = aie.tile(8, 2) - %tile_8_3 = aie.tile(8, 3) - %tile_8_4 = aie.tile(8, 4) - %tile_8_5 = aie.tile(8, 5) - %tile_8_6 = aie.tile(8, 6) - %tile_8_7 = aie.tile(8, 7) - %tile_8_8 = aie.tile(8, 8) - %tile_9_1 = aie.tile(9, 1) - %tile_9_2 = aie.tile(9, 2) - %tile_9_3 = aie.tile(9, 3) - %tile_9_4 = aie.tile(9, 4) - %tile_9_5 = aie.tile(9, 5) - %tile_9_6 = aie.tile(9, 6) - %tile_9_7 = aie.tile(9, 7) - %tile_9_8 = aie.tile(9, 8) - %tile_10_1 = aie.tile(10, 1) - %tile_10_2 = aie.tile(10, 2) - %tile_10_3 = aie.tile(10, 3) - %tile_10_4 = aie.tile(10, 4) - %tile_10_5 = aie.tile(10, 5) - %tile_10_6 = aie.tile(10, 6) - %tile_10_7 = aie.tile(10, 7) - %tile_10_8 = aie.tile(10, 8) - %tile_11_1 = aie.tile(11, 1) - %tile_11_2 = aie.tile(11, 2) - %tile_11_3 = aie.tile(11, 3) - %tile_11_4 = aie.tile(11, 4) - %tile_11_5 = aie.tile(11, 5) - %tile_11_6 = aie.tile(11, 6) - %tile_11_7 = aie.tile(11, 7) - %tile_11_8 = aie.tile(11, 8) - %tile_12_1 = aie.tile(12, 1) - %tile_12_2 = aie.tile(12, 2) - %tile_12_3 = aie.tile(12, 3) - %tile_12_4 = aie.tile(12, 4) - %tile_12_5 = aie.tile(12, 5) - %tile_12_6 = aie.tile(12, 6) - %tile_12_7 = aie.tile(12, 7) - %tile_12_8 = aie.tile(12, 8) - %tile_13_0 = aie.tile(13, 0) - %tile_13_1 = aie.tile(13, 1) - %tile_13_2 = aie.tile(13, 2) - %tile_13_3 = aie.tile(13, 3) - %tile_13_4 = aie.tile(13, 4) - %tile_13_5 = aie.tile(13, 5) - %tile_13_6 = aie.tile(13, 6) - %tile_13_7 = aie.tile(13, 7) - %tile_13_8 = aie.tile(13, 8) - %tile_14_1 = aie.tile(14, 1) - %tile_14_2 = aie.tile(14, 2) - %tile_14_3 = aie.tile(14, 3) - %tile_14_4 = aie.tile(14, 4) - %tile_14_5 = aie.tile(14, 5) - %tile_14_6 = aie.tile(14, 6) - %tile_14_7 = aie.tile(14, 7) - %tile_14_8 = aie.tile(14, 8) - %switchbox_0_1 = aie.switchbox(%tile_0_1) { - } - %switchbox_0_2 = aie.switchbox(%tile_0_2) { - } - %switchbox_0_3 = aie.switchbox(%tile_0_3) { - } - %switchbox_0_4 = aie.switchbox(%tile_0_4) { - } - %switchbox_1_1 = aie.switchbox(%tile_1_1) { - } - %switchbox_1_2 = aie.switchbox(%tile_1_2) { - } - %switchbox_1_3 = aie.switchbox(%tile_1_3) { - } - %switchbox_1_4 = aie.switchbox(%tile_1_4) { - } - %switchbox_2_1 = aie.switchbox(%tile_2_1) { - } - %switchbox_2_2 = aie.switchbox(%tile_2_2) { - } - %switchbox_2_3 = aie.switchbox(%tile_2_3) { - } - %switchbox_2_4 = aie.switchbox(%tile_2_4) { - aie.connect - } - %switchbox_2_5 = aie.switchbox(%tile_2_5) { - aie.connect - aie.connect - } - %switchbox_3_1 = aie.switchbox(%tile_3_1) { - aie.connect - aie.connect - } - %switchbox_3_2 = aie.switchbox(%tile_3_2) { - aie.connect - } - %switchbox_3_3 = aie.switchbox(%tile_3_3) { - aie.connect - } - %switchbox_3_4 = aie.switchbox(%tile_3_4) { - aie.connect - } - %switchbox_3_5 = aie.switchbox(%tile_3_5) { - aie.connect - } - %switchbox_4_1 = aie.switchbox(%tile_4_1) { - } - %switchbox_4_2 = aie.switchbox(%tile_4_2) { - } - %switchbox_4_3 = aie.switchbox(%tile_4_3) { - } - %switchbox_4_4 = aie.switchbox(%tile_4_4) { - } - %switchbox_5_1 = aie.switchbox(%tile_5_1) { - } - %switchbox_5_2 = aie.switchbox(%tile_5_2) { - } - %switchbox_5_3 = aie.switchbox(%tile_5_3) { - } - %switchbox_5_4 = aie.switchbox(%tile_5_4) { - } - %switchbox_5_5 = aie.switchbox(%tile_5_5) { - } - %switchbox_5_6 = aie.switchbox(%tile_5_6) { - aie.connect - } - %switchbox_6_1 = aie.switchbox(%tile_6_1) { - } - %switchbox_6_2 = aie.switchbox(%tile_6_2) { - } - %switchbox_6_3 = aie.switchbox(%tile_6_3) { - } - %switchbox_6_4 = aie.switchbox(%tile_6_4) { - } - %switchbox_6_5 = aie.switchbox(%tile_6_5) { - } - %switchbox_6_6 = aie.switchbox(%tile_6_6) { - aie.connect - aie.connect - } - %switchbox_7_1 = aie.switchbox(%tile_7_1) { - } - %switchbox_7_2 = aie.switchbox(%tile_7_2) { - } - %switchbox_7_3 = aie.switchbox(%tile_7_3) { - aie.connect - aie.connect - } - %switchbox_7_4 = aie.switchbox(%tile_7_4) { - aie.connect - } - %switchbox_7_5 = aie.switchbox(%tile_7_5) { - aie.connect - } - %switchbox_7_6 = aie.switchbox(%tile_7_6) { - aie.connect - } - %switchbox_8_1 = aie.switchbox(%tile_8_1) { - } - %switchbox_8_2 = aie.switchbox(%tile_8_2) { - } - %switchbox_8_3 = aie.switchbox(%tile_8_3) { - aie.connect - } - %switchbox_8_4 = aie.switchbox(%tile_8_4) { - } - %switchbox_9_1 = aie.switchbox(%tile_9_1) { - } - %switchbox_9_2 = aie.switchbox(%tile_9_2) { - } - %switchbox_9_3 = aie.switchbox(%tile_9_3) { - } - %switchbox_9_4 = aie.switchbox(%tile_9_4) { - } - %switchbox_10_1 = aie.switchbox(%tile_10_1) { - } - %switchbox_10_2 = aie.switchbox(%tile_10_2) { - } - %switchbox_10_3 = aie.switchbox(%tile_10_3) { - } - %switchbox_10_4 = aie.switchbox(%tile_10_4) { - } - %switchbox_11_1 = aie.switchbox(%tile_11_1) { - } - %switchbox_11_2 = aie.switchbox(%tile_11_2) { - } - %switchbox_11_3 = aie.switchbox(%tile_11_3) { - } - %switchbox_11_4 = aie.switchbox(%tile_11_4) { - } - %switchbox_12_1 = aie.switchbox(%tile_12_1) { - } - %switchbox_12_2 = aie.switchbox(%tile_12_2) { - } - %switchbox_12_3 = aie.switchbox(%tile_12_3) { - } - %switchbox_12_4 = aie.switchbox(%tile_12_4) { - } - %switchbox_12_5 = aie.switchbox(%tile_12_5) { - aie.connect - aie.connect - } - %switchbox_13_1 = aie.switchbox(%tile_13_1) { - aie.connect - } - %switchbox_13_2 = aie.switchbox(%tile_13_2) { - aie.connect - } - %switchbox_13_3 = aie.switchbox(%tile_13_3) { - aie.connect - aie.connect - } - %switchbox_13_4 = aie.switchbox(%tile_13_4) { - aie.connect - } - %switchbox_13_5 = aie.switchbox(%tile_13_5) { - aie.connect - aie.connect - } - aie.flow(%tile_3_0, DMA : 0, %tile_3_0, North : 0) - aie.flow(%tile_4_5, West : 0, %tile_6_0, DMA : 0) - aie.flow(%tile_10_0, DMA : 0, %tile_9_3, West : 0) - aie.flow(%tile_4_6, East : 0, %tile_2_0, DMA : 0) - aie.flow(%tile_11_0, DMA : 0, %tile_13_0, North : 0) - aie.flow(%tile_14_5, West : 0, %tile_18_0, DMA : 0) - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple.mlir deleted file mode 100644 index e5e1fdfaa..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple.mlir +++ /dev/null @@ -1,44 +0,0 @@ - -// RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) -// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) -// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) -// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.packet_flow(16) { -// CHECK: aie.packet_source<%[[TILE_0_1]], Core : 0> -// CHECK: aie.packet_dest<%[[TILE_1_2]], Core : 0> -// CHECK: aie.packet_dest<%[[TILE_0_2]], DMA : 1> -// CHECK: } -// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) -// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) -// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) -// CHECK: } - -module { - aie.device(xcvc1902) { - %01 = aie.tile(0, 1) - %12 = aie.tile(1, 2) - %02 = aie.tile(0, 2) - aie.flow(%01, DMA : 0, %12, Core : 1) - aie.packet_flow(0x10) { - aie.packet_source < %01, Core : 0> - aie.packet_dest < %12, Core : 0> - aie.packet_dest < %02, DMA : 1> - } - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple2.mlir index e29007154..da12a3e85 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple2.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) @@ -9,7 +9,7 @@ // CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { // CHECK: aie.connect @@ -25,9 +25,9 @@ // CHECK: } module { - aie.device(xcvc1902) { + aie.device(npu1_4col) { %0 = aie.tile(2, 3) %1 = aie.tile(3, 2) - aie.flow(%0, Core : 1, %1, DMA : 0) + aie.flow(%0, Core : 0, %1, DMA : 0) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows.mlir index 13a8541e2..cb4550ab6 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows.mlir @@ -1,17 +1,17 @@ // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) // CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) // CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } // CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) // CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) @@ -21,11 +21,11 @@ // CHECK: } module { - aie.device(xcvc1902) { + aie.device(npu1_4col) { %t23 = aie.tile(2, 3) %t22 = aie.tile(2, 2) - aie.flow(%t23, Core : 0, %t22, Core : 1) - aie.flow(%t22, Core : 0, %t22, Core : 0) - aie.flow(%t22, Core : 1, %t23, Core : 1) + aie.flow(%t23, DMA : 0, %t22, DMA : 1) + aie.flow(%t22, DMA : 0, %t22, DMA : 0) + aie.flow(%t22, DMA : 1, %t23, DMA : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows2.mlir index b25fc9439..0443eb296 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows2.mlir @@ -1,43 +1,43 @@ // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) -// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) -// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { +// CHECK: aie.connect +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { +// CHECK: aie.connect // CHECK: } -// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) -// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK: aie.connect +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { +// CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) -// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) -// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2]] : Core) // CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) -// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) +// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) // CHECK: } module { - aie.device(xcvc1902) { - %t23 = aie.tile(2, 3) - %t22 = aie.tile(2, 2) - %t11 = aie.tile(1, 1) - aie.flow(%t23, Core : 0, %t22, Core : 1) - aie.flow(%t22, Core : 0, %t11, Core : 0) + aie.device(npu1_4col) { + %t11 = aie.tile(1, 2) + %t32 = aie.tile(3, 2) + %t33 = aie.tile(3, 3) + aie.flow(%t33, DMA : 0, %t32, DMA : 1) + aie.flow(%t32, DMA : 0, %t11, DMA : 0) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows_shim.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows_shim.mlir index 2daad27b7..165cf242a 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows_shim.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows_shim.mlir @@ -1,85 +1,52 @@ // RUN: iree-opt --split-input-file --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) -// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_0:.*]] : North, %[[SWITCHBOX_2_1]] : South) -// CHECK: } - -module { - aie.device(xcvc1902) { - %t23 = aie.tile(2, 1) - %t22 = aie.tile(2, 0) - aie.flow(%t23, North : 0, %t22, PLIO : 0) - } -} - -// ----- - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) -// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) // CHECK: } module { - aie.device(xcvc1902) { - %t20 = aie.tile(2, 0) - %t21 = aie.tile(2, 1) - aie.flow(%t21, Core : 0, %t20, DMA : 1) + aie.device(npu1_4col) { + %t22 = aie.tile(2, 2) + %t23 = aie.tile(2, 3) + aie.flow(%t23, Core : 0, %t22, DMA : 1) } } // ----- -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) -// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK: aie.connect +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { +// CHECK: aie.connect // CHECK: } -// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK: aie.connect +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { +// CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) -// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) // CHECK: } module { - aie.device(xcvc1902) { - %t20 = aie.tile(2, 0) - %t30 = aie.tile(3, 0) - aie.flow(%t20, DMA : 0, %t30, DMA : 1) + aie.device(npu1_4col) { + %t22 = aie.tile(2, 2) + %t32 = aie.tile(3, 2) + aie.flow(%t22, DMA : 0, %t32, DMA : 1) } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_vecmul_4x4.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_vecmul_4x4.mlir deleted file mode 100644 index 43fc956f8..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_vecmul_4x4.mlir +++ /dev/null @@ -1,3855 +0,0 @@ - -// RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s - -// CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[TILE_47_2:.*]] = aie.tile(47, 2) -// CHECK: %[[TILE_47_1:.*]] = aie.tile(47, 1) -// CHECK: %[[TILE_47_0:.*]] = aie.tile(47, 0) -// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[TILE_10_5:.*]] = aie.tile(10, 5) -// CHECK: %[[LOCK_10_5:.*]] = aie.lock(%[[TILE_10_5]], 2) -// CHECK: %[[BUF47:.*]] = aie.buffer(%[[TILE_10_5]]) {sym_name = "buf47"} : memref<64xi32, 2> -// CHECK: %[[LOCK_10_5_0:.*]] = aie.lock(%[[TILE_10_5]], 1) -// CHECK: %[[BUF46:.*]] = aie.buffer(%[[TILE_10_5]]) {sym_name = "buf46"} : memref<64xi32, 2> -// CHECK: %[[LOCK_10_5_1:.*]] = aie.lock(%[[TILE_10_5]], 0) -// CHECK: %[[BUF45:.*]] = aie.buffer(%[[TILE_10_5]]) {sym_name = "buf45"} : memref<64xi32, 2> -// CHECK: %[[MEM_10_5:.*]] = aie.mem(%[[TILE_10_5]]) { -// CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_10_5_1]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF45]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_10_5_1]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_10_5_0]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF46]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_10_5_0]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_2:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_10_5]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF47]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_10_5]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_10_5:.*]] = aie.core(%[[TILE_10_5]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_10_5_1]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_10_5_0]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_10_5]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_3:.*]] = affine.load %[[BUF45]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_4:.*]] = affine.load %[[BUF46]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_5:.*]] = arith.muli %[[VAL_3]], %[[VAL_4]] : i32 -// CHECK: affine.store %[[VAL_5]], %[[BUF47]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_10_5]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_10_5_0]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_10_5_1]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_46_2:.*]] = aie.tile(46, 2) -// CHECK: %[[TILE_46_1:.*]] = aie.tile(46, 1) -// CHECK: %[[TILE_46_0:.*]] = aie.tile(46, 0) -// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) -// CHECK: %[[TILE_9_5:.*]] = aie.tile(9, 5) -// CHECK: %[[LOCK_9_5:.*]] = aie.lock(%[[TILE_9_5]], 2) -// CHECK: %[[BUF44:.*]] = aie.buffer(%[[TILE_9_5]]) {sym_name = "buf44"} : memref<64xi32, 2> -// CHECK: %[[LOCK_9_5_2:.*]] = aie.lock(%[[TILE_9_5]], 1) -// CHECK: %[[BUF43:.*]] = aie.buffer(%[[TILE_9_5]]) {sym_name = "buf43"} : memref<64xi32, 2> -// CHECK: %[[LOCK_9_5_3:.*]] = aie.lock(%[[TILE_9_5]], 0) -// CHECK: %[[BUF42:.*]] = aie.buffer(%[[TILE_9_5]]) {sym_name = "buf42"} : memref<64xi32, 2> -// CHECK: %[[MEM_9_5:.*]] = aie.mem(%[[TILE_9_5]]) { -// CHECK: %[[VAL_6:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_9_5_3]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF42]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_9_5_3]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_7:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_9_5_2]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF43]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_9_5_2]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_8:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_9_5]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF44]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_9_5]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_9_5:.*]] = aie.core(%[[TILE_9_5]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_9_5_3]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_9_5_2]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_9_5]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_9:.*]] = affine.load %[[BUF42]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_10:.*]] = affine.load %[[BUF43]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_11:.*]] = arith.muli %[[VAL_9]], %[[VAL_10]] : i32 -// CHECK: affine.store %[[VAL_11]], %[[BUF44]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_9_5]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_9_5_2]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_9_5_3]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_43_2:.*]] = aie.tile(43, 2) -// CHECK: %[[TILE_43_1:.*]] = aie.tile(43, 1) -// CHECK: %[[TILE_43_0:.*]] = aie.tile(43, 0) -// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) -// CHECK: %[[TILE_8_5:.*]] = aie.tile(8, 5) -// CHECK: %[[LOCK_8_5:.*]] = aie.lock(%[[TILE_8_5]], 2) -// CHECK: %[[BUF41:.*]] = aie.buffer(%[[TILE_8_5]]) {sym_name = "buf41"} : memref<64xi32, 2> -// CHECK: %[[LOCK_8_5_4:.*]] = aie.lock(%[[TILE_8_5]], 1) -// CHECK: %[[BUF40:.*]] = aie.buffer(%[[TILE_8_5]]) {sym_name = "buf40"} : memref<64xi32, 2> -// CHECK: %[[LOCK_8_5_5:.*]] = aie.lock(%[[TILE_8_5]], 0) -// CHECK: %[[BUF39:.*]] = aie.buffer(%[[TILE_8_5]]) {sym_name = "buf39"} : memref<64xi32, 2> -// CHECK: %[[MEM_8_5:.*]] = aie.mem(%[[TILE_8_5]]) { -// CHECK: %[[VAL_12:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_8_5_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF39]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_8_5_5]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_13:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_8_5_4]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF40]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_8_5_4]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_14:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_8_5]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF41]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_8_5]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_8_5:.*]] = aie.core(%[[TILE_8_5]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_8_5_5]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_8_5_4]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_8_5]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_15:.*]] = affine.load %[[BUF39]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_16:.*]] = affine.load %[[BUF40]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_17:.*]] = arith.muli %[[VAL_15]], %[[VAL_16]] : i32 -// CHECK: affine.store %[[VAL_17]], %[[BUF41]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_8_5]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_8_5_4]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_8_5_5]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_42_2:.*]] = aie.tile(42, 2) -// CHECK: %[[TILE_42_1:.*]] = aie.tile(42, 1) -// CHECK: %[[TILE_42_0:.*]] = aie.tile(42, 0) -// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) -// CHECK: %[[TILE_7_5:.*]] = aie.tile(7, 5) -// CHECK: %[[LOCK_7_5:.*]] = aie.lock(%[[TILE_7_5]], 2) -// CHECK: %[[BUF38:.*]] = aie.buffer(%[[TILE_7_5]]) {sym_name = "buf38"} : memref<64xi32, 2> -// CHECK: %[[LOCK_7_5_6:.*]] = aie.lock(%[[TILE_7_5]], 1) -// CHECK: %[[BUF37:.*]] = aie.buffer(%[[TILE_7_5]]) {sym_name = "buf37"} : memref<64xi32, 2> -// CHECK: %[[LOCK_7_5_7:.*]] = aie.lock(%[[TILE_7_5]], 0) -// CHECK: %[[BUF36:.*]] = aie.buffer(%[[TILE_7_5]]) {sym_name = "buf36"} : memref<64xi32, 2> -// CHECK: %[[MEM_7_5:.*]] = aie.mem(%[[TILE_7_5]]) { -// CHECK: %[[VAL_18:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_7_5_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF36]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_7_5_7]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_19:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_7_5_6]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF37]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_7_5_6]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_20:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_7_5]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF38]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_7_5]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_7_5:.*]] = aie.core(%[[TILE_7_5]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_7_5_7]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_7_5_6]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_7_5]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_21:.*]] = affine.load %[[BUF36]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_22:.*]] = affine.load %[[BUF37]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_23:.*]] = arith.muli %[[VAL_21]], %[[VAL_22]] : i32 -// CHECK: affine.store %[[VAL_23]], %[[BUF38]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_7_5]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_7_5_6]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_7_5_7]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_35_2:.*]] = aie.tile(35, 2) -// CHECK: %[[TILE_35_1:.*]] = aie.tile(35, 1) -// CHECK: %[[TILE_35_0:.*]] = aie.tile(35, 0) -// CHECK: %[[TILE_10_4:.*]] = aie.tile(10, 4) -// CHECK: %[[LOCK_10_4:.*]] = aie.lock(%[[TILE_10_4]], 2) -// CHECK: %[[BUF35:.*]] = aie.buffer(%[[TILE_10_4]]) {sym_name = "buf35"} : memref<64xi32, 2> -// CHECK: %[[LOCK_10_4_8:.*]] = aie.lock(%[[TILE_10_4]], 1) -// CHECK: %[[BUF34:.*]] = aie.buffer(%[[TILE_10_4]]) {sym_name = "buf34"} : memref<64xi32, 2> -// CHECK: %[[LOCK_10_4_9:.*]] = aie.lock(%[[TILE_10_4]], 0) -// CHECK: %[[BUF33:.*]] = aie.buffer(%[[TILE_10_4]]) {sym_name = "buf33"} : memref<64xi32, 2> -// CHECK: %[[MEM_10_4:.*]] = aie.mem(%[[TILE_10_4]]) { -// CHECK: %[[VAL_24:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_10_4_9]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF33]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_10_4_9]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_25:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_10_4_8]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF34]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_10_4_8]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_26:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_10_4]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF35]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_10_4]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_10_4:.*]] = aie.core(%[[TILE_10_4]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_10_4_9]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_10_4_8]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_10_4]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_27:.*]] = affine.load %[[BUF33]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_28:.*]] = affine.load %[[BUF34]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_29:.*]] = arith.muli %[[VAL_27]], %[[VAL_28]] : i32 -// CHECK: affine.store %[[VAL_29]], %[[BUF35]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_10_4]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_10_4_8]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_10_4_9]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_34_2:.*]] = aie.tile(34, 2) -// CHECK: %[[TILE_34_1:.*]] = aie.tile(34, 1) -// CHECK: %[[TILE_34_0:.*]] = aie.tile(34, 0) -// CHECK: %[[TILE_9_4:.*]] = aie.tile(9, 4) -// CHECK: %[[LOCK_9_4:.*]] = aie.lock(%[[TILE_9_4]], 2) -// CHECK: %[[BUF32:.*]] = aie.buffer(%[[TILE_9_4]]) {sym_name = "buf32"} : memref<64xi32, 2> -// CHECK: %[[LOCK_9_4_10:.*]] = aie.lock(%[[TILE_9_4]], 1) -// CHECK: %[[BUF31:.*]] = aie.buffer(%[[TILE_9_4]]) {sym_name = "buf31"} : memref<64xi32, 2> -// CHECK: %[[LOCK_9_4_11:.*]] = aie.lock(%[[TILE_9_4]], 0) -// CHECK: %[[BUF30:.*]] = aie.buffer(%[[TILE_9_4]]) {sym_name = "buf30"} : memref<64xi32, 2> -// CHECK: %[[MEM_9_4:.*]] = aie.mem(%[[TILE_9_4]]) { -// CHECK: %[[VAL_30:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_9_4_11]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF30]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_9_4_11]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_31:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_9_4_10]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF31]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_9_4_10]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_32:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_9_4]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF32]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_9_4]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_9_4:.*]] = aie.core(%[[TILE_9_4]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_9_4_11]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_9_4_10]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_9_4]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_33:.*]] = affine.load %[[BUF30]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_34:.*]] = affine.load %[[BUF31]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_35:.*]] = arith.muli %[[VAL_33]], %[[VAL_34]] : i32 -// CHECK: affine.store %[[VAL_35]], %[[BUF32]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_9_4]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_9_4_10]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_9_4_11]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_27_2:.*]] = aie.tile(27, 2) -// CHECK: %[[TILE_27_1:.*]] = aie.tile(27, 1) -// CHECK: %[[TILE_27_0:.*]] = aie.tile(27, 0) -// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) -// CHECK: %[[TILE_8_4:.*]] = aie.tile(8, 4) -// CHECK: %[[LOCK_8_4:.*]] = aie.lock(%[[TILE_8_4]], 2) -// CHECK: %[[BUF29:.*]] = aie.buffer(%[[TILE_8_4]]) {sym_name = "buf29"} : memref<64xi32, 2> -// CHECK: %[[LOCK_8_4_12:.*]] = aie.lock(%[[TILE_8_4]], 1) -// CHECK: %[[BUF28:.*]] = aie.buffer(%[[TILE_8_4]]) {sym_name = "buf28"} : memref<64xi32, 2> -// CHECK: %[[LOCK_8_4_13:.*]] = aie.lock(%[[TILE_8_4]], 0) -// CHECK: %[[BUF27:.*]] = aie.buffer(%[[TILE_8_4]]) {sym_name = "buf27"} : memref<64xi32, 2> -// CHECK: %[[MEM_8_4:.*]] = aie.mem(%[[TILE_8_4]]) { -// CHECK: %[[VAL_36:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_8_4_13]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF27]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_8_4_13]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_37:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_8_4_12]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF28]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_8_4_12]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_38:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_8_4]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF29]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_8_4]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_8_4:.*]] = aie.core(%[[TILE_8_4]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_8_4_13]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_8_4_12]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_8_4]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_39:.*]] = affine.load %[[BUF27]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_40:.*]] = affine.load %[[BUF28]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_41:.*]] = arith.muli %[[VAL_39]], %[[VAL_40]] : i32 -// CHECK: affine.store %[[VAL_41]], %[[BUF29]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_8_4]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_8_4_12]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_8_4_13]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_26_2:.*]] = aie.tile(26, 2) -// CHECK: %[[TILE_26_1:.*]] = aie.tile(26, 1) -// CHECK: %[[TILE_26_0:.*]] = aie.tile(26, 0) -// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) -// CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) -// CHECK: %[[LOCK_7_4:.*]] = aie.lock(%[[TILE_7_4]], 2) -// CHECK: %[[BUF26:.*]] = aie.buffer(%[[TILE_7_4]]) {sym_name = "buf26"} : memref<64xi32, 2> -// CHECK: %[[LOCK_7_4_14:.*]] = aie.lock(%[[TILE_7_4]], 1) -// CHECK: %[[BUF25:.*]] = aie.buffer(%[[TILE_7_4]]) {sym_name = "buf25"} : memref<64xi32, 2> -// CHECK: %[[LOCK_7_4_15:.*]] = aie.lock(%[[TILE_7_4]], 0) -// CHECK: %[[BUF24:.*]] = aie.buffer(%[[TILE_7_4]]) {sym_name = "buf24"} : memref<64xi32, 2> -// CHECK: %[[MEM_7_4:.*]] = aie.mem(%[[TILE_7_4]]) { -// CHECK: %[[VAL_42:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_7_4_15]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF24]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_7_4_15]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_43:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_7_4_14]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF25]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_7_4_14]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_44:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_7_4]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF26]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_7_4]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_7_4:.*]] = aie.core(%[[TILE_7_4]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_7_4_15]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_7_4_14]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_7_4]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_45:.*]] = affine.load %[[BUF24]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_46:.*]] = affine.load %[[BUF25]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_47:.*]] = arith.muli %[[VAL_45]], %[[VAL_46]] : i32 -// CHECK: affine.store %[[VAL_47]], %[[BUF26]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_7_4]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_7_4_14]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_7_4_15]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_19_2:.*]] = aie.tile(19, 2) -// CHECK: %[[TILE_19_1:.*]] = aie.tile(19, 1) -// CHECK: %[[TILE_19_0:.*]] = aie.tile(19, 0) -// CHECK: %[[TILE_10_3:.*]] = aie.tile(10, 3) -// CHECK: %[[LOCK_10_3:.*]] = aie.lock(%[[TILE_10_3]], 2) -// CHECK: %[[BUF23:.*]] = aie.buffer(%[[TILE_10_3]]) {sym_name = "buf23"} : memref<64xi32, 2> -// CHECK: %[[LOCK_10_3_16:.*]] = aie.lock(%[[TILE_10_3]], 1) -// CHECK: %[[BUF22:.*]] = aie.buffer(%[[TILE_10_3]]) {sym_name = "buf22"} : memref<64xi32, 2> -// CHECK: %[[LOCK_10_3_17:.*]] = aie.lock(%[[TILE_10_3]], 0) -// CHECK: %[[BUF21:.*]] = aie.buffer(%[[TILE_10_3]]) {sym_name = "buf21"} : memref<64xi32, 2> -// CHECK: %[[MEM_10_3:.*]] = aie.mem(%[[TILE_10_3]]) { -// CHECK: %[[VAL_48:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_10_3_17]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF21]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_10_3_17]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_49:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_10_3_16]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF22]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_10_3_16]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_50:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_10_3]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF23]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_10_3]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_10_3:.*]] = aie.core(%[[TILE_10_3]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_10_3_17]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_10_3_16]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_10_3]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_51:.*]] = affine.load %[[BUF21]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_52:.*]] = affine.load %[[BUF22]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_53:.*]] = arith.muli %[[VAL_51]], %[[VAL_52]] : i32 -// CHECK: affine.store %[[VAL_53]], %[[BUF23]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_10_3]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_10_3_16]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_10_3_17]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_18_2:.*]] = aie.tile(18, 2) -// CHECK: %[[TILE_18_1:.*]] = aie.tile(18, 1) -// CHECK: %[[TILE_18_0:.*]] = aie.tile(18, 0) -// CHECK: %[[TILE_9_3:.*]] = aie.tile(9, 3) -// CHECK: %[[LOCK_9_3:.*]] = aie.lock(%[[TILE_9_3]], 2) -// CHECK: %[[BUF20:.*]] = aie.buffer(%[[TILE_9_3]]) {sym_name = "buf20"} : memref<64xi32, 2> -// CHECK: %[[LOCK_9_3_18:.*]] = aie.lock(%[[TILE_9_3]], 1) -// CHECK: %[[BUF19:.*]] = aie.buffer(%[[TILE_9_3]]) {sym_name = "buf19"} : memref<64xi32, 2> -// CHECK: %[[LOCK_9_3_19:.*]] = aie.lock(%[[TILE_9_3]], 0) -// CHECK: %[[BUF18:.*]] = aie.buffer(%[[TILE_9_3]]) {sym_name = "buf18"} : memref<64xi32, 2> -// CHECK: %[[MEM_9_3:.*]] = aie.mem(%[[TILE_9_3]]) { -// CHECK: %[[VAL_54:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_9_3_19]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF18]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_9_3_19]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_55:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_9_3_18]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF19]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_9_3_18]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_56:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_9_3]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF20]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_9_3]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_9_3:.*]] = aie.core(%[[TILE_9_3]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_9_3_19]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_9_3_18]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_9_3]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_57:.*]] = affine.load %[[BUF18]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_58:.*]] = affine.load %[[BUF19]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_59:.*]] = arith.muli %[[VAL_57]], %[[VAL_58]] : i32 -// CHECK: affine.store %[[VAL_59]], %[[BUF20]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_9_3]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_9_3_18]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_9_3_19]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_11_2:.*]] = aie.tile(11, 2) -// CHECK: %[[TILE_11_1:.*]] = aie.tile(11, 1) -// CHECK: %[[TILE_11_0:.*]] = aie.tile(11, 0) -// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) -// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) -// CHECK: %[[LOCK_8_3:.*]] = aie.lock(%[[TILE_8_3]], 2) -// CHECK: %[[BUF17:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf17"} : memref<64xi32, 2> -// CHECK: %[[LOCK_8_3_20:.*]] = aie.lock(%[[TILE_8_3]], 1) -// CHECK: %[[BUF16:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf16"} : memref<64xi32, 2> -// CHECK: %[[LOCK_8_3_21:.*]] = aie.lock(%[[TILE_8_3]], 0) -// CHECK: %[[BUF15:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf15"} : memref<64xi32, 2> -// CHECK: %[[MEM_8_3:.*]] = aie.mem(%[[TILE_8_3]]) { -// CHECK: %[[VAL_60:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_8_3_21]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF15]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_8_3_21]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_61:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_8_3_20]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF16]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_8_3_20]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_62:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_8_3]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF17]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_8_3]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_8_3:.*]] = aie.core(%[[TILE_8_3]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_8_3_21]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_8_3_20]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_8_3]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_63:.*]] = affine.load %[[BUF15]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_64:.*]] = affine.load %[[BUF16]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_65:.*]] = arith.muli %[[VAL_63]], %[[VAL_64]] : i32 -// CHECK: affine.store %[[VAL_65]], %[[BUF17]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_8_3]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_8_3_20]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_8_3_21]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_10_1:.*]] = aie.tile(10, 1) -// CHECK: %[[TILE_10_0:.*]] = aie.tile(10, 0) -// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) -// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) -// CHECK: %[[LOCK_7_3:.*]] = aie.lock(%[[TILE_7_3]], 2) -// CHECK: %[[BUF14:.*]] = aie.buffer(%[[TILE_7_3]]) {sym_name = "buf14"} : memref<64xi32, 2> -// CHECK: %[[LOCK_7_3_22:.*]] = aie.lock(%[[TILE_7_3]], 1) -// CHECK: %[[BUF13:.*]] = aie.buffer(%[[TILE_7_3]]) {sym_name = "buf13"} : memref<64xi32, 2> -// CHECK: %[[LOCK_7_3_23:.*]] = aie.lock(%[[TILE_7_3]], 0) -// CHECK: %[[BUF12:.*]] = aie.buffer(%[[TILE_7_3]]) {sym_name = "buf12"} : memref<64xi32, 2> -// CHECK: %[[MEM_7_3:.*]] = aie.mem(%[[TILE_7_3]]) { -// CHECK: %[[VAL_66:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_7_3_23]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF12]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_7_3_23]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_67:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_7_3_22]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF13]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_7_3_22]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_68:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_7_3]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF14]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_7_3]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_7_3:.*]] = aie.core(%[[TILE_7_3]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_7_3_23]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_7_3_22]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_7_3]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_69:.*]] = affine.load %[[BUF12]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_70:.*]] = affine.load %[[BUF13]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_71:.*]] = arith.muli %[[VAL_69]], %[[VAL_70]] : i32 -// CHECK: affine.store %[[VAL_71]], %[[BUF14]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_7_3]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_7_3_22]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_7_3_23]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) -// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) -// CHECK: %[[TILE_10_2:.*]] = aie.tile(10, 2) -// CHECK: %[[LOCK_10_2:.*]] = aie.lock(%[[TILE_10_2]], 2) -// CHECK: %[[BUF11:.*]] = aie.buffer(%[[TILE_10_2]]) {sym_name = "buf11"} : memref<64xi32, 2> -// CHECK: %[[LOCK_10_2_24:.*]] = aie.lock(%[[TILE_10_2]], 1) -// CHECK: %[[BUF10:.*]] = aie.buffer(%[[TILE_10_2]]) {sym_name = "buf10"} : memref<64xi32, 2> -// CHECK: %[[LOCK_10_2_25:.*]] = aie.lock(%[[TILE_10_2]], 0) -// CHECK: %[[BUF9:.*]] = aie.buffer(%[[TILE_10_2]]) {sym_name = "buf9"} : memref<64xi32, 2> -// CHECK: %[[MEM_10_2:.*]] = aie.mem(%[[TILE_10_2]]) { -// CHECK: %[[VAL_72:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_10_2_25]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF9]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_10_2_25]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_73:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_10_2_24]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF10]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_10_2_24]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_74:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_10_2]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF11]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_10_2]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_10_2:.*]] = aie.core(%[[TILE_10_2]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_10_2_25]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_10_2_24]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_10_2]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_75:.*]] = affine.load %[[BUF9]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_76:.*]] = affine.load %[[BUF10]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_77:.*]] = arith.muli %[[VAL_75]], %[[VAL_76]] : i32 -// CHECK: affine.store %[[VAL_77]], %[[BUF11]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_10_2]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_10_2_24]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_10_2_25]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) -// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) -// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) -// CHECK: %[[TILE_9_2:.*]] = aie.tile(9, 2) -// CHECK: %[[LOCK_9_2:.*]] = aie.lock(%[[TILE_9_2]], 2) -// CHECK: %[[BUF8:.*]] = aie.buffer(%[[TILE_9_2]]) {sym_name = "buf8"} : memref<64xi32, 2> -// CHECK: %[[LOCK_9_2_26:.*]] = aie.lock(%[[TILE_9_2]], 1) -// CHECK: %[[BUF7:.*]] = aie.buffer(%[[TILE_9_2]]) {sym_name = "buf7"} : memref<64xi32, 2> -// CHECK: %[[LOCK_9_2_27:.*]] = aie.lock(%[[TILE_9_2]], 0) -// CHECK: %[[BUF6:.*]] = aie.buffer(%[[TILE_9_2]]) {sym_name = "buf6"} : memref<64xi32, 2> -// CHECK: %[[MEM_9_2:.*]] = aie.mem(%[[TILE_9_2]]) { -// CHECK: %[[VAL_78:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_9_2_27]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF6]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_9_2_27]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_79:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_9_2_26]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF7]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_9_2_26]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_80:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_9_2]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF8]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_9_2]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_9_2:.*]] = aie.core(%[[TILE_9_2]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_9_2_27]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_9_2_26]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_9_2]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_81:.*]] = affine.load %[[BUF6]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_82:.*]] = affine.load %[[BUF7]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_83:.*]] = arith.muli %[[VAL_81]], %[[VAL_82]] : i32 -// CHECK: affine.store %[[VAL_83]], %[[BUF8]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_9_2]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_9_2_26]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_9_2_27]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) -// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) -// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) -// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) -// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) -// CHECK: %[[LOCK_8_2:.*]] = aie.lock(%[[TILE_8_2]], 2) -// CHECK: %[[BUF5:.*]] = aie.buffer(%[[TILE_8_2]]) {sym_name = "buf5"} : memref<64xi32, 2> -// CHECK: %[[LOCK_8_2_28:.*]] = aie.lock(%[[TILE_8_2]], 1) -// CHECK: %[[BUF4:.*]] = aie.buffer(%[[TILE_8_2]]) {sym_name = "buf4"} : memref<64xi32, 2> -// CHECK: %[[LOCK_8_2_29:.*]] = aie.lock(%[[TILE_8_2]], 0) -// CHECK: %[[BUF3:.*]] = aie.buffer(%[[TILE_8_2]]) {sym_name = "buf3"} : memref<64xi32, 2> -// CHECK: %[[MEM_8_2:.*]] = aie.mem(%[[TILE_8_2]]) { -// CHECK: %[[VAL_84:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_8_2_29]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF3]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_8_2_29]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_85:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_8_2_28]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF4]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_8_2_28]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_86:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_8_2]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF5]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_8_2]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_8_2:.*]] = aie.core(%[[TILE_8_2]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_8_2_29]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_8_2_28]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_8_2]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_87:.*]] = affine.load %[[BUF3]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_88:.*]] = affine.load %[[BUF4]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_89:.*]] = arith.muli %[[VAL_87]], %[[VAL_88]] : i32 -// CHECK: affine.store %[[VAL_89]], %[[BUF5]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_8_2]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_8_2_28]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_8_2_29]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) -// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) -// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) -// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) -// CHECK: %[[LOCK_7_2:.*]] = aie.lock(%[[TILE_7_2]], 2) -// CHECK: %[[BUF2:.*]] = aie.buffer(%[[TILE_7_2]]) {sym_name = "buf2"} : memref<64xi32, 2> -// CHECK: %[[LOCK_7_2_30:.*]] = aie.lock(%[[TILE_7_2]], 1) -// CHECK: %[[BUF1:.*]] = aie.buffer(%[[TILE_7_2]]) {sym_name = "buf1"} : memref<64xi32, 2> -// CHECK: %[[LOCK_7_2_31:.*]] = aie.lock(%[[TILE_7_2]], 0) -// CHECK: %[[BUF0:.*]] = aie.buffer(%[[TILE_7_2]]) {sym_name = "buf0"} : memref<64xi32, 2> -// CHECK: %[[MEM_7_2:.*]] = aie.mem(%[[TILE_7_2]]) { -// CHECK: %[[VAL_90:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: -// CHECK: aie.use_lock(%[[LOCK_7_2_31]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF0]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_7_2_31]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: -// CHECK: %[[VAL_91:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) -// CHECK: ^bb3: -// CHECK: aie.use_lock(%[[LOCK_7_2_30]], Acquire, 0) -// CHECK: aie.dma_bd(%[[BUF1]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_7_2_30]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: -// CHECK: %[[VAL_92:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) -// CHECK: ^bb5: -// CHECK: aie.use_lock(%[[LOCK_7_2]], Acquire, 1) -// CHECK: aie.dma_bd(%[[BUF2]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[LOCK_7_2]], Release, 0) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb6: -// CHECK: aie.end -// CHECK: } -// CHECK: %[[CORE_7_2:.*]] = aie.core(%[[TILE_7_2]]) { -// CHECK: cf.br ^bb1 -// CHECK: ^bb1: -// CHECK: cf.br ^bb2 -// CHECK: ^bb2: -// CHECK: aie.use_lock(%[[LOCK_7_2_31]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_7_2_30]], Acquire, 1) -// CHECK: aie.use_lock(%[[LOCK_7_2]], Acquire, 0) -// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { -// CHECK: %[[VAL_93:.*]] = affine.load %[[BUF0]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_94:.*]] = affine.load %[[BUF1]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: %[[VAL_95:.*]] = arith.muli %[[VAL_93]], %[[VAL_94]] : i32 -// CHECK: affine.store %[[VAL_95]], %[[BUF2]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> -// CHECK: } -// CHECK: aie.use_lock(%[[LOCK_7_2]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_7_2_30]], Release, 0) -// CHECK: aie.use_lock(%[[LOCK_7_2_31]], Release, 0) -// CHECK: cf.br ^bb1 -// CHECK: } -// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) -// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) -// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) -// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) -// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) -// CHECK: %[[SWITCHBOX_8_0:.*]] = aie.switchbox(%[[TILE_8_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_9_0:.*]] = aie.tile(9, 0) -// CHECK: %[[SWITCHBOX_9_0:.*]] = aie.switchbox(%[[TILE_9_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_9_1:.*]] = aie.tile(9, 1) -// CHECK: %[[SWITCHBOX_9_1:.*]] = aie.switchbox(%[[TILE_9_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_9_2:.*]] = aie.switchbox(%[[TILE_9_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_0:.*]] = aie.switchbox(%[[TILE_10_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_1:.*]] = aie.switchbox(%[[TILE_10_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_2:.*]] = aie.switchbox(%[[TILE_10_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_8_1:.*]] = aie.tile(8, 1) -// CHECK: %[[SWITCHBOX_8_1:.*]] = aie.switchbox(%[[TILE_8_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_10_0:.*]] = aie.shim_mux(%[[TILE_10_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_9_3:.*]] = aie.switchbox(%[[TILE_9_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_11_0:.*]] = aie.switchbox(%[[TILE_11_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_11_0:.*]] = aie.shim_mux(%[[TILE_11_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_3:.*]] = aie.switchbox(%[[TILE_10_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_12_0:.*]] = aie.tile(12, 0) -// CHECK: %[[SWITCHBOX_12_0:.*]] = aie.switchbox(%[[TILE_12_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_13_0:.*]] = aie.tile(13, 0) -// CHECK: %[[SWITCHBOX_13_0:.*]] = aie.switchbox(%[[TILE_13_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_14_0:.*]] = aie.tile(14, 0) -// CHECK: %[[SWITCHBOX_14_0:.*]] = aie.switchbox(%[[TILE_14_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_15_0:.*]] = aie.tile(15, 0) -// CHECK: %[[SWITCHBOX_15_0:.*]] = aie.switchbox(%[[TILE_15_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_16_0:.*]] = aie.tile(16, 0) -// CHECK: %[[SWITCHBOX_16_0:.*]] = aie.switchbox(%[[TILE_16_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_17_0:.*]] = aie.tile(17, 0) -// CHECK: %[[SWITCHBOX_17_0:.*]] = aie.switchbox(%[[TILE_17_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_18_0:.*]] = aie.switchbox(%[[TILE_18_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_18_0:.*]] = aie.shim_mux(%[[TILE_18_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_11_1:.*]] = aie.switchbox(%[[TILE_11_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_11_2:.*]] = aie.switchbox(%[[TILE_11_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_11_3:.*]] = aie.tile(11, 3) -// CHECK: %[[SWITCHBOX_11_3:.*]] = aie.switchbox(%[[TILE_11_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_19_0:.*]] = aie.switchbox(%[[TILE_19_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_19_0:.*]] = aie.shim_mux(%[[TILE_19_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_12_1:.*]] = aie.tile(12, 1) -// CHECK: %[[SWITCHBOX_12_1:.*]] = aie.switchbox(%[[TILE_12_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_13_1:.*]] = aie.tile(13, 1) -// CHECK: %[[SWITCHBOX_13_1:.*]] = aie.switchbox(%[[TILE_13_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_14_1:.*]] = aie.tile(14, 1) -// CHECK: %[[SWITCHBOX_14_1:.*]] = aie.switchbox(%[[TILE_14_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_15_1:.*]] = aie.tile(15, 1) -// CHECK: %[[SWITCHBOX_15_1:.*]] = aie.switchbox(%[[TILE_15_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_16_1:.*]] = aie.tile(16, 1) -// CHECK: %[[SWITCHBOX_16_1:.*]] = aie.switchbox(%[[TILE_16_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_17_1:.*]] = aie.tile(17, 1) -// CHECK: %[[SWITCHBOX_17_1:.*]] = aie.switchbox(%[[TILE_17_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_18_1:.*]] = aie.switchbox(%[[TILE_18_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_20_0:.*]] = aie.tile(20, 0) -// CHECK: %[[SWITCHBOX_20_0:.*]] = aie.switchbox(%[[TILE_20_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_21_0:.*]] = aie.tile(21, 0) -// CHECK: %[[SWITCHBOX_21_0:.*]] = aie.switchbox(%[[TILE_21_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_22_0:.*]] = aie.tile(22, 0) -// CHECK: %[[SWITCHBOX_22_0:.*]] = aie.switchbox(%[[TILE_22_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_23_0:.*]] = aie.tile(23, 0) -// CHECK: %[[SWITCHBOX_23_0:.*]] = aie.switchbox(%[[TILE_23_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_24_0:.*]] = aie.tile(24, 0) -// CHECK: %[[SWITCHBOX_24_0:.*]] = aie.switchbox(%[[TILE_24_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_25_0:.*]] = aie.tile(25, 0) -// CHECK: %[[SWITCHBOX_25_0:.*]] = aie.switchbox(%[[TILE_25_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_26_0:.*]] = aie.switchbox(%[[TILE_26_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_26_0:.*]] = aie.shim_mux(%[[TILE_26_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_9_4:.*]] = aie.switchbox(%[[TILE_9_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_19_1:.*]] = aie.switchbox(%[[TILE_19_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_27_0:.*]] = aie.switchbox(%[[TILE_27_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_27_0:.*]] = aie.shim_mux(%[[TILE_27_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_12_2:.*]] = aie.tile(12, 2) -// CHECK: %[[SWITCHBOX_12_2:.*]] = aie.switchbox(%[[TILE_12_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_13_2:.*]] = aie.tile(13, 2) -// CHECK: %[[SWITCHBOX_13_2:.*]] = aie.switchbox(%[[TILE_13_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_14_2:.*]] = aie.tile(14, 2) -// CHECK: %[[SWITCHBOX_14_2:.*]] = aie.switchbox(%[[TILE_14_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_15_2:.*]] = aie.tile(15, 2) -// CHECK: %[[SWITCHBOX_15_2:.*]] = aie.switchbox(%[[TILE_15_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_16_2:.*]] = aie.tile(16, 2) -// CHECK: %[[SWITCHBOX_16_2:.*]] = aie.switchbox(%[[TILE_16_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_17_2:.*]] = aie.tile(17, 2) -// CHECK: %[[SWITCHBOX_17_2:.*]] = aie.switchbox(%[[TILE_17_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_18_2:.*]] = aie.switchbox(%[[TILE_18_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_19_2:.*]] = aie.switchbox(%[[TILE_19_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_20_1:.*]] = aie.tile(20, 1) -// CHECK: %[[SWITCHBOX_20_1:.*]] = aie.switchbox(%[[TILE_20_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_20_2:.*]] = aie.tile(20, 2) -// CHECK: %[[SWITCHBOX_20_2:.*]] = aie.switchbox(%[[TILE_20_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_21_1:.*]] = aie.tile(21, 1) -// CHECK: %[[SWITCHBOX_21_1:.*]] = aie.switchbox(%[[TILE_21_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_22_1:.*]] = aie.tile(22, 1) -// CHECK: %[[SWITCHBOX_22_1:.*]] = aie.switchbox(%[[TILE_22_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_23_1:.*]] = aie.tile(23, 1) -// CHECK: %[[SWITCHBOX_23_1:.*]] = aie.switchbox(%[[TILE_23_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_24_1:.*]] = aie.tile(24, 1) -// CHECK: %[[SWITCHBOX_24_1:.*]] = aie.switchbox(%[[TILE_24_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_25_1:.*]] = aie.tile(25, 1) -// CHECK: %[[SWITCHBOX_25_1:.*]] = aie.switchbox(%[[TILE_25_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_26_1:.*]] = aie.switchbox(%[[TILE_26_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_28_0:.*]] = aie.tile(28, 0) -// CHECK: %[[SWITCHBOX_28_0:.*]] = aie.switchbox(%[[TILE_28_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_29_0:.*]] = aie.tile(29, 0) -// CHECK: %[[SWITCHBOX_29_0:.*]] = aie.switchbox(%[[TILE_29_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_30_0:.*]] = aie.tile(30, 0) -// CHECK: %[[SWITCHBOX_30_0:.*]] = aie.switchbox(%[[TILE_30_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_31_0:.*]] = aie.tile(31, 0) -// CHECK: %[[SWITCHBOX_31_0:.*]] = aie.switchbox(%[[TILE_31_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_32_0:.*]] = aie.tile(32, 0) -// CHECK: %[[SWITCHBOX_32_0:.*]] = aie.switchbox(%[[TILE_32_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_33_0:.*]] = aie.tile(33, 0) -// CHECK: %[[SWITCHBOX_33_0:.*]] = aie.switchbox(%[[TILE_33_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_34_0:.*]] = aie.switchbox(%[[TILE_34_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_34_0:.*]] = aie.shim_mux(%[[TILE_34_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_4:.*]] = aie.switchbox(%[[TILE_10_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_12_3:.*]] = aie.tile(12, 3) -// CHECK: %[[SWITCHBOX_12_3:.*]] = aie.switchbox(%[[TILE_12_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_13_3:.*]] = aie.tile(13, 3) -// CHECK: %[[SWITCHBOX_13_3:.*]] = aie.switchbox(%[[TILE_13_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_14_3:.*]] = aie.tile(14, 3) -// CHECK: %[[SWITCHBOX_14_3:.*]] = aie.switchbox(%[[TILE_14_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_15_3:.*]] = aie.tile(15, 3) -// CHECK: %[[SWITCHBOX_15_3:.*]] = aie.switchbox(%[[TILE_15_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_16_3:.*]] = aie.tile(16, 3) -// CHECK: %[[SWITCHBOX_16_3:.*]] = aie.switchbox(%[[TILE_16_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_17_3:.*]] = aie.tile(17, 3) -// CHECK: %[[SWITCHBOX_17_3:.*]] = aie.switchbox(%[[TILE_17_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_18_3:.*]] = aie.tile(18, 3) -// CHECK: %[[SWITCHBOX_18_3:.*]] = aie.switchbox(%[[TILE_18_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_19_3:.*]] = aie.tile(19, 3) -// CHECK: %[[SWITCHBOX_19_3:.*]] = aie.switchbox(%[[TILE_19_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_20_3:.*]] = aie.tile(20, 3) -// CHECK: %[[SWITCHBOX_20_3:.*]] = aie.switchbox(%[[TILE_20_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_27_1:.*]] = aie.switchbox(%[[TILE_27_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_35_0:.*]] = aie.switchbox(%[[TILE_35_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_35_0:.*]] = aie.shim_mux(%[[TILE_35_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_7_5:.*]] = aie.switchbox(%[[TILE_7_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_8_5:.*]] = aie.switchbox(%[[TILE_8_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_9_5:.*]] = aie.switchbox(%[[TILE_9_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_10_5:.*]] = aie.switchbox(%[[TILE_10_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_11_5:.*]] = aie.tile(11, 5) -// CHECK: %[[SWITCHBOX_11_5:.*]] = aie.switchbox(%[[TILE_11_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_12_5:.*]] = aie.tile(12, 5) -// CHECK: %[[SWITCHBOX_12_5:.*]] = aie.switchbox(%[[TILE_12_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_13_5:.*]] = aie.tile(13, 5) -// CHECK: %[[SWITCHBOX_13_5:.*]] = aie.switchbox(%[[TILE_13_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_14_5:.*]] = aie.tile(14, 5) -// CHECK: %[[SWITCHBOX_14_5:.*]] = aie.switchbox(%[[TILE_14_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_15_4:.*]] = aie.tile(15, 4) -// CHECK: %[[SWITCHBOX_15_4:.*]] = aie.switchbox(%[[TILE_15_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_15_5:.*]] = aie.tile(15, 5) -// CHECK: %[[SWITCHBOX_15_5:.*]] = aie.switchbox(%[[TILE_15_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_21_3:.*]] = aie.tile(21, 3) -// CHECK: %[[SWITCHBOX_21_3:.*]] = aie.switchbox(%[[TILE_21_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_22_3:.*]] = aie.tile(22, 3) -// CHECK: %[[SWITCHBOX_22_3:.*]] = aie.switchbox(%[[TILE_22_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_23_3:.*]] = aie.tile(23, 3) -// CHECK: %[[SWITCHBOX_23_3:.*]] = aie.switchbox(%[[TILE_23_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_24_2:.*]] = aie.tile(24, 2) -// CHECK: %[[SWITCHBOX_24_2:.*]] = aie.switchbox(%[[TILE_24_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_24_3:.*]] = aie.tile(24, 3) -// CHECK: %[[SWITCHBOX_24_3:.*]] = aie.switchbox(%[[TILE_24_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_25_2:.*]] = aie.tile(25, 2) -// CHECK: %[[SWITCHBOX_25_2:.*]] = aie.switchbox(%[[TILE_25_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_26_2:.*]] = aie.switchbox(%[[TILE_26_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_28_1:.*]] = aie.tile(28, 1) -// CHECK: %[[SWITCHBOX_28_1:.*]] = aie.switchbox(%[[TILE_28_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_29_1:.*]] = aie.tile(29, 1) -// CHECK: %[[SWITCHBOX_29_1:.*]] = aie.switchbox(%[[TILE_29_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_30_1:.*]] = aie.tile(30, 1) -// CHECK: %[[SWITCHBOX_30_1:.*]] = aie.switchbox(%[[TILE_30_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_31_1:.*]] = aie.tile(31, 1) -// CHECK: %[[SWITCHBOX_31_1:.*]] = aie.switchbox(%[[TILE_31_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_32_1:.*]] = aie.tile(32, 1) -// CHECK: %[[SWITCHBOX_32_1:.*]] = aie.switchbox(%[[TILE_32_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_33_1:.*]] = aie.tile(33, 1) -// CHECK: %[[SWITCHBOX_33_1:.*]] = aie.switchbox(%[[TILE_33_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_34_1:.*]] = aie.switchbox(%[[TILE_34_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_36_0:.*]] = aie.tile(36, 0) -// CHECK: %[[SWITCHBOX_36_0:.*]] = aie.switchbox(%[[TILE_36_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_37_0:.*]] = aie.tile(37, 0) -// CHECK: %[[SWITCHBOX_37_0:.*]] = aie.switchbox(%[[TILE_37_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_38_0:.*]] = aie.tile(38, 0) -// CHECK: %[[SWITCHBOX_38_0:.*]] = aie.switchbox(%[[TILE_38_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_39_0:.*]] = aie.tile(39, 0) -// CHECK: %[[SWITCHBOX_39_0:.*]] = aie.switchbox(%[[TILE_39_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_40_0:.*]] = aie.tile(40, 0) -// CHECK: %[[SWITCHBOX_40_0:.*]] = aie.switchbox(%[[TILE_40_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_41_0:.*]] = aie.tile(41, 0) -// CHECK: %[[SWITCHBOX_41_0:.*]] = aie.switchbox(%[[TILE_41_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_42_0:.*]] = aie.switchbox(%[[TILE_42_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_42_0:.*]] = aie.shim_mux(%[[TILE_42_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_11_4:.*]] = aie.tile(11, 4) -// CHECK: %[[SWITCHBOX_11_4:.*]] = aie.switchbox(%[[TILE_11_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_12_4:.*]] = aie.tile(12, 4) -// CHECK: %[[SWITCHBOX_12_4:.*]] = aie.switchbox(%[[TILE_12_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_13_4:.*]] = aie.tile(13, 4) -// CHECK: %[[SWITCHBOX_13_4:.*]] = aie.switchbox(%[[TILE_13_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_14_4:.*]] = aie.tile(14, 4) -// CHECK: %[[SWITCHBOX_14_4:.*]] = aie.switchbox(%[[TILE_14_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_16_4:.*]] = aie.tile(16, 4) -// CHECK: %[[SWITCHBOX_16_4:.*]] = aie.switchbox(%[[TILE_16_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_17_4:.*]] = aie.tile(17, 4) -// CHECK: %[[SWITCHBOX_17_4:.*]] = aie.switchbox(%[[TILE_17_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_21_2:.*]] = aie.tile(21, 2) -// CHECK: %[[SWITCHBOX_21_2:.*]] = aie.switchbox(%[[TILE_21_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_22_2:.*]] = aie.tile(22, 2) -// CHECK: %[[SWITCHBOX_22_2:.*]] = aie.switchbox(%[[TILE_22_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_23_2:.*]] = aie.tile(23, 2) -// CHECK: %[[SWITCHBOX_23_2:.*]] = aie.switchbox(%[[TILE_23_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_27_2:.*]] = aie.switchbox(%[[TILE_27_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_35_1:.*]] = aie.switchbox(%[[TILE_35_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_43_0:.*]] = aie.switchbox(%[[TILE_43_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_43_0:.*]] = aie.shim_mux(%[[TILE_43_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_18_4:.*]] = aie.tile(18, 4) -// CHECK: %[[SWITCHBOX_18_4:.*]] = aie.switchbox(%[[TILE_18_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_19_4:.*]] = aie.tile(19, 4) -// CHECK: %[[SWITCHBOX_19_4:.*]] = aie.switchbox(%[[TILE_19_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_20_4:.*]] = aie.tile(20, 4) -// CHECK: %[[SWITCHBOX_20_4:.*]] = aie.switchbox(%[[TILE_20_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_25_3:.*]] = aie.tile(25, 3) -// CHECK: %[[SWITCHBOX_25_3:.*]] = aie.switchbox(%[[TILE_25_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_26_3:.*]] = aie.tile(26, 3) -// CHECK: %[[SWITCHBOX_26_3:.*]] = aie.switchbox(%[[TILE_26_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_28_2:.*]] = aie.tile(28, 2) -// CHECK: %[[SWITCHBOX_28_2:.*]] = aie.switchbox(%[[TILE_28_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_29_2:.*]] = aie.tile(29, 2) -// CHECK: %[[SWITCHBOX_29_2:.*]] = aie.switchbox(%[[TILE_29_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_30_2:.*]] = aie.tile(30, 2) -// CHECK: %[[SWITCHBOX_30_2:.*]] = aie.switchbox(%[[TILE_30_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_31_2:.*]] = aie.tile(31, 2) -// CHECK: %[[SWITCHBOX_31_2:.*]] = aie.switchbox(%[[TILE_31_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_32_2:.*]] = aie.tile(32, 2) -// CHECK: %[[SWITCHBOX_32_2:.*]] = aie.switchbox(%[[TILE_32_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_33_2:.*]] = aie.tile(33, 2) -// CHECK: %[[SWITCHBOX_33_2:.*]] = aie.switchbox(%[[TILE_33_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_34_2:.*]] = aie.switchbox(%[[TILE_34_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_35_2:.*]] = aie.switchbox(%[[TILE_35_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_36_2:.*]] = aie.tile(36, 2) -// CHECK: %[[SWITCHBOX_36_2:.*]] = aie.switchbox(%[[TILE_36_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_37_2:.*]] = aie.tile(37, 2) -// CHECK: %[[SWITCHBOX_37_2:.*]] = aie.switchbox(%[[TILE_37_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_38_2:.*]] = aie.tile(38, 2) -// CHECK: %[[SWITCHBOX_38_2:.*]] = aie.switchbox(%[[TILE_38_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_39_2:.*]] = aie.tile(39, 2) -// CHECK: %[[SWITCHBOX_39_2:.*]] = aie.switchbox(%[[TILE_39_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_40_2:.*]] = aie.tile(40, 2) -// CHECK: %[[SWITCHBOX_40_2:.*]] = aie.switchbox(%[[TILE_40_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_41_1:.*]] = aie.tile(41, 1) -// CHECK: %[[SWITCHBOX_41_1:.*]] = aie.switchbox(%[[TILE_41_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_41_2:.*]] = aie.tile(41, 2) -// CHECK: %[[SWITCHBOX_41_2:.*]] = aie.switchbox(%[[TILE_41_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_42_1:.*]] = aie.switchbox(%[[TILE_42_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_44_0:.*]] = aie.tile(44, 0) -// CHECK: %[[SWITCHBOX_44_0:.*]] = aie.switchbox(%[[TILE_44_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_45_0:.*]] = aie.tile(45, 0) -// CHECK: %[[SWITCHBOX_45_0:.*]] = aie.switchbox(%[[TILE_45_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_46_0:.*]] = aie.switchbox(%[[TILE_46_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_46_0:.*]] = aie.shim_mux(%[[TILE_46_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_16_5:.*]] = aie.tile(16, 5) -// CHECK: %[[SWITCHBOX_16_5:.*]] = aie.switchbox(%[[TILE_16_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_17_5:.*]] = aie.tile(17, 5) -// CHECK: %[[SWITCHBOX_17_5:.*]] = aie.switchbox(%[[TILE_17_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_18_5:.*]] = aie.tile(18, 5) -// CHECK: %[[SWITCHBOX_18_5:.*]] = aie.switchbox(%[[TILE_18_5]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_21_4:.*]] = aie.tile(21, 4) -// CHECK: %[[SWITCHBOX_21_4:.*]] = aie.switchbox(%[[TILE_21_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_22_4:.*]] = aie.tile(22, 4) -// CHECK: %[[SWITCHBOX_22_4:.*]] = aie.switchbox(%[[TILE_22_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_23_4:.*]] = aie.tile(23, 4) -// CHECK: %[[SWITCHBOX_23_4:.*]] = aie.switchbox(%[[TILE_23_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_24_4:.*]] = aie.tile(24, 4) -// CHECK: %[[SWITCHBOX_24_4:.*]] = aie.switchbox(%[[TILE_24_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_25_4:.*]] = aie.tile(25, 4) -// CHECK: %[[SWITCHBOX_25_4:.*]] = aie.switchbox(%[[TILE_25_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_26_4:.*]] = aie.tile(26, 4) -// CHECK: %[[SWITCHBOX_26_4:.*]] = aie.switchbox(%[[TILE_26_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_27_4:.*]] = aie.tile(27, 4) -// CHECK: %[[SWITCHBOX_27_4:.*]] = aie.switchbox(%[[TILE_27_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_28_4:.*]] = aie.tile(28, 4) -// CHECK: %[[SWITCHBOX_28_4:.*]] = aie.switchbox(%[[TILE_28_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_29_4:.*]] = aie.tile(29, 4) -// CHECK: %[[SWITCHBOX_29_4:.*]] = aie.switchbox(%[[TILE_29_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_30_4:.*]] = aie.tile(30, 4) -// CHECK: %[[SWITCHBOX_30_4:.*]] = aie.switchbox(%[[TILE_30_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_31_4:.*]] = aie.tile(31, 4) -// CHECK: %[[SWITCHBOX_31_4:.*]] = aie.switchbox(%[[TILE_31_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_32_4:.*]] = aie.tile(32, 4) -// CHECK: %[[SWITCHBOX_32_4:.*]] = aie.switchbox(%[[TILE_32_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_33_4:.*]] = aie.tile(33, 4) -// CHECK: %[[SWITCHBOX_33_4:.*]] = aie.switchbox(%[[TILE_33_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_34_4:.*]] = aie.tile(34, 4) -// CHECK: %[[SWITCHBOX_34_4:.*]] = aie.switchbox(%[[TILE_34_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_35_4:.*]] = aie.tile(35, 4) -// CHECK: %[[SWITCHBOX_35_4:.*]] = aie.switchbox(%[[TILE_35_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_36_4:.*]] = aie.tile(36, 4) -// CHECK: %[[SWITCHBOX_36_4:.*]] = aie.switchbox(%[[TILE_36_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_37_4:.*]] = aie.tile(37, 4) -// CHECK: %[[SWITCHBOX_37_4:.*]] = aie.switchbox(%[[TILE_37_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_38_4:.*]] = aie.tile(38, 4) -// CHECK: %[[SWITCHBOX_38_4:.*]] = aie.switchbox(%[[TILE_38_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_39_4:.*]] = aie.tile(39, 4) -// CHECK: %[[SWITCHBOX_39_4:.*]] = aie.switchbox(%[[TILE_39_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_40_4:.*]] = aie.tile(40, 4) -// CHECK: %[[SWITCHBOX_40_4:.*]] = aie.switchbox(%[[TILE_40_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_41_4:.*]] = aie.tile(41, 4) -// CHECK: %[[SWITCHBOX_41_4:.*]] = aie.switchbox(%[[TILE_41_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_42_3:.*]] = aie.tile(42, 3) -// CHECK: %[[SWITCHBOX_42_3:.*]] = aie.switchbox(%[[TILE_42_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_42_4:.*]] = aie.tile(42, 4) -// CHECK: %[[SWITCHBOX_42_4:.*]] = aie.switchbox(%[[TILE_42_4]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_43_3:.*]] = aie.tile(43, 3) -// CHECK: %[[SWITCHBOX_43_3:.*]] = aie.switchbox(%[[TILE_43_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_44_3:.*]] = aie.tile(44, 3) -// CHECK: %[[SWITCHBOX_44_3:.*]] = aie.switchbox(%[[TILE_44_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_45_2:.*]] = aie.tile(45, 2) -// CHECK: %[[SWITCHBOX_45_2:.*]] = aie.switchbox(%[[TILE_45_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[TILE_45_3:.*]] = aie.tile(45, 3) -// CHECK: %[[SWITCHBOX_45_3:.*]] = aie.switchbox(%[[TILE_45_3]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_46_1:.*]] = aie.switchbox(%[[TILE_46_1]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_46_2:.*]] = aie.switchbox(%[[TILE_46_2]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SWITCHBOX_47_0:.*]] = aie.switchbox(%[[TILE_47_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SHIM_MUX_47_0:.*]] = aie.shim_mux(%[[TILE_47_0]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) -// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) -// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) -// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) -// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) -// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) -// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) -// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : East, %[[SWITCHBOX_5_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) -// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) -// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) -// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) -// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) -// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) -// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) -// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) -// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) -// CHECK: aie.wire(%[[TILE_7_4]] : Core, %[[SWITCHBOX_7_4:.*]] : Core) -// CHECK: aie.wire(%[[TILE_7_4]] : DMA, %[[SWITCHBOX_7_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : North, %[[SWITCHBOX_7_4]] : South) -// CHECK: aie.wire(%[[TILE_7_5]] : Core, %[[SWITCHBOX_7_5:.*]] : Core) -// CHECK: aie.wire(%[[TILE_7_5]] : DMA, %[[SWITCHBOX_7_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : North, %[[SWITCHBOX_7_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : East, %[[SWITCHBOX_8_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : East, %[[SWITCHBOX_8_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_1]] : Core, %[[SWITCHBOX_8_1]] : Core) -// CHECK: aie.wire(%[[TILE_8_1]] : DMA, %[[SWITCHBOX_8_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_0]] : North, %[[SWITCHBOX_8_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) -// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : North, %[[SWITCHBOX_8_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) -// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : East, %[[SWITCHBOX_8_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_4]] : Core, %[[SWITCHBOX_8_4]] : Core) -// CHECK: aie.wire(%[[TILE_8_4]] : DMA, %[[SWITCHBOX_8_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : North, %[[SWITCHBOX_8_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_7_5]] : East, %[[SWITCHBOX_8_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_8_5]] : Core, %[[SWITCHBOX_8_5]] : Core) -// CHECK: aie.wire(%[[TILE_8_5]] : DMA, %[[SWITCHBOX_8_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_8_4]] : North, %[[SWITCHBOX_8_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_8_0]] : East, %[[SWITCHBOX_9_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : East, %[[SWITCHBOX_9_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_1]] : Core, %[[SWITCHBOX_9_1]] : Core) -// CHECK: aie.wire(%[[TILE_9_1]] : DMA, %[[SWITCHBOX_9_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_0]] : North, %[[SWITCHBOX_9_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : East, %[[SWITCHBOX_9_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_2]] : Core, %[[SWITCHBOX_9_2]] : Core) -// CHECK: aie.wire(%[[TILE_9_2]] : DMA, %[[SWITCHBOX_9_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_1]] : North, %[[SWITCHBOX_9_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : East, %[[SWITCHBOX_9_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_3]] : Core, %[[SWITCHBOX_9_3]] : Core) -// CHECK: aie.wire(%[[TILE_9_3]] : DMA, %[[SWITCHBOX_9_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : North, %[[SWITCHBOX_9_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_8_4]] : East, %[[SWITCHBOX_9_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_4]] : Core, %[[SWITCHBOX_9_4]] : Core) -// CHECK: aie.wire(%[[TILE_9_4]] : DMA, %[[SWITCHBOX_9_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_3]] : North, %[[SWITCHBOX_9_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_8_5]] : East, %[[SWITCHBOX_9_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_9_5]] : Core, %[[SWITCHBOX_9_5]] : Core) -// CHECK: aie.wire(%[[TILE_9_5]] : DMA, %[[SWITCHBOX_9_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_4]] : North, %[[SWITCHBOX_9_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_9_0]] : East, %[[SWITCHBOX_10_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_10_0:.*]] : North, %[[SWITCHBOX_10_0]] : South) -// CHECK: aie.wire(%[[TILE_10_0]] : DMA, %[[SHIM_MUX_10_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_9_1]] : East, %[[SWITCHBOX_10_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_1]] : Core, %[[SWITCHBOX_10_1]] : Core) -// CHECK: aie.wire(%[[TILE_10_1]] : DMA, %[[SWITCHBOX_10_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : North, %[[SWITCHBOX_10_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : East, %[[SWITCHBOX_10_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_2]] : Core, %[[SWITCHBOX_10_2]] : Core) -// CHECK: aie.wire(%[[TILE_10_2]] : DMA, %[[SWITCHBOX_10_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_1]] : North, %[[SWITCHBOX_10_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_9_3]] : East, %[[SWITCHBOX_10_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_3]] : Core, %[[SWITCHBOX_10_3]] : Core) -// CHECK: aie.wire(%[[TILE_10_3]] : DMA, %[[SWITCHBOX_10_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_2]] : North, %[[SWITCHBOX_10_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_9_4]] : East, %[[SWITCHBOX_10_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_4]] : Core, %[[SWITCHBOX_10_4]] : Core) -// CHECK: aie.wire(%[[TILE_10_4]] : DMA, %[[SWITCHBOX_10_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_3]] : North, %[[SWITCHBOX_10_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_9_5]] : East, %[[SWITCHBOX_10_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_10_5]] : Core, %[[SWITCHBOX_10_5]] : Core) -// CHECK: aie.wire(%[[TILE_10_5]] : DMA, %[[SWITCHBOX_10_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_4]] : North, %[[SWITCHBOX_10_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : East, %[[SWITCHBOX_11_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_11_0:.*]] : North, %[[SWITCHBOX_11_0]] : South) -// CHECK: aie.wire(%[[TILE_11_0]] : DMA, %[[SHIM_MUX_11_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_10_1]] : East, %[[SWITCHBOX_11_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_1]] : Core, %[[SWITCHBOX_11_1]] : Core) -// CHECK: aie.wire(%[[TILE_11_1]] : DMA, %[[SWITCHBOX_11_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_0]] : North, %[[SWITCHBOX_11_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_2]] : East, %[[SWITCHBOX_11_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_2]] : Core, %[[SWITCHBOX_11_2]] : Core) -// CHECK: aie.wire(%[[TILE_11_2]] : DMA, %[[SWITCHBOX_11_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_1]] : North, %[[SWITCHBOX_11_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_3]] : East, %[[SWITCHBOX_11_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_3]] : Core, %[[SWITCHBOX_11_3]] : Core) -// CHECK: aie.wire(%[[TILE_11_3]] : DMA, %[[SWITCHBOX_11_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_2]] : North, %[[SWITCHBOX_11_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_4]] : East, %[[SWITCHBOX_11_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_4]] : Core, %[[SWITCHBOX_11_4]] : Core) -// CHECK: aie.wire(%[[TILE_11_4]] : DMA, %[[SWITCHBOX_11_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_3]] : North, %[[SWITCHBOX_11_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_10_5]] : East, %[[SWITCHBOX_11_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_11_5]] : Core, %[[SWITCHBOX_11_5]] : Core) -// CHECK: aie.wire(%[[TILE_11_5]] : DMA, %[[SWITCHBOX_11_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_11_4]] : North, %[[SWITCHBOX_11_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_11_0]] : East, %[[SWITCHBOX_12_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_11_1]] : East, %[[SWITCHBOX_12_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_12_1]] : Core, %[[SWITCHBOX_12_1]] : Core) -// CHECK: aie.wire(%[[TILE_12_1]] : DMA, %[[SWITCHBOX_12_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_12_0]] : North, %[[SWITCHBOX_12_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_11_2]] : East, %[[SWITCHBOX_12_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_12_2]] : Core, %[[SWITCHBOX_12_2]] : Core) -// CHECK: aie.wire(%[[TILE_12_2]] : DMA, %[[SWITCHBOX_12_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_12_1]] : North, %[[SWITCHBOX_12_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_11_3]] : East, %[[SWITCHBOX_12_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_12_3]] : Core, %[[SWITCHBOX_12_3]] : Core) -// CHECK: aie.wire(%[[TILE_12_3]] : DMA, %[[SWITCHBOX_12_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_12_2]] : North, %[[SWITCHBOX_12_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_11_4]] : East, %[[SWITCHBOX_12_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_12_4]] : Core, %[[SWITCHBOX_12_4]] : Core) -// CHECK: aie.wire(%[[TILE_12_4]] : DMA, %[[SWITCHBOX_12_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_12_3]] : North, %[[SWITCHBOX_12_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_11_5]] : East, %[[SWITCHBOX_12_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_12_5]] : Core, %[[SWITCHBOX_12_5]] : Core) -// CHECK: aie.wire(%[[TILE_12_5]] : DMA, %[[SWITCHBOX_12_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_12_4]] : North, %[[SWITCHBOX_12_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_12_0]] : East, %[[SWITCHBOX_13_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_12_1]] : East, %[[SWITCHBOX_13_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_13_1]] : Core, %[[SWITCHBOX_13_1]] : Core) -// CHECK: aie.wire(%[[TILE_13_1]] : DMA, %[[SWITCHBOX_13_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_13_0]] : North, %[[SWITCHBOX_13_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_12_2]] : East, %[[SWITCHBOX_13_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_13_2]] : Core, %[[SWITCHBOX_13_2]] : Core) -// CHECK: aie.wire(%[[TILE_13_2]] : DMA, %[[SWITCHBOX_13_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_13_1]] : North, %[[SWITCHBOX_13_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_12_3]] : East, %[[SWITCHBOX_13_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_13_3]] : Core, %[[SWITCHBOX_13_3]] : Core) -// CHECK: aie.wire(%[[TILE_13_3]] : DMA, %[[SWITCHBOX_13_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_13_2]] : North, %[[SWITCHBOX_13_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_12_4]] : East, %[[SWITCHBOX_13_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_13_4]] : Core, %[[SWITCHBOX_13_4]] : Core) -// CHECK: aie.wire(%[[TILE_13_4]] : DMA, %[[SWITCHBOX_13_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_13_3]] : North, %[[SWITCHBOX_13_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_12_5]] : East, %[[SWITCHBOX_13_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_13_5]] : Core, %[[SWITCHBOX_13_5]] : Core) -// CHECK: aie.wire(%[[TILE_13_5]] : DMA, %[[SWITCHBOX_13_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_13_4]] : North, %[[SWITCHBOX_13_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_13_0]] : East, %[[SWITCHBOX_14_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_13_1]] : East, %[[SWITCHBOX_14_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_14_1]] : Core, %[[SWITCHBOX_14_1]] : Core) -// CHECK: aie.wire(%[[TILE_14_1]] : DMA, %[[SWITCHBOX_14_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_14_0]] : North, %[[SWITCHBOX_14_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_13_2]] : East, %[[SWITCHBOX_14_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_14_2]] : Core, %[[SWITCHBOX_14_2]] : Core) -// CHECK: aie.wire(%[[TILE_14_2]] : DMA, %[[SWITCHBOX_14_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_14_1]] : North, %[[SWITCHBOX_14_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_13_3]] : East, %[[SWITCHBOX_14_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_14_3]] : Core, %[[SWITCHBOX_14_3]] : Core) -// CHECK: aie.wire(%[[TILE_14_3]] : DMA, %[[SWITCHBOX_14_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_14_2]] : North, %[[SWITCHBOX_14_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_13_4]] : East, %[[SWITCHBOX_14_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_14_4]] : Core, %[[SWITCHBOX_14_4]] : Core) -// CHECK: aie.wire(%[[TILE_14_4]] : DMA, %[[SWITCHBOX_14_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_14_3]] : North, %[[SWITCHBOX_14_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_13_5]] : East, %[[SWITCHBOX_14_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_14_5]] : Core, %[[SWITCHBOX_14_5]] : Core) -// CHECK: aie.wire(%[[TILE_14_5]] : DMA, %[[SWITCHBOX_14_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_14_4]] : North, %[[SWITCHBOX_14_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_14_0]] : East, %[[SWITCHBOX_15_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_14_1]] : East, %[[SWITCHBOX_15_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_15_1]] : Core, %[[SWITCHBOX_15_1]] : Core) -// CHECK: aie.wire(%[[TILE_15_1]] : DMA, %[[SWITCHBOX_15_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_15_0]] : North, %[[SWITCHBOX_15_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_14_2]] : East, %[[SWITCHBOX_15_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_15_2]] : Core, %[[SWITCHBOX_15_2]] : Core) -// CHECK: aie.wire(%[[TILE_15_2]] : DMA, %[[SWITCHBOX_15_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_15_1]] : North, %[[SWITCHBOX_15_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_14_3]] : East, %[[SWITCHBOX_15_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_15_3]] : Core, %[[SWITCHBOX_15_3]] : Core) -// CHECK: aie.wire(%[[TILE_15_3]] : DMA, %[[SWITCHBOX_15_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_15_2]] : North, %[[SWITCHBOX_15_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_14_4]] : East, %[[SWITCHBOX_15_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_15_4]] : Core, %[[SWITCHBOX_15_4]] : Core) -// CHECK: aie.wire(%[[TILE_15_4]] : DMA, %[[SWITCHBOX_15_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_15_3]] : North, %[[SWITCHBOX_15_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_14_5]] : East, %[[SWITCHBOX_15_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_15_5]] : Core, %[[SWITCHBOX_15_5]] : Core) -// CHECK: aie.wire(%[[TILE_15_5]] : DMA, %[[SWITCHBOX_15_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_15_4]] : North, %[[SWITCHBOX_15_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_15_0]] : East, %[[SWITCHBOX_16_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_15_1]] : East, %[[SWITCHBOX_16_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_16_1]] : Core, %[[SWITCHBOX_16_1]] : Core) -// CHECK: aie.wire(%[[TILE_16_1]] : DMA, %[[SWITCHBOX_16_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_16_0]] : North, %[[SWITCHBOX_16_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_15_2]] : East, %[[SWITCHBOX_16_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_16_2]] : Core, %[[SWITCHBOX_16_2]] : Core) -// CHECK: aie.wire(%[[TILE_16_2]] : DMA, %[[SWITCHBOX_16_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_16_1]] : North, %[[SWITCHBOX_16_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_15_3]] : East, %[[SWITCHBOX_16_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_16_3]] : Core, %[[SWITCHBOX_16_3]] : Core) -// CHECK: aie.wire(%[[TILE_16_3]] : DMA, %[[SWITCHBOX_16_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_16_2]] : North, %[[SWITCHBOX_16_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_15_4]] : East, %[[SWITCHBOX_16_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_16_4]] : Core, %[[SWITCHBOX_16_4]] : Core) -// CHECK: aie.wire(%[[TILE_16_4]] : DMA, %[[SWITCHBOX_16_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_16_3]] : North, %[[SWITCHBOX_16_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_15_5]] : East, %[[SWITCHBOX_16_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_16_5]] : Core, %[[SWITCHBOX_16_5]] : Core) -// CHECK: aie.wire(%[[TILE_16_5]] : DMA, %[[SWITCHBOX_16_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_16_4]] : North, %[[SWITCHBOX_16_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_16_0]] : East, %[[SWITCHBOX_17_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_16_1]] : East, %[[SWITCHBOX_17_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_17_1]] : Core, %[[SWITCHBOX_17_1]] : Core) -// CHECK: aie.wire(%[[TILE_17_1]] : DMA, %[[SWITCHBOX_17_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_17_0]] : North, %[[SWITCHBOX_17_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_16_2]] : East, %[[SWITCHBOX_17_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_17_2]] : Core, %[[SWITCHBOX_17_2]] : Core) -// CHECK: aie.wire(%[[TILE_17_2]] : DMA, %[[SWITCHBOX_17_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_17_1]] : North, %[[SWITCHBOX_17_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_16_3]] : East, %[[SWITCHBOX_17_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_17_3]] : Core, %[[SWITCHBOX_17_3]] : Core) -// CHECK: aie.wire(%[[TILE_17_3]] : DMA, %[[SWITCHBOX_17_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_17_2]] : North, %[[SWITCHBOX_17_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_16_4]] : East, %[[SWITCHBOX_17_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_17_4]] : Core, %[[SWITCHBOX_17_4]] : Core) -// CHECK: aie.wire(%[[TILE_17_4]] : DMA, %[[SWITCHBOX_17_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_17_3]] : North, %[[SWITCHBOX_17_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_16_5]] : East, %[[SWITCHBOX_17_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_17_5]] : Core, %[[SWITCHBOX_17_5]] : Core) -// CHECK: aie.wire(%[[TILE_17_5]] : DMA, %[[SWITCHBOX_17_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_17_4]] : North, %[[SWITCHBOX_17_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_17_0]] : East, %[[SWITCHBOX_18_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_18_0:.*]] : North, %[[SWITCHBOX_18_0]] : South) -// CHECK: aie.wire(%[[TILE_18_0]] : DMA, %[[SHIM_MUX_18_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_17_1]] : East, %[[SWITCHBOX_18_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_18_1]] : Core, %[[SWITCHBOX_18_1]] : Core) -// CHECK: aie.wire(%[[TILE_18_1]] : DMA, %[[SWITCHBOX_18_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_18_0]] : North, %[[SWITCHBOX_18_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_17_2]] : East, %[[SWITCHBOX_18_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_18_2]] : Core, %[[SWITCHBOX_18_2]] : Core) -// CHECK: aie.wire(%[[TILE_18_2]] : DMA, %[[SWITCHBOX_18_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_18_1]] : North, %[[SWITCHBOX_18_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_17_3]] : East, %[[SWITCHBOX_18_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_18_3]] : Core, %[[SWITCHBOX_18_3]] : Core) -// CHECK: aie.wire(%[[TILE_18_3]] : DMA, %[[SWITCHBOX_18_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_18_2]] : North, %[[SWITCHBOX_18_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_17_4]] : East, %[[SWITCHBOX_18_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_18_4]] : Core, %[[SWITCHBOX_18_4]] : Core) -// CHECK: aie.wire(%[[TILE_18_4]] : DMA, %[[SWITCHBOX_18_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_18_3]] : North, %[[SWITCHBOX_18_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_17_5]] : East, %[[SWITCHBOX_18_5:.*]] : West) -// CHECK: aie.wire(%[[TILE_18_5]] : Core, %[[SWITCHBOX_18_5]] : Core) -// CHECK: aie.wire(%[[TILE_18_5]] : DMA, %[[SWITCHBOX_18_5]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_18_4]] : North, %[[SWITCHBOX_18_5]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_18_0]] : East, %[[SWITCHBOX_19_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_19_0:.*]] : North, %[[SWITCHBOX_19_0]] : South) -// CHECK: aie.wire(%[[TILE_19_0]] : DMA, %[[SHIM_MUX_19_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_18_1]] : East, %[[SWITCHBOX_19_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_19_1]] : Core, %[[SWITCHBOX_19_1]] : Core) -// CHECK: aie.wire(%[[TILE_19_1]] : DMA, %[[SWITCHBOX_19_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_19_0]] : North, %[[SWITCHBOX_19_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_18_2]] : East, %[[SWITCHBOX_19_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_19_2]] : Core, %[[SWITCHBOX_19_2]] : Core) -// CHECK: aie.wire(%[[TILE_19_2]] : DMA, %[[SWITCHBOX_19_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_19_1]] : North, %[[SWITCHBOX_19_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_18_3]] : East, %[[SWITCHBOX_19_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_19_3]] : Core, %[[SWITCHBOX_19_3]] : Core) -// CHECK: aie.wire(%[[TILE_19_3]] : DMA, %[[SWITCHBOX_19_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_19_2]] : North, %[[SWITCHBOX_19_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_18_4]] : East, %[[SWITCHBOX_19_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_19_4]] : Core, %[[SWITCHBOX_19_4]] : Core) -// CHECK: aie.wire(%[[TILE_19_4]] : DMA, %[[SWITCHBOX_19_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_19_3]] : North, %[[SWITCHBOX_19_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_19_0]] : East, %[[SWITCHBOX_20_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_19_1]] : East, %[[SWITCHBOX_20_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_20_1]] : Core, %[[SWITCHBOX_20_1]] : Core) -// CHECK: aie.wire(%[[TILE_20_1]] : DMA, %[[SWITCHBOX_20_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_20_0]] : North, %[[SWITCHBOX_20_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_19_2]] : East, %[[SWITCHBOX_20_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_20_2]] : Core, %[[SWITCHBOX_20_2]] : Core) -// CHECK: aie.wire(%[[TILE_20_2]] : DMA, %[[SWITCHBOX_20_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_20_1]] : North, %[[SWITCHBOX_20_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_19_3]] : East, %[[SWITCHBOX_20_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_20_3]] : Core, %[[SWITCHBOX_20_3]] : Core) -// CHECK: aie.wire(%[[TILE_20_3]] : DMA, %[[SWITCHBOX_20_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_20_2]] : North, %[[SWITCHBOX_20_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_19_4]] : East, %[[SWITCHBOX_20_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_20_4]] : Core, %[[SWITCHBOX_20_4]] : Core) -// CHECK: aie.wire(%[[TILE_20_4]] : DMA, %[[SWITCHBOX_20_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_20_3]] : North, %[[SWITCHBOX_20_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_20_0]] : East, %[[SWITCHBOX_21_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_20_1]] : East, %[[SWITCHBOX_21_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_21_1]] : Core, %[[SWITCHBOX_21_1]] : Core) -// CHECK: aie.wire(%[[TILE_21_1]] : DMA, %[[SWITCHBOX_21_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_21_0]] : North, %[[SWITCHBOX_21_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_20_2]] : East, %[[SWITCHBOX_21_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_21_2]] : Core, %[[SWITCHBOX_21_2]] : Core) -// CHECK: aie.wire(%[[TILE_21_2]] : DMA, %[[SWITCHBOX_21_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_21_1]] : North, %[[SWITCHBOX_21_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_20_3]] : East, %[[SWITCHBOX_21_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_21_3]] : Core, %[[SWITCHBOX_21_3]] : Core) -// CHECK: aie.wire(%[[TILE_21_3]] : DMA, %[[SWITCHBOX_21_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_21_2]] : North, %[[SWITCHBOX_21_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_20_4]] : East, %[[SWITCHBOX_21_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_21_4]] : Core, %[[SWITCHBOX_21_4]] : Core) -// CHECK: aie.wire(%[[TILE_21_4]] : DMA, %[[SWITCHBOX_21_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_21_3]] : North, %[[SWITCHBOX_21_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_21_0]] : East, %[[SWITCHBOX_22_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_21_1]] : East, %[[SWITCHBOX_22_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_22_1]] : Core, %[[SWITCHBOX_22_1]] : Core) -// CHECK: aie.wire(%[[TILE_22_1]] : DMA, %[[SWITCHBOX_22_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_22_0]] : North, %[[SWITCHBOX_22_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_21_2]] : East, %[[SWITCHBOX_22_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_22_2]] : Core, %[[SWITCHBOX_22_2]] : Core) -// CHECK: aie.wire(%[[TILE_22_2]] : DMA, %[[SWITCHBOX_22_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_22_1]] : North, %[[SWITCHBOX_22_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_21_3]] : East, %[[SWITCHBOX_22_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_22_3]] : Core, %[[SWITCHBOX_22_3]] : Core) -// CHECK: aie.wire(%[[TILE_22_3]] : DMA, %[[SWITCHBOX_22_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_22_2]] : North, %[[SWITCHBOX_22_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_21_4]] : East, %[[SWITCHBOX_22_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_22_4]] : Core, %[[SWITCHBOX_22_4]] : Core) -// CHECK: aie.wire(%[[TILE_22_4]] : DMA, %[[SWITCHBOX_22_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_22_3]] : North, %[[SWITCHBOX_22_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_22_0]] : East, %[[SWITCHBOX_23_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_22_1]] : East, %[[SWITCHBOX_23_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_23_1]] : Core, %[[SWITCHBOX_23_1]] : Core) -// CHECK: aie.wire(%[[TILE_23_1]] : DMA, %[[SWITCHBOX_23_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_23_0]] : North, %[[SWITCHBOX_23_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_22_2]] : East, %[[SWITCHBOX_23_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_23_2]] : Core, %[[SWITCHBOX_23_2]] : Core) -// CHECK: aie.wire(%[[TILE_23_2]] : DMA, %[[SWITCHBOX_23_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_23_1]] : North, %[[SWITCHBOX_23_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_22_3]] : East, %[[SWITCHBOX_23_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_23_3]] : Core, %[[SWITCHBOX_23_3]] : Core) -// CHECK: aie.wire(%[[TILE_23_3]] : DMA, %[[SWITCHBOX_23_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_23_2]] : North, %[[SWITCHBOX_23_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_22_4]] : East, %[[SWITCHBOX_23_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_23_4]] : Core, %[[SWITCHBOX_23_4]] : Core) -// CHECK: aie.wire(%[[TILE_23_4]] : DMA, %[[SWITCHBOX_23_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_23_3]] : North, %[[SWITCHBOX_23_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_23_0]] : East, %[[SWITCHBOX_24_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_23_1]] : East, %[[SWITCHBOX_24_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_24_1]] : Core, %[[SWITCHBOX_24_1]] : Core) -// CHECK: aie.wire(%[[TILE_24_1]] : DMA, %[[SWITCHBOX_24_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_24_0]] : North, %[[SWITCHBOX_24_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_23_2]] : East, %[[SWITCHBOX_24_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_24_2]] : Core, %[[SWITCHBOX_24_2]] : Core) -// CHECK: aie.wire(%[[TILE_24_2]] : DMA, %[[SWITCHBOX_24_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_24_1]] : North, %[[SWITCHBOX_24_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_23_3]] : East, %[[SWITCHBOX_24_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_24_3]] : Core, %[[SWITCHBOX_24_3]] : Core) -// CHECK: aie.wire(%[[TILE_24_3]] : DMA, %[[SWITCHBOX_24_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_24_2]] : North, %[[SWITCHBOX_24_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_23_4]] : East, %[[SWITCHBOX_24_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_24_4]] : Core, %[[SWITCHBOX_24_4]] : Core) -// CHECK: aie.wire(%[[TILE_24_4]] : DMA, %[[SWITCHBOX_24_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_24_3]] : North, %[[SWITCHBOX_24_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_24_0]] : East, %[[SWITCHBOX_25_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_24_1]] : East, %[[SWITCHBOX_25_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_25_1]] : Core, %[[SWITCHBOX_25_1]] : Core) -// CHECK: aie.wire(%[[TILE_25_1]] : DMA, %[[SWITCHBOX_25_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_25_0]] : North, %[[SWITCHBOX_25_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_24_2]] : East, %[[SWITCHBOX_25_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_25_2]] : Core, %[[SWITCHBOX_25_2]] : Core) -// CHECK: aie.wire(%[[TILE_25_2]] : DMA, %[[SWITCHBOX_25_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_25_1]] : North, %[[SWITCHBOX_25_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_24_3]] : East, %[[SWITCHBOX_25_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_25_3]] : Core, %[[SWITCHBOX_25_3]] : Core) -// CHECK: aie.wire(%[[TILE_25_3]] : DMA, %[[SWITCHBOX_25_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_25_2]] : North, %[[SWITCHBOX_25_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_24_4]] : East, %[[SWITCHBOX_25_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_25_4]] : Core, %[[SWITCHBOX_25_4]] : Core) -// CHECK: aie.wire(%[[TILE_25_4]] : DMA, %[[SWITCHBOX_25_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_25_3]] : North, %[[SWITCHBOX_25_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_25_0]] : East, %[[SWITCHBOX_26_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_26_0:.*]] : North, %[[SWITCHBOX_26_0]] : South) -// CHECK: aie.wire(%[[TILE_26_0]] : DMA, %[[SHIM_MUX_26_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_25_1]] : East, %[[SWITCHBOX_26_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_26_1]] : Core, %[[SWITCHBOX_26_1]] : Core) -// CHECK: aie.wire(%[[TILE_26_1]] : DMA, %[[SWITCHBOX_26_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_26_0]] : North, %[[SWITCHBOX_26_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_25_2]] : East, %[[SWITCHBOX_26_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_26_2]] : Core, %[[SWITCHBOX_26_2]] : Core) -// CHECK: aie.wire(%[[TILE_26_2]] : DMA, %[[SWITCHBOX_26_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_26_1]] : North, %[[SWITCHBOX_26_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_25_3]] : East, %[[SWITCHBOX_26_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_26_3]] : Core, %[[SWITCHBOX_26_3]] : Core) -// CHECK: aie.wire(%[[TILE_26_3]] : DMA, %[[SWITCHBOX_26_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_26_2]] : North, %[[SWITCHBOX_26_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_25_4]] : East, %[[SWITCHBOX_26_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_26_4]] : Core, %[[SWITCHBOX_26_4]] : Core) -// CHECK: aie.wire(%[[TILE_26_4]] : DMA, %[[SWITCHBOX_26_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_26_3]] : North, %[[SWITCHBOX_26_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_26_0]] : East, %[[SWITCHBOX_27_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_27_0:.*]] : North, %[[SWITCHBOX_27_0]] : South) -// CHECK: aie.wire(%[[TILE_27_0]] : DMA, %[[SHIM_MUX_27_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_26_1]] : East, %[[SWITCHBOX_27_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_27_1]] : Core, %[[SWITCHBOX_27_1]] : Core) -// CHECK: aie.wire(%[[TILE_27_1]] : DMA, %[[SWITCHBOX_27_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_27_0]] : North, %[[SWITCHBOX_27_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_26_2]] : East, %[[SWITCHBOX_27_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_27_2]] : Core, %[[SWITCHBOX_27_2]] : Core) -// CHECK: aie.wire(%[[TILE_27_2]] : DMA, %[[SWITCHBOX_27_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_27_1]] : North, %[[SWITCHBOX_27_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_26_4]] : East, %[[SWITCHBOX_27_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_27_4]] : Core, %[[SWITCHBOX_27_4]] : Core) -// CHECK: aie.wire(%[[TILE_27_4]] : DMA, %[[SWITCHBOX_27_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_27_0]] : East, %[[SWITCHBOX_28_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_27_1]] : East, %[[SWITCHBOX_28_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_28_1]] : Core, %[[SWITCHBOX_28_1]] : Core) -// CHECK: aie.wire(%[[TILE_28_1]] : DMA, %[[SWITCHBOX_28_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_28_0]] : North, %[[SWITCHBOX_28_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_27_2]] : East, %[[SWITCHBOX_28_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_28_2]] : Core, %[[SWITCHBOX_28_2]] : Core) -// CHECK: aie.wire(%[[TILE_28_2]] : DMA, %[[SWITCHBOX_28_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_28_1]] : North, %[[SWITCHBOX_28_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_27_4]] : East, %[[SWITCHBOX_28_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_28_4]] : Core, %[[SWITCHBOX_28_4]] : Core) -// CHECK: aie.wire(%[[TILE_28_4]] : DMA, %[[SWITCHBOX_28_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_28_0]] : East, %[[SWITCHBOX_29_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_28_1]] : East, %[[SWITCHBOX_29_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_29_1]] : Core, %[[SWITCHBOX_29_1]] : Core) -// CHECK: aie.wire(%[[TILE_29_1]] : DMA, %[[SWITCHBOX_29_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_29_0]] : North, %[[SWITCHBOX_29_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_28_2]] : East, %[[SWITCHBOX_29_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_29_2]] : Core, %[[SWITCHBOX_29_2]] : Core) -// CHECK: aie.wire(%[[TILE_29_2]] : DMA, %[[SWITCHBOX_29_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_29_1]] : North, %[[SWITCHBOX_29_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_28_4]] : East, %[[SWITCHBOX_29_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_29_4]] : Core, %[[SWITCHBOX_29_4]] : Core) -// CHECK: aie.wire(%[[TILE_29_4]] : DMA, %[[SWITCHBOX_29_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_29_0]] : East, %[[SWITCHBOX_30_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_29_1]] : East, %[[SWITCHBOX_30_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_30_1]] : Core, %[[SWITCHBOX_30_1]] : Core) -// CHECK: aie.wire(%[[TILE_30_1]] : DMA, %[[SWITCHBOX_30_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_30_0]] : North, %[[SWITCHBOX_30_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_29_2]] : East, %[[SWITCHBOX_30_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_30_2]] : Core, %[[SWITCHBOX_30_2]] : Core) -// CHECK: aie.wire(%[[TILE_30_2]] : DMA, %[[SWITCHBOX_30_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_30_1]] : North, %[[SWITCHBOX_30_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_29_4]] : East, %[[SWITCHBOX_30_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_30_4]] : Core, %[[SWITCHBOX_30_4]] : Core) -// CHECK: aie.wire(%[[TILE_30_4]] : DMA, %[[SWITCHBOX_30_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_30_0]] : East, %[[SWITCHBOX_31_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_30_1]] : East, %[[SWITCHBOX_31_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_31_1]] : Core, %[[SWITCHBOX_31_1]] : Core) -// CHECK: aie.wire(%[[TILE_31_1]] : DMA, %[[SWITCHBOX_31_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_31_0]] : North, %[[SWITCHBOX_31_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_30_2]] : East, %[[SWITCHBOX_31_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_31_2]] : Core, %[[SWITCHBOX_31_2]] : Core) -// CHECK: aie.wire(%[[TILE_31_2]] : DMA, %[[SWITCHBOX_31_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_31_1]] : North, %[[SWITCHBOX_31_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_30_4]] : East, %[[SWITCHBOX_31_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_31_4]] : Core, %[[SWITCHBOX_31_4]] : Core) -// CHECK: aie.wire(%[[TILE_31_4]] : DMA, %[[SWITCHBOX_31_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_31_0]] : East, %[[SWITCHBOX_32_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_31_1]] : East, %[[SWITCHBOX_32_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_32_1]] : Core, %[[SWITCHBOX_32_1]] : Core) -// CHECK: aie.wire(%[[TILE_32_1]] : DMA, %[[SWITCHBOX_32_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_32_0]] : North, %[[SWITCHBOX_32_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_31_2]] : East, %[[SWITCHBOX_32_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_32_2]] : Core, %[[SWITCHBOX_32_2]] : Core) -// CHECK: aie.wire(%[[TILE_32_2]] : DMA, %[[SWITCHBOX_32_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_32_1]] : North, %[[SWITCHBOX_32_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_31_4]] : East, %[[SWITCHBOX_32_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_32_4]] : Core, %[[SWITCHBOX_32_4]] : Core) -// CHECK: aie.wire(%[[TILE_32_4]] : DMA, %[[SWITCHBOX_32_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_32_0]] : East, %[[SWITCHBOX_33_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_32_1]] : East, %[[SWITCHBOX_33_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_33_1]] : Core, %[[SWITCHBOX_33_1]] : Core) -// CHECK: aie.wire(%[[TILE_33_1]] : DMA, %[[SWITCHBOX_33_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_33_0]] : North, %[[SWITCHBOX_33_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_32_2]] : East, %[[SWITCHBOX_33_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_33_2]] : Core, %[[SWITCHBOX_33_2]] : Core) -// CHECK: aie.wire(%[[TILE_33_2]] : DMA, %[[SWITCHBOX_33_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_33_1]] : North, %[[SWITCHBOX_33_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_32_4]] : East, %[[SWITCHBOX_33_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_33_4]] : Core, %[[SWITCHBOX_33_4]] : Core) -// CHECK: aie.wire(%[[TILE_33_4]] : DMA, %[[SWITCHBOX_33_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_33_0]] : East, %[[SWITCHBOX_34_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_34_0:.*]] : North, %[[SWITCHBOX_34_0]] : South) -// CHECK: aie.wire(%[[TILE_34_0]] : DMA, %[[SHIM_MUX_34_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_33_1]] : East, %[[SWITCHBOX_34_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_34_1]] : Core, %[[SWITCHBOX_34_1]] : Core) -// CHECK: aie.wire(%[[TILE_34_1]] : DMA, %[[SWITCHBOX_34_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_34_0]] : North, %[[SWITCHBOX_34_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_33_2]] : East, %[[SWITCHBOX_34_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_34_2]] : Core, %[[SWITCHBOX_34_2]] : Core) -// CHECK: aie.wire(%[[TILE_34_2]] : DMA, %[[SWITCHBOX_34_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_34_1]] : North, %[[SWITCHBOX_34_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_33_4]] : East, %[[SWITCHBOX_34_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_34_4]] : Core, %[[SWITCHBOX_34_4]] : Core) -// CHECK: aie.wire(%[[TILE_34_4]] : DMA, %[[SWITCHBOX_34_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_34_0]] : East, %[[SWITCHBOX_35_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_35_0:.*]] : North, %[[SWITCHBOX_35_0]] : South) -// CHECK: aie.wire(%[[TILE_35_0]] : DMA, %[[SHIM_MUX_35_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_34_1]] : East, %[[SWITCHBOX_35_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_35_1]] : Core, %[[SWITCHBOX_35_1]] : Core) -// CHECK: aie.wire(%[[TILE_35_1]] : DMA, %[[SWITCHBOX_35_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_35_0]] : North, %[[SWITCHBOX_35_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_34_2]] : East, %[[SWITCHBOX_35_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_35_2]] : Core, %[[SWITCHBOX_35_2]] : Core) -// CHECK: aie.wire(%[[TILE_35_2]] : DMA, %[[SWITCHBOX_35_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_35_1]] : North, %[[SWITCHBOX_35_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_34_4]] : East, %[[SWITCHBOX_35_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_35_4]] : Core, %[[SWITCHBOX_35_4]] : Core) -// CHECK: aie.wire(%[[TILE_35_4]] : DMA, %[[SWITCHBOX_35_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_35_0]] : East, %[[SWITCHBOX_36_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_35_2]] : East, %[[SWITCHBOX_36_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_36_2]] : Core, %[[SWITCHBOX_36_2]] : Core) -// CHECK: aie.wire(%[[TILE_36_2]] : DMA, %[[SWITCHBOX_36_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_35_4]] : East, %[[SWITCHBOX_36_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_36_4]] : Core, %[[SWITCHBOX_36_4]] : Core) -// CHECK: aie.wire(%[[TILE_36_4]] : DMA, %[[SWITCHBOX_36_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_36_0]] : East, %[[SWITCHBOX_37_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_36_2]] : East, %[[SWITCHBOX_37_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_37_2]] : Core, %[[SWITCHBOX_37_2]] : Core) -// CHECK: aie.wire(%[[TILE_37_2]] : DMA, %[[SWITCHBOX_37_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_36_4]] : East, %[[SWITCHBOX_37_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_37_4]] : Core, %[[SWITCHBOX_37_4]] : Core) -// CHECK: aie.wire(%[[TILE_37_4]] : DMA, %[[SWITCHBOX_37_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_37_0]] : East, %[[SWITCHBOX_38_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_37_2]] : East, %[[SWITCHBOX_38_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_38_2]] : Core, %[[SWITCHBOX_38_2]] : Core) -// CHECK: aie.wire(%[[TILE_38_2]] : DMA, %[[SWITCHBOX_38_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_37_4]] : East, %[[SWITCHBOX_38_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_38_4]] : Core, %[[SWITCHBOX_38_4]] : Core) -// CHECK: aie.wire(%[[TILE_38_4]] : DMA, %[[SWITCHBOX_38_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_38_0]] : East, %[[SWITCHBOX_39_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_38_2]] : East, %[[SWITCHBOX_39_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_39_2]] : Core, %[[SWITCHBOX_39_2]] : Core) -// CHECK: aie.wire(%[[TILE_39_2]] : DMA, %[[SWITCHBOX_39_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_38_4]] : East, %[[SWITCHBOX_39_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_39_4]] : Core, %[[SWITCHBOX_39_4]] : Core) -// CHECK: aie.wire(%[[TILE_39_4]] : DMA, %[[SWITCHBOX_39_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_39_0]] : East, %[[SWITCHBOX_40_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_39_2]] : East, %[[SWITCHBOX_40_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_40_2]] : Core, %[[SWITCHBOX_40_2]] : Core) -// CHECK: aie.wire(%[[TILE_40_2]] : DMA, %[[SWITCHBOX_40_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_39_4]] : East, %[[SWITCHBOX_40_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_40_4]] : Core, %[[SWITCHBOX_40_4]] : Core) -// CHECK: aie.wire(%[[TILE_40_4]] : DMA, %[[SWITCHBOX_40_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_40_0]] : East, %[[SWITCHBOX_41_0:.*]] : West) -// CHECK: aie.wire(%[[TILE_41_1]] : Core, %[[SWITCHBOX_41_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_41_1]] : DMA, %[[SWITCHBOX_41_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_41_0]] : North, %[[SWITCHBOX_41_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_40_2]] : East, %[[SWITCHBOX_41_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_41_2]] : Core, %[[SWITCHBOX_41_2]] : Core) -// CHECK: aie.wire(%[[TILE_41_2]] : DMA, %[[SWITCHBOX_41_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_41_1]] : North, %[[SWITCHBOX_41_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_40_4]] : East, %[[SWITCHBOX_41_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_41_4]] : Core, %[[SWITCHBOX_41_4]] : Core) -// CHECK: aie.wire(%[[TILE_41_4]] : DMA, %[[SWITCHBOX_41_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_41_0]] : East, %[[SWITCHBOX_42_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_42_0:.*]] : North, %[[SWITCHBOX_42_0]] : South) -// CHECK: aie.wire(%[[TILE_42_0]] : DMA, %[[SHIM_MUX_42_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_41_1]] : East, %[[SWITCHBOX_42_1:.*]] : West) -// CHECK: aie.wire(%[[TILE_42_1]] : Core, %[[SWITCHBOX_42_1]] : Core) -// CHECK: aie.wire(%[[TILE_42_1]] : DMA, %[[SWITCHBOX_42_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_42_0]] : North, %[[SWITCHBOX_42_1]] : South) -// CHECK: aie.wire(%[[TILE_42_3]] : Core, %[[SWITCHBOX_42_3:.*]] : Core) -// CHECK: aie.wire(%[[TILE_42_3]] : DMA, %[[SWITCHBOX_42_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_41_4]] : East, %[[SWITCHBOX_42_4:.*]] : West) -// CHECK: aie.wire(%[[TILE_42_4]] : Core, %[[SWITCHBOX_42_4]] : Core) -// CHECK: aie.wire(%[[TILE_42_4]] : DMA, %[[SWITCHBOX_42_4]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_42_3]] : North, %[[SWITCHBOX_42_4]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_42_0]] : East, %[[SWITCHBOX_43_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_43_0:.*]] : North, %[[SWITCHBOX_43_0]] : South) -// CHECK: aie.wire(%[[TILE_43_0]] : DMA, %[[SHIM_MUX_43_0]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_42_3]] : East, %[[SWITCHBOX_43_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_43_3]] : Core, %[[SWITCHBOX_43_3]] : Core) -// CHECK: aie.wire(%[[TILE_43_3]] : DMA, %[[SWITCHBOX_43_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_43_0]] : East, %[[SWITCHBOX_44_0:.*]] : West) -// CHECK: aie.wire(%[[SWITCHBOX_43_3]] : East, %[[SWITCHBOX_44_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_44_3]] : Core, %[[SWITCHBOX_44_3]] : Core) -// CHECK: aie.wire(%[[TILE_44_3]] : DMA, %[[SWITCHBOX_44_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_44_0]] : East, %[[SWITCHBOX_45_0:.*]] : West) -// CHECK: aie.wire(%[[TILE_45_2]] : Core, %[[SWITCHBOX_45_2:.*]] : Core) -// CHECK: aie.wire(%[[TILE_45_2]] : DMA, %[[SWITCHBOX_45_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_44_3]] : East, %[[SWITCHBOX_45_3:.*]] : West) -// CHECK: aie.wire(%[[TILE_45_3]] : Core, %[[SWITCHBOX_45_3]] : Core) -// CHECK: aie.wire(%[[TILE_45_3]] : DMA, %[[SWITCHBOX_45_3]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_45_2]] : North, %[[SWITCHBOX_45_3]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_45_0]] : East, %[[SWITCHBOX_46_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_46_0:.*]] : North, %[[SWITCHBOX_46_0]] : South) -// CHECK: aie.wire(%[[TILE_46_0]] : DMA, %[[SHIM_MUX_46_0]] : DMA) -// CHECK: aie.wire(%[[TILE_46_1]] : Core, %[[SWITCHBOX_46_1:.*]] : Core) -// CHECK: aie.wire(%[[TILE_46_1]] : DMA, %[[SWITCHBOX_46_1]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_46_0]] : North, %[[SWITCHBOX_46_1]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_45_2]] : East, %[[SWITCHBOX_46_2:.*]] : West) -// CHECK: aie.wire(%[[TILE_46_2]] : Core, %[[SWITCHBOX_46_2]] : Core) -// CHECK: aie.wire(%[[TILE_46_2]] : DMA, %[[SWITCHBOX_46_2]] : DMA) -// CHECK: aie.wire(%[[SWITCHBOX_46_1]] : North, %[[SWITCHBOX_46_2]] : South) -// CHECK: aie.wire(%[[SWITCHBOX_46_0]] : East, %[[SWITCHBOX_47_0:.*]] : West) -// CHECK: aie.wire(%[[SHIM_MUX_47_0:.*]] : North, %[[SWITCHBOX_47_0]] : South) -// CHECK: aie.wire(%[[TILE_47_0]] : DMA, %[[SHIM_MUX_47_0]] : DMA) -// CHECK: } - -module @vecmul_4x4 { - aie.device(xcvc1902) { - %0 = aie.tile(47, 2) - %1 = aie.tile(47, 1) - %2 = aie.tile(47, 0) - %3 = aie.tile(3, 3) - %4 = aie.tile(10, 5) - %5 = aie.lock(%4, 2) - %6 = aie.buffer(%4) {sym_name = "buf47"} : memref<64xi32, 2> - %7 = aie.lock(%4, 1) - %8 = aie.buffer(%4) {sym_name = "buf46"} : memref<64xi32, 2> - %9 = aie.lock(%4, 0) - %10 = aie.buffer(%4) {sym_name = "buf45"} : memref<64xi32, 2> - %11 = aie.mem(%4) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%9, Acquire, 0) - aie.dma_bd(%10 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%9, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%7, Acquire, 0) - aie.dma_bd(%8 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%7, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%5, Acquire, 1) - aie.dma_bd(%6 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%5, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %12 = aie.core(%4) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%9, Acquire, 1) - aie.use_lock(%7, Acquire, 1) - aie.use_lock(%5, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %10[%arg0] : memref<64xi32, 2> - %201 = affine.load %8[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %6[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%5, Release, 1) - aie.use_lock(%7, Release, 0) - aie.use_lock(%9, Release, 0) - cf.br ^bb1 - } - %13 = aie.tile(46, 2) - %14 = aie.tile(46, 1) - %15 = aie.tile(46, 0) - %16 = aie.tile(2, 3) - %17 = aie.tile(9, 5) - %18 = aie.lock(%17, 2) - %19 = aie.buffer(%17) {sym_name = "buf44"} : memref<64xi32, 2> - %20 = aie.lock(%17, 1) - %21 = aie.buffer(%17) {sym_name = "buf43"} : memref<64xi32, 2> - %22 = aie.lock(%17, 0) - %23 = aie.buffer(%17) {sym_name = "buf42"} : memref<64xi32, 2> - %24 = aie.mem(%17) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%22, Acquire, 0) - aie.dma_bd(%23 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%22, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%20, Acquire, 0) - aie.dma_bd(%21 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%20, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%18, Acquire, 1) - aie.dma_bd(%19 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%18, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %25 = aie.core(%17) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%22, Acquire, 1) - aie.use_lock(%20, Acquire, 1) - aie.use_lock(%18, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %23[%arg0] : memref<64xi32, 2> - %201 = affine.load %21[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %19[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%18, Release, 1) - aie.use_lock(%20, Release, 0) - aie.use_lock(%22, Release, 0) - cf.br ^bb1 - } - %26 = aie.tile(43, 2) - %27 = aie.tile(43, 1) - %28 = aie.tile(43, 0) - %29 = aie.tile(1, 3) - %30 = aie.tile(8, 5) - %31 = aie.lock(%30, 2) - %32 = aie.buffer(%30) {sym_name = "buf41"} : memref<64xi32, 2> - %33 = aie.lock(%30, 1) - %34 = aie.buffer(%30) {sym_name = "buf40"} : memref<64xi32, 2> - %35 = aie.lock(%30, 0) - %36 = aie.buffer(%30) {sym_name = "buf39"} : memref<64xi32, 2> - %37 = aie.mem(%30) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%35, Acquire, 0) - aie.dma_bd(%36 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%35, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%33, Acquire, 0) - aie.dma_bd(%34 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%33, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%31, Acquire, 1) - aie.dma_bd(%32 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%31, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %38 = aie.core(%30) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%35, Acquire, 1) - aie.use_lock(%33, Acquire, 1) - aie.use_lock(%31, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %36[%arg0] : memref<64xi32, 2> - %201 = affine.load %34[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %32[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%31, Release, 1) - aie.use_lock(%33, Release, 0) - aie.use_lock(%35, Release, 0) - cf.br ^bb1 - } - %39 = aie.tile(42, 2) - %40 = aie.tile(42, 1) - %41 = aie.tile(42, 0) - %42 = aie.tile(0, 3) - %43 = aie.tile(7, 5) - %44 = aie.lock(%43, 2) - %45 = aie.buffer(%43) {sym_name = "buf38"} : memref<64xi32, 2> - %46 = aie.lock(%43, 1) - %47 = aie.buffer(%43) {sym_name = "buf37"} : memref<64xi32, 2> - %48 = aie.lock(%43, 0) - %49 = aie.buffer(%43) {sym_name = "buf36"} : memref<64xi32, 2> - %50 = aie.mem(%43) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%48, Acquire, 0) - aie.dma_bd(%49 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%48, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%46, Acquire, 0) - aie.dma_bd(%47 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%46, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%44, Acquire, 1) - aie.dma_bd(%45 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%44, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %51 = aie.core(%43) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%48, Acquire, 1) - aie.use_lock(%46, Acquire, 1) - aie.use_lock(%44, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %49[%arg0] : memref<64xi32, 2> - %201 = affine.load %47[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %45[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%44, Release, 1) - aie.use_lock(%46, Release, 0) - aie.use_lock(%48, Release, 0) - cf.br ^bb1 - } - %52 = aie.tile(35, 2) - %53 = aie.tile(35, 1) - %54 = aie.tile(35, 0) - %55 = aie.tile(10, 4) - %56 = aie.lock(%55, 2) - %57 = aie.buffer(%55) {sym_name = "buf35"} : memref<64xi32, 2> - %58 = aie.lock(%55, 1) - %59 = aie.buffer(%55) {sym_name = "buf34"} : memref<64xi32, 2> - %60 = aie.lock(%55, 0) - %61 = aie.buffer(%55) {sym_name = "buf33"} : memref<64xi32, 2> - %62 = aie.mem(%55) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%60, Acquire, 0) - aie.dma_bd(%61 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%60, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%58, Acquire, 0) - aie.dma_bd(%59 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%58, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%56, Acquire, 1) - aie.dma_bd(%57 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%56, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %63 = aie.core(%55) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%60, Acquire, 1) - aie.use_lock(%58, Acquire, 1) - aie.use_lock(%56, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %61[%arg0] : memref<64xi32, 2> - %201 = affine.load %59[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %57[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%56, Release, 1) - aie.use_lock(%58, Release, 0) - aie.use_lock(%60, Release, 0) - cf.br ^bb1 - } - %64 = aie.tile(34, 2) - %65 = aie.tile(34, 1) - %66 = aie.tile(34, 0) - %67 = aie.tile(9, 4) - %68 = aie.lock(%67, 2) - %69 = aie.buffer(%67) {sym_name = "buf32"} : memref<64xi32, 2> - %70 = aie.lock(%67, 1) - %71 = aie.buffer(%67) {sym_name = "buf31"} : memref<64xi32, 2> - %72 = aie.lock(%67, 0) - %73 = aie.buffer(%67) {sym_name = "buf30"} : memref<64xi32, 2> - %74 = aie.mem(%67) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%72, Acquire, 0) - aie.dma_bd(%73 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%72, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%70, Acquire, 0) - aie.dma_bd(%71 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%70, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%68, Acquire, 1) - aie.dma_bd(%69 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%68, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %75 = aie.core(%67) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%72, Acquire, 1) - aie.use_lock(%70, Acquire, 1) - aie.use_lock(%68, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %73[%arg0] : memref<64xi32, 2> - %201 = affine.load %71[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %69[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%68, Release, 1) - aie.use_lock(%70, Release, 0) - aie.use_lock(%72, Release, 0) - cf.br ^bb1 - } - %76 = aie.tile(27, 2) - %77 = aie.tile(27, 1) - %78 = aie.tile(27, 0) - %79 = aie.tile(1, 2) - %80 = aie.tile(8, 4) - %81 = aie.lock(%80, 2) - %82 = aie.buffer(%80) {sym_name = "buf29"} : memref<64xi32, 2> - %83 = aie.lock(%80, 1) - %84 = aie.buffer(%80) {sym_name = "buf28"} : memref<64xi32, 2> - %85 = aie.lock(%80, 0) - %86 = aie.buffer(%80) {sym_name = "buf27"} : memref<64xi32, 2> - %87 = aie.mem(%80) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%85, Acquire, 0) - aie.dma_bd(%86 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%85, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%83, Acquire, 0) - aie.dma_bd(%84 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%83, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%81, Acquire, 1) - aie.dma_bd(%82 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%81, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %88 = aie.core(%80) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%85, Acquire, 1) - aie.use_lock(%83, Acquire, 1) - aie.use_lock(%81, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %86[%arg0] : memref<64xi32, 2> - %201 = affine.load %84[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %82[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%81, Release, 1) - aie.use_lock(%83, Release, 0) - aie.use_lock(%85, Release, 0) - cf.br ^bb1 - } - %89 = aie.tile(26, 2) - %90 = aie.tile(26, 1) - %91 = aie.tile(26, 0) - %92 = aie.tile(0, 2) - %93 = aie.tile(7, 4) - %94 = aie.lock(%93, 2) - %95 = aie.buffer(%93) {sym_name = "buf26"} : memref<64xi32, 2> - %96 = aie.lock(%93, 1) - %97 = aie.buffer(%93) {sym_name = "buf25"} : memref<64xi32, 2> - %98 = aie.lock(%93, 0) - %99 = aie.buffer(%93) {sym_name = "buf24"} : memref<64xi32, 2> - %100 = aie.mem(%93) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%98, Acquire, 0) - aie.dma_bd(%99 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%98, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%96, Acquire, 0) - aie.dma_bd(%97 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%96, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%94, Acquire, 1) - aie.dma_bd(%95 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%94, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %101 = aie.core(%93) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%98, Acquire, 1) - aie.use_lock(%96, Acquire, 1) - aie.use_lock(%94, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %99[%arg0] : memref<64xi32, 2> - %201 = affine.load %97[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %95[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%94, Release, 1) - aie.use_lock(%96, Release, 0) - aie.use_lock(%98, Release, 0) - cf.br ^bb1 - } - %102 = aie.tile(19, 2) - %103 = aie.tile(19, 1) - %104 = aie.tile(19, 0) - %105 = aie.tile(10, 3) - %106 = aie.lock(%105, 2) - %107 = aie.buffer(%105) {sym_name = "buf23"} : memref<64xi32, 2> - %108 = aie.lock(%105, 1) - %109 = aie.buffer(%105) {sym_name = "buf22"} : memref<64xi32, 2> - %110 = aie.lock(%105, 0) - %111 = aie.buffer(%105) {sym_name = "buf21"} : memref<64xi32, 2> - %112 = aie.mem(%105) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%110, Acquire, 0) - aie.dma_bd(%111 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%110, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%108, Acquire, 0) - aie.dma_bd(%109 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%108, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%106, Acquire, 1) - aie.dma_bd(%107 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%106, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %113 = aie.core(%105) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%110, Acquire, 1) - aie.use_lock(%108, Acquire, 1) - aie.use_lock(%106, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %111[%arg0] : memref<64xi32, 2> - %201 = affine.load %109[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %107[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%106, Release, 1) - aie.use_lock(%108, Release, 0) - aie.use_lock(%110, Release, 0) - cf.br ^bb1 - } - %114 = aie.tile(18, 2) - %115 = aie.tile(18, 1) - %116 = aie.tile(18, 0) - %117 = aie.tile(9, 3) - %118 = aie.lock(%117, 2) - %119 = aie.buffer(%117) {sym_name = "buf20"} : memref<64xi32, 2> - %120 = aie.lock(%117, 1) - %121 = aie.buffer(%117) {sym_name = "buf19"} : memref<64xi32, 2> - %122 = aie.lock(%117, 0) - %123 = aie.buffer(%117) {sym_name = "buf18"} : memref<64xi32, 2> - %124 = aie.mem(%117) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%122, Acquire, 0) - aie.dma_bd(%123 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%122, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%120, Acquire, 0) - aie.dma_bd(%121 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%120, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%118, Acquire, 1) - aie.dma_bd(%119 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%118, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %125 = aie.core(%117) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%122, Acquire, 1) - aie.use_lock(%120, Acquire, 1) - aie.use_lock(%118, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %123[%arg0] : memref<64xi32, 2> - %201 = affine.load %121[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %119[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%118, Release, 1) - aie.use_lock(%120, Release, 0) - aie.use_lock(%122, Release, 0) - cf.br ^bb1 - } - %126 = aie.tile(11, 2) - %127 = aie.tile(11, 1) - %128 = aie.tile(11, 0) - %129 = aie.tile(1, 1) - %130 = aie.tile(8, 3) - %131 = aie.lock(%130, 2) - %132 = aie.buffer(%130) {sym_name = "buf17"} : memref<64xi32, 2> - %133 = aie.lock(%130, 1) - %134 = aie.buffer(%130) {sym_name = "buf16"} : memref<64xi32, 2> - %135 = aie.lock(%130, 0) - %136 = aie.buffer(%130) {sym_name = "buf15"} : memref<64xi32, 2> - %137 = aie.mem(%130) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%135, Acquire, 0) - aie.dma_bd(%136 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%135, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%133, Acquire, 0) - aie.dma_bd(%134 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%133, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%131, Acquire, 1) - aie.dma_bd(%132 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%131, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %138 = aie.core(%130) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%135, Acquire, 1) - aie.use_lock(%133, Acquire, 1) - aie.use_lock(%131, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %136[%arg0] : memref<64xi32, 2> - %201 = affine.load %134[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %132[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%131, Release, 1) - aie.use_lock(%133, Release, 0) - aie.use_lock(%135, Release, 0) - cf.br ^bb1 - } - %139 = aie.tile(10, 1) - %140 = aie.tile(10, 0) - %141 = aie.tile(0, 1) - %142 = aie.tile(7, 3) - %143 = aie.lock(%142, 2) - %144 = aie.buffer(%142) {sym_name = "buf14"} : memref<64xi32, 2> - %145 = aie.lock(%142, 1) - %146 = aie.buffer(%142) {sym_name = "buf13"} : memref<64xi32, 2> - %147 = aie.lock(%142, 0) - %148 = aie.buffer(%142) {sym_name = "buf12"} : memref<64xi32, 2> - %149 = aie.mem(%142) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%147, Acquire, 0) - aie.dma_bd(%148 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%147, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%145, Acquire, 0) - aie.dma_bd(%146 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%145, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%143, Acquire, 1) - aie.dma_bd(%144 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%143, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %150 = aie.core(%142) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%147, Acquire, 1) - aie.use_lock(%145, Acquire, 1) - aie.use_lock(%143, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %148[%arg0] : memref<64xi32, 2> - %201 = affine.load %146[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %144[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%143, Release, 1) - aie.use_lock(%145, Release, 0) - aie.use_lock(%147, Release, 0) - cf.br ^bb1 - } - %151 = aie.tile(7, 1) - %152 = aie.tile(7, 0) - %153 = aie.tile(10, 2) - %154 = aie.lock(%153, 2) - %155 = aie.buffer(%153) {sym_name = "buf11"} : memref<64xi32, 2> - %156 = aie.lock(%153, 1) - %157 = aie.buffer(%153) {sym_name = "buf10"} : memref<64xi32, 2> - %158 = aie.lock(%153, 0) - %159 = aie.buffer(%153) {sym_name = "buf9"} : memref<64xi32, 2> - %160 = aie.mem(%153) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%158, Acquire, 0) - aie.dma_bd(%159 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%158, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%156, Acquire, 0) - aie.dma_bd(%157 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%156, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%154, Acquire, 1) - aie.dma_bd(%155 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%154, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %161 = aie.core(%153) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%158, Acquire, 1) - aie.use_lock(%156, Acquire, 1) - aie.use_lock(%154, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %159[%arg0] : memref<64xi32, 2> - %201 = affine.load %157[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %155[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%154, Release, 1) - aie.use_lock(%156, Release, 0) - aie.use_lock(%158, Release, 0) - cf.br ^bb1 - } - %162 = aie.tile(6, 2) - %163 = aie.tile(6, 1) - %164 = aie.tile(6, 0) - %165 = aie.tile(9, 2) - %166 = aie.lock(%165, 2) - %167 = aie.buffer(%165) {sym_name = "buf8"} : memref<64xi32, 2> - %168 = aie.lock(%165, 1) - %169 = aie.buffer(%165) {sym_name = "buf7"} : memref<64xi32, 2> - %170 = aie.lock(%165, 0) - %171 = aie.buffer(%165) {sym_name = "buf6"} : memref<64xi32, 2> - %172 = aie.mem(%165) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%170, Acquire, 0) - aie.dma_bd(%171 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%170, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%168, Acquire, 0) - aie.dma_bd(%169 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%168, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%166, Acquire, 1) - aie.dma_bd(%167 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%166, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %173 = aie.core(%165) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%170, Acquire, 1) - aie.use_lock(%168, Acquire, 1) - aie.use_lock(%166, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %171[%arg0] : memref<64xi32, 2> - %201 = affine.load %169[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %167[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%166, Release, 1) - aie.use_lock(%168, Release, 0) - aie.use_lock(%170, Release, 0) - cf.br ^bb1 - } - %174 = aie.tile(3, 2) - %175 = aie.tile(3, 1) - %176 = aie.tile(3, 0) - %177 = aie.tile(1, 0) - %178 = aie.tile(8, 2) - %179 = aie.lock(%178, 2) - %180 = aie.buffer(%178) {sym_name = "buf5"} : memref<64xi32, 2> - %181 = aie.lock(%178, 1) - %182 = aie.buffer(%178) {sym_name = "buf4"} : memref<64xi32, 2> - %183 = aie.lock(%178, 0) - %184 = aie.buffer(%178) {sym_name = "buf3"} : memref<64xi32, 2> - %185 = aie.mem(%178) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%183, Acquire, 0) - aie.dma_bd(%184 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%183, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%181, Acquire, 0) - aie.dma_bd(%182 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%181, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%179, Acquire, 1) - aie.dma_bd(%180 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%179, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %186 = aie.core(%178) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%183, Acquire, 1) - aie.use_lock(%181, Acquire, 1) - aie.use_lock(%179, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %184[%arg0] : memref<64xi32, 2> - %201 = affine.load %182[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %180[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%179, Release, 1) - aie.use_lock(%181, Release, 0) - aie.use_lock(%183, Release, 0) - cf.br ^bb1 - } - %187 = aie.tile(2, 2) - %188 = aie.tile(2, 1) - %189 = aie.tile(2, 0) - %190 = aie.tile(0, 0) - %191 = aie.tile(7, 2) - %192 = aie.lock(%191, 2) - %193 = aie.buffer(%191) {sym_name = "buf2"} : memref<64xi32, 2> - %194 = aie.lock(%191, 1) - %195 = aie.buffer(%191) {sym_name = "buf1"} : memref<64xi32, 2> - %196 = aie.lock(%191, 0) - %197 = aie.buffer(%191) {sym_name = "buf0"} : memref<64xi32, 2> - %198 = aie.mem(%191) { - %200 = aie.dma_start(S2MM, 0, ^bb1, ^bb4) - ^bb1: // 2 preds: ^bb0, ^bb1 - aie.use_lock(%196, Acquire, 0) - aie.dma_bd(%197 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%196, Release, 1) - aie.next_bd ^bb1 - ^bb2: // pred: ^bb4 - %201 = aie.dma_start(S2MM, 1, ^bb3, ^bb6) - ^bb3: // 2 preds: ^bb2, ^bb3 - aie.use_lock(%194, Acquire, 0) - aie.dma_bd(%195 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%194, Release, 1) - aie.next_bd ^bb3 - ^bb4: // pred: ^bb0 - %202 = aie.dma_start(MM2S, 0, ^bb5, ^bb2) - ^bb5: // 2 preds: ^bb4, ^bb5 - aie.use_lock(%192, Acquire, 1) - aie.dma_bd(%193 : memref<64xi32, 2>, 0, 64) - aie.use_lock(%192, Release, 0) - aie.next_bd ^bb5 - ^bb6: // pred: ^bb2 - aie.end - } - %199 = aie.core(%191) { - cf.br ^bb1 - ^bb1: // 2 preds: ^bb0, ^bb2 - cf.br ^bb2 - ^bb2: // pred: ^bb1 - aie.use_lock(%196, Acquire, 1) - aie.use_lock(%194, Acquire, 1) - aie.use_lock(%192, Acquire, 0) - affine.for %arg0 = 0 to 64 { - %200 = affine.load %197[%arg0] : memref<64xi32, 2> - %201 = affine.load %195[%arg0] : memref<64xi32, 2> - %202 = arith.muli %200, %201 : i32 - affine.store %202, %193[%arg0] : memref<64xi32, 2> - } - aie.use_lock(%192, Release, 1) - aie.use_lock(%194, Release, 0) - aie.use_lock(%196, Release, 0) - cf.br ^bb1 - } - aie.flow(%189, DMA : 0, %191, DMA : 0) - aie.flow(%189, DMA : 1, %191, DMA : 1) - aie.flow(%191, DMA : 0, %189, DMA : 0) - aie.flow(%176, DMA : 0, %178, DMA : 0) - aie.flow(%176, DMA : 1, %178, DMA : 1) - aie.flow(%178, DMA : 0, %189, DMA : 1) - aie.flow(%164, DMA : 0, %165, DMA : 0) - aie.flow(%164, DMA : 1, %165, DMA : 1) - aie.flow(%165, DMA : 0, %176, DMA : 0) - aie.flow(%152, DMA : 0, %153, DMA : 0) - aie.flow(%152, DMA : 1, %153, DMA : 1) - aie.flow(%153, DMA : 0, %176, DMA : 1) - aie.flow(%140, DMA : 0, %142, DMA : 0) - aie.flow(%140, DMA : 1, %142, DMA : 1) - aie.flow(%142, DMA : 0, %164, DMA : 0) - aie.flow(%128, DMA : 0, %130, DMA : 0) - aie.flow(%128, DMA : 1, %130, DMA : 1) - aie.flow(%130, DMA : 0, %164, DMA : 1) - aie.flow(%116, DMA : 0, %117, DMA : 0) - aie.flow(%116, DMA : 1, %117, DMA : 1) - aie.flow(%117, DMA : 0, %152, DMA : 0) - aie.flow(%104, DMA : 0, %105, DMA : 0) - aie.flow(%104, DMA : 1, %105, DMA : 1) - aie.flow(%105, DMA : 0, %152, DMA : 1) - aie.flow(%91, DMA : 0, %93, DMA : 0) - aie.flow(%91, DMA : 1, %93, DMA : 1) - aie.flow(%93, DMA : 0, %140, DMA : 0) - aie.flow(%78, DMA : 0, %80, DMA : 0) - aie.flow(%78, DMA : 1, %80, DMA : 1) - aie.flow(%80, DMA : 0, %140, DMA : 1) - aie.flow(%66, DMA : 0, %67, DMA : 0) - aie.flow(%66, DMA : 1, %67, DMA : 1) - aie.flow(%67, DMA : 0, %128, DMA : 0) - aie.flow(%54, DMA : 0, %55, DMA : 0) - aie.flow(%54, DMA : 1, %55, DMA : 1) - aie.flow(%55, DMA : 0, %128, DMA : 1) - aie.flow(%41, DMA : 0, %43, DMA : 0) - aie.flow(%41, DMA : 1, %43, DMA : 1) - aie.flow(%43, DMA : 0, %116, DMA : 0) - aie.flow(%28, DMA : 0, %30, DMA : 0) - aie.flow(%28, DMA : 1, %30, DMA : 1) - aie.flow(%30, DMA : 0, %116, DMA : 1) - aie.flow(%15, DMA : 0, %17, DMA : 0) - aie.flow(%15, DMA : 1, %17, DMA : 1) - aie.flow(%17, DMA : 0, %104, DMA : 0) - aie.flow(%2, DMA : 0, %4, DMA : 0) - aie.flow(%2, DMA : 1, %4, DMA : 1) - aie.flow(%4, DMA : 0, %104, DMA : 1) - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/user_assigned.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/user_assigned.mlir index 79e08f0cb..fb8587705 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/user_assigned.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/user_assigned.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-assign-bd-ids --split-input-file %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) // CHECK: %[[IN:.*]] = aie.buffer(%[[TILE_2_1]]) {address = 8192 : i32, sym_name = "in"} : memref<16xi32> // CHECK: %[[OUT:.*]] = aie.buffer(%[[TILE_2_1]]) {address = 1824 : i32, sym_name = "out"} : memref<16xi32> @@ -43,7 +43,7 @@ // CHECK: } module @aie_module { - aie.device(xcve2302) { + aie.device(npu1_4col) { %t01 = aie.tile(2, 1) %buf01_0 = aie.buffer(%t01) { address = 8192 : i32, sym_name = "in" } : memref<16xi32> %buf01_1 = aie.buffer(%t01) { address = 1824 : i32, sym_name = "out" } : memref<16xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/via_DMA_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/via_DMA_test.mlir index 76d76e700..98d349e7e 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/via_DMA_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/via_DMA_test.mlir @@ -1,7 +1,7 @@ // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(npu1_4col) { // CHECK: memref.global "public" @of_stream_cons : memref<16xi32> // CHECK: memref.global "public" @of_stream : memref<16xi32> // CHECK: memref.global "public" @of_shared : memref<16xi32> @@ -53,7 +53,7 @@ // CHECK: } module @viaDMA { - aie.device(xcve2302) { + aie.device(npu1_4col) { %tile12 = aie.tile(1, 2) %tile13 = aie.tile(1, 3) aie.objectfifo @of_shared (%tile12, {%tile13}, 2 : i32) : !aie.objectfifo> diff --git a/runtime/src/iree-amd-aie/runtime/CMakeLists.txt b/runtime/src/iree-amd-aie/runtime/CMakeLists.txt index a750e308e..e66198788 100644 --- a/runtime/src/iree-amd-aie/runtime/CMakeLists.txt +++ b/runtime/src/iree-amd-aie/runtime/CMakeLists.txt @@ -136,4 +136,4 @@ iree_cc_library( ) target_link_libraries(iree-amd-aie_runtime_iree_aie_runtime_static - PRIVATE aienginev2) + PRIVATE aienginev2 LLVMSupport) diff --git a/runtime/src/iree-amd-aie/runtime/iree_aie_runtime.cc b/runtime/src/iree-amd-aie/runtime/iree_aie_runtime.cc index 44039e8a4..5af3db452 100644 --- a/runtime/src/iree-amd-aie/runtime/iree_aie_runtime.cc +++ b/runtime/src/iree-amd-aie/runtime/iree_aie_runtime.cc @@ -3,3 +3,337 @@ // #include "iree_aie_runtime.h" + +#include +#include + +#define DEBUG_TYPE "iree-aie-runtime" + +#define AIERC_STR(x) x, #x +static const std::map _AIERCTOSTR = { + {AIERC_STR(XAIE_OK)}, + {AIERC_STR(XAIE_ERR)}, + {AIERC_STR(XAIE_INVALID_DEVICE)}, + {AIERC_STR(XAIE_INVALID_RANGE)}, + {AIERC_STR(XAIE_INVALID_ARGS)}, + {AIERC_STR(XAIE_INVALID_TILE)}, + {AIERC_STR(XAIE_ERR_STREAM_PORT)}, + {AIERC_STR(XAIE_INVALID_DMA_TILE)}, + {AIERC_STR(XAIE_INVALID_BD_NUM)}, + {AIERC_STR(XAIE_ERR_OUTOFBOUND)}, + {AIERC_STR(XAIE_INVALID_DATA_MEM_ADDR)}, + {AIERC_STR(XAIE_INVALID_ELF)}, + {AIERC_STR(XAIE_CORE_STATUS_TIMEOUT)}, + {AIERC_STR(XAIE_INVALID_CHANNEL_NUM)}, + {AIERC_STR(XAIE_INVALID_LOCK)}, + {AIERC_STR(XAIE_INVALID_DMA_DIRECTION)}, + {AIERC_STR(XAIE_INVALID_PLIF_WIDTH)}, + {AIERC_STR(XAIE_INVALID_LOCK_ID)}, + {AIERC_STR(XAIE_INVALID_LOCK_VALUE)}, + {AIERC_STR(XAIE_LOCK_RESULT_FAILED)}, + {AIERC_STR(XAIE_INVALID_DMA_DESC)}, + {AIERC_STR(XAIE_INVALID_ADDRESS)}, + {AIERC_STR(XAIE_FEATURE_NOT_SUPPORTED)}, + {AIERC_STR(XAIE_INVALID_BURST_LENGTH)}, + {AIERC_STR(XAIE_INVALID_BACKEND)}, + {AIERC_STR(XAIE_INSUFFICIENT_BUFFER_SIZE)}, + {AIERC_STR(XAIE_ERR_MAX)}}; +#undef AIERC_STR + +std::string AIERCTOSTR(AieRC rc) { return _AIERCTOSTR.at(rc); } + +llvm::raw_ostream &operator<<(llvm::raw_ostream &os, const XAie_LocType &loc) { + os << "XAie_LocType(col: " << std::to_string(loc.Col) + << ", row: " << std::to_string(loc.Row) << ")"; + return os; +} + +llvm::raw_ostream &operator<<(llvm::raw_ostream &os, const XAie_Lock &lock) { + os << "XAie_Lock(id: " << std::to_string(lock.LockId) + << ", val: " << std::to_string(lock.LockVal) << ")"; + return os; +} + +llvm::raw_ostream &operator<<(llvm::raw_ostream &os, + const XAie_Packet &packet) { + os << "XAie_Packet(id: " << std::to_string(packet.PktId) + << ", type: " << std::to_string(packet.PktType) << ")"; + return os; +} + +bool isInternal(uint8_t srcCol, uint8_t srcRow, uint8_t dstCol, + uint8_t dstRow) { + return srcCol == dstCol && srcRow == dstRow; +} + +bool isWest(uint8_t srcCol, uint8_t srcRow, uint8_t dstCol, uint8_t dstRow) { + return srcCol == dstCol + 1 && srcRow == dstRow; +} + +bool isEast(uint8_t srcCol, uint8_t srcRow, uint8_t dstCol, uint8_t dstRow) { + return srcCol == dstCol - 1 && srcRow == dstRow; +} + +bool isNorth(uint8_t srcCol, uint8_t srcRow, uint8_t dstCol, uint8_t dstRow) { + return srcCol == dstCol && srcRow == dstRow - 1; +} + +bool isSouth(uint8_t srcCol, uint8_t srcRow, uint8_t dstCol, uint8_t dstRow) { + return srcCol == dstCol && srcRow == dstRow + 1; +} + +AMDAIENPUDeviceModel::AMDAIENPUDeviceModel(size_t partitionStartCol, + bool aieSim, bool xaieDebug) + : configPtr{ + /*AieGen*/ XAIE_DEV_GEN_AIEML, + /*BaseAddr*/ XAIE_BASE_ADDR, + /*ColShift*/ XAIE_COL_SHIFT, + /*RowShift*/ XAIE_ROW_SHIFT, + /*NumRows*/ static_cast(rows()), + /*NumCols*/ static_cast(columns() + partitionStartCol), + /*ShimRowNum*/ XAIE_SHIM_ROW, + /*MemTileRowStart*/ XAIE_MEM_TILE_ROW_START, + /*MemTileNumRows*/ static_cast(getNumMemTileRows()), + /*AieTileRowStart*/ + static_cast(XAIE_MEM_TILE_ROW_START + getNumMemTileRows()), + /*AieTileNumRows*/ + static_cast(rows() - getNumMemTileRows() - 1), + /*PartProp*/ {}, + /*Backend*/ XAIE_IO_BACKEND_CDO}, + devInst{} { + size_t partitionNumCols = columns(); + TRY_XAIE_API_FATAL_ERROR(XAie_SetupPartitionConfig, &devInst, + XAIE_PARTITION_BASE_ADDR, partitionStartCol, + partitionNumCols); + TRY_XAIE_API_FATAL_ERROR(XAie_CfgInitialize, &devInst, &configPtr); + if (aieSim) { + TRY_XAIE_API_FATAL_ERROR(XAie_SetIOBackend, &devInst, XAIE_IO_BACKEND_SIM); + } else if (xaieDebug) + TRY_XAIE_API_FATAL_ERROR(XAie_SetIOBackend, &devInst, + XAIE_IO_BACKEND_DEBUG); + else + TRY_XAIE_API_FATAL_ERROR(XAie_SetIOBackend, &devInst, XAIE_IO_BACKEND_CDO); + + TRY_XAIE_API_FATAL_ERROR(XAie_UpdateNpiAddr, &devInst, NPI_ADDR); +} + +int AMDAIENPUDeviceModel::rows() { + return 6; /* 1 Shim row, 1 memtile row, and 4 Core rows. */ +} + +int AMDAIENPUDeviceModel::columns() { return 5; } + +uint32_t AMDAIENPUDeviceModel::getNumMemTileRows() { return 1; } + +// TODO(max): these are buried somewhere in aie-rt... +uint32_t AMDAIENPUDeviceModel::getMemSouthBaseAddress() { return 0x00040000; } +uint32_t AMDAIENPUDeviceModel::getMemWestBaseAddress() { return 0x00050000; } +uint32_t AMDAIENPUDeviceModel::getMemNorthBaseAddress() { return 0x00060000; } +uint32_t AMDAIENPUDeviceModel::getMemEastBaseAddress() { return 0x00070000; } + +bool AMDAIENPUDeviceModel::isCoreTile(uint8_t col, uint8_t row) { + return devInst.DevOps->GetTTypefromLoc(&devInst, {row, col}) == + XAIEGBL_TILE_TYPE_AIETILE; +} + +bool AMDAIENPUDeviceModel::isMemTile(uint8_t col, uint8_t row) { + return devInst.DevOps->GetTTypefromLoc(&devInst, {row, col}) == + XAIEGBL_TILE_TYPE_MEMTILE; +} + +bool AMDAIENPUDeviceModel::isShimNOCTile(uint8_t col, uint8_t row) { + return devInst.DevOps->GetTTypefromLoc(&devInst, {row, col}) == + XAIEGBL_TILE_TYPE_SHIMNOC; +} + +bool AMDAIENPUDeviceModel::isShimPLTile(uint8_t col, uint8_t row) { + return devInst.DevOps->GetTTypefromLoc(&devInst, {row, col}) == + XAIEGBL_TILE_TYPE_SHIMPL; +} + +uint32_t AMDAIENPUDeviceModel::getNumLocks(uint8_t col, uint8_t row) { + uint8_t tileType = devInst.DevOps->GetTTypefromLoc(&devInst, {row, col}); + return devInst.DevProp.DevMod[tileType].LockMod->NumLocks; +} + +uint32_t AMDAIENPUDeviceModel::getNumBDs(uint8_t col, uint8_t row) { + uint8_t tileType = devInst.DevOps->GetTTypefromLoc(&devInst, {row, col}); + const XAie_DmaMod *dmaMod = devInst.DevProp.DevMod[tileType].DmaMod; + return dmaMod->NumBds; +} + +std::optional AMDAIENPUDeviceModel::getMemWest(TileLoc src) { + XAie_LocType ret = XAie_TileLoc(src.col - 1, src.row); + if (devInst.DevOps->GetTTypefromLoc(&devInst, ret) == XAIEGBL_TILE_TYPE_MAX) + return std::nullopt; + return ret; +} + +std::optional AMDAIENPUDeviceModel::getMemEast(TileLoc src) { + // east is self + return src; +} + +std::optional AMDAIENPUDeviceModel::getMemNorth(TileLoc src) { + XAie_LocType ret = XAie_TileLoc(src.col, src.row + 1); + if (devInst.DevOps->GetTTypefromLoc(&devInst, ret) == XAIEGBL_TILE_TYPE_MAX) + return std::nullopt; + return ret; +} + +std::optional AMDAIENPUDeviceModel::getMemSouth(TileLoc src) { + XAie_LocType ret = XAie_TileLoc(src.col, src.row - 1); + auto tt = devInst.DevOps->GetTTypefromLoc(&devInst, ret); + // The first row doesn't have a tile memory south + // Memtiles don't have memory adjacency to neighboring core tiles. + if (tt == XAIEGBL_TILE_TYPE_MAX || ret.Row == 0 || + tt == XAIEGBL_TILE_TYPE_MEMTILE) + return std::nullopt; + return ret; +} + +// I don't know why you don't need to check for memtile or core tile here +// but this repros what mlir-aie does +bool AMDAIENPUDeviceModel::hasMemWest(uint8_t srcCol, uint8_t srcRow, + uint8_t dstCol, uint8_t dstRow) { + return isWest(srcCol, srcRow, dstCol, dstRow); +} + +bool AMDAIENPUDeviceModel::hasMemEast(uint8_t srcCol, uint8_t srcRow, + uint8_t dstCol, uint8_t dstRow) { + return isInternal(srcCol, srcRow, dstCol, dstRow); +} + +bool AMDAIENPUDeviceModel::hasMemNorth(uint8_t srcCol, uint8_t srcRow, + uint8_t dstCol, uint8_t dstRow) { + return isNorth(srcCol, srcRow, dstCol, dstRow); +} + +bool AMDAIENPUDeviceModel::hasMemSouth(uint8_t srcCol, uint8_t srcRow, + uint8_t dstCol, uint8_t dstRow) { + return isSouth(srcCol, srcRow, dstCol, dstRow); +} + +uint32_t AMDAIENPUDeviceModel::getLocalMemorySize(uint8_t col, uint8_t row) { + auto tileLoc = XAie_TileLoc(col, row); + uint8_t tileType = devInst.DevOps->GetTTypefromLoc(&devInst, tileLoc); + return devInst.DevProp.DevMod[tileType].CoreMod->DataMemSize; +} + +uint32_t AMDAIENPUDeviceModel::getMemInternalBaseAddress() { + return getMemEastBaseAddress(); +} + +uint32_t AMDAIENPUDeviceModel::getMemTileSize(uint8_t col, uint8_t row) { + auto tileLoc = XAie_TileLoc(col, row); + uint8_t tileType = devInst.DevOps->GetTTypefromLoc(&devInst, tileLoc); + return devInst.DevProp.DevMod[tileType].MemMod->Size; +} + +bool AMDAIENPUDeviceModel::hasLegalMemAffinity(uint8_t coreCol, uint8_t coreRow, + uint8_t memCol, uint8_t memRow) { + bool isMemWest = hasMemWest(coreCol, coreRow, memCol, memRow); + bool isMemEast = hasMemEast(coreCol, coreRow, memCol, memRow); + bool isMemNorth = hasMemNorth(coreCol, coreRow, memCol, memRow); + bool isMemSouth = hasMemSouth(coreCol, coreRow, memCol, memRow); + + if (isMemTile(coreCol, coreRow)) + return isEast(coreCol, coreRow, memCol, memRow) || + isInternal(coreCol, coreRow, memCol, memRow) || + isWest(coreCol, coreRow, memCol, memRow); + return (isMemSouth && !isMemTile(memCol, memRow)) || isMemNorth || + isMemWest || isMemEast; +} + +bool AMDAIENPUDeviceModel::isLegalMemtileConnection(uint8_t col, uint8_t row, + StrmSwPortType srcBundle, + uint8_t srcChan, + StrmSwPortType dstBundle, + uint8_t dstChan) { + // this isn't correct but for agreement with mlir-aie... + if (srcBundle == dstBundle and srcBundle != DMA) return true; + assert(isMemTile(col, row) && "expected memtile"); + auto tileLoc = XAie_TileLoc(col, row); + uint8_t tileType = devInst.DevOps->GetTTypefromLoc(&devInst, tileLoc); + const XAie_StrmMod *strmMod = devInst.DevProp.DevMod[tileType].StrmSw; + AieRC RC = strmMod->PortVerify(/*slave*/ srcBundle, srcChan, + /*master*/ dstBundle, dstChan); + if (RC != XAIE_OK) { + LLVM_DEBUG(llvm::dbgs() << "PortVerify failed with " << AIERCTOSTR(RC)); + LLVM_DEBUG(SHOW_ARGS(llvm::dbgs(), col, row, srcBundle, srcChan, dstBundle, + dstChan)); + return false; + } + return true; +} + +// source <-> slave and dest <-> master +uint32_t AMDAIENPUDeviceModel::getNumSourceSwitchboxConnections( + uint8_t col, uint8_t row, StrmSwPortType bundle) { + // not sure if this makes sense but agrees with mlir-aie + if ((bundle == NORTH && row == rows() - 1) || (bundle == WEST && col == 0) || + (bundle == EAST && col == columns() - 1)) + return 0; + uint8_t tileType = devInst.DevOps->GetTTypefromLoc(&devInst, {row, col}); + const XAie_StrmMod *strmMod = devInst.DevProp.DevMod[tileType].StrmSw; + return strmMod->SlvConfig[bundle].NumPorts; +} + +uint32_t AMDAIENPUDeviceModel::getNumDestSwitchboxConnections( + uint8_t col, uint8_t row, StrmSwPortType bundle) { + // not sure if this makes sense but agrees with mlir-aie + if ((bundle == NORTH && row == rows() - 1) || (bundle == WEST && col == 0) || + (bundle == EAST && col == columns() - 1)) + return 0; + + uint8_t tileType = devInst.DevOps->GetTTypefromLoc(&devInst, {row, col}); + const XAie_StrmMod *strmMod = devInst.DevProp.DevMod[tileType].StrmSw; + return strmMod->MstrConfig[bundle].NumPorts; +} + +// TODO(max): obv this should be in the context or something like that +static struct AMDAIENPUDeviceModel targetModel(/*partitionStartCol*/ 1); + +struct AMDAIENPUDeviceModel &mlir::iree_compiler::AMDAIE::getDeviceModel() { + return targetModel; +} + +StrmSwPortType getConnectingStrmSwPortType(StrmSwPortType dir) { + switch (dir) { + case StrmSwPortType::NORTH: + return StrmSwPortType::SOUTH; + case StrmSwPortType::SOUTH: + return StrmSwPortType::NORTH; + case StrmSwPortType::EAST: + return StrmSwPortType::WEST; + case StrmSwPortType::WEST: + return StrmSwPortType::EAST; + default: + return dir; + } +} + +std::string stringifyStrmSwPortType(StrmSwPortType val) { + switch (val) { + case StrmSwPortType::CORE: + return "Core"; + case StrmSwPortType::DMA: + return "DMA"; + case StrmSwPortType::FIFO: + return "FIFO"; + case StrmSwPortType::SOUTH: + return "South"; + case StrmSwPortType::WEST: + return "West"; + case StrmSwPortType::NORTH: + return "North"; + case StrmSwPortType::EAST: + return "East"; + case StrmSwPortType::TRACE: + return "Trace"; + case StrmSwPortType::CTRL: + return "Ctrl"; + default: + return "UNSUPPORTED"; + } +} \ No newline at end of file diff --git a/runtime/src/iree-amd-aie/runtime/iree_aie_runtime.h b/runtime/src/iree-amd-aie/runtime/iree_aie_runtime.h index 20117d650..ab8b7968e 100644 --- a/runtime/src/iree-amd-aie/runtime/iree_aie_runtime.h +++ b/runtime/src/iree-amd-aie/runtime/iree_aie_runtime.h @@ -6,6 +6,12 @@ #define IREE_AIE_RUNTIME_H #include +#include +#include + +#include "llvm/ADT/Twine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/FormattedStream.h" #ifdef _WIN32 #ifndef IREE_AIE_RUNTIME_EXPORT @@ -25,8 +31,14 @@ extern "C" { #include "xaiengine.h" -enum byte_ordering { Little_Endian, Big_Endian }; -void startCDOFileStream(const char* cdoFileName); +#define s8 +#define u8 +#define u16 +#define s32 +#define u32 +#define u64 + +void startCDOFileStream(const char *cdoFileName); void endCurrentCDOFileStream(); void FileHeader(); void EnAXIdebug(); @@ -34,63 +46,151 @@ void setEndianness(bool endianness); void configureHeader(); } -struct AMDAIENPUTargetModel { - int rows() { return 6; /* 1 Shim row, 1 memtile row, and 4 Core rows. */ } - int columns() { return 5; } - - bool isCoreTile(int col, int row) { return row > 1; } +#define XAIE_BASE_ADDR 0x40000000 +#define XAIE_COL_SHIFT 25 +#define XAIE_ROW_SHIFT 20 +#define XAIE_SHIM_ROW 0 +#define XAIE_MEM_TILE_ROW_START 1 +#define XAIE_PARTITION_BASE_ADDR 0x0 + +#define NPI_ADDR 0x0 +#define NUM_LOCKS 16 +#define MEM_TILE_LOCK_ID_INCR 64 +#define BASE_ADDR_A_INCR 0x80000 + +std::string AIERCTOSTR(AieRC rc); + +// https://stackoverflow.com/a/32230306 +template +llvm::raw_ostream &showArgs(llvm::raw_ostream &out, const char *label, + H1 &&value) { + return out << label << "=" << std::forward

(value); +} - bool isMemTile(int col, int row) { return row == 1; } +template +llvm::raw_ostream &showArgs(llvm::raw_ostream &out, const char *label, + H1 &&value, T &&...rest) { + const char *pcomma = strchr(label, ','); + return showArgs(out.write(label, pcomma - label) + << "=" << std::forward

(value) << ',', + pcomma + 1, std::forward(rest)...); +} - uint32_t getNumLocks(int col, int row) { - return isMemTile(col, row) ? 64 : 16; +llvm::raw_ostream &operator<<(llvm::raw_ostream &os, const XAie_LocType &loc); + +llvm::raw_ostream &operator<<(llvm::raw_ostream &os, const XAie_Lock &lock); + +llvm::raw_ostream &operator<<(llvm::raw_ostream &os, const XAie_Packet &packet); + +#define SHOW_ARGS(os, ...) showArgs(os, #__VA_ARGS__, __VA_ARGS__) +#define TRY_XAIE_API_FATAL_ERROR(API, ...) \ + do { \ + LLVM_DEBUG(llvm::dbgs() << "XAIE API: " << #API << " with args: "); \ + LLVM_DEBUG(SHOW_ARGS(llvm::dbgs(), __VA_ARGS__)); \ + LLVM_DEBUG(llvm::dbgs() << "\n"); \ + if (auto r = API(__VA_ARGS__)) \ + llvm::report_fatal_error(llvm::Twine(#API " failed with ") + \ + AIERCTOSTR(r)); \ + } while (0) + +struct TileLoc { + // friend definition (will define the function as a non-member function in the + // namespace surrounding the class). + friend std::ostream &operator<<(std::ostream &os, const TileLoc &s) { + os << "TileLoc(" << s.col << ", " << s.row << ")"; + return os; } - bool isShimNOCTile(int col, int row) { return row == 0 && col > 0; } - - bool isShimPLTile(int col, int row) { - // This isn't useful because it's not connected to anything. - return row == 0 && col == 0; + friend std::string to_string(const TileLoc &s) { + std::ostringstream ss; + ss << s; + return ss.str(); } - uint32_t getNumMemTileRows() { return 1; } - - std::optional getMemWest(XAie_LocType src); - std::optional getMemEast(XAie_LocType src); - std::optional getMemNorth(XAie_LocType src); - std::optional getMemSouth(XAie_LocType src); - - bool isMemWest(int srcCol, int srcRow, int dstCol, int dstRow); - bool isMemEast(int srcCol, int srcRow, int dstCol, int dstRow); - bool isMemNorth(int srcCol, int srcRow, int dstCol, int dstRow); - bool isMemSouth(int srcCol, int srcRow, int dstCol, int dstRow); + friend llvm::raw_ostream &operator<<(llvm::raw_ostream &os, + const TileLoc &s) { + os << to_string(s); + return os; + } - bool isLegalMemAffinity(int coreCol, int coreRow, int memCol, int memRow); + inline bool operator<(const TileLoc &rhs) const { + return std::tie(col, row) < std::tie(rhs.col, rhs.row); + } - static uint32_t getMemInternalBaseAddress() { - return getMemEastBaseAddress(); + bool operator==(const TileLoc &rhs) const { + return std::tie(col, row) == std::tie(rhs.col, rhs.row); } - static uint32_t getMemSouthBaseAddress() { return 0x00040000; } - static uint32_t getMemWestBaseAddress() { return 0x00050000; } - static uint32_t getMemNorthBaseAddress() { return 0x00060000; } - static uint32_t getMemEastBaseAddress() { return 0x00070000; } - static uint32_t getLocalMemorySize() { return 0x00010000; } + bool operator!=(const TileLoc &rhs) const { return !(*this == rhs); } - uint32_t getNumBDs(int col, int row) { return isMemTile(col, row) ? 48 : 16; } + operator XAie_LocType() const { return XAie_TileLoc(col, row); } + TileLoc(XAie_LocType loc) : col(loc.Col), row(loc.Row) {} + TileLoc(int col, int row) : col(col), row(row) {} - uint32_t getMemTileSize() { return 0x00080000; } + int col, row; +}; - uint32_t getNumDestSwitchboxConnections(int col, int row, - StrmSwPortType bundle); - uint32_t getNumSourceSwitchboxConnections(int col, int row, +struct AMDAIENPUDeviceModel { + XAie_Config configPtr; + XAie_DevInst devInst; + + explicit AMDAIENPUDeviceModel(size_t partitionStartCol, bool aieSim = false, + bool xaieDebug = false); + + static int rows(); + static int columns(); + static uint32_t getNumMemTileRows(); + + bool isCoreTile(uint8_t col, uint8_t row); + bool isMemTile(uint8_t col, uint8_t row); + bool isShimNOCTile(uint8_t col, uint8_t row); + bool isShimPLTile(uint8_t col, uint8_t row); + + uint32_t getNumLocks(uint8_t col, uint8_t row); + + std::optional getMemWest(TileLoc src); + static std::optional getMemEast(TileLoc src); + std::optional getMemNorth(TileLoc src); + std::optional getMemSouth(TileLoc src); + + static bool hasMemWest(uint8_t srcCol, uint8_t srcRow, uint8_t dstCol, + uint8_t dstRow); + static bool hasMemEast(uint8_t srcCol, uint8_t srcRow, uint8_t dstCol, + uint8_t dstRow); + static bool hasMemNorth(uint8_t srcCol, uint8_t srcRow, uint8_t dstCol, + uint8_t dstRow); + static bool hasMemSouth(uint8_t srcCol, uint8_t srcRow, uint8_t dstCol, + uint8_t dstRow); + /// Return true if core can access the memory in mem + bool hasLegalMemAffinity(uint8_t coreCol, uint8_t coreRow, uint8_t memCol, + uint8_t memRow); + + uint32_t getMemInternalBaseAddress(); + static uint32_t getMemSouthBaseAddress(); + static uint32_t getMemWestBaseAddress(); + static uint32_t getMemNorthBaseAddress(); + static uint32_t getMemEastBaseAddress(); + uint32_t getLocalMemorySize(uint8_t col, uint8_t row); + uint32_t getMemTileSize(uint8_t col, uint8_t row); + + uint32_t getNumBDs(uint8_t col, uint8_t row); + + uint32_t getNumSourceSwitchboxConnections(uint8_t col, uint8_t row, StrmSwPortType bundle); - uint32_t getNumDestShimMuxConnections(int col, int row, - StrmSwPortType bundle); - uint32_t getNumSourceShimMuxConnections(int col, int row, + uint32_t getNumDestSwitchboxConnections(uint8_t col, uint8_t row, StrmSwPortType bundle); - bool isLegalMemtileConnection(StrmSwPortType srcBundle, int srcChan, - StrmSwPortType dstBundle, int dstChan); + bool isLegalMemtileConnection(uint8_t col, uint8_t row, + StrmSwPortType srcBundle, uint8_t srcChan, + StrmSwPortType dstBundle, uint8_t dstChan); }; +namespace mlir::iree_compiler::AMDAIE { + +struct AMDAIENPUDeviceModel &getDeviceModel(); + +} // namespace mlir::iree_compiler::AMDAIE + +StrmSwPortType getConnectingStrmSwPortType(StrmSwPortType dir); +std::string stringifyStrmSwPortType(StrmSwPortType val); + #endif // IREE_AIE_RUNTIME_H diff --git a/tests/aie_runtime/utest.cxx b/tests/aie_runtime/utest.cxx index 941a7c22f..ed7342597 100755 --- a/tests/aie_runtime/utest.cxx +++ b/tests/aie_runtime/utest.cxx @@ -15,14 +15,16 @@ #define XAIE_SHIM_ROW 0 #define XAIE_MEM_TILE_ROW_START 1 +enum byte_ordering { Little_Endian, Big_Endian }; + int main(int argc, char** argv) { std::string elfPath(argv[1]); int col = 0; // XAie_LocType is row, col but we always think col, row - XAie_LocType tile_0_0 = {0, static_cast(col)}; - XAie_LocType tile_0_1 = {1, static_cast(col)}; - XAie_LocType tile_0_2 = {2, static_cast(col)}; + XAie_LocType tile_0_0 = {0, static_cast(col)}; + XAie_LocType tile_0_1 = {1, static_cast(col)}; + XAie_LocType tile_0_2 = {2, static_cast(col)}; XAie_Lock lock_0_1 = XAie_Lock{0, 1}; XAie_Lock lock_1_0 = XAie_Lock{1, 0};