diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_dma.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_dma.mlir index 59b32b74c..e1d59ef9b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_dma.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_dma.mlir @@ -1,134 +1,135 @@ -//===- AIE2_cyclostatic_dma.mlir -------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// In this test, data is exchanged the same as in AIE2_cyclostatic_l1, but -// tiles are farther apart and have to use the network/DMAs to communicate. // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK: module @aie2_cyclostatic_dma { -// CHECK: aie.device(xcve2302) { -// CHECK: %[[t0:.*]] = aie.tile(2, 2) -// CHECK: %[[t1:.*]] = aie.tile(8, 3) -// CHECK: %[[buf1_0:.*]] = aie.buffer(%[[t1]]) {sym_name = "fifo_cons_buff_0"} : memref -// CHECK: %[[buf1_1:.*]] = aie.buffer(%[[t1]]) {sym_name = "fifo_cons_buff_1"} : memref -// CHECK: %[[buf1_2:.*]] = aie.buffer(%[[t1]]) {sym_name = "fifo_cons_buff_2"} : memref -// CHECK: %[[C_PL:.*]] = aie.lock(%[[t1]], 0) {init = 3 : i32, sym_name = "fifo_cons_prod_lock"} -// CHECK: %[[C_CL:.*]] = aie.lock(%[[t1]], 1) {init = 0 : i32, sym_name = "fifo_cons_cons_lock"} -// CHECK: %[[buf0_0:.*]] = aie.buffer(%[[t0]]) {sym_name = "fifo_buff_0"} : memref -// CHECK: %[[buf0_1:.*]] = aie.buffer(%[[t0]]) {sym_name = "fifo_buff_1"} : memref -// CHECK: %[[PL:.*]] = aie.lock(%[[t0]], 0) {init = 2 : i32, sym_name = "fifo_prod_lock"} -// CHECK: %[[CL:.*]] = aie.lock(%[[t0]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} -// CHECK: aie.flow(%[[t0]], DMA : 0, %[[t1]], DMA : 0) -// CHECK: %[[c0:.*]] = aie.core(%[[t0]]) { -// CHECK: aie.use_lock(%[[PL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[CL]], Release, 1) -// CHECK: aie.use_lock(%[[PL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[CL]], Release, 1) -// CHECK: aie.use_lock(%[[PL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[CL]], Release, 1) -// CHECK: aie.use_lock(%[[PL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[CL]], Release, 1) -// CHECK: aie.end -// CHECK: } -// CHECK: %[[c1:.*]] = aie.core(%[[t1]]) { -// CHECK: aie.use_lock(%[[C_CL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[C_PL]], Release, 1) -// CHECK: aie.use_lock(%[[C_CL]], AcquireGreaterEqual, 2) -// CHECK: aie.use_lock(%[[C_PL]], Release, 2) -// CHECK: aie.use_lock(%[[C_CL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[C_PL]], Release, 1) -// CHECK: aie.end -// CHECK: } -// CHECK: %[[m0:.*]] = aie.mem(%[[t0]]) { -// CHECK: %[[dma0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[CL]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[buf0_0]] : memref, 0, 1) -// CHECK: aie.use_lock(%[[PL]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[CL]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[buf0_1:.*]] : memref, 0, 1) -// CHECK: aie.use_lock(%[[PL]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: %[[m1:.*]] = aie.mem(%[[t1]]) { -// CHECK: %[[dma1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 -// CHECK: aie.use_lock(%[[C_PL]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[buf1_0:.*]] : memref, 0, 1) -// CHECK: aie.use_lock(%[[C_CL]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[C_PL]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[buf1_1]] : memref, 0, 1) -// CHECK: aie.use_lock(%[[C_CL]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[C_PL]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[buf1_2]] : memref, 0, 1) -// CHECK: aie.use_lock(%[[C_CL]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb4: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: } -// CHECK: } + +// CHECK-LABEL: aie.device(xcve2302) { +// CHECK: memref.global "public" @fifo_cons : memref +// CHECK: memref.global "public" @fifo : memref +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) +// CHECK: %[[FIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_0"} : memref +// CHECK: %[[FIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_1"} : memref +// CHECK: %[[FIFO_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo_cons_buff_2"} : memref +// CHECK: %[[FIFO_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 0) {init = 3 : i32, sym_name = "fifo_cons_prod_lock"} +// CHECK: %[[FIFO_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 1) {init = 0 : i32, sym_name = "fifo_cons_cons_lock"} +// CHECK: %[[FIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_0"} : memref +// CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref +// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "fifo_prod_lock"} +// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} +// CHECK: %[[BUF83:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf83"} : memref<4xi32> +// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_8_3]], DMA : 0) +// CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { +// CHECK: %[[C55_I32:.*]] = arith.constant 55 : i32 +// CHECK: %[[C66_I32:.*]] = arith.constant 66 : i32 +// CHECK: %[[C77_I32:.*]] = arith.constant 77 : i32 +// CHECK: %[[C88_I32:.*]] = arith.constant 88 : i32 +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C55_I32]], %[[FIFO_BUFF_0]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C66_I32]], %[[FIFO_BUFF_1]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C77_I32]], %[[FIFO_BUFF_0]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C88_I32]], %[[FIFO_BUFF_1]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: aie.end +// CHECK: } +// CHECK: %[[CORE_8_3:.*]] = aie.core(%[[TILE_8_3]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: %[[C3:.*]] = arith.constant 3 : index +// CHECK: aie.use_lock(%[[FIFO_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[VAL_0:.*]] = memref.load %[[FIFO_CONS_BUFF_0]][] : memref +// CHECK: memref.store %[[VAL_0]], %[[BUF83]]{{\[}}%[[C0]]] : memref<4xi32> +// CHECK: aie.use_lock(%[[FIFO_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO_CONS_CONS_LOCK]], AcquireGreaterEqual, 2) +// CHECK: %[[VAL_1:.*]] = memref.load %[[FIFO_CONS_BUFF_1]][] : memref +// CHECK: %[[VAL_2:.*]] = memref.load %[[FIFO_CONS_BUFF_2]][] : memref +// CHECK: memref.store %[[VAL_1]], %[[BUF83]]{{\[}}%[[C1]]] : memref<4xi32> +// CHECK: memref.store %[[VAL_2]], %[[BUF83]]{{\[}}%[[C2]]] : memref<4xi32> +// CHECK: aie.use_lock(%[[FIFO_CONS_PROD_LOCK]], Release, 2) +// CHECK: aie.use_lock(%[[FIFO_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[VAL_3:.*]] = memref.load %[[FIFO_CONS_BUFF_0]][] : memref +// CHECK: memref.store %[[VAL_3]], %[[BUF83]]{{\[}}%[[C3]]] : memref<4xi32> +// CHECK: aie.use_lock(%[[FIFO_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_4:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO_BUFF_0]] : memref, 0, 1) +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO_BUFF_1]] : memref, 0, 1) +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEM_8_3:.*]] = aie.mem(%[[TILE_8_3]]) { +// CHECK: %[[VAL_5:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[FIFO_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO_CONS_BUFF_0]] : memref, 0, 1) +// CHECK: aie.use_lock(%[[FIFO_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[FIFO_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO_CONS_BUFF_1]] : memref, 0, 1) +// CHECK: aie.use_lock(%[[FIFO_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb3 +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[FIFO_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO_CONS_BUFF_2]] : memref, 0, 1) +// CHECK: aie.use_lock(%[[FIFO_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb4: +// CHECK: aie.end +// CHECK: } +// CHECK: } module @aie2_cyclostatic_dma { aie.device(xcve2302) { - %tile22 = aie.tile(2, 2) // producer tile %tile83 = aie.tile(8, 3) // consumer tile %buf83 = aie.buffer(%tile83) {sym_name = "buf83"} : memref<4xi32> - // ObjectFifo that can hold 4 memrefs, populated by tile22 and // consumed by tile23 aie.objectfifo @fifo (%tile22, {%tile83}, 4 : i32) : !aie.objectfifo> - // Producer core %core22 = aie.core(%tile22) { %c55 = arith.constant 55 : i32 %c66 = arith.constant 66 : i32 %c77 = arith.constant 77 : i32 %c88 = arith.constant 88 : i32 - // Push 55 %subview0 = aie.objectfifo.acquire @fifo (Produce, 1) : !aie.objectfifosubview> %subview0_obj = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref memref.store %c55, %subview0_obj[] : memref aie.objectfifo.release @fifo (Produce, 1) - // Push 66 %subview1 = aie.objectfifo.acquire @fifo (Produce, 1) : !aie.objectfifosubview> %subview1_obj = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref memref.store %c66, %subview1_obj[] : memref aie.objectfifo.release @fifo (Produce, 1) - // Push 77 %subview2 = aie.objectfifo.acquire @fifo (Produce, 1) : !aie.objectfifosubview> %subview2_obj = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref memref.store %c77, %subview2_obj[] : memref aie.objectfifo.release @fifo (Produce, 1) - // Push 88 %subview3 = aie.objectfifo.acquire @fifo (Produce, 1) : !aie.objectfifosubview> %subview3_obj = aie.objectfifo.subview.access %subview3[0] : !aie.objectfifosubview> -> memref memref.store %c88, %subview3_obj[] : memref aie.objectfifo.release @fifo (Produce, 1) - aie.end } - // Consumer core %core28 = aie.core(%tile83) { // Consumer pattern: {1, 2, 1} @@ -136,14 +137,12 @@ module @aie2_cyclostatic_dma { %i1 = arith.constant 1 : index %i2 = arith.constant 2 : index %i3 = arith.constant 3 : index - // Pop 1 object off queue %subview0 = aie.objectfifo.acquire @fifo (Consume, 1) : !aie.objectfifosubview> %subview0_obj = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref %v55 = memref.load %subview0_obj[] : memref memref.store %v55, %buf83[%i0] : memref<4xi32> aie.objectfifo.release @fifo (Consume, 1) - // Pop 2 objects off queue %subview1 = aie.objectfifo.acquire @fifo (Consume, 2) : !aie.objectfifosubview> %subview1_obj0 = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref @@ -153,14 +152,12 @@ module @aie2_cyclostatic_dma { memref.store %v66, %buf83[%i1] : memref<4xi32> memref.store %v77, %buf83[%i2] : memref<4xi32> aie.objectfifo.release @fifo (Consume, 2) - // Pop 1 object off queue %subview2 = aie.objectfifo.acquire @fifo (Consume, 1) : !aie.objectfifosubview> %subview2_obj = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref %v88 = memref.load %subview2_obj[] : memref memref.store %v88, %buf83[%i3] : memref<4xi32> aie.objectfifo.release @fifo (Consume, 1) - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l1.mlir index a816be2c2..36d4c46bb 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l1.mlir @@ -1,92 +1,95 @@ -//===- AIE2_cyclostatic_l1.mlir --------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// In this cyclostatic pattern, the producer produces one object at a time -// and pushes them into L1 memory, shared with the adjacent consumer tile. -// The consumer consumes {1, 2, 1} elements, in that order. // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK: module @aie2_cyclostatic_l1 { -// CHECK: aie.device(xcve2302) { -// CHECK: %[[t0:.*]] = aie.tile(2, 2) -// CHECK: %[[t1:.*]] = aie.tile(2, 3) -// CHECK: %[[PL:.*]] = aie.lock(%[[t0]], 0) {init = 4 : i32, sym_name = "fifo_prod_lock"} -// CHECK: %[[CL:.*]] = aie.lock(%[[t0]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} -// CHECK: %[[c0:.*]] = aie.core(%[[t0]]) { -// CHECK: aie.use_lock(%[[PL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[CL]], Release, 1) -// CHECK: aie.use_lock(%[[PL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[CL]], Release, 1) -// CHECK: aie.use_lock(%[[PL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[CL]], Release, 1) -// CHECK: aie.use_lock(%[[PL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[CL]], Release, 1) -// CHECK: aie.end -// CHECK: } -// CHECK: %[[c1:.*]] = aie.core(%[[t1]]) { -// CHECK: aie.use_lock(%[[CL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[PL]], Release, 1) -// CHECK: aie.use_lock(%[[CL]], AcquireGreaterEqual, 2) -// CHECK: aie.use_lock(%[[PL]], Release, 2) -// CHECK: aie.use_lock(%[[CL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[PL]], Release, 1) -// CHECK: aie.end -// CHECK: } -// CHECK: } -// CHECK: } + +// CHECK-LABEL: aie.device(xcve2302) { +// CHECK: memref.global "public" @fifo : memref +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[FIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_0"} : memref +// CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref +// CHECK: %[[FIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_2"} : memref +// CHECK: %[[FIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_3"} : memref +// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i32, sym_name = "fifo_prod_lock"} +// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} +// CHECK: %[[BUF23:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "buf23"} : memref<4xi32> +// CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { +// CHECK: %[[C55_I32:.*]] = arith.constant 55 : i32 +// CHECK: %[[C66_I32:.*]] = arith.constant 66 : i32 +// CHECK: %[[C77_I32:.*]] = arith.constant 77 : i32 +// CHECK: %[[C88_I32:.*]] = arith.constant 88 : i32 +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C55_I32]], %[[FIFO_BUFF_0]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C66_I32]], %[[FIFO_BUFF_1]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C77_I32]], %[[FIFO_BUFF_2]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C88_I32]], %[[FIFO_BUFF_3]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: aie.end +// CHECK: } +// CHECK: %[[CORE_2_3:.*]] = aie.core(%[[TILE_2_3]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: %[[C3:.*]] = arith.constant 3 : index +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[VAL_0:.*]] = memref.load %[[FIFO_BUFF_0]][] : memref +// CHECK: memref.store %[[VAL_0]], %[[BUF23]]{{\[}}%[[C0]]] : memref<4xi32> +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], AcquireGreaterEqual, 2) +// CHECK: %[[VAL_1:.*]] = memref.load %[[FIFO_BUFF_1]][] : memref +// CHECK: %[[VAL_2:.*]] = memref.load %[[FIFO_BUFF_2]][] : memref +// CHECK: memref.store %[[VAL_1]], %[[BUF23]]{{\[}}%[[C1]]] : memref<4xi32> +// CHECK: memref.store %[[VAL_2]], %[[BUF23]]{{\[}}%[[C2]]] : memref<4xi32> +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], Release, 2) +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[VAL_3:.*]] = memref.load %[[FIFO_BUFF_3]][] : memref +// CHECK: memref.store %[[VAL_3]], %[[BUF23]]{{\[}}%[[C3]]] : memref<4xi32> +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], Release, 1) +// CHECK: aie.end +// CHECK: } +// CHECK: } module @aie2_cyclostatic_l1 { aie.device(xcve2302) { - %tile22 = aie.tile(2, 2) // producer tile %tile23 = aie.tile(2, 3) // consumer tile %buf23 = aie.buffer(%tile23) {sym_name = "buf23"} : memref<4xi32> - // ObjectFifo that can hold 4 memrefs, populated by tile22 and // consumed by tile23 aie.objectfifo @fifo (%tile22, {%tile23}, 4 : i32) : !aie.objectfifo> - // Producer core %core22 = aie.core(%tile22) { %c55 = arith.constant 55 : i32 %c66 = arith.constant 66 : i32 %c77 = arith.constant 77 : i32 %c88 = arith.constant 88 : i32 - // Push 55 %subview0 = aie.objectfifo.acquire @fifo (Produce, 1) : !aie.objectfifosubview> %subview0_obj = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref memref.store %c55, %subview0_obj[] : memref aie.objectfifo.release @fifo (Produce, 1) - // Push 66 %subview1 = aie.objectfifo.acquire @fifo (Produce, 1) : !aie.objectfifosubview> %subview1_obj = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref memref.store %c66, %subview1_obj[] : memref aie.objectfifo.release @fifo (Produce, 1) - // Push 77 %subview2 = aie.objectfifo.acquire @fifo (Produce, 1) : !aie.objectfifosubview> %subview2_obj = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref memref.store %c77, %subview2_obj[] : memref aie.objectfifo.release @fifo (Produce, 1) - // Push 88 %subview3 = aie.objectfifo.acquire @fifo (Produce, 1) : !aie.objectfifosubview> %subview3_obj = aie.objectfifo.subview.access %subview3[0] : !aie.objectfifosubview> -> memref memref.store %c88, %subview3_obj[] : memref aie.objectfifo.release @fifo (Produce, 1) - aie.end } - // Consumer core %core23 = aie.core(%tile23) { // Consumer pattern: {1, 2, 1} @@ -94,14 +97,12 @@ module @aie2_cyclostatic_l1 { %i1 = arith.constant 1 : index %i2 = arith.constant 2 : index %i3 = arith.constant 3 : index - // Pop 1 object off queue %subview0 = aie.objectfifo.acquire @fifo (Consume, 1) : !aie.objectfifosubview> %subview0_obj = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref %v55 = memref.load %subview0_obj[] : memref memref.store %v55, %buf23[%i0] : memref<4xi32> aie.objectfifo.release @fifo (Consume, 1) - // Pop 2 objects off queue %subview1 = aie.objectfifo.acquire @fifo (Consume, 2) : !aie.objectfifosubview> %subview1_obj0 = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref @@ -111,14 +112,12 @@ module @aie2_cyclostatic_l1 { memref.store %v66, %buf23[%i1] : memref<4xi32> memref.store %v77, %buf23[%i2] : memref<4xi32> aie.objectfifo.release @fifo (Consume, 2) - // Pop 1 object off queue %subview2 = aie.objectfifo.acquire @fifo (Consume, 1) : !aie.objectfifosubview> %subview2_obj = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref %v88 = memref.load %subview2_obj[] : memref memref.store %v88, %buf23[%i3] : memref<4xi32> aie.objectfifo.release @fifo (Consume, 1) - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l2.mlir index 4f18782a0..ecea483a6 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_cyclostatic_l2.mlir @@ -1,290 +1,174 @@ -//===- AIE2_cyclostatic_l2.mlir --------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// In this example, an AIE core pushes data into a memtile, in a one-by-one -// fashion. The memtile forwards this one-by-one to a consumer tile. The -// consumer tile cyclostatically consumes {1, 2, 1} elements at a time. - -// The way this gets lowered is as follows: -// -// - On the producer tile, two buffers get allocated. Each time the producer -// wishes to push onto the objectFifo, the implementation alternates between -// the two buffers (ping-pong). This way, the previous buffer remains -// untouched while it is being pushed onto the stream. The other one can -// meanwhile be filled with the next object. -// -// - On the memory tile, objects are read in from the stream one-by-one. Since -// the objectFifo is allocated to hold _up to_ 4 elements, four buffers are -// provisioned on the memory tile, into which data from the stream is -// received. The "_cons" locks are used to notify the memory tile whenever -// a single new object is ready on the stream. As the objects get pushed -// from memory back out onto the stream, backpressure makes sure that no more -// elements are written to the stream than are read on the receiving end. -// Therefore, this boils down to forwarding objects one-by-one through the -// memory tile (irrespective of what chunk size the consumer consumes). -// -// - On the receiving consumer end, four buffers are also preallocated, into -// which the DMA copies objects arriving from the stream. This again is done -// object-by-object. If the consumer needs more than one object at once, it -// acquires the consumer locks multiple times. // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK: module @aie2_cyclostatic_l2 { -// CHECK: aie.device(xcve2302) { -// CHECK: %[[t0:.*]] = aie.tile(2, 2) -// CHECK: %[[t1:.*]] = aie.tile(2, 1) -// CHECK: %[[t2:.*]] = aie.tile(8, 3) - -// CHECK: %[[fifo1_cons_buff_0:.*]] = aie.buffer(%[[t2]]) {sym_name = "fifo1_cons_buff_0"} : memref<1xi32> -// CHECK: %[[fifo1_cons_buff_1:.*]] = aie.buffer(%[[t2]]) {sym_name = "fifo1_cons_buff_1"} : memref<1xi32> -// CHECK: %[[fifo1_cons_buff_2:.*]] = aie.buffer(%[[t2]]) {sym_name = "fifo1_cons_buff_2"} : memref<1xi32> -// CHECK: %[[fifo1_cons_buff_3:.*]] = aie.buffer(%[[t2]]) {sym_name = "fifo1_cons_buff_3"} : memref<1xi32> -// CHECK: %[[fifo1_cons_prod_lock:.*]] = aie.lock(%[[t2]], 0) {init = 4 : i32, sym_name = "fifo1_cons_prod_lock"} -// CHECK: %[[fifo1_cons_cons_lock:.*]] = aie.lock(%[[t2]], 1) {init = 0 : i32, sym_name = "fifo1_cons_cons_lock"} - -// The consume buffers are used at the receiving end of a stream to notify the -// sender to send more objects once they have been consumed. In this case, -// the (intermediary) consumer is the memtile. -// CHECK: %[[fifo0_cons_buff_0:.*]] = aie.buffer(%[[t1]]) {sym_name = "fifo0_cons_buff_0"} : memref<1xi32> -// CHECK: %[[fifo0_cons_buff_1:.*]] = aie.buffer(%[[t1]]) {sym_name = "fifo0_cons_buff_1"} : memref<1xi32> -// CHECK: %[[fifo0_cons_buff_2:.*]] = aie.buffer(%[[t1]]) {sym_name = "fifo0_cons_buff_2"} : memref<1xi32> -// CHECK: %[[fifo0_cons_buff_3:.*]] = aie.buffer(%[[t1]]) {sym_name = "fifo0_cons_buff_3"} : memref<1xi32> - -// CHECK: %[[fifo0_cons_prod_lock:.*]] = aie.lock(%[[t1]], 0) {init = 4 : i32, sym_name = "fifo0_cons_prod_lock"} -// CHECK: %[[fifo0_cons_cons_lock:.*]] = aie.lock(%[[t1]], 1) {init = 0 : i32, sym_name = "fifo0_cons_cons_lock"} - -// The objectFifo lowering creates two buffers (for ping-pong) on the producer -// side to which elements are written. -// CHECK: %[[fifo0_buff_0:.*]] = aie.buffer(%[[t0]]) {sym_name = "fifo0_buff_0"} : memref<1xi32> -// CHECK: %[[fifo0_buff_1:.*]] = aie.buffer(%[[t0]]) {sym_name = "fifo0_buff_1"} : memref<1xi32> - -// Whenever the prod lock can be acquired, the core can proceed to put another -// object into the fifo, i.e. there is space in the queue. -// CHECK: %[[fifo0_prod_lock:.*]] = aie.lock(%[[t0]], 0) {init = 2 : i32, sym_name = "fifo0_prod_lock"} - -// Whenever the cons lock can be acquired, there is an object available in the -// queue to be consumed. -// CHECK: %[[fifo0_cons_lock:.*]] = aie.lock(%[[t0]], 1) {init = 0 : i32, sym_name = "fifo0_cons_lock"} - -// CHECK: %[[buf83:.*]] = aie.buffer(%[[t2]]) {sym_name = "buf83"} : memref<1xi32> - -// We expect a flow out of t0's core into the memtile: -// CHECK: aie.flow(%[[t0]], DMA : 0, %[[t1]], DMA : 0) - -// Flow out of the memtile into t2's DMA. This is mostly analogous to the -// flow from t0 to the memtile. -// CHECK: aie.flow(%[[t1]], DMA : 0, %[[t2]], DMA : 0) - - -// ////////////////////////////////////////////////////////////////////////// // -// Producer core: -// ////////////////////////////////////////////////////////////////////////// // - -// CHECK: %[[c0:.*]] = aie.core(%[[t0]]) { -// CHECK: %c0 = arith.constant 0 : index -// CHECK: aie.use_lock(%[[fifo0_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: memref.store %c55_i32, %[[fifo0_buff_0]][%c0] : memref<1xi32> -// CHECK: aie.use_lock(%[[fifo0_cons_lock]], Release, 1) -// CHECK: aie.use_lock(%[[fifo0_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: memref.store %c66_i32, %[[fifo0_buff_1]][%c0] : memref<1xi32> -// CHECK: aie.use_lock(%[[fifo0_cons_lock]], Release, 1) -// CHECK: aie.use_lock(%[[fifo0_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: memref.store %c77_i32, %[[fifo0_buff_0]][%c0] : memref<1xi32> -// CHECK: aie.use_lock(%[[fifo0_cons_lock]], Release, 1) -// CHECK: aie.use_lock(%[[fifo0_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: memref.store %c88_i32, %[[fifo0_buff_1]][%c0] : memref<1xi32> -// CHECK: aie.use_lock(%[[fifo0_cons_lock]], Release, 1) -// CHECK: aie.end -// CHECK: } - - -// ////////////////////////////////////////////////////////////////////////// // -// Consumer core: -// ////////////////////////////////////////////////////////////////////////// // - -// CHECK: %[[c2:.*]] = aie.core(%[[t2]]) { -// CHECK: %c0 = arith.constant 0 : index -// CHECK: %c1 = arith.constant 1 : index -// CHECK: %c2 = arith.constant 2 : index -// CHECK: %c3 = arith.constant 3 : index - -// The fifo1_cons_cons_lock will be released with a value of 1 whenever the -// DMA received an object from the stream and wrote it to the buffer. First, -// we only want to consume one object, so it suffices to acquire this lock -// with a value of 1: -// CHECK: aie.use_lock(%[[fifo1_cons_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: %[[load0:.*]] = memref.load %[[fifo1_cons_buff_0]][%c0] : memref<1xi32> -// CHECK: aie.use_lock(%[[fifo1_cons_prod_lock]], Release, 1) - -// We released the lock above, meaning we are done with the one object we -// received. Now we want 2 _new_ objects, so the cons_cons lock is acquired -// twice, meaning it has to be released twice before both acquires succeed; -// this, again, meaning that the DMA has received two objects on the stream -// and put them in the respective buffers. -// CHECK: aie.use_lock(%[[fifo1_cons_cons_lock]], AcquireGreaterEqual, 2) -// CHECK: %[[load1:.*]] = memref.load %[[fifo1_cons_buff_1]][%c0] : memref<1xi32> -// CHECK: %[[load2:.*]] = memref.load %[[fifo1_cons_buff_2]][%c0] : memref<1xi32> -// CHECK: aie.use_lock(%[[fifo1_cons_prod_lock]], Release, 2) - -// Lastly, receive just one object: -// CHECK: aie.use_lock(%[[fifo1_cons_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: %[[load3:.*]] = memref.load %[[fifo1_cons_buff_3]][%c0] : memref<1xi32> -// CHECK: aie.use_lock(%[[fifo1_cons_prod_lock]], Release, 1) -// CHECK: aie.end -// CHECK: } - - -// ////////////////////////////////////////////////////////////////////////// // -// Producer tile's DMA: -// ////////////////////////////////////////////////////////////////////////// // - -// CHECK: %[[mem0:.*]] = aie.mem(%[[t0]]) { -// CHECK: %[[dma0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) - -// Memory to stream: As soon as we get an object in fifo0_buff_0, put it onto -// the stream, then move on to bb2. -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[fifo0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_buff_0]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo0_prod_lock]], Release, 1) -// CHECK: aie.next_bd ^bb2 - -// Now, if we get 4 bytes in fifo0_buff_1, put that on the stream, then -// go back to bb1. Ping-pong. -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[fifo0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_buff_1]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo0_prod_lock]], Release, 1) -// CHECK: aie.next_bd ^bb1 - -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } - - -// ////////////////////////////////////////////////////////////////////////// // -// Mem tile: -// ////////////////////////////////////////////////////////////////////////// // - -// CHECK: %[[memtile:.*]] = aie.memtile_dma(%[[t1]]) { -// CHECK: %[[VAL_25:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) - -// Fill our four buffers, fifo0_cons_buff_0 through fif0_cons_buff_3, -// allocated inside the memory tile, one by one (round robin) as we receive -// things through the stream: -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 -// CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_0]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_1]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_2]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], Release, 1) -// CHECK: aie.next_bd ^bb4 -// CHECK: ^bb4: // pred: ^bb3 -// CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_3]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], Release, 1) -// CHECK: aie.next_bd ^bb1 - -// Now map everything we read in back out onto the stream towards tile 2: -// CHECK: ^bb5: // pred: ^bb0 -// CHECK: %[[VAL_26:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb10) -// CHECK: ^bb6: // 2 preds: ^bb5, ^bb9 -// CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_0]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], Release, 1) -// CHECK: aie.next_bd ^bb7 -// CHECK: ^bb7: // pred: ^bb6 -// CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_1]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], Release, 1) -// CHECK: aie.next_bd ^bb8 -// CHECK: ^bb8: // pred: ^bb7 -// CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_2]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], Release, 1) -// CHECK: aie.next_bd ^bb9 -// CHECK: ^bb9: // pred: ^bb8 -// CHECK: aie.use_lock(%[[fifo0_cons_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo0_cons_buff_3]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo0_cons_prod_lock]], Release, 1) -// CHECK: aie.next_bd ^bb6 -// CHECK: ^bb10: // pred: ^bb5 -// CHECK: aie.end -// CHECK: } - - -// ////////////////////////////////////////////////////////////////////////// // -// Consumer tile's DMA: -// ////////////////////////////////////////////////////////////////////////// // - -// Things are read from the stream into memory object-by-object, -// irrespective of the number of objects that the consumer wants to consume -// at a time. This uses the separate _cons locks, which increase/decrease -// by one. - -// CHECK: %[[mem2:.*]] = aie.mem(%[[t2]]) { -// CHECK: %[[dma2:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 -// CHECK: aie.use_lock(%[[fifo1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo1_cons_buff_0]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo1_cons_cons_lock]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[fifo1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo1_cons_buff_1]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo1_cons_cons_lock]], Release, 1) -// CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[fifo1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo1_cons_buff_2]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo1_cons_cons_lock]], Release, 1) -// CHECK: aie.next_bd ^bb4 -// CHECK: ^bb4: // pred: ^bb3 -// CHECK: aie.use_lock(%[[fifo1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo1_cons_buff_3]] : memref<1xi32>, 0, 1) -// CHECK: aie.use_lock(%[[fifo1_cons_cons_lock]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb5: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: } -// CHECK: } - - -// ////////////////////////////////////////////////////////////////////////// // -// Test input: -// ////////////////////////////////////////////////////////////////////////// // +// CHECK-LABEL: aie.device(xcve2302) { +// CHECK: memref.global "public" @fifo1_cons : memref<1xi32> +// CHECK: memref.global "public" @fifo1 : memref<1xi32> +// CHECK: memref.global "public" @fifo0_cons : memref<1xi32> +// CHECK: memref.global "public" @fifo0 : memref<1xi32> +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) +// CHECK: %[[FIFO1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_0"} : memref<1xi32> +// CHECK: %[[FIFO1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_1"} : memref<1xi32> +// CHECK: %[[FIFO1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_2"} : memref<1xi32> +// CHECK: %[[FIFO1_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "fifo1_cons_buff_3"} : memref<1xi32> +// CHECK: %[[FIFO1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 0) {init = 4 : i32, sym_name = "fifo1_cons_prod_lock"} +// CHECK: %[[FIFO1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_8_3]], 1) {init = 0 : i32, sym_name = "fifo1_cons_cons_lock"} +// CHECK: %[[FIFO0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_0"} : memref<1xi32> +// CHECK: %[[FIFO0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_1"} : memref<1xi32> +// CHECK: %[[FIFO0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_2"} : memref<1xi32> +// CHECK: %[[FIFO0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "fifo0_cons_buff_3"} : memref<1xi32> +// CHECK: %[[FIFO0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 4 : i32, sym_name = "fifo0_cons_prod_lock"} +// CHECK: %[[FIFO0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "fifo0_cons_cons_lock"} +// CHECK: %[[FIFO0_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo0_buff_0"} : memref<1xi32> +// CHECK: %[[FIFO0_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo0_buff_1"} : memref<1xi32> +// CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "fifo0_prod_lock"} +// CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "fifo0_cons_lock"} +// CHECK: %[[BUF83:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf83"} : memref<1xi32> +// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_1]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_8_3]], DMA : 0) +// CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C55_I32:.*]] = arith.constant 55 : i32 +// CHECK: %[[C66_I32:.*]] = arith.constant 66 : i32 +// CHECK: %[[C77_I32:.*]] = arith.constant 77 : i32 +// CHECK: %[[C88_I32:.*]] = arith.constant 88 : i32 +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C55_I32]], %[[FIFO0_BUFF_0]]{{\[}}%[[C0]]] : memref<1xi32> +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C66_I32]], %[[FIFO0_BUFF_1]]{{\[}}%[[C0]]] : memref<1xi32> +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C77_I32]], %[[FIFO0_BUFF_0]]{{\[}}%[[C0]]] : memref<1xi32> +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C88_I32]], %[[FIFO0_BUFF_1]]{{\[}}%[[C0]]] : memref<1xi32> +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], Release, 1) +// CHECK: aie.end +// CHECK: } +// CHECK: %[[CORE_8_3:.*]] = aie.core(%[[TILE_8_3]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: %[[C3:.*]] = arith.constant 3 : index +// CHECK: aie.use_lock(%[[FIFO1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[VAL_0:.*]] = memref.load %[[FIFO1_CONS_BUFF_0]]{{\[}}%[[C0]]] : memref<1xi32> +// CHECK: memref.store %[[VAL_0]], %[[BUF83]]{{\[}}%[[C0]]] : memref<1xi32> +// CHECK: aie.use_lock(%[[FIFO1_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO1_CONS_CONS_LOCK]], AcquireGreaterEqual, 2) +// CHECK: %[[VAL_1:.*]] = memref.load %[[FIFO1_CONS_BUFF_1]]{{\[}}%[[C0]]] : memref<1xi32> +// CHECK: %[[VAL_2:.*]] = memref.load %[[FIFO1_CONS_BUFF_2]]{{\[}}%[[C0]]] : memref<1xi32> +// CHECK: memref.store %[[VAL_1]], %[[BUF83]]{{\[}}%[[C1]]] : memref<1xi32> +// CHECK: memref.store %[[VAL_2]], %[[BUF83]]{{\[}}%[[C2]]] : memref<1xi32> +// CHECK: aie.use_lock(%[[FIFO1_CONS_PROD_LOCK]], Release, 2) +// CHECK: aie.use_lock(%[[FIFO1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[VAL_3:.*]] = memref.load %[[FIFO1_CONS_BUFF_3]]{{\[}}%[[C0]]] : memref<1xi32> +// CHECK: memref.store %[[VAL_3]], %[[BUF83]]{{\[}}%[[C3]]] : memref<1xi32> +// CHECK: aie.use_lock(%[[FIFO1_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_4:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO0_BUFF_0]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO0_BUFF_1]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { +// CHECK: %[[VAL_5:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[FIFO0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO0_CONS_BUFF_0]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO0_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[FIFO0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO0_CONS_BUFF_1]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO0_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb3 +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[FIFO0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO0_CONS_BUFF_2]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO0_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb4 +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[FIFO0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO0_CONS_BUFF_3]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO0_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb5: +// CHECK: %[[VAL_6:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb10) +// CHECK: ^bb6: +// CHECK: aie.use_lock(%[[FIFO0_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO0_CONS_BUFF_0]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO0_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb7 +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[FIFO0_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO0_CONS_BUFF_1]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO0_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb8 +// CHECK: ^bb8: +// CHECK: aie.use_lock(%[[FIFO0_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO0_CONS_BUFF_2]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO0_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb9 +// CHECK: ^bb9: +// CHECK: aie.use_lock(%[[FIFO0_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO0_CONS_BUFF_3]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO0_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb6 +// CHECK: ^bb10: +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEM_8_3:.*]] = aie.mem(%[[TILE_8_3]]) { +// CHECK: %[[VAL_7:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[FIFO1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO1_CONS_BUFF_0]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO1_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[FIFO1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO1_CONS_BUFF_1]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO1_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb3 +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[FIFO1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO1_CONS_BUFF_2]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO1_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb4 +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[FIFO1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FIFO1_CONS_BUFF_3]] : memref<1xi32>, 0, 1) +// CHECK: aie.use_lock(%[[FIFO1_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb5: +// CHECK: aie.end +// CHECK: } +// CHECK: } module @aie2_cyclostatic_l2 { aie.device(xcve2302) { - %tile22 = aie.tile(2, 2) // producer tile %memtile = aie.tile(2, 1) // mem tile %tile83 = aie.tile(8, 3) // consumer tile %buf83 = aie.buffer(%tile83) {sym_name = "buf83"} : memref<1xi32> - // ObjectFifo that can hold 4 memref<1xi32>s, populated by tile22 and // consumed by tile23 aie.objectfifo @fifo0 (%tile22, {%memtile}, 4 : i32) : !aie.objectfifo> aie.objectfifo @fifo1 (%memtile, {%tile83}, [4, 4]) : !aie.objectfifo> aie.objectfifo.link [@fifo0] -> [@fifo1] () - // Producer core %core22 = aie.core(%tile22) { %i0 = arith.constant 0 : index @@ -292,34 +176,28 @@ module @aie2_cyclostatic_l2 { %c66 = arith.constant 66 : i32 %c77 = arith.constant 77 : i32 %c88 = arith.constant 88 : i32 - // Push 55 %subview0 = aie.objectfifo.acquire @fifo0 (Produce, 1) : !aie.objectfifosubview> %subview0_obj = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref<1xi32> memref.store %c55, %subview0_obj[%i0] : memref<1xi32> aie.objectfifo.release @fifo0 (Produce, 1) - // Push 66 %subview1 = aie.objectfifo.acquire @fifo0 (Produce, 1) : !aie.objectfifosubview> %subview1_obj = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref<1xi32> memref.store %c66, %subview1_obj[%i0] : memref<1xi32> aie.objectfifo.release @fifo0 (Produce, 1) - // Push 77 %subview2 = aie.objectfifo.acquire @fifo0 (Produce, 1) : !aie.objectfifosubview> %subview2_obj = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref<1xi32> memref.store %c77, %subview2_obj[%i0] : memref<1xi32> aie.objectfifo.release @fifo0 (Produce, 1) - // Push 88 %subview3 = aie.objectfifo.acquire @fifo0 (Produce, 1) : !aie.objectfifosubview> %subview3_obj = aie.objectfifo.subview.access %subview3[0] : !aie.objectfifosubview> -> memref<1xi32> memref.store %c88, %subview3_obj[%i0] : memref<1xi32> aie.objectfifo.release @fifo0 (Produce, 1) - aie.end } - // Consumer core %core28 = aie.core(%tile83) { // Consumer pattern: {1, 2, 1} @@ -327,14 +205,12 @@ module @aie2_cyclostatic_l2 { %i1 = arith.constant 1 : index %i2 = arith.constant 2 : index %i3 = arith.constant 3 : index - // Pop 1 object off queue %subview0 = aie.objectfifo.acquire @fifo1 (Consume, 1) : !aie.objectfifosubview> %subview0_obj = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref<1xi32> %v55 = memref.load %subview0_obj[%i0] : memref<1xi32> memref.store %v55, %buf83[%i0] : memref<1xi32> aie.objectfifo.release @fifo1 (Consume, 1) - // Pop 2 objects off queue %subview1 = aie.objectfifo.acquire @fifo1 (Consume, 2) : !aie.objectfifosubview> %subview1_obj0 = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref<1xi32> @@ -344,16 +220,13 @@ module @aie2_cyclostatic_l2 { memref.store %v66, %buf83[%i1] : memref<1xi32> memref.store %v77, %buf83[%i2] : memref<1xi32> aie.objectfifo.release @fifo1 (Consume, 2) - // Pop 1 object off queue %subview2 = aie.objectfifo.acquire @fifo1 (Consume, 1) : !aie.objectfifosubview> %subview2_obj = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref<1xi32> %v88 = memref.load %subview2_obj[%i0] : memref<1xi32> memref.store %v88, %buf83[%i3] : memref<1xi32> aie.objectfifo.release @fifo1 (Consume, 1) - aie.end } - } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_delayed_release.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_delayed_release.mlir index b3d4f5df3..44082c4dd 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_delayed_release.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_delayed_release.mlir @@ -1,130 +1,63 @@ -//===- AIE2_delayed_release.mlir -------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// The expected semantics of objectFIFO aquire/releases are such that the most -// recent acquire will always name the _total_ number of elements available -// to the core. For example, an acquire(2) followed by an acquire(1) means that -// after the second acquire, the core can only read one object (not three!), -// even though none of the previously acquired elements haven't been freed. -// Essentially, the smaller-numbered acquire will reduce the set of legally -// accessible objects. (The remaining accessible element will be the same as -// the most recent one of the previously acquired two elements.) - -// objectFifo (capacity 4) -// [ | | | | ] -// x x after acquire(2) x = consumable data -// . x after acquire(1) . = produced, not yet freed -// after release(2) (all slots empty, ready for produce) - -// You always want to release(max(acquire no. since last release)) - -// This tests ensures that locks are acquired correctly to preserve these -// semantics. // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK: module @AIE2_delayed_release { -// CHECK: aie.device(xcve2302) { -// CHECK: %[[tile0:.*]] = aie.tile(2, 2) -// CHECK: %[[tile1:.*]] = aie.tile(2, 3) -// CHECK: %[[fifo_buff_0:.*]] = aie.buffer(%[[tile0]]) {sym_name = "fifo_buff_0"} : memref -// CHECK: %[[fifo_buff_1:.*]] = aie.buffer(%[[tile0]]) {sym_name = "fifo_buff_1"} : memref -// CHECK: %[[fifo_buff_2:.*]] = aie.buffer(%[[tile0]]) {sym_name = "fifo_buff_2"} : memref -// CHECK: %[[fifo_buff_3:.*]] = aie.buffer(%[[tile0]]) {sym_name = "fifo_buff_3"} : memref -// CHECK: %[[fifo_prod_lock:.*]] = aie.lock(%[[tile0]], 0) {init = 4 : i32, sym_name = "fifo_prod_lock"} -// CHECK: %[[fifo_cons_lock:.*]] = aie.lock(%[[tile0]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} -// CHECK: %[[buf23:.*]] = aie.buffer(%[[tile1]]) {sym_name = "buf23"} : memref<4xi32> -// CHECK: %[[core0:.*]] = aie.core(%[[tile0]]) { -// CHECK: %c99_i32 = arith.constant 99 : i32 -// CHECK: %c0 = arith.constant 0 : index -// CHECK: %c1 = arith.constant 1 : index -// CHECK: %c4 = arith.constant 4 : index - -// # Objects Held: 0 # Objects Requested: 1 # Acquire Needed: 1 -// CHECK: aie.use_lock(%[[fifo_prod_lock]], AcquireGreaterEqual, 1) -// # Objects Held: 1 -// CHECK: memref.store %c99_i32, %[[fifo_buff_0]][] : memref -// CHECK: aie.use_lock(%[[fifo_cons_lock]], Release, 1) -// # Objects Held: 0 (After release) - -// # Objects Held: 0 # Objects Requested: 1 # Acquire Needed: 1 -// CHECK: aie.use_lock(%[[fifo_prod_lock]], AcquireGreaterEqual, 1) -// # Objects Held: 1 -// CHECK: memref.store %c99_i32, %[[fifo_buff_1]][] : memref -// CHECK: aie.use_lock(%[[fifo_cons_lock]], Release, 1) -// # Objects Held: 0 (After release) - -// # Objects Held: 0 # Objects Requested: 1 # Acquire Needed: 1 -// CHECK: aie.use_lock(%[[fifo_prod_lock]], AcquireGreaterEqual, 1) -// # Objects Held: 1 -// CHECK: memref.store %c99_i32, %[[fifo_buff_2]][] : memref -// CHECK: aie.use_lock(%[[fifo_cons_lock]], Release, 1) -// # Objects Held: 0 (After release) - -// # Objects Held: 0 # Objects Requested: 1 # Acquire Needed: 1 -// CHECK: aie.use_lock(%[[fifo_prod_lock]], AcquireGreaterEqual, 1) -// # Objects Held: 1 -// CHECK: memref.store %c99_i32, %[[fifo_buff_3]][] : memref -// CHECK: aie.use_lock(%[[fifo_cons_lock]], Release, 1) -// # Objects Held: 0 (After release) -// CHECK: aie.end -// CHECK: } - -// CHECK: %[[core1:.*]] = aie.core(%[[tile1]]) { -// CHECK: %c0 = arith.constant 0 : index -// CHECK: %c1 = arith.constant 1 : index -// CHECK: %c2 = arith.constant 2 : index -// CHECK: %c3 = arith.constant 3 : index - -// -- Requested: 2 -- -// # Objects Held: 0 # Objects Requested: 2 # Acquire Needed: 2 -// CHECK: aie.use_lock(%[[fifo_cons_lock]], AcquireGreaterEqual, 2) -// # Objects Held: 2 - -// CHECK: %[[VAL_11:.*]] = memref.load %[[fifo_buff_0]][] : memref -// CHECK: memref.store %[[VAL_11]], %[[buf23]][%c0] : memref<4xi32> - -// -- Requested: 1 -- -// Since we already hold 2, we expect not to see any lock acquires here. -// # Objects Held: 2 # Objects Requested: 1 # Acquire Needed: 0 -// CHECK: %[[VAL_12:.*]] = memref.load %[[fifo_buff_0]][] : memref -// CHECK: memref.store %[[VAL_12]], %[[buf23]][%c1] : memref<4xi32> - -// -- Requested: 3 -- -// Since we already hold 2 and are requesting 3, we expect one acquire here. -// # Objects Held: 2 # Objects Requested: 3 # Acquire Needed: 1 -// CHECK: aie.use_lock(%[[fifo_cons_lock]], AcquireGreaterEqual, 1) -// # Objects Held: 3 -// CHECK: %[[VAL_13:.*]] = memref.load %[[fifo_buff_0]][] : memref -// CHECK: memref.store %[[VAL_13]], %[[buf23]][%c2] : memref<4xi32> - -// -- Requested: 1 -- -// # Objects Held: 3 # Objects Requested: 1 # Acquire Needed: 0 -// CHECK: %[[VAL_14:.*]] = memref.load %[[fifo_buff_0]][] : memref -// CHECK: memref.store %[[VAL_14]], %[[buf23]][%c3] : memref<4xi32> - -// These releases should all succeed. -// CHECK: aie.use_lock(%[[fifo_prod_lock]], Release, 3) -// CHECK: aie.end -// CHECK: } -// CHECK: } -// CHECK: } +// CHECK-LABEL: aie.device(xcve2302) { +// CHECK: memref.global "public" @fifo : memref +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[FIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_0"} : memref +// CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref +// CHECK: %[[FIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_2"} : memref +// CHECK: %[[FIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_3"} : memref +// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i32, sym_name = "fifo_prod_lock"} +// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} +// CHECK: %[[BUF23:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "buf23"} : memref<4xi32> +// CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { +// CHECK: %[[C99_I32:.*]] = arith.constant 99 : i32 +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C4:.*]] = arith.constant 4 : index +// CHECK: %[[C4_0:.*]] = arith.constant 4 : index +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C99_I32]], %[[FIFO_BUFF_0]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C99_I32]], %[[FIFO_BUFF_1]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C99_I32]], %[[FIFO_BUFF_2]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C99_I32]], %[[FIFO_BUFF_3]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: aie.end +// CHECK: } +// CHECK: %[[CORE_2_3:.*]] = aie.core(%[[TILE_2_3]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: %[[C3:.*]] = arith.constant 3 : index +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], AcquireGreaterEqual, 2) +// CHECK: %[[VAL_0:.*]] = memref.load %[[FIFO_BUFF_0]][] : memref +// CHECK: memref.store %[[VAL_0]], %[[BUF23]]{{\[}}%[[C0]]] : memref<4xi32> +// CHECK: %[[VAL_1:.*]] = memref.load %[[FIFO_BUFF_0]][] : memref +// CHECK: memref.store %[[VAL_1]], %[[BUF23]]{{\[}}%[[C1]]] : memref<4xi32> +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[VAL_2:.*]] = memref.load %[[FIFO_BUFF_0]][] : memref +// CHECK: memref.store %[[VAL_2]], %[[BUF23]]{{\[}}%[[C2]]] : memref<4xi32> +// CHECK: %[[VAL_3:.*]] = memref.load %[[FIFO_BUFF_0]][] : memref +// CHECK: memref.store %[[VAL_3]], %[[BUF23]]{{\[}}%[[C3]]] : memref<4xi32> +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], Release, 3) +// CHECK: aie.end +// CHECK: } +// CHECK: } module @AIE2_delayed_release { aie.device(xcve2302) { %tile22 = aie.tile(2, 2) %tile23 = aie.tile(2, 3) %buf23 = aie.buffer(%tile23) {sym_name = "buf23"} : memref<4xi32> - aie.objectfifo @fifo (%tile22, {%tile23}, 4 : i32) : !aie.objectfifo> - // Producer -- produces one element at a time %core22 = aie.core(%tile22) { %c99 = arith.constant 99 : i32 @@ -141,41 +74,34 @@ module @AIE2_delayed_release { } aie.end } - // Consumer -- consumes {2, 1, 3, 1}; releases {0, 0, 0, 2} %core23 = aie.core(%tile23) { %i0 = arith.constant 0 : index %i1 = arith.constant 1 : index %i2 = arith.constant 2 : index %i3 = arith.constant 3 : index - // Begin consuming 2 elements (acquire consumer lock with value 2) %subview0 = aie.objectfifo.acquire @fifo (Consume, 2) : !aie.objectfifosubview> %subview0_obj = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref %v0 = memref.load %subview0_obj[] : memref memref.store %v0, %buf23[%i0] : memref<4xi32> - // For the next step, we only need one element (this could be a subroutine that acquires 1, not knowing that we already acquired 2) %subview1 = aie.objectfifo.acquire @fifo (Consume, 1) : !aie.objectfifosubview> %subview1_obj = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref %v1 = memref.load %subview1_obj[] : memref memref.store %v1, %buf23[%i1] : memref<4xi32> - // Actually, give us the two from before and one more for three objects total (consumer lock should increase by one) %subview2 = aie.objectfifo.acquire @fifo (Consume, 3) : !aie.objectfifosubview> %subview2_obj = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref %v2 = memref.load %subview2_obj[] : memref memref.store %v2, %buf23[%i2] : memref<4xi32> - // Now let's just work on one element (consumer lock should not change value) %subview3 = aie.objectfifo.acquire @fifo (Consume, 1) : !aie.objectfifosubview> %subview3_obj = aie.objectfifo.subview.access %subview3[0] : !aie.objectfifosubview> -> memref %v3 = memref.load %subview3_obj[] : memref memref.store %v3, %buf23[%i3] : memref<4xi32> - // Done, let's release everything we hold (we hold 3 objects from our max acquire) aie.objectfifo.release @fifo (Consume, 3) - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_delayed_release_inside_funcs.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_delayed_release_inside_funcs.mlir deleted file mode 100644 index 03246a15b..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_delayed_release_inside_funcs.mlir +++ /dev/null @@ -1,103 +0,0 @@ -//===- AIE2_delayed_release_inside_funcs.mlir ------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// This tests ensures that locks are acquired correctly to preserve the same -// semantics as in the AIE2_delayed_release.mlir test, even if the acquires -// and releases happen across function calls. - -// What this boils down to is simply verifying that an error is generated -// when acquire/release is called from within a function. If this behavior -// is ever to be changed, this test can easily be adapted to make sure -// semantics are preserved. - -// RUN: iree-opt --verify-diagnostics --aie-objectFifo-stateful-transform %s - -module @AIE2_delayed_release { - aie.device(xcve2302) { - %tile22 = aie.tile(2, 2) - %tile23 = aie.tile(2, 3) - %buf23 = aie.buffer(%tile23) {sym_name = "buf23"} : memref<4xi32> - - aie.objectfifo @fifo (%tile22, {%tile23}, 4 : i32) : !aie.objectfifo> - - // Producer -- produces one element at a time - %core22 = aie.core(%tile22) { - %c99 = arith.constant 99 : i32 - %i0 = arith.constant 0 : index - %i1 = arith.constant 1 : index - %i4 = arith.constant 4 : index - scf.for %it = %i0 to %i4 step %i1 { - // Produce one 1 element (acquire producer lock) ... - %subview = aie.objectfifo.acquire @fifo (Produce, 1) : !aie.objectfifosubview> - %subview_obj = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref - memref.store %c99, %subview_obj[] : memref - aie.objectfifo.release @fifo (Produce, 1) - // ... done producing (release consumer lock) - } - aie.end - } - - // The following three functions encapsulate the consumers functionality - - func.func @step1(%buf : memref<4xi32>) -> () { - %i0 = arith.constant 0 : index - // Begin consuming 2 elements (acquire consumer lock with value 2) - // expected-error@+1 {{op must be called from inside a CoreOp}} - %subview0 = aie.objectfifo.acquire @fifo (Consume, 2) : !aie.objectfifosubview> - %subview0_obj = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref - %v0 = memref.load %subview0_obj[] : memref - memref.store %v0, %buf[%i0] : memref<4xi32> - return - } - - func.func @step2(%buf : memref<4xi32>) -> () { - %i1 = arith.constant 1 : index - // For the next step, we only need one element (this could be a subroutine that acquires 1, not knowing that we already acquired 2) - %subview1 = aie.objectfifo.acquire @fifo (Consume, 1) : !aie.objectfifosubview> - %subview1_obj = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref - %v1 = memref.load %subview1_obj[] : memref - memref.store %v1, %buf[%i1] : memref<4xi32> - return - } - - func.func @step3(%buf : memref<4xi32>) -> () { - %i2 = arith.constant 2 : index - // Actually, give us the two from before and one more for three objects total (consumer lock should increase by one) - %subview2 = aie.objectfifo.acquire @fifo (Consume, 3) : !aie.objectfifosubview> - %subview2_obj = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref - %v2 = memref.load %subview2_obj[] : memref - memref.store %v2, %buf[%i2] : memref<4xi32> - return - } - - func.func @step4(%buf : memref<4xi32>) -> () { - %i3 = arith.constant 3 : index - // Now let's just work on one element (consumer lock should not change value) - %subview3 = aie.objectfifo.acquire @fifo (Consume, 1) : !aie.objectfifosubview> - %subview3_obj = aie.objectfifo.subview.access %subview3[0] : !aie.objectfifosubview> -> memref - %v3 = memref.load %subview3_obj[] : memref - memref.store %v3, %buf[%i3] : memref<4xi32> - return - } - - // Consumer -- consumes {2, 1, 3, 1}; releases {0, 0, 0, 2} - %core23 = aie.core(%tile23) { - func.call @step1(%buf23) : (memref<4xi32>) -> () - func.call @step2(%buf23) : (memref<4xi32>) -> () - func.call @step3(%buf23) : (memref<4xi32>) -> () - func.call @step4(%buf23) : (memref<4xi32>) -> () - - // Done, let's release everything we hold (we hold 3 objects from our max acquire) - aie.objectfifo.release @fifo (Consume, 3) - - aie.end - } - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_dynamic_locks.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_dynamic_locks.mlir deleted file mode 100644 index e6045180d..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_dynamic_locks.mlir +++ /dev/null @@ -1,198 +0,0 @@ -//===- AIE2_dynamic_locks.mlir ---------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// This test uses the objectFifo in a context where the number of held objects -// cannot be (easily) determined statically. -// -// Note that an objectFifo.acquire and objectFifo.release always denotes -// the _absolute_ number of objects we wish to be able to access after the -// operation completes. To enable this, however, we need to acquire or release -// a number of locks relative to the number of objects already held. For -// example, if we already hold a producer lock to create 2 objects, and we -// call objectFifo.acquire(..., 2), ZERO more locks need to be -// acquired. -// -// Therefore, we must do bookkeeping to know for each acquire/release how much -// to increment/decrement locks by. This is not always statically possible -// (e.g. inside functions that can be called from anywhere, with any number -// of locks held). - -// RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s - -// The following is an idea of how a dynamically managed objectFifo could look -// like, where lock acquire/release numbers are not known statically. The -// test currently fails because this is only a concept and not yet implemented: - -// CHECK: module @aie2_dynamic_locks { -// CHECK: aie.device(xcve2302) { -// CHECK: %[[tile23:.*]] = aie.tile(2, 2) -// CHECK: %[[tile43:.*]] = aie.tile(4, 3) - -// The setup for flows, locks, and buffers can be the same in the dynamic case: -// CHECK: %[[fifo_buff_0:.*]] = aie.buffer(%[[tile23]]) {sym_name = "fifo_buff_0"} : memref -// CHECK: %[[fifo_prod_lock:.*]] = aie.lock(%[[tile23]], 0) {init = 1 : i32, sym_name = "fifo_prod_lock"} -// CHECK: %[[fifo_cons_lock:.*]] = aie.lock(%[[tile23]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} -// CHECK: %[[fifo_cons_buff_0:.*]] = aie.buffer(%[[tile43]]) {sym_name = "fifo_cons_buff_0"} : memref -// CHECK: %[[fifo_cons_prod_lock:.*]] = aie.lock(%[[tile43]], 0) {init = 1 : i32, sym_name = "fifo_cons_prod_lock"} -// CHECK: %[[fifo_cons_cons_lock:.*]] = aie.lock(%[[tile43]], 1) {init = 0 : i32, sym_name = "fifo_cons_cons_lock"} -// CHECK: aie.flow(%[[tile23]], DMA : 0, %[[tile43]], DMA : 0) - -// CHECK: %[[ssa8:.*]] = aie.core(%[[tile23]]) { -// CHECK: %c0 = arith.constant 0 : index -// CHECK: %c1 = arith.constant 1 : index -// CHECK: %c3 = arith.constant 3 : index -// CHECK: %c16 = arith.constant 16 : index -// CHECK: %c1_i64 = arith.constant 1 : i64 - -// We need a SSA value that keeps track of the number of objects currently -// held so the lock acquire can be appropriately increased/decreased. -// At a lower level, we would do this with PHI nodes, which in MLIR look like -// arguments to the basic blocks. The "scf" dialect can also generated phi -// nodes by using iter_args, and scf.yield, which we use here (untested, -// and I have not used this before so it may be wrong, but the idea is to -// have the value change from iteration to iteration). - -// This is what currently is being generated: -// aie.use_lock(%[[fifo_prod_lock]], AcquireGreaterEqual, 1) -// Instead: -// Initialize the number of objects held, which is always zero at the -// beginning before any acquires: -// CHECK: %[[lock0_num0:.*]] = arith.constant 0 : i32 -// The number of objects to acquire is statically encoded as a constant (this -// is XXX copied straight from the argument to acquire(..., XXX)) -// CHECK: %[[uselock0_target:.*]] = arith.constant 1 : i32 -// Calculate the difference between currently held objects and how many we -// target, then acquire that many: -// CHECK: %[[uselock0_diff:.*]] = arith.subi %[[lock0_num0]], %[[uselock0_target:.*]] : i32 -// If the difference is greater than zero, this means we want more objects -// than we already hold. Therefore we need to acquire a lock. If it is smaller -// (the below SSA evaluates to false), no additional locks need to be -// acquired. -// CHECK: %[[uselock0_need_acq:.*]] = arith.cmpi "sgt" %[[uselock0_diff]], 1 : i32 -// If we enter the if condition, we acquire more objects, thus must update our -// SSA value for the number of objects currently held. -// CHECK: %[[lock0_num1:.*]] = scf.if %[[uselock0_need_acq]] -> (i32) { -// The only thing that is different about acquiring the lock is that we use -// a new useLockDyn that takes an SSA value instead of a constant for the -// lock value, so that it can be dynamic. -// CHECK: aiex.useLockDyn(%[[fifo_prod_lock]], AcquireGreaterEqual, %[[uselock0_diff]]) -// We also need to update how many elements we hold now that we acquired more: -// CHECK: %[[uselock0_newnum:.*]] = arith.addi %[[lock0_num0]], 1 : i32 -// CHECK: scf.yield %[[uselock0_newnum]] -// CHECK: } else { -// The number of objects held remains unchanged since we did not need to -// acquire any additional ones: -// CHECK: scf.yield %[[lock0_num0]] -// } - -// No release in input code here, so there's nothing for lowering it here -// either. Let's go into the loop. - -// CHECK: %c1_0 = arith.constant 1 : index - -// The number of objects held varies from iteration to iteration. In scf we -// can treat this as if the loop was a function and the number of locks held -// were an argument to the loop function. `scf.yield` tells what the value for -// that argument will be on the next iteration. The value assigned in the -// `iter_args()` is the value it will hold on the first iteration. -// CHECK: %[[lock0_num2]] = scf.for %arg0 = %c0 to %c3 step %c1_0 iter_args(%[[lock0_num_iter:.*]] = %[[lock0_num1]]) -> (i32) { - -// Acquire inside loop: -// The current implementation does not generate a lock acquire here at all. -// We need one, but only on the second iteration. The same code as above will -// figure this out: -// CHECK: %[[uselock1_target:.*]] = arith.constant 1 : i32 -// CHECK: %[[uselock1_diff:.*]] = arith.subi %[[lock0_num_iter]], %[[uselock1_target:.*]] : i32 -// CHECK: %[[uselock1_need_acq:.*]] = arith.cmpi "sgt" %[[uselock1_diff]], 1 : i32 -// CHECK: %[[lock0_num3:.*]] = scf.if %[[uselock1_need_acq]] -> (i32) { -// CHECK: aiex.useLockDyn(%[[fifo_prod_lock]], AcquireGreaterEqual, %[[uselock1_diff]]) -// CHECK: %[[uselock1_newnum:.*]] = arith.addi %[[lock0_num_iter]], 1 : i32 -// CHECK: scf.yield %[[uselock1_newnum]] -// CHECK: } else { -// CHECK: scf.yield %[[lock0_num_iter]] -// } -// CHECK: memref.store %c1_i64, %[[fifo_buff_0]][] : memref - -// Release inside loop: -// The release will always release, but additionally to -// CHECK: aie.use_lock(%[[fifo_cons_lock]], Release, 1) -// CHECK: %[[lock0_num4:.*]] = arith.subi %[[lock0_num3]], 1 : i32 - -// At the very end of the loop, we need to yield how many objects are being held -// after all the acquires and releases inside the loop: -// CHECK: scf.yield %lock0_num4 -// CHECK: } -// CHECK: aie.end -// CHECK: } - -// The DMAs should remain all the same and will be configured statically: -// CHECK: %[[ssa9:.*]] = aie.mem(%[[tile23]]) { -// CHECK: %11 = aie.dma_start(MM2S, 0, ^bb1, ^bb2) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 -// CHECK: aie.use_lock(%[[fifo_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo_buff_0]] : memref, 0, 1) -// CHECK: aie.use_lock(%[[fifo_prod_lock]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: %10 = aie.mem(%[[tile43]]) { -// CHECK: %11 = aie.dma_start(S2MM, 0, ^bb1, ^bb2) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 -// CHECK: aie.use_lock(%[[fifo_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[fifo_cons_buff_0]] : memref, 0, 1) -// CHECK: aie.use_lock(%[[fifo_cons_cons_lock]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: } -// CHECK: } - - -// Again, none of this has been implemented yet, so we expect this all to fail: -// XFAIL: * - - -module @aie2_dynamic_locks { - aie.device(xcve2302) { - %tile22 = aie.tile(2, 2) // producer tile - %tile43 = aie.tile(4, 3) // consumer tile - aie.objectfifo @fifo (%tile22, {%tile43}, 1 : i32) : !aie.objectfifo> - - // Producer core - %core22 = aie.core(%tile22) { - // Initialize value to zero - %i_c0 = arith.constant 0 : index - %i_c1 = arith.constant 1 : index - %i_c3 = arith.constant 3 : index - %i_c16 = arith.constant 16 : index - %c1 = arith.constant 1 : i64 - - // Acquire one element. - %subview0 = aie.objectfifo.acquire @fifo (Produce, 1) : !aie.objectfifosubview> - - scf.for %idx = %i_c0 to %i_c3 step %i_c1 { - // Acquire one element (again). In the first iteration of the - // loop, this does not require taking any additional locks, - // since we already hold an element from the acquire - // just above the loop. In the second iteration, that object - // has been released, and now a lock acquire 1 would be - // required. - %subview = aie.objectfifo.acquire @fifo (Produce, 1) : !aie.objectfifosubview> - %elem = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref - memref.store %c1, %elem[] : memref - aie.objectfifo.release @fifo (Produce, 1) - } - - aie.end - } - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_static_l1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_static_l1.mlir index 5f266303e..d08ee86f7 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_static_l1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/AIE2_static_l1.mlir @@ -1,49 +1,100 @@ -//===- AIE2_static_l1.mlir -------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// This tests a static pattern where a producer writes one element and a -// consumer consumes two elements at a time. The cores are adjacent to -// one another and should use shared memory. -// In this case, "objects" really are just simple i32s. -// The producer simply counts up from 0, step size 1. -// The consumer copies what it sees into %dstbuf23. -// In the end, %dstbuf23 should hold [0, 1, 2, 3, 4, 5, ... 15] // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK: %[[t0:.*]] = aie.tile(2, 2) -// CHECK: %[[t1:.*]] = aie.tile(2, 3) -// CHECK: %[[PL:.*]] = aie.lock(%[[t0]], 0) {init = 4 : i32, sym_name = "fifo_prod_lock"} -// CHECK: %[[CL:.*]] = aie.lock(%[[t0]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} -// CHECK: %[[c0:.*]] = aie.core(%[[t0]]) { -// CHECK: aie.use_lock(%[[PL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[CL]], Release, 1) -// CHECK: aie.use_lock(%[[PL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[CL]], Release, 1) -// CHECK: aie.use_lock(%[[PL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[CL]], Release, 1) -// CHECK: aie.use_lock(%[[PL]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[CL]], Release, 1) -// CHECK: aie.end -// CHECK: } -// CHECK: %[[c1:.*]] = aie.core(%[[t1]]) { -// CHECK: aie.use_lock(%[[CL]], AcquireGreaterEqual, 2) -// CHECK: aie.use_lock(%[[PL]], Release, 2) -// CHECK: aie.use_lock(%[[CL]], AcquireGreaterEqual, 2) -// CHECK: aie.use_lock(%[[PL]], Release, 2) -// CHECK: aie.use_lock(%[[CL]], AcquireGreaterEqual, 2) -// CHECK: aie.use_lock(%[[PL]], Release, 2) -// CHECK: aie.use_lock(%[[CL]], AcquireGreaterEqual, 2) -// CHECK: aie.use_lock(%[[PL]], Release, 2) -// CHECK: } -// CHECK: aie.end -// CHECK: } + +// CHECK-LABEL: aie.device(xcve2302) { +// CHECK: memref.global "public" @fifo : memref +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: %[[C16:.*]] = arith.constant 16 : index +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[SRCBUF22:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "srcbuf22"} : memref +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[FIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_0"} : memref +// CHECK: %[[FIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_1"} : memref +// CHECK: %[[FIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_2"} : memref +// CHECK: %[[FIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "fifo_buff_3"} : memref +// CHECK: %[[FIFO_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 4 : i32, sym_name = "fifo_prod_lock"} +// CHECK: %[[FIFO_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "fifo_cons_lock"} +// CHECK: %[[DSTBUF22:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "dstbuf22"} : memref<16xi32> +// CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { +// CHECK: %[[C0_I32:.*]] = arith.constant 0 : i32 +// CHECK: %[[C1_I32:.*]] = arith.constant 1 : i32 +// CHECK: memref.store %[[C0_I32]], %[[SRCBUF22]][] : memref +// CHECK: %[[C4:.*]] = arith.constant 4 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C16]] step %[[C4]] { +// CHECK: %[[VAL_0:.*]] = memref.load %[[SRCBUF22]][] : memref +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[VAL_0]], %[[FIFO_BUFF_0]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: %[[VAL_1:.*]] = arith.addi %[[C1_I32]], %[[VAL_0]] : i32 +// CHECK: memref.store %[[VAL_1]], %[[SRCBUF22]][] : memref +// CHECK: %[[VAL_2:.*]] = memref.load %[[SRCBUF22]][] : memref +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[VAL_2]], %[[FIFO_BUFF_1]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: %[[VAL_3:.*]] = arith.addi %[[C1_I32]], %[[VAL_2]] : i32 +// CHECK: memref.store %[[VAL_3]], %[[SRCBUF22]][] : memref +// CHECK: %[[VAL_4:.*]] = memref.load %[[SRCBUF22]][] : memref +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[VAL_4]], %[[FIFO_BUFF_2]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: %[[VAL_5:.*]] = arith.addi %[[C1_I32]], %[[VAL_4]] : i32 +// CHECK: memref.store %[[VAL_5]], %[[SRCBUF22]][] : memref +// CHECK: %[[VAL_6:.*]] = memref.load %[[SRCBUF22]][] : memref +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[VAL_6]], %[[FIFO_BUFF_3]][] : memref +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], Release, 1) +// CHECK: %[[VAL_7:.*]] = arith.addi %[[C1_I32]], %[[VAL_6]] : i32 +// CHECK: memref.store %[[VAL_7]], %[[SRCBUF22]][] : memref +// CHECK: } +// CHECK: aie.end +// CHECK: } +// CHECK: %[[CORE_2_3:.*]] = aie.core(%[[TILE_2_3]]) { +// CHECK: %[[C8:.*]] = arith.constant 8 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C16]] step %[[C8]] { +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], AcquireGreaterEqual, 2) +// CHECK: %[[VAL_8:.*]] = memref.load %[[FIFO_BUFF_0]][] : memref +// CHECK: %[[VAL_9:.*]] = memref.load %[[FIFO_BUFF_1]][] : memref +// CHECK: func.call @store2(%[[VAL_8]], %[[VAL_9]], %[[ARG0]], %[[DSTBUF22]]) : (i32, i32, index, memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], Release, 2) +// CHECK: %[[C1_0:.*]] = arith.constant 1 : index +// CHECK: %[[VAL_10:.*]] = arith.muli %[[C2]], %[[C1_0]] : index +// CHECK: %[[VAL_11:.*]] = arith.addi %[[ARG0]], %[[VAL_10]] : index +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], AcquireGreaterEqual, 2) +// CHECK: %[[VAL_12:.*]] = memref.load %[[FIFO_BUFF_2]][] : memref +// CHECK: %[[VAL_13:.*]] = memref.load %[[FIFO_BUFF_3]][] : memref +// CHECK: func.call @store2(%[[VAL_12]], %[[VAL_13]], %[[VAL_11]], %[[DSTBUF22]]) : (i32, i32, index, memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], Release, 2) +// CHECK: %[[C2_1:.*]] = arith.constant 2 : index +// CHECK: %[[VAL_14:.*]] = arith.muli %[[C2]], %[[C2_1]] : index +// CHECK: %[[VAL_15:.*]] = arith.addi %[[ARG0]], %[[VAL_14]] : index +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], AcquireGreaterEqual, 2) +// CHECK: %[[VAL_16:.*]] = memref.load %[[FIFO_BUFF_0]][] : memref +// CHECK: %[[VAL_17:.*]] = memref.load %[[FIFO_BUFF_1]][] : memref +// CHECK: func.call @store2(%[[VAL_16]], %[[VAL_17]], %[[VAL_15]], %[[DSTBUF22]]) : (i32, i32, index, memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], Release, 2) +// CHECK: %[[C3:.*]] = arith.constant 3 : index +// CHECK: %[[VAL_18:.*]] = arith.muli %[[C2]], %[[C3]] : index +// CHECK: %[[VAL_19:.*]] = arith.addi %[[ARG0]], %[[VAL_18]] : index +// CHECK: aie.use_lock(%[[FIFO_CONS_LOCK]], AcquireGreaterEqual, 2) +// CHECK: %[[VAL_20:.*]] = memref.load %[[FIFO_BUFF_2]][] : memref +// CHECK: %[[VAL_21:.*]] = memref.load %[[FIFO_BUFF_3]][] : memref +// CHECK: func.call @store2(%[[VAL_20]], %[[VAL_21]], %[[VAL_19]], %[[DSTBUF22]]) : (i32, i32, index, memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[FIFO_PROD_LOCK]], Release, 2) +// CHECK: } +// CHECK: aie.end +// CHECK: } +// CHECK: func.func @store2(%[[ARG0:.*]]: i32, %[[ARG1:.*]]: i32, %[[ARG2:.*]]: index, %[[ARG3:.*]]: memref<16xi32>) { +// CHECK: %[[C0_0:.*]] = arith.constant 0 : index +// CHECK: %[[C1_1:.*]] = arith.constant 1 : index +// CHECK: %[[VAL_22:.*]] = arith.addi %[[C0_0]], %[[ARG2]] : index +// CHECK: %[[VAL_23:.*]] = arith.addi %[[C1_1]], %[[ARG2]] : index +// CHECK: memref.store %[[ARG0]], %[[ARG3]]{{\[}}%[[VAL_22]]] : memref<16xi32> +// CHECK: memref.store %[[ARG1]], %[[ARG3]]{{\[}}%[[VAL_23]]] : memref<16xi32> +// CHECK: return +// CHECK: } +// CHECK: } module @aie2_static_l1 { aie.device(xcve2302) { @@ -51,24 +102,19 @@ module @aie2_static_l1 { %i_c1 = arith.constant 1 : index %i_c2 = arith.constant 2 : index %i_c16 = arith.constant 16 : index - %tile22 = aie.tile(2, 2) // producer tile %srcbuf22 = aie.buffer(%tile22) { sym_name = "srcbuf22" } : memref - %tile23 = aie.tile(2, 3) // consumer tile %dstbuf23 = aie.buffer(%tile23) { sym_name = "dstbuf22" } : memref<16xi32> - // ObjectFifo that can hold 4 memrefs, populated by tile22 and // consumed by tile23 aie.objectfifo @fifo (%tile22, {%tile23}, 4 : i32) : !aie.objectfifo> - // Producer core %core22 = aie.core(%tile22) { // Initialize value to zero %c0 = arith.constant 0 : i32 %c1 = arith.constant 1 : i32 memref.store %c0, %srcbuf22[] : memref - // Count up, with each iteration pushing a new element on to the fifo scf.for %idx = %i_c0 to %i_c16 step %i_c1 { %val0 = memref.load %srcbuf22[] : memref @@ -81,10 +127,8 @@ module @aie2_static_l1 { %val1 = arith.addi %c1, %val0 : i32 memref.store %val1, %srcbuf22[] : memref } - aie.end } - // Consumer core %core23 = aie.core(%tile23) { scf.for %idx = %i_c0 to %i_c16 step %i_c2 { @@ -99,10 +143,8 @@ module @aie2_static_l1 { // Release consumed objects aie.objectfifo.release @fifo (Consume, 2) } - aie.end } - func.func @store2(%val0: i32, %val1: i32, %base : index, %buf : memref<16xi32>) -> () { %ic0 = arith.constant 0 : index %ic1 = arith.constant 1 : index diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/CMakeLists.txt b/compiler/plugins/target/AMD-AIE/aie/aie_passes/CMakeLists.txt index 3591c1041..9560a848f 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/CMakeLists.txt +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/CMakeLists.txt @@ -1,90 +1,10 @@ +file(GLOB _mlir_files *.mlir) + iree_lit_test_suite( NAME lit SRCS - AIE2_cyclostatic_dma.mlir - AIE2_cyclostatic_l1.mlir - AIE2_cyclostatic_l2.mlir - AIE2_delayed_release.mlir - AIE2_delayed_release_inside_funcs.mlir - AIE2_dynamic_locks.mlir - AIE2_static_l1.mlir - aiert_insts.mlir - aiex_standard_lowering.mlir - allocation_info_test.mlir - assign-lockIDs.mlir - base_test_AIE1.mlir - base_test_AIE2.mlir - basic.mlir - basic_alloc_simple.mlir - broadcast_error_test.mlir - broadcast_test.mlir - cyclostatic_AIE2_sharedMem.mlir - dma_to_npu.mlir - dma_to_npu_issue_token.mlir - link_test_AIE1.mlir - link_test_AIE2.mlir - link_test_DDR_to_L1.mlir - link_test_L1_to_DDR.mlir - link_test_broadcast.mlir - link_test_distribute.mlir - link_test_join.mlir - local_locks.mlir - locks1.mlir - loop_test.aie.mlir - loop_test_nested.mlir - lower_buffer.mlir - lower_buffer_and_lock.mlir - lower_dma.mlir - lower_event.mlir - lower_stream.mlir - matmul_test.mlir - memTile_test.mlir - nd_dma_base_AIE2.mlir - nd_dma_distribute_AIE2.mlir - nd_dma_distribute_AIE2_bad.mlir - nd_dma_distribute_broadcast_AIE2_bad.mlir - nd_dma_multiple_consumers_AIE2.mlir - nested_loop_test.mlir - non_adjacency_test_1.mlir - non_adjacency_test_2.mlir - non_adjacency_test_AIE2.mlir - npu_instgen.mlir - push_to_queue.mlir - register_external_buffers_test.mlir - roundtrip.mlir - same_core_producer_consumer_test.mlir - shimRow_mem_test.mlir - shim_AIE2_test.mlir - shim_broadcast_test.mlir - subview_test_1.mlir - subview_test_2.mlir - subview_test_3.mlir - tileDMA_test.mlir - unit_broadcast.mlir - unit_fixed_connections.mlir - unit_flow_test_1.mlir - unit_flow_test_2.mlir - unit_flow_test_3.mlir - unit_many_flows.mlir - unit_many_flows2.mlir - unit_maxiter_err_test.mlir - unit_memtile.mlir - unit_memtile_routing_constraints.mlir - unit_mmult.mlir - unit_more_flows_shim.mlir - unit_over_flows.mlir - unit_routed_herd_3x1.mlir - unit_routed_herd_3x2.mlir - unit_simple.mlir - unit_simple2.mlir - unit_simple_flows.mlir - unit_simple_flows2.mlir - unit_simple_flows_shim.mlir - unit_vecmul_4x4.mlir - useLock_in_func.mlir - user_assigned.mlir - via_DMA_test.mlir + ${_mlir_files} TOOLS ${IREE_LLD_TARGET} FileCheck diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/aie_roundtrip.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/aie_roundtrip.mlir new file mode 100644 index 000000000..d7b437894 --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/aie_roundtrip.mlir @@ -0,0 +1,31 @@ + +// RUN: iree-opt %s | FileCheck %s + +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: memref.global "public" @out0 : memref<16xi32> +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: aie.objectfifo @obj1(%[[TILE_0_0]], {%[[TILE_0_1]]}, 4 : i32) : !aie.objectfifo> +// CHECK: aie.objectfifo @obj2(%[[TILE_0_1]] toStream [, , ], {%[[TILE_0_2]], %[[TILE_0_3]]}, 4 : i32) : !aie.objectfifo> +// CHECK: aie.objectfifo @obj3(%[[TILE_0_1]] toStream [, , ], {%[[TILE_1_2]], %[[TILE_1_3]]}, 4 : i32) : !aie.objectfifo> +// CHECK: aie.objectfifo.link [@obj1] -> [@obj2, @obj3]() +// CHECK: } + +// aie.objectfifo.link with multiple consumers with toStream +aie.device(npu1_4col) { + memref.global "public" @out0 : memref<16xi32> + %tile_0_2 = aie.tile(0, 2) + %tile_0_3 = aie.tile(0, 3) + %tile_1_2 = aie.tile(1, 2) + %tile_1_3 = aie.tile(1, 3) + %tile_0_0 = aie.tile(0, 0) + %tile_0_1 = aie.tile(0, 1) + aie.objectfifo @obj1(%tile_0_0, {%tile_0_1}, 4 : i32) : !aie.objectfifo> + aie.objectfifo @obj2(%tile_0_1 toStream [, , ], {%tile_0_2, %tile_0_3}, 4 : i32) : !aie.objectfifo> + aie.objectfifo @obj3(%tile_0_1 toStream [, , ], {%tile_1_2, %tile_1_3}, 4 : i32) : !aie.objectfifo> + aie.objectfifo.link [@obj1] -> [@obj2, @obj3]() +} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/aiert_insts.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/aiert_insts.mlir index 5e2c7cb27..dcc666341 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/aiert_insts.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/aiert_insts.mlir @@ -7,9 +7,13 @@ //===----------------------------------------------------------------------===// // RUN: iree-opt --aie-dma-to-npu %s | FileCheck %s -// CHECK: aiex.npu.writebd {bd_id = 1 : i32, buffer_length = 32 : i32, buffer_offset = 0 : i32, column = 0 : i32, d0_size = 0 : i32, d0_stride = 0 : i32, d1_size = 0 : i32, d1_stride = 0 : i32, d2_stride = 0 : i32, ddr_id = 2 : i32, enable_packet = 0 : i32, iteration_current = 0 : i32, iteration_size = 0 : i32, iteration_stride = 0 : i32, lock_acq_enable = 0 : i32, lock_acq_id = 0 : i32, lock_acq_val = 0 : i32, lock_rel_id = 0 : i32, lock_rel_val = 0 : i32, next_bd = 0 : i32, out_of_order_id = 0 : i32, packet_id = 0 : i32, packet_type = 0 : i32, row = 0 : i32, use_next_bd = 0 : i32, valid_bd = 1 : i32} +// XFAIL: * +// waiting on catching up to https://github.com/Xilinx/mlir-aie/pull/1559 +// i.e. we're still outputting ddr_id here + +// CHECK: aiex.npu.writebd {bd_id = 1 : i32, buffer_length = 32 : i32, buffer_offset = 0 : i32, column = 0 : i32, d0_size = 0 : i32, d0_stride = 0 : i32, d1_size = 0 : i32, d1_stride = 0 : i32, d2_stride = 0 : i32, enable_packet = 0 : i32, iteration_current = 0 : i32, iteration_size = 0 : i32, iteration_stride = 0 : i32, lock_acq_enable = 0 : i32, lock_acq_id = 0 : i32, lock_acq_val = 0 : i32, lock_rel_id = 0 : i32, lock_rel_val = 0 : i32, next_bd = 0 : i32, out_of_order_id = 0 : i32, packet_id = 0 : i32, packet_type = 0 : i32, row = 0 : i32, use_next_bd = 0 : i32, valid_bd = 1 : i32} // CHECK: aiex.npu.write32 {address = 119300 : ui32, column = 0 : i32, row = 0 : i32, value = 2147483649 : ui32} -// CHECK: aiex.npu.writebd {bd_id = 0 : i32, buffer_length = 32 : i32, buffer_offset = 128 : i32, column = 0 : i32, d0_size = 8 : i32, d0_stride = 0 : i32, d1_size = 2 : i32, d1_stride = 7 : i32, d2_stride = 15 : i32, ddr_id = 0 : i32, enable_packet = 0 : i32, iteration_current = 0 : i32, iteration_size = 0 : i32, iteration_stride = 0 : i32, lock_acq_enable = 0 : i32, lock_acq_id = 0 : i32, lock_acq_val = 0 : i32, lock_rel_id = 0 : i32, lock_rel_val = 0 : i32, next_bd = 0 : i32, out_of_order_id = 0 : i32, packet_id = 0 : i32, packet_type = 0 : i32, row = 0 : i32, use_next_bd = 0 : i32, valid_bd = 1 : i32} +// CHECK: aiex.npu.writebd {bd_id = 0 : i32, buffer_length = 32 : i32, buffer_offset = 128 : i32, column = 0 : i32, d0_size = 8 : i32, d0_stride = 0 : i32, d1_size = 2 : i32, d1_stride = 7 : i32, d2_stride = 15 : i32, enable_packet = 0 : i32, iteration_current = 0 : i32, iteration_size = 0 : i32, iteration_stride = 0 : i32, lock_acq_enable = 0 : i32, lock_acq_id = 0 : i32, lock_acq_val = 0 : i32, lock_rel_id = 0 : i32, lock_rel_val = 0 : i32, next_bd = 0 : i32, out_of_order_id = 0 : i32, packet_id = 0 : i32, packet_type = 0 : i32, row = 0 : i32, use_next_bd = 0 : i32, valid_bd = 1 : i32} // CHECK: aiex.npu.write32 {address = 119316 : ui32, column = 0 : i32, row = 0 : i32, value = 0 : ui32} module { @@ -31,4 +35,4 @@ module { aie.shim_dma_allocation @of_fromMem (MM2S, 0, 0) aie.shim_dma_allocation @of_toMem (S2MM, 0, 0) } -} \ No newline at end of file +} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/aiex_standard_lowering.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/aiex_standard_lowering.mlir index 5965c0a73..edc031c40 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/aiex_standard_lowering.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/aiex_standard_lowering.mlir @@ -1,18 +1,14 @@ -//===- aiex_standard_lowering.mlir -----------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2024 Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// -// RUN: iree-opt --split-input-file --aiex-standard-lowering %s | FileCheck %s +// RUN: iree-opt --aiex-standard-lowering %s | FileCheck %s + +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: memref.global "public" @toMem : memref<16xi32> +// CHECK: func.func @dma_and_wait(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: memref<16xi32>) { +// CHECK: return +// CHECK: } +// CHECK: aie.shim_dma_allocation @toMem(MM2S, 1, 1) +// CHECK: } -// CHECK-LABEL: dma_and_wait -// CHECK-NOT: aiex.npu.dma_memcpy_nd -// CHECK-NOT: aiex.npu.dma_wait module { aie.device(npu1_4col) { memref.global "public" @toMem : memref<16xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/aiexx_roundtrip.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/aiexx_roundtrip.mlir new file mode 100644 index 000000000..d68daa60a --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/aiexx_roundtrip.mlir @@ -0,0 +1,42 @@ + +// RUN: iree-opt --split-input-file %s | FileCheck %s + +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: memref.global "public" @out0 : memref<16xi32> +// CHECK: func.func @npu_dma_wait() { +// CHECK: aiex.npu.dma_wait {symbol = @out0} +// CHECK: return +// CHECK: } +// CHECK: } + +aie.device(npu1_4col) { + memref.global "public" @out0 : memref<16xi32> + func.func @npu_dma_wait() { + aiex.npu.dma_wait {symbol = @out0} + return + } +} + +// ----- + +// CHECK-LABEL: func.func @npu_dma_wait_no_device() { +// CHECK: aiex.npu.dma_wait {symbol = @out0} +// CHECK: return +// CHECK: } + +func.func @npu_dma_wait_no_device() { + aiex.npu.dma_wait {symbol = @out0} + return +} + +// ----- + +// CHECK-LABEL: func.func @npu_addr_patch() { +// CHECK: aiex.npu.address_patch {addr = 123 : ui32, arg_idx = 3 : i32, arg_plus = 0 : i32} +// CHECK: return +// CHECK: } + +func.func @npu_addr_patch() { + aiex.npu.address_patch {addr = 123 : ui32, arg_idx = 3 : i32, arg_plus = 0 : i32} + return +} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/allocation_info_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/allocation_info_test.mlir index 37dd3d7b6..c7efee118 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/allocation_info_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/allocation_info_test.mlir @@ -1,29 +1,104 @@ -//===- allocation_info_test.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: May 20th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcve2302) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 3) -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_0]], DMA : 0) -// CHECK: aie.flow(%[[VAL_0]], DMA : 1, %[[VAL_2]], DMA : 0) -// CHECK: aie.flow(%[[VAL_2]], DMA : 0, %[[VAL_0]], DMA : 1) +// CHECK: memref.global "public" @of_out_1_cons : memref<64xi16> +// CHECK: memref.global "public" @of_out_1 : memref<64xi16> +// CHECK: memref.global "public" @of_in_1_cons : memref<64xi16> +// CHECK: memref.global "public" @of_in_1 : memref<64xi16> +// CHECK: memref.global "public" @of_out_0_cons : memref<64xi16> +// CHECK: memref.global "public" @of_out_0 : memref<64xi16> +// CHECK: memref.global "public" @of_in_0_cons : memref<64xi16> +// CHECK: memref.global "public" @of_in_0 : memref<64xi16> +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[OF_OUT_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 6) {init = 0 : i32, sym_name = "of_out_1_cons_prod_lock"} +// CHECK: %[[OF_OUT_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 7) {init = 0 : i32, sym_name = "of_out_1_cons_cons_lock"} +// CHECK: %[[OF_OUT_1_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_out_1_buff_0"} : memref<64xi16> +// CHECK: %[[OF_OUT_1_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_out_1_buff_1"} : memref<64xi16> +// CHECK: %[[OF_OUT_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 2) {init = 2 : i32, sym_name = "of_out_1_prod_lock"} +// CHECK: %[[OF_OUT_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 3) {init = 0 : i32, sym_name = "of_out_1_cons_lock"} +// CHECK: %[[OF_IN_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_0"} : memref<64xi16> +// CHECK: %[[OF_IN_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_1"} : memref<64xi16> +// CHECK: %[[OF_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i32, sym_name = "of_in_1_cons_prod_lock"} +// CHECK: %[[OF_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i32, sym_name = "of_in_1_cons_cons_lock"} +// CHECK: %[[OF_IN_1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 4) {init = 0 : i32, sym_name = "of_in_1_prod_lock"} +// CHECK: %[[OF_IN_1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 5) {init = 0 : i32, sym_name = "of_in_1_cons_lock"} +// CHECK: %[[OF_OUT_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 2) {init = 0 : i32, sym_name = "of_out_0_cons_prod_lock"} +// CHECK: %[[OF_OUT_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 3) {init = 0 : i32, sym_name = "of_out_0_cons_cons_lock"} +// CHECK: %[[OF_OUT_0_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_0_buff_0"} : memref<64xi16> +// CHECK: %[[OF_OUT_0_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_0_buff_1"} : memref<64xi16> +// CHECK: %[[OF_OUT_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i32, sym_name = "of_out_0_prod_lock"} +// CHECK: %[[OF_OUT_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i32, sym_name = "of_out_0_cons_lock"} +// CHECK: %[[OF_IN_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_0"} : memref<64xi16> +// CHECK: %[[OF_IN_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_1"} : memref<64xi16> +// CHECK: %[[OF_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of_in_0_cons_prod_lock"} +// CHECK: %[[OF_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of_in_0_cons_cons_lock"} +// CHECK: %[[OF_IN_0_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i32, sym_name = "of_in_0_prod_lock"} +// CHECK: %[[OF_IN_0_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "of_in_0_cons_lock"} +// CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_2]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_0]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_0]], DMA : 1, %[[TILE_2_3]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_3]], DMA : 0, %[[TILE_2_0]], DMA : 1) // CHECK: aie.shim_dma_allocation @of_in_0(MM2S, 0, 2) // CHECK: aie.shim_dma_allocation @of_out_0(S2MM, 0, 2) // CHECK: aie.shim_dma_allocation @of_in_1(MM2S, 1, 2) +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_IN_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_IN_0_CONS_BUFF_0]] : memref<64xi16>, 0, 64) +// CHECK: aie.use_lock(%[[OF_IN_0_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF_IN_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_IN_0_CONS_BUFF_1]] : memref<64xi16>, 0, 64) +// CHECK: aie.use_lock(%[[OF_IN_0_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: %[[VAL_1:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[OF_OUT_0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_OUT_0_BUFF_0]] : memref<64xi16>, 0, 64) +// CHECK: aie.use_lock(%[[OF_OUT_0_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb5 +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[OF_OUT_0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_OUT_0_BUFF_1]] : memref<64xi16>, 0, 64) +// CHECK: aie.use_lock(%[[OF_OUT_0_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb4 +// CHECK: ^bb6: +// CHECK: aie.end +// CHECK: } // CHECK: aie.shim_dma_allocation @of_out_1(S2MM, 1, 2) +// CHECK: %[[MEM_2_3:.*]] = aie.mem(%[[TILE_2_3]]) { +// CHECK: %[[VAL_2:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_IN_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_IN_1_CONS_BUFF_0]] : memref<64xi16>, 0, 64) +// CHECK: aie.use_lock(%[[OF_IN_1_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF_IN_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_IN_1_CONS_BUFF_1]] : memref<64xi16>, 0, 64) +// CHECK: aie.use_lock(%[[OF_IN_1_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: %[[VAL_3:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[OF_OUT_1_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_OUT_1_BUFF_0]] : memref<64xi16>, 0, 64) +// CHECK: aie.use_lock(%[[OF_OUT_1_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb5 +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[OF_OUT_1_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_OUT_1_BUFF_1]] : memref<64xi16>, 0, 64) +// CHECK: aie.use_lock(%[[OF_OUT_1_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb4 +// CHECK: ^bb6: +// CHECK: aie.end +// CHECK: } // CHECK: } module @alloc { @@ -31,10 +106,8 @@ module @alloc { %tile20 = aie.tile(2, 0) %tile22 = aie.tile(2, 2) %tile23 = aie.tile(2, 3) - aie.objectfifo @of_in_0 (%tile20, {%tile22}, 2 : i32) : !aie.objectfifo> aie.objectfifo @of_out_0 (%tile22, {%tile20}, 2 : i32) : !aie.objectfifo> - aie.objectfifo @of_in_1 (%tile20, {%tile23}, 2 : i32) : !aie.objectfifo> aie.objectfifo @of_out_1 (%tile23, {%tile20}, 2 : i32) : !aie.objectfifo> } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/assign-lockIDs.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/assign-lockIDs.mlir index 944ba3571..18da25850 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/assign-lockIDs.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/assign-lockIDs.mlir @@ -1,47 +1,41 @@ -//===- assign-lockIDs.mlir ---------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2022 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-assign-lock-ids --split-input-file %s | FileCheck %s -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_2:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_3:.*]] = aie.tile(3, 4) -// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_0]], 0) -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_0]], 2) -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_0]], 1) -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_1]], 0) -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_1]], 1) -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_1]], 4) -// CHECK: %[[VAL_10:.*]] = aie.lock(%[[VAL_1]], 2) -// CHECK: %[[VAL_11:.*]] = aie.lock(%[[VAL_1]], 3) -// CHECK: %[[VAL_12:.*]] = aie.lock(%[[VAL_1]], 5) -// CHECK: %[[VAL_13:.*]] = aie.lock(%[[VAL_1]], 6) -// CHECK: %[[VAL_14:.*]] = aie.lock(%[[VAL_1]], 7) -// CHECK: %[[VAL_15:.*]] = aie.lock(%[[VAL_1]], 10) -// CHECK: %[[VAL_16:.*]] = aie.lock(%[[VAL_1]], 11) -// CHECK: %[[VAL_17:.*]] = aie.lock(%[[VAL_1]], 8) -// CHECK: %[[VAL_18:.*]] = aie.lock(%[[VAL_1]], 9) -// CHECK: %[[VAL_19:.*]] = aie.lock(%[[VAL_1]], 12) -// CHECK: %[[VAL_20:.*]] = aie.lock(%[[VAL_1]], 13) -// CHECK: %[[VAL_21:.*]] = aie.lock(%[[VAL_1]], 14) -// CHECK: %[[VAL_22:.*]] = aie.lock(%[[VAL_1]], 15) -// CHECK: %[[VAL_23:.*]] = aie.lock(%[[VAL_2]], 0) -// CHECK: %[[VAL_24:.*]] = aie.lock(%[[VAL_2]], 1) -// CHECK: %[[VAL_25:.*]] = aie.lock(%[[VAL_2]], 9) -// CHECK: %[[VAL_26:.*]] = aie.lock(%[[VAL_2]], 2) -// CHECK: %[[VAL_27:.*]] = aie.lock(%[[VAL_3]], 0) -// CHECK: %[[VAL_28:.*]] = aie.lock(%[[VAL_3]], 1) -// CHECK: %[[VAL_29:.*]] = aie.lock(%[[VAL_3]], 2) -// CHECK: %[[VAL_30:.*]] = aie.lock(%[[VAL_3]], 3) -// CHECK: %[[VAL_31:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_32:.*]] = aie.lock(%[[VAL_31]], 0) + +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) +// CHECK: %[[LOCK_2_2:.*]] = aie.lock(%[[TILE_2_2]], 0) +// CHECK: %[[LOCK_2_2_0:.*]] = aie.lock(%[[TILE_2_2]], 2) +// CHECK: %[[LOCK_2_2_1:.*]] = aie.lock(%[[TILE_2_2]], 1) +// CHECK: %[[LOCK_2_3:.*]] = aie.lock(%[[TILE_2_3]], 0) +// CHECK: %[[LOCK_2_3_2:.*]] = aie.lock(%[[TILE_2_3]], 1) +// CHECK: %[[LOCK_2_3_3:.*]] = aie.lock(%[[TILE_2_3]], 4) +// CHECK: %[[LOCK_2_3_4:.*]] = aie.lock(%[[TILE_2_3]], 2) +// CHECK: %[[LOCK_2_3_5:.*]] = aie.lock(%[[TILE_2_3]], 3) +// CHECK: %[[LOCK_2_3_6:.*]] = aie.lock(%[[TILE_2_3]], 5) +// CHECK: %[[LOCK_2_3_7:.*]] = aie.lock(%[[TILE_2_3]], 6) +// CHECK: %[[LOCK_2_3_8:.*]] = aie.lock(%[[TILE_2_3]], 7) +// CHECK: %[[LOCK_2_3_9:.*]] = aie.lock(%[[TILE_2_3]], 10) +// CHECK: %[[LOCK_2_3_10:.*]] = aie.lock(%[[TILE_2_3]], 11) +// CHECK: %[[LOCK_2_3_11:.*]] = aie.lock(%[[TILE_2_3]], 8) +// CHECK: %[[LOCK_2_3_12:.*]] = aie.lock(%[[TILE_2_3]], 9) +// CHECK: %[[LOCK_2_3_13:.*]] = aie.lock(%[[TILE_2_3]], 12) +// CHECK: %[[LOCK_2_3_14:.*]] = aie.lock(%[[TILE_2_3]], 13) +// CHECK: %[[LOCK_2_3_15:.*]] = aie.lock(%[[TILE_2_3]], 14) +// CHECK: %[[LOCK_2_3_16:.*]] = aie.lock(%[[TILE_2_3]], 15) +// CHECK: %[[LOCK_3_3:.*]] = aie.lock(%[[TILE_3_3]], 0) +// CHECK: %[[LOCK_3_3_17:.*]] = aie.lock(%[[TILE_3_3]], 1) +// CHECK: %[[LOCK_3_3_18:.*]] = aie.lock(%[[TILE_3_3]], 9) +// CHECK: %[[LOCK_3_3_19:.*]] = aie.lock(%[[TILE_3_3]], 2) +// CHECK: %[[LOCK_3_4:.*]] = aie.lock(%[[TILE_3_4]], 0) +// CHECK: %[[LOCK_3_4_20:.*]] = aie.lock(%[[TILE_3_4]], 1) +// CHECK: %[[LOCK_3_4_21:.*]] = aie.lock(%[[TILE_3_4]], 2) +// CHECK: %[[LOCK_3_4_22:.*]] = aie.lock(%[[TILE_3_4]], 3) +// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) +// CHECK: %[[LOCK_6_0:.*]] = aie.lock(%[[TILE_6_0]], 0) +// CHECK: } module @test_assign_lockIDs { aie.device(xcvc1902) { @@ -49,11 +43,9 @@ module @test_assign_lockIDs { %t23 = aie.tile(2, 3) %t33 = aie.tile(3, 3) %t34 = aie.tile(3, 4) - %l22_0 = aie.lock(%t22, 0) %l22_2 = aie.lock(%t22, 2) %l22_1 = aie.lock(%t22) - %l23_0 = aie.lock(%t23) %l23_1 = aie.lock(%t23) %l23_4 = aie.lock(%t23, 4) @@ -70,17 +62,14 @@ module @test_assign_lockIDs { %l23_13 = aie.lock(%t23) %l23_14 = aie.lock(%t23) %l23_15 = aie.lock(%t23) - %l33_0 = aie.lock(%t33, 0) %l33_1 = aie.lock(%t33) %l33_9 = aie.lock(%t33, 9) %l33_2 = aie.lock(%t33) - %l34_0 = aie.lock(%t34) %l34_1 = aie.lock(%t34) %l34_2 = aie.lock(%t34) %l34_3 = aie.lock(%t34) - %t60 = aie.tile(6, 0) %l60 = aie.lock(%t60) } @@ -88,9 +77,32 @@ module @test_assign_lockIDs { // ----- +// CHECK-LABEL: aie.device(xcve2802) { +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[LOCK_1_1:.*]] = aie.lock(%[[TILE_1_1]], 1) +// CHECK: %[[LOCK_1_1_0:.*]] = aie.lock(%[[TILE_1_1]], 0) +// CHECK: %[[LOCK_1_1_1:.*]] = aie.lock(%[[TILE_1_1]], 3) +// CHECK: %[[LOCK_1_1_2:.*]] = aie.lock(%[[TILE_1_1]], 4) +// CHECK: %[[LOCK_1_1_3:.*]] = aie.lock(%[[TILE_1_1]], 5) +// CHECK: %[[LOCK_1_1_4:.*]] = aie.lock(%[[TILE_1_1]], 6) +// CHECK: %[[LOCK_1_1_5:.*]] = aie.lock(%[[TILE_1_1]], 7) +// CHECK: %[[LOCK_1_1_6:.*]] = aie.lock(%[[TILE_1_1]], 8) +// CHECK: %[[LOCK_1_1_7:.*]] = aie.lock(%[[TILE_1_1]], 9) +// CHECK: %[[LOCK_1_1_8:.*]] = aie.lock(%[[TILE_1_1]], 10) +// CHECK: %[[LOCK_1_1_9:.*]] = aie.lock(%[[TILE_1_1]], 11) +// CHECK: %[[LOCK_1_1_10:.*]] = aie.lock(%[[TILE_1_1]], 12) +// CHECK: %[[LOCK_1_1_11:.*]] = aie.lock(%[[TILE_1_1]], 13) +// CHECK: %[[LOCK_1_1_12:.*]] = aie.lock(%[[TILE_1_1]], 14) +// CHECK: %[[LOCK_1_1_13:.*]] = aie.lock(%[[TILE_1_1]], 33) +// CHECK: %[[LOCK_1_1_14:.*]] = aie.lock(%[[TILE_1_1]], 15) +// CHECK: %[[LOCK_1_1_15:.*]] = aie.lock(%[[TILE_1_1]], 16) +// CHECK: %[[LOCK_1_1_16:.*]] = aie.lock(%[[TILE_1_1]], 17) +// CHECK: %[[LOCK_1_1_17:.*]] = aie.lock(%[[TILE_1_1]], 18) +// CHECK: %[[LOCK_1_1_18:.*]] = aie.lock(%[[TILE_1_1]], 2) +// CHECK: } + module @memTileTest { aie.device(xcve2802) { - // Memory tiles on xcve have 64 locks. %tmemtile = aie.tile(1,1) %l0 = aie.lock(%tmemtile, 1) @@ -115,8 +127,3 @@ module @memTileTest { %l19 = aie.lock(%tmemtile,2) } } - - -// CHECK-LABEL: memTileTest -// CHECK-COUNT-20: aie.lock -// CHECK-NOT: aie.lock diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/base_test_AIE1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/base_test_AIE1.mlir index ea5dce768..365a17837 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/base_test_AIE1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/base_test_AIE1.mlir @@ -1,82 +1,69 @@ -//===- base_test_AIE1.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2022, Xilinx Inc. -// Copyright (C) 2022, Advanced Micro Devices, Inc. -// -// Date: July 26th 2022 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK: module @elementGenerationAIE1 { -// CHECK: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_2:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "of1_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "of1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_2]], 0) {init = 0 : i32, sym_name = "of1_cons_lock_0"} -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_2]], 1) {init = 0 : i32, sym_name = "of1_cons_lock_1"} -// CHECK: %[[VAL_7:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of1_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of1_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_0]], 4) {init = 0 : i32, sym_name = "of1_lock_0"} -// CHECK: %[[VAL_10:.*]] = aie.lock(%[[VAL_0]], 5) {init = 0 : i32, sym_name = "of1_lock_1"} -// CHECK: %[[VAL_11:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of0_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_12:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of0_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_13:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of0_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_14:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of0_buff_3"} : memref<16xi32> -// CHECK: %[[VAL_15:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "of0_lock_0"} -// CHECK: %[[VAL_16:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "of0_lock_1"} -// CHECK: %[[VAL_17:.*]] = aie.lock(%[[VAL_0]], 2) {init = 0 : i32, sym_name = "of0_lock_2"} -// CHECK: %[[VAL_18:.*]] = aie.lock(%[[VAL_0]], 3) {init = 0 : i32, sym_name = "of0_lock_3"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_2]], DMA : 0) -// CHECK: %[[VAL_19:.*]] = aie.mem(%[[VAL_0]]) { -// CHECK: aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 0) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_10]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 0) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.mem(%[[VAL_2]]) { -// CHECK: aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: } -// CHECK: } +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: memref.global "public" @of1_cons : memref<16xi32> +// CHECK: memref.global "public" @of1 : memref<16xi32> +// CHECK: memref.global "public" @of0 : memref<16xi32> +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OF1_CONS_LOCK_0:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 0 : i32, sym_name = "of1_cons_lock_0"} +// CHECK: %[[OF1_CONS_LOCK_1:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "of1_cons_lock_1"} +// CHECK: %[[OF1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_0"} : memref<16xi32> +// CHECK: %[[OF1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_1"} : memref<16xi32> +// CHECK: %[[OF1_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 4) {init = 0 : i32, sym_name = "of1_lock_0"} +// CHECK: %[[OF1_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 5) {init = 0 : i32, sym_name = "of1_lock_1"} +// CHECK: %[[OF0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_0"} : memref<16xi32> +// CHECK: %[[OF0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_1"} : memref<16xi32> +// CHECK: %[[OF0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_2"} : memref<16xi32> +// CHECK: %[[OF0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_3"} : memref<16xi32> +// CHECK: %[[OF0_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 0 : i32, sym_name = "of0_lock_0"} +// CHECK: %[[OF0_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of0_lock_1"} +// CHECK: %[[OF0_LOCK_2:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 0 : i32, sym_name = "of0_lock_2"} +// CHECK: %[[OF0_LOCK_3:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "of0_lock_3"} +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF1_LOCK_0]], Acquire, 1) +// CHECK: aie.dma_bd(%[[OF1_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_LOCK_0]], Release, 0) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF1_LOCK_1]], Acquire, 1) +// CHECK: aie.dma_bd(%[[OF1_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_LOCK_1]], Release, 0) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK_0]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK_1]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: aie.end +// CHECK: } +// CHECK: } module @elementGenerationAIE1 { aie.device(xcvc1902) { %tile12 = aie.tile(1, 2) %tile13 = aie.tile(1, 3) %tile33 = aie.tile(3, 3) - // In the shared memory case, the number of elements does not change. aie.objectfifo @of0 (%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> - // In the non-adjacent memory case, the number of elements depends on the max amount acquired by // the processes running on each core (here nothing is specified so it cannot be derived). aie.objectfifo @of1 (%tile12, {%tile33}, 2 : i32) : !aie.objectfifo> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/base_test_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/base_test_AIE2.mlir index 8e6f00016..27c147164 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/base_test_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/base_test_AIE2.mlir @@ -1,80 +1,67 @@ -//===- base_test_AIE2.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Xilinx Inc. -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: May 9th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK: module @elementGenerationAIE2 { -// CHECK: aie.device(xcve2302) { -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_2:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "of1_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "of1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_2]], 0) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_2]], 1) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} -// CHECK: %[[VAL_7:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of1_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of1_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_0]], 2) {init = 2 : i32, sym_name = "of1_prod_lock"} -// CHECK: %[[VAL_10:.*]] = aie.lock(%[[VAL_0]], 3) {init = 0 : i32, sym_name = "of1_cons_lock"} -// CHECK: %[[VAL_11:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of0_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_12:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of0_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_13:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of0_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_14:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of0_buff_3"} : memref<16xi32> -// CHECK: %[[VAL_15:.*]] = aie.lock(%[[VAL_0]], 0) {init = 4 : i32, sym_name = "of0_prod_lock"} -// CHECK: %[[VAL_16:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_2]], DMA : 0) -// CHECK: %[[VAL_17:.*]] = aie.mem(%[[VAL_0]]) { -// CHECK: aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: %[[VAL_18:.*]] = aie.mem(%[[VAL_2]]) { -// CHECK: aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_5]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_5]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: } -// CHECK: } +// CHECK-LABEL: aie.device(xcve2302) { +// CHECK: memref.global "public" @of1_cons : memref<16xi32> +// CHECK: memref.global "public" @of1 : memref<16xi32> +// CHECK: memref.global "public" @of0 : memref<16xi32> +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_0"} : memref<16xi32> +// CHECK: %[[OF1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_1"} : memref<16xi32> +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i32, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "of1_cons_lock"} +// CHECK: %[[OF0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_0"} : memref<16xi32> +// CHECK: %[[OF0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_1"} : memref<16xi32> +// CHECK: %[[OF0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_2"} : memref<16xi32> +// CHECK: %[[OF0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_3"} : memref<16xi32> +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: aie.end +// CHECK: } +// CHECK: } module @elementGenerationAIE2 { aie.device(xcve2302) { %tile12 = aie.tile(1, 2) %tile13 = aie.tile(1, 3) %tile33 = aie.tile(3, 3) - // In the shared memory case, the number of elements does not change. aie.objectfifo @of0 (%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> - // In the non-adjacent memory case, the number of elements depends on the max amount acquired by // the processes running on each core (here nothing is specified so it cannot be derived). aie.objectfifo @of1 (%tile12, {%tile33}, 2 : i32) : !aie.objectfifo> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic.mlir index 14806a8f9..ec29ec08a 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic.mlir @@ -1,33 +1,71 @@ -//===- basic.mlir ----------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2024 Advanced Micro Devices Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-assign-bd-ids --split-input-file %s | FileCheck %s // CHECK-LABEL: aie.device(npu1_4col) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "double_buffer"} : memref<32xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_1]]) : memref<32xi32> -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_2]]) {init = 1 : i32, sym_name = "lock_X"} -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_2]]) {init = 0 : i32, sym_name = "lock_Y"} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>, 0) {bd_id = 0 : i32, next_bd_id = 1 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 1 : i32, next_bd_id = 2 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 2 : i32, next_bd_id = 0 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>, 0) {bd_id = 3 : i32, next_bd_id = 4 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 4 : i32, next_bd_id = 5 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 5 : i32, next_bd_id = 3 : i32} -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 0 : i32} -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 1 : i32} -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 24 : i32} -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 25 : i32} +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[DOUBLE_BUFFER:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "double_buffer"} : memref<32xi32> +// CHECK: %[[BUFFER_0_1:.*]] = aie.buffer(%[[TILE_0_1]]) : memref<32xi32> +// CHECK: %[[LOCK_X:.*]] = aie.lock(%[[TILE_0_2]]) {init = 1 : i32, sym_name = "lock_X"} +// CHECK: %[[LOCK_Y:.*]] = aie.lock(%[[TILE_0_2]]) {init = 0 : i32, sym_name = "lock_Y"} +// CHECK: %[[MEM_0_2:.*]] = aie.mem(%[[TILE_0_2]]) { +// CHECK: %[[PLAYER_A:.*]] = aie.dma(S2MM, 0) {sym_name = "player_a"} [{ +// CHECK: aie.use_lock(%[[LOCK_Y]], Acquire, 0) +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>, 0) {bd_id = 0 : i32, next_bd_id = 1 : i32} +// CHECK: aie.use_lock(%[[LOCK_Y]], Release, 0) +// CHECK: }, { +// CHECK: aie.use_lock(%[[LOCK_X]], Acquire, 1) +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>) {bd_id = 1 : i32, next_bd_id = 2 : i32} +// CHECK: aie.use_lock(%[[LOCK_X]], Release, -1) +// CHECK: }, { +// CHECK: aie.use_lock(%[[LOCK_Y]], Acquire) {acq_en = false} +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>) {bd_id = 2 : i32, next_bd_id = 0 : i32} +// CHECK: aie.use_lock(%[[LOCK_Y]], Release, 1) +// CHECK: }] +// CHECK: %[[PLAYER_B:.*]] = aie.dma(S2MM, 1) {sym_name = "player_b"} [{ +// CHECK: aie.use_lock(%[[LOCK_Y]], Acquire, 1) +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>, 0) {bd_id = 3 : i32, next_bd_id = 4 : i32} +// CHECK: aie.use_lock(%[[LOCK_Y]], Release, 0) +// CHECK: }, { +// CHECK: aie.use_lock(%[[LOCK_X]], Acquire, 1) +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>) {bd_id = 4 : i32, next_bd_id = 5 : i32} +// CHECK: aie.use_lock(%[[LOCK_X]], Release, -1) +// CHECK: }, { +// CHECK: aie.use_lock(%[[LOCK_Y]], Acquire) {acq_en = false} +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>) {bd_id = 5 : i32, next_bd_id = 3 : i32} +// CHECK: aie.use_lock(%[[LOCK_Y]], Release, -1) +// CHECK: }] +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEMTILE_DMA_0_1:.*]] = aie.memtile_dma(%[[TILE_0_1]]) { +// CHECK: %[[LOCK_0_1:.*]] = aie.lock(%[[TILE_0_1]]) {init = 1 : i32} +// CHECK: %[[LOCK_0_1_0:.*]] = aie.lock(%[[TILE_0_1]]) {init = 0 : i32} +// CHECK: %[[VAL_0:.*]] = aie.dma(S2MM, 0) {loop = false, repeat_count = 10 : i32} [{ +// CHECK: aie.use_lock(%[[LOCK_0_1]], AcquireGreaterEqual) +// CHECK: aie.dma_bd(%[[BUFFER_0_1]] : memref<32xi32>) {bd_id = 0 : i32} +// CHECK: aie.use_lock(%[[LOCK_0_1_0]], Release) +// CHECK: }] +// CHECK: %[[VAL_1:.*]] = aie.dma(MM2S, 0) {loop = false, repeat_count = 10 : i32} [{ +// CHECK: aie.use_lock(%[[LOCK_0_1_0]], AcquireGreaterEqual) +// CHECK: aie.dma_bd(%[[BUFFER_0_1]] : memref<32xi32>) {bd_id = 1 : i32} +// CHECK: aie.use_lock(%[[LOCK_0_1]], Release) +// CHECK: }] +// CHECK: %[[LOCK_0_1_1:.*]] = aie.lock(%[[TILE_0_1]]) {init = 1 : i32} +// CHECK: %[[LOCK_0_1_2:.*]] = aie.lock(%[[TILE_0_1]]) {init = 0 : i32} +// CHECK: %[[VAL_2:.*]] = aie.dma(S2MM, 1) {loop = false, repeat_count = 10 : i32} [{ +// CHECK: aie.use_lock(%[[LOCK_0_1_1]], AcquireGreaterEqual) +// CHECK: aie.dma_bd(%[[BUFFER_0_1]] : memref<32xi32>) {bd_id = 24 : i32} +// CHECK: aie.use_lock(%[[LOCK_0_1_2]], Release) +// CHECK: }] +// CHECK: %[[VAL_3:.*]] = aie.dma(MM2S, 1) {loop = false, repeat_count = 10 : i32} [{ +// CHECK: aie.use_lock(%[[LOCK_0_1_2]], AcquireGreaterEqual) +// CHECK: aie.dma_bd(%[[BUFFER_0_1]] : memref<32xi32>) {bd_id = 25 : i32} +// CHECK: aie.use_lock(%[[LOCK_0_1_1]], Release) +// CHECK: }] +// CHECK: aie.end +// CHECK: } +// CHECK: } module { aie.device(npu1_4col) { @@ -100,26 +138,55 @@ module { // ----- // CHECK-LABEL: aie.device(xcve2302) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_1:.*]] = aie.buffer(%[[VAL_0]]) {address = 8192 : i32, sym_name = "in"} : memref<16xi32> -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_0]]) {address = 1824 : i32, sym_name = "out"} : memref<16xi32> -// CHECK: %[[VAL_8:.*]] = aie.memtile_dma(%[[VAL_0]]) { -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<16xi32>, 0, 128, [, , , ]) {bd_id = 0 : i32, next_bd_id = 0 : i32} -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<16xi32>, 0, 16) {bd_id = 24 : i32, next_bd_id = 24 : i32} -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) {bd_id = 25 : i32, next_bd_id = 25 : i32} -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) {bd_id = 1 : i32, next_bd_id = 1 : i32} +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[IN:.*]] = aie.buffer(%[[TILE_2_1]]) {address = 8192 : i32, sym_name = "in"} : memref<16xi32> +// CHECK: %[[OUT:.*]] = aie.buffer(%[[TILE_2_1]]) {address = 1824 : i32, sym_name = "out"} : memref<16xi32> +// CHECK: %[[LOCK_2_1:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 1 : i32} +// CHECK: %[[LOCK_2_1_0:.*]] = aie.lock(%[[TILE_2_1]], 1) +// CHECK: %[[LOCK_2_1_1:.*]] = aie.lock(%[[TILE_2_1]], 2) {init = 1 : i32} +// CHECK: %[[LOCK_2_1_2:.*]] = aie.lock(%[[TILE_2_1]], 3) +// CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb4, ^bb1) +// CHECK: ^bb1: +// CHECK: %[[VAL_1:.*]] = aie.dma_start(MM2S, 1, ^bb5, ^bb2) +// CHECK: ^bb2: +// CHECK: %[[VAL_2:.*]] = aie.dma_start(S2MM, 1, ^bb6, ^bb3) +// CHECK: ^bb3: +// CHECK: %[[VAL_3:.*]] = aie.dma_start(MM2S, 0, ^bb7, ^bb8) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[LOCK_2_1]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN]] : memref<16xi32>, 0, 128, [, , , ]) {bd_id = 0 : i32, next_bd_id = 0 : i32} +// CHECK: aie.use_lock(%[[LOCK_2_1_0]], Release, 1) +// CHECK: aie.next_bd ^bb4 +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[LOCK_2_1_0]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN]] : memref<16xi32>, 0, 16) {bd_id = 24 : i32, next_bd_id = 24 : i32} +// CHECK: aie.use_lock(%[[LOCK_2_1]], Release, 1) +// CHECK: aie.next_bd ^bb5 +// CHECK: ^bb6: +// CHECK: aie.use_lock(%[[LOCK_2_1_1]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OUT]] : memref<16xi32>, 0, 16) {bd_id = 25 : i32, next_bd_id = 25 : i32} +// CHECK: aie.use_lock(%[[LOCK_2_1_2]], Release, 1) +// CHECK: aie.next_bd ^bb6 +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[LOCK_2_1_2]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OUT]] : memref<16xi32>, 0, 16) {bd_id = 1 : i32, next_bd_id = 1 : i32} +// CHECK: aie.use_lock(%[[LOCK_2_1_1]], Release, 1) +// CHECK: aie.next_bd ^bb7 +// CHECK: ^bb8: +// CHECK: aie.end +// CHECK: } +// CHECK: } module @aie_module { aie.device(xcve2302) { %t01 = aie.tile(2, 1) %buf01_0 = aie.buffer(%t01) { address = 8192 : i32, sym_name = "in" } : memref<16xi32> %buf01_1 = aie.buffer(%t01) { address = 1824 : i32, sym_name = "out" } : memref<16xi32> - %l01_0 = aie.lock(%t01, 0) { init = 1 : i32 } %l01_1 = aie.lock(%t01, 1) %l01_2 = aie.lock(%t01, 2) { init = 1 : i32 } %l01_3 = aie.lock(%t01, 3) - %m01 = aie.memtile_dma(%t01) { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^dma0) ^dma0: @@ -153,5 +220,3 @@ module @aie_module { } } } - - diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_memtile_simple.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_memtile_simple.mlir new file mode 100644 index 000000000..6a94a8060 --- /dev/null +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_memtile_simple.mlir @@ -0,0 +1,20 @@ + +// RUN: iree-opt --aie-assign-buffer-addresses-basic %s | FileCheck %s + +// CHECK-LABEL: aie.device(xcve2302) { +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[A:.*]] = aie.buffer(%[[TILE_3_1]]) {address = 0 : i32, sym_name = "a"} : memref<65536xi32> +// CHECK: %[[MEMTILE_DMA_3_1:.*]] = aie.memtile_dma(%[[TILE_3_1]]) { +// CHECK: aie.end +// CHECK: } +// CHECK: } + +module @test { + aie.device(xcve2302) { + %0 = aie.tile(3, 1) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<65536xi32> + aie.memtile_dma(%0) { + aie.end + } + } +} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_simple.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_simple.mlir index b96b65be6..f700fae4b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_simple.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/basic_alloc_simple.mlir @@ -1,18 +1,20 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-assign-buffer-addresses-basic %s | FileCheck %s -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 3104 : i32, sym_name = "a"} : memref<16xi8> -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, sym_name = "b"} : memref<512xi32> -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 3072 : i32, sym_name = "c"} : memref<16xi16> -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, sym_name = "_anonymous0"} : memref<500xi32> + +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[A:.*]] = aie.buffer(%[[TILE_3_3]]) {address = 3104 : i32, sym_name = "a"} : memref<16xi8> +// CHECK: %[[B:.*]] = aie.buffer(%[[TILE_3_3]]) {address = 1024 : i32, sym_name = "b"} : memref<512xi32> +// CHECK: %[[C:.*]] = aie.buffer(%[[TILE_3_3]]) {address = 3072 : i32, sym_name = "c"} : memref<16xi16> +// CHECK: %[[TILE_4_4:.*]] = aie.tile(4, 4) +// CHECK: %[[VAL_0:.*]] = aie.buffer(%[[TILE_4_4]]) {address = 1024 : i32, sym_name = "_anonymous0"} : memref<500xi32> +// CHECK: %[[CORE_3_3:.*]] = aie.core(%[[TILE_3_3]]) { +// CHECK: aie.end +// CHECK: } +// CHECK: %[[CORE_4_4:.*]] = aie.core(%[[TILE_4_4]]) { +// CHECK: aie.end +// CHECK: } +// CHECK: } module @test { aie.device(xcvc1902) { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/broadcast_error_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/broadcast_error_test.mlir deleted file mode 100644 index 2b1639bbb..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/broadcast_error_test.mlir +++ /dev/null @@ -1,27 +0,0 @@ -//===- broadcast_error.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: June 6th 2023 -// -//===----------------------------------------------------------------------===// - -// RUN: not iree-opt --aie-objectFifo-stateful-transform %s 2>&1 | FileCheck %s - -// CHECK: error: 'aie.objectfifo' op does not have enough depths specified for producer and for each consumer. - -module @broadcast_error { - aie.device(xcvc1902) { - %tile12 = aie.tile(1, 2) - %tile13 = aie.tile(1, 3) - %tile14 = aie.tile(1, 4) - %tile32 = aie.tile(3, 2) - %tile33 = aie.tile(3, 3) - - aie.objectfifo @broadcast_of (%tile13, {%tile12, %tile14, %tile32, %tile33}, [2, 2, 3]) : !aie.objectfifo> - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/broadcast_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/broadcast_test.mlir index a3d604f65..33cf0de9d 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/broadcast_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/broadcast_test.mlir @@ -1,15 +1,3 @@ -//===- broadcast_test.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2022, Xilinx Inc. -// Copyright (C) 2022, Advanced Micro Devices, Inc. -// -// Date: September 5th 2022 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s @@ -19,249 +7,249 @@ // CHECK: memref.global "public" @broadcast_of_2_cons : memref<16xi32> // CHECK: memref.global "public" @broadcast_of_3_cons : memref<16xi32> // CHECK: memref.global "public" @broadcast_of : memref<16xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_2:.*]] = aie.tile(1, 4) -// CHECK: %[[VAL_3:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_4:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_5:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "broadcast_of_0_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_6:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "broadcast_of_0_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "broadcast_of_0_cons_lock_0"} -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "broadcast_of_0_cons_lock_1"} -// CHECK: %[[VAL_9:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "broadcast_of_1_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "broadcast_of_1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_11:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "broadcast_of_1_cons_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_12:.*]] = aie.lock(%[[VAL_2]], 0) {init = 0 : i32, sym_name = "broadcast_of_1_cons_lock_0"} -// CHECK: %[[VAL_13:.*]] = aie.lock(%[[VAL_2]], 1) {init = 0 : i32, sym_name = "broadcast_of_1_cons_lock_1"} -// CHECK: %[[VAL_14:.*]] = aie.lock(%[[VAL_2]], 2) {init = 0 : i32, sym_name = "broadcast_of_1_cons_lock_2"} -// CHECK: %[[VAL_15:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "broadcast_of_2_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_16:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "broadcast_of_2_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_17:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "broadcast_of_2_cons_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_18:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "broadcast_of_2_cons_buff_3"} : memref<16xi32> -// CHECK: %[[VAL_19:.*]] = aie.lock(%[[VAL_3]], 0) {init = 0 : i32, sym_name = "broadcast_of_2_cons_lock_0"} -// CHECK: %[[VAL_20:.*]] = aie.lock(%[[VAL_3]], 1) {init = 0 : i32, sym_name = "broadcast_of_2_cons_lock_1"} -// CHECK: %[[VAL_21:.*]] = aie.lock(%[[VAL_3]], 2) {init = 0 : i32, sym_name = "broadcast_of_2_cons_lock_2"} -// CHECK: %[[VAL_22:.*]] = aie.lock(%[[VAL_3]], 3) {init = 0 : i32, sym_name = "broadcast_of_2_cons_lock_3"} -// CHECK: %[[VAL_23:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "broadcast_of_3_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_24:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "broadcast_of_3_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_25:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "broadcast_of_3_cons_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_26:.*]] = aie.lock(%[[VAL_4]], 0) {init = 0 : i32, sym_name = "broadcast_of_3_cons_lock_0"} -// CHECK: %[[VAL_27:.*]] = aie.lock(%[[VAL_4]], 1) {init = 0 : i32, sym_name = "broadcast_of_3_cons_lock_1"} -// CHECK: %[[VAL_28:.*]] = aie.lock(%[[VAL_4]], 2) {init = 0 : i32, sym_name = "broadcast_of_3_cons_lock_2"} -// CHECK: %[[VAL_29:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "broadcast_of_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_30:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "broadcast_of_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_31:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32, sym_name = "broadcast_of_lock_0"} -// CHECK: %[[VAL_32:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "broadcast_of_lock_1"} -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_4]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_3]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_2]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_0]], DMA : 0) -// CHECK: func.func @some_work(%[[VAL_33:.*]]: memref<16xi32>) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_1_4:.*]] = aie.tile(1, 4) +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[BROADCAST_OF_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "broadcast_of_0_cons_buff_0"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "broadcast_of_0_cons_buff_1"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_0_CONS_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 0 : i32, sym_name = "broadcast_of_0_cons_lock_0"} +// CHECK: %[[BROADCAST_OF_0_CONS_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "broadcast_of_0_cons_lock_1"} +// CHECK: %[[BROADCAST_OF_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_4]]) {sym_name = "broadcast_of_1_cons_buff_0"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_4]]) {sym_name = "broadcast_of_1_cons_buff_1"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_1_4]]) {sym_name = "broadcast_of_1_cons_buff_2"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_1_CONS_LOCK_0:.*]] = aie.lock(%[[TILE_1_4]], 0) {init = 0 : i32, sym_name = "broadcast_of_1_cons_lock_0"} +// CHECK: %[[BROADCAST_OF_1_CONS_LOCK_1:.*]] = aie.lock(%[[TILE_1_4]], 1) {init = 0 : i32, sym_name = "broadcast_of_1_cons_lock_1"} +// CHECK: %[[BROADCAST_OF_1_CONS_LOCK_2:.*]] = aie.lock(%[[TILE_1_4]], 2) {init = 0 : i32, sym_name = "broadcast_of_1_cons_lock_2"} +// CHECK: %[[BROADCAST_OF_2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "broadcast_of_2_cons_buff_0"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "broadcast_of_2_cons_buff_1"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_2_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "broadcast_of_2_cons_buff_2"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_2_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_3_2]]) {sym_name = "broadcast_of_2_cons_buff_3"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_2_CONS_LOCK_0:.*]] = aie.lock(%[[TILE_3_2]], 0) {init = 0 : i32, sym_name = "broadcast_of_2_cons_lock_0"} +// CHECK: %[[BROADCAST_OF_2_CONS_LOCK_1:.*]] = aie.lock(%[[TILE_3_2]], 1) {init = 0 : i32, sym_name = "broadcast_of_2_cons_lock_1"} +// CHECK: %[[BROADCAST_OF_2_CONS_LOCK_2:.*]] = aie.lock(%[[TILE_3_2]], 2) {init = 0 : i32, sym_name = "broadcast_of_2_cons_lock_2"} +// CHECK: %[[BROADCAST_OF_2_CONS_LOCK_3:.*]] = aie.lock(%[[TILE_3_2]], 3) {init = 0 : i32, sym_name = "broadcast_of_2_cons_lock_3"} +// CHECK: %[[BROADCAST_OF_3_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "broadcast_of_3_cons_buff_0"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_3_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "broadcast_of_3_cons_buff_1"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_3_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "broadcast_of_3_cons_buff_2"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_3_CONS_LOCK_0:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 0 : i32, sym_name = "broadcast_of_3_cons_lock_0"} +// CHECK: %[[BROADCAST_OF_3_CONS_LOCK_1:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "broadcast_of_3_cons_lock_1"} +// CHECK: %[[BROADCAST_OF_3_CONS_LOCK_2:.*]] = aie.lock(%[[TILE_3_3]], 2) {init = 0 : i32, sym_name = "broadcast_of_3_cons_lock_2"} +// CHECK: %[[BROADCAST_OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "broadcast_of_buff_0"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "broadcast_of_buff_1"} : memref<16xi32> +// CHECK: %[[BROADCAST_OF_LOCK_0:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 0 : i32, sym_name = "broadcast_of_lock_0"} +// CHECK: %[[BROADCAST_OF_LOCK_1:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i32, sym_name = "broadcast_of_lock_1"} +// CHECK: aie.flow(%[[TILE_1_3]], DMA : 0, %[[TILE_3_3]], DMA : 0) +// CHECK: aie.flow(%[[TILE_1_3]], DMA : 0, %[[TILE_3_2]], DMA : 0) +// CHECK: aie.flow(%[[TILE_1_3]], DMA : 0, %[[TILE_1_4]], DMA : 0) +// CHECK: aie.flow(%[[TILE_1_3]], DMA : 0, %[[TILE_1_2]], DMA : 0) +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } -// CHECK: %[[VAL_34:.*]] = aie.core(%[[VAL_1]]) { -// CHECK: %[[VAL_35:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_36:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_37:.*]] = arith.constant 12 : index -// CHECK: %[[VAL_38:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[VAL_39:.*]] = %[[VAL_35]] to %[[VAL_37]] step %[[VAL_38]] { -// CHECK: aie.use_lock(%[[VAL_31]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_29]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_31]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_32]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_30]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_32]], Release, 1) +// CHECK: %[[CORE_1_3:.*]] = aie.core(%[[TILE_1_3]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C12]] step %[[C2]] { +// CHECK: aie.use_lock(%[[BROADCAST_OF_LOCK_0]], Acquire, 0) +// CHECK: func.call @some_work(%[[BROADCAST_OF_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_LOCK_0]], Release, 1) +// CHECK: aie.use_lock(%[[BROADCAST_OF_LOCK_1]], Acquire, 0) +// CHECK: func.call @some_work(%[[BROADCAST_OF_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_LOCK_1]], Release, 1) // CHECK: } // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_40:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: %[[VAL_41:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_42:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_43:.*]] = arith.constant 12 : index -// CHECK: %[[VAL_44:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[VAL_45:.*]] = %[[VAL_41]] to %[[VAL_43]] step %[[VAL_44]] { -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_5]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_7]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_8]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_6]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_8]], Release, 0) +// CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C12]] step %[[C2]] { +// CHECK: aie.use_lock(%[[BROADCAST_OF_0_CONS_LOCK_0]], Acquire, 1) +// CHECK: func.call @some_work(%[[BROADCAST_OF_0_CONS_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_0_CONS_LOCK_0]], Release, 0) +// CHECK: aie.use_lock(%[[BROADCAST_OF_0_CONS_LOCK_1]], Acquire, 1) +// CHECK: func.call @some_work(%[[BROADCAST_OF_0_CONS_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_0_CONS_LOCK_1]], Release, 0) // CHECK: } // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_46:.*]] = aie.core(%[[VAL_2]]) { -// CHECK: %[[VAL_47:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_48:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_49:.*]] = arith.constant 12 : index -// CHECK: %[[VAL_50:.*]] = arith.constant 3 : index -// CHECK: scf.for %[[VAL_51:.*]] = %[[VAL_47]] to %[[VAL_49]] step %[[VAL_50]] { -// CHECK: aie.use_lock(%[[VAL_12]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_13]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_9]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_10]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_12]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_13]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_14]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_12]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_11]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_9]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_14]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_12]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_13]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_14]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_10]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_11]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_13]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_14]], Release, 0) +// CHECK: %[[CORE_1_4:.*]] = aie.core(%[[TILE_1_4]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: %[[C3:.*]] = arith.constant 3 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C12]] step %[[C3]] { +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_0]], Acquire, 1) +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_1]], Acquire, 1) +// CHECK: func.call @some_work(%[[BROADCAST_OF_1_CONS_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_1_CONS_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_0]], Release, 0) +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_1]], Release, 0) +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_2]], Acquire, 1) +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_0]], Acquire, 1) +// CHECK: func.call @some_work(%[[BROADCAST_OF_1_CONS_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_1_CONS_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_2]], Release, 0) +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_0]], Release, 0) +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_1]], Acquire, 1) +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_2]], Acquire, 1) +// CHECK: func.call @some_work(%[[BROADCAST_OF_1_CONS_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_1_CONS_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_1]], Release, 0) +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_2]], Release, 0) // CHECK: } // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_52:.*]] = aie.core(%[[VAL_3]]) { -// CHECK: %[[VAL_53:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_54:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_55:.*]] = arith.constant 12 : index -// CHECK: %[[VAL_56:.*]] = arith.constant 4 : index -// CHECK: scf.for %[[VAL_57:.*]] = %[[VAL_53]] to %[[VAL_55]] step %[[VAL_56]] { -// CHECK: aie.use_lock(%[[VAL_19]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_20]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_21]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_15]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_16]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_17]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_19]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_22]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_16]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_17]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_18]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_20]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_19]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_17]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_18]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_15]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_21]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_20]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_18]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_15]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_16]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_22]], Release, 0) +// CHECK: %[[CORE_3_2:.*]] = aie.core(%[[TILE_3_2]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: %[[C4:.*]] = arith.constant 4 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C12]] step %[[C4]] { +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_0]], Acquire, 1) +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_1]], Acquire, 1) +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_2]], Acquire, 1) +// CHECK: func.call @some_work(%[[BROADCAST_OF_2_CONS_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_2_CONS_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_2_CONS_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_0]], Release, 0) +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_3]], Acquire, 1) +// CHECK: func.call @some_work(%[[BROADCAST_OF_2_CONS_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_2_CONS_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_2_CONS_BUFF_3]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_1]], Release, 0) +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_0]], Acquire, 1) +// CHECK: func.call @some_work(%[[BROADCAST_OF_2_CONS_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_2_CONS_BUFF_3]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_2_CONS_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_2]], Release, 0) +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_1]], Acquire, 1) +// CHECK: func.call @some_work(%[[BROADCAST_OF_2_CONS_BUFF_3]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_2_CONS_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_2_CONS_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_3]], Release, 0) // CHECK: } // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_58:.*]] = aie.core(%[[VAL_4]]) { -// CHECK: %[[VAL_59:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_60:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_61:.*]] = arith.constant 12 : index -// CHECK: %[[VAL_62:.*]] = arith.constant 3 : index -// CHECK: scf.for %[[VAL_63:.*]] = %[[VAL_59]] to %[[VAL_61]] step %[[VAL_62]] { -// CHECK: aie.use_lock(%[[VAL_26]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_27]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_23]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_24]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_26]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_28]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_24]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_25]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_27]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_26]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_25]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_23]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_28]], Release, 0) +// CHECK: %[[CORE_3_3:.*]] = aie.core(%[[TILE_3_3]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: %[[C3:.*]] = arith.constant 3 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C12]] step %[[C3]] { +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_0]], Acquire, 1) +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_1]], Acquire, 1) +// CHECK: func.call @some_work(%[[BROADCAST_OF_3_CONS_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_3_CONS_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_0]], Release, 0) +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_2]], Acquire, 1) +// CHECK: func.call @some_work(%[[BROADCAST_OF_3_CONS_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_3_CONS_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_1]], Release, 0) +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_0]], Acquire, 1) +// CHECK: func.call @some_work(%[[BROADCAST_OF_3_CONS_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[BROADCAST_OF_3_CONS_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_2]], Release, 0) // CHECK: } // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_64:.*]] = aie.mem(%[[VAL_1]]) { -// CHECK: %[[VAL_65:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_31]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_29]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_31]], Release, 0) +// CHECK: %[[MEM_1_3:.*]] = aie.mem(%[[TILE_1_3]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[BROADCAST_OF_LOCK_0]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_LOCK_0]], Release, 0) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_32]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_30]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_32]], Release, 0) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[BROADCAST_OF_LOCK_1]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_LOCK_1]], Release, 0) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_66:.*]] = aie.mem(%[[VAL_0]]) { -// CHECK: %[[VAL_67:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[BROADCAST_OF_0_CONS_LOCK_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_0_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_0_CONS_LOCK_0]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_8]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[BROADCAST_OF_0_CONS_LOCK_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_0_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_0_CONS_LOCK_1]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_68:.*]] = aie.mem(%[[VAL_2]]) { -// CHECK: %[[VAL_69:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 -// CHECK: aie.use_lock(%[[VAL_12]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_12]], Release, 1) +// CHECK: %[[MEM_1_4:.*]] = aie.mem(%[[TILE_1_4]]) { +// CHECK: %[[VAL_2:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_1_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_0]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_13]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_13]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_1_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_1]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[VAL_14]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_11]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_14]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_2]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_1_CONS_BUFF_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_1_CONS_LOCK_2]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb4: // pred: ^bb0 +// CHECK: ^bb4: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_70:.*]] = aie.mem(%[[VAL_3]]) { -// CHECK: %[[VAL_71:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 -// CHECK: aie.use_lock(%[[VAL_19]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_15]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_19]], Release, 1) +// CHECK: %[[MEM_3_2:.*]] = aie.mem(%[[TILE_3_2]]) { +// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_2_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_0]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_20]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_16]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_20]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_2_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_1]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[VAL_21]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_21]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_2]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_2_CONS_BUFF_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_2]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb4: // pred: ^bb3 -// CHECK: aie.use_lock(%[[VAL_22]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_22]], Release, 1) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_3]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_2_CONS_BUFF_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_2_CONS_LOCK_3]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb5: // pred: ^bb0 +// CHECK: ^bb5: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_72:.*]] = aie.mem(%[[VAL_4]]) { -// CHECK: %[[VAL_73:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 -// CHECK: aie.use_lock(%[[VAL_26]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_23]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_26]], Release, 1) +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_4:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_3_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_0]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_27]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_24]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_27]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_3_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_1]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[VAL_28]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_25]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_28]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_2]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BROADCAST_OF_3_CONS_BUFF_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[BROADCAST_OF_3_CONS_LOCK_2]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb4: // pred: ^bb0 +// CHECK: ^bb4: // CHECK: aie.end // CHECK: } // CHECK: } @@ -273,48 +261,38 @@ module @broadcast { %tile14 = aie.tile(1, 4) %tile32 = aie.tile(3, 2) %tile33 = aie.tile(3, 3) - aie.objectfifo @broadcast_of (%tile13, {%tile12, %tile14, %tile32, %tile33}, [2, 2, 3, 4, 3]) : !aie.objectfifo> - func.func @some_work(%lineOut : memref<16xi32>) -> () { return } - %core13 = aie.core(%tile13) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - scf.for %indexInHeight = %c0 to %height step %c1 { %subview = aie.objectfifo.acquire @broadcast_of (Produce, 1) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem0) : (memref<16xi32>) -> () aie.objectfifo.release @broadcast_of (Produce, 1) } - aie.end } - %core12 = aie.core(%tile12) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - scf.for %indexInHeight = %c0 to %height step %c1 { %subview = aie.objectfifo.acquire @broadcast_of (Consume, 1) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem0) : (memref<16xi32>) -> () aie.objectfifo.release @broadcast_of (Consume, 1) } - aie.end } - %core14 = aie.core(%tile14) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - scf.for %indexInHeight = %c0 to %height step %c1 { %subview = aie.objectfifo.acquire @broadcast_of (Consume, 2) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -323,15 +301,12 @@ module @broadcast { func.call @some_work(%elem1) : (memref<16xi32>) -> () aie.objectfifo.release @broadcast_of (Consume, 2) } - aie.end } - %core32 = aie.core(%tile32) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - scf.for %indexInHeight = %c0 to %height step %c1 { %subview = aie.objectfifo.acquire @broadcast_of (Consume, 3) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -342,15 +317,12 @@ module @broadcast { func.call @some_work(%elem2) : (memref<16xi32>) -> () aie.objectfifo.release @broadcast_of (Consume, 1) } - aie.end } - %core33 = aie.core(%tile33) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - scf.for %indexInHeight = %c0 to %height step %c1 { %subview = aie.objectfifo.acquire @broadcast_of (Consume, 2) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -359,7 +331,6 @@ module @broadcast { func.call @some_work(%elem1) : (memref<16xi32>) -> () aie.objectfifo.release @broadcast_of (Consume, 1) } - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/cyclostatic_AIE2_sharedMem.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/cyclostatic_AIE2_sharedMem.mlir index 4266bd495..11be73c1d 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/cyclostatic_AIE2_sharedMem.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/cyclostatic_AIE2_sharedMem.mlir @@ -1,91 +1,81 @@ -//===- cyclostatic_AIE2.mlir ------------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: July 10th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcve2302) { -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "fifo0_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "fifo0_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "fifo0_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "fifo0_buff_3"} : memref<16xi32> -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_0]], 0) {init = 4 : i32, sym_name = "fifo0_prod_lock"} -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "fifo0_cons_lock"} -// CHECK: %[[VAL_8:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: %[[VAL_9:.*]] = arith.constant 11 : i32 -// CHECK: %[[VAL_10:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_11:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_12:.*]] = arith.constant 9 : index -// CHECK: %[[VAL_13:.*]] = arith.constant 8 : index -// CHECK: %[[VAL_14:.*]] = arith.constant 4 : index -// CHECK: scf.for %[[VAL_15:.*]] = %[[VAL_10]] to %[[VAL_13]] step %[[VAL_14]] { -// CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: memref.store %[[VAL_9]], %[[VAL_2]]{{\[}}%[[VAL_10]]] : memref<16xi32> -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: memref.store %[[VAL_9]], %[[VAL_3]]{{\[}}%[[VAL_10]]] : memref<16xi32> -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: memref.store %[[VAL_9]], %[[VAL_4]]{{\[}}%[[VAL_10]]] : memref<16xi32> -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: memref.store %[[VAL_9]], %[[VAL_5]]{{\[}}%[[VAL_10]]] : memref<16xi32> -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: memref.global "public" @fifo0 : memref<16xi32> +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[FIFO0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "fifo0_buff_0"} : memref<16xi32> +// CHECK: %[[FIFO0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "fifo0_buff_1"} : memref<16xi32> +// CHECK: %[[FIFO0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "fifo0_buff_2"} : memref<16xi32> +// CHECK: %[[FIFO0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "fifo0_buff_3"} : memref<16xi32> +// CHECK: %[[FIFO0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "fifo0_prod_lock"} +// CHECK: %[[FIFO0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "fifo0_cons_lock"} +// CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { +// CHECK: %[[C11_I32:.*]] = arith.constant 11 : i32 +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C9:.*]] = arith.constant 9 : index +// CHECK: %[[C8:.*]] = arith.constant 8 : index +// CHECK: %[[C4:.*]] = arith.constant 4 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C8]] step %[[C4]] { +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C11_I32]], %[[FIFO0_BUFF_0]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C11_I32]], %[[FIFO0_BUFF_1]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C11_I32]], %[[FIFO0_BUFF_2]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C11_I32]], %[[FIFO0_BUFF_3]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], Release, 1) // CHECK: } -// CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: memref.store %[[VAL_9]], %[[VAL_2]]{{\[}}%[[VAL_10]]] : memref<16xi32> -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C11_I32]], %[[FIFO0_BUFF_0]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], Release, 1) // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_16:.*]] = aie.core(%[[VAL_1]]) { -// CHECK: %[[VAL_17:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_18:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_19:.*]] = arith.constant 9 : index -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: %[[VAL_20:.*]] = memref.load %[[VAL_2]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) -// CHECK: %[[VAL_21:.*]] = arith.constant 8 : index -// CHECK: %[[VAL_22:.*]] = arith.constant 4 : index -// CHECK: scf.for %[[VAL_23:.*]] = %[[VAL_17]] to %[[VAL_21]] step %[[VAL_22]] { -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 3) -// CHECK: %[[VAL_24:.*]] = memref.load %[[VAL_3]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: %[[VAL_25:.*]] = memref.load %[[VAL_4]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: %[[VAL_26:.*]] = memref.load %[[VAL_5]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: %[[VAL_27:.*]] = memref.load %[[VAL_4]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: %[[VAL_28:.*]] = memref.load %[[VAL_5]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: %[[VAL_29:.*]] = memref.load %[[VAL_2]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: %[[VAL_30:.*]] = memref.load %[[VAL_5]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: %[[VAL_31:.*]] = memref.load %[[VAL_2]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: %[[VAL_32:.*]] = memref.load %[[VAL_3]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: %[[VAL_33:.*]] = memref.load %[[VAL_2]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: %[[VAL_34:.*]] = memref.load %[[VAL_3]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: %[[VAL_35:.*]] = memref.load %[[VAL_4]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) +// CHECK: %[[CORE_2_2:.*]] = aie.core(%[[TILE_2_2]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C9:.*]] = arith.constant 9 : index +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[VAL_0:.*]] = memref.load %[[FIFO0_BUFF_0]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], Release, 1) +// CHECK: %[[C8:.*]] = arith.constant 8 : index +// CHECK: %[[C4:.*]] = arith.constant 4 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C8]] step %[[C4]] { +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], AcquireGreaterEqual, 3) +// CHECK: %[[VAL_1:.*]] = memref.load %[[FIFO0_BUFF_1]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: %[[VAL_2:.*]] = memref.load %[[FIFO0_BUFF_2]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: %[[VAL_3:.*]] = memref.load %[[FIFO0_BUFF_3]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[VAL_4:.*]] = memref.load %[[FIFO0_BUFF_2]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: %[[VAL_5:.*]] = memref.load %[[FIFO0_BUFF_3]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: %[[VAL_6:.*]] = memref.load %[[FIFO0_BUFF_0]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[VAL_7:.*]] = memref.load %[[FIFO0_BUFF_3]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: %[[VAL_8:.*]] = memref.load %[[FIFO0_BUFF_0]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: %[[VAL_9:.*]] = memref.load %[[FIFO0_BUFF_1]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[VAL_10:.*]] = memref.load %[[FIFO0_BUFF_0]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: %[[VAL_11:.*]] = memref.load %[[FIFO0_BUFF_1]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: %[[VAL_12:.*]] = memref.load %[[FIFO0_BUFF_2]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], Release, 1) // CHECK: } -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: %[[VAL_36:.*]] = memref.load %[[VAL_3]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: %[[VAL_37:.*]] = memref.load %[[VAL_4]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: %[[VAL_38:.*]] = memref.load %[[VAL_5]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) -// CHECK: %[[VAL_39:.*]] = memref.load %[[VAL_4]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: %[[VAL_40:.*]] = memref.load %[[VAL_5]]{{\[}}%[[VAL_17]]] : memref<16xi32> -// CHECK: aie.use_lock(%[[VAL_6]], Release, 2) +// CHECK: aie.use_lock(%[[FIFO0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[VAL_13:.*]] = memref.load %[[FIFO0_BUFF_1]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: %[[VAL_14:.*]] = memref.load %[[FIFO0_BUFF_2]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: %[[VAL_15:.*]] = memref.load %[[FIFO0_BUFF_3]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], Release, 1) +// CHECK: %[[VAL_16:.*]] = memref.load %[[FIFO0_BUFF_2]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: %[[VAL_17:.*]] = memref.load %[[FIFO0_BUFF_3]]{{\[}}%[[C0]]] : memref<16xi32> +// CHECK: aie.use_lock(%[[FIFO0_PROD_LOCK]], Release, 2) // CHECK: aie.end // CHECK: } // CHECK: } @@ -94,35 +84,28 @@ module @cyclostatic { aie.device(xcve2302) { %tile12 = aie.tile(1, 2) %tile23 = aie.tile(2, 2) - aie.objectfifo @fifo0 (%tile12, {%tile23}, 4 : i32) : !aie.objectfifo> - %core12 = aie.core(%tile12) { %v11 = arith.constant 11 : i32 %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %c9 = arith.constant 9 : index - scf.for %indexInHeight = %c0 to %c9 step %c1 { %subview1 = aie.objectfifo.acquire @fifo0 (Produce, 1) : !aie.objectfifosubview> %subview1_obj = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref<16xi32> memref.store %v11, %subview1_obj[%c0] : memref<16xi32> aie.objectfifo.release @fifo0 (Produce, 1) } - aie.end } - %core23 = aie.core(%tile23) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %c9 = arith.constant 9 : index - %subview0 = aie.objectfifo.acquire @fifo0 (Consume, 1) : !aie.objectfifosubview> %subview0_obj = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref<16xi32> %v0 = memref.load %subview0_obj[%c0] : memref<16xi32> aie.objectfifo.release @fifo0 (Consume, 1) - scf.for %indexInHeight = %c0 to %c9 step %c1 { %subview1 = aie.objectfifo.acquire @fifo0 (Consume, 3) : !aie.objectfifosubview> %subview1_obj = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -133,14 +116,12 @@ module @cyclostatic { %v3 = memref.load %subview1_obj2[%c0] : memref<16xi32> aie.objectfifo.release @fifo0 (Consume, 1) } - %subview2 = aie.objectfifo.acquire @fifo0 (Consume, 2) : !aie.objectfifosubview> %subview2_obj = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref<16xi32> %subview2_obj1 = aie.objectfifo.subview.access %subview2[1] : !aie.objectfifosubview> -> memref<16xi32> %v4 = memref.load %subview2_obj[%c0] : memref<16xi32> %v5 = memref.load %subview2_obj1[%c0] : memref<16xi32> aie.objectfifo.release @fifo0 (Consume, 2) - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/dma_to_npu.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/dma_to_npu.mlir index 66f52e807..8c07e0afc 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/dma_to_npu.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/dma_to_npu.mlir @@ -1,22 +1,25 @@ -//===- dma_to_npu.mlir -----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2023 Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// -// RUN: iree-opt --split-input-file -aie-dma-to-npu %s | FileCheck %s +// RUN: iree-opt --split-input-file --aie-dma-to-npu %s | FileCheck %s +// XFAIL: * +// waiting on catching up to https://github.com/Xilinx/mlir-aie/pull/1559 +// i.e. we're still outputting ddr_id here + +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: memref.global "public" @toMem : memref<16xi32> +// CHECK: memref.global "public" @fromMem : memref<16xi32> +// CHECK: func.func @dma_memcpy_nd_0(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: memref<16xi32>) { +// CHECK: aiex.npu.writebd {bd_id = 1 : i32, buffer_length = 256 : i32, buffer_offset = 0 : i32, column = 0 : i32, d0_size = 16 : i32, d0_stride = 0 : i32, d1_size = 0 : i32, d1_stride = 63 : i32, d2_stride = 0 : i32, enable_packet = 0 : i32, iteration_current = 0 : i32, iteration_size = 0 : i32, iteration_stride = 0 : i32, lock_acq_enable = 0 : i32, lock_acq_id = 0 : i32, lock_acq_val = 0 : i32, lock_rel_id = 0 : i32, lock_rel_val = 0 : i32, next_bd = 0 : i32, out_of_order_id = 0 : i32, packet_id = 0 : i32, packet_type = 0 : i32, row = 0 : i32, use_next_bd = 0 : i32, valid_bd = 1 : i32} +// CHECK: aiex.npu.address_patch {addr = 118820 : ui32, arg_idx = 0 : i32, arg_plus = 0 : i32} +// CHECK: aiex.npu.write32 {address = 119300 : ui32, column = 0 : i32, row = 0 : i32, value = 2147483649 : ui32} +// CHECK: aiex.npu.writebd {bd_id = 0 : i32, buffer_length = 256 : i32, buffer_offset = 64 : i32, column = 0 : i32, d0_size = 16 : i32, d0_stride = 0 : i32, d1_size = 0 : i32, d1_stride = 63 : i32, d2_stride = 0 : i32, enable_packet = 0 : i32, iteration_current = 0 : i32, iteration_size = 0 : i32, iteration_stride = 0 : i32, lock_acq_enable = 0 : i32, lock_acq_id = 0 : i32, lock_acq_val = 0 : i32, lock_rel_id = 0 : i32, lock_rel_val = 0 : i32, next_bd = 0 : i32, out_of_order_id = 0 : i32, packet_id = 0 : i32, packet_type = 0 : i32, row = 0 : i32, use_next_bd = 0 : i32, valid_bd = 1 : i32} +// CHECK: aiex.npu.address_patch {addr = 118788 : ui32, arg_idx = 1 : i32, arg_plus = 64 : i32} +// CHECK: aiex.npu.write32 {address = 119316 : ui32, column = 0 : i32, row = 0 : i32, value = 0 : ui32} +// CHECK: return +// CHECK: } +// CHECK: aie.shim_dma_allocation @fromMem(MM2S, 0, 0) +// CHECK: aie.shim_dma_allocation @toMem(S2MM, 0, 0) +// CHECK: } -// TODO - more -// CHECK-LABEL: dma_memcpy_nd_0 -// CHECK: aiex.npu.writebd -// CHECK-SAME: ddr_id = 0 : i32 -// CHECK-SAME: valid_bd = 1 : i32 -// CHECK: aiex.npu.writebd -// CHECK-SAME: ddr_id = 1 : i32 module { aie.device(npu1_4col) { memref.global "public" @toMem : memref<16xi32> @@ -33,18 +36,18 @@ module { // ----- -// CHECK-LABEL: dma_wait_s2mm -// CHECK: aiex.npu.writebd -// CHECK-SAME: ddr_id = 0 : i32 -// CHECK-SAME: valid_bd = 1 : i32 -// CHECK: aiex.npu.write32 -// CHECK: aiex.npu.sync -// CHECK-SAME: channel = 0 : i32 -// CHECK-SAME: column = 0 : i32 -// CHECK-SAME: column_num = 1 : i32 -// CHECK-SAME: direction = 0 : i32 -// CHECK-SAME: row = 0 : i32 -// CHECK-SAME: row_num = 1 : i32 +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: memref.global "public" @toMem : memref<16xi32> +// CHECK: func.func @dma_wait_s2mm(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: memref<16xi32>) { +// CHECK: aiex.npu.writebd {bd_id = 1 : i32, buffer_length = 256 : i32, buffer_offset = 0 : i32, column = 0 : i32, d0_size = 16 : i32, d0_stride = 0 : i32, d1_size = 0 : i32, d1_stride = 63 : i32, d2_stride = 0 : i32, enable_packet = 0 : i32, iteration_current = 0 : i32, iteration_size = 0 : i32, iteration_stride = 0 : i32, lock_acq_enable = 0 : i32, lock_acq_id = 0 : i32, lock_acq_val = 0 : i32, lock_rel_id = 0 : i32, lock_rel_val = 0 : i32, next_bd = 0 : i32, out_of_order_id = 0 : i32, packet_id = 0 : i32, packet_type = 0 : i32, row = 0 : i32, use_next_bd = 0 : i32, valid_bd = 1 : i32} +// CHECK: aiex.npu.address_patch {addr = 118820 : ui32, arg_idx = 0 : i32, arg_plus = 0 : i32} +// CHECK: aiex.npu.write32 {address = 119300 : ui32, column = 0 : i32, row = 0 : i32, value = 2147483649 : ui32} +// CHECK: aiex.npu.sync {channel = 0 : i32, column = 0 : i32, column_num = 1 : i32, direction = 0 : i32, row = 0 : i32, row_num = 1 : i32} +// CHECK: return +// CHECK: } +// CHECK: aie.shim_dma_allocation @toMem(S2MM, 0, 0) +// CHECK: } + module { aie.device(npu1_4col) { memref.global "public" @toMem : memref<16xi32> @@ -59,18 +62,18 @@ module { // ----- -// CHECK-LABEL: dma_wait_mm2s -// CHECK: aiex.npu.writebd -// CHECK-SAME: ddr_id = 0 : i32 -// CHECK-SAME: valid_bd = 1 : i32 -// CHECK: aiex.npu.write32 -// CHECK: aiex.npu.sync -// CHECK-SAME: channel = 1 : i32 -// CHECK-SAME: column = 1 : i32 -// CHECK-SAME: column_num = 1 : i32 -// CHECK-SAME: direction = 1 : i32 -// CHECK-SAME: row = 0 : i32 -// CHECK-SAME: row_num = 1 : i32 +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: memref.global "public" @toMem : memref<16xi32> +// CHECK: func.func @dma_wait_mm2s(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: memref<16xi32>) { +// CHECK: aiex.npu.writebd {bd_id = 1 : i32, buffer_length = 256 : i32, buffer_offset = 0 : i32, column = 1 : i32, d0_size = 16 : i32, d0_stride = 0 : i32, d1_size = 0 : i32, d1_stride = 63 : i32, d2_stride = 0 : i32, enable_packet = 0 : i32, iteration_current = 0 : i32, iteration_size = 0 : i32, iteration_stride = 0 : i32, lock_acq_enable = 0 : i32, lock_acq_id = 0 : i32, lock_acq_val = 0 : i32, lock_rel_id = 0 : i32, lock_rel_val = 0 : i32, next_bd = 0 : i32, out_of_order_id = 0 : i32, packet_id = 0 : i32, packet_type = 0 : i32, row = 0 : i32, use_next_bd = 0 : i32, valid_bd = 1 : i32} +// CHECK: aiex.npu.address_patch {addr = 33673252 : ui32, arg_idx = 0 : i32, arg_plus = 0 : i32} +// CHECK: aiex.npu.write32 {address = 119324 : ui32, column = 1 : i32, row = 0 : i32, value = 1 : ui32} +// CHECK: aiex.npu.sync {channel = 1 : i32, column = 1 : i32, column_num = 1 : i32, direction = 1 : i32, row = 0 : i32, row_num = 1 : i32} +// CHECK: return +// CHECK: } +// CHECK: aie.shim_dma_allocation @toMem(MM2S, 1, 1) +// CHECK: } + module { aie.device(npu1_4col) { memref.global "public" @toMem : memref<16xi32> @@ -82,4 +85,3 @@ module { aie.shim_dma_allocation @toMem (MM2S, 1, 1) } } - diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/dma_to_npu_issue_token.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/dma_to_npu_issue_token.mlir index cf99de3d1..2b6484289 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/dma_to_npu_issue_token.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/dma_to_npu_issue_token.mlir @@ -1,26 +1,25 @@ -//===- dma_to_npu_issue_token.mlir -----------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2024 Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// -// RUN: iree-opt -aie-dma-to-npu %s | FileCheck %s +// RUN: iree-opt --aie-dma-to-npu %s | FileCheck %s +// XFAIL: * +// waiting on catching up to https://github.com/Xilinx/mlir-aie/pull/1559 +// i.e. we're still outputting ddr_id here + +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: memref.global "public" @toMem : memref<16xi32> +// CHECK: memref.global "public" @fromMem : memref<16xi32> +// CHECK: func.func @test1(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: memref<16xi32>) { +// CHECK: aiex.npu.writebd {bd_id = 1 : i32, buffer_length = 256 : i32, buffer_offset = 0 : i32, column = 0 : i32, d0_size = 16 : i32, d0_stride = 0 : i32, d1_size = 0 : i32, d1_stride = 63 : i32, d2_stride = 0 : i32, enable_packet = 0 : i32, iteration_current = 0 : i32, iteration_size = 0 : i32, iteration_stride = 0 : i32, lock_acq_enable = 0 : i32, lock_acq_id = 0 : i32, lock_acq_val = 0 : i32, lock_rel_id = 0 : i32, lock_rel_val = 0 : i32, next_bd = 0 : i32, out_of_order_id = 0 : i32, packet_id = 0 : i32, packet_type = 0 : i32, row = 0 : i32, use_next_bd = 0 : i32, valid_bd = 1 : i32} +// CHECK: aiex.npu.address_patch {addr = 118820 : ui32, arg_idx = 0 : i32, arg_plus = 0 : i32} +// CHECK: aiex.npu.write32 {address = 119300 : ui32, column = 0 : i32, row = 0 : i32, value = 2147483649 : ui32} +// CHECK: aiex.npu.writebd {bd_id = 0 : i32, buffer_length = 256 : i32, buffer_offset = 64 : i32, column = 0 : i32, d0_size = 16 : i32, d0_stride = 0 : i32, d1_size = 0 : i32, d1_stride = 63 : i32, d2_stride = 0 : i32, enable_packet = 0 : i32, iteration_current = 0 : i32, iteration_size = 0 : i32, iteration_stride = 0 : i32, lock_acq_enable = 0 : i32, lock_acq_id = 0 : i32, lock_acq_val = 0 : i32, lock_rel_id = 0 : i32, lock_rel_val = 0 : i32, next_bd = 0 : i32, out_of_order_id = 0 : i32, packet_id = 0 : i32, packet_type = 0 : i32, row = 0 : i32, use_next_bd = 0 : i32, valid_bd = 1 : i32} +// CHECK: aiex.npu.address_patch {addr = 118788 : ui32, arg_idx = 1 : i32, arg_plus = 64 : i32} +// CHECK: aiex.npu.write32 {address = 119316 : ui32, column = 0 : i32, row = 0 : i32, value = 0 : ui32} +// CHECK: return +// CHECK: } +// CHECK: aie.shim_dma_allocation @fromMem(MM2S, 0, 0) +// CHECK: aie.shim_dma_allocation @toMem(S2MM, 0, 0) +// CHECK: } -// TODO - more -// CHECK-LABEL: test1 -// CHECK: aiex.npu.writebd -// CHECK-SAME: ddr_id = 0 : i32 -// CHECK-SAME: valid_bd = 1 : i32 -// CHECK: aiex.npu.write32 -// CHECK-SAME: value = 2147483649 -// CHECK: aiex.npu.writebd -// CHECK-SAME: ddr_id = 1 : i32 -// CHECK: aiex.npu.write32 -// CHECK-SAME: value = 0 module { aie.device(npu1_4col) { memref.global "public" @toMem : memref<16xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_AIE1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_AIE1.mlir index 5c7e0122d..b13d09df3 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_AIE1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_AIE1.mlir @@ -1,14 +1,3 @@ -//===- link_test_AIE1.mlir --------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: May 9th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s @@ -17,72 +6,72 @@ // CHECK: memref.global "public" @of2 : memref<16xi32> // CHECK: memref.global "public" @of1_cons : memref<16xi32> // CHECK: memref.global "public" @of1 : memref<16xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "of2_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "of2_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_2]], 0) {init = 0 : i32, sym_name = "of2_cons_lock_0"} -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_2]], 1) {init = 0 : i32, sym_name = "of2_cons_lock_1"} -// CHECK: %[[VAL_7:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "of1_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "of1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32, sym_name = "of1_cons_lock_0"} -// CHECK: %[[VAL_10:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "of1_cons_lock_1"} -// CHECK: %[[VAL_11:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "of1_lock_0"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_2]], DMA : 0) -// CHECK: %[[VAL_12:.*]] = aie.external_buffer {sym_name = "ext_buff_in"} : memref<16xi32> +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[OF2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of2_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OF2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of2_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OF2_CONS_LOCK_0:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 0 : i32, sym_name = "of2_cons_lock_0"} +// CHECK: %[[OF2_CONS_LOCK_1:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of2_cons_lock_1"} +// CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OF1_CONS_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 0 : i32, sym_name = "of1_cons_lock_0"} +// CHECK: %[[OF1_CONS_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of1_cons_lock_1"} +// CHECK: %[[OF1_LOCK_0:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i32, sym_name = "of1_lock_0"} +// CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_1_2]], DMA : 0) +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_2_2]], DMA : 0) +// CHECK: %[[EXT_BUFF_IN:.*]] = aie.external_buffer {sym_name = "ext_buff_in"} : memref<16xi32> // CHECK: aie.shim_dma_allocation @of1(MM2S, 0, 2) -// CHECK: %[[VAL_13:.*]] = aie.shim_dma(%[[VAL_0]]) { -// CHECK: %[[VAL_14:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 -// CHECK: aie.use_lock(%[[VAL_11]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_12]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 0) +// CHECK: %[[SHIM_DMA_2_0:.*]] = aie.shim_dma(%[[TILE_2_0]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF1_LOCK_0]], Acquire, 1) +// CHECK: aie.dma_bd(%[[EXT_BUFF_IN]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_LOCK_0]], Release, 0) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: // pred: ^bb0 +// CHECK: ^bb2: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_15:.*]] = aie.mem(%[[VAL_1]]) { -// CHECK: %[[VAL_16:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK_0]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_10]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK_1]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: %[[VAL_17:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) -// CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 0) +// CHECK: ^bb3: +// CHECK: %[[VAL_2:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK_0]], Acquire, 1) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK_0]], Release, 0) // CHECK: aie.next_bd ^bb5 -// CHECK: ^bb5: // pred: ^bb4 -// CHECK: aie.use_lock(%[[VAL_10]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 0) +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK_1]], Acquire, 1) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK_1]], Release, 0) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb6: // pred: ^bb3 +// CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_18:.*]] = aie.mem(%[[VAL_2]]) { -// CHECK: %[[VAL_19:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF2_CONS_LOCK_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OF2_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF2_CONS_LOCK_0]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF2_CONS_LOCK_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OF2_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF2_CONS_LOCK_1]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } // CHECK: } @@ -92,12 +81,9 @@ module @link_AIE1 { %tile20 = aie.tile(2, 0) %tile12 = aie.tile(1, 2) %tile22 = aie.tile(2, 2) - aie.objectfifo @of1 (%tile20, {%tile12}, 2 : i32) : !aie.objectfifo> aie.objectfifo @of2 (%tile12, {%tile22}, 2 : i32) : !aie.objectfifo> - aie.objectfifo.link [@of1] -> [@of2] () - %ext_buff_in = aie.external_buffer {sym_name = "ext_buff_in"} : memref<16xi32> aie.objectfifo.register_external_buffers @of1 (%tile20, {%ext_buff_in}) : (memref<16xi32>) } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_AIE2.mlir index 509c3663f..b161ac334 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_AIE2.mlir @@ -1,14 +1,3 @@ -//===- link_test_AIE2.mlir --------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: July 31st 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s @@ -18,164 +7,164 @@ // CHECK: memref.global "public" @mem_in_0_cons : memref<3000xi32> // CHECK: memref.global "public" @mem_in_1_cons : memref<3000xi32> // CHECK: memref.global "public" @mem_in : memref<3000xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_3:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "mem_out_cons_buff_0"} : memref<3000xi32> -// CHECK: %[[VAL_5:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "mem_out_cons_buff_1"} : memref<3000xi32> -// CHECK: %[[VAL_6:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "mem_out_cons_buff_2"} : memref<3000xi32> -// CHECK: %[[VAL_7:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "mem_out_cons_buff_3"} : memref<3000xi32> -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_3]], 0) {init = 4 : i32, sym_name = "mem_out_cons_prod_lock"} -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_3]], 1) {init = 0 : i32, sym_name = "mem_out_cons_cons_lock"} -// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "mem_in_0_cons_buff_0"} : memref<3000xi32> -// CHECK: %[[VAL_11:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "mem_in_0_cons_buff_1"} : memref<3000xi32> -// CHECK: %[[VAL_12:.*]] = aie.lock(%[[VAL_2]], 0) {init = 2 : i32, sym_name = "mem_in_0_cons_prod_lock"} -// CHECK: %[[VAL_13:.*]] = aie.lock(%[[VAL_2]], 1) {init = 0 : i32, sym_name = "mem_in_0_cons_cons_lock"} -// CHECK: %[[VAL_14:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "mem_in_1_cons_buff_0"} : memref<3000xi32> -// CHECK: %[[VAL_15:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "mem_in_1_cons_buff_1"} : memref<3000xi32> -// CHECK: %[[VAL_16:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "mem_in_1_cons_buff_2"} : memref<3000xi32> -// CHECK: %[[VAL_17:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "mem_in_1_cons_buff_3"} : memref<3000xi32> -// CHECK: %[[VAL_18:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "mem_in_1_cons_buff_4"} : memref<3000xi32> -// CHECK: %[[VAL_19:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "mem_in_1_cons_buff_5"} : memref<3000xi32> -// CHECK: %[[VAL_20:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "mem_in_1_cons_buff_6"} : memref<3000xi32> -// CHECK: %[[VAL_21:.*]] = aie.lock(%[[VAL_1]], 0) {init = 7 : i32, sym_name = "mem_in_1_cons_prod_lock"} -// CHECK: %[[VAL_22:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "mem_in_1_cons_cons_lock"} -// CHECK: %[[VAL_23:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "mem_in_prod_lock"} -// CHECK: %[[VAL_24:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "mem_in_cons_lock"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_2]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_3]], DMA : 0) -// CHECK: %[[VAL_25:.*]] = aie.core(%[[VAL_2]]) { -// CHECK: %[[VAL_26:.*]] = arith.constant 11 : i32 -// CHECK: %[[VAL_27:.*]] = arith.constant 0 : index -// CHECK: aie.use_lock(%[[VAL_13]], AcquireGreaterEqual, 1) -// CHECK: memref.store %[[VAL_26]], %[[VAL_10]]{{\[}}%[[VAL_27]]] : memref<3000xi32> +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[MEM_OUT_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_3]]) {sym_name = "mem_out_cons_buff_0"} : memref<3000xi32> +// CHECK: %[[MEM_OUT_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_3]]) {sym_name = "mem_out_cons_buff_1"} : memref<3000xi32> +// CHECK: %[[MEM_OUT_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_0_3]]) {sym_name = "mem_out_cons_buff_2"} : memref<3000xi32> +// CHECK: %[[MEM_OUT_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_0_3]]) {sym_name = "mem_out_cons_buff_3"} : memref<3000xi32> +// CHECK: %[[MEM_OUT_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_3]], 0) {init = 4 : i32, sym_name = "mem_out_cons_prod_lock"} +// CHECK: %[[MEM_OUT_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_3]], 1) {init = 0 : i32, sym_name = "mem_out_cons_cons_lock"} +// CHECK: %[[MEM_IN_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "mem_in_0_cons_buff_0"} : memref<3000xi32> +// CHECK: %[[MEM_IN_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "mem_in_0_cons_buff_1"} : memref<3000xi32> +// CHECK: %[[MEM_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 0) {init = 2 : i32, sym_name = "mem_in_0_cons_prod_lock"} +// CHECK: %[[MEM_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 1) {init = 0 : i32, sym_name = "mem_in_0_cons_cons_lock"} +// CHECK: %[[MEM_IN_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_0"} : memref<3000xi32> +// CHECK: %[[MEM_IN_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_1"} : memref<3000xi32> +// CHECK: %[[MEM_IN_1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_2"} : memref<3000xi32> +// CHECK: %[[MEM_IN_1_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_3"} : memref<3000xi32> +// CHECK: %[[MEM_IN_1_CONS_BUFF_4:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_4"} : memref<3000xi32> +// CHECK: %[[MEM_IN_1_CONS_BUFF_5:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_5"} : memref<3000xi32> +// CHECK: %[[MEM_IN_1_CONS_BUFF_6:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "mem_in_1_cons_buff_6"} : memref<3000xi32> +// CHECK: %[[MEM_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 0) {init = 7 : i32, sym_name = "mem_in_1_cons_prod_lock"} +// CHECK: %[[MEM_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 1) {init = 0 : i32, sym_name = "mem_in_1_cons_cons_lock"} +// CHECK: %[[MEM_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 0) {init = 0 : i32, sym_name = "mem_in_prod_lock"} +// CHECK: %[[MEM_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 1) {init = 0 : i32, sym_name = "mem_in_cons_lock"} +// CHECK: aie.flow(%[[TILE_0_0]], DMA : 0, %[[TILE_0_1]], DMA : 0) +// CHECK: aie.flow(%[[TILE_0_0]], DMA : 0, %[[TILE_0_2]], DMA : 0) +// CHECK: aie.flow(%[[TILE_0_1]], DMA : 0, %[[TILE_0_3]], DMA : 0) +// CHECK: %[[CORE_0_2:.*]] = aie.core(%[[TILE_0_2]]) { +// CHECK: %[[C11_I32:.*]] = arith.constant 11 : i32 +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: aie.use_lock(%[[MEM_IN_0_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: memref.store %[[C11_I32]], %[[MEM_IN_0_CONS_BUFF_0]]{{\[}}%[[C0]]] : memref<3000xi32> // CHECK: aie.end // CHECK: } // CHECK: aie.shim_dma_allocation @mem_in(MM2S, 0, 0) -// CHECK: %[[VAL_28:.*]] = aie.core(%[[VAL_3]]) { -// CHECK: %[[VAL_29:.*]] = arith.constant 11 : i32 -// CHECK: %[[VAL_30:.*]] = arith.constant 0 : index -// CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 3) -// CHECK: memref.store %[[VAL_29]], %[[VAL_4]]{{\[}}%[[VAL_30]]] : memref<3000xi32> +// CHECK: %[[CORE_0_3:.*]] = aie.core(%[[TILE_0_3]]) { +// CHECK: %[[C11_I32:.*]] = arith.constant 11 : i32 +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: aie.use_lock(%[[MEM_OUT_CONS_CONS_LOCK]], AcquireGreaterEqual, 3) +// CHECK: memref.store %[[C11_I32]], %[[MEM_OUT_CONS_BUFF_0]]{{\[}}%[[C0]]] : memref<3000xi32> // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.mem(%[[VAL_2]]) { -// CHECK: %[[VAL_32:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_12]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_13]], Release, 1) +// CHECK: %[[MEM_0_2:.*]] = aie.mem(%[[TILE_0_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[MEM_IN_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_0_CONS_BUFF_0]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_12]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_11]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_13]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[MEM_IN_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_0_CONS_BUFF_1]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.memtile_dma(%[[VAL_1]]) { -// CHECK: %[[VAL_34:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb8) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb7 -// CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_14]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_22]], Release, 1) +// CHECK: %[[MEMTILE_DMA_0_1:.*]] = aie.memtile_dma(%[[TILE_0_1]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb8) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_0]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_15]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_22]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_1]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_16]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_22]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_2]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb4: // pred: ^bb3 -// CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_22]], Release, 1) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_3]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb5 -// CHECK: ^bb5: // pred: ^bb4 -// CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_22]], Release, 1) +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_4]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb6 -// CHECK: ^bb6: // pred: ^bb5 -// CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_19]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_22]], Release, 1) +// CHECK: ^bb6: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_5]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb7 -// CHECK: ^bb7: // pred: ^bb6 -// CHECK: aie.use_lock(%[[VAL_21]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_20]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_22]], Release, 1) +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_6]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb8: // pred: ^bb0 -// CHECK: %[[VAL_35:.*]] = aie.dma_start(MM2S, 0, ^bb9, ^bb16) -// CHECK: ^bb9: // 2 preds: ^bb8, ^bb15 -// CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_14]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_21]], Release, 1) +// CHECK: ^bb8: +// CHECK: %[[VAL_2:.*]] = aie.dma_start(MM2S, 0, ^bb9, ^bb16) +// CHECK: ^bb9: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_0]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb10 -// CHECK: ^bb10: // pred: ^bb9 -// CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_15]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_21]], Release, 1) +// CHECK: ^bb10: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_1]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb11 -// CHECK: ^bb11: // pred: ^bb10 -// CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_16]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_21]], Release, 1) +// CHECK: ^bb11: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_2]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb12 -// CHECK: ^bb12: // pred: ^bb11 -// CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_21]], Release, 1) +// CHECK: ^bb12: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_3]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb13 -// CHECK: ^bb13: // pred: ^bb12 -// CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_21]], Release, 1) +// CHECK: ^bb13: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_4]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb14 -// CHECK: ^bb14: // pred: ^bb13 -// CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_19]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_21]], Release, 1) +// CHECK: ^bb14: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_5]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb15 -// CHECK: ^bb15: // pred: ^bb14 -// CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_20]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_21]], Release, 1) +// CHECK: ^bb15: +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_IN_1_CONS_BUFF_6]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_IN_1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb9 -// CHECK: ^bb16: // pred: ^bb8 +// CHECK: ^bb16: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_36:.*]] = aie.mem(%[[VAL_3]]) { -// CHECK: %[[VAL_37:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 -// CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: %[[MEM_0_3:.*]] = aie.mem(%[[TILE_0_3]]) { +// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[MEM_OUT_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_OUT_CONS_BUFF_0]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_OUT_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[MEM_OUT_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_OUT_CONS_BUFF_1]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_OUT_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[MEM_OUT_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_OUT_CONS_BUFF_2]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_OUT_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb4: // pred: ^bb3 -// CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<3000xi32>, 0, 3000) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[MEM_OUT_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[MEM_OUT_CONS_BUFF_3]] : memref<3000xi32>, 0, 3000) +// CHECK: aie.use_lock(%[[MEM_OUT_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb5: // pred: ^bb0 +// CHECK: ^bb5: // CHECK: aie.end // CHECK: } // CHECK: } @@ -186,25 +175,20 @@ module @link_AIE2 { %tile01 = aie.tile(0, 1) %tile02 = aie.tile(0, 2) %tile03 = aie.tile(0, 3) - aie.objectfifo @mem_in (%tile00, {%tile02, %tile01}, [2,2,7]) : !aie.objectfifo> aie.objectfifo @mem_out (%tile01, {%tile03}, 7 : i32) : !aie.objectfifo> aie.objectfifo.link [@mem_in] -> [@mem_out] () - %core02 = aie.core(%tile02) { %v11 = arith.constant 11 : i32 %c0 = arith.constant 0 : index - %subview = aie.objectfifo.acquire @mem_in (Consume, 1) : !aie.objectfifosubview> %subview_obj = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<3000xi32> memref.store %v11, %subview_obj[%c0] : memref<3000xi32> aie.end } - %core03 = aie.core(%tile03) { %v11 = arith.constant 11 : i32 %c0 = arith.constant 0 : index - %subview = aie.objectfifo.acquire @mem_out (Consume, 3) : !aie.objectfifosubview> %subview_obj = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<3000xi32> memref.store %v11, %subview_obj[%c0] : memref<3000xi32> diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_DDR_to_L1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_DDR_to_L1.mlir index a8c141cd7..2c79e6644 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_DDR_to_L1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_DDR_to_L1.mlir @@ -1,14 +1,3 @@ -//===- link_test_DDR_to_L1.mlir ------------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: May 9th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s @@ -17,73 +6,73 @@ // CHECK: memref.global "public" @from_memTile : memref<16xi32> // CHECK: memref.global "public" @to_memTile_cons : memref<16xi32> // CHECK: memref.global "public" @to_memTile : memref<16xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "from_memTile_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "from_memTile_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_2]], 0) {init = 2 : i32, sym_name = "from_memTile_cons_prod_lock"} -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_2]], 1) {init = 0 : i32, sym_name = "from_memTile_cons_cons_lock"} -// CHECK: %[[VAL_7:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "to_memTile_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "to_memTile_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_1]], 0) {init = 2 : i32, sym_name = "to_memTile_cons_prod_lock"} -// CHECK: %[[VAL_10:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "to_memTile_cons_cons_lock"} -// CHECK: %[[VAL_11:.*]] = aie.lock(%[[VAL_0]], 0) {init = 1 : i32, sym_name = "to_memTile_prod_lock"} -// CHECK: %[[VAL_12:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "to_memTile_cons_lock"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_2]], DMA : 0) -// CHECK: %[[VAL_13:.*]] = aie.external_buffer {sym_name = "ext_buff_in"} : memref<16xi32> +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[FROM_MEMTILE_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "from_memTile_cons_buff_0"} : memref<16xi32> +// CHECK: %[[FROM_MEMTILE_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "from_memTile_cons_buff_1"} : memref<16xi32> +// CHECK: %[[FROM_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "from_memTile_cons_prod_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "from_memTile_cons_cons_lock"} +// CHECK: %[[TO_MEMTILE_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "to_memTile_cons_buff_0"} : memref<16xi32> +// CHECK: %[[TO_MEMTILE_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "to_memTile_cons_buff_1"} : memref<16xi32> +// CHECK: %[[TO_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i32, sym_name = "to_memTile_cons_prod_lock"} +// CHECK: %[[TO_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "to_memTile_cons_cons_lock"} +// CHECK: %[[TO_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 1 : i32, sym_name = "to_memTile_prod_lock"} +// CHECK: %[[TO_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "to_memTile_cons_lock"} +// CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_1]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) +// CHECK: %[[EXT_BUFF_IN:.*]] = aie.external_buffer {sym_name = "ext_buff_in"} : memref<16xi32> // CHECK: aie.shim_dma_allocation @to_memTile(MM2S, 0, 2) -// CHECK: %[[VAL_14:.*]] = aie.shim_dma(%[[VAL_0]]) { -// CHECK: %[[VAL_15:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 -// CHECK: aie.use_lock(%[[VAL_12]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_13]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: %[[SHIM_DMA_2_0:.*]] = aie.shim_dma(%[[TILE_2_0]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[TO_MEMTILE_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[EXT_BUFF_IN]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[TO_MEMTILE_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: // pred: ^bb0 +// CHECK: ^bb2: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_16:.*]] = aie.memtile_dma(%[[VAL_1]]) { -// CHECK: %[[VAL_17:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 1) +// CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[TO_MEMTILE_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[TO_MEMTILE_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[TO_MEMTILE_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[TO_MEMTILE_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[TO_MEMTILE_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[TO_MEMTILE_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: %[[VAL_18:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) -// CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: ^bb3: +// CHECK: %[[VAL_2:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[TO_MEMTILE_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[TO_MEMTILE_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[TO_MEMTILE_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb5 -// CHECK: ^bb5: // pred: ^bb4 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[TO_MEMTILE_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[TO_MEMTILE_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[TO_MEMTILE_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb6: // pred: ^bb3 +// CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_19:.*]] = aie.mem(%[[VAL_2]]) { -// CHECK: %[[VAL_20:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_5]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[FROM_MEMTILE_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FROM_MEMTILE_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[FROM_MEMTILE_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_5]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[FROM_MEMTILE_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FROM_MEMTILE_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[FROM_MEMTILE_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } // CHECK: } @@ -93,12 +82,9 @@ module @link_DDR_L1 { %tile20 = aie.tile(2, 0) %tile21 = aie.tile(2, 1) %tile22 = aie.tile(2, 2) - aie.objectfifo @to_memTile (%tile20, {%tile21}, 2 : i32) : !aie.objectfifo> aie.objectfifo @from_memTile (%tile21, {%tile22}, 2 : i32) : !aie.objectfifo> - aie.objectfifo.link [@to_memTile] -> [@from_memTile] () - %ext_buff_in = aie.external_buffer {sym_name = "ext_buff_in"}: memref<16xi32> aie.objectfifo.register_external_buffers @to_memTile (%tile20, {%ext_buff_in}) : (memref<16xi32>) } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_L1_to_DDR.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_L1_to_DDR.mlir index dae55ed53..47c7127f7 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_L1_to_DDR.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_L1_to_DDR.mlir @@ -1,14 +1,3 @@ -//===- link_test_L1_to_DDR.mlir ------------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: June 30th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s @@ -17,73 +6,73 @@ // CHECK: memref.global "public" @from_memTile : memref<48xi32> // CHECK: memref.global "public" @to_memTile_cons : memref<16xi32> // CHECK: memref.global "public" @to_memTile : memref<16xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_3:.*]] = aie.lock(%[[VAL_0]], 0) {init = 1 : i32, sym_name = "from_memTile_cons_prod_lock"} -// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "from_memTile_cons_cons_lock"} -// CHECK: %[[VAL_5:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "from_memTile_buff_0"} : memref<48xi32> -// CHECK: %[[VAL_6:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "from_memTile_buff_1"} : memref<48xi32> -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_1]], 0) {init = 2 : i32, sym_name = "from_memTile_prod_lock"} -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "from_memTile_cons_lock"} -// CHECK: %[[VAL_9:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "to_memTile_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "to_memTile_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_11:.*]] = aie.lock(%[[VAL_2]], 0) {init = 2 : i32, sym_name = "to_memTile_prod_lock"} -// CHECK: %[[VAL_12:.*]] = aie.lock(%[[VAL_2]], 1) {init = 0 : i32, sym_name = "to_memTile_cons_lock"} -// CHECK: aie.flow(%[[VAL_2]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_0]], DMA : 0) -// CHECK: %[[VAL_13:.*]] = aie.external_buffer {sym_name = "ext_buff_in"} : memref<48xi32> -// CHECK: %[[VAL_14:.*]] = aie.mem(%[[VAL_2]]) { -// CHECK: %[[VAL_15:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_12]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[FROM_MEMTILE_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 1 : i32, sym_name = "from_memTile_cons_prod_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "from_memTile_cons_cons_lock"} +// CHECK: %[[FROM_MEMTILE_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "from_memTile_buff_0"} : memref<48xi32> +// CHECK: %[[FROM_MEMTILE_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "from_memTile_buff_1"} : memref<48xi32> +// CHECK: %[[FROM_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i32, sym_name = "from_memTile_prod_lock"} +// CHECK: %[[FROM_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "from_memTile_cons_lock"} +// CHECK: %[[TO_MEMTILE_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "to_memTile_buff_0"} : memref<16xi32> +// CHECK: %[[TO_MEMTILE_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "to_memTile_buff_1"} : memref<16xi32> +// CHECK: %[[TO_MEMTILE_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "to_memTile_prod_lock"} +// CHECK: %[[TO_MEMTILE_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "to_memTile_cons_lock"} +// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_1]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_0]], DMA : 0) +// CHECK: %[[EXT_BUFF_IN:.*]] = aie.external_buffer {sym_name = "ext_buff_in"} : memref<48xi32> +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[TO_MEMTILE_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[TO_MEMTILE_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[TO_MEMTILE_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_12]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[TO_MEMTILE_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[TO_MEMTILE_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[TO_MEMTILE_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_16:.*]] = aie.memtile_dma(%[[VAL_1]]) { -// CHECK: %[[VAL_17:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<48xi32>, 0, 48) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 1) +// CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[FROM_MEMTILE_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FROM_MEMTILE_BUFF_0]] : memref<48xi32>, 0, 48) +// CHECK: aie.use_lock(%[[FROM_MEMTILE_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<48xi32>, 0, 48) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[FROM_MEMTILE_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FROM_MEMTILE_BUFF_1]] : memref<48xi32>, 0, 48) +// CHECK: aie.use_lock(%[[FROM_MEMTILE_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: %[[VAL_18:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) -// CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 -// CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<48xi32>, 0, 48) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: ^bb3: +// CHECK: %[[VAL_2:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[FROM_MEMTILE_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FROM_MEMTILE_BUFF_0]] : memref<48xi32>, 0, 48) +// CHECK: aie.use_lock(%[[FROM_MEMTILE_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb5 -// CHECK: ^bb5: // pred: ^bb4 -// CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<48xi32>, 0, 48) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[FROM_MEMTILE_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[FROM_MEMTILE_BUFF_1]] : memref<48xi32>, 0, 48) +// CHECK: aie.use_lock(%[[FROM_MEMTILE_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb6: // pred: ^bb3 +// CHECK: ^bb6: // CHECK: aie.end // CHECK: } // CHECK: aie.shim_dma_allocation @from_memTile(S2MM, 0, 2) -// CHECK: %[[VAL_19:.*]] = aie.shim_dma(%[[VAL_0]]) { -// CHECK: %[[VAL_20:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 -// CHECK: aie.use_lock(%[[VAL_3]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_13]] : memref<48xi32>, 0, 48) -// CHECK: aie.use_lock(%[[VAL_4]], Release, 1) +// CHECK: %[[SHIM_DMA_2_0:.*]] = aie.shim_dma(%[[TILE_2_0]]) { +// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[FROM_MEMTILE_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[EXT_BUFF_IN]] : memref<48xi32>, 0, 48) +// CHECK: aie.use_lock(%[[FROM_MEMTILE_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: // pred: ^bb0 +// CHECK: ^bb2: // CHECK: aie.end // CHECK: } // CHECK: } @@ -93,12 +82,9 @@ module @link_L1_DDR { %tile20 = aie.tile(2, 0) %tile21 = aie.tile(2, 1) %tile22 = aie.tile(2, 2) - aie.objectfifo @to_memTile (%tile22, {%tile21}, 2 : i32) : !aie.objectfifo> aie.objectfifo @from_memTile (%tile21, {%tile20}, 2 : i32) : !aie.objectfifo> - aie.objectfifo.link [@to_memTile] -> [@from_memTile] () - %ext_buff_in = aie.external_buffer {sym_name = "ext_buff_in"}: memref<48xi32> aie.objectfifo.register_external_buffers @from_memTile (%tile20, {%ext_buff_in}) : (memref<48xi32>) } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_broadcast.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_broadcast.mlir index 422058547..80b0fb5cd 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_broadcast.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_broadcast.mlir @@ -1,14 +1,3 @@ -//===- link_test_broadcast.mlir ------------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: June 28th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s @@ -20,122 +9,122 @@ // CHECK: memref.global "public" @link2 : memref<16xi32> // CHECK: memref.global "public" @link1_cons : memref<48xi32> // CHECK: memref.global "public" @link1 : memref<48xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_3:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "skip_connection_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "skip_connection_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_3]], 2) {init = 2 : i32, sym_name = "skip_connection_cons_prod_lock"} -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_3]], 3) {init = 0 : i32, sym_name = "skip_connection_cons_cons_lock"} -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "skip_connection_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_9:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "skip_connection_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_10:.*]] = aie.lock(%[[VAL_2]], 2) {init = 2 : i32, sym_name = "skip_connection_prod_lock"} -// CHECK: %[[VAL_11:.*]] = aie.lock(%[[VAL_2]], 3) {init = 0 : i32, sym_name = "skip_connection_cons_lock"} -// CHECK: %[[VAL_12:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "link2_0_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_13:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "link2_0_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_14:.*]] = aie.lock(%[[VAL_2]], 0) {init = 2 : i32, sym_name = "link2_0_cons_prod_lock"} -// CHECK: %[[VAL_15:.*]] = aie.lock(%[[VAL_2]], 1) {init = 0 : i32, sym_name = "link2_0_cons_cons_lock"} -// CHECK: %[[VAL_16:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "link2_1_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_17:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "link2_1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_18:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "link2_1_cons_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_19:.*]] = aie.lock(%[[VAL_3]], 0) {init = 3 : i32, sym_name = "link2_1_cons_prod_lock"} -// CHECK: %[[VAL_20:.*]] = aie.lock(%[[VAL_3]], 1) {init = 0 : i32, sym_name = "link2_1_cons_cons_lock"} -// CHECK: %[[VAL_21:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "link1_cons_buff_0"} : memref<48xi32> -// CHECK: %[[VAL_22:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "link1_cons_buff_1"} : memref<48xi32> -// CHECK: %[[VAL_23:.*]] = aie.lock(%[[VAL_1]], 0) {init = 2 : i32, sym_name = "link1_cons_prod_lock"} -// CHECK: %[[VAL_24:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "link1_cons_cons_lock"} -// CHECK: %[[VAL_25:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "link1_prod_lock"} -// CHECK: %[[VAL_26:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "link1_cons_lock"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_3]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_2]], DMA : 0) -// CHECK: aie.flow(%[[VAL_2]], DMA : 0, %[[VAL_3]], DMA : 1) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[SKIP_CONNECTION_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "skip_connection_cons_buff_0"} : memref<16xi32> +// CHECK: %[[SKIP_CONNECTION_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "skip_connection_cons_buff_1"} : memref<16xi32> +// CHECK: %[[SKIP_CONNECTION_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 2) {init = 2 : i32, sym_name = "skip_connection_cons_prod_lock"} +// CHECK: %[[SKIP_CONNECTION_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 3) {init = 0 : i32, sym_name = "skip_connection_cons_cons_lock"} +// CHECK: %[[SKIP_CONNECTION_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "skip_connection_buff_0"} : memref<16xi32> +// CHECK: %[[SKIP_CONNECTION_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "skip_connection_buff_1"} : memref<16xi32> +// CHECK: %[[SKIP_CONNECTION_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i32, sym_name = "skip_connection_prod_lock"} +// CHECK: %[[SKIP_CONNECTION_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i32, sym_name = "skip_connection_cons_lock"} +// CHECK: %[[LINK2_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_0_cons_buff_0"} : memref<16xi32> +// CHECK: %[[LINK2_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_0_cons_buff_1"} : memref<16xi32> +// CHECK: %[[LINK2_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "link2_0_cons_prod_lock"} +// CHECK: %[[LINK2_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "link2_0_cons_cons_lock"} +// CHECK: %[[LINK2_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link2_1_cons_buff_0"} : memref<16xi32> +// CHECK: %[[LINK2_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link2_1_cons_buff_1"} : memref<16xi32> +// CHECK: %[[LINK2_1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link2_1_cons_buff_2"} : memref<16xi32> +// CHECK: %[[LINK2_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 3 : i32, sym_name = "link2_1_cons_prod_lock"} +// CHECK: %[[LINK2_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "link2_1_cons_cons_lock"} +// CHECK: %[[LINK1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link1_cons_buff_0"} : memref<48xi32> +// CHECK: %[[LINK1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link1_cons_buff_1"} : memref<48xi32> +// CHECK: %[[LINK1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i32, sym_name = "link1_cons_prod_lock"} +// CHECK: %[[LINK1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "link1_cons_cons_lock"} +// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 0 : i32, sym_name = "link1_prod_lock"} +// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "link1_cons_lock"} +// CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_1]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_3_3]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_3_3]], DMA : 1) // CHECK: aie.shim_dma_allocation @link1(MM2S, 0, 2) -// CHECK: %[[VAL_27:.*]] = aie.memtile_dma(%[[VAL_1]]) { -// CHECK: %[[VAL_28:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_23]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_21]] : memref<48xi32>, 0, 48) -// CHECK: aie.use_lock(%[[VAL_24]], Release, 1) +// CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK1_CONS_BUFF_0]] : memref<48xi32>, 0, 48) +// CHECK: aie.use_lock(%[[LINK1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_23]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_22]] : memref<48xi32>, 0, 48) -// CHECK: aie.use_lock(%[[VAL_24]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LINK1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK1_CONS_BUFF_1]] : memref<48xi32>, 0, 48) +// CHECK: aie.use_lock(%[[LINK1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: %[[VAL_29:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) -// CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 -// CHECK: aie.use_lock(%[[VAL_24]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_21]] : memref<48xi32>, 0, 48) -// CHECK: aie.use_lock(%[[VAL_23]], Release, 1) +// CHECK: ^bb3: +// CHECK: %[[VAL_1:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[LINK1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK1_CONS_BUFF_0]] : memref<48xi32>, 0, 48) +// CHECK: aie.use_lock(%[[LINK1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb5 -// CHECK: ^bb5: // pred: ^bb4 -// CHECK: aie.use_lock(%[[VAL_24]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_22]] : memref<48xi32>, 0, 48) -// CHECK: aie.use_lock(%[[VAL_23]], Release, 1) +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[LINK1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK1_CONS_BUFF_1]] : memref<48xi32>, 0, 48) +// CHECK: aie.use_lock(%[[LINK1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb6: // pred: ^bb3 +// CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.mem(%[[VAL_2]]) { -// CHECK: %[[VAL_31:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_14]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_12]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_15]], Release, 1) +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_2:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK2_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK2_0_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[LINK2_0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_14]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_13]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_15]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LINK2_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK2_0_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[LINK2_0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: %[[VAL_32:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) -// CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 -// CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 1) +// CHECK: ^bb3: +// CHECK: %[[VAL_3:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[SKIP_CONNECTION_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[SKIP_CONNECTION_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[SKIP_CONNECTION_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb5 -// CHECK: ^bb5: // pred: ^bb4 -// CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 1) +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[SKIP_CONNECTION_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[SKIP_CONNECTION_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[SKIP_CONNECTION_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb6: // pred: ^bb3 +// CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.mem(%[[VAL_3]]) { -// CHECK: %[[VAL_34:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 -// CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_16]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_20]], Release, 1) +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_4:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK2_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK2_1_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[LINK2_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_20]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LINK2_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK2_1_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[LINK2_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_20]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[LINK2_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK2_1_CONS_BUFF_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[LINK2_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb4: // pred: ^bb0 -// CHECK: %[[VAL_35:.*]] = aie.dma_start(S2MM, 1, ^bb5, ^bb7) -// CHECK: ^bb5: // 2 preds: ^bb4, ^bb6 -// CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: ^bb4: +// CHECK: %[[VAL_5:.*]] = aie.dma_start(S2MM, 1, ^bb5, ^bb7) +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[SKIP_CONNECTION_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[SKIP_CONNECTION_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[SKIP_CONNECTION_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb6 -// CHECK: ^bb6: // pred: ^bb5 -// CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: ^bb6: +// CHECK: aie.use_lock(%[[SKIP_CONNECTION_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[SKIP_CONNECTION_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[SKIP_CONNECTION_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb5 -// CHECK: ^bb7: // pred: ^bb4 +// CHECK: ^bb7: // CHECK: aie.end // CHECK: } // CHECK: } @@ -146,12 +135,9 @@ module @link_broadcast { %tile21 = aie.tile(2, 1) %tile22 = aie.tile(2, 2) %tile33 = aie.tile(3, 3) - aie.objectfifo @link1 (%tile20, {%tile21}, 2 : i32) : !aie.objectfifo> aie.objectfifo @link2 (%tile21, {%tile22, %tile33}, [2, 2, 3]) : !aie.objectfifo> - aie.objectfifo @skip_connection (%tile22, {%tile33}, 2 : i32) : !aie.objectfifo> - aie.objectfifo.link [@link1] -> [@link2] () } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_distribute.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_distribute.mlir index de4d12947..b051eca67 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_distribute.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_distribute.mlir @@ -1,14 +1,3 @@ -//===- link_test_distribute.mlir ------------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: June 28th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s @@ -21,139 +10,139 @@ // CHECK: memref.global "public" @link2 : memref<4x4xi32> // CHECK: memref.global "public" @link1_cons : memref<48xi32> // CHECK: memref.global "public" @link1 : memref<48xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_3:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_5:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "link4_cons_buff_0"} : memref<12xi32> -// CHECK: %[[VAL_6:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "link4_cons_buff_1"} : memref<12xi32> -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_4]], 0) {init = 2 : i32, sym_name = "link4_cons_prod_lock"} -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_4]], 1) {init = 0 : i32, sym_name = "link4_cons_cons_lock"} -// CHECK: %[[VAL_9:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "link3_cons_buff_0"} : memref<20xi32> -// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "link3_cons_buff_1"} : memref<20xi32> -// CHECK: %[[VAL_11:.*]] = aie.lock(%[[VAL_3]], 0) {init = 2 : i32, sym_name = "link3_cons_prod_lock"} -// CHECK: %[[VAL_12:.*]] = aie.lock(%[[VAL_3]], 1) {init = 0 : i32, sym_name = "link3_cons_cons_lock"} -// CHECK: %[[VAL_13:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "link2_cons_buff_0"} : memref<4x4xi32> -// CHECK: %[[VAL_14:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "link2_cons_buff_1"} : memref<4x4xi32> -// CHECK: %[[VAL_15:.*]] = aie.lock(%[[VAL_2]], 0) {init = 2 : i32, sym_name = "link2_cons_prod_lock"} -// CHECK: %[[VAL_16:.*]] = aie.lock(%[[VAL_2]], 1) {init = 0 : i32, sym_name = "link2_cons_cons_lock"} -// CHECK: %[[VAL_17:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "link1_cons_buff_0"} : memref<48xi32> -// CHECK: %[[VAL_18:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "link1_cons_buff_1"} : memref<48xi32> -// CHECK: %[[VAL_19:.*]] = aie.lock(%[[VAL_1]], 0) {init = 6 : i32, sym_name = "link1_cons_prod_lock"} -// CHECK: %[[VAL_20:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "link1_cons_cons_lock"} -// CHECK: %[[VAL_21:.*]] = aie.lock(%[[VAL_0]], 0) {init = 1 : i32, sym_name = "link1_prod_lock"} -// CHECK: %[[VAL_22:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "link1_cons_lock"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_2]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 1, %[[VAL_3]], DMA : 0) -// CHECK: aie.flow(%[[VAL_1]], DMA : 2, %[[VAL_4]], DMA : 0) -// CHECK: %[[VAL_23:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<48xi32> +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[LINK4_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link4_cons_buff_0"} : memref<12xi32> +// CHECK: %[[LINK4_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link4_cons_buff_1"} : memref<12xi32> +// CHECK: %[[LINK4_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "link4_cons_prod_lock"} +// CHECK: %[[LINK4_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "link4_cons_cons_lock"} +// CHECK: %[[LINK3_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "link3_cons_buff_0"} : memref<20xi32> +// CHECK: %[[LINK3_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "link3_cons_buff_1"} : memref<20xi32> +// CHECK: %[[LINK3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i32, sym_name = "link3_cons_prod_lock"} +// CHECK: %[[LINK3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i32, sym_name = "link3_cons_cons_lock"} +// CHECK: %[[LINK2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_cons_buff_0"} : memref<4x4xi32> +// CHECK: %[[LINK2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_cons_buff_1"} : memref<4x4xi32> +// CHECK: %[[LINK2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "link2_cons_prod_lock"} +// CHECK: %[[LINK2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "link2_cons_cons_lock"} +// CHECK: %[[LINK1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link1_cons_buff_0"} : memref<48xi32> +// CHECK: %[[LINK1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link1_cons_buff_1"} : memref<48xi32> +// CHECK: %[[LINK1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 6 : i32, sym_name = "link1_cons_prod_lock"} +// CHECK: %[[LINK1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "link1_cons_cons_lock"} +// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 1 : i32, sym_name = "link1_prod_lock"} +// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "link1_cons_lock"} +// CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_1]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_1]], DMA : 1, %[[TILE_2_3]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_1]], DMA : 2, %[[TILE_3_3]], DMA : 0) +// CHECK: %[[EXT_BUFFER_IN:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<48xi32> // CHECK: aie.shim_dma_allocation @link1(MM2S, 0, 2) -// CHECK: %[[VAL_24:.*]] = aie.shim_dma(%[[VAL_0]]) { -// CHECK: %[[VAL_25:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 -// CHECK: aie.use_lock(%[[VAL_22]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_23]] : memref<48xi32>, 0, 48) -// CHECK: aie.use_lock(%[[VAL_21]], Release, 1) +// CHECK: %[[SHIM_DMA_2_0:.*]] = aie.shim_dma(%[[TILE_2_0]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK1_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[EXT_BUFFER_IN]] : memref<48xi32>, 0, 48) +// CHECK: aie.use_lock(%[[LINK1_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: // pred: ^bb0 +// CHECK: ^bb2: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.memtile_dma(%[[VAL_1]]) { -// CHECK: %[[VAL_27:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 3) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<48xi32>, 0, 48) -// CHECK: aie.use_lock(%[[VAL_20]], Release, 3) +// CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK1_CONS_PROD_LOCK]], AcquireGreaterEqual, 3) +// CHECK: aie.dma_bd(%[[LINK1_CONS_BUFF_0]] : memref<48xi32>, 0, 48) +// CHECK: aie.use_lock(%[[LINK1_CONS_CONS_LOCK]], Release, 3) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 3) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<48xi32>, 0, 48) -// CHECK: aie.use_lock(%[[VAL_20]], Release, 3) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LINK1_CONS_PROD_LOCK]], AcquireGreaterEqual, 3) +// CHECK: aie.dma_bd(%[[LINK1_CONS_BUFF_1]] : memref<48xi32>, 0, 48) +// CHECK: aie.use_lock(%[[LINK1_CONS_CONS_LOCK]], Release, 3) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: %[[VAL_28:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) -// CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 -// CHECK: aie.use_lock(%[[VAL_20]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<48xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_19]], Release, 1) +// CHECK: ^bb3: +// CHECK: %[[VAL_2:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[LINK1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK1_CONS_BUFF_0]] : memref<48xi32>, 0, 16) +// CHECK: aie.use_lock(%[[LINK1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb5 -// CHECK: ^bb5: // pred: ^bb4 -// CHECK: aie.use_lock(%[[VAL_20]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<48xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_19]], Release, 1) +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[LINK1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK1_CONS_BUFF_1]] : memref<48xi32>, 0, 16) +// CHECK: aie.use_lock(%[[LINK1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb6: // pred: ^bb3 -// CHECK: %[[VAL_29:.*]] = aie.dma_start(MM2S, 1, ^bb7, ^bb9) -// CHECK: ^bb7: // 2 preds: ^bb6, ^bb8 -// CHECK: aie.use_lock(%[[VAL_20]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<48xi32>, 16, 20) -// CHECK: aie.use_lock(%[[VAL_19]], Release, 1) +// CHECK: ^bb6: +// CHECK: %[[VAL_3:.*]] = aie.dma_start(MM2S, 1, ^bb7, ^bb9) +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[LINK1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK1_CONS_BUFF_0]] : memref<48xi32>, 16, 20) +// CHECK: aie.use_lock(%[[LINK1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb8 -// CHECK: ^bb8: // pred: ^bb7 -// CHECK: aie.use_lock(%[[VAL_20]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<48xi32>, 16, 20) -// CHECK: aie.use_lock(%[[VAL_19]], Release, 1) +// CHECK: ^bb8: +// CHECK: aie.use_lock(%[[LINK1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK1_CONS_BUFF_1]] : memref<48xi32>, 16, 20) +// CHECK: aie.use_lock(%[[LINK1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb7 -// CHECK: ^bb9: // pred: ^bb6 -// CHECK: %[[VAL_30:.*]] = aie.dma_start(MM2S, 2, ^bb10, ^bb12) -// CHECK: ^bb10: // 2 preds: ^bb9, ^bb11 -// CHECK: aie.use_lock(%[[VAL_20]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<48xi32>, 36, 12) -// CHECK: aie.use_lock(%[[VAL_19]], Release, 1) +// CHECK: ^bb9: +// CHECK: %[[VAL_4:.*]] = aie.dma_start(MM2S, 2, ^bb10, ^bb12) +// CHECK: ^bb10: +// CHECK: aie.use_lock(%[[LINK1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK1_CONS_BUFF_0]] : memref<48xi32>, 36, 12) +// CHECK: aie.use_lock(%[[LINK1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb11 -// CHECK: ^bb11: // pred: ^bb10 -// CHECK: aie.use_lock(%[[VAL_20]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<48xi32>, 36, 12) -// CHECK: aie.use_lock(%[[VAL_19]], Release, 1) +// CHECK: ^bb11: +// CHECK: aie.use_lock(%[[LINK1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK1_CONS_BUFF_1]] : memref<48xi32>, 36, 12) +// CHECK: aie.use_lock(%[[LINK1_CONS_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb10 -// CHECK: ^bb12: // pred: ^bb9 +// CHECK: ^bb12: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.mem(%[[VAL_2]]) { -// CHECK: %[[VAL_32:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_15]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_13]] : memref<4x4xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_16]], Release, 1) +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_5:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK2_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK2_CONS_BUFF_0]] : memref<4x4xi32>, 0, 16) +// CHECK: aie.use_lock(%[[LINK2_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_15]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_14]] : memref<4x4xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_16]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LINK2_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK2_CONS_BUFF_1]] : memref<4x4xi32>, 0, 16) +// CHECK: aie.use_lock(%[[LINK2_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.mem(%[[VAL_3]]) { -// CHECK: %[[VAL_34:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<20xi32>, 0, 20) -// CHECK: aie.use_lock(%[[VAL_12]], Release, 1) +// CHECK: %[[MEM_2_3:.*]] = aie.mem(%[[TILE_2_3]]) { +// CHECK: %[[VAL_6:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK3_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK3_CONS_BUFF_0]] : memref<20xi32>, 0, 20) +// CHECK: aie.use_lock(%[[LINK3_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<20xi32>, 0, 20) -// CHECK: aie.use_lock(%[[VAL_12]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LINK3_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK3_CONS_BUFF_1]] : memref<20xi32>, 0, 20) +// CHECK: aie.use_lock(%[[LINK3_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.mem(%[[VAL_4]]) { -// CHECK: %[[VAL_36:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<12xi32>, 0, 12) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 1) +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_7:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK4_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK4_CONS_BUFF_0]] : memref<12xi32>, 0, 12) +// CHECK: aie.use_lock(%[[LINK4_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<12xi32>, 0, 12) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LINK4_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK4_CONS_BUFF_1]] : memref<12xi32>, 0, 12) +// CHECK: aie.use_lock(%[[LINK4_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } // CHECK: } @@ -165,15 +154,12 @@ module @link_distribute { %tile22 = aie.tile(2, 2) %tile23 = aie.tile(2, 3) %tile33 = aie.tile(3, 3) - aie.objectfifo @link1 (%tile20, {%tile21}, 2 : i32) : !aie.objectfifo> aie.objectfifo @link2 (%tile21, {%tile22}, 2 : i32) : !aie.objectfifo> aie.objectfifo @link3 (%tile21, {%tile23}, 2 : i32) : !aie.objectfifo> aie.objectfifo @link4 (%tile21, {%tile33}, 2 : i32) : !aie.objectfifo> - %ext_buffer_in = aie.external_buffer {sym_name = "ext_buffer_in"}: memref<48xi32> aie.objectfifo.register_external_buffers @link1 (%tile20, {%ext_buffer_in}) : (memref<48xi32>) - aie.objectfifo.link [@link1] -> [@link2, @link3, @link4] () } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_join.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_join.mlir index bb16cca93..f417f8ab9 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_join.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/link_test_join.mlir @@ -1,14 +1,3 @@ -//===- link_test_join.mlir ------------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: June 30th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s @@ -23,172 +12,172 @@ // CHECK: memref.global "public" @link2 : memref<128xi8> // CHECK: memref.global "public" @link1_cons : memref<128xi8> // CHECK: memref.global "public" @link1 : memref<128xi8> -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_2:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_3:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_4:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_5:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_0]], 0) {init = 1 : i32, sym_name = "link5_cons_prod_lock"} -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "link5_cons_cons_lock"} -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "link5_buff_0"} : memref<512xi8> -// CHECK: %[[VAL_9:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "link5_buff_1"} : memref<512xi8> -// CHECK: %[[VAL_10:.*]] = aie.lock(%[[VAL_1]], 0) {init = 8 : i32, sym_name = "link5_prod_lock"} -// CHECK: %[[VAL_11:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "link5_cons_lock"} -// CHECK: %[[VAL_12:.*]] = aie.buffer(%[[VAL_5]]) {sym_name = "link4_buff_0"} : memref<128xi8> -// CHECK: %[[VAL_13:.*]] = aie.buffer(%[[VAL_5]]) {sym_name = "link4_buff_1"} : memref<128xi8> -// CHECK: %[[VAL_14:.*]] = aie.lock(%[[VAL_5]], 0) {init = 2 : i32, sym_name = "link4_prod_lock"} -// CHECK: %[[VAL_15:.*]] = aie.lock(%[[VAL_5]], 1) {init = 0 : i32, sym_name = "link4_cons_lock"} -// CHECK: %[[VAL_16:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "link3_buff_0"} : memref<128xi8> -// CHECK: %[[VAL_17:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "link3_buff_1"} : memref<128xi8> -// CHECK: %[[VAL_18:.*]] = aie.lock(%[[VAL_4]], 0) {init = 2 : i32, sym_name = "link3_prod_lock"} -// CHECK: %[[VAL_19:.*]] = aie.lock(%[[VAL_4]], 1) {init = 0 : i32, sym_name = "link3_cons_lock"} -// CHECK: %[[VAL_20:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "link2_buff_0"} : memref<128xi8> -// CHECK: %[[VAL_21:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "link2_buff_1"} : memref<128xi8> -// CHECK: %[[VAL_22:.*]] = aie.lock(%[[VAL_3]], 0) {init = 2 : i32, sym_name = "link2_prod_lock"} -// CHECK: %[[VAL_23:.*]] = aie.lock(%[[VAL_3]], 1) {init = 0 : i32, sym_name = "link2_cons_lock"} -// CHECK: %[[VAL_24:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "link1_buff_0"} : memref<128xi8> -// CHECK: %[[VAL_25:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "link1_buff_1"} : memref<128xi8> -// CHECK: %[[VAL_26:.*]] = aie.lock(%[[VAL_2]], 0) {init = 2 : i32, sym_name = "link1_prod_lock"} -// CHECK: %[[VAL_27:.*]] = aie.lock(%[[VAL_2]], 1) {init = 0 : i32, sym_name = "link1_cons_lock"} -// CHECK: aie.flow(%[[VAL_2]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: aie.flow(%[[VAL_3]], DMA : 0, %[[VAL_1]], DMA : 1) -// CHECK: aie.flow(%[[VAL_4]], DMA : 0, %[[VAL_1]], DMA : 2) -// CHECK: aie.flow(%[[VAL_5]], DMA : 0, %[[VAL_1]], DMA : 3) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_0]], DMA : 0) -// CHECK: %[[VAL_28:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<512xi8> -// CHECK: %[[VAL_29:.*]] = aie.mem(%[[VAL_2]]) { -// CHECK: %[[VAL_30:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_27]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_24]] : memref<128xi8>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_26]], Release, 1) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[LINK5_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 1 : i32, sym_name = "link5_cons_prod_lock"} +// CHECK: %[[LINK5_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "link5_cons_cons_lock"} +// CHECK: %[[LINK5_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link5_buff_0"} : memref<512xi8> +// CHECK: %[[LINK5_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "link5_buff_1"} : memref<512xi8> +// CHECK: %[[LINK5_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 8 : i32, sym_name = "link5_prod_lock"} +// CHECK: %[[LINK5_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "link5_cons_lock"} +// CHECK: %[[LINK4_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link4_buff_0"} : memref<128xi8> +// CHECK: %[[LINK4_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "link4_buff_1"} : memref<128xi8> +// CHECK: %[[LINK4_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "link4_prod_lock"} +// CHECK: %[[LINK4_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "link4_cons_lock"} +// CHECK: %[[LINK3_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "link3_buff_0"} : memref<128xi8> +// CHECK: %[[LINK3_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "link3_buff_1"} : memref<128xi8> +// CHECK: %[[LINK3_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i32, sym_name = "link3_prod_lock"} +// CHECK: %[[LINK3_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i32, sym_name = "link3_cons_lock"} +// CHECK: %[[LINK2_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_buff_0"} : memref<128xi8> +// CHECK: %[[LINK2_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "link2_buff_1"} : memref<128xi8> +// CHECK: %[[LINK2_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "link2_prod_lock"} +// CHECK: %[[LINK2_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "link2_cons_lock"} +// CHECK: %[[LINK1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "link1_buff_0"} : memref<128xi8> +// CHECK: %[[LINK1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "link1_buff_1"} : memref<128xi8> +// CHECK: %[[LINK1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i32, sym_name = "link1_prod_lock"} +// CHECK: %[[LINK1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "link1_cons_lock"} +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_2_1]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_1]], DMA : 1) +// CHECK: aie.flow(%[[TILE_2_3]], DMA : 0, %[[TILE_2_1]], DMA : 2) +// CHECK: aie.flow(%[[TILE_3_3]], DMA : 0, %[[TILE_2_1]], DMA : 3) +// CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_0]], DMA : 0) +// CHECK: %[[EXT_BUFFER_IN:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<512xi8> +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK1_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK1_BUFF_0]] : memref<128xi8>, 0, 128) +// CHECK: aie.use_lock(%[[LINK1_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_27]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_25]] : memref<128xi8>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_26]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LINK1_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK1_BUFF_1]] : memref<128xi8>, 0, 128) +// CHECK: aie.use_lock(%[[LINK1_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.memtile_dma(%[[VAL_1]]) { -// CHECK: %[[VAL_32:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK5_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK5_BUFF_0]] : memref<512xi8>, 0, 128) +// CHECK: aie.use_lock(%[[LINK5_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LINK5_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK5_BUFF_1]] : memref<512xi8>, 0, 128) +// CHECK: aie.use_lock(%[[LINK5_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: %[[VAL_33:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb6) -// CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>, 128, 128) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: ^bb3: +// CHECK: %[[VAL_2:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[LINK5_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK5_BUFF_0]] : memref<512xi8>, 128, 128) +// CHECK: aie.use_lock(%[[LINK5_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb5 -// CHECK: ^bb5: // pred: ^bb4 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>, 128, 128) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[LINK5_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK5_BUFF_1]] : memref<512xi8>, 128, 128) +// CHECK: aie.use_lock(%[[LINK5_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb6: // pred: ^bb3 -// CHECK: %[[VAL_34:.*]] = aie.dma_start(S2MM, 2, ^bb7, ^bb9) -// CHECK: ^bb7: // 2 preds: ^bb6, ^bb8 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>, 256, 128) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: ^bb6: +// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 2, ^bb7, ^bb9) +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[LINK5_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK5_BUFF_0]] : memref<512xi8>, 256, 128) +// CHECK: aie.use_lock(%[[LINK5_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb8 -// CHECK: ^bb8: // pred: ^bb7 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>, 256, 128) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: ^bb8: +// CHECK: aie.use_lock(%[[LINK5_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK5_BUFF_1]] : memref<512xi8>, 256, 128) +// CHECK: aie.use_lock(%[[LINK5_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb7 -// CHECK: ^bb9: // pred: ^bb6 -// CHECK: %[[VAL_35:.*]] = aie.dma_start(S2MM, 3, ^bb10, ^bb12) -// CHECK: ^bb10: // 2 preds: ^bb9, ^bb11 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>, 384, 128) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: ^bb9: +// CHECK: %[[VAL_4:.*]] = aie.dma_start(S2MM, 3, ^bb10, ^bb12) +// CHECK: ^bb10: +// CHECK: aie.use_lock(%[[LINK5_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK5_BUFF_0]] : memref<512xi8>, 384, 128) +// CHECK: aie.use_lock(%[[LINK5_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb11 -// CHECK: ^bb11: // pred: ^bb10 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>, 384, 128) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: ^bb11: +// CHECK: aie.use_lock(%[[LINK5_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK5_BUFF_1]] : memref<512xi8>, 384, 128) +// CHECK: aie.use_lock(%[[LINK5_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb10 -// CHECK: ^bb12: // pred: ^bb9 -// CHECK: %[[VAL_36:.*]] = aie.dma_start(MM2S, 0, ^bb13, ^bb15) -// CHECK: ^bb13: // 2 preds: ^bb12, ^bb14 -// CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 4) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<512xi8>, 0, 512) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 4) +// CHECK: ^bb12: +// CHECK: %[[VAL_5:.*]] = aie.dma_start(MM2S, 0, ^bb13, ^bb15) +// CHECK: ^bb13: +// CHECK: aie.use_lock(%[[LINK5_CONS_LOCK]], AcquireGreaterEqual, 4) +// CHECK: aie.dma_bd(%[[LINK5_BUFF_0]] : memref<512xi8>, 0, 512) +// CHECK: aie.use_lock(%[[LINK5_PROD_LOCK]], Release, 4) // CHECK: aie.next_bd ^bb14 -// CHECK: ^bb14: // pred: ^bb13 -// CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 4) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<512xi8>, 0, 512) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 4) +// CHECK: ^bb14: +// CHECK: aie.use_lock(%[[LINK5_CONS_LOCK]], AcquireGreaterEqual, 4) +// CHECK: aie.dma_bd(%[[LINK5_BUFF_1]] : memref<512xi8>, 0, 512) +// CHECK: aie.use_lock(%[[LINK5_PROD_LOCK]], Release, 4) // CHECK: aie.next_bd ^bb13 -// CHECK: ^bb15: // pred: ^bb12 +// CHECK: ^bb15: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_37:.*]] = aie.mem(%[[VAL_3]]) { -// CHECK: %[[VAL_38:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_23]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_20]] : memref<128xi8>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_22]], Release, 1) +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_6:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK2_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK2_BUFF_0]] : memref<128xi8>, 0, 128) +// CHECK: aie.use_lock(%[[LINK2_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_23]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_21]] : memref<128xi8>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_22]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LINK2_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK2_BUFF_1]] : memref<128xi8>, 0, 128) +// CHECK: aie.use_lock(%[[LINK2_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_39:.*]] = aie.mem(%[[VAL_4]]) { -// CHECK: %[[VAL_40:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_16]] : memref<128xi8>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_18]], Release, 1) +// CHECK: %[[MEM_2_3:.*]] = aie.mem(%[[TILE_2_3]]) { +// CHECK: %[[VAL_7:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK3_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK3_BUFF_0]] : memref<128xi8>, 0, 128) +// CHECK: aie.use_lock(%[[LINK3_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_19]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_17]] : memref<128xi8>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_18]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LINK3_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK3_BUFF_1]] : memref<128xi8>, 0, 128) +// CHECK: aie.use_lock(%[[LINK3_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.mem(%[[VAL_5]]) { -// CHECK: %[[VAL_42:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_15]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_12]] : memref<128xi8>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_14]], Release, 1) +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_8:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK4_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK4_BUFF_0]] : memref<128xi8>, 0, 128) +// CHECK: aie.use_lock(%[[LINK4_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_15]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_13]] : memref<128xi8>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_14]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LINK4_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[LINK4_BUFF_1]] : memref<128xi8>, 0, 128) +// CHECK: aie.use_lock(%[[LINK4_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } // CHECK: aie.shim_dma_allocation @link5(S2MM, 0, 2) -// CHECK: %[[VAL_43:.*]] = aie.shim_dma(%[[VAL_0]]) { -// CHECK: %[[VAL_44:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 -// CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_28]] : memref<512xi8>, 0, 512) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: %[[SHIM_DMA_2_0:.*]] = aie.shim_dma(%[[TILE_2_0]]) { +// CHECK: %[[VAL_9:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb2) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LINK5_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[EXT_BUFFER_IN]] : memref<512xi8>, 0, 512) +// CHECK: aie.use_lock(%[[LINK5_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: // pred: ^bb0 +// CHECK: ^bb2: // CHECK: aie.end // CHECK: } // CHECK: } @@ -201,16 +190,13 @@ module @link_join { %tile22 = aie.tile(2, 2) %tile23 = aie.tile(2, 3) %tile33 = aie.tile(3, 3) - aie.objectfifo @link1 (%tile12, {%tile21}, 2 : i32) : !aie.objectfifo> aie.objectfifo @link2 (%tile22, {%tile21}, 2 : i32) : !aie.objectfifo> aie.objectfifo @link3 (%tile23, {%tile21}, 2 : i32) : !aie.objectfifo> aie.objectfifo @link4 (%tile33, {%tile21}, 2 : i32) : !aie.objectfifo> aie.objectfifo @link5 (%tile21, {%tile20}, 2 : i32) : !aie.objectfifo> - %ext_buffer_in = aie.external_buffer {sym_name = "ext_buffer_in"}: memref<512xi8> aie.objectfifo.register_external_buffers @link5 (%tile20, {%ext_buffer_in}) : (memref<512xi8>) - aie.objectfifo.link [@link1, @link2, @link3, @link4] -> [@link5] () } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/local_locks.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/local_locks.mlir index 2b63f5aff..2775f4d92 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/local_locks.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/local_locks.mlir @@ -1,25 +1,15 @@ -//===- local_locks.mlir ----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// +// RUN: iree-opt --aie-standard-lowering %s | FileCheck %s -// RUN: iree-opt --aie-standard-lowering="tilecol=3 tilerow=3" %s | FileCheck --check-prefix=CHECK33 %s - -// CHECK33: func.func @core_3_3() { -// CHECK33: %c56 = arith.constant 56 : index -// CHECK33: %0 = arith.index_cast %c56 : index to i32 -// CHECK33: %c0_i32 = arith.constant 0 : i32 -// CHECK33: call @llvm.aie.lock.acquire.reg(%0, %c0_i32) : (i32, i32) -> () -// CHECK33: %1 = arith.index_cast %c56 : index to i32 -// CHECK33: %c1_i32 = arith.constant 1 : i32 -// CHECK33: call @llvm.aie.lock.release.reg(%1, %c1_i32) : (i32, i32) -> () -// CHECK33: return -// CHECK33: } +// CHECK-LABEL: func.func @core_3_3() { +// CHECK: %[[C56:.*]] = arith.constant 56 : index +// CHECK: %[[VAL_0:.*]] = arith.index_cast %[[C56]] : index to i32 +// CHECK: %[[C0_I32:.*]] = arith.constant 0 : i32 +// CHECK: call @llvm.aie.lock.acquire.reg(%[[VAL_0]], %[[C0_I32]]) : (i32, i32) -> () +// CHECK: %[[VAL_1:.*]] = arith.index_cast %[[C56]] : index to i32 +// CHECK: %[[C1_I32:.*]] = arith.constant 1 : i32 +// CHECK: call @llvm.aie.lock.release.reg(%[[VAL_1]], %[[C1_I32]]) : (i32, i32) -> () +// CHECK: return +// CHECK: } module @local_locks { aie.device(xcvc1902) { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/locks1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/locks1.mlir index 8eee39573..6c9f6376e 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/locks1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/locks1.mlir @@ -1,54 +1,46 @@ -//===- locks1.mlir ---------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// + // RUN: iree-opt --aie-localize-locks %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_1:.*]] = aie.tile(3, 4) -// CHECK: %[[VAL_2:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_3:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_0]], 0) -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_3]], 8) -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_4]], 8) -// CHECK: %[[VAL_8:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: %[[VAL_9:.*]] = arith.constant 48 : index -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) +// CHECK: %[[LOCK_1_1:.*]] = aie.lock(%[[TILE_1_1]], 0) +// CHECK: %[[LOCK_3_3:.*]] = aie.lock(%[[TILE_3_3]], 8) +// CHECK: %[[LOCK_4_3:.*]] = aie.lock(%[[TILE_4_3]], 8) +// CHECK: %[[CORE_1_1:.*]] = aie.core(%[[TILE_1_1]]) { +// CHECK: %[[C48:.*]] = arith.constant 48 : index +// CHECK: aie.use_lock(%[[C48]], Acquire, 0) +// CHECK: aie.use_lock(%[[C48]], Release, 1) // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_10:.*]] = aie.core(%[[VAL_1]]) { -// CHECK: %[[VAL_11:.*]] = arith.constant 8 : index -// CHECK: aie.use_lock(%[[VAL_11]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: %[[CORE_3_4:.*]] = aie.core(%[[TILE_3_4]]) { +// CHECK: %[[C8:.*]] = arith.constant 8 : index +// CHECK: aie.use_lock(%[[C8]], Acquire, 0) +// CHECK: aie.use_lock(%[[C8]], Release, 1) // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_12:.*]] = aie.core(%[[VAL_2]]) { -// CHECK: %[[VAL_13:.*]] = arith.constant 40 : index -// CHECK: aie.use_lock(%[[VAL_13]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_13]], Release, 1) +// CHECK: %[[CORE_3_2:.*]] = aie.core(%[[TILE_3_2]]) { +// CHECK: %[[C40:.*]] = arith.constant 40 : index +// CHECK: aie.use_lock(%[[C40]], Acquire, 0) +// CHECK: aie.use_lock(%[[C40]], Release, 1) // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_14:.*]] = aie.core(%[[VAL_3]]) { -// CHECK: %[[VAL_15:.*]] = arith.constant 56 : index -// CHECK: aie.use_lock(%[[VAL_15]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_15]], Release, 1) +// CHECK: %[[CORE_3_3:.*]] = aie.core(%[[TILE_3_3]]) { +// CHECK: %[[C56:.*]] = arith.constant 56 : index +// CHECK: aie.use_lock(%[[C56]], Acquire, 0) +// CHECK: aie.use_lock(%[[C56]], Release, 1) // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_16:.*]] = aie.core(%[[VAL_4]]) { -// CHECK: %[[VAL_17:.*]] = arith.constant 56 : index -// CHECK: %[[VAL_18:.*]] = arith.constant 24 : index -// CHECK: aie.use_lock(%[[VAL_18]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_18]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_17]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_17]], Release, 1) +// CHECK: %[[CORE_4_3:.*]] = aie.core(%[[TILE_4_3]]) { +// CHECK: %[[C56:.*]] = arith.constant 56 : index +// CHECK: %[[C24:.*]] = arith.constant 24 : index +// CHECK: aie.use_lock(%[[C24]], Acquire, 0) +// CHECK: aie.use_lock(%[[C24]], Release, 1) +// CHECK: aie.use_lock(%[[C56]], Acquire, 0) +// CHECK: aie.use_lock(%[[C56]], Release, 1) // CHECK: aie.end // CHECK: } // CHECK: } @@ -60,11 +52,9 @@ module @test_xaie0 { %t32 = aie.tile(3, 2) %t33 = aie.tile(3, 3) %t43 = aie.tile(4, 3) - %l11_8 = aie.lock(%t11, 0) %l33_8 = aie.lock(%t33, 8) %l43_8 = aie.lock(%t43, 8) - aie.core(%t11) { aie.use_lock(%l11_8, Acquire, 0) aie.use_lock(%l11_8, Release, 1) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/loop_test.aie.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/loop_test.aie.mlir index 4faf2894a..f2159fa4a 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/loop_test.aie.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/loop_test.aie.mlir @@ -1,99 +1,94 @@ -//===- loop_test.aie.mlir --------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -// Date: February 9th 2022 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK-DAG: %[[TILE_1_2:.*]] = aie.tile(1, 2) -// CHECK-DAG: %[[BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_0"} : memref<16xi32> -// CHECK-DAG: %[[BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_1"} : memref<16xi32> -// CHECK-DAG: %[[BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_2"} : memref<16xi32> -// CHECK-DAG: %[[BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_3"} : memref<16xi32> -// CHECK-DAG: %[[LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 0 : i32, sym_name = "loop_of_lock_0"} -// CHECK-DAG: %[[LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "loop_of_lock_1"} -// CHECK-DAG: %[[LOCK_2:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 0 : i32, sym_name = "loop_of_lock_2"} -// CHECK-DAG: %[[LOCK_3:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "loop_of_lock_3"} -// CHECK: func.func @some_work(%[[VAL_10:.*]]: memref<16xi32>, %[[VAL_11:.*]]: index) { +// CHECK: memref.global "public" @loop_of : memref<16xi32> +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[LOOP_OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_0"} : memref<16xi32> +// CHECK: %[[LOOP_OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_1"} : memref<16xi32> +// CHECK: %[[LOOP_OF_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_2"} : memref<16xi32> +// CHECK: %[[LOOP_OF_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_3"} : memref<16xi32> +// CHECK: %[[LOOP_OF_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 0 : i32, sym_name = "loop_of_lock_0"} +// CHECK: %[[LOOP_OF_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "loop_of_lock_1"} +// CHECK: %[[LOOP_OF_LOCK_2:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 0 : i32, sym_name = "loop_of_lock_2"} +// CHECK: %[[LOOP_OF_LOCK_3:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "loop_of_lock_3"} +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: index) { // CHECK: return // CHECK: } // CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { -// CHECK: %[[VAL_13:.*]] = arith.constant 0 : index +// CHECK: %[[C0:.*]] = arith.constant 0 : index // CHECK: %[[C1:.*]] = arith.constant 1 : index // CHECK: %[[C2:.*]] = arith.constant 2 : index // CHECK: %[[C4:.*]] = arith.constant 4 : index // CHECK: %[[C21:.*]] = arith.constant 21 : index -// CHECK: aie.use_lock(%[[LOCK_0]], Acquire, 0) -// CHECK: func.call @some_work(%[[BUFF_0]], %[[VAL_13]]) : (memref<16xi32>, index) -> () -// CHECK: aie.use_lock(%[[LOCK_0]], Release, 1) +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Acquire, 0) +// CHECK: func.call @some_work(%[[LOOP_OF_BUFF_0]], %[[C0]]) : (memref<16xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Release, 1) // CHECK: %[[C17:.*]] = arith.constant 17 : index -// CHECK: %[[VAL_19:.*]] = arith.constant 8 : index -// CHECK: scf.for %[[ARG0:.*]] = %[[C1]] to %[[C17]] step %[[VAL_19]] { -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Acquire, 0) -// CHECK-NEXT: func.call @some_work(%[[BUFF_1]], %[[ARG0]]) : (memref<16xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Release, 1) -// CHECK-DAG: %[[C1_1:.*]] = arith.constant 1 : index -// CHECK-DAG: %[[MUL_0:.*]] = arith.muli %[[C2]], %[[C1_1]] : index -// CHECK-DAG: %[[ADD_0:.*]] = arith.addi %[[ARG0]], %[[MUL_0]] : index -// CHECK-DAG: aie.use_lock(%[[LOCK_2]], Acquire, 0) -// CHECK: func.call @some_work(%[[BUFF_2]], %[[ADD_0]]) : (memref<16xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_2]], Release, 1) -// CHECK-DAG: %[[C2_1:.*]] = arith.constant 2 : index -// CHECK-DAG: %[[MUL_1:.*]] = arith.muli %[[C2]], %[[C2_1]] : index -// CHECK-DAG: %[[ADD_1:.*]] = arith.addi %[[ARG0]], %[[MUL_1]] : index -// CHECK-DAG: aie.use_lock(%[[LOCK_3]], Acquire, 0) -// CHECK: func.call @some_work(%[[BUFF_3]], %[[ADD_1]]) : (memref<16xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_3]], Release, 1) -// CHECK-DAG: %[[C3_1:.*]] = arith.constant 3 : index -// CHECK-DAG: %[[MUL_2:.*]] = arith.muli %[[C2]], %[[C3_1]] : index -// CHECK-DAG: %[[ADD_2:.*]] = arith.addi %[[ARG0]], %[[MUL_2]] : index -// CHECK-DAG: aie.use_lock(%[[LOCK_0]], Acquire, 0) -// CHECK: func.call @some_work(%[[BUFF_0]], %[[ADD_2]]) : (memref<16xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_0]], Release, 1) -// CHECK-NEXT: } -// CHECK: scf.for %[[ARG0:.+]] = %[[C17]] to %[[C21]] step %c2 { -// CHECK-DAG: aie.use_lock(%[[LOCK_1]], Acquire, 0) -// CHECK: func.call @some_work(%[[BUFF_1]], %[[ARG0]]) : (memref<16xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Release, 1) -// CHECK-NEXT: } -// CHECK: %[[C1_0:.+]] = arith.constant 1 : index -// CHECK: %[[C4_1:.+]] = arith.constant 4 : index -// CHECK: scf.for %[[ARG0:.+]] = %[[C1]] to %[[C1_0]] step %[[C4_1]] { -// CHECK-NEXT: aie.use_lock(%[[LOCK_2]], Acquire, 0) -// CHECK-NEXT: func.call @some_work(%[[BUFF_2]], %[[ARG0]]) : (memref<16xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_2]], Release, 1) -// CHECK-DAG: %[[C1_2:.*]] = arith.constant 1 : index -// CHECK-DAG: %[[MUL_0:.*]] = arith.muli %[[C1]], %[[C1_2]] : index -// CHECK-DAG: %[[ADD_0:.*]] = arith.addi %[[ARG0]], %[[MUL_0]] : index -// CHECK-DAG: aie.use_lock(%[[LOCK_3]], Acquire, 0) -// CHECK: func.call @some_work(%[[BUFF_3]], %[[ADD_0]]) : (memref<16xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_3]], Release, 1) -// CHECK-DAG: %[[C2_3:.*]] = arith.constant 2 : index -// CHECK-DAG: %[[MUL_1:.*]] = arith.muli %[[C1]], %[[C2_3]] : index -// CHECK-DAG: %[[ADD_1:.*]] = arith.addi %[[ARG0]], %[[MUL_1]] : index -// CHECK-DAG: aie.use_lock(%[[LOCK_0]], Acquire, 0) -// CHECK: func.call @some_work(%[[BUFF_0]], %[[ADD_1]]) : (memref<16xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_0]], Release, 1) -// CHECK-DAG: %[[C3:.*]] = arith.constant 3 : index -// CHECK-DAG: %[[MUL_2:.*]] = arith.muli %[[C1]], %[[C3]] : index -// CHECK-DAG: %[[ADD_2:.*]] = arith.addi %[[ARG0]], %[[MUL_2]] : index -// CHECK-DAG: aie.use_lock(%[[LOCK_1]], Acquire, 0) -// CHECK: func.call @some_work(%[[BUFF_1]], %[[ADD_2]]) : (memref<16xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Release, 1) -// CHECK-NEXT: } -// CHECK: scf.for %[[ARG0:.+]] = %[[C1_0]] to %[[C4]] step %[[C1]] { -// CHECK-DAG: aie.use_lock(%[[LOCK_2]], Acquire, 0) -// CHECK: func.call @some_work(%[[BUFF_2]], %[[ARG0]]) : (memref<16xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_2]], Release, 1) -// CHECK-NEXT: } +// CHECK: %[[C8:.*]] = arith.constant 8 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C1]] to %[[C17]] step %[[C8]] { +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Acquire, 0) +// CHECK: func.call @some_work(%[[LOOP_OF_BUFF_1]], %[[ARG0]]) : (memref<16xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Release, 1) +// CHECK: %[[C1_2:.*]] = arith.constant 1 : index +// CHECK: %[[VAL_0:.*]] = arith.muli %[[C2]], %[[C1_2]] : index +// CHECK: %[[VAL_1:.*]] = arith.addi %[[ARG0]], %[[VAL_0]] : index +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_2]], Acquire, 0) +// CHECK: func.call @some_work(%[[LOOP_OF_BUFF_2]], %[[VAL_1]]) : (memref<16xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_2]], Release, 1) +// CHECK: %[[C2_3:.*]] = arith.constant 2 : index +// CHECK: %[[VAL_2:.*]] = arith.muli %[[C2]], %[[C2_3]] : index +// CHECK: %[[VAL_3:.*]] = arith.addi %[[ARG0]], %[[VAL_2]] : index +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_3]], Acquire, 0) +// CHECK: func.call @some_work(%[[LOOP_OF_BUFF_3]], %[[VAL_3]]) : (memref<16xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_3]], Release, 1) +// CHECK: %[[C3:.*]] = arith.constant 3 : index +// CHECK: %[[VAL_4:.*]] = arith.muli %[[C2]], %[[C3]] : index +// CHECK: %[[VAL_5:.*]] = arith.addi %[[ARG0]], %[[VAL_4]] : index +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Acquire, 0) +// CHECK: func.call @some_work(%[[LOOP_OF_BUFF_0]], %[[VAL_5]]) : (memref<16xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Release, 1) +// CHECK: } +// CHECK: scf.for %[[ARG0:.*]] = %[[C17]] to %[[C21]] step %[[C2]] { +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Acquire, 0) +// CHECK: func.call @some_work(%[[LOOP_OF_BUFF_1]], %[[ARG0]]) : (memref<16xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Release, 1) +// CHECK: } +// CHECK: %[[C1_0:.*]] = arith.constant 1 : index +// CHECK: %[[C4_1:.*]] = arith.constant 4 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C1]] to %[[C1_0]] step %[[C4_1]] { +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_2]], Acquire, 0) +// CHECK: func.call @some_work(%[[LOOP_OF_BUFF_2]], %[[ARG0]]) : (memref<16xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_2]], Release, 1) +// CHECK: %[[C1_2:.*]] = arith.constant 1 : index +// CHECK: %[[VAL_6:.*]] = arith.muli %[[C1]], %[[C1_2]] : index +// CHECK: %[[VAL_7:.*]] = arith.addi %[[ARG0]], %[[VAL_6]] : index +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_3]], Acquire, 0) +// CHECK: func.call @some_work(%[[LOOP_OF_BUFF_3]], %[[VAL_7]]) : (memref<16xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_3]], Release, 1) +// CHECK: %[[C2_3:.*]] = arith.constant 2 : index +// CHECK: %[[VAL_8:.*]] = arith.muli %[[C1]], %[[C2_3]] : index +// CHECK: %[[VAL_9:.*]] = arith.addi %[[ARG0]], %[[VAL_8]] : index +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Acquire, 0) +// CHECK: func.call @some_work(%[[LOOP_OF_BUFF_0]], %[[VAL_9]]) : (memref<16xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Release, 1) +// CHECK: %[[C3:.*]] = arith.constant 3 : index +// CHECK: %[[VAL_10:.*]] = arith.muli %[[C1]], %[[C3]] : index +// CHECK: %[[VAL_11:.*]] = arith.addi %[[ARG0]], %[[VAL_10]] : index +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Acquire, 0) +// CHECK: func.call @some_work(%[[LOOP_OF_BUFF_1]], %[[VAL_11]]) : (memref<16xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Release, 1) +// CHECK: } +// CHECK: scf.for %[[ARG0:.*]] = %[[C1_0]] to %[[C4]] step %[[C1]] { +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_2]], Acquire, 0) +// CHECK: func.call @some_work(%[[LOOP_OF_BUFF_2]], %[[ARG0]]) : (memref<16xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_2]], Release, 1) +// CHECK: } +// CHECK: aie.end +// CHECK: } +// CHECK: } + module { aie.device(xcvc1902) { %tile12 = aie.tile(1, 2) @@ -127,4 +122,4 @@ module { aie.end } } -} \ No newline at end of file +} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/loop_test_nested.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/loop_test_nested.mlir index d550c4b9c..3ea2174d5 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/loop_test_nested.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/loop_test_nested.mlir @@ -1,102 +1,98 @@ -//===- loop_test_nested.mlir -----------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2024 AMD Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { // CHECK: memref.global "public" @loop_of : memref<16xi32> -// CHECK-DAG: %[[TILE_1_2:.*]] = aie.tile(1, 2) -// CHECK-DAG: %[[BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_0"} : memref<16xi32> -// CHECK-DAG: %[[BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_1"} : memref<16xi32> -// CHECK-DAG: %[[LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 0 : i32, sym_name = "loop_of_lock_0"} -// CHECK-DAG: %[[LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "loop_of_lock_1"} -// CHECK: func.func @some_work(%{{.+}}: memref<4x4xi32>, %{{.+}}: index) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[LOOP_OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_0"} : memref<16xi32> +// CHECK: %[[LOOP_OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "loop_of_buff_1"} : memref<16xi32> +// CHECK: %[[LOOP_OF_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 0 : i32, sym_name = "loop_of_lock_0"} +// CHECK: %[[LOOP_OF_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "loop_of_lock_1"} +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<4x4xi32>, %[[ARG1:.*]]: index) { // CHECK: return // CHECK: } // CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { -// CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index -// CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index -// CHECK-DAG: %[[C2:.*]] = arith.constant 2 : index -// CHECK-DAG: %[[C4:.*]] = arith.constant 4 : index -// CHECK-DAG: %[[C21:.*]] = arith.constant 21 : index -// CHECK-DAG: %[[C4294967295:.*]] = arith.constant 4294967295 : index -// CHECK-DAG: %[[C4294967294:.*]] = arith.constant 4294967294 : index -// CHECK-DAG: %[[C2_0:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[ARG0:.+]] = %[[C0]] to %[[C4294967294]] step %[[C2_0]] { -// CHECK: aie.use_lock(%[[LOCK_0]], Acquire, 0) -// CHECK-NEXT: %[[REINTERPRET_0:.+]] = memref.reinterpret_cast %[[BUFF_0]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> -// CHECK-NEXT: func.call @some_work(%[[REINTERPRET_0]], %[[C0]]) : (memref<4x4xi32>, index) -> () -// CHECK: aie.use_lock(%[[LOCK_0]], Release, 1) -// CHECK-DAG: %[[C2_4:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[ARG1:.+]] = %[[C1]] to %[[C21]] step %[[C2_4]] { -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Acquire, 0) -// CHECK-NEXT: %[[REINTERPRET_1:.+]] = memref.reinterpret_cast %[[BUFF_1]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> -// CHECK-NEXT: func.call @some_work(%[[REINTERPRET_1]], %[[ARG1]]) : (memref<4x4xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Release, 1) -// CHECK-DAG: %[[C1_1:.*]] = arith.constant 1 : index -// CHECK-DAG: %[[MUL_0:.*]] = arith.muli %[[C1]], %[[C1_1]] : index -// CHECK-DAG: %[[ADD_0:.*]] = arith.addi %[[ARG1]], %[[MUL_0]] : index -// CHECK-DAG: aie.use_lock(%[[LOCK_0]], Acquire, 0) -// CHECK: %[[REINTERPRET_2:.+]] = memref.reinterpret_cast %[[BUFF_0]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> -// CHECK-NEXT: func.call @some_work(%[[REINTERPRET_2]], %[[ADD_0]]) : (memref<4x4xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_0]], Release, 1) -// CHECK-NEXT: } -// CHECK: aie.use_lock(%[[LOCK_1]], Acquire, 0) -// CHECK-NEXT: %[[REINTERPRET_3:.+]] = memref.reinterpret_cast %[[BUFF_1]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> -// CHECK-NEXT: func.call @some_work(%[[REINTERPRET_3]], %[[C0]]) : (memref<4x4xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Release, 1) -// CHECK: aie.use_lock(%[[LOCK_0]], Acquire, 0) -// CHECK-NEXT: %[[REINTERPRET_4:.+]] = memref.reinterpret_cast %[[BUFF_0]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> -// CHECK-NEXT: func.call @some_work(%[[REINTERPRET_4]], %[[C0]]) : (memref<4x4xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_0]], Release, 1) -// CHECK: %[[C2_3:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[ARG1:.+]] = %[[C1]] to %[[C21]] step %[[C2_3]] { -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Acquire, 0) -// CHECK-NEXT: %[[REINTERPRET_5:.+]] = memref.reinterpret_cast %[[BUFF_1]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> -// CHECK-NEXT: func.call @some_work(%[[REINTERPRET_5]], %[[ARG1]]) : (memref<4x4xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Release, 1) -// CHECK-DAG: %[[C1_1:.*]] = arith.constant 1 : index -// CHECK-DAG: %[[MUL_1:.*]] = arith.muli %[[C1]], %[[C1_1]] : index -// CHECK-DAG: %[[ADD_1:.*]] = arith.addi %[[ARG1]], %[[MUL_1]] : index -// CHECK-DAG: aie.use_lock(%[[LOCK_0]], Acquire, 0) -// CHECK: %[[REINTERPRET_6:.+]] = memref.reinterpret_cast %[[BUFF_0]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> -// CHECK-NEXT: func.call @some_work(%[[REINTERPRET_6]], %[[ADD_1]]) : (memref<4x4xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_0]], Release, 1) -// CHECK-NEXT: } -// CHECK: aie.use_lock(%[[LOCK_1]], Acquire, 0) -// CHECK-NEXT: %[[REINTERPRET_7:.+]] = memref.reinterpret_cast %[[BUFF_1]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> -// CHECK-NEXT: func.call @some_work(%[[REINTERPRET_7]], %[[C0]]) : (memref<4x4xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Release, 1) -// CHECK-NEXT: } -// CHECK: aie.use_lock(%[[LOCK_0]], Acquire, 0) -// CHECK-NEXT: %[[REINTERPRET_8:.+]] = memref.reinterpret_cast %[[BUFF_0]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> -// CHECK-NEXT: func.call @some_work(%[[REINTERPRET_8]], %[[C0]]) : (memref<4x4xi32>, index) -> () -// CHECK: aie.use_lock(%[[LOCK_0]], Release, 1) -// CHECK: %[[C2_4:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[ARG0:.+]] = %[[C1]] to %[[C21]] step %[[C2_4]] { -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Acquire, 0) -// CHECK-NEXT: %[[REINTERPRET_9:.+]] = memref.reinterpret_cast %[[BUFF_1]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> -// CHECK-NEXT: func.call @some_work(%[[REINTERPRET_9]], %[[ARG0]]) : (memref<4x4xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Release, 1) -// CHECK-DAG: %[[C1_4:.*]] = arith.constant 1 : index -// CHECK-DAG: %[[MUL_2:.*]] = arith.muli %[[C1]], %[[C1_4]] : index -// CHECK-DAG: %[[ADD_2:.*]] = arith.addi %[[ARG0]], %[[MUL_2]] : index -// CHECK-DAG: aie.use_lock(%[[LOCK_0]], Acquire, 0) -// CHECK: %[[REINTERPRET_10:.+]] = memref.reinterpret_cast %[[BUFF_0]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> -// CHECK-NEXT: func.call @some_work(%[[REINTERPRET_10]], %[[ADD_1]]) : (memref<4x4xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_0]], Release, 1) -// CHECK-NEXT: } -// CHECK: aie.use_lock(%[[LOCK_1]], Acquire, 0) -// CHECK-NEXT: %[[REINTERPRET_11:.+]] = memref.reinterpret_cast %[[BUFF_1]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> -// CHECK-NEXT: func.call @some_work(%[[REINTERPRET_11]], %[[C0]]) : (memref<4x4xi32>, index) -> () -// CHECK-NEXT: aie.use_lock(%[[LOCK_1]], Release, 1) +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: %[[C4:.*]] = arith.constant 4 : index +// CHECK: %[[C21:.*]] = arith.constant 21 : index +// CHECK: %[[C4294967295:.*]] = arith.constant 4294967295 : index +// CHECK: %[[C4294967294:.*]] = arith.constant 4294967294 : index +// CHECK: %[[C2_0:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C4294967294]] step %[[C2_0]] { +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Acquire, 0) +// CHECK: %[[REINTERPRET_CAST_3:.*]] = memref.reinterpret_cast %[[LOOP_OF_BUFF_0]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> +// CHECK: func.call @some_work(%[[REINTERPRET_CAST_3]], %[[C0]]) : (memref<4x4xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Release, 1) +// CHECK: %[[C2_4:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG1:.*]] = %[[C1]] to %[[C21]] step %[[C2_4]] { +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Acquire, 0) +// CHECK: %[[REINTERPRET_CAST_9:.*]] = memref.reinterpret_cast %[[LOOP_OF_BUFF_1]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> +// CHECK: func.call @some_work(%[[REINTERPRET_CAST_9]], %[[ARG1]]) : (memref<4x4xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Release, 1) +// CHECK: %[[C1_10:.*]] = arith.constant 1 : index +// CHECK: %[[VAL_0:.*]] = arith.muli %[[C1]], %[[C1_10]] : index +// CHECK: %[[VAL_1:.*]] = arith.addi %[[ARG1]], %[[VAL_0]] : index +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Acquire, 0) +// CHECK: %[[REINTERPRET_CAST_11:.*]] = memref.reinterpret_cast %[[LOOP_OF_BUFF_0]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> +// CHECK: func.call @some_work(%[[REINTERPRET_CAST_11]], %[[VAL_1]]) : (memref<4x4xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Release, 1) +// CHECK: } +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Acquire, 0) +// CHECK: %[[REINTERPRET_CAST_5:.*]] = memref.reinterpret_cast %[[LOOP_OF_BUFF_1]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> +// CHECK: func.call @some_work(%[[REINTERPRET_CAST_5]], %[[C0]]) : (memref<4x4xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Release, 1) +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Acquire, 0) +// CHECK: %[[REINTERPRET_CAST_6:.*]] = memref.reinterpret_cast %[[LOOP_OF_BUFF_0]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> +// CHECK: func.call @some_work(%[[REINTERPRET_CAST_6]], %[[C0]]) : (memref<4x4xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Release, 1) +// CHECK: %[[C2_7:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG1:.*]] = %[[C1]] to %[[C21]] step %[[C2_7]] { +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Acquire, 0) +// CHECK: %[[REINTERPRET_CAST_9:.*]] = memref.reinterpret_cast %[[LOOP_OF_BUFF_1]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> +// CHECK: func.call @some_work(%[[REINTERPRET_CAST_9]], %[[ARG1]]) : (memref<4x4xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Release, 1) +// CHECK: %[[C1_10:.*]] = arith.constant 1 : index +// CHECK: %[[VAL_2:.*]] = arith.muli %[[C1]], %[[C1_10]] : index +// CHECK: %[[VAL_3:.*]] = arith.addi %[[ARG1]], %[[VAL_2]] : index +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Acquire, 0) +// CHECK: %[[REINTERPRET_CAST_11:.*]] = memref.reinterpret_cast %[[LOOP_OF_BUFF_0]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> +// CHECK: func.call @some_work(%[[REINTERPRET_CAST_11]], %[[VAL_3]]) : (memref<4x4xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Release, 1) +// CHECK: } +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Acquire, 0) +// CHECK: %[[REINTERPRET_CAST_8:.*]] = memref.reinterpret_cast %[[LOOP_OF_BUFF_1]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> +// CHECK: func.call @some_work(%[[REINTERPRET_CAST_8]], %[[C0]]) : (memref<4x4xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Release, 1) +// CHECK: } +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Acquire, 0) +// CHECK: %[[REINTERPRET_CAST:.*]] = memref.reinterpret_cast %[[LOOP_OF_BUFF_0]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> +// CHECK: func.call @some_work(%[[REINTERPRET_CAST]], %[[C0]]) : (memref<4x4xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Release, 1) +// CHECK: %[[C2_1:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C1]] to %[[C21]] step %[[C2_1]] { +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Acquire, 0) +// CHECK: %[[REINTERPRET_CAST_3:.*]] = memref.reinterpret_cast %[[LOOP_OF_BUFF_1]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> +// CHECK: func.call @some_work(%[[REINTERPRET_CAST_3]], %[[ARG0]]) : (memref<4x4xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Release, 1) +// CHECK: %[[C1_4:.*]] = arith.constant 1 : index +// CHECK: %[[VAL_4:.*]] = arith.muli %[[C1]], %[[C1_4]] : index +// CHECK: %[[VAL_5:.*]] = arith.addi %[[ARG0]], %[[VAL_4]] : index +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Acquire, 0) +// CHECK: %[[REINTERPRET_CAST_5:.*]] = memref.reinterpret_cast %[[LOOP_OF_BUFF_0]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> +// CHECK: func.call @some_work(%[[REINTERPRET_CAST_5]], %[[VAL_5]]) : (memref<4x4xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_0]], Release, 1) +// CHECK: } +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Acquire, 0) +// CHECK: %[[REINTERPRET_CAST_2:.*]] = memref.reinterpret_cast %[[LOOP_OF_BUFF_1]] to offset: [0], sizes: [4, 4], strides: [4, 1] : memref<16xi32> to memref<4x4xi32> +// CHECK: func.call @some_work(%[[REINTERPRET_CAST_2]], %[[C0]]) : (memref<4x4xi32>, index) -> () +// CHECK: aie.use_lock(%[[LOOP_OF_LOCK_1]], Release, 1) +// CHECK: aie.end +// CHECK: } +// CHECK: } + module { aie.device(xcvc1902) { %tile12 = aie.tile(1, 2) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_buffer.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_buffer.mlir index 8b015932b..ac75b7513 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_buffer.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_buffer.mlir @@ -1,32 +1,22 @@ -//===- lower_buffer.mlir ---------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// +// RUN: iree-opt --aie-standard-lowering %s | FileCheck %s -// RUN: iree-opt --aie-standard-lowering="tilecol=3 tilerow=3" %s | FileCheck --check-prefixes=CHECKALL,CHECK33 %s -// RUN: iree-opt --aie-standard-lowering="tilecol=4 tilerow=3" %s | FileCheck --check-prefixes=CHECKALL,CHECK43 %s -// RUN: iree-opt --aie-standard-lowering %s | FileCheck --check-prefixes=CHECKALL,CHECK33,CHECK43 %s +// CHECK: memref.global "public" @a : memref<4xi32> +// CHECK-LABEL: func.func @core_4_3() { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[VAL_0:.*]] = memref.get_global @a : memref<4xi32> +// CHECK: memref.assume_alignment %[[VAL_0]], 32 : memref<4xi32> +// CHECK: %[[VAL_1:.*]] = memref.load %[[VAL_0]]{{\[}}%[[C0]]] : memref<4xi32> +// CHECK: return +// CHECK: } -// CHECKALL: memref.global "public" @a : memref<4xi32> -// CHECK43-LABEL: func.func @core_4_3() { -// CHECK43: %c0 = arith.constant 0 : index -// CHECK43: %0 = memref.get_global @a : memref<4xi32> -// CHECK43: %1 = memref.load %0[%c0] : memref<4xi32> -// CHECK43: return -// CHECK43: } - -// CHECK33-LABEL: func.func @core_3_3() { -// CHECK33: %c0 = arith.constant 0 : index -// CHECK33: %c377_i32 = arith.constant 377 : i32 -// CHECK33: %0 = memref.get_global @a : memref<4xi32> -// CHECK33: memref.store %c377_i32, %0[%c0] : memref<4xi32> -// CHECK33: return -// CHECK33: } +// CHECK-LABEL: func.func @core_3_3() { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C377_I32:.*]] = arith.constant 377 : i32 +// CHECK: %[[VAL_0:.*]] = memref.get_global @a : memref<4xi32> +// CHECK: memref.assume_alignment %[[VAL_0]], 32 : memref<4xi32> +// CHECK: memref.store %[[C377_I32]], %[[VAL_0]]{{\[}}%[[C0]]] : memref<4xi32> +// CHECK: return +// CHECK: } module @codegen1 { aie.device(xcvc1902) { @@ -43,7 +33,6 @@ module @codegen1 { %core34 = aie.core(%t34) { %0 = arith.constant 0 : index %1 = memref.load %a[%0] : memref<4xi32> -// aie.debug(%1 : i32) aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_buffer_and_lock.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_buffer_and_lock.mlir index 8eda0d3ff..ff3b8df19 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_buffer_and_lock.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_buffer_and_lock.mlir @@ -1,56 +1,53 @@ -//===- lower_buffer_and_lock.mlir ------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// +// RUN: iree-opt --aie-localize-locks --aie-standard-lowering %s | FileCheck %s -// RUN: iree-opt --aie-localize-locks --aie-standard-lowering="tilecol=1 tilerow=1" %s | FileCheck --check-prefix=CHECK11 %s -// RUN: iree-opt --aie-localize-locks --aie-standard-lowering="tilecol=1 tilerow=2" %s | FileCheck --check-prefix=CHECK12 %s +// CHECK-LABEL: memref.global "public" @a : memref<256xi32> +// CHECK: func.func private @debug_i32(i32) +// CHECK: func.func private @llvm.aie.event0() +// CHECK: func.func private @llvm.aie.event1() +// CHECK: func.func private @llvm.aie.put.ms(i32, i32) +// CHECK: func.func private @llvm.aie.put.wms(i32, i128) +// CHECK: func.func private @llvm.aie.put.fms(i32, f32) +// CHECK: func.func private @llvm.aie.get.ss(i32) -> i32 +// CHECK: func.func private @llvm.aie.get.wss(i32) -> i128 +// CHECK: func.func private @llvm.aie.get.fss(i32) -> f32 +// CHECK: func.func private @llvm.aie.put.mcd(i384) +// CHECK: func.func private @llvm.aie.get.scd() -> i384 +// CHECK: func.func private @llvm.aie.lock.acquire.reg(i32, i32) +// CHECK: func.func private @llvm.aie.lock.release.reg(i32, i32) + +// CHECK-LABEL: func.func @core_1_2() { +// CHECK: %[[C8:.*]] = arith.constant 8 : index +// CHECK: %[[VAL_0:.*]] = arith.index_cast %[[C8]] : index to i32 +// CHECK: %[[C1_I32:.*]] = arith.constant 1 : i32 +// CHECK: call @llvm.aie.lock.acquire.reg(%[[VAL_0]], %[[C1_I32]]) : (i32, i32) -> () +// CHECK: %[[C16:.*]] = arith.constant 16 : index +// CHECK: %[[VAL_1:.*]] = memref.get_global @a : memref<256xi32> +// CHECK: memref.assume_alignment %[[VAL_1]], 32 : memref<256xi32> +// CHECK: %[[VAL_2:.*]] = memref.load %[[VAL_1]]{{\[}}%[[C16]]] : memref<256xi32> +// CHECK: %[[VAL_3:.*]] = arith.index_cast %[[C8]] : index to i32 +// CHECK: %[[C0_I32:.*]] = arith.constant 0 : i32 +// CHECK: call @llvm.aie.lock.release.reg(%[[VAL_3]], %[[C0_I32]]) : (i32, i32) -> () +// CHECK: return +// CHECK: } + +// CHECK-LABEL: func.func @core_1_1() { +// CHECK: %[[C56:.*]] = arith.constant 56 : index +// CHECK: %[[VAL_0:.*]] = arith.index_cast %[[C56]] : index to i32 +// CHECK: %[[C0_I32:.*]] = arith.constant 0 : i32 +// CHECK: call @llvm.aie.lock.acquire.reg(%[[VAL_0]], %[[C0_I32]]) : (i32, i32) -> () +// CHECK: %[[C1_I32:.*]] = arith.constant 1 : i32 +// CHECK: %[[C16:.*]] = arith.constant 16 : index +// CHECK: %[[VAL_1:.*]] = memref.get_global @a : memref<256xi32> +// CHECK: memref.assume_alignment %[[VAL_1]], 32 : memref<256xi32> +// CHECK: memref.store %[[C1_I32]], %[[VAL_1]]{{\[}}%[[C16]]] : memref<256xi32> +// CHECK: %[[VAL_2:.*]] = arith.index_cast %[[C56]] : index to i32 +// CHECK: %[[C1_I32_0:.*]] = arith.constant 1 : i32 +// CHECK: call @llvm.aie.lock.release.reg(%[[VAL_2]], %[[C1_I32_0]]) : (i32, i32) -> () +// CHECK: return +// CHECK: } -// Test LLVM lowering for lock accesses and memory accesses (LockOp, UseLockOp, and BufferOp) -// Things to make sure: -// - LockID: depending on which tile (or memory module) a lock is instantiated, create a lock ID -// that has correct offset from a core's view (based on cardinal direction) -// - Buffer: depending on which tile (or memory module) a buffer is instantiated, create an LLVM -// static allocation (for now) for each core that can access to the buffer module @test_core_llvm1 { aie.device(xcvc1902) { -// CHECK11: memref.global "public" @a : memref<256xi32> -// CHECK11: func.func @core_1_1() { -// CHECK11: %c56 = arith.constant 56 : index -// CHECK11: %0 = arith.index_cast %c56 : index to i32 -// CHECK11: %c0_i32 = arith.constant 0 : i32 -// CHECK11: call @llvm.aie.lock.acquire.reg(%0, %c0_i32) : (i32, i32) -> () -// CHECK11: %c1_i32 = arith.constant 1 : i32 -// CHECK11: %c16 = arith.constant 16 : index -// CHECK11: %1 = memref.get_global @a : memref<256xi32> -// CHECK11: memref.assume_alignment %1, 32 : memref<256xi32> -// CHECK11: memref.store %c1_i32, %1[%c16] : memref<256xi32> -// CHECK11: %2 = arith.index_cast %c56 : index to i32 -// CHECK11: %c1_i32_0 = arith.constant 1 : i32 -// CHECK11: call @llvm.aie.lock.release.reg(%2, %c1_i32_0) : (i32, i32) -> () -// CHECK11: return -// CHECK11: } - -// CHECK12: memref.global "public" @a : memref<256xi32> -// CHECK12: func.func @core_1_2() { -// CHECK12: %c8 = arith.constant 8 : index -// CHECK12: %0 = arith.index_cast %c8 : index to i32 -// CHECK12: %c1_i32 = arith.constant 1 : i32 -// CHECK12: call @llvm.aie.lock.acquire.reg(%0, %c1_i32) : (i32, i32) -> () -// CHECK12: %c16 = arith.constant 16 : index -// CHECK12: %1 = memref.get_global @a : memref<256xi32> -// CHECK12: memref.assume_alignment %1, 32 : memref<256xi32> -// CHECK12: %2 = memref.load %1[%c16] : memref<256xi32> -// CHECK12: %3 = arith.index_cast %c8 : index to i32 -// CHECK12: %c0_i32 = arith.constant 0 : i32 -// CHECK12: call @llvm.aie.lock.release.reg(%3, %c0_i32) : (i32, i32) -> () -// CHECK12: return -// CHECK12: } %tile11 = aie.tile(1, 1) %tile12 = aie.tile(1, 2) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_dma.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_dma.mlir index 356c06676..c46b64ccf 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_dma.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_dma.mlir @@ -1,20 +1,36 @@ -//===- lower_dma.mlir ------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: iree-opt --aie-localize-locks --aie-standard-lowering="tilecol=3 tilerow=3" %s | FileCheck %s - -// CHECK: call @llvm.aie.lock.acquire.reg({{.*}}, %c0_i32) : (i32, i32) -> () -// CHECK: call @llvm.aie.put.ms(%c0_i32_0, %c16_i32) : (i32, i32) -> () -// CHECK: {{.*}} = call @llvm.aie.get.wss(%c0_i32_0) : (i32) -> i128 -// CHECK: call @llvm.aie.put.mcd(%c1_i384) : (i384) -> () -// CHECK: call @llvm.aie.lock.release.reg({{.*}}, %c1_i32) : (i32, i32) -> () +// RUN: iree-opt --aie-localize-locks --aie-standard-lowering %s | FileCheck %s + +// CHECK-LABEL: func.func @core_4_3() { +// CHECK: %[[C48:.*]] = arith.constant 48 : index +// CHECK: %[[C16:.*]] = arith.constant 16 : index +// CHECK: %[[C17:.*]] = arith.constant 17 : index +// CHECK: %[[VAL_0:.*]] = arith.index_cast %[[C48]] : index to i32 +// CHECK: %[[C1_I32:.*]] = arith.constant 1 : i32 +// CHECK: call @llvm.aie.lock.acquire.reg(%[[VAL_0]], %[[C1_I32]]) : (i32, i32) -> () +// CHECK: %[[VAL_1:.*]] = arith.index_cast %[[C48]] : index to i32 +// CHECK: %[[C0_I32:.*]] = arith.constant 0 : i32 +// CHECK: call @llvm.aie.lock.release.reg(%[[VAL_1]], %[[C0_I32]]) : (i32, i32) -> () +// CHECK: return +// CHECK: } + +// CHECK-LABEL: func.func @core_3_3() { +// CHECK: %[[C48:.*]] = arith.constant 48 : index +// CHECK: %[[C49:.*]] = arith.constant 49 : index +// CHECK: %[[VAL_0:.*]] = arith.index_cast %[[C48]] : index to i32 +// CHECK: %[[C0_I32:.*]] = arith.constant 0 : i32 +// CHECK: call @llvm.aie.lock.acquire.reg(%[[VAL_0]], %[[C0_I32]]) : (i32, i32) -> () +// CHECK: %[[C16_I32:.*]] = arith.constant 16 : i32 +// CHECK: %[[C0_I32_0:.*]] = arith.constant 0 : i32 +// CHECK: call @llvm.aie.put.ms(%[[C0_I32_0]], %[[C16_I32]]) : (i32, i32) -> () +// CHECK: %[[VAL_1:.*]] = call @llvm.aie.get.wss(%[[C0_I32_0]]) : (i32) -> i128 +// CHECK: %[[C1_I384:.*]] = arith.constant 1 : i384 +// CHECK: call @llvm.aie.put.mcd(%[[C1_I384]]) : (i384) -> () +// CHECK: %[[VAL_2:.*]] = arith.index_cast %[[C48]] : index to i32 +// CHECK: %[[C1_I32:.*]] = arith.constant 1 : i32 +// CHECK: call @llvm.aie.lock.release.reg(%[[VAL_2]], %[[C1_I32]]) : (i32, i32) -> () +// CHECK: return +// CHECK: } + module @example0 { aie.device(xcvc1902) { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_event.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_event.mlir index 2f0825075..d73165604 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_event.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_event.mlir @@ -1,17 +1,11 @@ -//===- lower_event.mlir ----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2023 Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - // RUN: iree-opt --aie-standard-lowering %s | FileCheck %s -// CHECK: call @llvm.aie.event0() -// CHECK: call @llvm.aie.event1() +// CHECK-LABEL: func.func @core_1_1() { +// CHECK: call @llvm.aie.event0() : () -> () +// CHECK: call @llvm.aie.event1() : () -> () +// CHECK: return +// CHECK: } + module @test { aie.device(xcvc1902) { %tile11 = aie.tile(1, 1) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_stream.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_stream.mlir index bea08ad93..f6cca50f0 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_stream.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/lower_stream.mlir @@ -1,40 +1,27 @@ -//===- lower_stream.mlir ---------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// +// RUN: iree-opt --aie-standard-lowering %s | FileCheck %s -// RUN: iree-opt --aie-standard-lowering="tilecol=1 tilerow=1" %s | FileCheck --check-prefix=CHECK11 %s -// RUN: iree-opt --aie-standard-lowering="tilecol=2 tilerow=1" %s | FileCheck --check-prefix=CHECK21 %s +// CHECK-LABEL: func.func @core_2_1() { +// CHECK: %[[C0_I32:.*]] = arith.constant 0 : i32 +// CHECK: %[[C1_I32:.*]] = arith.constant 1 : i32 +// CHECK: %[[VAL_0:.*]] = call @llvm.aie.get.ss(%[[C0_I32]]) : (i32) -> i32 +// CHECK: %[[VAL_1:.*]] = call @llvm.aie.get.ss(%[[C1_I32]]) : (i32) -> i32 +// CHECK: %[[VAL_2:.*]] = arith.addi %[[VAL_0]], %[[VAL_1]] : i32 +// CHECK: %[[VAL_3:.*]] = call @llvm.aie.get.scd() : () -> i384 +// CHECK: return +// CHECK: } -//CHECK11: func.func @core_1_1() { -//CHECK11: %c0_i32 = arith.constant 0 : i32 -//CHECK11: %c1_i32 = arith.constant 1 : i32 -//CHECK11: %c16_i32 = arith.constant 16 : i32 -//CHECK11: %c32_i128 = arith.constant 32 : i128 -//CHECK11: call @llvm.aie.put.ms(%c0_i32, %c16_i32) : (i32, i32) -> () -//CHECK11: call @llvm.aie.put.wms(%c1_i32, %c32_i128) : (i32, i128) -> () -//CHECK11: %c64_i384 = arith.constant 64 : i384 -//CHECK11: call @llvm.aie.put.mcd(%c64_i384) : (i384) -> () -//CHECK11: return -//CHECK11: } +// CHECK-LABEL: func.func @core_1_1() { +// CHECK: %[[C0_I32:.*]] = arith.constant 0 : i32 +// CHECK: %[[C1_I32:.*]] = arith.constant 1 : i32 +// CHECK: %[[C16_I32:.*]] = arith.constant 16 : i32 +// CHECK: %[[C32_I128:.*]] = arith.constant 32 : i128 +// CHECK: call @llvm.aie.put.ms(%[[C0_I32]], %[[C16_I32]]) : (i32, i32) -> () +// CHECK: call @llvm.aie.put.wms(%[[C1_I32]], %[[C32_I128]]) : (i32, i128) -> () +// CHECK: %[[C64_I384:.*]] = arith.constant 64 : i384 +// CHECK: call @llvm.aie.put.mcd(%[[C64_I384]]) : (i384) -> () +// CHECK: return +// CHECK: } -//CHECK21: func.func @core_2_1() { -//CHECK21: %c0_i32 = arith.constant 0 : i32 -//CHECK21: %c1_i32 = arith.constant 1 : i32 -//CHECK21: %0 = call @llvm.aie.get.ss(%c0_i32) : (i32) -> i32 -//CHECK21: %1 = call @llvm.aie.get.ss(%c1_i32) : (i32) -> i32 -//CHECK21: %2 = arith.addi %0, %1 : i32 -//CHECK21: %3 = call @llvm.aie.get.scd() : () -> i384 -//CHECK21: return -//CHECK21: } - -// Test LLVM lowering to some AIE scalar intrinsic functions (streams, cascades) -// Each core's region is lowered to LLVM Dialect module @test_core_llvm0 { aie.device(xcvc1902) { %tile11 = aie.tile(1, 1) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/matmul_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/matmul_test.mlir index dd4f40949..35386a828 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/matmul_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/matmul_test.mlir @@ -1,164 +1,155 @@ -//===- matmul_test.mlir -----------------------------------------*- MLIR -*-===// -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Date: September 5th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_2:.*]] = aie.lock(%[[VAL_0]], 4) {init = 0 : i32, sym_name = "outC_cons_prod_lock"} -// CHECK: %[[VAL_3:.*]] = aie.lock(%[[VAL_0]], 5) {init = 0 : i32, sym_name = "outC_cons_cons_lock"} -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "outC_buff_0"} : memref<16x16xi16> -// CHECK: %[[VAL_5:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "outC_buff_1"} : memref<16x16xi16> -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_1]], 4) {init = 2 : i32, sym_name = "outC_prod_lock"} -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_1]], 5) {init = 0 : i32, sym_name = "outC_cons_lock"} -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "inB_cons_buff_0"} : memref<8x16xi16> -// CHECK: %[[VAL_9:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "inB_cons_buff_1"} : memref<8x16xi16> -// CHECK: %[[VAL_10:.*]] = aie.lock(%[[VAL_1]], 2) {init = 2 : i32, sym_name = "inB_cons_prod_lock"} -// CHECK: %[[VAL_11:.*]] = aie.lock(%[[VAL_1]], 3) {init = 0 : i32, sym_name = "inB_cons_cons_lock"} -// CHECK: %[[VAL_12:.*]] = aie.lock(%[[VAL_0]], 2) {init = 0 : i32, sym_name = "inB_prod_lock"} -// CHECK: %[[VAL_13:.*]] = aie.lock(%[[VAL_0]], 3) {init = 0 : i32, sym_name = "inB_cons_lock"} -// CHECK: %[[VAL_14:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "inA_cons_buff_0"} : memref<16x8xi16> -// CHECK: %[[VAL_15:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "inA_cons_buff_1"} : memref<16x8xi16> -// CHECK: %[[VAL_16:.*]] = aie.lock(%[[VAL_1]], 0) {init = 2 : i32, sym_name = "inA_cons_prod_lock"} -// CHECK: %[[VAL_17:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "inA_cons_cons_lock"} -// CHECK: %[[VAL_18:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "inA_prod_lock"} -// CHECK: %[[VAL_19:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "inA_cons_lock"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: aie.flow(%[[VAL_0]], DMA : 1, %[[VAL_1]], DMA : 1) -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_0]], DMA : 0) -// CHECK: func.func @zero_scalar_i16(%[[VAL_20:.*]]: memref<16x16xi16>) { +// CHECK-LABEL: aie.device(xcve2302) { +// CHECK: memref.global "public" @outC_cons : memref<16x16xi16> +// CHECK: memref.global "public" @outC : memref<16x16xi16> +// CHECK: memref.global "public" @inB_cons : memref<8x16xi16> +// CHECK: memref.global "public" @inB : memref<8x16xi16> +// CHECK: memref.global "public" @inA_cons : memref<16x8xi16> +// CHECK: memref.global "public" @inA : memref<16x8xi16> +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[OUTC_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 4) {init = 0 : i32, sym_name = "outC_cons_prod_lock"} +// CHECK: %[[OUTC_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 5) {init = 0 : i32, sym_name = "outC_cons_cons_lock"} +// CHECK: %[[OUTC_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "outC_buff_0"} : memref<16x16xi16> +// CHECK: %[[OUTC_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "outC_buff_1"} : memref<16x16xi16> +// CHECK: %[[OUTC_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 4) {init = 2 : i32, sym_name = "outC_prod_lock"} +// CHECK: %[[OUTC_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 5) {init = 0 : i32, sym_name = "outC_cons_lock"} +// CHECK: %[[INB_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "inB_cons_buff_0"} : memref<8x16xi16> +// CHECK: %[[INB_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "inB_cons_buff_1"} : memref<8x16xi16> +// CHECK: %[[INB_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 2) {init = 2 : i32, sym_name = "inB_cons_prod_lock"} +// CHECK: %[[INB_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 3) {init = 0 : i32, sym_name = "inB_cons_cons_lock"} +// CHECK: %[[INB_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 2) {init = 0 : i32, sym_name = "inB_prod_lock"} +// CHECK: %[[INB_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 3) {init = 0 : i32, sym_name = "inB_cons_lock"} +// CHECK: %[[INA_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "inA_cons_buff_0"} : memref<16x8xi16> +// CHECK: %[[INA_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "inA_cons_buff_1"} : memref<16x8xi16> +// CHECK: %[[INA_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 0) {init = 2 : i32, sym_name = "inA_cons_prod_lock"} +// CHECK: %[[INA_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 1) {init = 0 : i32, sym_name = "inA_cons_cons_lock"} +// CHECK: %[[INA_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 0) {init = 0 : i32, sym_name = "inA_prod_lock"} +// CHECK: %[[INA_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_0]], 1) {init = 0 : i32, sym_name = "inA_cons_lock"} +// CHECK: aie.flow(%[[TILE_0_0]], DMA : 0, %[[TILE_0_2]], DMA : 0) +// CHECK: aie.flow(%[[TILE_0_0]], DMA : 1, %[[TILE_0_2]], DMA : 1) +// CHECK: aie.flow(%[[TILE_0_2]], DMA : 0, %[[TILE_0_0]], DMA : 0) +// CHECK: func.func @zero_scalar_i16(%[[ARG0:.*]]: memref<16x16xi16>) { // CHECK: return // CHECK: } -// CHECK: func.func @matmul_scalar_i16_i16(%[[VAL_21:.*]]: memref<16x8xi16>, %[[VAL_22:.*]]: memref<8x16xi16>, %[[VAL_23:.*]]: memref<16x16xi16>) { +// CHECK: func.func @matmul_scalar_i16_i16(%[[ARG0:.*]]: memref<16x8xi16>, %[[ARG1:.*]]: memref<8x16xi16>, %[[ARG2:.*]]: memref<16x16xi16>) { // CHECK: return // CHECK: } // CHECK: aie.shim_dma_allocation @inA(MM2S, 0, 0) -// CHECK: %[[VAL_24:.*]] = aie.core(%[[VAL_1]]) { -// CHECK: %[[VAL_25:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_26:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_27:.*]] = arith.constant 4 : index -// CHECK: %[[VAL_28:.*]] = arith.constant 4294967295 : index -// CHECK: scf.for %[[VAL_29:.*]] = %[[VAL_25]] to %[[VAL_28]] step %[[VAL_26]] { -// CHECK: %[[VAL_30:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[VAL_31:.*]] = %[[VAL_25]] to %[[VAL_27]] step %[[VAL_30]] { -// CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: func.call @zero_scalar_i16(%[[VAL_4]]) : (memref<16x16xi16>) -> () -// CHECK: %[[VAL_32:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[VAL_33:.*]] = %[[VAL_25]] to %[[VAL_27]] step %[[VAL_32]] { -// CHECK: aie.use_lock(%[[VAL_17]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 1) -// CHECK: func.call @matmul_scalar_i16_i16(%[[VAL_14]], %[[VAL_8]], %[[VAL_4]]) : (memref<16x8xi16>, memref<8x16xi16>, memref<16x16xi16>) -> () -// CHECK: aie.use_lock(%[[VAL_16]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_17]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 1) -// CHECK: func.call @matmul_scalar_i16_i16(%[[VAL_15]], %[[VAL_9]], %[[VAL_4]]) : (memref<16x8xi16>, memref<8x16xi16>, memref<16x16xi16>) -> () -// CHECK: aie.use_lock(%[[VAL_16]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 1) +// CHECK: %[[CORE_0_2:.*]] = aie.core(%[[TILE_0_2]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C4:.*]] = arith.constant 4 : index +// CHECK: %[[C4294967295:.*]] = arith.constant 4294967295 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C4294967295]] step %[[C1]] { +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG1:.*]] = %[[C0]] to %[[C4]] step %[[C2]] { +// CHECK: aie.use_lock(%[[OUTC_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: func.call @zero_scalar_i16(%[[OUTC_BUFF_0]]) : (memref<16x16xi16>) -> () +// CHECK: %[[C2_0:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG2:.*]] = %[[C0]] to %[[C4]] step %[[C2_0]] { +// CHECK: aie.use_lock(%[[INA_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.use_lock(%[[INB_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: func.call @matmul_scalar_i16_i16(%[[INA_CONS_BUFF_0]], %[[INB_CONS_BUFF_0]], %[[OUTC_BUFF_0]]) : (memref<16x8xi16>, memref<8x16xi16>, memref<16x16xi16>) -> () +// CHECK: aie.use_lock(%[[INA_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[INB_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[INA_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.use_lock(%[[INB_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: func.call @matmul_scalar_i16_i16(%[[INA_CONS_BUFF_1]], %[[INB_CONS_BUFF_1]], %[[OUTC_BUFF_0]]) : (memref<16x8xi16>, memref<8x16xi16>, memref<16x16xi16>) -> () +// CHECK: aie.use_lock(%[[INA_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[INB_CONS_PROD_LOCK]], Release, 1) // CHECK: } -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: func.call @zero_scalar_i16(%[[VAL_5]]) : (memref<16x16xi16>) -> () -// CHECK: %[[VAL_34:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[VAL_35:.*]] = %[[VAL_25]] to %[[VAL_27]] step %[[VAL_34]] { -// CHECK: aie.use_lock(%[[VAL_17]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 1) -// CHECK: func.call @matmul_scalar_i16_i16(%[[VAL_14]], %[[VAL_8]], %[[VAL_5]]) : (memref<16x8xi16>, memref<8x16xi16>, memref<16x16xi16>) -> () -// CHECK: aie.use_lock(%[[VAL_16]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_17]], AcquireGreaterEqual, 1) -// CHECK: aie.use_lock(%[[VAL_11]], AcquireGreaterEqual, 1) -// CHECK: func.call @matmul_scalar_i16_i16(%[[VAL_15]], %[[VAL_9]], %[[VAL_5]]) : (memref<16x8xi16>, memref<8x16xi16>, memref<16x16xi16>) -> () -// CHECK: aie.use_lock(%[[VAL_16]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_10]], Release, 1) +// CHECK: aie.use_lock(%[[OUTC_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[OUTC_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: func.call @zero_scalar_i16(%[[OUTC_BUFF_1]]) : (memref<16x16xi16>) -> () +// CHECK: %[[C2_1:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG2:.*]] = %[[C0]] to %[[C4]] step %[[C2_1]] { +// CHECK: aie.use_lock(%[[INA_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.use_lock(%[[INB_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: func.call @matmul_scalar_i16_i16(%[[INA_CONS_BUFF_0]], %[[INB_CONS_BUFF_0]], %[[OUTC_BUFF_1]]) : (memref<16x8xi16>, memref<8x16xi16>, memref<16x16xi16>) -> () +// CHECK: aie.use_lock(%[[INA_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[INB_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[INA_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.use_lock(%[[INB_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: func.call @matmul_scalar_i16_i16(%[[INA_CONS_BUFF_1]], %[[INB_CONS_BUFF_1]], %[[OUTC_BUFF_1]]) : (memref<16x8xi16>, memref<8x16xi16>, memref<16x16xi16>) -> () +// CHECK: aie.use_lock(%[[INA_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[INB_CONS_PROD_LOCK]], Release, 1) // CHECK: } -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: aie.use_lock(%[[OUTC_CONS_LOCK]], Release, 1) // CHECK: } // CHECK: } // CHECK: aie.end // CHECK: } // CHECK: aie.shim_dma_allocation @inB(MM2S, 1, 0) // CHECK: aie.shim_dma_allocation @outC(S2MM, 0, 0) -// CHECK: %[[VAL_36:.*]] = aie.mem(%[[VAL_1]]) { -// CHECK: %[[VAL_37:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_16]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_14]] : memref<16x8xi16>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_17]], Release, 1) +// CHECK: %[[MEM_0_2:.*]] = aie.mem(%[[TILE_0_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[INA_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[INA_CONS_BUFF_0]] : memref<16x8xi16>, 0, 128) +// CHECK: aie.use_lock(%[[INA_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_16]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_15]] : memref<16x8xi16>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_17]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[INA_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[INA_CONS_BUFF_1]] : memref<16x8xi16>, 0, 128) +// CHECK: aie.use_lock(%[[INA_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: %[[VAL_38:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb6) -// CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<8x16xi16>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: ^bb3: +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[INB_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[INB_CONS_BUFF_0]] : memref<8x16xi16>, 0, 128) +// CHECK: aie.use_lock(%[[INB_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb5 -// CHECK: ^bb5: // pred: ^bb4 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<8x16xi16>, 0, 128) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[INB_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[INB_CONS_BUFF_1]] : memref<8x16xi16>, 0, 128) +// CHECK: aie.use_lock(%[[INB_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb6: // pred: ^bb3 -// CHECK: %[[VAL_39:.*]] = aie.dma_start(MM2S, 0, ^bb7, ^bb9) -// CHECK: ^bb7: // 2 preds: ^bb6, ^bb8 -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16x16xi16>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) +// CHECK: ^bb6: +// CHECK: %[[VAL_2:.*]] = aie.dma_start(MM2S, 0, ^bb7, ^bb9) +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[OUTC_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OUTC_BUFF_0]] : memref<16x16xi16>, 0, 256) +// CHECK: aie.use_lock(%[[OUTC_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb8 -// CHECK: ^bb8: // pred: ^bb7 -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16x16xi16>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) +// CHECK: ^bb8: +// CHECK: aie.use_lock(%[[OUTC_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OUTC_BUFF_1]] : memref<16x16xi16>, 0, 256) +// CHECK: aie.use_lock(%[[OUTC_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb7 -// CHECK: ^bb9: // pred: ^bb6 +// CHECK: ^bb9: // CHECK: aie.end // CHECK: } +// CHECK: } module @matmul { aie.device(xcve2302) { - %t00 = aie.tile(0, 0) %t02 = aie.tile(0, 2) - aie.objectfifo @inA (%t00, { %t02 }, 2 : i32) : !aie.objectfifo> aie.objectfifo @inB (%t00, { %t02 }, 2 : i32) : !aie.objectfifo> aie.objectfifo @outC (%t02, { %t00 }, 2 : i32) : !aie.objectfifo> - func.func @zero_scalar_i16(%elem0 : memref<16x16xi16>) -> () { return } func.func @matmul_scalar_i16_i16(%elem0 : memref<16x8xi16>, %elem1 : memref<8x16xi16>, %elem2 : memref<16x16xi16>) -> () { return } - aie.core(%t02) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %c4 = arith.constant 4 : index %intmax = arith.constant 0xFFFFFFFF : index - scf.for %reps = %c0 to %intmax step %c1 { - scf.for %arg2 = %c0 to %c4 step %c1 { %subview2 = aie.objectfifo.acquire @outC (Produce, 1) : !aie.objectfifosubview> %elem2 = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref<16x16xi16> func.call @zero_scalar_i16(%elem2) : (memref<16x16xi16>) -> () - scf.for %arg3 = %c0 to %c4 step %c1 { %subview0 = aie.objectfifo.acquire @inA (Consume, 1) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref<16x8xi16> %subview1 = aie.objectfifo.acquire @inB (Consume, 1) : !aie.objectfifosubview> %elem1 = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref<8x16xi16> - func.call @matmul_scalar_i16_i16(%elem0, %elem1, %elem2) : (memref<16x8xi16>, memref<8x16xi16>, memref<16x16xi16>) -> () - aie.objectfifo.release @inA (Consume, 1) aie.objectfifo.release @inB (Consume, 1) } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/memTile_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/memTile_test.mlir index 1cfeafd51..c86482a82 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/memTile_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/memTile_test.mlir @@ -1,60 +1,48 @@ -//===- memTile_test.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Xilinx Inc. -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: May 9th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcve2302) { // CHECK: memref.global "public" @of_cons : memref<16xi32> // CHECK: memref.global "public" @of : memref<16xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "of_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "of_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 0) {init = 2 : i32, sym_name = "of_cons_prod_lock"} -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "of_cons_cons_lock"} -// CHECK: %[[VAL_6:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_7:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_0]], 0) {init = 2 : i32, sym_name = "of_prod_lock"} -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "of_cons_lock"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: %[[VAL_10:.*]] = aie.memtile_dma(%[[VAL_0]]) { -// CHECK: %[[VAL_11:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 1) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[OF_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OF_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of_cons_prod_lock"} +// CHECK: %[[OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of_cons_cons_lock"} +// CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "of_buff_0"} : memref<16xi32> +// CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_2_1]]) {sym_name = "of_buff_1"} : memref<16xi32> +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 2 : i32, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_1]], 1) {init = 0 : i32, sym_name = "of_cons_lock"} +// CHECK: aie.flow(%[[TILE_2_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) +// CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_12:.*]] = aie.mem(%[[VAL_1]]) { -// CHECK: %[[VAL_13:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_4]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_4]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } // CHECK: } @@ -63,7 +51,6 @@ module @memTile { aie.device(xcve2302) { %tile11 = aie.tile(2, 1) %tile12 = aie.tile(2, 2) - aie.objectfifo @of (%tile11, {%tile12}, 2 : i32) : !aie.objectfifo> } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_base_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_base_AIE2.mlir index 7e275d591..cf2890344 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_base_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_base_AIE2.mlir @@ -1,124 +1,111 @@ -//===- base_test_AIE2.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Xilinx Inc. -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: May 9th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK: module @ndDMAObjFifoAIE2 { -// CHECK: aie.device(xcve2302) { +// CHECK-LABEL: aie.device(xcve2302) { // CHECK: memref.global "public" @of1_cons : memref<256xi32> // CHECK: memref.global "public" @of1 : memref<256xi32> // CHECK: memref.global "public" @of0_cons : memref<256xi32> // CHECK: memref.global "public" @of0 : memref<256xi32> -// CHECK: %[[tile_1_2:.*]] = aie.tile(1, 2) -// CHECK: %[[tile_1_3:.*]] = aie.tile(1, 3) -// CHECK: %[[tile_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[of1_cons_buff_0:.*]] = aie.buffer(%[[tile_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<256xi32> -// CHECK: %[[of1_cons_buff_1:.*]] = aie.buffer(%[[tile_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<256xi32> -// CHECK: %[[of1_cons_prod_lock:.*]] = aie.lock(%[[tile_3_3]], 0) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[of1_cons_cons_lock:.*]] = aie.lock(%[[tile_3_3]], 1) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} -// CHECK: %[[of1_buff_0:.*]] = aie.buffer(%[[tile_1_2]]) {sym_name = "of1_buff_0"} : memref<256xi32> -// CHECK: %[[of1_buff_1:.*]] = aie.buffer(%[[tile_1_2]]) {sym_name = "of1_buff_1"} : memref<256xi32> -// CHECK: %[[of1_prod_lock:.*]] = aie.lock(%[[tile_1_2]], 2) {init = 2 : i32, sym_name = "of1_prod_lock"} -// CHECK: %[[of1_cons_lock:.*]] = aie.lock(%[[tile_1_2]], 3) {init = 0 : i32, sym_name = "of1_cons_lock"} -// CHECK: %[[of0_cons_buff_0:.*]] = aie.buffer(%[[tile_1_3]]) {sym_name = "of0_cons_buff_0"} : memref<256xi32> -// CHECK: %[[of0_cons_buff_1:.*]] = aie.buffer(%[[tile_1_3]]) {sym_name = "of0_cons_buff_1"} : memref<256xi32> -// CHECK: %[[of0_cons_buff_2:.*]] = aie.buffer(%[[tile_1_3]]) {sym_name = "of0_cons_buff_2"} : memref<256xi32> -// CHECK: %[[of0_cons_buff_3:.*]] = aie.buffer(%[[tile_1_3]]) {sym_name = "of0_cons_buff_3"} : memref<256xi32> -// CHECK: %[[of0_cons_prod_lock:.*]] = aie.lock(%[[tile_1_3]], 0) {init = 4 : i32, sym_name = "of0_cons_prod_lock"} -// CHECK: %[[of0_cons_cons_lock:.*]] = aie.lock(%[[tile_1_3]], 1) {init = 0 : i32, sym_name = "of0_cons_cons_lock"} -// CHECK: %[[of0_buff_0:.*]] = aie.buffer(%[[tile_1_2]]) {sym_name = "of0_buff_0"} : memref<256xi32> -// CHECK: %[[of0_buff_1:.*]] = aie.buffer(%[[tile_1_2]]) {sym_name = "of0_buff_1"} : memref<256xi32> -// CHECK: %[[of0_buff_2:.*]] = aie.buffer(%[[tile_1_2]]) {sym_name = "of0_buff_2"} : memref<256xi32> -// CHECK: %[[of0_buff_3:.*]] = aie.buffer(%[[tile_1_2]]) {sym_name = "of0_buff_3"} : memref<256xi32> -// CHECK: %[[of0_prod_lock:.*]] = aie.lock(%[[tile_1_2]], 0) {init = 4 : i32, sym_name = "of0_prod_lock"} -// CHECK: %[[of0_cons_lock:.*]] = aie.lock(%[[tile_1_2]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} -// CHECK: aie.flow(%[[tile_1_2]], DMA : 0, %[[tile_1_3]], DMA : 0) -// CHECK: aie.flow(%[[tile_1_2]], DMA : 1, %[[tile_3_3]], DMA : 0) -// CHECK: %[[VAL_23:.*]] = aie.mem(%[[tile_1_2]]) { -// CHECK: %[[VAL_26:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb5) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 -// CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_0]] : memref<256xi32>, 0, 256, [, , ]) -// CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<256xi32> +// CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<256xi32> +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_0"} : memref<256xi32> +// CHECK: %[[OF1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_1"} : memref<256xi32> +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i32, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "of1_cons_lock"} +// CHECK: %[[OF0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_cons_buff_0"} : memref<256xi32> +// CHECK: %[[OF0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_cons_buff_1"} : memref<256xi32> +// CHECK: %[[OF0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_cons_buff_2"} : memref<256xi32> +// CHECK: %[[OF0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_cons_buff_3"} : memref<256xi32> +// CHECK: %[[OF0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 4 : i32, sym_name = "of0_cons_prod_lock"} +// CHECK: %[[OF0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i32, sym_name = "of0_cons_cons_lock"} +// CHECK: %[[OF0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_0"} : memref<256xi32> +// CHECK: %[[OF0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_1"} : memref<256xi32> +// CHECK: %[[OF0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_2"} : memref<256xi32> +// CHECK: %[[OF0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_3"} : memref<256xi32> +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_1_3]], DMA : 0) +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 1, %[[TILE_3_3]], DMA : 0) +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb5) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_BUFF_0]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.use_lock(%[[OF0_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_1]] : memref<256xi32>, 0, 256, [, , ]) -// CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_BUFF_1]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.use_lock(%[[OF0_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_2]] : memref<256xi32>, 0, 256, [, , ]) -// CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[OF0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_BUFF_2]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.use_lock(%[[OF0_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb4: // pred: ^bb3 -// CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_3]] : memref<256xi32>, 0, 256, [, , ]) -// CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[OF0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_BUFF_3]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.use_lock(%[[OF0_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb5: // pred: ^bb0 -// CHECK: %[[VAL_27:.*]] = aie.dma_start(MM2S, 1, ^bb6, ^bb8) -// CHECK: ^bb6: // 2 preds: ^bb5, ^bb7 -// CHECK: aie.use_lock(%[[of1_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_buff_0]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of1_prod_lock]], Release, 1) +// CHECK: ^bb5: +// CHECK: %[[VAL_1:.*]] = aie.dma_start(MM2S, 1, ^bb6, ^bb8) +// CHECK: ^bb6: +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_BUFF_0]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF1_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb7 -// CHECK: ^bb7: // pred: ^bb6 -// CHECK: aie.use_lock(%[[of1_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_buff_1]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of1_prod_lock]], Release, 1) +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_BUFF_1]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF1_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb6 -// CHECK: ^bb8: // pred: ^bb5 +// CHECK: ^bb8: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.mem(%[[tile_1_3]]) { -// CHECK: %[[VAL_26:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 -// CHECK: aie.use_lock(%[[of0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buff_0]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of0_cons_cons_lock]], Release, 1) +// CHECK: %[[MEM_1_3:.*]] = aie.mem(%[[TILE_1_3]]) { +// CHECK: %[[VAL_2:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_CONS_BUFF_0]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[of0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buff_1]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of0_cons_cons_lock]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_CONS_BUFF_1]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[of0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buff_2]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of0_cons_cons_lock]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[OF0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_CONS_BUFF_2]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb4: // pred: ^bb3 -// CHECK: aie.use_lock(%[[of0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buff_3]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of0_cons_cons_lock]], Release, 1) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[OF0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_CONS_BUFF_3]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb5: // pred: ^bb0 +// CHECK: ^bb5: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_25:.*]] = aie.mem(%[[tile_3_3]]) { -// CHECK: %[[VAL_26:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[of1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_cons_buff_0]] : memref<256xi32>, 0, 256) -// CHECK: aie.use_lock(%[[of1_cons_cons_lock]], Release, 1) +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_0]] : memref<256xi32>, 0, 256) +// CHECK: aie.use_lock(%[[OF1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[of1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_cons_buff_1]] : memref<256xi32>, 0, 256) -// CHECK: aie.use_lock(%[[of1_cons_cons_lock]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_1]] : memref<256xi32>, 0, 256) +// CHECK: aie.use_lock(%[[OF1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } // CHECK: } @@ -128,14 +115,12 @@ module @ndDMAObjFifoAIE2 { %tile12 = aie.tile(1, 2) %tile13 = aie.tile(1, 3) %tile33 = aie.tile(3, 3) - // Even if an objectFifo could be implemented in shared memory, as with // this case between two adjacent tiles, we need to use DMAs if a data // layout transformation with toStream and fromStream was specified. aie.objectfifo @of0 (%tile12 toStream [, , ], // transpose {%tile13 fromStream []}, 4 : i32) : !aie.objectfifo> - aie.objectfifo @of1 (%tile12 toStream [], {%tile33}, 2 : i32) : !aie.objectfifo> } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_AIE2.mlir index 664fe428b..cf52624ab 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_AIE2.mlir @@ -1,116 +1,105 @@ -//===- nd_dma_distribute_AIE2.mlir -----------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s -// CHECK: module @ndDMAObjFifoAIE2 { -// CHECK: aie.device(xcve2302) { -// CHECK: memref.global "public" @of2_cons : memref<128xi32> -// CHECK: memref.global "public" @of2 : memref<128xi32> -// CHECK: memref.global "public" @of1_cons : memref<128xi32> -// CHECK: memref.global "public" @of1 : memref<128xi32> -// CHECK: memref.global "public" @of0_cons : memref<256xi32> -// CHECK: memref.global "public" @of0 : memref<256xi32> -// CHECK: %[[tile_1_0:.*]] = aie.tile(1, 0) -// CHECK: %[[tile_1_1:.*]] = aie.tile(1, 1) -// CHECK: %[[tile_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[tile_2_3:.*]] = aie.tile(2, 3) -// CHECK: %[[of2_cons_buf_0:.*]] = aie.buffer(%[[tile_2_3:.*]]) {sym_name = "of2_cons_buff_0"} : memref<128xi32> -// CHECK: %[[of2_cons_buf_1:.*]] = aie.buffer(%[[tile_2_3:.*]]) {sym_name = "of2_cons_buff_1"} : memref<128xi32> -// CHECK: %[[of2_cons_prod_lock:.*]] = aie.lock(%[[tile_2_3:.*]], 0) {init = 2 : i32, sym_name = "of2_cons_prod_lock"} -// CHECK: %[[of2_cons_cons_lock:.*]] = aie.lock(%[[tile_2_3:.*]], 1) {init = 0 : i32, sym_name = "of2_cons_cons_lock"} -// CHECK: %[[of1_cons_buf_0:.*]] = aie.buffer(%[[tile_2_2:.*]]) {sym_name = "of1_cons_buff_0"} : memref<128xi32> -// CHECK: %[[of1_cons_buf_1:.*]] = aie.buffer(%[[tile_2_2:.*]]) {sym_name = "of1_cons_buff_1"} : memref<128xi32> -// CHECK: %[[of1_cons_prod_lock:.*]] = aie.lock(%[[tile_2_2:.*]], 0) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[of1_cons_cons_lock:.*]] = aie.lock(%[[tile_2_2:.*]], 1) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} -// CHECK: %[[of0_cons_buf_0:.*]] = aie.buffer(%[[tile_1_1:.*]]) {sym_name = "of0_cons_buff_0"} : memref<256xi32> -// CHECK: %[[of0_cons_buf_1:.*]] = aie.buffer(%[[tile_1_1:.*]]) {sym_name = "of0_cons_buff_1"} : memref<256xi32> -// CHECK: %[[of0_cons_prod_lock:.*]] = aie.lock(%[[tile_1_1:.*]], 0) {init = 4 : i32, sym_name = "of0_cons_prod_lock"} -// CHECK: %[[of0_cons_cons_lock:.*]] = aie.lock(%[[tile_1_1:.*]], 1) {init = 0 : i32, sym_name = "of0_cons_cons_lock"} -// CHECK: %[[of0_prod_lock:.*]] = aie.lock(%[[tile_1_0:.*]], 0) {init = 0 : i32, sym_name = "of0_prod_lock"} -// CHECK: %[[of0_cons_lock:.*]] = aie.lock(%[[tile_1_0:.*]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} -// CHECK: aie.flow(%[[tile_1_0:.*]], DMA : 0, %[[tile_1_1:.*]], DMA : 0) -// CHECK: aie.flow(%[[tile_1_1:.*]], DMA : 0, %[[tile_2_2:.*]], DMA : 0) -// CHECK: aie.flow(%[[tile_1_1:.*]], DMA : 1, %[[tile_2_3:.*]], DMA : 0) -// CHECK: aie.shim_dma_allocation @of0(MM2S, 0, 1) -// CHECK: %18 = aie.memtile_dma(%[[tile_1_1:.*]]) { -// CHECK: %21 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[of0_cons_prod_lock:.*]], AcquireGreaterEqual, 2) -// CHECK: aie.dma_bd(%[[of0_cons_buf_0:.*]] : memref<256xi32>, 0, 256) -// CHECK: aie.use_lock(%[[of0_cons_cons_lock:.*]], Release, 2) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[of0_cons_prod_lock:.*]], AcquireGreaterEqual, 2) -// CHECK: aie.dma_bd(%[[of0_cons_buf_1:.*]] : memref<256xi32>, 0, 256) -// CHECK: aie.use_lock(%[[of0_cons_cons_lock:.*]], Release, 2) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: %22 = aie.dma_start(MM2S, 0, ^bb4, ^bb6) -// CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 -// CHECK: aie.use_lock(%[[of0_cons_cons_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buf_0:.*]] : memref<256xi32>, 0, 128, [, , , ]) -// CHECK: aie.use_lock(%[[of0_cons_prod_lock:.*]], Release, 1) -// CHECK: aie.next_bd ^bb5 -// CHECK: ^bb5: // pred: ^bb4 -// CHECK: aie.use_lock(%[[of0_cons_cons_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buf_1:.*]] : memref<256xi32>, 0, 128, [, , , ]) -// CHECK: aie.use_lock(%[[of0_cons_prod_lock:.*]], Release, 1) -// CHECK: aie.next_bd ^bb4 -// CHECK: ^bb6: // pred: ^bb3 -// CHECK: %23 = aie.dma_start(MM2S, 1, ^bb7, ^bb9) -// CHECK: ^bb7: // 2 preds: ^bb6, ^bb8 -// CHECK: aie.use_lock(%[[of0_cons_cons_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buf_0:.*]] : memref<256xi32>, 512, 128, [, , , ]) -// CHECK: aie.use_lock(%[[of0_cons_prod_lock:.*]], Release, 1) -// CHECK: aie.next_bd ^bb8 -// CHECK: ^bb8: // pred: ^bb7 -// CHECK: aie.use_lock(%[[of0_cons_cons_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_cons_buf_1:.*]] : memref<256xi32>, 512, 128, [, , , ]) -// CHECK: aie.use_lock(%[[of0_cons_prod_lock:.*]], Release, 1) -// CHECK: aie.next_bd ^bb7 -// CHECK: ^bb9: // pred: ^bb6 -// CHECK: aie.end -// CHECK: } -// CHECK: %19 = aie.mem(%[[tile_2_2:.*]]) { -// CHECK: %21 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[of1_cons_prod_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_cons_buf_0:.*]] : memref<128xi32>, 0, 128) -// CHECK: aie.use_lock(%[[of1_cons_cons_lock:.*]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[of1_cons_prod_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_cons_buf_1:.*]] : memref<128xi32>, 0, 128) -// CHECK: aie.use_lock(%[[of1_cons_cons_lock:.*]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: %20 = aie.mem(%[[tile_2_3:.*]]) { -// CHECK: %21 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[of2_cons_prod_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of2_cons_buf_0:.*]] : memref<128xi32>, 0, 128) -// CHECK: aie.use_lock(%[[of2_cons_cons_lock:.*]], Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[of2_cons_prod_lock:.*]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of2_cons_buf_1:.*]] : memref<128xi32>, 0, 128) -// CHECK: aie.use_lock(%[[of2_cons_cons_lock:.*]], Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: } -// CHECK: } +// CHECK-LABEL: aie.device(xcve2302) { +// CHECK: memref.global "public" @of2_cons : memref<128xi32> +// CHECK: memref.global "public" @of2 : memref<128xi32> +// CHECK: memref.global "public" @of1_cons : memref<128xi32> +// CHECK: memref.global "public" @of1 : memref<128xi32> +// CHECK: memref.global "public" @of0_cons : memref<256xi32> +// CHECK: memref.global "public" @of0 : memref<256xi32> +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[OF2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of2_cons_buff_0"} : memref<128xi32> +// CHECK: %[[OF2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of2_cons_buff_1"} : memref<128xi32> +// CHECK: %[[OF2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i32, sym_name = "of2_cons_prod_lock"} +// CHECK: %[[OF2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i32, sym_name = "of2_cons_cons_lock"} +// CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of1_cons_buff_0"} : memref<128xi32> +// CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of1_cons_buff_1"} : memref<128xi32> +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_1]]) {sym_name = "of0_cons_buff_0"} : memref<256xi32> +// CHECK: %[[OF0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_1]]) {sym_name = "of0_cons_buff_1"} : memref<256xi32> +// CHECK: %[[OF0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_1]], 0) {init = 4 : i32, sym_name = "of0_cons_prod_lock"} +// CHECK: %[[OF0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_1]], 1) {init = 0 : i32, sym_name = "of0_cons_cons_lock"} +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_0]], 0) {init = 0 : i32, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_0]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} +// CHECK: aie.flow(%[[TILE_1_0]], DMA : 0, %[[TILE_1_1]], DMA : 0) +// CHECK: aie.flow(%[[TILE_1_1]], DMA : 0, %[[TILE_2_2]], DMA : 0) +// CHECK: aie.flow(%[[TILE_1_1]], DMA : 1, %[[TILE_2_3]], DMA : 0) +// CHECK: aie.shim_dma_allocation @of0(MM2S, 0, 1) +// CHECK: %[[MEMTILE_DMA_1_1:.*]] = aie.memtile_dma(%[[TILE_1_1]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF0_CONS_PROD_LOCK]], AcquireGreaterEqual, 2) +// CHECK: aie.dma_bd(%[[OF0_CONS_BUFF_0]] : memref<256xi32>, 0, 256) +// CHECK: aie.use_lock(%[[OF0_CONS_CONS_LOCK]], Release, 2) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF0_CONS_PROD_LOCK]], AcquireGreaterEqual, 2) +// CHECK: aie.dma_bd(%[[OF0_CONS_BUFF_1]] : memref<256xi32>, 0, 256) +// CHECK: aie.use_lock(%[[OF0_CONS_CONS_LOCK]], Release, 2) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: %[[VAL_1:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[OF0_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_CONS_BUFF_0]] : memref<256xi32>, 0, 128, [, , , ]) +// CHECK: aie.use_lock(%[[OF0_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb5 +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[OF0_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_CONS_BUFF_1]] : memref<256xi32>, 0, 128, [, , , ]) +// CHECK: aie.use_lock(%[[OF0_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb4 +// CHECK: ^bb6: +// CHECK: %[[VAL_2:.*]] = aie.dma_start(MM2S, 1, ^bb7, ^bb9) +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[OF0_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_CONS_BUFF_0]] : memref<256xi32>, 128, 128, [, , , ]) +// CHECK: aie.use_lock(%[[OF0_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb8 +// CHECK: ^bb8: +// CHECK: aie.use_lock(%[[OF0_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_CONS_BUFF_1]] : memref<256xi32>, 128, 128, [, , , ]) +// CHECK: aie.use_lock(%[[OF0_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb7 +// CHECK: ^bb9: +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_0]] : memref<128xi32>, 0, 128) +// CHECK: aie.use_lock(%[[OF1_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_1]] : memref<128xi32>, 0, 128) +// CHECK: aie.use_lock(%[[OF1_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEM_2_3:.*]] = aie.mem(%[[TILE_2_3]]) { +// CHECK: %[[VAL_4:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF2_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF2_CONS_BUFF_0]] : memref<128xi32>, 0, 128) +// CHECK: aie.use_lock(%[[OF2_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF2_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF2_CONS_BUFF_1]] : memref<128xi32>, 0, 128) +// CHECK: aie.use_lock(%[[OF2_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: aie.end +// CHECK: } +// CHECK: } module @ndDMAObjFifoAIE2 { aie.device(xcve2302) { @@ -118,16 +107,13 @@ module @ndDMAObjFifoAIE2 { %tile11 = aie.tile(1, 1) %tile22 = aie.tile(2, 2) %tile23 = aie.tile(2, 3) - aie.objectfifo @of0 (%tile10, {%tile11}, 2 : i32) : !aie.objectfifo> - aie.objectfifo @of1 (%tile11 toStream [, , , ], {%tile22}, 2 : i32) : !aie.objectfifo> - aie.objectfifo @of2 (%tile11 toStream [, , , diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_AIE2_bad.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_AIE2_bad.mlir deleted file mode 100644 index 879181824..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_AIE2_bad.mlir +++ /dev/null @@ -1,38 +0,0 @@ -//===- nd_dma_distribute_AIE2_bad.mlir -------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: iree-opt --aie-objectFifo-stateful-transform --verify-diagnostics %s - -module @ndDMAObjFifoAIE2 { - aie.device(xcve2302) { - %tile10 = aie.tile(1, 0) - %tile11 = aie.tile(1, 1) - %tile22 = aie.tile(2, 2) - %tile23 = aie.tile(2, 3) - - aie.objectfifo @of0 (%tile10, {%tile11 fromStream [, - ]}, - 2 : i32) : !aie.objectfifo> - - aie.objectfifo @of1 (%tile11 toStream [, - , - , - ], - {%tile22}, 2 : i32) : !aie.objectfifo> - - aie.objectfifo @of2 (%tile11 toStream [, - , - , - ], - {%tile23}, 2 : i32) : !aie.objectfifo> - // expected-error@+1 {{'aie.objectfifo.link' op currently does not support objectFifos with dimensionsFromStreamPerConsumer.}} - aie.objectfifo.link [ @of0 ] -> [ @of1, @of2 ] () - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_broadcast_AIE2_bad.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_broadcast_AIE2_bad.mlir deleted file mode 100644 index da159c8da..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_distribute_broadcast_AIE2_bad.mlir +++ /dev/null @@ -1,38 +0,0 @@ -//===- nd_dma_distribute_broadcast_AIE2_bad.mlir ---------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: iree-opt --aie-objectFifo-stateful-transform --verify-diagnostics %s - -module @ndDMAObjFifoAIE2 { - aie.device(xcve2302) { - %tile10 = aie.tile(1, 0) - %tile11 = aie.tile(1, 1) - %tile12 = aie.tile(1, 2) - %tile22 = aie.tile(2, 2) - %tile13 = aie.tile(1, 3) - %tile23 = aie.tile(2, 3) - - aie.objectfifo @of0 (%tile10, {%tile11}, - 2 : i32) : !aie.objectfifo> - - aie.objectfifo @of1 (%tile11 toStream [, - , - , - ], - {%tile12, %tile22}, 2 : i32) : !aie.objectfifo> - - aie.objectfifo @of2 (%tile11 toStream [, - , - , - ], - {%tile13, %tile23}, 2 : i32) : !aie.objectfifo> - aie.objectfifo.link [ @of0 ] -> [ @of1, @of2 ] () - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_multiple_consumers_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_multiple_consumers_AIE2.mlir index 17edf6061..6d7050116 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_multiple_consumers_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nd_dma_multiple_consumers_AIE2.mlir @@ -1,194 +1,187 @@ -//===- base_test_AIE2.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Xilinx Inc. -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: May 9th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK: module @ndDMAObjFifoAIE2 { -// CHECK: aie.device(xcve2302) { -// CHECK: %[[tile_1_2:.*]] = aie.tile(1, 2) -// CHECK: %[[tile_1_3:.*]] = aie.tile(1, 3) -// CHECK: %[[tile_3_3:.*]] = aie.tile(3, 3) -// CHECK: %[[tile_2_2:.*]] = aie.tile(2, 2) -// CHECK: %[[tile_2_3:.*]] = aie.tile(2, 3) -// CHECK: %[[of3_cons_buff_0:.*]] = aie.buffer(%[[tile_2_3]]) {sym_name = "of3_cons_buff_0"} : memref<256xi32> -// CHECK: %[[of3_cons_buff_1:.*]] = aie.buffer(%[[tile_2_3]]) {sym_name = "of3_cons_buff_1"} : memref<256xi32> -// CHECK: %[[of3_cons_prod_lock:.*]] = aie.lock(%[[tile_2_3]], 0) {init = 2 : i32, sym_name = "of3_cons_prod_lock"} -// CHECK: %[[of3_cons_cons_lock:.*]] = aie.lock(%[[tile_2_3]], 1) {init = 0 : i32, sym_name = "of3_cons_cons_lock"} -// CHECK: %[[of3_buff_0:.*]] = aie.buffer(%[[tile_2_2]]) {sym_name = "of3_buff_0"} : memref<256xi32> -// CHECK: %[[of3_buff_1:.*]] = aie.buffer(%[[tile_2_2]]) {sym_name = "of3_buff_1"} : memref<256xi32> -// CHECK: %[[of3_prod_lock:.*]] = aie.lock(%[[tile_2_2]], 0) {init = 2 : i32, sym_name = "of3_prod_lock"} -// CHECK: %[[of3_cons_lock:.*]] = aie.lock(%[[tile_2_2]], 1) {init = 0 : i32, sym_name = "of3_cons_lock"} -// CHECK: %[[of1_cons_buff_0:.*]] = aie.buffer(%[[tile_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<256xi32> -// CHECK: %[[of1_cons_buff_1:.*]] = aie.buffer(%[[tile_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<256xi32> -// CHECK: %[[of1_cons_prod_lock:.*]] = aie.lock(%[[tile_3_3]], 2) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} -// CHECK: %[[of1_cons_cons_lock:.*]] = aie.lock(%[[tile_3_3]], 3) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} -// CHECK: %[[of1_buff_0:.*]] = aie.buffer(%[[tile_1_2]]) {sym_name = "of1_buff_0"} : memref<256xi32> -// CHECK: %[[of1_buff_1:.*]] = aie.buffer(%[[tile_1_2]]) {sym_name = "of1_buff_1"} : memref<256xi32> -// CHECK: %[[of1_prod_lock:.*]] = aie.lock(%[[tile_1_2]], 2) {init = 2 : i32, sym_name = "of1_prod_lock"} -// CHECK: %[[of1_cons_lock:.*]] = aie.lock(%[[tile_1_2]], 3) {init = 0 : i32, sym_name = "of1_cons_lock"} -// CHECK: %[[of0_0_cons_buff_0:.*]] = aie.buffer(%[[tile_1_3]]) {sym_name = "of0_0_cons_buff_0"} : memref<256xi32> -// CHECK: %[[of0_0_cons_buff_1:.*]] = aie.buffer(%[[tile_1_3]]) {sym_name = "of0_0_cons_buff_1"} : memref<256xi32> -// CHECK: %[[of0_0_cons_buff_2:.*]] = aie.buffer(%[[tile_1_3]]) {sym_name = "of0_0_cons_buff_2"} : memref<256xi32> -// CHECK: %[[of0_0_cons_buff_3:.*]] = aie.buffer(%[[tile_1_3]]) {sym_name = "of0_0_cons_buff_3"} : memref<256xi32> -// CHECK: %[[of0_0_cons_prod_lock:.*]] = aie.lock(%[[tile_1_3]], 0) {init = 4 : i32, sym_name = "of0_0_cons_prod_lock"} -// CHECK: %[[of0_0_cons_cons_lock:.*]] = aie.lock(%[[tile_1_3]], 1) {init = 0 : i32, sym_name = "of0_0_cons_cons_lock"} -// CHECK: %[[of0_1_cons_buff_0:.*]] = aie.buffer(%[[tile_3_3]]) {sym_name = "of0_1_cons_buff_0"} : memref<256xi32> -// CHECK: %[[of0_1_cons_buff_1:.*]] = aie.buffer(%[[tile_3_3]]) {sym_name = "of0_1_cons_buff_1"} : memref<256xi32> -// CHECK: %[[of0_1_cons_buff_2:.*]] = aie.buffer(%[[tile_3_3]]) {sym_name = "of0_1_cons_buff_2"} : memref<256xi32> -// CHECK: %[[of0_1_cons_buff_3:.*]] = aie.buffer(%[[tile_3_3]]) {sym_name = "of0_1_cons_buff_3"} : memref<256xi32> -// CHECK: %[[of0_1_cons_prod_lock:.*]] = aie.lock(%[[tile_3_3]], 0) {init = 4 : i32, sym_name = "of0_1_cons_prod_lock"} -// CHECK: %[[of0_1_cons_cons_lock:.*]] = aie.lock(%[[tile_3_3]], 1) {init = 0 : i32, sym_name = "of0_1_cons_cons_lock"} -// CHECK: %[[of0_buff_0:.*]] = aie.buffer(%[[tile_1_2]]) {sym_name = "of0_buff_0"} : memref<256xi32> -// CHECK: %[[of0_buff_1:.*]] = aie.buffer(%[[tile_1_2]]) {sym_name = "of0_buff_1"} : memref<256xi32> -// CHECK: %[[of0_buff_2:.*]] = aie.buffer(%[[tile_1_2]]) {sym_name = "of0_buff_2"} : memref<256xi32> -// CHECK: %[[of0_buff_3:.*]] = aie.buffer(%[[tile_1_2]]) {sym_name = "of0_buff_3"} : memref<256xi32> -// CHECK: %[[of0_prod_lock:.*]] = aie.lock(%[[tile_1_2]], 0) {init = 4 : i32, sym_name = "of0_prod_lock"} -// CHECK: %[[of0_cons_lock:.*]] = aie.lock(%[[tile_1_2]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} -// CHECK: aie.flow(%[[tile_1_2]], DMA : 0, %[[tile_3_3]], DMA : 0) -// CHECK: aie.flow(%[[tile_1_2]], DMA : 0, %[[tile_1_3]], DMA : 0) -// CHECK: aie.flow(%[[tile_1_2]], DMA : 1, %[[tile_3_3]], DMA : 1) -// CHECK: aie.flow(%[[tile_2_2]], DMA : 0, %[[tile_2_3]], DMA : 0) -// CHECK: %[[VAL_39:.*]] = aie.mem(%[[tile_1_2]]) { -// CHECK: %[[VAL_44:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb5) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 -// CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_0]] : memref<256xi32>, 0, 256, [, , ]) -// CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) +// CHECK-LABEL: aie.device(xcve2302) { +// CHECK: memref.global "public" @of3_cons : memref<256xi32> +// CHECK: memref.global "public" @of3 : memref<256xi32> +// CHECK: memref.global "public" @of1_cons : memref<256xi32> +// CHECK: memref.global "public" @of1 : memref<256xi32> +// CHECK: memref.global "public" @of0_0_cons : memref<256xi32> +// CHECK: memref.global "public" @of0_1_cons : memref<256xi32> +// CHECK: memref.global "public" @of0 : memref<256xi32> +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[OF3_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of3_cons_buff_0"} : memref<256xi32> +// CHECK: %[[OF3_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of3_cons_buff_1"} : memref<256xi32> +// CHECK: %[[OF3_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i32, sym_name = "of3_cons_prod_lock"} +// CHECK: %[[OF3_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i32, sym_name = "of3_cons_cons_lock"} +// CHECK: %[[OF3_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of3_buff_0"} : memref<256xi32> +// CHECK: %[[OF3_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of3_buff_1"} : memref<256xi32> +// CHECK: %[[OF3_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of3_prod_lock"} +// CHECK: %[[OF3_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of3_cons_lock"} +// CHECK: %[[OF1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_0"} : memref<256xi32> +// CHECK: %[[OF1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of1_cons_buff_1"} : memref<256xi32> +// CHECK: %[[OF1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 2) {init = 2 : i32, sym_name = "of1_cons_prod_lock"} +// CHECK: %[[OF1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 3) {init = 0 : i32, sym_name = "of1_cons_cons_lock"} +// CHECK: %[[OF1_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_0"} : memref<256xi32> +// CHECK: %[[OF1_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of1_buff_1"} : memref<256xi32> +// CHECK: %[[OF1_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i32, sym_name = "of1_prod_lock"} +// CHECK: %[[OF1_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "of1_cons_lock"} +// CHECK: %[[OF0_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_0_cons_buff_0"} : memref<256xi32> +// CHECK: %[[OF0_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_0_cons_buff_1"} : memref<256xi32> +// CHECK: %[[OF0_0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_0_cons_buff_2"} : memref<256xi32> +// CHECK: %[[OF0_0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of0_0_cons_buff_3"} : memref<256xi32> +// CHECK: %[[OF0_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 4 : i32, sym_name = "of0_0_cons_prod_lock"} +// CHECK: %[[OF0_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i32, sym_name = "of0_0_cons_cons_lock"} +// CHECK: %[[OF0_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of0_1_cons_buff_0"} : memref<256xi32> +// CHECK: %[[OF0_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of0_1_cons_buff_1"} : memref<256xi32> +// CHECK: %[[OF0_1_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of0_1_cons_buff_2"} : memref<256xi32> +// CHECK: %[[OF0_1_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of0_1_cons_buff_3"} : memref<256xi32> +// CHECK: %[[OF0_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 4 : i32, sym_name = "of0_1_cons_prod_lock"} +// CHECK: %[[OF0_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "of0_1_cons_cons_lock"} +// CHECK: %[[OF0_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_0"} : memref<256xi32> +// CHECK: %[[OF0_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_1"} : memref<256xi32> +// CHECK: %[[OF0_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_2"} : memref<256xi32> +// CHECK: %[[OF0_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of0_buff_3"} : memref<256xi32> +// CHECK: %[[OF0_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 4 : i32, sym_name = "of0_prod_lock"} +// CHECK: %[[OF0_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of0_cons_lock"} +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_1_3]], DMA : 0) +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 1, %[[TILE_3_3]], DMA : 1) +// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_3]], DMA : 0) +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb5) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_BUFF_0]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.use_lock(%[[OF0_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_1]] : memref<256xi32>, 0, 256, [, , ]) -// CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_BUFF_1]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.use_lock(%[[OF0_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_2]] : memref<256xi32>, 0, 256, [, , ]) -// CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[OF0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_BUFF_2]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.use_lock(%[[OF0_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb4: // pred: ^bb3 -// CHECK: aie.use_lock(%[[of0_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_buff_3]] : memref<256xi32>, 0, 256, [, , ]) -// CHECK: aie.use_lock(%[[of0_prod_lock]], Release, 1) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[OF0_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_BUFF_3]] : memref<256xi32>, 0, 256, [, , ]) +// CHECK: aie.use_lock(%[[OF0_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb5: // pred: ^bb0 -// CHECK: %[[VAL_45:.*]] = aie.dma_start(MM2S, 1, ^bb6, ^bb8) -// CHECK: ^bb6: // 2 preds: ^bb5, ^bb7 -// CHECK: aie.use_lock(%[[of1_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_buff_0]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of1_prod_lock]], Release, 1) +// CHECK: ^bb5: +// CHECK: %[[VAL_1:.*]] = aie.dma_start(MM2S, 1, ^bb6, ^bb8) +// CHECK: ^bb6: +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_BUFF_0]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF1_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb7 -// CHECK: ^bb7: // pred: ^bb6 -// CHECK: aie.use_lock(%[[of1_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_buff_1]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of1_prod_lock]], Release, 1) +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[OF1_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_BUFF_1]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF1_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb6 -// CHECK: ^bb8: // pred: ^bb5 +// CHECK: ^bb8: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_40:.*]] = aie.mem(%[[tile_1_3]]) { -// CHECK: %[[VAL_44:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 -// CHECK: aie.use_lock(%[[of0_0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_0_cons_buff_0]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of0_0_cons_cons_lock]], Release, 1) +// CHECK: %[[MEM_1_3:.*]] = aie.mem(%[[TILE_1_3]]) { +// CHECK: %[[VAL_2:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF0_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_0_CONS_BUFF_0]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF0_0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[of0_0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_0_cons_buff_1]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of0_0_cons_cons_lock]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF0_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_0_CONS_BUFF_1]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF0_0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[of0_0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_0_cons_buff_2]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of0_0_cons_cons_lock]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[OF0_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_0_CONS_BUFF_2]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF0_0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb4: // pred: ^bb3 -// CHECK: aie.use_lock(%[[of0_0_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_0_cons_buff_3]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of0_0_cons_cons_lock]], Release, 1) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[OF0_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_0_CONS_BUFF_3]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF0_0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb5: // pred: ^bb0 +// CHECK: ^bb5: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.mem(%[[tile_3_3]]) { -// CHECK: %[[VAL_44:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 -// CHECK: aie.use_lock(%[[of0_1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_1_cons_buff_0]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of0_1_cons_cons_lock]], Release, 1) +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF0_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_1_CONS_BUFF_0]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF0_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[of0_1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_1_cons_buff_1]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of0_1_cons_cons_lock]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF0_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_1_CONS_BUFF_1]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF0_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[of0_1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_1_cons_buff_2]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of0_1_cons_cons_lock]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[OF0_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_1_CONS_BUFF_2]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF0_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb4: // pred: ^bb3 -// CHECK: aie.use_lock(%[[of0_1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of0_1_cons_buff_3]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of0_1_cons_cons_lock]], Release, 1) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[OF0_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF0_1_CONS_BUFF_3]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF0_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb5: // pred: ^bb0 -// CHECK: %[[VAL_45:.*]] = aie.dma_start(S2MM, 1, ^bb6, ^bb8) -// CHECK: ^bb6: // 2 preds: ^bb5, ^bb7 -// CHECK: aie.use_lock(%[[of1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_cons_buff_0]] : memref<256xi32>, 0, 256) -// CHECK: aie.use_lock(%[[of1_cons_cons_lock]], Release, 1) +// CHECK: ^bb5: +// CHECK: %[[VAL_4:.*]] = aie.dma_start(S2MM, 1, ^bb6, ^bb8) +// CHECK: ^bb6: +// CHECK: aie.use_lock(%[[OF1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_0]] : memref<256xi32>, 0, 256) +// CHECK: aie.use_lock(%[[OF1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb7 -// CHECK: ^bb7: // pred: ^bb6 -// CHECK: aie.use_lock(%[[of1_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of1_cons_buff_1]] : memref<256xi32>, 0, 256) -// CHECK: aie.use_lock(%[[of1_cons_cons_lock]], Release, 1) +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[OF1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF1_CONS_BUFF_1]] : memref<256xi32>, 0, 256) +// CHECK: aie.use_lock(%[[OF1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb6 -// CHECK: ^bb8: // pred: ^bb5 +// CHECK: ^bb8: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_42:.*]] = aie.mem(%[[tile_2_2]]) { -// CHECK: %[[VAL_44:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[of3_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of3_buff_0]] : memref<256xi32>, 0, 256) -// CHECK: aie.use_lock(%[[of3_prod_lock]], Release, 1) +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_5:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF3_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF3_BUFF_0]] : memref<256xi32>, 0, 256) +// CHECK: aie.use_lock(%[[OF3_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[of3_cons_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of3_buff_1]] : memref<256xi32>, 0, 256) -// CHECK: aie.use_lock(%[[of3_prod_lock]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF3_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF3_BUFF_1]] : memref<256xi32>, 0, 256) +// CHECK: aie.use_lock(%[[OF3_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_43:.*]] = aie.mem(%[[tile_2_3]]) { -// CHECK: %[[VAL_44:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[of3_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of3_cons_buff_0]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of3_cons_cons_lock]], Release, 1) +// CHECK: %[[MEM_2_3:.*]] = aie.mem(%[[TILE_2_3]]) { +// CHECK: %[[VAL_6:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF3_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF3_CONS_BUFF_0]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF3_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[of3_cons_prod_lock]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[of3_cons_buff_1]] : memref<256xi32>, 0, 256, []) -// CHECK: aie.use_lock(%[[of3_cons_cons_lock]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF3_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF3_CONS_BUFF_1]] : memref<256xi32>, 0, 256, []) +// CHECK: aie.use_lock(%[[OF3_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } // CHECK: } -// CHECK: } module @ndDMAObjFifoAIE2 { aie.device(xcve2302) { @@ -197,15 +190,12 @@ module @ndDMAObjFifoAIE2 { %tile33 = aie.tile(3, 3) %tile22 = aie.tile(2, 2) %tile23 = aie.tile(2, 3) - aie.objectfifo @of0 (%tile12 toStream [, , ], // transpose {%tile13 fromStream [], %tile33 fromStream []}, 4 : i32) : !aie.objectfifo> - aie.objectfifo @of1 (%tile12 toStream [], {%tile33}, 2 : i32) : !aie.objectfifo> - aie.objectfifo @of3 (%tile22, {%tile23 fromStream []}, 2 : i32) : !aie.objectfifo> } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nested_loop_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nested_loop_test.mlir index 10bd99366..c1b492839 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/nested_loop_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/nested_loop_test.mlir @@ -1,78 +1,255 @@ -//===- nested_loop_test.mlir -----------------------------------------*- MLIR -*-===// -// -// Copyright (C) 2024, Advanced Micro Devices, Inc. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Date: April 3rd 2024 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK-LABEL: aie.device(npu1_4col) -// CHECK: scf.for -// CHECK: { -// CHECK: aie.use_lock -// CHECK: memref.reinterpret_cast -// CHECK: aie.use_lock -// CHECK: memref.reinterpret_cast -// CHECK: scf.for -// CHECK: { -// CHECK: scf.for -// CHECK: { -// CHECK: scf.for -// CHECK: { -// CHECK: scf.for -// CHECK: { -// CHECK: scf.for -// CHECK: { -// CHECK: scf.for -// CHECK: { -// CHECK: memref.load -// CHECK: memref.load -// CHECK: memref.load -// CHECK: arith.muli -// CHECK: arith.addi -// CHECK: memref.store -// CHECK: } -// CHECK: } -// CHECK: } -// CHECK: } -// CHECK: } -// CHECK: } -// CHECK: aie.use_lock -// CHECK: aie.use_lock -// CHECK: aie.use_lock -// CHECK: memref.reinterpret_cast -// CHECK: aie.use_lock -// CHECK: memref.reinterpret_cast -// CHECK: scf.for -// CHECK: { -// CHECK: scf.for -// CHECK: { -// CHECK: scf.for -// CHECK: { -// CHECK: scf.for -// CHECK: { -// CHECK: scf.for -// CHECK: { -// CHECK: scf.for -// CHECK: { -// CHECK: memref.load -// CHECK: memref.load -// CHECK: memref.load -// CHECK: arith.muli -// CHECK: arith.addi -// CHECK: memref.store -// CHECK: } -// CHECK: } -// CHECK: } -// CHECK: } -// CHECK: } -// CHECK: } -// CHECK: aie.use_lock -// CHECK: aie.use_lock -// CHECK: } +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: memref.global "public" @in8_cons : memref<32x32xi32, 1> +// CHECK: memref.global "public" @in8 : memref<32x32xi32, 1> +// CHECK: memref.global "public" @in7_cons : memref<64x32xi32, 1> +// CHECK: memref.global "public" @in7 : memref<64x32xi32, 1> +// CHECK: memref.global "public" @in2_0_cons : memref<32x64xi32, 1> +// CHECK: memref.global "public" @in2_1_cons : memref<32x64xi32, 1> +// CHECK: memref.global "public" @in2 : memref<32x64xi32, 1> +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[IN8_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in8_cons_buff_0"} : memref<32x32xi32, 1> +// CHECK: %[[IN8_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in8_cons_buff_1"} : memref<32x32xi32, 1> +// CHECK: %[[IN8_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in8_cons_buff_2"} : memref<32x32xi32, 1> +// CHECK: %[[IN8_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in8_cons_buff_3"} : memref<32x32xi32, 1> +// CHECK: %[[IN8_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 4) {init = 4 : i32, sym_name = "in8_cons_prod_lock"} +// CHECK: %[[IN8_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 5) {init = 0 : i32, sym_name = "in8_cons_cons_lock"} +// CHECK: %[[IN8_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in8_buff_0"} : memref<32x32xi32, 1> +// CHECK: %[[IN8_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in8_buff_1"} : memref<32x32xi32, 1> +// CHECK: %[[IN8_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 4) {init = 2 : i32, sym_name = "in8_prod_lock"} +// CHECK: %[[IN8_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 5) {init = 0 : i32, sym_name = "in8_cons_lock"} +// CHECK: %[[IN7_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in7_cons_buff_0"} : memref<64x32xi32, 1> +// CHECK: %[[IN7_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in7_cons_buff_1"} : memref<64x32xi32, 1> +// CHECK: %[[IN7_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i32, sym_name = "in7_cons_prod_lock"} +// CHECK: %[[IN7_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "in7_cons_cons_lock"} +// CHECK: %[[IN7_BUFF_0:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in7_buff_0"} : memref<64x32xi32, 1> +// CHECK: %[[IN7_BUFF_1:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in7_buff_1"} : memref<64x32xi32, 1> +// CHECK: %[[IN7_BUFF_2:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in7_buff_2"} : memref<64x32xi32, 1> +// CHECK: %[[IN7_BUFF_3:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in7_buff_3"} : memref<64x32xi32, 1> +// CHECK: %[[IN7_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 2) {init = 4 : i32, sym_name = "in7_prod_lock"} +// CHECK: %[[IN7_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 3) {init = 0 : i32, sym_name = "in7_cons_lock"} +// CHECK: %[[IN2_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "in2_0_cons_buff_0"} : memref<32x64xi32, 1> +// CHECK: %[[IN2_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "in2_0_cons_buff_1"} : memref<32x64xi32, 1> +// CHECK: %[[IN2_0_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "in2_0_cons_buff_2"} : memref<32x64xi32, 1> +// CHECK: %[[IN2_0_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "in2_0_cons_buff_3"} : memref<32x64xi32, 1> +// CHECK: %[[IN2_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 0) {init = 4 : i32, sym_name = "in2_0_cons_prod_lock"} +// CHECK: %[[IN2_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_2]], 1) {init = 0 : i32, sym_name = "in2_0_cons_cons_lock"} +// CHECK: %[[IN2_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in2_1_cons_buff_0"} : memref<32x64xi32, 1> +// CHECK: %[[IN2_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "in2_1_cons_buff_1"} : memref<32x64xi32, 1> +// CHECK: %[[IN2_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i32, sym_name = "in2_1_cons_prod_lock"} +// CHECK: %[[IN2_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "in2_1_cons_cons_lock"} +// CHECK: %[[IN2_BUFF_0:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in2_buff_0"} : memref<32x64xi32, 1> +// CHECK: %[[IN2_BUFF_1:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in2_buff_1"} : memref<32x64xi32, 1> +// CHECK: %[[IN2_BUFF_2:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in2_buff_2"} : memref<32x64xi32, 1> +// CHECK: %[[IN2_BUFF_3:.*]] = aie.buffer(%[[TILE_0_1]]) {sym_name = "in2_buff_3"} : memref<32x64xi32, 1> +// CHECK: %[[IN2_PROD_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 0) {init = 4 : i32, sym_name = "in2_prod_lock"} +// CHECK: %[[IN2_CONS_LOCK:.*]] = aie.lock(%[[TILE_0_1]], 1) {init = 0 : i32, sym_name = "in2_cons_lock"} +// CHECK: aie.flow(%[[TILE_0_1]], DMA : 0, %[[TILE_1_2]], DMA : 0) +// CHECK: aie.flow(%[[TILE_0_1]], DMA : 0, %[[TILE_0_2]], DMA : 0) +// CHECK: aie.flow(%[[TILE_0_1]], DMA : 1, %[[TILE_1_2]], DMA : 1) +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_0_1]], DMA : 0) +// CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { +// CHECK: %[[C8:.*]] = arith.constant 8 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C4:.*]] = arith.constant 4 : index +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C64:.*]] = arith.constant 64 : index +// CHECK: %[[C960:.*]] = arith.constant 960 : index +// CHECK: aie.use_lock(%[[IN8_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[REINTERPRET_CAST:.*]] = memref.reinterpret_cast %[[IN8_BUFF_0]] to offset: [0], sizes: [4, 8, 4, 8], strides: [256, 32, 8, 1] : memref<32x32xi32, 1> to memref<4x8x4x8xi32, 1> +// CHECK: aie.use_lock(%[[IN2_1_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[IN7_CONS_PROD_LOCK]], Release, 1) +// CHECK: %[[C128:.*]] = arith.constant 128 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C64]] to %[[C960]] step %[[C128]] { +// CHECK: aie.use_lock(%[[IN2_1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[REINTERPRET_CAST_0:.*]] = memref.reinterpret_cast %[[IN2_1_CONS_BUFF_0]] to offset: [0], sizes: [8, 8, 4, 8], strides: [256, 32, 8, 1] : memref<32x64xi32, 1> to memref<8x8x4x8xi32, 1> +// CHECK: aie.use_lock(%[[IN7_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[REINTERPRET_CAST_1:.*]] = memref.reinterpret_cast %[[IN7_CONS_BUFF_0]] to offset: [0], sizes: [4, 8, 8, 8], strides: [512, 64, 8, 1] : memref<64x32xi32, 1> to memref<4x8x8x8xi32, 1> +// CHECK: scf.for %[[ARG1:.*]] = %[[C0]] to %[[C8]] step %[[C1]] { +// CHECK: scf.for %[[ARG2:.*]] = %[[C0]] to %[[C4]] step %[[C1]] { +// CHECK: scf.for %[[ARG3:.*]] = %[[C0]] to %[[C8]] step %[[C1]] { +// CHECK: scf.for %[[ARG4:.*]] = %[[C0]] to %[[C4]] step %[[C1]] { +// CHECK: scf.for %[[ARG5:.*]] = %[[C0]] to %[[C8]] step %[[C1]] { +// CHECK: scf.for %[[ARG6:.*]] = %[[C0]] to %[[C8]] step %[[C1]] { +// CHECK: %[[VAL_0:.*]] = memref.load %[[REINTERPRET_CAST_0]]{{\[}}%[[ARG3]], %[[ARG1]], %[[ARG4]], %[[ARG6]]] : memref<8x8x4x8xi32, 1> +// CHECK: %[[VAL_1:.*]] = memref.load %[[REINTERPRET_CAST_1]]{{\[}}%[[ARG2]], %[[ARG3]], %[[ARG6]], %[[ARG5]]] : memref<4x8x8x8xi32, 1> +// CHECK: %[[VAL_2:.*]] = memref.load %[[REINTERPRET_CAST]]{{\[}}%[[ARG2]], %[[ARG1]], %[[ARG4]], %[[ARG5]]] : memref<4x8x4x8xi32, 1> +// CHECK: %[[VAL_3:.*]] = arith.muli %[[VAL_0]], %[[VAL_1]] : i32 +// CHECK: %[[VAL_4:.*]] = arith.addi %[[VAL_2]], %[[VAL_3]] : i32 +// CHECK: memref.store %[[VAL_4]], %[[REINTERPRET_CAST]]{{\[}}%[[ARG2]], %[[ARG1]], %[[ARG4]], %[[ARG5]]] : memref<4x8x4x8xi32, 1> +// CHECK: } +// CHECK: } +// CHECK: } +// CHECK: } +// CHECK: } +// CHECK: } +// CHECK: aie.use_lock(%[[IN2_1_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[IN7_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[IN2_1_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[REINTERPRET_CAST_2:.*]] = memref.reinterpret_cast %[[IN2_1_CONS_BUFF_1]] to offset: [0], sizes: [8, 8, 4, 8], strides: [256, 32, 8, 1] : memref<32x64xi32, 1> to memref<8x8x4x8xi32, 1> +// CHECK: aie.use_lock(%[[IN7_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: %[[REINTERPRET_CAST_3:.*]] = memref.reinterpret_cast %[[IN7_CONS_BUFF_1]] to offset: [0], sizes: [4, 8, 8, 8], strides: [512, 64, 8, 1] : memref<64x32xi32, 1> to memref<4x8x8x8xi32, 1> +// CHECK: scf.for %[[ARG1:.*]] = %[[C0]] to %[[C8]] step %[[C1]] { +// CHECK: scf.for %[[ARG2:.*]] = %[[C0]] to %[[C4]] step %[[C1]] { +// CHECK: scf.for %[[ARG3:.*]] = %[[C0]] to %[[C8]] step %[[C1]] { +// CHECK: scf.for %[[ARG4:.*]] = %[[C0]] to %[[C4]] step %[[C1]] { +// CHECK: scf.for %[[ARG5:.*]] = %[[C0]] to %[[C8]] step %[[C1]] { +// CHECK: scf.for %[[ARG6:.*]] = %[[C0]] to %[[C8]] step %[[C1]] { +// CHECK: %[[VAL_5:.*]] = memref.load %[[REINTERPRET_CAST_2]]{{\[}}%[[ARG3]], %[[ARG1]], %[[ARG4]], %[[ARG6]]] : memref<8x8x4x8xi32, 1> +// CHECK: %[[VAL_6:.*]] = memref.load %[[REINTERPRET_CAST_3]]{{\[}}%[[ARG2]], %[[ARG3]], %[[ARG6]], %[[ARG5]]] : memref<4x8x8x8xi32, 1> +// CHECK: %[[VAL_7:.*]] = memref.load %[[REINTERPRET_CAST]]{{\[}}%[[ARG2]], %[[ARG1]], %[[ARG4]], %[[ARG5]]] : memref<4x8x4x8xi32, 1> +// CHECK: %[[VAL_8:.*]] = arith.muli %[[VAL_5]], %[[VAL_6]] : i32 +// CHECK: %[[VAL_9:.*]] = arith.addi %[[VAL_7]], %[[VAL_8]] : i32 +// CHECK: memref.store %[[VAL_9]], %[[REINTERPRET_CAST]]{{\[}}%[[ARG2]], %[[ARG1]], %[[ARG4]], %[[ARG5]]] : memref<4x8x4x8xi32, 1> +// CHECK: } +// CHECK: } +// CHECK: } +// CHECK: } +// CHECK: } +// CHECK: } +// CHECK: aie.use_lock(%[[IN2_1_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[IN7_CONS_PROD_LOCK]], Release, 1) +// CHECK: } +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEMTILE_DMA_0_1:.*]] = aie.memtile_dma(%[[TILE_0_1]]) { +// CHECK: %[[VAL_10:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb5) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[IN2_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN2_BUFF_0]] : memref<32x64xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN2_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[IN2_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN2_BUFF_1]] : memref<32x64xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN2_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb3 +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[IN2_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN2_BUFF_2]] : memref<32x64xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN2_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb4 +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[IN2_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN2_BUFF_3]] : memref<32x64xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN2_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb5: +// CHECK: %[[VAL_11:.*]] = aie.dma_start(MM2S, 1, ^bb6, ^bb10) +// CHECK: ^bb6: +// CHECK: aie.use_lock(%[[IN7_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN7_BUFF_0]] : memref<64x32xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN7_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb7 +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[IN7_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN7_BUFF_1]] : memref<64x32xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN7_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb8 +// CHECK: ^bb8: +// CHECK: aie.use_lock(%[[IN7_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN7_BUFF_2]] : memref<64x32xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN7_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb9 +// CHECK: ^bb9: +// CHECK: aie.use_lock(%[[IN7_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN7_BUFF_3]] : memref<64x32xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN7_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb6 +// CHECK: ^bb10: +// CHECK: %[[VAL_12:.*]] = aie.dma_start(S2MM, 0, ^bb11, ^bb15) +// CHECK: ^bb11: +// CHECK: aie.use_lock(%[[IN8_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN8_CONS_BUFF_0]] : memref<32x32xi32, 1>, 0, 1024) +// CHECK: aie.use_lock(%[[IN8_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb12 +// CHECK: ^bb12: +// CHECK: aie.use_lock(%[[IN8_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN8_CONS_BUFF_1]] : memref<32x32xi32, 1>, 0, 1024) +// CHECK: aie.use_lock(%[[IN8_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb13 +// CHECK: ^bb13: +// CHECK: aie.use_lock(%[[IN8_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN8_CONS_BUFF_2]] : memref<32x32xi32, 1>, 0, 1024) +// CHECK: aie.use_lock(%[[IN8_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb14 +// CHECK: ^bb14: +// CHECK: aie.use_lock(%[[IN8_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN8_CONS_BUFF_3]] : memref<32x32xi32, 1>, 0, 1024) +// CHECK: aie.use_lock(%[[IN8_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb11 +// CHECK: ^bb15: +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEM_0_2:.*]] = aie.mem(%[[TILE_0_2]]) { +// CHECK: %[[VAL_13:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[IN2_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN2_0_CONS_BUFF_0]] : memref<32x64xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN2_0_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[IN2_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN2_0_CONS_BUFF_1]] : memref<32x64xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN2_0_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb3 +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[IN2_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN2_0_CONS_BUFF_2]] : memref<32x64xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN2_0_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb4 +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[IN2_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN2_0_CONS_BUFF_3]] : memref<32x64xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN2_0_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb5: +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_14:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[IN2_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN2_1_CONS_BUFF_0]] : memref<32x64xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN2_1_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[IN2_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN2_1_CONS_BUFF_1]] : memref<32x64xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN2_1_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: %[[VAL_15:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[IN7_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN7_CONS_BUFF_0]] : memref<64x32xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN7_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb5 +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[IN7_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN7_CONS_BUFF_1]] : memref<64x32xi32, 1>, 0, 2048) +// CHECK: aie.use_lock(%[[IN7_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb4 +// CHECK: ^bb6: +// CHECK: %[[VAL_16:.*]] = aie.dma_start(MM2S, 0, ^bb7, ^bb9) +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[IN8_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN8_BUFF_0]] : memref<32x32xi32, 1>, 0, 1024) +// CHECK: aie.use_lock(%[[IN8_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb8 +// CHECK: ^bb8: +// CHECK: aie.use_lock(%[[IN8_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN8_BUFF_1]] : memref<32x32xi32, 1>, 0, 1024) +// CHECK: aie.use_lock(%[[IN8_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb7 +// CHECK: ^bb9: +// CHECK: aie.end +// CHECK: } +// CHECK: } aie.device(npu1_4col) { %tile_0_1 = aie.tile(0, 1) @@ -123,4 +300,4 @@ aie.device(npu1_4col) { } aie.end } -} \ No newline at end of file +} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_1.mlir index f95cf7851..e49219f4a 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_1.mlir @@ -1,92 +1,81 @@ -//===- non_adjacency_test_1.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -// Date: February 10th 2022 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { // CHECK: memref.global "public" @objfifo_cons : memref<16xi32> // CHECK: memref.global "public" @objfifo : memref<16xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32, sym_name = "objfifo_cons_lock_0"} -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "objfifo_cons_lock_1"} -// CHECK: %[[VAL_6:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_7:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "objfifo_lock_0"} -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "objfifo_lock_1"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: func.func @some_work(%[[VAL_10:.*]]: memref<16xi32>) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[OBJFIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OBJFIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OBJFIFO_CONS_LOCK_0:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 0 : i32, sym_name = "objfifo_cons_lock_0"} +// CHECK: %[[OBJFIFO_CONS_LOCK_1:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "objfifo_cons_lock_1"} +// CHECK: %[[OBJFIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> +// CHECK: %[[OBJFIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> +// CHECK: %[[OBJFIFO_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 0 : i32, sym_name = "objfifo_lock_0"} +// CHECK: %[[OBJFIFO_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "objfifo_lock_1"} +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } -// CHECK: %[[VAL_11:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: %[[VAL_12:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_13:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_14:.*]] = arith.constant 12 : index -// CHECK: %[[VAL_15:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[VAL_16:.*]] = %[[VAL_12]] to %[[VAL_14]] step %[[VAL_15]] { -// CHECK: aie.use_lock(%[[VAL_8]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_6]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_8]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_7]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C12]] step %[[C2]] { +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Acquire, 0) +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Release, 1) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Acquire, 0) +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Release, 1) // CHECK: } // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_17:.*]] = aie.core(%[[VAL_1]]) { -// CHECK: %[[VAL_18:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_19:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_20:.*]] = arith.constant 12 : index -// CHECK: %[[VAL_21:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[VAL_22:.*]] = %[[VAL_18]] to %[[VAL_20]] step %[[VAL_21]] { -// CHECK: aie.use_lock(%[[VAL_4]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_2]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_4]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_3]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_5]], Release, 0) +// CHECK: %[[CORE_3_3:.*]] = aie.core(%[[TILE_3_3]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C12]] step %[[C2]] { +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Acquire, 1) +// CHECK: func.call @some_work(%[[OBJFIFO_CONS_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Release, 0) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Acquire, 1) +// CHECK: func.call @some_work(%[[OBJFIFO_CONS_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Release, 0) // CHECK: } // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_23:.*]] = aie.mem(%[[VAL_0]]) { -// CHECK: %[[VAL_24:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_8]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 0) +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Acquire, 1) +// CHECK: aie.dma_bd(%[[OBJFIFO_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Release, 0) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 0) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Acquire, 1) +// CHECK: aie.dma_bd(%[[OBJFIFO_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Release, 0) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_25:.*]] = aie.mem(%[[VAL_1]]) { -// CHECK: %[[VAL_26:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_4]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_4]], Release, 1) +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OBJFIFO_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OBJFIFO_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } // CHECK: } @@ -95,40 +84,32 @@ module @non_adjacency { aie.device(xcvc1902) { %tile12 = aie.tile(1, 2) %tile33 = aie.tile(3, 3) - aie.objectfifo @objfifo (%tile12, {%tile33}, 2 : i32) : !aie.objectfifo> - func.func @some_work(%lineOut : memref<16xi32>) -> () { return } - %core12 = aie.core(%tile12) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - scf.for %indexInHeight = %c0 to %height step %c1 { %subview = aie.objectfifo.acquire @objfifo (Produce, 1) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem0) : (memref<16xi32>) -> () aie.objectfifo.release @objfifo (Produce, 1) } - aie.end } - %core33 = aie.core(%tile33) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - scf.for %indexInHeight = %c0 to %height step %c1 { %subview = aie.objectfifo.acquire @objfifo (Consume, 1) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem0) : (memref<16xi32>) -> () aie.objectfifo.release @objfifo (Consume, 1) } - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_2.mlir index 6a8446300..8b9387735 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_2.mlir @@ -1,114 +1,103 @@ -//===- non_adjacency_test_2.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -// Date: May 24th 2022 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { // CHECK: memref.global "public" @objfifo_cons : memref<16xi32> // CHECK: memref.global "public" @objfifo : memref<16xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "objfifo_cons_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "objfifo_cons_buff_3"} : memref<16xi32> -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32, sym_name = "objfifo_cons_lock_0"} -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "objfifo_cons_lock_1"} -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_1]], 2) {init = 0 : i32, sym_name = "objfifo_cons_lock_2"} -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_1]], 3) {init = 0 : i32, sym_name = "objfifo_cons_lock_3"} -// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_11:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_12:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "objfifo_lock_0"} -// CHECK: %[[VAL_13:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "objfifo_lock_1"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: func.func @some_work(%[[VAL_14:.*]]: memref<16xi32>) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[OBJFIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OBJFIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OBJFIFO_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_2"} : memref<16xi32> +// CHECK: %[[OBJFIFO_CONS_BUFF_3:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_3"} : memref<16xi32> +// CHECK: %[[OBJFIFO_CONS_LOCK_0:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 0 : i32, sym_name = "objfifo_cons_lock_0"} +// CHECK: %[[OBJFIFO_CONS_LOCK_1:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "objfifo_cons_lock_1"} +// CHECK: %[[OBJFIFO_CONS_LOCK_2:.*]] = aie.lock(%[[TILE_3_3]], 2) {init = 0 : i32, sym_name = "objfifo_cons_lock_2"} +// CHECK: %[[OBJFIFO_CONS_LOCK_3:.*]] = aie.lock(%[[TILE_3_3]], 3) {init = 0 : i32, sym_name = "objfifo_cons_lock_3"} +// CHECK: %[[OBJFIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> +// CHECK: %[[OBJFIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> +// CHECK: %[[OBJFIFO_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 0 : i32, sym_name = "objfifo_lock_0"} +// CHECK: %[[OBJFIFO_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "objfifo_lock_1"} +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } -// CHECK: %[[VAL_15:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: %[[VAL_16:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_17:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_18:.*]] = arith.constant 12 : index -// CHECK: %[[VAL_19:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[VAL_20:.*]] = %[[VAL_16]] to %[[VAL_18]] step %[[VAL_19]] { -// CHECK: aie.use_lock(%[[VAL_12]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_10]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_12]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_13]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_11]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_13]], Release, 1) +// CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C12]] step %[[C2]] { +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Acquire, 0) +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Release, 1) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Acquire, 0) +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Release, 1) // CHECK: } // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_21:.*]] = aie.core(%[[VAL_1]]) { -// CHECK: %[[VAL_22:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_23:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_24:.*]] = arith.constant 12 : index -// CHECK: %[[VAL_25:.*]] = arith.constant 4 : index -// CHECK: scf.for %[[VAL_26:.*]] = %[[VAL_22]] to %[[VAL_24]] step %[[VAL_25]] { -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_8]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_2]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_6]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_3]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_7]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_4]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_8]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_5]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_9]], Release, 0) +// CHECK: %[[CORE_3_3:.*]] = aie.core(%[[TILE_3_3]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: %[[C4:.*]] = arith.constant 4 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C12]] step %[[C4]] { +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Acquire, 1) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Acquire, 1) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_2]], Acquire, 1) +// CHECK: func.call @some_work(%[[OBJFIFO_CONS_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Release, 0) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_3]], Acquire, 1) +// CHECK: func.call @some_work(%[[OBJFIFO_CONS_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Release, 0) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Acquire, 1) +// CHECK: func.call @some_work(%[[OBJFIFO_CONS_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_2]], Release, 0) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Acquire, 1) +// CHECK: func.call @some_work(%[[OBJFIFO_CONS_BUFF_3]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_3]], Release, 0) // CHECK: } // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.mem(%[[VAL_0]]) { -// CHECK: %[[VAL_28:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_12]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_12]], Release, 0) +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Acquire, 1) +// CHECK: aie.dma_bd(%[[OBJFIFO_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Release, 0) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_13]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_11]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_13]], Release, 0) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Acquire, 1) +// CHECK: aie.dma_bd(%[[OBJFIFO_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Release, 0) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.mem(%[[VAL_1]]) { -// CHECK: %[[VAL_30:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OBJFIFO_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OBJFIFO_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[VAL_8]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_2]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OBJFIFO_CONS_BUFF_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_2]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb4: // pred: ^bb3 -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_3]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OBJFIFO_CONS_BUFF_3]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_3]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb5: // pred: ^bb0 +// CHECK: ^bb5: // CHECK: aie.end // CHECK: } // CHECK: } @@ -117,33 +106,26 @@ module @non_adjacency { aie.device(xcvc1902) { %tile12 = aie.tile(1, 2) %tile33 = aie.tile(3, 3) - aie.objectfifo @objfifo (%tile12, {%tile33}, 2 : i32) : !aie.objectfifo> - func.func @some_work(%lineOut : memref<16xi32>) -> () { return } - %core12 = aie.core(%tile12) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - scf.for %indexInHeight = %c0 to %height step %c1 { %subview = aie.objectfifo.acquire @objfifo (Produce, 1) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem0) : (memref<16xi32>) -> () aie.objectfifo.release @objfifo (Produce, 1) } - aie.end } - %core33 = aie.core(%tile33) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - scf.for %indexInHeight = %c0 to %height step %c1 { %subview = aie.objectfifo.acquire @objfifo (Consume, 3) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -152,7 +134,6 @@ module @non_adjacency { func.call @some_work(%elem0) : (memref<16xi32>) -> () aie.objectfifo.release @objfifo (Consume, 1) } - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_AIE2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_AIE2.mlir index 53f6e885c..07aaba180 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_AIE2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/non_adjacency_test_AIE2.mlir @@ -1,93 +1,81 @@ -//===- non_adjacency_test_AIE2.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Xilinx Inc. -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: May 9th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcve2302) { // CHECK: memref.global "public" @of_cons : memref<16xi32> // CHECK: memref.global "public" @of : memref<16xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "of_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "of_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 0) {init = 2 : i32, sym_name = "of_cons_prod_lock"} -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "of_cons_cons_lock"} -// CHECK: %[[VAL_6:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_7:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_0]], 0) {init = 2 : i32, sym_name = "of_prod_lock"} -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "of_cons_lock"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: func.func @some_work(%[[VAL_10:.*]]: memref<16xi32>) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[OF_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OF_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OF_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "of_cons_prod_lock"} +// CHECK: %[[OF_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "of_cons_cons_lock"} +// CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> +// CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_1"} : memref<16xi32> +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i32, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of_cons_lock"} +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_3_3]], DMA : 0) +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } -// CHECK: %[[VAL_11:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: %[[VAL_12:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_13:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_14:.*]] = arith.constant 12 : index -// CHECK: %[[VAL_15:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[VAL_16:.*]] = %[[VAL_12]] to %[[VAL_14]] step %[[VAL_15]] { -// CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: func.call @some_work(%[[VAL_6]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_8]], AcquireGreaterEqual, 1) -// CHECK: func.call @some_work(%[[VAL_7]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C12]] step %[[C2]] { +// CHECK: aie.use_lock(%[[OF_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: func.call @some_work(%[[OF_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[OF_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: func.call @some_work(%[[OF_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_CONS_LOCK]], Release, 1) // CHECK: } // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_17:.*]] = aie.core(%[[VAL_1]]) { -// CHECK: %[[VAL_18:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_19:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_20:.*]] = arith.constant 12 : index -// CHECK: %[[VAL_21:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[VAL_22:.*]] = %[[VAL_18]] to %[[VAL_20]] step %[[VAL_21]] { -// CHECK: aie.use_lock(%[[VAL_5]], AcquireGreaterEqual, 1) -// CHECK: func.call @some_work(%[[VAL_2]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_4]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_5]], AcquireGreaterEqual, 1) -// CHECK: func.call @some_work(%[[VAL_3]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_4]], Release, 1) +// CHECK: %[[CORE_3_3:.*]] = aie.core(%[[TILE_3_3]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C12]] step %[[C2]] { +// CHECK: aie.use_lock(%[[OF_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: func.call @some_work(%[[OF_CONS_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_CONS_PROD_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[OF_CONS_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: func.call @some_work(%[[OF_CONS_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_CONS_PROD_LOCK]], Release, 1) // CHECK: } // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_23:.*]] = aie.mem(%[[VAL_0]]) { -// CHECK: %[[VAL_24:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 1) +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_9]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_25:.*]] = aie.mem(%[[VAL_1]]) { -// CHECK: %[[VAL_26:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_4]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_4]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } // CHECK: } @@ -96,40 +84,32 @@ module @non_adjacency_AIE2 { aie.device(xcve2302) { %tile12 = aie.tile(1, 2) %tile33 = aie.tile(3, 3) - aie.objectfifo @of (%tile12, {%tile33}, 2 : i32) : !aie.objectfifo> - func.func @some_work(%lineOut : memref<16xi32>) -> () { return } - %core12 = aie.core(%tile12) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - scf.for %indexInHeight = %c0 to %height step %c1 { %subview = aie.objectfifo.acquire @of (Produce, 1) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem0) : (memref<16xi32>) -> () aie.objectfifo.release @of (Produce, 1) } - aie.end } - %core33 = aie.core(%tile33) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - scf.for %indexInHeight = %c0 to %height step %c1 { %subview = aie.objectfifo.acquire @of (Consume, 1) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem0) : (memref<16xi32>) -> () aie.objectfifo.release @of (Consume, 1) } - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/npu_instgen.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/npu_instgen.mlir index 0ad63dc22..9ce8b2038 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/npu_instgen.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/npu_instgen.mlir @@ -1,13 +1,3 @@ -//===- npu_instgen.mlir ----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates -// -//===----------------------------------------------------------------------===// - // RUN: iree-compile --compile-mode=hal-executable --iree-hal-target-backends=amd-aie-direct %s --iree-hal-dump-executable-files-to %T // RUN: FileCheck %s --input-file=%T/module_dummy1_amdaie_xclbin_fb/module_dummy1_amdaie_xclbin_fb.npu.txt diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/push_to_queue.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/push_to_queue.mlir index 87c3d8c72..511e8c4f5 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/push_to_queue.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/push_to_queue.mlir @@ -1,14 +1,13 @@ -//===- push_to_queue.mlir ---------------------------------------*- MLIR -*-===// -// -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2023 Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-dma-to-npu %s | FileCheck %s -// CHECK: aiex.npu.write32 {address = 119308 : ui32, column = 0 : i32, row = 0 : i32, value = 2147483651 : ui32} -// CHECK: aiex.npu.write32 {address = 119316 : ui32, column = 2 : i32, row = 0 : i32, value = 196610 : ui32} + +// CHECK-LABEL: aie.device(npu1_4col) { +// CHECK: func.func @sequence() { +// CHECK: aiex.npu.write32 {address = 119308 : ui32, column = 0 : i32, row = 0 : i32, value = 2147483651 : ui32} +// CHECK: aiex.npu.write32 {address = 119316 : ui32, column = 2 : i32, row = 0 : i32, value = 196610 : ui32} +// CHECK: return +// CHECK: } +// CHECK: } module { aie.device(npu1_4col) { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/register_external_buffers_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/register_external_buffers_test.mlir index 5003befc8..c626427c8 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/register_external_buffers_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/register_external_buffers_test.mlir @@ -1,74 +1,62 @@ -//===- register_external_buffers_test.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2022, Xilinx Inc. -// Copyright (C) 2022, Advanced Micro Devices, Inc. -// -// Date: January 27th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { // CHECK: memref.global "public" @ext_of_cons : memref<16xi32> // CHECK: memref.global "public" @ext_of : memref<16xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_1:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "ext_of_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "ext_of_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "ext_of_cons_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "ext_of_cons_lock_0"} -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "ext_of_cons_lock_1"} -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_0]], 2) {init = 0 : i32, sym_name = "ext_of_cons_lock_2"} -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32, sym_name = "ext_of_lock_0"} -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_0]], DMA : 0) -// CHECK: %[[VAL_9:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> -// CHECK: func.func @some_work(%[[VAL_10:.*]]: memref<16xi32>, %[[VAL_11:.*]]: memref<16xi32>) { +// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[EXT_OF_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_7_1]]) {sym_name = "ext_of_cons_buff_0"} : memref<16xi32> +// CHECK: %[[EXT_OF_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_7_1]]) {sym_name = "ext_of_cons_buff_1"} : memref<16xi32> +// CHECK: %[[EXT_OF_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_7_1]]) {sym_name = "ext_of_cons_buff_2"} : memref<16xi32> +// CHECK: %[[EXT_OF_CONS_LOCK_0:.*]] = aie.lock(%[[TILE_7_1]], 0) {init = 0 : i32, sym_name = "ext_of_cons_lock_0"} +// CHECK: %[[EXT_OF_CONS_LOCK_1:.*]] = aie.lock(%[[TILE_7_1]], 1) {init = 0 : i32, sym_name = "ext_of_cons_lock_1"} +// CHECK: %[[EXT_OF_CONS_LOCK_2:.*]] = aie.lock(%[[TILE_7_1]], 2) {init = 0 : i32, sym_name = "ext_of_cons_lock_2"} +// CHECK: %[[EXT_OF_LOCK_0:.*]] = aie.lock(%[[TILE_7_0]], 0) {init = 0 : i32, sym_name = "ext_of_lock_0"} +// CHECK: aie.flow(%[[TILE_7_0]], DMA : 0, %[[TILE_7_1]], DMA : 0) +// CHECK: %[[EXT_BUFFER_IN:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } -// CHECK: %[[VAL_12:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: %[[VAL_13:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_14:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_15:.*]] = arith.constant 12 : index -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_2]], %[[VAL_3]]) : (memref<16xi32>, memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_5]], Release, 0) +// CHECK: %[[CORE_7_1:.*]] = aie.core(%[[TILE_7_1]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: aie.use_lock(%[[EXT_OF_CONS_LOCK_0]], Acquire, 1) +// CHECK: aie.use_lock(%[[EXT_OF_CONS_LOCK_1]], Acquire, 1) +// CHECK: func.call @some_work(%[[EXT_OF_CONS_BUFF_0]], %[[EXT_OF_CONS_BUFF_1]]) : (memref<16xi32>, memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[EXT_OF_CONS_LOCK_0]], Release, 0) // CHECK: aie.end // CHECK: } // CHECK: aie.shim_dma_allocation @ext_of(MM2S, 0, 7) -// CHECK: %[[VAL_16:.*]] = aie.shim_dma(%[[VAL_1]]) { -// CHECK: %[[VAL_17:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 -// CHECK: aie.use_lock(%[[VAL_8]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<64xi32>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 0) +// CHECK: %[[SHIM_DMA_7_0:.*]] = aie.shim_dma(%[[TILE_7_0]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[EXT_OF_LOCK_0]], Acquire, 1) +// CHECK: aie.dma_bd(%[[EXT_BUFFER_IN]] : memref<64xi32>, 0, 64) +// CHECK: aie.use_lock(%[[EXT_OF_LOCK_0]], Release, 0) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: // pred: ^bb0 +// CHECK: ^bb2: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_18:.*]] = aie.mem(%[[VAL_0]]) { -// CHECK: %[[VAL_19:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) +// CHECK: %[[MEM_7_1:.*]] = aie.mem(%[[TILE_7_1]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[EXT_OF_CONS_LOCK_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[EXT_OF_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[EXT_OF_CONS_LOCK_0]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[EXT_OF_CONS_LOCK_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[EXT_OF_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[EXT_OF_CONS_LOCK_1]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[EXT_OF_CONS_LOCK_2]], Acquire, 0) +// CHECK: aie.dma_bd(%[[EXT_OF_CONS_BUFF_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[EXT_OF_CONS_LOCK_2]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb4: // pred: ^bb0 +// CHECK: ^bb4: // CHECK: aie.end // CHECK: } // CHECK: } @@ -77,27 +65,21 @@ module @register_external_buffers { aie.device(xcvc1902) { %tile71 = aie.tile(7, 1) %tile70 = aie.tile(7, 0) - aie.objectfifo @ext_of (%tile70, {%tile71}, 3 : i32) : !aie.objectfifo> - %ext_buffer_in = aie.external_buffer {sym_name = "ext_buffer_in"}: memref<64xi32> aie.objectfifo.register_external_buffers @ext_of (%tile70, {%ext_buffer_in}) : (memref<64xi32>) - func.func @some_work(%a : memref<16xi32>, %b : memref<16xi32>) -> () { return } - %core71 = aie.core(%tile71) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - %subview = aie.objectfifo.acquire @ext_of (Consume, 2) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> %elem1 = aie.objectfifo.subview.access %subview[1] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem0, %elem1) : (memref<16xi32>, memref<16xi32>) -> () aie.objectfifo.release @ext_of (Consume, 1) - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/roundtrip.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/roundtrip.mlir deleted file mode 100644 index f1ee4f458..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/roundtrip.mlir +++ /dev/null @@ -1,39 +0,0 @@ -//===- roundtrip.mlir ------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2024, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: iree-opt --split-input-file %s | FileCheck %s - -// CHECK-LABEL: func.func @npu_dma_wait -// CHECK: aiex.npu.dma_wait {symbol = @out0} -aie.device(npu1_4col) { - memref.global "public" @out0 : memref<16xi32> - func.func @npu_dma_wait() { - aiex.npu.dma_wait {symbol = @out0} - return - } -} - -// ----- - -// CHECK-LABEL: func.func @npu_dma_wait_no_device -// CHECK: aiex.npu.dma_wait {symbol = @out0} -func.func @npu_dma_wait_no_device() { - aiex.npu.dma_wait {symbol = @out0} - return -} - -// ----- - -// CHECK-LABEL: func.func @npu_addr_patch -// CHECK: aiex.npu.address_patch {addr = 123 : ui32, arg_idx = 3 : i32, arg_plus = 0 : i32} -func.func @npu_addr_patch() { - aiex.npu.address_patch {addr = 123 : ui32, arg_idx = 3 : i32, arg_plus = 0 : i32} - return -} \ No newline at end of file diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/same_core_producer_consumer_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/same_core_producer_consumer_test.mlir index e3c4355fc..5ad514d11 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/same_core_producer_consumer_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/same_core_producer_consumer_test.mlir @@ -1,41 +1,30 @@ -//===- same_core_producer_consumer_test.mlir --------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: August 2nd 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcve2302) { // CHECK: memref.global "public" @of : memref<16xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_1:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_0]], 0) {init = 3 : i32, sym_name = "of_prod_lock"} -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "of_cons_lock"} -// CHECK: func.func @some_work(%[[VAL_6:.*]]: memref<16xi32>) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> +// CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_1"} : memref<16xi32> +// CHECK: %[[OF_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_2"} : memref<16xi32> +// CHECK: %[[OF_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 3 : i32, sym_name = "of_prod_lock"} +// CHECK: %[[OF_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of_cons_lock"} +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } -// CHECK: %[[VAL_7:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: aie.use_lock(%[[VAL_4]], AcquireGreaterEqual, 2) -// CHECK: func.call @some_work(%[[VAL_1]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_2]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_5]], AcquireGreaterEqual, 1) -// CHECK: func.call @some_work(%[[VAL_1]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_4]], Release, 1) -// CHECK: func.call @some_work(%[[VAL_2]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_5]], AcquireGreaterEqual, 1) -// CHECK: func.call @some_work(%[[VAL_2]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_4]], Release, 1) +// CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { +// CHECK: aie.use_lock(%[[OF_PROD_LOCK]], AcquireGreaterEqual, 2) +// CHECK: func.call @some_work(%[[OF_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[OF_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: func.call @some_work(%[[OF_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_PROD_LOCK]], Release, 1) +// CHECK: func.call @some_work(%[[OF_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_CONS_LOCK]], Release, 1) +// CHECK: aie.use_lock(%[[OF_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: func.call @some_work(%[[OF_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_PROD_LOCK]], Release, 1) // CHECK: aie.end // CHECK: } // CHECK: } @@ -43,13 +32,10 @@ module @same_core { aie.device(xcve2302) { %tile12 = aie.tile(1, 2) - aie.objectfifo @of (%tile12, {%tile12}, 3 : i32) : !aie.objectfifo> - func.func @some_work(%line_in:memref<16xi32>) -> () { return } - %core12 = aie.core(%tile12) { // this acquires 2 elements %subview0 = aie.objectfifo.acquire @of (Produce, 2) : !aie.objectfifosubview> @@ -58,22 +44,18 @@ module @same_core { func.call @some_work(%elem00) : (memref<16xi32>) -> () func.call @some_work(%elem01) : (memref<16xi32>) -> () aie.objectfifo.release @of (Produce, 1) - %subview1 = aie.objectfifo.acquire @of (Consume, 1) : !aie.objectfifosubview> %elem10 = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem10) : (memref<16xi32>) -> () aie.objectfifo.release @of (Consume, 1) - %subview2 = aie.objectfifo.acquire @of (Produce, 1) : !aie.objectfifosubview> %elem20 = aie.objectfifo.subview.access %subview2[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem20) : (memref<16xi32>) -> () aie.objectfifo.release @of (Produce, 1) - %subview3 = aie.objectfifo.acquire @of (Consume, 1) : !aie.objectfifosubview> %elem30 = aie.objectfifo.subview.access %subview3[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem30) : (memref<16xi32>) -> () aie.objectfifo.release @of (Consume, 1) - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/shimRow_mem_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/shimRow_mem_test.mlir index fd91e653b..989f72170 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/shimRow_mem_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/shimRow_mem_test.mlir @@ -1,72 +1,62 @@ -//===- shimRow_mem_test.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2022, Xilinx Inc. -// Copyright (C) 2022, Advanced Micro Devices, Inc. -// -// Date: January 26th 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_1:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_cons_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "objfifo_cons_lock_0"} -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "objfifo_cons_lock_1"} -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_0]], 2) {init = 0 : i32, sym_name = "objfifo_cons_lock_2"} -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32, sym_name = "objfifo_lock_0"} -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_0]], DMA : 0) -// CHECK: %[[VAL_9:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> -// CHECK: func.func @some_work(%[[VAL_10:.*]]: memref<16xi32>, %[[VAL_11:.*]]: memref<16xi32>) { +// CHECK: memref.global "public" @objfifo_cons : memref<16xi32> +// CHECK: memref.global "public" @objfifo : memref<16xi32> +// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[OBJFIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_7_1]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OBJFIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_7_1]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OBJFIFO_CONS_BUFF_2:.*]] = aie.buffer(%[[TILE_7_1]]) {sym_name = "objfifo_cons_buff_2"} : memref<16xi32> +// CHECK: %[[OBJFIFO_CONS_LOCK_0:.*]] = aie.lock(%[[TILE_7_1]], 0) {init = 0 : i32, sym_name = "objfifo_cons_lock_0"} +// CHECK: %[[OBJFIFO_CONS_LOCK_1:.*]] = aie.lock(%[[TILE_7_1]], 1) {init = 0 : i32, sym_name = "objfifo_cons_lock_1"} +// CHECK: %[[OBJFIFO_CONS_LOCK_2:.*]] = aie.lock(%[[TILE_7_1]], 2) {init = 0 : i32, sym_name = "objfifo_cons_lock_2"} +// CHECK: %[[OBJFIFO_LOCK_0:.*]] = aie.lock(%[[TILE_7_0]], 0) {init = 0 : i32, sym_name = "objfifo_lock_0"} +// CHECK: aie.flow(%[[TILE_7_0]], DMA : 0, %[[TILE_7_1]], DMA : 0) +// CHECK: %[[EXT_BUFFER_IN:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>, %[[ARG1:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } -// CHECK: %[[VAL_12:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: %[[VAL_13:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_14:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_15:.*]] = arith.constant 12 : index -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_2]], %[[VAL_3]]) : (memref<16xi32>, memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_5]], Release, 0) +// CHECK: %[[CORE_7_1:.*]] = aie.core(%[[TILE_7_1]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Acquire, 1) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Acquire, 1) +// CHECK: func.call @some_work(%[[OBJFIFO_CONS_BUFF_0]], %[[OBJFIFO_CONS_BUFF_1]]) : (memref<16xi32>, memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Release, 0) // CHECK: aie.end // CHECK: } // CHECK: aie.shim_dma_allocation @objfifo(MM2S, 0, 7) -// CHECK: %[[VAL_16:.*]] = aie.shim_dma(%[[VAL_1]]) { -// CHECK: %[[VAL_17:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 -// CHECK: aie.use_lock(%[[VAL_8]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<64xi32>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 0) +// CHECK: %[[SHIM_DMA_7_0:.*]] = aie.shim_dma(%[[TILE_7_0]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Acquire, 1) +// CHECK: aie.dma_bd(%[[EXT_BUFFER_IN]] : memref<64xi32>, 0, 64) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Release, 0) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: // pred: ^bb0 +// CHECK: ^bb2: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_18:.*]] = aie.mem(%[[VAL_0]]) { -// CHECK: %[[VAL_19:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) +// CHECK: %[[MEM_7_1:.*]] = aie.mem(%[[TILE_7_1]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OBJFIFO_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OBJFIFO_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb3: // pred: ^bb2 -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_2]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OBJFIFO_CONS_BUFF_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_2]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb4: // pred: ^bb0 +// CHECK: ^bb4: // CHECK: aie.end // CHECK: } // CHECK: } @@ -75,27 +65,21 @@ module @shimRow_mem { aie.device(xcvc1902) { %tile71 = aie.tile(7, 1) %tile70 = aie.tile(7, 0) - aie.objectfifo @objfifo (%tile70, {%tile71}, 3 : i32) : !aie.objectfifo> - %ext_buffer_in = aie.external_buffer {sym_name = "ext_buffer_in"}: memref<64xi32> aie.objectfifo.register_external_buffers @objfifo (%tile70, {%ext_buffer_in}) : (memref<64xi32>) - func.func @some_work(%a : memref<16xi32>, %b : memref<16xi32>) -> () { return } - %core71 = aie.core(%tile71) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - %subview = aie.objectfifo.acquire @objfifo (Consume, 2) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> %elem1 = aie.objectfifo.subview.access %subview[1] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem0, %elem1) : (memref<16xi32>, memref<16xi32>) -> () aie.objectfifo.release @objfifo (Consume, 1) - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_AIE2_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_AIE2_test.mlir index 1bf9fe5fe..3c8397557 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_AIE2_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_AIE2_test.mlir @@ -1,80 +1,73 @@ -//===- shim_AIE2_test.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: July 3rd 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcve2302) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_2:.*]] = aie.lock(%[[VAL_1]], 2) {init = 1 : i32, sym_name = "of_out_cons_prod_lock"} -// CHECK: %[[VAL_3:.*]] = aie.lock(%[[VAL_1]], 3) {init = 0 : i32, sym_name = "of_out_cons_cons_lock"} -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_out_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_out_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_0]], 2) {init = 2 : i32, sym_name = "of_out_prod_lock"} -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_0]], 3) {init = 0 : i32, sym_name = "of_out_cons_lock"} -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_in_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_9:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_in_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_10:.*]] = aie.lock(%[[VAL_0]], 0) {init = 2 : i32, sym_name = "of_in_cons_prod_lock"} -// CHECK: %[[VAL_11:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "of_in_cons_cons_lock"} -// CHECK: %[[VAL_12:.*]] = aie.lock(%[[VAL_1]], 0) {init = 1 : i32, sym_name = "of_in_prod_lock"} -// CHECK: %[[VAL_13:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "of_in_cons_lock"} -// CHECK: aie.flow(%[[VAL_1]], DMA : 0, %[[VAL_0]], DMA : 0) -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: %[[VAL_14:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> -// CHECK: %[[VAL_15:.*]] = aie.external_buffer {sym_name = "ext_buffer_out"} : memref<64xi32> +// CHECK: memref.global "public" @of_out_cons : memref<16xi32> +// CHECK: memref.global "public" @of_out : memref<16xi32> +// CHECK: memref.global "public" @of_in_cons : memref<16xi32> +// CHECK: memref.global "public" @of_in : memref<16xi32> +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[OF_OUT_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 2) {init = 1 : i32, sym_name = "of_out_cons_prod_lock"} +// CHECK: %[[OF_OUT_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 3) {init = 0 : i32, sym_name = "of_out_cons_cons_lock"} +// CHECK: %[[OF_OUT_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_buff_0"} : memref<16xi32> +// CHECK: %[[OF_OUT_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_out_buff_1"} : memref<16xi32> +// CHECK: %[[OF_OUT_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 2) {init = 2 : i32, sym_name = "of_out_prod_lock"} +// CHECK: %[[OF_OUT_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 3) {init = 0 : i32, sym_name = "of_out_cons_lock"} +// CHECK: %[[OF_IN_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OF_IN_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OF_IN_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of_in_cons_prod_lock"} +// CHECK: %[[OF_IN_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of_in_cons_cons_lock"} +// CHECK: %[[OF_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 1 : i32, sym_name = "of_in_prod_lock"} +// CHECK: %[[OF_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "of_in_cons_lock"} +// CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_2]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_2]], DMA : 0, %[[TILE_2_0]], DMA : 0) +// CHECK: %[[EXT_BUFFER_IN:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> +// CHECK: %[[EXT_BUFFER_OUT:.*]] = aie.external_buffer {sym_name = "ext_buffer_out"} : memref<64xi32> // CHECK: aie.shim_dma_allocation @of_in(MM2S, 0, 2) -// CHECK: %[[VAL_16:.*]] = aie.shim_dma(%[[VAL_1]]) { -// CHECK: %[[VAL_17:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 -// CHECK: aie.use_lock(%[[VAL_13]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_14]] : memref<64xi32>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_12]], Release, 1) +// CHECK: %[[SHIM_DMA_2_0:.*]] = aie.shim_dma(%[[TILE_2_0]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_IN_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[EXT_BUFFER_IN]] : memref<64xi32>, 0, 64) +// CHECK: aie.use_lock(%[[OF_IN_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: // pred: ^bb0 -// CHECK: %[[VAL_18:.*]] = aie.dma_start(S2MM, 0, ^bb3, ^bb4) -// CHECK: ^bb3: // 2 preds: ^bb2, ^bb3 -// CHECK: aie.use_lock(%[[VAL_2]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_15]] : memref<64xi32>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_3]], Release, 1) +// CHECK: ^bb2: +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb3, ^bb4) +// CHECK: ^bb3: +// CHECK: aie.use_lock(%[[OF_OUT_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[EXT_BUFFER_OUT]] : memref<64xi32>, 0, 64) +// CHECK: aie.use_lock(%[[OF_OUT_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb3 -// CHECK: ^bb4: // pred: ^bb2 +// CHECK: ^bb4: // CHECK: aie.end // CHECK: } // CHECK: aie.shim_dma_allocation @of_out(S2MM, 0, 2) -// CHECK: %[[VAL_19:.*]] = aie.mem(%[[VAL_0]]) { -// CHECK: %[[VAL_20:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_2:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_IN_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_IN_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_IN_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF_IN_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_IN_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_IN_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: %[[VAL_21:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) -// CHECK: ^bb4: // 2 preds: ^bb3, ^bb5 -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) +// CHECK: ^bb3: +// CHECK: %[[VAL_3:.*]] = aie.dma_start(MM2S, 0, ^bb4, ^bb6) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[OF_OUT_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_OUT_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_OUT_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb5 -// CHECK: ^bb5: // pred: ^bb4 -// CHECK: aie.use_lock(%[[VAL_7]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[OF_OUT_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_OUT_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_OUT_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb6: // pred: ^bb3 +// CHECK: ^bb6: // CHECK: aie.end // CHECK: } // CHECK: } @@ -83,10 +76,8 @@ module @shim_AIE2 { aie.device(xcve2302) { %tile22 = aie.tile(2, 2) %tile20 = aie.tile(2, 0) - aie.objectfifo @of_in (%tile20, {%tile22}, 2 : i32) : !aie.objectfifo> aie.objectfifo @of_out (%tile22, {%tile20}, 2 : i32) : !aie.objectfifo> - %ext_buffer_in = aie.external_buffer {sym_name = "ext_buffer_in"}: memref<64xi32> %ext_buffer_out = aie.external_buffer {sym_name = "ext_buffer_out"}: memref<64xi32> aie.objectfifo.register_external_buffers @of_in (%tile20, {%ext_buffer_in}) : (memref<64xi32>) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_broadcast_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_broadcast_test.mlir index 05277f99a..57b4cd3ca 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_broadcast_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/shim_broadcast_test.mlir @@ -1,94 +1,87 @@ -//===- shim_broadcast_test.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2023, Advanced Micro Devices, Inc. -// -// Date: July 3rd 2023 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcve2302) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_3:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "of_in_0_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "of_in_0_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_1]], 0) {init = 2 : i32, sym_name = "of_in_0_cons_prod_lock"} -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "of_in_0_cons_cons_lock"} -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "of_in_1_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_9:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "of_in_1_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_10:.*]] = aie.lock(%[[VAL_2]], 0) {init = 2 : i32, sym_name = "of_in_1_cons_prod_lock"} -// CHECK: %[[VAL_11:.*]] = aie.lock(%[[VAL_2]], 1) {init = 0 : i32, sym_name = "of_in_1_cons_cons_lock"} -// CHECK: %[[VAL_12:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "of_in_2_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_13:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "of_in_2_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_14:.*]] = aie.lock(%[[VAL_3]], 0) {init = 2 : i32, sym_name = "of_in_2_cons_prod_lock"} -// CHECK: %[[VAL_15:.*]] = aie.lock(%[[VAL_3]], 1) {init = 0 : i32, sym_name = "of_in_2_cons_cons_lock"} -// CHECK: %[[VAL_16:.*]] = aie.lock(%[[VAL_0]], 0) {init = 1 : i32, sym_name = "of_in_prod_lock"} -// CHECK: %[[VAL_17:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "of_in_cons_lock"} -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_3]], DMA : 0) -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_2]], DMA : 0) -// CHECK: aie.flow(%[[VAL_0]], DMA : 0, %[[VAL_1]], DMA : 0) -// CHECK: %[[VAL_18:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> +// CHECK: memref.global "public" @of_in_0_cons : memref<16xi32> +// CHECK: memref.global "public" @of_in_1_cons : memref<16xi32> +// CHECK: memref.global "public" @of_in_2_cons : memref<16xi32> +// CHECK: memref.global "public" @of_in : memref<16xi32> +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[OF_IN_0_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OF_IN_0_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_2]]) {sym_name = "of_in_0_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OF_IN_0_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 0) {init = 2 : i32, sym_name = "of_in_0_cons_prod_lock"} +// CHECK: %[[OF_IN_0_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_2]], 1) {init = 0 : i32, sym_name = "of_in_0_cons_cons_lock"} +// CHECK: %[[OF_IN_1_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OF_IN_1_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_2_3]]) {sym_name = "of_in_1_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OF_IN_1_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 0) {init = 2 : i32, sym_name = "of_in_1_cons_prod_lock"} +// CHECK: %[[OF_IN_1_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_3]], 1) {init = 0 : i32, sym_name = "of_in_1_cons_cons_lock"} +// CHECK: %[[OF_IN_2_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of_in_2_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OF_IN_2_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "of_in_2_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OF_IN_2_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 2 : i32, sym_name = "of_in_2_cons_prod_lock"} +// CHECK: %[[OF_IN_2_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "of_in_2_cons_cons_lock"} +// CHECK: %[[OF_IN_PROD_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 0) {init = 1 : i32, sym_name = "of_in_prod_lock"} +// CHECK: %[[OF_IN_CONS_LOCK:.*]] = aie.lock(%[[TILE_2_0]], 1) {init = 0 : i32, sym_name = "of_in_cons_lock"} +// CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_3_3]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_3]], DMA : 0) +// CHECK: aie.flow(%[[TILE_2_0]], DMA : 0, %[[TILE_2_2]], DMA : 0) +// CHECK: %[[EXT_BUFFER_IN:.*]] = aie.external_buffer {sym_name = "ext_buffer_in"} : memref<64xi32> // CHECK: aie.shim_dma_allocation @of_in(MM2S, 0, 2) -// CHECK: %[[VAL_19:.*]] = aie.shim_dma(%[[VAL_0]]) { -// CHECK: %[[VAL_20:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb1 -// CHECK: aie.use_lock(%[[VAL_17]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_18]] : memref<64xi32>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_16]], Release, 1) +// CHECK: %[[SHIM_DMA_2_0:.*]] = aie.shim_dma(%[[TILE_2_0]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb2) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_IN_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[EXT_BUFFER_IN]] : memref<64xi32>, 0, 64) +// CHECK: aie.use_lock(%[[OF_IN_PROD_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb2: // pred: ^bb0 +// CHECK: ^bb2: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_21:.*]] = aie.mem(%[[VAL_1]]) { -// CHECK: %[[VAL_22:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: %[[MEM_2_2:.*]] = aie.mem(%[[TILE_2_2]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_IN_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_IN_0_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_IN_0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_6]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_5]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF_IN_0_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_IN_0_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_IN_0_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_23:.*]] = aie.mem(%[[VAL_2]]) { -// CHECK: %[[VAL_24:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: %[[MEM_2_3:.*]] = aie.mem(%[[TILE_2_3]]) { +// CHECK: %[[VAL_2:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_IN_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_IN_1_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_IN_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_10]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_9]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF_IN_1_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_IN_1_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_IN_1_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_25:.*]] = aie.mem(%[[VAL_3]]) { -// CHECK: %[[VAL_26:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_14]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_12]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_15]], Release, 1) +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_IN_2_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_IN_2_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_IN_2_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_14]], AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%[[VAL_13]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_15]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF_IN_2_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_IN_2_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_IN_2_CONS_CONS_LOCK]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } // CHECK: } @@ -99,9 +92,7 @@ module @shim_broadcast { %tile22 = aie.tile(2, 2) %tile23 = aie.tile(2, 3) %tile33 = aie.tile(3, 3) - aie.objectfifo @of_in (%tile20, {%tile22, %tile23, %tile33}, 2 : i32) : !aie.objectfifo> - %ext_buffer_in = aie.external_buffer {sym_name = "ext_buffer_in"}: memref<64xi32> aie.objectfifo.register_external_buffers @of_in (%tile20, {%ext_buffer_in}) : (memref<64xi32>) } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/subview_test_1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/subview_test_1.mlir index de9e435cb..b636207e3 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/subview_test_1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/subview_test_1.mlir @@ -1,47 +1,37 @@ -//===- subview_test_1.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -// Date: October 26th 2021 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_buff_3"} : memref<16xi32> -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "objfifo_lock_0"} -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "objfifo_lock_1"} -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_0]], 2) {init = 0 : i32, sym_name = "objfifo_lock_2"} -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_0]], 3) {init = 0 : i32, sym_name = "objfifo_lock_3"} -// CHECK: func.func @some_work(%[[VAL_10:.*]]: memref<16xi32>) { +// CHECK: memref.global "public" @objfifo : memref<16xi32> +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[OBJFIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> +// CHECK: %[[OBJFIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> +// CHECK: %[[OBJFIFO_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_2"} : memref<16xi32> +// CHECK: %[[OBJFIFO_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_3"} : memref<16xi32> +// CHECK: %[[OBJFIFO_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 0 : i32, sym_name = "objfifo_lock_0"} +// CHECK: %[[OBJFIFO_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "objfifo_lock_1"} +// CHECK: %[[OBJFIFO_LOCK_2:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 0 : i32, sym_name = "objfifo_lock_2"} +// CHECK: %[[OBJFIFO_LOCK_3:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "objfifo_lock_3"} +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } -// CHECK: %[[VAL_11:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_2]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_3]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_8]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_2]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_3]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_4]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_4]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_5]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_4]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_5]]) : (memref<16xi32>) -> () +// CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Acquire, 0) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Acquire, 0) +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_2]], Acquire, 0) +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Release, 1) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Release, 1) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_3]], Acquire, 0) +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_3]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_3]]) : (memref<16xi32>) -> () // CHECK: aie.end // CHECK: } // CHECK: } @@ -50,13 +40,10 @@ module @singleFifo { aie.device(xcvc1902) { %tile12 = aie.tile(1, 2) %tile13 = aie.tile(1, 3) - aie.objectfifo @objfifo (%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> - func.func @some_work(%line_in:memref<16xi32>) -> () { return } - %core12 = aie.core(%tile12) { // this acquires 2 elements %subview0 = aie.objectfifo.acquire @objfifo (Produce, 2) : !aie.objectfifosubview> @@ -64,7 +51,6 @@ module @singleFifo { %elem01 = aie.objectfifo.subview.access %subview0[1] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem00) : (memref<16xi32>) -> () func.call @some_work(%elem01) : (memref<16xi32>) -> () - // this should only acquire one new element, previous two are still acquired %subview1 = aie.objectfifo.acquire @objfifo (Produce, 3) : !aie.objectfifosubview> %elem10 = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -73,7 +59,6 @@ module @singleFifo { func.call @some_work(%elem10) : (memref<16xi32>) -> () func.call @some_work(%elem11) : (memref<16xi32>) -> () func.call @some_work(%elem12) : (memref<16xi32>) -> () - // one new acquire should take place aie.objectfifo.release @objfifo (Produce, 1) aie.objectfifo.release @objfifo (Produce, 1) @@ -82,7 +67,6 @@ module @singleFifo { %elem21 = aie.objectfifo.subview.access %subview2[1] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem20) : (memref<16xi32>) -> () func.call @some_work(%elem21) : (memref<16xi32>) -> () - // no new acquires should take place, elem30 should be third element of objFifo (with index 2) %subview3 = aie.objectfifo.acquire @objfifo (Produce, 2) : !aie.objectfifosubview> %elem30 = aie.objectfifo.subview.access %subview3[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -90,7 +74,6 @@ module @singleFifo { //%elem32 = aie.subview.access %subview3[2] : !aie.subview> -> memref<16xi32> // expected to fail if this line is uncommented func.call @some_work(%elem30) : (memref<16xi32>) -> () func.call @some_work(%elem31) : (memref<16xi32>) -> () - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/subview_test_2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/subview_test_2.mlir index 7a279faf5..6efe3f59b 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/subview_test_2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/subview_test_2.mlir @@ -1,79 +1,68 @@ -//===- subview_test_2.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -// Date: November 19th 2021 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { // CHECK: memref.global "public" @of2 : memref<16xi32> // CHECK: memref.global "public" @of : memref<16xi32> -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of2_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of2_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of2_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_0]], 4) {init = 0 : i32, sym_name = "of2_lock_0"} -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_0]], 5) {init = 0 : i32, sym_name = "of2_lock_1"} -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_0]], 6) {init = 0 : i32, sym_name = "of2_lock_2"} -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_9:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_11:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_3"} : memref<16xi32> -// CHECK: %[[VAL_12:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "of_lock_0"} -// CHECK: %[[VAL_13:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "of_lock_1"} -// CHECK: %[[VAL_14:.*]] = aie.lock(%[[VAL_0]], 2) {init = 0 : i32, sym_name = "of_lock_2"} -// CHECK: %[[VAL_15:.*]] = aie.lock(%[[VAL_0]], 3) {init = 0 : i32, sym_name = "of_lock_3"} -// CHECK: func.func @some_work(%[[VAL_16:.*]]: memref<16xi32>) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[OF2_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of2_buff_0"} : memref<16xi32> +// CHECK: %[[OF2_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of2_buff_1"} : memref<16xi32> +// CHECK: %[[OF2_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of2_buff_2"} : memref<16xi32> +// CHECK: %[[OF2_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 4) {init = 0 : i32, sym_name = "of2_lock_0"} +// CHECK: %[[OF2_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 5) {init = 0 : i32, sym_name = "of2_lock_1"} +// CHECK: %[[OF2_LOCK_2:.*]] = aie.lock(%[[TILE_1_2]], 6) {init = 0 : i32, sym_name = "of2_lock_2"} +// CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> +// CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_1"} : memref<16xi32> +// CHECK: %[[OF_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_2"} : memref<16xi32> +// CHECK: %[[OF_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_3"} : memref<16xi32> +// CHECK: %[[OF_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 0 : i32, sym_name = "of_lock_0"} +// CHECK: %[[OF_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of_lock_1"} +// CHECK: %[[OF_LOCK_2:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 0 : i32, sym_name = "of_lock_2"} +// CHECK: %[[OF_LOCK_3:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "of_lock_3"} +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } -// CHECK: %[[VAL_17:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: aie.use_lock(%[[VAL_12]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_13]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_8]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_9]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_2]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_12]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_14]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_15]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_9]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_10]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_11]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_13]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_14]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_15]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_3]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_4]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) +// CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { +// CHECK: aie.use_lock(%[[OF_LOCK_0]], Acquire, 0) +// CHECK: aie.use_lock(%[[OF_LOCK_1]], Acquire, 0) +// CHECK: func.call @some_work(%[[OF_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF2_LOCK_0]], Acquire, 0) +// CHECK: func.call @some_work(%[[OF2_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_LOCK_0]], Release, 1) +// CHECK: aie.use_lock(%[[OF_LOCK_2]], Acquire, 0) +// CHECK: aie.use_lock(%[[OF_LOCK_3]], Acquire, 0) +// CHECK: func.call @some_work(%[[OF_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF_BUFF_3]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_LOCK_1]], Release, 1) +// CHECK: aie.use_lock(%[[OF_LOCK_2]], Release, 1) +// CHECK: aie.use_lock(%[[OF_LOCK_3]], Release, 1) +// CHECK: aie.use_lock(%[[OF2_LOCK_0]], Release, 1) +// CHECK: aie.use_lock(%[[OF2_LOCK_1]], Acquire, 0) +// CHECK: aie.use_lock(%[[OF2_LOCK_2]], Acquire, 0) +// CHECK: func.call @some_work(%[[OF2_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF2_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF2_LOCK_1]], Release, 1) // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_18:.*]] = aie.core(%[[VAL_1]]) { -// CHECK: aie.use_lock(%[[VAL_12]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_8]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_2]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_3]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_5]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_12]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_13]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_14]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_9]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_10]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_13]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_14]], Release, 0) +// CHECK: %[[CORE_1_3:.*]] = aie.core(%[[TILE_1_3]]) { +// CHECK: aie.use_lock(%[[OF_LOCK_0]], Acquire, 1) +// CHECK: func.call @some_work(%[[OF_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF2_LOCK_0]], Acquire, 1) +// CHECK: aie.use_lock(%[[OF2_LOCK_1]], Acquire, 1) +// CHECK: func.call @some_work(%[[OF2_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF2_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF2_LOCK_0]], Release, 0) +// CHECK: aie.use_lock(%[[OF2_LOCK_1]], Release, 0) +// CHECK: aie.use_lock(%[[OF_LOCK_0]], Release, 0) +// CHECK: aie.use_lock(%[[OF_LOCK_1]], Acquire, 1) +// CHECK: aie.use_lock(%[[OF_LOCK_2]], Acquire, 1) +// CHECK: func.call @some_work(%[[OF_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_LOCK_1]], Release, 0) +// CHECK: aie.use_lock(%[[OF_LOCK_2]], Release, 0) // CHECK: aie.end // CHECK: } // CHECK: } @@ -82,25 +71,20 @@ module @multiFifo { aie.device(xcvc1902) { %tile12 = aie.tile(1, 2) %tile13 = aie.tile(1, 3) - aie.objectfifo @of (%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> aie.objectfifo @of2 (%tile12, {%tile13}, 3 : i32) : !aie.objectfifo> - func.func @some_work(%line_in:memref<16xi32>) -> () { return } - %core12 = aie.core(%tile12) { %subview0 = aie.objectfifo.acquire @of (Produce, 2) : !aie.objectfifosubview> %elem00 = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref<16xi32> %elem01 = aie.objectfifo.subview.access %subview0[1] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem00) : (memref<16xi32>) -> () func.call @some_work(%elem01) : (memref<16xi32>) -> () - %subview02 = aie.objectfifo.acquire @of2 (Produce, 1) : !aie.objectfifosubview> %elem002 = aie.objectfifo.subview.access %subview02[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem002) : (memref<16xi32>) -> () - aie.objectfifo.release @of (Produce, 1) %subview1 = aie.objectfifo.acquire @of (Produce, 3) : !aie.objectfifosubview> %elem10 = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -110,7 +94,6 @@ module @multiFifo { func.call @some_work(%elem11) : (memref<16xi32>) -> () func.call @some_work(%elem12) : (memref<16xi32>) -> () aie.objectfifo.release @of (Produce, 3) - aie.objectfifo.release @of2 (Produce, 1) %subview12 = aie.objectfifo.acquire @of2 (Produce, 2) : !aie.objectfifosubview> %elem102 = aie.objectfifo.subview.access %subview12[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -118,22 +101,18 @@ module @multiFifo { func.call @some_work(%elem102) : (memref<16xi32>) -> () func.call @some_work(%elem112) : (memref<16xi32>) -> () aie.objectfifo.release @of2 (Produce, 1) - aie.end } - %core13 = aie.core(%tile13) { %subview0 = aie.objectfifo.acquire @of (Consume, 1) : !aie.objectfifosubview> %elem00 = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem00) : (memref<16xi32>) -> () - %subview02 = aie.objectfifo.acquire @of2 (Consume, 2) : !aie.objectfifosubview> %elem002 = aie.objectfifo.subview.access %subview02[0] : !aie.objectfifosubview> -> memref<16xi32> %elem012 = aie.objectfifo.subview.access %subview02[1] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem002) : (memref<16xi32>) -> () func.call @some_work(%elem012) : (memref<16xi32>) -> () aie.objectfifo.release @of2 (Consume, 2) - aie.objectfifo.release @of (Consume, 1) %subview1 = aie.objectfifo.acquire @of (Consume, 2) : !aie.objectfifosubview> %elem10 = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -141,7 +120,6 @@ module @multiFifo { func.call @some_work(%elem10) : (memref<16xi32>) -> () func.call @some_work(%elem11) : (memref<16xi32>) -> () aie.objectfifo.release @of (Consume, 2) - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/subview_test_3.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/subview_test_3.mlir index 070b0b675..07aa6ace1 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/subview_test_3.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/subview_test_3.mlir @@ -1,77 +1,68 @@ -//===- subview_test_3.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -// Date: November 19th 2021 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "of2_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "of2_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "of2_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32, sym_name = "of2_lock_0"} -// CHECK: %[[VAL_6:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "of2_lock_1"} -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_1]], 2) {init = 0 : i32, sym_name = "of2_lock_2"} -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_9:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_2"} : memref<16xi32> -// CHECK: %[[VAL_11:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "of_buff_3"} : memref<16xi32> -// CHECK: %[[VAL_12:.*]] = aie.lock(%[[VAL_0]], 0) {init = 0 : i32, sym_name = "of_lock_0"} -// CHECK: %[[VAL_13:.*]] = aie.lock(%[[VAL_0]], 1) {init = 0 : i32, sym_name = "of_lock_1"} -// CHECK: %[[VAL_14:.*]] = aie.lock(%[[VAL_0]], 2) {init = 0 : i32, sym_name = "of_lock_2"} -// CHECK: %[[VAL_15:.*]] = aie.lock(%[[VAL_0]], 3) {init = 0 : i32, sym_name = "of_lock_3"} -// CHECK: func.func @some_work(%[[VAL_16:.*]]: memref<16xi32>) { +// CHECK: memref.global "public" @of2 : memref<16xi32> +// CHECK: memref.global "public" @of : memref<16xi32> +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[OF2_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of2_buff_0"} : memref<16xi32> +// CHECK: %[[OF2_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of2_buff_1"} : memref<16xi32> +// CHECK: %[[OF2_BUFF_2:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of2_buff_2"} : memref<16xi32> +// CHECK: %[[OF2_LOCK_0:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 0 : i32, sym_name = "of2_lock_0"} +// CHECK: %[[OF2_LOCK_1:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i32, sym_name = "of2_lock_1"} +// CHECK: %[[OF2_LOCK_2:.*]] = aie.lock(%[[TILE_1_3]], 2) {init = 0 : i32, sym_name = "of2_lock_2"} +// CHECK: %[[OF_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_0"} : memref<16xi32> +// CHECK: %[[OF_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_1"} : memref<16xi32> +// CHECK: %[[OF_BUFF_2:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_2"} : memref<16xi32> +// CHECK: %[[OF_BUFF_3:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_buff_3"} : memref<16xi32> +// CHECK: %[[OF_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 0 : i32, sym_name = "of_lock_0"} +// CHECK: %[[OF_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of_lock_1"} +// CHECK: %[[OF_LOCK_2:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 0 : i32, sym_name = "of_lock_2"} +// CHECK: %[[OF_LOCK_3:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "of_lock_3"} +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } -// CHECK: %[[VAL_17:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: aie.use_lock(%[[VAL_12]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_13]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_8]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_9]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_2]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_12]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_14]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_15]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_9]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_10]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_11]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_13]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_14]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_15]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_3]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_4]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_6]], Release, 0) +// CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { +// CHECK: aie.use_lock(%[[OF_LOCK_0]], Acquire, 0) +// CHECK: aie.use_lock(%[[OF_LOCK_1]], Acquire, 0) +// CHECK: func.call @some_work(%[[OF_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF2_LOCK_0]], Acquire, 1) +// CHECK: func.call @some_work(%[[OF2_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_LOCK_0]], Release, 1) +// CHECK: aie.use_lock(%[[OF_LOCK_2]], Acquire, 0) +// CHECK: aie.use_lock(%[[OF_LOCK_3]], Acquire, 0) +// CHECK: func.call @some_work(%[[OF_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF_BUFF_3]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_LOCK_1]], Release, 1) +// CHECK: aie.use_lock(%[[OF_LOCK_2]], Release, 1) +// CHECK: aie.use_lock(%[[OF_LOCK_3]], Release, 1) +// CHECK: aie.use_lock(%[[OF2_LOCK_0]], Release, 0) +// CHECK: aie.use_lock(%[[OF2_LOCK_1]], Acquire, 1) +// CHECK: aie.use_lock(%[[OF2_LOCK_2]], Acquire, 1) +// CHECK: func.call @some_work(%[[OF2_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF2_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF2_LOCK_1]], Release, 0) // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_18:.*]] = aie.core(%[[VAL_1]]) { -// CHECK: aie.use_lock(%[[VAL_12]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_8]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.use_lock(%[[VAL_6]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_2]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_3]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_6]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_12]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_13]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_14]], Acquire, 1) -// CHECK: func.call @some_work(%[[VAL_9]]) : (memref<16xi32>) -> () -// CHECK: func.call @some_work(%[[VAL_10]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_13]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_14]], Release, 0) +// CHECK: %[[CORE_1_3:.*]] = aie.core(%[[TILE_1_3]]) { +// CHECK: aie.use_lock(%[[OF_LOCK_0]], Acquire, 1) +// CHECK: func.call @some_work(%[[OF_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF2_LOCK_0]], Acquire, 0) +// CHECK: aie.use_lock(%[[OF2_LOCK_1]], Acquire, 0) +// CHECK: func.call @some_work(%[[OF2_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF2_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF2_LOCK_0]], Release, 1) +// CHECK: aie.use_lock(%[[OF2_LOCK_1]], Release, 1) +// CHECK: aie.use_lock(%[[OF_LOCK_0]], Release, 0) +// CHECK: aie.use_lock(%[[OF_LOCK_1]], Acquire, 1) +// CHECK: aie.use_lock(%[[OF_LOCK_2]], Acquire, 1) +// CHECK: func.call @some_work(%[[OF_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: func.call @some_work(%[[OF_BUFF_2]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OF_LOCK_1]], Release, 0) +// CHECK: aie.use_lock(%[[OF_LOCK_2]], Release, 0) // CHECK: aie.end // CHECK: } // CHECK: } @@ -80,25 +71,20 @@ module @multiCoreMixedFifo { aie.device(xcvc1902) { %tile12 = aie.tile(1, 2) %tile13 = aie.tile(1, 3) - aie.objectfifo @of (%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> aie.objectfifo @of2 (%tile13, {%tile12}, 3 : i32) : !aie.objectfifo> - func.func @some_work(%line_in:memref<16xi32>) -> () { return } - %core11 = aie.core(%tile12) { %subview0 = aie.objectfifo.acquire @of (Produce, 2) : !aie.objectfifosubview> %elem00 = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref<16xi32> %elem01 = aie.objectfifo.subview.access %subview0[1] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem00) : (memref<16xi32>) -> () func.call @some_work(%elem01) : (memref<16xi32>) -> () - %subview02 = aie.objectfifo.acquire @of2 (Consume, 1) : !aie.objectfifosubview> %elem002 = aie.objectfifo.subview.access %subview02[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem002) : (memref<16xi32>) -> () - aie.objectfifo.release @of (Produce, 1) %subview1 = aie.objectfifo.acquire @of (Produce, 3) : !aie.objectfifosubview> %elem10 = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -108,7 +94,6 @@ module @multiCoreMixedFifo { func.call @some_work(%elem11) : (memref<16xi32>) -> () func.call @some_work(%elem12) : (memref<16xi32>) -> () aie.objectfifo.release @of (Produce, 3) - aie.objectfifo.release @of2 (Consume, 1) %subview12 = aie.objectfifo.acquire @of2 (Consume, 2) : !aie.objectfifosubview> %elem102 = aie.objectfifo.subview.access %subview12[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -116,22 +101,18 @@ module @multiCoreMixedFifo { func.call @some_work(%elem102) : (memref<16xi32>) -> () func.call @some_work(%elem112) : (memref<16xi32>) -> () aie.objectfifo.release @of2 (Consume, 1) - aie.end } - %core12 = aie.core(%tile13) { %subview0 = aie.objectfifo.acquire @of (Consume, 1) : !aie.objectfifosubview> %elem00 = aie.objectfifo.subview.access %subview0[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem00) : (memref<16xi32>) -> () - %subview02 = aie.objectfifo.acquire @of2 (Produce, 2) : !aie.objectfifosubview> %elem002 = aie.objectfifo.subview.access %subview02[0] : !aie.objectfifosubview> -> memref<16xi32> %elem012 = aie.objectfifo.subview.access %subview02[1] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem002) : (memref<16xi32>) -> () func.call @some_work(%elem012) : (memref<16xi32>) -> () aie.objectfifo.release @of2 (Produce, 2) - aie.objectfifo.release @of (Consume, 1) %subview1 = aie.objectfifo.acquire @of (Consume, 2) : !aie.objectfifosubview> %elem10 = aie.objectfifo.subview.access %subview1[0] : !aie.objectfifosubview> -> memref<16xi32> @@ -139,7 +120,6 @@ module @multiCoreMixedFifo { func.call @some_work(%elem10) : (memref<16xi32>) -> () func.call @some_work(%elem11) : (memref<16xi32>) -> () aie.objectfifo.release @of (Consume, 2) - aie.end } } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/tileDMA_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/tileDMA_test.mlir index 30e9d1b48..a436d61be 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/tileDMA_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/tileDMA_test.mlir @@ -1,101 +1,91 @@ -//===- tileDMA_test.mlir --------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2022, Xilinx Inc. -// Copyright (C) 2022, Advanced Micro Devices, Inc. -// -// Date: September 22nd 2022 -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_1]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_1]], 0) {init = 0 : i32, sym_name = "objfifo_cons_lock_0"} -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_1]], 1) {init = 0 : i32, sym_name = "objfifo_cons_lock_1"} -// CHECK: %[[VAL_6:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> -// CHECK: %[[VAL_7:.*]] = aie.buffer(%[[VAL_0]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> -// CHECK: %[[VAL_8:.*]] = aie.lock(%[[VAL_0]], 3) {init = 0 : i32, sym_name = "objfifo_lock_0"} -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_0]], 4) {init = 0 : i32, sym_name = "objfifo_lock_1"} -// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_0]]) : memref<16xi32> -// CHECK: %[[VAL_11:.*]] = aie.lock(%[[VAL_0]], 0) -// CHECK: %[[VAL_12:.*]] = aie.buffer(%[[VAL_0]]) : memref<16xi32> -// CHECK: %[[VAL_13:.*]] = aie.lock(%[[VAL_0]], 1) -// CHECK: %[[VAL_14:.*]] = aie.buffer(%[[VAL_0]]) : memref<16xi32> -// CHECK: %[[VAL_15:.*]] = aie.lock(%[[VAL_0]], 2) -// CHECK: aie.flow(%[[VAL_0]], DMA : 1, %[[VAL_1]], DMA : 0) -// CHECK: func.func @some_work(%[[VAL_16:.*]]: memref<16xi32>) { +// CHECK: memref.global "public" @objfifo_cons : memref<16xi32> +// CHECK: memref.global "public" @objfifo : memref<16xi32> +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[OBJFIFO_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OBJFIFO_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_3_3]]) {sym_name = "objfifo_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OBJFIFO_CONS_LOCK_0:.*]] = aie.lock(%[[TILE_3_3]], 0) {init = 0 : i32, sym_name = "objfifo_cons_lock_0"} +// CHECK: %[[OBJFIFO_CONS_LOCK_1:.*]] = aie.lock(%[[TILE_3_3]], 1) {init = 0 : i32, sym_name = "objfifo_cons_lock_1"} +// CHECK: %[[OBJFIFO_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_0"} : memref<16xi32> +// CHECK: %[[OBJFIFO_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "objfifo_buff_1"} : memref<16xi32> +// CHECK: %[[OBJFIFO_LOCK_0:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "objfifo_lock_0"} +// CHECK: %[[OBJFIFO_LOCK_1:.*]] = aie.lock(%[[TILE_1_2]], 4) {init = 0 : i32, sym_name = "objfifo_lock_1"} +// CHECK: %[[BUFFER_1_2:.*]] = aie.buffer(%[[TILE_1_2]]) : memref<16xi32> +// CHECK: %[[LOCK_1_2:.*]] = aie.lock(%[[TILE_1_2]], 0) +// CHECK: %[[BUFFER_1_2_0:.*]] = aie.buffer(%[[TILE_1_2]]) : memref<16xi32> +// CHECK: %[[LOCK_1_2_1:.*]] = aie.lock(%[[TILE_1_2]], 1) +// CHECK: %[[BUFFER_1_2_2:.*]] = aie.buffer(%[[TILE_1_2]]) : memref<16xi32> +// CHECK: %[[LOCK_1_2_3:.*]] = aie.lock(%[[TILE_1_2]], 2) +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 1, %[[TILE_3_3]], DMA : 0) +// CHECK: func.func @some_work(%[[ARG0:.*]]: memref<16xi32>) { // CHECK: return // CHECK: } -// CHECK: %[[VAL_17:.*]] = aie.core(%[[VAL_0]]) { -// CHECK: %[[VAL_18:.*]] = arith.constant 0 : index -// CHECK: %[[VAL_19:.*]] = arith.constant 1 : index -// CHECK: %[[VAL_20:.*]] = arith.constant 12 : index -// CHECK: %[[VAL_21:.*]] = arith.constant 2 : index -// CHECK: scf.for %[[VAL_22:.*]] = %[[VAL_18]] to %[[VAL_20]] step %[[VAL_21]] { -// CHECK: aie.use_lock(%[[VAL_8]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_6]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_8]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: func.call @some_work(%[[VAL_7]]) : (memref<16xi32>) -> () -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: %[[CORE_1_2:.*]] = aie.core(%[[TILE_1_2]]) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C1:.*]] = arith.constant 1 : index +// CHECK: %[[C12:.*]] = arith.constant 12 : index +// CHECK: %[[C2:.*]] = arith.constant 2 : index +// CHECK: scf.for %[[ARG0:.*]] = %[[C0]] to %[[C12]] step %[[C2]] { +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Acquire, 0) +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_0]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Release, 1) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Acquire, 0) +// CHECK: func.call @some_work(%[[OBJFIFO_BUFF_1]]) : (memref<16xi32>) -> () +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Release, 1) // CHECK: } // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_23:.*]] = aie.mem(%[[VAL_0]]) { -// CHECK: %[[VAL_24:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_11]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_11]], Release, 0) +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[LOCK_1_2]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUFFER_1_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[LOCK_1_2]], Release, 0) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_13]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_12]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_13]], Release, 0) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[LOCK_1_2_1]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUFFER_1_2_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[LOCK_1_2_1]], Release, 0) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: %[[VAL_25:.*]] = aie.dma_start(S2MM, 0, ^bb4, ^bb5) -// CHECK: ^bb4: // 2 preds: ^bb3, ^bb4 -// CHECK: aie.use_lock(%[[VAL_15]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_14]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_15]], Release, 1) +// CHECK: ^bb3: +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb4, ^bb5) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[LOCK_1_2_3]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUFFER_1_2_2]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[LOCK_1_2_3]], Release, 1) // CHECK: aie.next_bd ^bb4 -// CHECK: ^bb5: // pred: ^bb3 -// CHECK: %[[VAL_26:.*]] = aie.dma_start(MM2S, 1, ^bb6, ^bb8) -// CHECK: ^bb6: // 2 preds: ^bb5, ^bb7 -// CHECK: aie.use_lock(%[[VAL_8]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_8]], Release, 0) +// CHECK: ^bb5: +// CHECK: %[[VAL_2:.*]] = aie.dma_start(MM2S, 1, ^bb6, ^bb8) +// CHECK: ^bb6: +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Acquire, 1) +// CHECK: aie.dma_bd(%[[OBJFIFO_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_0]], Release, 0) // CHECK: aie.next_bd ^bb7 -// CHECK: ^bb7: // pred: ^bb6 -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_7]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 0) +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Acquire, 1) +// CHECK: aie.dma_bd(%[[OBJFIFO_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_LOCK_1]], Release, 0) // CHECK: aie.next_bd ^bb6 -// CHECK: ^bb8: // pred: ^bb5 +// CHECK: ^bb8: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.mem(%[[VAL_1]]) { -// CHECK: %[[VAL_28:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%[[VAL_4]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_4]], Release, 1) +// CHECK: %[[MEM_3_3:.*]] = aie.mem(%[[TILE_3_3]]) { +// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OBJFIFO_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_0]], Release, 1) // CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[OBJFIFO_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OBJFIFO_CONS_LOCK_1]], Release, 1) // CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 +// CHECK: ^bb3: // CHECK: aie.end // CHECK: } // CHECK: } @@ -104,35 +94,28 @@ module @tileDMA_channels { aie.device(xcvc1902) { %tile12 = aie.tile(1, 2) %tile33 = aie.tile(3, 3) - %buff0 = aie.buffer(%tile12) : memref<16xi32> %lock0 = aie.lock(%tile12, 0) %buff1 = aie.buffer(%tile12) : memref<16xi32> %lock1 = aie.lock(%tile12, 1) %buff2 = aie.buffer(%tile12) : memref<16xi32> %lock2 = aie.lock(%tile12, 2) - aie.objectfifo @objfifo (%tile12, {%tile33}, 2 : i32) : !aie.objectfifo> - func.func @some_work(%lineOut : memref<16xi32>) -> () { return } - %core12 = aie.core(%tile12) { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %height = arith.constant 12 : index - scf.for %indexInHeight = %c0 to %height step %c1 { %subview = aie.objectfifo.acquire @objfifo (Produce, 1) : !aie.objectfifosubview> %elem0 = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview> -> memref<16xi32> func.call @some_work(%elem0) : (memref<16xi32>) -> () aie.objectfifo.release @objfifo (Produce, 1) } - aie.end } - %mem12 = aie.mem(%tile12) { %dma1 = aie.dma_start(MM2S, 0, ^bb1, ^bb3) ^bb1: diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_broadcast.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_broadcast.mlir index 56786ea30..afd7c6a54 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_broadcast.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_broadcast.mlir @@ -1,218 +1,209 @@ -//===- broadcast.mlir ------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_3:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_5:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_6:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_8:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_9:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_10:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_11:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_12:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_13:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_14:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_15:.*]] = aie.tile(8, 0) -// CHECK: %[[VAL_16:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_17:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_18:.*]] = aie.switchbox(%[[VAL_3]]) { +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) +// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) +// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) +// CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) +// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) +// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) +// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_19:.*]] = aie.switchbox(%[[VAL_6]]) { +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.shim_mux(%[[VAL_6]]) { +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_21:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_22:.*]] = aie.switchbox(%[[VAL_21]]) { +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_8]]) { +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_24]]) { +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_7]]) { +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.switchbox(%[[VAL_9]]) { +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_28:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_29:.*]] = aie.switchbox(%[[VAL_28]]) { +// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) +// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_31:.*]] = aie.switchbox(%[[VAL_30]]) { +// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) +// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_32:.*]] = aie.switchbox(%[[VAL_10]]) { +// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_34:.*]] = aie.switchbox(%[[VAL_33]]) { +// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) +// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_36:.*]] = aie.switchbox(%[[VAL_35]]) { +// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) +// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_37:.*]] = aie.switchbox(%[[VAL_11]]) { +// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_38:.*]] = aie.switchbox(%[[VAL_12]]) { +// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_39:.*]] = aie.switchbox(%[[VAL_13]]) { +// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_40:.*]] = aie.switchbox(%[[VAL_16]]) { +// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_42:.*]] = aie.switchbox(%[[VAL_41]]) { +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_43:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_44:.*]] = aie.switchbox(%[[VAL_4]]) { +// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_45:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_46:.*]] = aie.switchbox(%[[VAL_45]]) { +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_47:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_48:.*]] = aie.switchbox(%[[VAL_47]]) { +// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) +// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_49:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_50:.*]] = aie.switchbox(%[[VAL_49]]) { +// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) +// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_51:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_52:.*]] = aie.switchbox(%[[VAL_51]]) { +// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) +// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_53:.*]] = aie.shim_mux(%[[VAL_10]]) { +// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_54:.*]] = aie.switchbox(%[[VAL_14]]) { +// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_55:.*]] = aie.switchbox(%[[VAL_17]]) { +// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_41]] : Core, %[[VAL_56:.*]] : Core) -// CHECK: aie.wire(%[[VAL_41]] : DMA, %[[VAL_56]] : DMA) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_57:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_57]] : DMA) -// CHECK: aie.wire(%[[VAL_56]] : North, %[[VAL_57]] : South) -// CHECK: aie.wire(%[[VAL_56]] : East, %[[VAL_58:.*]] : West) -// CHECK: aie.wire(%[[VAL_4]] : Core, %[[VAL_58]] : Core) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_58]] : DMA) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_59:.*]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_59]] : DMA) -// CHECK: aie.wire(%[[VAL_60:.*]] : North, %[[VAL_61:.*]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_60]] : DMA) -// CHECK: aie.wire(%[[VAL_58]] : East, %[[VAL_62:.*]] : West) -// CHECK: aie.wire(%[[VAL_21]] : Core, %[[VAL_62]] : Core) -// CHECK: aie.wire(%[[VAL_21]] : DMA, %[[VAL_62]] : DMA) -// CHECK: aie.wire(%[[VAL_61]] : North, %[[VAL_62]] : South) -// CHECK: aie.wire(%[[VAL_8]] : Core, %[[VAL_63:.*]] : Core) -// CHECK: aie.wire(%[[VAL_8]] : DMA, %[[VAL_63]] : DMA) -// CHECK: aie.wire(%[[VAL_62]] : North, %[[VAL_63]] : South) -// CHECK: aie.wire(%[[VAL_59]] : East, %[[VAL_64:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_64]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_64]] : DMA) -// CHECK: aie.wire(%[[VAL_63]] : North, %[[VAL_64]] : South) -// CHECK: aie.wire(%[[VAL_61]] : East, %[[VAL_65:.*]] : West) -// CHECK: aie.wire(%[[VAL_62]] : East, %[[VAL_66:.*]] : West) -// CHECK: aie.wire(%[[VAL_9]] : Core, %[[VAL_66]] : Core) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_66]] : DMA) -// CHECK: aie.wire(%[[VAL_65]] : North, %[[VAL_66]] : South) -// CHECK: aie.wire(%[[VAL_63]] : East, %[[VAL_67:.*]] : West) -// CHECK: aie.wire(%[[VAL_45]] : Core, %[[VAL_67]] : Core) -// CHECK: aie.wire(%[[VAL_45]] : DMA, %[[VAL_67]] : DMA) -// CHECK: aie.wire(%[[VAL_66]] : North, %[[VAL_67]] : South) -// CHECK: aie.wire(%[[VAL_65]] : East, %[[VAL_68:.*]] : West) -// CHECK: aie.wire(%[[VAL_66]] : East, %[[VAL_69:.*]] : West) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_69]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_69]] : DMA) -// CHECK: aie.wire(%[[VAL_68]] : North, %[[VAL_69]] : South) -// CHECK: aie.wire(%[[VAL_67]] : East, %[[VAL_70:.*]] : West) -// CHECK: aie.wire(%[[VAL_49]] : Core, %[[VAL_70]] : Core) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_70]] : DMA) -// CHECK: aie.wire(%[[VAL_69]] : North, %[[VAL_70]] : South) -// CHECK: aie.wire(%[[VAL_68]] : East, %[[VAL_71:.*]] : West) -// CHECK: aie.wire(%[[VAL_69]] : East, %[[VAL_72:.*]] : West) -// CHECK: aie.wire(%[[VAL_51]] : Core, %[[VAL_72]] : Core) -// CHECK: aie.wire(%[[VAL_51]] : DMA, %[[VAL_72]] : DMA) -// CHECK: aie.wire(%[[VAL_71]] : North, %[[VAL_72]] : South) -// CHECK: aie.wire(%[[VAL_71]] : East, %[[VAL_73:.*]] : West) -// CHECK: aie.wire(%[[VAL_74:.*]] : North, %[[VAL_73]] : South) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_74]] : DMA) -// CHECK: aie.wire(%[[VAL_72]] : East, %[[VAL_75:.*]] : West) -// CHECK: aie.wire(%[[VAL_33]] : Core, %[[VAL_75]] : Core) -// CHECK: aie.wire(%[[VAL_33]] : DMA, %[[VAL_75]] : DMA) -// CHECK: aie.wire(%[[VAL_73]] : North, %[[VAL_75]] : South) -// CHECK: aie.wire(%[[VAL_35]] : Core, %[[VAL_76:.*]] : Core) -// CHECK: aie.wire(%[[VAL_35]] : DMA, %[[VAL_76]] : DMA) -// CHECK: aie.wire(%[[VAL_75]] : North, %[[VAL_76]] : South) -// CHECK: aie.wire(%[[VAL_73]] : East, %[[VAL_77:.*]] : West) -// CHECK: aie.wire(%[[VAL_75]] : East, %[[VAL_78:.*]] : West) -// CHECK: aie.wire(%[[VAL_12]] : Core, %[[VAL_78]] : Core) -// CHECK: aie.wire(%[[VAL_12]] : DMA, %[[VAL_78]] : DMA) -// CHECK: aie.wire(%[[VAL_77]] : North, %[[VAL_78]] : South) -// CHECK: aie.wire(%[[VAL_76]] : East, %[[VAL_79:.*]] : West) -// CHECK: aie.wire(%[[VAL_13]] : Core, %[[VAL_79]] : Core) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_79]] : DMA) -// CHECK: aie.wire(%[[VAL_78]] : North, %[[VAL_79]] : South) -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_80:.*]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_80]] : DMA) -// CHECK: aie.wire(%[[VAL_79]] : North, %[[VAL_80]] : South) -// CHECK: aie.wire(%[[VAL_79]] : East, %[[VAL_81:.*]] : West) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_81]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_81]] : DMA) -// CHECK: aie.wire(%[[VAL_80]] : East, %[[VAL_82:.*]] : West) -// CHECK: aie.wire(%[[VAL_17]] : Core, %[[VAL_82]] : Core) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_82]] : DMA) -// CHECK: aie.wire(%[[VAL_81]] : North, %[[VAL_82]] : South) +// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) +// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) +// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) +// CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : East, %[[SWITCHBOX_2_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3]] : Core) +// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) +// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : North, %[[SWITCHBOX_4_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) +// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : East, %[[SWITCHBOX_5_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) +// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : North, %[[SWITCHBOX_5_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) +// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) +// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) +// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) +// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) +// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) +// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) +// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) +// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) // CHECK: } module { @@ -235,16 +226,13 @@ module { %t80 = aie.tile(8, 0) %t82 = aie.tile(8, 2) %t83 = aie.tile(8, 3) - aie.flow(%t20, DMA : 0, %t13, DMA : 0) aie.flow(%t20, DMA : 0, %t31, DMA : 0) aie.flow(%t20, DMA : 0, %t71, DMA : 0) aie.flow(%t20, DMA : 0, %t82, DMA : 0) - aie.flow(%t60, DMA : 0, %t02, DMA : 1) aie.flow(%t60, DMA : 0, %t83, DMA : 1) aie.flow(%t60, DMA : 0, %t22, DMA : 1) aie.flow(%t60, DMA : 0, %t31, DMA : 1) } } - diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_fixed_connections.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_fixed_connections.mlir index 3a1c73069..aad54dea2 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_fixed_connections.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_fixed_connections.mlir @@ -1,37 +1,30 @@ -//===- flow_test_1.mlir ----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows --split-input-file %s | FileCheck %s -// CHECK: %tile_2_0 = aie.tile(2, 0) -// CHECK: %tile_3_0 = aie.tile(3, 0) -// CHECK: %tile_6_0 = aie.tile(6, 0) -// CHECK: %tile_7_0 = aie.tile(7, 0) -// CHECK: %switchbox_2_0 = aie.switchbox(%tile_2_0) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_3_0 = aie.switchbox(%tile_3_0) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_6_0 = aie.switchbox(%tile_6_0) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_7_0 = aie.switchbox(%tile_7_0) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%switchbox_2_0 : East, %switchbox_3_0 : West) -// CHECK: aie.wire(%switchbox_6_0 : East, %switchbox_7_0 : West) +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: aie.wire(%[[SWITCHBOX_2_0:.*]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_6_0:.*]] : East, %[[SWITCHBOX_7_0:.*]] : West) +// CHECK: } module { aie.device(xcvc1902) { @@ -39,7 +32,6 @@ module { %tile_3_0 = aie.tile(3, 0) %tile_6_0 = aie.tile(6, 0) %tile_7_0 = aie.tile(7, 0) - %switchbox_2_0 = aie.switchbox(%tile_2_0) { aie.connect aie.connect @@ -61,72 +53,74 @@ module { // ----- -// CHECK: %tile_0_3 = aie.tile(0, 3) -// CHECK: %tile_1_4 = aie.tile(1, 4) -// CHECK: %tile_3_3 = aie.tile(3, 3) -// CHECK: %tile_4_2 = aie.tile(4, 2) -// CHECK: %tile_5_3 = aie.tile(5, 3) -// CHECK: %tile_6_3 = aie.tile(6, 3) -// CHECK: %tile_7_4 = aie.tile(7, 4) -// CHECK: %tile_9_2 = aie.tile(9, 2) -// CHECK: %tile_10_2 = aie.tile(10, 2) -// CHECK: %tile_11_3 = aie.tile(11, 3) -// CHECK: %switchbox_0_3 = aie.switchbox(%tile_0_3) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_1_4 = aie.switchbox(%tile_1_4) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_3_3 = aie.switchbox(%tile_3_3) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_4_2 = aie.switchbox(%tile_4_2) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_5_3 = aie.switchbox(%tile_5_3) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_6_3 = aie.switchbox(%tile_6_3) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_7_4 = aie.switchbox(%tile_7_4) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_9_2 = aie.switchbox(%tile_9_2) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_10_2 = aie.switchbox(%tile_10_2) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_11_3 = aie.switchbox(%tile_11_3) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%tile_0_3 : Core, %switchbox_0_3 : Core) -// CHECK: aie.wire(%tile_0_3 : DMA, %switchbox_0_3 : DMA) -// CHECK: aie.wire(%tile_1_4 : Core, %switchbox_1_4 : Core) -// CHECK: aie.wire(%tile_1_4 : DMA, %switchbox_1_4 : DMA) -// CHECK: aie.wire(%tile_3_3 : Core, %switchbox_3_3 : Core) -// CHECK: aie.wire(%tile_3_3 : DMA, %switchbox_3_3 : DMA) -// CHECK: aie.wire(%tile_4_2 : Core, %switchbox_4_2 : Core) -// CHECK: aie.wire(%tile_4_2 : DMA, %switchbox_4_2 : DMA) -// CHECK: aie.wire(%tile_5_3 : Core, %switchbox_5_3 : Core) -// CHECK: aie.wire(%tile_5_3 : DMA, %switchbox_5_3 : DMA) -// CHECK: aie.wire(%switchbox_5_3 : East, %switchbox_6_3 : West) -// CHECK: aie.wire(%tile_6_3 : Core, %switchbox_6_3 : Core) -// CHECK: aie.wire(%tile_6_3 : DMA, %switchbox_6_3 : DMA) -// CHECK: aie.wire(%tile_7_4 : Core, %switchbox_7_4 : Core) -// CHECK: aie.wire(%tile_7_4 : DMA, %switchbox_7_4 : DMA) -// CHECK: aie.wire(%tile_9_2 : Core, %switchbox_9_2 : Core) -// CHECK: aie.wire(%tile_9_2 : DMA, %switchbox_9_2 : DMA) -// CHECK: aie.wire(%switchbox_9_2 : East, %switchbox_10_2 : West) -// CHECK: aie.wire(%tile_10_2 : Core, %switchbox_10_2 : Core) -// CHECK: aie.wire(%tile_10_2 : DMA, %switchbox_10_2 : DMA) -// CHECK: aie.wire(%tile_11_3 : Core, %switchbox_11_3 : Core) -// CHECK: aie.wire(%tile_11_3 : DMA, %switchbox_11_3 : DMA) +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_1_4:.*]] = aie.tile(1, 4) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) +// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) +// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) +// CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) +// CHECK: %[[TILE_9_2:.*]] = aie.tile(9, 2) +// CHECK: %[[TILE_10_2:.*]] = aie.tile(10, 2) +// CHECK: %[[TILE_11_3:.*]] = aie.tile(11, 3) +// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_9_2:.*]] = aie.switchbox(%[[TILE_9_2]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_10_2:.*]] = aie.switchbox(%[[TILE_10_2]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_11_3:.*]] = aie.switchbox(%[[TILE_11_3]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) +// CHECK: aie.wire(%[[TILE_1_4]] : Core, %[[SWITCHBOX_1_4:.*]] : Core) +// CHECK: aie.wire(%[[TILE_1_4]] : DMA, %[[SWITCHBOX_1_4]] : DMA) +// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) +// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) +// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) +// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) +// CHECK: aie.wire(%[[TILE_7_4]] : Core, %[[SWITCHBOX_7_4:.*]] : Core) +// CHECK: aie.wire(%[[TILE_7_4]] : DMA, %[[SWITCHBOX_7_4]] : DMA) +// CHECK: aie.wire(%[[TILE_9_2]] : Core, %[[SWITCHBOX_9_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_9_2]] : DMA, %[[SWITCHBOX_9_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : East, %[[SWITCHBOX_10_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_2]] : Core, %[[SWITCHBOX_10_2]] : Core) +// CHECK: aie.wire(%[[TILE_10_2]] : DMA, %[[SWITCHBOX_10_2]] : DMA) +// CHECK: aie.wire(%[[TILE_11_3]] : Core, %[[SWITCHBOX_11_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_11_3]] : DMA, %[[SWITCHBOX_11_3]] : DMA) +// CHECK: } module { aie.device(xcvc1902) { @@ -140,7 +134,6 @@ module { %tile_9_2 = aie.tile(9, 2) %tile_10_2 = aie.tile(10, 2) %tile_11_3 = aie.tile(11, 3) - %switchbox_0_3 = aie.switchbox(%tile_0_3) { aie.connect aie.connect @@ -180,48 +173,50 @@ module { // ----- -// CHECK: %tile_2_5 = aie.tile(2, 5) -// CHECK: %tile_3_1 = aie.tile(3, 1) -// CHECK: %tile_6_6 = aie.tile(6, 6) -// CHECK: %tile_7_3 = aie.tile(7, 3) -// CHECK: %tile_12_5 = aie.tile(12, 5) -// CHECK: %tile_13_3 = aie.tile(13, 3) -// CHECK: %switchbox_2_5 = aie.switchbox(%tile_2_5) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_3_1 = aie.switchbox(%tile_3_1) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_6_6 = aie.switchbox(%tile_6_6) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_7_3 = aie.switchbox(%tile_7_3) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_12_5 = aie.switchbox(%tile_12_5) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_13_3 = aie.switchbox(%tile_13_3) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: aie.wire(%tile_2_5 : Core, %switchbox_2_5 : Core) -// CHECK: aie.wire(%tile_2_5 : DMA, %switchbox_2_5 : DMA) -// CHECK: aie.wire(%tile_3_1 : Core, %switchbox_3_1 : Core) -// CHECK: aie.wire(%tile_3_1 : DMA, %switchbox_3_1 : DMA) -// CHECK: aie.wire(%tile_6_6 : Core, %switchbox_6_6 : Core) -// CHECK: aie.wire(%tile_6_6 : DMA, %switchbox_6_6 : DMA) -// CHECK: aie.wire(%tile_7_3 : Core, %switchbox_7_3 : Core) -// CHECK: aie.wire(%tile_7_3 : DMA, %switchbox_7_3 : DMA) -// CHECK: aie.wire(%tile_12_5 : Core, %switchbox_12_5 : Core) -// CHECK: aie.wire(%tile_12_5 : DMA, %switchbox_12_5 : DMA) -// CHECK: aie.wire(%tile_13_3 : Core, %switchbox_13_3 : Core) -// CHECK: aie.wire(%tile_13_3 : DMA, %switchbox_13_3 : DMA) +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: %[[TILE_2_5:.*]] = aie.tile(2, 5) +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[TILE_6_6:.*]] = aie.tile(6, 6) +// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) +// CHECK: %[[TILE_12_5:.*]] = aie.tile(12, 5) +// CHECK: %[[TILE_13_3:.*]] = aie.tile(13, 3) +// CHECK: %[[SWITCHBOX_2_5:.*]] = aie.switchbox(%[[TILE_2_5]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_6_6:.*]] = aie.switchbox(%[[TILE_6_6]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_12_5:.*]] = aie.switchbox(%[[TILE_12_5]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_13_3:.*]] = aie.switchbox(%[[TILE_13_3]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: aie.wire(%[[TILE_2_5]] : Core, %[[SWITCHBOX_2_5:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_5]] : DMA, %[[SWITCHBOX_2_5]] : DMA) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) +// CHECK: aie.wire(%[[TILE_6_6]] : Core, %[[SWITCHBOX_6_6:.*]] : Core) +// CHECK: aie.wire(%[[TILE_6_6]] : DMA, %[[SWITCHBOX_6_6]] : DMA) +// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) +// CHECK: aie.wire(%[[TILE_12_5]] : Core, %[[SWITCHBOX_12_5:.*]] : Core) +// CHECK: aie.wire(%[[TILE_12_5]] : DMA, %[[SWITCHBOX_12_5]] : DMA) +// CHECK: aie.wire(%[[TILE_13_3]] : Core, %[[SWITCHBOX_13_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_13_3]] : DMA, %[[SWITCHBOX_13_3]] : DMA) +// CHECK: } module { aie.device(xcvc1902) { @@ -231,7 +226,6 @@ module { %tile_7_3 = aie.tile(7, 3) %tile_12_5 = aie.tile(12, 5) %tile_13_3 = aie.tile(13, 3) - %switchbox_2_5 = aie.switchbox(%tile_2_5) { aie.connect aie.connect diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_1.mlir index f2cf91bbc..f94d1995f 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_1.mlir @@ -1,60 +1,51 @@ -//===- flow_test_1.mlir ----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_2:.*]] = aie.tile(3, 4) -// CHECK: %[[VAL_3:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(4, 4) -// CHECK: %[[VAL_5:.*]] = aie.tile(5, 4) -// CHECK: %[[VAL_6:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_8:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_10:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_11:.*]] = aie.tile(8, 4) -// CHECK: %[[VAL_12:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) +// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) +// CHECK: %[[TILE_4_4:.*]] = aie.tile(4, 4) +// CHECK: %[[TILE_5_4:.*]] = aie.tile(5, 4) +// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) +// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) +// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) +// CHECK: %[[TILE_8_4:.*]] = aie.tile(8, 4) +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_13:.*]] = aie.shim_mux(%[[VAL_0]]) { +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_14:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_15:.*]] = aie.switchbox(%[[VAL_14]]) { +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_16:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_17:.*]] = aie.switchbox(%[[VAL_16]]) { +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_18:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_19:.*]] = aie.switchbox(%[[VAL_18]]) { +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_21:.*]] = aie.switchbox(%[[VAL_20]]) { +// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) +// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -63,8 +54,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_22:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_22]]) { +// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) +// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -73,8 +64,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_24]]) { +// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) +// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -87,7 +78,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_7]]) { +// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -99,8 +90,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_27]]) { +// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) +// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -109,7 +100,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.switchbox(%[[VAL_10]]) { +// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -118,7 +109,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -126,27 +117,27 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.shim_mux(%[[VAL_1]]) { +// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_32:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_33:.*]] = aie.switchbox(%[[VAL_32]]) { +// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) +// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_34:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_35:.*]] = aie.switchbox(%[[VAL_34]]) { +// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) +// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_36:.*]] = aie.switchbox(%[[VAL_6]]) { +// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -154,22 +145,22 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_37:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_38:.*]] = aie.switchbox(%[[VAL_37]]) { +// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) +// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_39:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_40:.*]] = aie.switchbox(%[[VAL_39]]) { +// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) +// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.switchbox(%[[VAL_9]]) { +// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -177,13 +168,13 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_42:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_43:.*]] = aie.switchbox(%[[VAL_42]]) { +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_44:.*]] = aie.switchbox(%[[VAL_5]]) { +// CHECK: %[[SWITCHBOX_5_4:.*]] = aie.switchbox(%[[TILE_5_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -192,13 +183,13 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_45:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_46:.*]] = aie.switchbox(%[[VAL_4]]) { +// CHECK: %[[SWITCHBOX_4_4:.*]] = aie.switchbox(%[[TILE_4_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -207,18 +198,18 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_47:.*]] = aie.tile(6, 4) -// CHECK: %[[VAL_48:.*]] = aie.switchbox(%[[VAL_47]]) { +// CHECK: %[[TILE_6_4:.*]] = aie.tile(6, 4) +// CHECK: %[[SWITCHBOX_6_4:.*]] = aie.switchbox(%[[TILE_6_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_49:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_50:.*]] = aie.switchbox(%[[VAL_49]]) { +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_51:.*]] = aie.switchbox(%[[VAL_3]]) { +// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -229,8 +220,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_52:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_53:.*]] = aie.switchbox(%[[VAL_52]]) { +// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) +// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -238,170 +229,170 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_54:.*]] = aie.switchbox(%[[VAL_8]]) { +// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_55:.*]] = aie.shim_mux(%[[VAL_8]]) { +// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_56:.*]] = aie.tile(7, 4) -// CHECK: %[[VAL_57:.*]] = aie.switchbox(%[[VAL_56]]) { +// CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) +// CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_58:.*]] = aie.switchbox(%[[VAL_11]]) { +// CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_59:.*]] = aie.shim_mux(%[[VAL_6]]) { +// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_60:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_61:.*]] = aie.switchbox(%[[VAL_60]]) { +// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) +// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_62:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_63:.*]] = aie.switchbox(%[[VAL_62]]) { +// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) +// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_64:.*]] = aie.tile(8, 0) -// CHECK: %[[VAL_65:.*]] = aie.switchbox(%[[VAL_64]]) { +// CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) +// CHECK: %[[SWITCHBOX_8_0:.*]] = aie.switchbox(%[[TILE_8_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_66:.*]] = aie.tile(8, 1) -// CHECK: %[[VAL_67:.*]] = aie.switchbox(%[[VAL_66]]) { +// CHECK: %[[TILE_8_1:.*]] = aie.tile(8, 1) +// CHECK: %[[SWITCHBOX_8_1:.*]] = aie.switchbox(%[[TILE_8_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_68:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_69:.*]] = aie.switchbox(%[[VAL_68]]) { +// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) +// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_70:.*]] : North, %[[VAL_71:.*]] : South) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_70]] : DMA) -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_72:.*]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_72]] : DMA) -// CHECK: aie.wire(%[[VAL_71]] : North, %[[VAL_72]] : South) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_73:.*]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_73]] : DMA) -// CHECK: aie.wire(%[[VAL_72]] : North, %[[VAL_73]] : South) -// CHECK: aie.wire(%[[VAL_71]] : East, %[[VAL_74:.*]] : West) -// CHECK: aie.wire(%[[VAL_75:.*]] : North, %[[VAL_74]] : South) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_75]] : DMA) -// CHECK: aie.wire(%[[VAL_72]] : East, %[[VAL_76:.*]] : West) -// CHECK: aie.wire(%[[VAL_42]] : Core, %[[VAL_76]] : Core) -// CHECK: aie.wire(%[[VAL_42]] : DMA, %[[VAL_76]] : DMA) -// CHECK: aie.wire(%[[VAL_74]] : North, %[[VAL_76]] : South) -// CHECK: aie.wire(%[[VAL_73]] : East, %[[VAL_77:.*]] : West) -// CHECK: aie.wire(%[[VAL_18]] : Core, %[[VAL_77]] : Core) -// CHECK: aie.wire(%[[VAL_18]] : DMA, %[[VAL_77]] : DMA) -// CHECK: aie.wire(%[[VAL_76]] : North, %[[VAL_77]] : South) -// CHECK: aie.wire(%[[VAL_49]] : Core, %[[VAL_78:.*]] : Core) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_78]] : DMA) -// CHECK: aie.wire(%[[VAL_77]] : North, %[[VAL_78]] : South) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_79:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_79]] : DMA) -// CHECK: aie.wire(%[[VAL_78]] : North, %[[VAL_79]] : South) -// CHECK: aie.wire(%[[VAL_74]] : East, %[[VAL_80:.*]] : West) -// CHECK: aie.wire(%[[VAL_76]] : East, %[[VAL_81:.*]] : West) -// CHECK: aie.wire(%[[VAL_60]] : Core, %[[VAL_81]] : Core) -// CHECK: aie.wire(%[[VAL_60]] : DMA, %[[VAL_81]] : DMA) -// CHECK: aie.wire(%[[VAL_80]] : North, %[[VAL_81]] : South) -// CHECK: aie.wire(%[[VAL_77]] : East, %[[VAL_82:.*]] : West) -// CHECK: aie.wire(%[[VAL_20]] : Core, %[[VAL_82]] : Core) -// CHECK: aie.wire(%[[VAL_20]] : DMA, %[[VAL_82]] : DMA) -// CHECK: aie.wire(%[[VAL_81]] : North, %[[VAL_82]] : South) -// CHECK: aie.wire(%[[VAL_78]] : East, %[[VAL_83:.*]] : West) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_83]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_83]] : DMA) -// CHECK: aie.wire(%[[VAL_82]] : North, %[[VAL_83]] : South) -// CHECK: aie.wire(%[[VAL_79]] : East, %[[VAL_84:.*]] : West) -// CHECK: aie.wire(%[[VAL_4]] : Core, %[[VAL_84]] : Core) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_84]] : DMA) -// CHECK: aie.wire(%[[VAL_83]] : North, %[[VAL_84]] : South) -// CHECK: aie.wire(%[[VAL_80]] : East, %[[VAL_85:.*]] : West) -// CHECK: aie.wire(%[[VAL_81]] : East, %[[VAL_86:.*]] : West) -// CHECK: aie.wire(%[[VAL_52]] : Core, %[[VAL_86]] : Core) -// CHECK: aie.wire(%[[VAL_52]] : DMA, %[[VAL_86]] : DMA) -// CHECK: aie.wire(%[[VAL_85]] : North, %[[VAL_86]] : South) -// CHECK: aie.wire(%[[VAL_82]] : East, %[[VAL_87:.*]] : West) -// CHECK: aie.wire(%[[VAL_22]] : Core, %[[VAL_87]] : Core) -// CHECK: aie.wire(%[[VAL_22]] : DMA, %[[VAL_87]] : DMA) -// CHECK: aie.wire(%[[VAL_86]] : North, %[[VAL_87]] : South) -// CHECK: aie.wire(%[[VAL_83]] : East, %[[VAL_88:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_88]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_88]] : DMA) -// CHECK: aie.wire(%[[VAL_87]] : North, %[[VAL_88]] : South) -// CHECK: aie.wire(%[[VAL_84]] : East, %[[VAL_89:.*]] : West) -// CHECK: aie.wire(%[[VAL_5]] : Core, %[[VAL_89]] : Core) -// CHECK: aie.wire(%[[VAL_5]] : DMA, %[[VAL_89]] : DMA) -// CHECK: aie.wire(%[[VAL_88]] : North, %[[VAL_89]] : South) -// CHECK: aie.wire(%[[VAL_85]] : East, %[[VAL_90:.*]] : West) -// CHECK: aie.wire(%[[VAL_91:.*]] : North, %[[VAL_90]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_91]] : DMA) -// CHECK: aie.wire(%[[VAL_86]] : East, %[[VAL_92:.*]] : West) -// CHECK: aie.wire(%[[VAL_37]] : Core, %[[VAL_92]] : Core) -// CHECK: aie.wire(%[[VAL_37]] : DMA, %[[VAL_92]] : DMA) -// CHECK: aie.wire(%[[VAL_90]] : North, %[[VAL_92]] : South) -// CHECK: aie.wire(%[[VAL_87]] : East, %[[VAL_93:.*]] : West) -// CHECK: aie.wire(%[[VAL_39]] : Core, %[[VAL_93]] : Core) -// CHECK: aie.wire(%[[VAL_39]] : DMA, %[[VAL_93]] : DMA) -// CHECK: aie.wire(%[[VAL_92]] : North, %[[VAL_93]] : South) -// CHECK: aie.wire(%[[VAL_88]] : East, %[[VAL_94:.*]] : West) -// CHECK: aie.wire(%[[VAL_7]] : Core, %[[VAL_94]] : Core) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_94]] : DMA) -// CHECK: aie.wire(%[[VAL_93]] : North, %[[VAL_94]] : South) -// CHECK: aie.wire(%[[VAL_89]] : East, %[[VAL_95:.*]] : West) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_95]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_95]] : DMA) -// CHECK: aie.wire(%[[VAL_94]] : North, %[[VAL_95]] : South) -// CHECK: aie.wire(%[[VAL_90]] : East, %[[VAL_96:.*]] : West) -// CHECK: aie.wire(%[[VAL_97:.*]] : North, %[[VAL_96]] : South) -// CHECK: aie.wire(%[[VAL_8]] : DMA, %[[VAL_97]] : DMA) -// CHECK: aie.wire(%[[VAL_92]] : East, %[[VAL_98:.*]] : West) -// CHECK: aie.wire(%[[VAL_62]] : Core, %[[VAL_98]] : Core) -// CHECK: aie.wire(%[[VAL_62]] : DMA, %[[VAL_98]] : DMA) -// CHECK: aie.wire(%[[VAL_96]] : North, %[[VAL_98]] : South) -// CHECK: aie.wire(%[[VAL_93]] : East, %[[VAL_99:.*]] : West) -// CHECK: aie.wire(%[[VAL_9]] : Core, %[[VAL_99]] : Core) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_99]] : DMA) -// CHECK: aie.wire(%[[VAL_98]] : North, %[[VAL_99]] : South) -// CHECK: aie.wire(%[[VAL_94]] : East, %[[VAL_100:.*]] : West) -// CHECK: aie.wire(%[[VAL_27]] : Core, %[[VAL_100]] : Core) -// CHECK: aie.wire(%[[VAL_27]] : DMA, %[[VAL_100]] : DMA) -// CHECK: aie.wire(%[[VAL_99]] : North, %[[VAL_100]] : South) -// CHECK: aie.wire(%[[VAL_95]] : East, %[[VAL_101:.*]] : West) -// CHECK: aie.wire(%[[VAL_56]] : Core, %[[VAL_101]] : Core) -// CHECK: aie.wire(%[[VAL_56]] : DMA, %[[VAL_101]] : DMA) -// CHECK: aie.wire(%[[VAL_100]] : North, %[[VAL_101]] : South) -// CHECK: aie.wire(%[[VAL_96]] : East, %[[VAL_102:.*]] : West) -// CHECK: aie.wire(%[[VAL_98]] : East, %[[VAL_103:.*]] : West) -// CHECK: aie.wire(%[[VAL_66]] : Core, %[[VAL_103]] : Core) -// CHECK: aie.wire(%[[VAL_66]] : DMA, %[[VAL_103]] : DMA) -// CHECK: aie.wire(%[[VAL_102]] : North, %[[VAL_103]] : South) -// CHECK: aie.wire(%[[VAL_99]] : East, %[[VAL_104:.*]] : West) -// CHECK: aie.wire(%[[VAL_68]] : Core, %[[VAL_104]] : Core) -// CHECK: aie.wire(%[[VAL_68]] : DMA, %[[VAL_104]] : DMA) -// CHECK: aie.wire(%[[VAL_103]] : North, %[[VAL_104]] : South) -// CHECK: aie.wire(%[[VAL_100]] : East, %[[VAL_105:.*]] : West) -// CHECK: aie.wire(%[[VAL_10]] : Core, %[[VAL_105]] : Core) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_105]] : DMA) -// CHECK: aie.wire(%[[VAL_104]] : North, %[[VAL_105]] : South) -// CHECK: aie.wire(%[[VAL_101]] : East, %[[VAL_106:.*]] : West) -// CHECK: aie.wire(%[[VAL_11]] : Core, %[[VAL_106]] : Core) -// CHECK: aie.wire(%[[VAL_11]] : DMA, %[[VAL_106]] : DMA) -// CHECK: aie.wire(%[[VAL_105]] : North, %[[VAL_106]] : South) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) +// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) +// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) +// CHECK: aie.wire(%[[TILE_3_4]] : Core, %[[SWITCHBOX_3_4:.*]] : Core) +// CHECK: aie.wire(%[[TILE_3_4]] : DMA, %[[SWITCHBOX_3_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : North, %[[SWITCHBOX_3_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) +// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : North, %[[SWITCHBOX_4_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) +// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) +// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : North, %[[SWITCHBOX_4_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_4]] : East, %[[SWITCHBOX_4_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_4]] : Core, %[[SWITCHBOX_4_4]] : Core) +// CHECK: aie.wire(%[[TILE_4_4]] : DMA, %[[SWITCHBOX_4_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : North, %[[SWITCHBOX_4_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : East, %[[SWITCHBOX_5_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) +// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : North, %[[SWITCHBOX_5_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) +// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) +// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_4]] : East, %[[SWITCHBOX_5_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_4]] : Core, %[[SWITCHBOX_5_4]] : Core) +// CHECK: aie.wire(%[[TILE_5_4]] : DMA, %[[SWITCHBOX_5_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : North, %[[SWITCHBOX_5_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) +// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) +// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) +// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) +// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_4]] : East, %[[SWITCHBOX_6_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_4]] : Core, %[[SWITCHBOX_6_4]] : Core) +// CHECK: aie.wire(%[[TILE_6_4]] : DMA, %[[SWITCHBOX_6_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : North, %[[SWITCHBOX_6_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) +// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) +// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) +// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) +// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_4]] : East, %[[SWITCHBOX_7_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_4]] : Core, %[[SWITCHBOX_7_4]] : Core) +// CHECK: aie.wire(%[[TILE_7_4]] : DMA, %[[SWITCHBOX_7_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : North, %[[SWITCHBOX_7_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : East, %[[SWITCHBOX_8_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : East, %[[SWITCHBOX_8_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_1]] : Core, %[[SWITCHBOX_8_1]] : Core) +// CHECK: aie.wire(%[[TILE_8_1]] : DMA, %[[SWITCHBOX_8_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_0]] : North, %[[SWITCHBOX_8_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) +// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : North, %[[SWITCHBOX_8_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) +// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : East, %[[SWITCHBOX_8_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_4]] : Core, %[[SWITCHBOX_8_4]] : Core) +// CHECK: aie.wire(%[[TILE_8_4]] : DMA, %[[SWITCHBOX_8_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : North, %[[SWITCHBOX_8_4]] : South) // CHECK: } module { @@ -418,32 +409,26 @@ module { %t72 = aie.tile(7, 2) %t83 = aie.tile(8, 3) %t84 = aie.tile(8, 4) - aie.flow(%t20, DMA : 0, %t63, DMA : 0) aie.flow(%t20, DMA : 1, %t83, DMA : 0) aie.flow(%t30, DMA : 0, %t72, DMA : 0) aie.flow(%t30, DMA : 1, %t54, DMA : 0) - aie.flow(%t34, Core : 0, %t63, Core : 1) aie.flow(%t34, DMA : 1, %t70, DMA : 0) aie.flow(%t43, Core : 0, %t84, Core : 1) aie.flow(%t43, DMA : 1, %t60, DMA : 1) - aie.flow(%t44, Core : 0, %t54, Core : 1) aie.flow(%t44, DMA : 1, %t60, DMA : 0) aie.flow(%t54, Core : 0, %t43, Core : 1) aie.flow(%t54, DMA : 1, %t30, DMA : 1) - aie.flow(%t60, DMA : 0, %t44, DMA : 0) aie.flow(%t60, DMA : 1, %t43, DMA : 0) aie.flow(%t63, Core : 0, %t34, Core : 1) aie.flow(%t63, DMA : 1, %t20, DMA : 1) - aie.flow(%t70, DMA : 0, %t34, DMA : 0) aie.flow(%t70, DMA : 1, %t84, DMA : 0) aie.flow(%t72, Core : 0, %t83, Core : 1) aie.flow(%t72, DMA : 1, %t30, DMA : 0) - aie.flow(%t83, Core : 0, %t44, Core : 1) aie.flow(%t83, DMA : 1, %t20, DMA : 0) aie.flow(%t84, Core : 0, %t72, Core : 1) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_2.mlir index f8e19ac9e..9b42d358f 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_2.mlir @@ -1,45 +1,36 @@ -//===- flow_test_2.mlir ----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_3:.*]] = aie.tile(0, 4) -// CHECK: %[[VAL_4:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_5:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_6:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_7:.*]] = aie.tile(1, 4) -// CHECK: %[[VAL_8:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_10:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_11:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_12:.*]] = aie.tile(2, 4) -// CHECK: %[[VAL_13:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_14:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_15:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_16:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_17:.*]] = aie.tile(3, 4) -// CHECK: %[[VAL_18:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_19:.*]] = aie.switchbox(%[[VAL_18]]) { +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_0_4:.*]] = aie.tile(0, 4) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_1_4:.*]] = aie.tile(1, 4) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_2_4:.*]] = aie.tile(2, 4) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.switchbox(%[[VAL_4]]) { +// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_21:.*]] = aie.switchbox(%[[VAL_8]]) { +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -47,35 +38,35 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_22:.*]] = aie.shim_mux(%[[VAL_8]]) { +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_5]]) { +// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_9]]) { +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.switchbox(%[[VAL_10]]) { +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -83,11 +74,11 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_7]]) { +// CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.switchbox(%[[VAL_11]]) { +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -96,7 +87,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.switchbox(%[[VAL_12]]) { +// CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -104,37 +95,37 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.switchbox(%[[VAL_3]]) { +// CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_32:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.switchbox(%[[VAL_6]]) { +// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_34:.*]] = aie.switchbox(%[[VAL_13]]) { +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.shim_mux(%[[VAL_13]]) { +// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_36:.*]] = aie.switchbox(%[[VAL_15]]) { +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_37:.*]] = aie.switchbox(%[[VAL_16]]) { +// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -142,82 +133,82 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_38:.*]] = aie.switchbox(%[[VAL_17]]) { +// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_39:.*]] = aie.switchbox(%[[VAL_14]]) { +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_40:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_40]] : DMA) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_41:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_41]] : DMA) -// CHECK: aie.wire(%[[VAL_40]] : North, %[[VAL_41]] : South) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_42:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_42]] : DMA) -// CHECK: aie.wire(%[[VAL_41]] : North, %[[VAL_42]] : South) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_43:.*]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_43]] : DMA) -// CHECK: aie.wire(%[[VAL_42]] : North, %[[VAL_43]] : South) -// CHECK: aie.wire(%[[VAL_40]] : East, %[[VAL_44:.*]] : West) -// CHECK: aie.wire(%[[VAL_4]] : Core, %[[VAL_44]] : Core) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_44]] : DMA) -// CHECK: aie.wire(%[[VAL_45:.*]] : North, %[[VAL_44]] : South) -// CHECK: aie.wire(%[[VAL_41]] : East, %[[VAL_46:.*]] : West) -// CHECK: aie.wire(%[[VAL_5]] : Core, %[[VAL_46]] : Core) -// CHECK: aie.wire(%[[VAL_5]] : DMA, %[[VAL_46]] : DMA) -// CHECK: aie.wire(%[[VAL_44]] : North, %[[VAL_46]] : South) -// CHECK: aie.wire(%[[VAL_42]] : East, %[[VAL_47:.*]] : West) -// CHECK: aie.wire(%[[VAL_6]] : Core, %[[VAL_47]] : Core) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_47]] : DMA) -// CHECK: aie.wire(%[[VAL_46]] : North, %[[VAL_47]] : South) -// CHECK: aie.wire(%[[VAL_43]] : East, %[[VAL_48:.*]] : West) -// CHECK: aie.wire(%[[VAL_7]] : Core, %[[VAL_48]] : Core) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_48]] : DMA) -// CHECK: aie.wire(%[[VAL_47]] : North, %[[VAL_48]] : South) -// CHECK: aie.wire(%[[VAL_45]] : East, %[[VAL_49:.*]] : West) -// CHECK: aie.wire(%[[VAL_50:.*]] : North, %[[VAL_49]] : South) -// CHECK: aie.wire(%[[VAL_8]] : DMA, %[[VAL_50]] : DMA) -// CHECK: aie.wire(%[[VAL_44]] : East, %[[VAL_51:.*]] : West) -// CHECK: aie.wire(%[[VAL_9]] : Core, %[[VAL_51]] : Core) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_51]] : DMA) -// CHECK: aie.wire(%[[VAL_49]] : North, %[[VAL_51]] : South) -// CHECK: aie.wire(%[[VAL_46]] : East, %[[VAL_52:.*]] : West) -// CHECK: aie.wire(%[[VAL_10]] : Core, %[[VAL_52]] : Core) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_52]] : DMA) -// CHECK: aie.wire(%[[VAL_51]] : North, %[[VAL_52]] : South) -// CHECK: aie.wire(%[[VAL_47]] : East, %[[VAL_53:.*]] : West) -// CHECK: aie.wire(%[[VAL_11]] : Core, %[[VAL_53]] : Core) -// CHECK: aie.wire(%[[VAL_11]] : DMA, %[[VAL_53]] : DMA) -// CHECK: aie.wire(%[[VAL_52]] : North, %[[VAL_53]] : South) -// CHECK: aie.wire(%[[VAL_48]] : East, %[[VAL_54:.*]] : West) -// CHECK: aie.wire(%[[VAL_12]] : Core, %[[VAL_54]] : Core) -// CHECK: aie.wire(%[[VAL_12]] : DMA, %[[VAL_54]] : DMA) -// CHECK: aie.wire(%[[VAL_53]] : North, %[[VAL_54]] : South) -// CHECK: aie.wire(%[[VAL_49]] : East, %[[VAL_55:.*]] : West) -// CHECK: aie.wire(%[[VAL_56:.*]] : North, %[[VAL_55]] : South) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_56]] : DMA) -// CHECK: aie.wire(%[[VAL_51]] : East, %[[VAL_57:.*]] : West) -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_57]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_57]] : DMA) -// CHECK: aie.wire(%[[VAL_55]] : North, %[[VAL_57]] : South) -// CHECK: aie.wire(%[[VAL_52]] : East, %[[VAL_58:.*]] : West) -// CHECK: aie.wire(%[[VAL_15]] : Core, %[[VAL_58]] : Core) -// CHECK: aie.wire(%[[VAL_15]] : DMA, %[[VAL_58]] : DMA) -// CHECK: aie.wire(%[[VAL_57]] : North, %[[VAL_58]] : South) -// CHECK: aie.wire(%[[VAL_53]] : East, %[[VAL_59:.*]] : West) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_59]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_59]] : DMA) -// CHECK: aie.wire(%[[VAL_58]] : North, %[[VAL_59]] : South) -// CHECK: aie.wire(%[[VAL_54]] : East, %[[VAL_60:.*]] : West) -// CHECK: aie.wire(%[[VAL_17]] : Core, %[[VAL_60]] : Core) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_60]] : DMA) -// CHECK: aie.wire(%[[VAL_59]] : North, %[[VAL_60]] : South) +// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) +// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) +// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) +// CHECK: aie.wire(%[[TILE_0_4]] : Core, %[[SWITCHBOX_0_4:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_4]] : DMA, %[[SWITCHBOX_0_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : North, %[[SWITCHBOX_0_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) +// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_0:.*]] : North, %[[SWITCHBOX_1_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) +// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) +// CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : North, %[[SWITCHBOX_1_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_4]] : East, %[[SWITCHBOX_1_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_4]] : Core, %[[SWITCHBOX_1_4]] : Core) +// CHECK: aie.wire(%[[TILE_1_4]] : DMA, %[[SWITCHBOX_1_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : North, %[[SWITCHBOX_1_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : East, %[[SWITCHBOX_2_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : East, %[[SWITCHBOX_2_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3]] : Core) +// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_4]] : East, %[[SWITCHBOX_2_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_4]] : Core, %[[SWITCHBOX_2_4]] : Core) +// CHECK: aie.wire(%[[TILE_2_4]] : DMA, %[[SWITCHBOX_2_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : North, %[[SWITCHBOX_2_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) +// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : East, %[[SWITCHBOX_3_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3]] : Core) +// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_4]] : East, %[[SWITCHBOX_3_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_4]] : Core, %[[SWITCHBOX_3_4]] : Core) +// CHECK: aie.wire(%[[TILE_3_4]] : DMA, %[[SWITCHBOX_3_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : North, %[[SWITCHBOX_3_4]] : South) // CHECK: } module { @@ -240,20 +231,17 @@ module { %t32 = aie.tile(3, 2) %t33 = aie.tile(3, 3) %t34 = aie.tile(3, 4) - //TASK 1 aie.flow(%t20, DMA : 0, %t11, DMA : 0) aie.flow(%t11, Core : 0, %t01, Core : 0) aie.flow(%t01, Core : 0, %t12, Core : 0) aie.flow(%t12, Core : 0, %t02, Core : 0) aie.flow(%t02, DMA : 0, %t20, DMA : 0) - //TASK 2 aie.flow(%t20, DMA : 1, %t14, DMA : 0) aie.flow(%t14, Core : 0, %t04, Core : 0) aie.flow(%t04, Core : 0, %t13, Core : 0) aie.flow(%t13, DMA : 0, %t20, DMA : 1) - //TASK 3 aie.flow(%t30, DMA : 0, %t21, DMA : 0) aie.flow(%t21, Core : 0, %t33, Core : 0) @@ -262,7 +250,6 @@ module { aie.flow(%t34, Core : 0, %t24, Core : 0) aie.flow(%t24, Core : 0, %t23, Core : 0) aie.flow(%t23, DMA : 0, %t30, DMA : 0) - //TASK 4 aie.flow(%t30, DMA : 1, %t31, DMA : 1) aie.flow(%t31, Core : 1, %t23, Core : 1) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_3.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_3.mlir index 1b0533e21..2e162549d 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_3.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_flow_test_3.mlir @@ -1,60 +1,51 @@ -//===- flow_test_3.mlir ----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_3:.*]] = aie.tile(0, 4) -// CHECK: %[[VAL_4:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_5:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_6:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_7:.*]] = aie.tile(1, 4) -// CHECK: %[[VAL_8:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_10:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_11:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_12:.*]] = aie.tile(2, 4) -// CHECK: %[[VAL_13:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_14:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_15:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_16:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_17:.*]] = aie.tile(7, 4) -// CHECK: %[[VAL_18:.*]] = aie.tile(8, 1) -// CHECK: %[[VAL_19:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_20:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_21:.*]] = aie.tile(8, 4) -// CHECK: %[[VAL_22:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_0_4:.*]] = aie.tile(0, 4) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_1_4:.*]] = aie.tile(1, 4) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_2_4:.*]] = aie.tile(2, 4) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) +// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) +// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) +// CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) +// CHECK: %[[TILE_8_1:.*]] = aie.tile(8, 1) +// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) +// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) +// CHECK: %[[TILE_8_4:.*]] = aie.tile(8, 4) +// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_25:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_25]]) { +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.switchbox(%[[VAL_4]]) { +// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -64,39 +55,39 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_8]]) { +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.shim_mux(%[[VAL_8]]) { +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.switchbox(%[[VAL_6]]) { +// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.switchbox(%[[VAL_11]]) { +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_32:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_33:.*]] = aie.switchbox(%[[VAL_32]]) { +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_34:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_35:.*]] = aie.switchbox(%[[VAL_34]]) { +// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) +// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -104,16 +95,16 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_36:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_37:.*]] = aie.switchbox(%[[VAL_36]]) { +// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) +// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_38:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_39:.*]] = aie.switchbox(%[[VAL_38]]) { +// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) +// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -121,13 +112,13 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_40:.*]] = aie.switchbox(%[[VAL_14]]) { +// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.switchbox(%[[VAL_15]]) { +// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -137,7 +128,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_42:.*]] = aie.switchbox(%[[VAL_16]]) { +// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -146,13 +137,13 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_43:.*]] = aie.switchbox(%[[VAL_19]]) { +// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_44:.*]] = aie.switchbox(%[[VAL_20]]) { +// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -160,13 +151,13 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_45:.*]] = aie.switchbox(%[[VAL_21]]) { +// CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_46:.*]] = aie.switchbox(%[[VAL_9]]) { +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -177,8 +168,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_47:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_48:.*]] = aie.switchbox(%[[VAL_47]]) { +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -187,16 +178,16 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_49:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_50:.*]] = aie.switchbox(%[[VAL_49]]) { +// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) +// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_51:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_52:.*]] = aie.switchbox(%[[VAL_51]]) { +// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) +// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -204,235 +195,235 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_53:.*]] = aie.tile(4, 4) -// CHECK: %[[VAL_54:.*]] = aie.switchbox(%[[VAL_53]]) { +// CHECK: %[[TILE_4_4:.*]] = aie.tile(4, 4) +// CHECK: %[[SWITCHBOX_4_4:.*]] = aie.switchbox(%[[TILE_4_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_55:.*]] = aie.tile(5, 4) -// CHECK: %[[VAL_56:.*]] = aie.switchbox(%[[VAL_55]]) { +// CHECK: %[[TILE_5_4:.*]] = aie.tile(5, 4) +// CHECK: %[[SWITCHBOX_5_4:.*]] = aie.switchbox(%[[TILE_5_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_57:.*]] = aie.tile(6, 4) -// CHECK: %[[VAL_58:.*]] = aie.switchbox(%[[VAL_57]]) { +// CHECK: %[[TILE_6_4:.*]] = aie.tile(6, 4) +// CHECK: %[[SWITCHBOX_6_4:.*]] = aie.switchbox(%[[TILE_6_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_59:.*]] = aie.switchbox(%[[VAL_17]]) { +// CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_60:.*]] = aie.switchbox(%[[VAL_5]]) { +// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_61:.*]] = aie.switchbox(%[[VAL_10]]) { +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_62:.*]] = aie.switchbox(%[[VAL_12]]) { +// CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_63:.*]] = aie.switchbox(%[[VAL_7]]) { +// CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_64:.*]] = aie.switchbox(%[[VAL_13]]) { +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_65:.*]] = aie.shim_mux(%[[VAL_13]]) { +// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_66:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_67:.*]] = aie.switchbox(%[[VAL_66]]) { +// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) +// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_68:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_69:.*]] = aie.switchbox(%[[VAL_68]]) { +// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) +// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_70:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_71:.*]] = aie.switchbox(%[[VAL_70]]) { +// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) +// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_72:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_73:.*]] = aie.switchbox(%[[VAL_72]]) { +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_74:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_75:.*]] = aie.switchbox(%[[VAL_74]]) { +// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) +// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_76:.*]] = aie.switchbox(%[[VAL_3]]) { +// CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_77:.*]] = aie.tile(3, 4) -// CHECK: %[[VAL_78:.*]] = aie.switchbox(%[[VAL_77]]) { +// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) +// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_79:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_79]] : DMA) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_80:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_80]] : DMA) -// CHECK: aie.wire(%[[VAL_79]] : North, %[[VAL_80]] : South) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_81:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_81]] : DMA) -// CHECK: aie.wire(%[[VAL_80]] : North, %[[VAL_81]] : South) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_82:.*]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_82]] : DMA) -// CHECK: aie.wire(%[[VAL_81]] : North, %[[VAL_82]] : South) -// CHECK: aie.wire(%[[VAL_79]] : East, %[[VAL_83:.*]] : West) -// CHECK: aie.wire(%[[VAL_4]] : Core, %[[VAL_83]] : Core) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_83]] : DMA) -// CHECK: aie.wire(%[[VAL_84:.*]] : North, %[[VAL_83]] : South) -// CHECK: aie.wire(%[[VAL_80]] : East, %[[VAL_85:.*]] : West) -// CHECK: aie.wire(%[[VAL_5]] : Core, %[[VAL_85]] : Core) -// CHECK: aie.wire(%[[VAL_5]] : DMA, %[[VAL_85]] : DMA) -// CHECK: aie.wire(%[[VAL_83]] : North, %[[VAL_85]] : South) -// CHECK: aie.wire(%[[VAL_81]] : East, %[[VAL_86:.*]] : West) -// CHECK: aie.wire(%[[VAL_6]] : Core, %[[VAL_86]] : Core) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_86]] : DMA) -// CHECK: aie.wire(%[[VAL_85]] : North, %[[VAL_86]] : South) -// CHECK: aie.wire(%[[VAL_82]] : East, %[[VAL_87:.*]] : West) -// CHECK: aie.wire(%[[VAL_7]] : Core, %[[VAL_87]] : Core) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_87]] : DMA) -// CHECK: aie.wire(%[[VAL_86]] : North, %[[VAL_87]] : South) -// CHECK: aie.wire(%[[VAL_84]] : East, %[[VAL_88:.*]] : West) -// CHECK: aie.wire(%[[VAL_89:.*]] : North, %[[VAL_88]] : South) -// CHECK: aie.wire(%[[VAL_8]] : DMA, %[[VAL_89]] : DMA) -// CHECK: aie.wire(%[[VAL_83]] : East, %[[VAL_90:.*]] : West) -// CHECK: aie.wire(%[[VAL_9]] : Core, %[[VAL_90]] : Core) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_90]] : DMA) -// CHECK: aie.wire(%[[VAL_88]] : North, %[[VAL_90]] : South) -// CHECK: aie.wire(%[[VAL_85]] : East, %[[VAL_91:.*]] : West) -// CHECK: aie.wire(%[[VAL_10]] : Core, %[[VAL_91]] : Core) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_91]] : DMA) -// CHECK: aie.wire(%[[VAL_90]] : North, %[[VAL_91]] : South) -// CHECK: aie.wire(%[[VAL_86]] : East, %[[VAL_92:.*]] : West) -// CHECK: aie.wire(%[[VAL_11]] : Core, %[[VAL_92]] : Core) -// CHECK: aie.wire(%[[VAL_11]] : DMA, %[[VAL_92]] : DMA) -// CHECK: aie.wire(%[[VAL_91]] : North, %[[VAL_92]] : South) -// CHECK: aie.wire(%[[VAL_87]] : East, %[[VAL_93:.*]] : West) -// CHECK: aie.wire(%[[VAL_12]] : Core, %[[VAL_93]] : Core) -// CHECK: aie.wire(%[[VAL_12]] : DMA, %[[VAL_93]] : DMA) -// CHECK: aie.wire(%[[VAL_92]] : North, %[[VAL_93]] : South) -// CHECK: aie.wire(%[[VAL_88]] : East, %[[VAL_94:.*]] : West) -// CHECK: aie.wire(%[[VAL_95:.*]] : North, %[[VAL_94]] : South) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_95]] : DMA) -// CHECK: aie.wire(%[[VAL_90]] : East, %[[VAL_96:.*]] : West) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_96]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_96]] : DMA) -// CHECK: aie.wire(%[[VAL_94]] : North, %[[VAL_96]] : South) -// CHECK: aie.wire(%[[VAL_91]] : East, %[[VAL_97:.*]] : West) -// CHECK: aie.wire(%[[VAL_72]] : Core, %[[VAL_97]] : Core) -// CHECK: aie.wire(%[[VAL_72]] : DMA, %[[VAL_97]] : DMA) -// CHECK: aie.wire(%[[VAL_96]] : North, %[[VAL_97]] : South) -// CHECK: aie.wire(%[[VAL_92]] : East, %[[VAL_98:.*]] : West) -// CHECK: aie.wire(%[[VAL_32]] : Core, %[[VAL_98]] : Core) -// CHECK: aie.wire(%[[VAL_32]] : DMA, %[[VAL_98]] : DMA) -// CHECK: aie.wire(%[[VAL_97]] : North, %[[VAL_98]] : South) -// CHECK: aie.wire(%[[VAL_93]] : East, %[[VAL_99:.*]] : West) -// CHECK: aie.wire(%[[VAL_77]] : Core, %[[VAL_99]] : Core) -// CHECK: aie.wire(%[[VAL_77]] : DMA, %[[VAL_99]] : DMA) -// CHECK: aie.wire(%[[VAL_98]] : North, %[[VAL_99]] : South) -// CHECK: aie.wire(%[[VAL_96]] : East, %[[VAL_100:.*]] : West) -// CHECK: aie.wire(%[[VAL_49]] : Core, %[[VAL_100]] : Core) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_100]] : DMA) -// CHECK: aie.wire(%[[VAL_97]] : East, %[[VAL_101:.*]] : West) -// CHECK: aie.wire(%[[VAL_51]] : Core, %[[VAL_101]] : Core) -// CHECK: aie.wire(%[[VAL_51]] : DMA, %[[VAL_101]] : DMA) -// CHECK: aie.wire(%[[VAL_100]] : North, %[[VAL_101]] : South) -// CHECK: aie.wire(%[[VAL_98]] : East, %[[VAL_102:.*]] : West) -// CHECK: aie.wire(%[[VAL_34]] : Core, %[[VAL_102]] : Core) -// CHECK: aie.wire(%[[VAL_34]] : DMA, %[[VAL_102]] : DMA) -// CHECK: aie.wire(%[[VAL_101]] : North, %[[VAL_102]] : South) -// CHECK: aie.wire(%[[VAL_99]] : East, %[[VAL_103:.*]] : West) -// CHECK: aie.wire(%[[VAL_53]] : Core, %[[VAL_103]] : Core) -// CHECK: aie.wire(%[[VAL_53]] : DMA, %[[VAL_103]] : DMA) -// CHECK: aie.wire(%[[VAL_102]] : North, %[[VAL_103]] : South) -// CHECK: aie.wire(%[[VAL_100]] : East, %[[VAL_104:.*]] : West) -// CHECK: aie.wire(%[[VAL_66]] : Core, %[[VAL_104]] : Core) -// CHECK: aie.wire(%[[VAL_66]] : DMA, %[[VAL_104]] : DMA) -// CHECK: aie.wire(%[[VAL_101]] : East, %[[VAL_105:.*]] : West) -// CHECK: aie.wire(%[[VAL_74]] : Core, %[[VAL_105]] : Core) -// CHECK: aie.wire(%[[VAL_74]] : DMA, %[[VAL_105]] : DMA) -// CHECK: aie.wire(%[[VAL_104]] : North, %[[VAL_105]] : South) -// CHECK: aie.wire(%[[VAL_102]] : East, %[[VAL_106:.*]] : West) -// CHECK: aie.wire(%[[VAL_36]] : Core, %[[VAL_106]] : Core) -// CHECK: aie.wire(%[[VAL_36]] : DMA, %[[VAL_106]] : DMA) -// CHECK: aie.wire(%[[VAL_105]] : North, %[[VAL_106]] : South) -// CHECK: aie.wire(%[[VAL_103]] : East, %[[VAL_107:.*]] : West) -// CHECK: aie.wire(%[[VAL_55]] : Core, %[[VAL_107]] : Core) -// CHECK: aie.wire(%[[VAL_55]] : DMA, %[[VAL_107]] : DMA) -// CHECK: aie.wire(%[[VAL_106]] : North, %[[VAL_107]] : South) -// CHECK: aie.wire(%[[VAL_104]] : East, %[[VAL_108:.*]] : West) -// CHECK: aie.wire(%[[VAL_68]] : Core, %[[VAL_108]] : Core) -// CHECK: aie.wire(%[[VAL_68]] : DMA, %[[VAL_108]] : DMA) -// CHECK: aie.wire(%[[VAL_105]] : East, %[[VAL_109:.*]] : West) -// CHECK: aie.wire(%[[VAL_70]] : Core, %[[VAL_109]] : Core) -// CHECK: aie.wire(%[[VAL_70]] : DMA, %[[VAL_109]] : DMA) -// CHECK: aie.wire(%[[VAL_108]] : North, %[[VAL_109]] : South) -// CHECK: aie.wire(%[[VAL_106]] : East, %[[VAL_110:.*]] : West) -// CHECK: aie.wire(%[[VAL_38]] : Core, %[[VAL_110]] : Core) -// CHECK: aie.wire(%[[VAL_38]] : DMA, %[[VAL_110]] : DMA) -// CHECK: aie.wire(%[[VAL_109]] : North, %[[VAL_110]] : South) -// CHECK: aie.wire(%[[VAL_107]] : East, %[[VAL_111:.*]] : West) -// CHECK: aie.wire(%[[VAL_57]] : Core, %[[VAL_111]] : Core) -// CHECK: aie.wire(%[[VAL_57]] : DMA, %[[VAL_111]] : DMA) -// CHECK: aie.wire(%[[VAL_110]] : North, %[[VAL_111]] : South) -// CHECK: aie.wire(%[[VAL_108]] : East, %[[VAL_112:.*]] : West) -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_112]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_112]] : DMA) -// CHECK: aie.wire(%[[VAL_109]] : East, %[[VAL_113:.*]] : West) -// CHECK: aie.wire(%[[VAL_15]] : Core, %[[VAL_113]] : Core) -// CHECK: aie.wire(%[[VAL_15]] : DMA, %[[VAL_113]] : DMA) -// CHECK: aie.wire(%[[VAL_112]] : North, %[[VAL_113]] : South) -// CHECK: aie.wire(%[[VAL_110]] : East, %[[VAL_114:.*]] : West) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_114]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_114]] : DMA) -// CHECK: aie.wire(%[[VAL_113]] : North, %[[VAL_114]] : South) -// CHECK: aie.wire(%[[VAL_111]] : East, %[[VAL_115:.*]] : West) -// CHECK: aie.wire(%[[VAL_17]] : Core, %[[VAL_115]] : Core) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_115]] : DMA) -// CHECK: aie.wire(%[[VAL_114]] : North, %[[VAL_115]] : South) -// CHECK: aie.wire(%[[VAL_113]] : East, %[[VAL_116:.*]] : West) -// CHECK: aie.wire(%[[VAL_19]] : Core, %[[VAL_116]] : Core) -// CHECK: aie.wire(%[[VAL_19]] : DMA, %[[VAL_116]] : DMA) -// CHECK: aie.wire(%[[VAL_114]] : East, %[[VAL_117:.*]] : West) -// CHECK: aie.wire(%[[VAL_20]] : Core, %[[VAL_117]] : Core) -// CHECK: aie.wire(%[[VAL_20]] : DMA, %[[VAL_117]] : DMA) -// CHECK: aie.wire(%[[VAL_116]] : North, %[[VAL_117]] : South) -// CHECK: aie.wire(%[[VAL_115]] : East, %[[VAL_118:.*]] : West) -// CHECK: aie.wire(%[[VAL_21]] : Core, %[[VAL_118]] : Core) -// CHECK: aie.wire(%[[VAL_21]] : DMA, %[[VAL_118]] : DMA) -// CHECK: aie.wire(%[[VAL_117]] : North, %[[VAL_118]] : South) +// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) +// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) +// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) +// CHECK: aie.wire(%[[TILE_0_4]] : Core, %[[SWITCHBOX_0_4:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_4]] : DMA, %[[SWITCHBOX_0_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : North, %[[SWITCHBOX_0_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) +// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_0:.*]] : North, %[[SWITCHBOX_1_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) +// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) +// CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : North, %[[SWITCHBOX_1_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_4]] : East, %[[SWITCHBOX_1_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_4]] : Core, %[[SWITCHBOX_1_4]] : Core) +// CHECK: aie.wire(%[[TILE_1_4]] : DMA, %[[SWITCHBOX_1_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : North, %[[SWITCHBOX_1_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : East, %[[SWITCHBOX_2_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : East, %[[SWITCHBOX_2_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3]] : Core) +// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_4]] : East, %[[SWITCHBOX_2_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_4]] : Core, %[[SWITCHBOX_2_4]] : Core) +// CHECK: aie.wire(%[[TILE_2_4]] : DMA, %[[SWITCHBOX_2_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : North, %[[SWITCHBOX_2_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) +// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : East, %[[SWITCHBOX_3_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3]] : Core) +// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_4]] : East, %[[SWITCHBOX_3_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_4]] : Core, %[[SWITCHBOX_3_4]] : Core) +// CHECK: aie.wire(%[[TILE_3_4]] : DMA, %[[SWITCHBOX_3_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : North, %[[SWITCHBOX_3_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) +// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) +// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) +// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : North, %[[SWITCHBOX_4_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_4]] : East, %[[SWITCHBOX_4_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_4]] : Core, %[[SWITCHBOX_4_4]] : Core) +// CHECK: aie.wire(%[[TILE_4_4]] : DMA, %[[SWITCHBOX_4_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : North, %[[SWITCHBOX_4_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) +// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) +// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) +// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_4]] : East, %[[SWITCHBOX_5_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_4]] : Core, %[[SWITCHBOX_5_4]] : Core) +// CHECK: aie.wire(%[[TILE_5_4]] : DMA, %[[SWITCHBOX_5_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : North, %[[SWITCHBOX_5_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) +// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) +// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) +// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_4]] : East, %[[SWITCHBOX_6_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_4]] : Core, %[[SWITCHBOX_6_4]] : Core) +// CHECK: aie.wire(%[[TILE_6_4]] : DMA, %[[SWITCHBOX_6_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : North, %[[SWITCHBOX_6_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) +// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) +// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) +// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_4]] : East, %[[SWITCHBOX_7_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_4]] : Core, %[[SWITCHBOX_7_4]] : Core) +// CHECK: aie.wire(%[[TILE_7_4]] : DMA, %[[SWITCHBOX_7_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : North, %[[SWITCHBOX_7_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) +// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) +// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : East, %[[SWITCHBOX_8_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_4]] : Core, %[[SWITCHBOX_8_4]] : Core) +// CHECK: aie.wire(%[[TILE_8_4]] : DMA, %[[SWITCHBOX_8_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : North, %[[SWITCHBOX_8_4]] : South) // CHECK: } module { @@ -459,7 +450,6 @@ module { %t82 = aie.tile(8, 2) %t83 = aie.tile(8, 3) %t84 = aie.tile(8, 4) - //TASK 1 aie.flow(%t20, DMA : 0, %t03, DMA : 0) aie.flow(%t03, Core : 0, %t71, Core : 0) @@ -467,7 +457,6 @@ module { aie.flow(%t84, Core : 0, %t11, Core : 0) aie.flow(%t11, Core : 0, %t24, Core : 0) aie.flow(%t24, DMA : 0, %t20, DMA : 0) - //TASK 2 aie.flow(%t30, DMA : 0, %t14, DMA : 0) aie.flow(%t14, Core : 0, %t01, Core : 0) @@ -476,7 +465,6 @@ module { aie.flow(%t21, Core : 0, %t73, Core : 0) aie.flow(%t73, Core : 0, %t82, Core : 0) aie.flow(%t82, DMA : 0, %t30, DMA : 0) - //TASK 3 aie.flow(%t20, DMA : 1, %t83, DMA : 1) aie.flow(%t83, Core : 1, %t01, Core : 1) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows.mlir index 1de46ebce..ec30373ad 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows.mlir @@ -1,55 +1,46 @@ -//===- many_flows.mlir -----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_2:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_3:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_5:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_6:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_8:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_10:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_11:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_12:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_13:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_14:.*]] = aie.switchbox(%[[VAL_13]]) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_15:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_16:.*]] = aie.switchbox(%[[VAL_15]]) { +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_17:.*]] = aie.switchbox(%[[VAL_5]]) { +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_18:.*]] = aie.switchbox(%[[VAL_7]]) { +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -58,8 +49,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_19:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_20:.*]] = aie.switchbox(%[[VAL_19]]) { +// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) +// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -67,8 +58,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_21:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_22:.*]] = aie.switchbox(%[[VAL_21]]) { +// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) +// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -76,231 +67,231 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_8]]) { +// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_24]]) { +// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) +// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_9]]) { +// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.shim_mux(%[[VAL_9]]) { +// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_3]]) { +// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_30:.*]] = aie.switchbox(%[[VAL_29]]) { +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_32:.*]] = aie.switchbox(%[[VAL_31]]) { +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_34:.*]] = aie.switchbox(%[[VAL_33]]) { +// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) +// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_36:.*]] = aie.switchbox(%[[VAL_35]]) { +// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) +// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_37:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_38:.*]] = aie.switchbox(%[[VAL_37]]) { +// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) +// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_39:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_40:.*]] = aie.switchbox(%[[VAL_39]]) { +// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) +// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_42:.*]] = aie.switchbox(%[[VAL_41]]) { +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_43:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_44:.*]] = aie.switchbox(%[[VAL_43]]) { +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_45:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_46:.*]] = aie.switchbox(%[[VAL_4]]) { +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_47:.*]] = aie.switchbox(%[[VAL_6]]) { +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_48:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_49:.*]] = aie.switchbox(%[[VAL_48]]) { +// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) +// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_50:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_51:.*]] = aie.switchbox(%[[VAL_50]]) { +// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) +// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_52:.*]] = aie.shim_mux(%[[VAL_8]]) { +// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_53:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_54:.*]] = aie.switchbox(%[[VAL_53]]) { +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_55:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_56:.*]] = aie.switchbox(%[[VAL_55]]) { +// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) +// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_57:.*]] = aie.shim_mux(%[[VAL_4]]) { +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_58:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_59:.*]] = aie.switchbox(%[[VAL_58]]) { +// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) +// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_60:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_61:.*]] = aie.switchbox(%[[VAL_60]]) { +// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) +// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_62:.*]] = aie.switchbox(%[[VAL_10]]) { +// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_63:.*]] = aie.shim_mux(%[[VAL_6]]) { +// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_41]] : Core, %[[VAL_64:.*]] : Core) -// CHECK: aie.wire(%[[VAL_41]] : DMA, %[[VAL_64]] : DMA) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_65:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_65]] : DMA) -// CHECK: aie.wire(%[[VAL_64]] : North, %[[VAL_65]] : South) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_66:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_66]] : DMA) -// CHECK: aie.wire(%[[VAL_65]] : North, %[[VAL_66]] : South) -// CHECK: aie.wire(%[[VAL_64]] : East, %[[VAL_67:.*]] : West) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_67]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_67]] : DMA) -// CHECK: aie.wire(%[[VAL_68:.*]] : North, %[[VAL_67]] : South) -// CHECK: aie.wire(%[[VAL_65]] : East, %[[VAL_69:.*]] : West) -// CHECK: aie.wire(%[[VAL_13]] : Core, %[[VAL_69]] : Core) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_69]] : DMA) -// CHECK: aie.wire(%[[VAL_67]] : North, %[[VAL_69]] : South) -// CHECK: aie.wire(%[[VAL_66]] : East, %[[VAL_70:.*]] : West) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_70]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_70]] : DMA) -// CHECK: aie.wire(%[[VAL_69]] : North, %[[VAL_70]] : South) -// CHECK: aie.wire(%[[VAL_68]] : East, %[[VAL_71:.*]] : West) -// CHECK: aie.wire(%[[VAL_72:.*]] : North, %[[VAL_71]] : South) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_72]] : DMA) -// CHECK: aie.wire(%[[VAL_67]] : East, %[[VAL_73:.*]] : West) -// CHECK: aie.wire(%[[VAL_15]] : Core, %[[VAL_73]] : Core) -// CHECK: aie.wire(%[[VAL_15]] : DMA, %[[VAL_73]] : DMA) -// CHECK: aie.wire(%[[VAL_71]] : North, %[[VAL_73]] : South) -// CHECK: aie.wire(%[[VAL_69]] : East, %[[VAL_74:.*]] : West) -// CHECK: aie.wire(%[[VAL_5]] : Core, %[[VAL_74]] : Core) -// CHECK: aie.wire(%[[VAL_5]] : DMA, %[[VAL_74]] : DMA) -// CHECK: aie.wire(%[[VAL_73]] : North, %[[VAL_74]] : South) -// CHECK: aie.wire(%[[VAL_70]] : East, %[[VAL_75:.*]] : West) -// CHECK: aie.wire(%[[VAL_29]] : Core, %[[VAL_75]] : Core) -// CHECK: aie.wire(%[[VAL_29]] : DMA, %[[VAL_75]] : DMA) -// CHECK: aie.wire(%[[VAL_74]] : North, %[[VAL_75]] : South) -// CHECK: aie.wire(%[[VAL_71]] : East, %[[VAL_76:.*]] : West) -// CHECK: aie.wire(%[[VAL_77:.*]] : North, %[[VAL_76]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_77]] : DMA) -// CHECK: aie.wire(%[[VAL_73]] : East, %[[VAL_78:.*]] : West) -// CHECK: aie.wire(%[[VAL_7]] : Core, %[[VAL_78]] : Core) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_78]] : DMA) -// CHECK: aie.wire(%[[VAL_76]] : North, %[[VAL_78]] : South) -// CHECK: aie.wire(%[[VAL_74]] : East, %[[VAL_79:.*]] : West) -// CHECK: aie.wire(%[[VAL_53]] : Core, %[[VAL_79]] : Core) -// CHECK: aie.wire(%[[VAL_53]] : DMA, %[[VAL_79]] : DMA) -// CHECK: aie.wire(%[[VAL_78]] : North, %[[VAL_79]] : South) -// CHECK: aie.wire(%[[VAL_75]] : East, %[[VAL_80:.*]] : West) -// CHECK: aie.wire(%[[VAL_31]] : Core, %[[VAL_80]] : Core) -// CHECK: aie.wire(%[[VAL_31]] : DMA, %[[VAL_80]] : DMA) -// CHECK: aie.wire(%[[VAL_79]] : North, %[[VAL_80]] : South) -// CHECK: aie.wire(%[[VAL_76]] : East, %[[VAL_81:.*]] : West) -// CHECK: aie.wire(%[[VAL_78]] : East, %[[VAL_82:.*]] : West) -// CHECK: aie.wire(%[[VAL_19]] : Core, %[[VAL_82]] : Core) -// CHECK: aie.wire(%[[VAL_19]] : DMA, %[[VAL_82]] : DMA) -// CHECK: aie.wire(%[[VAL_81]] : North, %[[VAL_82]] : South) -// CHECK: aie.wire(%[[VAL_79]] : East, %[[VAL_83:.*]] : West) -// CHECK: aie.wire(%[[VAL_55]] : Core, %[[VAL_83]] : Core) -// CHECK: aie.wire(%[[VAL_55]] : DMA, %[[VAL_83]] : DMA) -// CHECK: aie.wire(%[[VAL_82]] : North, %[[VAL_83]] : South) -// CHECK: aie.wire(%[[VAL_80]] : East, %[[VAL_84:.*]] : West) -// CHECK: aie.wire(%[[VAL_33]] : Core, %[[VAL_84]] : Core) -// CHECK: aie.wire(%[[VAL_33]] : DMA, %[[VAL_84]] : DMA) -// CHECK: aie.wire(%[[VAL_83]] : North, %[[VAL_84]] : South) -// CHECK: aie.wire(%[[VAL_81]] : East, %[[VAL_85:.*]] : West) -// CHECK: aie.wire(%[[VAL_82]] : East, %[[VAL_86:.*]] : West) -// CHECK: aie.wire(%[[VAL_21]] : Core, %[[VAL_86]] : Core) -// CHECK: aie.wire(%[[VAL_21]] : DMA, %[[VAL_86]] : DMA) -// CHECK: aie.wire(%[[VAL_85]] : North, %[[VAL_86]] : South) -// CHECK: aie.wire(%[[VAL_83]] : East, %[[VAL_87:.*]] : West) -// CHECK: aie.wire(%[[VAL_58]] : Core, %[[VAL_87]] : Core) -// CHECK: aie.wire(%[[VAL_58]] : DMA, %[[VAL_87]] : DMA) -// CHECK: aie.wire(%[[VAL_86]] : North, %[[VAL_87]] : South) -// CHECK: aie.wire(%[[VAL_84]] : East, %[[VAL_88:.*]] : West) -// CHECK: aie.wire(%[[VAL_35]] : Core, %[[VAL_88]] : Core) -// CHECK: aie.wire(%[[VAL_35]] : DMA, %[[VAL_88]] : DMA) -// CHECK: aie.wire(%[[VAL_87]] : North, %[[VAL_88]] : South) -// CHECK: aie.wire(%[[VAL_85]] : East, %[[VAL_89:.*]] : West) -// CHECK: aie.wire(%[[VAL_90:.*]] : North, %[[VAL_89]] : South) -// CHECK: aie.wire(%[[VAL_8]] : DMA, %[[VAL_90]] : DMA) -// CHECK: aie.wire(%[[VAL_86]] : East, %[[VAL_91:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_91]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_91]] : DMA) -// CHECK: aie.wire(%[[VAL_89]] : North, %[[VAL_91]] : South) -// CHECK: aie.wire(%[[VAL_87]] : East, %[[VAL_92:.*]] : West) -// CHECK: aie.wire(%[[VAL_37]] : Core, %[[VAL_92]] : Core) -// CHECK: aie.wire(%[[VAL_37]] : DMA, %[[VAL_92]] : DMA) -// CHECK: aie.wire(%[[VAL_91]] : North, %[[VAL_92]] : South) -// CHECK: aie.wire(%[[VAL_88]] : East, %[[VAL_93:.*]] : West) -// CHECK: aie.wire(%[[VAL_39]] : Core, %[[VAL_93]] : Core) -// CHECK: aie.wire(%[[VAL_39]] : DMA, %[[VAL_93]] : DMA) -// CHECK: aie.wire(%[[VAL_92]] : North, %[[VAL_93]] : South) -// CHECK: aie.wire(%[[VAL_89]] : East, %[[VAL_94:.*]] : West) -// CHECK: aie.wire(%[[VAL_95:.*]] : North, %[[VAL_94]] : South) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_95]] : DMA) -// CHECK: aie.wire(%[[VAL_92]] : East, %[[VAL_96:.*]] : West) -// CHECK: aie.wire(%[[VAL_60]] : Core, %[[VAL_96]] : Core) -// CHECK: aie.wire(%[[VAL_60]] : DMA, %[[VAL_96]] : DMA) -// CHECK: aie.wire(%[[VAL_93]] : East, %[[VAL_97:.*]] : West) -// CHECK: aie.wire(%[[VAL_10]] : Core, %[[VAL_97]] : Core) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_97]] : DMA) -// CHECK: aie.wire(%[[VAL_96]] : North, %[[VAL_97]] : South) +// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) +// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) +// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) +// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_0:.*]] : North, %[[SWITCHBOX_1_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) +// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) +// CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : North, %[[SWITCHBOX_1_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : East, %[[SWITCHBOX_2_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : East, %[[SWITCHBOX_2_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3]] : Core) +// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) +// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : East, %[[SWITCHBOX_3_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3]] : Core) +// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) +// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : North, %[[SWITCHBOX_4_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) +// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) +// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : North, %[[SWITCHBOX_4_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : East, %[[SWITCHBOX_5_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) +// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : North, %[[SWITCHBOX_5_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) +// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) +// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) +// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) +// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) +// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) +// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) +// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) +// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) +// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) // CHECK: } module { @@ -316,22 +307,18 @@ module { %t60 = aie.tile(6, 0) %t70 = aie.tile(7, 0) %t73 = aie.tile(7, 3) - aie.flow(%t03, DMA : 0, %t70, DMA : 0) aie.flow(%t13, DMA : 0, %t70, DMA : 1) aie.flow(%t02, DMA : 0, %t60, DMA : 0) aie.flow(%t22, DMA : 0, %t60, DMA : 1) - aie.flow(%t03, Core : 0, %t13, Core : 0) aie.flow(%t03, Core : 1, %t02, Core : 0) aie.flow(%t13, Core : 1, %t22, Core : 0) aie.flow(%t02, Core : 1, %t22, Core : 1) - aie.flow(%t73, DMA : 0, %t20, DMA : 0) aie.flow(%t73, DMA : 1, %t30, DMA : 0) aie.flow(%t31, DMA : 0, %t20, DMA : 1) aie.flow(%t31, DMA : 1, %t30, DMA : 1) - aie.flow(%t73, Core : 0, %t31, Core : 0) aie.flow(%t73, Core : 1, %t31, Core : 1) } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows2.mlir index 253112889..ab6ac0aa0 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_many_flows2.mlir @@ -1,60 +1,51 @@ -//===- many_flows2.mlir ----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_2:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_3:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_5:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_6:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_8:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_10:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_11:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_12:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_13:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_14:.*]] = aie.switchbox(%[[VAL_13]]) { +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_15:.*]] = aie.switchbox(%[[VAL_4]]) { +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_16:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_17:.*]] = aie.switchbox(%[[VAL_16]]) { +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_18:.*]] = aie.switchbox(%[[VAL_5]]) { +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -62,223 +53,223 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_19:.*]] = aie.switchbox(%[[VAL_6]]) { +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.shim_mux(%[[VAL_6]]) { +// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_21:.*]] = aie.switchbox(%[[VAL_7]]) { +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_22:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_22]]) { +// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) +// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_24]]) { +// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) +// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.switchbox(%[[VAL_8]]) { +// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_27:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_27]]) { +// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) +// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.switchbox(%[[VAL_9]]) { +// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.shim_mux(%[[VAL_9]]) { +// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_32:.*]] = aie.switchbox(%[[VAL_31]]) { +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_34:.*]] = aie.switchbox(%[[VAL_33]]) { +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_36:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_37:.*]] = aie.switchbox(%[[VAL_36]]) { +// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) +// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_38:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_39:.*]] = aie.switchbox(%[[VAL_38]]) { +// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) +// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_40:.*]] = aie.shim_mux(%[[VAL_8]]) { +// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.shim_mux(%[[VAL_4]]) { +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_42:.*]] = aie.switchbox(%[[VAL_3]]) { +// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_43:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_44:.*]] = aie.switchbox(%[[VAL_43]]) { +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_45:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_46:.*]] = aie.switchbox(%[[VAL_45]]) { +// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) +// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_47:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_48:.*]] = aie.switchbox(%[[VAL_47]]) { +// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) +// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_49:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_50:.*]] = aie.switchbox(%[[VAL_49]]) { +// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) +// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_51:.*]] = aie.switchbox(%[[VAL_10]]) { +// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_52:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_53:.*]] = aie.switchbox(%[[VAL_52]]) { +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_54:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_55:.*]] = aie.switchbox(%[[VAL_54]]) { +// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) +// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_56:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_57:.*]] = aie.switchbox(%[[VAL_56]]) { +// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) +// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_58:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_59:.*]] = aie.switchbox(%[[VAL_58]]) { +// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) +// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_60:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_61:.*]] = aie.switchbox(%[[VAL_60]]) { +// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) +// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_31]] : Core, %[[VAL_62:.*]] : Core) -// CHECK: aie.wire(%[[VAL_31]] : DMA, %[[VAL_62]] : DMA) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_63:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_63]] : DMA) -// CHECK: aie.wire(%[[VAL_62]] : North, %[[VAL_63]] : South) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_64:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_64]] : DMA) -// CHECK: aie.wire(%[[VAL_63]] : North, %[[VAL_64]] : South) -// CHECK: aie.wire(%[[VAL_62]] : East, %[[VAL_65:.*]] : West) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_65]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_65]] : DMA) -// CHECK: aie.wire(%[[VAL_66:.*]] : North, %[[VAL_65]] : South) -// CHECK: aie.wire(%[[VAL_63]] : East, %[[VAL_67:.*]] : West) -// CHECK: aie.wire(%[[VAL_13]] : Core, %[[VAL_67]] : Core) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_67]] : DMA) -// CHECK: aie.wire(%[[VAL_65]] : North, %[[VAL_67]] : South) -// CHECK: aie.wire(%[[VAL_64]] : East, %[[VAL_68:.*]] : West) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_68]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_68]] : DMA) -// CHECK: aie.wire(%[[VAL_67]] : North, %[[VAL_68]] : South) -// CHECK: aie.wire(%[[VAL_66]] : East, %[[VAL_69:.*]] : West) -// CHECK: aie.wire(%[[VAL_70:.*]] : North, %[[VAL_69]] : South) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_70]] : DMA) -// CHECK: aie.wire(%[[VAL_65]] : East, %[[VAL_71:.*]] : West) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_71]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_71]] : DMA) -// CHECK: aie.wire(%[[VAL_69]] : North, %[[VAL_71]] : South) -// CHECK: aie.wire(%[[VAL_67]] : East, %[[VAL_72:.*]] : West) -// CHECK: aie.wire(%[[VAL_5]] : Core, %[[VAL_72]] : Core) -// CHECK: aie.wire(%[[VAL_5]] : DMA, %[[VAL_72]] : DMA) -// CHECK: aie.wire(%[[VAL_71]] : North, %[[VAL_72]] : South) -// CHECK: aie.wire(%[[VAL_68]] : East, %[[VAL_73:.*]] : West) -// CHECK: aie.wire(%[[VAL_43]] : Core, %[[VAL_73]] : Core) -// CHECK: aie.wire(%[[VAL_43]] : DMA, %[[VAL_73]] : DMA) -// CHECK: aie.wire(%[[VAL_72]] : North, %[[VAL_73]] : South) -// CHECK: aie.wire(%[[VAL_69]] : East, %[[VAL_74:.*]] : West) -// CHECK: aie.wire(%[[VAL_75:.*]] : North, %[[VAL_74]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_75]] : DMA) -// CHECK: aie.wire(%[[VAL_71]] : East, %[[VAL_76:.*]] : West) -// CHECK: aie.wire(%[[VAL_7]] : Core, %[[VAL_76]] : Core) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_76]] : DMA) -// CHECK: aie.wire(%[[VAL_74]] : North, %[[VAL_76]] : South) -// CHECK: aie.wire(%[[VAL_73]] : East, %[[VAL_77:.*]] : West) -// CHECK: aie.wire(%[[VAL_52]] : Core, %[[VAL_77]] : Core) -// CHECK: aie.wire(%[[VAL_52]] : DMA, %[[VAL_77]] : DMA) -// CHECK: aie.wire(%[[VAL_74]] : East, %[[VAL_78:.*]] : West) -// CHECK: aie.wire(%[[VAL_76]] : East, %[[VAL_79:.*]] : West) -// CHECK: aie.wire(%[[VAL_22]] : Core, %[[VAL_79]] : Core) -// CHECK: aie.wire(%[[VAL_22]] : DMA, %[[VAL_79]] : DMA) -// CHECK: aie.wire(%[[VAL_78]] : North, %[[VAL_79]] : South) -// CHECK: aie.wire(%[[VAL_77]] : East, %[[VAL_80:.*]] : West) -// CHECK: aie.wire(%[[VAL_54]] : Core, %[[VAL_80]] : Core) -// CHECK: aie.wire(%[[VAL_54]] : DMA, %[[VAL_80]] : DMA) -// CHECK: aie.wire(%[[VAL_78]] : East, %[[VAL_81:.*]] : West) -// CHECK: aie.wire(%[[VAL_79]] : East, %[[VAL_82:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_82]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_82]] : DMA) -// CHECK: aie.wire(%[[VAL_81]] : North, %[[VAL_82]] : South) -// CHECK: aie.wire(%[[VAL_45]] : Core, %[[VAL_83:.*]] : Core) -// CHECK: aie.wire(%[[VAL_45]] : DMA, %[[VAL_83]] : DMA) -// CHECK: aie.wire(%[[VAL_82]] : North, %[[VAL_83]] : South) -// CHECK: aie.wire(%[[VAL_80]] : East, %[[VAL_84:.*]] : West) -// CHECK: aie.wire(%[[VAL_56]] : Core, %[[VAL_84]] : Core) -// CHECK: aie.wire(%[[VAL_56]] : DMA, %[[VAL_84]] : DMA) -// CHECK: aie.wire(%[[VAL_83]] : North, %[[VAL_84]] : South) -// CHECK: aie.wire(%[[VAL_81]] : East, %[[VAL_85:.*]] : West) -// CHECK: aie.wire(%[[VAL_86:.*]] : North, %[[VAL_85]] : South) -// CHECK: aie.wire(%[[VAL_8]] : DMA, %[[VAL_86]] : DMA) -// CHECK: aie.wire(%[[VAL_82]] : East, %[[VAL_87:.*]] : West) -// CHECK: aie.wire(%[[VAL_27]] : Core, %[[VAL_87]] : Core) -// CHECK: aie.wire(%[[VAL_27]] : DMA, %[[VAL_87]] : DMA) -// CHECK: aie.wire(%[[VAL_85]] : North, %[[VAL_87]] : South) -// CHECK: aie.wire(%[[VAL_83]] : East, %[[VAL_88:.*]] : West) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_88]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_88]] : DMA) -// CHECK: aie.wire(%[[VAL_87]] : North, %[[VAL_88]] : South) -// CHECK: aie.wire(%[[VAL_84]] : East, %[[VAL_89:.*]] : West) -// CHECK: aie.wire(%[[VAL_58]] : Core, %[[VAL_89]] : Core) -// CHECK: aie.wire(%[[VAL_58]] : DMA, %[[VAL_89]] : DMA) -// CHECK: aie.wire(%[[VAL_88]] : North, %[[VAL_89]] : South) -// CHECK: aie.wire(%[[VAL_85]] : East, %[[VAL_90:.*]] : West) -// CHECK: aie.wire(%[[VAL_91:.*]] : North, %[[VAL_90]] : South) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_91]] : DMA) -// CHECK: aie.wire(%[[VAL_87]] : East, %[[VAL_92:.*]] : West) -// CHECK: aie.wire(%[[VAL_60]] : Core, %[[VAL_92]] : Core) -// CHECK: aie.wire(%[[VAL_60]] : DMA, %[[VAL_92]] : DMA) -// CHECK: aie.wire(%[[VAL_90]] : North, %[[VAL_92]] : South) -// CHECK: aie.wire(%[[VAL_88]] : East, %[[VAL_93:.*]] : West) -// CHECK: aie.wire(%[[VAL_49]] : Core, %[[VAL_93]] : Core) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_93]] : DMA) -// CHECK: aie.wire(%[[VAL_92]] : North, %[[VAL_93]] : South) -// CHECK: aie.wire(%[[VAL_89]] : East, %[[VAL_94:.*]] : West) -// CHECK: aie.wire(%[[VAL_10]] : Core, %[[VAL_94]] : Core) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_94]] : DMA) -// CHECK: aie.wire(%[[VAL_93]] : North, %[[VAL_94]] : South) +// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) +// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) +// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) +// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_0:.*]] : North, %[[SWITCHBOX_1_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) +// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) +// CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : North, %[[SWITCHBOX_1_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : East, %[[SWITCHBOX_2_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : East, %[[SWITCHBOX_2_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3]] : Core) +// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) +// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : East, %[[SWITCHBOX_3_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3]] : Core) +// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) +// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : North, %[[SWITCHBOX_4_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) +// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : East, %[[SWITCHBOX_5_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) +// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : North, %[[SWITCHBOX_5_1]] : South) +// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) +// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) +// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) +// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) +// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) +// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) +// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) +// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) +// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) +// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) // CHECK: } module { @@ -294,22 +285,18 @@ module { %t60 = aie.tile(6, 0) %t70 = aie.tile(7, 0) %t73 = aie.tile(7, 3) - aie.flow(%t03, DMA : 0, %t30, DMA : 0) aie.flow(%t03, DMA : 1, %t70, DMA : 1) aie.flow(%t02, DMA : 0, %t60, DMA : 0) aie.flow(%t22, DMA : 0, %t20, DMA : 0) - aie.flow(%t22, Core : 0, %t13, Core : 0) aie.flow(%t03, Core : 1, %t02, Core : 0) aie.flow(%t73, Core : 0, %t31, Core : 0) aie.flow(%t73, Core : 1, %t22, Core : 1) - aie.flow(%t73, DMA : 0, %t60, DMA : 1) aie.flow(%t73, DMA : 1, %t70, DMA : 0) aie.flow(%t31, DMA : 0, %t20, DMA : 1) aie.flow(%t31, DMA : 1, %t30, DMA : 1) - aie.flow(%t03, Core : 0, %t02, Core : 1) aie.flow(%t13, Core : 1, %t31, Core : 1) } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_maxiter_err_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_maxiter_err_test.mlir deleted file mode 100644 index 194555398..000000000 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_maxiter_err_test.mlir +++ /dev/null @@ -1,81 +0,0 @@ -//===- maxiter_err_test.mlir -----------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: not iree-opt --aie-create-pathfinder-flows %s 2>&1 | FileCheck %s -// CHECK: error: Unable to find a legal routing - -module { - aie.device(xcvc1902) { - %t01 = aie.tile(0, 1) - %t11 = aie.tile(1, 1) - %t21 = aie.tile(2, 1) - %t31 = aie.tile(3, 1) - %t41 = aie.tile(4, 1) - %t51 = aie.tile(5, 1) - %t61 = aie.tile(6, 1) - %t71 = aie.tile(7, 1) - %t81 = aie.tile(8, 1) - %t02 = aie.tile(0, 2) - %t12 = aie.tile(1, 2) - %t22 = aie.tile(2, 2) - %t32 = aie.tile(3, 2) - %t42 = aie.tile(4, 2) - %t52 = aie.tile(5, 2) - %t62 = aie.tile(6, 2) - %t72 = aie.tile(7, 2) - %t82 = aie.tile(8, 2) - %t03 = aie.tile(0, 3) - %t13 = aie.tile(1, 3) - %t23 = aie.tile(2, 3) - %t33 = aie.tile(3, 3) - %t43 = aie.tile(4, 3) - %t53 = aie.tile(5, 3) - %t63 = aie.tile(6, 3) - %t73 = aie.tile(7, 3) - %t83 = aie.tile(8, 3) - %t04 = aie.tile(0, 4) - %t14 = aie.tile(1, 4) - %t24 = aie.tile(2, 4) - %t34 = aie.tile(3, 4) - %t44 = aie.tile(4, 4) - %t54 = aie.tile(5, 4) - %t64 = aie.tile(6, 4) - %t74 = aie.tile(7, 4) - %t84 = aie.tile(8, 4) - %t20 = aie.tile(2, 0) - %t60 = aie.tile(6, 0) - - aie.flow(%t01, DMA : 0, %t51, DMA : 0) - aie.flow(%t11, DMA : 0, %t61, DMA : 0) - aie.flow(%t21, DMA : 0, %t71, DMA : 0) - aie.flow(%t31, DMA : 0, %t81, DMA : 0) - aie.flow(%t41, DMA : 0, %t81, DMA : 1) - - aie.flow(%t02, DMA : 0, %t52, DMA : 0) - aie.flow(%t12, DMA : 0, %t62, DMA : 0) - aie.flow(%t22, DMA : 0, %t72, DMA : 0) - aie.flow(%t32, DMA : 0, %t82, DMA : 0) - aie.flow(%t42, DMA : 0, %t82, DMA : 1) - - aie.flow(%t03, DMA : 0, %t53, DMA : 0) - aie.flow(%t13, DMA : 0, %t63, DMA : 0) - aie.flow(%t23, DMA : 0, %t73, DMA : 0) - aie.flow(%t33, DMA : 0, %t83, DMA : 0) - aie.flow(%t43, DMA : 0, %t83, DMA : 1) - - aie.flow(%t04, DMA : 0, %t54, DMA : 0) - aie.flow(%t14, DMA : 0, %t64, DMA : 0) - aie.flow(%t24, DMA : 0, %t74, DMA : 0) - aie.flow(%t34, DMA : 0, %t84, DMA : 0) - aie.flow(%t44, DMA : 0, %t84, DMA : 1) - - aie.flow(%t20, DMA : 0, %t60, DMA : 0) - } -} diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile.mlir index 623676c90..3af08e130 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile.mlir @@ -1,27 +1,18 @@ -//===- memtile.mlir --------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcve2802) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 4) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_3:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_4:.*]] = aie.switchbox(%[[VAL_3]]) { +// CHECK: %[[TILE_0_4:.*]] = aie.tile(0, 4) +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_5:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -35,7 +26,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_6:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -45,23 +36,23 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_7:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_8:.*]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_8]] : DMA) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_9:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_9]] : DMA) -// CHECK: aie.wire(%[[VAL_8]] : North, %[[VAL_9]] : South) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_10:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_10]] : DMA) -// CHECK: aie.wire(%[[VAL_9]] : North, %[[VAL_10]] : South) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_11:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_11]] : DMA) -// CHECK: aie.wire(%[[VAL_10]] : North, %[[VAL_11]] : South) +// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) +// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) +// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) +// CHECK: aie.wire(%[[TILE_0_4]] : Core, %[[SWITCHBOX_0_4:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_4]] : DMA, %[[SWITCHBOX_0_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : North, %[[SWITCHBOX_0_4]] : South) // CHECK: } module { @@ -70,21 +61,17 @@ module { %t03 = aie.tile(0, 3) %t02 = aie.tile(0, 2) %t01 = aie.tile(0, 1) - aie.flow(%t01, DMA : 0, %t02, DMA : 0) aie.flow(%t01, DMA : 1, %t02, DMA : 1) aie.flow(%t02, DMA : 0, %t01, DMA : 0) aie.flow(%t02, DMA : 1, %t01, DMA : 1) - aie.flow(%t02, DMA : 2, %t03, DMA : 0) aie.flow(%t02, DMA : 3, %t03, DMA : 1) aie.flow(%t03, DMA : 0, %t02, DMA : 2) aie.flow(%t03, DMA : 1, %t02, DMA : 3) - aie.flow(%t02, DMA : 4, %t04, DMA : 0) aie.flow(%t02, DMA : 5, %t04, DMA : 1) aie.flow(%t04, DMA : 0, %t02, DMA : 4) aie.flow(%t04, DMA : 1, %t02, DMA : 5) } } - diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile_routing_constraints.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile_routing_constraints.mlir index c2d504df7..76d4286a5 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile_routing_constraints.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_memtile_routing_constraints.mlir @@ -1,36 +1,40 @@ -//===- memtile_routing_constraints.mlir ------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2023, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK: %tile_2_0 = aie.tile(2, 0) -// CHECK: %tile_2_1 = aie.tile(2, 1) -// CHECK: %tile_2_2 = aie.tile(2, 2) -// CHECK: %tile_2_3 = aie.tile(2, 3) -// CHECK: %switchbox_2_1 = aie.switchbox(%tile_2_1) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_2_2 = aie.switchbox(%tile_2_2) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_2_0 = aie.switchbox(%tile_2_0) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %shim_mux_2_0 = aie.shim_mux(%tile_2_0) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %switchbox_2_3 = aie.switchbox(%tile_2_3) { -// CHECK: aie.connect -// CHECK: } +// CHECK-LABEL: aie.device(xcve2802) { +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) +// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) +// CHECK: } module { aie.device(xcve2802) { @@ -38,7 +42,6 @@ module { %tile_2_1 = aie.tile(2, 1) %tile_2_2 = aie.tile(2, 2) %tile_2_3 = aie.tile(2, 3) - aie.flow(%tile_2_2, DMA : 0, %tile_2_1, DMA : 0) aie.flow(%tile_2_3, DMA : 0, %tile_2_0, DMA : 0) } diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_mmult.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_mmult.mlir index 51cd20eb2..e226f36fb 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_mmult.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_mmult.mlir @@ -1,192 +1,183 @@ -//===- mmult.mlir ----------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_1:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_2:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_3:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_4:.*]] = aie.lock(%[[VAL_3]], 1) -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_3]], 3) -// CHECK: %[[VAL_6:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "buf11"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_3]], 2) -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "buf10"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_3]], 0) -// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_3]]) {sym_name = "buf9"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_11:.*]] = aie.mem(%[[VAL_3]]) { -// CHECK: %[[VAL_12:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) +// CHECK: %[[LOCK_8_3:.*]] = aie.lock(%[[TILE_8_3]], 1) +// CHECK: %[[LOCK_8_3_0:.*]] = aie.lock(%[[TILE_8_3]], 3) +// CHECK: %[[BUF11:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf11"} : memref<16x16xf32, 2> +// CHECK: %[[LOCK_8_3_1:.*]] = aie.lock(%[[TILE_8_3]], 2) +// CHECK: %[[BUF10:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf10"} : memref<16x16xf32, 2> +// CHECK: %[[LOCK_8_3_2:.*]] = aie.lock(%[[TILE_8_3]], 0) +// CHECK: %[[BUF9:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf9"} : memref<16x16xf32, 2> +// CHECK: %[[MEM_8_3:.*]] = aie.mem(%[[TILE_8_3]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_3_2]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF9]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_8_3_2]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_4]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_4]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_3]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF11]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_8_3]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: -// CHECK: %[[VAL_13:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) // CHECK: ^bb4: -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_3_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF10]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_8_3_1]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb5: -// CHECK: %[[VAL_14:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) +// CHECK: %[[VAL_2:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) // CHECK: ^bb6: -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_3_0]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF11]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_8_3_0]], Release, 0) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb7: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_15:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_16:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_17:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_18:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_19:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_20:.*]] = aie.lock(%[[VAL_19]], 1) -// CHECK: %[[VAL_21:.*]] = aie.lock(%[[VAL_19]], 3) -// CHECK: %[[VAL_22:.*]] = aie.buffer(%[[VAL_19]]) {sym_name = "buf8"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_23:.*]] = aie.lock(%[[VAL_19]], 2) -// CHECK: %[[VAL_24:.*]] = aie.buffer(%[[VAL_19]]) {sym_name = "buf7"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_25:.*]] = aie.lock(%[[VAL_19]], 0) -// CHECK: %[[VAL_26:.*]] = aie.buffer(%[[VAL_19]]) {sym_name = "buf6"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_27:.*]] = aie.mem(%[[VAL_19]]) { -// CHECK: %[[VAL_28:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) +// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) +// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) +// CHECK: %[[LOCK_7_3:.*]] = aie.lock(%[[TILE_7_3]], 1) +// CHECK: %[[LOCK_7_3_3:.*]] = aie.lock(%[[TILE_7_3]], 3) +// CHECK: %[[BUF8:.*]] = aie.buffer(%[[TILE_7_3]]) {sym_name = "buf8"} : memref<16x16xf32, 2> +// CHECK: %[[LOCK_7_3_4:.*]] = aie.lock(%[[TILE_7_3]], 2) +// CHECK: %[[BUF7:.*]] = aie.buffer(%[[TILE_7_3]]) {sym_name = "buf7"} : memref<16x16xf32, 2> +// CHECK: %[[LOCK_7_3_5:.*]] = aie.lock(%[[TILE_7_3]], 0) +// CHECK: %[[BUF6:.*]] = aie.buffer(%[[TILE_7_3]]) {sym_name = "buf6"} : memref<16x16xf32, 2> +// CHECK: %[[MEM_7_3:.*]] = aie.mem(%[[TILE_7_3]]) { +// CHECK: %[[VAL_3:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_25]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_26]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_25]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_3_5]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF6]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_7_3_5]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_20]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_22]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_20]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_3]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF8]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_7_3]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: -// CHECK: %[[VAL_29:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) +// CHECK: %[[VAL_4:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) // CHECK: ^bb4: -// CHECK: aie.use_lock(%[[VAL_23]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_24]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_23]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_3_4]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF7]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_7_3_4]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb5: -// CHECK: %[[VAL_30:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) +// CHECK: %[[VAL_5:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) // CHECK: ^bb6: -// CHECK: aie.use_lock(%[[VAL_21]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_22]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_21]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_3_3]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF8]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_7_3_3]], Release, 0) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb7: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_32:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_33:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_34:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_35:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_36:.*]] = aie.lock(%[[VAL_35]], 1) -// CHECK: %[[VAL_37:.*]] = aie.lock(%[[VAL_35]], 3) -// CHECK: %[[VAL_38:.*]] = aie.buffer(%[[VAL_35]]) {sym_name = "buf5"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_39:.*]] = aie.lock(%[[VAL_35]], 2) -// CHECK: %[[VAL_40:.*]] = aie.buffer(%[[VAL_35]]) {sym_name = "buf4"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_41:.*]] = aie.lock(%[[VAL_35]], 0) -// CHECK: %[[VAL_42:.*]] = aie.buffer(%[[VAL_35]]) {sym_name = "buf3"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_43:.*]] = aie.mem(%[[VAL_35]]) { -// CHECK: %[[VAL_44:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) +// CHECK: %[[LOCK_8_2:.*]] = aie.lock(%[[TILE_8_2]], 1) +// CHECK: %[[LOCK_8_2_6:.*]] = aie.lock(%[[TILE_8_2]], 3) +// CHECK: %[[BUF5:.*]] = aie.buffer(%[[TILE_8_2]]) {sym_name = "buf5"} : memref<16x16xf32, 2> +// CHECK: %[[LOCK_8_2_7:.*]] = aie.lock(%[[TILE_8_2]], 2) +// CHECK: %[[BUF4:.*]] = aie.buffer(%[[TILE_8_2]]) {sym_name = "buf4"} : memref<16x16xf32, 2> +// CHECK: %[[LOCK_8_2_8:.*]] = aie.lock(%[[TILE_8_2]], 0) +// CHECK: %[[BUF3:.*]] = aie.buffer(%[[TILE_8_2]]) {sym_name = "buf3"} : memref<16x16xf32, 2> +// CHECK: %[[MEM_8_2:.*]] = aie.mem(%[[TILE_8_2]]) { +// CHECK: %[[VAL_6:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_41]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_42]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_41]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_2_8]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF3]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_8_2_8]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_36]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_38]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_36]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_2]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF5]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_8_2]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: -// CHECK: %[[VAL_45:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) +// CHECK: %[[VAL_7:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) // CHECK: ^bb4: -// CHECK: aie.use_lock(%[[VAL_39]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_40]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_39]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_2_7]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF4]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_8_2_7]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb5: -// CHECK: %[[VAL_46:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) +// CHECK: %[[VAL_8:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) // CHECK: ^bb6: -// CHECK: aie.use_lock(%[[VAL_37]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_38]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_37]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_2_6]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF5]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_8_2_6]], Release, 0) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb7: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_47:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_48:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_49:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_50:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_51:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_52:.*]] = aie.lock(%[[VAL_51]], 1) -// CHECK: %[[VAL_53:.*]] = aie.lock(%[[VAL_51]], 3) -// CHECK: %[[VAL_54:.*]] = aie.buffer(%[[VAL_51]]) {sym_name = "buf2"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_55:.*]] = aie.lock(%[[VAL_51]], 2) -// CHECK: %[[VAL_56:.*]] = aie.buffer(%[[VAL_51]]) {sym_name = "buf1"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_57:.*]] = aie.lock(%[[VAL_51]], 0) -// CHECK: %[[VAL_58:.*]] = aie.buffer(%[[VAL_51]]) {sym_name = "buf0"} : memref<16x16xf32, 2> -// CHECK: %[[VAL_59:.*]] = aie.mem(%[[VAL_51]]) { -// CHECK: %[[VAL_60:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) +// CHECK: %[[LOCK_7_2:.*]] = aie.lock(%[[TILE_7_2]], 1) +// CHECK: %[[LOCK_7_2_9:.*]] = aie.lock(%[[TILE_7_2]], 3) +// CHECK: %[[BUF2:.*]] = aie.buffer(%[[TILE_7_2]]) {sym_name = "buf2"} : memref<16x16xf32, 2> +// CHECK: %[[LOCK_7_2_10:.*]] = aie.lock(%[[TILE_7_2]], 2) +// CHECK: %[[BUF1:.*]] = aie.buffer(%[[TILE_7_2]]) {sym_name = "buf1"} : memref<16x16xf32, 2> +// CHECK: %[[LOCK_7_2_11:.*]] = aie.lock(%[[TILE_7_2]], 0) +// CHECK: %[[BUF0:.*]] = aie.buffer(%[[TILE_7_2]]) {sym_name = "buf0"} : memref<16x16xf32, 2> +// CHECK: %[[MEM_7_2:.*]] = aie.mem(%[[TILE_7_2]]) { +// CHECK: %[[VAL_9:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb5) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_57]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_58]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_57]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_2_11]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF0]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_7_2_11]], Release, 1) // CHECK: aie.next_bd ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_52]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_54]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_52]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_2]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF2]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_7_2]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb3: -// CHECK: %[[VAL_61:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) +// CHECK: %[[VAL_10:.*]] = aie.dma_start(S2MM, 1, ^bb4, ^bb7) // CHECK: ^bb4: -// CHECK: aie.use_lock(%[[VAL_55]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_56]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_55]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_2_10]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF1]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_7_2_10]], Release, 1) // CHECK: aie.next_bd ^bb4 // CHECK: ^bb5: -// CHECK: %[[VAL_62:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) +// CHECK: %[[VAL_11:.*]] = aie.dma_start(MM2S, 0, ^bb6, ^bb3) // CHECK: ^bb6: -// CHECK: aie.use_lock(%[[VAL_53]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_54]] : memref<16x16xf32, 2>, 0, 256) -// CHECK: aie.use_lock(%[[VAL_53]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_2_9]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF2]] : memref<16x16xf32, 2>, 0, 256) +// CHECK: aie.use_lock(%[[LOCK_7_2_9]], Release, 0) // CHECK: aie.next_bd ^bb6 // CHECK: ^bb7: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_63:.*]] = aie.switchbox(%[[VAL_49]]) { +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_64:.*]] = aie.switchbox(%[[VAL_48]]) { +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_65:.*]] = aie.switchbox(%[[VAL_32]]) { +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -195,23 +186,23 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_66:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_67:.*]] = aie.switchbox(%[[VAL_66]]) { +// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) +// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_68:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_69:.*]] = aie.switchbox(%[[VAL_68]]) { +// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) +// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_70:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_71:.*]] = aie.switchbox(%[[VAL_70]]) { +// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) +// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -219,7 +210,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_72:.*]] = aie.switchbox(%[[VAL_15]]) { +// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -228,7 +219,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_73:.*]] = aie.switchbox(%[[VAL_51]]) { +// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -241,24 +232,24 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_74:.*]] = aie.switchbox(%[[VAL_31]]) { +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_75:.*]] = aie.switchbox(%[[VAL_33]]) { +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_76:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_77:.*]] = aie.switchbox(%[[VAL_76]]) { +// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) +// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_78:.*]] = aie.switchbox(%[[VAL_35]]) { +// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -266,162 +257,162 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_79:.*]] = aie.switchbox(%[[VAL_47]]) { +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_80:.*]] = aie.switchbox(%[[VAL_17]]) { +// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_81:.*]] = aie.switchbox(%[[VAL_16]]) { +// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_82:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_83:.*]] = aie.switchbox(%[[VAL_19]]) { +// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_84:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_85:.*]] = aie.switchbox(%[[VAL_84]]) { +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_86:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_87:.*]] = aie.switchbox(%[[VAL_86]]) { +// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) +// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_88:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_89:.*]] = aie.switchbox(%[[VAL_88]]) { +// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) +// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_90:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_91:.*]] = aie.switchbox(%[[VAL_90]]) { +// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) +// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_92:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_93:.*]] = aie.switchbox(%[[VAL_3]]) { +// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_94:.*]] = aie.shim_mux(%[[VAL_49]]) { +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_95:.*]] = aie.shim_mux(%[[VAL_33]]) { +// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_96:.*]] = aie.shim_mux(%[[VAL_17]]) { +// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_97:.*]] = aie.shim_mux(%[[VAL_1]]) { +// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_98:.*]] : North, %[[VAL_99:.*]] : South) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_98]] : DMA) -// CHECK: aie.wire(%[[VAL_48]] : Core, %[[VAL_100:.*]] : Core) -// CHECK: aie.wire(%[[VAL_48]] : DMA, %[[VAL_100]] : DMA) -// CHECK: aie.wire(%[[VAL_99]] : North, %[[VAL_100]] : South) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_101:.*]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_101]] : DMA) -// CHECK: aie.wire(%[[VAL_100]] : North, %[[VAL_101]] : South) -// CHECK: aie.wire(%[[VAL_99]] : East, %[[VAL_102:.*]] : West) -// CHECK: aie.wire(%[[VAL_103:.*]] : North, %[[VAL_102]] : South) -// CHECK: aie.wire(%[[VAL_33]] : DMA, %[[VAL_103]] : DMA) -// CHECK: aie.wire(%[[VAL_100]] : East, %[[VAL_104:.*]] : West) -// CHECK: aie.wire(%[[VAL_32]] : Core, %[[VAL_104]] : Core) -// CHECK: aie.wire(%[[VAL_32]] : DMA, %[[VAL_104]] : DMA) -// CHECK: aie.wire(%[[VAL_102]] : North, %[[VAL_104]] : South) -// CHECK: aie.wire(%[[VAL_101]] : East, %[[VAL_105:.*]] : West) -// CHECK: aie.wire(%[[VAL_31]] : Core, %[[VAL_105]] : Core) -// CHECK: aie.wire(%[[VAL_31]] : DMA, %[[VAL_105]] : DMA) -// CHECK: aie.wire(%[[VAL_104]] : North, %[[VAL_105]] : South) -// CHECK: aie.wire(%[[VAL_84]] : Core, %[[VAL_106:.*]] : Core) -// CHECK: aie.wire(%[[VAL_84]] : DMA, %[[VAL_106]] : DMA) -// CHECK: aie.wire(%[[VAL_105]] : North, %[[VAL_106]] : South) -// CHECK: aie.wire(%[[VAL_104]] : East, %[[VAL_107:.*]] : West) -// CHECK: aie.wire(%[[VAL_66]] : Core, %[[VAL_107]] : Core) -// CHECK: aie.wire(%[[VAL_66]] : DMA, %[[VAL_107]] : DMA) -// CHECK: aie.wire(%[[VAL_105]] : East, %[[VAL_108:.*]] : West) -// CHECK: aie.wire(%[[VAL_68]] : Core, %[[VAL_108]] : Core) -// CHECK: aie.wire(%[[VAL_68]] : DMA, %[[VAL_108]] : DMA) -// CHECK: aie.wire(%[[VAL_107]] : North, %[[VAL_108]] : South) -// CHECK: aie.wire(%[[VAL_106]] : East, %[[VAL_109:.*]] : West) -// CHECK: aie.wire(%[[VAL_86]] : Core, %[[VAL_109]] : Core) -// CHECK: aie.wire(%[[VAL_86]] : DMA, %[[VAL_109]] : DMA) -// CHECK: aie.wire(%[[VAL_108]] : North, %[[VAL_109]] : South) -// CHECK: aie.wire(%[[VAL_107]] : East, %[[VAL_110:.*]] : West) -// CHECK: aie.wire(%[[VAL_76]] : Core, %[[VAL_110]] : Core) -// CHECK: aie.wire(%[[VAL_76]] : DMA, %[[VAL_110]] : DMA) -// CHECK: aie.wire(%[[VAL_108]] : East, %[[VAL_111:.*]] : West) -// CHECK: aie.wire(%[[VAL_70]] : Core, %[[VAL_111]] : Core) -// CHECK: aie.wire(%[[VAL_70]] : DMA, %[[VAL_111]] : DMA) -// CHECK: aie.wire(%[[VAL_110]] : North, %[[VAL_111]] : South) -// CHECK: aie.wire(%[[VAL_109]] : East, %[[VAL_112:.*]] : West) -// CHECK: aie.wire(%[[VAL_88]] : Core, %[[VAL_112]] : Core) -// CHECK: aie.wire(%[[VAL_88]] : DMA, %[[VAL_112]] : DMA) -// CHECK: aie.wire(%[[VAL_111]] : North, %[[VAL_112]] : South) -// CHECK: aie.wire(%[[VAL_113:.*]] : North, %[[VAL_114:.*]] : South) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_113]] : DMA) -// CHECK: aie.wire(%[[VAL_110]] : East, %[[VAL_115:.*]] : West) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_115]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_115]] : DMA) -// CHECK: aie.wire(%[[VAL_114]] : North, %[[VAL_115]] : South) -// CHECK: aie.wire(%[[VAL_111]] : East, %[[VAL_116:.*]] : West) -// CHECK: aie.wire(%[[VAL_15]] : Core, %[[VAL_116]] : Core) -// CHECK: aie.wire(%[[VAL_15]] : DMA, %[[VAL_116]] : DMA) -// CHECK: aie.wire(%[[VAL_115]] : North, %[[VAL_116]] : South) -// CHECK: aie.wire(%[[VAL_112]] : East, %[[VAL_117:.*]] : West) -// CHECK: aie.wire(%[[VAL_90]] : Core, %[[VAL_117]] : Core) -// CHECK: aie.wire(%[[VAL_90]] : DMA, %[[VAL_117]] : DMA) -// CHECK: aie.wire(%[[VAL_116]] : North, %[[VAL_117]] : South) -// CHECK: aie.wire(%[[VAL_114]] : East, %[[VAL_118:.*]] : West) -// CHECK: aie.wire(%[[VAL_119:.*]] : North, %[[VAL_118]] : South) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_119]] : DMA) -// CHECK: aie.wire(%[[VAL_115]] : East, %[[VAL_120:.*]] : West) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_120]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_120]] : DMA) -// CHECK: aie.wire(%[[VAL_118]] : North, %[[VAL_120]] : South) -// CHECK: aie.wire(%[[VAL_116]] : East, %[[VAL_121:.*]] : West) -// CHECK: aie.wire(%[[VAL_51]] : Core, %[[VAL_121]] : Core) -// CHECK: aie.wire(%[[VAL_51]] : DMA, %[[VAL_121]] : DMA) -// CHECK: aie.wire(%[[VAL_120]] : North, %[[VAL_121]] : South) -// CHECK: aie.wire(%[[VAL_117]] : East, %[[VAL_122:.*]] : West) -// CHECK: aie.wire(%[[VAL_19]] : Core, %[[VAL_122]] : Core) -// CHECK: aie.wire(%[[VAL_19]] : DMA, %[[VAL_122]] : DMA) -// CHECK: aie.wire(%[[VAL_121]] : North, %[[VAL_122]] : South) -// CHECK: aie.wire(%[[VAL_121]] : East, %[[VAL_123:.*]] : West) -// CHECK: aie.wire(%[[VAL_35]] : Core, %[[VAL_123]] : Core) -// CHECK: aie.wire(%[[VAL_35]] : DMA, %[[VAL_123]] : DMA) -// CHECK: aie.wire(%[[VAL_122]] : East, %[[VAL_124:.*]] : West) -// CHECK: aie.wire(%[[VAL_3]] : Core, %[[VAL_124]] : Core) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_124]] : DMA) -// CHECK: aie.wire(%[[VAL_123]] : North, %[[VAL_124]] : South) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) +// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) +// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) +// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) +// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) +// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : North, %[[SWITCHBOX_4_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) +// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) +// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) +// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) +// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) +// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) +// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) +// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) +// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) +// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) +// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) +// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) +// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) +// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) // CHECK: } module @aie.herd_0 { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_more_flows_shim.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_more_flows_shim.mlir index 6f12a567f..3e87bc19f 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_more_flows_shim.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_more_flows_shim.mlir @@ -1,31 +1,24 @@ -//===- more_flows_shim.mlir ------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// - -// -// These tests verify pathfinder routing flows to/from PLIO in shim tiles. -// // RUN: iree-opt --split-input-file --aie-create-pathfinder-flows -split-input-file %s | FileCheck %s -// CHECK-LABEL: test70 -// CHECK: %[[T70:.*]] = aie.tile(7, 0) -// CHECK: %[[T71:.*]] = aie.tile(7, 1) -// CHECK: %[[SB70:.*]] = aie.switchbox(%[[T70]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SH70:.*]] = aie.shim_mux(%[[T70]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SB71:.*]] = aie.switchbox(%[[T71]]) { -// CHECK: aie.connect -// CHECK: } +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) +// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) +// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) +// CHECK: } // Tile 7,0 is a shim NoC tile that has a ShimMux. // The ShimMux must be configured for streams to PLIO 2,3,4,5 @@ -39,18 +32,24 @@ module @test70 { // ----- -// CHECK-LABEL: test60 -// CHECK: %[[T60:.*]] = aie.tile(6, 0) -// CHECK: %[[T61:.*]] = aie.tile(6, 1) -// CHECK: %[[SB60:.*]] = aie.switchbox(%[[T60]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SH60:.*]] = aie.shim_mux(%[[T60]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SB61:.*]] = aie.switchbox(%[[T61]]) { -// CHECK: aie.connect -// CHECK: } +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) +// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) +// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) +// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) +// CHECK: } // Tile 6,0 is a shim NoC tile that has a ShimMux. // The ShimMux must be configured for streams from PLIO 2,3,6,7 @@ -64,17 +63,21 @@ module @test60 { // ----- -// CHECK-LABEL: test40 -// CHECK: %[[T40:.*]] = aie.tile(4, 0) -// CHECK: %[[T41:.*]] = aie.tile(4, 1) -// CHECK: %[[SB40:.*]] = aie.switchbox(%[[T40]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SB41:.*]] = aie.switchbox(%[[T41]]) { -// CHECK: aie.connect -// CHECK: aie.connect -// CHECK: } +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) +// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) +// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { +// CHECK: aie.connect +// CHECK: aie.connect +// CHECK: } +// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_0:.*]] : North, %[[SWITCHBOX_4_1]] : South) +// CHECK: } // Tile 4,0 is a shim PL tile and does not contain a ShimMux. module @test40 { @@ -88,18 +91,24 @@ module @test40 { // ----- -// CHECK-LABEL: test100 -// CHECK: %[[T100:.*]] = aie.tile(10, 0) -// CHECK: %[[T101:.*]] = aie.tile(10, 1) -// CHECK: %[[SB100:.*]] = aie.switchbox(%[[T100]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SH100:.*]] = aie.shim_mux(%[[T100]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %[[SB101:.*]] = aie.switchbox(%[[T101]]) { -// CHECK: aie.connect -// CHECK: } +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: %[[TILE_10_0:.*]] = aie.tile(10, 0) +// CHECK: %[[TILE_10_1:.*]] = aie.tile(10, 1) +// CHECK: %[[SWITCHBOX_10_0:.*]] = aie.switchbox(%[[TILE_10_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SHIM_MUX_10_0:.*]] = aie.shim_mux(%[[TILE_10_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_10_1:.*]] = aie.switchbox(%[[TILE_10_1]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: aie.wire(%[[SHIM_MUX_10_0:.*]] : North, %[[SWITCHBOX_10_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_10_0]] : DMA, %[[SHIM_MUX_10_0]] : DMA) +// CHECK: aie.wire(%[[TILE_10_1]] : Core, %[[SWITCHBOX_10_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_10_1]] : DMA, %[[SWITCHBOX_10_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : North, %[[SWITCHBOX_10_1]] : South) +// CHECK: } // Tile 10,0 is a shim NoC tile that has a ShimMux. // The ShimMux must be configured for streams to NOC 0,1,2,3 @@ -110,4 +119,3 @@ module @test100 { aie.flow(%t101, North : 0, %t100, NOC : 2) } } - diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_over_flows.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_over_flows.mlir index 82c0b51bd..4c63f1dc3 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_over_flows.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_over_flows.mlir @@ -1,74 +1,65 @@ -//===- over_flows.mlir -----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_3:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_5:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_6:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_8:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_9:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_10:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_11:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_12:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_13:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_14:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_15:.*]] = aie.tile(8, 0) -// CHECK: %[[VAL_16:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_17:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_18:.*]] = aie.switchbox(%[[VAL_6]]) { +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) +// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) +// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) +// CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) +// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) +// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_19:.*]] = aie.shim_mux(%[[VAL_6]]) { +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.switchbox(%[[VAL_7]]) { +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_21:.*]] = aie.switchbox(%[[VAL_9]]) { +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_22:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_23:.*]] = aie.switchbox(%[[VAL_22]]) { +// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) +// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_24:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_25:.*]] = aie.switchbox(%[[VAL_24]]) { +// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) +// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_26:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_27:.*]] = aie.switchbox(%[[VAL_26]]) { +// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) +// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_28:.*]] = aie.switchbox(%[[VAL_12]]) { +// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -76,21 +67,21 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_29:.*]] = aie.switchbox(%[[VAL_10]]) { +// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_30:.*]] = aie.shim_mux(%[[VAL_10]]) { +// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_31:.*]] = aie.switchbox(%[[VAL_11]]) { +// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_32:.*]] = aie.switchbox(%[[VAL_13]]) { +// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -98,82 +89,82 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_33:.*]] = aie.shim_mux(%[[VAL_11]]) { +// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_34:.*]] = aie.switchbox(%[[VAL_14]]) { +// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.shim_mux(%[[VAL_7]]) { +// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_36:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_37:.*]] = aie.switchbox(%[[VAL_36]]) { +// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) +// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_38:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_39:.*]] = aie.switchbox(%[[VAL_38]]) { +// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) +// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_40:.*]] = aie.switchbox(%[[VAL_16]]) { +// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_41:.*]] = aie.switchbox(%[[VAL_17]]) { +// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_42:.*]] : North, %[[VAL_43:.*]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_42]] : DMA) -// CHECK: aie.wire(%[[VAL_43]] : East, %[[VAL_44:.*]] : West) -// CHECK: aie.wire(%[[VAL_45:.*]] : North, %[[VAL_44]] : South) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_45]] : DMA) -// CHECK: aie.wire(%[[VAL_9]] : Core, %[[VAL_46:.*]] : Core) -// CHECK: aie.wire(%[[VAL_9]] : DMA, %[[VAL_46]] : DMA) -// CHECK: aie.wire(%[[VAL_44]] : North, %[[VAL_46]] : South) -// CHECK: aie.wire(%[[VAL_44]] : East, %[[VAL_47:.*]] : West) -// CHECK: aie.wire(%[[VAL_46]] : East, %[[VAL_48:.*]] : West) -// CHECK: aie.wire(%[[VAL_22]] : Core, %[[VAL_48]] : Core) -// CHECK: aie.wire(%[[VAL_22]] : DMA, %[[VAL_48]] : DMA) -// CHECK: aie.wire(%[[VAL_47]] : North, %[[VAL_48]] : South) -// CHECK: aie.wire(%[[VAL_48]] : East, %[[VAL_49:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_49]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_49]] : DMA) -// CHECK: aie.wire(%[[VAL_50:.*]] : North, %[[VAL_51:.*]] : South) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_50]] : DMA) -// CHECK: aie.wire(%[[VAL_49]] : East, %[[VAL_52:.*]] : West) -// CHECK: aie.wire(%[[VAL_26]] : Core, %[[VAL_52]] : Core) -// CHECK: aie.wire(%[[VAL_26]] : DMA, %[[VAL_52]] : DMA) -// CHECK: aie.wire(%[[VAL_51]] : North, %[[VAL_52]] : South) -// CHECK: aie.wire(%[[VAL_38]] : Core, %[[VAL_53:.*]] : Core) -// CHECK: aie.wire(%[[VAL_38]] : DMA, %[[VAL_53]] : DMA) -// CHECK: aie.wire(%[[VAL_52]] : North, %[[VAL_53]] : South) -// CHECK: aie.wire(%[[VAL_51]] : East, %[[VAL_54:.*]] : West) -// CHECK: aie.wire(%[[VAL_55:.*]] : North, %[[VAL_54]] : South) -// CHECK: aie.wire(%[[VAL_11]] : DMA, %[[VAL_55]] : DMA) -// CHECK: aie.wire(%[[VAL_52]] : East, %[[VAL_56:.*]] : West) -// CHECK: aie.wire(%[[VAL_12]] : Core, %[[VAL_56]] : Core) -// CHECK: aie.wire(%[[VAL_12]] : DMA, %[[VAL_56]] : DMA) -// CHECK: aie.wire(%[[VAL_54]] : North, %[[VAL_56]] : South) -// CHECK: aie.wire(%[[VAL_53]] : East, %[[VAL_57:.*]] : West) -// CHECK: aie.wire(%[[VAL_13]] : Core, %[[VAL_57]] : Core) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_57]] : DMA) -// CHECK: aie.wire(%[[VAL_56]] : North, %[[VAL_57]] : South) -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_58:.*]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_58]] : DMA) -// CHECK: aie.wire(%[[VAL_57]] : North, %[[VAL_58]] : South) -// CHECK: aie.wire(%[[VAL_57]] : East, %[[VAL_59:.*]] : West) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_59]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_59]] : DMA) -// CHECK: aie.wire(%[[VAL_58]] : East, %[[VAL_60:.*]] : West) -// CHECK: aie.wire(%[[VAL_17]] : Core, %[[VAL_60]] : Core) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_60]] : DMA) -// CHECK: aie.wire(%[[VAL_59]] : North, %[[VAL_60]] : South) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) +// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) +// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : North, %[[SWITCHBOX_4_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) +// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) +// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) +// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) +// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) +// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) +// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) +// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) +// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) +// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) +// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) // CHECK: } module { @@ -196,7 +187,6 @@ module { %t80 = aie.tile(8, 0) %t82 = aie.tile(8, 2) %t83 = aie.tile(8, 3) - aie.flow(%t71, DMA : 0, %t20, DMA : 0) aie.flow(%t71, DMA : 1, %t20, DMA : 1) aie.flow(%t72, DMA : 0, %t60, DMA : 0) @@ -207,4 +197,3 @@ module { aie.flow(%t83, DMA : 1, %t30, DMA : 1) } } - diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x1.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x1.mlir index 49e98b834..329bc2078 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x1.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x1.mlir @@ -1,247 +1,238 @@ -//===- routed_herd_3x1.mlir ------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_3:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_4:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_5:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_6:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_8:.*]] = aie.tile(8, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(9, 0) -// CHECK: %[[VAL_10:.*]] = aie.tile(10, 0) -// CHECK: %[[VAL_11:.*]] = aie.tile(11, 0) -// CHECK: %[[VAL_12:.*]] = aie.tile(18, 0) -// CHECK: %[[VAL_13:.*]] = aie.tile(19, 0) -// CHECK: %[[VAL_14:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_15:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_16:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_17:.*]] = aie.tile(0, 4) -// CHECK: %[[VAL_18:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_19:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_20:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_21:.*]] = aie.tile(1, 4) -// CHECK: %[[VAL_22:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_23:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_24:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_25:.*]] = aie.tile(2, 4) -// CHECK: %[[VAL_26:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_27:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_28:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_29:.*]] = aie.tile(3, 4) -// CHECK: %[[VAL_30:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_31:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_32:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_33:.*]] = aie.tile(4, 4) -// CHECK: %[[VAL_34:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_35:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_36:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_37:.*]] = aie.tile(5, 4) -// CHECK: %[[VAL_38:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_39:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_40:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_41:.*]] = aie.tile(6, 4) -// CHECK: %[[VAL_42:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_43:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_44:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_45:.*]] = aie.tile(7, 4) -// CHECK: %[[VAL_46:.*]] = aie.tile(8, 1) -// CHECK: %[[VAL_47:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_48:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_49:.*]] = aie.tile(8, 4) -// CHECK: %[[VAL_50:.*]] = aie.tile(9, 1) -// CHECK: %[[VAL_51:.*]] = aie.tile(9, 2) -// CHECK: %[[VAL_52:.*]] = aie.tile(9, 3) -// CHECK: %[[VAL_53:.*]] = aie.tile(9, 4) -// CHECK: %[[VAL_54:.*]] = aie.tile(10, 1) -// CHECK: %[[VAL_55:.*]] = aie.tile(10, 2) -// CHECK: %[[VAL_56:.*]] = aie.tile(10, 3) -// CHECK: %[[VAL_57:.*]] = aie.tile(10, 4) -// CHECK: %[[VAL_58:.*]] = aie.tile(11, 1) -// CHECK: %[[VAL_59:.*]] = aie.tile(11, 2) -// CHECK: %[[VAL_60:.*]] = aie.tile(11, 3) -// CHECK: %[[VAL_61:.*]] = aie.tile(11, 4) -// CHECK: %[[VAL_62:.*]] = aie.tile(12, 1) -// CHECK: %[[VAL_63:.*]] = aie.tile(12, 2) -// CHECK: %[[VAL_64:.*]] = aie.tile(12, 3) -// CHECK: %[[VAL_65:.*]] = aie.tile(12, 4) -// CHECK: %[[VAL_66:.*]] = aie.switchbox(%[[VAL_14]]) { +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) +// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) +// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) +// CHECK: %[[TILE_9_0:.*]] = aie.tile(9, 0) +// CHECK: %[[TILE_10_0:.*]] = aie.tile(10, 0) +// CHECK: %[[TILE_11_0:.*]] = aie.tile(11, 0) +// CHECK: %[[TILE_18_0:.*]] = aie.tile(18, 0) +// CHECK: %[[TILE_19_0:.*]] = aie.tile(19, 0) +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_0_4:.*]] = aie.tile(0, 4) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_1_4:.*]] = aie.tile(1, 4) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_2_4:.*]] = aie.tile(2, 4) +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) +// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) +// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) +// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) +// CHECK: %[[TILE_4_4:.*]] = aie.tile(4, 4) +// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) +// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) +// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) +// CHECK: %[[TILE_5_4:.*]] = aie.tile(5, 4) +// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) +// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) +// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) +// CHECK: %[[TILE_6_4:.*]] = aie.tile(6, 4) +// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) +// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) +// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) +// CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) +// CHECK: %[[TILE_8_1:.*]] = aie.tile(8, 1) +// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) +// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) +// CHECK: %[[TILE_8_4:.*]] = aie.tile(8, 4) +// CHECK: %[[TILE_9_1:.*]] = aie.tile(9, 1) +// CHECK: %[[TILE_9_2:.*]] = aie.tile(9, 2) +// CHECK: %[[TILE_9_3:.*]] = aie.tile(9, 3) +// CHECK: %[[TILE_9_4:.*]] = aie.tile(9, 4) +// CHECK: %[[TILE_10_1:.*]] = aie.tile(10, 1) +// CHECK: %[[TILE_10_2:.*]] = aie.tile(10, 2) +// CHECK: %[[TILE_10_3:.*]] = aie.tile(10, 3) +// CHECK: %[[TILE_10_4:.*]] = aie.tile(10, 4) +// CHECK: %[[TILE_11_1:.*]] = aie.tile(11, 1) +// CHECK: %[[TILE_11_2:.*]] = aie.tile(11, 2) +// CHECK: %[[TILE_11_3:.*]] = aie.tile(11, 3) +// CHECK: %[[TILE_11_4:.*]] = aie.tile(11, 4) +// CHECK: %[[TILE_12_1:.*]] = aie.tile(12, 1) +// CHECK: %[[TILE_12_2:.*]] = aie.tile(12, 2) +// CHECK: %[[TILE_12_3:.*]] = aie.tile(12, 3) +// CHECK: %[[TILE_12_4:.*]] = aie.tile(12, 4) +// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_67:.*]] = aie.switchbox(%[[VAL_15]]) { +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_68:.*]] = aie.switchbox(%[[VAL_16]]) { +// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_69:.*]] = aie.switchbox(%[[VAL_17]]) { +// CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { // CHECK: } -// CHECK: %[[VAL_70:.*]] = aie.switchbox(%[[VAL_18]]) { +// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_71:.*]] = aie.switchbox(%[[VAL_19]]) { +// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_72:.*]] = aie.switchbox(%[[VAL_20]]) { +// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_73:.*]] = aie.switchbox(%[[VAL_21]]) { +// CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_74:.*]] = aie.switchbox(%[[VAL_22]]) { +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_75:.*]] = aie.switchbox(%[[VAL_23]]) { +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_76:.*]] = aie.switchbox(%[[VAL_24]]) { +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_77:.*]] = aie.switchbox(%[[VAL_25]]) { +// CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_78:.*]] = aie.switchbox(%[[VAL_26]]) { +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_79:.*]] = aie.switchbox(%[[VAL_27]]) { +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_80:.*]] = aie.switchbox(%[[VAL_28]]) { +// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_81:.*]] = aie.switchbox(%[[VAL_29]]) { +// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { // CHECK: } -// CHECK: %[[VAL_82:.*]] = aie.switchbox(%[[VAL_30]]) { +// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_83:.*]] = aie.switchbox(%[[VAL_31]]) { +// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_84:.*]] = aie.switchbox(%[[VAL_32]]) { +// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { // CHECK: } -// CHECK: %[[VAL_85:.*]] = aie.switchbox(%[[VAL_33]]) { +// CHECK: %[[SWITCHBOX_4_4:.*]] = aie.switchbox(%[[TILE_4_4]]) { // CHECK: } -// CHECK: %[[VAL_86:.*]] = aie.switchbox(%[[VAL_34]]) { +// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_87:.*]] = aie.switchbox(%[[VAL_35]]) { +// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_88:.*]] = aie.switchbox(%[[VAL_36]]) { +// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_89:.*]] = aie.switchbox(%[[VAL_37]]) { +// CHECK: %[[SWITCHBOX_5_4:.*]] = aie.switchbox(%[[TILE_5_4]]) { // CHECK: } -// CHECK: %[[VAL_90:.*]] = aie.switchbox(%[[VAL_38]]) { +// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_91:.*]] = aie.switchbox(%[[VAL_39]]) { +// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_92:.*]] = aie.switchbox(%[[VAL_40]]) { +// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_93:.*]] = aie.switchbox(%[[VAL_41]]) { +// CHECK: %[[SWITCHBOX_6_4:.*]] = aie.switchbox(%[[TILE_6_4]]) { // CHECK: } -// CHECK: %[[VAL_94:.*]] = aie.switchbox(%[[VAL_42]]) { +// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_95:.*]] = aie.switchbox(%[[VAL_43]]) { +// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_96:.*]] = aie.switchbox(%[[VAL_44]]) { +// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_97:.*]] = aie.switchbox(%[[VAL_45]]) { +// CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_98:.*]] = aie.switchbox(%[[VAL_46]]) { +// CHECK: %[[SWITCHBOX_8_1:.*]] = aie.switchbox(%[[TILE_8_1]]) { // CHECK: } -// CHECK: %[[VAL_99:.*]] = aie.switchbox(%[[VAL_47]]) { +// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { // CHECK: } -// CHECK: %[[VAL_100:.*]] = aie.switchbox(%[[VAL_48]]) { +// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { // CHECK: } -// CHECK: %[[VAL_101:.*]] = aie.switchbox(%[[VAL_49]]) { +// CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { // CHECK: } -// CHECK: %[[VAL_102:.*]] = aie.switchbox(%[[VAL_50]]) { +// CHECK: %[[SWITCHBOX_9_1:.*]] = aie.switchbox(%[[TILE_9_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_103:.*]] = aie.switchbox(%[[VAL_51]]) { +// CHECK: %[[SWITCHBOX_9_2:.*]] = aie.switchbox(%[[TILE_9_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_104:.*]] = aie.switchbox(%[[VAL_52]]) { +// CHECK: %[[SWITCHBOX_9_3:.*]] = aie.switchbox(%[[TILE_9_3]]) { // CHECK: } -// CHECK: %[[VAL_105:.*]] = aie.switchbox(%[[VAL_53]]) { +// CHECK: %[[SWITCHBOX_9_4:.*]] = aie.switchbox(%[[TILE_9_4]]) { // CHECK: } -// CHECK: %[[VAL_106:.*]] = aie.switchbox(%[[VAL_54]]) { +// CHECK: %[[SWITCHBOX_10_1:.*]] = aie.switchbox(%[[TILE_10_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_107:.*]] = aie.switchbox(%[[VAL_55]]) { +// CHECK: %[[SWITCHBOX_10_2:.*]] = aie.switchbox(%[[TILE_10_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_108:.*]] = aie.switchbox(%[[VAL_56]]) { +// CHECK: %[[SWITCHBOX_10_3:.*]] = aie.switchbox(%[[TILE_10_3]]) { // CHECK: } -// CHECK: %[[VAL_109:.*]] = aie.switchbox(%[[VAL_57]]) { +// CHECK: %[[SWITCHBOX_10_4:.*]] = aie.switchbox(%[[TILE_10_4]]) { // CHECK: } -// CHECK: %[[VAL_110:.*]] = aie.switchbox(%[[VAL_58]]) { +// CHECK: %[[SWITCHBOX_11_1:.*]] = aie.switchbox(%[[TILE_11_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_111:.*]] = aie.switchbox(%[[VAL_59]]) { +// CHECK: %[[SWITCHBOX_11_2:.*]] = aie.switchbox(%[[TILE_11_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_112:.*]] = aie.switchbox(%[[VAL_60]]) { +// CHECK: %[[SWITCHBOX_11_3:.*]] = aie.switchbox(%[[TILE_11_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_113:.*]] = aie.switchbox(%[[VAL_61]]) { +// CHECK: %[[SWITCHBOX_11_4:.*]] = aie.switchbox(%[[TILE_11_4]]) { // CHECK: } -// CHECK: %[[VAL_114:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_115:.*]] = aie.shim_mux(%[[VAL_2]]) { +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_116:.*]] = aie.switchbox(%[[VAL_3]]) { +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_117:.*]] = aie.switchbox(%[[VAL_4]]) { +// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_118:.*]] = aie.switchbox(%[[VAL_5]]) { +// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -249,7 +240,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_119:.*]] = aie.switchbox(%[[VAL_6]]) { +// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -258,343 +249,343 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_120:.*]] = aie.shim_mux(%[[VAL_3]]) { +// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_121:.*]] = aie.switchbox(%[[VAL_7]]) { +// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_122:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: %[[SWITCHBOX_0_0:.*]] = aie.switchbox(%[[TILE_0_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_123:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[SWITCHBOX_1_0:.*]] = aie.switchbox(%[[TILE_1_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_124:.*]] = aie.shim_mux(%[[VAL_6]]) { +// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_125:.*]] = aie.shim_mux(%[[VAL_7]]) { +// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_126:.*]] = aie.switchbox(%[[VAL_10]]) { +// CHECK: %[[SWITCHBOX_10_0:.*]] = aie.switchbox(%[[TILE_10_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_127:.*]] = aie.shim_mux(%[[VAL_10]]) { +// CHECK: %[[SHIM_MUX_10_0:.*]] = aie.shim_mux(%[[TILE_10_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_128:.*]] = aie.switchbox(%[[VAL_11]]) { +// CHECK: %[[SWITCHBOX_11_0:.*]] = aie.switchbox(%[[TILE_11_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_129:.*]] = aie.shim_mux(%[[VAL_11]]) { +// CHECK: %[[SHIM_MUX_11_0:.*]] = aie.shim_mux(%[[TILE_11_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_130:.*]] = aie.switchbox(%[[VAL_8]]) { +// CHECK: %[[SWITCHBOX_8_0:.*]] = aie.switchbox(%[[TILE_8_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_131:.*]] = aie.switchbox(%[[VAL_9]]) { +// CHECK: %[[SWITCHBOX_9_0:.*]] = aie.switchbox(%[[TILE_9_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_132:.*]] = aie.tile(12, 0) -// CHECK: %[[VAL_133:.*]] = aie.switchbox(%[[VAL_132]]) { +// CHECK: %[[TILE_12_0:.*]] = aie.tile(12, 0) +// CHECK: %[[SWITCHBOX_12_0:.*]] = aie.switchbox(%[[TILE_12_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_134:.*]] = aie.tile(13, 0) -// CHECK: %[[VAL_135:.*]] = aie.switchbox(%[[VAL_134]]) { +// CHECK: %[[TILE_13_0:.*]] = aie.tile(13, 0) +// CHECK: %[[SWITCHBOX_13_0:.*]] = aie.switchbox(%[[TILE_13_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_136:.*]] = aie.tile(14, 0) -// CHECK: %[[VAL_137:.*]] = aie.switchbox(%[[VAL_136]]) { +// CHECK: %[[TILE_14_0:.*]] = aie.tile(14, 0) +// CHECK: %[[SWITCHBOX_14_0:.*]] = aie.switchbox(%[[TILE_14_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_138:.*]] = aie.tile(15, 0) -// CHECK: %[[VAL_139:.*]] = aie.switchbox(%[[VAL_138]]) { +// CHECK: %[[TILE_15_0:.*]] = aie.tile(15, 0) +// CHECK: %[[SWITCHBOX_15_0:.*]] = aie.switchbox(%[[TILE_15_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_140:.*]] = aie.tile(16, 0) -// CHECK: %[[VAL_141:.*]] = aie.switchbox(%[[VAL_140]]) { +// CHECK: %[[TILE_16_0:.*]] = aie.tile(16, 0) +// CHECK: %[[SWITCHBOX_16_0:.*]] = aie.switchbox(%[[TILE_16_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_142:.*]] = aie.tile(17, 0) -// CHECK: %[[VAL_143:.*]] = aie.switchbox(%[[VAL_142]]) { +// CHECK: %[[TILE_17_0:.*]] = aie.tile(17, 0) +// CHECK: %[[SWITCHBOX_17_0:.*]] = aie.switchbox(%[[TILE_17_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_144:.*]] = aie.switchbox(%[[VAL_12]]) { +// CHECK: %[[SWITCHBOX_18_0:.*]] = aie.switchbox(%[[TILE_18_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_145:.*]] = aie.shim_mux(%[[VAL_12]]) { +// CHECK: %[[SHIM_MUX_18_0:.*]] = aie.shim_mux(%[[TILE_18_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_146:.*]] = aie.switchbox(%[[VAL_13]]) { +// CHECK: %[[SWITCHBOX_19_0:.*]] = aie.switchbox(%[[TILE_19_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_147:.*]] = aie.shim_mux(%[[VAL_13]]) { +// CHECK: %[[SHIM_MUX_19_0:.*]] = aie.shim_mux(%[[TILE_19_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_148:.*]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_148]] : DMA) -// CHECK: aie.wire(%[[VAL_149:.*]] : North, %[[VAL_148]] : South) -// CHECK: aie.wire(%[[VAL_15]] : Core, %[[VAL_150:.*]] : Core) -// CHECK: aie.wire(%[[VAL_15]] : DMA, %[[VAL_150]] : DMA) -// CHECK: aie.wire(%[[VAL_148]] : North, %[[VAL_150]] : South) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_151:.*]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_151]] : DMA) -// CHECK: aie.wire(%[[VAL_150]] : North, %[[VAL_151]] : South) -// CHECK: aie.wire(%[[VAL_17]] : Core, %[[VAL_152:.*]] : Core) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_152]] : DMA) -// CHECK: aie.wire(%[[VAL_151]] : North, %[[VAL_152]] : South) -// CHECK: aie.wire(%[[VAL_149]] : East, %[[VAL_153:.*]] : West) -// CHECK: aie.wire(%[[VAL_148]] : East, %[[VAL_154:.*]] : West) -// CHECK: aie.wire(%[[VAL_18]] : Core, %[[VAL_154]] : Core) -// CHECK: aie.wire(%[[VAL_18]] : DMA, %[[VAL_154]] : DMA) -// CHECK: aie.wire(%[[VAL_153]] : North, %[[VAL_154]] : South) -// CHECK: aie.wire(%[[VAL_150]] : East, %[[VAL_155:.*]] : West) -// CHECK: aie.wire(%[[VAL_19]] : Core, %[[VAL_155]] : Core) -// CHECK: aie.wire(%[[VAL_19]] : DMA, %[[VAL_155]] : DMA) -// CHECK: aie.wire(%[[VAL_154]] : North, %[[VAL_155]] : South) -// CHECK: aie.wire(%[[VAL_151]] : East, %[[VAL_156:.*]] : West) -// CHECK: aie.wire(%[[VAL_20]] : Core, %[[VAL_156]] : Core) -// CHECK: aie.wire(%[[VAL_20]] : DMA, %[[VAL_156]] : DMA) -// CHECK: aie.wire(%[[VAL_155]] : North, %[[VAL_156]] : South) -// CHECK: aie.wire(%[[VAL_152]] : East, %[[VAL_157:.*]] : West) -// CHECK: aie.wire(%[[VAL_21]] : Core, %[[VAL_157]] : Core) -// CHECK: aie.wire(%[[VAL_21]] : DMA, %[[VAL_157]] : DMA) -// CHECK: aie.wire(%[[VAL_156]] : North, %[[VAL_157]] : South) -// CHECK: aie.wire(%[[VAL_153]] : East, %[[VAL_158:.*]] : West) -// CHECK: aie.wire(%[[VAL_159:.*]] : North, %[[VAL_158]] : South) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_159]] : DMA) -// CHECK: aie.wire(%[[VAL_154]] : East, %[[VAL_160:.*]] : West) -// CHECK: aie.wire(%[[VAL_22]] : Core, %[[VAL_160]] : Core) -// CHECK: aie.wire(%[[VAL_22]] : DMA, %[[VAL_160]] : DMA) -// CHECK: aie.wire(%[[VAL_158]] : North, %[[VAL_160]] : South) -// CHECK: aie.wire(%[[VAL_155]] : East, %[[VAL_161:.*]] : West) -// CHECK: aie.wire(%[[VAL_23]] : Core, %[[VAL_161]] : Core) -// CHECK: aie.wire(%[[VAL_23]] : DMA, %[[VAL_161]] : DMA) -// CHECK: aie.wire(%[[VAL_160]] : North, %[[VAL_161]] : South) -// CHECK: aie.wire(%[[VAL_156]] : East, %[[VAL_162:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_162]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_162]] : DMA) -// CHECK: aie.wire(%[[VAL_161]] : North, %[[VAL_162]] : South) -// CHECK: aie.wire(%[[VAL_157]] : East, %[[VAL_163:.*]] : West) -// CHECK: aie.wire(%[[VAL_25]] : Core, %[[VAL_163]] : Core) -// CHECK: aie.wire(%[[VAL_25]] : DMA, %[[VAL_163]] : DMA) -// CHECK: aie.wire(%[[VAL_162]] : North, %[[VAL_163]] : South) -// CHECK: aie.wire(%[[VAL_158]] : East, %[[VAL_164:.*]] : West) -// CHECK: aie.wire(%[[VAL_165:.*]] : North, %[[VAL_164]] : South) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_165]] : DMA) -// CHECK: aie.wire(%[[VAL_160]] : East, %[[VAL_166:.*]] : West) -// CHECK: aie.wire(%[[VAL_26]] : Core, %[[VAL_166]] : Core) -// CHECK: aie.wire(%[[VAL_26]] : DMA, %[[VAL_166]] : DMA) -// CHECK: aie.wire(%[[VAL_164]] : North, %[[VAL_166]] : South) -// CHECK: aie.wire(%[[VAL_161]] : East, %[[VAL_167:.*]] : West) -// CHECK: aie.wire(%[[VAL_27]] : Core, %[[VAL_167]] : Core) -// CHECK: aie.wire(%[[VAL_27]] : DMA, %[[VAL_167]] : DMA) -// CHECK: aie.wire(%[[VAL_166]] : North, %[[VAL_167]] : South) -// CHECK: aie.wire(%[[VAL_162]] : East, %[[VAL_168:.*]] : West) -// CHECK: aie.wire(%[[VAL_28]] : Core, %[[VAL_168]] : Core) -// CHECK: aie.wire(%[[VAL_28]] : DMA, %[[VAL_168]] : DMA) -// CHECK: aie.wire(%[[VAL_167]] : North, %[[VAL_168]] : South) -// CHECK: aie.wire(%[[VAL_163]] : East, %[[VAL_169:.*]] : West) -// CHECK: aie.wire(%[[VAL_29]] : Core, %[[VAL_169]] : Core) -// CHECK: aie.wire(%[[VAL_29]] : DMA, %[[VAL_169]] : DMA) -// CHECK: aie.wire(%[[VAL_168]] : North, %[[VAL_169]] : South) -// CHECK: aie.wire(%[[VAL_164]] : East, %[[VAL_170:.*]] : West) -// CHECK: aie.wire(%[[VAL_166]] : East, %[[VAL_171:.*]] : West) -// CHECK: aie.wire(%[[VAL_30]] : Core, %[[VAL_171]] : Core) -// CHECK: aie.wire(%[[VAL_30]] : DMA, %[[VAL_171]] : DMA) -// CHECK: aie.wire(%[[VAL_170]] : North, %[[VAL_171]] : South) -// CHECK: aie.wire(%[[VAL_167]] : East, %[[VAL_172:.*]] : West) -// CHECK: aie.wire(%[[VAL_31]] : Core, %[[VAL_172]] : Core) -// CHECK: aie.wire(%[[VAL_31]] : DMA, %[[VAL_172]] : DMA) -// CHECK: aie.wire(%[[VAL_171]] : North, %[[VAL_172]] : South) -// CHECK: aie.wire(%[[VAL_168]] : East, %[[VAL_173:.*]] : West) -// CHECK: aie.wire(%[[VAL_32]] : Core, %[[VAL_173]] : Core) -// CHECK: aie.wire(%[[VAL_32]] : DMA, %[[VAL_173]] : DMA) -// CHECK: aie.wire(%[[VAL_172]] : North, %[[VAL_173]] : South) -// CHECK: aie.wire(%[[VAL_169]] : East, %[[VAL_174:.*]] : West) -// CHECK: aie.wire(%[[VAL_33]] : Core, %[[VAL_174]] : Core) -// CHECK: aie.wire(%[[VAL_33]] : DMA, %[[VAL_174]] : DMA) -// CHECK: aie.wire(%[[VAL_173]] : North, %[[VAL_174]] : South) -// CHECK: aie.wire(%[[VAL_170]] : East, %[[VAL_175:.*]] : West) -// CHECK: aie.wire(%[[VAL_171]] : East, %[[VAL_176:.*]] : West) -// CHECK: aie.wire(%[[VAL_34]] : Core, %[[VAL_176]] : Core) -// CHECK: aie.wire(%[[VAL_34]] : DMA, %[[VAL_176]] : DMA) -// CHECK: aie.wire(%[[VAL_175]] : North, %[[VAL_176]] : South) -// CHECK: aie.wire(%[[VAL_172]] : East, %[[VAL_177:.*]] : West) -// CHECK: aie.wire(%[[VAL_35]] : Core, %[[VAL_177]] : Core) -// CHECK: aie.wire(%[[VAL_35]] : DMA, %[[VAL_177]] : DMA) -// CHECK: aie.wire(%[[VAL_176]] : North, %[[VAL_177]] : South) -// CHECK: aie.wire(%[[VAL_173]] : East, %[[VAL_178:.*]] : West) -// CHECK: aie.wire(%[[VAL_36]] : Core, %[[VAL_178]] : Core) -// CHECK: aie.wire(%[[VAL_36]] : DMA, %[[VAL_178]] : DMA) -// CHECK: aie.wire(%[[VAL_177]] : North, %[[VAL_178]] : South) -// CHECK: aie.wire(%[[VAL_174]] : East, %[[VAL_179:.*]] : West) -// CHECK: aie.wire(%[[VAL_37]] : Core, %[[VAL_179]] : Core) -// CHECK: aie.wire(%[[VAL_37]] : DMA, %[[VAL_179]] : DMA) -// CHECK: aie.wire(%[[VAL_178]] : North, %[[VAL_179]] : South) -// CHECK: aie.wire(%[[VAL_175]] : East, %[[VAL_180:.*]] : West) -// CHECK: aie.wire(%[[VAL_181:.*]] : North, %[[VAL_180]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_181]] : DMA) -// CHECK: aie.wire(%[[VAL_176]] : East, %[[VAL_182:.*]] : West) -// CHECK: aie.wire(%[[VAL_38]] : Core, %[[VAL_182]] : Core) -// CHECK: aie.wire(%[[VAL_38]] : DMA, %[[VAL_182]] : DMA) -// CHECK: aie.wire(%[[VAL_180]] : North, %[[VAL_182]] : South) -// CHECK: aie.wire(%[[VAL_177]] : East, %[[VAL_183:.*]] : West) -// CHECK: aie.wire(%[[VAL_39]] : Core, %[[VAL_183]] : Core) -// CHECK: aie.wire(%[[VAL_39]] : DMA, %[[VAL_183]] : DMA) -// CHECK: aie.wire(%[[VAL_182]] : North, %[[VAL_183]] : South) -// CHECK: aie.wire(%[[VAL_178]] : East, %[[VAL_184:.*]] : West) -// CHECK: aie.wire(%[[VAL_40]] : Core, %[[VAL_184]] : Core) -// CHECK: aie.wire(%[[VAL_40]] : DMA, %[[VAL_184]] : DMA) -// CHECK: aie.wire(%[[VAL_183]] : North, %[[VAL_184]] : South) -// CHECK: aie.wire(%[[VAL_179]] : East, %[[VAL_185:.*]] : West) -// CHECK: aie.wire(%[[VAL_41]] : Core, %[[VAL_185]] : Core) -// CHECK: aie.wire(%[[VAL_41]] : DMA, %[[VAL_185]] : DMA) -// CHECK: aie.wire(%[[VAL_184]] : North, %[[VAL_185]] : South) -// CHECK: aie.wire(%[[VAL_180]] : East, %[[VAL_186:.*]] : West) -// CHECK: aie.wire(%[[VAL_187:.*]] : North, %[[VAL_186]] : South) -// CHECK: aie.wire(%[[VAL_7]] : DMA, %[[VAL_187]] : DMA) -// CHECK: aie.wire(%[[VAL_182]] : East, %[[VAL_188:.*]] : West) -// CHECK: aie.wire(%[[VAL_42]] : Core, %[[VAL_188]] : Core) -// CHECK: aie.wire(%[[VAL_42]] : DMA, %[[VAL_188]] : DMA) -// CHECK: aie.wire(%[[VAL_186]] : North, %[[VAL_188]] : South) -// CHECK: aie.wire(%[[VAL_183]] : East, %[[VAL_189:.*]] : West) -// CHECK: aie.wire(%[[VAL_43]] : Core, %[[VAL_189]] : Core) -// CHECK: aie.wire(%[[VAL_43]] : DMA, %[[VAL_189]] : DMA) -// CHECK: aie.wire(%[[VAL_188]] : North, %[[VAL_189]] : South) -// CHECK: aie.wire(%[[VAL_184]] : East, %[[VAL_190:.*]] : West) -// CHECK: aie.wire(%[[VAL_44]] : Core, %[[VAL_190]] : Core) -// CHECK: aie.wire(%[[VAL_44]] : DMA, %[[VAL_190]] : DMA) -// CHECK: aie.wire(%[[VAL_189]] : North, %[[VAL_190]] : South) -// CHECK: aie.wire(%[[VAL_185]] : East, %[[VAL_191:.*]] : West) -// CHECK: aie.wire(%[[VAL_45]] : Core, %[[VAL_191]] : Core) -// CHECK: aie.wire(%[[VAL_45]] : DMA, %[[VAL_191]] : DMA) -// CHECK: aie.wire(%[[VAL_190]] : North, %[[VAL_191]] : South) -// CHECK: aie.wire(%[[VAL_186]] : East, %[[VAL_192:.*]] : West) -// CHECK: aie.wire(%[[VAL_188]] : East, %[[VAL_193:.*]] : West) -// CHECK: aie.wire(%[[VAL_46]] : Core, %[[VAL_193]] : Core) -// CHECK: aie.wire(%[[VAL_46]] : DMA, %[[VAL_193]] : DMA) -// CHECK: aie.wire(%[[VAL_192]] : North, %[[VAL_193]] : South) -// CHECK: aie.wire(%[[VAL_189]] : East, %[[VAL_194:.*]] : West) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_194]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_194]] : DMA) -// CHECK: aie.wire(%[[VAL_193]] : North, %[[VAL_194]] : South) -// CHECK: aie.wire(%[[VAL_190]] : East, %[[VAL_195:.*]] : West) -// CHECK: aie.wire(%[[VAL_48]] : Core, %[[VAL_195]] : Core) -// CHECK: aie.wire(%[[VAL_48]] : DMA, %[[VAL_195]] : DMA) -// CHECK: aie.wire(%[[VAL_194]] : North, %[[VAL_195]] : South) -// CHECK: aie.wire(%[[VAL_191]] : East, %[[VAL_196:.*]] : West) -// CHECK: aie.wire(%[[VAL_49]] : Core, %[[VAL_196]] : Core) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_196]] : DMA) -// CHECK: aie.wire(%[[VAL_195]] : North, %[[VAL_196]] : South) -// CHECK: aie.wire(%[[VAL_192]] : East, %[[VAL_197:.*]] : West) -// CHECK: aie.wire(%[[VAL_193]] : East, %[[VAL_198:.*]] : West) -// CHECK: aie.wire(%[[VAL_50]] : Core, %[[VAL_198]] : Core) -// CHECK: aie.wire(%[[VAL_50]] : DMA, %[[VAL_198]] : DMA) -// CHECK: aie.wire(%[[VAL_197]] : North, %[[VAL_198]] : South) -// CHECK: aie.wire(%[[VAL_194]] : East, %[[VAL_199:.*]] : West) -// CHECK: aie.wire(%[[VAL_51]] : Core, %[[VAL_199]] : Core) -// CHECK: aie.wire(%[[VAL_51]] : DMA, %[[VAL_199]] : DMA) -// CHECK: aie.wire(%[[VAL_198]] : North, %[[VAL_199]] : South) -// CHECK: aie.wire(%[[VAL_195]] : East, %[[VAL_200:.*]] : West) -// CHECK: aie.wire(%[[VAL_52]] : Core, %[[VAL_200]] : Core) -// CHECK: aie.wire(%[[VAL_52]] : DMA, %[[VAL_200]] : DMA) -// CHECK: aie.wire(%[[VAL_199]] : North, %[[VAL_200]] : South) -// CHECK: aie.wire(%[[VAL_196]] : East, %[[VAL_201:.*]] : West) -// CHECK: aie.wire(%[[VAL_53]] : Core, %[[VAL_201]] : Core) -// CHECK: aie.wire(%[[VAL_53]] : DMA, %[[VAL_201]] : DMA) -// CHECK: aie.wire(%[[VAL_200]] : North, %[[VAL_201]] : South) -// CHECK: aie.wire(%[[VAL_197]] : East, %[[VAL_202:.*]] : West) -// CHECK: aie.wire(%[[VAL_203:.*]] : North, %[[VAL_202]] : South) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_203]] : DMA) -// CHECK: aie.wire(%[[VAL_198]] : East, %[[VAL_204:.*]] : West) -// CHECK: aie.wire(%[[VAL_54]] : Core, %[[VAL_204]] : Core) -// CHECK: aie.wire(%[[VAL_54]] : DMA, %[[VAL_204]] : DMA) -// CHECK: aie.wire(%[[VAL_202]] : North, %[[VAL_204]] : South) -// CHECK: aie.wire(%[[VAL_199]] : East, %[[VAL_205:.*]] : West) -// CHECK: aie.wire(%[[VAL_55]] : Core, %[[VAL_205]] : Core) -// CHECK: aie.wire(%[[VAL_55]] : DMA, %[[VAL_205]] : DMA) -// CHECK: aie.wire(%[[VAL_204]] : North, %[[VAL_205]] : South) -// CHECK: aie.wire(%[[VAL_200]] : East, %[[VAL_206:.*]] : West) -// CHECK: aie.wire(%[[VAL_56]] : Core, %[[VAL_206]] : Core) -// CHECK: aie.wire(%[[VAL_56]] : DMA, %[[VAL_206]] : DMA) -// CHECK: aie.wire(%[[VAL_205]] : North, %[[VAL_206]] : South) -// CHECK: aie.wire(%[[VAL_201]] : East, %[[VAL_207:.*]] : West) -// CHECK: aie.wire(%[[VAL_57]] : Core, %[[VAL_207]] : Core) -// CHECK: aie.wire(%[[VAL_57]] : DMA, %[[VAL_207]] : DMA) -// CHECK: aie.wire(%[[VAL_206]] : North, %[[VAL_207]] : South) -// CHECK: aie.wire(%[[VAL_202]] : East, %[[VAL_208:.*]] : West) -// CHECK: aie.wire(%[[VAL_209:.*]] : North, %[[VAL_208]] : South) -// CHECK: aie.wire(%[[VAL_11]] : DMA, %[[VAL_209]] : DMA) -// CHECK: aie.wire(%[[VAL_204]] : East, %[[VAL_210:.*]] : West) -// CHECK: aie.wire(%[[VAL_58]] : Core, %[[VAL_210]] : Core) -// CHECK: aie.wire(%[[VAL_58]] : DMA, %[[VAL_210]] : DMA) -// CHECK: aie.wire(%[[VAL_208]] : North, %[[VAL_210]] : South) -// CHECK: aie.wire(%[[VAL_205]] : East, %[[VAL_211:.*]] : West) -// CHECK: aie.wire(%[[VAL_59]] : Core, %[[VAL_211]] : Core) -// CHECK: aie.wire(%[[VAL_59]] : DMA, %[[VAL_211]] : DMA) -// CHECK: aie.wire(%[[VAL_210]] : North, %[[VAL_211]] : South) -// CHECK: aie.wire(%[[VAL_206]] : East, %[[VAL_212:.*]] : West) -// CHECK: aie.wire(%[[VAL_60]] : Core, %[[VAL_212]] : Core) -// CHECK: aie.wire(%[[VAL_60]] : DMA, %[[VAL_212]] : DMA) -// CHECK: aie.wire(%[[VAL_211]] : North, %[[VAL_212]] : South) -// CHECK: aie.wire(%[[VAL_207]] : East, %[[VAL_213:.*]] : West) -// CHECK: aie.wire(%[[VAL_61]] : Core, %[[VAL_213]] : Core) -// CHECK: aie.wire(%[[VAL_61]] : DMA, %[[VAL_213]] : DMA) -// CHECK: aie.wire(%[[VAL_212]] : North, %[[VAL_213]] : South) -// CHECK: aie.wire(%[[VAL_208]] : East, %[[VAL_214:.*]] : West) -// CHECK: aie.wire(%[[VAL_214]] : East, %[[VAL_215:.*]] : West) -// CHECK: aie.wire(%[[VAL_215]] : East, %[[VAL_216:.*]] : West) -// CHECK: aie.wire(%[[VAL_216]] : East, %[[VAL_217:.*]] : West) -// CHECK: aie.wire(%[[VAL_217]] : East, %[[VAL_218:.*]] : West) -// CHECK: aie.wire(%[[VAL_218]] : East, %[[VAL_219:.*]] : West) -// CHECK: aie.wire(%[[VAL_219]] : East, %[[VAL_220:.*]] : West) -// CHECK: aie.wire(%[[VAL_221:.*]] : North, %[[VAL_220]] : South) -// CHECK: aie.wire(%[[VAL_12]] : DMA, %[[VAL_221]] : DMA) -// CHECK: aie.wire(%[[VAL_220]] : East, %[[VAL_222:.*]] : West) -// CHECK: aie.wire(%[[VAL_223:.*]] : North, %[[VAL_222]] : South) -// CHECK: aie.wire(%[[VAL_13]] : DMA, %[[VAL_223]] : DMA) +// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_0:.*]] : North, %[[SWITCHBOX_0_1]] : South) +// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) +// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) +// CHECK: aie.wire(%[[TILE_0_4]] : Core, %[[SWITCHBOX_0_4:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_4]] : DMA, %[[SWITCHBOX_0_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : North, %[[SWITCHBOX_0_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_0]] : East, %[[SWITCHBOX_1_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) +// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : North, %[[SWITCHBOX_1_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) +// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) +// CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : North, %[[SWITCHBOX_1_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_4]] : East, %[[SWITCHBOX_1_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_4]] : Core, %[[SWITCHBOX_1_4]] : Core) +// CHECK: aie.wire(%[[TILE_1_4]] : DMA, %[[SWITCHBOX_1_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : North, %[[SWITCHBOX_1_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_0]] : East, %[[SWITCHBOX_2_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : East, %[[SWITCHBOX_2_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3]] : Core) +// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_4]] : East, %[[SWITCHBOX_2_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_4]] : Core, %[[SWITCHBOX_2_4]] : Core) +// CHECK: aie.wire(%[[TILE_2_4]] : DMA, %[[SWITCHBOX_2_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : North, %[[SWITCHBOX_2_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) +// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : East, %[[SWITCHBOX_3_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3]] : Core) +// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_4]] : East, %[[SWITCHBOX_3_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_4]] : Core, %[[SWITCHBOX_3_4]] : Core) +// CHECK: aie.wire(%[[TILE_3_4]] : DMA, %[[SWITCHBOX_3_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : North, %[[SWITCHBOX_3_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) +// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : North, %[[SWITCHBOX_4_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) +// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) +// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : North, %[[SWITCHBOX_4_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_4]] : East, %[[SWITCHBOX_4_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_4]] : Core, %[[SWITCHBOX_4_4]] : Core) +// CHECK: aie.wire(%[[TILE_4_4]] : DMA, %[[SWITCHBOX_4_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : North, %[[SWITCHBOX_4_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : East, %[[SWITCHBOX_5_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) +// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : North, %[[SWITCHBOX_5_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) +// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) +// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_4]] : East, %[[SWITCHBOX_5_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_4]] : Core, %[[SWITCHBOX_5_4]] : Core) +// CHECK: aie.wire(%[[TILE_5_4]] : DMA, %[[SWITCHBOX_5_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : North, %[[SWITCHBOX_5_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) +// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) +// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) +// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) +// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_4]] : East, %[[SWITCHBOX_6_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_4]] : Core, %[[SWITCHBOX_6_4]] : Core) +// CHECK: aie.wire(%[[TILE_6_4]] : DMA, %[[SWITCHBOX_6_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : North, %[[SWITCHBOX_6_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) +// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) +// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) +// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) +// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_4]] : East, %[[SWITCHBOX_7_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_4]] : Core, %[[SWITCHBOX_7_4]] : Core) +// CHECK: aie.wire(%[[TILE_7_4]] : DMA, %[[SWITCHBOX_7_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : North, %[[SWITCHBOX_7_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : East, %[[SWITCHBOX_8_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : East, %[[SWITCHBOX_8_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_1]] : Core, %[[SWITCHBOX_8_1]] : Core) +// CHECK: aie.wire(%[[TILE_8_1]] : DMA, %[[SWITCHBOX_8_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_0]] : North, %[[SWITCHBOX_8_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) +// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : North, %[[SWITCHBOX_8_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) +// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : East, %[[SWITCHBOX_8_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_4]] : Core, %[[SWITCHBOX_8_4]] : Core) +// CHECK: aie.wire(%[[TILE_8_4]] : DMA, %[[SWITCHBOX_8_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : North, %[[SWITCHBOX_8_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_8_0]] : East, %[[SWITCHBOX_9_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : East, %[[SWITCHBOX_9_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_1]] : Core, %[[SWITCHBOX_9_1]] : Core) +// CHECK: aie.wire(%[[TILE_9_1]] : DMA, %[[SWITCHBOX_9_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_0]] : North, %[[SWITCHBOX_9_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : East, %[[SWITCHBOX_9_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_2]] : Core, %[[SWITCHBOX_9_2]] : Core) +// CHECK: aie.wire(%[[TILE_9_2]] : DMA, %[[SWITCHBOX_9_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_1]] : North, %[[SWITCHBOX_9_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : East, %[[SWITCHBOX_9_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_3]] : Core, %[[SWITCHBOX_9_3]] : Core) +// CHECK: aie.wire(%[[TILE_9_3]] : DMA, %[[SWITCHBOX_9_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : North, %[[SWITCHBOX_9_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_8_4]] : East, %[[SWITCHBOX_9_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_4]] : Core, %[[SWITCHBOX_9_4]] : Core) +// CHECK: aie.wire(%[[TILE_9_4]] : DMA, %[[SWITCHBOX_9_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_3]] : North, %[[SWITCHBOX_9_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_9_0]] : East, %[[SWITCHBOX_10_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_10_0:.*]] : North, %[[SWITCHBOX_10_0]] : South) +// CHECK: aie.wire(%[[TILE_10_0]] : DMA, %[[SHIM_MUX_10_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_1]] : East, %[[SWITCHBOX_10_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_1]] : Core, %[[SWITCHBOX_10_1]] : Core) +// CHECK: aie.wire(%[[TILE_10_1]] : DMA, %[[SWITCHBOX_10_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : North, %[[SWITCHBOX_10_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : East, %[[SWITCHBOX_10_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_2]] : Core, %[[SWITCHBOX_10_2]] : Core) +// CHECK: aie.wire(%[[TILE_10_2]] : DMA, %[[SWITCHBOX_10_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_1]] : North, %[[SWITCHBOX_10_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_9_3]] : East, %[[SWITCHBOX_10_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_3]] : Core, %[[SWITCHBOX_10_3]] : Core) +// CHECK: aie.wire(%[[TILE_10_3]] : DMA, %[[SWITCHBOX_10_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_2]] : North, %[[SWITCHBOX_10_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_9_4]] : East, %[[SWITCHBOX_10_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_4]] : Core, %[[SWITCHBOX_10_4]] : Core) +// CHECK: aie.wire(%[[TILE_10_4]] : DMA, %[[SWITCHBOX_10_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_3]] : North, %[[SWITCHBOX_10_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : East, %[[SWITCHBOX_11_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_11_0:.*]] : North, %[[SWITCHBOX_11_0]] : South) +// CHECK: aie.wire(%[[TILE_11_0]] : DMA, %[[SHIM_MUX_11_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_1]] : East, %[[SWITCHBOX_11_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_1]] : Core, %[[SWITCHBOX_11_1]] : Core) +// CHECK: aie.wire(%[[TILE_11_1]] : DMA, %[[SWITCHBOX_11_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_0]] : North, %[[SWITCHBOX_11_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_2]] : East, %[[SWITCHBOX_11_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_2]] : Core, %[[SWITCHBOX_11_2]] : Core) +// CHECK: aie.wire(%[[TILE_11_2]] : DMA, %[[SWITCHBOX_11_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_1]] : North, %[[SWITCHBOX_11_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_3]] : East, %[[SWITCHBOX_11_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_3]] : Core, %[[SWITCHBOX_11_3]] : Core) +// CHECK: aie.wire(%[[TILE_11_3]] : DMA, %[[SWITCHBOX_11_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_2]] : North, %[[SWITCHBOX_11_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_4]] : East, %[[SWITCHBOX_11_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_4]] : Core, %[[SWITCHBOX_11_4]] : Core) +// CHECK: aie.wire(%[[TILE_11_4]] : DMA, %[[SWITCHBOX_11_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_3]] : North, %[[SWITCHBOX_11_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_11_0]] : East, %[[SWITCHBOX_12_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_12_0]] : East, %[[SWITCHBOX_13_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_13_0]] : East, %[[SWITCHBOX_14_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_14_0]] : East, %[[SWITCHBOX_15_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_15_0]] : East, %[[SWITCHBOX_16_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_16_0]] : East, %[[SWITCHBOX_17_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_17_0]] : East, %[[SWITCHBOX_18_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_18_0:.*]] : North, %[[SWITCHBOX_18_0]] : South) +// CHECK: aie.wire(%[[TILE_18_0]] : DMA, %[[SHIM_MUX_18_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_18_0]] : East, %[[SWITCHBOX_19_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_19_0:.*]] : North, %[[SWITCHBOX_19_0]] : South) +// CHECK: aie.wire(%[[TILE_19_0]] : DMA, %[[SHIM_MUX_19_0]] : DMA) // CHECK: } module { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x2.mlir index 242634192..5fe7af528 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_routed_herd_3x2.mlir @@ -1,715 +1,706 @@ -//===- routed_herd_3x2.mlir ------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_3:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_4:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_5:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_6:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_7:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_8:.*]] = aie.tile(8, 0) -// CHECK: %[[VAL_9:.*]] = aie.tile(9, 0) -// CHECK: %[[VAL_10:.*]] = aie.tile(10, 0) -// CHECK: %[[VAL_11:.*]] = aie.tile(11, 0) -// CHECK: %[[VAL_12:.*]] = aie.tile(18, 0) -// CHECK: %[[VAL_13:.*]] = aie.tile(19, 0) -// CHECK: %[[VAL_14:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_15:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_16:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_17:.*]] = aie.tile(0, 4) -// CHECK: %[[VAL_18:.*]] = aie.tile(0, 5) -// CHECK: %[[VAL_19:.*]] = aie.tile(0, 6) -// CHECK: %[[VAL_20:.*]] = aie.tile(0, 7) -// CHECK: %[[VAL_21:.*]] = aie.tile(0, 8) -// CHECK: %[[VAL_22:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_23:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_24:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_25:.*]] = aie.tile(1, 4) -// CHECK: %[[VAL_26:.*]] = aie.tile(1, 5) -// CHECK: %[[VAL_27:.*]] = aie.tile(1, 6) -// CHECK: %[[VAL_28:.*]] = aie.tile(1, 7) -// CHECK: %[[VAL_29:.*]] = aie.tile(1, 8) -// CHECK: %[[VAL_30:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_31:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_32:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_33:.*]] = aie.tile(2, 4) -// CHECK: %[[VAL_34:.*]] = aie.tile(2, 5) -// CHECK: %[[VAL_35:.*]] = aie.tile(2, 6) -// CHECK: %[[VAL_36:.*]] = aie.tile(2, 7) -// CHECK: %[[VAL_37:.*]] = aie.tile(2, 8) -// CHECK: %[[VAL_38:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_39:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_40:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_41:.*]] = aie.tile(3, 4) -// CHECK: %[[VAL_42:.*]] = aie.tile(3, 5) -// CHECK: %[[VAL_43:.*]] = aie.tile(3, 6) -// CHECK: %[[VAL_44:.*]] = aie.tile(3, 7) -// CHECK: %[[VAL_45:.*]] = aie.tile(3, 8) -// CHECK: %[[VAL_46:.*]] = aie.tile(4, 1) -// CHECK: %[[VAL_47:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_48:.*]] = aie.tile(4, 3) -// CHECK: %[[VAL_49:.*]] = aie.tile(4, 4) -// CHECK: %[[VAL_50:.*]] = aie.tile(4, 5) -// CHECK: %[[VAL_51:.*]] = aie.tile(4, 6) -// CHECK: %[[VAL_52:.*]] = aie.tile(4, 7) -// CHECK: %[[VAL_53:.*]] = aie.tile(4, 8) -// CHECK: %[[VAL_54:.*]] = aie.tile(5, 1) -// CHECK: %[[VAL_55:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_56:.*]] = aie.tile(5, 3) -// CHECK: %[[VAL_57:.*]] = aie.tile(5, 4) -// CHECK: %[[VAL_58:.*]] = aie.tile(5, 5) -// CHECK: %[[VAL_59:.*]] = aie.tile(5, 6) -// CHECK: %[[VAL_60:.*]] = aie.tile(5, 7) -// CHECK: %[[VAL_61:.*]] = aie.tile(5, 8) -// CHECK: %[[VAL_62:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_63:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_64:.*]] = aie.tile(6, 3) -// CHECK: %[[VAL_65:.*]] = aie.tile(6, 4) -// CHECK: %[[VAL_66:.*]] = aie.tile(6, 5) -// CHECK: %[[VAL_67:.*]] = aie.tile(6, 6) -// CHECK: %[[VAL_68:.*]] = aie.tile(6, 7) -// CHECK: %[[VAL_69:.*]] = aie.tile(6, 8) -// CHECK: %[[VAL_70:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_71:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_72:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_73:.*]] = aie.tile(7, 4) -// CHECK: %[[VAL_74:.*]] = aie.tile(7, 5) -// CHECK: %[[VAL_75:.*]] = aie.tile(7, 6) -// CHECK: %[[VAL_76:.*]] = aie.tile(7, 7) -// CHECK: %[[VAL_77:.*]] = aie.tile(7, 8) -// CHECK: %[[VAL_78:.*]] = aie.tile(8, 1) -// CHECK: %[[VAL_79:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_80:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_81:.*]] = aie.tile(8, 4) -// CHECK: %[[VAL_82:.*]] = aie.tile(8, 5) -// CHECK: %[[VAL_83:.*]] = aie.tile(8, 6) -// CHECK: %[[VAL_84:.*]] = aie.tile(8, 7) -// CHECK: %[[VAL_85:.*]] = aie.tile(8, 8) -// CHECK: %[[VAL_86:.*]] = aie.tile(9, 1) -// CHECK: %[[VAL_87:.*]] = aie.tile(9, 2) -// CHECK: %[[VAL_88:.*]] = aie.tile(9, 3) -// CHECK: %[[VAL_89:.*]] = aie.tile(9, 4) -// CHECK: %[[VAL_90:.*]] = aie.tile(9, 5) -// CHECK: %[[VAL_91:.*]] = aie.tile(9, 6) -// CHECK: %[[VAL_92:.*]] = aie.tile(9, 7) -// CHECK: %[[VAL_93:.*]] = aie.tile(9, 8) -// CHECK: %[[VAL_94:.*]] = aie.tile(10, 1) -// CHECK: %[[VAL_95:.*]] = aie.tile(10, 2) -// CHECK: %[[VAL_96:.*]] = aie.tile(10, 3) -// CHECK: %[[VAL_97:.*]] = aie.tile(10, 4) -// CHECK: %[[VAL_98:.*]] = aie.tile(10, 5) -// CHECK: %[[VAL_99:.*]] = aie.tile(10, 6) -// CHECK: %[[VAL_100:.*]] = aie.tile(10, 7) -// CHECK: %[[VAL_101:.*]] = aie.tile(10, 8) -// CHECK: %[[VAL_102:.*]] = aie.tile(11, 1) -// CHECK: %[[VAL_103:.*]] = aie.tile(11, 2) -// CHECK: %[[VAL_104:.*]] = aie.tile(11, 3) -// CHECK: %[[VAL_105:.*]] = aie.tile(11, 4) -// CHECK: %[[VAL_106:.*]] = aie.tile(11, 5) -// CHECK: %[[VAL_107:.*]] = aie.tile(11, 6) -// CHECK: %[[VAL_108:.*]] = aie.tile(11, 7) -// CHECK: %[[VAL_109:.*]] = aie.tile(11, 8) -// CHECK: %[[VAL_110:.*]] = aie.tile(12, 1) -// CHECK: %[[VAL_111:.*]] = aie.tile(12, 2) -// CHECK: %[[VAL_112:.*]] = aie.tile(12, 3) -// CHECK: %[[VAL_113:.*]] = aie.tile(12, 4) -// CHECK: %[[VAL_114:.*]] = aie.tile(12, 5) -// CHECK: %[[VAL_115:.*]] = aie.tile(12, 6) -// CHECK: %[[VAL_116:.*]] = aie.tile(12, 7) -// CHECK: %[[VAL_117:.*]] = aie.tile(12, 8) -// CHECK: %[[VAL_118:.*]] = aie.tile(13, 0) -// CHECK: %[[VAL_119:.*]] = aie.tile(13, 1) -// CHECK: %[[VAL_120:.*]] = aie.tile(13, 2) -// CHECK: %[[VAL_121:.*]] = aie.tile(13, 3) -// CHECK: %[[VAL_122:.*]] = aie.tile(13, 4) -// CHECK: %[[VAL_123:.*]] = aie.tile(13, 5) -// CHECK: %[[VAL_124:.*]] = aie.tile(13, 6) -// CHECK: %[[VAL_125:.*]] = aie.tile(13, 7) -// CHECK: %[[VAL_126:.*]] = aie.tile(13, 8) -// CHECK: %[[VAL_127:.*]] = aie.tile(14, 1) -// CHECK: %[[VAL_128:.*]] = aie.tile(14, 2) -// CHECK: %[[VAL_129:.*]] = aie.tile(14, 3) -// CHECK: %[[VAL_130:.*]] = aie.tile(14, 4) -// CHECK: %[[VAL_131:.*]] = aie.tile(14, 5) -// CHECK: %[[VAL_132:.*]] = aie.tile(14, 6) -// CHECK: %[[VAL_133:.*]] = aie.tile(14, 7) -// CHECK: %[[VAL_134:.*]] = aie.tile(14, 8) -// CHECK: %[[VAL_135:.*]] = aie.switchbox(%[[VAL_14]]) { -// CHECK: } -// CHECK: %[[VAL_136:.*]] = aie.switchbox(%[[VAL_15]]) { -// CHECK: } -// CHECK: %[[VAL_137:.*]] = aie.switchbox(%[[VAL_16]]) { -// CHECK: } -// CHECK: %[[VAL_138:.*]] = aie.switchbox(%[[VAL_17]]) { -// CHECK: } -// CHECK: %[[VAL_139:.*]] = aie.switchbox(%[[VAL_22]]) { -// CHECK: } -// CHECK: %[[VAL_140:.*]] = aie.switchbox(%[[VAL_23]]) { -// CHECK: } -// CHECK: %[[VAL_141:.*]] = aie.switchbox(%[[VAL_24]]) { -// CHECK: } -// CHECK: %[[VAL_142:.*]] = aie.switchbox(%[[VAL_25]]) { -// CHECK: } -// CHECK: %[[VAL_143:.*]] = aie.switchbox(%[[VAL_30]]) { +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) +// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) +// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) +// CHECK: %[[TILE_9_0:.*]] = aie.tile(9, 0) +// CHECK: %[[TILE_10_0:.*]] = aie.tile(10, 0) +// CHECK: %[[TILE_11_0:.*]] = aie.tile(11, 0) +// CHECK: %[[TILE_18_0:.*]] = aie.tile(18, 0) +// CHECK: %[[TILE_19_0:.*]] = aie.tile(19, 0) +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_0_4:.*]] = aie.tile(0, 4) +// CHECK: %[[TILE_0_5:.*]] = aie.tile(0, 5) +// CHECK: %[[TILE_0_6:.*]] = aie.tile(0, 6) +// CHECK: %[[TILE_0_7:.*]] = aie.tile(0, 7) +// CHECK: %[[TILE_0_8:.*]] = aie.tile(0, 8) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_1_4:.*]] = aie.tile(1, 4) +// CHECK: %[[TILE_1_5:.*]] = aie.tile(1, 5) +// CHECK: %[[TILE_1_6:.*]] = aie.tile(1, 6) +// CHECK: %[[TILE_1_7:.*]] = aie.tile(1, 7) +// CHECK: %[[TILE_1_8:.*]] = aie.tile(1, 8) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_2_4:.*]] = aie.tile(2, 4) +// CHECK: %[[TILE_2_5:.*]] = aie.tile(2, 5) +// CHECK: %[[TILE_2_6:.*]] = aie.tile(2, 6) +// CHECK: %[[TILE_2_7:.*]] = aie.tile(2, 7) +// CHECK: %[[TILE_2_8:.*]] = aie.tile(2, 8) +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[TILE_3_4:.*]] = aie.tile(3, 4) +// CHECK: %[[TILE_3_5:.*]] = aie.tile(3, 5) +// CHECK: %[[TILE_3_6:.*]] = aie.tile(3, 6) +// CHECK: %[[TILE_3_7:.*]] = aie.tile(3, 7) +// CHECK: %[[TILE_3_8:.*]] = aie.tile(3, 8) +// CHECK: %[[TILE_4_1:.*]] = aie.tile(4, 1) +// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) +// CHECK: %[[TILE_4_3:.*]] = aie.tile(4, 3) +// CHECK: %[[TILE_4_4:.*]] = aie.tile(4, 4) +// CHECK: %[[TILE_4_5:.*]] = aie.tile(4, 5) +// CHECK: %[[TILE_4_6:.*]] = aie.tile(4, 6) +// CHECK: %[[TILE_4_7:.*]] = aie.tile(4, 7) +// CHECK: %[[TILE_4_8:.*]] = aie.tile(4, 8) +// CHECK: %[[TILE_5_1:.*]] = aie.tile(5, 1) +// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) +// CHECK: %[[TILE_5_3:.*]] = aie.tile(5, 3) +// CHECK: %[[TILE_5_4:.*]] = aie.tile(5, 4) +// CHECK: %[[TILE_5_5:.*]] = aie.tile(5, 5) +// CHECK: %[[TILE_5_6:.*]] = aie.tile(5, 6) +// CHECK: %[[TILE_5_7:.*]] = aie.tile(5, 7) +// CHECK: %[[TILE_5_8:.*]] = aie.tile(5, 8) +// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) +// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) +// CHECK: %[[TILE_6_3:.*]] = aie.tile(6, 3) +// CHECK: %[[TILE_6_4:.*]] = aie.tile(6, 4) +// CHECK: %[[TILE_6_5:.*]] = aie.tile(6, 5) +// CHECK: %[[TILE_6_6:.*]] = aie.tile(6, 6) +// CHECK: %[[TILE_6_7:.*]] = aie.tile(6, 7) +// CHECK: %[[TILE_6_8:.*]] = aie.tile(6, 8) +// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) +// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) +// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) +// CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) +// CHECK: %[[TILE_7_5:.*]] = aie.tile(7, 5) +// CHECK: %[[TILE_7_6:.*]] = aie.tile(7, 6) +// CHECK: %[[TILE_7_7:.*]] = aie.tile(7, 7) +// CHECK: %[[TILE_7_8:.*]] = aie.tile(7, 8) +// CHECK: %[[TILE_8_1:.*]] = aie.tile(8, 1) +// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) +// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) +// CHECK: %[[TILE_8_4:.*]] = aie.tile(8, 4) +// CHECK: %[[TILE_8_5:.*]] = aie.tile(8, 5) +// CHECK: %[[TILE_8_6:.*]] = aie.tile(8, 6) +// CHECK: %[[TILE_8_7:.*]] = aie.tile(8, 7) +// CHECK: %[[TILE_8_8:.*]] = aie.tile(8, 8) +// CHECK: %[[TILE_9_1:.*]] = aie.tile(9, 1) +// CHECK: %[[TILE_9_2:.*]] = aie.tile(9, 2) +// CHECK: %[[TILE_9_3:.*]] = aie.tile(9, 3) +// CHECK: %[[TILE_9_4:.*]] = aie.tile(9, 4) +// CHECK: %[[TILE_9_5:.*]] = aie.tile(9, 5) +// CHECK: %[[TILE_9_6:.*]] = aie.tile(9, 6) +// CHECK: %[[TILE_9_7:.*]] = aie.tile(9, 7) +// CHECK: %[[TILE_9_8:.*]] = aie.tile(9, 8) +// CHECK: %[[TILE_10_1:.*]] = aie.tile(10, 1) +// CHECK: %[[TILE_10_2:.*]] = aie.tile(10, 2) +// CHECK: %[[TILE_10_3:.*]] = aie.tile(10, 3) +// CHECK: %[[TILE_10_4:.*]] = aie.tile(10, 4) +// CHECK: %[[TILE_10_5:.*]] = aie.tile(10, 5) +// CHECK: %[[TILE_10_6:.*]] = aie.tile(10, 6) +// CHECK: %[[TILE_10_7:.*]] = aie.tile(10, 7) +// CHECK: %[[TILE_10_8:.*]] = aie.tile(10, 8) +// CHECK: %[[TILE_11_1:.*]] = aie.tile(11, 1) +// CHECK: %[[TILE_11_2:.*]] = aie.tile(11, 2) +// CHECK: %[[TILE_11_3:.*]] = aie.tile(11, 3) +// CHECK: %[[TILE_11_4:.*]] = aie.tile(11, 4) +// CHECK: %[[TILE_11_5:.*]] = aie.tile(11, 5) +// CHECK: %[[TILE_11_6:.*]] = aie.tile(11, 6) +// CHECK: %[[TILE_11_7:.*]] = aie.tile(11, 7) +// CHECK: %[[TILE_11_8:.*]] = aie.tile(11, 8) +// CHECK: %[[TILE_12_1:.*]] = aie.tile(12, 1) +// CHECK: %[[TILE_12_2:.*]] = aie.tile(12, 2) +// CHECK: %[[TILE_12_3:.*]] = aie.tile(12, 3) +// CHECK: %[[TILE_12_4:.*]] = aie.tile(12, 4) +// CHECK: %[[TILE_12_5:.*]] = aie.tile(12, 5) +// CHECK: %[[TILE_12_6:.*]] = aie.tile(12, 6) +// CHECK: %[[TILE_12_7:.*]] = aie.tile(12, 7) +// CHECK: %[[TILE_12_8:.*]] = aie.tile(12, 8) +// CHECK: %[[TILE_13_0:.*]] = aie.tile(13, 0) +// CHECK: %[[TILE_13_1:.*]] = aie.tile(13, 1) +// CHECK: %[[TILE_13_2:.*]] = aie.tile(13, 2) +// CHECK: %[[TILE_13_3:.*]] = aie.tile(13, 3) +// CHECK: %[[TILE_13_4:.*]] = aie.tile(13, 4) +// CHECK: %[[TILE_13_5:.*]] = aie.tile(13, 5) +// CHECK: %[[TILE_13_6:.*]] = aie.tile(13, 6) +// CHECK: %[[TILE_13_7:.*]] = aie.tile(13, 7) +// CHECK: %[[TILE_13_8:.*]] = aie.tile(13, 8) +// CHECK: %[[TILE_14_1:.*]] = aie.tile(14, 1) +// CHECK: %[[TILE_14_2:.*]] = aie.tile(14, 2) +// CHECK: %[[TILE_14_3:.*]] = aie.tile(14, 3) +// CHECK: %[[TILE_14_4:.*]] = aie.tile(14, 4) +// CHECK: %[[TILE_14_5:.*]] = aie.tile(14, 5) +// CHECK: %[[TILE_14_6:.*]] = aie.tile(14, 6) +// CHECK: %[[TILE_14_7:.*]] = aie.tile(14, 7) +// CHECK: %[[TILE_14_8:.*]] = aie.tile(14, 8) +// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { +// CHECK: } +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { +// CHECK: } +// CHECK: %[[SWITCHBOX_0_3:.*]] = aie.switchbox(%[[TILE_0_3]]) { +// CHECK: } +// CHECK: %[[SWITCHBOX_0_4:.*]] = aie.switchbox(%[[TILE_0_4]]) { +// CHECK: } +// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { +// CHECK: } +// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { +// CHECK: } +// CHECK: %[[SWITCHBOX_1_3:.*]] = aie.switchbox(%[[TILE_1_3]]) { +// CHECK: } +// CHECK: %[[SWITCHBOX_1_4:.*]] = aie.switchbox(%[[TILE_1_4]]) { +// CHECK: } +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_144:.*]] = aie.switchbox(%[[VAL_31]]) { +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: } -// CHECK: %[[VAL_145:.*]] = aie.switchbox(%[[VAL_32]]) { +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: } -// CHECK: %[[VAL_146:.*]] = aie.switchbox(%[[VAL_33]]) { +// CHECK: %[[SWITCHBOX_2_4:.*]] = aie.switchbox(%[[TILE_2_4]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_147:.*]] = aie.switchbox(%[[VAL_34]]) { +// CHECK: %[[SWITCHBOX_2_5:.*]] = aie.switchbox(%[[TILE_2_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_148:.*]] = aie.switchbox(%[[VAL_38]]) { +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_149:.*]] = aie.switchbox(%[[VAL_39]]) { +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_150:.*]] = aie.switchbox(%[[VAL_40]]) { +// CHECK: %[[SWITCHBOX_3_3:.*]] = aie.switchbox(%[[TILE_3_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_151:.*]] = aie.switchbox(%[[VAL_41]]) { +// CHECK: %[[SWITCHBOX_3_4:.*]] = aie.switchbox(%[[TILE_3_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_152:.*]] = aie.switchbox(%[[VAL_42]]) { +// CHECK: %[[SWITCHBOX_3_5:.*]] = aie.switchbox(%[[TILE_3_5]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_153:.*]] = aie.switchbox(%[[VAL_46]]) { +// CHECK: %[[SWITCHBOX_4_1:.*]] = aie.switchbox(%[[TILE_4_1]]) { // CHECK: } -// CHECK: %[[VAL_154:.*]] = aie.switchbox(%[[VAL_47]]) { +// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_155:.*]] = aie.switchbox(%[[VAL_48]]) { +// CHECK: %[[SWITCHBOX_4_3:.*]] = aie.switchbox(%[[TILE_4_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_156:.*]] = aie.switchbox(%[[VAL_49]]) { +// CHECK: %[[SWITCHBOX_4_4:.*]] = aie.switchbox(%[[TILE_4_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_157:.*]] = aie.switchbox(%[[VAL_54]]) { +// CHECK: %[[SWITCHBOX_5_1:.*]] = aie.switchbox(%[[TILE_5_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_158:.*]] = aie.switchbox(%[[VAL_55]]) { +// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_159:.*]] = aie.switchbox(%[[VAL_56]]) { +// CHECK: %[[SWITCHBOX_5_3:.*]] = aie.switchbox(%[[TILE_5_3]]) { // CHECK: } -// CHECK: %[[VAL_160:.*]] = aie.switchbox(%[[VAL_57]]) { +// CHECK: %[[SWITCHBOX_5_4:.*]] = aie.switchbox(%[[TILE_5_4]]) { // CHECK: } -// CHECK: %[[VAL_161:.*]] = aie.switchbox(%[[VAL_58]]) { +// CHECK: %[[SWITCHBOX_5_5:.*]] = aie.switchbox(%[[TILE_5_5]]) { // CHECK: } -// CHECK: %[[VAL_162:.*]] = aie.switchbox(%[[VAL_59]]) { +// CHECK: %[[SWITCHBOX_5_6:.*]] = aie.switchbox(%[[TILE_5_6]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_163:.*]] = aie.switchbox(%[[VAL_62]]) { +// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { // CHECK: } -// CHECK: %[[VAL_164:.*]] = aie.switchbox(%[[VAL_63]]) { +// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { // CHECK: } -// CHECK: %[[VAL_165:.*]] = aie.switchbox(%[[VAL_64]]) { +// CHECK: %[[SWITCHBOX_6_3:.*]] = aie.switchbox(%[[TILE_6_3]]) { // CHECK: } -// CHECK: %[[VAL_166:.*]] = aie.switchbox(%[[VAL_65]]) { +// CHECK: %[[SWITCHBOX_6_4:.*]] = aie.switchbox(%[[TILE_6_4]]) { // CHECK: } -// CHECK: %[[VAL_167:.*]] = aie.switchbox(%[[VAL_66]]) { +// CHECK: %[[SWITCHBOX_6_5:.*]] = aie.switchbox(%[[TILE_6_5]]) { // CHECK: } -// CHECK: %[[VAL_168:.*]] = aie.switchbox(%[[VAL_67]]) { +// CHECK: %[[SWITCHBOX_6_6:.*]] = aie.switchbox(%[[TILE_6_6]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_169:.*]] = aie.switchbox(%[[VAL_70]]) { +// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { // CHECK: } -// CHECK: %[[VAL_170:.*]] = aie.switchbox(%[[VAL_71]]) { +// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { // CHECK: } -// CHECK: %[[VAL_171:.*]] = aie.switchbox(%[[VAL_72]]) { +// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_172:.*]] = aie.switchbox(%[[VAL_73]]) { +// CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_173:.*]] = aie.switchbox(%[[VAL_74]]) { +// CHECK: %[[SWITCHBOX_7_5:.*]] = aie.switchbox(%[[TILE_7_5]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_174:.*]] = aie.switchbox(%[[VAL_75]]) { +// CHECK: %[[SWITCHBOX_7_6:.*]] = aie.switchbox(%[[TILE_7_6]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_175:.*]] = aie.switchbox(%[[VAL_78]]) { +// CHECK: %[[SWITCHBOX_8_1:.*]] = aie.switchbox(%[[TILE_8_1]]) { // CHECK: } -// CHECK: %[[VAL_176:.*]] = aie.switchbox(%[[VAL_79]]) { +// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { // CHECK: } -// CHECK: %[[VAL_177:.*]] = aie.switchbox(%[[VAL_80]]) { +// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_178:.*]] = aie.switchbox(%[[VAL_81]]) { +// CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { // CHECK: } -// CHECK: %[[VAL_179:.*]] = aie.switchbox(%[[VAL_86]]) { +// CHECK: %[[SWITCHBOX_9_1:.*]] = aie.switchbox(%[[TILE_9_1]]) { // CHECK: } -// CHECK: %[[VAL_180:.*]] = aie.switchbox(%[[VAL_87]]) { +// CHECK: %[[SWITCHBOX_9_2:.*]] = aie.switchbox(%[[TILE_9_2]]) { // CHECK: } -// CHECK: %[[VAL_181:.*]] = aie.switchbox(%[[VAL_88]]) { +// CHECK: %[[SWITCHBOX_9_3:.*]] = aie.switchbox(%[[TILE_9_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_182:.*]] = aie.switchbox(%[[VAL_89]]) { +// CHECK: %[[SWITCHBOX_9_4:.*]] = aie.switchbox(%[[TILE_9_4]]) { // CHECK: } -// CHECK: %[[VAL_183:.*]] = aie.switchbox(%[[VAL_94]]) { +// CHECK: %[[SWITCHBOX_10_1:.*]] = aie.switchbox(%[[TILE_10_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_184:.*]] = aie.switchbox(%[[VAL_95]]) { +// CHECK: %[[SWITCHBOX_10_2:.*]] = aie.switchbox(%[[TILE_10_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_185:.*]] = aie.switchbox(%[[VAL_96]]) { +// CHECK: %[[SWITCHBOX_10_3:.*]] = aie.switchbox(%[[TILE_10_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_186:.*]] = aie.switchbox(%[[VAL_97]]) { +// CHECK: %[[SWITCHBOX_10_4:.*]] = aie.switchbox(%[[TILE_10_4]]) { // CHECK: } -// CHECK: %[[VAL_187:.*]] = aie.switchbox(%[[VAL_102]]) { +// CHECK: %[[SWITCHBOX_11_1:.*]] = aie.switchbox(%[[TILE_11_1]]) { // CHECK: } -// CHECK: %[[VAL_188:.*]] = aie.switchbox(%[[VAL_103]]) { +// CHECK: %[[SWITCHBOX_11_2:.*]] = aie.switchbox(%[[TILE_11_2]]) { // CHECK: } -// CHECK: %[[VAL_189:.*]] = aie.switchbox(%[[VAL_104]]) { +// CHECK: %[[SWITCHBOX_11_3:.*]] = aie.switchbox(%[[TILE_11_3]]) { // CHECK: } -// CHECK: %[[VAL_190:.*]] = aie.switchbox(%[[VAL_105]]) { +// CHECK: %[[SWITCHBOX_11_4:.*]] = aie.switchbox(%[[TILE_11_4]]) { // CHECK: } -// CHECK: %[[VAL_191:.*]] = aie.switchbox(%[[VAL_110]]) { +// CHECK: %[[SWITCHBOX_12_1:.*]] = aie.switchbox(%[[TILE_12_1]]) { // CHECK: } -// CHECK: %[[VAL_192:.*]] = aie.switchbox(%[[VAL_111]]) { +// CHECK: %[[SWITCHBOX_12_2:.*]] = aie.switchbox(%[[TILE_12_2]]) { // CHECK: } -// CHECK: %[[VAL_193:.*]] = aie.switchbox(%[[VAL_112]]) { +// CHECK: %[[SWITCHBOX_12_3:.*]] = aie.switchbox(%[[TILE_12_3]]) { // CHECK: } -// CHECK: %[[VAL_194:.*]] = aie.switchbox(%[[VAL_113]]) { +// CHECK: %[[SWITCHBOX_12_4:.*]] = aie.switchbox(%[[TILE_12_4]]) { // CHECK: } -// CHECK: %[[VAL_195:.*]] = aie.switchbox(%[[VAL_114]]) { +// CHECK: %[[SWITCHBOX_12_5:.*]] = aie.switchbox(%[[TILE_12_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_196:.*]] = aie.switchbox(%[[VAL_119]]) { +// CHECK: %[[SWITCHBOX_13_1:.*]] = aie.switchbox(%[[TILE_13_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_197:.*]] = aie.switchbox(%[[VAL_120]]) { +// CHECK: %[[SWITCHBOX_13_2:.*]] = aie.switchbox(%[[TILE_13_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_198:.*]] = aie.switchbox(%[[VAL_121]]) { +// CHECK: %[[SWITCHBOX_13_3:.*]] = aie.switchbox(%[[TILE_13_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_199:.*]] = aie.switchbox(%[[VAL_122]]) { +// CHECK: %[[SWITCHBOX_13_4:.*]] = aie.switchbox(%[[TILE_13_4]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_200:.*]] = aie.switchbox(%[[VAL_123]]) { +// CHECK: %[[SWITCHBOX_13_5:.*]] = aie.switchbox(%[[TILE_13_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_201:.*]] = aie.switchbox(%[[VAL_3]]) { +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_202:.*]] = aie.shim_mux(%[[VAL_3]]) { +// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_203:.*]] = aie.switchbox(%[[VAL_50]]) { +// CHECK: %[[SWITCHBOX_4_5:.*]] = aie.switchbox(%[[TILE_4_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_204:.*]] = aie.switchbox(%[[VAL_5]]) { +// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_205:.*]] = aie.switchbox(%[[VAL_6]]) { +// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_206:.*]] = aie.shim_mux(%[[VAL_6]]) { +// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_207:.*]] = aie.switchbox(%[[VAL_10]]) { +// CHECK: %[[SWITCHBOX_10_0:.*]] = aie.switchbox(%[[TILE_10_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_208:.*]] = aie.shim_mux(%[[VAL_10]]) { +// CHECK: %[[SHIM_MUX_10_0:.*]] = aie.shim_mux(%[[TILE_10_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_209:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_210:.*]] = aie.shim_mux(%[[VAL_2]]) { +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_211:.*]] = aie.switchbox(%[[VAL_51]]) { +// CHECK: %[[SWITCHBOX_4_6:.*]] = aie.switchbox(%[[TILE_4_6]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_212:.*]] = aie.switchbox(%[[VAL_11]]) { +// CHECK: %[[SWITCHBOX_11_0:.*]] = aie.switchbox(%[[TILE_11_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_213:.*]] = aie.shim_mux(%[[VAL_11]]) { +// CHECK: %[[SHIM_MUX_11_0:.*]] = aie.shim_mux(%[[TILE_11_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_214:.*]] = aie.tile(12, 0) -// CHECK: %[[VAL_215:.*]] = aie.switchbox(%[[VAL_214]]) { +// CHECK: %[[TILE_12_0:.*]] = aie.tile(12, 0) +// CHECK: %[[SWITCHBOX_12_0:.*]] = aie.switchbox(%[[TILE_12_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_216:.*]] = aie.switchbox(%[[VAL_118]]) { +// CHECK: %[[SWITCHBOX_13_0:.*]] = aie.switchbox(%[[TILE_13_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_217:.*]] = aie.switchbox(%[[VAL_128]]) { +// CHECK: %[[SWITCHBOX_14_2:.*]] = aie.switchbox(%[[TILE_14_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_218:.*]] = aie.switchbox(%[[VAL_129]]) { +// CHECK: %[[SWITCHBOX_14_3:.*]] = aie.switchbox(%[[TILE_14_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_219:.*]] = aie.switchbox(%[[VAL_130]]) { +// CHECK: %[[SWITCHBOX_14_4:.*]] = aie.switchbox(%[[TILE_14_4]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_220:.*]] = aie.switchbox(%[[VAL_131]]) { +// CHECK: %[[SWITCHBOX_14_5:.*]] = aie.switchbox(%[[TILE_14_5]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_221:.*]] = aie.tile(15, 2) -// CHECK: %[[VAL_222:.*]] = aie.switchbox(%[[VAL_221]]) { +// CHECK: %[[TILE_15_2:.*]] = aie.tile(15, 2) +// CHECK: %[[SWITCHBOX_15_2:.*]] = aie.switchbox(%[[TILE_15_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_223:.*]] = aie.tile(16, 2) -// CHECK: %[[VAL_224:.*]] = aie.switchbox(%[[VAL_223]]) { +// CHECK: %[[TILE_16_2:.*]] = aie.tile(16, 2) +// CHECK: %[[SWITCHBOX_16_2:.*]] = aie.switchbox(%[[TILE_16_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_225:.*]] = aie.tile(17, 0) -// CHECK: %[[VAL_226:.*]] = aie.switchbox(%[[VAL_225]]) { +// CHECK: %[[TILE_17_0:.*]] = aie.tile(17, 0) +// CHECK: %[[SWITCHBOX_17_0:.*]] = aie.switchbox(%[[TILE_17_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_227:.*]] = aie.tile(17, 1) -// CHECK: %[[VAL_228:.*]] = aie.switchbox(%[[VAL_227]]) { +// CHECK: %[[TILE_17_1:.*]] = aie.tile(17, 1) +// CHECK: %[[SWITCHBOX_17_1:.*]] = aie.switchbox(%[[TILE_17_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_229:.*]] = aie.tile(17, 2) -// CHECK: %[[VAL_230:.*]] = aie.switchbox(%[[VAL_229]]) { +// CHECK: %[[TILE_17_2:.*]] = aie.tile(17, 2) +// CHECK: %[[SWITCHBOX_17_2:.*]] = aie.switchbox(%[[TILE_17_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_231:.*]] = aie.switchbox(%[[VAL_12]]) { +// CHECK: %[[SWITCHBOX_18_0:.*]] = aie.switchbox(%[[TILE_18_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_232:.*]] = aie.shim_mux(%[[VAL_12]]) { +// CHECK: %[[SHIM_MUX_18_0:.*]] = aie.shim_mux(%[[TILE_18_0]]) { // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_14]] : Core, %[[VAL_233:.*]] : Core) -// CHECK: aie.wire(%[[VAL_14]] : DMA, %[[VAL_233]] : DMA) -// CHECK: aie.wire(%[[VAL_15]] : Core, %[[VAL_234:.*]] : Core) -// CHECK: aie.wire(%[[VAL_15]] : DMA, %[[VAL_234]] : DMA) -// CHECK: aie.wire(%[[VAL_233]] : North, %[[VAL_234]] : South) -// CHECK: aie.wire(%[[VAL_16]] : Core, %[[VAL_235:.*]] : Core) -// CHECK: aie.wire(%[[VAL_16]] : DMA, %[[VAL_235]] : DMA) -// CHECK: aie.wire(%[[VAL_234]] : North, %[[VAL_235]] : South) -// CHECK: aie.wire(%[[VAL_17]] : Core, %[[VAL_236:.*]] : Core) -// CHECK: aie.wire(%[[VAL_17]] : DMA, %[[VAL_236]] : DMA) -// CHECK: aie.wire(%[[VAL_235]] : North, %[[VAL_236]] : South) -// CHECK: aie.wire(%[[VAL_233]] : East, %[[VAL_237:.*]] : West) -// CHECK: aie.wire(%[[VAL_22]] : Core, %[[VAL_237]] : Core) -// CHECK: aie.wire(%[[VAL_22]] : DMA, %[[VAL_237]] : DMA) -// CHECK: aie.wire(%[[VAL_234]] : East, %[[VAL_238:.*]] : West) -// CHECK: aie.wire(%[[VAL_23]] : Core, %[[VAL_238]] : Core) -// CHECK: aie.wire(%[[VAL_23]] : DMA, %[[VAL_238]] : DMA) -// CHECK: aie.wire(%[[VAL_237]] : North, %[[VAL_238]] : South) -// CHECK: aie.wire(%[[VAL_235]] : East, %[[VAL_239:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_239]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_239]] : DMA) -// CHECK: aie.wire(%[[VAL_238]] : North, %[[VAL_239]] : South) -// CHECK: aie.wire(%[[VAL_236]] : East, %[[VAL_240:.*]] : West) -// CHECK: aie.wire(%[[VAL_25]] : Core, %[[VAL_240]] : Core) -// CHECK: aie.wire(%[[VAL_25]] : DMA, %[[VAL_240]] : DMA) -// CHECK: aie.wire(%[[VAL_239]] : North, %[[VAL_240]] : South) -// CHECK: aie.wire(%[[VAL_241:.*]] : North, %[[VAL_242:.*]] : South) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_241]] : DMA) -// CHECK: aie.wire(%[[VAL_237]] : East, %[[VAL_243:.*]] : West) -// CHECK: aie.wire(%[[VAL_30]] : Core, %[[VAL_243]] : Core) -// CHECK: aie.wire(%[[VAL_30]] : DMA, %[[VAL_243]] : DMA) -// CHECK: aie.wire(%[[VAL_242]] : North, %[[VAL_243]] : South) -// CHECK: aie.wire(%[[VAL_238]] : East, %[[VAL_244:.*]] : West) -// CHECK: aie.wire(%[[VAL_31]] : Core, %[[VAL_244]] : Core) -// CHECK: aie.wire(%[[VAL_31]] : DMA, %[[VAL_244]] : DMA) -// CHECK: aie.wire(%[[VAL_243]] : North, %[[VAL_244]] : South) -// CHECK: aie.wire(%[[VAL_239]] : East, %[[VAL_245:.*]] : West) -// CHECK: aie.wire(%[[VAL_32]] : Core, %[[VAL_245]] : Core) -// CHECK: aie.wire(%[[VAL_32]] : DMA, %[[VAL_245]] : DMA) -// CHECK: aie.wire(%[[VAL_244]] : North, %[[VAL_245]] : South) -// CHECK: aie.wire(%[[VAL_240]] : East, %[[VAL_246:.*]] : West) -// CHECK: aie.wire(%[[VAL_33]] : Core, %[[VAL_246]] : Core) -// CHECK: aie.wire(%[[VAL_33]] : DMA, %[[VAL_246]] : DMA) -// CHECK: aie.wire(%[[VAL_245]] : North, %[[VAL_246]] : South) -// CHECK: aie.wire(%[[VAL_34]] : Core, %[[VAL_247:.*]] : Core) -// CHECK: aie.wire(%[[VAL_34]] : DMA, %[[VAL_247]] : DMA) -// CHECK: aie.wire(%[[VAL_246]] : North, %[[VAL_247]] : South) -// CHECK: aie.wire(%[[VAL_242]] : East, %[[VAL_248:.*]] : West) -// CHECK: aie.wire(%[[VAL_249:.*]] : North, %[[VAL_248]] : South) -// CHECK: aie.wire(%[[VAL_3]] : DMA, %[[VAL_249]] : DMA) -// CHECK: aie.wire(%[[VAL_243]] : East, %[[VAL_250:.*]] : West) -// CHECK: aie.wire(%[[VAL_38]] : Core, %[[VAL_250]] : Core) -// CHECK: aie.wire(%[[VAL_38]] : DMA, %[[VAL_250]] : DMA) -// CHECK: aie.wire(%[[VAL_248]] : North, %[[VAL_250]] : South) -// CHECK: aie.wire(%[[VAL_244]] : East, %[[VAL_251:.*]] : West) -// CHECK: aie.wire(%[[VAL_39]] : Core, %[[VAL_251]] : Core) -// CHECK: aie.wire(%[[VAL_39]] : DMA, %[[VAL_251]] : DMA) -// CHECK: aie.wire(%[[VAL_250]] : North, %[[VAL_251]] : South) -// CHECK: aie.wire(%[[VAL_245]] : East, %[[VAL_252:.*]] : West) -// CHECK: aie.wire(%[[VAL_40]] : Core, %[[VAL_252]] : Core) -// CHECK: aie.wire(%[[VAL_40]] : DMA, %[[VAL_252]] : DMA) -// CHECK: aie.wire(%[[VAL_251]] : North, %[[VAL_252]] : South) -// CHECK: aie.wire(%[[VAL_246]] : East, %[[VAL_253:.*]] : West) -// CHECK: aie.wire(%[[VAL_41]] : Core, %[[VAL_253]] : Core) -// CHECK: aie.wire(%[[VAL_41]] : DMA, %[[VAL_253]] : DMA) -// CHECK: aie.wire(%[[VAL_252]] : North, %[[VAL_253]] : South) -// CHECK: aie.wire(%[[VAL_247]] : East, %[[VAL_254:.*]] : West) -// CHECK: aie.wire(%[[VAL_42]] : Core, %[[VAL_254]] : Core) -// CHECK: aie.wire(%[[VAL_42]] : DMA, %[[VAL_254]] : DMA) -// CHECK: aie.wire(%[[VAL_253]] : North, %[[VAL_254]] : South) -// CHECK: aie.wire(%[[VAL_250]] : East, %[[VAL_255:.*]] : West) -// CHECK: aie.wire(%[[VAL_46]] : Core, %[[VAL_255]] : Core) -// CHECK: aie.wire(%[[VAL_46]] : DMA, %[[VAL_255]] : DMA) -// CHECK: aie.wire(%[[VAL_251]] : East, %[[VAL_256:.*]] : West) -// CHECK: aie.wire(%[[VAL_47]] : Core, %[[VAL_256]] : Core) -// CHECK: aie.wire(%[[VAL_47]] : DMA, %[[VAL_256]] : DMA) -// CHECK: aie.wire(%[[VAL_255]] : North, %[[VAL_256]] : South) -// CHECK: aie.wire(%[[VAL_252]] : East, %[[VAL_257:.*]] : West) -// CHECK: aie.wire(%[[VAL_48]] : Core, %[[VAL_257]] : Core) -// CHECK: aie.wire(%[[VAL_48]] : DMA, %[[VAL_257]] : DMA) -// CHECK: aie.wire(%[[VAL_256]] : North, %[[VAL_257]] : South) -// CHECK: aie.wire(%[[VAL_253]] : East, %[[VAL_258:.*]] : West) -// CHECK: aie.wire(%[[VAL_49]] : Core, %[[VAL_258]] : Core) -// CHECK: aie.wire(%[[VAL_49]] : DMA, %[[VAL_258]] : DMA) -// CHECK: aie.wire(%[[VAL_257]] : North, %[[VAL_258]] : South) -// CHECK: aie.wire(%[[VAL_254]] : East, %[[VAL_259:.*]] : West) -// CHECK: aie.wire(%[[VAL_50]] : Core, %[[VAL_259]] : Core) -// CHECK: aie.wire(%[[VAL_50]] : DMA, %[[VAL_259]] : DMA) -// CHECK: aie.wire(%[[VAL_258]] : North, %[[VAL_259]] : South) -// CHECK: aie.wire(%[[VAL_51]] : Core, %[[VAL_260:.*]] : Core) -// CHECK: aie.wire(%[[VAL_51]] : DMA, %[[VAL_260]] : DMA) -// CHECK: aie.wire(%[[VAL_259]] : North, %[[VAL_260]] : South) -// CHECK: aie.wire(%[[VAL_255]] : East, %[[VAL_261:.*]] : West) -// CHECK: aie.wire(%[[VAL_54]] : Core, %[[VAL_261]] : Core) -// CHECK: aie.wire(%[[VAL_54]] : DMA, %[[VAL_261]] : DMA) -// CHECK: aie.wire(%[[VAL_262:.*]] : North, %[[VAL_261]] : South) -// CHECK: aie.wire(%[[VAL_256]] : East, %[[VAL_263:.*]] : West) -// CHECK: aie.wire(%[[VAL_55]] : Core, %[[VAL_263]] : Core) -// CHECK: aie.wire(%[[VAL_55]] : DMA, %[[VAL_263]] : DMA) -// CHECK: aie.wire(%[[VAL_261]] : North, %[[VAL_263]] : South) -// CHECK: aie.wire(%[[VAL_257]] : East, %[[VAL_264:.*]] : West) -// CHECK: aie.wire(%[[VAL_56]] : Core, %[[VAL_264]] : Core) -// CHECK: aie.wire(%[[VAL_56]] : DMA, %[[VAL_264]] : DMA) -// CHECK: aie.wire(%[[VAL_263]] : North, %[[VAL_264]] : South) -// CHECK: aie.wire(%[[VAL_258]] : East, %[[VAL_265:.*]] : West) -// CHECK: aie.wire(%[[VAL_57]] : Core, %[[VAL_265]] : Core) -// CHECK: aie.wire(%[[VAL_57]] : DMA, %[[VAL_265]] : DMA) -// CHECK: aie.wire(%[[VAL_264]] : North, %[[VAL_265]] : South) -// CHECK: aie.wire(%[[VAL_259]] : East, %[[VAL_266:.*]] : West) -// CHECK: aie.wire(%[[VAL_58]] : Core, %[[VAL_266]] : Core) -// CHECK: aie.wire(%[[VAL_58]] : DMA, %[[VAL_266]] : DMA) -// CHECK: aie.wire(%[[VAL_265]] : North, %[[VAL_266]] : South) -// CHECK: aie.wire(%[[VAL_260]] : East, %[[VAL_267:.*]] : West) -// CHECK: aie.wire(%[[VAL_59]] : Core, %[[VAL_267]] : Core) -// CHECK: aie.wire(%[[VAL_59]] : DMA, %[[VAL_267]] : DMA) -// CHECK: aie.wire(%[[VAL_266]] : North, %[[VAL_267]] : South) -// CHECK: aie.wire(%[[VAL_262]] : East, %[[VAL_268:.*]] : West) -// CHECK: aie.wire(%[[VAL_269:.*]] : North, %[[VAL_268]] : South) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_269]] : DMA) -// CHECK: aie.wire(%[[VAL_261]] : East, %[[VAL_270:.*]] : West) -// CHECK: aie.wire(%[[VAL_62]] : Core, %[[VAL_270]] : Core) -// CHECK: aie.wire(%[[VAL_62]] : DMA, %[[VAL_270]] : DMA) -// CHECK: aie.wire(%[[VAL_268]] : North, %[[VAL_270]] : South) -// CHECK: aie.wire(%[[VAL_263]] : East, %[[VAL_271:.*]] : West) -// CHECK: aie.wire(%[[VAL_63]] : Core, %[[VAL_271]] : Core) -// CHECK: aie.wire(%[[VAL_63]] : DMA, %[[VAL_271]] : DMA) -// CHECK: aie.wire(%[[VAL_270]] : North, %[[VAL_271]] : South) -// CHECK: aie.wire(%[[VAL_264]] : East, %[[VAL_272:.*]] : West) -// CHECK: aie.wire(%[[VAL_64]] : Core, %[[VAL_272]] : Core) -// CHECK: aie.wire(%[[VAL_64]] : DMA, %[[VAL_272]] : DMA) -// CHECK: aie.wire(%[[VAL_271]] : North, %[[VAL_272]] : South) -// CHECK: aie.wire(%[[VAL_265]] : East, %[[VAL_273:.*]] : West) -// CHECK: aie.wire(%[[VAL_65]] : Core, %[[VAL_273]] : Core) -// CHECK: aie.wire(%[[VAL_65]] : DMA, %[[VAL_273]] : DMA) -// CHECK: aie.wire(%[[VAL_272]] : North, %[[VAL_273]] : South) -// CHECK: aie.wire(%[[VAL_266]] : East, %[[VAL_274:.*]] : West) -// CHECK: aie.wire(%[[VAL_66]] : Core, %[[VAL_274]] : Core) -// CHECK: aie.wire(%[[VAL_66]] : DMA, %[[VAL_274]] : DMA) -// CHECK: aie.wire(%[[VAL_273]] : North, %[[VAL_274]] : South) -// CHECK: aie.wire(%[[VAL_267]] : East, %[[VAL_275:.*]] : West) -// CHECK: aie.wire(%[[VAL_67]] : Core, %[[VAL_275]] : Core) -// CHECK: aie.wire(%[[VAL_67]] : DMA, %[[VAL_275]] : DMA) -// CHECK: aie.wire(%[[VAL_274]] : North, %[[VAL_275]] : South) -// CHECK: aie.wire(%[[VAL_270]] : East, %[[VAL_276:.*]] : West) -// CHECK: aie.wire(%[[VAL_70]] : Core, %[[VAL_276]] : Core) -// CHECK: aie.wire(%[[VAL_70]] : DMA, %[[VAL_276]] : DMA) -// CHECK: aie.wire(%[[VAL_271]] : East, %[[VAL_277:.*]] : West) -// CHECK: aie.wire(%[[VAL_71]] : Core, %[[VAL_277]] : Core) -// CHECK: aie.wire(%[[VAL_71]] : DMA, %[[VAL_277]] : DMA) -// CHECK: aie.wire(%[[VAL_276]] : North, %[[VAL_277]] : South) -// CHECK: aie.wire(%[[VAL_272]] : East, %[[VAL_278:.*]] : West) -// CHECK: aie.wire(%[[VAL_72]] : Core, %[[VAL_278]] : Core) -// CHECK: aie.wire(%[[VAL_72]] : DMA, %[[VAL_278]] : DMA) -// CHECK: aie.wire(%[[VAL_277]] : North, %[[VAL_278]] : South) -// CHECK: aie.wire(%[[VAL_273]] : East, %[[VAL_279:.*]] : West) -// CHECK: aie.wire(%[[VAL_73]] : Core, %[[VAL_279]] : Core) -// CHECK: aie.wire(%[[VAL_73]] : DMA, %[[VAL_279]] : DMA) -// CHECK: aie.wire(%[[VAL_278]] : North, %[[VAL_279]] : South) -// CHECK: aie.wire(%[[VAL_274]] : East, %[[VAL_280:.*]] : West) -// CHECK: aie.wire(%[[VAL_74]] : Core, %[[VAL_280]] : Core) -// CHECK: aie.wire(%[[VAL_74]] : DMA, %[[VAL_280]] : DMA) -// CHECK: aie.wire(%[[VAL_279]] : North, %[[VAL_280]] : South) -// CHECK: aie.wire(%[[VAL_275]] : East, %[[VAL_281:.*]] : West) -// CHECK: aie.wire(%[[VAL_75]] : Core, %[[VAL_281]] : Core) -// CHECK: aie.wire(%[[VAL_75]] : DMA, %[[VAL_281]] : DMA) -// CHECK: aie.wire(%[[VAL_280]] : North, %[[VAL_281]] : South) -// CHECK: aie.wire(%[[VAL_276]] : East, %[[VAL_282:.*]] : West) -// CHECK: aie.wire(%[[VAL_78]] : Core, %[[VAL_282]] : Core) -// CHECK: aie.wire(%[[VAL_78]] : DMA, %[[VAL_282]] : DMA) -// CHECK: aie.wire(%[[VAL_277]] : East, %[[VAL_283:.*]] : West) -// CHECK: aie.wire(%[[VAL_79]] : Core, %[[VAL_283]] : Core) -// CHECK: aie.wire(%[[VAL_79]] : DMA, %[[VAL_283]] : DMA) -// CHECK: aie.wire(%[[VAL_282]] : North, %[[VAL_283]] : South) -// CHECK: aie.wire(%[[VAL_278]] : East, %[[VAL_284:.*]] : West) -// CHECK: aie.wire(%[[VAL_80]] : Core, %[[VAL_284]] : Core) -// CHECK: aie.wire(%[[VAL_80]] : DMA, %[[VAL_284]] : DMA) -// CHECK: aie.wire(%[[VAL_283]] : North, %[[VAL_284]] : South) -// CHECK: aie.wire(%[[VAL_279]] : East, %[[VAL_285:.*]] : West) -// CHECK: aie.wire(%[[VAL_81]] : Core, %[[VAL_285]] : Core) -// CHECK: aie.wire(%[[VAL_81]] : DMA, %[[VAL_285]] : DMA) -// CHECK: aie.wire(%[[VAL_284]] : North, %[[VAL_285]] : South) -// CHECK: aie.wire(%[[VAL_282]] : East, %[[VAL_286:.*]] : West) -// CHECK: aie.wire(%[[VAL_86]] : Core, %[[VAL_286]] : Core) -// CHECK: aie.wire(%[[VAL_86]] : DMA, %[[VAL_286]] : DMA) -// CHECK: aie.wire(%[[VAL_283]] : East, %[[VAL_287:.*]] : West) -// CHECK: aie.wire(%[[VAL_87]] : Core, %[[VAL_287]] : Core) -// CHECK: aie.wire(%[[VAL_87]] : DMA, %[[VAL_287]] : DMA) -// CHECK: aie.wire(%[[VAL_286]] : North, %[[VAL_287]] : South) -// CHECK: aie.wire(%[[VAL_284]] : East, %[[VAL_288:.*]] : West) -// CHECK: aie.wire(%[[VAL_88]] : Core, %[[VAL_288]] : Core) -// CHECK: aie.wire(%[[VAL_88]] : DMA, %[[VAL_288]] : DMA) -// CHECK: aie.wire(%[[VAL_287]] : North, %[[VAL_288]] : South) -// CHECK: aie.wire(%[[VAL_285]] : East, %[[VAL_289:.*]] : West) -// CHECK: aie.wire(%[[VAL_89]] : Core, %[[VAL_289]] : Core) -// CHECK: aie.wire(%[[VAL_89]] : DMA, %[[VAL_289]] : DMA) -// CHECK: aie.wire(%[[VAL_288]] : North, %[[VAL_289]] : South) -// CHECK: aie.wire(%[[VAL_290:.*]] : North, %[[VAL_291:.*]] : South) -// CHECK: aie.wire(%[[VAL_10]] : DMA, %[[VAL_290]] : DMA) -// CHECK: aie.wire(%[[VAL_286]] : East, %[[VAL_292:.*]] : West) -// CHECK: aie.wire(%[[VAL_94]] : Core, %[[VAL_292]] : Core) -// CHECK: aie.wire(%[[VAL_94]] : DMA, %[[VAL_292]] : DMA) -// CHECK: aie.wire(%[[VAL_291]] : North, %[[VAL_292]] : South) -// CHECK: aie.wire(%[[VAL_287]] : East, %[[VAL_293:.*]] : West) -// CHECK: aie.wire(%[[VAL_95]] : Core, %[[VAL_293]] : Core) -// CHECK: aie.wire(%[[VAL_95]] : DMA, %[[VAL_293]] : DMA) -// CHECK: aie.wire(%[[VAL_292]] : North, %[[VAL_293]] : South) -// CHECK: aie.wire(%[[VAL_288]] : East, %[[VAL_294:.*]] : West) -// CHECK: aie.wire(%[[VAL_96]] : Core, %[[VAL_294]] : Core) -// CHECK: aie.wire(%[[VAL_96]] : DMA, %[[VAL_294]] : DMA) -// CHECK: aie.wire(%[[VAL_293]] : North, %[[VAL_294]] : South) -// CHECK: aie.wire(%[[VAL_289]] : East, %[[VAL_295:.*]] : West) -// CHECK: aie.wire(%[[VAL_97]] : Core, %[[VAL_295]] : Core) -// CHECK: aie.wire(%[[VAL_97]] : DMA, %[[VAL_295]] : DMA) -// CHECK: aie.wire(%[[VAL_294]] : North, %[[VAL_295]] : South) -// CHECK: aie.wire(%[[VAL_291]] : East, %[[VAL_296:.*]] : West) -// CHECK: aie.wire(%[[VAL_297:.*]] : North, %[[VAL_296]] : South) -// CHECK: aie.wire(%[[VAL_11]] : DMA, %[[VAL_297]] : DMA) -// CHECK: aie.wire(%[[VAL_292]] : East, %[[VAL_298:.*]] : West) -// CHECK: aie.wire(%[[VAL_102]] : Core, %[[VAL_298]] : Core) -// CHECK: aie.wire(%[[VAL_102]] : DMA, %[[VAL_298]] : DMA) -// CHECK: aie.wire(%[[VAL_296]] : North, %[[VAL_298]] : South) -// CHECK: aie.wire(%[[VAL_293]] : East, %[[VAL_299:.*]] : West) -// CHECK: aie.wire(%[[VAL_103]] : Core, %[[VAL_299]] : Core) -// CHECK: aie.wire(%[[VAL_103]] : DMA, %[[VAL_299]] : DMA) -// CHECK: aie.wire(%[[VAL_298]] : North, %[[VAL_299]] : South) -// CHECK: aie.wire(%[[VAL_294]] : East, %[[VAL_300:.*]] : West) -// CHECK: aie.wire(%[[VAL_104]] : Core, %[[VAL_300]] : Core) -// CHECK: aie.wire(%[[VAL_104]] : DMA, %[[VAL_300]] : DMA) -// CHECK: aie.wire(%[[VAL_299]] : North, %[[VAL_300]] : South) -// CHECK: aie.wire(%[[VAL_295]] : East, %[[VAL_301:.*]] : West) -// CHECK: aie.wire(%[[VAL_105]] : Core, %[[VAL_301]] : Core) -// CHECK: aie.wire(%[[VAL_105]] : DMA, %[[VAL_301]] : DMA) -// CHECK: aie.wire(%[[VAL_300]] : North, %[[VAL_301]] : South) -// CHECK: aie.wire(%[[VAL_296]] : East, %[[VAL_302:.*]] : West) -// CHECK: aie.wire(%[[VAL_298]] : East, %[[VAL_303:.*]] : West) -// CHECK: aie.wire(%[[VAL_110]] : Core, %[[VAL_303]] : Core) -// CHECK: aie.wire(%[[VAL_110]] : DMA, %[[VAL_303]] : DMA) -// CHECK: aie.wire(%[[VAL_302]] : North, %[[VAL_303]] : South) -// CHECK: aie.wire(%[[VAL_299]] : East, %[[VAL_304:.*]] : West) -// CHECK: aie.wire(%[[VAL_111]] : Core, %[[VAL_304]] : Core) -// CHECK: aie.wire(%[[VAL_111]] : DMA, %[[VAL_304]] : DMA) -// CHECK: aie.wire(%[[VAL_303]] : North, %[[VAL_304]] : South) -// CHECK: aie.wire(%[[VAL_300]] : East, %[[VAL_305:.*]] : West) -// CHECK: aie.wire(%[[VAL_112]] : Core, %[[VAL_305]] : Core) -// CHECK: aie.wire(%[[VAL_112]] : DMA, %[[VAL_305]] : DMA) -// CHECK: aie.wire(%[[VAL_304]] : North, %[[VAL_305]] : South) -// CHECK: aie.wire(%[[VAL_301]] : East, %[[VAL_306:.*]] : West) -// CHECK: aie.wire(%[[VAL_113]] : Core, %[[VAL_306]] : Core) -// CHECK: aie.wire(%[[VAL_113]] : DMA, %[[VAL_306]] : DMA) -// CHECK: aie.wire(%[[VAL_305]] : North, %[[VAL_306]] : South) -// CHECK: aie.wire(%[[VAL_114]] : Core, %[[VAL_307:.*]] : Core) -// CHECK: aie.wire(%[[VAL_114]] : DMA, %[[VAL_307]] : DMA) -// CHECK: aie.wire(%[[VAL_306]] : North, %[[VAL_307]] : South) -// CHECK: aie.wire(%[[VAL_302]] : East, %[[VAL_308:.*]] : West) -// CHECK: aie.wire(%[[VAL_303]] : East, %[[VAL_309:.*]] : West) -// CHECK: aie.wire(%[[VAL_119]] : Core, %[[VAL_309]] : Core) -// CHECK: aie.wire(%[[VAL_119]] : DMA, %[[VAL_309]] : DMA) -// CHECK: aie.wire(%[[VAL_308]] : North, %[[VAL_309]] : South) -// CHECK: aie.wire(%[[VAL_304]] : East, %[[VAL_310:.*]] : West) -// CHECK: aie.wire(%[[VAL_120]] : Core, %[[VAL_310]] : Core) -// CHECK: aie.wire(%[[VAL_120]] : DMA, %[[VAL_310]] : DMA) -// CHECK: aie.wire(%[[VAL_309]] : North, %[[VAL_310]] : South) -// CHECK: aie.wire(%[[VAL_305]] : East, %[[VAL_311:.*]] : West) -// CHECK: aie.wire(%[[VAL_121]] : Core, %[[VAL_311]] : Core) -// CHECK: aie.wire(%[[VAL_121]] : DMA, %[[VAL_311]] : DMA) -// CHECK: aie.wire(%[[VAL_310]] : North, %[[VAL_311]] : South) -// CHECK: aie.wire(%[[VAL_306]] : East, %[[VAL_312:.*]] : West) -// CHECK: aie.wire(%[[VAL_122]] : Core, %[[VAL_312]] : Core) -// CHECK: aie.wire(%[[VAL_122]] : DMA, %[[VAL_312]] : DMA) -// CHECK: aie.wire(%[[VAL_311]] : North, %[[VAL_312]] : South) -// CHECK: aie.wire(%[[VAL_307]] : East, %[[VAL_313:.*]] : West) -// CHECK: aie.wire(%[[VAL_123]] : Core, %[[VAL_313]] : Core) -// CHECK: aie.wire(%[[VAL_123]] : DMA, %[[VAL_313]] : DMA) -// CHECK: aie.wire(%[[VAL_312]] : North, %[[VAL_313]] : South) -// CHECK: aie.wire(%[[VAL_310]] : East, %[[VAL_314:.*]] : West) -// CHECK: aie.wire(%[[VAL_128]] : Core, %[[VAL_314]] : Core) -// CHECK: aie.wire(%[[VAL_128]] : DMA, %[[VAL_314]] : DMA) -// CHECK: aie.wire(%[[VAL_311]] : East, %[[VAL_315:.*]] : West) -// CHECK: aie.wire(%[[VAL_129]] : Core, %[[VAL_315]] : Core) -// CHECK: aie.wire(%[[VAL_129]] : DMA, %[[VAL_315]] : DMA) -// CHECK: aie.wire(%[[VAL_314]] : North, %[[VAL_315]] : South) -// CHECK: aie.wire(%[[VAL_312]] : East, %[[VAL_316:.*]] : West) -// CHECK: aie.wire(%[[VAL_130]] : Core, %[[VAL_316]] : Core) -// CHECK: aie.wire(%[[VAL_130]] : DMA, %[[VAL_316]] : DMA) -// CHECK: aie.wire(%[[VAL_315]] : North, %[[VAL_316]] : South) -// CHECK: aie.wire(%[[VAL_313]] : East, %[[VAL_317:.*]] : West) -// CHECK: aie.wire(%[[VAL_131]] : Core, %[[VAL_317]] : Core) -// CHECK: aie.wire(%[[VAL_131]] : DMA, %[[VAL_317]] : DMA) -// CHECK: aie.wire(%[[VAL_316]] : North, %[[VAL_317]] : South) -// CHECK: aie.wire(%[[VAL_314]] : East, %[[VAL_318:.*]] : West) -// CHECK: aie.wire(%[[VAL_221]] : Core, %[[VAL_318]] : Core) -// CHECK: aie.wire(%[[VAL_221]] : DMA, %[[VAL_318]] : DMA) -// CHECK: aie.wire(%[[VAL_318]] : East, %[[VAL_319:.*]] : West) -// CHECK: aie.wire(%[[VAL_223]] : Core, %[[VAL_319]] : Core) -// CHECK: aie.wire(%[[VAL_223]] : DMA, %[[VAL_319]] : DMA) -// CHECK: aie.wire(%[[VAL_227]] : Core, %[[VAL_320:.*]] : Core) -// CHECK: aie.wire(%[[VAL_227]] : DMA, %[[VAL_320]] : DMA) -// CHECK: aie.wire(%[[VAL_321:.*]] : North, %[[VAL_320]] : South) -// CHECK: aie.wire(%[[VAL_319]] : East, %[[VAL_322:.*]] : West) -// CHECK: aie.wire(%[[VAL_229]] : Core, %[[VAL_322]] : Core) -// CHECK: aie.wire(%[[VAL_229]] : DMA, %[[VAL_322]] : DMA) -// CHECK: aie.wire(%[[VAL_320]] : North, %[[VAL_322]] : South) -// CHECK: aie.wire(%[[VAL_321]] : East, %[[VAL_323:.*]] : West) -// CHECK: aie.wire(%[[VAL_324:.*]] : North, %[[VAL_323]] : South) -// CHECK: aie.wire(%[[VAL_12]] : DMA, %[[VAL_324]] : DMA) +// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) +// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) +// CHECK: aie.wire(%[[TILE_0_3]] : Core, %[[SWITCHBOX_0_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_3]] : DMA, %[[SWITCHBOX_0_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : North, %[[SWITCHBOX_0_3]] : South) +// CHECK: aie.wire(%[[TILE_0_4]] : Core, %[[SWITCHBOX_0_4:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_4]] : DMA, %[[SWITCHBOX_0_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : North, %[[SWITCHBOX_0_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : East, %[[SWITCHBOX_1_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1]] : Core) +// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) +// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : North, %[[SWITCHBOX_1_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_3]] : East, %[[SWITCHBOX_1_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_3]] : Core, %[[SWITCHBOX_1_3]] : Core) +// CHECK: aie.wire(%[[TILE_1_3]] : DMA, %[[SWITCHBOX_1_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : North, %[[SWITCHBOX_1_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_4]] : East, %[[SWITCHBOX_1_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_4]] : Core, %[[SWITCHBOX_1_4]] : Core) +// CHECK: aie.wire(%[[TILE_1_4]] : DMA, %[[SWITCHBOX_1_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : North, %[[SWITCHBOX_1_4]] : South) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_2]] : East, %[[SWITCHBOX_2_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_3]] : East, %[[SWITCHBOX_2_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3]] : Core) +// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_1_4]] : East, %[[SWITCHBOX_2_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_4]] : Core, %[[SWITCHBOX_2_4]] : Core) +// CHECK: aie.wire(%[[TILE_2_4]] : DMA, %[[SWITCHBOX_2_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : North, %[[SWITCHBOX_2_4]] : South) +// CHECK: aie.wire(%[[TILE_2_5]] : Core, %[[SWITCHBOX_2_5:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_5]] : DMA, %[[SWITCHBOX_2_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_4]] : North, %[[SWITCHBOX_2_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) +// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_3]] : East, %[[SWITCHBOX_3_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_3]] : Core, %[[SWITCHBOX_3_3]] : Core) +// CHECK: aie.wire(%[[TILE_3_3]] : DMA, %[[SWITCHBOX_3_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : North, %[[SWITCHBOX_3_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_4]] : East, %[[SWITCHBOX_3_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_4]] : Core, %[[SWITCHBOX_3_4]] : Core) +// CHECK: aie.wire(%[[TILE_3_4]] : DMA, %[[SWITCHBOX_3_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : North, %[[SWITCHBOX_3_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_5]] : East, %[[SWITCHBOX_3_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_5]] : Core, %[[SWITCHBOX_3_5]] : Core) +// CHECK: aie.wire(%[[TILE_3_5]] : DMA, %[[SWITCHBOX_3_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_4]] : North, %[[SWITCHBOX_3_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : East, %[[SWITCHBOX_4_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_1]] : Core, %[[SWITCHBOX_4_1]] : Core) +// CHECK: aie.wire(%[[TILE_4_1]] : DMA, %[[SWITCHBOX_4_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) +// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : North, %[[SWITCHBOX_4_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_3]] : East, %[[SWITCHBOX_4_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_3]] : Core, %[[SWITCHBOX_4_3]] : Core) +// CHECK: aie.wire(%[[TILE_4_3]] : DMA, %[[SWITCHBOX_4_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : North, %[[SWITCHBOX_4_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_4]] : East, %[[SWITCHBOX_4_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_4]] : Core, %[[SWITCHBOX_4_4]] : Core) +// CHECK: aie.wire(%[[TILE_4_4]] : DMA, %[[SWITCHBOX_4_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : North, %[[SWITCHBOX_4_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_5]] : East, %[[SWITCHBOX_4_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_5]] : Core, %[[SWITCHBOX_4_5]] : Core) +// CHECK: aie.wire(%[[TILE_4_5]] : DMA, %[[SWITCHBOX_4_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_4]] : North, %[[SWITCHBOX_4_5]] : South) +// CHECK: aie.wire(%[[TILE_4_6]] : Core, %[[SWITCHBOX_4_6:.*]] : Core) +// CHECK: aie.wire(%[[TILE_4_6]] : DMA, %[[SWITCHBOX_4_6]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_5]] : North, %[[SWITCHBOX_4_6]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_1]] : East, %[[SWITCHBOX_5_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_1]] : Core, %[[SWITCHBOX_5_1]] : Core) +// CHECK: aie.wire(%[[TILE_5_1]] : DMA, %[[SWITCHBOX_5_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_0:.*]] : North, %[[SWITCHBOX_5_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) +// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : North, %[[SWITCHBOX_5_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_3]] : East, %[[SWITCHBOX_5_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_3]] : Core, %[[SWITCHBOX_5_3]] : Core) +// CHECK: aie.wire(%[[TILE_5_3]] : DMA, %[[SWITCHBOX_5_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : North, %[[SWITCHBOX_5_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_4]] : East, %[[SWITCHBOX_5_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_4]] : Core, %[[SWITCHBOX_5_4]] : Core) +// CHECK: aie.wire(%[[TILE_5_4]] : DMA, %[[SWITCHBOX_5_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : North, %[[SWITCHBOX_5_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_5]] : East, %[[SWITCHBOX_5_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_5]] : Core, %[[SWITCHBOX_5_5]] : Core) +// CHECK: aie.wire(%[[TILE_5_5]] : DMA, %[[SWITCHBOX_5_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_4]] : North, %[[SWITCHBOX_5_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_4_6]] : East, %[[SWITCHBOX_5_6:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_6]] : Core, %[[SWITCHBOX_5_6]] : Core) +// CHECK: aie.wire(%[[TILE_5_6]] : DMA, %[[SWITCHBOX_5_6]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_5]] : North, %[[SWITCHBOX_5_6]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) +// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_1]] : East, %[[SWITCHBOX_6_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1]] : Core) +// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) +// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_3]] : East, %[[SWITCHBOX_6_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_3]] : Core, %[[SWITCHBOX_6_3]] : Core) +// CHECK: aie.wire(%[[TILE_6_3]] : DMA, %[[SWITCHBOX_6_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : North, %[[SWITCHBOX_6_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_4]] : East, %[[SWITCHBOX_6_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_4]] : Core, %[[SWITCHBOX_6_4]] : Core) +// CHECK: aie.wire(%[[TILE_6_4]] : DMA, %[[SWITCHBOX_6_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : North, %[[SWITCHBOX_6_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_5]] : East, %[[SWITCHBOX_6_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_5]] : Core, %[[SWITCHBOX_6_5]] : Core) +// CHECK: aie.wire(%[[TILE_6_5]] : DMA, %[[SWITCHBOX_6_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_4]] : North, %[[SWITCHBOX_6_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_6]] : East, %[[SWITCHBOX_6_6:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_6]] : Core, %[[SWITCHBOX_6_6]] : Core) +// CHECK: aie.wire(%[[TILE_6_6]] : DMA, %[[SWITCHBOX_6_6]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_5]] : North, %[[SWITCHBOX_6_6]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) +// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) +// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_3]] : East, %[[SWITCHBOX_7_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3]] : Core) +// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_4]] : East, %[[SWITCHBOX_7_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_4]] : Core, %[[SWITCHBOX_7_4]] : Core) +// CHECK: aie.wire(%[[TILE_7_4]] : DMA, %[[SWITCHBOX_7_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : North, %[[SWITCHBOX_7_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_5]] : East, %[[SWITCHBOX_7_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_5]] : Core, %[[SWITCHBOX_7_5]] : Core) +// CHECK: aie.wire(%[[TILE_7_5]] : DMA, %[[SWITCHBOX_7_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : North, %[[SWITCHBOX_7_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_6]] : East, %[[SWITCHBOX_7_6:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_6]] : Core, %[[SWITCHBOX_7_6]] : Core) +// CHECK: aie.wire(%[[TILE_7_6]] : DMA, %[[SWITCHBOX_7_6]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_5]] : North, %[[SWITCHBOX_7_6]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : East, %[[SWITCHBOX_8_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_1]] : Core, %[[SWITCHBOX_8_1]] : Core) +// CHECK: aie.wire(%[[TILE_8_1]] : DMA, %[[SWITCHBOX_8_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) +// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : North, %[[SWITCHBOX_8_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) +// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : East, %[[SWITCHBOX_8_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_4]] : Core, %[[SWITCHBOX_8_4]] : Core) +// CHECK: aie.wire(%[[TILE_8_4]] : DMA, %[[SWITCHBOX_8_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : North, %[[SWITCHBOX_8_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : East, %[[SWITCHBOX_9_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_1]] : Core, %[[SWITCHBOX_9_1]] : Core) +// CHECK: aie.wire(%[[TILE_9_1]] : DMA, %[[SWITCHBOX_9_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : East, %[[SWITCHBOX_9_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_2]] : Core, %[[SWITCHBOX_9_2]] : Core) +// CHECK: aie.wire(%[[TILE_9_2]] : DMA, %[[SWITCHBOX_9_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_1]] : North, %[[SWITCHBOX_9_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : East, %[[SWITCHBOX_9_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_3]] : Core, %[[SWITCHBOX_9_3]] : Core) +// CHECK: aie.wire(%[[TILE_9_3]] : DMA, %[[SWITCHBOX_9_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : North, %[[SWITCHBOX_9_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_8_4]] : East, %[[SWITCHBOX_9_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_4]] : Core, %[[SWITCHBOX_9_4]] : Core) +// CHECK: aie.wire(%[[TILE_9_4]] : DMA, %[[SWITCHBOX_9_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_3]] : North, %[[SWITCHBOX_9_4]] : South) +// CHECK: aie.wire(%[[SHIM_MUX_10_0:.*]] : North, %[[SWITCHBOX_10_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_10_0]] : DMA, %[[SHIM_MUX_10_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_1]] : East, %[[SWITCHBOX_10_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_1]] : Core, %[[SWITCHBOX_10_1]] : Core) +// CHECK: aie.wire(%[[TILE_10_1]] : DMA, %[[SWITCHBOX_10_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : North, %[[SWITCHBOX_10_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : East, %[[SWITCHBOX_10_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_2]] : Core, %[[SWITCHBOX_10_2]] : Core) +// CHECK: aie.wire(%[[TILE_10_2]] : DMA, %[[SWITCHBOX_10_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_1]] : North, %[[SWITCHBOX_10_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_9_3]] : East, %[[SWITCHBOX_10_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_3]] : Core, %[[SWITCHBOX_10_3]] : Core) +// CHECK: aie.wire(%[[TILE_10_3]] : DMA, %[[SWITCHBOX_10_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_2]] : North, %[[SWITCHBOX_10_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_9_4]] : East, %[[SWITCHBOX_10_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_4]] : Core, %[[SWITCHBOX_10_4]] : Core) +// CHECK: aie.wire(%[[TILE_10_4]] : DMA, %[[SWITCHBOX_10_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_3]] : North, %[[SWITCHBOX_10_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : East, %[[SWITCHBOX_11_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_11_0:.*]] : North, %[[SWITCHBOX_11_0]] : South) +// CHECK: aie.wire(%[[TILE_11_0]] : DMA, %[[SHIM_MUX_11_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_1]] : East, %[[SWITCHBOX_11_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_1]] : Core, %[[SWITCHBOX_11_1]] : Core) +// CHECK: aie.wire(%[[TILE_11_1]] : DMA, %[[SWITCHBOX_11_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_0]] : North, %[[SWITCHBOX_11_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_2]] : East, %[[SWITCHBOX_11_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_2]] : Core, %[[SWITCHBOX_11_2]] : Core) +// CHECK: aie.wire(%[[TILE_11_2]] : DMA, %[[SWITCHBOX_11_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_1]] : North, %[[SWITCHBOX_11_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_3]] : East, %[[SWITCHBOX_11_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_3]] : Core, %[[SWITCHBOX_11_3]] : Core) +// CHECK: aie.wire(%[[TILE_11_3]] : DMA, %[[SWITCHBOX_11_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_2]] : North, %[[SWITCHBOX_11_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_4]] : East, %[[SWITCHBOX_11_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_4]] : Core, %[[SWITCHBOX_11_4]] : Core) +// CHECK: aie.wire(%[[TILE_11_4]] : DMA, %[[SWITCHBOX_11_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_3]] : North, %[[SWITCHBOX_11_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_11_0]] : East, %[[SWITCHBOX_12_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_11_1]] : East, %[[SWITCHBOX_12_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_12_1]] : Core, %[[SWITCHBOX_12_1]] : Core) +// CHECK: aie.wire(%[[TILE_12_1]] : DMA, %[[SWITCHBOX_12_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_12_0]] : North, %[[SWITCHBOX_12_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_11_2]] : East, %[[SWITCHBOX_12_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_12_2]] : Core, %[[SWITCHBOX_12_2]] : Core) +// CHECK: aie.wire(%[[TILE_12_2]] : DMA, %[[SWITCHBOX_12_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_12_1]] : North, %[[SWITCHBOX_12_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_11_3]] : East, %[[SWITCHBOX_12_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_12_3]] : Core, %[[SWITCHBOX_12_3]] : Core) +// CHECK: aie.wire(%[[TILE_12_3]] : DMA, %[[SWITCHBOX_12_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_12_2]] : North, %[[SWITCHBOX_12_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_11_4]] : East, %[[SWITCHBOX_12_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_12_4]] : Core, %[[SWITCHBOX_12_4]] : Core) +// CHECK: aie.wire(%[[TILE_12_4]] : DMA, %[[SWITCHBOX_12_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_12_3]] : North, %[[SWITCHBOX_12_4]] : South) +// CHECK: aie.wire(%[[TILE_12_5]] : Core, %[[SWITCHBOX_12_5:.*]] : Core) +// CHECK: aie.wire(%[[TILE_12_5]] : DMA, %[[SWITCHBOX_12_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_12_4]] : North, %[[SWITCHBOX_12_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_12_0]] : East, %[[SWITCHBOX_13_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_12_1]] : East, %[[SWITCHBOX_13_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_13_1]] : Core, %[[SWITCHBOX_13_1]] : Core) +// CHECK: aie.wire(%[[TILE_13_1]] : DMA, %[[SWITCHBOX_13_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_13_0]] : North, %[[SWITCHBOX_13_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_12_2]] : East, %[[SWITCHBOX_13_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_13_2]] : Core, %[[SWITCHBOX_13_2]] : Core) +// CHECK: aie.wire(%[[TILE_13_2]] : DMA, %[[SWITCHBOX_13_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_13_1]] : North, %[[SWITCHBOX_13_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_12_3]] : East, %[[SWITCHBOX_13_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_13_3]] : Core, %[[SWITCHBOX_13_3]] : Core) +// CHECK: aie.wire(%[[TILE_13_3]] : DMA, %[[SWITCHBOX_13_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_13_2]] : North, %[[SWITCHBOX_13_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_12_4]] : East, %[[SWITCHBOX_13_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_13_4]] : Core, %[[SWITCHBOX_13_4]] : Core) +// CHECK: aie.wire(%[[TILE_13_4]] : DMA, %[[SWITCHBOX_13_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_13_3]] : North, %[[SWITCHBOX_13_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_12_5]] : East, %[[SWITCHBOX_13_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_13_5]] : Core, %[[SWITCHBOX_13_5]] : Core) +// CHECK: aie.wire(%[[TILE_13_5]] : DMA, %[[SWITCHBOX_13_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_13_4]] : North, %[[SWITCHBOX_13_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_13_2]] : East, %[[SWITCHBOX_14_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_14_2]] : Core, %[[SWITCHBOX_14_2]] : Core) +// CHECK: aie.wire(%[[TILE_14_2]] : DMA, %[[SWITCHBOX_14_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_13_3]] : East, %[[SWITCHBOX_14_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_14_3]] : Core, %[[SWITCHBOX_14_3]] : Core) +// CHECK: aie.wire(%[[TILE_14_3]] : DMA, %[[SWITCHBOX_14_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_14_2]] : North, %[[SWITCHBOX_14_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_13_4]] : East, %[[SWITCHBOX_14_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_14_4]] : Core, %[[SWITCHBOX_14_4]] : Core) +// CHECK: aie.wire(%[[TILE_14_4]] : DMA, %[[SWITCHBOX_14_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_14_3]] : North, %[[SWITCHBOX_14_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_13_5]] : East, %[[SWITCHBOX_14_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_14_5]] : Core, %[[SWITCHBOX_14_5]] : Core) +// CHECK: aie.wire(%[[TILE_14_5]] : DMA, %[[SWITCHBOX_14_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_14_4]] : North, %[[SWITCHBOX_14_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_14_2]] : East, %[[SWITCHBOX_15_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_15_2]] : Core, %[[SWITCHBOX_15_2]] : Core) +// CHECK: aie.wire(%[[TILE_15_2]] : DMA, %[[SWITCHBOX_15_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_15_2]] : East, %[[SWITCHBOX_16_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_16_2]] : Core, %[[SWITCHBOX_16_2]] : Core) +// CHECK: aie.wire(%[[TILE_16_2]] : DMA, %[[SWITCHBOX_16_2]] : DMA) +// CHECK: aie.wire(%[[TILE_17_1]] : Core, %[[SWITCHBOX_17_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_17_1]] : DMA, %[[SWITCHBOX_17_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_17_0:.*]] : North, %[[SWITCHBOX_17_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_16_2]] : East, %[[SWITCHBOX_17_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_17_2]] : Core, %[[SWITCHBOX_17_2]] : Core) +// CHECK: aie.wire(%[[TILE_17_2]] : DMA, %[[SWITCHBOX_17_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_17_1]] : North, %[[SWITCHBOX_17_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_17_0]] : East, %[[SWITCHBOX_18_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_18_0:.*]] : North, %[[SWITCHBOX_18_0]] : South) +// CHECK: aie.wire(%[[TILE_18_0]] : DMA, %[[SHIM_MUX_18_0]] : DMA) // CHECK: } module { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple.mlir index 0ab440df4..e5e1fdfaa 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple.mlir @@ -1,41 +1,32 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_1:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_3:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[SWITCHBOX_0_1:.*]] = aie.switchbox(%[[TILE_0_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_4:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: %[[SWITCHBOX_0_2:.*]] = aie.switchbox(%[[TILE_0_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_5:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[SWITCHBOX_1_2:.*]] = aie.switchbox(%[[TILE_1_2]]) { // CHECK: aie.connect // CHECK: } // CHECK: aie.packet_flow(16) { -// CHECK: aie.packet_source<%[[VAL_0]], Core : 0> -// CHECK: aie.packet_dest<%[[VAL_1]], Core : 0> -// CHECK: aie.packet_dest<%[[VAL_2]], DMA : 1> +// CHECK: aie.packet_source<%[[TILE_0_1]], Core : 0> +// CHECK: aie.packet_dest<%[[TILE_1_2]], Core : 0> +// CHECK: aie.packet_dest<%[[TILE_0_2]], DMA : 1> // CHECK: } -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_6:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_6]] : DMA) -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_7:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_7]] : DMA) -// CHECK: aie.wire(%[[VAL_6]] : North, %[[VAL_7]] : South) -// CHECK: aie.wire(%[[VAL_7]] : East, %[[VAL_8:.*]] : West) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_8]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_8]] : DMA) +// CHECK: aie.wire(%[[TILE_0_1]] : Core, %[[SWITCHBOX_0_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_1]] : DMA, %[[SWITCHBOX_0_1]] : DMA) +// CHECK: aie.wire(%[[TILE_0_2]] : Core, %[[SWITCHBOX_0_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_0_2]] : DMA, %[[SWITCHBOX_0_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_0_1]] : North, %[[SWITCHBOX_0_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_0_2]] : East, %[[SWITCHBOX_1_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_1_2]] : Core, %[[SWITCHBOX_1_2]] : Core) +// CHECK: aie.wire(%[[TILE_1_2]] : DMA, %[[SWITCHBOX_1_2]] : DMA) // CHECK: } module { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple2.mlir index 003c87ed8..e29007154 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple2.mlir @@ -1,36 +1,27 @@ -//===- simple2.mlir --------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_1:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_3:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_4:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_5:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_6:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_6]] : DMA) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_7:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_7]] : DMA) -// CHECK: aie.wire(%[[VAL_6]] : North, %[[VAL_7]] : South) -// CHECK: aie.wire(%[[VAL_6]] : East, %[[VAL_8:.*]] : West) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_8]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_8]] : DMA) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) // CHECK: } module { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows.mlir index e56b076b5..13a8541e2 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows.mlir @@ -1,32 +1,23 @@ -//===- simple_flows.mlir ---------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_2:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_3:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_4:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_4]] : DMA) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_5:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_5]] : DMA) -// CHECK: aie.wire(%[[VAL_4]] : North, %[[VAL_5]] : South) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) // CHECK: } module { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows2.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows2.mlir index d4ef64d2b..b25fc9439 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows2.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows2.mlir @@ -1,44 +1,35 @@ -//===- simple_flows2.mlir --------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_1:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_2:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_3:.*]] = aie.switchbox(%[[VAL_1]]) { +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_4:.*]] = aie.switchbox(%[[VAL_0]]) { +// CHECK: %[[SWITCHBOX_2_3:.*]] = aie.switchbox(%[[TILE_2_3]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_5:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: %[[SWITCHBOX_1_1:.*]] = aie.switchbox(%[[TILE_1_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_6:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_7:.*]] = aie.switchbox(%[[VAL_6]]) { +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_2]] : Core, %[[VAL_8:.*]] : Core) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_8]] : DMA) -// CHECK: aie.wire(%[[VAL_8]] : East, %[[VAL_9:.*]] : West) -// CHECK: aie.wire(%[[VAL_6]] : Core, %[[VAL_9]] : Core) -// CHECK: aie.wire(%[[VAL_6]] : DMA, %[[VAL_9]] : DMA) -// CHECK: aie.wire(%[[VAL_1]] : Core, %[[VAL_10:.*]] : Core) -// CHECK: aie.wire(%[[VAL_1]] : DMA, %[[VAL_10]] : DMA) -// CHECK: aie.wire(%[[VAL_9]] : North, %[[VAL_10]] : South) -// CHECK: aie.wire(%[[VAL_0]] : Core, %[[VAL_11:.*]] : Core) -// CHECK: aie.wire(%[[VAL_0]] : DMA, %[[VAL_11]] : DMA) -// CHECK: aie.wire(%[[VAL_10]] : North, %[[VAL_11]] : South) +// CHECK: aie.wire(%[[TILE_1_1]] : Core, %[[SWITCHBOX_1_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_1_1]] : DMA, %[[SWITCHBOX_1_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_1_1]] : East, %[[SWITCHBOX_2_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) +// CHECK: aie.wire(%[[TILE_2_3]] : Core, %[[SWITCHBOX_2_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_3]] : DMA, %[[SWITCHBOX_2_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : North, %[[SWITCHBOX_2_3]] : South) // CHECK: } module { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows_shim.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows_shim.mlir index 7c307c447..2daad27b7 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows_shim.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_simple_flows_shim.mlir @@ -1,23 +1,20 @@ -//===- simple_flows_shim.mlir ----------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --split-input-file --aie-create-pathfinder-flows %s | FileCheck %s -// CHECK: module -// CHECK: %[[T21:.*]] = aie.tile(2, 1) -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %{{.*}} = aie.switchbox(%[[T20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.switchbox(%[[T21]]) { -// CHECK: aie.connect -// CHECK: } + +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0:.*]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: } + module { aie.device(xcvc1902) { %t23 = aie.tile(2, 1) @@ -28,18 +25,25 @@ module { // ----- -// CHECK: module -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %[[T21:.*]] = aie.tile(2, 1) -// CHECK: %{{.*}} = aie.switchbox(%[[T20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.shim_mux(%[[T20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.switchbox(%[[T21]]) { -// CHECK: aie.connect -// CHECK: } +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: } + module { aie.device(xcvc1902) { %t20 = aie.tile(2, 0) @@ -50,21 +54,28 @@ module { // ----- -// CHECK: module -// CHECK: %[[T20:.*]] = aie.tile(2, 0) -// CHECK: %[[T30:.*]] = aie.tile(3, 0) -// CHECK: %{{.*}} = aie.switchbox(%[[T20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.shim_mux(%[[T20]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.switchbox(%[[T30]]) { -// CHECK: aie.connect -// CHECK: } -// CHECK: %{{.*}} = aie.shim_mux(%[[T30]]) { -// CHECK: aie.connect -// CHECK: } +// CHECK-LABEL: aie.device(xcvc1902) { +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { +// CHECK: aie.connect +// CHECK: } +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) +// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) +// CHECK: } + module { aie.device(xcvc1902) { %t20 = aie.tile(2, 0) diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_vecmul_4x4.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_vecmul_4x4.mlir index 691a719e1..43fc956f8 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_vecmul_4x4.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/unit_vecmul_4x4.mlir @@ -1,897 +1,888 @@ -//===- vecmul_4x4.mlir -----------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2021 Xilinx Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-create-pathfinder-flows %s | FileCheck %s // CHECK-LABEL: aie.device(xcvc1902) { -// CHECK: %[[VAL_0:.*]] = aie.tile(47, 2) -// CHECK: %[[VAL_1:.*]] = aie.tile(47, 1) -// CHECK: %[[VAL_2:.*]] = aie.tile(47, 0) -// CHECK: %[[VAL_3:.*]] = aie.tile(3, 3) -// CHECK: %[[VAL_4:.*]] = aie.tile(10, 5) -// CHECK: %[[VAL_5:.*]] = aie.lock(%[[VAL_4]], 2) -// CHECK: %[[VAL_6:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "buf47"} : memref<64xi32, 2> -// CHECK: %[[VAL_7:.*]] = aie.lock(%[[VAL_4]], 1) -// CHECK: %[[VAL_8:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "buf46"} : memref<64xi32, 2> -// CHECK: %[[VAL_9:.*]] = aie.lock(%[[VAL_4]], 0) -// CHECK: %[[VAL_10:.*]] = aie.buffer(%[[VAL_4]]) {sym_name = "buf45"} : memref<64xi32, 2> -// CHECK: %[[VAL_11:.*]] = aie.mem(%[[VAL_4]]) { -// CHECK: %[[VAL_12:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_47_2:.*]] = aie.tile(47, 2) +// CHECK: %[[TILE_47_1:.*]] = aie.tile(47, 1) +// CHECK: %[[TILE_47_0:.*]] = aie.tile(47, 0) +// CHECK: %[[TILE_3_3:.*]] = aie.tile(3, 3) +// CHECK: %[[TILE_10_5:.*]] = aie.tile(10, 5) +// CHECK: %[[LOCK_10_5:.*]] = aie.lock(%[[TILE_10_5]], 2) +// CHECK: %[[BUF47:.*]] = aie.buffer(%[[TILE_10_5]]) {sym_name = "buf47"} : memref<64xi32, 2> +// CHECK: %[[LOCK_10_5_0:.*]] = aie.lock(%[[TILE_10_5]], 1) +// CHECK: %[[BUF46:.*]] = aie.buffer(%[[TILE_10_5]]) {sym_name = "buf46"} : memref<64xi32, 2> +// CHECK: %[[LOCK_10_5_1:.*]] = aie.lock(%[[TILE_10_5]], 0) +// CHECK: %[[BUF45:.*]] = aie.buffer(%[[TILE_10_5]]) {sym_name = "buf45"} : memref<64xi32, 2> +// CHECK: %[[MEM_10_5:.*]] = aie.mem(%[[TILE_10_5]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_10]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_10_5_1]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF45]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_10_5_1]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_13:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_8]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_10_5_0]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF46]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_10_5_0]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_14:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_2:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_6]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_5]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_10_5]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF47]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_10_5]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_15:.*]] = aie.core(%[[VAL_4]]) { +// CHECK: %[[CORE_10_5:.*]] = aie.core(%[[TILE_10_5]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_9]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_7]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_5]], Acquire, 0) -// CHECK: affine.for %[[VAL_16:.*]] = 0 to 64 { -// CHECK: %[[VAL_17:.*]] = affine.load %[[VAL_10]]{{\[}}%[[VAL_16]]] : memref<64xi32, 2> -// CHECK: %[[VAL_18:.*]] = affine.load %[[VAL_8]]{{\[}}%[[VAL_16]]] : memref<64xi32, 2> -// CHECK: %[[VAL_19:.*]] = arith.muli %[[VAL_17]], %[[VAL_18]] : i32 -// CHECK: affine.store %[[VAL_19]], %[[VAL_6]]{{\[}}%[[VAL_16]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_10_5_1]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_10_5_0]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_10_5]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_3:.*]] = affine.load %[[BUF45]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_4:.*]] = affine.load %[[BUF46]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_5:.*]] = arith.muli %[[VAL_3]], %[[VAL_4]] : i32 +// CHECK: affine.store %[[VAL_5]], %[[BUF47]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_5]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_7]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_9]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_10_5]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_10_5_0]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_10_5_1]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_20:.*]] = aie.tile(46, 2) -// CHECK: %[[VAL_21:.*]] = aie.tile(46, 1) -// CHECK: %[[VAL_22:.*]] = aie.tile(46, 0) -// CHECK: %[[VAL_23:.*]] = aie.tile(2, 3) -// CHECK: %[[VAL_24:.*]] = aie.tile(9, 5) -// CHECK: %[[VAL_25:.*]] = aie.lock(%[[VAL_24]], 2) -// CHECK: %[[VAL_26:.*]] = aie.buffer(%[[VAL_24]]) {sym_name = "buf44"} : memref<64xi32, 2> -// CHECK: %[[VAL_27:.*]] = aie.lock(%[[VAL_24]], 1) -// CHECK: %[[VAL_28:.*]] = aie.buffer(%[[VAL_24]]) {sym_name = "buf43"} : memref<64xi32, 2> -// CHECK: %[[VAL_29:.*]] = aie.lock(%[[VAL_24]], 0) -// CHECK: %[[VAL_30:.*]] = aie.buffer(%[[VAL_24]]) {sym_name = "buf42"} : memref<64xi32, 2> -// CHECK: %[[VAL_31:.*]] = aie.mem(%[[VAL_24]]) { -// CHECK: %[[VAL_32:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_46_2:.*]] = aie.tile(46, 2) +// CHECK: %[[TILE_46_1:.*]] = aie.tile(46, 1) +// CHECK: %[[TILE_46_0:.*]] = aie.tile(46, 0) +// CHECK: %[[TILE_2_3:.*]] = aie.tile(2, 3) +// CHECK: %[[TILE_9_5:.*]] = aie.tile(9, 5) +// CHECK: %[[LOCK_9_5:.*]] = aie.lock(%[[TILE_9_5]], 2) +// CHECK: %[[BUF44:.*]] = aie.buffer(%[[TILE_9_5]]) {sym_name = "buf44"} : memref<64xi32, 2> +// CHECK: %[[LOCK_9_5_2:.*]] = aie.lock(%[[TILE_9_5]], 1) +// CHECK: %[[BUF43:.*]] = aie.buffer(%[[TILE_9_5]]) {sym_name = "buf43"} : memref<64xi32, 2> +// CHECK: %[[LOCK_9_5_3:.*]] = aie.lock(%[[TILE_9_5]], 0) +// CHECK: %[[BUF42:.*]] = aie.buffer(%[[TILE_9_5]]) {sym_name = "buf42"} : memref<64xi32, 2> +// CHECK: %[[MEM_9_5:.*]] = aie.mem(%[[TILE_9_5]]) { +// CHECK: %[[VAL_6:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_29]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_30]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_29]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_9_5_3]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF42]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_9_5_3]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_33:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_7:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_27]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_28]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_27]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_9_5_2]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF43]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_9_5_2]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_34:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_8:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_25]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_26]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_25]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_9_5]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF44]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_9_5]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_35:.*]] = aie.core(%[[VAL_24]]) { +// CHECK: %[[CORE_9_5:.*]] = aie.core(%[[TILE_9_5]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_29]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_27]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_25]], Acquire, 0) -// CHECK: affine.for %[[VAL_36:.*]] = 0 to 64 { -// CHECK: %[[VAL_37:.*]] = affine.load %[[VAL_30]]{{\[}}%[[VAL_36]]] : memref<64xi32, 2> -// CHECK: %[[VAL_38:.*]] = affine.load %[[VAL_28]]{{\[}}%[[VAL_36]]] : memref<64xi32, 2> -// CHECK: %[[VAL_39:.*]] = arith.muli %[[VAL_37]], %[[VAL_38]] : i32 -// CHECK: affine.store %[[VAL_39]], %[[VAL_26]]{{\[}}%[[VAL_36]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_9_5_3]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_9_5_2]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_9_5]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_9:.*]] = affine.load %[[BUF42]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_10:.*]] = affine.load %[[BUF43]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_11:.*]] = arith.muli %[[VAL_9]], %[[VAL_10]] : i32 +// CHECK: affine.store %[[VAL_11]], %[[BUF44]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_25]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_27]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_29]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_9_5]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_9_5_2]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_9_5_3]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_40:.*]] = aie.tile(43, 2) -// CHECK: %[[VAL_41:.*]] = aie.tile(43, 1) -// CHECK: %[[VAL_42:.*]] = aie.tile(43, 0) -// CHECK: %[[VAL_43:.*]] = aie.tile(1, 3) -// CHECK: %[[VAL_44:.*]] = aie.tile(8, 5) -// CHECK: %[[VAL_45:.*]] = aie.lock(%[[VAL_44]], 2) -// CHECK: %[[VAL_46:.*]] = aie.buffer(%[[VAL_44]]) {sym_name = "buf41"} : memref<64xi32, 2> -// CHECK: %[[VAL_47:.*]] = aie.lock(%[[VAL_44]], 1) -// CHECK: %[[VAL_48:.*]] = aie.buffer(%[[VAL_44]]) {sym_name = "buf40"} : memref<64xi32, 2> -// CHECK: %[[VAL_49:.*]] = aie.lock(%[[VAL_44]], 0) -// CHECK: %[[VAL_50:.*]] = aie.buffer(%[[VAL_44]]) {sym_name = "buf39"} : memref<64xi32, 2> -// CHECK: %[[VAL_51:.*]] = aie.mem(%[[VAL_44]]) { -// CHECK: %[[VAL_52:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_43_2:.*]] = aie.tile(43, 2) +// CHECK: %[[TILE_43_1:.*]] = aie.tile(43, 1) +// CHECK: %[[TILE_43_0:.*]] = aie.tile(43, 0) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[TILE_8_5:.*]] = aie.tile(8, 5) +// CHECK: %[[LOCK_8_5:.*]] = aie.lock(%[[TILE_8_5]], 2) +// CHECK: %[[BUF41:.*]] = aie.buffer(%[[TILE_8_5]]) {sym_name = "buf41"} : memref<64xi32, 2> +// CHECK: %[[LOCK_8_5_4:.*]] = aie.lock(%[[TILE_8_5]], 1) +// CHECK: %[[BUF40:.*]] = aie.buffer(%[[TILE_8_5]]) {sym_name = "buf40"} : memref<64xi32, 2> +// CHECK: %[[LOCK_8_5_5:.*]] = aie.lock(%[[TILE_8_5]], 0) +// CHECK: %[[BUF39:.*]] = aie.buffer(%[[TILE_8_5]]) {sym_name = "buf39"} : memref<64xi32, 2> +// CHECK: %[[MEM_8_5:.*]] = aie.mem(%[[TILE_8_5]]) { +// CHECK: %[[VAL_12:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_49]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_50]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_49]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_5_5]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF39]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_8_5_5]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_53:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_13:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_47]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_48]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_47]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_5_4]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF40]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_8_5_4]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_54:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_14:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_45]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_46]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_45]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_5]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF41]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_8_5]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_55:.*]] = aie.core(%[[VAL_44]]) { +// CHECK: %[[CORE_8_5:.*]] = aie.core(%[[TILE_8_5]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_49]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_47]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_45]], Acquire, 0) -// CHECK: affine.for %[[VAL_56:.*]] = 0 to 64 { -// CHECK: %[[VAL_57:.*]] = affine.load %[[VAL_50]]{{\[}}%[[VAL_56]]] : memref<64xi32, 2> -// CHECK: %[[VAL_58:.*]] = affine.load %[[VAL_48]]{{\[}}%[[VAL_56]]] : memref<64xi32, 2> -// CHECK: %[[VAL_59:.*]] = arith.muli %[[VAL_57]], %[[VAL_58]] : i32 -// CHECK: affine.store %[[VAL_59]], %[[VAL_46]]{{\[}}%[[VAL_56]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_8_5_5]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_8_5_4]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_8_5]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_15:.*]] = affine.load %[[BUF39]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_16:.*]] = affine.load %[[BUF40]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_17:.*]] = arith.muli %[[VAL_15]], %[[VAL_16]] : i32 +// CHECK: affine.store %[[VAL_17]], %[[BUF41]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_45]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_47]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_49]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_5]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_5_4]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_5_5]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_60:.*]] = aie.tile(42, 2) -// CHECK: %[[VAL_61:.*]] = aie.tile(42, 1) -// CHECK: %[[VAL_62:.*]] = aie.tile(42, 0) -// CHECK: %[[VAL_63:.*]] = aie.tile(0, 3) -// CHECK: %[[VAL_64:.*]] = aie.tile(7, 5) -// CHECK: %[[VAL_65:.*]] = aie.lock(%[[VAL_64]], 2) -// CHECK: %[[VAL_66:.*]] = aie.buffer(%[[VAL_64]]) {sym_name = "buf38"} : memref<64xi32, 2> -// CHECK: %[[VAL_67:.*]] = aie.lock(%[[VAL_64]], 1) -// CHECK: %[[VAL_68:.*]] = aie.buffer(%[[VAL_64]]) {sym_name = "buf37"} : memref<64xi32, 2> -// CHECK: %[[VAL_69:.*]] = aie.lock(%[[VAL_64]], 0) -// CHECK: %[[VAL_70:.*]] = aie.buffer(%[[VAL_64]]) {sym_name = "buf36"} : memref<64xi32, 2> -// CHECK: %[[VAL_71:.*]] = aie.mem(%[[VAL_64]]) { -// CHECK: %[[VAL_72:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_42_2:.*]] = aie.tile(42, 2) +// CHECK: %[[TILE_42_1:.*]] = aie.tile(42, 1) +// CHECK: %[[TILE_42_0:.*]] = aie.tile(42, 0) +// CHECK: %[[TILE_0_3:.*]] = aie.tile(0, 3) +// CHECK: %[[TILE_7_5:.*]] = aie.tile(7, 5) +// CHECK: %[[LOCK_7_5:.*]] = aie.lock(%[[TILE_7_5]], 2) +// CHECK: %[[BUF38:.*]] = aie.buffer(%[[TILE_7_5]]) {sym_name = "buf38"} : memref<64xi32, 2> +// CHECK: %[[LOCK_7_5_6:.*]] = aie.lock(%[[TILE_7_5]], 1) +// CHECK: %[[BUF37:.*]] = aie.buffer(%[[TILE_7_5]]) {sym_name = "buf37"} : memref<64xi32, 2> +// CHECK: %[[LOCK_7_5_7:.*]] = aie.lock(%[[TILE_7_5]], 0) +// CHECK: %[[BUF36:.*]] = aie.buffer(%[[TILE_7_5]]) {sym_name = "buf36"} : memref<64xi32, 2> +// CHECK: %[[MEM_7_5:.*]] = aie.mem(%[[TILE_7_5]]) { +// CHECK: %[[VAL_18:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_69]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_70]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_69]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_5_7]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF36]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_7_5_7]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_73:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_19:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_67]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_68]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_67]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_5_6]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF37]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_7_5_6]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_74:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_20:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_65]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_66]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_65]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_5]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF38]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_7_5]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_75:.*]] = aie.core(%[[VAL_64]]) { +// CHECK: %[[CORE_7_5:.*]] = aie.core(%[[TILE_7_5]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_69]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_67]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_65]], Acquire, 0) -// CHECK: affine.for %[[VAL_76:.*]] = 0 to 64 { -// CHECK: %[[VAL_77:.*]] = affine.load %[[VAL_70]]{{\[}}%[[VAL_76]]] : memref<64xi32, 2> -// CHECK: %[[VAL_78:.*]] = affine.load %[[VAL_68]]{{\[}}%[[VAL_76]]] : memref<64xi32, 2> -// CHECK: %[[VAL_79:.*]] = arith.muli %[[VAL_77]], %[[VAL_78]] : i32 -// CHECK: affine.store %[[VAL_79]], %[[VAL_66]]{{\[}}%[[VAL_76]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_7_5_7]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_7_5_6]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_7_5]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_21:.*]] = affine.load %[[BUF36]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_22:.*]] = affine.load %[[BUF37]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_23:.*]] = arith.muli %[[VAL_21]], %[[VAL_22]] : i32 +// CHECK: affine.store %[[VAL_23]], %[[BUF38]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_65]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_67]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_69]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_5]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_5_6]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_5_7]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_80:.*]] = aie.tile(35, 2) -// CHECK: %[[VAL_81:.*]] = aie.tile(35, 1) -// CHECK: %[[VAL_82:.*]] = aie.tile(35, 0) -// CHECK: %[[VAL_83:.*]] = aie.tile(10, 4) -// CHECK: %[[VAL_84:.*]] = aie.lock(%[[VAL_83]], 2) -// CHECK: %[[VAL_85:.*]] = aie.buffer(%[[VAL_83]]) {sym_name = "buf35"} : memref<64xi32, 2> -// CHECK: %[[VAL_86:.*]] = aie.lock(%[[VAL_83]], 1) -// CHECK: %[[VAL_87:.*]] = aie.buffer(%[[VAL_83]]) {sym_name = "buf34"} : memref<64xi32, 2> -// CHECK: %[[VAL_88:.*]] = aie.lock(%[[VAL_83]], 0) -// CHECK: %[[VAL_89:.*]] = aie.buffer(%[[VAL_83]]) {sym_name = "buf33"} : memref<64xi32, 2> -// CHECK: %[[VAL_90:.*]] = aie.mem(%[[VAL_83]]) { -// CHECK: %[[VAL_91:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_35_2:.*]] = aie.tile(35, 2) +// CHECK: %[[TILE_35_1:.*]] = aie.tile(35, 1) +// CHECK: %[[TILE_35_0:.*]] = aie.tile(35, 0) +// CHECK: %[[TILE_10_4:.*]] = aie.tile(10, 4) +// CHECK: %[[LOCK_10_4:.*]] = aie.lock(%[[TILE_10_4]], 2) +// CHECK: %[[BUF35:.*]] = aie.buffer(%[[TILE_10_4]]) {sym_name = "buf35"} : memref<64xi32, 2> +// CHECK: %[[LOCK_10_4_8:.*]] = aie.lock(%[[TILE_10_4]], 1) +// CHECK: %[[BUF34:.*]] = aie.buffer(%[[TILE_10_4]]) {sym_name = "buf34"} : memref<64xi32, 2> +// CHECK: %[[LOCK_10_4_9:.*]] = aie.lock(%[[TILE_10_4]], 0) +// CHECK: %[[BUF33:.*]] = aie.buffer(%[[TILE_10_4]]) {sym_name = "buf33"} : memref<64xi32, 2> +// CHECK: %[[MEM_10_4:.*]] = aie.mem(%[[TILE_10_4]]) { +// CHECK: %[[VAL_24:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_88]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_89]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_88]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_10_4_9]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF33]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_10_4_9]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_92:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_25:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_86]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_87]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_86]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_10_4_8]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF34]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_10_4_8]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_93:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_26:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_84]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_85]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_84]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_10_4]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF35]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_10_4]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_94:.*]] = aie.core(%[[VAL_83]]) { +// CHECK: %[[CORE_10_4:.*]] = aie.core(%[[TILE_10_4]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_88]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_86]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_84]], Acquire, 0) -// CHECK: affine.for %[[VAL_95:.*]] = 0 to 64 { -// CHECK: %[[VAL_96:.*]] = affine.load %[[VAL_89]]{{\[}}%[[VAL_95]]] : memref<64xi32, 2> -// CHECK: %[[VAL_97:.*]] = affine.load %[[VAL_87]]{{\[}}%[[VAL_95]]] : memref<64xi32, 2> -// CHECK: %[[VAL_98:.*]] = arith.muli %[[VAL_96]], %[[VAL_97]] : i32 -// CHECK: affine.store %[[VAL_98]], %[[VAL_85]]{{\[}}%[[VAL_95]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_10_4_9]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_10_4_8]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_10_4]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_27:.*]] = affine.load %[[BUF33]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_28:.*]] = affine.load %[[BUF34]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_29:.*]] = arith.muli %[[VAL_27]], %[[VAL_28]] : i32 +// CHECK: affine.store %[[VAL_29]], %[[BUF35]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_84]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_86]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_88]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_10_4]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_10_4_8]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_10_4_9]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_99:.*]] = aie.tile(34, 2) -// CHECK: %[[VAL_100:.*]] = aie.tile(34, 1) -// CHECK: %[[VAL_101:.*]] = aie.tile(34, 0) -// CHECK: %[[VAL_102:.*]] = aie.tile(9, 4) -// CHECK: %[[VAL_103:.*]] = aie.lock(%[[VAL_102]], 2) -// CHECK: %[[VAL_104:.*]] = aie.buffer(%[[VAL_102]]) {sym_name = "buf32"} : memref<64xi32, 2> -// CHECK: %[[VAL_105:.*]] = aie.lock(%[[VAL_102]], 1) -// CHECK: %[[VAL_106:.*]] = aie.buffer(%[[VAL_102]]) {sym_name = "buf31"} : memref<64xi32, 2> -// CHECK: %[[VAL_107:.*]] = aie.lock(%[[VAL_102]], 0) -// CHECK: %[[VAL_108:.*]] = aie.buffer(%[[VAL_102]]) {sym_name = "buf30"} : memref<64xi32, 2> -// CHECK: %[[VAL_109:.*]] = aie.mem(%[[VAL_102]]) { -// CHECK: %[[VAL_110:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_34_2:.*]] = aie.tile(34, 2) +// CHECK: %[[TILE_34_1:.*]] = aie.tile(34, 1) +// CHECK: %[[TILE_34_0:.*]] = aie.tile(34, 0) +// CHECK: %[[TILE_9_4:.*]] = aie.tile(9, 4) +// CHECK: %[[LOCK_9_4:.*]] = aie.lock(%[[TILE_9_4]], 2) +// CHECK: %[[BUF32:.*]] = aie.buffer(%[[TILE_9_4]]) {sym_name = "buf32"} : memref<64xi32, 2> +// CHECK: %[[LOCK_9_4_10:.*]] = aie.lock(%[[TILE_9_4]], 1) +// CHECK: %[[BUF31:.*]] = aie.buffer(%[[TILE_9_4]]) {sym_name = "buf31"} : memref<64xi32, 2> +// CHECK: %[[LOCK_9_4_11:.*]] = aie.lock(%[[TILE_9_4]], 0) +// CHECK: %[[BUF30:.*]] = aie.buffer(%[[TILE_9_4]]) {sym_name = "buf30"} : memref<64xi32, 2> +// CHECK: %[[MEM_9_4:.*]] = aie.mem(%[[TILE_9_4]]) { +// CHECK: %[[VAL_30:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_107]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_108]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_107]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_9_4_11]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF30]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_9_4_11]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_111:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_31:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_105]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_106]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_105]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_9_4_10]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF31]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_9_4_10]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_112:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_32:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_103]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_104]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_103]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_9_4]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF32]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_9_4]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_113:.*]] = aie.core(%[[VAL_102]]) { +// CHECK: %[[CORE_9_4:.*]] = aie.core(%[[TILE_9_4]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_107]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_105]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_103]], Acquire, 0) -// CHECK: affine.for %[[VAL_114:.*]] = 0 to 64 { -// CHECK: %[[VAL_115:.*]] = affine.load %[[VAL_108]]{{\[}}%[[VAL_114]]] : memref<64xi32, 2> -// CHECK: %[[VAL_116:.*]] = affine.load %[[VAL_106]]{{\[}}%[[VAL_114]]] : memref<64xi32, 2> -// CHECK: %[[VAL_117:.*]] = arith.muli %[[VAL_115]], %[[VAL_116]] : i32 -// CHECK: affine.store %[[VAL_117]], %[[VAL_104]]{{\[}}%[[VAL_114]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_9_4_11]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_9_4_10]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_9_4]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_33:.*]] = affine.load %[[BUF30]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_34:.*]] = affine.load %[[BUF31]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_35:.*]] = arith.muli %[[VAL_33]], %[[VAL_34]] : i32 +// CHECK: affine.store %[[VAL_35]], %[[BUF32]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_103]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_105]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_107]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_9_4]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_9_4_10]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_9_4_11]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_118:.*]] = aie.tile(27, 2) -// CHECK: %[[VAL_119:.*]] = aie.tile(27, 1) -// CHECK: %[[VAL_120:.*]] = aie.tile(27, 0) -// CHECK: %[[VAL_121:.*]] = aie.tile(1, 2) -// CHECK: %[[VAL_122:.*]] = aie.tile(8, 4) -// CHECK: %[[VAL_123:.*]] = aie.lock(%[[VAL_122]], 2) -// CHECK: %[[VAL_124:.*]] = aie.buffer(%[[VAL_122]]) {sym_name = "buf29"} : memref<64xi32, 2> -// CHECK: %[[VAL_125:.*]] = aie.lock(%[[VAL_122]], 1) -// CHECK: %[[VAL_126:.*]] = aie.buffer(%[[VAL_122]]) {sym_name = "buf28"} : memref<64xi32, 2> -// CHECK: %[[VAL_127:.*]] = aie.lock(%[[VAL_122]], 0) -// CHECK: %[[VAL_128:.*]] = aie.buffer(%[[VAL_122]]) {sym_name = "buf27"} : memref<64xi32, 2> -// CHECK: %[[VAL_129:.*]] = aie.mem(%[[VAL_122]]) { -// CHECK: %[[VAL_130:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_27_2:.*]] = aie.tile(27, 2) +// CHECK: %[[TILE_27_1:.*]] = aie.tile(27, 1) +// CHECK: %[[TILE_27_0:.*]] = aie.tile(27, 0) +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_8_4:.*]] = aie.tile(8, 4) +// CHECK: %[[LOCK_8_4:.*]] = aie.lock(%[[TILE_8_4]], 2) +// CHECK: %[[BUF29:.*]] = aie.buffer(%[[TILE_8_4]]) {sym_name = "buf29"} : memref<64xi32, 2> +// CHECK: %[[LOCK_8_4_12:.*]] = aie.lock(%[[TILE_8_4]], 1) +// CHECK: %[[BUF28:.*]] = aie.buffer(%[[TILE_8_4]]) {sym_name = "buf28"} : memref<64xi32, 2> +// CHECK: %[[LOCK_8_4_13:.*]] = aie.lock(%[[TILE_8_4]], 0) +// CHECK: %[[BUF27:.*]] = aie.buffer(%[[TILE_8_4]]) {sym_name = "buf27"} : memref<64xi32, 2> +// CHECK: %[[MEM_8_4:.*]] = aie.mem(%[[TILE_8_4]]) { +// CHECK: %[[VAL_36:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_127]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_128]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_127]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_4_13]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF27]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_8_4_13]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_131:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_37:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_125]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_126]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_125]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_4_12]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF28]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_8_4_12]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_132:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_38:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_123]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_124]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_123]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_4]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF29]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_8_4]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_133:.*]] = aie.core(%[[VAL_122]]) { +// CHECK: %[[CORE_8_4:.*]] = aie.core(%[[TILE_8_4]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_127]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_125]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_123]], Acquire, 0) -// CHECK: affine.for %[[VAL_134:.*]] = 0 to 64 { -// CHECK: %[[VAL_135:.*]] = affine.load %[[VAL_128]]{{\[}}%[[VAL_134]]] : memref<64xi32, 2> -// CHECK: %[[VAL_136:.*]] = affine.load %[[VAL_126]]{{\[}}%[[VAL_134]]] : memref<64xi32, 2> -// CHECK: %[[VAL_137:.*]] = arith.muli %[[VAL_135]], %[[VAL_136]] : i32 -// CHECK: affine.store %[[VAL_137]], %[[VAL_124]]{{\[}}%[[VAL_134]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_8_4_13]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_8_4_12]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_8_4]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_39:.*]] = affine.load %[[BUF27]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_40:.*]] = affine.load %[[BUF28]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_41:.*]] = arith.muli %[[VAL_39]], %[[VAL_40]] : i32 +// CHECK: affine.store %[[VAL_41]], %[[BUF29]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_123]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_125]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_127]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_4]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_4_12]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_4_13]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_138:.*]] = aie.tile(26, 2) -// CHECK: %[[VAL_139:.*]] = aie.tile(26, 1) -// CHECK: %[[VAL_140:.*]] = aie.tile(26, 0) -// CHECK: %[[VAL_141:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_142:.*]] = aie.tile(7, 4) -// CHECK: %[[VAL_143:.*]] = aie.lock(%[[VAL_142]], 2) -// CHECK: %[[VAL_144:.*]] = aie.buffer(%[[VAL_142]]) {sym_name = "buf26"} : memref<64xi32, 2> -// CHECK: %[[VAL_145:.*]] = aie.lock(%[[VAL_142]], 1) -// CHECK: %[[VAL_146:.*]] = aie.buffer(%[[VAL_142]]) {sym_name = "buf25"} : memref<64xi32, 2> -// CHECK: %[[VAL_147:.*]] = aie.lock(%[[VAL_142]], 0) -// CHECK: %[[VAL_148:.*]] = aie.buffer(%[[VAL_142]]) {sym_name = "buf24"} : memref<64xi32, 2> -// CHECK: %[[VAL_149:.*]] = aie.mem(%[[VAL_142]]) { -// CHECK: %[[VAL_150:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_26_2:.*]] = aie.tile(26, 2) +// CHECK: %[[TILE_26_1:.*]] = aie.tile(26, 1) +// CHECK: %[[TILE_26_0:.*]] = aie.tile(26, 0) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[TILE_7_4:.*]] = aie.tile(7, 4) +// CHECK: %[[LOCK_7_4:.*]] = aie.lock(%[[TILE_7_4]], 2) +// CHECK: %[[BUF26:.*]] = aie.buffer(%[[TILE_7_4]]) {sym_name = "buf26"} : memref<64xi32, 2> +// CHECK: %[[LOCK_7_4_14:.*]] = aie.lock(%[[TILE_7_4]], 1) +// CHECK: %[[BUF25:.*]] = aie.buffer(%[[TILE_7_4]]) {sym_name = "buf25"} : memref<64xi32, 2> +// CHECK: %[[LOCK_7_4_15:.*]] = aie.lock(%[[TILE_7_4]], 0) +// CHECK: %[[BUF24:.*]] = aie.buffer(%[[TILE_7_4]]) {sym_name = "buf24"} : memref<64xi32, 2> +// CHECK: %[[MEM_7_4:.*]] = aie.mem(%[[TILE_7_4]]) { +// CHECK: %[[VAL_42:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_147]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_148]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_147]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_4_15]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF24]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_7_4_15]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_151:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_43:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_145]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_146]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_145]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_4_14]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF25]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_7_4_14]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_152:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_44:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_143]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_144]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_143]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_4]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF26]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_7_4]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_153:.*]] = aie.core(%[[VAL_142]]) { +// CHECK: %[[CORE_7_4:.*]] = aie.core(%[[TILE_7_4]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_147]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_145]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_143]], Acquire, 0) -// CHECK: affine.for %[[VAL_154:.*]] = 0 to 64 { -// CHECK: %[[VAL_155:.*]] = affine.load %[[VAL_148]]{{\[}}%[[VAL_154]]] : memref<64xi32, 2> -// CHECK: %[[VAL_156:.*]] = affine.load %[[VAL_146]]{{\[}}%[[VAL_154]]] : memref<64xi32, 2> -// CHECK: %[[VAL_157:.*]] = arith.muli %[[VAL_155]], %[[VAL_156]] : i32 -// CHECK: affine.store %[[VAL_157]], %[[VAL_144]]{{\[}}%[[VAL_154]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_7_4_15]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_7_4_14]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_7_4]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_45:.*]] = affine.load %[[BUF24]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_46:.*]] = affine.load %[[BUF25]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_47:.*]] = arith.muli %[[VAL_45]], %[[VAL_46]] : i32 +// CHECK: affine.store %[[VAL_47]], %[[BUF26]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_143]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_145]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_147]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_4]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_4_14]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_4_15]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_158:.*]] = aie.tile(19, 2) -// CHECK: %[[VAL_159:.*]] = aie.tile(19, 1) -// CHECK: %[[VAL_160:.*]] = aie.tile(19, 0) -// CHECK: %[[VAL_161:.*]] = aie.tile(10, 3) -// CHECK: %[[VAL_162:.*]] = aie.lock(%[[VAL_161]], 2) -// CHECK: %[[VAL_163:.*]] = aie.buffer(%[[VAL_161]]) {sym_name = "buf23"} : memref<64xi32, 2> -// CHECK: %[[VAL_164:.*]] = aie.lock(%[[VAL_161]], 1) -// CHECK: %[[VAL_165:.*]] = aie.buffer(%[[VAL_161]]) {sym_name = "buf22"} : memref<64xi32, 2> -// CHECK: %[[VAL_166:.*]] = aie.lock(%[[VAL_161]], 0) -// CHECK: %[[VAL_167:.*]] = aie.buffer(%[[VAL_161]]) {sym_name = "buf21"} : memref<64xi32, 2> -// CHECK: %[[VAL_168:.*]] = aie.mem(%[[VAL_161]]) { -// CHECK: %[[VAL_169:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_19_2:.*]] = aie.tile(19, 2) +// CHECK: %[[TILE_19_1:.*]] = aie.tile(19, 1) +// CHECK: %[[TILE_19_0:.*]] = aie.tile(19, 0) +// CHECK: %[[TILE_10_3:.*]] = aie.tile(10, 3) +// CHECK: %[[LOCK_10_3:.*]] = aie.lock(%[[TILE_10_3]], 2) +// CHECK: %[[BUF23:.*]] = aie.buffer(%[[TILE_10_3]]) {sym_name = "buf23"} : memref<64xi32, 2> +// CHECK: %[[LOCK_10_3_16:.*]] = aie.lock(%[[TILE_10_3]], 1) +// CHECK: %[[BUF22:.*]] = aie.buffer(%[[TILE_10_3]]) {sym_name = "buf22"} : memref<64xi32, 2> +// CHECK: %[[LOCK_10_3_17:.*]] = aie.lock(%[[TILE_10_3]], 0) +// CHECK: %[[BUF21:.*]] = aie.buffer(%[[TILE_10_3]]) {sym_name = "buf21"} : memref<64xi32, 2> +// CHECK: %[[MEM_10_3:.*]] = aie.mem(%[[TILE_10_3]]) { +// CHECK: %[[VAL_48:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_166]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_167]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_166]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_10_3_17]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF21]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_10_3_17]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_170:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_49:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_164]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_165]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_164]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_10_3_16]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF22]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_10_3_16]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_171:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_50:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_162]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_163]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_162]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_10_3]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF23]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_10_3]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_172:.*]] = aie.core(%[[VAL_161]]) { +// CHECK: %[[CORE_10_3:.*]] = aie.core(%[[TILE_10_3]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_166]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_164]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_162]], Acquire, 0) -// CHECK: affine.for %[[VAL_173:.*]] = 0 to 64 { -// CHECK: %[[VAL_174:.*]] = affine.load %[[VAL_167]]{{\[}}%[[VAL_173]]] : memref<64xi32, 2> -// CHECK: %[[VAL_175:.*]] = affine.load %[[VAL_165]]{{\[}}%[[VAL_173]]] : memref<64xi32, 2> -// CHECK: %[[VAL_176:.*]] = arith.muli %[[VAL_174]], %[[VAL_175]] : i32 -// CHECK: affine.store %[[VAL_176]], %[[VAL_163]]{{\[}}%[[VAL_173]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_10_3_17]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_10_3_16]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_10_3]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_51:.*]] = affine.load %[[BUF21]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_52:.*]] = affine.load %[[BUF22]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_53:.*]] = arith.muli %[[VAL_51]], %[[VAL_52]] : i32 +// CHECK: affine.store %[[VAL_53]], %[[BUF23]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_162]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_164]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_166]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_10_3]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_10_3_16]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_10_3_17]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_177:.*]] = aie.tile(18, 2) -// CHECK: %[[VAL_178:.*]] = aie.tile(18, 1) -// CHECK: %[[VAL_179:.*]] = aie.tile(18, 0) -// CHECK: %[[VAL_180:.*]] = aie.tile(9, 3) -// CHECK: %[[VAL_181:.*]] = aie.lock(%[[VAL_180]], 2) -// CHECK: %[[VAL_182:.*]] = aie.buffer(%[[VAL_180]]) {sym_name = "buf20"} : memref<64xi32, 2> -// CHECK: %[[VAL_183:.*]] = aie.lock(%[[VAL_180]], 1) -// CHECK: %[[VAL_184:.*]] = aie.buffer(%[[VAL_180]]) {sym_name = "buf19"} : memref<64xi32, 2> -// CHECK: %[[VAL_185:.*]] = aie.lock(%[[VAL_180]], 0) -// CHECK: %[[VAL_186:.*]] = aie.buffer(%[[VAL_180]]) {sym_name = "buf18"} : memref<64xi32, 2> -// CHECK: %[[VAL_187:.*]] = aie.mem(%[[VAL_180]]) { -// CHECK: %[[VAL_188:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_18_2:.*]] = aie.tile(18, 2) +// CHECK: %[[TILE_18_1:.*]] = aie.tile(18, 1) +// CHECK: %[[TILE_18_0:.*]] = aie.tile(18, 0) +// CHECK: %[[TILE_9_3:.*]] = aie.tile(9, 3) +// CHECK: %[[LOCK_9_3:.*]] = aie.lock(%[[TILE_9_3]], 2) +// CHECK: %[[BUF20:.*]] = aie.buffer(%[[TILE_9_3]]) {sym_name = "buf20"} : memref<64xi32, 2> +// CHECK: %[[LOCK_9_3_18:.*]] = aie.lock(%[[TILE_9_3]], 1) +// CHECK: %[[BUF19:.*]] = aie.buffer(%[[TILE_9_3]]) {sym_name = "buf19"} : memref<64xi32, 2> +// CHECK: %[[LOCK_9_3_19:.*]] = aie.lock(%[[TILE_9_3]], 0) +// CHECK: %[[BUF18:.*]] = aie.buffer(%[[TILE_9_3]]) {sym_name = "buf18"} : memref<64xi32, 2> +// CHECK: %[[MEM_9_3:.*]] = aie.mem(%[[TILE_9_3]]) { +// CHECK: %[[VAL_54:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_185]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_186]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_185]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_9_3_19]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF18]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_9_3_19]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_189:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_55:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_183]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_184]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_183]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_9_3_18]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF19]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_9_3_18]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_190:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_56:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_181]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_182]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_181]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_9_3]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF20]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_9_3]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_191:.*]] = aie.core(%[[VAL_180]]) { +// CHECK: %[[CORE_9_3:.*]] = aie.core(%[[TILE_9_3]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_185]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_183]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_181]], Acquire, 0) -// CHECK: affine.for %[[VAL_192:.*]] = 0 to 64 { -// CHECK: %[[VAL_193:.*]] = affine.load %[[VAL_186]]{{\[}}%[[VAL_192]]] : memref<64xi32, 2> -// CHECK: %[[VAL_194:.*]] = affine.load %[[VAL_184]]{{\[}}%[[VAL_192]]] : memref<64xi32, 2> -// CHECK: %[[VAL_195:.*]] = arith.muli %[[VAL_193]], %[[VAL_194]] : i32 -// CHECK: affine.store %[[VAL_195]], %[[VAL_182]]{{\[}}%[[VAL_192]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_9_3_19]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_9_3_18]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_9_3]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_57:.*]] = affine.load %[[BUF18]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_58:.*]] = affine.load %[[BUF19]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_59:.*]] = arith.muli %[[VAL_57]], %[[VAL_58]] : i32 +// CHECK: affine.store %[[VAL_59]], %[[BUF20]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_181]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_183]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_185]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_9_3]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_9_3_18]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_9_3_19]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_196:.*]] = aie.tile(11, 2) -// CHECK: %[[VAL_197:.*]] = aie.tile(11, 1) -// CHECK: %[[VAL_198:.*]] = aie.tile(11, 0) -// CHECK: %[[VAL_199:.*]] = aie.tile(1, 1) -// CHECK: %[[VAL_200:.*]] = aie.tile(8, 3) -// CHECK: %[[VAL_201:.*]] = aie.lock(%[[VAL_200]], 2) -// CHECK: %[[VAL_202:.*]] = aie.buffer(%[[VAL_200]]) {sym_name = "buf17"} : memref<64xi32, 2> -// CHECK: %[[VAL_203:.*]] = aie.lock(%[[VAL_200]], 1) -// CHECK: %[[VAL_204:.*]] = aie.buffer(%[[VAL_200]]) {sym_name = "buf16"} : memref<64xi32, 2> -// CHECK: %[[VAL_205:.*]] = aie.lock(%[[VAL_200]], 0) -// CHECK: %[[VAL_206:.*]] = aie.buffer(%[[VAL_200]]) {sym_name = "buf15"} : memref<64xi32, 2> -// CHECK: %[[VAL_207:.*]] = aie.mem(%[[VAL_200]]) { -// CHECK: %[[VAL_208:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_11_2:.*]] = aie.tile(11, 2) +// CHECK: %[[TILE_11_1:.*]] = aie.tile(11, 1) +// CHECK: %[[TILE_11_0:.*]] = aie.tile(11, 0) +// CHECK: %[[TILE_1_1:.*]] = aie.tile(1, 1) +// CHECK: %[[TILE_8_3:.*]] = aie.tile(8, 3) +// CHECK: %[[LOCK_8_3:.*]] = aie.lock(%[[TILE_8_3]], 2) +// CHECK: %[[BUF17:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf17"} : memref<64xi32, 2> +// CHECK: %[[LOCK_8_3_20:.*]] = aie.lock(%[[TILE_8_3]], 1) +// CHECK: %[[BUF16:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf16"} : memref<64xi32, 2> +// CHECK: %[[LOCK_8_3_21:.*]] = aie.lock(%[[TILE_8_3]], 0) +// CHECK: %[[BUF15:.*]] = aie.buffer(%[[TILE_8_3]]) {sym_name = "buf15"} : memref<64xi32, 2> +// CHECK: %[[MEM_8_3:.*]] = aie.mem(%[[TILE_8_3]]) { +// CHECK: %[[VAL_60:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_205]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_206]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_205]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_3_21]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF15]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_8_3_21]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_209:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_61:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_203]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_204]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_203]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_3_20]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF16]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_8_3_20]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_210:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_62:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_201]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_202]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_201]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_3]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF17]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_8_3]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_211:.*]] = aie.core(%[[VAL_200]]) { +// CHECK: %[[CORE_8_3:.*]] = aie.core(%[[TILE_8_3]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_205]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_203]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_201]], Acquire, 0) -// CHECK: affine.for %[[VAL_212:.*]] = 0 to 64 { -// CHECK: %[[VAL_213:.*]] = affine.load %[[VAL_206]]{{\[}}%[[VAL_212]]] : memref<64xi32, 2> -// CHECK: %[[VAL_214:.*]] = affine.load %[[VAL_204]]{{\[}}%[[VAL_212]]] : memref<64xi32, 2> -// CHECK: %[[VAL_215:.*]] = arith.muli %[[VAL_213]], %[[VAL_214]] : i32 -// CHECK: affine.store %[[VAL_215]], %[[VAL_202]]{{\[}}%[[VAL_212]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_8_3_21]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_8_3_20]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_8_3]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_63:.*]] = affine.load %[[BUF15]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_64:.*]] = affine.load %[[BUF16]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_65:.*]] = arith.muli %[[VAL_63]], %[[VAL_64]] : i32 +// CHECK: affine.store %[[VAL_65]], %[[BUF17]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_201]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_203]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_205]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_3]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_3_20]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_3_21]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_216:.*]] = aie.tile(10, 1) -// CHECK: %[[VAL_217:.*]] = aie.tile(10, 0) -// CHECK: %[[VAL_218:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_219:.*]] = aie.tile(7, 3) -// CHECK: %[[VAL_220:.*]] = aie.lock(%[[VAL_219]], 2) -// CHECK: %[[VAL_221:.*]] = aie.buffer(%[[VAL_219]]) {sym_name = "buf14"} : memref<64xi32, 2> -// CHECK: %[[VAL_222:.*]] = aie.lock(%[[VAL_219]], 1) -// CHECK: %[[VAL_223:.*]] = aie.buffer(%[[VAL_219]]) {sym_name = "buf13"} : memref<64xi32, 2> -// CHECK: %[[VAL_224:.*]] = aie.lock(%[[VAL_219]], 0) -// CHECK: %[[VAL_225:.*]] = aie.buffer(%[[VAL_219]]) {sym_name = "buf12"} : memref<64xi32, 2> -// CHECK: %[[VAL_226:.*]] = aie.mem(%[[VAL_219]]) { -// CHECK: %[[VAL_227:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_10_1:.*]] = aie.tile(10, 1) +// CHECK: %[[TILE_10_0:.*]] = aie.tile(10, 0) +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_7_3:.*]] = aie.tile(7, 3) +// CHECK: %[[LOCK_7_3:.*]] = aie.lock(%[[TILE_7_3]], 2) +// CHECK: %[[BUF14:.*]] = aie.buffer(%[[TILE_7_3]]) {sym_name = "buf14"} : memref<64xi32, 2> +// CHECK: %[[LOCK_7_3_22:.*]] = aie.lock(%[[TILE_7_3]], 1) +// CHECK: %[[BUF13:.*]] = aie.buffer(%[[TILE_7_3]]) {sym_name = "buf13"} : memref<64xi32, 2> +// CHECK: %[[LOCK_7_3_23:.*]] = aie.lock(%[[TILE_7_3]], 0) +// CHECK: %[[BUF12:.*]] = aie.buffer(%[[TILE_7_3]]) {sym_name = "buf12"} : memref<64xi32, 2> +// CHECK: %[[MEM_7_3:.*]] = aie.mem(%[[TILE_7_3]]) { +// CHECK: %[[VAL_66:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_224]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_225]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_224]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_3_23]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF12]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_7_3_23]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_228:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_67:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_222]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_223]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_222]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_3_22]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF13]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_7_3_22]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_229:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_68:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_220]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_221]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_220]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_3]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF14]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_7_3]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_230:.*]] = aie.core(%[[VAL_219]]) { +// CHECK: %[[CORE_7_3:.*]] = aie.core(%[[TILE_7_3]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_224]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_222]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_220]], Acquire, 0) -// CHECK: affine.for %[[VAL_231:.*]] = 0 to 64 { -// CHECK: %[[VAL_232:.*]] = affine.load %[[VAL_225]]{{\[}}%[[VAL_231]]] : memref<64xi32, 2> -// CHECK: %[[VAL_233:.*]] = affine.load %[[VAL_223]]{{\[}}%[[VAL_231]]] : memref<64xi32, 2> -// CHECK: %[[VAL_234:.*]] = arith.muli %[[VAL_232]], %[[VAL_233]] : i32 -// CHECK: affine.store %[[VAL_234]], %[[VAL_221]]{{\[}}%[[VAL_231]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_7_3_23]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_7_3_22]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_7_3]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_69:.*]] = affine.load %[[BUF12]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_70:.*]] = affine.load %[[BUF13]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_71:.*]] = arith.muli %[[VAL_69]], %[[VAL_70]] : i32 +// CHECK: affine.store %[[VAL_71]], %[[BUF14]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_220]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_222]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_224]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_3]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_3_22]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_3_23]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_235:.*]] = aie.tile(7, 1) -// CHECK: %[[VAL_236:.*]] = aie.tile(7, 0) -// CHECK: %[[VAL_237:.*]] = aie.tile(10, 2) -// CHECK: %[[VAL_238:.*]] = aie.lock(%[[VAL_237]], 2) -// CHECK: %[[VAL_239:.*]] = aie.buffer(%[[VAL_237]]) {sym_name = "buf11"} : memref<64xi32, 2> -// CHECK: %[[VAL_240:.*]] = aie.lock(%[[VAL_237]], 1) -// CHECK: %[[VAL_241:.*]] = aie.buffer(%[[VAL_237]]) {sym_name = "buf10"} : memref<64xi32, 2> -// CHECK: %[[VAL_242:.*]] = aie.lock(%[[VAL_237]], 0) -// CHECK: %[[VAL_243:.*]] = aie.buffer(%[[VAL_237]]) {sym_name = "buf9"} : memref<64xi32, 2> -// CHECK: %[[VAL_244:.*]] = aie.mem(%[[VAL_237]]) { -// CHECK: %[[VAL_245:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_7_1:.*]] = aie.tile(7, 1) +// CHECK: %[[TILE_7_0:.*]] = aie.tile(7, 0) +// CHECK: %[[TILE_10_2:.*]] = aie.tile(10, 2) +// CHECK: %[[LOCK_10_2:.*]] = aie.lock(%[[TILE_10_2]], 2) +// CHECK: %[[BUF11:.*]] = aie.buffer(%[[TILE_10_2]]) {sym_name = "buf11"} : memref<64xi32, 2> +// CHECK: %[[LOCK_10_2_24:.*]] = aie.lock(%[[TILE_10_2]], 1) +// CHECK: %[[BUF10:.*]] = aie.buffer(%[[TILE_10_2]]) {sym_name = "buf10"} : memref<64xi32, 2> +// CHECK: %[[LOCK_10_2_25:.*]] = aie.lock(%[[TILE_10_2]], 0) +// CHECK: %[[BUF9:.*]] = aie.buffer(%[[TILE_10_2]]) {sym_name = "buf9"} : memref<64xi32, 2> +// CHECK: %[[MEM_10_2:.*]] = aie.mem(%[[TILE_10_2]]) { +// CHECK: %[[VAL_72:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_242]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_243]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_242]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_10_2_25]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF9]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_10_2_25]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_246:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_73:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_240]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_241]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_240]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_10_2_24]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF10]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_10_2_24]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_247:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_74:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_238]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_239]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_238]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_10_2]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF11]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_10_2]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_248:.*]] = aie.core(%[[VAL_237]]) { +// CHECK: %[[CORE_10_2:.*]] = aie.core(%[[TILE_10_2]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_242]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_240]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_238]], Acquire, 0) -// CHECK: affine.for %[[VAL_249:.*]] = 0 to 64 { -// CHECK: %[[VAL_250:.*]] = affine.load %[[VAL_243]]{{\[}}%[[VAL_249]]] : memref<64xi32, 2> -// CHECK: %[[VAL_251:.*]] = affine.load %[[VAL_241]]{{\[}}%[[VAL_249]]] : memref<64xi32, 2> -// CHECK: %[[VAL_252:.*]] = arith.muli %[[VAL_250]], %[[VAL_251]] : i32 -// CHECK: affine.store %[[VAL_252]], %[[VAL_239]]{{\[}}%[[VAL_249]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_10_2_25]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_10_2_24]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_10_2]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_75:.*]] = affine.load %[[BUF9]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_76:.*]] = affine.load %[[BUF10]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_77:.*]] = arith.muli %[[VAL_75]], %[[VAL_76]] : i32 +// CHECK: affine.store %[[VAL_77]], %[[BUF11]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_238]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_240]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_242]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_10_2]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_10_2_24]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_10_2_25]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_253:.*]] = aie.tile(6, 2) -// CHECK: %[[VAL_254:.*]] = aie.tile(6, 1) -// CHECK: %[[VAL_255:.*]] = aie.tile(6, 0) -// CHECK: %[[VAL_256:.*]] = aie.tile(9, 2) -// CHECK: %[[VAL_257:.*]] = aie.lock(%[[VAL_256]], 2) -// CHECK: %[[VAL_258:.*]] = aie.buffer(%[[VAL_256]]) {sym_name = "buf8"} : memref<64xi32, 2> -// CHECK: %[[VAL_259:.*]] = aie.lock(%[[VAL_256]], 1) -// CHECK: %[[VAL_260:.*]] = aie.buffer(%[[VAL_256]]) {sym_name = "buf7"} : memref<64xi32, 2> -// CHECK: %[[VAL_261:.*]] = aie.lock(%[[VAL_256]], 0) -// CHECK: %[[VAL_262:.*]] = aie.buffer(%[[VAL_256]]) {sym_name = "buf6"} : memref<64xi32, 2> -// CHECK: %[[VAL_263:.*]] = aie.mem(%[[VAL_256]]) { -// CHECK: %[[VAL_264:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_6_2:.*]] = aie.tile(6, 2) +// CHECK: %[[TILE_6_1:.*]] = aie.tile(6, 1) +// CHECK: %[[TILE_6_0:.*]] = aie.tile(6, 0) +// CHECK: %[[TILE_9_2:.*]] = aie.tile(9, 2) +// CHECK: %[[LOCK_9_2:.*]] = aie.lock(%[[TILE_9_2]], 2) +// CHECK: %[[BUF8:.*]] = aie.buffer(%[[TILE_9_2]]) {sym_name = "buf8"} : memref<64xi32, 2> +// CHECK: %[[LOCK_9_2_26:.*]] = aie.lock(%[[TILE_9_2]], 1) +// CHECK: %[[BUF7:.*]] = aie.buffer(%[[TILE_9_2]]) {sym_name = "buf7"} : memref<64xi32, 2> +// CHECK: %[[LOCK_9_2_27:.*]] = aie.lock(%[[TILE_9_2]], 0) +// CHECK: %[[BUF6:.*]] = aie.buffer(%[[TILE_9_2]]) {sym_name = "buf6"} : memref<64xi32, 2> +// CHECK: %[[MEM_9_2:.*]] = aie.mem(%[[TILE_9_2]]) { +// CHECK: %[[VAL_78:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_261]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_262]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_261]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_9_2_27]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF6]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_9_2_27]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_265:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_79:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_259]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_260]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_259]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_9_2_26]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF7]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_9_2_26]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_266:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_80:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_257]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_258]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_257]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_9_2]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF8]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_9_2]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_267:.*]] = aie.core(%[[VAL_256]]) { +// CHECK: %[[CORE_9_2:.*]] = aie.core(%[[TILE_9_2]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_261]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_259]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_257]], Acquire, 0) -// CHECK: affine.for %[[VAL_268:.*]] = 0 to 64 { -// CHECK: %[[VAL_269:.*]] = affine.load %[[VAL_262]]{{\[}}%[[VAL_268]]] : memref<64xi32, 2> -// CHECK: %[[VAL_270:.*]] = affine.load %[[VAL_260]]{{\[}}%[[VAL_268]]] : memref<64xi32, 2> -// CHECK: %[[VAL_271:.*]] = arith.muli %[[VAL_269]], %[[VAL_270]] : i32 -// CHECK: affine.store %[[VAL_271]], %[[VAL_258]]{{\[}}%[[VAL_268]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_9_2_27]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_9_2_26]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_9_2]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_81:.*]] = affine.load %[[BUF6]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_82:.*]] = affine.load %[[BUF7]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_83:.*]] = arith.muli %[[VAL_81]], %[[VAL_82]] : i32 +// CHECK: affine.store %[[VAL_83]], %[[BUF8]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_257]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_259]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_261]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_9_2]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_9_2_26]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_9_2_27]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_272:.*]] = aie.tile(3, 2) -// CHECK: %[[VAL_273:.*]] = aie.tile(3, 1) -// CHECK: %[[VAL_274:.*]] = aie.tile(3, 0) -// CHECK: %[[VAL_275:.*]] = aie.tile(1, 0) -// CHECK: %[[VAL_276:.*]] = aie.tile(8, 2) -// CHECK: %[[VAL_277:.*]] = aie.lock(%[[VAL_276]], 2) -// CHECK: %[[VAL_278:.*]] = aie.buffer(%[[VAL_276]]) {sym_name = "buf5"} : memref<64xi32, 2> -// CHECK: %[[VAL_279:.*]] = aie.lock(%[[VAL_276]], 1) -// CHECK: %[[VAL_280:.*]] = aie.buffer(%[[VAL_276]]) {sym_name = "buf4"} : memref<64xi32, 2> -// CHECK: %[[VAL_281:.*]] = aie.lock(%[[VAL_276]], 0) -// CHECK: %[[VAL_282:.*]] = aie.buffer(%[[VAL_276]]) {sym_name = "buf3"} : memref<64xi32, 2> -// CHECK: %[[VAL_283:.*]] = aie.mem(%[[VAL_276]]) { -// CHECK: %[[VAL_284:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_3_2:.*]] = aie.tile(3, 2) +// CHECK: %[[TILE_3_1:.*]] = aie.tile(3, 1) +// CHECK: %[[TILE_3_0:.*]] = aie.tile(3, 0) +// CHECK: %[[TILE_1_0:.*]] = aie.tile(1, 0) +// CHECK: %[[TILE_8_2:.*]] = aie.tile(8, 2) +// CHECK: %[[LOCK_8_2:.*]] = aie.lock(%[[TILE_8_2]], 2) +// CHECK: %[[BUF5:.*]] = aie.buffer(%[[TILE_8_2]]) {sym_name = "buf5"} : memref<64xi32, 2> +// CHECK: %[[LOCK_8_2_28:.*]] = aie.lock(%[[TILE_8_2]], 1) +// CHECK: %[[BUF4:.*]] = aie.buffer(%[[TILE_8_2]]) {sym_name = "buf4"} : memref<64xi32, 2> +// CHECK: %[[LOCK_8_2_29:.*]] = aie.lock(%[[TILE_8_2]], 0) +// CHECK: %[[BUF3:.*]] = aie.buffer(%[[TILE_8_2]]) {sym_name = "buf3"} : memref<64xi32, 2> +// CHECK: %[[MEM_8_2:.*]] = aie.mem(%[[TILE_8_2]]) { +// CHECK: %[[VAL_84:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_281]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_282]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_281]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_2_29]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF3]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_8_2_29]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_285:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_85:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_279]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_280]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_279]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_2_28]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF4]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_8_2_28]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_286:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_86:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_277]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_278]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_277]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_2]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF5]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_8_2]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_287:.*]] = aie.core(%[[VAL_276]]) { +// CHECK: %[[CORE_8_2:.*]] = aie.core(%[[TILE_8_2]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_281]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_279]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_277]], Acquire, 0) -// CHECK: affine.for %[[VAL_288:.*]] = 0 to 64 { -// CHECK: %[[VAL_289:.*]] = affine.load %[[VAL_282]]{{\[}}%[[VAL_288]]] : memref<64xi32, 2> -// CHECK: %[[VAL_290:.*]] = affine.load %[[VAL_280]]{{\[}}%[[VAL_288]]] : memref<64xi32, 2> -// CHECK: %[[VAL_291:.*]] = arith.muli %[[VAL_289]], %[[VAL_290]] : i32 -// CHECK: affine.store %[[VAL_291]], %[[VAL_278]]{{\[}}%[[VAL_288]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_8_2_29]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_8_2_28]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_8_2]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_87:.*]] = affine.load %[[BUF3]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_88:.*]] = affine.load %[[BUF4]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_89:.*]] = arith.muli %[[VAL_87]], %[[VAL_88]] : i32 +// CHECK: affine.store %[[VAL_89]], %[[BUF5]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_277]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_279]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_281]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_2]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_8_2_28]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_8_2_29]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_292:.*]] = aie.tile(2, 2) -// CHECK: %[[VAL_293:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_294:.*]] = aie.tile(2, 0) -// CHECK: %[[VAL_295:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_296:.*]] = aie.tile(7, 2) -// CHECK: %[[VAL_297:.*]] = aie.lock(%[[VAL_296]], 2) -// CHECK: %[[VAL_298:.*]] = aie.buffer(%[[VAL_296]]) {sym_name = "buf2"} : memref<64xi32, 2> -// CHECK: %[[VAL_299:.*]] = aie.lock(%[[VAL_296]], 1) -// CHECK: %[[VAL_300:.*]] = aie.buffer(%[[VAL_296]]) {sym_name = "buf1"} : memref<64xi32, 2> -// CHECK: %[[VAL_301:.*]] = aie.lock(%[[VAL_296]], 0) -// CHECK: %[[VAL_302:.*]] = aie.buffer(%[[VAL_296]]) {sym_name = "buf0"} : memref<64xi32, 2> -// CHECK: %[[VAL_303:.*]] = aie.mem(%[[VAL_296]]) { -// CHECK: %[[VAL_304:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) +// CHECK: %[[TILE_2_2:.*]] = aie.tile(2, 2) +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[TILE_2_0:.*]] = aie.tile(2, 0) +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_7_2:.*]] = aie.tile(7, 2) +// CHECK: %[[LOCK_7_2:.*]] = aie.lock(%[[TILE_7_2]], 2) +// CHECK: %[[BUF2:.*]] = aie.buffer(%[[TILE_7_2]]) {sym_name = "buf2"} : memref<64xi32, 2> +// CHECK: %[[LOCK_7_2_30:.*]] = aie.lock(%[[TILE_7_2]], 1) +// CHECK: %[[BUF1:.*]] = aie.buffer(%[[TILE_7_2]]) {sym_name = "buf1"} : memref<64xi32, 2> +// CHECK: %[[LOCK_7_2_31:.*]] = aie.lock(%[[TILE_7_2]], 0) +// CHECK: %[[BUF0:.*]] = aie.buffer(%[[TILE_7_2]]) {sym_name = "buf0"} : memref<64xi32, 2> +// CHECK: %[[MEM_7_2:.*]] = aie.mem(%[[TILE_7_2]]) { +// CHECK: %[[VAL_90:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb4) // CHECK: ^bb1: -// CHECK: aie.use_lock(%[[VAL_301]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_302]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_301]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_2_31]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF0]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_7_2_31]], Release, 1) // CHECK: aie.next_bd ^bb1 // CHECK: ^bb2: -// CHECK: %[[VAL_305:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) +// CHECK: %[[VAL_91:.*]] = aie.dma_start(S2MM, 1, ^bb3, ^bb6) // CHECK: ^bb3: -// CHECK: aie.use_lock(%[[VAL_299]], Acquire, 0) -// CHECK: aie.dma_bd(%[[VAL_300]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_299]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_2_30]], Acquire, 0) +// CHECK: aie.dma_bd(%[[BUF1]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_7_2_30]], Release, 1) // CHECK: aie.next_bd ^bb3 // CHECK: ^bb4: -// CHECK: %[[VAL_306:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) +// CHECK: %[[VAL_92:.*]] = aie.dma_start(MM2S, 0, ^bb5, ^bb2) // CHECK: ^bb5: -// CHECK: aie.use_lock(%[[VAL_297]], Acquire, 1) -// CHECK: aie.dma_bd(%[[VAL_298]] : memref<64xi32, 2>, 0, 64) -// CHECK: aie.use_lock(%[[VAL_297]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_2]], Acquire, 1) +// CHECK: aie.dma_bd(%[[BUF2]] : memref<64xi32, 2>, 0, 64) +// CHECK: aie.use_lock(%[[LOCK_7_2]], Release, 0) // CHECK: aie.next_bd ^bb5 // CHECK: ^bb6: // CHECK: aie.end // CHECK: } -// CHECK: %[[VAL_307:.*]] = aie.core(%[[VAL_296]]) { +// CHECK: %[[CORE_7_2:.*]] = aie.core(%[[TILE_7_2]]) { // CHECK: cf.br ^bb1 // CHECK: ^bb1: // CHECK: cf.br ^bb2 // CHECK: ^bb2: -// CHECK: aie.use_lock(%[[VAL_301]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_299]], Acquire, 1) -// CHECK: aie.use_lock(%[[VAL_297]], Acquire, 0) -// CHECK: affine.for %[[VAL_308:.*]] = 0 to 64 { -// CHECK: %[[VAL_309:.*]] = affine.load %[[VAL_302]]{{\[}}%[[VAL_308]]] : memref<64xi32, 2> -// CHECK: %[[VAL_310:.*]] = affine.load %[[VAL_300]]{{\[}}%[[VAL_308]]] : memref<64xi32, 2> -// CHECK: %[[VAL_311:.*]] = arith.muli %[[VAL_309]], %[[VAL_310]] : i32 -// CHECK: affine.store %[[VAL_311]], %[[VAL_298]]{{\[}}%[[VAL_308]]] : memref<64xi32, 2> +// CHECK: aie.use_lock(%[[LOCK_7_2_31]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_7_2_30]], Acquire, 1) +// CHECK: aie.use_lock(%[[LOCK_7_2]], Acquire, 0) +// CHECK: affine.for %[[ARG0:.*]] = 0 to 64 { +// CHECK: %[[VAL_93:.*]] = affine.load %[[BUF0]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_94:.*]] = affine.load %[[BUF1]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> +// CHECK: %[[VAL_95:.*]] = arith.muli %[[VAL_93]], %[[VAL_94]] : i32 +// CHECK: affine.store %[[VAL_95]], %[[BUF2]]{{\[}}%[[ARG0]]] : memref<64xi32, 2> // CHECK: } -// CHECK: aie.use_lock(%[[VAL_297]], Release, 1) -// CHECK: aie.use_lock(%[[VAL_299]], Release, 0) -// CHECK: aie.use_lock(%[[VAL_301]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_2]], Release, 1) +// CHECK: aie.use_lock(%[[LOCK_7_2_30]], Release, 0) +// CHECK: aie.use_lock(%[[LOCK_7_2_31]], Release, 0) // CHECK: cf.br ^bb1 // CHECK: } -// CHECK: %[[VAL_312:.*]] = aie.switchbox(%[[VAL_294]]) { +// CHECK: %[[SWITCHBOX_2_0:.*]] = aie.switchbox(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_313:.*]] = aie.shim_mux(%[[VAL_294]]) { +// CHECK: %[[SHIM_MUX_2_0:.*]] = aie.shim_mux(%[[TILE_2_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_314:.*]] = aie.switchbox(%[[VAL_293]]) { +// CHECK: %[[SWITCHBOX_2_1:.*]] = aie.switchbox(%[[TILE_2_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_315:.*]] = aie.switchbox(%[[VAL_292]]) { +// CHECK: %[[SWITCHBOX_2_2:.*]] = aie.switchbox(%[[TILE_2_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_316:.*]] = aie.switchbox(%[[VAL_272]]) { +// CHECK: %[[SWITCHBOX_3_2:.*]] = aie.switchbox(%[[TILE_3_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -899,8 +890,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_317:.*]] = aie.tile(4, 2) -// CHECK: %[[VAL_318:.*]] = aie.switchbox(%[[VAL_317]]) { +// CHECK: %[[TILE_4_2:.*]] = aie.tile(4, 2) +// CHECK: %[[SWITCHBOX_4_2:.*]] = aie.switchbox(%[[TILE_4_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -908,8 +899,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_319:.*]] = aie.tile(5, 2) -// CHECK: %[[VAL_320:.*]] = aie.switchbox(%[[VAL_319]]) { +// CHECK: %[[TILE_5_2:.*]] = aie.tile(5, 2) +// CHECK: %[[SWITCHBOX_5_2:.*]] = aie.switchbox(%[[TILE_5_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -917,7 +908,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_321:.*]] = aie.switchbox(%[[VAL_253]]) { +// CHECK: %[[SWITCHBOX_6_2:.*]] = aie.switchbox(%[[TILE_6_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -927,7 +918,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_322:.*]] = aie.switchbox(%[[VAL_296]]) { +// CHECK: %[[SWITCHBOX_7_2:.*]] = aie.switchbox(%[[TILE_7_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -939,29 +930,29 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_323:.*]] = aie.switchbox(%[[VAL_274]]) { +// CHECK: %[[SWITCHBOX_3_0:.*]] = aie.switchbox(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_324:.*]] = aie.shim_mux(%[[VAL_274]]) { +// CHECK: %[[SHIM_MUX_3_0:.*]] = aie.shim_mux(%[[TILE_3_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_325:.*]] = aie.tile(4, 0) -// CHECK: %[[VAL_326:.*]] = aie.switchbox(%[[VAL_325]]) { +// CHECK: %[[TILE_4_0:.*]] = aie.tile(4, 0) +// CHECK: %[[SWITCHBOX_4_0:.*]] = aie.switchbox(%[[TILE_4_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_327:.*]] = aie.tile(5, 0) -// CHECK: %[[VAL_328:.*]] = aie.switchbox(%[[VAL_327]]) { +// CHECK: %[[TILE_5_0:.*]] = aie.tile(5, 0) +// CHECK: %[[SWITCHBOX_5_0:.*]] = aie.switchbox(%[[TILE_5_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_329:.*]] = aie.switchbox(%[[VAL_255]]) { +// CHECK: %[[SWITCHBOX_6_0:.*]] = aie.switchbox(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -969,13 +960,13 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_330:.*]] = aie.switchbox(%[[VAL_254]]) { +// CHECK: %[[SWITCHBOX_6_1:.*]] = aie.switchbox(%[[TILE_6_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_331:.*]] = aie.switchbox(%[[VAL_276]]) { +// CHECK: %[[SWITCHBOX_8_2:.*]] = aie.switchbox(%[[TILE_8_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -987,13 +978,13 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_332:.*]] = aie.shim_mux(%[[VAL_255]]) { +// CHECK: %[[SHIM_MUX_6_0:.*]] = aie.shim_mux(%[[TILE_6_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_333:.*]] = aie.switchbox(%[[VAL_236]]) { +// CHECK: %[[SWITCHBOX_7_0:.*]] = aie.switchbox(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1001,15 +992,15 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_334:.*]] = aie.tile(8, 0) -// CHECK: %[[VAL_335:.*]] = aie.switchbox(%[[VAL_334]]) { +// CHECK: %[[TILE_8_0:.*]] = aie.tile(8, 0) +// CHECK: %[[SWITCHBOX_8_0:.*]] = aie.switchbox(%[[TILE_8_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_336:.*]] = aie.tile(9, 0) -// CHECK: %[[VAL_337:.*]] = aie.switchbox(%[[VAL_336]]) { +// CHECK: %[[TILE_9_0:.*]] = aie.tile(9, 0) +// CHECK: %[[SWITCHBOX_9_0:.*]] = aie.switchbox(%[[TILE_9_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1017,8 +1008,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_338:.*]] = aie.tile(9, 1) -// CHECK: %[[VAL_339:.*]] = aie.switchbox(%[[VAL_338]]) { +// CHECK: %[[TILE_9_1:.*]] = aie.tile(9, 1) +// CHECK: %[[SWITCHBOX_9_1:.*]] = aie.switchbox(%[[TILE_9_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1032,7 +1023,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_340:.*]] = aie.switchbox(%[[VAL_256]]) { +// CHECK: %[[SWITCHBOX_9_2:.*]] = aie.switchbox(%[[TILE_9_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1046,17 +1037,17 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_341:.*]] = aie.switchbox(%[[VAL_273]]) { +// CHECK: %[[SWITCHBOX_3_1:.*]] = aie.switchbox(%[[TILE_3_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_342:.*]] = aie.shim_mux(%[[VAL_236]]) { +// CHECK: %[[SHIM_MUX_7_0:.*]] = aie.shim_mux(%[[TILE_7_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_343:.*]] = aie.switchbox(%[[VAL_217]]) { +// CHECK: %[[SWITCHBOX_10_0:.*]] = aie.switchbox(%[[TILE_10_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1068,7 +1059,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_344:.*]] = aie.switchbox(%[[VAL_216]]) { +// CHECK: %[[SWITCHBOX_10_1:.*]] = aie.switchbox(%[[TILE_10_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1084,7 +1075,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_345:.*]] = aie.switchbox(%[[VAL_237]]) { +// CHECK: %[[SWITCHBOX_10_2:.*]] = aie.switchbox(%[[TILE_10_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1098,15 +1089,15 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_346:.*]] = aie.switchbox(%[[VAL_219]]) { +// CHECK: %[[SWITCHBOX_7_3:.*]] = aie.switchbox(%[[TILE_7_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_347:.*]] = aie.tile(8, 1) -// CHECK: %[[VAL_348:.*]] = aie.switchbox(%[[VAL_347]]) { +// CHECK: %[[TILE_8_1:.*]] = aie.tile(8, 1) +// CHECK: %[[SWITCHBOX_8_1:.*]] = aie.switchbox(%[[TILE_8_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1115,7 +1106,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_349:.*]] = aie.switchbox(%[[VAL_200]]) { +// CHECK: %[[SWITCHBOX_8_3:.*]] = aie.switchbox(%[[TILE_8_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1125,20 +1116,20 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_350:.*]] = aie.shim_mux(%[[VAL_217]]) { +// CHECK: %[[SHIM_MUX_10_0:.*]] = aie.shim_mux(%[[TILE_10_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_351:.*]] = aie.switchbox(%[[VAL_235]]) { +// CHECK: %[[SWITCHBOX_7_1:.*]] = aie.switchbox(%[[TILE_7_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_352:.*]] = aie.switchbox(%[[VAL_180]]) { +// CHECK: %[[SWITCHBOX_9_3:.*]] = aie.switchbox(%[[TILE_9_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1152,7 +1143,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_353:.*]] = aie.switchbox(%[[VAL_198]]) { +// CHECK: %[[SWITCHBOX_11_0:.*]] = aie.switchbox(%[[TILE_11_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1162,13 +1153,13 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_354:.*]] = aie.shim_mux(%[[VAL_198]]) { +// CHECK: %[[SHIM_MUX_11_0:.*]] = aie.shim_mux(%[[TILE_11_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_355:.*]] = aie.switchbox(%[[VAL_161]]) { +// CHECK: %[[SWITCHBOX_10_3:.*]] = aie.switchbox(%[[TILE_10_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1181,49 +1172,49 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_356:.*]] = aie.tile(12, 0) -// CHECK: %[[VAL_357:.*]] = aie.switchbox(%[[VAL_356]]) { +// CHECK: %[[TILE_12_0:.*]] = aie.tile(12, 0) +// CHECK: %[[SWITCHBOX_12_0:.*]] = aie.switchbox(%[[TILE_12_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_358:.*]] = aie.tile(13, 0) -// CHECK: %[[VAL_359:.*]] = aie.switchbox(%[[VAL_358]]) { +// CHECK: %[[TILE_13_0:.*]] = aie.tile(13, 0) +// CHECK: %[[SWITCHBOX_13_0:.*]] = aie.switchbox(%[[TILE_13_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_360:.*]] = aie.tile(14, 0) -// CHECK: %[[VAL_361:.*]] = aie.switchbox(%[[VAL_360]]) { +// CHECK: %[[TILE_14_0:.*]] = aie.tile(14, 0) +// CHECK: %[[SWITCHBOX_14_0:.*]] = aie.switchbox(%[[TILE_14_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_362:.*]] = aie.tile(15, 0) -// CHECK: %[[VAL_363:.*]] = aie.switchbox(%[[VAL_362]]) { +// CHECK: %[[TILE_15_0:.*]] = aie.tile(15, 0) +// CHECK: %[[SWITCHBOX_15_0:.*]] = aie.switchbox(%[[TILE_15_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_364:.*]] = aie.tile(16, 0) -// CHECK: %[[VAL_365:.*]] = aie.switchbox(%[[VAL_364]]) { +// CHECK: %[[TILE_16_0:.*]] = aie.tile(16, 0) +// CHECK: %[[SWITCHBOX_16_0:.*]] = aie.switchbox(%[[TILE_16_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_366:.*]] = aie.tile(17, 0) -// CHECK: %[[VAL_367:.*]] = aie.switchbox(%[[VAL_366]]) { +// CHECK: %[[TILE_17_0:.*]] = aie.tile(17, 0) +// CHECK: %[[SWITCHBOX_17_0:.*]] = aie.switchbox(%[[TILE_17_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_368:.*]] = aie.switchbox(%[[VAL_179]]) { +// CHECK: %[[SWITCHBOX_18_0:.*]] = aie.switchbox(%[[TILE_18_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1233,13 +1224,13 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_369:.*]] = aie.shim_mux(%[[VAL_179]]) { +// CHECK: %[[SHIM_MUX_18_0:.*]] = aie.shim_mux(%[[TILE_18_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_370:.*]] = aie.switchbox(%[[VAL_197]]) { +// CHECK: %[[SWITCHBOX_11_1:.*]] = aie.switchbox(%[[TILE_11_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1249,7 +1240,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_371:.*]] = aie.switchbox(%[[VAL_196]]) { +// CHECK: %[[SWITCHBOX_11_2:.*]] = aie.switchbox(%[[TILE_11_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1257,15 +1248,15 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_372:.*]] = aie.tile(11, 3) -// CHECK: %[[VAL_373:.*]] = aie.switchbox(%[[VAL_372]]) { +// CHECK: %[[TILE_11_3:.*]] = aie.tile(11, 3) +// CHECK: %[[SWITCHBOX_11_3:.*]] = aie.switchbox(%[[TILE_11_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_374:.*]] = aie.switchbox(%[[VAL_160]]) { +// CHECK: %[[SWITCHBOX_19_0:.*]] = aie.switchbox(%[[TILE_19_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1275,55 +1266,55 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_375:.*]] = aie.shim_mux(%[[VAL_160]]) { +// CHECK: %[[SHIM_MUX_19_0:.*]] = aie.shim_mux(%[[TILE_19_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_376:.*]] = aie.switchbox(%[[VAL_142]]) { +// CHECK: %[[SWITCHBOX_7_4:.*]] = aie.switchbox(%[[TILE_7_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_377:.*]] = aie.tile(12, 1) -// CHECK: %[[VAL_378:.*]] = aie.switchbox(%[[VAL_377]]) { +// CHECK: %[[TILE_12_1:.*]] = aie.tile(12, 1) +// CHECK: %[[SWITCHBOX_12_1:.*]] = aie.switchbox(%[[TILE_12_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_379:.*]] = aie.tile(13, 1) -// CHECK: %[[VAL_380:.*]] = aie.switchbox(%[[VAL_379]]) { +// CHECK: %[[TILE_13_1:.*]] = aie.tile(13, 1) +// CHECK: %[[SWITCHBOX_13_1:.*]] = aie.switchbox(%[[TILE_13_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_381:.*]] = aie.tile(14, 1) -// CHECK: %[[VAL_382:.*]] = aie.switchbox(%[[VAL_381]]) { +// CHECK: %[[TILE_14_1:.*]] = aie.tile(14, 1) +// CHECK: %[[SWITCHBOX_14_1:.*]] = aie.switchbox(%[[TILE_14_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_383:.*]] = aie.tile(15, 1) -// CHECK: %[[VAL_384:.*]] = aie.switchbox(%[[VAL_383]]) { +// CHECK: %[[TILE_15_1:.*]] = aie.tile(15, 1) +// CHECK: %[[SWITCHBOX_15_1:.*]] = aie.switchbox(%[[TILE_15_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_385:.*]] = aie.tile(16, 1) -// CHECK: %[[VAL_386:.*]] = aie.switchbox(%[[VAL_385]]) { +// CHECK: %[[TILE_16_1:.*]] = aie.tile(16, 1) +// CHECK: %[[SWITCHBOX_16_1:.*]] = aie.switchbox(%[[TILE_16_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_387:.*]] = aie.tile(17, 1) -// CHECK: %[[VAL_388:.*]] = aie.switchbox(%[[VAL_387]]) { +// CHECK: %[[TILE_17_1:.*]] = aie.tile(17, 1) +// CHECK: %[[SWITCHBOX_17_1:.*]] = aie.switchbox(%[[TILE_17_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1332,7 +1323,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_389:.*]] = aie.switchbox(%[[VAL_178]]) { +// CHECK: %[[SWITCHBOX_18_1:.*]] = aie.switchbox(%[[TILE_18_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1341,49 +1332,49 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_390:.*]] = aie.tile(20, 0) -// CHECK: %[[VAL_391:.*]] = aie.switchbox(%[[VAL_390]]) { +// CHECK: %[[TILE_20_0:.*]] = aie.tile(20, 0) +// CHECK: %[[SWITCHBOX_20_0:.*]] = aie.switchbox(%[[TILE_20_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_392:.*]] = aie.tile(21, 0) -// CHECK: %[[VAL_393:.*]] = aie.switchbox(%[[VAL_392]]) { +// CHECK: %[[TILE_21_0:.*]] = aie.tile(21, 0) +// CHECK: %[[SWITCHBOX_21_0:.*]] = aie.switchbox(%[[TILE_21_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_394:.*]] = aie.tile(22, 0) -// CHECK: %[[VAL_395:.*]] = aie.switchbox(%[[VAL_394]]) { +// CHECK: %[[TILE_22_0:.*]] = aie.tile(22, 0) +// CHECK: %[[SWITCHBOX_22_0:.*]] = aie.switchbox(%[[TILE_22_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_396:.*]] = aie.tile(23, 0) -// CHECK: %[[VAL_397:.*]] = aie.switchbox(%[[VAL_396]]) { +// CHECK: %[[TILE_23_0:.*]] = aie.tile(23, 0) +// CHECK: %[[SWITCHBOX_23_0:.*]] = aie.switchbox(%[[TILE_23_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_398:.*]] = aie.tile(24, 0) -// CHECK: %[[VAL_399:.*]] = aie.switchbox(%[[VAL_398]]) { +// CHECK: %[[TILE_24_0:.*]] = aie.tile(24, 0) +// CHECK: %[[SWITCHBOX_24_0:.*]] = aie.switchbox(%[[TILE_24_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_400:.*]] = aie.tile(25, 0) -// CHECK: %[[VAL_401:.*]] = aie.switchbox(%[[VAL_400]]) { +// CHECK: %[[TILE_25_0:.*]] = aie.tile(25, 0) +// CHECK: %[[SWITCHBOX_25_0:.*]] = aie.switchbox(%[[TILE_25_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_402:.*]] = aie.switchbox(%[[VAL_140]]) { +// CHECK: %[[SWITCHBOX_26_0:.*]] = aie.switchbox(%[[TILE_26_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1391,18 +1382,18 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_403:.*]] = aie.shim_mux(%[[VAL_140]]) { +// CHECK: %[[SHIM_MUX_26_0:.*]] = aie.shim_mux(%[[TILE_26_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_404:.*]] = aie.switchbox(%[[VAL_122]]) { +// CHECK: %[[SWITCHBOX_8_4:.*]] = aie.switchbox(%[[TILE_8_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_405:.*]] = aie.switchbox(%[[VAL_102]]) { +// CHECK: %[[SWITCHBOX_9_4:.*]] = aie.switchbox(%[[TILE_9_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1412,13 +1403,13 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_406:.*]] = aie.switchbox(%[[VAL_159]]) { +// CHECK: %[[SWITCHBOX_19_1:.*]] = aie.switchbox(%[[TILE_19_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_407:.*]] = aie.switchbox(%[[VAL_120]]) { +// CHECK: %[[SWITCHBOX_27_0:.*]] = aie.switchbox(%[[TILE_27_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1426,44 +1417,44 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_408:.*]] = aie.shim_mux(%[[VAL_120]]) { +// CHECK: %[[SHIM_MUX_27_0:.*]] = aie.shim_mux(%[[TILE_27_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_409:.*]] = aie.tile(12, 2) -// CHECK: %[[VAL_410:.*]] = aie.switchbox(%[[VAL_409]]) { +// CHECK: %[[TILE_12_2:.*]] = aie.tile(12, 2) +// CHECK: %[[SWITCHBOX_12_2:.*]] = aie.switchbox(%[[TILE_12_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_411:.*]] = aie.tile(13, 2) -// CHECK: %[[VAL_412:.*]] = aie.switchbox(%[[VAL_411]]) { +// CHECK: %[[TILE_13_2:.*]] = aie.tile(13, 2) +// CHECK: %[[SWITCHBOX_13_2:.*]] = aie.switchbox(%[[TILE_13_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_413:.*]] = aie.tile(14, 2) -// CHECK: %[[VAL_414:.*]] = aie.switchbox(%[[VAL_413]]) { +// CHECK: %[[TILE_14_2:.*]] = aie.tile(14, 2) +// CHECK: %[[SWITCHBOX_14_2:.*]] = aie.switchbox(%[[TILE_14_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_415:.*]] = aie.tile(15, 2) -// CHECK: %[[VAL_416:.*]] = aie.switchbox(%[[VAL_415]]) { +// CHECK: %[[TILE_15_2:.*]] = aie.tile(15, 2) +// CHECK: %[[SWITCHBOX_15_2:.*]] = aie.switchbox(%[[TILE_15_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_417:.*]] = aie.tile(16, 2) -// CHECK: %[[VAL_418:.*]] = aie.switchbox(%[[VAL_417]]) { +// CHECK: %[[TILE_16_2:.*]] = aie.tile(16, 2) +// CHECK: %[[SWITCHBOX_16_2:.*]] = aie.switchbox(%[[TILE_16_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_419:.*]] = aie.tile(17, 2) -// CHECK: %[[VAL_420:.*]] = aie.switchbox(%[[VAL_419]]) { +// CHECK: %[[TILE_17_2:.*]] = aie.tile(17, 2) +// CHECK: %[[SWITCHBOX_17_2:.*]] = aie.switchbox(%[[TILE_17_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1471,28 +1462,28 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_421:.*]] = aie.switchbox(%[[VAL_177]]) { +// CHECK: %[[SWITCHBOX_18_2:.*]] = aie.switchbox(%[[TILE_18_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_422:.*]] = aie.switchbox(%[[VAL_158]]) { +// CHECK: %[[SWITCHBOX_19_2:.*]] = aie.switchbox(%[[TILE_19_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_423:.*]] = aie.tile(20, 1) -// CHECK: %[[VAL_424:.*]] = aie.switchbox(%[[VAL_423]]) { +// CHECK: %[[TILE_20_1:.*]] = aie.tile(20, 1) +// CHECK: %[[SWITCHBOX_20_1:.*]] = aie.switchbox(%[[TILE_20_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_425:.*]] = aie.tile(20, 2) -// CHECK: %[[VAL_426:.*]] = aie.switchbox(%[[VAL_425]]) { +// CHECK: %[[TILE_20_2:.*]] = aie.tile(20, 2) +// CHECK: %[[SWITCHBOX_20_2:.*]] = aie.switchbox(%[[TILE_20_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1500,42 +1491,42 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_427:.*]] = aie.tile(21, 1) -// CHECK: %[[VAL_428:.*]] = aie.switchbox(%[[VAL_427]]) { +// CHECK: %[[TILE_21_1:.*]] = aie.tile(21, 1) +// CHECK: %[[SWITCHBOX_21_1:.*]] = aie.switchbox(%[[TILE_21_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_429:.*]] = aie.tile(22, 1) -// CHECK: %[[VAL_430:.*]] = aie.switchbox(%[[VAL_429]]) { +// CHECK: %[[TILE_22_1:.*]] = aie.tile(22, 1) +// CHECK: %[[SWITCHBOX_22_1:.*]] = aie.switchbox(%[[TILE_22_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_431:.*]] = aie.tile(23, 1) -// CHECK: %[[VAL_432:.*]] = aie.switchbox(%[[VAL_431]]) { +// CHECK: %[[TILE_23_1:.*]] = aie.tile(23, 1) +// CHECK: %[[SWITCHBOX_23_1:.*]] = aie.switchbox(%[[TILE_23_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_433:.*]] = aie.tile(24, 1) -// CHECK: %[[VAL_434:.*]] = aie.switchbox(%[[VAL_433]]) { +// CHECK: %[[TILE_24_1:.*]] = aie.tile(24, 1) +// CHECK: %[[SWITCHBOX_24_1:.*]] = aie.switchbox(%[[TILE_24_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_435:.*]] = aie.tile(25, 1) -// CHECK: %[[VAL_436:.*]] = aie.switchbox(%[[VAL_435]]) { +// CHECK: %[[TILE_25_1:.*]] = aie.tile(25, 1) +// CHECK: %[[SWITCHBOX_25_1:.*]] = aie.switchbox(%[[TILE_25_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_437:.*]] = aie.switchbox(%[[VAL_139]]) { +// CHECK: %[[SWITCHBOX_26_1:.*]] = aie.switchbox(%[[TILE_26_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1543,49 +1534,49 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_438:.*]] = aie.tile(28, 0) -// CHECK: %[[VAL_439:.*]] = aie.switchbox(%[[VAL_438]]) { +// CHECK: %[[TILE_28_0:.*]] = aie.tile(28, 0) +// CHECK: %[[SWITCHBOX_28_0:.*]] = aie.switchbox(%[[TILE_28_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_440:.*]] = aie.tile(29, 0) -// CHECK: %[[VAL_441:.*]] = aie.switchbox(%[[VAL_440]]) { +// CHECK: %[[TILE_29_0:.*]] = aie.tile(29, 0) +// CHECK: %[[SWITCHBOX_29_0:.*]] = aie.switchbox(%[[TILE_29_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_442:.*]] = aie.tile(30, 0) -// CHECK: %[[VAL_443:.*]] = aie.switchbox(%[[VAL_442]]) { +// CHECK: %[[TILE_30_0:.*]] = aie.tile(30, 0) +// CHECK: %[[SWITCHBOX_30_0:.*]] = aie.switchbox(%[[TILE_30_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_444:.*]] = aie.tile(31, 0) -// CHECK: %[[VAL_445:.*]] = aie.switchbox(%[[VAL_444]]) { +// CHECK: %[[TILE_31_0:.*]] = aie.tile(31, 0) +// CHECK: %[[SWITCHBOX_31_0:.*]] = aie.switchbox(%[[TILE_31_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_446:.*]] = aie.tile(32, 0) -// CHECK: %[[VAL_447:.*]] = aie.switchbox(%[[VAL_446]]) { +// CHECK: %[[TILE_32_0:.*]] = aie.tile(32, 0) +// CHECK: %[[SWITCHBOX_32_0:.*]] = aie.switchbox(%[[TILE_32_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_448:.*]] = aie.tile(33, 0) -// CHECK: %[[VAL_449:.*]] = aie.switchbox(%[[VAL_448]]) { +// CHECK: %[[TILE_33_0:.*]] = aie.tile(33, 0) +// CHECK: %[[SWITCHBOX_33_0:.*]] = aie.switchbox(%[[TILE_33_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_450:.*]] = aie.switchbox(%[[VAL_101]]) { +// CHECK: %[[SWITCHBOX_34_0:.*]] = aie.switchbox(%[[TILE_34_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1593,11 +1584,11 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_451:.*]] = aie.shim_mux(%[[VAL_101]]) { +// CHECK: %[[SHIM_MUX_34_0:.*]] = aie.shim_mux(%[[TILE_34_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_452:.*]] = aie.switchbox(%[[VAL_83]]) { +// CHECK: %[[SWITCHBOX_10_4:.*]] = aie.switchbox(%[[TILE_10_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1606,24 +1597,24 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_453:.*]] = aie.tile(12, 3) -// CHECK: %[[VAL_454:.*]] = aie.switchbox(%[[VAL_453]]) { +// CHECK: %[[TILE_12_3:.*]] = aie.tile(12, 3) +// CHECK: %[[SWITCHBOX_12_3:.*]] = aie.switchbox(%[[TILE_12_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_455:.*]] = aie.tile(13, 3) -// CHECK: %[[VAL_456:.*]] = aie.switchbox(%[[VAL_455]]) { +// CHECK: %[[TILE_13_3:.*]] = aie.tile(13, 3) +// CHECK: %[[SWITCHBOX_13_3:.*]] = aie.switchbox(%[[TILE_13_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_457:.*]] = aie.tile(14, 3) -// CHECK: %[[VAL_458:.*]] = aie.switchbox(%[[VAL_457]]) { +// CHECK: %[[TILE_14_3:.*]] = aie.tile(14, 3) +// CHECK: %[[SWITCHBOX_14_3:.*]] = aie.switchbox(%[[TILE_14_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_459:.*]] = aie.tile(15, 3) -// CHECK: %[[VAL_460:.*]] = aie.switchbox(%[[VAL_459]]) { +// CHECK: %[[TILE_15_3:.*]] = aie.tile(15, 3) +// CHECK: %[[SWITCHBOX_15_3:.*]] = aie.switchbox(%[[TILE_15_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1631,16 +1622,16 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_461:.*]] = aie.tile(16, 3) -// CHECK: %[[VAL_462:.*]] = aie.switchbox(%[[VAL_461]]) { +// CHECK: %[[TILE_16_3:.*]] = aie.tile(16, 3) +// CHECK: %[[SWITCHBOX_16_3:.*]] = aie.switchbox(%[[TILE_16_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_463:.*]] = aie.tile(17, 3) -// CHECK: %[[VAL_464:.*]] = aie.switchbox(%[[VAL_463]]) { +// CHECK: %[[TILE_17_3:.*]] = aie.tile(17, 3) +// CHECK: %[[SWITCHBOX_17_3:.*]] = aie.switchbox(%[[TILE_17_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1649,23 +1640,23 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_465:.*]] = aie.tile(18, 3) -// CHECK: %[[VAL_466:.*]] = aie.switchbox(%[[VAL_465]]) { +// CHECK: %[[TILE_18_3:.*]] = aie.tile(18, 3) +// CHECK: %[[SWITCHBOX_18_3:.*]] = aie.switchbox(%[[TILE_18_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_467:.*]] = aie.tile(19, 3) -// CHECK: %[[VAL_468:.*]] = aie.switchbox(%[[VAL_467]]) { +// CHECK: %[[TILE_19_3:.*]] = aie.tile(19, 3) +// CHECK: %[[SWITCHBOX_19_3:.*]] = aie.switchbox(%[[TILE_19_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_469:.*]] = aie.tile(20, 3) -// CHECK: %[[VAL_470:.*]] = aie.switchbox(%[[VAL_469]]) { +// CHECK: %[[TILE_20_3:.*]] = aie.tile(20, 3) +// CHECK: %[[SWITCHBOX_20_3:.*]] = aie.switchbox(%[[TILE_20_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1673,7 +1664,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_471:.*]] = aie.switchbox(%[[VAL_119]]) { +// CHECK: %[[SWITCHBOX_27_1:.*]] = aie.switchbox(%[[TILE_27_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1681,7 +1672,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_472:.*]] = aie.switchbox(%[[VAL_82]]) { +// CHECK: %[[SWITCHBOX_35_0:.*]] = aie.switchbox(%[[TILE_35_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1689,16 +1680,16 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_473:.*]] = aie.shim_mux(%[[VAL_82]]) { +// CHECK: %[[SHIM_MUX_35_0:.*]] = aie.shim_mux(%[[TILE_35_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_474:.*]] = aie.switchbox(%[[VAL_64]]) { +// CHECK: %[[SWITCHBOX_7_5:.*]] = aie.switchbox(%[[TILE_7_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_475:.*]] = aie.switchbox(%[[VAL_44]]) { +// CHECK: %[[SWITCHBOX_8_5:.*]] = aie.switchbox(%[[TILE_8_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1706,7 +1697,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_476:.*]] = aie.switchbox(%[[VAL_24]]) { +// CHECK: %[[SWITCHBOX_9_5:.*]] = aie.switchbox(%[[TILE_9_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1716,7 +1707,7 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_477:.*]] = aie.switchbox(%[[VAL_4]]) { +// CHECK: %[[SWITCHBOX_10_5:.*]] = aie.switchbox(%[[TILE_10_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1727,8 +1718,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_478:.*]] = aie.tile(11, 5) -// CHECK: %[[VAL_479:.*]] = aie.switchbox(%[[VAL_478]]) { +// CHECK: %[[TILE_11_5:.*]] = aie.tile(11, 5) +// CHECK: %[[SWITCHBOX_11_5:.*]] = aie.switchbox(%[[TILE_11_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1737,8 +1728,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_480:.*]] = aie.tile(12, 5) -// CHECK: %[[VAL_481:.*]] = aie.switchbox(%[[VAL_480]]) { +// CHECK: %[[TILE_12_5:.*]] = aie.tile(12, 5) +// CHECK: %[[SWITCHBOX_12_5:.*]] = aie.switchbox(%[[TILE_12_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1747,8 +1738,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_482:.*]] = aie.tile(13, 5) -// CHECK: %[[VAL_483:.*]] = aie.switchbox(%[[VAL_482]]) { +// CHECK: %[[TILE_13_5:.*]] = aie.tile(13, 5) +// CHECK: %[[SWITCHBOX_13_5:.*]] = aie.switchbox(%[[TILE_13_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1757,8 +1748,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_484:.*]] = aie.tile(14, 5) -// CHECK: %[[VAL_485:.*]] = aie.switchbox(%[[VAL_484]]) { +// CHECK: %[[TILE_14_5:.*]] = aie.tile(14, 5) +// CHECK: %[[SWITCHBOX_14_5:.*]] = aie.switchbox(%[[TILE_14_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1766,8 +1757,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_486:.*]] = aie.tile(15, 4) -// CHECK: %[[VAL_487:.*]] = aie.switchbox(%[[VAL_486]]) { +// CHECK: %[[TILE_15_4:.*]] = aie.tile(15, 4) +// CHECK: %[[SWITCHBOX_15_4:.*]] = aie.switchbox(%[[TILE_15_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1776,8 +1767,8 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_488:.*]] = aie.tile(15, 5) -// CHECK: %[[VAL_489:.*]] = aie.switchbox(%[[VAL_488]]) { +// CHECK: %[[TILE_15_5:.*]] = aie.tile(15, 5) +// CHECK: %[[SWITCHBOX_15_5:.*]] = aie.switchbox(%[[TILE_15_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1785,49 +1776,49 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_490:.*]] = aie.tile(21, 3) -// CHECK: %[[VAL_491:.*]] = aie.switchbox(%[[VAL_490]]) { +// CHECK: %[[TILE_21_3:.*]] = aie.tile(21, 3) +// CHECK: %[[SWITCHBOX_21_3:.*]] = aie.switchbox(%[[TILE_21_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_492:.*]] = aie.tile(22, 3) -// CHECK: %[[VAL_493:.*]] = aie.switchbox(%[[VAL_492]]) { +// CHECK: %[[TILE_22_3:.*]] = aie.tile(22, 3) +// CHECK: %[[SWITCHBOX_22_3:.*]] = aie.switchbox(%[[TILE_22_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_494:.*]] = aie.tile(23, 3) -// CHECK: %[[VAL_495:.*]] = aie.switchbox(%[[VAL_494]]) { +// CHECK: %[[TILE_23_3:.*]] = aie.tile(23, 3) +// CHECK: %[[SWITCHBOX_23_3:.*]] = aie.switchbox(%[[TILE_23_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_496:.*]] = aie.tile(24, 2) -// CHECK: %[[VAL_497:.*]] = aie.switchbox(%[[VAL_496]]) { +// CHECK: %[[TILE_24_2:.*]] = aie.tile(24, 2) +// CHECK: %[[SWITCHBOX_24_2:.*]] = aie.switchbox(%[[TILE_24_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_498:.*]] = aie.tile(24, 3) -// CHECK: %[[VAL_499:.*]] = aie.switchbox(%[[VAL_498]]) { +// CHECK: %[[TILE_24_3:.*]] = aie.tile(24, 3) +// CHECK: %[[SWITCHBOX_24_3:.*]] = aie.switchbox(%[[TILE_24_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_500:.*]] = aie.tile(25, 2) -// CHECK: %[[VAL_501:.*]] = aie.switchbox(%[[VAL_500]]) { +// CHECK: %[[TILE_25_2:.*]] = aie.tile(25, 2) +// CHECK: %[[SWITCHBOX_25_2:.*]] = aie.switchbox(%[[TILE_25_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_502:.*]] = aie.switchbox(%[[VAL_138]]) { +// CHECK: %[[SWITCHBOX_26_2:.*]] = aie.switchbox(%[[TILE_26_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1835,97 +1826,97 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_503:.*]] = aie.tile(28, 1) -// CHECK: %[[VAL_504:.*]] = aie.switchbox(%[[VAL_503]]) { +// CHECK: %[[TILE_28_1:.*]] = aie.tile(28, 1) +// CHECK: %[[SWITCHBOX_28_1:.*]] = aie.switchbox(%[[TILE_28_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_505:.*]] = aie.tile(29, 1) -// CHECK: %[[VAL_506:.*]] = aie.switchbox(%[[VAL_505]]) { +// CHECK: %[[TILE_29_1:.*]] = aie.tile(29, 1) +// CHECK: %[[SWITCHBOX_29_1:.*]] = aie.switchbox(%[[TILE_29_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_507:.*]] = aie.tile(30, 1) -// CHECK: %[[VAL_508:.*]] = aie.switchbox(%[[VAL_507]]) { +// CHECK: %[[TILE_30_1:.*]] = aie.tile(30, 1) +// CHECK: %[[SWITCHBOX_30_1:.*]] = aie.switchbox(%[[TILE_30_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_509:.*]] = aie.tile(31, 1) -// CHECK: %[[VAL_510:.*]] = aie.switchbox(%[[VAL_509]]) { +// CHECK: %[[TILE_31_1:.*]] = aie.tile(31, 1) +// CHECK: %[[SWITCHBOX_31_1:.*]] = aie.switchbox(%[[TILE_31_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_511:.*]] = aie.tile(32, 1) -// CHECK: %[[VAL_512:.*]] = aie.switchbox(%[[VAL_511]]) { +// CHECK: %[[TILE_32_1:.*]] = aie.tile(32, 1) +// CHECK: %[[SWITCHBOX_32_1:.*]] = aie.switchbox(%[[TILE_32_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_513:.*]] = aie.tile(33, 1) -// CHECK: %[[VAL_514:.*]] = aie.switchbox(%[[VAL_513]]) { +// CHECK: %[[TILE_33_1:.*]] = aie.tile(33, 1) +// CHECK: %[[SWITCHBOX_33_1:.*]] = aie.switchbox(%[[TILE_33_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_515:.*]] = aie.switchbox(%[[VAL_100]]) { +// CHECK: %[[SWITCHBOX_34_1:.*]] = aie.switchbox(%[[TILE_34_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_516:.*]] = aie.tile(36, 0) -// CHECK: %[[VAL_517:.*]] = aie.switchbox(%[[VAL_516]]) { +// CHECK: %[[TILE_36_0:.*]] = aie.tile(36, 0) +// CHECK: %[[SWITCHBOX_36_0:.*]] = aie.switchbox(%[[TILE_36_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_518:.*]] = aie.tile(37, 0) -// CHECK: %[[VAL_519:.*]] = aie.switchbox(%[[VAL_518]]) { +// CHECK: %[[TILE_37_0:.*]] = aie.tile(37, 0) +// CHECK: %[[SWITCHBOX_37_0:.*]] = aie.switchbox(%[[TILE_37_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_520:.*]] = aie.tile(38, 0) -// CHECK: %[[VAL_521:.*]] = aie.switchbox(%[[VAL_520]]) { +// CHECK: %[[TILE_38_0:.*]] = aie.tile(38, 0) +// CHECK: %[[SWITCHBOX_38_0:.*]] = aie.switchbox(%[[TILE_38_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_522:.*]] = aie.tile(39, 0) -// CHECK: %[[VAL_523:.*]] = aie.switchbox(%[[VAL_522]]) { +// CHECK: %[[TILE_39_0:.*]] = aie.tile(39, 0) +// CHECK: %[[SWITCHBOX_39_0:.*]] = aie.switchbox(%[[TILE_39_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_524:.*]] = aie.tile(40, 0) -// CHECK: %[[VAL_525:.*]] = aie.switchbox(%[[VAL_524]]) { +// CHECK: %[[TILE_40_0:.*]] = aie.tile(40, 0) +// CHECK: %[[SWITCHBOX_40_0:.*]] = aie.switchbox(%[[TILE_40_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_526:.*]] = aie.tile(41, 0) -// CHECK: %[[VAL_527:.*]] = aie.switchbox(%[[VAL_526]]) { +// CHECK: %[[TILE_41_0:.*]] = aie.tile(41, 0) +// CHECK: %[[SWITCHBOX_41_0:.*]] = aie.switchbox(%[[TILE_41_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_528:.*]] = aie.switchbox(%[[VAL_62]]) { +// CHECK: %[[SWITCHBOX_42_0:.*]] = aie.switchbox(%[[TILE_42_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect @@ -1933,1025 +1924,1025 @@ // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_529:.*]] = aie.shim_mux(%[[VAL_62]]) { +// CHECK: %[[SHIM_MUX_42_0:.*]] = aie.shim_mux(%[[TILE_42_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_530:.*]] = aie.tile(11, 4) -// CHECK: %[[VAL_531:.*]] = aie.switchbox(%[[VAL_530]]) { +// CHECK: %[[TILE_11_4:.*]] = aie.tile(11, 4) +// CHECK: %[[SWITCHBOX_11_4:.*]] = aie.switchbox(%[[TILE_11_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_532:.*]] = aie.tile(12, 4) -// CHECK: %[[VAL_533:.*]] = aie.switchbox(%[[VAL_532]]) { +// CHECK: %[[TILE_12_4:.*]] = aie.tile(12, 4) +// CHECK: %[[SWITCHBOX_12_4:.*]] = aie.switchbox(%[[TILE_12_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_534:.*]] = aie.tile(13, 4) -// CHECK: %[[VAL_535:.*]] = aie.switchbox(%[[VAL_534]]) { +// CHECK: %[[TILE_13_4:.*]] = aie.tile(13, 4) +// CHECK: %[[SWITCHBOX_13_4:.*]] = aie.switchbox(%[[TILE_13_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_536:.*]] = aie.tile(14, 4) -// CHECK: %[[VAL_537:.*]] = aie.switchbox(%[[VAL_536]]) { +// CHECK: %[[TILE_14_4:.*]] = aie.tile(14, 4) +// CHECK: %[[SWITCHBOX_14_4:.*]] = aie.switchbox(%[[TILE_14_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_538:.*]] = aie.tile(16, 4) -// CHECK: %[[VAL_539:.*]] = aie.switchbox(%[[VAL_538]]) { +// CHECK: %[[TILE_16_4:.*]] = aie.tile(16, 4) +// CHECK: %[[SWITCHBOX_16_4:.*]] = aie.switchbox(%[[TILE_16_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_540:.*]] = aie.tile(17, 4) -// CHECK: %[[VAL_541:.*]] = aie.switchbox(%[[VAL_540]]) { +// CHECK: %[[TILE_17_4:.*]] = aie.tile(17, 4) +// CHECK: %[[SWITCHBOX_17_4:.*]] = aie.switchbox(%[[TILE_17_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_542:.*]] = aie.tile(21, 2) -// CHECK: %[[VAL_543:.*]] = aie.switchbox(%[[VAL_542]]) { +// CHECK: %[[TILE_21_2:.*]] = aie.tile(21, 2) +// CHECK: %[[SWITCHBOX_21_2:.*]] = aie.switchbox(%[[TILE_21_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_544:.*]] = aie.tile(22, 2) -// CHECK: %[[VAL_545:.*]] = aie.switchbox(%[[VAL_544]]) { +// CHECK: %[[TILE_22_2:.*]] = aie.tile(22, 2) +// CHECK: %[[SWITCHBOX_22_2:.*]] = aie.switchbox(%[[TILE_22_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_546:.*]] = aie.tile(23, 2) -// CHECK: %[[VAL_547:.*]] = aie.switchbox(%[[VAL_546]]) { +// CHECK: %[[TILE_23_2:.*]] = aie.tile(23, 2) +// CHECK: %[[SWITCHBOX_23_2:.*]] = aie.switchbox(%[[TILE_23_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_548:.*]] = aie.switchbox(%[[VAL_118]]) { +// CHECK: %[[SWITCHBOX_27_2:.*]] = aie.switchbox(%[[TILE_27_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_549:.*]] = aie.switchbox(%[[VAL_81]]) { +// CHECK: %[[SWITCHBOX_35_1:.*]] = aie.switchbox(%[[TILE_35_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_550:.*]] = aie.switchbox(%[[VAL_42]]) { +// CHECK: %[[SWITCHBOX_43_0:.*]] = aie.switchbox(%[[TILE_43_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_551:.*]] = aie.shim_mux(%[[VAL_42]]) { +// CHECK: %[[SHIM_MUX_43_0:.*]] = aie.shim_mux(%[[TILE_43_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_552:.*]] = aie.tile(18, 4) -// CHECK: %[[VAL_553:.*]] = aie.switchbox(%[[VAL_552]]) { +// CHECK: %[[TILE_18_4:.*]] = aie.tile(18, 4) +// CHECK: %[[SWITCHBOX_18_4:.*]] = aie.switchbox(%[[TILE_18_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_554:.*]] = aie.tile(19, 4) -// CHECK: %[[VAL_555:.*]] = aie.switchbox(%[[VAL_554]]) { +// CHECK: %[[TILE_19_4:.*]] = aie.tile(19, 4) +// CHECK: %[[SWITCHBOX_19_4:.*]] = aie.switchbox(%[[TILE_19_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_556:.*]] = aie.tile(20, 4) -// CHECK: %[[VAL_557:.*]] = aie.switchbox(%[[VAL_556]]) { +// CHECK: %[[TILE_20_4:.*]] = aie.tile(20, 4) +// CHECK: %[[SWITCHBOX_20_4:.*]] = aie.switchbox(%[[TILE_20_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_558:.*]] = aie.tile(25, 3) -// CHECK: %[[VAL_559:.*]] = aie.switchbox(%[[VAL_558]]) { +// CHECK: %[[TILE_25_3:.*]] = aie.tile(25, 3) +// CHECK: %[[SWITCHBOX_25_3:.*]] = aie.switchbox(%[[TILE_25_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_560:.*]] = aie.tile(26, 3) -// CHECK: %[[VAL_561:.*]] = aie.switchbox(%[[VAL_560]]) { +// CHECK: %[[TILE_26_3:.*]] = aie.tile(26, 3) +// CHECK: %[[SWITCHBOX_26_3:.*]] = aie.switchbox(%[[TILE_26_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_562:.*]] = aie.tile(28, 2) -// CHECK: %[[VAL_563:.*]] = aie.switchbox(%[[VAL_562]]) { +// CHECK: %[[TILE_28_2:.*]] = aie.tile(28, 2) +// CHECK: %[[SWITCHBOX_28_2:.*]] = aie.switchbox(%[[TILE_28_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_564:.*]] = aie.tile(29, 2) -// CHECK: %[[VAL_565:.*]] = aie.switchbox(%[[VAL_564]]) { +// CHECK: %[[TILE_29_2:.*]] = aie.tile(29, 2) +// CHECK: %[[SWITCHBOX_29_2:.*]] = aie.switchbox(%[[TILE_29_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_566:.*]] = aie.tile(30, 2) -// CHECK: %[[VAL_567:.*]] = aie.switchbox(%[[VAL_566]]) { +// CHECK: %[[TILE_30_2:.*]] = aie.tile(30, 2) +// CHECK: %[[SWITCHBOX_30_2:.*]] = aie.switchbox(%[[TILE_30_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_568:.*]] = aie.tile(31, 2) -// CHECK: %[[VAL_569:.*]] = aie.switchbox(%[[VAL_568]]) { +// CHECK: %[[TILE_31_2:.*]] = aie.tile(31, 2) +// CHECK: %[[SWITCHBOX_31_2:.*]] = aie.switchbox(%[[TILE_31_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_570:.*]] = aie.tile(32, 2) -// CHECK: %[[VAL_571:.*]] = aie.switchbox(%[[VAL_570]]) { +// CHECK: %[[TILE_32_2:.*]] = aie.tile(32, 2) +// CHECK: %[[SWITCHBOX_32_2:.*]] = aie.switchbox(%[[TILE_32_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_572:.*]] = aie.tile(33, 2) -// CHECK: %[[VAL_573:.*]] = aie.switchbox(%[[VAL_572]]) { +// CHECK: %[[TILE_33_2:.*]] = aie.tile(33, 2) +// CHECK: %[[SWITCHBOX_33_2:.*]] = aie.switchbox(%[[TILE_33_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_574:.*]] = aie.switchbox(%[[VAL_99]]) { +// CHECK: %[[SWITCHBOX_34_2:.*]] = aie.switchbox(%[[TILE_34_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_575:.*]] = aie.switchbox(%[[VAL_80]]) { +// CHECK: %[[SWITCHBOX_35_2:.*]] = aie.switchbox(%[[TILE_35_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_576:.*]] = aie.tile(36, 2) -// CHECK: %[[VAL_577:.*]] = aie.switchbox(%[[VAL_576]]) { +// CHECK: %[[TILE_36_2:.*]] = aie.tile(36, 2) +// CHECK: %[[SWITCHBOX_36_2:.*]] = aie.switchbox(%[[TILE_36_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_578:.*]] = aie.tile(37, 2) -// CHECK: %[[VAL_579:.*]] = aie.switchbox(%[[VAL_578]]) { +// CHECK: %[[TILE_37_2:.*]] = aie.tile(37, 2) +// CHECK: %[[SWITCHBOX_37_2:.*]] = aie.switchbox(%[[TILE_37_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_580:.*]] = aie.tile(38, 2) -// CHECK: %[[VAL_581:.*]] = aie.switchbox(%[[VAL_580]]) { +// CHECK: %[[TILE_38_2:.*]] = aie.tile(38, 2) +// CHECK: %[[SWITCHBOX_38_2:.*]] = aie.switchbox(%[[TILE_38_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_582:.*]] = aie.tile(39, 2) -// CHECK: %[[VAL_583:.*]] = aie.switchbox(%[[VAL_582]]) { +// CHECK: %[[TILE_39_2:.*]] = aie.tile(39, 2) +// CHECK: %[[SWITCHBOX_39_2:.*]] = aie.switchbox(%[[TILE_39_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_584:.*]] = aie.tile(40, 2) -// CHECK: %[[VAL_585:.*]] = aie.switchbox(%[[VAL_584]]) { +// CHECK: %[[TILE_40_2:.*]] = aie.tile(40, 2) +// CHECK: %[[SWITCHBOX_40_2:.*]] = aie.switchbox(%[[TILE_40_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_586:.*]] = aie.tile(41, 1) -// CHECK: %[[VAL_587:.*]] = aie.switchbox(%[[VAL_586]]) { +// CHECK: %[[TILE_41_1:.*]] = aie.tile(41, 1) +// CHECK: %[[SWITCHBOX_41_1:.*]] = aie.switchbox(%[[TILE_41_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_588:.*]] = aie.tile(41, 2) -// CHECK: %[[VAL_589:.*]] = aie.switchbox(%[[VAL_588]]) { +// CHECK: %[[TILE_41_2:.*]] = aie.tile(41, 2) +// CHECK: %[[SWITCHBOX_41_2:.*]] = aie.switchbox(%[[TILE_41_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_590:.*]] = aie.switchbox(%[[VAL_61]]) { +// CHECK: %[[SWITCHBOX_42_1:.*]] = aie.switchbox(%[[TILE_42_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_591:.*]] = aie.tile(44, 0) -// CHECK: %[[VAL_592:.*]] = aie.switchbox(%[[VAL_591]]) { +// CHECK: %[[TILE_44_0:.*]] = aie.tile(44, 0) +// CHECK: %[[SWITCHBOX_44_0:.*]] = aie.switchbox(%[[TILE_44_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_593:.*]] = aie.tile(45, 0) -// CHECK: %[[VAL_594:.*]] = aie.switchbox(%[[VAL_593]]) { +// CHECK: %[[TILE_45_0:.*]] = aie.tile(45, 0) +// CHECK: %[[SWITCHBOX_45_0:.*]] = aie.switchbox(%[[TILE_45_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_595:.*]] = aie.switchbox(%[[VAL_22]]) { +// CHECK: %[[SWITCHBOX_46_0:.*]] = aie.switchbox(%[[TILE_46_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_596:.*]] = aie.shim_mux(%[[VAL_22]]) { +// CHECK: %[[SHIM_MUX_46_0:.*]] = aie.shim_mux(%[[TILE_46_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_597:.*]] = aie.tile(16, 5) -// CHECK: %[[VAL_598:.*]] = aie.switchbox(%[[VAL_597]]) { +// CHECK: %[[TILE_16_5:.*]] = aie.tile(16, 5) +// CHECK: %[[SWITCHBOX_16_5:.*]] = aie.switchbox(%[[TILE_16_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_599:.*]] = aie.tile(17, 5) -// CHECK: %[[VAL_600:.*]] = aie.switchbox(%[[VAL_599]]) { +// CHECK: %[[TILE_17_5:.*]] = aie.tile(17, 5) +// CHECK: %[[SWITCHBOX_17_5:.*]] = aie.switchbox(%[[TILE_17_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_601:.*]] = aie.tile(18, 5) -// CHECK: %[[VAL_602:.*]] = aie.switchbox(%[[VAL_601]]) { +// CHECK: %[[TILE_18_5:.*]] = aie.tile(18, 5) +// CHECK: %[[SWITCHBOX_18_5:.*]] = aie.switchbox(%[[TILE_18_5]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_603:.*]] = aie.tile(21, 4) -// CHECK: %[[VAL_604:.*]] = aie.switchbox(%[[VAL_603]]) { +// CHECK: %[[TILE_21_4:.*]] = aie.tile(21, 4) +// CHECK: %[[SWITCHBOX_21_4:.*]] = aie.switchbox(%[[TILE_21_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_605:.*]] = aie.tile(22, 4) -// CHECK: %[[VAL_606:.*]] = aie.switchbox(%[[VAL_605]]) { +// CHECK: %[[TILE_22_4:.*]] = aie.tile(22, 4) +// CHECK: %[[SWITCHBOX_22_4:.*]] = aie.switchbox(%[[TILE_22_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_607:.*]] = aie.tile(23, 4) -// CHECK: %[[VAL_608:.*]] = aie.switchbox(%[[VAL_607]]) { +// CHECK: %[[TILE_23_4:.*]] = aie.tile(23, 4) +// CHECK: %[[SWITCHBOX_23_4:.*]] = aie.switchbox(%[[TILE_23_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_609:.*]] = aie.tile(24, 4) -// CHECK: %[[VAL_610:.*]] = aie.switchbox(%[[VAL_609]]) { +// CHECK: %[[TILE_24_4:.*]] = aie.tile(24, 4) +// CHECK: %[[SWITCHBOX_24_4:.*]] = aie.switchbox(%[[TILE_24_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_611:.*]] = aie.tile(25, 4) -// CHECK: %[[VAL_612:.*]] = aie.switchbox(%[[VAL_611]]) { +// CHECK: %[[TILE_25_4:.*]] = aie.tile(25, 4) +// CHECK: %[[SWITCHBOX_25_4:.*]] = aie.switchbox(%[[TILE_25_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_613:.*]] = aie.tile(26, 4) -// CHECK: %[[VAL_614:.*]] = aie.switchbox(%[[VAL_613]]) { +// CHECK: %[[TILE_26_4:.*]] = aie.tile(26, 4) +// CHECK: %[[SWITCHBOX_26_4:.*]] = aie.switchbox(%[[TILE_26_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_615:.*]] = aie.tile(27, 4) -// CHECK: %[[VAL_616:.*]] = aie.switchbox(%[[VAL_615]]) { +// CHECK: %[[TILE_27_4:.*]] = aie.tile(27, 4) +// CHECK: %[[SWITCHBOX_27_4:.*]] = aie.switchbox(%[[TILE_27_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_617:.*]] = aie.tile(28, 4) -// CHECK: %[[VAL_618:.*]] = aie.switchbox(%[[VAL_617]]) { +// CHECK: %[[TILE_28_4:.*]] = aie.tile(28, 4) +// CHECK: %[[SWITCHBOX_28_4:.*]] = aie.switchbox(%[[TILE_28_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_619:.*]] = aie.tile(29, 4) -// CHECK: %[[VAL_620:.*]] = aie.switchbox(%[[VAL_619]]) { +// CHECK: %[[TILE_29_4:.*]] = aie.tile(29, 4) +// CHECK: %[[SWITCHBOX_29_4:.*]] = aie.switchbox(%[[TILE_29_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_621:.*]] = aie.tile(30, 4) -// CHECK: %[[VAL_622:.*]] = aie.switchbox(%[[VAL_621]]) { +// CHECK: %[[TILE_30_4:.*]] = aie.tile(30, 4) +// CHECK: %[[SWITCHBOX_30_4:.*]] = aie.switchbox(%[[TILE_30_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_623:.*]] = aie.tile(31, 4) -// CHECK: %[[VAL_624:.*]] = aie.switchbox(%[[VAL_623]]) { +// CHECK: %[[TILE_31_4:.*]] = aie.tile(31, 4) +// CHECK: %[[SWITCHBOX_31_4:.*]] = aie.switchbox(%[[TILE_31_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_625:.*]] = aie.tile(32, 4) -// CHECK: %[[VAL_626:.*]] = aie.switchbox(%[[VAL_625]]) { +// CHECK: %[[TILE_32_4:.*]] = aie.tile(32, 4) +// CHECK: %[[SWITCHBOX_32_4:.*]] = aie.switchbox(%[[TILE_32_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_627:.*]] = aie.tile(33, 4) -// CHECK: %[[VAL_628:.*]] = aie.switchbox(%[[VAL_627]]) { +// CHECK: %[[TILE_33_4:.*]] = aie.tile(33, 4) +// CHECK: %[[SWITCHBOX_33_4:.*]] = aie.switchbox(%[[TILE_33_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_629:.*]] = aie.tile(34, 4) -// CHECK: %[[VAL_630:.*]] = aie.switchbox(%[[VAL_629]]) { +// CHECK: %[[TILE_34_4:.*]] = aie.tile(34, 4) +// CHECK: %[[SWITCHBOX_34_4:.*]] = aie.switchbox(%[[TILE_34_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_631:.*]] = aie.tile(35, 4) -// CHECK: %[[VAL_632:.*]] = aie.switchbox(%[[VAL_631]]) { +// CHECK: %[[TILE_35_4:.*]] = aie.tile(35, 4) +// CHECK: %[[SWITCHBOX_35_4:.*]] = aie.switchbox(%[[TILE_35_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_633:.*]] = aie.tile(36, 4) -// CHECK: %[[VAL_634:.*]] = aie.switchbox(%[[VAL_633]]) { +// CHECK: %[[TILE_36_4:.*]] = aie.tile(36, 4) +// CHECK: %[[SWITCHBOX_36_4:.*]] = aie.switchbox(%[[TILE_36_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_635:.*]] = aie.tile(37, 4) -// CHECK: %[[VAL_636:.*]] = aie.switchbox(%[[VAL_635]]) { +// CHECK: %[[TILE_37_4:.*]] = aie.tile(37, 4) +// CHECK: %[[SWITCHBOX_37_4:.*]] = aie.switchbox(%[[TILE_37_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_637:.*]] = aie.tile(38, 4) -// CHECK: %[[VAL_638:.*]] = aie.switchbox(%[[VAL_637]]) { +// CHECK: %[[TILE_38_4:.*]] = aie.tile(38, 4) +// CHECK: %[[SWITCHBOX_38_4:.*]] = aie.switchbox(%[[TILE_38_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_639:.*]] = aie.tile(39, 4) -// CHECK: %[[VAL_640:.*]] = aie.switchbox(%[[VAL_639]]) { +// CHECK: %[[TILE_39_4:.*]] = aie.tile(39, 4) +// CHECK: %[[SWITCHBOX_39_4:.*]] = aie.switchbox(%[[TILE_39_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_641:.*]] = aie.tile(40, 4) -// CHECK: %[[VAL_642:.*]] = aie.switchbox(%[[VAL_641]]) { +// CHECK: %[[TILE_40_4:.*]] = aie.tile(40, 4) +// CHECK: %[[SWITCHBOX_40_4:.*]] = aie.switchbox(%[[TILE_40_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_643:.*]] = aie.tile(41, 4) -// CHECK: %[[VAL_644:.*]] = aie.switchbox(%[[VAL_643]]) { +// CHECK: %[[TILE_41_4:.*]] = aie.tile(41, 4) +// CHECK: %[[SWITCHBOX_41_4:.*]] = aie.switchbox(%[[TILE_41_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_645:.*]] = aie.tile(42, 3) -// CHECK: %[[VAL_646:.*]] = aie.switchbox(%[[VAL_645]]) { +// CHECK: %[[TILE_42_3:.*]] = aie.tile(42, 3) +// CHECK: %[[SWITCHBOX_42_3:.*]] = aie.switchbox(%[[TILE_42_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_647:.*]] = aie.tile(42, 4) -// CHECK: %[[VAL_648:.*]] = aie.switchbox(%[[VAL_647]]) { +// CHECK: %[[TILE_42_4:.*]] = aie.tile(42, 4) +// CHECK: %[[SWITCHBOX_42_4:.*]] = aie.switchbox(%[[TILE_42_4]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_649:.*]] = aie.tile(43, 3) -// CHECK: %[[VAL_650:.*]] = aie.switchbox(%[[VAL_649]]) { +// CHECK: %[[TILE_43_3:.*]] = aie.tile(43, 3) +// CHECK: %[[SWITCHBOX_43_3:.*]] = aie.switchbox(%[[TILE_43_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_651:.*]] = aie.tile(44, 3) -// CHECK: %[[VAL_652:.*]] = aie.switchbox(%[[VAL_651]]) { +// CHECK: %[[TILE_44_3:.*]] = aie.tile(44, 3) +// CHECK: %[[SWITCHBOX_44_3:.*]] = aie.switchbox(%[[TILE_44_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_653:.*]] = aie.tile(45, 2) -// CHECK: %[[VAL_654:.*]] = aie.switchbox(%[[VAL_653]]) { +// CHECK: %[[TILE_45_2:.*]] = aie.tile(45, 2) +// CHECK: %[[SWITCHBOX_45_2:.*]] = aie.switchbox(%[[TILE_45_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_655:.*]] = aie.tile(45, 3) -// CHECK: %[[VAL_656:.*]] = aie.switchbox(%[[VAL_655]]) { +// CHECK: %[[TILE_45_3:.*]] = aie.tile(45, 3) +// CHECK: %[[SWITCHBOX_45_3:.*]] = aie.switchbox(%[[TILE_45_3]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_657:.*]] = aie.switchbox(%[[VAL_21]]) { +// CHECK: %[[SWITCHBOX_46_1:.*]] = aie.switchbox(%[[TILE_46_1]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_658:.*]] = aie.switchbox(%[[VAL_20]]) { +// CHECK: %[[SWITCHBOX_46_2:.*]] = aie.switchbox(%[[TILE_46_2]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_659:.*]] = aie.switchbox(%[[VAL_2]]) { +// CHECK: %[[SWITCHBOX_47_0:.*]] = aie.switchbox(%[[TILE_47_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: %[[VAL_660:.*]] = aie.shim_mux(%[[VAL_2]]) { +// CHECK: %[[SHIM_MUX_47_0:.*]] = aie.shim_mux(%[[TILE_47_0]]) { // CHECK: aie.connect // CHECK: aie.connect // CHECK: } -// CHECK: aie.wire(%[[VAL_661:.*]] : North, %[[VAL_662:.*]] : South) -// CHECK: aie.wire(%[[VAL_294]] : DMA, %[[VAL_661]] : DMA) -// CHECK: aie.wire(%[[VAL_293]] : Core, %[[VAL_663:.*]] : Core) -// CHECK: aie.wire(%[[VAL_293]] : DMA, %[[VAL_663]] : DMA) -// CHECK: aie.wire(%[[VAL_662]] : North, %[[VAL_663]] : South) -// CHECK: aie.wire(%[[VAL_292]] : Core, %[[VAL_664:.*]] : Core) -// CHECK: aie.wire(%[[VAL_292]] : DMA, %[[VAL_664]] : DMA) -// CHECK: aie.wire(%[[VAL_663]] : North, %[[VAL_664]] : South) -// CHECK: aie.wire(%[[VAL_662]] : East, %[[VAL_665:.*]] : West) -// CHECK: aie.wire(%[[VAL_666:.*]] : North, %[[VAL_665]] : South) -// CHECK: aie.wire(%[[VAL_274]] : DMA, %[[VAL_666]] : DMA) -// CHECK: aie.wire(%[[VAL_663]] : East, %[[VAL_667:.*]] : West) -// CHECK: aie.wire(%[[VAL_273]] : Core, %[[VAL_667]] : Core) -// CHECK: aie.wire(%[[VAL_273]] : DMA, %[[VAL_667]] : DMA) -// CHECK: aie.wire(%[[VAL_665]] : North, %[[VAL_667]] : South) -// CHECK: aie.wire(%[[VAL_664]] : East, %[[VAL_668:.*]] : West) -// CHECK: aie.wire(%[[VAL_272]] : Core, %[[VAL_668]] : Core) -// CHECK: aie.wire(%[[VAL_272]] : DMA, %[[VAL_668]] : DMA) -// CHECK: aie.wire(%[[VAL_667]] : North, %[[VAL_668]] : South) -// CHECK: aie.wire(%[[VAL_665]] : East, %[[VAL_669:.*]] : West) -// CHECK: aie.wire(%[[VAL_668]] : East, %[[VAL_670:.*]] : West) -// CHECK: aie.wire(%[[VAL_317]] : Core, %[[VAL_670]] : Core) -// CHECK: aie.wire(%[[VAL_317]] : DMA, %[[VAL_670]] : DMA) -// CHECK: aie.wire(%[[VAL_669]] : East, %[[VAL_671:.*]] : West) -// CHECK: aie.wire(%[[VAL_670]] : East, %[[VAL_672:.*]] : West) -// CHECK: aie.wire(%[[VAL_319]] : Core, %[[VAL_672]] : Core) -// CHECK: aie.wire(%[[VAL_319]] : DMA, %[[VAL_672]] : DMA) -// CHECK: aie.wire(%[[VAL_671]] : East, %[[VAL_673:.*]] : West) -// CHECK: aie.wire(%[[VAL_674:.*]] : North, %[[VAL_673]] : South) -// CHECK: aie.wire(%[[VAL_255]] : DMA, %[[VAL_674]] : DMA) -// CHECK: aie.wire(%[[VAL_254]] : Core, %[[VAL_675:.*]] : Core) -// CHECK: aie.wire(%[[VAL_254]] : DMA, %[[VAL_675]] : DMA) -// CHECK: aie.wire(%[[VAL_673]] : North, %[[VAL_675]] : South) -// CHECK: aie.wire(%[[VAL_672]] : East, %[[VAL_676:.*]] : West) -// CHECK: aie.wire(%[[VAL_253]] : Core, %[[VAL_676]] : Core) -// CHECK: aie.wire(%[[VAL_253]] : DMA, %[[VAL_676]] : DMA) -// CHECK: aie.wire(%[[VAL_675]] : North, %[[VAL_676]] : South) -// CHECK: aie.wire(%[[VAL_673]] : East, %[[VAL_677:.*]] : West) -// CHECK: aie.wire(%[[VAL_678:.*]] : North, %[[VAL_677]] : South) -// CHECK: aie.wire(%[[VAL_236]] : DMA, %[[VAL_678]] : DMA) -// CHECK: aie.wire(%[[VAL_675]] : East, %[[VAL_679:.*]] : West) -// CHECK: aie.wire(%[[VAL_235]] : Core, %[[VAL_679]] : Core) -// CHECK: aie.wire(%[[VAL_235]] : DMA, %[[VAL_679]] : DMA) -// CHECK: aie.wire(%[[VAL_677]] : North, %[[VAL_679]] : South) -// CHECK: aie.wire(%[[VAL_676]] : East, %[[VAL_680:.*]] : West) -// CHECK: aie.wire(%[[VAL_296]] : Core, %[[VAL_680]] : Core) -// CHECK: aie.wire(%[[VAL_296]] : DMA, %[[VAL_680]] : DMA) -// CHECK: aie.wire(%[[VAL_679]] : North, %[[VAL_680]] : South) -// CHECK: aie.wire(%[[VAL_219]] : Core, %[[VAL_681:.*]] : Core) -// CHECK: aie.wire(%[[VAL_219]] : DMA, %[[VAL_681]] : DMA) -// CHECK: aie.wire(%[[VAL_680]] : North, %[[VAL_681]] : South) -// CHECK: aie.wire(%[[VAL_142]] : Core, %[[VAL_682:.*]] : Core) -// CHECK: aie.wire(%[[VAL_142]] : DMA, %[[VAL_682]] : DMA) -// CHECK: aie.wire(%[[VAL_681]] : North, %[[VAL_682]] : South) -// CHECK: aie.wire(%[[VAL_64]] : Core, %[[VAL_683:.*]] : Core) -// CHECK: aie.wire(%[[VAL_64]] : DMA, %[[VAL_683]] : DMA) -// CHECK: aie.wire(%[[VAL_682]] : North, %[[VAL_683]] : South) -// CHECK: aie.wire(%[[VAL_677]] : East, %[[VAL_684:.*]] : West) -// CHECK: aie.wire(%[[VAL_679]] : East, %[[VAL_685:.*]] : West) -// CHECK: aie.wire(%[[VAL_347]] : Core, %[[VAL_685]] : Core) -// CHECK: aie.wire(%[[VAL_347]] : DMA, %[[VAL_685]] : DMA) -// CHECK: aie.wire(%[[VAL_684]] : North, %[[VAL_685]] : South) -// CHECK: aie.wire(%[[VAL_680]] : East, %[[VAL_686:.*]] : West) -// CHECK: aie.wire(%[[VAL_276]] : Core, %[[VAL_686]] : Core) -// CHECK: aie.wire(%[[VAL_276]] : DMA, %[[VAL_686]] : DMA) -// CHECK: aie.wire(%[[VAL_685]] : North, %[[VAL_686]] : South) -// CHECK: aie.wire(%[[VAL_681]] : East, %[[VAL_687:.*]] : West) -// CHECK: aie.wire(%[[VAL_200]] : Core, %[[VAL_687]] : Core) -// CHECK: aie.wire(%[[VAL_200]] : DMA, %[[VAL_687]] : DMA) -// CHECK: aie.wire(%[[VAL_686]] : North, %[[VAL_687]] : South) -// CHECK: aie.wire(%[[VAL_682]] : East, %[[VAL_688:.*]] : West) -// CHECK: aie.wire(%[[VAL_122]] : Core, %[[VAL_688]] : Core) -// CHECK: aie.wire(%[[VAL_122]] : DMA, %[[VAL_688]] : DMA) -// CHECK: aie.wire(%[[VAL_687]] : North, %[[VAL_688]] : South) -// CHECK: aie.wire(%[[VAL_683]] : East, %[[VAL_689:.*]] : West) -// CHECK: aie.wire(%[[VAL_44]] : Core, %[[VAL_689]] : Core) -// CHECK: aie.wire(%[[VAL_44]] : DMA, %[[VAL_689]] : DMA) -// CHECK: aie.wire(%[[VAL_688]] : North, %[[VAL_689]] : South) -// CHECK: aie.wire(%[[VAL_684]] : East, %[[VAL_690:.*]] : West) -// CHECK: aie.wire(%[[VAL_685]] : East, %[[VAL_691:.*]] : West) -// CHECK: aie.wire(%[[VAL_338]] : Core, %[[VAL_691]] : Core) -// CHECK: aie.wire(%[[VAL_338]] : DMA, %[[VAL_691]] : DMA) -// CHECK: aie.wire(%[[VAL_690]] : North, %[[VAL_691]] : South) -// CHECK: aie.wire(%[[VAL_686]] : East, %[[VAL_692:.*]] : West) -// CHECK: aie.wire(%[[VAL_256]] : Core, %[[VAL_692]] : Core) -// CHECK: aie.wire(%[[VAL_256]] : DMA, %[[VAL_692]] : DMA) -// CHECK: aie.wire(%[[VAL_691]] : North, %[[VAL_692]] : South) -// CHECK: aie.wire(%[[VAL_687]] : East, %[[VAL_693:.*]] : West) -// CHECK: aie.wire(%[[VAL_180]] : Core, %[[VAL_693]] : Core) -// CHECK: aie.wire(%[[VAL_180]] : DMA, %[[VAL_693]] : DMA) -// CHECK: aie.wire(%[[VAL_692]] : North, %[[VAL_693]] : South) -// CHECK: aie.wire(%[[VAL_688]] : East, %[[VAL_694:.*]] : West) -// CHECK: aie.wire(%[[VAL_102]] : Core, %[[VAL_694]] : Core) -// CHECK: aie.wire(%[[VAL_102]] : DMA, %[[VAL_694]] : DMA) -// CHECK: aie.wire(%[[VAL_693]] : North, %[[VAL_694]] : South) -// CHECK: aie.wire(%[[VAL_689]] : East, %[[VAL_695:.*]] : West) -// CHECK: aie.wire(%[[VAL_24]] : Core, %[[VAL_695]] : Core) -// CHECK: aie.wire(%[[VAL_24]] : DMA, %[[VAL_695]] : DMA) -// CHECK: aie.wire(%[[VAL_694]] : North, %[[VAL_695]] : South) -// CHECK: aie.wire(%[[VAL_690]] : East, %[[VAL_696:.*]] : West) -// CHECK: aie.wire(%[[VAL_697:.*]] : North, %[[VAL_696]] : South) -// CHECK: aie.wire(%[[VAL_217]] : DMA, %[[VAL_697]] : DMA) -// CHECK: aie.wire(%[[VAL_691]] : East, %[[VAL_698:.*]] : West) -// CHECK: aie.wire(%[[VAL_216]] : Core, %[[VAL_698]] : Core) -// CHECK: aie.wire(%[[VAL_216]] : DMA, %[[VAL_698]] : DMA) -// CHECK: aie.wire(%[[VAL_696]] : North, %[[VAL_698]] : South) -// CHECK: aie.wire(%[[VAL_692]] : East, %[[VAL_699:.*]] : West) -// CHECK: aie.wire(%[[VAL_237]] : Core, %[[VAL_699]] : Core) -// CHECK: aie.wire(%[[VAL_237]] : DMA, %[[VAL_699]] : DMA) -// CHECK: aie.wire(%[[VAL_698]] : North, %[[VAL_699]] : South) -// CHECK: aie.wire(%[[VAL_693]] : East, %[[VAL_700:.*]] : West) -// CHECK: aie.wire(%[[VAL_161]] : Core, %[[VAL_700]] : Core) -// CHECK: aie.wire(%[[VAL_161]] : DMA, %[[VAL_700]] : DMA) -// CHECK: aie.wire(%[[VAL_699]] : North, %[[VAL_700]] : South) -// CHECK: aie.wire(%[[VAL_694]] : East, %[[VAL_701:.*]] : West) -// CHECK: aie.wire(%[[VAL_83]] : Core, %[[VAL_701]] : Core) -// CHECK: aie.wire(%[[VAL_83]] : DMA, %[[VAL_701]] : DMA) -// CHECK: aie.wire(%[[VAL_700]] : North, %[[VAL_701]] : South) -// CHECK: aie.wire(%[[VAL_695]] : East, %[[VAL_702:.*]] : West) -// CHECK: aie.wire(%[[VAL_4]] : Core, %[[VAL_702]] : Core) -// CHECK: aie.wire(%[[VAL_4]] : DMA, %[[VAL_702]] : DMA) -// CHECK: aie.wire(%[[VAL_701]] : North, %[[VAL_702]] : South) -// CHECK: aie.wire(%[[VAL_696]] : East, %[[VAL_703:.*]] : West) -// CHECK: aie.wire(%[[VAL_704:.*]] : North, %[[VAL_703]] : South) -// CHECK: aie.wire(%[[VAL_198]] : DMA, %[[VAL_704]] : DMA) -// CHECK: aie.wire(%[[VAL_698]] : East, %[[VAL_705:.*]] : West) -// CHECK: aie.wire(%[[VAL_197]] : Core, %[[VAL_705]] : Core) -// CHECK: aie.wire(%[[VAL_197]] : DMA, %[[VAL_705]] : DMA) -// CHECK: aie.wire(%[[VAL_703]] : North, %[[VAL_705]] : South) -// CHECK: aie.wire(%[[VAL_699]] : East, %[[VAL_706:.*]] : West) -// CHECK: aie.wire(%[[VAL_196]] : Core, %[[VAL_706]] : Core) -// CHECK: aie.wire(%[[VAL_196]] : DMA, %[[VAL_706]] : DMA) -// CHECK: aie.wire(%[[VAL_705]] : North, %[[VAL_706]] : South) -// CHECK: aie.wire(%[[VAL_700]] : East, %[[VAL_707:.*]] : West) -// CHECK: aie.wire(%[[VAL_372]] : Core, %[[VAL_707]] : Core) -// CHECK: aie.wire(%[[VAL_372]] : DMA, %[[VAL_707]] : DMA) -// CHECK: aie.wire(%[[VAL_706]] : North, %[[VAL_707]] : South) -// CHECK: aie.wire(%[[VAL_701]] : East, %[[VAL_708:.*]] : West) -// CHECK: aie.wire(%[[VAL_530]] : Core, %[[VAL_708]] : Core) -// CHECK: aie.wire(%[[VAL_530]] : DMA, %[[VAL_708]] : DMA) -// CHECK: aie.wire(%[[VAL_707]] : North, %[[VAL_708]] : South) -// CHECK: aie.wire(%[[VAL_702]] : East, %[[VAL_709:.*]] : West) -// CHECK: aie.wire(%[[VAL_478]] : Core, %[[VAL_709]] : Core) -// CHECK: aie.wire(%[[VAL_478]] : DMA, %[[VAL_709]] : DMA) -// CHECK: aie.wire(%[[VAL_708]] : North, %[[VAL_709]] : South) -// CHECK: aie.wire(%[[VAL_703]] : East, %[[VAL_710:.*]] : West) -// CHECK: aie.wire(%[[VAL_705]] : East, %[[VAL_711:.*]] : West) -// CHECK: aie.wire(%[[VAL_377]] : Core, %[[VAL_711]] : Core) -// CHECK: aie.wire(%[[VAL_377]] : DMA, %[[VAL_711]] : DMA) -// CHECK: aie.wire(%[[VAL_710]] : North, %[[VAL_711]] : South) -// CHECK: aie.wire(%[[VAL_706]] : East, %[[VAL_712:.*]] : West) -// CHECK: aie.wire(%[[VAL_409]] : Core, %[[VAL_712]] : Core) -// CHECK: aie.wire(%[[VAL_409]] : DMA, %[[VAL_712]] : DMA) -// CHECK: aie.wire(%[[VAL_711]] : North, %[[VAL_712]] : South) -// CHECK: aie.wire(%[[VAL_707]] : East, %[[VAL_713:.*]] : West) -// CHECK: aie.wire(%[[VAL_453]] : Core, %[[VAL_713]] : Core) -// CHECK: aie.wire(%[[VAL_453]] : DMA, %[[VAL_713]] : DMA) -// CHECK: aie.wire(%[[VAL_712]] : North, %[[VAL_713]] : South) -// CHECK: aie.wire(%[[VAL_708]] : East, %[[VAL_714:.*]] : West) -// CHECK: aie.wire(%[[VAL_532]] : Core, %[[VAL_714]] : Core) -// CHECK: aie.wire(%[[VAL_532]] : DMA, %[[VAL_714]] : DMA) -// CHECK: aie.wire(%[[VAL_713]] : North, %[[VAL_714]] : South) -// CHECK: aie.wire(%[[VAL_709]] : East, %[[VAL_715:.*]] : West) -// CHECK: aie.wire(%[[VAL_480]] : Core, %[[VAL_715]] : Core) -// CHECK: aie.wire(%[[VAL_480]] : DMA, %[[VAL_715]] : DMA) -// CHECK: aie.wire(%[[VAL_714]] : North, %[[VAL_715]] : South) -// CHECK: aie.wire(%[[VAL_710]] : East, %[[VAL_716:.*]] : West) -// CHECK: aie.wire(%[[VAL_711]] : East, %[[VAL_717:.*]] : West) -// CHECK: aie.wire(%[[VAL_379]] : Core, %[[VAL_717]] : Core) -// CHECK: aie.wire(%[[VAL_379]] : DMA, %[[VAL_717]] : DMA) -// CHECK: aie.wire(%[[VAL_716]] : North, %[[VAL_717]] : South) -// CHECK: aie.wire(%[[VAL_712]] : East, %[[VAL_718:.*]] : West) -// CHECK: aie.wire(%[[VAL_411]] : Core, %[[VAL_718]] : Core) -// CHECK: aie.wire(%[[VAL_411]] : DMA, %[[VAL_718]] : DMA) -// CHECK: aie.wire(%[[VAL_717]] : North, %[[VAL_718]] : South) -// CHECK: aie.wire(%[[VAL_713]] : East, %[[VAL_719:.*]] : West) -// CHECK: aie.wire(%[[VAL_455]] : Core, %[[VAL_719]] : Core) -// CHECK: aie.wire(%[[VAL_455]] : DMA, %[[VAL_719]] : DMA) -// CHECK: aie.wire(%[[VAL_718]] : North, %[[VAL_719]] : South) -// CHECK: aie.wire(%[[VAL_714]] : East, %[[VAL_720:.*]] : West) -// CHECK: aie.wire(%[[VAL_534]] : Core, %[[VAL_720]] : Core) -// CHECK: aie.wire(%[[VAL_534]] : DMA, %[[VAL_720]] : DMA) -// CHECK: aie.wire(%[[VAL_719]] : North, %[[VAL_720]] : South) -// CHECK: aie.wire(%[[VAL_715]] : East, %[[VAL_721:.*]] : West) -// CHECK: aie.wire(%[[VAL_482]] : Core, %[[VAL_721]] : Core) -// CHECK: aie.wire(%[[VAL_482]] : DMA, %[[VAL_721]] : DMA) -// CHECK: aie.wire(%[[VAL_720]] : North, %[[VAL_721]] : South) -// CHECK: aie.wire(%[[VAL_716]] : East, %[[VAL_722:.*]] : West) -// CHECK: aie.wire(%[[VAL_717]] : East, %[[VAL_723:.*]] : West) -// CHECK: aie.wire(%[[VAL_381]] : Core, %[[VAL_723]] : Core) -// CHECK: aie.wire(%[[VAL_381]] : DMA, %[[VAL_723]] : DMA) -// CHECK: aie.wire(%[[VAL_722]] : North, %[[VAL_723]] : South) -// CHECK: aie.wire(%[[VAL_718]] : East, %[[VAL_724:.*]] : West) -// CHECK: aie.wire(%[[VAL_413]] : Core, %[[VAL_724]] : Core) -// CHECK: aie.wire(%[[VAL_413]] : DMA, %[[VAL_724]] : DMA) -// CHECK: aie.wire(%[[VAL_723]] : North, %[[VAL_724]] : South) -// CHECK: aie.wire(%[[VAL_719]] : East, %[[VAL_725:.*]] : West) -// CHECK: aie.wire(%[[VAL_457]] : Core, %[[VAL_725]] : Core) -// CHECK: aie.wire(%[[VAL_457]] : DMA, %[[VAL_725]] : DMA) -// CHECK: aie.wire(%[[VAL_724]] : North, %[[VAL_725]] : South) -// CHECK: aie.wire(%[[VAL_720]] : East, %[[VAL_726:.*]] : West) -// CHECK: aie.wire(%[[VAL_536]] : Core, %[[VAL_726]] : Core) -// CHECK: aie.wire(%[[VAL_536]] : DMA, %[[VAL_726]] : DMA) -// CHECK: aie.wire(%[[VAL_725]] : North, %[[VAL_726]] : South) -// CHECK: aie.wire(%[[VAL_721]] : East, %[[VAL_727:.*]] : West) -// CHECK: aie.wire(%[[VAL_484]] : Core, %[[VAL_727]] : Core) -// CHECK: aie.wire(%[[VAL_484]] : DMA, %[[VAL_727]] : DMA) -// CHECK: aie.wire(%[[VAL_726]] : North, %[[VAL_727]] : South) -// CHECK: aie.wire(%[[VAL_722]] : East, %[[VAL_728:.*]] : West) -// CHECK: aie.wire(%[[VAL_723]] : East, %[[VAL_729:.*]] : West) -// CHECK: aie.wire(%[[VAL_383]] : Core, %[[VAL_729]] : Core) -// CHECK: aie.wire(%[[VAL_383]] : DMA, %[[VAL_729]] : DMA) -// CHECK: aie.wire(%[[VAL_728]] : North, %[[VAL_729]] : South) -// CHECK: aie.wire(%[[VAL_724]] : East, %[[VAL_730:.*]] : West) -// CHECK: aie.wire(%[[VAL_415]] : Core, %[[VAL_730]] : Core) -// CHECK: aie.wire(%[[VAL_415]] : DMA, %[[VAL_730]] : DMA) -// CHECK: aie.wire(%[[VAL_729]] : North, %[[VAL_730]] : South) -// CHECK: aie.wire(%[[VAL_725]] : East, %[[VAL_731:.*]] : West) -// CHECK: aie.wire(%[[VAL_459]] : Core, %[[VAL_731]] : Core) -// CHECK: aie.wire(%[[VAL_459]] : DMA, %[[VAL_731]] : DMA) -// CHECK: aie.wire(%[[VAL_730]] : North, %[[VAL_731]] : South) -// CHECK: aie.wire(%[[VAL_726]] : East, %[[VAL_732:.*]] : West) -// CHECK: aie.wire(%[[VAL_486]] : Core, %[[VAL_732]] : Core) -// CHECK: aie.wire(%[[VAL_486]] : DMA, %[[VAL_732]] : DMA) -// CHECK: aie.wire(%[[VAL_731]] : North, %[[VAL_732]] : South) -// CHECK: aie.wire(%[[VAL_727]] : East, %[[VAL_733:.*]] : West) -// CHECK: aie.wire(%[[VAL_488]] : Core, %[[VAL_733]] : Core) -// CHECK: aie.wire(%[[VAL_488]] : DMA, %[[VAL_733]] : DMA) -// CHECK: aie.wire(%[[VAL_732]] : North, %[[VAL_733]] : South) -// CHECK: aie.wire(%[[VAL_728]] : East, %[[VAL_734:.*]] : West) -// CHECK: aie.wire(%[[VAL_729]] : East, %[[VAL_735:.*]] : West) -// CHECK: aie.wire(%[[VAL_385]] : Core, %[[VAL_735]] : Core) -// CHECK: aie.wire(%[[VAL_385]] : DMA, %[[VAL_735]] : DMA) -// CHECK: aie.wire(%[[VAL_734]] : North, %[[VAL_735]] : South) -// CHECK: aie.wire(%[[VAL_730]] : East, %[[VAL_736:.*]] : West) -// CHECK: aie.wire(%[[VAL_417]] : Core, %[[VAL_736]] : Core) -// CHECK: aie.wire(%[[VAL_417]] : DMA, %[[VAL_736]] : DMA) -// CHECK: aie.wire(%[[VAL_735]] : North, %[[VAL_736]] : South) -// CHECK: aie.wire(%[[VAL_731]] : East, %[[VAL_737:.*]] : West) -// CHECK: aie.wire(%[[VAL_461]] : Core, %[[VAL_737]] : Core) -// CHECK: aie.wire(%[[VAL_461]] : DMA, %[[VAL_737]] : DMA) -// CHECK: aie.wire(%[[VAL_736]] : North, %[[VAL_737]] : South) -// CHECK: aie.wire(%[[VAL_732]] : East, %[[VAL_738:.*]] : West) -// CHECK: aie.wire(%[[VAL_538]] : Core, %[[VAL_738]] : Core) -// CHECK: aie.wire(%[[VAL_538]] : DMA, %[[VAL_738]] : DMA) -// CHECK: aie.wire(%[[VAL_737]] : North, %[[VAL_738]] : South) -// CHECK: aie.wire(%[[VAL_733]] : East, %[[VAL_739:.*]] : West) -// CHECK: aie.wire(%[[VAL_597]] : Core, %[[VAL_739]] : Core) -// CHECK: aie.wire(%[[VAL_597]] : DMA, %[[VAL_739]] : DMA) -// CHECK: aie.wire(%[[VAL_738]] : North, %[[VAL_739]] : South) -// CHECK: aie.wire(%[[VAL_734]] : East, %[[VAL_740:.*]] : West) -// CHECK: aie.wire(%[[VAL_735]] : East, %[[VAL_741:.*]] : West) -// CHECK: aie.wire(%[[VAL_387]] : Core, %[[VAL_741]] : Core) -// CHECK: aie.wire(%[[VAL_387]] : DMA, %[[VAL_741]] : DMA) -// CHECK: aie.wire(%[[VAL_740]] : North, %[[VAL_741]] : South) -// CHECK: aie.wire(%[[VAL_736]] : East, %[[VAL_742:.*]] : West) -// CHECK: aie.wire(%[[VAL_419]] : Core, %[[VAL_742]] : Core) -// CHECK: aie.wire(%[[VAL_419]] : DMA, %[[VAL_742]] : DMA) -// CHECK: aie.wire(%[[VAL_741]] : North, %[[VAL_742]] : South) -// CHECK: aie.wire(%[[VAL_737]] : East, %[[VAL_743:.*]] : West) -// CHECK: aie.wire(%[[VAL_463]] : Core, %[[VAL_743]] : Core) -// CHECK: aie.wire(%[[VAL_463]] : DMA, %[[VAL_743]] : DMA) -// CHECK: aie.wire(%[[VAL_742]] : North, %[[VAL_743]] : South) -// CHECK: aie.wire(%[[VAL_738]] : East, %[[VAL_744:.*]] : West) -// CHECK: aie.wire(%[[VAL_540]] : Core, %[[VAL_744]] : Core) -// CHECK: aie.wire(%[[VAL_540]] : DMA, %[[VAL_744]] : DMA) -// CHECK: aie.wire(%[[VAL_743]] : North, %[[VAL_744]] : South) -// CHECK: aie.wire(%[[VAL_739]] : East, %[[VAL_745:.*]] : West) -// CHECK: aie.wire(%[[VAL_599]] : Core, %[[VAL_745]] : Core) -// CHECK: aie.wire(%[[VAL_599]] : DMA, %[[VAL_745]] : DMA) -// CHECK: aie.wire(%[[VAL_744]] : North, %[[VAL_745]] : South) -// CHECK: aie.wire(%[[VAL_740]] : East, %[[VAL_746:.*]] : West) -// CHECK: aie.wire(%[[VAL_747:.*]] : North, %[[VAL_746]] : South) -// CHECK: aie.wire(%[[VAL_179]] : DMA, %[[VAL_747]] : DMA) -// CHECK: aie.wire(%[[VAL_741]] : East, %[[VAL_748:.*]] : West) -// CHECK: aie.wire(%[[VAL_178]] : Core, %[[VAL_748]] : Core) -// CHECK: aie.wire(%[[VAL_178]] : DMA, %[[VAL_748]] : DMA) -// CHECK: aie.wire(%[[VAL_746]] : North, %[[VAL_748]] : South) -// CHECK: aie.wire(%[[VAL_742]] : East, %[[VAL_749:.*]] : West) -// CHECK: aie.wire(%[[VAL_177]] : Core, %[[VAL_749]] : Core) -// CHECK: aie.wire(%[[VAL_177]] : DMA, %[[VAL_749]] : DMA) -// CHECK: aie.wire(%[[VAL_748]] : North, %[[VAL_749]] : South) -// CHECK: aie.wire(%[[VAL_743]] : East, %[[VAL_750:.*]] : West) -// CHECK: aie.wire(%[[VAL_465]] : Core, %[[VAL_750]] : Core) -// CHECK: aie.wire(%[[VAL_465]] : DMA, %[[VAL_750]] : DMA) -// CHECK: aie.wire(%[[VAL_749]] : North, %[[VAL_750]] : South) -// CHECK: aie.wire(%[[VAL_744]] : East, %[[VAL_751:.*]] : West) -// CHECK: aie.wire(%[[VAL_552]] : Core, %[[VAL_751]] : Core) -// CHECK: aie.wire(%[[VAL_552]] : DMA, %[[VAL_751]] : DMA) -// CHECK: aie.wire(%[[VAL_750]] : North, %[[VAL_751]] : South) -// CHECK: aie.wire(%[[VAL_745]] : East, %[[VAL_752:.*]] : West) -// CHECK: aie.wire(%[[VAL_601]] : Core, %[[VAL_752]] : Core) -// CHECK: aie.wire(%[[VAL_601]] : DMA, %[[VAL_752]] : DMA) -// CHECK: aie.wire(%[[VAL_751]] : North, %[[VAL_752]] : South) -// CHECK: aie.wire(%[[VAL_746]] : East, %[[VAL_753:.*]] : West) -// CHECK: aie.wire(%[[VAL_754:.*]] : North, %[[VAL_753]] : South) -// CHECK: aie.wire(%[[VAL_160]] : DMA, %[[VAL_754]] : DMA) -// CHECK: aie.wire(%[[VAL_748]] : East, %[[VAL_755:.*]] : West) -// CHECK: aie.wire(%[[VAL_159]] : Core, %[[VAL_755]] : Core) -// CHECK: aie.wire(%[[VAL_159]] : DMA, %[[VAL_755]] : DMA) -// CHECK: aie.wire(%[[VAL_753]] : North, %[[VAL_755]] : South) -// CHECK: aie.wire(%[[VAL_749]] : East, %[[VAL_756:.*]] : West) -// CHECK: aie.wire(%[[VAL_158]] : Core, %[[VAL_756]] : Core) -// CHECK: aie.wire(%[[VAL_158]] : DMA, %[[VAL_756]] : DMA) -// CHECK: aie.wire(%[[VAL_755]] : North, %[[VAL_756]] : South) -// CHECK: aie.wire(%[[VAL_750]] : East, %[[VAL_757:.*]] : West) -// CHECK: aie.wire(%[[VAL_467]] : Core, %[[VAL_757]] : Core) -// CHECK: aie.wire(%[[VAL_467]] : DMA, %[[VAL_757]] : DMA) -// CHECK: aie.wire(%[[VAL_756]] : North, %[[VAL_757]] : South) -// CHECK: aie.wire(%[[VAL_751]] : East, %[[VAL_758:.*]] : West) -// CHECK: aie.wire(%[[VAL_554]] : Core, %[[VAL_758]] : Core) -// CHECK: aie.wire(%[[VAL_554]] : DMA, %[[VAL_758]] : DMA) -// CHECK: aie.wire(%[[VAL_757]] : North, %[[VAL_758]] : South) -// CHECK: aie.wire(%[[VAL_753]] : East, %[[VAL_759:.*]] : West) -// CHECK: aie.wire(%[[VAL_755]] : East, %[[VAL_760:.*]] : West) -// CHECK: aie.wire(%[[VAL_423]] : Core, %[[VAL_760]] : Core) -// CHECK: aie.wire(%[[VAL_423]] : DMA, %[[VAL_760]] : DMA) -// CHECK: aie.wire(%[[VAL_759]] : North, %[[VAL_760]] : South) -// CHECK: aie.wire(%[[VAL_756]] : East, %[[VAL_761:.*]] : West) -// CHECK: aie.wire(%[[VAL_425]] : Core, %[[VAL_761]] : Core) -// CHECK: aie.wire(%[[VAL_425]] : DMA, %[[VAL_761]] : DMA) -// CHECK: aie.wire(%[[VAL_760]] : North, %[[VAL_761]] : South) -// CHECK: aie.wire(%[[VAL_757]] : East, %[[VAL_762:.*]] : West) -// CHECK: aie.wire(%[[VAL_469]] : Core, %[[VAL_762]] : Core) -// CHECK: aie.wire(%[[VAL_469]] : DMA, %[[VAL_762]] : DMA) -// CHECK: aie.wire(%[[VAL_761]] : North, %[[VAL_762]] : South) -// CHECK: aie.wire(%[[VAL_758]] : East, %[[VAL_763:.*]] : West) -// CHECK: aie.wire(%[[VAL_556]] : Core, %[[VAL_763]] : Core) -// CHECK: aie.wire(%[[VAL_556]] : DMA, %[[VAL_763]] : DMA) -// CHECK: aie.wire(%[[VAL_762]] : North, %[[VAL_763]] : South) -// CHECK: aie.wire(%[[VAL_759]] : East, %[[VAL_764:.*]] : West) -// CHECK: aie.wire(%[[VAL_760]] : East, %[[VAL_765:.*]] : West) -// CHECK: aie.wire(%[[VAL_427]] : Core, %[[VAL_765]] : Core) -// CHECK: aie.wire(%[[VAL_427]] : DMA, %[[VAL_765]] : DMA) -// CHECK: aie.wire(%[[VAL_764]] : North, %[[VAL_765]] : South) -// CHECK: aie.wire(%[[VAL_761]] : East, %[[VAL_766:.*]] : West) -// CHECK: aie.wire(%[[VAL_542]] : Core, %[[VAL_766]] : Core) -// CHECK: aie.wire(%[[VAL_542]] : DMA, %[[VAL_766]] : DMA) -// CHECK: aie.wire(%[[VAL_765]] : North, %[[VAL_766]] : South) -// CHECK: aie.wire(%[[VAL_762]] : East, %[[VAL_767:.*]] : West) -// CHECK: aie.wire(%[[VAL_490]] : Core, %[[VAL_767]] : Core) -// CHECK: aie.wire(%[[VAL_490]] : DMA, %[[VAL_767]] : DMA) -// CHECK: aie.wire(%[[VAL_766]] : North, %[[VAL_767]] : South) -// CHECK: aie.wire(%[[VAL_763]] : East, %[[VAL_768:.*]] : West) -// CHECK: aie.wire(%[[VAL_603]] : Core, %[[VAL_768]] : Core) -// CHECK: aie.wire(%[[VAL_603]] : DMA, %[[VAL_768]] : DMA) -// CHECK: aie.wire(%[[VAL_767]] : North, %[[VAL_768]] : South) -// CHECK: aie.wire(%[[VAL_764]] : East, %[[VAL_769:.*]] : West) -// CHECK: aie.wire(%[[VAL_765]] : East, %[[VAL_770:.*]] : West) -// CHECK: aie.wire(%[[VAL_429]] : Core, %[[VAL_770]] : Core) -// CHECK: aie.wire(%[[VAL_429]] : DMA, %[[VAL_770]] : DMA) -// CHECK: aie.wire(%[[VAL_769]] : North, %[[VAL_770]] : South) -// CHECK: aie.wire(%[[VAL_766]] : East, %[[VAL_771:.*]] : West) -// CHECK: aie.wire(%[[VAL_544]] : Core, %[[VAL_771]] : Core) -// CHECK: aie.wire(%[[VAL_544]] : DMA, %[[VAL_771]] : DMA) -// CHECK: aie.wire(%[[VAL_770]] : North, %[[VAL_771]] : South) -// CHECK: aie.wire(%[[VAL_767]] : East, %[[VAL_772:.*]] : West) -// CHECK: aie.wire(%[[VAL_492]] : Core, %[[VAL_772]] : Core) -// CHECK: aie.wire(%[[VAL_492]] : DMA, %[[VAL_772]] : DMA) -// CHECK: aie.wire(%[[VAL_771]] : North, %[[VAL_772]] : South) -// CHECK: aie.wire(%[[VAL_768]] : East, %[[VAL_773:.*]] : West) -// CHECK: aie.wire(%[[VAL_605]] : Core, %[[VAL_773]] : Core) -// CHECK: aie.wire(%[[VAL_605]] : DMA, %[[VAL_773]] : DMA) -// CHECK: aie.wire(%[[VAL_772]] : North, %[[VAL_773]] : South) -// CHECK: aie.wire(%[[VAL_769]] : East, %[[VAL_774:.*]] : West) -// CHECK: aie.wire(%[[VAL_770]] : East, %[[VAL_775:.*]] : West) -// CHECK: aie.wire(%[[VAL_431]] : Core, %[[VAL_775]] : Core) -// CHECK: aie.wire(%[[VAL_431]] : DMA, %[[VAL_775]] : DMA) -// CHECK: aie.wire(%[[VAL_774]] : North, %[[VAL_775]] : South) -// CHECK: aie.wire(%[[VAL_771]] : East, %[[VAL_776:.*]] : West) -// CHECK: aie.wire(%[[VAL_546]] : Core, %[[VAL_776]] : Core) -// CHECK: aie.wire(%[[VAL_546]] : DMA, %[[VAL_776]] : DMA) -// CHECK: aie.wire(%[[VAL_775]] : North, %[[VAL_776]] : South) -// CHECK: aie.wire(%[[VAL_772]] : East, %[[VAL_777:.*]] : West) -// CHECK: aie.wire(%[[VAL_494]] : Core, %[[VAL_777]] : Core) -// CHECK: aie.wire(%[[VAL_494]] : DMA, %[[VAL_777]] : DMA) -// CHECK: aie.wire(%[[VAL_776]] : North, %[[VAL_777]] : South) -// CHECK: aie.wire(%[[VAL_773]] : East, %[[VAL_778:.*]] : West) -// CHECK: aie.wire(%[[VAL_607]] : Core, %[[VAL_778]] : Core) -// CHECK: aie.wire(%[[VAL_607]] : DMA, %[[VAL_778]] : DMA) -// CHECK: aie.wire(%[[VAL_777]] : North, %[[VAL_778]] : South) -// CHECK: aie.wire(%[[VAL_774]] : East, %[[VAL_779:.*]] : West) -// CHECK: aie.wire(%[[VAL_775]] : East, %[[VAL_780:.*]] : West) -// CHECK: aie.wire(%[[VAL_433]] : Core, %[[VAL_780]] : Core) -// CHECK: aie.wire(%[[VAL_433]] : DMA, %[[VAL_780]] : DMA) -// CHECK: aie.wire(%[[VAL_779]] : North, %[[VAL_780]] : South) -// CHECK: aie.wire(%[[VAL_776]] : East, %[[VAL_781:.*]] : West) -// CHECK: aie.wire(%[[VAL_496]] : Core, %[[VAL_781]] : Core) -// CHECK: aie.wire(%[[VAL_496]] : DMA, %[[VAL_781]] : DMA) -// CHECK: aie.wire(%[[VAL_780]] : North, %[[VAL_781]] : South) -// CHECK: aie.wire(%[[VAL_777]] : East, %[[VAL_782:.*]] : West) -// CHECK: aie.wire(%[[VAL_498]] : Core, %[[VAL_782]] : Core) -// CHECK: aie.wire(%[[VAL_498]] : DMA, %[[VAL_782]] : DMA) -// CHECK: aie.wire(%[[VAL_781]] : North, %[[VAL_782]] : South) -// CHECK: aie.wire(%[[VAL_778]] : East, %[[VAL_783:.*]] : West) -// CHECK: aie.wire(%[[VAL_609]] : Core, %[[VAL_783]] : Core) -// CHECK: aie.wire(%[[VAL_609]] : DMA, %[[VAL_783]] : DMA) -// CHECK: aie.wire(%[[VAL_782]] : North, %[[VAL_783]] : South) -// CHECK: aie.wire(%[[VAL_779]] : East, %[[VAL_784:.*]] : West) -// CHECK: aie.wire(%[[VAL_780]] : East, %[[VAL_785:.*]] : West) -// CHECK: aie.wire(%[[VAL_435]] : Core, %[[VAL_785]] : Core) -// CHECK: aie.wire(%[[VAL_435]] : DMA, %[[VAL_785]] : DMA) -// CHECK: aie.wire(%[[VAL_784]] : North, %[[VAL_785]] : South) -// CHECK: aie.wire(%[[VAL_781]] : East, %[[VAL_786:.*]] : West) -// CHECK: aie.wire(%[[VAL_500]] : Core, %[[VAL_786]] : Core) -// CHECK: aie.wire(%[[VAL_500]] : DMA, %[[VAL_786]] : DMA) -// CHECK: aie.wire(%[[VAL_785]] : North, %[[VAL_786]] : South) -// CHECK: aie.wire(%[[VAL_782]] : East, %[[VAL_787:.*]] : West) -// CHECK: aie.wire(%[[VAL_558]] : Core, %[[VAL_787]] : Core) -// CHECK: aie.wire(%[[VAL_558]] : DMA, %[[VAL_787]] : DMA) -// CHECK: aie.wire(%[[VAL_786]] : North, %[[VAL_787]] : South) -// CHECK: aie.wire(%[[VAL_783]] : East, %[[VAL_788:.*]] : West) -// CHECK: aie.wire(%[[VAL_611]] : Core, %[[VAL_788]] : Core) -// CHECK: aie.wire(%[[VAL_611]] : DMA, %[[VAL_788]] : DMA) -// CHECK: aie.wire(%[[VAL_787]] : North, %[[VAL_788]] : South) -// CHECK: aie.wire(%[[VAL_784]] : East, %[[VAL_789:.*]] : West) -// CHECK: aie.wire(%[[VAL_790:.*]] : North, %[[VAL_789]] : South) -// CHECK: aie.wire(%[[VAL_140]] : DMA, %[[VAL_790]] : DMA) -// CHECK: aie.wire(%[[VAL_785]] : East, %[[VAL_791:.*]] : West) -// CHECK: aie.wire(%[[VAL_139]] : Core, %[[VAL_791]] : Core) -// CHECK: aie.wire(%[[VAL_139]] : DMA, %[[VAL_791]] : DMA) -// CHECK: aie.wire(%[[VAL_789]] : North, %[[VAL_791]] : South) -// CHECK: aie.wire(%[[VAL_786]] : East, %[[VAL_792:.*]] : West) -// CHECK: aie.wire(%[[VAL_138]] : Core, %[[VAL_792]] : Core) -// CHECK: aie.wire(%[[VAL_138]] : DMA, %[[VAL_792]] : DMA) -// CHECK: aie.wire(%[[VAL_791]] : North, %[[VAL_792]] : South) -// CHECK: aie.wire(%[[VAL_787]] : East, %[[VAL_793:.*]] : West) -// CHECK: aie.wire(%[[VAL_560]] : Core, %[[VAL_793]] : Core) -// CHECK: aie.wire(%[[VAL_560]] : DMA, %[[VAL_793]] : DMA) -// CHECK: aie.wire(%[[VAL_792]] : North, %[[VAL_793]] : South) -// CHECK: aie.wire(%[[VAL_788]] : East, %[[VAL_794:.*]] : West) -// CHECK: aie.wire(%[[VAL_613]] : Core, %[[VAL_794]] : Core) -// CHECK: aie.wire(%[[VAL_613]] : DMA, %[[VAL_794]] : DMA) -// CHECK: aie.wire(%[[VAL_793]] : North, %[[VAL_794]] : South) -// CHECK: aie.wire(%[[VAL_789]] : East, %[[VAL_795:.*]] : West) -// CHECK: aie.wire(%[[VAL_796:.*]] : North, %[[VAL_795]] : South) -// CHECK: aie.wire(%[[VAL_120]] : DMA, %[[VAL_796]] : DMA) -// CHECK: aie.wire(%[[VAL_791]] : East, %[[VAL_797:.*]] : West) -// CHECK: aie.wire(%[[VAL_119]] : Core, %[[VAL_797]] : Core) -// CHECK: aie.wire(%[[VAL_119]] : DMA, %[[VAL_797]] : DMA) -// CHECK: aie.wire(%[[VAL_795]] : North, %[[VAL_797]] : South) -// CHECK: aie.wire(%[[VAL_792]] : East, %[[VAL_798:.*]] : West) -// CHECK: aie.wire(%[[VAL_118]] : Core, %[[VAL_798]] : Core) -// CHECK: aie.wire(%[[VAL_118]] : DMA, %[[VAL_798]] : DMA) -// CHECK: aie.wire(%[[VAL_797]] : North, %[[VAL_798]] : South) -// CHECK: aie.wire(%[[VAL_794]] : East, %[[VAL_799:.*]] : West) -// CHECK: aie.wire(%[[VAL_615]] : Core, %[[VAL_799]] : Core) -// CHECK: aie.wire(%[[VAL_615]] : DMA, %[[VAL_799]] : DMA) -// CHECK: aie.wire(%[[VAL_795]] : East, %[[VAL_800:.*]] : West) -// CHECK: aie.wire(%[[VAL_797]] : East, %[[VAL_801:.*]] : West) -// CHECK: aie.wire(%[[VAL_503]] : Core, %[[VAL_801]] : Core) -// CHECK: aie.wire(%[[VAL_503]] : DMA, %[[VAL_801]] : DMA) -// CHECK: aie.wire(%[[VAL_800]] : North, %[[VAL_801]] : South) -// CHECK: aie.wire(%[[VAL_798]] : East, %[[VAL_802:.*]] : West) -// CHECK: aie.wire(%[[VAL_562]] : Core, %[[VAL_802]] : Core) -// CHECK: aie.wire(%[[VAL_562]] : DMA, %[[VAL_802]] : DMA) -// CHECK: aie.wire(%[[VAL_801]] : North, %[[VAL_802]] : South) -// CHECK: aie.wire(%[[VAL_799]] : East, %[[VAL_803:.*]] : West) -// CHECK: aie.wire(%[[VAL_617]] : Core, %[[VAL_803]] : Core) -// CHECK: aie.wire(%[[VAL_617]] : DMA, %[[VAL_803]] : DMA) -// CHECK: aie.wire(%[[VAL_800]] : East, %[[VAL_804:.*]] : West) -// CHECK: aie.wire(%[[VAL_801]] : East, %[[VAL_805:.*]] : West) -// CHECK: aie.wire(%[[VAL_505]] : Core, %[[VAL_805]] : Core) -// CHECK: aie.wire(%[[VAL_505]] : DMA, %[[VAL_805]] : DMA) -// CHECK: aie.wire(%[[VAL_804]] : North, %[[VAL_805]] : South) -// CHECK: aie.wire(%[[VAL_802]] : East, %[[VAL_806:.*]] : West) -// CHECK: aie.wire(%[[VAL_564]] : Core, %[[VAL_806]] : Core) -// CHECK: aie.wire(%[[VAL_564]] : DMA, %[[VAL_806]] : DMA) -// CHECK: aie.wire(%[[VAL_805]] : North, %[[VAL_806]] : South) -// CHECK: aie.wire(%[[VAL_803]] : East, %[[VAL_807:.*]] : West) -// CHECK: aie.wire(%[[VAL_619]] : Core, %[[VAL_807]] : Core) -// CHECK: aie.wire(%[[VAL_619]] : DMA, %[[VAL_807]] : DMA) -// CHECK: aie.wire(%[[VAL_804]] : East, %[[VAL_808:.*]] : West) -// CHECK: aie.wire(%[[VAL_805]] : East, %[[VAL_809:.*]] : West) -// CHECK: aie.wire(%[[VAL_507]] : Core, %[[VAL_809]] : Core) -// CHECK: aie.wire(%[[VAL_507]] : DMA, %[[VAL_809]] : DMA) -// CHECK: aie.wire(%[[VAL_808]] : North, %[[VAL_809]] : South) -// CHECK: aie.wire(%[[VAL_806]] : East, %[[VAL_810:.*]] : West) -// CHECK: aie.wire(%[[VAL_566]] : Core, %[[VAL_810]] : Core) -// CHECK: aie.wire(%[[VAL_566]] : DMA, %[[VAL_810]] : DMA) -// CHECK: aie.wire(%[[VAL_809]] : North, %[[VAL_810]] : South) -// CHECK: aie.wire(%[[VAL_807]] : East, %[[VAL_811:.*]] : West) -// CHECK: aie.wire(%[[VAL_621]] : Core, %[[VAL_811]] : Core) -// CHECK: aie.wire(%[[VAL_621]] : DMA, %[[VAL_811]] : DMA) -// CHECK: aie.wire(%[[VAL_808]] : East, %[[VAL_812:.*]] : West) -// CHECK: aie.wire(%[[VAL_809]] : East, %[[VAL_813:.*]] : West) -// CHECK: aie.wire(%[[VAL_509]] : Core, %[[VAL_813]] : Core) -// CHECK: aie.wire(%[[VAL_509]] : DMA, %[[VAL_813]] : DMA) -// CHECK: aie.wire(%[[VAL_812]] : North, %[[VAL_813]] : South) -// CHECK: aie.wire(%[[VAL_810]] : East, %[[VAL_814:.*]] : West) -// CHECK: aie.wire(%[[VAL_568]] : Core, %[[VAL_814]] : Core) -// CHECK: aie.wire(%[[VAL_568]] : DMA, %[[VAL_814]] : DMA) -// CHECK: aie.wire(%[[VAL_813]] : North, %[[VAL_814]] : South) -// CHECK: aie.wire(%[[VAL_811]] : East, %[[VAL_815:.*]] : West) -// CHECK: aie.wire(%[[VAL_623]] : Core, %[[VAL_815]] : Core) -// CHECK: aie.wire(%[[VAL_623]] : DMA, %[[VAL_815]] : DMA) -// CHECK: aie.wire(%[[VAL_812]] : East, %[[VAL_816:.*]] : West) -// CHECK: aie.wire(%[[VAL_813]] : East, %[[VAL_817:.*]] : West) -// CHECK: aie.wire(%[[VAL_511]] : Core, %[[VAL_817]] : Core) -// CHECK: aie.wire(%[[VAL_511]] : DMA, %[[VAL_817]] : DMA) -// CHECK: aie.wire(%[[VAL_816]] : North, %[[VAL_817]] : South) -// CHECK: aie.wire(%[[VAL_814]] : East, %[[VAL_818:.*]] : West) -// CHECK: aie.wire(%[[VAL_570]] : Core, %[[VAL_818]] : Core) -// CHECK: aie.wire(%[[VAL_570]] : DMA, %[[VAL_818]] : DMA) -// CHECK: aie.wire(%[[VAL_817]] : North, %[[VAL_818]] : South) -// CHECK: aie.wire(%[[VAL_815]] : East, %[[VAL_819:.*]] : West) -// CHECK: aie.wire(%[[VAL_625]] : Core, %[[VAL_819]] : Core) -// CHECK: aie.wire(%[[VAL_625]] : DMA, %[[VAL_819]] : DMA) -// CHECK: aie.wire(%[[VAL_816]] : East, %[[VAL_820:.*]] : West) -// CHECK: aie.wire(%[[VAL_817]] : East, %[[VAL_821:.*]] : West) -// CHECK: aie.wire(%[[VAL_513]] : Core, %[[VAL_821]] : Core) -// CHECK: aie.wire(%[[VAL_513]] : DMA, %[[VAL_821]] : DMA) -// CHECK: aie.wire(%[[VAL_820]] : North, %[[VAL_821]] : South) -// CHECK: aie.wire(%[[VAL_818]] : East, %[[VAL_822:.*]] : West) -// CHECK: aie.wire(%[[VAL_572]] : Core, %[[VAL_822]] : Core) -// CHECK: aie.wire(%[[VAL_572]] : DMA, %[[VAL_822]] : DMA) -// CHECK: aie.wire(%[[VAL_821]] : North, %[[VAL_822]] : South) -// CHECK: aie.wire(%[[VAL_819]] : East, %[[VAL_823:.*]] : West) -// CHECK: aie.wire(%[[VAL_627]] : Core, %[[VAL_823]] : Core) -// CHECK: aie.wire(%[[VAL_627]] : DMA, %[[VAL_823]] : DMA) -// CHECK: aie.wire(%[[VAL_820]] : East, %[[VAL_824:.*]] : West) -// CHECK: aie.wire(%[[VAL_825:.*]] : North, %[[VAL_824]] : South) -// CHECK: aie.wire(%[[VAL_101]] : DMA, %[[VAL_825]] : DMA) -// CHECK: aie.wire(%[[VAL_821]] : East, %[[VAL_826:.*]] : West) -// CHECK: aie.wire(%[[VAL_100]] : Core, %[[VAL_826]] : Core) -// CHECK: aie.wire(%[[VAL_100]] : DMA, %[[VAL_826]] : DMA) -// CHECK: aie.wire(%[[VAL_824]] : North, %[[VAL_826]] : South) -// CHECK: aie.wire(%[[VAL_822]] : East, %[[VAL_827:.*]] : West) -// CHECK: aie.wire(%[[VAL_99]] : Core, %[[VAL_827]] : Core) -// CHECK: aie.wire(%[[VAL_99]] : DMA, %[[VAL_827]] : DMA) -// CHECK: aie.wire(%[[VAL_826]] : North, %[[VAL_827]] : South) -// CHECK: aie.wire(%[[VAL_823]] : East, %[[VAL_828:.*]] : West) -// CHECK: aie.wire(%[[VAL_629]] : Core, %[[VAL_828]] : Core) -// CHECK: aie.wire(%[[VAL_629]] : DMA, %[[VAL_828]] : DMA) -// CHECK: aie.wire(%[[VAL_824]] : East, %[[VAL_829:.*]] : West) -// CHECK: aie.wire(%[[VAL_830:.*]] : North, %[[VAL_829]] : South) -// CHECK: aie.wire(%[[VAL_82]] : DMA, %[[VAL_830]] : DMA) -// CHECK: aie.wire(%[[VAL_826]] : East, %[[VAL_831:.*]] : West) -// CHECK: aie.wire(%[[VAL_81]] : Core, %[[VAL_831]] : Core) -// CHECK: aie.wire(%[[VAL_81]] : DMA, %[[VAL_831]] : DMA) -// CHECK: aie.wire(%[[VAL_829]] : North, %[[VAL_831]] : South) -// CHECK: aie.wire(%[[VAL_827]] : East, %[[VAL_832:.*]] : West) -// CHECK: aie.wire(%[[VAL_80]] : Core, %[[VAL_832]] : Core) -// CHECK: aie.wire(%[[VAL_80]] : DMA, %[[VAL_832]] : DMA) -// CHECK: aie.wire(%[[VAL_831]] : North, %[[VAL_832]] : South) -// CHECK: aie.wire(%[[VAL_828]] : East, %[[VAL_833:.*]] : West) -// CHECK: aie.wire(%[[VAL_631]] : Core, %[[VAL_833]] : Core) -// CHECK: aie.wire(%[[VAL_631]] : DMA, %[[VAL_833]] : DMA) -// CHECK: aie.wire(%[[VAL_829]] : East, %[[VAL_834:.*]] : West) -// CHECK: aie.wire(%[[VAL_832]] : East, %[[VAL_835:.*]] : West) -// CHECK: aie.wire(%[[VAL_576]] : Core, %[[VAL_835]] : Core) -// CHECK: aie.wire(%[[VAL_576]] : DMA, %[[VAL_835]] : DMA) -// CHECK: aie.wire(%[[VAL_833]] : East, %[[VAL_836:.*]] : West) -// CHECK: aie.wire(%[[VAL_633]] : Core, %[[VAL_836]] : Core) -// CHECK: aie.wire(%[[VAL_633]] : DMA, %[[VAL_836]] : DMA) -// CHECK: aie.wire(%[[VAL_834]] : East, %[[VAL_837:.*]] : West) -// CHECK: aie.wire(%[[VAL_835]] : East, %[[VAL_838:.*]] : West) -// CHECK: aie.wire(%[[VAL_578]] : Core, %[[VAL_838]] : Core) -// CHECK: aie.wire(%[[VAL_578]] : DMA, %[[VAL_838]] : DMA) -// CHECK: aie.wire(%[[VAL_836]] : East, %[[VAL_839:.*]] : West) -// CHECK: aie.wire(%[[VAL_635]] : Core, %[[VAL_839]] : Core) -// CHECK: aie.wire(%[[VAL_635]] : DMA, %[[VAL_839]] : DMA) -// CHECK: aie.wire(%[[VAL_837]] : East, %[[VAL_840:.*]] : West) -// CHECK: aie.wire(%[[VAL_838]] : East, %[[VAL_841:.*]] : West) -// CHECK: aie.wire(%[[VAL_580]] : Core, %[[VAL_841]] : Core) -// CHECK: aie.wire(%[[VAL_580]] : DMA, %[[VAL_841]] : DMA) -// CHECK: aie.wire(%[[VAL_839]] : East, %[[VAL_842:.*]] : West) -// CHECK: aie.wire(%[[VAL_637]] : Core, %[[VAL_842]] : Core) -// CHECK: aie.wire(%[[VAL_637]] : DMA, %[[VAL_842]] : DMA) -// CHECK: aie.wire(%[[VAL_840]] : East, %[[VAL_843:.*]] : West) -// CHECK: aie.wire(%[[VAL_841]] : East, %[[VAL_844:.*]] : West) -// CHECK: aie.wire(%[[VAL_582]] : Core, %[[VAL_844]] : Core) -// CHECK: aie.wire(%[[VAL_582]] : DMA, %[[VAL_844]] : DMA) -// CHECK: aie.wire(%[[VAL_842]] : East, %[[VAL_845:.*]] : West) -// CHECK: aie.wire(%[[VAL_639]] : Core, %[[VAL_845]] : Core) -// CHECK: aie.wire(%[[VAL_639]] : DMA, %[[VAL_845]] : DMA) -// CHECK: aie.wire(%[[VAL_843]] : East, %[[VAL_846:.*]] : West) -// CHECK: aie.wire(%[[VAL_844]] : East, %[[VAL_847:.*]] : West) -// CHECK: aie.wire(%[[VAL_584]] : Core, %[[VAL_847]] : Core) -// CHECK: aie.wire(%[[VAL_584]] : DMA, %[[VAL_847]] : DMA) -// CHECK: aie.wire(%[[VAL_845]] : East, %[[VAL_848:.*]] : West) -// CHECK: aie.wire(%[[VAL_641]] : Core, %[[VAL_848]] : Core) -// CHECK: aie.wire(%[[VAL_641]] : DMA, %[[VAL_848]] : DMA) -// CHECK: aie.wire(%[[VAL_846]] : East, %[[VAL_849:.*]] : West) -// CHECK: aie.wire(%[[VAL_586]] : Core, %[[VAL_850:.*]] : Core) -// CHECK: aie.wire(%[[VAL_586]] : DMA, %[[VAL_850]] : DMA) -// CHECK: aie.wire(%[[VAL_849]] : North, %[[VAL_850]] : South) -// CHECK: aie.wire(%[[VAL_847]] : East, %[[VAL_851:.*]] : West) -// CHECK: aie.wire(%[[VAL_588]] : Core, %[[VAL_851]] : Core) -// CHECK: aie.wire(%[[VAL_588]] : DMA, %[[VAL_851]] : DMA) -// CHECK: aie.wire(%[[VAL_850]] : North, %[[VAL_851]] : South) -// CHECK: aie.wire(%[[VAL_848]] : East, %[[VAL_852:.*]] : West) -// CHECK: aie.wire(%[[VAL_643]] : Core, %[[VAL_852]] : Core) -// CHECK: aie.wire(%[[VAL_643]] : DMA, %[[VAL_852]] : DMA) -// CHECK: aie.wire(%[[VAL_849]] : East, %[[VAL_853:.*]] : West) -// CHECK: aie.wire(%[[VAL_854:.*]] : North, %[[VAL_853]] : South) -// CHECK: aie.wire(%[[VAL_62]] : DMA, %[[VAL_854]] : DMA) -// CHECK: aie.wire(%[[VAL_850]] : East, %[[VAL_855:.*]] : West) -// CHECK: aie.wire(%[[VAL_61]] : Core, %[[VAL_855]] : Core) -// CHECK: aie.wire(%[[VAL_61]] : DMA, %[[VAL_855]] : DMA) -// CHECK: aie.wire(%[[VAL_853]] : North, %[[VAL_855]] : South) -// CHECK: aie.wire(%[[VAL_645]] : Core, %[[VAL_856:.*]] : Core) -// CHECK: aie.wire(%[[VAL_645]] : DMA, %[[VAL_856]] : DMA) -// CHECK: aie.wire(%[[VAL_852]] : East, %[[VAL_857:.*]] : West) -// CHECK: aie.wire(%[[VAL_647]] : Core, %[[VAL_857]] : Core) -// CHECK: aie.wire(%[[VAL_647]] : DMA, %[[VAL_857]] : DMA) -// CHECK: aie.wire(%[[VAL_856]] : North, %[[VAL_857]] : South) -// CHECK: aie.wire(%[[VAL_853]] : East, %[[VAL_858:.*]] : West) -// CHECK: aie.wire(%[[VAL_859:.*]] : North, %[[VAL_858]] : South) -// CHECK: aie.wire(%[[VAL_42]] : DMA, %[[VAL_859]] : DMA) -// CHECK: aie.wire(%[[VAL_856]] : East, %[[VAL_860:.*]] : West) -// CHECK: aie.wire(%[[VAL_649]] : Core, %[[VAL_860]] : Core) -// CHECK: aie.wire(%[[VAL_649]] : DMA, %[[VAL_860]] : DMA) -// CHECK: aie.wire(%[[VAL_858]] : East, %[[VAL_861:.*]] : West) -// CHECK: aie.wire(%[[VAL_860]] : East, %[[VAL_862:.*]] : West) -// CHECK: aie.wire(%[[VAL_651]] : Core, %[[VAL_862]] : Core) -// CHECK: aie.wire(%[[VAL_651]] : DMA, %[[VAL_862]] : DMA) -// CHECK: aie.wire(%[[VAL_861]] : East, %[[VAL_863:.*]] : West) -// CHECK: aie.wire(%[[VAL_653]] : Core, %[[VAL_864:.*]] : Core) -// CHECK: aie.wire(%[[VAL_653]] : DMA, %[[VAL_864]] : DMA) -// CHECK: aie.wire(%[[VAL_862]] : East, %[[VAL_865:.*]] : West) -// CHECK: aie.wire(%[[VAL_655]] : Core, %[[VAL_865]] : Core) -// CHECK: aie.wire(%[[VAL_655]] : DMA, %[[VAL_865]] : DMA) -// CHECK: aie.wire(%[[VAL_864]] : North, %[[VAL_865]] : South) -// CHECK: aie.wire(%[[VAL_863]] : East, %[[VAL_866:.*]] : West) -// CHECK: aie.wire(%[[VAL_867:.*]] : North, %[[VAL_866]] : South) -// CHECK: aie.wire(%[[VAL_22]] : DMA, %[[VAL_867]] : DMA) -// CHECK: aie.wire(%[[VAL_21]] : Core, %[[VAL_868:.*]] : Core) -// CHECK: aie.wire(%[[VAL_21]] : DMA, %[[VAL_868]] : DMA) -// CHECK: aie.wire(%[[VAL_866]] : North, %[[VAL_868]] : South) -// CHECK: aie.wire(%[[VAL_864]] : East, %[[VAL_869:.*]] : West) -// CHECK: aie.wire(%[[VAL_20]] : Core, %[[VAL_869]] : Core) -// CHECK: aie.wire(%[[VAL_20]] : DMA, %[[VAL_869]] : DMA) -// CHECK: aie.wire(%[[VAL_868]] : North, %[[VAL_869]] : South) -// CHECK: aie.wire(%[[VAL_866]] : East, %[[VAL_870:.*]] : West) -// CHECK: aie.wire(%[[VAL_871:.*]] : North, %[[VAL_870]] : South) -// CHECK: aie.wire(%[[VAL_2]] : DMA, %[[VAL_871]] : DMA) +// CHECK: aie.wire(%[[SHIM_MUX_2_0:.*]] : North, %[[SWITCHBOX_2_0:.*]] : South) +// CHECK: aie.wire(%[[TILE_2_0]] : DMA, %[[SHIM_MUX_2_0]] : DMA) +// CHECK: aie.wire(%[[TILE_2_1]] : Core, %[[SWITCHBOX_2_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_1]] : DMA, %[[SWITCHBOX_2_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : North, %[[SWITCHBOX_2_1]] : South) +// CHECK: aie.wire(%[[TILE_2_2]] : Core, %[[SWITCHBOX_2_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_2_2]] : DMA, %[[SWITCHBOX_2_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : North, %[[SWITCHBOX_2_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_0]] : East, %[[SWITCHBOX_3_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_3_0:.*]] : North, %[[SWITCHBOX_3_0]] : South) +// CHECK: aie.wire(%[[TILE_3_0]] : DMA, %[[SHIM_MUX_3_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_2_1]] : East, %[[SWITCHBOX_3_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_1]] : Core, %[[SWITCHBOX_3_1]] : Core) +// CHECK: aie.wire(%[[TILE_3_1]] : DMA, %[[SWITCHBOX_3_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : North, %[[SWITCHBOX_3_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_2_2]] : East, %[[SWITCHBOX_3_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_3_2]] : Core, %[[SWITCHBOX_3_2]] : Core) +// CHECK: aie.wire(%[[TILE_3_2]] : DMA, %[[SWITCHBOX_3_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_3_1]] : North, %[[SWITCHBOX_3_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_3_0]] : East, %[[SWITCHBOX_4_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_3_2]] : East, %[[SWITCHBOX_4_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_4_2]] : Core, %[[SWITCHBOX_4_2]] : Core) +// CHECK: aie.wire(%[[TILE_4_2]] : DMA, %[[SWITCHBOX_4_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_4_0]] : East, %[[SWITCHBOX_5_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_4_2]] : East, %[[SWITCHBOX_5_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_5_2]] : Core, %[[SWITCHBOX_5_2]] : Core) +// CHECK: aie.wire(%[[TILE_5_2]] : DMA, %[[SWITCHBOX_5_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_5_0]] : East, %[[SWITCHBOX_6_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_6_0:.*]] : North, %[[SWITCHBOX_6_0]] : South) +// CHECK: aie.wire(%[[TILE_6_0]] : DMA, %[[SHIM_MUX_6_0]] : DMA) +// CHECK: aie.wire(%[[TILE_6_1]] : Core, %[[SWITCHBOX_6_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_6_1]] : DMA, %[[SWITCHBOX_6_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : North, %[[SWITCHBOX_6_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_5_2]] : East, %[[SWITCHBOX_6_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_6_2]] : Core, %[[SWITCHBOX_6_2]] : Core) +// CHECK: aie.wire(%[[TILE_6_2]] : DMA, %[[SWITCHBOX_6_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : North, %[[SWITCHBOX_6_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_0]] : East, %[[SWITCHBOX_7_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_7_0:.*]] : North, %[[SWITCHBOX_7_0]] : South) +// CHECK: aie.wire(%[[TILE_7_0]] : DMA, %[[SHIM_MUX_7_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_6_1]] : East, %[[SWITCHBOX_7_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_1]] : Core, %[[SWITCHBOX_7_1]] : Core) +// CHECK: aie.wire(%[[TILE_7_1]] : DMA, %[[SWITCHBOX_7_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : North, %[[SWITCHBOX_7_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_6_2]] : East, %[[SWITCHBOX_7_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_7_2]] : Core, %[[SWITCHBOX_7_2]] : Core) +// CHECK: aie.wire(%[[TILE_7_2]] : DMA, %[[SWITCHBOX_7_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : North, %[[SWITCHBOX_7_2]] : South) +// CHECK: aie.wire(%[[TILE_7_3]] : Core, %[[SWITCHBOX_7_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_7_3]] : DMA, %[[SWITCHBOX_7_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : North, %[[SWITCHBOX_7_3]] : South) +// CHECK: aie.wire(%[[TILE_7_4]] : Core, %[[SWITCHBOX_7_4:.*]] : Core) +// CHECK: aie.wire(%[[TILE_7_4]] : DMA, %[[SWITCHBOX_7_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : North, %[[SWITCHBOX_7_4]] : South) +// CHECK: aie.wire(%[[TILE_7_5]] : Core, %[[SWITCHBOX_7_5:.*]] : Core) +// CHECK: aie.wire(%[[TILE_7_5]] : DMA, %[[SWITCHBOX_7_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : North, %[[SWITCHBOX_7_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_0]] : East, %[[SWITCHBOX_8_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_7_1]] : East, %[[SWITCHBOX_8_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_1]] : Core, %[[SWITCHBOX_8_1]] : Core) +// CHECK: aie.wire(%[[TILE_8_1]] : DMA, %[[SWITCHBOX_8_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_0]] : North, %[[SWITCHBOX_8_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_2]] : East, %[[SWITCHBOX_8_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_2]] : Core, %[[SWITCHBOX_8_2]] : Core) +// CHECK: aie.wire(%[[TILE_8_2]] : DMA, %[[SWITCHBOX_8_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : North, %[[SWITCHBOX_8_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_3]] : East, %[[SWITCHBOX_8_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_3]] : Core, %[[SWITCHBOX_8_3]] : Core) +// CHECK: aie.wire(%[[TILE_8_3]] : DMA, %[[SWITCHBOX_8_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : North, %[[SWITCHBOX_8_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_4]] : East, %[[SWITCHBOX_8_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_4]] : Core, %[[SWITCHBOX_8_4]] : Core) +// CHECK: aie.wire(%[[TILE_8_4]] : DMA, %[[SWITCHBOX_8_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : North, %[[SWITCHBOX_8_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_7_5]] : East, %[[SWITCHBOX_8_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_8_5]] : Core, %[[SWITCHBOX_8_5]] : Core) +// CHECK: aie.wire(%[[TILE_8_5]] : DMA, %[[SWITCHBOX_8_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_8_4]] : North, %[[SWITCHBOX_8_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_8_0]] : East, %[[SWITCHBOX_9_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_8_1]] : East, %[[SWITCHBOX_9_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_1]] : Core, %[[SWITCHBOX_9_1]] : Core) +// CHECK: aie.wire(%[[TILE_9_1]] : DMA, %[[SWITCHBOX_9_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_0]] : North, %[[SWITCHBOX_9_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_8_2]] : East, %[[SWITCHBOX_9_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_2]] : Core, %[[SWITCHBOX_9_2]] : Core) +// CHECK: aie.wire(%[[TILE_9_2]] : DMA, %[[SWITCHBOX_9_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_1]] : North, %[[SWITCHBOX_9_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_8_3]] : East, %[[SWITCHBOX_9_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_3]] : Core, %[[SWITCHBOX_9_3]] : Core) +// CHECK: aie.wire(%[[TILE_9_3]] : DMA, %[[SWITCHBOX_9_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : North, %[[SWITCHBOX_9_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_8_4]] : East, %[[SWITCHBOX_9_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_4]] : Core, %[[SWITCHBOX_9_4]] : Core) +// CHECK: aie.wire(%[[TILE_9_4]] : DMA, %[[SWITCHBOX_9_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_3]] : North, %[[SWITCHBOX_9_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_8_5]] : East, %[[SWITCHBOX_9_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_9_5]] : Core, %[[SWITCHBOX_9_5]] : Core) +// CHECK: aie.wire(%[[TILE_9_5]] : DMA, %[[SWITCHBOX_9_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_4]] : North, %[[SWITCHBOX_9_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_9_0]] : East, %[[SWITCHBOX_10_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_10_0:.*]] : North, %[[SWITCHBOX_10_0]] : South) +// CHECK: aie.wire(%[[TILE_10_0]] : DMA, %[[SHIM_MUX_10_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_9_1]] : East, %[[SWITCHBOX_10_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_1]] : Core, %[[SWITCHBOX_10_1]] : Core) +// CHECK: aie.wire(%[[TILE_10_1]] : DMA, %[[SWITCHBOX_10_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : North, %[[SWITCHBOX_10_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_9_2]] : East, %[[SWITCHBOX_10_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_2]] : Core, %[[SWITCHBOX_10_2]] : Core) +// CHECK: aie.wire(%[[TILE_10_2]] : DMA, %[[SWITCHBOX_10_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_1]] : North, %[[SWITCHBOX_10_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_9_3]] : East, %[[SWITCHBOX_10_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_3]] : Core, %[[SWITCHBOX_10_3]] : Core) +// CHECK: aie.wire(%[[TILE_10_3]] : DMA, %[[SWITCHBOX_10_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_2]] : North, %[[SWITCHBOX_10_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_9_4]] : East, %[[SWITCHBOX_10_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_4]] : Core, %[[SWITCHBOX_10_4]] : Core) +// CHECK: aie.wire(%[[TILE_10_4]] : DMA, %[[SWITCHBOX_10_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_3]] : North, %[[SWITCHBOX_10_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_9_5]] : East, %[[SWITCHBOX_10_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_10_5]] : Core, %[[SWITCHBOX_10_5]] : Core) +// CHECK: aie.wire(%[[TILE_10_5]] : DMA, %[[SWITCHBOX_10_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_4]] : North, %[[SWITCHBOX_10_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_0]] : East, %[[SWITCHBOX_11_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_11_0:.*]] : North, %[[SWITCHBOX_11_0]] : South) +// CHECK: aie.wire(%[[TILE_11_0]] : DMA, %[[SHIM_MUX_11_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_10_1]] : East, %[[SWITCHBOX_11_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_1]] : Core, %[[SWITCHBOX_11_1]] : Core) +// CHECK: aie.wire(%[[TILE_11_1]] : DMA, %[[SWITCHBOX_11_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_0]] : North, %[[SWITCHBOX_11_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_2]] : East, %[[SWITCHBOX_11_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_2]] : Core, %[[SWITCHBOX_11_2]] : Core) +// CHECK: aie.wire(%[[TILE_11_2]] : DMA, %[[SWITCHBOX_11_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_1]] : North, %[[SWITCHBOX_11_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_3]] : East, %[[SWITCHBOX_11_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_3]] : Core, %[[SWITCHBOX_11_3]] : Core) +// CHECK: aie.wire(%[[TILE_11_3]] : DMA, %[[SWITCHBOX_11_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_2]] : North, %[[SWITCHBOX_11_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_4]] : East, %[[SWITCHBOX_11_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_4]] : Core, %[[SWITCHBOX_11_4]] : Core) +// CHECK: aie.wire(%[[TILE_11_4]] : DMA, %[[SWITCHBOX_11_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_3]] : North, %[[SWITCHBOX_11_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_10_5]] : East, %[[SWITCHBOX_11_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_11_5]] : Core, %[[SWITCHBOX_11_5]] : Core) +// CHECK: aie.wire(%[[TILE_11_5]] : DMA, %[[SWITCHBOX_11_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_11_4]] : North, %[[SWITCHBOX_11_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_11_0]] : East, %[[SWITCHBOX_12_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_11_1]] : East, %[[SWITCHBOX_12_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_12_1]] : Core, %[[SWITCHBOX_12_1]] : Core) +// CHECK: aie.wire(%[[TILE_12_1]] : DMA, %[[SWITCHBOX_12_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_12_0]] : North, %[[SWITCHBOX_12_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_11_2]] : East, %[[SWITCHBOX_12_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_12_2]] : Core, %[[SWITCHBOX_12_2]] : Core) +// CHECK: aie.wire(%[[TILE_12_2]] : DMA, %[[SWITCHBOX_12_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_12_1]] : North, %[[SWITCHBOX_12_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_11_3]] : East, %[[SWITCHBOX_12_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_12_3]] : Core, %[[SWITCHBOX_12_3]] : Core) +// CHECK: aie.wire(%[[TILE_12_3]] : DMA, %[[SWITCHBOX_12_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_12_2]] : North, %[[SWITCHBOX_12_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_11_4]] : East, %[[SWITCHBOX_12_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_12_4]] : Core, %[[SWITCHBOX_12_4]] : Core) +// CHECK: aie.wire(%[[TILE_12_4]] : DMA, %[[SWITCHBOX_12_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_12_3]] : North, %[[SWITCHBOX_12_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_11_5]] : East, %[[SWITCHBOX_12_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_12_5]] : Core, %[[SWITCHBOX_12_5]] : Core) +// CHECK: aie.wire(%[[TILE_12_5]] : DMA, %[[SWITCHBOX_12_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_12_4]] : North, %[[SWITCHBOX_12_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_12_0]] : East, %[[SWITCHBOX_13_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_12_1]] : East, %[[SWITCHBOX_13_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_13_1]] : Core, %[[SWITCHBOX_13_1]] : Core) +// CHECK: aie.wire(%[[TILE_13_1]] : DMA, %[[SWITCHBOX_13_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_13_0]] : North, %[[SWITCHBOX_13_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_12_2]] : East, %[[SWITCHBOX_13_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_13_2]] : Core, %[[SWITCHBOX_13_2]] : Core) +// CHECK: aie.wire(%[[TILE_13_2]] : DMA, %[[SWITCHBOX_13_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_13_1]] : North, %[[SWITCHBOX_13_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_12_3]] : East, %[[SWITCHBOX_13_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_13_3]] : Core, %[[SWITCHBOX_13_3]] : Core) +// CHECK: aie.wire(%[[TILE_13_3]] : DMA, %[[SWITCHBOX_13_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_13_2]] : North, %[[SWITCHBOX_13_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_12_4]] : East, %[[SWITCHBOX_13_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_13_4]] : Core, %[[SWITCHBOX_13_4]] : Core) +// CHECK: aie.wire(%[[TILE_13_4]] : DMA, %[[SWITCHBOX_13_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_13_3]] : North, %[[SWITCHBOX_13_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_12_5]] : East, %[[SWITCHBOX_13_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_13_5]] : Core, %[[SWITCHBOX_13_5]] : Core) +// CHECK: aie.wire(%[[TILE_13_5]] : DMA, %[[SWITCHBOX_13_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_13_4]] : North, %[[SWITCHBOX_13_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_13_0]] : East, %[[SWITCHBOX_14_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_13_1]] : East, %[[SWITCHBOX_14_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_14_1]] : Core, %[[SWITCHBOX_14_1]] : Core) +// CHECK: aie.wire(%[[TILE_14_1]] : DMA, %[[SWITCHBOX_14_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_14_0]] : North, %[[SWITCHBOX_14_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_13_2]] : East, %[[SWITCHBOX_14_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_14_2]] : Core, %[[SWITCHBOX_14_2]] : Core) +// CHECK: aie.wire(%[[TILE_14_2]] : DMA, %[[SWITCHBOX_14_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_14_1]] : North, %[[SWITCHBOX_14_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_13_3]] : East, %[[SWITCHBOX_14_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_14_3]] : Core, %[[SWITCHBOX_14_3]] : Core) +// CHECK: aie.wire(%[[TILE_14_3]] : DMA, %[[SWITCHBOX_14_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_14_2]] : North, %[[SWITCHBOX_14_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_13_4]] : East, %[[SWITCHBOX_14_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_14_4]] : Core, %[[SWITCHBOX_14_4]] : Core) +// CHECK: aie.wire(%[[TILE_14_4]] : DMA, %[[SWITCHBOX_14_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_14_3]] : North, %[[SWITCHBOX_14_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_13_5]] : East, %[[SWITCHBOX_14_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_14_5]] : Core, %[[SWITCHBOX_14_5]] : Core) +// CHECK: aie.wire(%[[TILE_14_5]] : DMA, %[[SWITCHBOX_14_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_14_4]] : North, %[[SWITCHBOX_14_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_14_0]] : East, %[[SWITCHBOX_15_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_14_1]] : East, %[[SWITCHBOX_15_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_15_1]] : Core, %[[SWITCHBOX_15_1]] : Core) +// CHECK: aie.wire(%[[TILE_15_1]] : DMA, %[[SWITCHBOX_15_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_15_0]] : North, %[[SWITCHBOX_15_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_14_2]] : East, %[[SWITCHBOX_15_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_15_2]] : Core, %[[SWITCHBOX_15_2]] : Core) +// CHECK: aie.wire(%[[TILE_15_2]] : DMA, %[[SWITCHBOX_15_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_15_1]] : North, %[[SWITCHBOX_15_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_14_3]] : East, %[[SWITCHBOX_15_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_15_3]] : Core, %[[SWITCHBOX_15_3]] : Core) +// CHECK: aie.wire(%[[TILE_15_3]] : DMA, %[[SWITCHBOX_15_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_15_2]] : North, %[[SWITCHBOX_15_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_14_4]] : East, %[[SWITCHBOX_15_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_15_4]] : Core, %[[SWITCHBOX_15_4]] : Core) +// CHECK: aie.wire(%[[TILE_15_4]] : DMA, %[[SWITCHBOX_15_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_15_3]] : North, %[[SWITCHBOX_15_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_14_5]] : East, %[[SWITCHBOX_15_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_15_5]] : Core, %[[SWITCHBOX_15_5]] : Core) +// CHECK: aie.wire(%[[TILE_15_5]] : DMA, %[[SWITCHBOX_15_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_15_4]] : North, %[[SWITCHBOX_15_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_15_0]] : East, %[[SWITCHBOX_16_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_15_1]] : East, %[[SWITCHBOX_16_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_16_1]] : Core, %[[SWITCHBOX_16_1]] : Core) +// CHECK: aie.wire(%[[TILE_16_1]] : DMA, %[[SWITCHBOX_16_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_16_0]] : North, %[[SWITCHBOX_16_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_15_2]] : East, %[[SWITCHBOX_16_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_16_2]] : Core, %[[SWITCHBOX_16_2]] : Core) +// CHECK: aie.wire(%[[TILE_16_2]] : DMA, %[[SWITCHBOX_16_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_16_1]] : North, %[[SWITCHBOX_16_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_15_3]] : East, %[[SWITCHBOX_16_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_16_3]] : Core, %[[SWITCHBOX_16_3]] : Core) +// CHECK: aie.wire(%[[TILE_16_3]] : DMA, %[[SWITCHBOX_16_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_16_2]] : North, %[[SWITCHBOX_16_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_15_4]] : East, %[[SWITCHBOX_16_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_16_4]] : Core, %[[SWITCHBOX_16_4]] : Core) +// CHECK: aie.wire(%[[TILE_16_4]] : DMA, %[[SWITCHBOX_16_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_16_3]] : North, %[[SWITCHBOX_16_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_15_5]] : East, %[[SWITCHBOX_16_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_16_5]] : Core, %[[SWITCHBOX_16_5]] : Core) +// CHECK: aie.wire(%[[TILE_16_5]] : DMA, %[[SWITCHBOX_16_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_16_4]] : North, %[[SWITCHBOX_16_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_16_0]] : East, %[[SWITCHBOX_17_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_16_1]] : East, %[[SWITCHBOX_17_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_17_1]] : Core, %[[SWITCHBOX_17_1]] : Core) +// CHECK: aie.wire(%[[TILE_17_1]] : DMA, %[[SWITCHBOX_17_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_17_0]] : North, %[[SWITCHBOX_17_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_16_2]] : East, %[[SWITCHBOX_17_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_17_2]] : Core, %[[SWITCHBOX_17_2]] : Core) +// CHECK: aie.wire(%[[TILE_17_2]] : DMA, %[[SWITCHBOX_17_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_17_1]] : North, %[[SWITCHBOX_17_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_16_3]] : East, %[[SWITCHBOX_17_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_17_3]] : Core, %[[SWITCHBOX_17_3]] : Core) +// CHECK: aie.wire(%[[TILE_17_3]] : DMA, %[[SWITCHBOX_17_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_17_2]] : North, %[[SWITCHBOX_17_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_16_4]] : East, %[[SWITCHBOX_17_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_17_4]] : Core, %[[SWITCHBOX_17_4]] : Core) +// CHECK: aie.wire(%[[TILE_17_4]] : DMA, %[[SWITCHBOX_17_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_17_3]] : North, %[[SWITCHBOX_17_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_16_5]] : East, %[[SWITCHBOX_17_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_17_5]] : Core, %[[SWITCHBOX_17_5]] : Core) +// CHECK: aie.wire(%[[TILE_17_5]] : DMA, %[[SWITCHBOX_17_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_17_4]] : North, %[[SWITCHBOX_17_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_17_0]] : East, %[[SWITCHBOX_18_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_18_0:.*]] : North, %[[SWITCHBOX_18_0]] : South) +// CHECK: aie.wire(%[[TILE_18_0]] : DMA, %[[SHIM_MUX_18_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_17_1]] : East, %[[SWITCHBOX_18_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_18_1]] : Core, %[[SWITCHBOX_18_1]] : Core) +// CHECK: aie.wire(%[[TILE_18_1]] : DMA, %[[SWITCHBOX_18_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_18_0]] : North, %[[SWITCHBOX_18_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_17_2]] : East, %[[SWITCHBOX_18_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_18_2]] : Core, %[[SWITCHBOX_18_2]] : Core) +// CHECK: aie.wire(%[[TILE_18_2]] : DMA, %[[SWITCHBOX_18_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_18_1]] : North, %[[SWITCHBOX_18_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_17_3]] : East, %[[SWITCHBOX_18_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_18_3]] : Core, %[[SWITCHBOX_18_3]] : Core) +// CHECK: aie.wire(%[[TILE_18_3]] : DMA, %[[SWITCHBOX_18_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_18_2]] : North, %[[SWITCHBOX_18_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_17_4]] : East, %[[SWITCHBOX_18_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_18_4]] : Core, %[[SWITCHBOX_18_4]] : Core) +// CHECK: aie.wire(%[[TILE_18_4]] : DMA, %[[SWITCHBOX_18_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_18_3]] : North, %[[SWITCHBOX_18_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_17_5]] : East, %[[SWITCHBOX_18_5:.*]] : West) +// CHECK: aie.wire(%[[TILE_18_5]] : Core, %[[SWITCHBOX_18_5]] : Core) +// CHECK: aie.wire(%[[TILE_18_5]] : DMA, %[[SWITCHBOX_18_5]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_18_4]] : North, %[[SWITCHBOX_18_5]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_18_0]] : East, %[[SWITCHBOX_19_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_19_0:.*]] : North, %[[SWITCHBOX_19_0]] : South) +// CHECK: aie.wire(%[[TILE_19_0]] : DMA, %[[SHIM_MUX_19_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_18_1]] : East, %[[SWITCHBOX_19_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_19_1]] : Core, %[[SWITCHBOX_19_1]] : Core) +// CHECK: aie.wire(%[[TILE_19_1]] : DMA, %[[SWITCHBOX_19_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_19_0]] : North, %[[SWITCHBOX_19_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_18_2]] : East, %[[SWITCHBOX_19_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_19_2]] : Core, %[[SWITCHBOX_19_2]] : Core) +// CHECK: aie.wire(%[[TILE_19_2]] : DMA, %[[SWITCHBOX_19_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_19_1]] : North, %[[SWITCHBOX_19_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_18_3]] : East, %[[SWITCHBOX_19_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_19_3]] : Core, %[[SWITCHBOX_19_3]] : Core) +// CHECK: aie.wire(%[[TILE_19_3]] : DMA, %[[SWITCHBOX_19_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_19_2]] : North, %[[SWITCHBOX_19_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_18_4]] : East, %[[SWITCHBOX_19_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_19_4]] : Core, %[[SWITCHBOX_19_4]] : Core) +// CHECK: aie.wire(%[[TILE_19_4]] : DMA, %[[SWITCHBOX_19_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_19_3]] : North, %[[SWITCHBOX_19_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_19_0]] : East, %[[SWITCHBOX_20_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_19_1]] : East, %[[SWITCHBOX_20_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_20_1]] : Core, %[[SWITCHBOX_20_1]] : Core) +// CHECK: aie.wire(%[[TILE_20_1]] : DMA, %[[SWITCHBOX_20_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_20_0]] : North, %[[SWITCHBOX_20_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_19_2]] : East, %[[SWITCHBOX_20_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_20_2]] : Core, %[[SWITCHBOX_20_2]] : Core) +// CHECK: aie.wire(%[[TILE_20_2]] : DMA, %[[SWITCHBOX_20_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_20_1]] : North, %[[SWITCHBOX_20_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_19_3]] : East, %[[SWITCHBOX_20_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_20_3]] : Core, %[[SWITCHBOX_20_3]] : Core) +// CHECK: aie.wire(%[[TILE_20_3]] : DMA, %[[SWITCHBOX_20_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_20_2]] : North, %[[SWITCHBOX_20_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_19_4]] : East, %[[SWITCHBOX_20_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_20_4]] : Core, %[[SWITCHBOX_20_4]] : Core) +// CHECK: aie.wire(%[[TILE_20_4]] : DMA, %[[SWITCHBOX_20_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_20_3]] : North, %[[SWITCHBOX_20_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_20_0]] : East, %[[SWITCHBOX_21_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_20_1]] : East, %[[SWITCHBOX_21_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_21_1]] : Core, %[[SWITCHBOX_21_1]] : Core) +// CHECK: aie.wire(%[[TILE_21_1]] : DMA, %[[SWITCHBOX_21_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_21_0]] : North, %[[SWITCHBOX_21_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_20_2]] : East, %[[SWITCHBOX_21_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_21_2]] : Core, %[[SWITCHBOX_21_2]] : Core) +// CHECK: aie.wire(%[[TILE_21_2]] : DMA, %[[SWITCHBOX_21_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_21_1]] : North, %[[SWITCHBOX_21_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_20_3]] : East, %[[SWITCHBOX_21_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_21_3]] : Core, %[[SWITCHBOX_21_3]] : Core) +// CHECK: aie.wire(%[[TILE_21_3]] : DMA, %[[SWITCHBOX_21_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_21_2]] : North, %[[SWITCHBOX_21_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_20_4]] : East, %[[SWITCHBOX_21_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_21_4]] : Core, %[[SWITCHBOX_21_4]] : Core) +// CHECK: aie.wire(%[[TILE_21_4]] : DMA, %[[SWITCHBOX_21_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_21_3]] : North, %[[SWITCHBOX_21_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_21_0]] : East, %[[SWITCHBOX_22_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_21_1]] : East, %[[SWITCHBOX_22_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_22_1]] : Core, %[[SWITCHBOX_22_1]] : Core) +// CHECK: aie.wire(%[[TILE_22_1]] : DMA, %[[SWITCHBOX_22_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_22_0]] : North, %[[SWITCHBOX_22_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_21_2]] : East, %[[SWITCHBOX_22_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_22_2]] : Core, %[[SWITCHBOX_22_2]] : Core) +// CHECK: aie.wire(%[[TILE_22_2]] : DMA, %[[SWITCHBOX_22_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_22_1]] : North, %[[SWITCHBOX_22_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_21_3]] : East, %[[SWITCHBOX_22_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_22_3]] : Core, %[[SWITCHBOX_22_3]] : Core) +// CHECK: aie.wire(%[[TILE_22_3]] : DMA, %[[SWITCHBOX_22_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_22_2]] : North, %[[SWITCHBOX_22_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_21_4]] : East, %[[SWITCHBOX_22_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_22_4]] : Core, %[[SWITCHBOX_22_4]] : Core) +// CHECK: aie.wire(%[[TILE_22_4]] : DMA, %[[SWITCHBOX_22_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_22_3]] : North, %[[SWITCHBOX_22_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_22_0]] : East, %[[SWITCHBOX_23_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_22_1]] : East, %[[SWITCHBOX_23_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_23_1]] : Core, %[[SWITCHBOX_23_1]] : Core) +// CHECK: aie.wire(%[[TILE_23_1]] : DMA, %[[SWITCHBOX_23_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_23_0]] : North, %[[SWITCHBOX_23_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_22_2]] : East, %[[SWITCHBOX_23_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_23_2]] : Core, %[[SWITCHBOX_23_2]] : Core) +// CHECK: aie.wire(%[[TILE_23_2]] : DMA, %[[SWITCHBOX_23_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_23_1]] : North, %[[SWITCHBOX_23_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_22_3]] : East, %[[SWITCHBOX_23_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_23_3]] : Core, %[[SWITCHBOX_23_3]] : Core) +// CHECK: aie.wire(%[[TILE_23_3]] : DMA, %[[SWITCHBOX_23_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_23_2]] : North, %[[SWITCHBOX_23_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_22_4]] : East, %[[SWITCHBOX_23_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_23_4]] : Core, %[[SWITCHBOX_23_4]] : Core) +// CHECK: aie.wire(%[[TILE_23_4]] : DMA, %[[SWITCHBOX_23_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_23_3]] : North, %[[SWITCHBOX_23_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_23_0]] : East, %[[SWITCHBOX_24_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_23_1]] : East, %[[SWITCHBOX_24_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_24_1]] : Core, %[[SWITCHBOX_24_1]] : Core) +// CHECK: aie.wire(%[[TILE_24_1]] : DMA, %[[SWITCHBOX_24_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_24_0]] : North, %[[SWITCHBOX_24_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_23_2]] : East, %[[SWITCHBOX_24_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_24_2]] : Core, %[[SWITCHBOX_24_2]] : Core) +// CHECK: aie.wire(%[[TILE_24_2]] : DMA, %[[SWITCHBOX_24_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_24_1]] : North, %[[SWITCHBOX_24_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_23_3]] : East, %[[SWITCHBOX_24_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_24_3]] : Core, %[[SWITCHBOX_24_3]] : Core) +// CHECK: aie.wire(%[[TILE_24_3]] : DMA, %[[SWITCHBOX_24_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_24_2]] : North, %[[SWITCHBOX_24_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_23_4]] : East, %[[SWITCHBOX_24_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_24_4]] : Core, %[[SWITCHBOX_24_4]] : Core) +// CHECK: aie.wire(%[[TILE_24_4]] : DMA, %[[SWITCHBOX_24_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_24_3]] : North, %[[SWITCHBOX_24_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_24_0]] : East, %[[SWITCHBOX_25_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_24_1]] : East, %[[SWITCHBOX_25_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_25_1]] : Core, %[[SWITCHBOX_25_1]] : Core) +// CHECK: aie.wire(%[[TILE_25_1]] : DMA, %[[SWITCHBOX_25_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_25_0]] : North, %[[SWITCHBOX_25_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_24_2]] : East, %[[SWITCHBOX_25_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_25_2]] : Core, %[[SWITCHBOX_25_2]] : Core) +// CHECK: aie.wire(%[[TILE_25_2]] : DMA, %[[SWITCHBOX_25_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_25_1]] : North, %[[SWITCHBOX_25_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_24_3]] : East, %[[SWITCHBOX_25_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_25_3]] : Core, %[[SWITCHBOX_25_3]] : Core) +// CHECK: aie.wire(%[[TILE_25_3]] : DMA, %[[SWITCHBOX_25_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_25_2]] : North, %[[SWITCHBOX_25_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_24_4]] : East, %[[SWITCHBOX_25_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_25_4]] : Core, %[[SWITCHBOX_25_4]] : Core) +// CHECK: aie.wire(%[[TILE_25_4]] : DMA, %[[SWITCHBOX_25_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_25_3]] : North, %[[SWITCHBOX_25_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_25_0]] : East, %[[SWITCHBOX_26_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_26_0:.*]] : North, %[[SWITCHBOX_26_0]] : South) +// CHECK: aie.wire(%[[TILE_26_0]] : DMA, %[[SHIM_MUX_26_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_25_1]] : East, %[[SWITCHBOX_26_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_26_1]] : Core, %[[SWITCHBOX_26_1]] : Core) +// CHECK: aie.wire(%[[TILE_26_1]] : DMA, %[[SWITCHBOX_26_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_26_0]] : North, %[[SWITCHBOX_26_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_25_2]] : East, %[[SWITCHBOX_26_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_26_2]] : Core, %[[SWITCHBOX_26_2]] : Core) +// CHECK: aie.wire(%[[TILE_26_2]] : DMA, %[[SWITCHBOX_26_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_26_1]] : North, %[[SWITCHBOX_26_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_25_3]] : East, %[[SWITCHBOX_26_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_26_3]] : Core, %[[SWITCHBOX_26_3]] : Core) +// CHECK: aie.wire(%[[TILE_26_3]] : DMA, %[[SWITCHBOX_26_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_26_2]] : North, %[[SWITCHBOX_26_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_25_4]] : East, %[[SWITCHBOX_26_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_26_4]] : Core, %[[SWITCHBOX_26_4]] : Core) +// CHECK: aie.wire(%[[TILE_26_4]] : DMA, %[[SWITCHBOX_26_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_26_3]] : North, %[[SWITCHBOX_26_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_26_0]] : East, %[[SWITCHBOX_27_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_27_0:.*]] : North, %[[SWITCHBOX_27_0]] : South) +// CHECK: aie.wire(%[[TILE_27_0]] : DMA, %[[SHIM_MUX_27_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_26_1]] : East, %[[SWITCHBOX_27_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_27_1]] : Core, %[[SWITCHBOX_27_1]] : Core) +// CHECK: aie.wire(%[[TILE_27_1]] : DMA, %[[SWITCHBOX_27_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_27_0]] : North, %[[SWITCHBOX_27_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_26_2]] : East, %[[SWITCHBOX_27_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_27_2]] : Core, %[[SWITCHBOX_27_2]] : Core) +// CHECK: aie.wire(%[[TILE_27_2]] : DMA, %[[SWITCHBOX_27_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_27_1]] : North, %[[SWITCHBOX_27_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_26_4]] : East, %[[SWITCHBOX_27_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_27_4]] : Core, %[[SWITCHBOX_27_4]] : Core) +// CHECK: aie.wire(%[[TILE_27_4]] : DMA, %[[SWITCHBOX_27_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_27_0]] : East, %[[SWITCHBOX_28_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_27_1]] : East, %[[SWITCHBOX_28_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_28_1]] : Core, %[[SWITCHBOX_28_1]] : Core) +// CHECK: aie.wire(%[[TILE_28_1]] : DMA, %[[SWITCHBOX_28_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_28_0]] : North, %[[SWITCHBOX_28_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_27_2]] : East, %[[SWITCHBOX_28_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_28_2]] : Core, %[[SWITCHBOX_28_2]] : Core) +// CHECK: aie.wire(%[[TILE_28_2]] : DMA, %[[SWITCHBOX_28_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_28_1]] : North, %[[SWITCHBOX_28_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_27_4]] : East, %[[SWITCHBOX_28_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_28_4]] : Core, %[[SWITCHBOX_28_4]] : Core) +// CHECK: aie.wire(%[[TILE_28_4]] : DMA, %[[SWITCHBOX_28_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_28_0]] : East, %[[SWITCHBOX_29_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_28_1]] : East, %[[SWITCHBOX_29_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_29_1]] : Core, %[[SWITCHBOX_29_1]] : Core) +// CHECK: aie.wire(%[[TILE_29_1]] : DMA, %[[SWITCHBOX_29_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_29_0]] : North, %[[SWITCHBOX_29_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_28_2]] : East, %[[SWITCHBOX_29_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_29_2]] : Core, %[[SWITCHBOX_29_2]] : Core) +// CHECK: aie.wire(%[[TILE_29_2]] : DMA, %[[SWITCHBOX_29_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_29_1]] : North, %[[SWITCHBOX_29_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_28_4]] : East, %[[SWITCHBOX_29_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_29_4]] : Core, %[[SWITCHBOX_29_4]] : Core) +// CHECK: aie.wire(%[[TILE_29_4]] : DMA, %[[SWITCHBOX_29_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_29_0]] : East, %[[SWITCHBOX_30_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_29_1]] : East, %[[SWITCHBOX_30_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_30_1]] : Core, %[[SWITCHBOX_30_1]] : Core) +// CHECK: aie.wire(%[[TILE_30_1]] : DMA, %[[SWITCHBOX_30_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_30_0]] : North, %[[SWITCHBOX_30_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_29_2]] : East, %[[SWITCHBOX_30_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_30_2]] : Core, %[[SWITCHBOX_30_2]] : Core) +// CHECK: aie.wire(%[[TILE_30_2]] : DMA, %[[SWITCHBOX_30_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_30_1]] : North, %[[SWITCHBOX_30_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_29_4]] : East, %[[SWITCHBOX_30_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_30_4]] : Core, %[[SWITCHBOX_30_4]] : Core) +// CHECK: aie.wire(%[[TILE_30_4]] : DMA, %[[SWITCHBOX_30_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_30_0]] : East, %[[SWITCHBOX_31_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_30_1]] : East, %[[SWITCHBOX_31_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_31_1]] : Core, %[[SWITCHBOX_31_1]] : Core) +// CHECK: aie.wire(%[[TILE_31_1]] : DMA, %[[SWITCHBOX_31_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_31_0]] : North, %[[SWITCHBOX_31_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_30_2]] : East, %[[SWITCHBOX_31_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_31_2]] : Core, %[[SWITCHBOX_31_2]] : Core) +// CHECK: aie.wire(%[[TILE_31_2]] : DMA, %[[SWITCHBOX_31_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_31_1]] : North, %[[SWITCHBOX_31_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_30_4]] : East, %[[SWITCHBOX_31_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_31_4]] : Core, %[[SWITCHBOX_31_4]] : Core) +// CHECK: aie.wire(%[[TILE_31_4]] : DMA, %[[SWITCHBOX_31_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_31_0]] : East, %[[SWITCHBOX_32_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_31_1]] : East, %[[SWITCHBOX_32_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_32_1]] : Core, %[[SWITCHBOX_32_1]] : Core) +// CHECK: aie.wire(%[[TILE_32_1]] : DMA, %[[SWITCHBOX_32_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_32_0]] : North, %[[SWITCHBOX_32_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_31_2]] : East, %[[SWITCHBOX_32_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_32_2]] : Core, %[[SWITCHBOX_32_2]] : Core) +// CHECK: aie.wire(%[[TILE_32_2]] : DMA, %[[SWITCHBOX_32_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_32_1]] : North, %[[SWITCHBOX_32_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_31_4]] : East, %[[SWITCHBOX_32_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_32_4]] : Core, %[[SWITCHBOX_32_4]] : Core) +// CHECK: aie.wire(%[[TILE_32_4]] : DMA, %[[SWITCHBOX_32_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_32_0]] : East, %[[SWITCHBOX_33_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_32_1]] : East, %[[SWITCHBOX_33_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_33_1]] : Core, %[[SWITCHBOX_33_1]] : Core) +// CHECK: aie.wire(%[[TILE_33_1]] : DMA, %[[SWITCHBOX_33_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_33_0]] : North, %[[SWITCHBOX_33_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_32_2]] : East, %[[SWITCHBOX_33_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_33_2]] : Core, %[[SWITCHBOX_33_2]] : Core) +// CHECK: aie.wire(%[[TILE_33_2]] : DMA, %[[SWITCHBOX_33_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_33_1]] : North, %[[SWITCHBOX_33_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_32_4]] : East, %[[SWITCHBOX_33_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_33_4]] : Core, %[[SWITCHBOX_33_4]] : Core) +// CHECK: aie.wire(%[[TILE_33_4]] : DMA, %[[SWITCHBOX_33_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_33_0]] : East, %[[SWITCHBOX_34_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_34_0:.*]] : North, %[[SWITCHBOX_34_0]] : South) +// CHECK: aie.wire(%[[TILE_34_0]] : DMA, %[[SHIM_MUX_34_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_33_1]] : East, %[[SWITCHBOX_34_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_34_1]] : Core, %[[SWITCHBOX_34_1]] : Core) +// CHECK: aie.wire(%[[TILE_34_1]] : DMA, %[[SWITCHBOX_34_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_34_0]] : North, %[[SWITCHBOX_34_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_33_2]] : East, %[[SWITCHBOX_34_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_34_2]] : Core, %[[SWITCHBOX_34_2]] : Core) +// CHECK: aie.wire(%[[TILE_34_2]] : DMA, %[[SWITCHBOX_34_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_34_1]] : North, %[[SWITCHBOX_34_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_33_4]] : East, %[[SWITCHBOX_34_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_34_4]] : Core, %[[SWITCHBOX_34_4]] : Core) +// CHECK: aie.wire(%[[TILE_34_4]] : DMA, %[[SWITCHBOX_34_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_34_0]] : East, %[[SWITCHBOX_35_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_35_0:.*]] : North, %[[SWITCHBOX_35_0]] : South) +// CHECK: aie.wire(%[[TILE_35_0]] : DMA, %[[SHIM_MUX_35_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_34_1]] : East, %[[SWITCHBOX_35_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_35_1]] : Core, %[[SWITCHBOX_35_1]] : Core) +// CHECK: aie.wire(%[[TILE_35_1]] : DMA, %[[SWITCHBOX_35_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_35_0]] : North, %[[SWITCHBOX_35_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_34_2]] : East, %[[SWITCHBOX_35_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_35_2]] : Core, %[[SWITCHBOX_35_2]] : Core) +// CHECK: aie.wire(%[[TILE_35_2]] : DMA, %[[SWITCHBOX_35_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_35_1]] : North, %[[SWITCHBOX_35_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_34_4]] : East, %[[SWITCHBOX_35_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_35_4]] : Core, %[[SWITCHBOX_35_4]] : Core) +// CHECK: aie.wire(%[[TILE_35_4]] : DMA, %[[SWITCHBOX_35_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_35_0]] : East, %[[SWITCHBOX_36_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_35_2]] : East, %[[SWITCHBOX_36_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_36_2]] : Core, %[[SWITCHBOX_36_2]] : Core) +// CHECK: aie.wire(%[[TILE_36_2]] : DMA, %[[SWITCHBOX_36_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_35_4]] : East, %[[SWITCHBOX_36_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_36_4]] : Core, %[[SWITCHBOX_36_4]] : Core) +// CHECK: aie.wire(%[[TILE_36_4]] : DMA, %[[SWITCHBOX_36_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_36_0]] : East, %[[SWITCHBOX_37_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_36_2]] : East, %[[SWITCHBOX_37_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_37_2]] : Core, %[[SWITCHBOX_37_2]] : Core) +// CHECK: aie.wire(%[[TILE_37_2]] : DMA, %[[SWITCHBOX_37_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_36_4]] : East, %[[SWITCHBOX_37_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_37_4]] : Core, %[[SWITCHBOX_37_4]] : Core) +// CHECK: aie.wire(%[[TILE_37_4]] : DMA, %[[SWITCHBOX_37_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_37_0]] : East, %[[SWITCHBOX_38_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_37_2]] : East, %[[SWITCHBOX_38_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_38_2]] : Core, %[[SWITCHBOX_38_2]] : Core) +// CHECK: aie.wire(%[[TILE_38_2]] : DMA, %[[SWITCHBOX_38_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_37_4]] : East, %[[SWITCHBOX_38_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_38_4]] : Core, %[[SWITCHBOX_38_4]] : Core) +// CHECK: aie.wire(%[[TILE_38_4]] : DMA, %[[SWITCHBOX_38_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_38_0]] : East, %[[SWITCHBOX_39_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_38_2]] : East, %[[SWITCHBOX_39_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_39_2]] : Core, %[[SWITCHBOX_39_2]] : Core) +// CHECK: aie.wire(%[[TILE_39_2]] : DMA, %[[SWITCHBOX_39_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_38_4]] : East, %[[SWITCHBOX_39_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_39_4]] : Core, %[[SWITCHBOX_39_4]] : Core) +// CHECK: aie.wire(%[[TILE_39_4]] : DMA, %[[SWITCHBOX_39_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_39_0]] : East, %[[SWITCHBOX_40_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_39_2]] : East, %[[SWITCHBOX_40_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_40_2]] : Core, %[[SWITCHBOX_40_2]] : Core) +// CHECK: aie.wire(%[[TILE_40_2]] : DMA, %[[SWITCHBOX_40_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_39_4]] : East, %[[SWITCHBOX_40_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_40_4]] : Core, %[[SWITCHBOX_40_4]] : Core) +// CHECK: aie.wire(%[[TILE_40_4]] : DMA, %[[SWITCHBOX_40_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_40_0]] : East, %[[SWITCHBOX_41_0:.*]] : West) +// CHECK: aie.wire(%[[TILE_41_1]] : Core, %[[SWITCHBOX_41_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_41_1]] : DMA, %[[SWITCHBOX_41_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_41_0]] : North, %[[SWITCHBOX_41_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_40_2]] : East, %[[SWITCHBOX_41_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_41_2]] : Core, %[[SWITCHBOX_41_2]] : Core) +// CHECK: aie.wire(%[[TILE_41_2]] : DMA, %[[SWITCHBOX_41_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_41_1]] : North, %[[SWITCHBOX_41_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_40_4]] : East, %[[SWITCHBOX_41_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_41_4]] : Core, %[[SWITCHBOX_41_4]] : Core) +// CHECK: aie.wire(%[[TILE_41_4]] : DMA, %[[SWITCHBOX_41_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_41_0]] : East, %[[SWITCHBOX_42_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_42_0:.*]] : North, %[[SWITCHBOX_42_0]] : South) +// CHECK: aie.wire(%[[TILE_42_0]] : DMA, %[[SHIM_MUX_42_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_41_1]] : East, %[[SWITCHBOX_42_1:.*]] : West) +// CHECK: aie.wire(%[[TILE_42_1]] : Core, %[[SWITCHBOX_42_1]] : Core) +// CHECK: aie.wire(%[[TILE_42_1]] : DMA, %[[SWITCHBOX_42_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_42_0]] : North, %[[SWITCHBOX_42_1]] : South) +// CHECK: aie.wire(%[[TILE_42_3]] : Core, %[[SWITCHBOX_42_3:.*]] : Core) +// CHECK: aie.wire(%[[TILE_42_3]] : DMA, %[[SWITCHBOX_42_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_41_4]] : East, %[[SWITCHBOX_42_4:.*]] : West) +// CHECK: aie.wire(%[[TILE_42_4]] : Core, %[[SWITCHBOX_42_4]] : Core) +// CHECK: aie.wire(%[[TILE_42_4]] : DMA, %[[SWITCHBOX_42_4]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_42_3]] : North, %[[SWITCHBOX_42_4]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_42_0]] : East, %[[SWITCHBOX_43_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_43_0:.*]] : North, %[[SWITCHBOX_43_0]] : South) +// CHECK: aie.wire(%[[TILE_43_0]] : DMA, %[[SHIM_MUX_43_0]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_42_3]] : East, %[[SWITCHBOX_43_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_43_3]] : Core, %[[SWITCHBOX_43_3]] : Core) +// CHECK: aie.wire(%[[TILE_43_3]] : DMA, %[[SWITCHBOX_43_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_43_0]] : East, %[[SWITCHBOX_44_0:.*]] : West) +// CHECK: aie.wire(%[[SWITCHBOX_43_3]] : East, %[[SWITCHBOX_44_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_44_3]] : Core, %[[SWITCHBOX_44_3]] : Core) +// CHECK: aie.wire(%[[TILE_44_3]] : DMA, %[[SWITCHBOX_44_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_44_0]] : East, %[[SWITCHBOX_45_0:.*]] : West) +// CHECK: aie.wire(%[[TILE_45_2]] : Core, %[[SWITCHBOX_45_2:.*]] : Core) +// CHECK: aie.wire(%[[TILE_45_2]] : DMA, %[[SWITCHBOX_45_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_44_3]] : East, %[[SWITCHBOX_45_3:.*]] : West) +// CHECK: aie.wire(%[[TILE_45_3]] : Core, %[[SWITCHBOX_45_3]] : Core) +// CHECK: aie.wire(%[[TILE_45_3]] : DMA, %[[SWITCHBOX_45_3]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_45_2]] : North, %[[SWITCHBOX_45_3]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_45_0]] : East, %[[SWITCHBOX_46_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_46_0:.*]] : North, %[[SWITCHBOX_46_0]] : South) +// CHECK: aie.wire(%[[TILE_46_0]] : DMA, %[[SHIM_MUX_46_0]] : DMA) +// CHECK: aie.wire(%[[TILE_46_1]] : Core, %[[SWITCHBOX_46_1:.*]] : Core) +// CHECK: aie.wire(%[[TILE_46_1]] : DMA, %[[SWITCHBOX_46_1]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_46_0]] : North, %[[SWITCHBOX_46_1]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_45_2]] : East, %[[SWITCHBOX_46_2:.*]] : West) +// CHECK: aie.wire(%[[TILE_46_2]] : Core, %[[SWITCHBOX_46_2]] : Core) +// CHECK: aie.wire(%[[TILE_46_2]] : DMA, %[[SWITCHBOX_46_2]] : DMA) +// CHECK: aie.wire(%[[SWITCHBOX_46_1]] : North, %[[SWITCHBOX_46_2]] : South) +// CHECK: aie.wire(%[[SWITCHBOX_46_0]] : East, %[[SWITCHBOX_47_0:.*]] : West) +// CHECK: aie.wire(%[[SHIM_MUX_47_0:.*]] : North, %[[SWITCHBOX_47_0]] : South) +// CHECK: aie.wire(%[[TILE_47_0]] : DMA, %[[SHIM_MUX_47_0]] : DMA) // CHECK: } module @vecmul_4x4 { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/useLock_in_func.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/useLock_in_func.mlir index 2ed5c8daa..4ecbc0dc8 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/useLock_in_func.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/useLock_in_func.mlir @@ -1,18 +1,19 @@ -// RUN: iree-opt --aie-localize-locks --aie-standard-lowering="tilecol=1 tilerow=3" %s | FileCheck --check-prefix=CHECK %s +// RUN: iree-opt --aie-localize-locks --aie-standard-lowering %s | FileCheck %s -// CHECK: module @test attributes {llvm.target_triple = "aie"} { -// CHECK: func.func private @kernel(%arg0: index) { -// CHECK-NEXT: %0 = arith.index_cast %arg0 : index to i32 -// CHECK-NEXT: %c0_i32 = arith.constant 0 : i32 -// CHECK-NEXT: call @llvm.aie.lock.acquire.reg(%0, %c0_i32) : (i32, i32) -> () -// CHECK-NEXT: return -// CHECK: } -// CHECK: func.func @core_1_3() { -// CHECK: %c48 = arith.constant 48 : index -// CHECK: call @kernel(%c48) : (index) -> () -// CHECK: return -// CHECK: } -// CHECK: } +// CHECK-LABEL: module @test attributes {llvm.target_triple = "aie"} { +// CHECK-LABEL: func.func private @kernel( +// CHECK-SAME: %[[ARG0:.*]]: index) { +// CHECK: %[[VAL_0:.*]] = arith.index_cast %[[ARG0]] : index to i32 +// CHECK: %[[C0_I32:.*]] = arith.constant 0 : i32 +// CHECK: call @llvm.aie.lock.acquire.reg(%[[VAL_0]], %[[C0_I32]]) : (i32, i32) -> () +// CHECK: return +// CHECK: } + +// CHECK-LABEL: func.func @core_1_3() { +// CHECK: %[[C48:.*]] = arith.constant 48 : index +// CHECK: call @kernel(%[[C48]]) : (index) -> () +// CHECK: return +// CHECK: } module @test { aie.device(xcvc1902) { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/user_assigned.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/user_assigned.mlir index 76e5858c8..2a08f9f11 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/user_assigned.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/user_assigned.mlir @@ -1,31 +1,71 @@ -//===- basic.mlir ----------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// (c) Copyright 2024 Advanced Micro Devices Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-assign-bd-ids --split-input-file %s | FileCheck %s // CHECK-LABEL: aie.device(npu1_4col) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "double_buffer"} : memref<32xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_1]]) : memref<32xi32> -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>, 0) {bd_id = 0 : i32, next_bd_id = 1 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 1 : i32, next_bd_id = 2 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 2 : i32, next_bd_id = 0 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>, 0) {bd_id = 3 : i32, next_bd_id = 4 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 4 : i32, next_bd_id = 5 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 5 : i32, next_bd_id = 3 : i32} -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 0 : i32} -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 1 : i32} -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 24 : i32} -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 25 : i32} +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[DOUBLE_BUFFER:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "double_buffer"} : memref<32xi32> +// CHECK: %[[BUFFER_0_1:.*]] = aie.buffer(%[[TILE_0_1]]) : memref<32xi32> +// CHECK: %[[LOCK_X:.*]] = aie.lock(%[[TILE_0_2]]) {init = 1 : i32, sym_name = "lock_X"} +// CHECK: %[[LOCK_Y:.*]] = aie.lock(%[[TILE_0_2]]) {init = 0 : i32, sym_name = "lock_Y"} +// CHECK: %[[MEM_0_2:.*]] = aie.mem(%[[TILE_0_2]]) { +// CHECK: %[[PLAYER_A:.*]] = aie.dma(S2MM, 0) {sym_name = "player_a"} [{ +// CHECK: aie.use_lock(%[[LOCK_Y]], Acquire, 0) +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>, 0) {bd_id = 0 : i32, next_bd_id = 1 : i32} +// CHECK: aie.use_lock(%[[LOCK_Y]], Release, 0) +// CHECK: }, { +// CHECK: aie.use_lock(%[[LOCK_X]], Acquire, 1) +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>) {bd_id = 1 : i32, next_bd_id = 2 : i32} +// CHECK: aie.use_lock(%[[LOCK_X]], Release, -1) +// CHECK: }, { +// CHECK: aie.use_lock(%[[LOCK_Y]], Acquire) {acq_en = false} +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>) {bd_id = 2 : i32, next_bd_id = 0 : i32} +// CHECK: aie.use_lock(%[[LOCK_Y]], Release, 1) +// CHECK: }] +// CHECK: %[[PLAYER_B:.*]] = aie.dma(S2MM, 1) {sym_name = "player_b"} [{ +// CHECK: aie.use_lock(%[[LOCK_Y]], Acquire, 1) +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>, 0) {bd_id = 3 : i32, next_bd_id = 4 : i32} +// CHECK: aie.use_lock(%[[LOCK_Y]], Release, 0) +// CHECK: }, { +// CHECK: aie.use_lock(%[[LOCK_X]], Acquire, 1) +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>) {bd_id = 4 : i32, next_bd_id = 5 : i32} +// CHECK: aie.use_lock(%[[LOCK_X]], Release, -1) +// CHECK: }, { +// CHECK: aie.use_lock(%[[LOCK_Y]], Acquire) {acq_en = false} +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>) {bd_id = 5 : i32, next_bd_id = 3 : i32} +// CHECK: aie.use_lock(%[[LOCK_Y]], Release, -1) +// CHECK: }] +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEMTILE_DMA_0_1:.*]] = aie.memtile_dma(%[[TILE_0_1]]) { +// CHECK: %[[LOCK_0_1:.*]] = aie.lock(%[[TILE_0_1]]) {init = 1 : i32} +// CHECK: %[[LOCK_0_1_0:.*]] = aie.lock(%[[TILE_0_1]]) {init = 0 : i32} +// CHECK: %[[VAL_0:.*]] = aie.dma(S2MM, 0) {loop = false, repeat_count = 10 : i32} [{ +// CHECK: aie.use_lock(%[[LOCK_0_1]], AcquireGreaterEqual) +// CHECK: aie.dma_bd(%[[BUFFER_0_1]] : memref<32xi32>) {bd_id = 0 : i32} +// CHECK: aie.use_lock(%[[LOCK_0_1_0]], Release) +// CHECK: }] +// CHECK: %[[VAL_1:.*]] = aie.dma(MM2S, 0) {loop = false, repeat_count = 10 : i32} [{ +// CHECK: aie.use_lock(%[[LOCK_0_1_0]], AcquireGreaterEqual) +// CHECK: aie.dma_bd(%[[BUFFER_0_1]] : memref<32xi32>) {bd_id = 1 : i32} +// CHECK: aie.use_lock(%[[LOCK_0_1]], Release) +// CHECK: }] +// CHECK: %[[LOCK_0_1_1:.*]] = aie.lock(%[[TILE_0_1]]) {init = 1 : i32} +// CHECK: %[[LOCK_0_1_2:.*]] = aie.lock(%[[TILE_0_1]]) {init = 0 : i32} +// CHECK: %[[VAL_2:.*]] = aie.dma(S2MM, 1) {loop = false, repeat_count = 10 : i32} [{ +// CHECK: aie.use_lock(%[[LOCK_0_1_1]], AcquireGreaterEqual) +// CHECK: aie.dma_bd(%[[BUFFER_0_1]] : memref<32xi32>) {bd_id = 24 : i32} +// CHECK: aie.use_lock(%[[LOCK_0_1_2]], Release) +// CHECK: }] +// CHECK: %[[VAL_3:.*]] = aie.dma(MM2S, 1) {loop = false, repeat_count = 10 : i32} [{ +// CHECK: aie.use_lock(%[[LOCK_0_1_2]], AcquireGreaterEqual) +// CHECK: aie.dma_bd(%[[BUFFER_0_1]] : memref<32xi32>) {bd_id = 25 : i32} +// CHECK: aie.use_lock(%[[LOCK_0_1_1]], Release) +// CHECK: }] +// CHECK: aie.end +// CHECK: } +// CHECK: } module { aie.device(npu1_4col) { @@ -98,25 +138,55 @@ module { // ----- // CHECK-LABEL: aie.device(xcve2302) { -// CHECK: %[[VAL_0:.*]] = aie.tile(2, 1) -// CHECK: %[[VAL_1:.*]] = aie.buffer(%[[VAL_0]]) {address = 8192 : i32, sym_name = "in"} : memref<16xi32> -// CHECK: %[[VAL_2:.*]] = aie.buffer(%[[VAL_0]]) {address = 1824 : i32, sym_name = "out"} : memref<16xi32> -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<16xi32>, 0, 128, [, , , ]) {bd_id = 0 : i32, next_bd_id = 0 : i32} -// CHECK: aie.dma_bd(%[[VAL_1]] : memref<16xi32>, 0, 16) {bd_id = 24 : i32, next_bd_id = 24 : i32} -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) {bd_id = 25 : i32, next_bd_id = 25 : i32} -// CHECK: aie.dma_bd(%[[VAL_2]] : memref<16xi32>, 0, 16) {bd_id = 1 : i32, next_bd_id = 1 : i32} +// CHECK: %[[TILE_2_1:.*]] = aie.tile(2, 1) +// CHECK: %[[IN:.*]] = aie.buffer(%[[TILE_2_1]]) {address = 8192 : i32, sym_name = "in"} : memref<16xi32> +// CHECK: %[[OUT:.*]] = aie.buffer(%[[TILE_2_1]]) {address = 1824 : i32, sym_name = "out"} : memref<16xi32> +// CHECK: %[[LOCK_2_1:.*]] = aie.lock(%[[TILE_2_1]], 0) {init = 1 : i32} +// CHECK: %[[LOCK_2_1_0:.*]] = aie.lock(%[[TILE_2_1]], 1) +// CHECK: %[[LOCK_2_1_1:.*]] = aie.lock(%[[TILE_2_1]], 2) {init = 1 : i32} +// CHECK: %[[LOCK_2_1_2:.*]] = aie.lock(%[[TILE_2_1]], 3) +// CHECK: %[[MEMTILE_DMA_2_1:.*]] = aie.memtile_dma(%[[TILE_2_1]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(S2MM, 0, ^bb4, ^bb1) +// CHECK: ^bb1: +// CHECK: %[[VAL_1:.*]] = aie.dma_start(MM2S, 1, ^bb5, ^bb2) +// CHECK: ^bb2: +// CHECK: %[[VAL_2:.*]] = aie.dma_start(S2MM, 1, ^bb6, ^bb3) +// CHECK: ^bb3: +// CHECK: %[[VAL_3:.*]] = aie.dma_start(MM2S, 0, ^bb7, ^bb8) +// CHECK: ^bb4: +// CHECK: aie.use_lock(%[[LOCK_2_1]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN]] : memref<16xi32>, 0, 128, [, , , ]) {bd_id = 0 : i32, next_bd_id = 0 : i32} +// CHECK: aie.use_lock(%[[LOCK_2_1_0]], Release, 1) +// CHECK: aie.next_bd ^bb4 +// CHECK: ^bb5: +// CHECK: aie.use_lock(%[[LOCK_2_1_0]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[IN]] : memref<16xi32>, 0, 16) {bd_id = 24 : i32, next_bd_id = 24 : i32} +// CHECK: aie.use_lock(%[[LOCK_2_1]], Release, 1) +// CHECK: aie.next_bd ^bb5 +// CHECK: ^bb6: +// CHECK: aie.use_lock(%[[LOCK_2_1_1]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OUT]] : memref<16xi32>, 0, 16) {bd_id = 25 : i32, next_bd_id = 25 : i32} +// CHECK: aie.use_lock(%[[LOCK_2_1_2]], Release, 1) +// CHECK: aie.next_bd ^bb6 +// CHECK: ^bb7: +// CHECK: aie.use_lock(%[[LOCK_2_1_2]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OUT]] : memref<16xi32>, 0, 16) {bd_id = 1 : i32, next_bd_id = 1 : i32} +// CHECK: aie.use_lock(%[[LOCK_2_1_1]], Release, 1) +// CHECK: aie.next_bd ^bb7 +// CHECK: ^bb8: +// CHECK: aie.end +// CHECK: } +// CHECK: } module @aie_module { aie.device(xcve2302) { %t01 = aie.tile(2, 1) %buf01_0 = aie.buffer(%t01) { address = 8192 : i32, sym_name = "in" } : memref<16xi32> %buf01_1 = aie.buffer(%t01) { address = 1824 : i32, sym_name = "out" } : memref<16xi32> - %l01_0 = aie.lock(%t01, 0) { init = 1 : i32 } %l01_1 = aie.lock(%t01, 1) %l01_2 = aie.lock(%t01, 2) { init = 1 : i32 } %l01_3 = aie.lock(%t01, 3) - %m01 = aie.memtile_dma(%t01) { %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^dma0) ^dma0: @@ -154,21 +224,70 @@ module @aie_module { // ----- // CHECK-LABEL: aie.device(npu1_4col) { -// CHECK: %[[VAL_0:.*]] = aie.tile(0, 0) -// CHECK: %[[VAL_1:.*]] = aie.tile(0, 1) -// CHECK: %[[VAL_2:.*]] = aie.tile(0, 2) -// CHECK: %[[VAL_3:.*]] = aie.buffer(%[[VAL_2]]) {sym_name = "double_buffer"} : memref<32xi32> -// CHECK: %[[VAL_4:.*]] = aie.buffer(%[[VAL_1]]) : memref<32xi32> -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>, 0) {bd_id = 5 : i32, next_bd_id = 4 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 4 : i32, next_bd_id = 3 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 3 : i32, next_bd_id = 5 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>, 0) {bd_id = 2 : i32, next_bd_id = 1 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 1 : i32, next_bd_id = 0 : i32} -// CHECK: aie.dma_bd(%[[VAL_3]] : memref<32xi32>) {bd_id = 0 : i32, next_bd_id = 2 : i32} -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 0 : i32} -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 1 : i32} -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 24 : i32} -// CHECK: aie.dma_bd(%[[VAL_4]] : memref<32xi32>) {bd_id = 25 : i32} +// CHECK: %[[TILE_0_0:.*]] = aie.tile(0, 0) +// CHECK: %[[TILE_0_1:.*]] = aie.tile(0, 1) +// CHECK: %[[TILE_0_2:.*]] = aie.tile(0, 2) +// CHECK: %[[DOUBLE_BUFFER:.*]] = aie.buffer(%[[TILE_0_2]]) {sym_name = "double_buffer"} : memref<32xi32> +// CHECK: %[[BUFFER_0_1:.*]] = aie.buffer(%[[TILE_0_1]]) : memref<32xi32> +// CHECK: %[[LOCK_X:.*]] = aie.lock(%[[TILE_0_2]]) {init = 1 : i32, sym_name = "lock_X"} +// CHECK: %[[LOCK_Y:.*]] = aie.lock(%[[TILE_0_2]]) {init = 0 : i32, sym_name = "lock_Y"} +// CHECK: %[[MEM_0_2:.*]] = aie.mem(%[[TILE_0_2]]) { +// CHECK: %[[PLAYER_A:.*]] = aie.dma(S2MM, 0) {sym_name = "player_a"} [{ +// CHECK: aie.use_lock(%[[LOCK_Y]], Acquire, 0) +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>, 0) {bd_id = 5 : i32, next_bd_id = 4 : i32} +// CHECK: aie.use_lock(%[[LOCK_Y]], Release, 0) +// CHECK: }, { +// CHECK: aie.use_lock(%[[LOCK_X]], Acquire, 1) +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>) {bd_id = 4 : i32, next_bd_id = 3 : i32} +// CHECK: aie.use_lock(%[[LOCK_X]], Release, -1) +// CHECK: }, { +// CHECK: aie.use_lock(%[[LOCK_Y]], Acquire) {acq_en = false} +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>) {bd_id = 3 : i32, next_bd_id = 5 : i32} +// CHECK: aie.use_lock(%[[LOCK_Y]], Release, 1) +// CHECK: }] +// CHECK: %[[PLAYER_B:.*]] = aie.dma(S2MM, 1) {sym_name = "player_b"} [{ +// CHECK: aie.use_lock(%[[LOCK_Y]], Acquire, 1) +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>, 0) {bd_id = 2 : i32, next_bd_id = 1 : i32} +// CHECK: aie.use_lock(%[[LOCK_Y]], Release, 0) +// CHECK: }, { +// CHECK: aie.use_lock(%[[LOCK_X]], Acquire, 1) +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>) {bd_id = 1 : i32, next_bd_id = 0 : i32} +// CHECK: aie.use_lock(%[[LOCK_X]], Release, -1) +// CHECK: }, { +// CHECK: aie.use_lock(%[[LOCK_Y]], Acquire) {acq_en = false} +// CHECK: aie.dma_bd(%[[DOUBLE_BUFFER]] : memref<32xi32>) {bd_id = 0 : i32, next_bd_id = 2 : i32} +// CHECK: aie.use_lock(%[[LOCK_Y]], Release, -1) +// CHECK: }] +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEMTILE_DMA_0_1:.*]] = aie.memtile_dma(%[[TILE_0_1]]) { +// CHECK: %[[LOCK_0_1:.*]] = aie.lock(%[[TILE_0_1]]) {init = 1 : i32} +// CHECK: %[[LOCK_0_1_0:.*]] = aie.lock(%[[TILE_0_1]]) {init = 0 : i32} +// CHECK: %[[VAL_0:.*]] = aie.dma(S2MM, 0) {loop = false, repeat_count = 10 : i32} [{ +// CHECK: aie.use_lock(%[[LOCK_0_1]], AcquireGreaterEqual) +// CHECK: aie.dma_bd(%[[BUFFER_0_1]] : memref<32xi32>) {bd_id = 0 : i32} +// CHECK: aie.use_lock(%[[LOCK_0_1_0]], Release) +// CHECK: }] +// CHECK: %[[VAL_1:.*]] = aie.dma(MM2S, 0) {loop = false, repeat_count = 10 : i32} [{ +// CHECK: aie.use_lock(%[[LOCK_0_1_0]], AcquireGreaterEqual) +// CHECK: aie.dma_bd(%[[BUFFER_0_1]] : memref<32xi32>) {bd_id = 1 : i32} +// CHECK: aie.use_lock(%[[LOCK_0_1]], Release) +// CHECK: }] +// CHECK: %[[LOCK_0_1_1:.*]] = aie.lock(%[[TILE_0_1]]) {init = 1 : i32} +// CHECK: %[[LOCK_0_1_2:.*]] = aie.lock(%[[TILE_0_1]]) {init = 0 : i32} +// CHECK: %[[VAL_2:.*]] = aie.dma(S2MM, 1) {loop = false, repeat_count = 10 : i32} [{ +// CHECK: aie.use_lock(%[[LOCK_0_1_1]], AcquireGreaterEqual) +// CHECK: aie.dma_bd(%[[BUFFER_0_1]] : memref<32xi32>) {bd_id = 24 : i32} +// CHECK: aie.use_lock(%[[LOCK_0_1_2]], Release) +// CHECK: }] +// CHECK: %[[VAL_3:.*]] = aie.dma(MM2S, 1) {loop = false, repeat_count = 10 : i32} [{ +// CHECK: aie.use_lock(%[[LOCK_0_1_2]], AcquireGreaterEqual) +// CHECK: aie.dma_bd(%[[BUFFER_0_1]] : memref<32xi32>) {bd_id = 25 : i32} +// CHECK: aie.use_lock(%[[LOCK_0_1_1]], Release) +// CHECK: }] +// CHECK: aie.end +// CHECK: } +// CHECK: } module { aie.device(npu1_4col) { diff --git a/compiler/plugins/target/AMD-AIE/aie/aie_passes/via_DMA_test.mlir b/compiler/plugins/target/AMD-AIE/aie/aie_passes/via_DMA_test.mlir index 3934fbd0f..76d76e700 100644 --- a/compiler/plugins/target/AMD-AIE/aie/aie_passes/via_DMA_test.mlir +++ b/compiler/plugins/target/AMD-AIE/aie/aie_passes/via_DMA_test.mlir @@ -1,73 +1,61 @@ -//===- via_DMA_test.mlir ---------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2024, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// // RUN: iree-opt --aie-objectFifo-stateful-transform %s | FileCheck %s -// CHECK: module @viaDMA { -// CHECK: aie.device(xcve2302) { -// CHECK: memref.global "public" @of_stream_cons : memref<16xi32> -// CHECK: memref.global "public" @of_stream : memref<16xi32> -// CHECK: memref.global "public" @of_shared : memref<16xi32> -// CHECK: %tile_1_2 = aie.tile(1, 2) -// CHECK: %tile_1_3 = aie.tile(1, 3) -// CHECK: %of_stream_cons_buff_0 = aie.buffer(%tile_1_3) {sym_name = "of_stream_cons_buff_0"} : memref<16xi32> -// CHECK: %of_stream_cons_buff_1 = aie.buffer(%tile_1_3) {sym_name = "of_stream_cons_buff_1"} : memref<16xi32> -// CHECK: %of_stream_cons_prod_lock = aie.lock(%tile_1_3, 0) {init = 2 : i32, sym_name = "of_stream_cons_prod_lock"} -// CHECK: %of_stream_cons_cons_lock = aie.lock(%tile_1_3, 1) {init = 0 : i32, sym_name = "of_stream_cons_cons_lock"} -// CHECK: %of_stream_buff_0 = aie.buffer(%tile_1_2) {sym_name = "of_stream_buff_0"} : memref<16xi32> -// CHECK: %of_stream_buff_1 = aie.buffer(%tile_1_2) {sym_name = "of_stream_buff_1"} : memref<16xi32> -// CHECK: %of_stream_prod_lock = aie.lock(%tile_1_2, 2) {init = 2 : i32, sym_name = "of_stream_prod_lock"} -// CHECK: %of_stream_cons_lock = aie.lock(%tile_1_2, 3) {init = 0 : i32, sym_name = "of_stream_cons_lock"} -// CHECK: %of_shared_buff_0 = aie.buffer(%tile_1_2) {sym_name = "of_shared_buff_0"} : memref<16xi32> -// CHECK: %of_shared_buff_1 = aie.buffer(%tile_1_2) {sym_name = "of_shared_buff_1"} : memref<16xi32> -// CHECK: %of_shared_prod_lock = aie.lock(%tile_1_2, 0) {init = 2 : i32, sym_name = "of_shared_prod_lock"} -// CHECK: %of_shared_cons_lock = aie.lock(%tile_1_2, 1) {init = 0 : i32, sym_name = "of_shared_cons_lock"} -// CHECK: aie.flow(%tile_1_2, DMA : 0, %tile_1_3, DMA : 0) -// CHECK: %mem_1_2 = aie.mem(%tile_1_2) { -// CHECK: %0 = aie.dma_start(MM2S, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%of_stream_cons_lock, AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%of_stream_buff_0 : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%of_stream_prod_lock, Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%of_stream_cons_lock, AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%of_stream_buff_1 : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%of_stream_prod_lock, Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: %mem_1_3 = aie.mem(%tile_1_3) { -// CHECK: %0 = aie.dma_start(S2MM, 0, ^bb1, ^bb3) -// CHECK: ^bb1: // 2 preds: ^bb0, ^bb2 -// CHECK: aie.use_lock(%of_stream_cons_prod_lock, AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%of_stream_cons_buff_0 : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%of_stream_cons_cons_lock, Release, 1) -// CHECK: aie.next_bd ^bb2 -// CHECK: ^bb2: // pred: ^bb1 -// CHECK: aie.use_lock(%of_stream_cons_prod_lock, AcquireGreaterEqual, 1) -// CHECK: aie.dma_bd(%of_stream_cons_buff_1 : memref<16xi32>, 0, 16) -// CHECK: aie.use_lock(%of_stream_cons_cons_lock, Release, 1) -// CHECK: aie.next_bd ^bb1 -// CHECK: ^bb3: // pred: ^bb0 -// CHECK: aie.end -// CHECK: } -// CHECK: } -// CHECK: } +// CHECK-LABEL: aie.device(xcve2302) { +// CHECK: memref.global "public" @of_stream_cons : memref<16xi32> +// CHECK: memref.global "public" @of_stream : memref<16xi32> +// CHECK: memref.global "public" @of_shared : memref<16xi32> +// CHECK: %[[TILE_1_2:.*]] = aie.tile(1, 2) +// CHECK: %[[TILE_1_3:.*]] = aie.tile(1, 3) +// CHECK: %[[OF_STREAM_CONS_BUFF_0:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of_stream_cons_buff_0"} : memref<16xi32> +// CHECK: %[[OF_STREAM_CONS_BUFF_1:.*]] = aie.buffer(%[[TILE_1_3]]) {sym_name = "of_stream_cons_buff_1"} : memref<16xi32> +// CHECK: %[[OF_STREAM_CONS_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 0) {init = 2 : i32, sym_name = "of_stream_cons_prod_lock"} +// CHECK: %[[OF_STREAM_CONS_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_3]], 1) {init = 0 : i32, sym_name = "of_stream_cons_cons_lock"} +// CHECK: %[[OF_STREAM_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_stream_buff_0"} : memref<16xi32> +// CHECK: %[[OF_STREAM_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_stream_buff_1"} : memref<16xi32> +// CHECK: %[[OF_STREAM_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 2) {init = 2 : i32, sym_name = "of_stream_prod_lock"} +// CHECK: %[[OF_STREAM_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 3) {init = 0 : i32, sym_name = "of_stream_cons_lock"} +// CHECK: %[[OF_SHARED_BUFF_0:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_shared_buff_0"} : memref<16xi32> +// CHECK: %[[OF_SHARED_BUFF_1:.*]] = aie.buffer(%[[TILE_1_2]]) {sym_name = "of_shared_buff_1"} : memref<16xi32> +// CHECK: %[[OF_SHARED_PROD_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 0) {init = 2 : i32, sym_name = "of_shared_prod_lock"} +// CHECK: %[[OF_SHARED_CONS_LOCK:.*]] = aie.lock(%[[TILE_1_2]], 1) {init = 0 : i32, sym_name = "of_shared_cons_lock"} +// CHECK: aie.flow(%[[TILE_1_2]], DMA : 0, %[[TILE_1_3]], DMA : 0) +// CHECK: %[[MEM_1_2:.*]] = aie.mem(%[[TILE_1_2]]) { +// CHECK: %[[VAL_0:.*]] = aie.dma_start(MM2S, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_STREAM_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_STREAM_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_STREAM_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF_STREAM_CONS_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_STREAM_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_STREAM_PROD_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: aie.end +// CHECK: } +// CHECK: %[[MEM_1_3:.*]] = aie.mem(%[[TILE_1_3]]) { +// CHECK: %[[VAL_1:.*]] = aie.dma_start(S2MM, 0, ^bb1, ^bb3) +// CHECK: ^bb1: +// CHECK: aie.use_lock(%[[OF_STREAM_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_STREAM_CONS_BUFF_0]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_STREAM_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb2 +// CHECK: ^bb2: +// CHECK: aie.use_lock(%[[OF_STREAM_CONS_PROD_LOCK]], AcquireGreaterEqual, 1) +// CHECK: aie.dma_bd(%[[OF_STREAM_CONS_BUFF_1]] : memref<16xi32>, 0, 16) +// CHECK: aie.use_lock(%[[OF_STREAM_CONS_CONS_LOCK]], Release, 1) +// CHECK: aie.next_bd ^bb1 +// CHECK: ^bb3: +// CHECK: aie.end +// CHECK: } +// CHECK: } module @viaDMA { aie.device(xcve2302) { %tile12 = aie.tile(1, 2) %tile13 = aie.tile(1, 3) - aie.objectfifo @of_shared (%tile12, {%tile13}, 2 : i32) : !aie.objectfifo> aie.objectfifo @of_stream (%tile12, {%tile13}, 2 : i32) {via_DMA = true} : !aie.objectfifo> } diff --git a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/tests/lower_objfifo/basic_dma_transpose.mlir b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/tests/lower_objfifo/basic_dma_transpose.mlir index 4b5a2cb94..8fc2f147b 100644 --- a/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/tests/lower_objfifo/basic_dma_transpose.mlir +++ b/compiler/plugins/target/AMD-AIE/iree-amd-aie/Target/tests/lower_objfifo/basic_dma_transpose.mlir @@ -1,7 +1,8 @@ // RUN: iree-compile --compile-mode=hal-executable --iree-hal-target-backends=amd-aie-direct %s | FileCheck %s // CHECK: Generating:{{.*}}aie_cdo_elfs.bin -// CHECK: Successfully wrote{{.*}}module_dummy1_amdaie_xclbin_fb.xclbin +// CHECK: Generating:{{.*}}aie_cdo_init.bin +// CHECK: Generating:{{.*}}aie_cdo_enable.bin module attributes {hal.device.targets = [#hal.device.target<"amd-aie-direct", [#hal.executable.target<"amd-aie-direct", "amdaie-xclbin-fb", {target_arch = "chip-tbd", ukernels = "none"}>]>]} { hal.executable private @dummy1 { hal.executable.variant public @amdaie_xclbin_fb target(<"amd-aie-direct", "amdaie-xclbin-fb", {target_arch = "chip-tbd", ukernels = "none"}>) { diff --git a/runtime/src/iree-amd-aie/runtime/CMakeLists.txt b/runtime/src/iree-amd-aie/runtime/CMakeLists.txt index 9e9f05571..a750e308e 100644 --- a/runtime/src/iree-amd-aie/runtime/CMakeLists.txt +++ b/runtime/src/iree-amd-aie/runtime/CMakeLists.txt @@ -101,11 +101,6 @@ include(${_aie_rt_source_dir}/fal/cmake/collect.cmake) # gotta add the subdirectory so the copies to build/include/xaiengine occur... add_subdirectory(${_aie_rt_source_dir}/driver/src iree_aie_runtime) -string(TOUPPER "${CMAKE_BUILD_TYPE}" uppercase_CMAKE_BUILD_TYPE) -if(uppercase_CMAKE_BUILD_TYPE STREQUAL "DEBUG") - set(XAIE_DEBUG "XAIE_DEBUG") -endif() - get_target_property(_aie_runtime_compile_options aienginev2 COMPILE_OPTIONS) list(REMOVE_ITEM _aie_runtime_compile_options -D__AIEBAREMETAL__) set_target_properties(