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myAVR.map.rpt
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myAVR.map.rpt
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Analysis & Synthesis report for myAVR
Sun Dec 16 01:12:18 2012
Quartus II 32-bit Version 12.0 Build 178 05/31/2012 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis IP Cores Summary
10. General Register Statistics
11. Multiplexer Restructuring Statistics (Restructuring Performed)
12. Source assignments for rom:prog|altsyncram:altsyncram_component|altsyncram_8i71:auto_generated
13. Parameter Settings for User Entity Instance: Top-level Entity: |myAVR
14. Parameter Settings for User Entity Instance: rom:prog|altsyncram:altsyncram_component
15. altsyncram Parameter Settings by Entity Instance
16. Elapsed Time Per Partition
17. Analysis & Synthesis Messages
18. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2012 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Dec 16 01:12:18 2012 ;
; Quartus II 32-bit Version ; 12.0 Build 178 05/31/2012 SJ Web Edition ;
; Revision Name ; myAVR ;
; Top-level Entity Name ; myAVR ;
; Family ; Cyclone II ;
; Total logic elements ; 1,396 ;
; Total combinational functions ; 1,396 ;
; Dedicated logic registers ; 290 ;
; Total registers ; 290 ;
; Total pins ; 18 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 4,096 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP2C5T144C8 ; ;
; Top-level entity name ; myAVR ; myAVR ;
; Family name ; Cyclone II ; Cyclone IV GX ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+--------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+--------------------------------------------------------------------------------------+---------+
; myAVR.v ; yes ; User Verilog HDL File ; /home/firefish/quartus/myAVR/myAVR.v ; ;
; rom.v ; yes ; User Wizard-Generated File ; /home/firefish/quartus/myAVR/rom.v ; ;
; rom.mif ; yes ; User Memory Initialization File ; /home/firefish/quartus/myAVR/rom.mif ; ;
; altsyncram.tdf ; yes ; Megafunction ; /media/data/soft/Radio/quartus/quartus/libraries/megafunctions/altsyncram.tdf ; ;
; stratix_ram_block.inc ; yes ; Megafunction ; /media/data/soft/Radio/quartus/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
; lpm_mux.inc ; yes ; Megafunction ; /media/data/soft/Radio/quartus/quartus/libraries/megafunctions/lpm_mux.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; /media/data/soft/Radio/quartus/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; aglobal120.inc ; yes ; Megafunction ; /media/data/soft/Radio/quartus/quartus/libraries/megafunctions/aglobal120.inc ; ;
; a_rdenreg.inc ; yes ; Megafunction ; /media/data/soft/Radio/quartus/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
; altrom.inc ; yes ; Megafunction ; /media/data/soft/Radio/quartus/quartus/libraries/megafunctions/altrom.inc ; ;
; altram.inc ; yes ; Megafunction ; /media/data/soft/Radio/quartus/quartus/libraries/megafunctions/altram.inc ; ;
; altdpram.inc ; yes ; Megafunction ; /media/data/soft/Radio/quartus/quartus/libraries/megafunctions/altdpram.inc ; ;
; db/altsyncram_8i71.tdf ; yes ; Auto-Generated Megafunction ; /home/firefish/quartus/myAVR/db/altsyncram_8i71.tdf ; ;
+----------------------------------+-----------------+----------------------------------+--------------------------------------------------------------------------------------+---------+
+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+---------+
; Resource ; Usage ;
+---------------------------------------------+---------+
; Estimated Total logic elements ; 1,396 ;
; ; ;
; Total combinational functions ; 1396 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 1113 ;
; -- 3 input functions ; 200 ;
; -- <=2 input functions ; 83 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 1352 ;
; -- arithmetic mode ; 44 ;
; ; ;
; Total registers ; 290 ;
; -- Dedicated logic registers ; 290 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 18 ;
; Total memory bits ; 4096 ;
; Maximum fan-out node ; cnt[25] ;
; Maximum fan-out ; 281 ;
; Total fan-out ; 6402 ;
; Average fan-out ; 3.72 ;
+---------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------+--------------+
; |myAVR ; 1396 (1396) ; 290 (290) ; 4096 ; 0 ; 0 ; 0 ; 18 ; 0 ; |myAVR ; ;
; |rom:prog| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |myAVR|rom:prog ; ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |myAVR|rom:prog|altsyncram:altsyncram_component ; ;
; |altsyncram_8i71:auto_generated| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |myAVR|rom:prog|altsyncram:altsyncram_component|altsyncram_8i71:auto_generated ; ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+---------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+---------+
; rom:prog|altsyncram:altsyncram_component|altsyncram_8i71:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 256 ; 16 ; -- ; -- ; 4096 ; rom.mif ;
+------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+---------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+-----------------+------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+-----------------+------------------------------------+
; Altera ; ROM: 1-PORT ; 12.0 ; N/A ; N/A ; |myAVR|rom:prog ; /home/firefish/quartus/myAVR/rom.v ;
+--------+--------------+---------+--------------+--------------+-----------------+------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 290 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 112 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 224 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+-------------------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+-------------------------+----------------------------+
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[15][4] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[14][4] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[13][6] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[12][6] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[11][6] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[10][7] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[9][3] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[8][7] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[7][4] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[6][4] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[5][3] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[4][3] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[3][3] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[2][6] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[1][1] ; ;
; 8:1 ; 7 bits ; 35 LEs ; 28 LEs ; 7 LEs ; |myAVR|registers[0][6] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[31][2] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[30][4] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[29][4] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[28][4] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[27][7] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[26][3] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[25][5] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[24][1] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[23][2] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[22][3] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[21][7] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[20][1] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[19][4] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[18][3] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[17][1] ; ;
; 9:1 ; 7 bits ; 42 LEs ; 28 LEs ; 14 LEs ; |myAVR|registers[16][2] ; ;
; 32:1 ; 8 bits ; 168 LEs ; 168 LEs ; 0 LEs ; |myAVR|Mux8 ; ;
; 32:1 ; 8 bits ; 168 LEs ; 168 LEs ; 0 LEs ; |myAVR|Mux4 ; ;
+--------------------+-----------+---------------+----------------------+------------------------+-------------------------+----------------------------+
+------------------------------------------------------------------------------------------------+
; Source assignments for rom:prog|altsyncram:altsyncram_component|altsyncram_8i71:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+----------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+----------------------------------+
+-----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |myAVR ;
+----------------+------------------+-----------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+------------------+-----------------------------------+
; CMD_ADD ; 000011XXXXXXXXXX ; Unsigned Binary ;
; CMD_SUB ; 000110XXXXXXXXXX ; Unsigned Binary ;
; CMD_AND ; 001000XXXXXXXXXX ; Unsigned Binary ;
; CMD_EOR ; 001001XXXXXXXXXX ; Unsigned Binary ;
; CMD_OR ; 001010XXXXXXXXXX ; Unsigned Binary ;
; CMD_MOV ; 001011XXXXXXXXXX ; Unsigned Binary ;
; CMD_CP ; 000101XXXXXXXXXX ; Unsigned Binary ;
; CMD_LSR ; 1001010XXXXX0110 ; Unsigned Binary ;
; CMD_LDI ; 1110XXXXXXXXXXXX ; Unsigned Binary ;
; CMD_BREQ ; 111100XXXXXXX001 ; Unsigned Binary ;
; CMD_BRNE ; 111101XXXXXXX001 ; Unsigned Binary ;
; CMD_BRCS ; 111100XXXXXXX000 ; Unsigned Binary ;
; CMD_BRCC ; 111101XXXXXXX000 ; Unsigned Binary ;
+----------------+------------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: rom:prog|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+---------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+---------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 16 ; Signed Integer ;
; WIDTHAD_A ; 8 ; Signed Integer ;
; NUMWORDS_A ; 256 ; Signed Integer ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; rom.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
; ENABLE_ECC ; FALSE ; Untyped ;
; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
; WIDTH_ECCSTATUS ; 3 ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CBXI_PARAMETER ; altsyncram_8i71 ; Untyped ;
+------------------------------------+----------------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance ;
+-------------------------------------------+------------------------------------------+
; Name ; Value ;
+-------------------------------------------+------------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; rom:prog|altsyncram:altsyncram_component ;
; -- OPERATION_MODE ; ROM ;
; -- WIDTH_A ; 16 ;
; -- NUMWORDS_A ; 256 ;
; -- OUTDATA_REG_A ; UNREGISTERED ;
; -- WIDTH_B ; 1 ;
; -- NUMWORDS_B ; 1 ;
; -- ADDRESS_REG_B ; CLOCK1 ;
; -- OUTDATA_REG_B ; UNREGISTERED ;
; -- RAM_BLOCK_TYPE ; AUTO ;
; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
+-------------------------------------------+------------------------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:07 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 12.0 Build 178 05/31/2012 SJ Web Edition
Info: Processing started: Sun Dec 16 01:12:09 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myAVR -c myAVR
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file myAVR.v
Info (12023): Found entity 1: myAVR
Info (12021): Found 1 design units, including 1 entities, in source file rom.v
Info (12023): Found entity 1: rom
Info (12127): Elaborating entity "myAVR" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at myAVR.v(62): object "K" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at myAVR.v(9): truncated value with size 32 to match size of target (26)
Info (12128): Elaborating entity "rom" for hierarchy "rom:prog"
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom:prog|altsyncram:altsyncram_component"
Info (12130): Elaborated megafunction instantiation "rom:prog|altsyncram:altsyncram_component"
Info (12133): Instantiated megafunction "rom:prog|altsyncram:altsyncram_component" with the following parameter:
Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
Info (12134): Parameter "init_file" = "rom.mif"
Info (12134): Parameter "intended_device_family" = "Cyclone II"
Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
Info (12134): Parameter "lpm_type" = "altsyncram"
Info (12134): Parameter "numwords_a" = "256"
Info (12134): Parameter "operation_mode" = "ROM"
Info (12134): Parameter "outdata_aclr_a" = "NONE"
Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
Info (12134): Parameter "widthad_a" = "8"
Info (12134): Parameter "width_a" = "16"
Info (12134): Parameter "width_byteena_a" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_8i71.tdf
Info (12023): Found entity 1: altsyncram_8i71
Info (12128): Elaborating entity "altsyncram_8i71" for hierarchy "rom:prog|altsyncram:altsyncram_component|altsyncram_8i71:auto_generated"
Info (144001): Generated suppressed messages file /home/firefish/quartus/myAVR/myAVR.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "reset"
Info (21057): Implemented 1430 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 2 input pins
Info (21059): Implemented 16 output pins
Info (21061): Implemented 1396 logic cells
Info (21064): Implemented 16 RAM segments
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 361 megabytes
Info: Processing ended: Sun Dec 16 01:12:18 2012
Info: Elapsed time: 00:00:09
Info: Total CPU time (on all processors): 00:00:09
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /home/firefish/quartus/myAVR/myAVR.map.smsg.