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compile.tcl
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compile.tcl
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# Run Synthesis
update_compile_order -fileset sources_1
reset_run impl_1
reset_run synth_1
launch_runs synth_1 -jobs 4
wait_on_run synth_1
open_run synth_1
# Set XDMA PCIe Constraints for OpenCAPI-to-PCIe Rev.2 Board
# which has reversed Lane-to-Channel ordering:
# Lane 0 = Channel X0Y16, Lane 1 = Channel X0Y17, ..., Lane 7 = Channel X0Y23
# The expected ordering is:
# Lane 0 = Channel X0Y23, Lane 1 = Channel X0Y22, ..., Lane 7 = Channel X0Y16
reset_property LOC [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[5].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST}]
reset_property LOC [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[5].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST}]
reset_property LOC [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[5].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST}]
reset_property LOC [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[5].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST}]
reset_property LOC [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[4].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST}]
reset_property LOC [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[4].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST}]
reset_property LOC [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[4].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST}]
reset_property LOC [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[4].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST}]
set_property LOC GTYE4_CHANNEL_X0Y16 [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[5].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST}]
set_property LOC GTYE4_CHANNEL_X0Y17 [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[5].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST}]
set_property LOC GTYE4_CHANNEL_X0Y18 [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[5].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST}]
set_property LOC GTYE4_CHANNEL_X0Y19 [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[5].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST}]
set_property LOC GTYE4_CHANNEL_X0Y20 [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[4].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST}]
set_property LOC GTYE4_CHANNEL_X0Y21 [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[4].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST}]
set_property LOC GTYE4_CHANNEL_X0Y22 [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[4].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST}]
set_property LOC GTYE4_CHANNEL_X0Y23 [get_cells {blockdiagram_i/xdma_0/inst/pcie4_ip_i/inst/blockdiagram_xdma_0_0_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/blockdiagram_xdma_0_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.blockdiagram_xdma_0_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[4].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST}]
# Run Implemention then generate reports and programming files
launch_runs impl_1 -jobs 4
wait_on_run impl_1
open_run impl_1
report_timing_summary -file ./innova2_xdma_opencapi/timing.rpt
report_utilization -file ./innova2_xdma_opencapi/utilization.rpt
report_io -file ./innova2_xdma_opencapi/io.rpt
write_debug_probes -force ./innova2_xdma_opencapi/innova2_xdma_opencapi.ltx
write_csv -force ./innova2_xdma_opencapi/impl_1_pins.csv
report_bus_skew -max 32 -nworst 1 -path_type full -input_pins -file ./innova2_xdma_opencapi/bus_skew.rpt
write_bitstream -verbose -force ./innova2_xdma_opencapi/innova2_xdma_opencapi.bit
write_cfgmem -force -format bin -size 128 -interface SPIx8 -loadbit {up 0x00000000 "./innova2_xdma_opencapi/innova2_xdma_opencapi.bit" } -file "innova2_xdma_opencapi/innova2_xdma_opencapi.bin"