From 94d27003ad3a5612076221626d7c0daacd4865bd Mon Sep 17 00:00:00 2001 From: Daniel Mangum Date: Sat, 8 Jul 2023 21:15:43 -0400 Subject: [PATCH 1/3] Add simulation for register file Adds basic simulation for the register file exercising writing data to a register then reading it back. Signed-off-by: Daniel Mangum --- Makefile | 2 +- sim/regfile.cpp | 73 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 sim/regfile.cpp diff --git a/Makefile b/Makefile index 04f4ee1..e91d045 100644 --- a/Makefile +++ b/Makefile @@ -63,7 +63,7 @@ VERILATOR=verilator $(SIMOUTDIR)/%.o: $(SIMDIR)/%.cpp $(RTLDIR)/%.v $(VERILATOR) -Wall --cc -I$(RTLDIR) --trace $*.v --exe --build $(SIMDIR)/$*.cpp -verilate: $(SIMOUTDIR)/top.o $(SIMOUTDIR)/alu.o +verilate: $(SIMOUTDIR)/top.o $(SIMOUTDIR)/alu.o $(SIMOUTDIR)/regfile.o simulate.%: verilate @$(SIMOUTDIR)/V$* diff --git a/sim/regfile.cpp b/sim/regfile.cpp new file mode 100644 index 0000000..0171bf9 --- /dev/null +++ b/sim/regfile.cpp @@ -0,0 +1,73 @@ +/* +Copyright 2023 The Moss Authors. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +#include +#include "Vregfile.h" +#include "verilated_vcd_c.h" + +int main(int argc, char** argv, char** env) { + // Pass all arguments to verilator. + Verilated::commandArgs(argc, argv); + + // Instantiate register file. + Vregfile *regfile = new Vregfile; + + // Setup tracing. + Verilated::traceEverOn(true); + VerilatedVcdC* tfp = new VerilatedVcdC; + regfile->trace(tfp, 99); + tfp->open("obj_dir/regfile.vcd"); + + // Sim counter. + int i = 0; + + // Cycle clock. + regfile->clk ^= 1; + regfile->eval(); + tfp->dump(i); + i++; + + // Write 12 to register 28. + regfile->clk ^= 1; + regfile->rd = 28; + regfile->data = 12; + regfile->write_ctrl = 1; + regfile->eval(); + tfp->dump(i); + i++; + + // Cycle clock. + regfile->clk ^= 1; + regfile->eval(); + tfp->dump(i); + i++; + + // Read value from register 28. + regfile->write_ctrl = 0; + regfile->clk ^= 1; + regfile->rs2 = 28; + regfile->eval(); + tfp->dump(i); + i++; + + // Cycle clock. + regfile->clk ^= 1; + regfile->eval(); + tfp->dump(i); + + tfp->close(); + exit(EXIT_SUCCESS); +} From b2c6831526da191f3c49306165c491972644f391 Mon Sep 17 00:00:00 2001 From: Daniel Mangum Date: Sat, 8 Jul 2023 21:17:24 -0400 Subject: [PATCH 2/3] Add wave target for viewing generated waveforms Adds a wave Makefile target to view waveforms generated from simulation. Signed-off-by: Daniel Mangum --- Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Makefile b/Makefile index e91d045..90a3564 100644 --- a/Makefile +++ b/Makefile @@ -59,6 +59,7 @@ RTLDIR=rtl SIMDIR=sim SIMOUTDIR=obj_dir VERILATOR=verilator +GTKWAVE=gtkwave $(SIMOUTDIR)/%.o: $(SIMDIR)/%.cpp $(RTLDIR)/%.v $(VERILATOR) -Wall --cc -I$(RTLDIR) --trace $*.v --exe --build $(SIMDIR)/$*.cpp @@ -67,3 +68,6 @@ verilate: $(SIMOUTDIR)/top.o $(SIMOUTDIR)/alu.o $(SIMOUTDIR)/regfile.o simulate.%: verilate @$(SIMOUTDIR)/V$* + +wave.%: simulate.% + $(GTKWAVE) obj_dir/$*.vcd From 04ba8ebfb26507b7cb81ffc56c064350b02c1364 Mon Sep 17 00:00:00 2001 From: Daniel Mangum Date: Sat, 8 Jul 2023 21:18:10 -0400 Subject: [PATCH 3/3] Fix text wrapping in sim/alu.cpp Fixes unwrapped comment in sim/alu.cpp. Signed-off-by: Daniel Mangum --- sim/alu.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sim/alu.cpp b/sim/alu.cpp index 4513b14..2e5ade4 100644 --- a/sim/alu.cpp +++ b/sim/alu.cpp @@ -48,8 +48,9 @@ int main(int argc, char** argv, char** env) { // Pass all arguments to verilator. Verilated::commandArgs(argc, argv); - // Initialize ALU. We don't trace in this test as the module is not clocked. - Valu *alu = new Valu; + // Initialize ALU. We don't trace in this test as the module is not + // clocked. + Valu *alu = new Valu; if (opAnd(alu, 1, 2) != (1 & 2)) { exit(EXIT_FAILURE);