clk_div.bsf

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2019  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 224 160)
	(text "clk_div" (rect 5 0 33 12)(font "Arial" ))
	(text "inst" (rect 8 128 20 140)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "clock_12MHz" (rect 0 0 53 12)(font "Arial" ))
		(text "clock_12MHz" (rect 21 27 74 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 208 32)
		(output)
		(text "clock_100kHz" (rect 0 0 54 12)(font "Arial" ))
		(text "clock_100kHz" (rect 133 27 187 39)(font "Arial" ))
		(line (pt 208 32)(pt 192 32)(line_width 1))
	)
	(port
		(pt 208 48)
		(output)
		(text "clock_10kHz" (rect 0 0 49 12)(font "Arial" ))
		(text "clock_10kHz" (rect 138 43 187 55)(font "Arial" ))
		(line (pt 208 48)(pt 192 48)(line_width 1))
	)
	(port
		(pt 208 64)
		(output)
		(text "clock_100Hz" (rect 0 0 49 12)(font "Arial" ))
		(text "clock_100Hz" (rect 138 59 187 71)(font "Arial" ))
		(line (pt 208 64)(pt 192 64)(line_width 1))
	)
	(port
		(pt 208 80)
		(output)
		(text "clock_32Hz" (rect 0 0 46 12)(font "Arial" ))
		(text "clock_32Hz" (rect 141 75 187 87)(font "Arial" ))
		(line (pt 208 80)(pt 192 80)(line_width 1))
	)
	(port
		(pt 208 96)
		(output)
		(text "clock_10Hz" (rect 0 0 44 12)(font "Arial" ))
		(text "clock_10Hz" (rect 143 91 187 103)(font "Arial" ))
		(line (pt 208 96)(pt 192 96)(line_width 1))
	)
	(port
		(pt 208 112)
		(output)
		(text "clock_4Hz" (rect 0 0 42 12)(font "Arial" ))
		(text "clock_4Hz" (rect 145 107 187 119)(font "Arial" ))
		(line (pt 208 112)(pt 192 112)(line_width 1))
	)
	(drawing
		(rectangle (rect 16 16 192 128)(line_width 1))
	)
)