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forth.asm
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; STM8EF for STM8S (Value line and Access Line devices)
;
; This is derived work based on
; http://www.forth.org/svfig/kk/07-2010.html
;
; Please refer to LICENSE.md for more information.
;
;--------------------------------------------------------
; Original author, and copyright:
; STM8EF, Version 2.1, 13jul10cht
; Copyright (c) 2000
; Dr. C. H. Ting
; 156 14th Avenue
; San Mateo, CA 94402
; (650) 571-7639
;
; Original main description:
; FORTH Virtual Machine:
; Subroutine threaded model
; SP Return stack pointer
; X Data stack pointer
; A,Y Scratch pad registers
;
;--------------------------------------------------------
; The latest version of this code is available at
; https://github.com/TG9541/stm8ef
;
;
; Docs for the SDCC integrated assembler are scarce, thus
; SDCC was used to write the skeleton for this file.
; However, the code in this file isn't SDCC code.
;--------------------------------------------------------
; File Created by SDCC : free open source ANSI-C Compiler
; Version 3.6.0 #9615 (Linux)
;--------------------------------------------------------
.module forth
.optsdcc -mstm8
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _TRAP_Handler
.globl _EXTI0_IRQHandler
.globl _EXTI1_IRQHandler
.globl _EXTI2_IRQHandler
.globl _EXTI3_IRQHandler
.globl _EXTI4_IRQHandler
.globl _TIM2_UO_IRQHandler
.globl _TIM4_IRQHandler
.globl _forth
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area DATA
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area INITIALIZED
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area DABS (ABS)
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area HOME
.area GSINIT
.area GSFINAL
.area GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area HOME
.area HOME
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area CODE
;************************************
;****** 1) General Constants ******
;************************************
TRUEE = 0xFFFF ; true flag
COMPO = 0x40 ; lexicon compile only bit
IMEDD = 0x80 ; lexicon immediate bit
MASKK = 0x1F7F ; lexicon bit mask
TIBLENGTH = 80 ; size of TIB (starting at TIBOFFS)
PADOFFS = 80 ; offset text buffer above dictionary
CELLL = 2 ; size of a cell
BASEE = 10 ; default radix
BKSPP = 8 ; backspace
LF = 10 ; line feed
PACE = 11 ; pace character for host handshake (ASCII VT)
CRR = 13 ; carriage return
ERR = 27 ; error escape
TIC = 39 ; tick
EXIT_OPC = 0x81 ; RET opcode
DOLIT_OPC = 0x83 ; TRAP opcode as DOLIT
CALLR_OPC = 0xAD ; CALLR opcode for relative addressing
BRAN_OPC = 0xCC ; JP opcode
CALL_OPC = 0xCD ; CALL opcode
STM8L051F3 = 051 ; L core, 8K flash, 1K RAM, 256 EEPROM, UART1
STM8L152C6 = 152 ; L core, 32K flash, 2K RAM, 1K EEPROM, UART1
STM8S003F3 = 103 ; 8K flash, 1K RAM, 128 EEPROM, UART1
STM8S103F3 = 103 ; like STM8S003F3, 640 EEPROM
STM8S105K4 = 105 ; 16K flash, 2K RAM, 1K EEPROM, UART2
STM8S105C6 = 105 ; 32K flash, 2K RAM, 1K EEPROM, UART2
STM8S207RB = 207 ; 32K+96K flash, 6K RAM, 2K EEPROM, UART1
DEFOSCFREQ = 16000 ; default oscillator frequency in kHz
;********************************************
;****** 2) Device hardware addresses ******
;********************************************
;****** STM8S memory addresses ******
RAMBASE = 0x0000 ; STM8S RAM start
EEPROMBASE = 0x4000 ; STM8S EEPROM start
; STM8 device specific include (provided by file in board folder)
; sets "TARGET" and memory layout
.include "target.inc"
; STM8 unified register addresses (depends on "TARGET")
.ifeq (TARGET - STM8L051F3)
.include "stm8ldevice.inc"
.else
.ifeq (TARGET - STM8L152C6)
.include "stm8ldevice.inc"
.else
.include "stm8device.inc"
.endif
.endif
;**********************************
;****** 3) Global defaults ******
;**********************************
; Note: add defaults for new features here
; and configure them in globconf.inc
.include "defconf.inc"
;********************************************
;****** 4) Device dependent features ******
;********************************************
; Define memory location for device dependent features here
.include "globconf.inc"
.include "linkopts.inc"
; console configuration: check if TX simulation has priority over UART
.ifge HAS_TXSIM - HAS_TXUART
.ifeq PNTX-PNRX
CONSOLE_HALF_DUPLEX = 1 ; single wire RX/TX simulation is half duplex
.else
CONSOLE_HALF_DUPLEX = 0 ; RX/TX simulation supports full duplex
.endif
.else
CONSOLE_HALF_DUPLEX = HALF_DUPLEX ; use hardware UART settings
.endif
OSCFREQ = DEFOSCFREQ ; "OSCFREQ" oscillator frequency in kHz
;**************************************
;****** 5) Board Driver Memory ******
;**************************************
; Memory for board related code, e.g. interrupt routines
RAMPOOL = FORTHRAM ; RAM for variables (growing up)
.macro RamByte varname
varname = RAMPOOL
RAMPOOL = RAMPOOL + 1
.endm
.macro RamWord varname
varname = RAMPOOL
RAMPOOL = RAMPOOL + 2
.endm
.macro RamBlck varname, size
varname = RAMPOOL
RAMPOOL = RAMPOOL + size
.endm
;****** Board variables ******
.ifne HAS_BACKGROUND
.ifne HAS_LED7SEG
.if gt,(HAS_LED7SEG-1)
RamByte LED7GROUP ; index [0..(HAS_LED7SEG-1)] of 7-SEG digit group
.endif
DIGITS = HAS_LED7SEG*LEN_7SGROUP
RamBlck LED7FIRST,DIGITS ; leftmost 7S-LED digit
LED7LAST = RAMPOOL-1 ; save memory location of rightmost 7S-LED digit
.endif
RamWord BGADDR ; address of background routine (0: off)
RamWord TICKCNT ; 16 bit ticker (counts up)
.ifne HAS_KEYS
RamByte KEYREPET ; board key repetition control (8 bit)
.endif
BSPPSIZE = 32 ; Size of data stack for background tasks
PADBG = 0x5F ; PAD in background task growing down from here
.else
BSPPSIZE = 0 ; no background, no extra data stack
.endif
;**************************************************
;****** 6) General User & System Variables ******
;**************************************************
; ****** Indirect variables for code in NVM *****
.ifne HAS_CPNVM
ISPPSIZE = 16 ; Size of data stack for interrupt tasks
.else
ISPPSIZE = 0 ; no interrupt tasks without NVM
.endif
UPP = UPPLOC ; "UPP" offset user area
CTOP = CTOPLOC ; dictionary start, growing up
; note: PAD is inbetween CTOP and SPP
SPP = ISPP-ISPPSIZE ; "SPP" data stack, growing down (with SPP-1 first)
ISPP = SPPLOC-BSPPSIZE ; "ISPP" Interrupt data stack, growing down
BSPP = SPPLOC ; "BSPP" Background data stack, growing down
TIBB = SPPLOC ; "TIB" Term. Input Buf. TIBLENGTH between SPPLOC and RPP
RPP = RPPLOC ; "RPP" return stack, growing down
; Core variables (same order as 'BOOT initializer block)
USRRAMINIT = USREMIT
USREMIT = UPP+0 ; "'EMIT" execution vector of EMIT
USRQKEY = UPP+2 ; "'?KEY" execution vector of QKEY
USRBASE = UPP+4 ; "BASE" radix base for numeric I/O
; USR_6 = UPP+6 ; free
USRPROMPT = UPP+8 ; "'PROMPT" point to prompt word (default .OK)
USRCP = UPP+10 ; "CP" point to top of dictionary
USRLAST = UPP+12 ; "LAST" currently last name in dictionary
NVMCP = UPP+14 ; point to top of dictionary in Non Volatile Memory
; Null initialized core variables (growing down)
USRCTOP = UPP+16 ; "CTOP" point to the start of RAM dictionary
USRVAR = UPP+18 ; "VAR" point to next free USR RAM location
NVMCONTEXT = UPP+20 ; point to top of dictionary in Non Volatile Memory
USRCONTEXT = UPP+22 ; "CONTEXT" start vocabulary search
USREVAL = UPP+24 ; "'EVAL" execution vector of EVAL
USRNTIB = UPP+26 ; "#TIB" count in terminal input buffer
USR_IN = UPP+28 ; ">IN" hold parsing pointer
USRBUFFER = UPP+30 ; "BUFFER" address, defaults to TIBB
; More core variables in zero page (instead of assigning fixed addresses)
RamWord USRHLD ; "HLD" hold a pointer of output string
RamWord YTEMP ; "YTEMP" extra working register for core words
RamWord USRIDLE ; "'IDLE" idle routine in KEY
;***********************
;****** 7) Code ******
;***********************
; ==============================================
; Forth header macros
; Macro support in SDCC's assembler "SDAS" has some quirks:
; * strings with "," and ";" aren't allowed in parameters
; * after include files, the first macro call may fail
; unless it's preceded by unconditional code
; ==============================================
LINK = 0 ;
.macro HEADER Label wName
.ifeq UNLINK_'Label
.dw LINK
LINK = .
.db (102$ - 101$)
101$:
.ascii wName
102$:
.endif
;'Label:
.endm
.macro HEADFLG Label wName wFlag
.ifeq UNLINK_'Label
.dw LINK
LINK = .
.db ((102$ - 101$) + wFlag)
101$:
.ascii wName
102$:
.endif
;'Label:
.endm
; ==============================================
; Low level code
; ==============================================
; TRAP handler for DOLIT
; Push the inline literal following the TRAP instruction
_TRAP_Handler:
.ifeq USE_CALLDOLIT
DECW X
DECW X
LDW (3,SP),X ; XH,XL
EXGW X,Y
LDW X,(8,SP) ; PC MSB/LSB
LDW X,(X)
LDW (Y),X
LDW (5,SP),X ; YH,YL
LDW X,(8,SP)
INCW X
INCW X
LDW (8,SP),X
IRET
; Macros for inline literals using the TRAP approach
.macro DoLitC c
TRAP
.dw c
.endm
.macro DoLitW w
TRAP
.dw w
.endm
.else
; Macros for inline literals using CALL DOLIT / CALL DOLITC
.macro DoLitC c
call DOLITC
.db c
.endm
.macro DoLitW w
call DOLIT
.dw w
.endm
.endif
; TIM2 interrupt handler for background task
_TIM2_UO_IRQHandler:
.ifne (HAS_LED7SEG + HAS_BACKGROUND)
BRES TIM2_SR1,#0 ; clear TIM2 UIF
.ifne HAS_LED7SEG
CALL LED_MPX ; board dependent code for 7Seg-LED-Displays
.endif
; Background operation saves & restores the context of the interactive task
; Cyclic context reset of Forth background task (stack, BASE, HLD, I/O vector)
.ifne HAS_BACKGROUND
LDW X,TICKCNT
INCW X
LDW TICKCNT,X
; fall through
.ifne BG_RUNMASK
LD A,XL ; Background task runs if "(BG_RUNMASK AND TICKCNT) equals 0"
AND A,#BG_RUNMASK
JRNE TIM2IRET
.endif
LDW Y,BGADDR ; address of background task
TNZW Y ; 0: background operation off
JREQ TIM2IRET
LDW X,YTEMP ; Save context
PUSHW X
PUSH USRBASE+1 ; 8bit since BASE should be < 36
MOV USRBASE+1,#10
LDW X,USREMIT ; save EMIT exection vector
PUSHW X
LDW X,#(EMIT_BG)
LDW USREMIT,X
LDW X,USRQKEY ; save QKEY exection vector
PUSHW X
LDW X,#(QKEY_BG)
LDW USRQKEY,X
LDW X,USRHLD
PUSHW X
LDW X,#(PADBG) ; in background task, alway start with an empty PAD
LDW USRHLD,X
LDW X,#(BSPP) ; init data stack for background task to BSPP
CALL (Y)
POPW X
LDW USRHLD,X
POPW X
LDW USRQKEY,X
POPW X
LDW USREMIT,X
POP USRBASE+1 ; this may not work in uCsim
POPW X
LDW YTEMP,X
TIM2IRET:
.endif
IRET
.endif
; ==============================================
; Configuation table with shadow data for RESET
; 'BOOT ( -- a )
; The application startup vector and NVM USR setting array
HEADER TBOOT "'BOOT"
TBOOT:
CALL DOVAR
UBOOT = .
.dw HI ; start-up code (can be changed with 'BOOT !)
; COLD initialization data (can be changed with <offset> 'BOOT + !)
UZERO = .
.ifge (HAS_TXUART-HAS_TXSIM)
.dw TXSTOR ; TX! as EMIT vector
.dw QRX ; ?KEY as ?KEY vector
.else
.dw TXPSTOR ; TXP! as EMIT vector if (HAS_TXSIM > HAS_TXUART)
.dw QRXP ; ?RXP as ?KEY vector
.endif
.dw BASEE ; BASE
.dw 0 ; (vacant)
.dw DOTOK ; 'PROMPT
COLDCTOP = .
.dw CTOP ; CP in RAM
COLDCONTEXT = .
.dw LASTN ; USRLAST
.ifne HAS_CPNVM
COLDNVMCP = .
.dw END_SDCC_FLASH ; CP in NVM
ULAST = .
; Shadow initialization data for RESET (can be changed with PERSIST)
UDEFAULTS = .
.dw HI ; 'BOOT
.ifge (HAS_TXUART-HAS_TXSIM)
.dw TXSTOR ; TX! as EMIT vector
.dw QRX ; ?KEY as ?KEY vector
.else
.dw TXPSTOR ; TXP! as EMIT vector
.dw QRXP ; ?RXP as ?KEY vector
.endif
.dw BASEE ; BASE
.dw 0 ; (vacant)
.dw DOTOK ; 'PROMPT
.dw CTOP ; CP in RAM
.dw LASTN ; CONTEXT pointer
.dw END_SDCC_FLASH ; CP in NVM
.else
ULAST = .
.endif
; Main entry points and COLD start data
; COLD ( -- )
; The hilevel cold start sequence.
HEADER COLD "COLD"
_forth: ; SDCC entry
; Note: no return to main.c possible unless RAMEND equals SP,
; and RPP init skipped
COLD:
SIM ; disable interrupts
MOV CLK_CKDIVR,#0 ; Clock divider register
LDW X,#(RAMEND-FORTHRAM)
1$: CLR (FORTHRAM,X)
DECW X
JRPL 1$
LDW X,#RPP ; initialize return stack
LDW SP,X
CALLR BOARDINIT ; Board initialization (see "boardcore.inc")
.ifne HAS_BACKGROUND
; init BG timer interrupt
MOV ITC_SPR4,#0xF7 ; Interrupt prio. low for TIM2 (Int13)
MOV TIM2_PSCR,#0x03 ; prescaler 1/8
MOV TIM2_ARRH,#(BG_TIM2_REL/256) ; reload H
MOV TIM2_ARRL,#(BG_TIM2_REL%256) ; L
MOV TIM2_CR1,#0x01 ; enable TIM2
MOV TIM2_IER,#0x01 ; enable TIM2 interrupt
.endif
.ifne HAS_RXUART+HAS_TXUART
; Init RS232 communication port
; STM8S[01]003F3 init UART
LDW X,#0x6803 ; 9600 baud
LDW UART_BRR1,X
.ifne HAS_RXUART*HAS_TXUART
MOV UART_CR2,#0x0C ; Use UART1 full duplex
.ifne HALF_DUPLEX
MOV UART1_CR5,#0x08 ; UART1 Half-Duplex
.endif
.else
.ifne HAS_TXUART
MOV UART_CR2,#0x08 ; UART1 enable tx
.endif
.ifne HAS_RXUART
MOV UART_CR2,#0x04 ; UART1 enable rx
.endif
.endif
.endif
.ifne HAS_RXSIM+HAS_TXSIM
; TIM4 based RXD or TXD: initialize timer
TIM4RELOAD = 0xCF ; reload 0.104 ms (9600 baud)
MOV TIM4_ARR,#TIM4RELOAD
MOV TIM4_PSCR,#0x03 ; prescaler 1/8
MOV TIM4_CR1,#0x01 ; enable TIM4
.endif
.ifne HAS_TXSIM*((PNRX-PNTX)+(1-HAS_RXSIM))
; init TxD through GPIO if not shared pin with PNRX
BSET PSIM+ODR,#PNTX ; PNTX GPIO high
BSET PSIM+DDR,#PNTX ; PNTX GPIO output
BSET PSIM+CR1,#PNTX ; enable PNTX push-pull
.endif
.ifne (HAS_RXSIM)
; init RxD through GPIO
.ifeq (PSIM-PORTA)
BSET EXTI_CR1,#1 ; External interrupt Port A falling edge
.else
.ifeq (PSIM-PORTB)
BSET EXTI_CR1,#3 ; External interrupt Port B falling edge
.else
.ifeq (PSIM-PORTC)
BSET EXTI_CR1,#5 ; External interrupt Port C falling edge
.else
BSET EXTI_CR1,#7 ; External interrupt Port D falling edge
.endif
.endif
.endif
BRES PSIM+DDR,#PNRX ; 0: input (default)
BSET PSIM+CR1,#PNRX ; enable PNRX pull-up
BSET PSIM+CR2,#PNRX ; enable PNRX external interrupt
.endif
.ifne HAS_LED7SEG
.if gt,(HAS_LED7SEG-1)
MOV LED7GROUP,#0 ; one of position HAS_LED7SEG 7-SEG digit groups
.endif
MOV LED7FIRST ,#0x66 ; 7S LEDs 4..
MOV LED7FIRST+1,#0x78 ; 7S LEDs .t.
MOV LED7FIRST+2,#0x74 ; 7S LEDs ..h
.endif
CALL PRESE ; initialize data stack, TIB
DoLitW UZERO
DoLitC USRRAMINIT
DoLitC (ULAST-UZERO)
CALL CMOVE ; initialize user area
CALL WIPE ; initialize dictionary
; Hardware initialization complete
RIM ; enable interrupts
CALL [TBOOT+3] ; application boot
JP QUIT ; start interpretation
; ==============================================
; Includes for board support code
; Board I/O initialization and E/E mapping code
; Hardware dependent words, e.g. BKEY, OUT!
.include "boardcore.inc"
; Generic board I/O: 7S-LED rendering, board key mapping
.include "board_io.inc"
; ==============================================
; ADC routines depending on STM8 family
.include "stm8_adc.inc"
; ==============================================
; Device dependent I/O
.ifne HAS_RXUART
; ?RX ( -- c T | F ) ( TOS STM8: -- Y,Z,N )
; Return serial interface input char from and true, or false.
HEADER QRX "?RX"
QRX:
CLR A ; A: flag false
BTJF UART_SR,#5,1$
LD A,UART_DR ; get char in A
1$: JP ATOKEY ; push char or flag false
.endif
.ifne HAS_TXUART
; TX! ( c -- )
; Send character c to the serial interface.
HEADER TXSTOR "TX!"
TXSTOR:
INCW X
LD A,(X)
INCW X
.ifne HALF_DUPLEX
; HALF_DUPLEX with normal UART (e.g. wired-or Rx and Tx)
1$: BTJF UART_SR,#7,1$ ; loop until tdre
BRES UART_CR2,#2 ; disable rx
LD UART_DR,A ; send A
2$: BTJF UART_SR,#6,2$ ; loop until tc
BSET UART_CR2,#2 ; enable rx
.else ; not HALF_DUPLEX
1$: BTJF UART_SR,#7,1$ ; loop until tdre
LD UART_DR,A ; send A
.endif
RET
.endif
; Simulated serial I/O
; either full or half duplex
.ifeq HAS_TXSIM + HAS_RXSIM
_TIM4_IRQHandler:
; dummy for linker - can be overwritten by Forth application
.else
; include required serial I/O code
.ifne PNRX^PNTX
.include "sser_fdx.inc" ; Full Duplex serial
.else
.include "sser_hdx.inc" ; Half Duplex serial
.endif
.endif
; ==============================================
; Device independent I/O
; ?KEY ( -- c T | F ) ( TOS STM8: -- Y,Z,N )
; Return input char and true, or false.
HEADER QKEY "?KEY"
QKEY:
JP [USRQKEY]
; EMIT ( c -- )
; Send character c to output device.
HEADER EMIT "EMIT"
EMIT:
JP [USREMIT]
; ==============================================
; The kernel
; PUSHLIT ( - C )
; Subroutine for DOLITC and CCOMMALIT
PUSHLIT:
LDW Y,(3,SP)
DECW X ; LSB = literal
LD A,(Y)
LD (X),A
DECW X ; MSB = 0
CLR A
LD (X),A
RET
; CCOMMALIT ( - )
; Compile inline literall byte into code dictionary.
CCOMMALIT:
CALLR PUSHLIT
CALL CCOMMA
CSKIPRET:
POPW Y
JP (1,Y)
.ifne USE_CALLDOLIT
; DOLITC ( - C )
; Push an inline literal character (8 bit).
DOLITC:
CALLR PUSHLIT
JRA CSKIPRET
; doLit ( -- w )
; Push an inline literal.
HEADFLG DOLIT "doLit" COMPO
DOLIT:
DECW X ;SUBW X,#2
DECW X
LDW Y,(1,SP)
LDW Y,(Y)
LDW (X),Y
JRA POPYJPY
.endif
.ifne HAS_DOLOOP
; (+loop) ( +n -- )
; Add n to index R@ and test for lower than limit (R-CELL)@.
HEADFLG DOPLOOP "(+loop)" COMPO
DOPLOOP:
LDW Y,(5,SP)
LDW YTEMP,Y
LDW Y,X
LDW Y,(Y)
LD A,YH
INCW X
INCW X
ADDW Y,(3,SP)
CPW Y,YTEMP
PUSH CC
TNZ A
JRMI 1$
POP CC
JRSGE LEAVE
JRA 2$
1$: POP CC
JRSLT LEAVE
2$: LDW (3,SP),Y
JRA BRAN
; LEAVE ( -- )
; Leave a DO .. LOOP/+LOOP loop.
HEADFLG LEAVE "LEAVE" COMPO
LEAVE:
ADDW SP,#6
POPW Y ; DO leaves the address of +loop on the R-stack
JP (2,Y)
.endif
; donext ( -- )
; Code for single index loop.
HEADFLG DONXT "donxt" COMPO
DONXT:
LDW Y,(3,SP)
DECW Y
JRPL NEX1
POPW Y
POP A
POP A
JP (2,Y)
NEX1: LDW (3,SP),Y
JRA BRAN
; QDQBRAN ( n - n )
; QDUP QBRANCH phrase
QDQBRAN:
CALL QDUP
JRA QBRAN
; ?branch ( f -- )
; Branch if flag is zero.
HEADFLG QBRAN "?branch" COMPO
QBRAN:
CALL YFLAGS ; Pull TOS to Y, flags
JREQ BRAN
POPYJPY:
POPW Y
JP (2,Y)
; branch ( -- )
; Branch to an inline address.
HEADFLG BRAN "branch" COMPO ; NOALIAS
BRAN:
POPW Y
LDW Y,(Y)
JP (Y)
; EXECUTE ( ca -- )
; Execute word at ca.
HEADER EXECU "EXECUTE"
EXECU:
CALL YFLAGS ; Pull TOS to Y, flags
JP (Y)
.ifeq REMOVE_EXIT
; EXIT ( -- )
; Terminate a colon definition.
HEADER EXIT "EXIT"
EXIT:
POPW Y
RET
.endif
.ifeq BOOTSTRAP
; 2! ( d a -- ) ( TOS STM8: -- Y,Z,N )
; Store double integer to address a.
HEADER DSTOR "2!"
DSTOR:
CALL SWAPP
CALL OVER
CALLR STORE
CALL CELLP
JRA STORE
.endif
.ifeq BOOTSTRAP
; 2@ ( a -- d )
; Fetch double integer from address a.
HEADER DAT "2@"
DAT:
CALL DUPP
CALL CELLP
CALLR AT
CALL SWAPP
JRA AT
.endif
.ifne WORDS_EXTRAMEM
; 2C! ( n a -- )
; Store word C-wise to 16 bit HW registers "MSB first"
HEADER DCSTOR "2C!"
DCSTOR:
CALL YFLAGS ; a
LD A,(X)
LD (Y),A ; write MSB(n) to a
INCW X
LD A,(X)
LD (1,Y),A ; write LSB(n) to a+1
INCW X
RET
; 2C@ ( a -- n )
; Fetch word C-wise from 16 bit HW config. registers "MSB first"
HEADER DCAT "2C@"
DCAT:
LDW Y,X
LDW X,(X)
LD A,(X)
LD (Y),A
LD A,(1,X)
EXGW X,Y
LD (1,X),A
RET
; B! ( t a u -- )
; Set/reset bit #u (0..7) in the byte at address a to bool t
; Note: creates/executes BSER/BRES + RET code on Data Stack
HEADER BRSS "B!"
BRSS:
LD A,#0x72 ; Opcode BSET/BRES
LD (X),A
LD A,(1,X) ; 2nd byte of BSET/BRES
SLA A ; n *= 2 -> A
OR A,#0x10
LDW Y,X
LDW Y,(4,Y) ; bool b (0..15) -> Z
JRNE 1$ ; b!=0: BSET
INC A ; b==0: BRES
1$: LD (1,X),A
LD A,#EXIT_OPC ; Opcode RET
LD (4,X),A
LDW Y,X
ADDW X,#6
JP (Y)
.endif
; @ ( a -- w ) ( TOS STM8: -- Y,Z,N )
; Push memory location to stack.
HEADER AT "@"
AT:
LDW Y,X
LDW X,(X)
LDW X,(X)
EXGW X,Y
LDW (X),Y
RET
; ! ( w a -- ) ( TOS STM8: -- Y,Z,N )
; Pop data stack to memory.
HEADER STORE "!"
STORE:
CALL YFLAGS ; a
PUSHW X
LDW X,(X) ; w
LDW (Y),X
POPW X
JRA DROP
; C@ ( a -- c ) ( TOS STM8: -- A,Z,N )
; Push byte in memory to stack.
; STM8: Z,N
HEADER CAT "C@"
CAT:
LDW Y,X ; Y=a
LDW Y,(Y)
YCAT:
LD A,(Y)
CLR (X)
LD (1,X),A
RET
; C! ( c a -- )
; Pop data stack to byte memory.
HEADER CSTOR "C!"
CSTOR:
CALL YFLAGS
INCW X
LD A,(X)
LD (Y),A
INCW X
RET
; R> ( -- w ) ( TOS STM8: -- Y,Z,N )
; Pop return stack to data stack.
HEADFLG RFROM "R>" COMPO
RFROM:
POPW Y ; save return addr
LDW YTEMP,Y
POPW Y
DECW X
DECW X
LDW (X),Y
JP [YTEMP]
.ifne HAS_CPNVM
; doVARPTR ( - a ) ( TOS STM8: - Y,Z,N )
DOVARPTR:
POPW Y ; get return addr (pfa)
LDW Y,(Y)
JRA YSTOR
.endif
; doVAR ( -- a ) ( TOS STM8: -- Y,Z,N )
; Code for VARIABLE and CREATE.
HEADFLG DOVAR "doVar" COMPO
DOVAR:
POPW Y ; get return addr (pfa)
; fall through
; Y> ( -- n ) ( TOS STM8: - Y,Z,N )
; push Y to stack
; GENALIAS YSTOR "Y>"
YSTOR:
DECW X ; SUBW X,#2
DECW X