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cpucounters.h
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/*
Copyright (c) 2009-2013, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// written by Roman Dementiev
// Thomas Willhalm
#ifndef CPUCOUNTERS_HEADER
#define CPUCOUNTERS_HEADER
/*! \file cpucounters.h
\brief Main CPU counters header
Include this header file if you want to access CPU counters (core and uncore - including memory controller chips and QPI)
*/
#define INTEL_PCM_VERSION "V2.11 (2016-04-20 12:01:09 +0200 ID=56de28a)"
#define INTEL_PCM_COPYRIGHT " Copyright (c) 2009-2016 Intel Corporation"
#ifndef INTELPCM_API
#define INTELPCM_API
#endif
#include "types.h"
#include "msr.h"
#include "pci.h"
#include "client_bw.h"
#include "width_extender.h"
#include <vector>
#include <limits>
#include <string>
#include <memory>
#include <string.h>
#ifdef PCM_USE_PERF
#include <linux/perf_event.h>
#include <sys/syscall.h>
#include <errno.h>
#define PCM_PERF_COUNT_HW_REF_CPU_CYCLES (9)
#endif
#ifndef _MSC_VER
#define NOMINMAX
#include <semaphore.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h>
#endif
class SystemCounterState;
class SocketCounterState;
class CoreCounterState;
class BasicCounterState;
class ServerUncorePowerState;
class PCM;
/*
CPU performance monitoring routines
A set of performance monitoring routines for recent Intel CPUs
*/
struct INTELPCM_API TopologyEntry // decribes a core
{
int32 os_id;
int32 socket;
int32 core_id;
TopologyEntry() : os_id(-1), socket(-1), core_id(-1) { }
};
//! Object to access uncore counters in a socket/processor with microarchitecture codename SandyBridge-EP (Jaketown) or Ivytown-EP or Ivytown-EX
class ServerPCICFGUncore
{
int32 bus;
uint32 groupnr;
std::vector<std::shared_ptr<PciHandleM> > imcHandles;
std::vector<std::shared_ptr<PciHandleM> > qpiLLHandles;
std::vector<uint64> qpi_speed;
uint32 num_imc;
uint32 MCX_CHY_REGISTER_DEV_ADDR[2][4];
uint32 MCX_CHY_REGISTER_FUNC_ADDR[2][4];
uint32 QPI_PORTX_REGISTER_DEV_ADDR[3];
uint32 QPI_PORTX_REGISTER_FUNC_ADDR[3];
static std::vector<std::pair<uint32,uint32> > socket2bus;
void initSocket2Bus();
ServerPCICFGUncore(); // forbidden
ServerPCICFGUncore(ServerPCICFGUncore &); // forbidden
ServerPCICFGUncore & operator =(const ServerPCICFGUncore &); // forbidden
PciHandleM * createIntelPerfMonDevice(uint32 groupnr, int32 bus, uint32 dev, uint32 func, bool checkVendor = false);
void programIMC(const uint32 * MCCntConfig);
public:
//! \brief Initialize access data structures
//! \param socket_ socket id
//! \param pcm pointer to PCM instance
ServerPCICFGUncore(uint32 socket_, PCM * pcm);
//! \brief Program performance counters (disables programming power counters)
void program();
//! \brief Get the number of integrated controller reads (in cache lines)
uint64 getImcReads();
//! \brief Get the number of integrated controller writes (in cache lines)
uint64 getImcWrites();
//! \brief Get the number of incoming data flits to the socket through a port
//! \param port QPI port id
uint64 getIncomingDataFlits(uint32 port);
//! \brief Get the number of outgoing data and non-data flits from the socket through a port
//! \param port QPI port id
uint64 getOutgoingDataNonDataFlits(uint32 port);
virtual ~ServerPCICFGUncore();
//! \brief Program power counters (disables programming performance counters)
//! \param mc_profile memory controller measurement profile. See description of profiles in pcm-power.cpp
void program_power_metrics(int mc_profile);
//! \brief Program memory counters (disables programming performance counters)
//! \param rankA count DIMM rank1 statistics (disables memory channel monitoring)
//! \param rankB count DIMM rank2 statistics (disables memory channel monitoring)
void programServerUncoreMemoryMetrics(int rankA = -1, int rankB = -1);
//! \brief Get number of QPI LL clocks on a QPI port
//! \param port QPI port number
uint64 getQPIClocks(uint32 port);
//! \brief Get number cycles on a QPI port when the link was in a power saving half-lane mode
//! \param port QPI port number
uint64 getQPIL0pTxCycles(uint32 port);
//! \brief Get number cycles on a QPI port when the link was in a power saving shutdown mode
//! \param port QPI port number
uint64 getQPIL1Cycles(uint32 port);
//! \brief Get number DRAM channel cycles
//! \param channel channel number
uint64 getDRAMClocks(uint32 channel);
//! \brief Direct read of memory controller PMU counter (counter meaning depends on the programming: power/performance/etc)
//! \param channel channel number
//! \param counter counter number
uint64 getMCCounter(uint32 channel, uint32 counter);
//! \brief Direct read of QPI LL PMU counter (counter meaning depends on the programming: power/performance/etc)
//! \param port port number
//! \param counter counter number
uint64 getQPILLCounter(uint32 port, uint32 counter);
//! \brief Freezes event counting
void freezeCounters();
//! \brief Unfreezes event counting
void unfreezeCounters();
//! \brief Measures/computes the maximum theoretical QPI link bandwidth speed in GByte/seconds
uint64 computeQPISpeed(const uint32 ref_core, const int cpumodel);
//! \brief Enable correct counting of various LLC events (with memory access perf penalty)
void enableJKTWorkaround(bool enable);
//! \brief Returns the number of detected QPI ports
size_t getNumQPIPorts() const { return (size_t)qpiLLHandles.size(); }
//! \brief Returns the speed of the QPI link
uint64 getQPILinkSpeed(const uint32 linkNr) const {
return qpi_speed.empty() ? 0 : qpi_speed[linkNr];
}
//! \brief Print QPI Speeds
void reportQPISpeed() const
{
std::cerr.precision(1);
std::cerr << std::fixed;
for (uint32 i = 0; i<(uint32)qpi_speed.size(); ++i)
std::cerr << "Max QPI link " << i << " speed: " << qpi_speed[i] / (1e9) << " GBytes/second (" << qpi_speed[i] / (1e9*double(DATA_BYTES_PER_QPI_CYCLE)) << " GT/second)" << std::endl;
}
//! \brief Returns the number of detected integrated memory controllers
uint32 getNumMC() const { return num_imc; }
//! \brief Returns the total number of detected memory channels on all integrated memory controllers
size_t getNumMCChannels() const { return (size_t) imcHandles.size(); }
};
class PCIeCounterState
{
friend uint64 getNumberOfEvents(PCIeCounterState before, PCIeCounterState after);
friend class PCM;
uint64 data;
public:
PCIeCounterState(): data(0)
{
}
virtual ~PCIeCounterState() {}
};
#ifndef HACK_TO_REMOVE_DUPLICATE_ERROR
template class INTELPCM_API std::allocator<TopologyEntry>;
template class INTELPCM_API std::vector<TopologyEntry>;
template class INTELPCM_API std::allocator<CounterWidthExtender*>;
template class INTELPCM_API std::vector<CounterWidthExtender*>;
template class INTELPCM_API std::allocator<uint32>;
template class INTELPCM_API std::vector<uint32>;
template class INTELPCM_API std::allocator<char>;
#endif
/*!
\brief CPU Performance Monitor
This singleton object needs to be instantiated for each process
before accessing counting and measuring routines
*/
class INTELPCM_API PCM
{
friend class BasicCounterState;
friend class UncoreCounterState;
PCM(); // forbidden to call directly because it is a singleton
int32 cpu_family;
int32 cpu_model, original_cpu_model;
int32 threads_per_core;
int32 num_cores;
int32 num_sockets;
int32 num_phys_cores_per_socket;
int32 num_online_cores;
uint32 core_gen_counter_num_max;
uint32 core_gen_counter_num_used;
uint32 core_gen_counter_width;
uint32 core_fixed_counter_num_max;
uint32 core_fixed_counter_num_used;
uint32 core_fixed_counter_width;
uint32 uncore_gen_counter_num_max;
uint32 uncore_gen_counter_num_used;
uint32 uncore_gen_counter_width;
uint32 uncore_fixed_counter_num_max;
uint32 uncore_fixed_counter_num_used;
uint32 uncore_fixed_counter_width;
uint32 perfmon_version;
int32 perfmon_config_anythread;
uint64 nominal_frequency;
uint64 max_qpi_speed; // in GBytes/second
uint32 L3ScalingFactor;
int32 pkgThermalSpecPower, pkgMinimumPower, pkgMaximumPower;
std::vector<TopologyEntry> topology;
std::string errorMessage;
static PCM * instance;
bool allow_multiple_instances;
bool programmed_pmu;
std::vector<std::shared_ptr<SafeMsrHandle> > MSR;
std::vector<std::shared_ptr<ServerPCICFGUncore> > server_pcicfg_uncore;
uint64 PCU_MSR_PMON_BOX_CTL_ADDR, PCU_MSR_PMON_CTRX_ADDR[4];
double joulesPerEnergyUnit;
std::vector<std::shared_ptr<CounterWidthExtender> > energy_status;
std::vector<std::shared_ptr<CounterWidthExtender> > dram_energy_status;
std::vector<std::shared_ptr<CounterWidthExtender> > memory_bw_local;
std::vector<std::shared_ptr<CounterWidthExtender> > memory_bw_total;
std::shared_ptr<ClientBW> clientBW;
std::shared_ptr<CounterWidthExtender> clientImcReads;
std::shared_ptr<CounterWidthExtender> clientImcWrites;
std::shared_ptr<CounterWidthExtender> clientIoRequests;
bool disable_JKT_workaround;
bool blocked; // track if time-driven counter update is running or not: PCM is blocked
uint64 * coreCStateMsr; // MSR addresses of core C-state free-running counters
uint64 * pkgCStateMsr; // MSR addresses of package C-state free-running counters
public:
enum { MAX_C_STATE = 10 }; // max C-state on Intel architecture
//! \brief Returns true if the specified core C-state residency metric is supported
bool isCoreCStateResidencySupported(int state)
{
if (state == 0 || state == 1)
return true;
return (coreCStateMsr != NULL && state <= ((int)MAX_C_STATE) && coreCStateMsr[state] != 0);
}
//! \brief Returns true if the specified package C-state residency metric is supported
bool isPackageCStateResidencySupported(int state)
{
return (pkgCStateMsr != NULL && state <= ((int)MAX_C_STATE) && pkgCStateMsr[state] != 0);
}
//! \brief Redirects output destination to provided file, instead of std::cout
void setOutput(const std::string filename);
//! \brief Restores output, closes output file if opened
void restoreOutput();
//! \brief Set Run State.
// Arguments:
// -- 1 - program is running
// -- 0 -pgram is sleeping
void setRunState(int new_state) { run_state = new_state; }
//! \brief Returns program's Run State.
// Results:
// -- 1 - program is running
// -- 0 -pgram is sleeping
int getRunState(void) { return run_state; }
bool isBlocked(void) { return blocked; }
void setBlocked(const bool new_blocked) { blocked = new_blocked; }
//! \brief Call it before program() to allow multiple running instances of PCM on the same system
void allowMultipleInstances()
{
allow_multiple_instances = true;
}
//! Mode of programming (parameter in the program() method)
enum ProgramMode {
DEFAULT_EVENTS = 0, /*!< Default choice of events, the additional parameter is not needed and ignored */
CUSTOM_CORE_EVENTS = 1, /*!< Custom set of core events specified in the parameter to the program method. The parameter must be a pointer to array of four \c CustomCoreEventDescription values */
EXT_CUSTOM_CORE_EVENTS = 2, /*!< Custom set of core events specified in the parameter to the program method. The parameter must be a pointer to a \c ExtendedCustomCoreEventDescription data structure */
INVALID_MODE /*!< Non-programmed mode */
};
//! Return codes (e.g. for program(..) method)
enum ErrorCode {
Success = 0,
MSRAccessDenied = 1,
PMUBusy = 2,
UnknownError
};
/*! \brief Custom Core event description
See "Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
System Programming Guide, Part 2" for the concrete values of the data structure fields,
e.g. Appendix A.2 "Performance Monitoring Events for Intel(r) Core(tm) Processor Family
and Xeon Processor Family"
*/
struct CustomCoreEventDescription
{
int32 event_number, umask_value;
};
/*! \brief Extended custom core event description
In contrast to CustomCoreEventDescription supports configuration of all fields.
See "Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
System Programming Guide, Part 2" for the concrete values of the data structure fields,
e.g. Appendix A.2 "Performance Monitoring Events for Intel(r) Core(tm) Processor Family
and Xeon Processor Family"
*/
struct ExtendedCustomCoreEventDescription
{
FixedEventControlRegister * fixedCfg; // if NULL, then default configuration performed for fixed counters
uint32 nGPCounters; // number of general purpose counters
EventSelectRegister * gpCounterCfg; // general purpose counters, if NULL, then default configuration performed for GP counters
uint64 OffcoreResponseMsrValue[2];
ExtendedCustomCoreEventDescription() : fixedCfg(NULL), nGPCounters(0), gpCounterCfg(NULL) {
OffcoreResponseMsrValue[0] = 0;
OffcoreResponseMsrValue[1] = 0;
}
};
private:
ProgramMode mode;
CustomCoreEventDescription coreEventDesc[4];
#ifdef _MSC_VER
HANDLE numInstancesSemaphore; // global semaphore that counts the number of PCM instances on the system
#else
// global semaphore that counts the number of PCM instances on the system
sem_t * numInstancesSemaphore;
#endif
std::vector<int32> socketRefCore;
bool canUsePerf;
#ifdef PCM_USE_PERF
std::vector< std::vector<int> > perfEventHandle;
void readPerfData(uint32 core, std::vector<uint64> & data);
enum {
PERF_INST_RETIRED_ANY_POS = 0,
PERF_CPU_CLK_UNHALTED_THREAD_POS = 1,
PERF_CPU_CLK_UNHALTED_REF_POS = 2,
PERF_GEN_EVENT_0_POS = 3,
PERF_GEN_EVENT_1_POS = 4,
PERF_GEN_EVENT_2_POS = 5,
PERF_GEN_EVENT_3_POS = 6
};
enum {
PERF_GROUP_LEADER_COUNTER = PERF_INST_RETIRED_ANY_POS
};
#endif
std::ofstream *outfile; // output file stream
std::streambuf *backup_ofile; // backup of original output = cout
int run_state; // either running (1) or sleeping (0)
bool PMUinUse();
void cleanupPMU();
void freeRMID();
bool decrementInstanceSemaphore(); // returns true if it was the last instance
#ifdef __APPLE__
// OSX does not have sem_getvalue, so we must get the number of instances by a different method
uint32 getNumInstances();
uint32 decrementNumInstances();
uint32 incrementNumInstances();
#endif
void computeQPISpeedBeckton(int core_nr);
void destroyMSR();
void computeNominalFrequency();
static bool isCPUModelSupported(int model_);
std::string getSupportedUarchCodenames() const;
std::string getUnsupportedMessage() const;
bool detectModel();
bool checkModel();
void initCStateSupportTables();
bool discoverSystemTopology();
void printSystemTopology() const;
bool initMSR();
bool detectNominalFrequency();
void initEnergyMonitoring();
void initUncoreObjects();
/*!
* \brief initializes each core with an RMID
*
* \returns nothing
*/
void initRMID();
/*!
* \brief initializes each core event MSR with an RMID for QOS event (L3 cache monitoring or memory bandwidth monitoring)
*
* \returns nothing
*/
void initQOSevent(const uint64 event, const int32 core);
void programBecktonUncore(int core);
void programNehalemEPUncore(int core);
void enableJKTWorkaround(bool enable);
template <class CounterStateType>
void readAndAggregateMemoryBWCounters(const uint32 core, CounterStateType & counterState);
template <class CounterStateType>
void readAndAggregateUncoreMCCounters(const uint32 socket, CounterStateType & counterState);
template <class CounterStateType>
void readAndAggregateEnergyCounters(const uint32 socket, CounterStateType & counterState);
template <class CounterStateType>
void readPackageThermalHeadroom(const uint32 socket, CounterStateType & counterState);
template <class CounterStateType>
void readAndAggregatePackageCStateResidencies(std::shared_ptr<SafeMsrHandle> msr, CounterStateType & result);
void readQPICounters(SystemCounterState & counterState);
void reportQPISpeed() const;
uint64 CX_MSR_PMON_CTRY(uint32 Cbo, uint32 Ctr) const;
uint64 CX_MSR_PMON_BOX_FILTER(uint32 Cbo) const;
uint64 CX_MSR_PMON_BOX_FILTER1(uint32 Cbo) const;
uint64 CX_MSR_PMON_CTLY(uint32 Cbo, uint32 Ctl) const;
uint64 CX_MSR_PMON_BOX_CTL(uint32 Cbo) const;
uint32 getMaxNumOfCBoxes() const;
void programCboOpcodeFilter(const uint32 opc, const uint32 cbo, std::shared_ptr<SafeMsrHandle> msr);
public:
/*!
\brief checks if QOS monitoring support present
\returns true or false
*/
bool QOSMetricAvailable();
/*!
\brief checks L3 cache support for QOS present
\returns true or false
*/
bool L3QOSMetricAvailable();
/*!
\brief checks if L3 cache monitoring present
\returns true or false
*/
bool L3CacheOccupancyMetricAvailable();
/*!
\brief checks if local memory bandwidth monitoring present
\returns true or false
*/
bool CoreLocalMemoryBWMetricAvailable();
/*!
\brief checks if total memory bandwidth monitoring present
\returns true or false
*/
bool CoreRemoteMemoryBWMetricAvailable();
/*!
* \brief returns the max number of RMID supported by socket
*
* \returns maximum number of RMID supported by socket
*/
unsigned getMaxRMID() const;
/*!
\brief Returns PCM object
Returns PCM object. If the PCM has not been created before than
an instance is created. PCM is a singleton.
\return Pointer to PCM object
*/
static PCM * getInstance(); // the only way to get access
/*!
\brief Checks the status of PCM object
Call this method to check if PCM gained access to model specific registers. The method is deprecated, see program error code instead.
\return true iff access to model specific registers works without problems
*/
bool good(); // true if access to CPU counters works
/*! \brief Returns the error message
Call this when good() returns false, otherwise return an empty string
*/
const std::string & getErrorMessage() const
{
return errorMessage;
}
/*! \brief Programs performance counters
\param mode_ mode of programming, see ProgramMode definition
\param parameter_ optional parameter for some of programming modes
Call this method before you start using the performance counting routines.
\warning Using this routines with other tools that *program* Performance Monitoring
Units (PMUs) on CPUs is not recommended because PMU can not be shared. Tools that are known to
program PMUs: Intel(r) VTune(tm), Intel(r) Performance Tuning Utility (PTU). This code may make
VTune or PTU measurements invalid. VTune or PTU measurement may make measurement with this code invalid. Please enable either usage of these routines or VTune/PTU/etc.
*/
ErrorCode program(const ProgramMode mode_ = DEFAULT_EVENTS, const void * parameter_ = NULL); // program counters and start counting
/*! \brief Programs uncore power/energy counters on microarchitectures codename SandyBridge-EP and later Xeon uarch
\param mc_profile profile for integrated memory controller PMU. See possible profile values in pcm-power.cpp example
\param pcu_profile profile for power control unit PMU. See possible profile values in pcm-power.cpp example
\param freq_bands array of three integer values for core frequency band monitoring. See usage in pcm-power.cpp example
Call this method before you start using the power counter routines on microarchitecture codename SandyBridge-EP and later Xeon uarch
\warning After this call the memory and QPI bandwidth counters on microarchitecture codename SandyBridge-EP and later Xeon uarch will not work.
\warning Using this routines with other tools that *program* Performance Monitoring
Units (PMUs) on CPUs is not recommended because PMU can not be shared. Tools that are known to
program PMUs: Intel(r) VTune(tm), Intel(r) Performance Tuning Utility (PTU). This code may make
VTune or PTU measurements invalid. VTune or PTU measurement may make measurement with this code invalid. Please enable either usage of these routines or VTune/PTU/etc.
*/
ErrorCode programServerUncorePowerMetrics(int mc_profile, int pcu_profile, int * freq_bands = NULL);
/*! \brief Programs uncore memory counters on microarchitectures codename SandyBridge-EP and later Xeon uarch
\param rankA count DIMM rank1 statistics (disables memory channel monitoring)
\param rankB count DIMM rank2 statistics (disables memory channel monitoring)
Call this method before you start using the memory counter routines on microarchitecture codename SandyBridge-EP and later Xeon uarch
\warning Using this routines with other tools that *program* Performance Monitoring
Units (PMUs) on CPUs is not recommended because PMU can not be shared. Tools that are known to
program PMUs: Intel(r) VTune(tm), Intel(r) Performance Tuning Utility (PTU). This code may make
VTune or PTU measurements invalid. VTune or PTU measurement may make measurement with this code invalid. Please enable either usage of these routines or VTune/PTU/etc.
*/
ErrorCode programServerUncoreMemoryMetrics(int rankA = -1, int rankB = -1);
//! \brief Freezes uncore event counting (works only on microarchitecture codename SandyBridge-EP and IvyTown)
void freezeServerUncoreCounters();
//! \brief Unfreezes uncore event counting (works only on microarchitecture codename SandyBridge-EP and IvyTown)
void unfreezeServerUncoreCounters();
/*! \brief Reads the power/energy counter state of a socket (works only on microarchitecture codename SandyBridge-EP)
\param socket socket id
\return State of power counters in the socket
*/
ServerUncorePowerState getServerUncorePowerState(uint32 socket);
/*! \brief Cleanups resources and stops performance counting
One needs to call this method when your program finishes or/and you are not going to use the
performance counting routines anymore.
*/
void cleanup();
/*! \brief Forces PMU reset
If there is no chance to free up PMU from other applications you might try to call this method at your own risk.
*/
void resetPMU();
/*! \brief Reads all counter states (including system, sockets and cores)
\param systemState system counter state (return parameter)
\param socketStates socket counter states (return parameter)
\param coreStates core counter states (return parameter)
*/
void getAllCounterStates(SystemCounterState & systemState, std::vector<SocketCounterState> & socketStates, std::vector<CoreCounterState> & coreStates);
/*! \brief Return true if the core in online
\param i OS core id
*/
bool isCoreOnline(int32 os_core_id) const;
/*! \brief Reads the counter state of the system
System consists of several sockets (CPUs).
Socket has a CPU in it. Socket (CPU) consists of several (logical) cores.
\return State of counters in the entire system
*/
SystemCounterState getSystemCounterState();
/*! \brief Reads the counter state of a socket
\param socket socket id
\return State of counters in the socket
*/
SocketCounterState getSocketCounterState(uint32 socket);
/*! \brief Reads the counter state of a (logical) core
Be aware that during the measurement other threads may be scheduled on the same core by the operating system (this is called context-switching). The performance events caused by these threads will be counted as well.
\param core core id
\return State of counters in the core
*/
CoreCounterState getCoreCounterState(uint32 core);
/*! \brief Reads number of logical cores in the system
\return Number of logical cores in the system
*/
uint32 getNumCores();
/*! \brief Reads number of online logical cores in the system
\return Number of online logical cores in the system
*/
uint32 getNumOnlineCores();
/*! \brief Reads number of sockets (CPUs) in the system
\return Number of sockets in the system
*/
uint32 getNumSockets();
/*! \brief Reads how many hardware threads has a physical core
"Hardware thread" is a logical core in a different terminology.
If Intel(r) Hyperthreading(tm) is enabled then this function returns 2.
\return Number of hardware threads per physical core
*/
uint32 getThreadsPerCore();
/*! \brief Checks if SMT (HyperThreading) is enabled.
\return true iff SMT (HyperThreading) is enabled.
*/
bool getSMT(); // returns true iff SMT ("Hyperthreading") is on
/*! \brief Reads the nominal core frequency
\return Nominal frequency in Hz
*/
uint64 getNominalFrequency(); // in Hz
/*! \brief runs CPUID.0xF.0x01 to get the L3 up scaling factor to calculate L3 Occupancy
* Scaling factor is returned in EBX register after running the CPU instruction
* \return L3 up scaling factor
*/
uint32 getL3ScalingFactor();
//! \brief Identifiers of supported CPU models
enum SupportedCPUModels
{
NEHALEM_EP = 26,
NEHALEM = 30,
ATOM = 28,
ATOM_2 = 53,
ATOM_CENTERTON = 54,
ATOM_BAYTRAIL = 55,
ATOM_AVOTON = 77,
ATOM_CHERRYTRAIL = 76,
CLARKDALE = 37,
WESTMERE_EP = 44,
NEHALEM_EX = 46,
WESTMERE_EX = 47,
SANDY_BRIDGE = 42,
JAKETOWN = 45,
IVY_BRIDGE = 58,
HASWELL = 60,
HASWELL_ULT = 69,
HASWELL_2 = 70,
IVYTOWN = 62,
HASWELLX = 63,
BROADWELL = 61,
BROADWELL_XEON_E3 = 71,
BDX_DE = 86,
SKL_UY = 78,
BDX = 79,
SKL = 94,
END_OF_MODEL_LIST = 0x0ffff
};
//! \brief Reads CPU model id
//! \return CPU model ID
uint32 getCPUModel() { return (uint32)cpu_model; }
//! \brief Reads original CPU model id
//! \return CPU model ID
uint32 getOriginalCPUModel() { return (uint32)original_cpu_model; }
//! \brief Determines socket of given core
//! \param core_id core identifier
//! \return socket identifier
int32 getSocketId(uint32 core_id)
{
return (int32)topology[core_id].socket;
}
//! \brief Returns the number of Intel(r) Quick Path Interconnect(tm) links per socket
//! \return number of QPI links per socket
uint64 getQPILinksPerSocket() const
{
switch (cpu_model)
{
case NEHALEM_EP:
case WESTMERE_EP:
case CLARKDALE:
if (num_sockets == 2)
return 2;
else
return 1;
case NEHALEM_EX:
case WESTMERE_EX:
return 4;
case JAKETOWN:
case IVYTOWN:
case HASWELLX:
case BDX_DE:
case BDX:
return (server_pcicfg_uncore.size() && server_pcicfg_uncore[0].get())?(server_pcicfg_uncore[0]->getNumQPIPorts()):0;
}
return 0;
}
//! \brief Returns the number of detected integrated memory controllers per socket
uint32 getMCPerSocket() const
{
switch (cpu_model)
{
case NEHALEM_EP:
case WESTMERE_EP:
case CLARKDALE:
return 1;
case NEHALEM_EX:
case WESTMERE_EX:
return 2;
case JAKETOWN:
case IVYTOWN:
case HASWELLX:
case BDX_DE:
case BDX:
return (server_pcicfg_uncore.size() && server_pcicfg_uncore[0].get())?(server_pcicfg_uncore[0]->getNumMC()):0;
}
return 0;
}
//! \brief Returns the total number of detected memory channels on all integrated memory controllers per socket
size_t getMCChannelsPerSocket() const
{
switch (cpu_model)
{
case NEHALEM_EP:
case WESTMERE_EP:
case CLARKDALE:
return 3;
case NEHALEM_EX:
case WESTMERE_EX:
return 4;
case JAKETOWN:
case IVYTOWN:
case HASWELLX:
case BDX_DE:
case BDX:
return (server_pcicfg_uncore.size() && server_pcicfg_uncore[0].get())?(server_pcicfg_uncore[0]->getNumMCChannels()):0;
}
return 0;
}
//! \brief Returns the max number of instructions per cycle
//! \return max number of instructions per cycle
uint32 getMaxIPC() const
{
switch (cpu_model)
{
case NEHALEM_EP:
case WESTMERE_EP:
case NEHALEM_EX:
case WESTMERE_EX:
case CLARKDALE:
case SANDY_BRIDGE:
case JAKETOWN:
case IVYTOWN:
case IVY_BRIDGE:
case HASWELL:
case HASWELLX:
case BROADWELL:
case BDX_DE:
case BDX:
case SKL:
return 4;
case ATOM:
return 2;
}
return 0;
}
//! \brief Returns the frequency of Power Control Unit
uint64 getPCUFrequency() const
{
switch (cpu_model)
{
case JAKETOWN:
case IVYTOWN:
return 800000000ULL; // 800 MHz
case HASWELLX:
case BDX_DE:
case BDX:
return 1000000000ULL; // 1 GHz
}
return 0;
}
//! \brief Return TSC timer value in time units
//! \param multiplier use 1 for seconds, 1000 for ms, 1000000 for mks, etc (default is 1000: ms)
//! \param core core to read on-chip TSC value (default is 0)
//! \return time counter value
uint64 getTickCount(uint64 multiplier = 1000 /* ms */, uint32 core = 0);
//! \brief Return TSC timer value in time units using rdtscp instruction from current core
//! \param multiplier use 1 for seconds, 1000 for ms, 1000000 for mks, etc (default is 1000: ms)
//! \warning Processor support is required bit 27 of cpuid EDX must be set, for Windows, Visual Studio 2010 is required
//! \return time counter value
uint64 getTickCountRDTSCP(uint64 multiplier = 1000 /* ms */);
//! \brief Return QPI Link Speed in GBytes/second
//! \warning Works only for Nehalem-EX (Xeon 7500) and Xeon E7 and E5 processors
//! \return QPI Link Speed in GBytes/second
uint64 getQPILinkSpeed(uint32 socketNr, uint32 linkNr) const
{ return hasPCICFGUncore() ? server_pcicfg_uncore[socketNr]->getQPILinkSpeed(linkNr) : max_qpi_speed; }
//! \brief Returns how many joules are in an internal processor energy unit
double getJoulesPerEnergyUnit() const { return joulesPerEnergyUnit; }
//! \brief Returns thermal specification power of the package domain in Watt
int32 getPackageThermalSpecPower() const { return pkgThermalSpecPower; }
//! \brief Returns minimum power derived from electrical spec of the package domain in Watt
int32 getPackageMinimumPower() const { return pkgMinimumPower; }
//! \brief Returns maximum power derived from electrical spec of the package domain in Watt
int32 getPackageMaximumPower() const { return pkgMaximumPower; }
//! \brief Loads and initializes Winring0 third party library for access to processor model specific and PCI configuration registers
//! \return returns true in case of success
static bool initWinRing0Lib();
inline void disableJKTWorkaround() { disable_JKT_workaround = true; }
enum PCIeEventCode
{
// PCIe read events (PCI devices reading from memory - application writes to disk/network/PCIe device)
PCIeRdCur = 0x19E, // PCIe read current (full cache line)
PCIeNSRd = 0x1E4, // PCIe non-snoop read (full cache line)
// PCIe write events (PCI devices writing to memory - application reads from disk/network/PCIe device)
PCIeWiLF = 0x194, // PCIe Write (non-allocating) (full cache line)
PCIeItoM = 0x19C, // PCIe Write (allocating) (full cache line)
PCIeNSWr = 0x1E5, // PCIe Non-snoop write (partial cache line)
PCIeNSWrF = 0x1E6, // PCIe Non-snoop write (full cache line)
// events shared by CPU and IO
RFO = 0x180, // Demand Data RFO; share the same code for CPU, use tid to filter PCIe only traffic
CRd = 0x181, // Demand Code Read
DRd = 0x182, // Demand Data Read
PRd = 0x187, // Partial Reads (UC) (MMIO Read)
WiL = 0x18F, // Write Invalidate Line - partial (MMIO write), PL: Not documented in HSX/IVT
ItoM = 0x1C8, // Request Invalidate Line; share the same code for CPU, use tid to filter PCIe only traffic
};
enum CBoEventTid
{
RFOtid = 0x3E,
ItoMtid = 0x3E,
};
//! \brief Program uncore PCIe monitoring event(s)
//! \param event_ a PCIe event to monitor
//! \param tid_ tid filter (PCM supports it only on Haswell server)
void programPCIeCounters(const PCIeEventCode event_, const uint32 tid_ = 0, const uint32 miss_ = 0);
void programPCIeMissCounters(const PCIeEventCode event_, const uint32 tid_ = 0);
//! \brief Get the state of PCIe counter(s)
//! \param socket_ socket of the PCIe controller
//! \return State of PCIe counter(s)
PCIeCounterState getPCIeCounterState(const uint32 socket_);
uint64 extractCoreGenCounterValue(uint64 val);
uint64 extractCoreFixedCounterValue(uint64 val);
uint64 extractUncoreGenCounterValue(uint64 val);
uint64 extractUncoreFixedCounterValue(uint64 val);
uint64 extractQOSMonitoring(uint64 val);
//! \brief Get a string describing the codename of the processor microarchitecture
//! \param cpu_model_ cpu model (if no parameter provided the codename of the detected CPU is returned)
const char * getUArchCodename(int32 cpu_model_ = -1) const;
//! \brief Get Brand string of processor
static std::string getCPUBrandString();
std::string getCPUFamilyModelString();
bool packageEnergyMetricsAvailable() const
{
return (
cpu_model == PCM::JAKETOWN
|| cpu_model == PCM::IVYTOWN
|| cpu_model == PCM::SANDY_BRIDGE
|| cpu_model == PCM::IVY_BRIDGE
|| cpu_model == PCM::HASWELL
|| original_cpu_model == PCM::ATOM_AVOTON
|| original_cpu_model == PCM::ATOM_CHERRYTRAIL
|| original_cpu_model == PCM::ATOM_BAYTRAIL
|| cpu_model == PCM::HASWELLX
|| cpu_model == PCM::BROADWELL
|| cpu_model == PCM::BDX_DE
|| cpu_model == PCM::BDX
|| cpu_model == PCM::SKL
);
}
bool dramEnergyMetricsAvailable() const
{
return (
cpu_model == PCM::JAKETOWN
|| cpu_model == PCM::IVYTOWN
|| cpu_model == PCM::HASWELLX
|| cpu_model == PCM::BDX_DE
|| cpu_model == PCM::BDX
);
}
bool packageThermalMetricsAvailable() const
{
return packageEnergyMetricsAvailable();
}
bool outgoingQPITrafficMetricsAvailable() const
{
return (
cpu_model == PCM::NEHALEM_EX
|| cpu_model == PCM::WESTMERE_EX
|| cpu_model == PCM::JAKETOWN
|| cpu_model == PCM::IVYTOWN
|| cpu_model == PCM::HASWELLX
|| cpu_model == PCM::BDX
);
}
bool incomingQPITrafficMetricsAvailable() const
{
return (
cpu_model == PCM::NEHALEM_EX
|| cpu_model == PCM::WESTMERE_EX
|| cpu_model == PCM::JAKETOWN
|| cpu_model == PCM::IVYTOWN
);
}
bool qpiUtilizationMetricsAvailable() const
{
return outgoingQPITrafficMetricsAvailable();
}
bool memoryTrafficMetricsAvailable() const
{
return !(