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It seems that ADDR_WIDTH changed to RAM_ADDR_WIDTH in latest wb_openram_wrapper version
zero_to_asic_mpw5/verilog/rtl/user_project_wrapper.v
Lines 194 to 196 in 8c3175a
https://github.com/embelon/wb_openram_wrapper/blob/f3184daafa1c6adf541747df3518d9ff5567d84c/src/wb_openram_wrapper.v#L19-L22
The text was updated successfully, but these errors were encountered:
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It seems that ADDR_WIDTH changed to RAM_ADDR_WIDTH in latest wb_openram_wrapper version
zero_to_asic_mpw5/verilog/rtl/user_project_wrapper.v
Lines 194 to 196 in 8c3175a
https://github.com/embelon/wb_openram_wrapper/blob/f3184daafa1c6adf541747df3518d9ff5567d84c/src/wb_openram_wrapper.v#L19-L22
The text was updated successfully, but these errors were encountered: