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ibex_core.sv
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// Copyright lowRISC contributors.
// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
`ifdef RISCV_FORMAL
`define RVFI
`endif
`include "prim_assert.sv"
`include "dv_fcov_macros.svh"
/**
* Top level module of the ibex RISC-V core
*/
module ibex_core import ibex_pkg::*; #(
parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
parameter ibex_pkg::pmp_cfg_t PMPRstCfg[16] = ibex_pkg::PmpCfgRst,
parameter logic [33:0] PMPRstAddr[16] = ibex_pkg::PmpAddrRst,
parameter ibex_pkg::pmp_mseccfg_t PMPRstMsecCfg = ibex_pkg::PmpMseccfgRst,
parameter int unsigned MHPMCounterNum = 0,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit RV32E = 1'b0,
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter bit BranchTargetALU = 1'b0,
parameter bit WritebackStage = 1'b0,
parameter bit ICache = 1'b0,
parameter bit ICacheECC = 1'b0,
parameter int unsigned BusSizeECC = BUS_SIZE,
parameter int unsigned TagSizeECC = IC_TAG_SIZE,
parameter int unsigned LineSizeECC = IC_LINE_SIZE,
parameter bit BranchPredictor = 1'b0,
parameter bit DbgTriggerEn = 1'b0,
parameter int unsigned DbgHwBreakNum = 1,
parameter bit ResetAll = 1'b0,
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
parameter bit SecureIbex = 1'b0,
parameter bit DummyInstructions= 1'b0,
parameter bit RegFileECC = 1'b0,
parameter int unsigned RegFileDataWidth = 32,
parameter bit MemECC = 1'b0,
parameter int unsigned MemDataWidth = MemECC ? 32 + 7 : 32,
parameter int unsigned DmBaseAddr = 32'h1A110000,
parameter int unsigned DmAddrMask = 32'h00000FFF,
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808
) (
// Clock and Reset
input logic clk_i,
// Internally generated resets in ibex_lockstep cause IMPERFECTSCH warnings.
// TODO: Remove when upgrading Verilator #2134.
/* verilator lint_off IMPERFECTSCH */
input logic rst_ni,
/* verilator lint_on IMPERFECTSCH */
input logic [31:0] hart_id_i,
input logic [31:0] boot_addr_i,
// Instruction memory interface
output logic instr_req_o,
input logic instr_gnt_i,
input logic instr_rvalid_i,
output logic [31:0] instr_addr_o,
input logic [MemDataWidth-1:0] instr_rdata_i,
input logic instr_err_i,
// Data memory interface
output logic data_req_o,
input logic data_gnt_i,
input logic data_rvalid_i,
output logic data_we_o,
output logic [3:0] data_be_o,
output logic [31:0] data_addr_o,
output logic [MemDataWidth-1:0] data_wdata_o,
input logic [MemDataWidth-1:0] data_rdata_i,
input logic data_err_i,
// Register file interface
output logic dummy_instr_id_o,
output logic dummy_instr_wb_o,
output logic [4:0] rf_raddr_a_o,
output logic [4:0] rf_raddr_b_o,
output logic [4:0] rf_waddr_wb_o,
output logic rf_we_wb_o,
output logic [RegFileDataWidth-1:0] rf_wdata_wb_ecc_o,
input logic [RegFileDataWidth-1:0] rf_rdata_a_ecc_i,
input logic [RegFileDataWidth-1:0] rf_rdata_b_ecc_i,
// RAMs interface
output logic [IC_NUM_WAYS-1:0] ic_tag_req_o,
output logic ic_tag_write_o,
output logic [IC_INDEX_W-1:0] ic_tag_addr_o,
output logic [TagSizeECC-1:0] ic_tag_wdata_o,
input logic [TagSizeECC-1:0] ic_tag_rdata_i [IC_NUM_WAYS],
output logic [IC_NUM_WAYS-1:0] ic_data_req_o,
output logic ic_data_write_o,
output logic [IC_INDEX_W-1:0] ic_data_addr_o,
output logic [LineSizeECC-1:0] ic_data_wdata_o,
input logic [LineSizeECC-1:0] ic_data_rdata_i [IC_NUM_WAYS],
input logic ic_scr_key_valid_i,
output logic ic_scr_key_req_o,
// Interrupt inputs
input logic irq_software_i,
input logic irq_timer_i,
input logic irq_external_i,
input logic [14:0] irq_fast_i,
input logic irq_nm_i, // non-maskeable interrupt
output logic irq_pending_o,
// Debug Interface
input logic debug_req_i,
output crash_dump_t crash_dump_o,
// SEC_CM: EXCEPTION.CTRL_FLOW.LOCAL_ESC
// SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC
output logic double_fault_seen_o,
// RISC-V Formal Interface
// Does not comply with the coding standards of _i/_o suffixes, but follows
// the convention of RISC-V Formal Interface Specification.
`ifdef RVFI
output logic rvfi_valid,
output logic [63:0] rvfi_order,
output logic [31:0] rvfi_insn,
output logic rvfi_trap,
output logic rvfi_halt,
output logic rvfi_intr,
output logic [ 1:0] rvfi_mode,
output logic [ 1:0] rvfi_ixl,
output logic [ 4:0] rvfi_rs1_addr,
output logic [ 4:0] rvfi_rs2_addr,
output logic [ 4:0] rvfi_rs3_addr,
output logic [31:0] rvfi_rs1_rdata,
output logic [31:0] rvfi_rs2_rdata,
output logic [31:0] rvfi_rs3_rdata,
output logic [ 4:0] rvfi_rd_addr,
output logic [31:0] rvfi_rd_wdata,
output logic [31:0] rvfi_pc_rdata,
output logic [31:0] rvfi_pc_wdata,
output logic [31:0] rvfi_mem_addr,
output logic [ 3:0] rvfi_mem_rmask,
output logic [ 3:0] rvfi_mem_wmask,
output logic [31:0] rvfi_mem_rdata,
output logic [31:0] rvfi_mem_wdata,
output logic [31:0] rvfi_ext_pre_mip,
output logic [31:0] rvfi_ext_post_mip,
output logic rvfi_ext_nmi,
output logic rvfi_ext_nmi_int,
output logic rvfi_ext_debug_req,
output logic rvfi_ext_debug_mode,
output logic rvfi_ext_rf_wr_suppress,
output logic [63:0] rvfi_ext_mcycle,
output logic [31:0] rvfi_ext_mhpmcounters [10],
output logic [31:0] rvfi_ext_mhpmcountersh [10],
output logic rvfi_ext_ic_scr_key_valid,
output logic rvfi_ext_irq_valid,
`endif
// CPU Control Signals
// SEC_CM: FETCH.CTRL.LC_GATED
input ibex_mubi_t fetch_enable_i,
output logic alert_minor_o,
output logic alert_major_internal_o,
output logic alert_major_bus_o,
output ibex_mubi_t core_busy_o
);
localparam int unsigned PMPNumChan = 3;
// SEC_CM: CORE.DATA_REG_SW.SCA
localparam bit DataIndTiming = SecureIbex;
localparam bit PCIncrCheck = SecureIbex;
localparam bit ShadowCSR = 1'b0;
// IF/ID signals
logic dummy_instr_id;
logic instr_valid_id;
logic instr_new_id;
logic [31:0] instr_rdata_id; // Instruction sampled inside IF stage
logic [31:0] instr_rdata_alu_id; // Instruction sampled inside IF stage (replicated to
// ease fan-out)
logic [15:0] instr_rdata_c_id; // Compressed instruction sampled inside IF stage
logic instr_is_compressed_id;
logic instr_perf_count_id;
logic instr_bp_taken_id;
logic instr_fetch_err; // Bus error on instr fetch
logic instr_fetch_err_plus2; // Instruction error is misaligned
logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage
logic [31:0] pc_if; // Program counter in IF stage
logic [31:0] pc_id; // Program counter in ID stage
logic [31:0] pc_wb; // Program counter in WB stage
logic [33:0] imd_val_d_ex[2]; // Intermediate register for multicycle Ops
logic [33:0] imd_val_q_ex[2]; // Intermediate register for multicycle Ops
logic [1:0] imd_val_we_ex;
logic data_ind_timing;
logic dummy_instr_en;
logic [2:0] dummy_instr_mask;
logic dummy_instr_seed_en;
logic [31:0] dummy_instr_seed;
logic icache_enable;
logic icache_inval;
logic icache_ecc_error;
logic pc_mismatch_alert;
logic csr_shadow_err;
logic instr_first_cycle_id;
logic instr_valid_clear;
logic pc_set;
logic nt_branch_mispredict;
logic [31:0] nt_branch_addr;
pc_sel_e pc_mux_id; // Mux selector for next PC
exc_pc_sel_e exc_pc_mux_id; // Mux selector for exception PC
exc_cause_t exc_cause; // Exception cause
logic instr_intg_err;
logic lsu_load_err, lsu_load_err_raw;
logic lsu_store_err, lsu_store_err_raw;
logic lsu_load_resp_intg_err;
logic lsu_store_resp_intg_err;
logic expecting_load_resp_id;
logic expecting_store_resp_id;
// LSU signals
logic lsu_addr_incr_req;
logic [31:0] lsu_addr_last;
// Jump and branch target and decision (EX->IF)
logic [31:0] branch_target_ex;
logic branch_decision;
// Core busy signals
logic ctrl_busy;
logic if_busy;
logic lsu_busy;
// Register File
logic [4:0] rf_raddr_a;
logic [31:0] rf_rdata_a;
logic [4:0] rf_raddr_b;
logic [31:0] rf_rdata_b;
logic rf_ren_a;
logic rf_ren_b;
logic [4:0] rf_waddr_wb;
logic [31:0] rf_wdata_wb;
// Writeback register write data that can be used on the forwarding path (doesn't factor in memory
// read data as this is too late for the forwarding path)
logic [31:0] rf_wdata_fwd_wb;
logic [31:0] rf_wdata_lsu;
logic rf_we_wb;
logic rf_we_lsu;
logic rf_ecc_err_comb;
logic [4:0] rf_waddr_id;
logic [31:0] rf_wdata_id;
logic rf_we_id;
logic rf_rd_a_wb_match;
logic rf_rd_b_wb_match;
// ALU Control
alu_op_e alu_operator_ex;
logic [31:0] alu_operand_a_ex;
logic [31:0] alu_operand_b_ex;
logic [31:0] bt_a_operand;
logic [31:0] bt_b_operand;
logic [31:0] alu_adder_result_ex; // Used to forward computed address to LSU
logic [31:0] result_ex;
// Multiplier Control
logic mult_en_ex;
logic div_en_ex;
logic mult_sel_ex;
logic div_sel_ex;
md_op_e multdiv_operator_ex;
logic [1:0] multdiv_signed_mode_ex;
logic [31:0] multdiv_operand_a_ex;
logic [31:0] multdiv_operand_b_ex;
logic multdiv_ready_id;
// CSR control
logic csr_access;
csr_op_e csr_op;
logic csr_op_en;
csr_num_e csr_addr;
logic [31:0] csr_rdata;
logic [31:0] csr_wdata;
logic illegal_csr_insn_id; // CSR access to non-existent register,
// with wrong priviledge level,
// or missing write permissions
// Data Memory Control
logic lsu_we;
logic [1:0] lsu_type;
logic lsu_sign_ext;
logic lsu_req;
logic lsu_rdata_valid;
logic [31:0] lsu_wdata;
logic lsu_req_done;
// stall control
logic id_in_ready;
logic ex_valid;
logic lsu_resp_valid;
logic lsu_resp_err;
// Signals between instruction core interface and pipe (if and id stages)
logic instr_req_int; // Id stage asserts a req to instruction core interface
logic instr_req_gated;
logic instr_exec;
// Writeback stage
logic en_wb;
wb_instr_type_e instr_type_wb;
logic ready_wb;
logic rf_write_wb;
logic outstanding_load_wb;
logic outstanding_store_wb;
logic dummy_instr_wb;
// Interrupts
logic nmi_mode;
irqs_t irqs;
logic csr_mstatus_mie;
logic [31:0] csr_mepc, csr_depc;
// PMP signals
logic [33:0] csr_pmp_addr [PMPNumRegions];
pmp_cfg_t csr_pmp_cfg [PMPNumRegions];
pmp_mseccfg_t csr_pmp_mseccfg;
logic pmp_req_err [PMPNumChan];
logic data_req_out;
logic csr_save_if;
logic csr_save_id;
logic csr_save_wb;
logic csr_restore_mret_id;
logic csr_restore_dret_id;
logic csr_save_cause;
logic csr_mtvec_init;
logic [31:0] csr_mtvec;
logic [31:0] csr_mtval;
logic csr_mstatus_tw;
priv_lvl_e priv_mode_id;
priv_lvl_e priv_mode_lsu;
// debug mode and dcsr configuration
logic debug_mode;
logic debug_mode_entering;
dbg_cause_e debug_cause;
logic debug_csr_save;
logic debug_single_step;
logic debug_ebreakm;
logic debug_ebreaku;
logic trigger_match;
// signals relating to instruction movements between pipeline stages
// used by performance counters and RVFI
logic instr_id_done;
logic instr_done_wb;
logic perf_instr_ret_wb;
logic perf_instr_ret_compressed_wb;
logic perf_instr_ret_wb_spec;
logic perf_instr_ret_compressed_wb_spec;
logic perf_iside_wait;
logic perf_dside_wait;
logic perf_mul_wait;
logic perf_div_wait;
logic perf_jump;
logic perf_branch;
logic perf_tbranch;
logic perf_load;
logic perf_store;
// for RVFI
logic illegal_insn_id, unused_illegal_insn_id; // ID stage sees an illegal instruction
//////////////////////
// Clock management //
//////////////////////
// Before going to sleep, wait for I- and D-side
// interfaces to finish ongoing operations.
if (SecureIbex) begin : g_core_busy_secure
// For secure Ibex, the individual bits of core_busy_o are generated from different copies of
// the various busy signal.
localparam int unsigned NumBusySignals = 3;
localparam int unsigned NumBusyBits = $bits(ibex_mubi_t) * NumBusySignals;
logic [NumBusyBits-1:0] busy_bits_buf;
prim_buf #(
.Width(NumBusyBits)
) u_fetch_enable_buf (
.in_i ({$bits(ibex_mubi_t){ctrl_busy, if_busy, lsu_busy}}),
.out_o(busy_bits_buf)
);
// Set core_busy_o to IbexMuBiOn if even a single input is high.
for (genvar i = 0; i < $bits(ibex_mubi_t); i++) begin : g_core_busy_bits
if (IbexMuBiOn[i] == 1'b1) begin : g_pos
assign core_busy_o[i] = |busy_bits_buf[i*NumBusySignals +: NumBusySignals];
end else begin : g_neg
assign core_busy_o[i] = ~|busy_bits_buf[i*NumBusySignals +: NumBusySignals];
end
end
end else begin : g_core_busy_non_secure
// For non secure Ibex, synthesis is allowed to optimize core_busy_o.
assign core_busy_o = (ctrl_busy || if_busy || lsu_busy) ? IbexMuBiOn : IbexMuBiOff;
end
//////////////
// IF stage //
//////////////
ibex_if_stage #(
.DmHaltAddr (DmHaltAddr),
.DmExceptionAddr (DmExceptionAddr),
.DummyInstructions(DummyInstructions),
.ICache (ICache),
.ICacheECC (ICacheECC),
.BusSizeECC (BusSizeECC),
.TagSizeECC (TagSizeECC),
.LineSizeECC (LineSizeECC),
.PCIncrCheck (PCIncrCheck),
.ResetAll (ResetAll),
.RndCnstLfsrSeed (RndCnstLfsrSeed),
.RndCnstLfsrPerm (RndCnstLfsrPerm),
.BranchPredictor (BranchPredictor),
.MemECC (MemECC),
.MemDataWidth (MemDataWidth)
) if_stage_i (
.clk_i (clk_i),
.rst_ni(rst_ni),
.boot_addr_i(boot_addr_i),
.req_i (instr_req_gated), // instruction request control
// instruction cache interface
.instr_req_o (instr_req_o),
.instr_addr_o (instr_addr_o),
.instr_gnt_i (instr_gnt_i),
.instr_rvalid_i (instr_rvalid_i),
.instr_rdata_i (instr_rdata_i),
.instr_bus_err_i (instr_err_i),
.instr_intg_err_o (instr_intg_err),
.ic_tag_req_o (ic_tag_req_o),
.ic_tag_write_o (ic_tag_write_o),
.ic_tag_addr_o (ic_tag_addr_o),
.ic_tag_wdata_o (ic_tag_wdata_o),
.ic_tag_rdata_i (ic_tag_rdata_i),
.ic_data_req_o (ic_data_req_o),
.ic_data_write_o (ic_data_write_o),
.ic_data_addr_o (ic_data_addr_o),
.ic_data_wdata_o (ic_data_wdata_o),
.ic_data_rdata_i (ic_data_rdata_i),
.ic_scr_key_valid_i(ic_scr_key_valid_i),
.ic_scr_key_req_o (ic_scr_key_req_o),
// outputs to ID stage
.instr_valid_id_o (instr_valid_id),
.instr_new_id_o (instr_new_id),
.instr_rdata_id_o (instr_rdata_id),
.instr_rdata_alu_id_o (instr_rdata_alu_id),
.instr_rdata_c_id_o (instr_rdata_c_id),
.instr_is_compressed_id_o(instr_is_compressed_id),
.instr_bp_taken_o (instr_bp_taken_id),
.instr_fetch_err_o (instr_fetch_err),
.instr_fetch_err_plus2_o (instr_fetch_err_plus2),
.illegal_c_insn_id_o (illegal_c_insn_id),
.dummy_instr_id_o (dummy_instr_id),
.pc_if_o (pc_if),
.pc_id_o (pc_id),
.pmp_err_if_i (pmp_req_err[PMP_I]),
.pmp_err_if_plus2_i (pmp_req_err[PMP_I2]),
// control signals
.instr_valid_clear_i (instr_valid_clear),
.pc_set_i (pc_set),
.pc_mux_i (pc_mux_id),
.nt_branch_mispredict_i(nt_branch_mispredict),
.exc_pc_mux_i (exc_pc_mux_id),
.exc_cause (exc_cause),
.dummy_instr_en_i (dummy_instr_en),
.dummy_instr_mask_i (dummy_instr_mask),
.dummy_instr_seed_en_i (dummy_instr_seed_en),
.dummy_instr_seed_i (dummy_instr_seed),
.icache_enable_i (icache_enable),
.icache_inval_i (icache_inval),
.icache_ecc_error_o (icache_ecc_error),
// branch targets
.branch_target_ex_i(branch_target_ex),
.nt_branch_addr_i (nt_branch_addr),
// CSRs
.csr_mepc_i (csr_mepc), // exception return address
.csr_depc_i (csr_depc), // debug return address
.csr_mtvec_i (csr_mtvec), // trap-vector base address
.csr_mtvec_init_o(csr_mtvec_init),
// pipeline stalls
.id_in_ready_i(id_in_ready),
.pc_mismatch_alert_o(pc_mismatch_alert),
.if_busy_o (if_busy)
);
// Core is waiting for the ISide when ID/EX stage is ready for a new instruction but none are
// available
assign perf_iside_wait = id_in_ready & ~instr_valid_id;
// Multi-bit fetch enable used when SecureIbex == 1. When SecureIbex == 0 only use the bottom-bit
// of fetch_enable_i. Ensure the multi-bit encoding has the bottom bit set for on and unset for
// off so IbexMuBiOn/IbexMuBiOff can be used without needing to know the value of SecureIbex.
`ASSERT_INIT(IbexMuBiSecureOnBottomBitSet, IbexMuBiOn[0] == 1'b1)
`ASSERT_INIT(IbexMuBiSecureOffBottomBitClear, IbexMuBiOff[0] == 1'b0)
// fetch_enable_i can be used to stop the core fetching new instructions
if (SecureIbex) begin : g_instr_req_gated_secure
// For secure Ibex fetch_enable_i must be a specific multi-bit pattern to enable instruction
// fetch
// SEC_CM: FETCH.CTRL.LC_GATED
assign instr_req_gated = instr_req_int & (fetch_enable_i == IbexMuBiOn);
assign instr_exec = fetch_enable_i == IbexMuBiOn;
end else begin : g_instr_req_gated_non_secure
// For non secure Ibex only the bottom bit of fetch enable is considered
logic unused_fetch_enable;
assign unused_fetch_enable = ^fetch_enable_i[$bits(ibex_mubi_t)-1:1];
assign instr_req_gated = instr_req_int & fetch_enable_i[0];
assign instr_exec = fetch_enable_i[0];
end
//////////////
// ID stage //
//////////////
ibex_id_stage #(
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU(BranchTargetALU),
.DataIndTiming (DataIndTiming),
.WritebackStage (WritebackStage),
.BranchPredictor(BranchPredictor),
.MemECC (MemECC)
) id_stage_i (
.clk_i (clk_i),
.rst_ni(rst_ni),
// Processor Enable
.ctrl_busy_o (ctrl_busy),
.illegal_insn_o(illegal_insn_id),
// from/to IF-ID pipeline register
.instr_valid_i (instr_valid_id),
.instr_rdata_i (instr_rdata_id),
.instr_rdata_alu_i (instr_rdata_alu_id),
.instr_rdata_c_i (instr_rdata_c_id),
.instr_is_compressed_i(instr_is_compressed_id),
.instr_bp_taken_i (instr_bp_taken_id),
// Jumps and branches
.branch_decision_i(branch_decision),
// IF and ID control signals
.instr_first_cycle_id_o(instr_first_cycle_id),
.instr_valid_clear_o (instr_valid_clear),
.id_in_ready_o (id_in_ready),
.instr_exec_i (instr_exec),
.instr_req_o (instr_req_int),
.pc_set_o (pc_set),
.pc_mux_o (pc_mux_id),
.nt_branch_mispredict_o(nt_branch_mispredict),
.nt_branch_addr_o (nt_branch_addr),
.exc_pc_mux_o (exc_pc_mux_id),
.exc_cause_o (exc_cause),
.icache_inval_o (icache_inval),
.instr_fetch_err_i (instr_fetch_err),
.instr_fetch_err_plus2_i(instr_fetch_err_plus2),
.illegal_c_insn_i (illegal_c_insn_id),
.pc_id_i(pc_id),
// Stalls
.ex_valid_i (ex_valid),
.lsu_resp_valid_i(lsu_resp_valid),
.alu_operator_ex_o (alu_operator_ex),
.alu_operand_a_ex_o(alu_operand_a_ex),
.alu_operand_b_ex_o(alu_operand_b_ex),
.imd_val_q_ex_o (imd_val_q_ex),
.imd_val_d_ex_i (imd_val_d_ex),
.imd_val_we_ex_i(imd_val_we_ex),
.bt_a_operand_o(bt_a_operand),
.bt_b_operand_o(bt_b_operand),
.mult_en_ex_o (mult_en_ex),
.div_en_ex_o (div_en_ex),
.mult_sel_ex_o (mult_sel_ex),
.div_sel_ex_o (div_sel_ex),
.multdiv_operator_ex_o (multdiv_operator_ex),
.multdiv_signed_mode_ex_o(multdiv_signed_mode_ex),
.multdiv_operand_a_ex_o (multdiv_operand_a_ex),
.multdiv_operand_b_ex_o (multdiv_operand_b_ex),
.multdiv_ready_id_o (multdiv_ready_id),
// CSR ID/EX
.csr_access_o (csr_access),
.csr_op_o (csr_op),
.csr_addr_o (csr_addr),
.csr_op_en_o (csr_op_en),
.csr_save_if_o (csr_save_if), // control signal to save PC
.csr_save_id_o (csr_save_id), // control signal to save PC
.csr_save_wb_o (csr_save_wb), // control signal to save PC
.csr_restore_mret_id_o(csr_restore_mret_id), // restore mstatus upon MRET
.csr_restore_dret_id_o(csr_restore_dret_id), // restore mstatus upon MRET
.csr_save_cause_o (csr_save_cause),
.csr_mtval_o (csr_mtval),
.priv_mode_i (priv_mode_id),
.csr_mstatus_tw_i (csr_mstatus_tw),
.illegal_csr_insn_i (illegal_csr_insn_id),
.data_ind_timing_i (data_ind_timing),
// LSU
.lsu_req_o (lsu_req), // to load store unit
.lsu_we_o (lsu_we), // to load store unit
.lsu_type_o (lsu_type), // to load store unit
.lsu_sign_ext_o(lsu_sign_ext), // to load store unit
.lsu_wdata_o (lsu_wdata), // to load store unit
.lsu_req_done_i(lsu_req_done), // from load store unit
.lsu_addr_incr_req_i(lsu_addr_incr_req),
.lsu_addr_last_i (lsu_addr_last),
.lsu_load_err_i (lsu_load_err),
.lsu_load_resp_intg_err_i (lsu_load_resp_intg_err),
.lsu_store_err_i (lsu_store_err),
.lsu_store_resp_intg_err_i(lsu_store_resp_intg_err),
.expecting_load_resp_o (expecting_load_resp_id),
.expecting_store_resp_o(expecting_store_resp_id),
// Interrupt Signals
.csr_mstatus_mie_i(csr_mstatus_mie),
.irq_pending_i (irq_pending_o),
.irqs_i (irqs),
.irq_nm_i (irq_nm_i),
.nmi_mode_o (nmi_mode),
// Debug Signal
.debug_mode_o (debug_mode),
.debug_mode_entering_o(debug_mode_entering),
.debug_cause_o (debug_cause),
.debug_csr_save_o (debug_csr_save),
.debug_req_i (debug_req_i),
.debug_single_step_i (debug_single_step),
.debug_ebreakm_i (debug_ebreakm),
.debug_ebreaku_i (debug_ebreaku),
.trigger_match_i (trigger_match),
// write data to commit in the register file
.result_ex_i(result_ex),
.csr_rdata_i(csr_rdata),
.rf_raddr_a_o (rf_raddr_a),
.rf_rdata_a_i (rf_rdata_a),
.rf_raddr_b_o (rf_raddr_b),
.rf_rdata_b_i (rf_rdata_b),
.rf_ren_a_o (rf_ren_a),
.rf_ren_b_o (rf_ren_b),
.rf_waddr_id_o (rf_waddr_id),
.rf_wdata_id_o (rf_wdata_id),
.rf_we_id_o (rf_we_id),
.rf_rd_a_wb_match_o(rf_rd_a_wb_match),
.rf_rd_b_wb_match_o(rf_rd_b_wb_match),
.rf_waddr_wb_i (rf_waddr_wb),
.rf_wdata_fwd_wb_i(rf_wdata_fwd_wb),
.rf_write_wb_i (rf_write_wb),
.en_wb_o (en_wb),
.instr_type_wb_o (instr_type_wb),
.instr_perf_count_id_o (instr_perf_count_id),
.ready_wb_i (ready_wb),
.outstanding_load_wb_i (outstanding_load_wb),
.outstanding_store_wb_i(outstanding_store_wb),
// Performance Counters
.perf_jump_o (perf_jump),
.perf_branch_o (perf_branch),
.perf_tbranch_o (perf_tbranch),
.perf_dside_wait_o(perf_dside_wait),
.perf_mul_wait_o (perf_mul_wait),
.perf_div_wait_o (perf_div_wait),
.instr_id_done_o (instr_id_done)
);
// for RVFI only
assign unused_illegal_insn_id = illegal_insn_id;
ibex_ex_block #(
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU(BranchTargetALU)
) ex_block_i (
.clk_i (clk_i),
.rst_ni(rst_ni),
// ALU signal from ID stage
.alu_operator_i (alu_operator_ex),
.alu_operand_a_i (alu_operand_a_ex),
.alu_operand_b_i (alu_operand_b_ex),
.alu_instr_first_cycle_i(instr_first_cycle_id),
// Branch target ALU signal from ID stage
.bt_a_operand_i(bt_a_operand),
.bt_b_operand_i(bt_b_operand),
// Multipler/Divider signal from ID stage
.multdiv_operator_i (multdiv_operator_ex),
.mult_en_i (mult_en_ex),
.div_en_i (div_en_ex),
.mult_sel_i (mult_sel_ex),
.div_sel_i (div_sel_ex),
.multdiv_signed_mode_i(multdiv_signed_mode_ex),
.multdiv_operand_a_i (multdiv_operand_a_ex),
.multdiv_operand_b_i (multdiv_operand_b_ex),
.multdiv_ready_id_i (multdiv_ready_id),
.data_ind_timing_i (data_ind_timing),
// Intermediate value register
.imd_val_we_o(imd_val_we_ex),
.imd_val_d_o (imd_val_d_ex),
.imd_val_q_i (imd_val_q_ex),
// Outputs
.alu_adder_result_ex_o(alu_adder_result_ex), // to LSU
.result_ex_o (result_ex), // to ID
.branch_target_o (branch_target_ex), // to IF
.branch_decision_o(branch_decision), // to ID
.ex_valid_o(ex_valid)
);
/////////////////////
// Load/store unit //
/////////////////////
assign data_req_o = data_req_out & ~pmp_req_err[PMP_D];
assign lsu_resp_err = lsu_load_err | lsu_store_err;
ibex_load_store_unit #(
.MemECC(MemECC),
.MemDataWidth(MemDataWidth)
) load_store_unit_i (
.clk_i (clk_i),
.rst_ni(rst_ni),
// data interface
.data_req_o (data_req_out),
.data_gnt_i (data_gnt_i),
.data_rvalid_i (data_rvalid_i),
.data_bus_err_i(data_err_i),
.data_pmp_err_i(pmp_req_err[PMP_D]),
.data_addr_o (data_addr_o),
.data_we_o (data_we_o),
.data_be_o (data_be_o),
.data_wdata_o (data_wdata_o),
.data_rdata_i (data_rdata_i),
// signals to/from ID/EX stage
.lsu_we_i (lsu_we),
.lsu_type_i (lsu_type),
.lsu_wdata_i (lsu_wdata),
.lsu_sign_ext_i(lsu_sign_ext),
.lsu_rdata_o (rf_wdata_lsu),
.lsu_rdata_valid_o(lsu_rdata_valid),
.lsu_req_i (lsu_req),
.lsu_req_done_o (lsu_req_done),
.adder_result_ex_i(alu_adder_result_ex),
.addr_incr_req_o(lsu_addr_incr_req),
.addr_last_o (lsu_addr_last),
.lsu_resp_valid_o(lsu_resp_valid),
// exception signals
.load_err_o (lsu_load_err_raw),
.load_resp_intg_err_o (lsu_load_resp_intg_err),
.store_err_o (lsu_store_err_raw),
.store_resp_intg_err_o(lsu_store_resp_intg_err),
.busy_o(lsu_busy),
.perf_load_o (perf_load),
.perf_store_o(perf_store)
);
ibex_wb_stage #(
.ResetAll (ResetAll),
.WritebackStage (WritebackStage),
.DummyInstructions(DummyInstructions)
) wb_stage_i (
.clk_i (clk_i),
.rst_ni (rst_ni),
.en_wb_i (en_wb),
.instr_type_wb_i (instr_type_wb),
.pc_id_i (pc_id),
.instr_is_compressed_id_i(instr_is_compressed_id),
.instr_perf_count_id_i (instr_perf_count_id),
.ready_wb_o (ready_wb),
.rf_write_wb_o (rf_write_wb),
.outstanding_load_wb_o (outstanding_load_wb),
.outstanding_store_wb_o (outstanding_store_wb),
.pc_wb_o (pc_wb),
.perf_instr_ret_wb_o (perf_instr_ret_wb),
.perf_instr_ret_compressed_wb_o (perf_instr_ret_compressed_wb),
.perf_instr_ret_wb_spec_o (perf_instr_ret_wb_spec),
.perf_instr_ret_compressed_wb_spec_o(perf_instr_ret_compressed_wb_spec),
.rf_waddr_id_i(rf_waddr_id),
.rf_wdata_id_i(rf_wdata_id),
.rf_we_id_i (rf_we_id),
.dummy_instr_id_i(dummy_instr_id),
.rf_wdata_lsu_i(rf_wdata_lsu),
.rf_we_lsu_i (rf_we_lsu),
.rf_wdata_fwd_wb_o(rf_wdata_fwd_wb),
.rf_waddr_wb_o(rf_waddr_wb),
.rf_wdata_wb_o(rf_wdata_wb),
.rf_we_wb_o (rf_we_wb),
.dummy_instr_wb_o(dummy_instr_wb),
.lsu_resp_valid_i(lsu_resp_valid),
.lsu_resp_err_i (lsu_resp_err),
.instr_done_wb_o(instr_done_wb)
);
if (SecureIbex) begin : g_check_mem_response
// For secure configurations only process load/store responses if we're expecting them to guard
// against false responses being injected on to the bus
assign lsu_load_err = lsu_load_err_raw & (outstanding_load_wb | expecting_load_resp_id);
assign lsu_store_err = lsu_store_err_raw & (outstanding_store_wb | expecting_store_resp_id);
assign rf_we_lsu = lsu_rdata_valid & (outstanding_load_wb | expecting_load_resp_id);
end else begin : g_no_check_mem_response
// For non-secure configurations trust the bus protocol is being followed and we'll only ever
// see a response if we have an outstanding request.
assign lsu_load_err = lsu_load_err_raw;
assign lsu_store_err = lsu_store_err_raw;
assign rf_we_lsu = lsu_rdata_valid;
// expected_load_resp_id/expected_store_resp_id signals are only used to guard against false
// responses so they are unused in non-secure configurations
logic unused_expecting_load_resp_id;
logic unused_expecting_store_resp_id;
assign unused_expecting_load_resp_id = expecting_load_resp_id;
assign unused_expecting_store_resp_id = expecting_store_resp_id;
end
/////////////////////////////
// Register file interface //
/////////////////////////////
assign dummy_instr_id_o = dummy_instr_id;
assign dummy_instr_wb_o = dummy_instr_wb;
assign rf_raddr_a_o = rf_raddr_a;
assign rf_waddr_wb_o = rf_waddr_wb;
assign rf_we_wb_o = rf_we_wb;
assign rf_raddr_b_o = rf_raddr_b;
if (RegFileECC) begin : gen_regfile_ecc
// SEC_CM: DATA_REG_SW.INTEGRITY
logic [1:0] rf_ecc_err_a, rf_ecc_err_b;
logic rf_ecc_err_a_id, rf_ecc_err_b_id;
// ECC checkbit generation for regiter file wdata
prim_secded_inv_39_32_enc regfile_ecc_enc (
.data_i(rf_wdata_wb),
.data_o(rf_wdata_wb_ecc_o)
);
// ECC checking on register file rdata
prim_secded_inv_39_32_dec regfile_ecc_dec_a (
.data_i (rf_rdata_a_ecc_i),
.data_o (),
.syndrome_o(),
.err_o (rf_ecc_err_a)
);
prim_secded_inv_39_32_dec regfile_ecc_dec_b (
.data_i (rf_rdata_b_ecc_i),
.data_o (),
.syndrome_o(),
.err_o (rf_ecc_err_b)
);
// Assign read outputs - no error correction, just trigger an alert
assign rf_rdata_a = rf_rdata_a_ecc_i[31:0];
assign rf_rdata_b = rf_rdata_b_ecc_i[31:0];
// Calculate errors - qualify with WB forwarding to avoid xprop into the alert signal
assign rf_ecc_err_a_id = |rf_ecc_err_a & rf_ren_a & ~(rf_rd_a_wb_match & rf_write_wb);
assign rf_ecc_err_b_id = |rf_ecc_err_b & rf_ren_b & ~(rf_rd_b_wb_match & rf_write_wb);
// Combined error
assign rf_ecc_err_comb = instr_valid_id & (rf_ecc_err_a_id | rf_ecc_err_b_id);
end else begin : gen_no_regfile_ecc
logic unused_rf_ren_a, unused_rf_ren_b;
logic unused_rf_rd_a_wb_match, unused_rf_rd_b_wb_match;
assign unused_rf_ren_a = rf_ren_a;
assign unused_rf_ren_b = rf_ren_b;
assign unused_rf_rd_a_wb_match = rf_rd_a_wb_match;
assign unused_rf_rd_b_wb_match = rf_rd_b_wb_match;
assign rf_wdata_wb_ecc_o = rf_wdata_wb;
assign rf_rdata_a = rf_rdata_a_ecc_i;
assign rf_rdata_b = rf_rdata_b_ecc_i;
assign rf_ecc_err_comb = 1'b0;
end
///////////////////////
// Crash dump output //
///////////////////////
logic [31:0] crash_dump_mtval;
assign crash_dump_o.current_pc = pc_id;
assign crash_dump_o.next_pc = pc_if;
assign crash_dump_o.last_data_addr = lsu_addr_last;
assign crash_dump_o.exception_pc = csr_mepc;
assign crash_dump_o.exception_addr = crash_dump_mtval;
///////////////////
// Alert outputs //
///////////////////
// Minor alert - core is in a recoverable state
assign alert_minor_o = icache_ecc_error;
// Major internal alert - core is unrecoverable
assign alert_major_internal_o = rf_ecc_err_comb | pc_mismatch_alert | csr_shadow_err;
// Major bus alert
assign alert_major_bus_o = lsu_load_resp_intg_err | lsu_store_resp_intg_err | instr_intg_err;
// Explict INC_ASSERT block to avoid unused signal lint warnings were asserts are not included
`ifdef INC_ASSERT
// Signals used for assertions only
logic outstanding_load_resp;
logic outstanding_store_resp;
logic outstanding_load_id;
logic outstanding_store_id;
assign outstanding_load_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec &
~id_stage_i.lsu_we;
assign outstanding_store_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec &
id_stage_i.lsu_we;
if (WritebackStage) begin : gen_wb_stage
// When the writeback stage is present a load/store could be in ID or WB. A Load/store in ID can
// see a response before it moves to WB when it is unaligned otherwise we should only see
// a response when load/store is in WB.
assign outstanding_load_resp = outstanding_load_wb |
(outstanding_load_id & load_store_unit_i.split_misaligned_access);
assign outstanding_store_resp = outstanding_store_wb |
(outstanding_store_id & load_store_unit_i.split_misaligned_access);
// When writing back the result of a load, the load must have made it to writeback
`ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_wb, clk_i, !rst_ni)
end else begin : gen_no_wb_stage
// Without writeback stage only look into whether load or store is in ID to determine if
// a response is expected.
assign outstanding_load_resp = outstanding_load_id;
assign outstanding_store_resp = outstanding_store_id;
`ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_id, clk_i, !rst_ni)