diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index b9c9070fcb22ff..cf1ba02cbc4b2f 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -907,6 +907,7 @@ Arm and AArch64 Support * Arm Cortex-A520AE (cortex-a520ae). * Arm Cortex-A720AE (cortex-a720ae). * Arm Cortex-R82AE (cortex-r82ae). + * Arm Cortex-R52+ (cortex-r52plus). * Arm Neoverse-N3 (neoverse-n3). * Arm Neoverse-V3 (neoverse-v3). * Arm Neoverse-V3AE (neoverse-v3ae). diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 5ec2743c8d41fc..845e6a09045a85 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -1,7 +1,7 @@ // Use CHECK-NEXT instead of multiple CHECK-SAME to ensure we will fail if there is anything extra in the output. // RUN: not %clang_cc1 -triple armv5--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix ARM // ARM: error: unknown target CPU 'not-a-cpu' -// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, cortex-r52, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, cortex-m35p, cortex-m55, cortex-m85, cortex-m52, cortex-a32, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-x1, cortex-x1c, neoverse-n1, neoverse-n2, neoverse-v1, cyclone, exynos-m3, exynos-m4, exynos-m5, kryo, iwmmxt, xscale, swift{{$}} +// ARM-NEXT: note: valid target CPU values are: arm8, arm810, strongarm, strongarm110, strongarm1100, strongarm1110, arm7tdmi, arm7tdmi-s, arm710t, arm720t, arm9, arm9tdmi, arm920, arm920t, arm922t, arm940t, ep9312, arm10tdmi, arm1020t, arm9e, arm946e-s, arm966e-s, arm968e-s, arm10e, arm1020e, arm1022e, arm926ej-s, arm1136j-s, arm1136jf-s, mpcore, mpcorenovfp, arm1176jz-s, arm1176jzf-s, arm1156t2-s, arm1156t2f-s, cortex-m0, cortex-m0plus, cortex-m1, sc000, cortex-a5, cortex-a7, cortex-a8, cortex-a9, cortex-a12, cortex-a15, cortex-a17, krait, cortex-r4, cortex-r4f, cortex-r5, cortex-r7, cortex-r8, cortex-r52, cortex-r52plus, sc300, cortex-m3, cortex-m4, cortex-m7, cortex-m23, cortex-m33, cortex-m35p, cortex-m55, cortex-m85, cortex-m52, cortex-a32, cortex-a35, cortex-a53, cortex-a55, cortex-a57, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-x1, cortex-x1c, neoverse-n1, neoverse-n2, neoverse-v1, cyclone, exynos-m3, exynos-m4, exynos-m5, kryo, iwmmxt, xscale, swift{{$}} // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64 // AARCH64: error: unknown target CPU 'not-a-cpu' diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index c4a85620fc3ee9..28dd567a610862 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -101,6 +101,7 @@ Changes to the AMDGPU Backend Changes to the ARM Backend -------------------------- +* Added support for Cortex-R52+ CPU. * FEAT_F32MM is no longer activated by default when using `+sve` on v8.6-A or greater. The feature is still available and can be used by adding `+f32mm` to the command line options. * armv8-r now implies only fp-armv8d16sp, rather than neon and full fp-armv8. These features are still included by default for cortex-r52. The default cpu for armv8-r is now "generic", for compatibility with variants that do not include neon, fp64, and d32. diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def b/llvm/include/llvm/TargetParser/ARMTargetParser.def index d7b77a6ef5b68f..e5a1ce54fd46a7 100644 --- a/llvm/include/llvm/TargetParser/ARMTargetParser.def +++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def @@ -330,6 +330,7 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false, ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false, (ARM::AEK_MP | ARM::AEK_HWDIVARM)) ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_NONE) +ARM_CPU_NAME("cortex-r52plus", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_NONE) ARM_CPU_NAME("sc300", ARMV7M, FK_NONE, false, ARM::AEK_NONE) ARM_CPU_NAME("cortex-m3", ARMV7M, FK_NONE, true, ARM::AEK_NONE) ARM_CPU_NAME("cortex-m4", ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE) diff --git a/llvm/lib/Target/ARM/ARMProcessors.td b/llvm/lib/Target/ARM/ARMProcessors.td index eb5ed41ae8a17c..e4e122a0d1339b 100644 --- a/llvm/lib/Target/ARM/ARMProcessors.td +++ b/llvm/lib/Target/ARM/ARMProcessors.td @@ -90,6 +90,8 @@ def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", "Cortex-R7 ARM processors", []>; def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", "Cortex-R52 ARM processors", []>; +def ProcR52plus : SubtargetFeature<"r52plus", "ARMProcFamily", "CortexR52plus", + "Cortex-R52plus ARM processors", []>; def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", "Cortex-M3 ARM processors", []>; @@ -577,3 +579,9 @@ def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, FeatureNEON, FeatureUseMISched, FeatureFPAO]>; + +def : ProcessorModel<"cortex-r52plus", CortexR52Model, [ARMv8r, ProcR52plus, + FeatureFPARMv8, + FeatureNEON, + FeatureUseMISched, + FeatureFPAO]>; diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 5e13d8fabe0485..a8c6cd99633f3e 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -298,6 +298,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { case CortexM3: case CortexM7: case CortexR52: + case CortexR52plus: case CortexX1: case CortexX1C: break; diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index b3b8486c604bdb..369287e2d2037c 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -213,6 +213,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { .Case("0xd23", "cortex-m85") .Case("0xc18", "cortex-r8") .Case("0xd13", "cortex-r52") + .Case("0xd16", "cortex-r52plus") .Case("0xd15", "cortex-r82") .Case("0xd14", "cortex-r82ae") .Case("0xd02", "cortex-a34") diff --git a/llvm/test/CodeGen/ARM/build-attributes.ll b/llvm/test/CodeGen/ARM/build-attributes.ll index e8c83b92f3f947..9220f73d94f8bf 100644 --- a/llvm/test/CodeGen/ARM/build-attributes.ll +++ b/llvm/test/CodeGen/ARM/build-attributes.ll @@ -224,6 +224,10 @@ ; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 -mattr=-neon,-fp64,-d32 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-SP ; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-NEON +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52plus -mattr=-vfp2sp,-fp16 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-NOFPU +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52plus -mattr=-neon,-fp64,-d32 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-SP +; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52plus | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-NEON + ; ARMv8-M ; RUN: llc < %s -mtriple=thumbv8-none-none-eabi -mcpu=cortex-m23 | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=thumbv8-none-none-eabi -mcpu=cortex-m33 | FileCheck %s --check-prefix=NO-STRICT-ALIGN diff --git a/llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll b/llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll index c6bff0c9d5ad50..0cefecd66c71d9 100644 --- a/llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll +++ b/llvm/test/CodeGen/ARM/cortexr52-misched-basic.ll @@ -1,5 +1,6 @@ ; REQUIRES: asserts ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52plus -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC ; ; Check the latency for instructions for both generic and cortex-r52. diff --git a/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll b/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll index 0c519f6285dc99..ea84a3762ec8b1 100644 --- a/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll +++ b/llvm/test/CodeGen/ARM/lsr-scale-addr-mode.ll @@ -4,6 +4,7 @@ ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52plus %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF ; Should not generate negated register offset define void @sintzero(ptr %a) nounwind { diff --git a/llvm/test/CodeGen/ARM/misched-fp-basic.ll b/llvm/test/CodeGen/ARM/misched-fp-basic.ll index 2f672b0cb540fe..eabede386f1f7c 100644 --- a/llvm/test/CodeGen/ARM/misched-fp-basic.ll +++ b/llvm/test/CodeGen/ARM/misched-fp-basic.ll @@ -5,6 +5,8 @@ ; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT ; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \ ; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 +; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52plus -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \ +; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 ; ; Check the latency of instructions for processors with sched-models ; diff --git a/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir b/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir index be5340bd51abbe..0cd20a9f1ff527 100644 --- a/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir +++ b/llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir @@ -5,6 +5,8 @@ # RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9 # RUN: llc -o /dev/null %s -mtriple=thumbv8r-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -verify-misched \ # RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 +# RUN: llc -o /dev/null %s -mtriple=thumbv8r-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -verify-misched \ +# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 # REQUIRES: asserts --- | ; ModuleID = 'foo.ll' diff --git a/llvm/test/CodeGen/ARM/misched-int-basic.mir b/llvm/test/CodeGen/ARM/misched-int-basic.mir index 4a52af1942473f..1a0ee9b19bc725 100644 --- a/llvm/test/CodeGen/ARM/misched-int-basic.mir +++ b/llvm/test/CodeGen/ARM/misched-int-basic.mir @@ -4,6 +4,8 @@ # RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9 # RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -verify-misched \ # RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 +# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -verify-misched \ +# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52 # REQUIRES: asserts --- | ; ModuleID = 'foo.ll' diff --git a/llvm/test/CodeGen/ARM/proc-resource-sched.ll b/llvm/test/CodeGen/ARM/proc-resource-sched.ll index 2dfadda755c6fe..3bd3bff847eefe 100644 --- a/llvm/test/CodeGen/ARM/proc-resource-sched.ll +++ b/llvm/test/CodeGen/ARM/proc-resource-sched.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-R52 +; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52plus -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-R52 ; REQUIRES: asserts ; source_filename = "sched-2.c" diff --git a/llvm/test/CodeGen/ARM/single-issue-r52.mir b/llvm/test/CodeGen/ARM/single-issue-r52.mir index 05b167316ca4e6..084afb6f666c1c 100644 --- a/llvm/test/CodeGen/ARM/single-issue-r52.mir +++ b/llvm/test/CodeGen/ARM/single-issue-r52.mir @@ -1,5 +1,7 @@ # RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN # RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP +# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-topdown 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=TOPDOWN +# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -debug-only=machine-scheduler -misched-bottomup 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=BOTTOMUP # REQUIRES: asserts --- | ; ModuleID = 'foo.ll' diff --git a/llvm/test/CodeGen/ARM/useaa.ll b/llvm/test/CodeGen/ARM/useaa.ll index d70d24b3fd3480..9be0b88b359896 100644 --- a/llvm/test/CodeGen/ARM/useaa.ll +++ b/llvm/test/CodeGen/ARM/useaa.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52plus | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA ; RUN: llc < %s -mtriple=armv7m-eabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA ; RUN: llc < %s -mtriple=armv8m-eabi -mcpu=cortex-m33 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA diff --git a/llvm/test/MC/ARM/dfb-neg.s b/llvm/test/MC/ARM/dfb-neg.s index 15c44877fa6fe5..ec9192bca3ccab 100644 --- a/llvm/test/MC/ARM/dfb-neg.s +++ b/llvm/test/MC/ARM/dfb-neg.s @@ -1,5 +1,7 @@ @ RUN: not llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 -mattr=-dfb -show-encoding < %s 2>&1 | FileCheck %s @ RUN: not llvm-mc -triple thumbv8-none-eabi -mcpu=cortex-r52 -mattr=-dfb -show-encoding < %s 2>&1 | FileCheck %s +@ RUN: not llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52plus -mattr=-dfb -show-encoding < %s 2>&1 | FileCheck %s +@ RUN: not llvm-mc -triple thumbv8-none-eabi -mcpu=cortex-r52plus -mattr=-dfb -show-encoding < %s 2>&1 | FileCheck %s dfb @ CHECK: error: instruction requires: full-data-barrier diff --git a/llvm/test/MC/ARM/dfb.s b/llvm/test/MC/ARM/dfb.s index 58477749807fee..9c4768f6e245b4 100644 --- a/llvm/test/MC/ARM/dfb.s +++ b/llvm/test/MC/ARM/dfb.s @@ -1,5 +1,7 @@ @ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-ARM @ RUN: llvm-mc -triple thumbv8-none-eabi -mcpu=cortex-r52 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-THUMB +@ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52plus -show-encoding < %s | FileCheck %s --check-prefix=CHECK-ARM +@ RUN: llvm-mc -triple thumbv8-none-eabi -mcpu=cortex-r52plus -show-encoding < %s | FileCheck %s --check-prefix=CHECK-THUMB dfb @ CHECK-ARM: dfb @ encoding: [0x4c,0xf0,0x7f,0xf5] diff --git a/llvm/test/MC/ARM/invalid-armv8r.s b/llvm/test/MC/ARM/invalid-armv8r.s new file mode 100644 index 00000000000000..c87875a22f1444 --- /dev/null +++ b/llvm/test/MC/ARM/invalid-armv8r.s @@ -0,0 +1,6 @@ +@ RUN: not llvm-mc -triple=armv8r-linux-gnu -mcpu=cortex-r52 -show-encoding < %s 2>&1 | FileCheck %s -check-prefix=CHECK-NOTZ +@ RUN: not llvm-mc -triple=armv8r-linux-gnu -mcpu=cortex-r52plus -show-encoding < %s 2>&1 | FileCheck %s -check-prefix=CHECK-NOTZ + + smc #0xf + +@ CHECK-NOTZ: error: instruction requires: TrustZone diff --git a/llvm/test/MC/ARM/thumb-hints.s b/llvm/test/MC/ARM/thumb-hints.s index b3c4cee40bbd09..53b7b91237cc2c 100644 --- a/llvm/test/MC/ARM/thumb-hints.s +++ b/llvm/test/MC/ARM/thumb-hints.s @@ -1,3 +1,5 @@ +@ RUN: llvm-mc -triple=thumbv8r-apple-darwin -mcpu=cortex-r52 -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv8r-apple-darwin -mcpu=cortex-r52plus -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=thumbv6-apple-darwin -mcpu=cortex-m0 -show-encoding < %s | FileCheck %s @ RUN: not llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s > %t 2> %t2 diff --git a/llvm/test/MC/Disassembler/ARM/dfb-thumb.txt b/llvm/test/MC/Disassembler/ARM/dfb-thumb.txt index aa8adc83c1f4dc..ae620cb458eb4b 100644 --- a/llvm/test/MC/Disassembler/ARM/dfb-thumb.txt +++ b/llvm/test/MC/Disassembler/ARM/dfb-thumb.txt @@ -1,5 +1,7 @@ # RUN: llvm-mc -disassemble -triple thumbv8-none-eabi -mcpu=cortex-r52 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DFB # RUN: llvm-mc -disassemble -triple thumbv8-none-eabi -mcpu=cortex-r52 -mattr=-dfb -show-encoding < %s | FileCheck %s --check-prefix=CHECK-NODFB +# RUN: llvm-mc -disassemble -triple thumbv8-none-eabi -mcpu=cortex-r52plus -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DFB +# RUN: llvm-mc -disassemble -triple thumbv8-none-eabi -mcpu=cortex-r52plus -mattr=-dfb -show-encoding < %s | FileCheck %s --check-prefix=CHECK-NODFB # CHECK-DFB: dfb @ encoding: [0xbf,0xf3,0x4c,0x8f] # CHECK-NODFB: dsb #0xc @ encoding: [0xbf,0xf3,0x4c,0x8f] diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 571031d07fcc60..b2e57f2cca13ed 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -356,6 +356,11 @@ INSTANTIATE_TEST_SUITE_P( ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "8-R"), + ARMCPUTestParams("cortex-r52plus", "armv8-r", "neon-fp-armv8", + ARM::AEK_NONE | ARM::AEK_CRC | ARM::AEK_MP | + ARM::AEK_VIRT | ARM::AEK_HWDIVARM | + ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, + "8-R"), ARMCPUTestParams("sc300", "armv7-m", "none", ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB, "7-M"), ARMCPUTestParams("cortex-m3", "armv7-m", "none", @@ -548,7 +553,7 @@ INSTANTIATE_TEST_SUITE_P( "7-S")), ARMCPUTestParams::PrintToStringParamName); -static constexpr unsigned NumARMCPUArchs = 91; +static constexpr unsigned NumARMCPUArchs = 92; TEST(TargetParserTest, testARMCPUArchList) { SmallVector List; @@ -692,6 +697,8 @@ TEST(TargetParserTest, testARMExtension) { EXPECT_FALSE( testARMExtension("cortex-a75", ARM::ArchKind::INVALID, "fp16fml")); EXPECT_FALSE(testARMExtension("cortex-r52", ARM::ArchKind::INVALID, "ras")); + EXPECT_FALSE( + testARMExtension("cortex-r52plus", ARM::ArchKind::INVALID, "ras")); EXPECT_FALSE(testARMExtension("iwmmxt", ARM::ArchKind::INVALID, "crc")); EXPECT_FALSE(testARMExtension("xscale", ARM::ArchKind::INVALID, "crc")); EXPECT_FALSE(testARMExtension("swift", ARM::ArchKind::INVALID, "crc"));