From 0cde3c41c6ff0a4e386d05c09129e3aa508297e2 Mon Sep 17 00:00:00 2001 From: Fabian Ritter Date: Wed, 22 May 2024 03:48:34 -0400 Subject: [PATCH] [AMDGPU] Copy Defs and Uses from Pseudo to Real Instructions Currently, the tablegen files that generate the instruction definitions in lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc often only include implicit operands for the architecture-independent pseudo instructions, but not for the corresponding real instructions. The missing implicit operands (most prominently: the EXEC mask) do not affect code generation, since that operates on pseudo instructions, but they are problematic when working with real instructions, e.g., as a decoding result from the MC layer. This patch copies the implicit Defs and Uses from pseudo instructions to the corresponding real instructions, so that implicit operands are also defined for real instructions. Addresses issue #89830. --- llvm/lib/Target/AMDGPU/BUFInstructions.td | 6 ++++++ llvm/lib/Target/AMDGPU/DSInstructions.td | 2 ++ llvm/lib/Target/AMDGPU/FLATInstructions.td | 4 ++++ llvm/lib/Target/AMDGPU/SMInstructions.td | 2 ++ llvm/lib/Target/AMDGPU/SOPInstructions.td | 10 ++++++++++ llvm/lib/Target/AMDGPU/VOPInstructions.td | 6 ++++++ 6 files changed, 30 insertions(+) diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td index 8eaa113ac18167..f419f0b17352f4 100644 --- a/llvm/lib/Target/AMDGPU/BUFInstructions.td +++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td @@ -137,6 +137,8 @@ class MTBUF_Real : let mayStore = ps.mayStore; let IsAtomicRet = ps.IsAtomicRet; let IsAtomicNoRet = ps.IsAtomicNoRet; + let Uses = ps.Uses; + let Defs = ps.Defs; bits<12> offset; bits<5> cpol; @@ -351,6 +353,8 @@ class MUBUF_Real : let IsAtomicNoRet = ps.IsAtomicNoRet; let VALU = ps.VALU; let LGKM_CNT = ps.LGKM_CNT; + let Uses = ps.Uses; + let Defs = ps.Defs; bits<12> offset; bits<5> cpol; @@ -2392,6 +2396,8 @@ class VBUFFER_Real op, BUF_Pseudo ps, string real_name> : let LGKM_CNT = ps.LGKM_CNT; let MUBUF = ps.MUBUF; let MTBUF = ps.MTBUF; + let Uses = ps.Uses; + let Defs = ps.Defs; bits<24> offset; bits<8> vaddr; diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td index f2825c48fceca4..19bb4300531cfa 100644 --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -71,6 +71,8 @@ class DS_Real : let mayStore = ps.mayStore; let IsAtomicRet = ps.IsAtomicRet; let IsAtomicNoRet = ps.IsAtomicNoRet; + let Uses = ps.Uses; + let Defs = ps.Defs; let Constraints = ps.Constraints; let DisableEncoding = ps.DisableEncoding; diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 377d48a48e9b9f..154a7401bd6c01 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -102,6 +102,8 @@ class FLAT_Real op, FLAT_Pseudo ps, string opName = ps.Mnemonic> : let VM_CNT = ps.VM_CNT; let LGKM_CNT = ps.LGKM_CNT; let VALU = ps.VALU; + let Uses = ps.Uses; + let Defs = ps.Defs; // encoding fields bits<8> vaddr; @@ -165,6 +167,8 @@ class VFLAT_Real op, FLAT_Pseudo ps, string opName = ps.Mnemonic> : let VM_CNT = ps.VM_CNT; let LGKM_CNT = ps.LGKM_CNT; let VALU = ps.VALU; + let Uses = ps.Uses; + let Defs = ps.Defs; bits<7> saddr; bits<8> vdst; diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td index 40ba47f8877106..1f1f86583b233f 100644 --- a/llvm/lib/Target/AMDGPU/SMInstructions.td +++ b/llvm/lib/Target/AMDGPU/SMInstructions.td @@ -71,6 +71,8 @@ class SM_Real let AsmMatchConverter = ps.AsmMatchConverter; let IsAtomicRet = ps.IsAtomicRet; let IsAtomicNoRet = ps.IsAtomicNoRet; + let Uses = ps.Uses; + let Defs = ps.Defs; let TSFlags = ps.TSFlags; diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 394a5ed991bced..aee518680a6071 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -65,6 +65,8 @@ class SOP1_Real op, SOP1_Pseudo ps, string real_name = ps.Mnemonic> : let isCall = ps.isCall; let isBranch = ps.isBranch; let isBarrier = ps.isBarrier; + let Uses = ps.Uses; + let Defs = ps.Defs; // encoding bits<7> sdst; @@ -570,6 +572,8 @@ class SOP2_Real : let mayStore = ps.mayStore; let Constraints = ps.Constraints; let DisableEncoding = ps.DisableEncoding; + let Uses = ps.Uses; + let Defs = ps.Defs; // encoding bits<7> sdst; @@ -985,6 +989,8 @@ class SOPK_Real : let isTerminator = ps.isTerminator; let isReturn = ps.isReturn; let isBarrier = ps.isBarrier; + let Uses = ps.Uses; + let Defs = ps.Defs; // encoding bits<7> sdst; @@ -1245,6 +1251,8 @@ class SOPC_Real op, SOPC_Pseudo ps> : let SchedRW = ps.SchedRW; let mayLoad = ps.mayLoad; let mayStore = ps.mayStore; + let Uses = ps.Uses; + let Defs = ps.Defs; // encoding bits<8> src0; @@ -1440,6 +1448,8 @@ class SOPP_Real : let isCall = ps.isCall; let isBranch = ps.isBranch; let isBarrier = ps.isBarrier; + let Uses = ps.Uses; + let Defs = ps.Defs; bits <16> simm16; } diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td index f45ab9bf46db1f..5d1573d8dec191 100644 --- a/llvm/lib/Target/AMDGPU/VOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td @@ -657,6 +657,8 @@ class VOP_SDWA_Real : let Constraints = ps.Constraints; let DisableEncoding = ps.DisableEncoding; let TSFlags = ps.TSFlags; + let Uses = ps.Uses; + let Defs = ps.Defs; let SchedRW = ps.SchedRW; let mayLoad = ps.mayLoad; let mayStore = ps.mayStore; @@ -691,6 +693,8 @@ class Base_VOP_SDWA9_Real : let Constraints = ps.Constraints; let DisableEncoding = ps.DisableEncoding; let TSFlags = ps.TSFlags; + let Uses = ps.Uses; + let Defs = ps.Defs; let SchedRW = ps.SchedRW; let mayLoad = ps.mayLoad; let mayStore = ps.mayStore; @@ -895,6 +899,8 @@ class VOP_DPP_Real : let Constraints = ps.Constraints; let DisableEncoding = ps.DisableEncoding; let TSFlags = ps.TSFlags; + let Uses = ps.Uses; + let Defs = ps.Defs; let SchedRW = ps.SchedRW; let mayLoad = ps.mayLoad; let mayStore = ps.mayStore;