From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 23 Apr 2024 17:41:25 +0100 Subject: [PATCH 01/15] Add initial support for AMDGCN flavoured SPIRV. --- clang/lib/Basic/Targets.cpp | 6 +- clang/lib/Basic/Targets/SPIR.cpp | 288 +++++++++++++++++ clang/lib/Basic/Targets/SPIR.h | 51 +++ clang/lib/CodeGen/CGBuiltin.cpp | 7 + clang/test/CodeGen/target-data.c | 4 + .../test/CodeGenCUDA/builtins-spirv-amdgcn.cu | 294 ++++++++++++++++++ ...tins-unsafe-atomics-spirv-amdgcn-gfx90a.cu | 31 ++ clang/test/CodeGenCUDA/long-double.cu | 4 + clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu | 129 ++++++++ .../test/CodeGenCXX/spirv-amdgcn-float16.cpp | 38 +++ clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp | 27 ++ .../spirv-amdgcn-dpp-const-fold.hip | 46 +++ clang/test/CodeGenHIP/spirv-amdgcn-half.hip | 15 + .../predefined-macros-no-warnings.c | 1 + clang/test/Preprocessor/predefined-macros.c | 10 + ...in-spirv-amdgcn-atomic-inc-dec-failure.cpp | 25 ++ .../Sema/inline-asm-validate-spirv-amdgcn.cl | 111 +++++++ clang/test/SemaCUDA/allow-int128.cu | 3 + clang/test/SemaCUDA/amdgpu-f128.cu | 1 + clang/test/SemaCUDA/float16.cu | 1 + clang/test/SemaCUDA/fp16-arg-return.cu | 1 + .../test/SemaCUDA/spirv-amdgcn-atomic-ops.cu | 86 +++++ 22 files changed, 1178 insertions(+), 1 deletion(-) create mode 100644 clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu create mode 100644 clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu create mode 100644 clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu create mode 100644 clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip create mode 100644 clang/test/CodeGenHIP/spirv-amdgcn-half.hip create mode 100644 clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp create mode 100644 clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl create mode 100644 clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index e3283510c6aac7..04a13e3385d1f6 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -673,8 +673,12 @@ std::unique_ptr AllocateTarget(const llvm::Triple &Triple, } case llvm::Triple::spirv64: { if (os != llvm::Triple::UnknownOS || - Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) + Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) { + if (os == llvm::Triple::OSType::AMDHSA) + return std::make_unique(Triple, Opts); + return nullptr; + } return std::make_unique(Triple, Opts); } case llvm::Triple::wasm32: diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp index dc920177d3a910..d7d232ac9484f8 100644 --- a/clang/lib/Basic/Targets/SPIR.cpp +++ b/clang/lib/Basic/Targets/SPIR.cpp @@ -12,6 +12,8 @@ #include "SPIR.h" #include "Targets.h" +#include "clang/Basic/Builtins.h" +#include "clang/Basic/TargetBuiltins.h" using namespace clang; using namespace clang::targets; @@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions &Opts, BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder); DefineStd(Builder, "SPIRV64", Opts); } + +static constexpr Builtin::Info BuiltinInfo[] = { +#define BUILTIN(ID, TYPE, ATTRS) \ + {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, +#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ + {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, +#include "clang/Basic/BuiltinsAMDGPU.def" +}; + +namespace { +const char *AMDGPUGCCRegNames[] = { + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", + "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", + "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", + "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35", + "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44", + "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53", + "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62", + "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", + "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80", + "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89", + "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98", + "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107", + "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116", + "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125", + "v126", "v127", "v128", "v129", "v130", "v131", "v132", "v133", "v134", + "v135", "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", + "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", "v152", + "v153", "v154", "v155", "v156", "v157", "v158", "v159", "v160", "v161", + "v162", "v163", "v164", "v165", "v166", "v167", "v168", "v169", "v170", + "v171", "v172", "v173", "v174", "v175", "v176", "v177", "v178", "v179", + "v180", "v181", "v182", "v183", "v184", "v185", "v186", "v187", "v188", + "v189", "v190", "v191", "v192", "v193", "v194", "v195", "v196", "v197", + "v198", "v199", "v200", "v201", "v202", "v203", "v204", "v205", "v206", + "v207", "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", + "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", "v224", + "v225", "v226", "v227", "v228", "v229", "v230", "v231", "v232", "v233", + "v234", "v235", "v236", "v237", "v238", "v239", "v240", "v241", "v242", + "v243", "v244", "v245", "v246", "v247", "v248", "v249", "v250", "v251", + "v252", "v253", "v254", "v255", "s0", "s1", "s2", "s3", "s4", + "s5", "s6", "s7", "s8", "s9", "s10", "s11", "s12", "s13", + "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22", + "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", + "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", "s40", + "s41", "s42", "s43", "s44", "s45", "s46", "s47", "s48", "s49", + "s50", "s51", "s52", "s53", "s54", "s55", "s56", "s57", "s58", + "s59", "s60", "s61", "s62", "s63", "s64", "s65", "s66", "s67", + "s68", "s69", "s70", "s71", "s72", "s73", "s74", "s75", "s76", + "s77", "s78", "s79", "s80", "s81", "s82", "s83", "s84", "s85", + "s86", "s87", "s88", "s89", "s90", "s91", "s92", "s93", "s94", + "s95", "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", + "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", "s112", + "s113", "s114", "s115", "s116", "s117", "s118", "s119", "s120", "s121", + "s122", "s123", "s124", "s125", "s126", "s127", "exec", "vcc", "scc", + "m0", "flat_scratch", "exec_lo", "exec_hi", "vcc_lo", "vcc_hi", + "flat_scratch_lo", "flat_scratch_hi", + "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", + "a9", "a10", "a11", "a12", "a13", "a14", "a15", "a16", "a17", + "a18", "a19", "a20", "a21", "a22", "a23", "a24", "a25", "a26", + "a27", "a28", "a29", "a30", "a31", "a32", "a33", "a34", "a35", + "a36", "a37", "a38", "a39", "a40", "a41", "a42", "a43", "a44", + "a45", "a46", "a47", "a48", "a49", "a50", "a51", "a52", "a53", + "a54", "a55", "a56", "a57", "a58", "a59", "a60", "a61", "a62", + "a63", "a64", "a65", "a66", "a67", "a68", "a69", "a70", "a71", + "a72", "a73", "a74", "a75", "a76", "a77", "a78", "a79", "a80", + "a81", "a82", "a83", "a84", "a85", "a86", "a87", "a88", "a89", + "a90", "a91", "a92", "a93", "a94", "a95", "a96", "a97", "a98", + "a99", "a100", "a101", "a102", "a103", "a104", "a105", "a106", "a107", + "a108", "a109", "a110", "a111", "a112", "a113", "a114", "a115", "a116", + "a117", "a118", "a119", "a120", "a121", "a122", "a123", "a124", "a125", + "a126", "a127", "a128", "a129", "a130", "a131", "a132", "a133", "a134", + "a135", "a136", "a137", "a138", "a139", "a140", "a141", "a142", "a143", + "a144", "a145", "a146", "a147", "a148", "a149", "a150", "a151", "a152", + "a153", "a154", "a155", "a156", "a157", "a158", "a159", "a160", "a161", + "a162", "a163", "a164", "a165", "a166", "a167", "a168", "a169", "a170", + "a171", "a172", "a173", "a174", "a175", "a176", "a177", "a178", "a179", + "a180", "a181", "a182", "a183", "a184", "a185", "a186", "a187", "a188", + "a189", "a190", "a191", "a192", "a193", "a194", "a195", "a196", "a197", + "a198", "a199", "a200", "a201", "a202", "a203", "a204", "a205", "a206", + "a207", "a208", "a209", "a210", "a211", "a212", "a213", "a214", "a215", + "a216", "a217", "a218", "a219", "a220", "a221", "a222", "a223", "a224", + "a225", "a226", "a227", "a228", "a229", "a230", "a231", "a232", "a233", + "a234", "a235", "a236", "a237", "a238", "a239", "a240", "a241", "a242", + "a243", "a244", "a245", "a246", "a247", "a248", "a249", "a250", "a251", + "a252", "a253", "a254", "a255" +}; + +} // anonymous namespace + +ArrayRef SPIRV64AMDGCNTargetInfo::getGCCRegNames() const { + return llvm::ArrayRef(AMDGPUGCCRegNames); +} + +bool SPIRV64AMDGCNTargetInfo::initFeatureMap( + llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef, + const std::vector &FeatureVec) const { + // This represents the union of all AMDGCN features. + Features["atomic-ds-pk-add-16-insts"] = true; + Features["atomic-flat-pk-add-16-insts"] = true; + Features["atomic-buffer-global-pk-add-f16-insts"] = true; + Features["atomic-global-pk-add-bf16-inst"] = true; + Features["atomic-fadd-rtn-insts"] = true; + Features["ci-insts"] = true; + Features["dot1-insts"] = true; + Features["dot2-insts"] = true; + Features["dot3-insts"] = true; + Features["dot4-insts"] = true; + Features["dot5-insts"] = true; + Features["dot7-insts"] = true; + Features["dot8-insts"] = true; + Features["dot9-insts"] = true; + Features["dot10-insts"] = true; + Features["dot11-insts"] = true; + Features["dl-insts"] = true; + Features["16-bit-insts"] = true; + Features["dpp"] = true; + Features["gfx8-insts"] = true; + Features["gfx9-insts"] = true; + Features["gfx90a-insts"] = true; + Features["gfx940-insts"] = true; + Features["gfx10-insts"] = true; + Features["gfx10-3-insts"] = true; + Features["gfx11-insts"] = true; + Features["gfx12-insts"] = true; + Features["image-insts"] = true; + Features["fp8-conversion-insts"] = true; + Features["s-memrealtime"] = true; + Features["s-memtime-inst"] = true; + Features["gws"] = true; + Features["fp8-insts"] = true; + Features["fp8-conversion-insts"] = true; + Features["atomic-ds-pk-add-16-insts"] = true; + Features["mai-insts"] = true; + + return TargetInfo::initFeatureMap(Features, Diags, {}, FeatureVec); +} + +bool SPIRV64AMDGCNTargetInfo::validateAsmConstraint( + const char *&Name, TargetInfo::ConstraintInfo &Info) const { + // This is a 1:1 copy of AMDGPUTargetInfo::validateAsmConstraint() + static const ::llvm::StringSet<> SpecialRegs({ + "exec", "vcc", "flat_scratch", "m0", "scc", "tba", "tma", + "flat_scratch_lo", "flat_scratch_hi", "vcc_lo", "vcc_hi", "exec_lo", + "exec_hi", "tma_lo", "tma_hi", "tba_lo", "tba_hi", + }); + + switch (*Name) { + case 'I': + Info.setRequiresImmediate(-16, 64); + return true; + case 'J': + Info.setRequiresImmediate(-32768, 32767); + return true; + case 'A': + case 'B': + case 'C': + Info.setRequiresImmediate(); + return true; + default: + break; + } + + StringRef S(Name); + + if (S == "DA" || S == "DB") { + Name++; + Info.setRequiresImmediate(); + return true; + } + + bool HasLeftParen = S.consume_front("{"); + if (S.empty()) + return false; + if (S.front() != 'v' && S.front() != 's' && S.front() != 'a') { + if (!HasLeftParen) + return false; + auto E = S.find('}'); + if (!SpecialRegs.count(S.substr(0, E))) + return false; + S = S.drop_front(E + 1); + if (!S.empty()) + return false; + // Found {S} where S is a special register. + Info.setAllowsRegister(); + Name = S.data() - 1; + return true; + } + S = S.drop_front(); + if (!HasLeftParen) { + if (!S.empty()) + return false; + // Found s, v or a. + Info.setAllowsRegister(); + Name = S.data() - 1; + return true; + } + bool HasLeftBracket = S.consume_front("["); + unsigned long long N; + if (S.empty() || consumeUnsignedInteger(S, 10, N)) + return false; + if (S.consume_front(":")) { + if (!HasLeftBracket) + return false; + unsigned long long M; + if (consumeUnsignedInteger(S, 10, M) || N >= M) + return false; + } + if (HasLeftBracket) { + if (!S.consume_front("]")) + return false; + } + if (!S.consume_front("}")) + return false; + if (!S.empty()) + return false; + // Found {vn}, {sn}, {an}, {v[n]}, {s[n]}, {a[n]}, {v[n:m]}, {s[n:m]} + // or {a[n:m]}. + Info.setAllowsRegister(); + Name = S.data() - 1; + return true; +} + +std::string +SPIRV64AMDGCNTargetInfo::convertConstraint(const char *&Constraint) const { + // This is a 1:1 copy of AMDGPUTargetInfo::convertConstraint() + StringRef S(Constraint); + if (S == "DA" || S == "DB") { + return std::string("^") + std::string(Constraint++, 2); + } + + const char *Begin = Constraint; + TargetInfo::ConstraintInfo Info("", ""); + if (validateAsmConstraint(Constraint, Info)) + return std::string(Begin).substr(0, Constraint - Begin + 1); + + Constraint = Begin; + return std::string(1, *Constraint); +} + +ArrayRef SPIRV64AMDGCNTargetInfo::getTargetBuiltins() const { + return llvm::ArrayRef(BuiltinInfo, + clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); +} + +void SPIRV64AMDGCNTargetInfo::getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const { + BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder); + DefineStd(Builder, "SPIRV64", Opts); + + Builder.defineMacro("__AMD__"); + Builder.defineMacro("__AMDGPU__"); + Builder.defineMacro("__AMDGCN__"); +} + +void SPIRV64AMDGCNTargetInfo::setAuxTarget(const TargetInfo *Aux) { + // This is a 1:1 copy of AMDGPUTargetInfo::setAuxTarget() + assert(HalfFormat == Aux->HalfFormat); + assert(FloatFormat == Aux->FloatFormat); + assert(DoubleFormat == Aux->DoubleFormat); + + // On x86_64 long double is 80-bit extended precision format, which is + // not supported by AMDGPU. 128-bit floating point format is also not + // supported by AMDGPU. Therefore keep its own format for these two types. + auto SaveLongDoubleFormat = LongDoubleFormat; + auto SaveFloat128Format = Float128Format; + auto SaveLongDoubleWidth = LongDoubleWidth; + auto SaveLongDoubleAlign = LongDoubleAlign; + copyAuxTarget(Aux); + LongDoubleFormat = SaveLongDoubleFormat; + Float128Format = SaveFloat128Format; + LongDoubleWidth = SaveLongDoubleWidth; + LongDoubleAlign = SaveLongDoubleAlign; + // For certain builtin types support on the host target, claim they are + // supported to pass the compilation of the host code during the device-side + // compilation. + // FIXME: As the side effect, we also accept `__float128` uses in the device + // code. To reject these builtin types supported in the host target but not in + // the device target, one approach would support `device_builtin` attribute + // so that we could tell the device builtin types from the host ones. This + // also solves the different representations of the same builtin type, such + // as `size_t` in the MSVC environment. + if (Aux->hasFloat128Type()) { + HasFloat128 = true; + Float128Format = DoubleFormat; + } +} diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h index 44265445ff004b..6b605979c9ab1d 100644 --- a/clang/lib/Basic/Targets/SPIR.h +++ b/clang/lib/Basic/Targets/SPIR.h @@ -364,6 +364,57 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64TargetInfo : public BaseSPIRVTargetInfo { MacroBuilder &Builder) const override; }; +class LLVM_LIBRARY_VISIBILITY SPIRV64AMDGCNTargetInfo + : public BaseSPIRVTargetInfo { +public: + SPIRV64AMDGCNTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) + : BaseSPIRVTargetInfo(Triple, Opts) { + assert(Triple.getArch() == llvm::Triple::spirv64 && + "Invalid architecture for 64-bit AMDGCN SPIR-V."); + assert(Triple.getVendor() == llvm::Triple::VendorType::AMD && + "64-bit AMDGCN SPIR-V target must use AMD vendor"); + assert(getTriple().getOS() == llvm::Triple::OSType::AMDHSA && + "64-bit AMDGCN SPIR-V target must use AMDHSA OS"); + assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && + "64-bit SPIR-V target must use unknown environment type"); + PointerWidth = PointerAlign = 64; + SizeType = TargetInfo::UnsignedLong; + PtrDiffType = IntPtrType = TargetInfo::SignedLong; + + resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" + "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1-P4-A0"); + + BFloat16Width = BFloat16Align = 16; + BFloat16Format = &llvm::APFloat::BFloat(); + + HasLegalHalfType = true; + HasFloat16 = true; + HalfArgsAndReturns = true; + } + + bool hasBFloat16Type() const override { return true; } + + ArrayRef getGCCRegNames() const override; + + bool initFeatureMap(llvm::StringMap &Features, DiagnosticsEngine &Diags, + StringRef, + const std::vector &) const override; + + bool validateAsmConstraint(const char *&Name, + TargetInfo::ConstraintInfo &Info) const override; + + std::string convertConstraint(const char *&Constraint) const override; + + ArrayRef getTargetBuiltins() const override; + + void getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const override; + + void setAuxTarget(const TargetInfo *Aux) override; + + bool hasInt128Type() const override { return TargetInfo::hasInt128Type(); } +}; + } // namespace targets } // namespace clang #endif // LLVM_CLANG_LIB_BASIC_TARGETS_SPIR_H diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 7e5f2edfc732cc..db64b0a436a095 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -6083,6 +6083,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, StringRef Prefix = llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch()); if (!Prefix.empty()) { + if (Prefix == "spv" && + getTarget().getTriple().getOS() == llvm::Triple::OSType::AMDHSA) + Prefix = "amdgcn"; IntrinsicID = Intrinsic::getIntrinsicForClangBuiltin(Prefix.data(), Name); // NOTE we don't need to perform a compatibility flag check here since the // intrinsics are declared in Builtins*.def via LANGBUILTIN which filter the @@ -6254,6 +6257,10 @@ static Value *EmitTargetArchBuiltinExpr(CodeGenFunction *CGF, case llvm::Triple::riscv32: case llvm::Triple::riscv64: return CGF->EmitRISCVBuiltinExpr(BuiltinID, E, ReturnValue); + case llvm::Triple::spirv64: + if (CGF->getTarget().getTriple().getOS() != llvm::Triple::OSType::AMDHSA) + return nullptr; + return CGF->EmitAMDGPUBuiltinExpr(BuiltinID, E); default: return nullptr; } diff --git a/clang/test/CodeGen/target-data.c b/clang/test/CodeGen/target-data.c index c184f314f68f80..1d40b8fe46063d 100644 --- a/clang/test/CodeGen/target-data.c +++ b/clang/test/CodeGen/target-data.c @@ -268,3 +268,7 @@ // RUN: %clang_cc1 -triple ve -o - -emit-llvm %s | \ // RUN: FileCheck %s -check-prefix=VE // VE: target datalayout = "e-m:e-i64:64-n32:64-S128-v64:64:64-v128:64:64-v256:64:64-v512:64:64-v1024:64:64-v2048:64:64-v4096:64:64-v8192:64:64-v16384:64:64" + +// RUN: %clang_cc1 -triple spirv64-amd -o - -emit-llvm %s | \ +// RUN: FileCheck %s -check-prefix=SPIR64 +// AMDGPUSPIRV64: target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1-P4-A0" diff --git a/clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu b/clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu new file mode 100644 index 00000000000000..8dbb8c538ddc16 --- /dev/null +++ b/clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu @@ -0,0 +1,294 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip \ +// RUN: -aux-triple x86_64-unknown-linux-gnu -fcuda-is-device -emit-llvm %s \ +// RUN: -o - | FileCheck %s + +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip \ +// RUN: -aux-triple x86_64-pc-windows-msvc -fcuda-is-device -emit-llvm %s \ +// RUN: -o - | FileCheck %s + +#include "Inputs/cuda.h" + +// CHECK-LABEL: @_Z16use_dispatch_ptrPi( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[OUT:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[DISPATCH_PTR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[OUT_ASCAST:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(4) +// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr [[OUT_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[DISPATCH_PTR_ASCAST:%.*]] = addrspacecast ptr [[DISPATCH_PTR]] to ptr addrspace(4) +// CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(1) [[OUT_COERCE:%.*]] to ptr addrspace(4) +// CHECK-NEXT: store ptr addrspace(4) [[TMP0]], ptr addrspace(4) [[OUT_ASCAST]], align 8 +// CHECK-NEXT: [[OUT1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ASCAST]], align 8 +// CHECK-NEXT: store ptr addrspace(4) [[OUT1]], ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call align 4 dereferenceable(64) addrspace(4) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() +// CHECK-NEXT: store ptr addrspace(4) [[TMP1]], ptr addrspace(4) [[DISPATCH_PTR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[DISPATCH_PTR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP3]], ptr addrspace(4) [[TMP4]], align 4 +// CHECK-NEXT: ret void +// +__global__ void use_dispatch_ptr(int* out) { + const int* dispatch_ptr = (const int*)__builtin_amdgcn_dispatch_ptr(); + *out = *dispatch_ptr; +} + +// CHECK-LABEL: @_Z13use_queue_ptrPi( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[OUT:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[QUEUE_PTR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[OUT_ASCAST:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(4) +// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr [[OUT_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[QUEUE_PTR_ASCAST:%.*]] = addrspacecast ptr [[QUEUE_PTR]] to ptr addrspace(4) +// CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(1) [[OUT_COERCE:%.*]] to ptr addrspace(4) +// CHECK-NEXT: store ptr addrspace(4) [[TMP0]], ptr addrspace(4) [[OUT_ASCAST]], align 8 +// CHECK-NEXT: [[OUT1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ASCAST]], align 8 +// CHECK-NEXT: store ptr addrspace(4) [[OUT1]], ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call addrspace(4) ptr addrspace(4) @llvm.amdgcn.queue.ptr() +// CHECK-NEXT: store ptr addrspace(4) [[TMP1]], ptr addrspace(4) [[QUEUE_PTR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[QUEUE_PTR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP3]], ptr addrspace(4) [[TMP4]], align 4 +// CHECK-NEXT: ret void +// +__global__ void use_queue_ptr(int* out) { + const int* queue_ptr = (const int*)__builtin_amdgcn_queue_ptr(); + *out = *queue_ptr; +} + +// CHECK-LABEL: @_Z19use_implicitarg_ptrPi( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[OUT:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[IMPLICITARG_PTR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[OUT_ASCAST:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(4) +// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr [[OUT_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[IMPLICITARG_PTR_ASCAST:%.*]] = addrspacecast ptr [[IMPLICITARG_PTR]] to ptr addrspace(4) +// CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(1) [[OUT_COERCE:%.*]] to ptr addrspace(4) +// CHECK-NEXT: store ptr addrspace(4) [[TMP0]], ptr addrspace(4) [[OUT_ASCAST]], align 8 +// CHECK-NEXT: [[OUT1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ASCAST]], align 8 +// CHECK-NEXT: store ptr addrspace(4) [[OUT1]], ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call addrspace(4) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() +// CHECK-NEXT: store ptr addrspace(4) [[TMP1]], ptr addrspace(4) [[IMPLICITARG_PTR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[IMPLICITARG_PTR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(4) [[TMP2]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[TMP3]], ptr addrspace(4) [[TMP4]], align 4 +// CHECK-NEXT: ret void +// +__global__ void use_implicitarg_ptr(int* out) { + const int* implicitarg_ptr = (const int*)__builtin_amdgcn_implicitarg_ptr(); + *out = *implicitarg_ptr; +} + +__global__ + // + void +// CHECK-LABEL: @_Z12test_ds_fmaxf( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[SRC_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: [[X:%.*]] = alloca float, align 4 +// CHECK-NEXT: [[SRC_ADDR_ASCAST:%.*]] = addrspacecast ptr [[SRC_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[X_ASCAST:%.*]] = addrspacecast ptr [[X]] to ptr addrspace(4) +// CHECK-NEXT: store float [[SRC:%.*]], ptr addrspace(4) [[SRC_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr addrspace(4) [[SRC_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = call contract addrspace(4) float @llvm.amdgcn.ds.fmax.f32(ptr addrspace(3) @_ZZ12test_ds_fmaxfE6shared, float [[TMP0]], i32 0, i32 0, i1 false) +// CHECK-NEXT: store volatile float [[TMP1]], ptr addrspace(4) [[X_ASCAST]], align 4 +// CHECK-NEXT: ret void +// + test_ds_fmax(float src) { + __shared__ float shared; + volatile float x = __builtin_amdgcn_ds_fmaxf(&shared, src, 0, 0, false); +} + +// CHECK-LABEL: @_Z12test_ds_faddf( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[SRC_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: [[X:%.*]] = alloca float, align 4 +// CHECK-NEXT: [[SRC_ADDR_ASCAST:%.*]] = addrspacecast ptr [[SRC_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[X_ASCAST:%.*]] = addrspacecast ptr [[X]] to ptr addrspace(4) +// CHECK-NEXT: store float [[SRC:%.*]], ptr addrspace(4) [[SRC_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr addrspace(4) [[SRC_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = call contract addrspace(4) float @llvm.amdgcn.ds.fadd.f32(ptr addrspace(3) @_ZZ12test_ds_faddfE6shared, float [[TMP0]], i32 0, i32 0, i1 false) +// CHECK-NEXT: store volatile float [[TMP1]], ptr addrspace(4) [[X_ASCAST]], align 4 +// CHECK-NEXT: ret void +// +__global__ void test_ds_fadd(float src) { + __shared__ float shared; + volatile float x = __builtin_amdgcn_ds_faddf(&shared, src, 0, 0, false); +} + +// CHECK-LABEL: @_Z12test_ds_fminfPf( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[SHARED:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[SRC_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: [[SHARED_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[X:%.*]] = alloca float, align 4 +// CHECK-NEXT: [[SHARED_ASCAST:%.*]] = addrspacecast ptr [[SHARED]] to ptr addrspace(4) +// CHECK-NEXT: [[SRC_ADDR_ASCAST:%.*]] = addrspacecast ptr [[SRC_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[SHARED_ADDR_ASCAST:%.*]] = addrspacecast ptr [[SHARED_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[X_ASCAST:%.*]] = addrspacecast ptr [[X]] to ptr addrspace(4) +// CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(1) [[SHARED_COERCE:%.*]] to ptr addrspace(4) +// CHECK-NEXT: store ptr addrspace(4) [[TMP0]], ptr addrspace(4) [[SHARED_ASCAST]], align 8 +// CHECK-NEXT: [[SHARED1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[SHARED_ASCAST]], align 8 +// CHECK-NEXT: store float [[SRC:%.*]], ptr addrspace(4) [[SRC_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store ptr addrspace(4) [[SHARED1]], ptr addrspace(4) [[SHARED_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[SHARED_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(4) [[TMP1]] to ptr addrspace(3) +// CHECK-NEXT: [[TMP3:%.*]] = load float, ptr addrspace(4) [[SRC_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = call contract addrspace(4) float @llvm.amdgcn.ds.fmin.f32(ptr addrspace(3) [[TMP2]], float [[TMP3]], i32 0, i32 0, i1 false) +// CHECK-NEXT: store volatile float [[TMP4]], ptr addrspace(4) [[X_ASCAST]], align 4 +// CHECK-NEXT: ret void +// +__global__ void test_ds_fmin(float src, float *shared) { + volatile float x = __builtin_amdgcn_ds_fminf(shared, src, 0, 0, false); +} + +#if 0 // FIXME: returning a pointer to AS4 explicitly is wrong for AMDGPU SPIRV +// +__device__ void test_ret_builtin_nondef_addrspace() { + void *x = __builtin_amdgcn_dispatch_ptr(); +} +#endif + +// CHECK-LABEL: @_Z6endpgmv( +// CHECK-NEXT: entry: +// CHECK-NEXT: call addrspace(4) void @llvm.amdgcn.endpgm() +// CHECK-NEXT: ret void +// +__global__ void endpgm() { + __builtin_amdgcn_endpgm(); +} + +// Check the 64 bit argument is correctly passed to the intrinsic without truncation or assertion. + +// CHECK-LABEL: @_Z14test_uicmp_i64Pyyy( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[OUT:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[OUT_ASCAST:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(4) +// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr [[OUT_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr [[A_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr [[B_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(1) [[OUT_COERCE:%.*]] to ptr addrspace(4) +// CHECK-NEXT: store ptr addrspace(4) [[TMP0]], ptr addrspace(4) [[OUT_ASCAST]], align 8 +// CHECK-NEXT: [[OUT1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ASCAST]], align 8 +// CHECK-NEXT: store ptr addrspace(4) [[OUT1]], ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[A:%.*]], ptr addrspace(4) [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[B:%.*]], ptr addrspace(4) [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr addrspace(4) [[A_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr addrspace(4) [[B_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = call addrspace(4) i64 @llvm.amdgcn.icmp.i64.i64(i64 [[TMP1]], i64 [[TMP2]], i32 35) +// CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TMP3]], ptr addrspace(4) [[TMP4]], align 8 +// CHECK-NEXT: ret void +// +__global__ void test_uicmp_i64(unsigned long long *out, unsigned long long a, unsigned long long b) +{ + *out = __builtin_amdgcn_uicmpl(a, b, 30+5); +} + +// Check the 64 bit return value is correctly returned without truncation or assertion. + +// CHECK-LABEL: @_Z14test_s_memtimePy( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[OUT:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[OUT_ASCAST:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(4) +// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr [[OUT_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(1) [[OUT_COERCE:%.*]] to ptr addrspace(4) +// CHECK-NEXT: store ptr addrspace(4) [[TMP0]], ptr addrspace(4) [[OUT_ASCAST]], align 8 +// CHECK-NEXT: [[OUT1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ASCAST]], align 8 +// CHECK-NEXT: store ptr addrspace(4) [[OUT1]], ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call addrspace(4) i64 @llvm.amdgcn.s.memtime() +// CHECK-NEXT: [[TMP2:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i64 [[TMP1]], ptr addrspace(4) [[TMP2]], align 8 +// CHECK-NEXT: ret void +// +__global__ void test_s_memtime(unsigned long long* out) +{ + *out = __builtin_amdgcn_s_memtime(); +} + +// Check a generic pointer can be passed as a shared pointer and a generic pointer. +__device__ void func(float *x); + +// CHECK-LABEL: @_Z17test_ds_fmin_funcfPf( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[SHARED:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[SRC_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: [[SHARED_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[X:%.*]] = alloca float, align 4 +// CHECK-NEXT: [[SHARED_ASCAST:%.*]] = addrspacecast ptr [[SHARED]] to ptr addrspace(4) +// CHECK-NEXT: [[SRC_ADDR_ASCAST:%.*]] = addrspacecast ptr [[SRC_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[SHARED_ADDR_ASCAST:%.*]] = addrspacecast ptr [[SHARED_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[X_ASCAST:%.*]] = addrspacecast ptr [[X]] to ptr addrspace(4) +// CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(1) [[SHARED_COERCE:%.*]] to ptr addrspace(4) +// CHECK-NEXT: store ptr addrspace(4) [[TMP0]], ptr addrspace(4) [[SHARED_ASCAST]], align 8 +// CHECK-NEXT: [[SHARED1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[SHARED_ASCAST]], align 8 +// CHECK-NEXT: store float [[SRC:%.*]], ptr addrspace(4) [[SRC_ADDR_ASCAST]], align 4 +// CHECK-NEXT: store ptr addrspace(4) [[SHARED1]], ptr addrspace(4) [[SHARED_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[SHARED_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(4) [[TMP1]] to ptr addrspace(3) +// CHECK-NEXT: [[TMP3:%.*]] = load float, ptr addrspace(4) [[SRC_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = call contract addrspace(4) float @llvm.amdgcn.ds.fmin.f32(ptr addrspace(3) [[TMP2]], float [[TMP3]], i32 0, i32 0, i1 false) +// CHECK-NEXT: store volatile float [[TMP4]], ptr addrspace(4) [[X_ASCAST]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[SHARED_ADDR_ASCAST]], align 8 +// CHECK-NEXT: call spir_func addrspace(4) void @_Z4funcPf(ptr addrspace(4) noundef [[TMP5]]) #[[ATTR7:[0-9]+]] +// CHECK-NEXT: ret void +// +__global__ void test_ds_fmin_func(float src, float *__restrict shared) { + volatile float x = __builtin_amdgcn_ds_fminf(shared, src, 0, 0, false); + func(shared); +} + +// CHECK-LABEL: @_Z14test_is_sharedPf( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[RET:%.*]] = alloca i8, align 1 +// CHECK-NEXT: [[X_ASCAST:%.*]] = addrspacecast ptr [[X]] to ptr addrspace(4) +// CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr [[X_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[RET_ASCAST:%.*]] = addrspacecast ptr [[RET]] to ptr addrspace(4) +// CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(1) [[X_COERCE:%.*]] to ptr addrspace(4) +// CHECK-NEXT: store ptr addrspace(4) [[TMP0]], ptr addrspace(4) [[X_ASCAST]], align 8 +// CHECK-NEXT: [[X1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[X_ASCAST]], align 8 +// CHECK-NEXT: store ptr addrspace(4) [[X1]], ptr addrspace(4) [[X_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[X_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(4) [[TMP1]] to ptr +// CHECK-NEXT: [[TMP3:%.*]] = call addrspace(4) i1 @llvm.amdgcn.is.shared(ptr [[TMP2]]) +// CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TMP3]] to i8 +// CHECK-NEXT: store i8 [[FROMBOOL]], ptr addrspace(4) [[RET_ASCAST]], align 1 +// CHECK-NEXT: ret void +// +__global__ void test_is_shared(float *x){ + bool ret = __builtin_amdgcn_is_shared(x); +} + +// CHECK-LABEL: @_Z15test_is_privatePi( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[X_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[RET:%.*]] = alloca i8, align 1 +// CHECK-NEXT: [[X_ASCAST:%.*]] = addrspacecast ptr [[X]] to ptr addrspace(4) +// CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr [[X_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[RET_ASCAST:%.*]] = addrspacecast ptr [[RET]] to ptr addrspace(4) +// CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(1) [[X_COERCE:%.*]] to ptr addrspace(4) +// CHECK-NEXT: store ptr addrspace(4) [[TMP0]], ptr addrspace(4) [[X_ASCAST]], align 8 +// CHECK-NEXT: [[X1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[X_ASCAST]], align 8 +// CHECK-NEXT: store ptr addrspace(4) [[X1]], ptr addrspace(4) [[X_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[X_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(4) [[TMP1]] to ptr +// CHECK-NEXT: [[TMP3:%.*]] = call addrspace(4) i1 @llvm.amdgcn.is.private(ptr [[TMP2]]) +// CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TMP3]] to i8 +// CHECK-NEXT: store i8 [[FROMBOOL]], ptr addrspace(4) [[RET_ASCAST]], align 1 +// CHECK-NEXT: ret void +// +__global__ void test_is_private(int *x){ + bool ret = __builtin_amdgcn_is_private(x); +} diff --git a/clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu b/clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu new file mode 100644 index 00000000000000..1ea1d5f454762d --- /dev/null +++ b/clang/test/CodeGenCUDA/builtins-unsafe-atomics-spirv-amdgcn-gfx90a.cu @@ -0,0 +1,31 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip \ +// RUN: -aux-triple x86_64-unknown-linux-gnu -fcuda-is-device -emit-llvm %s \ +// RUN: -o - | FileCheck %s + +#define __device__ __attribute__((device)) +typedef __attribute__((address_space(3))) float *LP; + +// CHECK-LABEL: define spir_func void @_Z22test_ds_atomic_add_f32Pff( +// CHECK-SAME: ptr addrspace(4) noundef [[ADDR:%.*]], float noundef [[VAL:%.*]]) addrspace(4) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: [[RTN:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[ADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr [[ADDR_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[VAL_ADDR_ASCAST:%.*]] = addrspacecast ptr [[VAL_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[RTN_ASCAST:%.*]] = addrspacecast ptr [[RTN]] to ptr addrspace(4) +// CHECK-NEXT: store ptr addrspace(4) [[ADDR]], ptr addrspace(4) [[ADDR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store float [[VAL]], ptr addrspace(4) [[VAL_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[ADDR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(4) [[TMP0]] to ptr addrspace(3) +// CHECK-NEXT: [[TMP2:%.*]] = load float, ptr addrspace(4) [[VAL_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = call contract addrspace(4) float @llvm.amdgcn.ds.fadd.f32(ptr addrspace(3) [[TMP1]], float [[TMP2]], i32 0, i32 0, i1 false) +// CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[RTN_ASCAST]], align 8 +// CHECK-NEXT: store float [[TMP3]], ptr addrspace(4) [[TMP4]], align 4 +// CHECK-NEXT: ret void +// +__device__ void test_ds_atomic_add_f32(float *addr, float val) { + float *rtn; + *rtn = __builtin_amdgcn_ds_faddf((LP)addr, val, 0, 0, 0); +} diff --git a/clang/test/CodeGenCUDA/long-double.cu b/clang/test/CodeGenCUDA/long-double.cu index d52de972ea3da4..898afcac124b5f 100644 --- a/clang/test/CodeGenCUDA/long-double.cu +++ b/clang/test/CodeGenCUDA/long-double.cu @@ -2,6 +2,10 @@ // RUN: -aux-triple x86_64-unknown-gnu-linux -fcuda-is-device \ // RUN: -emit-llvm -o - -x hip %s 2>&1 | FileCheck %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa \ +// RUN: -aux-triple x86_64-unknown-gnu-linux -fcuda-is-device \ +// RUN: -emit-llvm -o - -x hip %s 2>&1 | FileCheck %s + // RUN: %clang_cc1 -triple nvptx \ // RUN: -aux-triple x86_64-unknown-gnu-linux -fcuda-is-device \ // RUN: -emit-llvm -o - %s 2>&1 | FileCheck %s diff --git a/clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu b/clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu new file mode 100644 index 00000000000000..2a0f84d1daa758 --- /dev/null +++ b/clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu @@ -0,0 +1,129 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: amdgpu-registered-target +// REQUIRES: x86-registered-target + +// RUN: %clang_cc1 "-aux-triple" "x86_64-unknown-linux-gnu" "-triple" "spirv64-amd-amdhsa" \ +// RUN: -fcuda-is-device "-aux-target-cpu" "x86-64" -emit-llvm -o - %s | FileCheck %s + +#include "Inputs/cuda.h" + +// CHECK-LABEL: @_Z8test_argPDF16bDF16b( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[IN_ADDR:%.*]] = alloca bfloat, align 2 +// CHECK-NEXT: [[BF16:%.*]] = alloca bfloat, align 2 +// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr [[OUT_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[IN_ADDR_ASCAST:%.*]] = addrspacecast ptr [[IN_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[BF16_ASCAST:%.*]] = addrspacecast ptr [[BF16]] to ptr addrspace(4) +// CHECK-NEXT: store ptr addrspace(4) [[OUT:%.*]], ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store bfloat [[IN:%.*]], ptr addrspace(4) [[IN_ADDR_ASCAST]], align 2 +// CHECK-NEXT: [[TMP0:%.*]] = load bfloat, ptr addrspace(4) [[IN_ADDR_ASCAST]], align 2 +// CHECK-NEXT: store bfloat [[TMP0]], ptr addrspace(4) [[BF16_ASCAST]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = load bfloat, ptr addrspace(4) [[BF16_ASCAST]], align 2 +// CHECK-NEXT: [[TMP2:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store bfloat [[TMP1]], ptr addrspace(4) [[TMP2]], align 2 +// CHECK-NEXT: ret void +// +__device__ void test_arg(__bf16 *out, __bf16 in) { + __bf16 bf16 = in; + *out = bf16; +} + +// CHECK-LABEL: @_Z9test_loadPDF16bS_( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[IN_ADDR:%.*]] = alloca ptr addrspace(4), align 8 +// CHECK-NEXT: [[BF16:%.*]] = alloca bfloat, align 2 +// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr [[OUT_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[IN_ADDR_ASCAST:%.*]] = addrspacecast ptr [[IN_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: [[BF16_ASCAST:%.*]] = addrspacecast ptr [[BF16]] to ptr addrspace(4) +// CHECK-NEXT: store ptr addrspace(4) [[OUT:%.*]], ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr addrspace(4) [[IN:%.*]], ptr addrspace(4) [[IN_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[IN_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load bfloat, ptr addrspace(4) [[TMP0]], align 2 +// CHECK-NEXT: store bfloat [[TMP1]], ptr addrspace(4) [[BF16_ASCAST]], align 2 +// CHECK-NEXT: [[TMP2:%.*]] = load bfloat, ptr addrspace(4) [[BF16_ASCAST]], align 2 +// CHECK-NEXT: [[TMP3:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store bfloat [[TMP2]], ptr addrspace(4) [[TMP3]], align 2 +// CHECK-NEXT: ret void +// +__device__ void test_load(__bf16 *out, __bf16 *in) { + __bf16 bf16 = *in; + *out = bf16; +} + +// CHECK-LABEL: @_Z8test_retDF16b( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[RETVAL:%.*]] = alloca bfloat, align 2 +// CHECK-NEXT: [[IN_ADDR:%.*]] = alloca bfloat, align 2 +// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4) +// CHECK-NEXT: [[IN_ADDR_ASCAST:%.*]] = addrspacecast ptr [[IN_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: store bfloat [[IN:%.*]], ptr addrspace(4) [[IN_ADDR_ASCAST]], align 2 +// CHECK-NEXT: [[TMP0:%.*]] = load bfloat, ptr addrspace(4) [[IN_ADDR_ASCAST]], align 2 +// CHECK-NEXT: ret bfloat [[TMP0]] +// +__device__ __bf16 test_ret( __bf16 in) { + return in; +} + +// CHECK-LABEL: @_Z9test_callDF16b( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[RETVAL:%.*]] = alloca bfloat, align 2 +// CHECK-NEXT: [[IN_ADDR:%.*]] = alloca bfloat, align 2 +// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4) +// CHECK-NEXT: [[IN_ADDR_ASCAST:%.*]] = addrspacecast ptr [[IN_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: store bfloat [[IN:%.*]], ptr addrspace(4) [[IN_ADDR_ASCAST]], align 2 +// CHECK-NEXT: [[TMP0:%.*]] = load bfloat, ptr addrspace(4) [[IN_ADDR_ASCAST]], align 2 +// CHECK-NEXT: [[CALL:%.*]] = call contract spir_func noundef addrspace(4) bfloat @_Z8test_retDF16b(bfloat noundef [[TMP0]]) #[[ATTR1:[0-9]+]] +// CHECK-NEXT: ret bfloat [[CALL]] +// +__device__ __bf16 test_call( __bf16 in) { + return test_ret(in); +} + + +// CHECK-LABEL: @_Z15test_vec_assignv( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[VEC2_A:%.*]] = alloca <2 x bfloat>, align 4 +// CHECK-NEXT: [[VEC2_B:%.*]] = alloca <2 x bfloat>, align 4 +// CHECK-NEXT: [[VEC4_A:%.*]] = alloca <4 x bfloat>, align 8 +// CHECK-NEXT: [[VEC4_B:%.*]] = alloca <4 x bfloat>, align 8 +// CHECK-NEXT: [[VEC8_A:%.*]] = alloca <8 x bfloat>, align 16 +// CHECK-NEXT: [[VEC8_B:%.*]] = alloca <8 x bfloat>, align 16 +// CHECK-NEXT: [[VEC16_A:%.*]] = alloca <16 x bfloat>, align 32 +// CHECK-NEXT: [[VEC16_B:%.*]] = alloca <16 x bfloat>, align 32 +// CHECK-NEXT: [[VEC2_A_ASCAST:%.*]] = addrspacecast ptr [[VEC2_A]] to ptr addrspace(4) +// CHECK-NEXT: [[VEC2_B_ASCAST:%.*]] = addrspacecast ptr [[VEC2_B]] to ptr addrspace(4) +// CHECK-NEXT: [[VEC4_A_ASCAST:%.*]] = addrspacecast ptr [[VEC4_A]] to ptr addrspace(4) +// CHECK-NEXT: [[VEC4_B_ASCAST:%.*]] = addrspacecast ptr [[VEC4_B]] to ptr addrspace(4) +// CHECK-NEXT: [[VEC8_A_ASCAST:%.*]] = addrspacecast ptr [[VEC8_A]] to ptr addrspace(4) +// CHECK-NEXT: [[VEC8_B_ASCAST:%.*]] = addrspacecast ptr [[VEC8_B]] to ptr addrspace(4) +// CHECK-NEXT: [[VEC16_A_ASCAST:%.*]] = addrspacecast ptr [[VEC16_A]] to ptr addrspace(4) +// CHECK-NEXT: [[VEC16_B_ASCAST:%.*]] = addrspacecast ptr [[VEC16_B]] to ptr addrspace(4) +// CHECK-NEXT: [[TMP0:%.*]] = load <2 x bfloat>, ptr addrspace(4) [[VEC2_B_ASCAST]], align 4 +// CHECK-NEXT: store <2 x bfloat> [[TMP0]], ptr addrspace(4) [[VEC2_A_ASCAST]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = load <4 x bfloat>, ptr addrspace(4) [[VEC4_B_ASCAST]], align 8 +// CHECK-NEXT: store <4 x bfloat> [[TMP1]], ptr addrspace(4) [[VEC4_A_ASCAST]], align 8 +// CHECK-NEXT: [[TMP2:%.*]] = load <8 x bfloat>, ptr addrspace(4) [[VEC8_B_ASCAST]], align 16 +// CHECK-NEXT: store <8 x bfloat> [[TMP2]], ptr addrspace(4) [[VEC8_A_ASCAST]], align 16 +// CHECK-NEXT: [[TMP3:%.*]] = load <16 x bfloat>, ptr addrspace(4) [[VEC16_B_ASCAST]], align 32 +// CHECK-NEXT: store <16 x bfloat> [[TMP3]], ptr addrspace(4) [[VEC16_A_ASCAST]], align 32 +// CHECK-NEXT: ret void +// +__device__ void test_vec_assign() { + typedef __attribute__((ext_vector_type(2))) __bf16 bf16_x2; + bf16_x2 vec2_a, vec2_b; + vec2_a = vec2_b; + + typedef __attribute__((ext_vector_type(4))) __bf16 bf16_x4; + bf16_x4 vec4_a, vec4_b; + vec4_a = vec4_b; + + typedef __attribute__((ext_vector_type(8))) __bf16 bf16_x8; + bf16_x8 vec8_a, vec8_b; + vec8_a = vec8_b; + + typedef __attribute__((ext_vector_type(16))) __bf16 bf16_x16; + bf16_x16 vec16_a, vec16_b; + vec16_a = vec16_b; +} diff --git a/clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp b/clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp new file mode 100644 index 00000000000000..2487e0fcd4343a --- /dev/null +++ b/clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp @@ -0,0 +1,38 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm -o - %s | FileCheck %s + +// CHECK-LABEL: define spir_func void @_Z1fv( +// CHECK-SAME: ) addrspace(4) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[X:%.*]] = alloca half, align 2 +// CHECK-NEXT: [[Y:%.*]] = alloca half, align 2 +// CHECK-NEXT: [[Z:%.*]] = alloca half, align 2 +// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[X]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[Y]], align 2 +// CHECK-NEXT: [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]] +// CHECK-NEXT: store half [[ADD]], ptr [[Z]], align 2 +// CHECK-NEXT: [[TMP2:%.*]] = load half, ptr [[X]], align 2 +// CHECK-NEXT: [[TMP3:%.*]] = load half, ptr [[Y]], align 2 +// CHECK-NEXT: [[SUB:%.*]] = fsub half [[TMP2]], [[TMP3]] +// CHECK-NEXT: store half [[SUB]], ptr [[Z]], align 2 +// CHECK-NEXT: [[TMP4:%.*]] = load half, ptr [[X]], align 2 +// CHECK-NEXT: [[TMP5:%.*]] = load half, ptr [[Y]], align 2 +// CHECK-NEXT: [[MUL:%.*]] = fmul half [[TMP4]], [[TMP5]] +// CHECK-NEXT: store half [[MUL]], ptr [[Z]], align 2 +// CHECK-NEXT: [[TMP6:%.*]] = load half, ptr [[X]], align 2 +// CHECK-NEXT: [[TMP7:%.*]] = load half, ptr [[Y]], align 2 +// CHECK-NEXT: [[DIV:%.*]] = fdiv half [[TMP6]], [[TMP7]] +// CHECK-NEXT: store half [[DIV]], ptr [[Z]], align 2 +// CHECK-NEXT: ret void +// +void f() { + _Float16 x, y, z; + + z = x + y; + + z = x - y; + + z = x * y; + + z = x / y; +} diff --git a/clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp b/clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp new file mode 100644 index 00000000000000..8226a109d8b8d9 --- /dev/null +++ b/clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp @@ -0,0 +1,27 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -aux-triple x86_64-pc-windows-msvc -x hip -emit-llvm -fcuda-is-device -o - %s | FileCheck %s + +// Unlike OpenCL, HIP depends on the C++ interpration of "unsigned long", which +// is 64 bits long on Linux and 32 bits long on Windows. The return type of the +// ballot intrinsic needs to be a 64 bit integer on both platforms. This test +// cross-compiles to Windows to confirm that the return type is indeed 64 bits +// on Windows. + +#define __device__ __attribute__((device)) + +// CHECK-LABEL: define spir_func noundef i64 @_Z3fooi( +// CHECK-SAME: i32 noundef [[P:%.*]]) addrspace(4) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[RETVAL:%.*]] = alloca i64, align 8 +// CHECK-NEXT: [[P_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4) +// CHECK-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr [[P_ADDR]] to ptr addrspace(4) +// CHECK-NEXT: store i32 [[P]], ptr addrspace(4) [[P_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) [[P_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 +// CHECK-NEXT: [[TMP1:%.*]] = call addrspace(4) i64 @llvm.amdgcn.ballot.i64(i1 [[TOBOOL]]) +// CHECK-NEXT: ret i64 [[TMP1]] +// +__device__ unsigned long long foo(int p) { + return __builtin_amdgcn_ballot_w64(p); +} diff --git a/clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip b/clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip new file mode 100644 index 00000000000000..2b785200e8eeab --- /dev/null +++ b/clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip @@ -0,0 +1,46 @@ +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip -fcuda-is-device -emit-llvm %s \ +// RUN: -o - | FileCheck %s + +constexpr static int OpCtrl() +{ + return 15 + 1; +} + +constexpr static int RowMask() +{ + return 3 + 1; +} + +constexpr static int BankMask() +{ + return 2 + 1; +} + +constexpr static bool BountCtrl() +{ + return true & false; +} + +// CHECK: call{{.*}} i32 @llvm.amdgcn.update.dpp.i32(i32 %1, i32 %2, i32 16, i32 0, i32 0, i1 false) +__attribute__((global)) void test_update_dpp_const_fold_imm_operand_2(int* out, int a, int b) +{ + *out = __builtin_amdgcn_update_dpp(a, b, OpCtrl(), 0, 0, false); +} + +// CHECK: call{{.*}} i32 @llvm.amdgcn.update.dpp.i32(i32 %1, i32 %2, i32 0, i32 4, i32 0, i1 false) +__attribute__((global)) void test_update_dpp_const_fold_imm_operand_3(int* out, int a, int b) +{ + *out = __builtin_amdgcn_update_dpp(a, b, 0, RowMask(), 0, false); +} + +// CHECK: call{{.*}} i32 @llvm.amdgcn.update.dpp.i32(i32 %1, i32 %2, i32 0, i32 0, i32 3, i1 false) +__attribute__((global)) void test_update_dpp_const_fold_imm_operand_4(int* out, int a, int b) +{ + *out = __builtin_amdgcn_update_dpp(a, b, 0, 0, BankMask(), false); +} + +// CHECK: call{{.*}} i32 @llvm.amdgcn.update.dpp.i32(i32 %1, i32 %2, i32 0, i32 0, i32 0, i1 false) +__attribute__((global)) void test_update_dpp_const_fold_imm_operand_5(int* out, int a, int b) +{ + *out = __builtin_amdgcn_update_dpp(a, b, 0, 0, 0, BountCtrl()); +} diff --git a/clang/test/CodeGenHIP/spirv-amdgcn-half.hip b/clang/test/CodeGenHIP/spirv-amdgcn-half.hip new file mode 100644 index 00000000000000..2caf766d943b11 --- /dev/null +++ b/clang/test/CodeGenHIP/spirv-amdgcn-half.hip @@ -0,0 +1,15 @@ +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip -emit-llvm -fcuda-is-device -o - %s | FileCheck %s + +#define __device__ __attribute__((device)) + +// CHECK-LABEL: @_Z2d0DF16_ +// CHECK: fpext +__device__ float d0(_Float16 x) { + return x; +} + +// CHECK-LABEL: @_Z2d1f +// CHECK: fptrunc +__device__ _Float16 d1(float x) { + return x; +} diff --git a/clang/test/Preprocessor/predefined-macros-no-warnings.c b/clang/test/Preprocessor/predefined-macros-no-warnings.c index e0617f8de4da38..722e3e77214b64 100644 --- a/clang/test/Preprocessor/predefined-macros-no-warnings.c +++ b/clang/test/Preprocessor/predefined-macros-no-warnings.c @@ -173,6 +173,7 @@ // RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple spir64 // RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple spirv32 // RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple spirv64 +// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple spirv64-amd-amdhsa // RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple wasm32 // RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple wasm32-wasi // RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple wasm32-emscripten diff --git a/clang/test/Preprocessor/predefined-macros.c b/clang/test/Preprocessor/predefined-macros.c index c4a9672f0814aa..7f036bff401ca0 100644 --- a/clang/test/Preprocessor/predefined-macros.c +++ b/clang/test/Preprocessor/predefined-macros.c @@ -236,6 +236,16 @@ // CHECK-SPIRV64-DAG: #define __SPIRV64__ 1 // CHECK-SPIRV64-NOT: #define __SPIRV32__ 1 +// RUN: %clang_cc1 %s -E -dM -o - -x cl -triple spirv64-amd-amdhsa \ +// RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SPIRV64-AMDGCN +// CHECK-SPIRV64-AMDGCN-DAG: #define __IMAGE_SUPPORT__ 1 +// CHECK-SPIRV64-AMDGCN-DAG: #define __SPIRV__ 1 +// CHECK-SPIRV64-AMDGCN-DAG: #define __SPIRV64__ 1 +// CHECK-SPIRV64-AMDGCN-DAG: #define __AMD__ 1 +// CHECK-SPIRV64-AMDGCN-DAG: #define __AMDGCN__ 1 +// CHECK-SPIRV64-AMDGCN-DAG: #define __AMDGPU__ 1 +// CHECK-SPIRV64-AMDGCN-NOT: #define __SPIRV32__ 1 + // RUN: %clang_cc1 %s -E -dM -o - -x hip -triple x86_64-unknown-linux-gnu \ // RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-HIP // CHECK-HIP: #define __HIPCC__ 1 diff --git a/clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp b/clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp new file mode 100644 index 00000000000000..2b8fac72847d6a --- /dev/null +++ b/clang/test/Sema/builtin-spirv-amdgcn-atomic-inc-dec-failure.cpp @@ -0,0 +1,25 @@ +// RUN: %clang_cc1 %s -x hip -fcuda-is-device -o - \ +// RUN: -triple=spirv64-amd-amdhsa -fsyntax-only \ +// RUN: -verify=dev +// RUN: %clang_cc1 %s -x hip -triple x86_64 -o - \ +// RUN: -aux-triple spirv64-amd-amdhsa -fsyntax-only \ +// RUN: -verify=host + +// dev-no-diagnostics + +void test_host() { + __UINT32_TYPE__ val32; + __UINT64_TYPE__ val64; + + // host-error@+1 {{reference to __device__ function '__builtin_amdgcn_atomic_inc32' in __host__ function}} + val32 = __builtin_amdgcn_atomic_inc32(&val32, val32, __ATOMIC_SEQ_CST, ""); + + // host-error@+1 {{reference to __device__ function '__builtin_amdgcn_atomic_inc64' in __host__ function}} + val64 = __builtin_amdgcn_atomic_inc64(&val64, val64, __ATOMIC_SEQ_CST, ""); + + // host-error@+1 {{reference to __device__ function '__builtin_amdgcn_atomic_dec32' in __host__ function}} + val32 = __builtin_amdgcn_atomic_dec32(&val32, val32, __ATOMIC_SEQ_CST, ""); + + // host-error@+1 {{reference to __device__ function '__builtin_amdgcn_atomic_dec64' in __host__ function}} + val64 = __builtin_amdgcn_atomic_dec64(&val64, val64, __ATOMIC_SEQ_CST, ""); +} diff --git a/clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl b/clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl new file mode 100644 index 00000000000000..0fb1b5f3672265 --- /dev/null +++ b/clang/test/Sema/inline-asm-validate-spirv-amdgcn.cl @@ -0,0 +1,111 @@ +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -fsyntax-only -verify %s + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +kernel void test () { + + int sgpr = 0, vgpr = 0, imm = 0; + + // sgpr constraints + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "s" (imm) : ); + + __asm__ ("s_mov_b32 %0, %1" : "={s1}" (sgpr) : "{exec}" (imm) : ); + __asm__ ("s_mov_b32 %0, %1" : "={s1}" (sgpr) : "{exe" (imm) : ); // expected-error {{invalid input constraint '{exe' in asm}} + __asm__ ("s_mov_b32 %0, %1" : "={s1}" (sgpr) : "{exec" (imm) : ); // expected-error {{invalid input constraint '{exec' in asm}} + __asm__ ("s_mov_b32 %0, %1" : "={s1}" (sgpr) : "{exec}a" (imm) : ); // expected-error {{invalid input constraint '{exec}a' in asm}} + + // vgpr constraints + __asm__ ("v_mov_b32 %0, %1" : "=v" (vgpr) : "v" (imm) : ); + + // 'I' constraint (an immediate integer in the range -16 to 64) + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "I" (imm) : ); + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "I" (-16) : ); + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "I" (64) : ); + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "I" (-17) : ); // expected-error {{value '-17' out of range for constraint 'I'}} + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "I" (65) : ); // expected-error {{value '65' out of range for constraint 'I'}} + + // 'J' constraint (an immediate 16-bit signed integer) + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "J" (imm) : ); + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "J" (-32768) : ); + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "J" (32767) : ); + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "J" (-32769) : ); // expected-error {{value '-32769' out of range for constraint 'J'}} + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "J" (32768) : ); // expected-error {{value '32768' out of range for constraint 'J'}} + + // 'A' constraint (an immediate constant that can be inlined) + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "A" (imm) : ); + + // 'B' constraint (an immediate 32-bit signed integer) + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "B" (imm) : ); + + // 'C' constraint (an immediate 32-bit unsigned integer or 'A' constraint) + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "C" (imm) : ); + + // 'DA' constraint (an immediate 64-bit constant that can be split into two 'A' constants) + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "DA" (imm) : ); + + // 'DB' constraint (an immediate 64-bit constant that can be split into two 'B' constants) + __asm__ ("s_mov_b32 %0, %1" : "=s" (sgpr) : "DB" (imm) : ); + +} + +__kernel void +test_float(const __global float *a, const __global float *b, __global float *c, unsigned i) +{ + float ai = a[i]; + float bi = b[i]; + float ci; + + __asm("v_add_f32_e32 v1, v2, v3" : "={v1}"(ci) : "{v2}"(ai), "{v3}"(bi) : ); + __asm("v_add_f32_e32 v1, v2, v3" : ""(ci) : "{v2}"(ai), "{v3}"(bi) : ); // expected-error {{invalid output constraint '' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "="(ci) : "{v2}"(ai), "{v3}"(bi) : ); // expected-error {{invalid output constraint '=' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "={a}"(ci) : "{v2}"(ai), "{v3}"(bi) : ); // expected-error {{invalid output constraint '={a}' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "={"(ci) : "{v2}"(ai), "{v3}"(bi) : ); // expected-error {{invalid output constraint '={' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "={}"(ci) : "{v2}"(ai), "{v3}"(bi) : ); // expected-error {{invalid output constraint '={}' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "={v"(ci) : "{v2}"(ai), "{v3}"(bi) : ); // expected-error {{invalid output constraint '={v' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "={v1a}"(ci) : "{v2}"(ai), "{v3}"(bi) : ); // expected-error {{invalid output constraint '={v1a}' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "={va}"(ci) : "{v2}"(ai), "{v3}"(bi) : ); // expected-error {{invalid output constraint '={va}' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "={v1}a"(ci) : "{v2}"(ai), "{v3}"(bi) : ); // expected-error {{invalid output constraint '={v1}a' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "={v1"(ci) : "{v2}"(ai), "{v3}"(bi) : ); // expected-error {{invalid output constraint '={v1' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "=v1}"(ci) : "{v2}"(ai), "{v3}"(bi) : ); // expected-error {{invalid output constraint '=v1}' in asm}} + + __asm("v_add_f32_e32 v1, v2, v3" : "={v[1]}"(ci) : "{v[2]}"(ai), "{v[3]}"(bi) : ); + __asm("v_add_f32_e32 v1, v2, v3" : "={v[1}"(ci) : "{v[2]}"(ai), "{v[3]}"(bi) : ); // expected-error {{invalid output constraint '={v[1}' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "={v[1]"(ci) : "{v[2]}"(ai), "{v[3]}"(bi) : ); // expected-error {{invalid output constraint '={v[1]' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "={v[a]}"(ci) : "{v[2]}"(ai), "{v[3]}"(bi) : ); // expected-error {{invalid output constraint '={v[a]}' in asm}} + + __asm("v_add_f32_e32 v1, v2, v3" : "=v"(ci) : "v"(ai), "v"(bi) : ); + __asm("v_add_f32_e32 v1, v2, v3" : "=v1"(ci) : "v2"(ai), "v3"(bi) : ); /// expected-error {{invalid output constraint '=v1' in asm}} + + __asm("v_add_f32_e32 v1, v2, v3" : "={v1}"(ci) : "{a}"(ai), "{v3}"(bi) : ); // expected-error {{invalid input constraint '{a}' in asm}} + __asm("v_add_f32_e32 v1, v2, v3" : "={v1}"(ci) : "{v2}"(ai), "{a}"(bi) : ); // expected-error {{invalid input constraint '{a}' in asm}} + c[i] = ci; +} + +__kernel void +test_double(const __global double *a, const __global double *b, __global double *c, unsigned i) +{ + double ai = a[i]; + double bi = b[i]; + double ci; + + __asm("v_add_f64_e64 v[1:2], v[3:4], v[5:6]" : "={v[1:2]}"(ci) : "{v[3:4]}"(ai), "{v[5:6]}"(bi) : ); + __asm("v_add_f64_e64 v[1:2], v[3:4], v[5:6]" : "=v{[1:2]}"(ci) : "{v[3:4]}"(ai), "{v[5:6]}"(bi) : ); //expected-error {{invalid output constraint '=v{[1:2]}' in asm}} + __asm("v_add_f64_e64 v[1:2], v[3:4], v[5:6]" : "={v[1:2]a}"(ci) : "{v[3:4]}"(ai), "{v[5:6]}"(bi) : ); //expected-error {{invalid output constraint '={v[1:2]a}' in asm}} + __asm("v_add_f64_e64 v[1:2], v[3:4], v[5:6]" : "={v[1:2]}a"(ci) : "{v[3:4]}"(ai), "{v[5:6]}"(bi) : ); //expected-error {{invalid output constraint '={v[1:2]}a' in asm}} + __asm("v_add_f64_e64 v[1:2], v[3:4], v[5:6]" : "={v[1:"(ci) : "{v[3:4]}"(ai), "{v[5:6]}"(bi) : ); //expected-error {{invalid output constraint '={v[1:' in asm}} + __asm("v_add_f64_e64 v[1:2], v[3:4], v[5:6]" : "={v[1:]}"(ci) : "{v[3:4]}"(ai), "{v[5:6]}"(bi) : ); //expected-error {{invalid output constraint '={v[1:]}' in asm}} + __asm("v_add_f64_e64 v[1:2], v[3:4], v[5:6]" : "={v[:2]}"(ci) : "{v[3:4]}"(ai), "{v[5:6]}"(bi) : ); //expected-error {{invalid output constraint '={v[:2]}' in asm}} + __asm("v_add_f64_e64 v[1:2], v[3:4], v[5:6]" : "={v[1:2]"(ci) : "{v[3:4]}"(ai), "{v[5:6]}"(bi) : ); //expected-error {{invalid output constraint '={v[1:2]' in asm}} + __asm("v_add_f64_e64 v[1:2], v[3:4], v[5:6]" : "={v[1:2}"(ci) : "{v[3:4]}"(ai), "{v[5:6]}"(bi) : ); //expected-error {{invalid output constraint '={v[1:2}' in asm}} + __asm("v_add_f64_e64 v[1:2], v[3:4], v[5:6]" : "={v[2:1]}"(ci) : "{v[3:4]}"(ai), "{v[5:6]}"(bi) : ); //expected-error {{invalid output constraint '={v[2:1]}' in asm}} + + __asm("v_add_f64_e64 v[1:2], v[3:4], v[5:6]" : "=v[1:2]"(ci) : "v[3:4]"(ai), "v[5:6]"(bi) : ); //expected-error {{invalid output constraint '=v[1:2]' in asm}} + + c[i] = ci; +} + +void test_long(int arg0) { + long v15_16; + __asm volatile("v_lshlrev_b64 v[15:16], 0, %0" : "={v[15:16]}"(v15_16) : "v"(arg0)); +} diff --git a/clang/test/SemaCUDA/allow-int128.cu b/clang/test/SemaCUDA/allow-int128.cu index eb7b7e7f52862b..af3e8c2453ad18 100644 --- a/clang/test/SemaCUDA/allow-int128.cu +++ b/clang/test/SemaCUDA/allow-int128.cu @@ -1,6 +1,9 @@ // RUN: %clang_cc1 -triple amdgcn-amd-amdhsa \ // RUN: -aux-triple x86_64-unknown-linux-gnu \ // RUN: -fcuda-is-device -verify -fsyntax-only %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa \ +// RUN: -aux-triple x86_64-unknown-linux-gnu \ +// RUN: -fcuda-is-device -verify -fsyntax-only %s // RUN: %clang_cc1 -triple nvptx \ // RUN: -aux-triple x86_64-unknown-linux-gnu \ // RUN: -fcuda-is-device -verify -fsyntax-only %s diff --git a/clang/test/SemaCUDA/amdgpu-f128.cu b/clang/test/SemaCUDA/amdgpu-f128.cu index 9a0212cdb93cff..1f5a6553dcc4fd 100644 --- a/clang/test/SemaCUDA/amdgpu-f128.cu +++ b/clang/test/SemaCUDA/amdgpu-f128.cu @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -aux-triple x86_64-unknown-linux-gnu -fcuda-is-device -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -aux-triple x86_64-unknown-linux-gnu -fcuda-is-device -fsyntax-only -verify %s // expected-no-diagnostics typedef __float128 f128_t; diff --git a/clang/test/SemaCUDA/float16.cu b/clang/test/SemaCUDA/float16.cu index bb5ed606438491..9c7faef284fee7 100644 --- a/clang/test/SemaCUDA/float16.cu +++ b/clang/test/SemaCUDA/float16.cu @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -fsyntax-only -triple x86_64 -aux-triple amdgcn -verify %s +// RUN: %clang_cc1 -fsyntax-only -triple x86_64 -aux-triple spirv64-amd-amdhsa -verify %s // RUN: %clang_cc1 -fsyntax-only -triple x86_64 -aux-triple nvptx64 -verify %s // expected-no-diagnostics #include "Inputs/cuda.h" diff --git a/clang/test/SemaCUDA/fp16-arg-return.cu b/clang/test/SemaCUDA/fp16-arg-return.cu index 23a9613b18b284..cc73dc4751d329 100644 --- a/clang/test/SemaCUDA/fp16-arg-return.cu +++ b/clang/test/SemaCUDA/fp16-arg-return.cu @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -emit-llvm -o - -triple amdgcn-amd-amdhsa -fcuda-is-device -fsyntax-only -verify %s +// RUN: %clang_cc1 -emit-llvm -o - -triple spirv64-amd-amdhsa -fcuda-is-device -fsyntax-only -verify %s // expected-no-diagnostics diff --git a/clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu b/clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu new file mode 100644 index 00000000000000..ea1f24670ff9a8 --- /dev/null +++ b/clang/test/SemaCUDA/spirv-amdgcn-atomic-ops.cu @@ -0,0 +1,86 @@ +// RUN: %clang_cc1 -x hip -std=c++11 -triple spirv64-amd-amdhsa -fcuda-is-device -verify -fsyntax-only %s + +#include "Inputs/cuda.h" + +__device__ int test_hip_atomic_load(int *pi32, unsigned int *pu32, long long *pll, unsigned long long *pull, float *fp, double *dbl) { + int val = __hip_atomic_load(0); // expected-error {{too few arguments to function call, expected 3, have 1}} + val = __hip_atomic_load(0, 0, 0, 0); // expected-error {{too many arguments to function call, expected 3, have 4}} + val = __hip_atomic_load(0, 0, 0); // expected-error {{address argument to atomic builtin must be a pointer ('int' invalid)}} + val = __hip_atomic_load(pi32, 0, 0); // expected-error {{synchronization scope argument to atomic operation is invalid}} + val = __hip_atomic_load(pi32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + val = __hip_atomic_load(pi32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); + val = __hip_atomic_load(pi32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); + val = __hip_atomic_load(pi32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); + val = __hip_atomic_load(pi32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); + val = __hip_atomic_load(pi32, __ATOMIC_RELAXED, 6); // expected-error {{synchronization scope argument to atomic operation is invalid}} + val = __hip_atomic_load(pi32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + val = __hip_atomic_load(pi32, __ATOMIC_SEQ_CST, __HIP_MEMORY_SCOPE_SINGLETHREAD); + val = __hip_atomic_load(pi32, __ATOMIC_CONSUME, __HIP_MEMORY_SCOPE_SINGLETHREAD); + val = __hip_atomic_load(pi32, __ATOMIC_ACQUIRE, __HIP_MEMORY_SCOPE_SINGLETHREAD); + val = __hip_atomic_load(pi32, __ATOMIC_ACQ_REL, __HIP_MEMORY_SCOPE_SINGLETHREAD); // expected-warning{{memory order argument to atomic operation is invalid}} + val = __hip_atomic_load(pu32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + val = __hip_atomic_load(pll, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + val = __hip_atomic_load(pull, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + val = __hip_atomic_load(fp, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + val = __hip_atomic_load(dbl, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + return val; +} + +__device__ int test_hip_atomic_store(int *pi32, unsigned int *pu32, long long *pll, unsigned long long *pull, float *fp, double *dbl, + int i32, unsigned int u32, long long i64, unsigned long long u64, float f32, double f64) { + __hip_atomic_store(0); // expected-error {{too few arguments to function call, expected 4, have 1}} + __hip_atomic_store(0, 0, 0, 0, 0); // expected-error {{too many arguments to function call, expected 4, have 5}} + __hip_atomic_store(0, 0, 0, 0); // expected-error {{address argument to atomic builtin must be a pointer ('int' invalid)}} + __hip_atomic_store(pi32, 0, 0, 0); // expected-error {{synchronization scope argument to atomic operation is invalid}} + __hip_atomic_store(pi32, 0, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(pi32, 0, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); + __hip_atomic_store(pi32, 0, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); + __hip_atomic_store(pi32, 0, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); + __hip_atomic_store(pi32, 0, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); + __hip_atomic_store(pi32, 0, __ATOMIC_RELAXED, 6); // expected-error {{synchronization scope argument to atomic operation is invalid}} + __hip_atomic_store(pi32, 0, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(pi32, 0, __ATOMIC_SEQ_CST, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(pi32, 0, __ATOMIC_CONSUME, __HIP_MEMORY_SCOPE_SINGLETHREAD); // expected-warning{{memory order argument to atomic operation is invalid}} + __hip_atomic_store(pi32, 0, __ATOMIC_ACQUIRE, __HIP_MEMORY_SCOPE_SINGLETHREAD); // expected-warning{{memory order argument to atomic operation is invalid}} + __hip_atomic_store(pi32, 0, __ATOMIC_ACQ_REL, __HIP_MEMORY_SCOPE_SINGLETHREAD); // expected-warning{{memory order argument to atomic operation is invalid}} + __hip_atomic_store(pi32, i32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(pi32, i32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(pu32, u32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(pll, i64, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(pull, u64, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(fp, f32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(dbl, f64, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(pi32, u32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(pi32, i64, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(pi32, u64, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(pll, i32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(fp, i32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(fp, i64, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(dbl, i64, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + __hip_atomic_store(dbl, i32, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + return 0; +} + +__device__ bool test_hip_atomic_cmpxchg_weak(int *ptr, int val, int desired) { + bool flag = __hip_atomic_compare_exchange_weak(0); // expected-error {{too few arguments to function call, expected 6, have 1}} + flag = __hip_atomic_compare_exchange_weak(0, 0, 0, 0, 0, 0, 0); // expected-error {{too many arguments to function call, expected 6, have 7}} + flag = __hip_atomic_compare_exchange_weak(0, 0, 0, 0, 0, 0); // expected-error {{address argument to atomic builtin must be a pointer ('int' invalid)}} + flag = __hip_atomic_compare_exchange_weak(ptr, 0, 0, 0, 0, 0); // expected-error {{synchronization scope argument to atomic operation is invalid}}, expected-warning {{null passed to a callee that requires a non-null argument}} + flag = __hip_atomic_compare_exchange_weak(ptr, 0, 0, 0, 0, __HIP_MEMORY_SCOPE_SYSTEM); // expected-warning {{null passed to a callee that requires a non-null argument}} + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_CONSUME, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_SEQ_CST, __HIP_MEMORY_SCOPE_SINGLETHREAD); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_CONSUME, __HIP_MEMORY_SCOPE_SINGLETHREAD); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_ACQUIRE, __HIP_MEMORY_SCOPE_SINGLETHREAD); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_ACQ_REL, __HIP_MEMORY_SCOPE_SINGLETHREAD); // expected-warning {{failure memory order argument to atomic operation is invalid}} + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_CONSUME, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_ACQUIRE, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + return flag; +} From 393ce66f98e8f1e96384b0028ad13dddf99a1f30 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 23 Apr 2024 18:22:59 +0100 Subject: [PATCH 02/15] Fix formatting. --- clang/lib/Basic/Targets/SPIR.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h index 6b605979c9ab1d..d68b6dcb1340f2 100644 --- a/clang/lib/Basic/Targets/SPIR.h +++ b/clang/lib/Basic/Targets/SPIR.h @@ -365,7 +365,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64TargetInfo : public BaseSPIRVTargetInfo { }; class LLVM_LIBRARY_VISIBILITY SPIRV64AMDGCNTargetInfo - : public BaseSPIRVTargetInfo { + : public BaseSPIRVTargetInfo { public: SPIRV64AMDGCNTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : BaseSPIRVTargetInfo(Triple, Opts) { From 98db8f7ad89d1239096d1c4f8695a1557bfe4429 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Thu, 25 Apr 2024 02:58:55 +0100 Subject: [PATCH 03/15] Use `fillAMDGPUFeatureMap` instead of copy-pasta. --- clang/lib/Basic/Targets/SPIR.cpp | 39 ++----------------------- llvm/lib/TargetParser/TargetParser.cpp | 40 +++++++++++++++++++++++++- 2 files changed, 41 insertions(+), 38 deletions(-) diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp index d7d232ac9484f8..edce728be40a20 100644 --- a/clang/lib/Basic/Targets/SPIR.cpp +++ b/clang/lib/Basic/Targets/SPIR.cpp @@ -14,6 +14,7 @@ #include "Targets.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/TargetBuiltins.h" +#include "llvm/TargetParser/TargetParser.h" using namespace clang; using namespace clang::targets; @@ -152,43 +153,7 @@ ArrayRef SPIRV64AMDGCNTargetInfo::getGCCRegNames() const { bool SPIRV64AMDGCNTargetInfo::initFeatureMap( llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef, const std::vector &FeatureVec) const { - // This represents the union of all AMDGCN features. - Features["atomic-ds-pk-add-16-insts"] = true; - Features["atomic-flat-pk-add-16-insts"] = true; - Features["atomic-buffer-global-pk-add-f16-insts"] = true; - Features["atomic-global-pk-add-bf16-inst"] = true; - Features["atomic-fadd-rtn-insts"] = true; - Features["ci-insts"] = true; - Features["dot1-insts"] = true; - Features["dot2-insts"] = true; - Features["dot3-insts"] = true; - Features["dot4-insts"] = true; - Features["dot5-insts"] = true; - Features["dot7-insts"] = true; - Features["dot8-insts"] = true; - Features["dot9-insts"] = true; - Features["dot10-insts"] = true; - Features["dot11-insts"] = true; - Features["dl-insts"] = true; - Features["16-bit-insts"] = true; - Features["dpp"] = true; - Features["gfx8-insts"] = true; - Features["gfx9-insts"] = true; - Features["gfx90a-insts"] = true; - Features["gfx940-insts"] = true; - Features["gfx10-insts"] = true; - Features["gfx10-3-insts"] = true; - Features["gfx11-insts"] = true; - Features["gfx12-insts"] = true; - Features["image-insts"] = true; - Features["fp8-conversion-insts"] = true; - Features["s-memrealtime"] = true; - Features["s-memtime-inst"] = true; - Features["gws"] = true; - Features["fp8-insts"] = true; - Features["fp8-conversion-insts"] = true; - Features["atomic-ds-pk-add-16-insts"] = true; - Features["mai-insts"] = true; + llvm::AMDGPU::fillAMDGPUFeatureMap({}, getTriple(), Features); return TargetInfo::initFeatureMap(Features, Diags, {}, FeatureVec); } diff --git a/llvm/lib/TargetParser/TargetParser.cpp b/llvm/lib/TargetParser/TargetParser.cpp index 0d784a79e5bac6..50757b74606f13 100644 --- a/llvm/lib/TargetParser/TargetParser.cpp +++ b/llvm/lib/TargetParser/TargetParser.cpp @@ -309,7 +309,45 @@ StringRef AMDGPU::getCanonicalArchName(const Triple &T, StringRef Arch) { void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple &T, StringMap &Features) { // XXX - What does the member GPU mean if device name string passed here? - if (T.isAMDGCN()) { + if (T.isSPIRV() && T.getOS() == Triple::OSType::AMDHSA) { + // AMDGCN SPIRV must support the union of all AMDGCN features. + Features["atomic-ds-pk-add-16-insts"] = true; + Features["atomic-flat-pk-add-16-insts"] = true; + Features["atomic-buffer-global-pk-add-f16-insts"] = true; + Features["atomic-global-pk-add-bf16-inst"] = true; + Features["atomic-fadd-rtn-insts"] = true; + Features["ci-insts"] = true; + Features["dot1-insts"] = true; + Features["dot2-insts"] = true; + Features["dot3-insts"] = true; + Features["dot4-insts"] = true; + Features["dot5-insts"] = true; + Features["dot7-insts"] = true; + Features["dot8-insts"] = true; + Features["dot9-insts"] = true; + Features["dot10-insts"] = true; + Features["dot11-insts"] = true; + Features["dl-insts"] = true; + Features["16-bit-insts"] = true; + Features["dpp"] = true; + Features["gfx8-insts"] = true; + Features["gfx9-insts"] = true; + Features["gfx90a-insts"] = true; + Features["gfx940-insts"] = true; + Features["gfx10-insts"] = true; + Features["gfx10-3-insts"] = true; + Features["gfx11-insts"] = true; + Features["gfx12-insts"] = true; + Features["image-insts"] = true; + Features["fp8-conversion-insts"] = true; + Features["s-memrealtime"] = true; + Features["s-memtime-inst"] = true; + Features["gws"] = true; + Features["fp8-insts"] = true; + Features["fp8-conversion-insts"] = true; + Features["atomic-ds-pk-add-16-insts"] = true; + Features["mai-insts"] = true; + } else if (T.isAMDGCN()) { switch (parseArchAMDGCN(GPU)) { case GK_GFX1201: case GK_GFX1200: From c359e0ac08781540ccd1e0b6059a66adf48c513b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Thu, 25 Apr 2024 02:59:14 +0100 Subject: [PATCH 04/15] Add `__has_builtin` test. --- clang/test/Preprocessor/hash_builtin.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/clang/test/Preprocessor/hash_builtin.cpp b/clang/test/Preprocessor/hash_builtin.cpp index 77d186c7883f22..018b71eca418eb 100644 --- a/clang/test/Preprocessor/hash_builtin.cpp +++ b/clang/test/Preprocessor/hash_builtin.cpp @@ -1,11 +1,14 @@ // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx906 -E %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -E %s -o - | FileCheck %s --check-prefix=SPIRV-AMDGCN // CHECK: has_s_memtime_inst +// SPIRV-AMDGCN: has_s_memtime_inst #if __has_builtin(__builtin_amdgcn_s_memtime) int has_s_memtime_inst; #endif // CHECK-NOT: has_gfx10_inst +// SPIRV-AMDGCN: has_gfx10_inst #if __has_builtin(__builtin_amdgcn_mov_dpp8) int has_gfx10_inst; #endif From c41726dec6f09934507e5a298ad5cfebbe36725f Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Sun, 28 Apr 2024 16:27:27 +0100 Subject: [PATCH 05/15] Re-use `AMDGPUTargetInfo`, where feasible, instead of copypasta-ing. --- clang/lib/Basic/Targets/SPIR.cpp | 189 +------------------------------ clang/lib/Basic/Targets/SPIR.h | 2 +- 2 files changed, 7 insertions(+), 184 deletions(-) diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp index edce728be40a20..e7936e39c7c986 100644 --- a/clang/lib/Basic/Targets/SPIR.cpp +++ b/clang/lib/Basic/Targets/SPIR.cpp @@ -10,10 +10,9 @@ // //===----------------------------------------------------------------------===// +#include "AMDGPU.h" #include "SPIR.h" #include "Targets.h" -#include "clang/Basic/Builtins.h" -#include "clang/Basic/TargetBuiltins.h" #include "llvm/TargetParser/TargetParser.h" using namespace clang; @@ -58,96 +57,13 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions &Opts, DefineStd(Builder, "SPIRV64", Opts); } -static constexpr Builtin::Info BuiltinInfo[] = { -#define BUILTIN(ID, TYPE, ATTRS) \ - {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, -#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ - {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, -#include "clang/Basic/BuiltinsAMDGPU.def" -}; - namespace { -const char *AMDGPUGCCRegNames[] = { - "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", - "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", - "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", - "v27", "v28", "v29", "v30", "v31", "v32", "v33", "v34", "v35", - "v36", "v37", "v38", "v39", "v40", "v41", "v42", "v43", "v44", - "v45", "v46", "v47", "v48", "v49", "v50", "v51", "v52", "v53", - "v54", "v55", "v56", "v57", "v58", "v59", "v60", "v61", "v62", - "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", - "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80", - "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89", - "v90", "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98", - "v99", "v100", "v101", "v102", "v103", "v104", "v105", "v106", "v107", - "v108", "v109", "v110", "v111", "v112", "v113", "v114", "v115", "v116", - "v117", "v118", "v119", "v120", "v121", "v122", "v123", "v124", "v125", - "v126", "v127", "v128", "v129", "v130", "v131", "v132", "v133", "v134", - "v135", "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", - "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", "v152", - "v153", "v154", "v155", "v156", "v157", "v158", "v159", "v160", "v161", - "v162", "v163", "v164", "v165", "v166", "v167", "v168", "v169", "v170", - "v171", "v172", "v173", "v174", "v175", "v176", "v177", "v178", "v179", - "v180", "v181", "v182", "v183", "v184", "v185", "v186", "v187", "v188", - "v189", "v190", "v191", "v192", "v193", "v194", "v195", "v196", "v197", - "v198", "v199", "v200", "v201", "v202", "v203", "v204", "v205", "v206", - "v207", "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", - "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", "v224", - "v225", "v226", "v227", "v228", "v229", "v230", "v231", "v232", "v233", - "v234", "v235", "v236", "v237", "v238", "v239", "v240", "v241", "v242", - "v243", "v244", "v245", "v246", "v247", "v248", "v249", "v250", "v251", - "v252", "v253", "v254", "v255", "s0", "s1", "s2", "s3", "s4", - "s5", "s6", "s7", "s8", "s9", "s10", "s11", "s12", "s13", - "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22", - "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", - "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", "s40", - "s41", "s42", "s43", "s44", "s45", "s46", "s47", "s48", "s49", - "s50", "s51", "s52", "s53", "s54", "s55", "s56", "s57", "s58", - "s59", "s60", "s61", "s62", "s63", "s64", "s65", "s66", "s67", - "s68", "s69", "s70", "s71", "s72", "s73", "s74", "s75", "s76", - "s77", "s78", "s79", "s80", "s81", "s82", "s83", "s84", "s85", - "s86", "s87", "s88", "s89", "s90", "s91", "s92", "s93", "s94", - "s95", "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", - "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", "s112", - "s113", "s114", "s115", "s116", "s117", "s118", "s119", "s120", "s121", - "s122", "s123", "s124", "s125", "s126", "s127", "exec", "vcc", "scc", - "m0", "flat_scratch", "exec_lo", "exec_hi", "vcc_lo", "vcc_hi", - "flat_scratch_lo", "flat_scratch_hi", - "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", - "a9", "a10", "a11", "a12", "a13", "a14", "a15", "a16", "a17", - "a18", "a19", "a20", "a21", "a22", "a23", "a24", "a25", "a26", - "a27", "a28", "a29", "a30", "a31", "a32", "a33", "a34", "a35", - "a36", "a37", "a38", "a39", "a40", "a41", "a42", "a43", "a44", - "a45", "a46", "a47", "a48", "a49", "a50", "a51", "a52", "a53", - "a54", "a55", "a56", "a57", "a58", "a59", "a60", "a61", "a62", - "a63", "a64", "a65", "a66", "a67", "a68", "a69", "a70", "a71", - "a72", "a73", "a74", "a75", "a76", "a77", "a78", "a79", "a80", - "a81", "a82", "a83", "a84", "a85", "a86", "a87", "a88", "a89", - "a90", "a91", "a92", "a93", "a94", "a95", "a96", "a97", "a98", - "a99", "a100", "a101", "a102", "a103", "a104", "a105", "a106", "a107", - "a108", "a109", "a110", "a111", "a112", "a113", "a114", "a115", "a116", - "a117", "a118", "a119", "a120", "a121", "a122", "a123", "a124", "a125", - "a126", "a127", "a128", "a129", "a130", "a131", "a132", "a133", "a134", - "a135", "a136", "a137", "a138", "a139", "a140", "a141", "a142", "a143", - "a144", "a145", "a146", "a147", "a148", "a149", "a150", "a151", "a152", - "a153", "a154", "a155", "a156", "a157", "a158", "a159", "a160", "a161", - "a162", "a163", "a164", "a165", "a166", "a167", "a168", "a169", "a170", - "a171", "a172", "a173", "a174", "a175", "a176", "a177", "a178", "a179", - "a180", "a181", "a182", "a183", "a184", "a185", "a186", "a187", "a188", - "a189", "a190", "a191", "a192", "a193", "a194", "a195", "a196", "a197", - "a198", "a199", "a200", "a201", "a202", "a203", "a204", "a205", "a206", - "a207", "a208", "a209", "a210", "a211", "a212", "a213", "a214", "a215", - "a216", "a217", "a218", "a219", "a220", "a221", "a222", "a223", "a224", - "a225", "a226", "a227", "a228", "a229", "a230", "a231", "a232", "a233", - "a234", "a235", "a236", "a237", "a238", "a239", "a240", "a241", "a242", - "a243", "a244", "a245", "a246", "a247", "a248", "a249", "a250", "a251", - "a252", "a253", "a254", "a255" -}; +const AMDGPUTargetInfo AMDGPUTI(llvm::Triple("amdgcn-amd-amdhsa"), {}); } // anonymous namespace ArrayRef SPIRV64AMDGCNTargetInfo::getGCCRegNames() const { - return llvm::ArrayRef(AMDGPUGCCRegNames); + return AMDGPUTI.getGCCRegNames(); } bool SPIRV64AMDGCNTargetInfo::initFeatureMap( @@ -160,109 +76,16 @@ bool SPIRV64AMDGCNTargetInfo::initFeatureMap( bool SPIRV64AMDGCNTargetInfo::validateAsmConstraint( const char *&Name, TargetInfo::ConstraintInfo &Info) const { - // This is a 1:1 copy of AMDGPUTargetInfo::validateAsmConstraint() - static const ::llvm::StringSet<> SpecialRegs({ - "exec", "vcc", "flat_scratch", "m0", "scc", "tba", "tma", - "flat_scratch_lo", "flat_scratch_hi", "vcc_lo", "vcc_hi", "exec_lo", - "exec_hi", "tma_lo", "tma_hi", "tba_lo", "tba_hi", - }); - - switch (*Name) { - case 'I': - Info.setRequiresImmediate(-16, 64); - return true; - case 'J': - Info.setRequiresImmediate(-32768, 32767); - return true; - case 'A': - case 'B': - case 'C': - Info.setRequiresImmediate(); - return true; - default: - break; - } - - StringRef S(Name); - - if (S == "DA" || S == "DB") { - Name++; - Info.setRequiresImmediate(); - return true; - } - - bool HasLeftParen = S.consume_front("{"); - if (S.empty()) - return false; - if (S.front() != 'v' && S.front() != 's' && S.front() != 'a') { - if (!HasLeftParen) - return false; - auto E = S.find('}'); - if (!SpecialRegs.count(S.substr(0, E))) - return false; - S = S.drop_front(E + 1); - if (!S.empty()) - return false; - // Found {S} where S is a special register. - Info.setAllowsRegister(); - Name = S.data() - 1; - return true; - } - S = S.drop_front(); - if (!HasLeftParen) { - if (!S.empty()) - return false; - // Found s, v or a. - Info.setAllowsRegister(); - Name = S.data() - 1; - return true; - } - bool HasLeftBracket = S.consume_front("["); - unsigned long long N; - if (S.empty() || consumeUnsignedInteger(S, 10, N)) - return false; - if (S.consume_front(":")) { - if (!HasLeftBracket) - return false; - unsigned long long M; - if (consumeUnsignedInteger(S, 10, M) || N >= M) - return false; - } - if (HasLeftBracket) { - if (!S.consume_front("]")) - return false; - } - if (!S.consume_front("}")) - return false; - if (!S.empty()) - return false; - // Found {vn}, {sn}, {an}, {v[n]}, {s[n]}, {a[n]}, {v[n:m]}, {s[n:m]} - // or {a[n:m]}. - Info.setAllowsRegister(); - Name = S.data() - 1; - return true; + return AMDGPUTI.validateAsmConstraint(Name, Info); } std::string SPIRV64AMDGCNTargetInfo::convertConstraint(const char *&Constraint) const { - // This is a 1:1 copy of AMDGPUTargetInfo::convertConstraint() - StringRef S(Constraint); - if (S == "DA" || S == "DB") { - return std::string("^") + std::string(Constraint++, 2); - } - - const char *Begin = Constraint; - TargetInfo::ConstraintInfo Info("", ""); - if (validateAsmConstraint(Constraint, Info)) - return std::string(Begin).substr(0, Constraint - Begin + 1); - - Constraint = Begin; - return std::string(1, *Constraint); + return AMDGPUTI.convertConstraint(Constraint); } ArrayRef SPIRV64AMDGCNTargetInfo::getTargetBuiltins() const { - return llvm::ArrayRef(BuiltinInfo, - clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); + return AMDGPUTI.getTargetBuiltins(); } void SPIRV64AMDGCNTargetInfo::getTargetDefines(const LangOptions &Opts, diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h index d68b6dcb1340f2..37cf9d7921bac5 100644 --- a/clang/lib/Basic/Targets/SPIR.h +++ b/clang/lib/Basic/Targets/SPIR.h @@ -364,7 +364,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64TargetInfo : public BaseSPIRVTargetInfo { MacroBuilder &Builder) const override; }; -class LLVM_LIBRARY_VISIBILITY SPIRV64AMDGCNTargetInfo +class LLVM_LIBRARY_VISIBILITY SPIRV64AMDGCNTargetInfo final : public BaseSPIRVTargetInfo { public: SPIRV64AMDGCNTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) From 4698b5823beab373f48dfb2f6b78e1b3fb3c89c5 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Sun, 28 Apr 2024 16:45:07 +0100 Subject: [PATCH 06/15] Incorporate review suggestions. --- clang/lib/Basic/Targets.cpp | 1 - clang/lib/Basic/Targets/SPIR.cpp | 7 +++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index 04a13e3385d1f6..ca1e2229f19a90 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -676,7 +676,6 @@ std::unique_ptr AllocateTarget(const llvm::Triple &Triple, Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) { if (os == llvm::Triple::OSType::AMDHSA) return std::make_unique(Triple, Opts); - return nullptr; } return std::make_unique(Triple, Opts); diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp index e7936e39c7c986..ee74ae22e88229 100644 --- a/clang/lib/Basic/Targets/SPIR.cpp +++ b/clang/lib/Basic/Targets/SPIR.cpp @@ -57,10 +57,7 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions &Opts, DefineStd(Builder, "SPIRV64", Opts); } -namespace { -const AMDGPUTargetInfo AMDGPUTI(llvm::Triple("amdgcn-amd-amdhsa"), {}); - -} // anonymous namespace +static const AMDGPUTargetInfo AMDGPUTI(llvm::Triple("amdgcn-amd-amdhsa"), {}); ArrayRef SPIRV64AMDGCNTargetInfo::getGCCRegNames() const { return AMDGPUTI.getGCCRegNames(); @@ -99,6 +96,8 @@ void SPIRV64AMDGCNTargetInfo::getTargetDefines(const LangOptions &Opts, } void SPIRV64AMDGCNTargetInfo::setAuxTarget(const TargetInfo *Aux) { + assert(Aux && "Cannot invoke setAuxTarget without a valid auxiliary target!"); + // This is a 1:1 copy of AMDGPUTargetInfo::setAuxTarget() assert(HalfFormat == Aux->HalfFormat); assert(FloatFormat == Aux->FloatFormat); From aa1cd7cc3cd6144be64e7a5ddb50fdf07a991dc2 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Mon, 29 Apr 2024 00:43:43 +0100 Subject: [PATCH 07/15] Fix header ordering. --- clang/lib/Basic/Targets/SPIR.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Basic/Targets/SPIR.cpp b/clang/lib/Basic/Targets/SPIR.cpp index ee74ae22e88229..040303983594f8 100644 --- a/clang/lib/Basic/Targets/SPIR.cpp +++ b/clang/lib/Basic/Targets/SPIR.cpp @@ -10,8 +10,8 @@ // //===----------------------------------------------------------------------===// -#include "AMDGPU.h" #include "SPIR.h" +#include "AMDGPU.h" #include "Targets.h" #include "llvm/TargetParser/TargetParser.h" From 3307f17a2efa63c9bca5a47a502416b1fd508924 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Sun, 12 May 2024 03:59:20 +0300 Subject: [PATCH 08/15] Handle `wavefrontsize` (we need both 32 and 64); add more tests. --- .../CodeGenOpenCL/amdgcn-flat-scratch-name.cl | 7 +- .../CodeGenOpenCL/builtins-amdgcn-gfx10.cl | 13 +- .../CodeGenOpenCL/builtins-amdgcn-gfx11.cl | 13 +- .../test/CodeGenOpenCL/builtins-amdgcn-vi.cl | 55 ++-- clang/test/CodeGenOpenCL/builtins-amdgcn.cl | 294 ++++++++++-------- clang/test/CodeGenOpenCL/inline-asm-amdgcn.cl | 13 +- .../builtins-amdgcn-error-gfx908-param.cl | 1 + .../builtins-amdgcn-error-gfx90a-param.cl | 1 + .../builtins-amdgcn-error-gfx940-param.cl | 1 + llvm/lib/TargetParser/TargetParser.cpp | 2 + 10 files changed, 225 insertions(+), 175 deletions(-) diff --git a/clang/test/CodeGenOpenCL/amdgcn-flat-scratch-name.cl b/clang/test/CodeGenOpenCL/amdgcn-flat-scratch-name.cl index 619a9a99568e20..40a523f0aa0bfd 100644 --- a/clang/test/CodeGenOpenCL/amdgcn-flat-scratch-name.cl +++ b/clang/test/CodeGenOpenCL/amdgcn-flat-scratch-name.cl @@ -1,15 +1,16 @@ // REQUIRES: amdgpu-registered-target // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm -o - %s | FileCheck %s // CHECK-LABEL: @use_flat_scratch_name kernel void use_flat_scratch_name() { -// CHECK: tail call void asm sideeffect "s_mov_b64 flat_scratch, 0", "~{flat_scratch}"() +// CHECK: tail call{{.*}} void asm sideeffect "s_mov_b64 flat_scratch, 0", "~{flat_scratch}"() __asm__ volatile("s_mov_b64 flat_scratch, 0" : : : "flat_scratch"); -// CHECK: tail call void asm sideeffect "s_mov_b32 flat_scratch_lo, 0", "~{flat_scratch_lo}"() +// CHECK: tail call{{.*}} void asm sideeffect "s_mov_b32 flat_scratch_lo, 0", "~{flat_scratch_lo}"() __asm__ volatile("s_mov_b32 flat_scratch_lo, 0" : : : "flat_scratch_lo"); -// CHECK: tail call void asm sideeffect "s_mov_b32 flat_scratch_hi, 0", "~{flat_scratch_hi}"() +// CHECK: tail call{{.*}} void asm sideeffect "s_mov_b32 flat_scratch_hi, 0", "~{flat_scratch_hi}"() __asm__ volatile("s_mov_b32 flat_scratch_hi, 0" : : : "flat_scratch_hi"); } diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl index 3c40370e7f1076..f30776a8bb85b9 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl @@ -2,44 +2,45 @@ // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1010 -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1011 -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1012 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm -o - %s | FileCheck %s typedef unsigned int uint; typedef unsigned long ulong; // CHECK-LABEL: @test_permlane16( -// CHECK: call i32 @llvm.amdgcn.permlane16(i32 %a, i32 %b, i32 %c, i32 %d, i1 false, i1 false) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.permlane16(i32 %a, i32 %b, i32 %c, i32 %d, i1 false, i1 false) void test_permlane16(global uint* out, uint a, uint b, uint c, uint d) { *out = __builtin_amdgcn_permlane16(a, b, c, d, 0, 0); } // CHECK-LABEL: @test_permlanex16( -// CHECK: call i32 @llvm.amdgcn.permlanex16(i32 %a, i32 %b, i32 %c, i32 %d, i1 false, i1 false) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.permlanex16(i32 %a, i32 %b, i32 %c, i32 %d, i1 false, i1 false) void test_permlanex16(global uint* out, uint a, uint b, uint c, uint d) { *out = __builtin_amdgcn_permlanex16(a, b, c, d, 0, 0); } // CHECK-LABEL: @test_mov_dpp8( -// CHECK: call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %a, i32 1) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.mov.dpp8.i32(i32 %a, i32 1) void test_mov_dpp8(global uint* out, uint a) { *out = __builtin_amdgcn_mov_dpp8(a, 1); } // CHECK-LABEL: @test_s_memtime -// CHECK: call i64 @llvm.amdgcn.s.memtime() +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.s.memtime() void test_s_memtime(global ulong* out) { *out = __builtin_amdgcn_s_memtime(); } // CHECK-LABEL: @test_groupstaticsize -// CHECK: call i32 @llvm.amdgcn.groupstaticsize() +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.groupstaticsize() void test_groupstaticsize(global uint* out) { *out = __builtin_amdgcn_groupstaticsize(); } // CHECK-LABEL: @test_ballot_wave32( -// CHECK: call i32 @llvm.amdgcn.ballot.i32(i1 %{{.+}}) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.ballot.i32(i1 %{{.+}}) void test_ballot_wave32(global uint* out, int a, int b) { *out = __builtin_amdgcn_ballot_w32(a == b); diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl index d17ff81e5d43ca..4123ff6044a547 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl @@ -5,6 +5,7 @@ // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1103 -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1150 -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1151 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm -o - %s | FileCheck %s typedef unsigned int uint; typedef unsigned long ulong; @@ -12,19 +13,19 @@ typedef uint uint2 __attribute__((ext_vector_type(2))); typedef uint uint4 __attribute__((ext_vector_type(4))); // CHECK-LABEL: @test_s_sendmsg_rtn( -// CHECK: call i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32 0) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.s.sendmsg.rtn.i32(i32 0) void test_s_sendmsg_rtn(global uint* out) { *out = __builtin_amdgcn_s_sendmsg_rtn(0); } // CHECK-LABEL: @test_s_sendmsg_rtnl( -// CHECK: call i64 @llvm.amdgcn.s.sendmsg.rtn.i64(i32 0) +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.s.sendmsg.rtn.i64(i32 0) void test_s_sendmsg_rtnl(global ulong* out) { *out = __builtin_amdgcn_s_sendmsg_rtnl(0); } // CHECK-LABEL: @test_ds_bvh_stack_rtn( -// CHECK: %0 = tail call { i32, i32 } @llvm.amdgcn.ds.bvh.stack.rtn(i32 %addr, i32 %data, <4 x i32> %data1, i32 128) +// CHECK: %0 = tail call{{.*}} { i32, i32 } @llvm.amdgcn.ds.bvh.stack.rtn(i32 %addr, i32 %data, <4 x i32> %data1, i32 128) // CHECK: %1 = extractvalue { i32, i32 } %0, 0 // CHECK: %2 = extractvalue { i32, i32 } %0, 1 // CHECK: %3 = insertelement <2 x i32> poison, i32 %1, i64 0 @@ -35,19 +36,19 @@ void test_ds_bvh_stack_rtn(global uint2* out, uint addr, uint data, uint4 data1) } // CHECK-LABEL: @test_permlane64( -// CHECK: call i32 @llvm.amdgcn.permlane64(i32 %a) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.permlane64(i32 %a) void test_permlane64(global uint* out, uint a) { *out = __builtin_amdgcn_permlane64(a); } // CHECK-LABEL: @test_s_wait_event_export_ready -// CHECK: call void @llvm.amdgcn.s.wait.event.export.ready +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.wait.event.export.ready void test_s_wait_event_export_ready() { __builtin_amdgcn_s_wait_event_export_ready(); } // CHECK-LABEL: @test_global_add_f32 -// CHECK: call float @llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1) %{{.*}}, float %{{.*}}) +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptr addrspace(1) %{{.*}}, float %{{.*}}) void test_global_add_f32(float *rtn, global float *addr, float x) { *rtn = __builtin_amdgcn_global_atomic_fadd_f32(addr, x); } diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl index d135d33d7dec6e..ea2aedf8d44a52 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl @@ -3,6 +3,7 @@ // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx900 -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1010 -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1012 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm -o - %s | FileCheck %s #pragma OPENCL EXTENSION cl_khr_fp16 : enable @@ -10,42 +11,42 @@ typedef unsigned long ulong; typedef unsigned int uint; // CHECK-LABEL: @test_div_fixup_f16 -// CHECK: call half @llvm.amdgcn.div.fixup.f16 +// CHECK: {{.*}}call{{.*}} half @llvm.amdgcn.div.fixup.f16 void test_div_fixup_f16(global half* out, half a, half b, half c) { *out = __builtin_amdgcn_div_fixuph(a, b, c); } // CHECK-LABEL: @test_rcp_f16 -// CHECK: call half @llvm.amdgcn.rcp.f16 +// CHECK: {{.*}}call{{.*}} half @llvm.amdgcn.rcp.f16 void test_rcp_f16(global half* out, half a) { *out = __builtin_amdgcn_rcph(a); } // CHECK-LABEL: @test_sqrt_f16 -// CHECK: call half @llvm.sqrt.f16 +// CHECK: {{.*}}call{{.*}} half @llvm.{{((amdgcn.){0,1})}}sqrt.f16 void test_sqrt_f16(global half* out, half a) { *out = __builtin_amdgcn_sqrth(a); } // CHECK-LABEL: @test_rsq_f16 -// CHECK: call half @llvm.amdgcn.rsq.f16 +// CHECK: {{.*}}call{{.*}} half @llvm.amdgcn.rsq.f16 void test_rsq_f16(global half* out, half a) { *out = __builtin_amdgcn_rsqh(a); } // CHECK-LABEL: @test_sin_f16 -// CHECK: call half @llvm.amdgcn.sin.f16 +// CHECK: {{.*}}call{{.*}} half @llvm.amdgcn.sin.f16 void test_sin_f16(global half* out, half a) { *out = __builtin_amdgcn_sinh(a); } // CHECK-LABEL: @test_cos_f16 -// CHECK: call half @llvm.amdgcn.cos.f16 +// CHECK: {{.*}}call{{.*}} half @llvm.amdgcn.cos.f16 void test_cos_f16(global half* out, half a) { *out = __builtin_amdgcn_cosh(a); @@ -53,102 +54,114 @@ void test_cos_f16(global half* out, half a) // CHECK-LABEL: @test_ldexp_f16 // CHECK: [[TRUNC:%[0-9a-z]+]] = trunc i32 -// CHECK: call half @llvm.ldexp.f16.i16(half %a, i16 [[TRUNC]]) +// CHECK: {{.*}}call{{.*}} half @llvm.ldexp.f16.i16(half %a, i16 [[TRUNC]]) void test_ldexp_f16(global half* out, half a, int b) { *out = __builtin_amdgcn_ldexph(a, b); } // CHECK-LABEL: @test_frexp_mant_f16 -// CHECK: call half @llvm.amdgcn.frexp.mant.f16 +// CHECK: {{.*}}call{{.*}} half @llvm.amdgcn.frexp.mant.f16 void test_frexp_mant_f16(global half* out, half a) { *out = __builtin_amdgcn_frexp_manth(a); } // CHECK-LABEL: @test_frexp_exp_f16 -// CHECK: call i16 @llvm.amdgcn.frexp.exp.i16.f16 +// CHECK: {{.*}}call{{.*}} i16 @llvm.amdgcn.frexp.exp.i16.f16 void test_frexp_exp_f16(global short* out, half a) { *out = __builtin_amdgcn_frexp_exph(a); } // CHECK-LABEL: @test_fract_f16 -// CHECK: call half @llvm.amdgcn.fract.f16 +// CHECK: {{.*}}call{{.*}} half @llvm.amdgcn.fract.f16 void test_fract_f16(global half* out, half a) { *out = __builtin_amdgcn_fracth(a); } // CHECK-LABEL: @test_class_f16 -// CHECK: call i1 @llvm.amdgcn.class.f16 +// CHECK: {{.*}}call{{.*}} i1 @llvm.amdgcn.class.f16 void test_class_f16(global half* out, half a, int b) { *out = __builtin_amdgcn_classh(a, b); } // CHECK-LABEL: @test_s_memrealtime -// CHECK: call i64 @llvm.amdgcn.s.memrealtime() +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.s.memrealtime() void test_s_memrealtime(global ulong* out) { *out = __builtin_amdgcn_s_memrealtime(); } // CHECK-LABEL: @test_s_dcache_wb() -// CHECK: call void @llvm.amdgcn.s.dcache.wb() +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.dcache.wb() void test_s_dcache_wb() { __builtin_amdgcn_s_dcache_wb(); } // CHECK-LABEL: @test_mov_dpp -// CHECK: call i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32 %src, i32 0, i32 0, i32 0, i1 false) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32 %src, i32 0, i32 0, i32 0, i1 false) void test_mov_dpp(global int* out, int src) { *out = __builtin_amdgcn_mov_dpp(src, 0, 0, 0, false); } // CHECK-LABEL: @test_update_dpp -// CHECK: call i32 @llvm.amdgcn.update.dpp.i32(i32 %arg1, i32 %arg2, i32 0, i32 0, i32 0, i1 false) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.update.dpp.i32(i32 %arg1, i32 %arg2, i32 0, i32 0, i32 0, i1 false) void test_update_dpp(global int* out, int arg1, int arg2) { *out = __builtin_amdgcn_update_dpp(arg1, arg2, 0, 0, 0, false); } // CHECK-LABEL: @test_ds_fadd -// CHECK: call float @llvm.amdgcn.ds.fadd.f32(ptr addrspace(3) %out, float %src, i32 0, i32 0, i1 false) +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.ds.fadd.f32(ptr addrspace(3) %out, float %src, i32 0, i32 0, i1 false) +#if !defined(__SPIRV__) void test_ds_faddf(local float *out, float src) { +#else +void test_ds_faddf(__attribute__((address_space(3))) float *out, float src) { +#endif *out = __builtin_amdgcn_ds_faddf(out, src, 0, 0, false); } // CHECK-LABEL: @test_ds_fmin -// CHECK: call float @llvm.amdgcn.ds.fmin.f32(ptr addrspace(3) %out, float %src, i32 0, i32 0, i1 false) +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.ds.fmin.f32(ptr addrspace(3) %out, float %src, i32 0, i32 0, i1 false) +#if !defined(__SPIRV__) void test_ds_fminf(local float *out, float src) { +#else +void test_ds_fminf(__attribute__((address_space(3))) float *out, float src) { +#endif *out = __builtin_amdgcn_ds_fminf(out, src, 0, 0, false); } // CHECK-LABEL: @test_ds_fmax -// CHECK: call float @llvm.amdgcn.ds.fmax.f32(ptr addrspace(3) %out, float %src, i32 0, i32 0, i1 false) +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.ds.fmax.f32(ptr addrspace(3) %out, float %src, i32 0, i32 0, i1 false) +#if !defined(__SPIRV__) void test_ds_fmaxf(local float *out, float src) { +#else +void test_ds_fmaxf(__attribute__((address_space(3))) float *out, float src) { +#endif *out = __builtin_amdgcn_ds_fmaxf(out, src, 0, 0, false); } // CHECK-LABEL: @test_s_memtime -// CHECK: call i64 @llvm.amdgcn.s.memtime() +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.s.memtime() void test_s_memtime(global ulong* out) { *out = __builtin_amdgcn_s_memtime(); } // CHECK-LABEL: @test_perm -// CHECK: call i32 @llvm.amdgcn.perm(i32 %a, i32 %b, i32 %s) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.perm(i32 %a, i32 %b, i32 %s) void test_perm(global uint* out, uint a, uint b, uint s) { *out = __builtin_amdgcn_perm(a, b, s); } // CHECK-LABEL: @test_groupstaticsize -// CHECK: call i32 @llvm.amdgcn.groupstaticsize() +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.groupstaticsize() void test_groupstaticsize(global uint* out) { *out = __builtin_amdgcn_groupstaticsize(); diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl index c2ef9ea947e93c..ffc190b76db98b 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl @@ -1,5 +1,7 @@ // REQUIRES: amdgpu-registered-target -// RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown -target-cpu tahiti -emit-llvm -o - %s | FileCheck -enable-var-scope %s +// RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown -target-cpu tahiti -emit-llvm -o - %s | FileCheck -enable-var-scope --check-prefixes=CHECK-AMDGCN,CHECK %s +// RUN: %clang_cc1 -cl-std=CL2.0 -triple spirv64-amd-amdhsa -emit-llvm -o - %s | FileCheck -enable-var-scope --check-prefix=CHECK %s + #pragma OPENCL EXTENSION cl_khr_fp64 : enable @@ -12,7 +14,7 @@ typedef ushort __attribute__((ext_vector_type(2))) ushort2; typedef uint __attribute__((ext_vector_type(4))) uint4; // CHECK-LABEL: @test_div_scale_f64 -// CHECK: call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) +// CHECK: {{.*}}call{{.*}} { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) // CHECK-DAG: [[FLAG:%.+]] = extractvalue { double, i1 } %{{.+}}, 1 // CHECK-DAG: [[VAL:%.+]] = extractvalue { double, i1 } %{{.+}}, 0 // CHECK: [[FLAGEXT:%.+]] = zext i1 [[FLAG]] to i32 @@ -25,7 +27,7 @@ void test_div_scale_f64(global double* out, global int* flagout, double a, doubl } // CHECK-LABEL: @test_div_scale_f32( -// CHECK: call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) +// CHECK: {{.*}}call{{.*}} { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) // CHECK-DAG: [[FLAG:%.+]] = extractvalue { float, i1 } %{{.+}}, 1 // CHECK-DAG: [[VAL:%.+]] = extractvalue { float, i1 } %{{.+}}, 0 // CHECK: [[FLAGEXT:%.+]] = zext i1 [[FLAG]] to i8 @@ -38,7 +40,7 @@ void test_div_scale_f32(global float* out, global bool* flagout, float a, float } // CHECK-LABEL: @test_div_scale_f32_global_ptr( -// CHECK: call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) +// CHECK: {{.*}}call{{.*}} { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) // CHECK-DAG: [[FLAG:%.+]] = extractvalue { float, i1 } %{{.+}}, 1 // CHECK-DAG: [[VAL:%.+]] = extractvalue { float, i1 } %{{.+}}, 0 // CHECK: [[FLAGEXT:%.+]] = zext i1 [[FLAG]] to i8 @@ -49,7 +51,7 @@ void test_div_scale_f32_global_ptr(global float* out, global int* flagout, float } // CHECK-LABEL: @test_div_scale_f32_generic_ptr( -// CHECK: call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) +// CHECK: {{.*}}call{{.*}} { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) // CHECK-DAG: [[FLAG:%.+]] = extractvalue { float, i1 } %{{.+}}, 1 // CHECK-DAG: [[VAL:%.+]] = extractvalue { float, i1 } %{{.+}}, 0 // CHECK: [[FLAGEXT:%.+]] = zext i1 [[FLAG]] to i8 @@ -61,360 +63,360 @@ void test_div_scale_f32_generic_ptr(global float* out, global int* flagout, floa } // CHECK-LABEL: @test_div_fmas_f32 -// CHECK: call float @llvm.amdgcn.div.fmas.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.div.fmas.f32 void test_div_fmas_f32(global float* out, float a, float b, float c, int d) { *out = __builtin_amdgcn_div_fmasf(a, b, c, d); } // CHECK-LABEL: @test_div_fmas_f64 -// CHECK: call double @llvm.amdgcn.div.fmas.f64 +// CHECK: {{.*}}call{{.*}} double @llvm.amdgcn.div.fmas.f64 void test_div_fmas_f64(global double* out, double a, double b, double c, int d) { *out = __builtin_amdgcn_div_fmas(a, b, c, d); } // CHECK-LABEL: @test_div_fixup_f32 -// CHECK: call float @llvm.amdgcn.div.fixup.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.div.fixup.f32 void test_div_fixup_f32(global float* out, float a, float b, float c) { *out = __builtin_amdgcn_div_fixupf(a, b, c); } // CHECK-LABEL: @test_div_fixup_f64 -// CHECK: call double @llvm.amdgcn.div.fixup.f64 +// CHECK: {{.*}}call{{.*}} double @llvm.amdgcn.div.fixup.f64 void test_div_fixup_f64(global double* out, double a, double b, double c) { *out = __builtin_amdgcn_div_fixup(a, b, c); } // CHECK-LABEL: @test_trig_preop_f32 -// CHECK: call float @llvm.amdgcn.trig.preop.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.trig.preop.f32 void test_trig_preop_f32(global float* out, float a, int b) { *out = __builtin_amdgcn_trig_preopf(a, b); } // CHECK-LABEL: @test_trig_preop_f64 -// CHECK: call double @llvm.amdgcn.trig.preop.f64 +// CHECK: {{.*}}call{{.*}} double @llvm.amdgcn.trig.preop.f64 void test_trig_preop_f64(global double* out, double a, int b) { *out = __builtin_amdgcn_trig_preop(a, b); } // CHECK-LABEL: @test_rcp_f32 -// CHECK: call float @llvm.amdgcn.rcp.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.rcp.f32 void test_rcp_f32(global float* out, float a) { *out = __builtin_amdgcn_rcpf(a); } // CHECK-LABEL: @test_rcp_f64 -// CHECK: call double @llvm.amdgcn.rcp.f64 +// CHECK: {{.*}}call{{.*}} double @llvm.amdgcn.rcp.f64 void test_rcp_f64(global double* out, double a) { *out = __builtin_amdgcn_rcp(a); } // CHECK-LABEL: @test_sqrt_f32 -// CHECK: call float @llvm.amdgcn.sqrt.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.{{((amdgcn.){0,1})}}sqrt.f32 void test_sqrt_f32(global float* out, float a) { *out = __builtin_amdgcn_sqrtf(a); } // CHECK-LABEL: @test_sqrt_f64 -// CHECK: call double @llvm.amdgcn.sqrt.f64 +// CHECK: {{.*}}call{{.*}} double @llvm.amdgcn.sqrt.f64 void test_sqrt_f64(global double* out, double a) { *out = __builtin_amdgcn_sqrt(a); } // CHECK-LABEL: @test_rsq_f32 -// CHECK: call float @llvm.amdgcn.rsq.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.rsq.f32 void test_rsq_f32(global float* out, float a) { *out = __builtin_amdgcn_rsqf(a); } // CHECK-LABEL: @test_rsq_f64 -// CHECK: call double @llvm.amdgcn.rsq.f64 +// CHECK: {{.*}}call{{.*}} double @llvm.amdgcn.rsq.f64 void test_rsq_f64(global double* out, double a) { *out = __builtin_amdgcn_rsq(a); } // CHECK-LABEL: @test_rsq_clamp_f32 -// CHECK: call float @llvm.amdgcn.rsq.clamp.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.rsq.clamp.f32 void test_rsq_clamp_f32(global float* out, float a) { *out = __builtin_amdgcn_rsq_clampf(a); } // CHECK-LABEL: @test_rsq_clamp_f64 -// CHECK: call double @llvm.amdgcn.rsq.clamp.f64 +// CHECK: {{.*}}call{{.*}} double @llvm.amdgcn.rsq.clamp.f64 void test_rsq_clamp_f64(global double* out, double a) { *out = __builtin_amdgcn_rsq_clamp(a); } // CHECK-LABEL: @test_sin_f32 -// CHECK: call float @llvm.amdgcn.sin.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.sin.f32 void test_sin_f32(global float* out, float a) { *out = __builtin_amdgcn_sinf(a); } // CHECK-LABEL: @test_cos_f32 -// CHECK: call float @llvm.amdgcn.cos.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.cos.f32 void test_cos_f32(global float* out, float a) { *out = __builtin_amdgcn_cosf(a); } // CHECK-LABEL: @test_log_f32 -// CHECK: call float @llvm.amdgcn.log.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.log.f32 void test_log_f32(global float* out, float a) { *out = __builtin_amdgcn_logf(a); } // CHECK-LABEL: @test_exp2_f32 -// CHECK: call float @llvm.amdgcn.exp2.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.exp2.f32 void test_exp2_f32(global float* out, float a) { *out = __builtin_amdgcn_exp2f(a); } // CHECK-LABEL: @test_log_clamp_f32 -// CHECK: call float @llvm.amdgcn.log.clamp.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.log.clamp.f32 void test_log_clamp_f32(global float* out, float a) { *out = __builtin_amdgcn_log_clampf(a); } // CHECK-LABEL: @test_ldexp_f32 -// CHECK: call float @llvm.ldexp.f32.i32 +// CHECK: {{.*}}call{{.*}} float @llvm.ldexp.f32.i32 void test_ldexp_f32(global float* out, float a, int b) { *out = __builtin_amdgcn_ldexpf(a, b); } // CHECK-LABEL: @test_ldexp_f64 -// CHECK: call double @llvm.ldexp.f64.i32 +// CHECK: {{.*}}call{{.*}} double @llvm.ldexp.f64.i32 void test_ldexp_f64(global double* out, double a, int b) { *out = __builtin_amdgcn_ldexp(a, b); } // CHECK-LABEL: @test_frexp_mant_f32 -// CHECK: call float @llvm.amdgcn.frexp.mant.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.frexp.mant.f32 void test_frexp_mant_f32(global float* out, float a) { *out = __builtin_amdgcn_frexp_mantf(a); } // CHECK-LABEL: @test_frexp_mant_f64 -// CHECK: call double @llvm.amdgcn.frexp.mant.f64 +// CHECK: {{.*}}call{{.*}} double @llvm.amdgcn.frexp.mant.f64 void test_frexp_mant_f64(global double* out, double a) { *out = __builtin_amdgcn_frexp_mant(a); } // CHECK-LABEL: @test_frexp_exp_f32 -// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f32 +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.frexp.exp.i32.f32 void test_frexp_exp_f32(global int* out, float a) { *out = __builtin_amdgcn_frexp_expf(a); } // CHECK-LABEL: @test_frexp_exp_f64 -// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f64 +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.frexp.exp.i32.f64 void test_frexp_exp_f64(global int* out, double a) { *out = __builtin_amdgcn_frexp_exp(a); } // CHECK-LABEL: @test_fract_f32 -// CHECK: call float @llvm.amdgcn.fract.f32 +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.fract.f32 void test_fract_f32(global int* out, float a) { *out = __builtin_amdgcn_fractf(a); } // CHECK-LABEL: @test_fract_f64 -// CHECK: call double @llvm.amdgcn.fract.f64 +// CHECK: {{.*}}call{{.*}} double @llvm.amdgcn.fract.f64 void test_fract_f64(global int* out, double a) { *out = __builtin_amdgcn_fract(a); } // CHECK-LABEL: @test_lerp -// CHECK: call i32 @llvm.amdgcn.lerp +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.lerp void test_lerp(global int* out, int a, int b, int c) { *out = __builtin_amdgcn_lerp(a, b, c); } // CHECK-LABEL: @test_sicmp_i32 -// CHECK: call i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 32) +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 32) void test_sicmp_i32(global ulong* out, int a, int b) { *out = __builtin_amdgcn_sicmp(a, b, 32); } // CHECK-LABEL: @test_uicmp_i32 -// CHECK: call i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 32) +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 32) void test_uicmp_i32(global ulong* out, uint a, uint b) { *out = __builtin_amdgcn_uicmp(a, b, 32); } // CHECK-LABEL: @test_sicmp_i64 -// CHECK: call i64 @llvm.amdgcn.icmp.i64.i64(i64 %a, i64 %b, i32 38) +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.icmp.i64.i64(i64 %a, i64 %b, i32 38) void test_sicmp_i64(global ulong* out, long a, long b) { *out = __builtin_amdgcn_sicmpl(a, b, 39-1); } // CHECK-LABEL: @test_uicmp_i64 -// CHECK: call i64 @llvm.amdgcn.icmp.i64.i64(i64 %a, i64 %b, i32 35) +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.icmp.i64.i64(i64 %a, i64 %b, i32 35) void test_uicmp_i64(global ulong* out, ulong a, ulong b) { *out = __builtin_amdgcn_uicmpl(a, b, 30+5); } // CHECK-LABEL: @test_ds_swizzle -// CHECK: call i32 @llvm.amdgcn.ds.swizzle(i32 %a, i32 32) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.ds.swizzle(i32 %a, i32 32) void test_ds_swizzle(global int* out, int a) { *out = __builtin_amdgcn_ds_swizzle(a, 32); } // CHECK-LABEL: @test_ds_permute -// CHECK: call i32 @llvm.amdgcn.ds.permute(i32 %a, i32 %b) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.ds.permute(i32 %a, i32 %b) void test_ds_permute(global int* out, int a, int b) { out[0] = __builtin_amdgcn_ds_permute(a, b); } // CHECK-LABEL: @test_ds_bpermute -// CHECK: call i32 @llvm.amdgcn.ds.bpermute(i32 %a, i32 %b) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.ds.bpermute(i32 %a, i32 %b) void test_ds_bpermute(global int* out, int a, int b) { *out = __builtin_amdgcn_ds_bpermute(a, b); } // CHECK-LABEL: @test_readfirstlane -// CHECK: call i32 @llvm.amdgcn.readfirstlane(i32 %a) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.readfirstlane(i32 %a) void test_readfirstlane(global int* out, int a) { *out = __builtin_amdgcn_readfirstlane(a); } // CHECK-LABEL: @test_readlane -// CHECK: call i32 @llvm.amdgcn.readlane(i32 %a, i32 %b) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.readlane(i32 %a, i32 %b) void test_readlane(global int* out, int a, int b) { *out = __builtin_amdgcn_readlane(a, b); } // CHECK-LABEL: @test_fcmp_f32 -// CHECK: call i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 5) +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 5) void test_fcmp_f32(global ulong* out, float a, float b) { *out = __builtin_amdgcn_fcmpf(a, b, 5); } // CHECK-LABEL: @test_fcmp_f64 -// CHECK: call i64 @llvm.amdgcn.fcmp.i64.f64(double %a, double %b, i32 6) +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.fcmp.i64.f64(double %a, double %b, i32 6) void test_fcmp_f64(global ulong* out, double a, double b) { *out = __builtin_amdgcn_fcmp(a, b, 3+3); } // CHECK-LABEL: @test_class_f32 -// CHECK: call i1 @llvm.amdgcn.class.f32 +// CHECK: {{.*}}call{{.*}} i1 @llvm.amdgcn.class.f32 void test_class_f32(global float* out, float a, int b) { *out = __builtin_amdgcn_classf(a, b); } // CHECK-LABEL: @test_class_f64 -// CHECK: call i1 @llvm.amdgcn.class.f64 +// CHECK: {{.*}}call{{.*}} i1 @llvm.amdgcn.class.f64 void test_class_f64(global double* out, double a, int b) { *out = __builtin_amdgcn_class(a, b); } // CHECK-LABEL: @test_buffer_wbinvl1 -// CHECK: call void @llvm.amdgcn.buffer.wbinvl1( +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.buffer.wbinvl1( void test_buffer_wbinvl1() { __builtin_amdgcn_buffer_wbinvl1(); } // CHECK-LABEL: @test_s_dcache_inv -// CHECK: call void @llvm.amdgcn.s.dcache.inv( +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.dcache.inv( void test_s_dcache_inv() { __builtin_amdgcn_s_dcache_inv(); } // CHECK-LABEL: @test_s_waitcnt -// CHECK: call void @llvm.amdgcn.s.waitcnt( +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.waitcnt( void test_s_waitcnt() { __builtin_amdgcn_s_waitcnt(0); } // CHECK-LABEL: @test_s_sendmsg -// CHECK: call void @llvm.amdgcn.s.sendmsg( +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.sendmsg( void test_s_sendmsg() { __builtin_amdgcn_s_sendmsg(1, 0); } // CHECK-LABEL: @test_s_sendmsg_var -// CHECK: call void @llvm.amdgcn.s.sendmsg( +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.sendmsg( void test_s_sendmsg_var(int in) { __builtin_amdgcn_s_sendmsg(1, in); } // CHECK-LABEL: @test_s_sendmsghalt -// CHECK: call void @llvm.amdgcn.s.sendmsghalt( +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.sendmsghalt( void test_s_sendmsghalt() { __builtin_amdgcn_s_sendmsghalt(1, 0); } // CHECK-LABEL: @test_s_sendmsghalt -// CHECK: call void @llvm.amdgcn.s.sendmsghalt( +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.sendmsghalt( void test_s_sendmsghalt_var(int in) { __builtin_amdgcn_s_sendmsghalt(1, in); } // CHECK-LABEL: @test_s_barrier -// CHECK: call void @llvm.amdgcn.s.barrier( +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.barrier( void test_s_barrier() { __builtin_amdgcn_s_barrier(); } // CHECK-LABEL: @test_wave_barrier -// CHECK: call void @llvm.amdgcn.wave.barrier( +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.wave.barrier( void test_wave_barrier() { __builtin_amdgcn_wave_barrier(); } // CHECK-LABEL: @test_sched_barrier -// CHECK: call void @llvm.amdgcn.sched.barrier(i32 0) -// CHECK: call void @llvm.amdgcn.sched.barrier(i32 1) -// CHECK: call void @llvm.amdgcn.sched.barrier(i32 4) -// CHECK: call void @llvm.amdgcn.sched.barrier(i32 15) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.sched.barrier(i32 0) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.sched.barrier(i32 1) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.sched.barrier(i32 4) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.sched.barrier(i32 15) void test_sched_barrier() { __builtin_amdgcn_sched_barrier(0); @@ -424,10 +426,10 @@ void test_sched_barrier() } // CHECK-LABEL: @test_sched_group_barrier -// CHECK: call void @llvm.amdgcn.sched.group.barrier(i32 0, i32 1, i32 2) -// CHECK: call void @llvm.amdgcn.sched.group.barrier(i32 1, i32 2, i32 4) -// CHECK: call void @llvm.amdgcn.sched.group.barrier(i32 4, i32 8, i32 16) -// CHECK: call void @llvm.amdgcn.sched.group.barrier(i32 15, i32 10000, i32 -1) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.sched.group.barrier(i32 0, i32 1, i32 2) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.sched.group.barrier(i32 1, i32 2, i32 4) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.sched.group.barrier(i32 4, i32 8, i32 16) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.sched.group.barrier(i32 15, i32 10000, i32 -1) void test_sched_group_barrier() { __builtin_amdgcn_sched_group_barrier(0, 1, 2); @@ -437,10 +439,10 @@ void test_sched_group_barrier() } // CHECK-LABEL: @test_iglp_opt -// CHECK: call void @llvm.amdgcn.iglp.opt(i32 0) -// CHECK: call void @llvm.amdgcn.iglp.opt(i32 1) -// CHECK: call void @llvm.amdgcn.iglp.opt(i32 4) -// CHECK: call void @llvm.amdgcn.iglp.opt(i32 15) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.iglp.opt(i32 0) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.iglp.opt(i32 1) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.iglp.opt(i32 4) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.iglp.opt(i32 15) void test_iglp_opt() { __builtin_amdgcn_iglp_opt(0); @@ -450,8 +452,8 @@ void test_iglp_opt() } // CHECK-LABEL: @test_s_sleep -// CHECK: call void @llvm.amdgcn.s.sleep(i32 1) -// CHECK: call void @llvm.amdgcn.s.sleep(i32 15) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.sleep(i32 1) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.sleep(i32 15) void test_s_sleep() { __builtin_amdgcn_s_sleep(1); @@ -459,8 +461,8 @@ void test_s_sleep() } // CHECK-LABEL: @test_s_incperflevel -// CHECK: call void @llvm.amdgcn.s.incperflevel(i32 1) -// CHECK: call void @llvm.amdgcn.s.incperflevel(i32 15) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.incperflevel(i32 1) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.incperflevel(i32 15) void test_s_incperflevel() { __builtin_amdgcn_s_incperflevel(1); @@ -468,8 +470,8 @@ void test_s_incperflevel() } // CHECK-LABEL: @test_s_decperflevel -// CHECK: call void @llvm.amdgcn.s.decperflevel(i32 1) -// CHECK: call void @llvm.amdgcn.s.decperflevel(i32 15) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.decperflevel(i32 1) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.decperflevel(i32 15) void test_s_decperflevel() { __builtin_amdgcn_s_decperflevel(1); @@ -477,8 +479,8 @@ void test_s_decperflevel() } // CHECK-LABEL: @test_s_setprio -// CHECK: call void @llvm.amdgcn.s.setprio(i16 0) -// CHECK: call void @llvm.amdgcn.s.setprio(i16 3) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.setprio(i16 0) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.setprio(i16 3) void test_s_setprio() { __builtin_amdgcn_s_setprio(0); @@ -486,47 +488,47 @@ void test_s_setprio() } // CHECK-LABEL: @test_cubeid( -// CHECK: call float @llvm.amdgcn.cubeid(float %a, float %b, float %c) +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.cubeid(float %a, float %b, float %c) void test_cubeid(global float* out, float a, float b, float c) { *out = __builtin_amdgcn_cubeid(a, b, c); } // CHECK-LABEL: @test_cubesc( -// CHECK: call float @llvm.amdgcn.cubesc(float %a, float %b, float %c) +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.cubesc(float %a, float %b, float %c) void test_cubesc(global float* out, float a, float b, float c) { *out = __builtin_amdgcn_cubesc(a, b, c); } // CHECK-LABEL: @test_cubetc( -// CHECK: call float @llvm.amdgcn.cubetc(float %a, float %b, float %c) +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.cubetc(float %a, float %b, float %c) void test_cubetc(global float* out, float a, float b, float c) { *out = __builtin_amdgcn_cubetc(a, b, c); } // CHECK-LABEL: @test_cubema( -// CHECK: call float @llvm.amdgcn.cubema(float %a, float %b, float %c) +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.cubema(float %a, float %b, float %c) void test_cubema(global float* out, float a, float b, float c) { *out = __builtin_amdgcn_cubema(a, b, c); } // CHECK-LABEL: @test_read_exec( -// CHECK: call i64 @llvm.amdgcn.ballot.i64(i1 true) +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.ballot.i64(i1 true) void test_read_exec(global ulong* out) { *out = __builtin_amdgcn_read_exec(); } -// CHECK: declare i64 @llvm.amdgcn.ballot.i64(i1) #[[$NOUNWIND_READONLY:[0-9]+]] +// CHECK: declare i64 @llvm.amdgcn.ballot.i64(i1){{.*}} #[[$NOUNWIND_READONLY:[0-9]+]] // CHECK-LABEL: @test_read_exec_lo( -// CHECK: call i32 @llvm.amdgcn.ballot.i32(i1 true) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.ballot.i32(i1 true) void test_read_exec_lo(global uint* out) { *out = __builtin_amdgcn_read_exec_lo(); } -// CHECK: declare i32 @llvm.amdgcn.ballot.i32(i1) #[[$NOUNWIND_READONLY:[0-9]+]] +// CHECK: declare i32 @llvm.amdgcn.ballot.i32(i1){{.*}} #[[$NOUNWIND_READONLY:[0-9]+]] // CHECK-LABEL: @test_read_exec_hi( -// CHECK: call i64 @llvm.amdgcn.ballot.i64(i1 true) +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.ballot.i64(i1 true) // CHECK: lshr i64 [[A:%.*]], 32 // CHECK: trunc nuw i64 [[B:%.*]] to i32 void test_read_exec_hi(global uint* out) { @@ -534,37 +536,53 @@ void test_read_exec_hi(global uint* out) { } // CHECK-LABEL: @test_dispatch_ptr -// CHECK: call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() +// CHECK: {{.*}}call align 4 dereferenceable(64){{.*}} ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() +#if !defined(__SPIRV__) void test_dispatch_ptr(__constant unsigned char ** out) +#else +void test_dispatch_ptr(__attribute__((address_space(4))) unsigned char ** out) +#endif { *out = __builtin_amdgcn_dispatch_ptr(); } // CHECK-LABEL: @test_queue_ptr -// CHECK: call ptr addrspace(4) @llvm.amdgcn.queue.ptr() +// CHECK: {{.*}}call{{.*}} ptr addrspace(4) @llvm.amdgcn.queue.ptr() +#if !defined(__SPIRV__) void test_queue_ptr(__constant unsigned char ** out) +#else +void test_queue_ptr(__attribute__((address_space(4))) unsigned char ** out) +#endif { *out = __builtin_amdgcn_queue_ptr(); } // CHECK-LABEL: @test_kernarg_segment_ptr -// CHECK: call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() +// CHECK: {{.*}}call{{.*}} ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() +#if !defined(__SPIRV__) void test_kernarg_segment_ptr(__constant unsigned char ** out) +#else +void test_kernarg_segment_ptr(__attribute__((address_space(4))) unsigned char ** out) +#endif { *out = __builtin_amdgcn_kernarg_segment_ptr(); } // CHECK-LABEL: @test_implicitarg_ptr -// CHECK: call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() +// CHECK: {{.*}}call{{.*}} ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() +#if !defined(__SPIRV__) void test_implicitarg_ptr(__constant unsigned char ** out) +#else +void test_implicitarg_ptr(__attribute__((address_space(4))) unsigned char ** out) +#endif { *out = __builtin_amdgcn_implicitarg_ptr(); } // CHECK-LABEL: @test_get_group_id( -// CHECK: tail call i32 @llvm.amdgcn.workgroup.id.x() -// CHECK: tail call i32 @llvm.amdgcn.workgroup.id.y() -// CHECK: tail call i32 @llvm.amdgcn.workgroup.id.z() +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.workgroup.id.x() +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.workgroup.id.y() +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.workgroup.id.z() void test_get_group_id(int d, global int *out) { switch (d) { @@ -576,9 +594,9 @@ void test_get_group_id(int d, global int *out) } // CHECK-LABEL: @test_s_getreg( -// CHECK: tail call i32 @llvm.amdgcn.s.getreg(i32 0) -// CHECK: tail call i32 @llvm.amdgcn.s.getreg(i32 1) -// CHECK: tail call i32 @llvm.amdgcn.s.getreg(i32 65535) +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.s.getreg(i32 0) +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.s.getreg(i32 1) +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.s.getreg(i32 65535) void test_s_getreg(volatile global uint *out) { *out = __builtin_amdgcn_s_getreg(0); @@ -587,9 +605,9 @@ void test_s_getreg(volatile global uint *out) } // CHECK-LABEL: @test_get_local_id( -// CHECK: tail call i32 @llvm.amdgcn.workitem.id.x(), !range [[$WI_RANGE:![0-9]*]], !noundef -// CHECK: tail call i32 @llvm.amdgcn.workitem.id.y(), !range [[$WI_RANGE]], !noundef -// CHECK: tail call i32 @llvm.amdgcn.workitem.id.z(), !range [[$WI_RANGE]], !noundef +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.workitem.id.x(), !range [[$WI_RANGE:![0-9]*]], !noundef +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.workitem.id.y(), !range [[$WI_RANGE]], !noundef +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.workitem.id.z(), !range [[$WI_RANGE]], !noundef void test_get_local_id(int d, global int *out) { switch (d) { @@ -601,7 +619,7 @@ void test_get_local_id(int d, global int *out) } // CHECK-LABEL: @test_get_workgroup_size( -// CHECK: call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() +// CHECK: {{.*}}call align 8 dereferenceable(256){{.*}} ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() // CHECK: getelementptr inbounds i8, ptr addrspace(4) %{{.*}}, i64 12 // CHECK: load i16, ptr addrspace(4) %{{.*}}, align 4, !range [[$WS_RANGE:![0-9]*]], !invariant.load{{.*}}, !noundef // CHECK: getelementptr inbounds i8, ptr addrspace(4) %{{.*}}, i64 14 @@ -619,7 +637,7 @@ void test_get_workgroup_size(int d, global int *out) } // CHECK-LABEL: @test_get_grid_size( -// CHECK: call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() +// CHECK: {{.*}}call align 4 dereferenceable(64){{.*}} ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() // CHECK: getelementptr inbounds i8, ptr addrspace(4) %{{.*}}, i64 12 // CHECK: load i32, ptr addrspace(4) %{{.*}}, align 4, !invariant.load // CHECK: getelementptr inbounds i8, ptr addrspace(4) %{{.*}}, i64 16 @@ -637,177 +655,185 @@ void test_get_grid_size(int d, global int *out) } // CHECK-LABEL: @test_fmed3_f32 -// CHECK: call float @llvm.amdgcn.fmed3.f32( +// CHECK: {{.*}}call{{.*}} float @llvm.amdgcn.fmed3.f32( void test_fmed3_f32(global float* out, float a, float b, float c) { *out = __builtin_amdgcn_fmed3f(a, b, c); } // CHECK-LABEL: @test_s_getpc -// CHECK: call i64 @llvm.amdgcn.s.getpc() +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.s.getpc() void test_s_getpc(global ulong* out) { *out = __builtin_amdgcn_s_getpc(); } // CHECK-LABEL: @test_ds_append_lds( -// CHECK: call i32 @llvm.amdgcn.ds.append.p3(ptr addrspace(3) %ptr, i1 false) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.ds.append.p3(ptr addrspace(3) %ptr, i1 false) kernel void test_ds_append_lds(global int* out, local int* ptr) { +#if !defined(__SPIRV__) *out = __builtin_amdgcn_ds_append(ptr); +#else + *out = __builtin_amdgcn_ds_append((__attribute__((address_space(3))) int*)(int*)ptr); +#endif } // CHECK-LABEL: @test_ds_consume_lds( -// CHECK: call i32 @llvm.amdgcn.ds.consume.p3(ptr addrspace(3) %ptr, i1 false) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.ds.consume.p3(ptr addrspace(3) %ptr, i1 false) kernel void test_ds_consume_lds(global int* out, local int* ptr) { +#if !defined(__SPIRV__) *out = __builtin_amdgcn_ds_consume(ptr); +#else + *out = __builtin_amdgcn_ds_consume((__attribute__((address_space(3))) int*)(int*)ptr); +#endif } // CHECK-LABEL: @test_gws_init( -// CHECK: call void @llvm.amdgcn.ds.gws.init(i32 %value, i32 %id) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.ds.gws.init(i32 %value, i32 %id) kernel void test_gws_init(uint value, uint id) { __builtin_amdgcn_ds_gws_init(value, id); } // CHECK-LABEL: @test_gws_barrier( -// CHECK: call void @llvm.amdgcn.ds.gws.barrier(i32 %value, i32 %id) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.ds.gws.barrier(i32 %value, i32 %id) kernel void test_gws_barrier(uint value, uint id) { __builtin_amdgcn_ds_gws_barrier(value, id); } // CHECK-LABEL: @test_gws_sema_v( -// CHECK: call void @llvm.amdgcn.ds.gws.sema.v(i32 %id) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.ds.gws.sema.v(i32 %id) kernel void test_gws_sema_v(uint id) { __builtin_amdgcn_ds_gws_sema_v(id); } // CHECK-LABEL: @test_gws_sema_br( -// CHECK: call void @llvm.amdgcn.ds.gws.sema.br(i32 %value, i32 %id) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.ds.gws.sema.br(i32 %value, i32 %id) kernel void test_gws_sema_br(uint value, uint id) { __builtin_amdgcn_ds_gws_sema_br(value, id); } // CHECK-LABEL: @test_gws_sema_p( -// CHECK: call void @llvm.amdgcn.ds.gws.sema.p(i32 %id) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.ds.gws.sema.p(i32 %id) kernel void test_gws_sema_p(uint id) { __builtin_amdgcn_ds_gws_sema_p(id); } // CHECK-LABEL: @test_mbcnt_lo( -// CHECK: call i32 @llvm.amdgcn.mbcnt.lo(i32 %src0, i32 %src1) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.mbcnt.lo(i32 %src0, i32 %src1) kernel void test_mbcnt_lo(global uint* out, uint src0, uint src1) { *out = __builtin_amdgcn_mbcnt_lo(src0, src1); } // CHECK-LABEL: @test_mbcnt_hi( -// CHECK: call i32 @llvm.amdgcn.mbcnt.hi(i32 %src0, i32 %src1) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.mbcnt.hi(i32 %src0, i32 %src1) kernel void test_mbcnt_hi(global uint* out, uint src0, uint src1) { *out = __builtin_amdgcn_mbcnt_hi(src0, src1); } // CHECK-LABEL: @test_alignbit( -// CHECK: tail call i32 @llvm.fshr.i32(i32 %src0, i32 %src1, i32 %src2) +// CHECK: tail call{{.*}} i32 @llvm.fshr.i32(i32 %src0, i32 %src1, i32 %src2) kernel void test_alignbit(global uint* out, uint src0, uint src1, uint src2) { *out = __builtin_amdgcn_alignbit(src0, src1, src2); } // CHECK-LABEL: @test_alignbyte( -// CHECK: tail call i32 @llvm.amdgcn.alignbyte(i32 %src0, i32 %src1, i32 %src2) +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.alignbyte(i32 %src0, i32 %src1, i32 %src2) kernel void test_alignbyte(global uint* out, uint src0, uint src1, uint src2) { *out = __builtin_amdgcn_alignbyte(src0, src1, src2); } // CHECK-LABEL: @test_ubfe( -// CHECK: tail call i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 %src1, i32 %src2) +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.ubfe.i32(i32 %src0, i32 %src1, i32 %src2) kernel void test_ubfe(global uint* out, uint src0, uint src1, uint src2) { *out = __builtin_amdgcn_ubfe(src0, src1, src2); } // CHECK-LABEL: @test_sbfe( -// CHECK: tail call i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 %src1, i32 %src2) +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.sbfe.i32(i32 %src0, i32 %src1, i32 %src2) kernel void test_sbfe(global uint* out, uint src0, uint src1, uint src2) { *out = __builtin_amdgcn_sbfe(src0, src1, src2); } // CHECK-LABEL: @test_cvt_pkrtz( -// CHECK: tail call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %src0, float %src1) +// CHECK: tail call{{.*}} <2 x half> @llvm.amdgcn.cvt.pkrtz(float %src0, float %src1) kernel void test_cvt_pkrtz(global half2* out, float src0, float src1) { *out = __builtin_amdgcn_cvt_pkrtz(src0, src1); } // CHECK-LABEL: @test_cvt_pknorm_i16( -// CHECK: tail call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %src0, float %src1) +// CHECK: tail call{{.*}} <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %src0, float %src1) kernel void test_cvt_pknorm_i16(global short2* out, float src0, float src1) { *out = __builtin_amdgcn_cvt_pknorm_i16(src0, src1); } // CHECK-LABEL: @test_cvt_pknorm_u16( -// CHECK: tail call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %src0, float %src1) +// CHECK: tail call{{.*}} <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %src0, float %src1) kernel void test_cvt_pknorm_u16(global ushort2* out, float src0, float src1) { *out = __builtin_amdgcn_cvt_pknorm_u16(src0, src1); } // CHECK-LABEL: @test_cvt_pk_i16( -// CHECK: tail call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %src0, i32 %src1) +// CHECK: tail call{{.*}} <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %src0, i32 %src1) kernel void test_cvt_pk_i16(global short2* out, int src0, int src1) { *out = __builtin_amdgcn_cvt_pk_i16(src0, src1); } // CHECK-LABEL: @test_cvt_pk_u16( -// CHECK: tail call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %src0, i32 %src1) +// CHECK: tail call{{.*}} <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %src0, i32 %src1) kernel void test_cvt_pk_u16(global ushort2* out, uint src0, uint src1) { *out = __builtin_amdgcn_cvt_pk_u16(src0, src1); } // CHECK-LABEL: @test_cvt_pk_u8_f32 -// CHECK: tail call i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src0, i32 %src1, i32 %src2) +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.cvt.pk.u8.f32(float %src0, i32 %src1, i32 %src2) kernel void test_cvt_pk_u8_f32(global uint* out, float src0, uint src1, uint src2) { *out = __builtin_amdgcn_cvt_pk_u8_f32(src0, src1, src2); } // CHECK-LABEL: @test_sad_u8( -// CHECK: tail call i32 @llvm.amdgcn.sad.u8(i32 %src0, i32 %src1, i32 %src2) +// CHECK: tail call{{.*}} i32 @llvm.amdgcn.sad.u8(i32 %src0, i32 %src1, i32 %src2) kernel void test_sad_u8(global uint* out, uint src0, uint src1, uint src2) { *out = __builtin_amdgcn_sad_u8(src0, src1, src2); } // CHECK-LABEL: test_msad_u8( -// CHECK: call i32 @llvm.amdgcn.msad.u8(i32 %src0, i32 %src1, i32 %src2) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.msad.u8(i32 %src0, i32 %src1, i32 %src2) kernel void test_msad_u8(global uint* out, uint src0, uint src1, uint src2) { *out = __builtin_amdgcn_msad_u8(src0, src1, src2); } // CHECK-LABEL: test_sad_hi_u8( -// CHECK: call i32 @llvm.amdgcn.sad.hi.u8(i32 %src0, i32 %src1, i32 %src2) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.sad.hi.u8(i32 %src0, i32 %src1, i32 %src2) kernel void test_sad_hi_u8(global uint* out, uint src0, uint src1, uint src2) { *out = __builtin_amdgcn_sad_hi_u8(src0, src1, src2); } // CHECK-LABEL: @test_sad_u16( -// CHECK: call i32 @llvm.amdgcn.sad.u16(i32 %src0, i32 %src1, i32 %src2) +// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.sad.u16(i32 %src0, i32 %src1, i32 %src2) kernel void test_sad_u16(global uint* out, uint src0, uint src1, uint src2) { *out = __builtin_amdgcn_sad_u16(src0, src1, src2); } // CHECK-LABEL: @test_qsad_pk_u16_u8( -// CHECK: call i64 @llvm.amdgcn.qsad.pk.u16.u8(i64 %src0, i32 %src1, i64 %src2) +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.qsad.pk.u16.u8(i64 %src0, i32 %src1, i64 %src2) kernel void test_qsad_pk_u16_u8(global ulong* out, ulong src0, uint src1, ulong src2) { *out = __builtin_amdgcn_qsad_pk_u16_u8(src0, src1, src2); } // CHECK-LABEL: @test_mqsad_pk_u16_u8( -// CHECK: call i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64 %src0, i32 %src1, i64 %src2) +// CHECK: {{.*}}call{{.*}} i64 @llvm.amdgcn.mqsad.pk.u16.u8(i64 %src0, i32 %src1, i64 %src2) kernel void test_mqsad_pk_u16_u8(global ulong* out, ulong src0, uint src1, ulong src2) { *out = __builtin_amdgcn_mqsad_pk_u16_u8(src0, src1, src2); } // CHECK-LABEL: test_mqsad_u32_u8( -// CHECK: call <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %src0, i32 %src1, <4 x i32> %src2) +// CHECK: {{.*}}call{{.*}} <4 x i32> @llvm.amdgcn.mqsad.u32.u8(i64 %src0, i32 %src1, <4 x i32> %src2) kernel void test_mqsad_u32_u8(global uint4* out, ulong src0, uint src1, uint4 src2) { *out = __builtin_amdgcn_mqsad_u32_u8(src0, src1, src2); } // CHECK-LABEL: test_s_setreg( -// CHECK: call void @llvm.amdgcn.s.setreg(i32 8193, i32 %val) +// CHECK: {{.*}}call{{.*}} void @llvm.amdgcn.s.setreg(i32 8193, i32 %val) kernel void test_s_setreg(uint val) { __builtin_amdgcn_s_setreg(8193, val); } @@ -835,31 +861,33 @@ void test_atomic_inc_dec(local uint *lptr, global uint *gptr, uint val) { // CHECK-LABEL test_wavefrontsize( unsigned test_wavefrontsize() { - // CHECK: call i32 @llvm.amdgcn.wavefrontsize() + // CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.wavefrontsize() return __builtin_amdgcn_wavefrontsize(); } // CHECK-LABEL test_flt_rounds( unsigned test_flt_rounds() { - // CHECK: call i32 @llvm.get.rounding() + // CHECK: {{.*}}call{{.*}} i32 @llvm.get.rounding() unsigned mode = __builtin_flt_rounds(); - // CHECK: call void @llvm.set.rounding(i32 %0) +#if !defined(__SPIRV__) + // CHECK-AMDGCN: call void @llvm.set.rounding(i32 %0) __builtin_set_flt_rounds(mode); +#endif return mode; } // CHECK-LABEL test_get_fpenv( unsigned long test_get_fpenv() { - // CHECK: call i64 @llvm.get.fpenv.i64() + // CHECK: {{.*}}call{{.*}} i64 @llvm.get.fpenv.i64() return __builtin_amdgcn_get_fpenv(); } // CHECK-LABEL test_set_fpenv( void test_set_fpenv(unsigned long env) { - // CHECK: call void @llvm.set.fpenv.i64(i64 %[[ENV:.+]]) + // CHECK: {{.*}}call{{.*}} void @llvm.set.fpenv.i64(i64 %[[ENV:.+]]) __builtin_amdgcn_set_fpenv(env); } diff --git a/clang/test/CodeGenOpenCL/inline-asm-amdgcn.cl b/clang/test/CodeGenOpenCL/inline-asm-amdgcn.cl index 259c12384f2c8d..5ebb0ea0c33c3e 100644 --- a/clang/test/CodeGenOpenCL/inline-asm-amdgcn.cl +++ b/clang/test/CodeGenOpenCL/inline-asm-amdgcn.cl @@ -1,11 +1,12 @@ // REQUIRES: amdgpu-registered-target // RUN: %clang_cc1 -emit-llvm -O0 -o - -triple amdgcn %s | FileCheck %s +// RUN: %clang_cc1 -emit-llvm -O0 -o - -triple spirv64-amd-amdhsa %s | FileCheck %s typedef float float32 __attribute__((ext_vector_type(32))); kernel void test_long(int arg0) { long v15_16; - // CHECK: call i64 asm sideeffect "v_lshlrev_b64 v[15:16], 0, $0", "={v[15:16]},v" + // CHECK: call{{.*}} i64 asm sideeffect "v_lshlrev_b64 v[15:16], 0, $0", "={v[15:16]},v" __asm volatile("v_lshlrev_b64 v[15:16], 0, %0" : "={v[15:16]}"(v15_16) : "v"(arg0)); } @@ -14,7 +15,7 @@ kernel void test_agpr() { float reg_a; float reg_b; float32 reg_c; - // CHECK: call <32 x float> asm "v_mfma_f32_32x32x1f32 $0, $1, $2, $3", "=a,v,v,a,~{a0},~{a1},~{a2},~{a3},~{a4},~{a5},~{a6},~{a7},~{a8},~{a9},~{a10},~{a11},~{a12},~{a13},~{a14},~{a15},~{a16},~{a17},~{a18},~{a19},~{a20},~{a21},~{a22},~{a23},~{a24},~{a25},~{a26},~{a27},~{a28},~{a29},~{a30},~{a31}" + // CHECK: call{{.*}} <32 x float> asm "v_mfma_f32_32x32x1f32 $0, $1, $2, $3", "=a,v,v,a,~{a0},~{a1},~{a2},~{a3},~{a4},~{a5},~{a6},~{a7},~{a8},~{a9},~{a10},~{a11},~{a12},~{a13},~{a14},~{a15},~{a16},~{a17},~{a18},~{a19},~{a20},~{a21},~{a22},~{a23},~{a24},~{a25},~{a26},~{a27},~{a28},~{a29},~{a30},~{a31}" __asm ("v_mfma_f32_32x32x1f32 %0, %1, %2, %3" : "=a"(acc_c) : "v"(reg_a), "v"(reg_b), "a"(reg_c) @@ -23,12 +24,12 @@ kernel void test_agpr() { "a16", "a17", "a18", "a19", "a20", "a21", "a22", "a23", "a24", "a25", "a26", "a27", "a28", "a29", "a30", "a31"); - // CHECK: call <32 x float> asm sideeffect "v_mfma_f32_32x32x1f32 a[0:31], $0, $1, a[0:31]", "={a[0:31]},v,v,{a[0:31]}" + // CHECK: call{{.*}} <32 x float> asm sideeffect "v_mfma_f32_32x32x1f32 a[0:31], $0, $1, a[0:31]", "={a[0:31]},v,v,{a[0:31]}" __asm volatile("v_mfma_f32_32x32x1f32 a[0:31], %0, %1, a[0:31]" : "={a[0:31]}"(acc_c) : "v"(reg_a),"v"(reg_b), "{a[0:31]}"(reg_c)); - // CHECK: call float asm "v_accvgpr_read_b32 $0, $1", "={a1},{a1}" + // CHECK: call{{.*}} float asm "v_accvgpr_read_b32 $0, $1", "={a1},{a1}" __asm ("v_accvgpr_read_b32 %0, %1" : "={a1}"(reg_a) : "{a1}"(reg_b)); @@ -37,13 +38,13 @@ kernel void test_agpr() { kernel void test_constraint_DA() { const long x = 0x200000001; int res; - // CHECK: call i32 asm sideeffect "v_mov_b32 $0, $1 & 0xFFFFFFFF", "=v,^DA"(i64 8589934593) + // CHECK: call{{.*}} i32 asm sideeffect "v_mov_b32 $0, $1 & 0xFFFFFFFF", "=v,^DA"(i64 8589934593) __asm volatile("v_mov_b32 %0, %1 & 0xFFFFFFFF" : "=v"(res) : "DA"(x)); } kernel void test_constraint_DB() { const long x = 0x200000001; int res; - // CHECK: call i32 asm sideeffect "v_mov_b32 $0, $1 & 0xFFFFFFFF", "=v,^DB"(i64 8589934593) + // CHECK: call{{.*}} i32 asm sideeffect "v_mov_b32 $0, $1 & 0xFFFFFFFF", "=v,^DB"(i64 8589934593) __asm volatile("v_mov_b32 %0, %1 & 0xFFFFFFFF" : "=v"(res) : "DB"(x)); } diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx908-param.cl b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx908-param.cl index bb949c0ddd10df..969ff4ba9c9203 100644 --- a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx908-param.cl +++ b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx908-param.cl @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -triple amdgcn-- -target-cpu gfx908 -verify -S -o - %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -verify -S -o - %s #pragma OPENCL EXTENSION cl_khr_fp64:enable diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx90a-param.cl b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx90a-param.cl index 701016148a893c..235fa826314025 100644 --- a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx90a-param.cl +++ b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx90a-param.cl @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -triple amdgcn-- -target-cpu gfx90a -verify -S -o - %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -verify -S -o - %s #pragma OPENCL EXTENSION cl_khr_fp64:enable diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx940-param.cl b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx940-param.cl index b177b93938e46e..0fc2304d51ce05 100644 --- a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx940-param.cl +++ b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx940-param.cl @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -triple amdgcn-- -target-cpu gfx940 -verify -S -o - %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -verify -S -o - %s typedef float v2f __attribute__((ext_vector_type(2))); typedef float v4f __attribute__((ext_vector_type(4))); diff --git a/llvm/lib/TargetParser/TargetParser.cpp b/llvm/lib/TargetParser/TargetParser.cpp index 50757b74606f13..f4f0721f89dbc4 100644 --- a/llvm/lib/TargetParser/TargetParser.cpp +++ b/llvm/lib/TargetParser/TargetParser.cpp @@ -347,6 +347,8 @@ void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple &T, Features["fp8-conversion-insts"] = true; Features["atomic-ds-pk-add-16-insts"] = true; Features["mai-insts"] = true; + Features["wavefrontsize32"] = true; + Features["wavefrontsize64"] = true; } else if (T.isAMDGCN()) { switch (parseArchAMDGCN(GPU)) { case GK_GFX1201: From d2f4244c5059cd6b51bdd44c44c1cc74cc9f5933 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 14 May 2024 18:49:33 +0100 Subject: [PATCH 09/15] Add an additional test. --- clang/test/CodeGenHIP/hipspv-addr-spaces.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/test/CodeGenHIP/hipspv-addr-spaces.cpp b/clang/test/CodeGenHIP/hipspv-addr-spaces.cpp index 9fcdc460482e7e..c575f49ff69716 100644 --- a/clang/test/CodeGenHIP/hipspv-addr-spaces.cpp +++ b/clang/test/CodeGenHIP/hipspv-addr-spaces.cpp @@ -1,5 +1,7 @@ // RUN: %clang_cc1 -triple spirv64 -x hip -emit-llvm -fcuda-is-device \ // RUN: -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip -emit-llvm -fcuda-is-device \ +// RUN: -o - %s | FileCheck %s #define __device__ __attribute__((device)) #define __shared__ __attribute__((shared)) From 1841385f86b44de4d3e8955f793f53bfdad9e05f Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 15 May 2024 12:14:27 +0100 Subject: [PATCH 10/15] AMDGCN SPIRV should allow both AMDGCN and SPIRV builtins. --- clang/lib/CodeGen/CGBuiltin.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 8edbc64af8113f..cc7c16fe7444c8 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -6014,10 +6014,10 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, StringRef Prefix = llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch()); if (!Prefix.empty()) { - if (Prefix == "spv" && - getTarget().getTriple().getOS() == llvm::Triple::OSType::AMDHSA) - Prefix = "amdgcn"; IntrinsicID = Intrinsic::getIntrinsicForClangBuiltin(Prefix.data(), Name); + if (IntrinsicID == Intrinsic::not_intrinsic && Prefix == "spv" && + getTarget().getTriple().getOS() == llvm::Triple::OSType::AMDHSA) + IntrinsicID = Intrinsic::getIntrinsicForClangBuiltin("amdgcn", Name); // NOTE we don't need to perform a compatibility flag check here since the // intrinsics are declared in Builtins*.def via LANGBUILTIN which filter the // MS builtins via ALL_MS_LANGUAGES and are filtered earlier. From 83cd5e089afc49f431745d9ef51579db60ba8431 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Thu, 16 May 2024 20:22:08 +0100 Subject: [PATCH 11/15] Enable AMDGCN flavoured SPIRV in the experimental SPIRV BE. --- llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp | 4 +++ .../test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll | 1 + .../SPIRV/CheckCapKernelWithoutKernel.ll | 1 + llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll | 1 + .../SPIRV/FOrdGreaterThanEqual_bool.ll | 1 + .../CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll | 1 + .../test/CodeGen/SPIRV/SampledImageRetType.ll | 1 + .../SpecConstants/bool-spirv-specconstant.ll | 1 + llvm/test/CodeGen/SPIRV/TruncToBool.ll | 1 + llvm/test/CodeGen/SPIRV/assume.ll | 2 ++ llvm/test/CodeGen/SPIRV/atomicrmw.ll | 1 + llvm/test/CodeGen/SPIRV/basic_float_types.ll | 2 ++ llvm/test/CodeGen/SPIRV/basic_int_types.ll | 2 ++ .../CodeGen/SPIRV/basic_int_types_spirvdis.ll | 1 + llvm/test/CodeGen/SPIRV/bitcast.ll | 2 ++ .../CodeGen/SPIRV/branching/OpSwitch32.ll | 1 + .../CodeGen/SPIRV/branching/OpSwitch64.ll | 1 + .../branching/Two_OpSwitch_same_register.ll | 1 + .../SPIRV/capability-Int64Atomics-store.ll | 1 + .../CodeGen/SPIRV/capability-Int64Atomics.ll | 1 + llvm/test/CodeGen/SPIRV/capability-kernel.ll | 2 ++ llvm/test/CodeGen/SPIRV/const-composite.ll | 2 ++ .../SPIRV/constant/global-constants.ll | 1 + llvm/test/CodeGen/SPIRV/empty-module.ll | 3 ++ llvm/test/CodeGen/SPIRV/empty-opencl64.ll | 2 ++ llvm/test/CodeGen/SPIRV/event_no_group_cap.ll | 1 + .../SPIRV/execution-mode-per-entry-point.ll | 3 ++ llvm/test/CodeGen/SPIRV/expect.ll | 2 ++ .../bfloat16-conv.ll | 3 +- .../fp_const_amdgcn.ll | 35 +++++++++++++++++++ .../fp_two_calls_amdgcn.ll | 35 +++++++++++++++++++ .../SPV_INTEL_variable_length_array/vararr.ll | 3 ++ .../vararr_spec_const.ll | 2 ++ .../subgroup-rotate.ll | 4 ++- llvm/test/CodeGen/SPIRV/fence.ll | 2 ++ .../function/multiple-anonymous-functions.ll | 1 + llvm/test/CodeGen/SPIRV/half_extension.ll | 1 + llvm/test/CodeGen/SPIRV/half_no_extension.ll | 1 + llvm/test/CodeGen/SPIRV/image.ll | 1 + llvm/test/CodeGen/SPIRV/image/sampler.ll | 2 ++ .../CodeGen/SPIRV/instructions/select-phi.ll | 3 ++ .../SPIRV/instructions/select-ptr-load.ll | 3 ++ .../test/CodeGen/SPIRV/instructions/select.ll | 3 ++ .../SPIRV/linkage/extern-weak-linkage.ll | 3 ++ .../CodeGen/SPIRV/linkage/link-attribute.ll | 1 + llvm/test/CodeGen/SPIRV/literals.ll | 1 + .../test/CodeGen/SPIRV/llvm-intrinsics/abs.ll | 1 + .../CodeGen/SPIRV/llvm-intrinsics/assume.ll | 1 + .../CodeGen/SPIRV/llvm-intrinsics/bswap.ll | 1 + .../CodeGen/SPIRV/llvm-intrinsics/ceil.ll | 1 + .../CodeGen/SPIRV/llvm-intrinsics/ctlz.ll | 1 + .../CodeGen/SPIRV/llvm-intrinsics/ctpop.ll | 1 + .../CodeGen/SPIRV/llvm-intrinsics/cttz.ll | 1 + .../CodeGen/SPIRV/llvm-intrinsics/expect.ll | 1 + .../CodeGen/SPIRV/llvm-intrinsics/fabs.ll | 1 + .../SPIRV/llvm-intrinsics/fp-intrinsics.ll | 1 + .../CodeGen/SPIRV/llvm-intrinsics/fshl.ll | 1 + .../CodeGen/SPIRV/llvm-intrinsics/fshr.ll | 1 + .../SPIRV/llvm-intrinsics/invariant.ll | 1 + .../llvm-intrinsics/llvm-vector-reduce/add.ll | 2 ++ .../llvm-intrinsics/llvm-vector-reduce/and.ll | 2 ++ .../llvm-vector-reduce/fadd.ll | 2 ++ .../llvm-vector-reduce/fmax.ll | 2 ++ .../llvm-vector-reduce/fmaximum.ll | 2 ++ .../llvm-vector-reduce/fmin.ll | 2 ++ .../llvm-vector-reduce/fminimum.ll | 2 ++ .../llvm-vector-reduce/fmul.ll | 2 ++ .../llvm-intrinsics/llvm-vector-reduce/mul.ll | 2 ++ .../llvm-intrinsics/llvm-vector-reduce/or.ll | 2 ++ .../llvm-vector-reduce/smax.ll | 2 ++ .../llvm-vector-reduce/smin.ll | 2 ++ .../llvm-vector-reduce/umax.ll | 2 ++ .../llvm-vector-reduce/umin.ll | 2 ++ .../llvm-intrinsics/llvm-vector-reduce/xor.ll | 2 ++ .../CodeGen/SPIRV/llvm-intrinsics/maxnum.ll | 1 + .../SPIRV/llvm-intrinsics/satur-arith.ll | 3 ++ llvm/test/CodeGen/SPIRV/lshr-constexpr.ll | 1 + llvm/test/CodeGen/SPIRV/multi_md.ll | 1 + .../CodeGen/SPIRV/no_capability_shader.ll | 1 + llvm/test/CodeGen/SPIRV/opaque_pointers.ll | 1 + .../SPIRV/opencl/basic/get_global_offset.ll | 1 + .../opencl/basic/progvar_prog_scope_init.ll | 1 + .../opencl/basic/progvar_prog_scope_uninit.ll | 1 + .../opencl/device_execution/execute_block.ll | 1 + .../CodeGen/SPIRV/opencl/get_global_id.ll | 1 + .../metadata/fp_contractions_metadata.ll | 1 + .../metadata/no_fp_contractions_metadata.ll | 1 + llvm/test/CodeGen/SPIRV/opencl/vload2.ll | 1 + llvm/test/CodeGen/SPIRV/opencl/vstore2.ll | 1 + ...cs-TargetExtType-arg-no-spv_assign_type.ll | 1 + ...insics-no-divergent-spv_assign_ptr_type.ll | 5 +-- ...Intrinsics-no-duplicate-spv_assign_type.ll | 5 +-- .../SPIRV/pointers/argument-ptr-to-struct.ll | 2 ++ .../SPIRV/pointers/bitcast-fix-accesschain.ll | 2 ++ .../SPIRV/pointers/bitcast-fix-load.ll | 2 ++ .../SPIRV/pointers/bitcast-fix-store.ll | 2 ++ .../pointers/getelementptr-addressspace.ll | 2 ++ .../SPIRV/pointers/getelementptr-base-type.ll | 2 ++ .../pointers/getelementptr-bitcast-load.ll | 2 ++ .../pointers/getelementptr-kernel-arg-char.ll | 2 ++ .../CodeGen/SPIRV/pointers/global-ptrtoint.ll | 3 ++ ...argument-builtin-vload-type-discrapency.ll | 2 ++ .../kernel-argument-pointer-addressspace.ll | 2 ++ ...rgument-pointer-type-deduction-mismatch.ll | 1 + ...er-type-deduction-no-bitcast-to-generic.ll | 2 ++ ...ment-pointer-type-deduction-no-metadata.ll | 2 ++ .../pointers/kernel-argument-pointer-type.ll | 2 ++ ...el-argument-ptr-i8-default-element-type.ll | 2 ++ .../kernel-argument-ptr-no-bitcast.ll | 2 ++ .../SPIRV/pointers/load-addressspace.ll | 2 ++ .../SPIRV/pointers/ptr-argument-byref.ll | 2 ++ .../SPIRV/pointers/ptr-argument-byval.ll | 2 ++ ...tore-kernel-arg-i8-ptr-as-value-operand.ll | 2 ++ .../store-kernel-arg-ptr-as-value-operand.ll | 2 ++ .../SPIRV/pointers/two-subsequent-bitcasts.ll | 2 ++ .../pointers/type-deduce-by-call-chain.ll | 2 ++ .../pointers/type-deduce-call-no-bitcast.ll | 2 ++ .../CodeGen/SPIRV/pointers/typeof-ptr-int.ll | 2 ++ .../SPIRV/pointers/variables-storage-class.ll | 2 ++ .../test/CodeGen/SPIRV/preprocess-metadata.ll | 1 + llvm/test/CodeGen/SPIRV/printf.ll | 3 ++ llvm/test/CodeGen/SPIRV/pstruct.ll | 1 + llvm/test/CodeGen/SPIRV/read_image.ll | 1 + llvm/test/CodeGen/SPIRV/select-builtin.ll | 2 ++ llvm/test/CodeGen/SPIRV/simple.ll | 2 ++ llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll | 1 + .../CodeGen/SPIRV/spec_const_decoration.ll | 1 + llvm/test/CodeGen/SPIRV/spirv-load-store.ll | 2 ++ llvm/test/CodeGen/SPIRV/struct.ll | 1 + .../CodeGen/SPIRV/switch-no-jump-table.ll | 1 + .../token-type-preallocated-setup-arg.ll | 1 + .../token/token-type-requires-extension.ll | 1 + .../SPIRV/transcoding/BitReversePref.ll | 2 ++ .../SPIRV/transcoding/BuildNDRange_2.ll | 2 ++ .../SPIRV/transcoding/DecorationAlignment.ll | 2 ++ .../SPIRV/transcoding/OpImageQuerySize.ll | 1 + .../transcoding/OpVectorInsertDynamic_i16.ll | 1 + .../transcoding/OpenCL/atomic_cmpxchg.ll | 1 + .../transcoding/SpecConstantComposite.ll | 1 + .../CodeGen/SPIRV/transcoding/atomic_flag.ll | 2 ++ .../test/CodeGen/SPIRV/transcoding/bitcast.ll | 2 ++ .../transcoding/builtin_vars_arithmetics.ll | 8 +++-- .../SPIRV/transcoding/builtin_vars_opt.ll | 2 ++ .../SPIRV/transcoding/check_ro_qualifier.ll | 2 ++ llvm/test/CodeGen/SPIRV/transcoding/fmod.ll | 2 ++ .../transcoding/get_image_num_mip_levels.ll | 2 ++ .../image_get_size_with_access_qualifiers.ll | 1 + .../test/CodeGen/SPIRV/transcoding/isequal.ll | 2 ++ .../CodeGen/SPIRV/transcoding/memcpy-zext.ll | 2 ++ .../SPIRV/transcoding/memory_access.ll | 1 + llvm/test/CodeGen/SPIRV/transcoding/non32.ll | 1 + .../CodeGen/SPIRV/transcoding/readonly.ll | 1 + .../SPIRV/transcoding/spirv-event-null.ll | 3 ++ .../spirv-private-array-initialization.ll | 2 ++ .../SPIRV/transcoding/sub_group_ballot.ll | 1 + .../transcoding/sub_group_clustered_reduce.ll | 1 + .../transcoding/sub_group_extended_types.ll | 1 + .../sub_group_non_uniform_arithmetic.ll | 1 + .../transcoding/sub_group_non_uniform_vote.ll | 3 +- .../SPIRV/transcoding/sub_group_shuffle.ll | 1 + .../transcoding/sub_group_shuffle_relative.ll | 1 + .../SPIRV/transcoding/vec_type_hint.ll | 1 + llvm/test/CodeGen/SPIRV/types/or-i1.ll | 2 ++ llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll | 1 + llvm/test/CodeGen/SPIRV/unnamed-global.ll | 1 + 165 files changed, 337 insertions(+), 10 deletions(-) create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const_amdgcn.ll create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls_amdgcn.ll diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp index ae8baa3f119132..1fd6b62966232e 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp @@ -56,6 +56,10 @@ static std::string computeDataLayout(const Triple &TT) { if (Arch == Triple::spirv32) return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"; + if (TT.getVendor() == Triple::VendorType::AMD && + TT.getOS() == Triple::OSType::AMDHSA) + return "e-i64:64-v16:16-v24:32-v32:32-v48:64-" + "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1-P4-A0"; return "e-i64:64-v16:16-v24:32-v32:32-v48:64-" "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"; } diff --git a/llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll b/llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll index 88565082ef01ef..0b9413e904d352 100644 --- a/llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll +++ b/llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ;; Types: ; CHECK: %[[#F32:]] = OpTypeFloat 32 diff --git a/llvm/test/CodeGen/SPIRV/CheckCapKernelWithoutKernel.ll b/llvm/test/CodeGen/SPIRV/CheckCapKernelWithoutKernel.ll index c61b3d90eb25a1..d65c8891de8663 100644 --- a/llvm/test/CodeGen/SPIRV/CheckCapKernelWithoutKernel.ll +++ b/llvm/test/CodeGen/SPIRV/CheckCapKernelWithoutKernel.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s @a = addrspace(2) constant i32 1, align 4 diff --git a/llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll b/llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll index a6f172a81dc7c8..793c6295ba8ed2 100644 --- a/llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll +++ b/llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; TODO(#60133): Requires updates following opaque pointer migration. ; XFAIL: * diff --git a/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_bool.ll b/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_bool.ll index 735b35d757e7d8..d8004a20268f03 100644 --- a/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_bool.ll +++ b/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_bool.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpFOrdGreaterThanEqual ; CHECK-SPIRV-NOT: OpSelect diff --git a/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll b/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll index 86581a54684058..fff87d5dff769b 100644 --- a/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll +++ b/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: %[[#result:]] = OpFOrdGreaterThanEqual %[[#]] %[[#]] %[[#]] ; CHECK-SPIRV: %[[#]] = OpSelect %[[#]] %[[#result]] %[[#]] %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll b/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll index 7af5876a023e5b..1f708de03f9a7c 100644 --- a/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll +++ b/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#image1d_t:]] = OpTypeImage ; CHECK: %[[#sampler_t:]] = OpTypeSampler diff --git a/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll b/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll index 6e414f79bdde54..77c7bf3f8891d7 100644 --- a/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll +++ b/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpDecorate %[[#BOOL_CONST:]] SpecId [[#]] ; CHECK: %[[#BOOL_TY:]] = OpTypeBool diff --git a/llvm/test/CodeGen/SPIRV/TruncToBool.ll b/llvm/test/CodeGen/SPIRV/TruncToBool.ll index 6682c23f34e969..540c4899a7e13a 100644 --- a/llvm/test/CodeGen/SPIRV/TruncToBool.ll +++ b/llvm/test/CodeGen/SPIRV/TruncToBool.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpBitwiseAnd ; CHECK-SPIRV-NEXT: OpINotEqual diff --git a/llvm/test/CodeGen/SPIRV/assume.ll b/llvm/test/CodeGen/SPIRV/assume.ll index fbf12ef184a891..37b40b1fe328db 100644 --- a/llvm/test/CodeGen/SPIRV/assume.ll +++ b/llvm/test/CodeGen/SPIRV/assume.ll @@ -2,6 +2,8 @@ ; RUN: llc -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=EXT,CHECK %s ; RUN: llc -mtriple=spirv32-unknown-unknown < %s | FileCheck --check-prefixes=NOEXT,CHECK %s ; RUN: llc -mtriple=spirv64-unknown-unknown < %s | FileCheck --check-prefixes=NOEXT,CHECK %s +; RUN: llc -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=EXT,CHECK %s +; RUN: llc -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=EXT,CHECK %s ; EXT: OpCapability ExpectAssumeKHR ; EXT-NEXT: OpExtension "SPV_KHR_expect_assume" diff --git a/llvm/test/CodeGen/SPIRV/atomicrmw.ll b/llvm/test/CodeGen/SPIRV/atomicrmw.ll index 81484771575367..0b87d32164e79a 100644 --- a/llvm/test/CodeGen/SPIRV/atomicrmw.ll +++ b/llvm/test/CodeGen/SPIRV/atomicrmw.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#Int:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#Scope_Device:]] = OpConstant %[[#Int]] 1{{$}} diff --git a/llvm/test/CodeGen/SPIRV/basic_float_types.ll b/llvm/test/CodeGen/SPIRV/basic_float_types.ll index 1c7a8a851f59c6..66bc2ac79ea5cb 100644 --- a/llvm/test/CodeGen/SPIRV/basic_float_types.ll +++ b/llvm/test/CodeGen/SPIRV/basic_float_types.ll @@ -1,7 +1,9 @@ ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} define void @main() { entry: diff --git a/llvm/test/CodeGen/SPIRV/basic_int_types.ll b/llvm/test/CodeGen/SPIRV/basic_int_types.ll index 6bfc99025ccba5..496237125e7522 100644 --- a/llvm/test/CodeGen/SPIRV/basic_int_types.ll +++ b/llvm/test/CodeGen/SPIRV/basic_int_types.ll @@ -1,7 +1,9 @@ ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-amd-amdhsa %s -o - -filetype=obj | spirv-val %} define void @main() { entry: diff --git a/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll b/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll index 3778d897929188..47b9937572fe4e 100644 --- a/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll +++ b/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll @@ -2,6 +2,7 @@ ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - --filetype=obj | spirv-dis | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - --filetype=obj | spirv-dis | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - --filetype=obj | spirv-dis | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - --filetype=obj | spirv-dis | FileCheck %s define void @main() { entry: diff --git a/llvm/test/CodeGen/SPIRV/bitcast.ll b/llvm/test/CodeGen/SPIRV/bitcast.ll index 242c5a46583c22..dc9010ce821cd6 100644 --- a/llvm/test/CodeGen/SPIRV/bitcast.ll +++ b/llvm/test/CodeGen/SPIRV/bitcast.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV-DAG: %[[#TyInt32:]] = OpTypeInt 32 0 ; CHECK-SPIRV-DAG: %[[#TyInt16:]] = OpTypeInt 16 0 diff --git a/llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll b/llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll index fdf4e4ddbefb7c..6f06eff18fc343 100644 --- a/llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll +++ b/llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll @@ -15,6 +15,7 @@ ;; bash$ clang -cc1 -triple spir64-unknown-unknown -x cl -cl-std=CL2.0 -O0 -include opencl.h -emit-llvm OpSwitch.cl -o test_32.ll ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpSwitch %[[#]] %[[#]] 0 %[[#]] 1 %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/branching/OpSwitch64.ll b/llvm/test/CodeGen/SPIRV/branching/OpSwitch64.ll index 5e4f1f14f8f917..5063fa2bbc3ce8 100644 --- a/llvm/test/CodeGen/SPIRV/branching/OpSwitch64.ll +++ b/llvm/test/CodeGen/SPIRV/branching/OpSwitch64.ll @@ -18,6 +18,7 @@ ;; bash$ clang -cc1 -triple spir64-unknown-unknown -x cl -cl-std=CL2.0 -O0 -include opencl.h -emit-llvm OpSwitch.cl -o test_64.ll ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpSwitch %[[#]] %[[#]] 0 0 %[[#]] 1 0 %[[#]] 1 5 %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll b/llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll index 19c11ff64476b9..01c7811baf70e5 100644 --- a/llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll +++ b/llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV define spir_kernel void @test_two_switch_same_register(i32 %value) { ; CHECK-SPIRV: OpSwitch %[[#REGISTER:]] %[[#DEFAULT1:]] 1 %[[#CASE1:]] 0 %[[#CASE2:]] diff --git a/llvm/test/CodeGen/SPIRV/capability-Int64Atomics-store.ll b/llvm/test/CodeGen/SPIRV/capability-Int64Atomics-store.ll index ee626db8d9672e..0c644c05549a69 100644 --- a/llvm/test/CodeGen/SPIRV/capability-Int64Atomics-store.ll +++ b/llvm/test/CodeGen/SPIRV/capability-Int64Atomics-store.ll @@ -7,6 +7,7 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpCapability Int64Atomics diff --git a/llvm/test/CodeGen/SPIRV/capability-Int64Atomics.ll b/llvm/test/CodeGen/SPIRV/capability-Int64Atomics.ll index 65047f8c6e48f4..32ddd5579e972b 100644 --- a/llvm/test/CodeGen/SPIRV/capability-Int64Atomics.ll +++ b/llvm/test/CodeGen/SPIRV/capability-Int64Atomics.ll @@ -7,6 +7,7 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpCapability Int64Atomics diff --git a/llvm/test/CodeGen/SPIRV/capability-kernel.ll b/llvm/test/CodeGen/SPIRV/capability-kernel.ll index fea19511d4fdcc..053e9ff52c59a2 100644 --- a/llvm/test/CodeGen/SPIRV/capability-kernel.ll +++ b/llvm/test/CodeGen/SPIRV/capability-kernel.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: OpCapability Addresses diff --git a/llvm/test/CodeGen/SPIRV/const-composite.ll b/llvm/test/CodeGen/SPIRV/const-composite.ll index 4e304bb9516702..d54563436e950f 100644 --- a/llvm/test/CodeGen/SPIRV/const-composite.ll +++ b/llvm/test/CodeGen/SPIRV/const-composite.ll @@ -4,7 +4,9 @@ ; and also takes part in a composite constant creation. ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: %[[#type_int32:]] = OpTypeInt 32 0 ; CHECK-SPIRV: %[[#const1:]] = OpConstant %[[#type_int32]] 1 diff --git a/llvm/test/CodeGen/SPIRV/constant/global-constants.ll b/llvm/test/CodeGen/SPIRV/constant/global-constants.ll index 74e28cbe7acb17..2ce92541ae834c 100644 --- a/llvm/test/CodeGen/SPIRV/constant/global-constants.ll +++ b/llvm/test/CodeGen/SPIRV/constant/global-constants.ll @@ -1,5 +1,6 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} @global = addrspace(1) constant i32 1 ; OpenCL global memory @constant = addrspace(2) constant i32 2 ; OpenCL constant memory diff --git a/llvm/test/CodeGen/SPIRV/empty-module.ll b/llvm/test/CodeGen/SPIRV/empty-module.ll index b7cea042ee5ddc..56d94b01abdf92 100644 --- a/llvm/test/CodeGen/SPIRV/empty-module.ll +++ b/llvm/test/CodeGen/SPIRV/empty-module.ll @@ -4,6 +4,9 @@ ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOOCL ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} + ; CHECK-DAG: OpCapability Linkage ; CHECK-NOOCL-DAG: OpCapability Shader ; CHECK-OCL-DAG: OpCapability Addresses diff --git a/llvm/test/CodeGen/SPIRV/empty-opencl64.ll b/llvm/test/CodeGen/SPIRV/empty-opencl64.ll index 4eaa2e4af0fc76..aa5370bf95d4d1 100644 --- a/llvm/test/CodeGen/SPIRV/empty-opencl64.ll +++ b/llvm/test/CodeGen/SPIRV/empty-opencl64.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; FIXME: ensure Magic Number, version number, generator's magic number, "bound" and "schema" are at least present diff --git a/llvm/test/CodeGen/SPIRV/event_no_group_cap.ll b/llvm/test/CodeGen/SPIRV/event_no_group_cap.ll index af4ac7cf44500b..50264ea0de21be 100644 --- a/llvm/test/CodeGen/SPIRV/event_no_group_cap.ll +++ b/llvm/test/CodeGen/SPIRV/event_no_group_cap.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; __kernel void test_fn( const __global char *src) ; { diff --git a/llvm/test/CodeGen/SPIRV/execution-mode-per-entry-point.ll b/llvm/test/CodeGen/SPIRV/execution-mode-per-entry-point.ll index 6fd1abd2be59ab..ba085e35366098 100644 --- a/llvm/test/CodeGen/SPIRV/execution-mode-per-entry-point.ll +++ b/llvm/test/CodeGen/SPIRV/execution-mode-per-entry-point.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: OpMemoryModel ; CHECK-DAG: OpEntryPoint Kernel %[[#ENTRY1:]] "foo1" @@ -10,6 +12,7 @@ ; CHECK: OpSource ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECKN +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECKN ; CHECKN: OpMemoryModel ; CHECKN-COUNT-2: OpEntryPoint Kernel diff --git a/llvm/test/CodeGen/SPIRV/expect.ll b/llvm/test/CodeGen/SPIRV/expect.ll index 82c1ec7dc916cf..3d4829184f3a9a 100644 --- a/llvm/test/CodeGen/SPIRV/expect.ll +++ b/llvm/test/CodeGen/SPIRV/expect.ll @@ -1,7 +1,9 @@ ; RUN: llc -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=CHECK,EXT %s ; RUN: llc -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=CHECK,EXT %s +; RUN: llc -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=CHECK,EXT %s ; RUN: llc -mtriple=spirv32-unknown-unknown < %s | FileCheck --check-prefixes=CHECK,NOEXT %s ; RUN: llc -mtriple=spirv64-unknown-unknown < %s | FileCheck --check-prefixes=CHECK,NOEXT %s +; RUN: llc -mtriple=spirv64-amd-amdhsa < %s | FileCheck --check-prefixes=CHECK,NOEXT %s ; EXT: OpCapability ExpectAssumeKHR ; EXT-NEXT: OpExtension "SPV_KHR_expect_assume" diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll index 91fa340e461121..e3a976499676e6 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll @@ -1,5 +1,6 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_bfloat16_conversion %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_bfloat16_conversion %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_bfloat16_conversion %s -o - -filetype=obj | spirv-val %} + ; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR ; CHECK-ERROR: the builtin requires the following SPIR-V extension: SPV_INTEL_bfloat16_conversion diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const_amdgcn.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const_amdgcn.ll new file mode 100644 index 00000000000000..8e1b0574725654 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const_amdgcn.ll @@ -0,0 +1,35 @@ +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: OpCapability Int8 +; CHECK-DAG: OpCapability GenericPointer +; CHECK-DAG: OpCapability FunctionPointersINTEL +; CHECK-DAG: OpCapability Int64 +; CHECK: OpExtension "SPV_INTEL_function_pointers" +; CHECK-DAG: %[[TyInt8:.*]] = OpTypeInt 8 0 +; CHECK-DAG: %[[TyVoid:.*]] = OpTypeVoid +; CHECK-DAG: %[[TyInt64:.*]] = OpTypeInt 64 0 +; CHECK-DAG: %[[TyFunFp:.*]] = OpTypeFunction %[[TyVoid]] %[[TyInt64]] +; CHECK-DAG: %[[ConstInt64:.*]] = OpConstant %[[TyInt64]] 42 +; CHECK-DAG: %[[TyPtrFunFp:.*]] = OpTypePointer Generic %[[TyFunFp]] +; CHECK-DAG: %[[ConstFunFp:.*]] = OpConstantFunctionPointerINTEL %[[TyPtrFunFp]] %[[DefFunFp:.*]] +; CHECK: %[[FunPtr1:.*]] = OpBitcast %[[#]] %[[ConstFunFp]] +; CHECK: %[[FunPtr2:.*]] = OpLoad %[[#]] %[[FunPtr1]] +; CHECK: OpFunctionPointerCallINTEL %[[TyInt64]] %[[FunPtr2]] %[[ConstInt64]] +; CHECK: OpReturn +; CHECK: OpFunctionEnd +; CHECK: %[[DefFunFp]] = OpFunction %[[TyVoid]] None %[[TyFunFp]] + +target triple = "spir64-unknown-unknown" + +define spir_kernel void @test() { +entry: + %0 = load ptr addrspace(4), ptr addrspace(4) @foo + %1 = call addrspace(4) i64 %0(i64 42) + ret void +} + +define void @foo(i64 %a) addrspace(4) { +entry: + ret void +} diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls_amdgcn.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls_amdgcn.ll new file mode 100644 index 00000000000000..3b9e721668c368 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls_amdgcn.ll @@ -0,0 +1,35 @@ +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: OpCapability Int8 +; CHECK-DAG: OpCapability GenericPointer +; CHECK-DAG: OpCapability FunctionPointersINTEL +; CHECK-DAG: OpCapability Int64 +; CHECK: OpExtension "SPV_INTEL_function_pointers" +; CHECK-DAG: %[[TyInt8:.*]] = OpTypeInt 8 0 +; CHECK-DAG: %[[TyVoid:.*]] = OpTypeVoid +; CHECK-DAG: %[[TyFloat32:.*]] = OpTypeFloat 32 +; CHECK-DAG: %[[TyInt64:.*]] = OpTypeInt 64 0 +; CHECK-DAG: %[[TyPtrInt8:.*]] = OpTypePointer Generic %[[TyInt8]] +; CHECK-DAG: %[[TyFunFp:.*]] = OpTypeFunction %[[TyFloat32]] %[[TyPtrInt8]] +; CHECK-DAG: %[[TyFunBar:.*]] = OpTypeFunction %[[TyInt64]] %[[TyPtrInt8]] %[[TyPtrInt8]] +; CHECK-DAG: %[[TyPtrFunFp:.*]] = OpTypePointer Function %[[TyFunFp]] +; CHECK-DAG: %[[TyPtrFunBar:.*]] = OpTypePointer Function %[[TyFunBar]] +; CHECK-DAG: %[[TyFunTest:.*]] = OpTypeFunction %[[TyVoid]] %[[TyPtrInt8]] %[[TyPtrInt8]] %[[TyPtrInt8]] +; CHECK: %[[FunTest:.*]] = OpFunction %[[TyVoid]] None %[[TyFunTest]] +; CHECK: %[[ArgFp:.*]] = OpFunctionParameter %[[TyPtrInt8]] +; CHECK: %[[ArgData:.*]] = OpFunctionParameter %[[TyPtrInt8]] +; CHECK: %[[ArgBar:.*]] = OpFunctionParameter %[[TyPtrInt8]] +; CHECK: OpFunctionPointerCallINTEL %[[TyFloat32]] %[[ArgFp]] %[[ArgBar]] +; CHECK: OpFunctionPointerCallINTEL %[[TyInt64]] %[[ArgBar]] %[[ArgFp]] %[[ArgData]] +; CHECK: OpReturn +; CHECK: OpFunctionEnd + +target triple = "spir64-unknown-unknown" + +define spir_kernel void @test(ptr addrspace(4) %fp, ptr addrspace(4) %data, ptr addrspace(4) %bar) { +entry: + %0 = call spir_func addrspace(4) float %fp(ptr addrspace(4) %bar) + %1 = call spir_func addrspace(4) i64 %bar(ptr addrspace(4) %fp, ptr addrspace(4) %data) + ret void +} diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll index 8a54d22a539db1..4ef3e72c78e5eb 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll @@ -1,8 +1,11 @@ ; Modified from: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/test/extensions/INTEL/SPV_INTEL_variable_length_array/basic.ll ; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR +; RUN: not llc -O0 -mtriple=spirv64-amd-amdhsa %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %} +; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %} ; CHECK-ERROR: LLVM ERROR: array allocation: this instruction requires the following SPIR-V extension: SPV_INTEL_variable_length_array diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll index 7b9f75d74db997..c7f7b0e881b1c3 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll @@ -1,7 +1,9 @@ ; Modified from: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/test/extensions/INTEL/SPV_INTEL_variable_length_array/vla_spec_const.ll ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %} +; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: Capability VariableLengthArrayINTEL ; CHECK-SPIRV: Extension "SPV_INTEL_variable_length_array" diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll index 63aade4f7f8daf..83318a0b504391 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll @@ -1,6 +1,8 @@ ; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_KHR_subgroup_rotate %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_KHR_subgroup_rotate %s -o - | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_subgroup_rotate %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_KHR_subgroup_rotate %s -o - -filetype=obj | spirv-val %} ; CHECK-ERROR: LLVM ERROR: OpGroupNonUniformRotateKHR instruction requires the following SPIR-V extension: SPV_KHR_subgroup_rotate @@ -17,7 +19,7 @@ ; CHECK-DAG: %[[ScopeSubgroup:.*]] = OpConstant %[[TyInt32]] 3 ; CHECK-DAG: %[[ConstInt2:.*]] = OpConstant %[[TyInt32]] 2 ; CHECK-DAG: %[[ConstInt4:.*]] = OpConstant %[[TyInt32]] 4 - + target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" target triple = "spir" diff --git a/llvm/test/CodeGen/SPIRV/fence.ll b/llvm/test/CodeGen/SPIRV/fence.ll index 5da58667f24f29..9dcc3f95e12b9c 100644 --- a/llvm/test/CodeGen/SPIRV/fence.ll +++ b/llvm/test/CodeGen/SPIRV/fence.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: OpName %[[#GetScope:]] "_Z8getScopev" ; CHECK-DAG: %[[#Long:]] = OpTypeInt 32 0 diff --git a/llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll b/llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll index 93bdbe3c1c2117..346595d786f26f 100644 --- a/llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll +++ b/llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ;; Types: ; CHECK-DAG: %[[#I32:]] = OpTypeInt 32 diff --git a/llvm/test/CodeGen/SPIRV/half_extension.ll b/llvm/test/CodeGen/SPIRV/half_extension.ll index b30e5514c95bea..0b0f0641420959 100644 --- a/llvm/test/CodeGen/SPIRV/half_extension.ll +++ b/llvm/test/CodeGen/SPIRV/half_extension.ll @@ -8,6 +8,7 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability Float16Buffer ; CHECK-SPIRV-DAG: OpCapability Float16 diff --git a/llvm/test/CodeGen/SPIRV/half_no_extension.ll b/llvm/test/CodeGen/SPIRV/half_no_extension.ll index a5b0ec9c92d236..66b8cbbcc38dc8 100644 --- a/llvm/test/CodeGen/SPIRV/half_no_extension.ll +++ b/llvm/test/CodeGen/SPIRV/half_no_extension.ll @@ -6,6 +6,7 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpCapability Float16Buffer ; CHECK-SPIRV-NOT: OpCapability Float16 diff --git a/llvm/test/CodeGen/SPIRV/image.ll b/llvm/test/CodeGen/SPIRV/image.ll index 8d4ab7f3cbf0ee..bc6d124ccb2205 100644 --- a/llvm/test/CodeGen/SPIRV/image.ll +++ b/llvm/test/CodeGen/SPIRV/image.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: %[[#VOID_TY:]] = OpTypeVoid ; CHECK-SPIRV-DAG: %[[#]] = OpTypeImage %[[#VOID_TY]] 2D 0 0 0 0 Unknown ReadOnly diff --git a/llvm/test/CodeGen/SPIRV/image/sampler.ll b/llvm/test/CodeGen/SPIRV/image/sampler.ll index 7b45c95f5ed433..9ad2244a9d28c1 100644 --- a/llvm/test/CodeGen/SPIRV/image/sampler.ll +++ b/llvm/test/CodeGen/SPIRV/image/sampler.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#i32:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#v4i32:]] = OpTypeVector %[[#i32]] 4 diff --git a/llvm/test/CodeGen/SPIRV/instructions/select-phi.ll b/llvm/test/CodeGen/SPIRV/instructions/select-phi.ll index 3828fe89e60aec..ac6f22aad196ed 100644 --- a/llvm/test/CodeGen/SPIRV/instructions/select-phi.ll +++ b/llvm/test/CodeGen/SPIRV/instructions/select-phi.ll @@ -1,10 +1,13 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --translator-compatibility-mode %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --translator-compatibility-mode %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa --translator-compatibility-mode %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[Char:.*]] = OpTypeInt 8 0 ; CHECK-DAG: %[[Long:.*]] = OpTypeInt 32 0 diff --git a/llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll b/llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll index 0ff28952f8081a..70699cf763eee5 100644 --- a/llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll +++ b/llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll @@ -4,6 +4,9 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} + ; CHECK-SPIRV-DAG: %[[Float:.*]] = OpTypeFloat 32 ; CHECK-SPIRV-DAG: %[[FloatPtr:.*]] = OpTypePointer Function %[[Float]] ; CHECK-SPIRV: OpInBoundsPtrAccessChain %[[FloatPtr]] diff --git a/llvm/test/CodeGen/SPIRV/instructions/select.ll b/llvm/test/CodeGen/SPIRV/instructions/select.ll index 9234b97157d9d8..f48983d8cd16a0 100644 --- a/llvm/test/CodeGen/SPIRV/instructions/select.ll +++ b/llvm/test/CodeGen/SPIRV/instructions/select.ll @@ -4,6 +4,9 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} + ; CHECK-DAG: OpName [[SCALARi32:%.+]] "select_i32" ; CHECK-DAG: OpName [[SCALARPTR:%.+]] "select_ptr" ; CHECK-DAG: OpName [[VEC2i32:%.+]] "select_i32v2" diff --git a/llvm/test/CodeGen/SPIRV/linkage/extern-weak-linkage.ll b/llvm/test/CodeGen/SPIRV/linkage/extern-weak-linkage.ll index e742de4bc1e217..1c2693d796cc83 100644 --- a/llvm/test/CodeGen/SPIRV/linkage/extern-weak-linkage.ll +++ b/llvm/test/CodeGen/SPIRV/linkage/extern-weak-linkage.ll @@ -1,6 +1,9 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} + ; CHECK-SPIRV: Capability Linkage ; CHECK-SPIRV-DAG: OpName %[[#AbsFun:]] "abs" ; CHECK-SPIRV-DAG: OpName %[[#ExternalFun:]] "__devicelib_abs" diff --git a/llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll b/llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll index f00c25a949b1e2..66964fe6a7abfe 100644 --- a/llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll +++ b/llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpDecorate %[[#ID:]] LinkageAttributes "imageSampler" Export ; CHECK: %[[#ID]] = OpVariable %[[#]] UniformConstant %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/literals.ll b/llvm/test/CodeGen/SPIRV/literals.ll index d99ec36537d10f..6f4858e59ef67a 100644 --- a/llvm/test/CodeGen/SPIRV/literals.ll +++ b/llvm/test/CodeGen/SPIRV/literals.ll @@ -1,6 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#F32:]] = OpTypeFloat 32 ; CHECK: %[[#F64:]] = OpTypeFloat 64 diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll index d627a2fc7838a9..d69d6569735e2d 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] s_abs ; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] s_abs diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll index 48c96fae8b03a0..44d00e6900e241 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-NOT: OpCapability ExpectAssumeKHR ; CHECK-SPIRV-NOT: OpExtension "SPV_KHR_expect_assume" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll index 3f2ab9fa7190bc..a57614287369ec 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpName %[[#FuncNameInt16:]] "spirv.llvm_bswap_i16" ; CHECK-SPIRV: OpName %[[#FuncNameInt32:]] "spirv.llvm_bswap_i32" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll index 8411d90e23f0d1..3e39e748b5df11 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll index 147fd80462f9ad..51a621db829ac1 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll index f2d881b083dd7e..b801836c057ac1 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#]] = OpBitCount %[[#]] %[[#]] ; CHECK: %[[#]] = OpBitCount %[[#]] %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll index b9bdcfdb162f76..f496dc7ed97ce9 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/expect.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/expect.ll index ec40c263be4112..fc6afd78e81e3a 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/expect.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/expect.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-NOT: OpCapability ExpectAssumeKHR ; CHECK-SPIRV-NOT: OpExtension "SPV_KHR_expect_assume" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll index 5de22021762927..20b6f6be0e5b37 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll index 8f14e8cf272ba7..a80b556033e740 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll index 2d5b30978aa221..e8646f9161ff38 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpName %[[#NAME_FSHL_FUNC_32:]] "spirv.llvm_fshl_i32" ; CHECK-SPIRV: OpName %[[#NAME_FSHL_FUNC_16:]] "spirv.llvm_fshl_i16" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll index 4cf5ca53a411b4..30a5a7ebf027b3 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpName %[[#NAME_FSHR_FUNC_32:]] "spirv.llvm_fshr_i32" ; CHECK-SPIRV: OpName %[[#NAME_FSHR_FUNC_16:]] "spirv.llvm_fshr_i16" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll index 5b700b7fcfee3e..0992aeb2a58280 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll @@ -1,5 +1,6 @@ ;; Make sure the backend doesn't crash if the input LLVM IR contains llvm.invariant.* intrinsics ; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK-NOT: OpFunctionParameter ; CHECK-NOT: OpFunctionCall diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll index e0c84ee3a3f1c1..0f6569418d6d50 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll index 12a4a86fa4a8be..c3f25c5ea110fa 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll index 459bc6bdcdaff8..238d39cb701efd 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll index 4f9cd29cd05d2a..22df4fba14228f 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll index 837bea0fbe6247..6203dd2cafd37a 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll index 475da2e1ec31ea..a3b05e5acc7738 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll index b525c849c3b59a..26cce2a91f1c19 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll index 0985be992ca74e..1194f6ecb393bf 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll index 1a700577e46b41..2bb78722c6f84d 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll index 90c6cf5562a924..3c5f5858866b97 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll index 4551fa31681d2b..b878e78e01f6eb 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll index a0d257bb131804..86bb4bdd582700 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll index ba5dba76aeecca..409dd3b69e55ec 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll index e16bde88ef5094..0845e81777db7f 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll index cf887bb358aca6..64259f34c6435d 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll index 7b8c05d9c98eda..00c82e21152d00 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s define spir_func float @Test(float %x, float %y) { entry: diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll index 5b59206ff7f2d3..530c5b4365060b 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll @@ -4,6 +4,9 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} + ; CHECK: OpExtInstImport "OpenCL.std" ; CHECK-DAG: OpName %[[#Foo:]] "foo" ; CHECK-DAG: OpName %[[#Bar:]] "bar" diff --git a/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll b/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll index 44b11f3ddb2731..dda5b0521a3c57 100644 --- a/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll +++ b/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: %[[#type_int32:]] = OpTypeInt 32 0 ; CHECK-SPIRV-DAG: %[[#type_int64:]] = OpTypeInt 64 0 diff --git a/llvm/test/CodeGen/SPIRV/multi_md.ll b/llvm/test/CodeGen/SPIRV/multi_md.ll index 6d8af7defd7526..8021d941b43cd5 100644 --- a/llvm/test/CodeGen/SPIRV/multi_md.ll +++ b/llvm/test/CodeGen/SPIRV/multi_md.ll @@ -2,6 +2,7 @@ ;; assertion. ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s %struct.my_struct_t = type { i8, i32 } diff --git a/llvm/test/CodeGen/SPIRV/no_capability_shader.ll b/llvm/test/CodeGen/SPIRV/no_capability_shader.ll index 954b7c83681bde..157ab583758948 100644 --- a/llvm/test/CodeGen/SPIRV/no_capability_shader.ll +++ b/llvm/test/CodeGen/SPIRV/no_capability_shader.ll @@ -1,6 +1,7 @@ ;; __kernel void sample_test(read_only image2d_t src, read_only image1d_buffer_t buff) {} ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-NOT: OpCapability Shader diff --git a/llvm/test/CodeGen/SPIRV/opaque_pointers.ll b/llvm/test/CodeGen/SPIRV/opaque_pointers.ll index db4d1b130b8523..5f156c67b45d86 100644 --- a/llvm/test/CodeGen/SPIRV/opaque_pointers.ll +++ b/llvm/test/CodeGen/SPIRV/opaque_pointers.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK ; CHECK-DAG: %[[#Int32Ty:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#PtrInt32Ty:]] = OpTypePointer Function %[[#Int32Ty]] diff --git a/llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll b/llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll index 46a7cf42494261..586564b08d5c81 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK-DAG: OpEntryPoint Kernel %[[#test_func:]] "test" ; CHECK-DAG: OpDecorate %[[#f2_decl:]] LinkageAttributes "BuiltInGlobalOffset" Import diff --git a/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_init.ll b/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_init.ll index 9d759a1cf47d07..a335e2600bbedb 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_init.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_init.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpEntryPoint Kernel %[[#f1:]] "writer" ; CHECK: OpEntryPoint Kernel %[[#f2:]] "reader" diff --git a/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_uninit.ll b/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_uninit.ll index fe02ba650aaa0f..48eea766cc26a7 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_uninit.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_uninit.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpEntryPoint Kernel %[[#f1:]] "global_check" %[[#var0:]] %[[#var1:]] %[[#var2:]] %[[#var3:]] ; CHECK: OpEntryPoint Kernel %[[#f2:]] "writer" %[[#var0:]] %[[#var1:]] %[[#var2:]] %[[#var3:]] diff --git a/llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll b/llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll index 562f5c7b6826e1..686fbd4eb3dc3b 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; REQUIRES: asserts diff --git a/llvm/test/CodeGen/SPIRV/opencl/get_global_id.ll b/llvm/test/CodeGen/SPIRV/opencl/get_global_id.ll index d6074191b3acb0..79b202b9b60fbe 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/get_global_id.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/get_global_id.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ;; The set of valid inputs for get_global_id depends on the runtime NDRange, ;; but inputs outside of [0, 2] always return 0. diff --git a/llvm/test/CodeGen/SPIRV/opencl/metadata/fp_contractions_metadata.ll b/llvm/test/CodeGen/SPIRV/opencl/metadata/fp_contractions_metadata.ll index 2b09f52f183be3..1225ba0c8ea7fe 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/metadata/fp_contractions_metadata.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/metadata/fp_contractions_metadata.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpEntryPoint Kernel %[[#ENTRY:]] "foo" ; CHECK-NOT: OpExecutionMode %[[#ENTRY]] ContractionOff diff --git a/llvm/test/CodeGen/SPIRV/opencl/metadata/no_fp_contractions_metadata.ll b/llvm/test/CodeGen/SPIRV/opencl/metadata/no_fp_contractions_metadata.ll index 10840125b9f61b..6689915b6a0143 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/metadata/no_fp_contractions_metadata.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/metadata/no_fp_contractions_metadata.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpEntryPoint Kernel %[[#ENTRY:]] "foo" ; CHECK: OpExecutionMode %[[#ENTRY]] ContractionOff diff --git a/llvm/test/CodeGen/SPIRV/opencl/vload2.ll b/llvm/test/CodeGen/SPIRV/opencl/vload2.ll index 592de33d4d3938..5e6a25ef1f87f8 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/vload2.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/vload2.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; This test only intends to check the vloadn builtin name resolution. ; The calls to the OpenCL builtins are not valid and will not pass SPIR-V validation. diff --git a/llvm/test/CodeGen/SPIRV/opencl/vstore2.ll b/llvm/test/CodeGen/SPIRV/opencl/vstore2.ll index 0ea14c7f25e877..d95ae972377573 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/vstore2.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/vstore2.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; This test only intends to check the vstoren builtin name resolution. ; The calls to the OpenCL builtins are not valid and will not pass SPIR-V validation. diff --git a/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll b/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll index d6cdcd7e20e8f2..cc188f3ade1198 100644 --- a/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll +++ b/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -print-after-all -o - 2>&1 | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -print-after-all -o - 2>&1 | FileCheck %s ; CHECK: *** IR Dump After SPIRV emit intrinsics (emit-intrinsics) *** diff --git a/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-divergent-spv_assign_ptr_type.ll b/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-divergent-spv_assign_ptr_type.ll index f728eda079860d..8d34a40326d70b 100644 --- a/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-divergent-spv_assign_ptr_type.ll +++ b/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-divergent-spv_assign_ptr_type.ll @@ -1,10 +1,11 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -print-after-all -o - 2>&1 | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -print-after-all -o - 2>&1 | FileCheck %s ; CHECK: *** IR Dump After SPIRV emit intrinsics (emit-intrinsics) *** define spir_kernel void @test_pointer_cast(ptr addrspace(1) %src) { -; CHECK-NOT: call void @llvm.spv.assign.ptr.type.p1(ptr addrspace(1) %src, metadata i8 undef, i32 1) -; CHECK: call void @llvm.spv.assign.ptr.type.p1(ptr addrspace(1) %src, metadata i32 0, i32 1) +; CHECK-NOT: call{{.*}} void @llvm.spv.assign.ptr.type.p1(ptr addrspace(1) %src, metadata i8 undef, i32 1) +; CHECK: call{{.*}} void @llvm.spv.assign.ptr.type.p1(ptr addrspace(1) %src, metadata i32 0, i32 1) %b = bitcast ptr addrspace(1) %src to ptr addrspace(1) %g = getelementptr inbounds i32, ptr addrspace(1) %b, i64 52 ret void diff --git a/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-duplicate-spv_assign_type.ll b/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-duplicate-spv_assign_type.ll index 7056b9cb1230dc..6ca3224f3950f5 100644 --- a/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-duplicate-spv_assign_type.ll +++ b/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-no-duplicate-spv_assign_type.ll @@ -1,11 +1,12 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -print-after-all -o - 2>&1 | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -print-after-all -o - 2>&1 | FileCheck %s ; CHECK: *** IR Dump After SPIRV emit intrinsics (emit-intrinsics) *** define spir_kernel void @test(ptr addrspace(1) %srcimg) { -; CHECK: call void @llvm.spv.assign.type.p1(ptr addrspace(1) %srcimg, metadata target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) undef) +; CHECK: call{{.*}} void @llvm.spv.assign.type.p1(ptr addrspace(1) %srcimg, metadata target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) undef) %call1 = call spir_func <2 x i32> @_Z13get_image_dim14ocl_image2d_ro(ptr addrspace(1) %srcimg) -; CHECK-NOT: call void @llvm.spv.assign.type.p1(ptr addrspace(1) %srcimg, metadata target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) undef) +; CHECK-NOT: call{{.*}} void @llvm.spv.assign.type.p1(ptr addrspace(1) %srcimg, metadata target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) undef) %call2 = call spir_func <2 x i32> @_Z13get_image_dim14ocl_image2d_ro(ptr addrspace(1) %srcimg) ret void ; CHECK: } diff --git a/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll b/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll index ac72ec28c37d9d..f9fe48df059eb7 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#VOID:]] = OpTypeVoid ; CHECK-DAG: %[[#FLOAT:]] = OpTypeFloat 32 diff --git a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll index 7fae6ca2c48cf1..b8770b6f607b38 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#TYCHAR:]] = OpTypeInt 8 0 ; CHECK-DAG: %[[#TYCHARPTR:]] = OpTypePointer Function %[[#TYCHAR]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll index 18752fdf843d20..4c85ef65b431d6 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#TYLONG:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#TYSTRUCTLONG:]] = OpTypeStruct %[[#TYLONG]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll index 202bcfbf2599a9..bb9859812ca9d0 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#TYLONG:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#TYLONGPTR:]] = OpTypePointer Function %[[#TYLONG]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll index 7e9c6214c2818a..4fd38c34c5acff 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: %[[#INT8:]] = OpTypeInt 8 0 ; CHECK: %[[#PTR1:]] = OpTypePointer CrossWorkgroup %[[#INT8]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll index fc999ba1a3cdac..f692829c8282c1 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: %[[#FLOAT32:]] = OpTypeFloat 32 ; CHECK: %[[#PTR:]] = OpTypePointer CrossWorkgroup %[[#FLOAT32]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll index 132f10262432b2..2cd171cee9d969 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#INT8:]] = OpTypeInt 8 0 ; CHECK-DAG: %[[#VEC3:]] = OpTypeVector %[[#INT8]] 3 diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll index d2a65917bfd659..b50f8ef95351d2 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll @@ -1,6 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#INT8:]] = OpTypeInt 8 0 ; CHECK-DAG: %[[#INT64:]] = OpTypeInt 64 0 diff --git a/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll b/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll index d0c64b4353ec68..22692b233c4fbb 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll @@ -6,6 +6,9 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} + ; CHECK: OpName %[[GlobalValue:.*]] "dev_global" ; CHECK-DAG: %[[TyI64:.*]] = OpTypeInt 64 0 ; CHECK-DAG: %[[TyStruct:.*]] = OpTypeStruct %[[TyI64]] %[[TyI64]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll index b4948b66aed86d..5a6fe7f6083c66 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#INT8:]] = OpTypeInt 8 0 ; CHECK-DAG: %[[#PTRINT8:]] = OpTypePointer CrossWorkgroup %[[#INT8]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll index a3a730ac67e782..fba8cf9dcb74ff 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#INT:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#PTR1:]] = OpTypePointer Function %[[#INT]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-mismatch.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-mismatch.ll index 46e315b2dc62a2..fc179cbf19f16d 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-mismatch.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-mismatch.ll @@ -1,4 +1,5 @@ ; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o - 2>&1 | FileCheck %s +; RUN: not llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Type mismatch {{.*}} diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll index b74a3449980d97..517683a3ca5241 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#IMAGE:]] = OpTypeImage %2 2D 0 0 0 0 Unknown ReadOnly diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll index a513d103970663..0bb265a7a70fc3 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} define spir_kernel void @test(ptr addrspace(1) %srcimg) { ; CHECK: %[[#VOID:]] = OpTypeVoid diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll index b8f205a68e5616..99f4c94db994f8 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#FLOAT32:]] = OpTypeFloat 32 ; CHECK-DAG: %[[#PTR1:]] = OpTypePointer Function %[[#FLOAT32]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll index 55bddfdad699b2..d988860ba97c85 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#CHAR:]] = OpTypeInt 8 ; CHECK-DAG: %[[#GLOBAL_PTR_CHAR:]] = OpTypePointer CrossWorkgroup %[[#CHAR]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll index 0d2a832c496b1b..c80b7ddcd3be65 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#CHAR:]] = OpTypeInt 8 ; CHECK-DAG: %[[#GLOBAL_PTR_CHAR:]] = OpTypePointer CrossWorkgroup %[[#CHAR]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll b/llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll index 1667abc51be9fc..95049bd4e2d065 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: %[[#INT8:]] = OpTypeInt 8 0 ; CHECK: %[[#PTR1:]] = OpTypePointer CrossWorkgroup %[[#INT8]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll b/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll index 639906af3a952f..3d1a5f8991dfcd 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spirv64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll b/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll index 6b684bf41bbb09..43b2c39befe435 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#VOID:]] = OpTypeVoid ; CHECK-DAG: %[[#INT32:]] = OpTypeInt 32 0 diff --git a/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll b/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll index 5adaf6f65688df..3e0567712a84df 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#CHAR:]] = OpTypeInt 8 ; CHECK-DAG: %[[#GLOBAL_PTR_CHAR:]] = OpTypePointer CrossWorkgroup %[[#CHAR]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll b/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll index e7ce3ef621e83a..430009b7de3978 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} define spir_kernel void @foo(ptr addrspace(1) %arg) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !4 { %var = alloca ptr addrspace(1), align 8 diff --git a/llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll b/llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll index 83234e3986c84f..b32291ed88e578 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#float:]] = OpTypeFloat 32 ; CHECK-DAG: %[[#pointer:]] = OpTypePointer CrossWorkgroup %[[#float]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll index b039f80860daf6..0741a88162333a 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV-DAG: OpName %[[ArgCum:.*]] "_arg_cum" ; CHECK-SPIRV-DAG: OpName %[[FunTest:.*]] "test" diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll index edb31ffeee8e86..e16faf7c43f722 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV-DAG: OpName %[[Foo:.*]] "foo" ; CHECK-SPIRV-DAG: %[[TyChar:.*]] = OpTypeInt 8 0 diff --git a/llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll b/llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll index f144418cf54259..9ac9faf9f42ce7 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll @@ -2,7 +2,9 @@ ; definitions, even though their LLVM function types are identical. ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: OpName %[[Fun32:.*]] "tp_arg_i32" ; CHECK-DAG: OpName %[[Fun64:.*]] "tp_arg_i64" diff --git a/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll b/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll index 034feed72dc7bc..dd0b8d9865aa1f 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} @Ptr = addrspace(1) global ptr addrspace(1) null @Init = private addrspace(2) constant i32 123 diff --git a/llvm/test/CodeGen/SPIRV/preprocess-metadata.ll b/llvm/test/CodeGen/SPIRV/preprocess-metadata.ll index 24e0851eb3833c..1916e39b9f5625 100644 --- a/llvm/test/CodeGen/SPIRV/preprocess-metadata.ll +++ b/llvm/test/CodeGen/SPIRV/preprocess-metadata.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ;; The purpose of this test is to check that some of OpenCL metadata are consumed ;; even if 'opencl.ocl.version' metadata is missed (i.e. LLVM IR was produced not diff --git a/llvm/test/CodeGen/SPIRV/printf.ll b/llvm/test/CodeGen/SPIRV/printf.ll index 483fc1f244e57c..5c8e1a3d890ce6 100644 --- a/llvm/test/CodeGen/SPIRV/printf.ll +++ b/llvm/test/CodeGen/SPIRV/printf.ll @@ -4,6 +4,9 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} + ; CHECK: %[[#ExtImport:]] = OpExtInstImport "OpenCL.std" ; CHECK: %[[#Char:]] = OpTypeInt 8 0 ; CHECK: %[[#CharPtr:]] = OpTypePointer UniformConstant %[[#Char]] diff --git a/llvm/test/CodeGen/SPIRV/pstruct.ll b/llvm/test/CodeGen/SPIRV/pstruct.ll index fd55e9b69e2609..ddc3f46fe23daa 100644 --- a/llvm/test/CodeGen/SPIRV/pstruct.ll +++ b/llvm/test/CodeGen/SPIRV/pstruct.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; TODO(#60133): Requires updates following opaque pointer migration. ; XFAIL: * diff --git a/llvm/test/CodeGen/SPIRV/read_image.ll b/llvm/test/CodeGen/SPIRV/read_image.ll index ede5994279d2ff..65b3a001409823 100644 --- a/llvm/test/CodeGen/SPIRV/read_image.ll +++ b/llvm/test/CodeGen/SPIRV/read_image.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: %[[#IntTy:]] = OpTypeInt ; CHECK-SPIRV: %[[#IVecTy:]] = OpTypeVector %[[#IntTy]] diff --git a/llvm/test/CodeGen/SPIRV/select-builtin.ll b/llvm/test/CodeGen/SPIRV/select-builtin.ll index 6717970d160fcf..327ef1e3209151 100644 --- a/llvm/test/CodeGen/SPIRV/select-builtin.ll +++ b/llvm/test/CodeGen/SPIRV/select-builtin.ll @@ -1,6 +1,8 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: OpSelect diff --git a/llvm/test/CodeGen/SPIRV/simple.ll b/llvm/test/CodeGen/SPIRV/simple.ll index 63c15968c72535..23a53473290d5e 100644 --- a/llvm/test/CodeGen/SPIRV/simple.ll +++ b/llvm/test/CodeGen/SPIRV/simple.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; Support of doubles is required. ; CHECK: OpCapability Float64 diff --git a/llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll b/llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll index d9145e8d9f0a94..717a5f66fd549e 100644 --- a/llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll +++ b/llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#float:]] = OpTypeFloat 32 diff --git a/llvm/test/CodeGen/SPIRV/spec_const_decoration.ll b/llvm/test/CodeGen/SPIRV/spec_const_decoration.ll index 485da19fd6da0a..3193ec1802aac4 100644 --- a/llvm/test/CodeGen/SPIRV/spec_const_decoration.ll +++ b/llvm/test/CodeGen/SPIRV/spec_const_decoration.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpDecorate %[[#SpecConst:]] SpecId 0 ; CHECK: %[[#SpecConst]] = OpSpecConstant %[[#]] 70 diff --git a/llvm/test/CodeGen/SPIRV/spirv-load-store.ll b/llvm/test/CodeGen/SPIRV/spirv-load-store.ll index 9188617312466d..83548fa9a121d4 100644 --- a/llvm/test/CodeGen/SPIRV/spirv-load-store.ll +++ b/llvm/test/CodeGen/SPIRV/spirv-load-store.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; Translate SPIR-V friendly OpLoad and OpStore calls ; CHECK-DAG: %[[#TYLONG:]] = OpTypeInt 32 0 diff --git a/llvm/test/CodeGen/SPIRV/struct.ll b/llvm/test/CodeGen/SPIRV/struct.ll index c3d2694cf929cc..51b7d1f06cac82 100644 --- a/llvm/test/CodeGen/SPIRV/struct.ll +++ b/llvm/test/CodeGen/SPIRV/struct.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s %struct.ST = type { i32, i32, i32 } diff --git a/llvm/test/CodeGen/SPIRV/switch-no-jump-table.ll b/llvm/test/CodeGen/SPIRV/switch-no-jump-table.ll index c9c0f17f0b91ef..2afde3b0d94802 100644 --- a/llvm/test/CodeGen/SPIRV/switch-no-jump-table.ll +++ b/llvm/test/CodeGen/SPIRV/switch-no-jump-table.ll @@ -2,6 +2,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: OpSwitch %[[#]] %[[Label:]] ; CHECK-4: OpBranch %[[Label]] diff --git a/llvm/test/CodeGen/SPIRV/token/token-type-preallocated-setup-arg.ll b/llvm/test/CodeGen/SPIRV/token/token-type-preallocated-setup-arg.ll index 42e59c726b6fdc..a02872b5a2f89f 100644 --- a/llvm/test/CodeGen/SPIRV/token/token-type-preallocated-setup-arg.ll +++ b/llvm/test/CodeGen/SPIRV/token/token-type-preallocated-setup-arg.ll @@ -1,6 +1,7 @@ ; Example of token usage is from https://llvm.org/docs/LangRef.html (Preallocated Operand Bundles) ; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o - 2>&1 | FileCheck %s +; RUN: not llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - 2>&1 | FileCheck %s ; CHECK: A token is encountered but SPIR-V without extensions does not support token type diff --git a/llvm/test/CodeGen/SPIRV/token/token-type-requires-extension.ll b/llvm/test/CodeGen/SPIRV/token/token-type-requires-extension.ll index ee545a77e5d68f..490f86320282fa 100644 --- a/llvm/test/CodeGen/SPIRV/token/token-type-requires-extension.ll +++ b/llvm/test/CodeGen/SPIRV/token/token-type-requires-extension.ll @@ -1,4 +1,5 @@ ; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o - 2>&1 | FileCheck %s +; RUN: not llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - 2>&1 | FileCheck %s ; CHECK: A token is encountered but SPIR-V without extensions does not support token type diff --git a/llvm/test/CodeGen/SPIRV/transcoding/BitReversePref.ll b/llvm/test/CodeGen/SPIRV/transcoding/BitReversePref.ll index 11b0578a0c9c07..8de3e34cc0d7d1 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/BitReversePref.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/BitReversePref.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: OpDecorate %[[#FUNC_NAME:]] LinkageAttributes "_Z10BitReversei" ; CHECK-NOT: OpBitReverse diff --git a/llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll b/llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll index 65c992c9b28ed3..eb5aaf7347bb7a 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll @@ -19,7 +19,9 @@ ;; bash$ $PATH_TO_GEN/bin/clang -cc1 -x cl -cl-std=CL2.0 -triple spir64-unknown-unknown -emit-llvm -include opencl-20.h BuildNDRange_2.cl -o BuildNDRange_2.ll ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; TODO(#60133): Requires updates following opaque pointer migration. ; XFAIL: * diff --git a/llvm/test/CodeGen/SPIRV/transcoding/DecorationAlignment.ll b/llvm/test/CodeGen/SPIRV/transcoding/DecorationAlignment.ll index d4fc5c3280b714..28459d9496a13f 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/DecorationAlignment.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/DecorationAlignment.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: OpDecorate %[[#ALIGNMENT:]] Alignment 16 ; CHECK-SPIRV: %[[#ALIGNMENT]] = OpFunctionParameter %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpImageQuerySize.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpImageQuerySize.ll index 0c1f8eaa34a408..db16c91f5ca01f 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpImageQuerySize.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpImageQuerySize.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ;; Check conversion of get_image_width, get_image_height, get_image_depth, ;; get_image_array_size, and get_image_dim OCL built-ins. diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll index cb41aad2a0c5fa..91947dbec1403a 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpName %[[#v:]] "v" ; CHECK-SPIRV: OpName %[[#index:]] "index" diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_cmpxchg.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_cmpxchg.ll index 417b89eb36f0f5..4c1894eae6f1dc 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_cmpxchg.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_cmpxchg.ll @@ -1,5 +1,6 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; This test checks that the backend is capable to correctly translate ;; atomic_cmpxchg OpenCL C 1.2 built-in function [1] into corresponding SPIR-V diff --git a/llvm/test/CodeGen/SPIRV/transcoding/SpecConstantComposite.ll b/llvm/test/CodeGen/SPIRV/transcoding/SpecConstantComposite.ll index e6f5c7ddb078d7..ddef6deeee8dd6 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/SpecConstantComposite.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/SpecConstantComposite.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpDecorate %[[#SC3:]] SpecId 3 ; CHECK-SPIRV-DAG: OpDecorate %[[#SC4:]] SpecId 4 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/atomic_flag.ll b/llvm/test/CodeGen/SPIRV/transcoding/atomic_flag.ll index 20204acb1ef584..b09e655c7aa04f 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/atomic_flag.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/atomic_flag.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; Types: ; CHECK-DAG: %[[#INT:]] = OpTypeInt 32 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/bitcast.ll b/llvm/test/CodeGen/SPIRV/transcoding/bitcast.ll index 2c0fc393b135a2..a27781c9199fbb 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/bitcast.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/bitcast.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; Check the bitcast is translated back to bitcast diff --git a/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_arithmetics.ll b/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_arithmetics.ll index d0c4dff43121cc..238559d1c85d63 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_arithmetics.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_arithmetics.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; The IR was generated from the following source: ;; #include @@ -32,9 +34,9 @@ ; CHECK-SPIRV-DAG: OpDecorate %[[#GlobalInvocationId]] Constant ; CHECK-SPIRV-DAG: OpDecorate %[[#GlobalSize]] Constant ; CHECK-SPIRV-DAG: OpDecorate %[[#GlobalOffset]] Constant -; CHECK-SPIRV-DAG: OpDecorate %[[#GlobalOffset]] LinkageAttributes "__spirv_BuiltInGlobalOffset" Import -; CHECK-SPIRV-DAG: OpDecorate %[[#GlobalSize]] LinkageAttributes "__spirv_BuiltInGlobalSize" Import -; CHECK-SPIRV-DAG: OpDecorate %[[#GlobalInvocationId]] LinkageAttributes "__spirv_BuiltInGlobalInvocationId" Import +; CHECK-SPIRV-DAG: OpDecorate %[[#GlobalOffset]] LinkageAttributes "__spirv_BuiltInGlobalOffset" Import +; CHECK-SPIRV-DAG: OpDecorate %[[#GlobalSize]] LinkageAttributes "__spirv_BuiltInGlobalSize" Import +; CHECK-SPIRV-DAG: OpDecorate %[[#GlobalInvocationId]] LinkageAttributes "__spirv_BuiltInGlobalInvocationId" Import %"class._ZTSN2cl4sycl5rangeILi2EEE.cl::sycl::range" = type { %"class._ZTSN2cl4sycl6detail5arrayILi2EEE.cl::sycl::detail::array" } %"class._ZTSN2cl4sycl6detail5arrayILi2EEE.cl::sycl::detail::array" = type { [2 x i64] } diff --git a/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_opt.ll b/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_opt.ll index 3885f070231442..16018d66ac2dbd 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_opt.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_opt.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; The IR was generated from the following source: ;; #include diff --git a/llvm/test/CodeGen/SPIRV/transcoding/check_ro_qualifier.ll b/llvm/test/CodeGen/SPIRV/transcoding/check_ro_qualifier.ll index 824ca1b2d69249..55e31d85bc7ff0 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/check_ro_qualifier.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/check_ro_qualifier.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: %[[#IMAGE_TYPE:]] = OpTypeImage ; CHECK-SPIRV: %[[#IMAGE_ARG:]] = OpFunctionParameter %[[#IMAGE_TYPE]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fmod.ll b/llvm/test/CodeGen/SPIRV/transcoding/fmod.ll index 683b5c24f5b712..bd7cf61690cbd2 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/fmod.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/fmod.ll @@ -2,7 +2,9 @@ ;; { out = fmod( in1, in2 ); } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: %[[#]] = OpExtInst %[[#]] %[[#]] fmod %[[#]] %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/get_image_num_mip_levels.ll b/llvm/test/CodeGen/SPIRV/transcoding/get_image_num_mip_levels.ll index fd241963d1e98d..724e49cce8a739 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/get_image_num_mip_levels.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/get_image_num_mip_levels.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; Types: ; CHECK-DAG: %[[#INT:]] = OpTypeInt 32 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/image_get_size_with_access_qualifiers.ll b/llvm/test/CodeGen/SPIRV/transcoding/image_get_size_with_access_qualifiers.ll index a39a3ce038d6ab..5597cd851d7d46 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/image_get_size_with_access_qualifiers.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/image_get_size_with_access_qualifiers.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: %[[#IntTyID:]] = OpTypeInt ; CHECK-SPIRV-DAG: %[[#VoidTyID:]] = OpTypeVoid diff --git a/llvm/test/CodeGen/SPIRV/transcoding/isequal.ll b/llvm/test/CodeGen/SPIRV/transcoding/isequal.ll index c5f3f9e1e2e74c..b1faa86ab3fc6e 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/isequal.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/isequal.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV-NOT: OpSConvert diff --git a/llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll b/llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll index 89fa93b4fcda1c..56f0d7a661475d 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll @@ -2,6 +2,8 @@ ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64 +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#i64:]] = OpTypeInt 64 0 ; CHECK-DAG: %[[#i8:]] = OpTypeInt 8 0 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/memory_access.ll b/llvm/test/CodeGen/SPIRV/transcoding/memory_access.ll index fc757112f168c8..02b3895cf81ec4 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/memory_access.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/memory_access.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-NOT: OpStore %[[#]] %[[#]] Volatile Aligned 8 ; CHECK-SPIRV: OpStore %[[#]] %[[#]] Volatile|Aligned 8 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll index d44e32141db75b..027571f2e177f4 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpTypeInt 16 ; CHECK: OpIAdd diff --git a/llvm/test/CodeGen/SPIRV/transcoding/readonly.ll b/llvm/test/CodeGen/SPIRV/transcoding/readonly.ll index 051d80319ee04d..8a14eeb45aee37 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/readonly.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/readonly.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpDecorate %[[#PARAM:]] FuncParamAttr NoWrite ; CHECK-SPIRV: %[[#PARAM]] = OpFunctionParameter %{{.*}} diff --git a/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll b/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll index fe0d96f2773ec6..a883a1d7b63d92 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll @@ -4,6 +4,9 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} + ; CHECK-DAG: %[[#TyEvent:]] = OpTypeEvent ; CHECK-DAG: %[[#TyStruct:]] = OpTypeStruct %[[#TyEvent]] ; CHECK-DAG: %[[#ConstEvent:]] = OpConstantNull %[[#TyEvent]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll b/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll index 04fb39118034c8..f9c6ea08032f52 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll @@ -2,6 +2,8 @@ ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-64 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-64 +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV-64-DAG: %[[#i64:]] = OpTypeInt 64 0 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll index 6cc9e0f3329287..a230e74083695f 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll @@ -156,6 +156,7 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability GroupNonUniformBallot diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_clustered_reduce.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_clustered_reduce.ll index 22bf747490da87..35e0b2dfcd2bbd 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_clustered_reduce.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_clustered_reduce.ll @@ -174,6 +174,7 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability GroupNonUniformClustered diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll index f605d0c42d34f7..ee403f612a4b9c 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll @@ -180,6 +180,7 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: %[[#char:]] = OpTypeInt 8 0 ; CHECK-SPIRV-DAG: %[[#short:]] = OpTypeInt 16 0 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll index 8f4910ff512f8d..d7f3bfc61c1a50 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll @@ -316,6 +316,7 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability GroupNonUniformArithmetic diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll index 9654de6b84132c..50f089b8215bbb 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll @@ -5,7 +5,7 @@ ;; } ;; ;; kernel void testSubGroupNonUniformAll(global int* dst) { -;; dst[0] = sub_group_non_uniform_all(0); +;; dst[0] = sub_group_non_uniform_all(0); ;; } ;; ;; kernel void testSubGroupNonUniformAny(global int* dst) { @@ -62,6 +62,7 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability GroupNonUniformVote diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll index 9ed5c78bd0ede6..24a13fc2ecba81 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll @@ -80,6 +80,7 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability GroupNonUniformShuffle diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll index 3ad2c2d87549c8..8576b22a1337a7 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll @@ -80,6 +80,7 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability GroupNonUniformShuffleRelative diff --git a/llvm/test/CodeGen/SPIRV/transcoding/vec_type_hint.ll b/llvm/test/CodeGen/SPIRV/transcoding/vec_type_hint.ll index 1d512a894d540a..9e7f83ec72301c 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/vec_type_hint.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/vec_type_hint.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ;; kernel ;; __attribute__((vec_type_hint(float4))) diff --git a/llvm/test/CodeGen/SPIRV/types/or-i1.ll b/llvm/test/CodeGen/SPIRV/types/or-i1.ll index 32dc258d85554f..8eed7b2b4dc73e 100644 --- a/llvm/test/CodeGen/SPIRV/types/or-i1.ll +++ b/llvm/test/CodeGen/SPIRV/types/or-i1.ll @@ -1,5 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#BOOL:]] = OpTypeBool ; CHECK: %[[#BOOL:]] = OpLogicalOr %[[#BOOL]] %[[#]] %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll b/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll index 6f793fc5d030e6..ff0db518dc6075 100644 --- a/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll +++ b/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll @@ -1,4 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=SPV +; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=SPV ;; The IR was generated from the following source: ;; void __kernel K(global float* A, int B) { diff --git a/llvm/test/CodeGen/SPIRV/unnamed-global.ll b/llvm/test/CodeGen/SPIRV/unnamed-global.ll index d2cd4ea8cafc36..5c35ebeb5b6b69 100644 --- a/llvm/test/CodeGen/SPIRV/unnamed-global.ll +++ b/llvm/test/CodeGen/SPIRV/unnamed-global.ll @@ -1,5 +1,6 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: %[[TyInt:.*]] = OpTypeInt 8 0 ; CHECK: %[[ConstInt:.*]] = OpConstant %[[TyInt]] 123 From 516e14cdb6e85f6bb9146eb38b9209956862369e Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 5 Jun 2024 17:32:18 +0100 Subject: [PATCH 12/15] Revert spurios testing noise, AMDGCN SPIRV is still SPIRV. --- llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll | 1 - llvm/test/CodeGen/SPIRV/CheckCapKernelWithoutKernel.ll | 1 - llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll | 1 - llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_bool.ll | 1 - llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll | 1 - llvm/test/CodeGen/SPIRV/SampledImageRetType.ll | 1 - .../CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll | 1 - llvm/test/CodeGen/SPIRV/TruncToBool.ll | 1 - llvm/test/CodeGen/SPIRV/assume.ll | 2 -- llvm/test/CodeGen/SPIRV/atomicrmw.ll | 1 - llvm/test/CodeGen/SPIRV/basic_float_types.ll | 2 -- llvm/test/CodeGen/SPIRV/basic_int_types.ll | 2 -- llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll | 1 - llvm/test/CodeGen/SPIRV/bitcast.ll | 2 -- llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll | 1 - llvm/test/CodeGen/SPIRV/branching/OpSwitch64.ll | 1 - .../test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll | 1 - llvm/test/CodeGen/SPIRV/capability-Int64Atomics-store.ll | 1 - llvm/test/CodeGen/SPIRV/capability-Int64Atomics.ll | 1 - llvm/test/CodeGen/SPIRV/capability-kernel.ll | 2 -- llvm/test/CodeGen/SPIRV/const-composite.ll | 2 -- llvm/test/CodeGen/SPIRV/constant/global-constants.ll | 1 - llvm/test/CodeGen/SPIRV/empty-module.ll | 3 --- llvm/test/CodeGen/SPIRV/empty-opencl64.ll | 2 -- llvm/test/CodeGen/SPIRV/event_no_group_cap.ll | 1 - llvm/test/CodeGen/SPIRV/execution-mode-per-entry-point.ll | 3 --- llvm/test/CodeGen/SPIRV/expect.ll | 2 -- .../extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll | 3 +-- .../SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll | 3 --- .../SPV_INTEL_variable_length_array/vararr_spec_const.ll | 2 -- .../extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll | 2 -- llvm/test/CodeGen/SPIRV/fence.ll | 2 -- .../CodeGen/SPIRV/function/multiple-anonymous-functions.ll | 1 - llvm/test/CodeGen/SPIRV/half_extension.ll | 1 - llvm/test/CodeGen/SPIRV/half_no_extension.ll | 1 - llvm/test/CodeGen/SPIRV/image.ll | 1 - llvm/test/CodeGen/SPIRV/image/sampler.ll | 2 -- llvm/test/CodeGen/SPIRV/instructions/select-phi.ll | 3 --- llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll | 3 --- llvm/test/CodeGen/SPIRV/instructions/select.ll | 3 --- llvm/test/CodeGen/SPIRV/linkage/extern-weak-linkage.ll | 3 --- llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll | 1 - llvm/test/CodeGen/SPIRV/literals.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/expect.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll | 1 - .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll | 2 -- .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll | 2 -- .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll | 2 -- .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll | 2 -- .../SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll | 2 -- .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll | 2 -- .../SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll | 2 -- .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll | 2 -- .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll | 2 -- .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll | 2 -- .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll | 2 -- .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll | 2 -- .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll | 2 -- .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll | 2 -- .../CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll | 2 -- llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll | 1 - llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll | 3 --- llvm/test/CodeGen/SPIRV/lshr-constexpr.ll | 1 - llvm/test/CodeGen/SPIRV/multi_md.ll | 1 - llvm/test/CodeGen/SPIRV/no_capability_shader.ll | 1 - llvm/test/CodeGen/SPIRV/opaque_pointers.ll | 1 - llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll | 1 - .../test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_init.ll | 1 - .../CodeGen/SPIRV/opencl/basic/progvar_prog_scope_uninit.ll | 1 - .../CodeGen/SPIRV/opencl/device_execution/execute_block.ll | 1 - llvm/test/CodeGen/SPIRV/opencl/get_global_id.ll | 1 - .../CodeGen/SPIRV/opencl/metadata/fp_contractions_metadata.ll | 1 - .../SPIRV/opencl/metadata/no_fp_contractions_metadata.ll | 1 - llvm/test/CodeGen/SPIRV/opencl/vload2.ll | 1 - llvm/test/CodeGen/SPIRV/opencl/vstore2.ll | 1 - ...SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll | 1 - llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll | 2 -- .../CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll | 3 --- .../pointers/kernel-argument-builtin-vload-type-discrapency.ll | 2 -- .../SPIRV/pointers/kernel-argument-pointer-addressspace.ll | 2 -- .../kernel-argument-pointer-type-deduction-mismatch.ll | 1 - ...el-argument-pointer-type-deduction-no-bitcast-to-generic.ll | 2 -- .../kernel-argument-pointer-type-deduction-no-metadata.ll | 2 -- .../CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll | 2 -- .../pointers/kernel-argument-ptr-i8-default-element-type.ll | 2 -- .../CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll | 2 -- .../SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll | 2 -- .../SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll | 2 -- .../test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll | 2 -- llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll | 2 -- llvm/test/CodeGen/SPIRV/preprocess-metadata.ll | 1 - llvm/test/CodeGen/SPIRV/printf.ll | 3 --- llvm/test/CodeGen/SPIRV/pstruct.ll | 1 - llvm/test/CodeGen/SPIRV/read_image.ll | 1 - llvm/test/CodeGen/SPIRV/select-builtin.ll | 2 -- llvm/test/CodeGen/SPIRV/simple.ll | 2 -- llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll | 1 - llvm/test/CodeGen/SPIRV/spec_const_decoration.ll | 1 - llvm/test/CodeGen/SPIRV/spirv-load-store.ll | 2 -- llvm/test/CodeGen/SPIRV/struct.ll | 1 - llvm/test/CodeGen/SPIRV/switch-no-jump-table.ll | 1 - .../CodeGen/SPIRV/token/token-type-preallocated-setup-arg.ll | 1 - llvm/test/CodeGen/SPIRV/token/token-type-requires-extension.ll | 1 - llvm/test/CodeGen/SPIRV/transcoding/BitReversePref.ll | 2 -- llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll | 2 -- llvm/test/CodeGen/SPIRV/transcoding/DecorationAlignment.ll | 2 -- llvm/test/CodeGen/SPIRV/transcoding/OpImageQuerySize.ll | 1 - .../CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll | 1 - llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_cmpxchg.ll | 1 - llvm/test/CodeGen/SPIRV/transcoding/SpecConstantComposite.ll | 1 - llvm/test/CodeGen/SPIRV/transcoding/atomic_flag.ll | 2 -- llvm/test/CodeGen/SPIRV/transcoding/bitcast.ll | 2 -- .../test/CodeGen/SPIRV/transcoding/builtin_vars_arithmetics.ll | 2 -- llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_opt.ll | 2 -- llvm/test/CodeGen/SPIRV/transcoding/check_ro_qualifier.ll | 2 -- llvm/test/CodeGen/SPIRV/transcoding/fmod.ll | 2 -- .../test/CodeGen/SPIRV/transcoding/get_image_num_mip_levels.ll | 2 -- .../SPIRV/transcoding/image_get_size_with_access_qualifiers.ll | 1 - llvm/test/CodeGen/SPIRV/transcoding/isequal.ll | 2 -- llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll | 2 -- llvm/test/CodeGen/SPIRV/transcoding/memory_access.ll | 1 - llvm/test/CodeGen/SPIRV/transcoding/non32.ll | 1 - llvm/test/CodeGen/SPIRV/transcoding/readonly.ll | 1 - llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll | 3 --- .../SPIRV/transcoding/spirv-private-array-initialization.ll | 2 -- llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll | 1 - .../CodeGen/SPIRV/transcoding/sub_group_clustered_reduce.ll | 1 - .../test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll | 1 - .../SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll | 1 - .../CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll | 1 - llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll | 1 - .../CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll | 1 - llvm/test/CodeGen/SPIRV/transcoding/vec_type_hint.ll | 1 - llvm/test/CodeGen/SPIRV/types/or-i1.ll | 2 -- llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll | 1 - llvm/test/CodeGen/SPIRV/unnamed-global.ll | 1 - 160 files changed, 1 insertion(+), 252 deletions(-) diff --git a/llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll b/llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll index 0b9413e904d352..88565082ef01ef 100644 --- a/llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll +++ b/llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ;; Types: ; CHECK: %[[#F32:]] = OpTypeFloat 32 diff --git a/llvm/test/CodeGen/SPIRV/CheckCapKernelWithoutKernel.ll b/llvm/test/CodeGen/SPIRV/CheckCapKernelWithoutKernel.ll index d65c8891de8663..c61b3d90eb25a1 100644 --- a/llvm/test/CodeGen/SPIRV/CheckCapKernelWithoutKernel.ll +++ b/llvm/test/CodeGen/SPIRV/CheckCapKernelWithoutKernel.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s @a = addrspace(2) constant i32 1, align 4 diff --git a/llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll b/llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll index 793c6295ba8ed2..a6f172a81dc7c8 100644 --- a/llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll +++ b/llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; TODO(#60133): Requires updates following opaque pointer migration. ; XFAIL: * diff --git a/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_bool.ll b/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_bool.ll index d8004a20268f03..735b35d757e7d8 100644 --- a/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_bool.ll +++ b/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_bool.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpFOrdGreaterThanEqual ; CHECK-SPIRV-NOT: OpSelect diff --git a/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll b/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll index fff87d5dff769b..86581a54684058 100644 --- a/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll +++ b/llvm/test/CodeGen/SPIRV/FOrdGreaterThanEqual_int.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: %[[#result:]] = OpFOrdGreaterThanEqual %[[#]] %[[#]] %[[#]] ; CHECK-SPIRV: %[[#]] = OpSelect %[[#]] %[[#result]] %[[#]] %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll b/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll index 1f708de03f9a7c..7af5876a023e5b 100644 --- a/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll +++ b/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#image1d_t:]] = OpTypeImage ; CHECK: %[[#sampler_t:]] = OpTypeSampler diff --git a/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll b/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll index 77c7bf3f8891d7..6e414f79bdde54 100644 --- a/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll +++ b/llvm/test/CodeGen/SPIRV/SpecConstants/bool-spirv-specconstant.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpDecorate %[[#BOOL_CONST:]] SpecId [[#]] ; CHECK: %[[#BOOL_TY:]] = OpTypeBool diff --git a/llvm/test/CodeGen/SPIRV/TruncToBool.ll b/llvm/test/CodeGen/SPIRV/TruncToBool.ll index 540c4899a7e13a..6682c23f34e969 100644 --- a/llvm/test/CodeGen/SPIRV/TruncToBool.ll +++ b/llvm/test/CodeGen/SPIRV/TruncToBool.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpBitwiseAnd ; CHECK-SPIRV-NEXT: OpINotEqual diff --git a/llvm/test/CodeGen/SPIRV/assume.ll b/llvm/test/CodeGen/SPIRV/assume.ll index 37b40b1fe328db..fbf12ef184a891 100644 --- a/llvm/test/CodeGen/SPIRV/assume.ll +++ b/llvm/test/CodeGen/SPIRV/assume.ll @@ -2,8 +2,6 @@ ; RUN: llc -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=EXT,CHECK %s ; RUN: llc -mtriple=spirv32-unknown-unknown < %s | FileCheck --check-prefixes=NOEXT,CHECK %s ; RUN: llc -mtriple=spirv64-unknown-unknown < %s | FileCheck --check-prefixes=NOEXT,CHECK %s -; RUN: llc -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=EXT,CHECK %s -; RUN: llc -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=EXT,CHECK %s ; EXT: OpCapability ExpectAssumeKHR ; EXT-NEXT: OpExtension "SPV_KHR_expect_assume" diff --git a/llvm/test/CodeGen/SPIRV/atomicrmw.ll b/llvm/test/CodeGen/SPIRV/atomicrmw.ll index 0b87d32164e79a..81484771575367 100644 --- a/llvm/test/CodeGen/SPIRV/atomicrmw.ll +++ b/llvm/test/CodeGen/SPIRV/atomicrmw.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#Int:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#Scope_Device:]] = OpConstant %[[#Int]] 1{{$}} diff --git a/llvm/test/CodeGen/SPIRV/basic_float_types.ll b/llvm/test/CodeGen/SPIRV/basic_float_types.ll index 66bc2ac79ea5cb..1c7a8a851f59c6 100644 --- a/llvm/test/CodeGen/SPIRV/basic_float_types.ll +++ b/llvm/test/CodeGen/SPIRV/basic_float_types.ll @@ -1,9 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} define void @main() { entry: diff --git a/llvm/test/CodeGen/SPIRV/basic_int_types.ll b/llvm/test/CodeGen/SPIRV/basic_int_types.ll index 496237125e7522..6bfc99025ccba5 100644 --- a/llvm/test/CodeGen/SPIRV/basic_int_types.ll +++ b/llvm/test/CodeGen/SPIRV/basic_int_types.ll @@ -1,9 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-amd-amdhsa %s -o - -filetype=obj | spirv-val %} define void @main() { entry: diff --git a/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll b/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll index 47b9937572fe4e..3778d897929188 100644 --- a/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll +++ b/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll @@ -2,7 +2,6 @@ ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - --filetype=obj | spirv-dis | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - --filetype=obj | spirv-dis | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - --filetype=obj | spirv-dis | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - --filetype=obj | spirv-dis | FileCheck %s define void @main() { entry: diff --git a/llvm/test/CodeGen/SPIRV/bitcast.ll b/llvm/test/CodeGen/SPIRV/bitcast.ll index dc9010ce821cd6..242c5a46583c22 100644 --- a/llvm/test/CodeGen/SPIRV/bitcast.ll +++ b/llvm/test/CodeGen/SPIRV/bitcast.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV-DAG: %[[#TyInt32:]] = OpTypeInt 32 0 ; CHECK-SPIRV-DAG: %[[#TyInt16:]] = OpTypeInt 16 0 diff --git a/llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll b/llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll index 6f06eff18fc343..fdf4e4ddbefb7c 100644 --- a/llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll +++ b/llvm/test/CodeGen/SPIRV/branching/OpSwitch32.ll @@ -15,7 +15,6 @@ ;; bash$ clang -cc1 -triple spir64-unknown-unknown -x cl -cl-std=CL2.0 -O0 -include opencl.h -emit-llvm OpSwitch.cl -o test_32.ll ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpSwitch %[[#]] %[[#]] 0 %[[#]] 1 %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/branching/OpSwitch64.ll b/llvm/test/CodeGen/SPIRV/branching/OpSwitch64.ll index 5063fa2bbc3ce8..5e4f1f14f8f917 100644 --- a/llvm/test/CodeGen/SPIRV/branching/OpSwitch64.ll +++ b/llvm/test/CodeGen/SPIRV/branching/OpSwitch64.ll @@ -18,7 +18,6 @@ ;; bash$ clang -cc1 -triple spir64-unknown-unknown -x cl -cl-std=CL2.0 -O0 -include opencl.h -emit-llvm OpSwitch.cl -o test_64.ll ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpSwitch %[[#]] %[[#]] 0 0 %[[#]] 1 0 %[[#]] 1 5 %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll b/llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll index 01c7811baf70e5..19c11ff64476b9 100644 --- a/llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll +++ b/llvm/test/CodeGen/SPIRV/branching/Two_OpSwitch_same_register.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV define spir_kernel void @test_two_switch_same_register(i32 %value) { ; CHECK-SPIRV: OpSwitch %[[#REGISTER:]] %[[#DEFAULT1:]] 1 %[[#CASE1:]] 0 %[[#CASE2:]] diff --git a/llvm/test/CodeGen/SPIRV/capability-Int64Atomics-store.ll b/llvm/test/CodeGen/SPIRV/capability-Int64Atomics-store.ll index 0c644c05549a69..ee626db8d9672e 100644 --- a/llvm/test/CodeGen/SPIRV/capability-Int64Atomics-store.ll +++ b/llvm/test/CodeGen/SPIRV/capability-Int64Atomics-store.ll @@ -7,7 +7,6 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpCapability Int64Atomics diff --git a/llvm/test/CodeGen/SPIRV/capability-Int64Atomics.ll b/llvm/test/CodeGen/SPIRV/capability-Int64Atomics.ll index 32ddd5579e972b..65047f8c6e48f4 100644 --- a/llvm/test/CodeGen/SPIRV/capability-Int64Atomics.ll +++ b/llvm/test/CodeGen/SPIRV/capability-Int64Atomics.ll @@ -7,7 +7,6 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpCapability Int64Atomics diff --git a/llvm/test/CodeGen/SPIRV/capability-kernel.ll b/llvm/test/CodeGen/SPIRV/capability-kernel.ll index 053e9ff52c59a2..fea19511d4fdcc 100644 --- a/llvm/test/CodeGen/SPIRV/capability-kernel.ll +++ b/llvm/test/CodeGen/SPIRV/capability-kernel.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: OpCapability Addresses diff --git a/llvm/test/CodeGen/SPIRV/const-composite.ll b/llvm/test/CodeGen/SPIRV/const-composite.ll index d54563436e950f..4e304bb9516702 100644 --- a/llvm/test/CodeGen/SPIRV/const-composite.ll +++ b/llvm/test/CodeGen/SPIRV/const-composite.ll @@ -4,9 +4,7 @@ ; and also takes part in a composite constant creation. ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: %[[#type_int32:]] = OpTypeInt 32 0 ; CHECK-SPIRV: %[[#const1:]] = OpConstant %[[#type_int32]] 1 diff --git a/llvm/test/CodeGen/SPIRV/constant/global-constants.ll b/llvm/test/CodeGen/SPIRV/constant/global-constants.ll index 2ce92541ae834c..74e28cbe7acb17 100644 --- a/llvm/test/CodeGen/SPIRV/constant/global-constants.ll +++ b/llvm/test/CodeGen/SPIRV/constant/global-constants.ll @@ -1,6 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} @global = addrspace(1) constant i32 1 ; OpenCL global memory @constant = addrspace(2) constant i32 2 ; OpenCL constant memory diff --git a/llvm/test/CodeGen/SPIRV/empty-module.ll b/llvm/test/CodeGen/SPIRV/empty-module.ll index 56d94b01abdf92..b7cea042ee5ddc 100644 --- a/llvm/test/CodeGen/SPIRV/empty-module.ll +++ b/llvm/test/CodeGen/SPIRV/empty-module.ll @@ -4,9 +4,6 @@ ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOOCL ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} - ; CHECK-DAG: OpCapability Linkage ; CHECK-NOOCL-DAG: OpCapability Shader ; CHECK-OCL-DAG: OpCapability Addresses diff --git a/llvm/test/CodeGen/SPIRV/empty-opencl64.ll b/llvm/test/CodeGen/SPIRV/empty-opencl64.ll index aa5370bf95d4d1..4eaa2e4af0fc76 100644 --- a/llvm/test/CodeGen/SPIRV/empty-opencl64.ll +++ b/llvm/test/CodeGen/SPIRV/empty-opencl64.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; FIXME: ensure Magic Number, version number, generator's magic number, "bound" and "schema" are at least present diff --git a/llvm/test/CodeGen/SPIRV/event_no_group_cap.ll b/llvm/test/CodeGen/SPIRV/event_no_group_cap.ll index 50264ea0de21be..af4ac7cf44500b 100644 --- a/llvm/test/CodeGen/SPIRV/event_no_group_cap.ll +++ b/llvm/test/CodeGen/SPIRV/event_no_group_cap.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; __kernel void test_fn( const __global char *src) ; { diff --git a/llvm/test/CodeGen/SPIRV/execution-mode-per-entry-point.ll b/llvm/test/CodeGen/SPIRV/execution-mode-per-entry-point.ll index ba085e35366098..6fd1abd2be59ab 100644 --- a/llvm/test/CodeGen/SPIRV/execution-mode-per-entry-point.ll +++ b/llvm/test/CodeGen/SPIRV/execution-mode-per-entry-point.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: OpMemoryModel ; CHECK-DAG: OpEntryPoint Kernel %[[#ENTRY1:]] "foo1" @@ -12,7 +10,6 @@ ; CHECK: OpSource ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECKN -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECKN ; CHECKN: OpMemoryModel ; CHECKN-COUNT-2: OpEntryPoint Kernel diff --git a/llvm/test/CodeGen/SPIRV/expect.ll b/llvm/test/CodeGen/SPIRV/expect.ll index 3d4829184f3a9a..82c1ec7dc916cf 100644 --- a/llvm/test/CodeGen/SPIRV/expect.ll +++ b/llvm/test/CodeGen/SPIRV/expect.ll @@ -1,9 +1,7 @@ ; RUN: llc -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=CHECK,EXT %s ; RUN: llc -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=CHECK,EXT %s -; RUN: llc -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_KHR_expect_assume < %s | FileCheck --check-prefixes=CHECK,EXT %s ; RUN: llc -mtriple=spirv32-unknown-unknown < %s | FileCheck --check-prefixes=CHECK,NOEXT %s ; RUN: llc -mtriple=spirv64-unknown-unknown < %s | FileCheck --check-prefixes=CHECK,NOEXT %s -; RUN: llc -mtriple=spirv64-amd-amdhsa < %s | FileCheck --check-prefixes=CHECK,NOEXT %s ; EXT: OpCapability ExpectAssumeKHR ; EXT-NEXT: OpExtension "SPV_KHR_expect_assume" diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll index e3a976499676e6..91fa340e461121 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_bfloat16_conversion/bfloat16-conv.ll @@ -1,6 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_bfloat16_conversion %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_bfloat16_conversion %s -o - -filetype=obj | spirv-val %} - +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_bfloat16_conversion %s -o - -filetype=obj | spirv-val %} ; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR ; CHECK-ERROR: the builtin requires the following SPIR-V extension: SPV_INTEL_bfloat16_conversion diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll index 4ef3e72c78e5eb..8a54d22a539db1 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr.ll @@ -1,11 +1,8 @@ ; Modified from: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/test/extensions/INTEL/SPV_INTEL_variable_length_array/basic.ll ; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR -; RUN: not llc -O0 -mtriple=spirv64-amd-amdhsa %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %} -; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %} ; CHECK-ERROR: LLVM ERROR: array allocation: this instruction requires the following SPIR-V extension: SPV_INTEL_variable_length_array diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll index c7f7b0e881b1c3..7b9f75d74db997 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_variable_length_array/vararr_spec_const.ll @@ -1,9 +1,7 @@ ; Modified from: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/test/extensions/INTEL/SPV_INTEL_variable_length_array/vla_spec_const.ll ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_variable_length_array %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %} -; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: Capability VariableLengthArrayINTEL ; CHECK-SPIRV: Extension "SPV_INTEL_variable_length_array" diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll index 83318a0b504391..a38c9072ed1bd4 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_subgroup_rotate/subgroup-rotate.ll @@ -1,8 +1,6 @@ ; RUN: not llc -O0 -mtriple=spirv32-unknown-unknown %s -o %t.spvt 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_KHR_subgroup_rotate %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_KHR_subgroup_rotate %s -o - | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_KHR_subgroup_rotate %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_KHR_subgroup_rotate %s -o - -filetype=obj | spirv-val %} ; CHECK-ERROR: LLVM ERROR: OpGroupNonUniformRotateKHR instruction requires the following SPIR-V extension: SPV_KHR_subgroup_rotate diff --git a/llvm/test/CodeGen/SPIRV/fence.ll b/llvm/test/CodeGen/SPIRV/fence.ll index 9dcc3f95e12b9c..5da58667f24f29 100644 --- a/llvm/test/CodeGen/SPIRV/fence.ll +++ b/llvm/test/CodeGen/SPIRV/fence.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: OpName %[[#GetScope:]] "_Z8getScopev" ; CHECK-DAG: %[[#Long:]] = OpTypeInt 32 0 diff --git a/llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll b/llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll index 346595d786f26f..93bdbe3c1c2117 100644 --- a/llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll +++ b/llvm/test/CodeGen/SPIRV/function/multiple-anonymous-functions.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ;; Types: ; CHECK-DAG: %[[#I32:]] = OpTypeInt 32 diff --git a/llvm/test/CodeGen/SPIRV/half_extension.ll b/llvm/test/CodeGen/SPIRV/half_extension.ll index 0b0f0641420959..b30e5514c95bea 100644 --- a/llvm/test/CodeGen/SPIRV/half_extension.ll +++ b/llvm/test/CodeGen/SPIRV/half_extension.ll @@ -8,7 +8,6 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability Float16Buffer ; CHECK-SPIRV-DAG: OpCapability Float16 diff --git a/llvm/test/CodeGen/SPIRV/half_no_extension.ll b/llvm/test/CodeGen/SPIRV/half_no_extension.ll index 66b8cbbcc38dc8..a5b0ec9c92d236 100644 --- a/llvm/test/CodeGen/SPIRV/half_no_extension.ll +++ b/llvm/test/CodeGen/SPIRV/half_no_extension.ll @@ -6,7 +6,6 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpCapability Float16Buffer ; CHECK-SPIRV-NOT: OpCapability Float16 diff --git a/llvm/test/CodeGen/SPIRV/image.ll b/llvm/test/CodeGen/SPIRV/image.ll index bc6d124ccb2205..8d4ab7f3cbf0ee 100644 --- a/llvm/test/CodeGen/SPIRV/image.ll +++ b/llvm/test/CodeGen/SPIRV/image.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: %[[#VOID_TY:]] = OpTypeVoid ; CHECK-SPIRV-DAG: %[[#]] = OpTypeImage %[[#VOID_TY]] 2D 0 0 0 0 Unknown ReadOnly diff --git a/llvm/test/CodeGen/SPIRV/image/sampler.ll b/llvm/test/CodeGen/SPIRV/image/sampler.ll index 9ad2244a9d28c1..7b45c95f5ed433 100644 --- a/llvm/test/CodeGen/SPIRV/image/sampler.ll +++ b/llvm/test/CodeGen/SPIRV/image/sampler.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#i32:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#v4i32:]] = OpTypeVector %[[#i32]] 4 diff --git a/llvm/test/CodeGen/SPIRV/instructions/select-phi.ll b/llvm/test/CodeGen/SPIRV/instructions/select-phi.ll index ac6f22aad196ed..3828fe89e60aec 100644 --- a/llvm/test/CodeGen/SPIRV/instructions/select-phi.ll +++ b/llvm/test/CodeGen/SPIRV/instructions/select-phi.ll @@ -1,13 +1,10 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --translator-compatibility-mode %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --translator-compatibility-mode %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa --translator-compatibility-mode %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[Char:.*]] = OpTypeInt 8 0 ; CHECK-DAG: %[[Long:.*]] = OpTypeInt 32 0 diff --git a/llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll b/llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll index 70699cf763eee5..0ff28952f8081a 100644 --- a/llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll +++ b/llvm/test/CodeGen/SPIRV/instructions/select-ptr-load.ll @@ -4,9 +4,6 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} - ; CHECK-SPIRV-DAG: %[[Float:.*]] = OpTypeFloat 32 ; CHECK-SPIRV-DAG: %[[FloatPtr:.*]] = OpTypePointer Function %[[Float]] ; CHECK-SPIRV: OpInBoundsPtrAccessChain %[[FloatPtr]] diff --git a/llvm/test/CodeGen/SPIRV/instructions/select.ll b/llvm/test/CodeGen/SPIRV/instructions/select.ll index f48983d8cd16a0..9234b97157d9d8 100644 --- a/llvm/test/CodeGen/SPIRV/instructions/select.ll +++ b/llvm/test/CodeGen/SPIRV/instructions/select.ll @@ -4,9 +4,6 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} - ; CHECK-DAG: OpName [[SCALARi32:%.+]] "select_i32" ; CHECK-DAG: OpName [[SCALARPTR:%.+]] "select_ptr" ; CHECK-DAG: OpName [[VEC2i32:%.+]] "select_i32v2" diff --git a/llvm/test/CodeGen/SPIRV/linkage/extern-weak-linkage.ll b/llvm/test/CodeGen/SPIRV/linkage/extern-weak-linkage.ll index 1c2693d796cc83..e742de4bc1e217 100644 --- a/llvm/test/CodeGen/SPIRV/linkage/extern-weak-linkage.ll +++ b/llvm/test/CodeGen/SPIRV/linkage/extern-weak-linkage.ll @@ -1,9 +1,6 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} - ; CHECK-SPIRV: Capability Linkage ; CHECK-SPIRV-DAG: OpName %[[#AbsFun:]] "abs" ; CHECK-SPIRV-DAG: OpName %[[#ExternalFun:]] "__devicelib_abs" diff --git a/llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll b/llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll index 66964fe6a7abfe..f00c25a949b1e2 100644 --- a/llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll +++ b/llvm/test/CodeGen/SPIRV/linkage/link-attribute.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpDecorate %[[#ID:]] LinkageAttributes "imageSampler" Export ; CHECK: %[[#ID]] = OpVariable %[[#]] UniformConstant %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/literals.ll b/llvm/test/CodeGen/SPIRV/literals.ll index 6f4858e59ef67a..d99ec36537d10f 100644 --- a/llvm/test/CodeGen/SPIRV/literals.ll +++ b/llvm/test/CodeGen/SPIRV/literals.ll @@ -1,7 +1,6 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#F32:]] = OpTypeFloat 32 ; CHECK: %[[#F64:]] = OpTypeFloat 64 diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll index d69d6569735e2d..d627a2fc7838a9 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/abs.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] s_abs ; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] s_abs diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll index 44d00e6900e241..48c96fae8b03a0 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/assume.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-NOT: OpCapability ExpectAssumeKHR ; CHECK-SPIRV-NOT: OpExtension "SPV_KHR_expect_assume" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll index a57614287369ec..3f2ab9fa7190bc 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/bswap.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpName %[[#FuncNameInt16:]] "spirv.llvm_bswap_i16" ; CHECK-SPIRV: OpName %[[#FuncNameInt32:]] "spirv.llvm_bswap_i32" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll index 3e39e748b5df11..8411d90e23f0d1 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ceil.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll index 51a621db829ac1..147fd80462f9ad 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctlz.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll index b801836c057ac1..f2d881b083dd7e 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/ctpop.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#]] = OpBitCount %[[#]] %[[#]] ; CHECK: %[[#]] = OpBitCount %[[#]] %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll index f496dc7ed97ce9..b9bdcfdb162f76 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/cttz.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/expect.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/expect.ll index fc6afd78e81e3a..ec40c263be4112 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/expect.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/expect.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-NOT: OpCapability ExpectAssumeKHR ; CHECK-SPIRV-NOT: OpExtension "SPV_KHR_expect_assume" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll index 20b6f6be0e5b37..5de22021762927 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fabs.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll index a80b556033e740..8f14e8cf272ba7 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fp-intrinsics.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll index e8646f9161ff38..2d5b30978aa221 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpName %[[#NAME_FSHL_FUNC_32:]] "spirv.llvm_fshl_i32" ; CHECK-SPIRV: OpName %[[#NAME_FSHL_FUNC_16:]] "spirv.llvm_fshl_i16" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll index 30a5a7ebf027b3..4cf5ca53a411b4 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpName %[[#NAME_FSHR_FUNC_32:]] "spirv.llvm_fshr_i32" ; CHECK-SPIRV: OpName %[[#NAME_FSHR_FUNC_16:]] "spirv.llvm_fshr_i16" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll index 0992aeb2a58280..5b700b7fcfee3e 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/invariant.ll @@ -1,6 +1,5 @@ ;; Make sure the backend doesn't crash if the input LLVM IR contains llvm.invariant.* intrinsics ; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK-NOT: OpFunctionParameter ; CHECK-NOT: OpFunctionCall diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll index 0f6569418d6d50..e0c84ee3a3f1c1 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/add.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll index c3f25c5ea110fa..12a4a86fa4a8be 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/and.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll index 238d39cb701efd..459bc6bdcdaff8 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fadd.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll index 22df4fba14228f..4f9cd29cd05d2a 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmax.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll index 6203dd2cafd37a..837bea0fbe6247 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmaximum.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll index a3b05e5acc7738..475da2e1ec31ea 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmin.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll index 26cce2a91f1c19..b525c849c3b59a 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fminimum.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll index 1194f6ecb393bf..0985be992ca74e 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/fmul.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll index 2bb78722c6f84d..1a700577e46b41 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/mul.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll index 3c5f5858866b97..90c6cf5562a924 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/or.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll index b878e78e01f6eb..4551fa31681d2b 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smax.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll index 86bb4bdd582700..a0d257bb131804 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/smin.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll index 409dd3b69e55ec..ba5dba76aeecca 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umax.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll index 0845e81777db7f..e16bde88ef5094 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/umin.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll index 64259f34c6435d..cf887bb358aca6 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llvm-vector-reduce/xor.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spir64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll index 00c82e21152d00..7b8c05d9c98eda 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/maxnum.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s define spir_func float @Test(float %x, float %y) { entry: diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll index 530c5b4365060b..5b59206ff7f2d3 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/satur-arith.ll @@ -4,9 +4,6 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} - ; CHECK: OpExtInstImport "OpenCL.std" ; CHECK-DAG: OpName %[[#Foo:]] "foo" ; CHECK-DAG: OpName %[[#Bar:]] "bar" diff --git a/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll b/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll index dda5b0521a3c57..44b11f3ddb2731 100644 --- a/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll +++ b/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: %[[#type_int32:]] = OpTypeInt 32 0 ; CHECK-SPIRV-DAG: %[[#type_int64:]] = OpTypeInt 64 0 diff --git a/llvm/test/CodeGen/SPIRV/multi_md.ll b/llvm/test/CodeGen/SPIRV/multi_md.ll index 8021d941b43cd5..6d8af7defd7526 100644 --- a/llvm/test/CodeGen/SPIRV/multi_md.ll +++ b/llvm/test/CodeGen/SPIRV/multi_md.ll @@ -2,7 +2,6 @@ ;; assertion. ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s %struct.my_struct_t = type { i8, i32 } diff --git a/llvm/test/CodeGen/SPIRV/no_capability_shader.ll b/llvm/test/CodeGen/SPIRV/no_capability_shader.ll index 157ab583758948..954b7c83681bde 100644 --- a/llvm/test/CodeGen/SPIRV/no_capability_shader.ll +++ b/llvm/test/CodeGen/SPIRV/no_capability_shader.ll @@ -1,7 +1,6 @@ ;; __kernel void sample_test(read_only image2d_t src, read_only image1d_buffer_t buff) {} ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-NOT: OpCapability Shader diff --git a/llvm/test/CodeGen/SPIRV/opaque_pointers.ll b/llvm/test/CodeGen/SPIRV/opaque_pointers.ll index 5f156c67b45d86..db4d1b130b8523 100644 --- a/llvm/test/CodeGen/SPIRV/opaque_pointers.ll +++ b/llvm/test/CodeGen/SPIRV/opaque_pointers.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK ; CHECK-DAG: %[[#Int32Ty:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#PtrInt32Ty:]] = OpTypePointer Function %[[#Int32Ty]] diff --git a/llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll b/llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll index 586564b08d5c81..46a7cf42494261 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/basic/get_global_offset.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK-DAG: OpEntryPoint Kernel %[[#test_func:]] "test" ; CHECK-DAG: OpDecorate %[[#f2_decl:]] LinkageAttributes "BuiltInGlobalOffset" Import diff --git a/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_init.ll b/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_init.ll index a335e2600bbedb..9d759a1cf47d07 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_init.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_init.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpEntryPoint Kernel %[[#f1:]] "writer" ; CHECK: OpEntryPoint Kernel %[[#f2:]] "reader" diff --git a/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_uninit.ll b/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_uninit.ll index 48eea766cc26a7..fe02ba650aaa0f 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_uninit.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/basic/progvar_prog_scope_uninit.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpEntryPoint Kernel %[[#f1:]] "global_check" %[[#var0:]] %[[#var1:]] %[[#var2:]] %[[#var3:]] ; CHECK: OpEntryPoint Kernel %[[#f2:]] "writer" %[[#var0:]] %[[#var1:]] %[[#var2:]] %[[#var3:]] diff --git a/llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll b/llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll index 686fbd4eb3dc3b..562f5c7b6826e1 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/device_execution/execute_block.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; REQUIRES: asserts diff --git a/llvm/test/CodeGen/SPIRV/opencl/get_global_id.ll b/llvm/test/CodeGen/SPIRV/opencl/get_global_id.ll index 79b202b9b60fbe..d6074191b3acb0 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/get_global_id.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/get_global_id.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ;; The set of valid inputs for get_global_id depends on the runtime NDRange, ;; but inputs outside of [0, 2] always return 0. diff --git a/llvm/test/CodeGen/SPIRV/opencl/metadata/fp_contractions_metadata.ll b/llvm/test/CodeGen/SPIRV/opencl/metadata/fp_contractions_metadata.ll index 1225ba0c8ea7fe..2b09f52f183be3 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/metadata/fp_contractions_metadata.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/metadata/fp_contractions_metadata.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpEntryPoint Kernel %[[#ENTRY:]] "foo" ; CHECK-NOT: OpExecutionMode %[[#ENTRY]] ContractionOff diff --git a/llvm/test/CodeGen/SPIRV/opencl/metadata/no_fp_contractions_metadata.ll b/llvm/test/CodeGen/SPIRV/opencl/metadata/no_fp_contractions_metadata.ll index 6689915b6a0143..10840125b9f61b 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/metadata/no_fp_contractions_metadata.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/metadata/no_fp_contractions_metadata.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpEntryPoint Kernel %[[#ENTRY:]] "foo" ; CHECK: OpExecutionMode %[[#ENTRY]] ContractionOff diff --git a/llvm/test/CodeGen/SPIRV/opencl/vload2.ll b/llvm/test/CodeGen/SPIRV/opencl/vload2.ll index 5e6a25ef1f87f8..592de33d4d3938 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/vload2.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/vload2.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; This test only intends to check the vloadn builtin name resolution. ; The calls to the OpenCL builtins are not valid and will not pass SPIR-V validation. diff --git a/llvm/test/CodeGen/SPIRV/opencl/vstore2.ll b/llvm/test/CodeGen/SPIRV/opencl/vstore2.ll index d95ae972377573..0ea14c7f25e877 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/vstore2.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/vstore2.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; This test only intends to check the vstoren builtin name resolution. ; The calls to the OpenCL builtins are not valid and will not pass SPIR-V validation. diff --git a/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll b/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll index cc188f3ade1198..d6cdcd7e20e8f2 100644 --- a/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll +++ b/llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-TargetExtType-arg-no-spv_assign_type.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -print-after-all -o - 2>&1 | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -print-after-all -o - 2>&1 | FileCheck %s ; CHECK: *** IR Dump After SPIRV emit intrinsics (emit-intrinsics) *** diff --git a/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll b/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll index f9fe48df059eb7..ac72ec28c37d9d 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#VOID:]] = OpTypeVoid ; CHECK-DAG: %[[#FLOAT:]] = OpTypeFloat 32 diff --git a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll index b8770b6f607b38..7fae6ca2c48cf1 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-accesschain.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#TYCHAR:]] = OpTypeInt 8 0 ; CHECK-DAG: %[[#TYCHARPTR:]] = OpTypePointer Function %[[#TYCHAR]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll index 4c85ef65b431d6..18752fdf843d20 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-load.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#TYLONG:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#TYSTRUCTLONG:]] = OpTypeStruct %[[#TYLONG]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll index bb9859812ca9d0..202bcfbf2599a9 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/bitcast-fix-store.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#TYLONG:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#TYLONGPTR:]] = OpTypePointer Function %[[#TYLONG]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll index 4fd38c34c5acff..7e9c6214c2818a 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-addressspace.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: %[[#INT8:]] = OpTypeInt 8 0 ; CHECK: %[[#PTR1:]] = OpTypePointer CrossWorkgroup %[[#INT8]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll index f692829c8282c1..fc999ba1a3cdac 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-base-type.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: %[[#FLOAT32:]] = OpTypeFloat 32 ; CHECK: %[[#PTR:]] = OpTypePointer CrossWorkgroup %[[#FLOAT32]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll index 2cd171cee9d969..132f10262432b2 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#INT8:]] = OpTypeInt 8 0 ; CHECK-DAG: %[[#VEC3:]] = OpTypeVector %[[#INT8]] 3 diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll index b50f8ef95351d2..d2a65917bfd659 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-kernel-arg-char.ll @@ -1,8 +1,6 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#INT8:]] = OpTypeInt 8 0 ; CHECK-DAG: %[[#INT64:]] = OpTypeInt 64 0 diff --git a/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll b/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll index 22692b233c4fbb..d0c64b4353ec68 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll @@ -6,9 +6,6 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} - ; CHECK: OpName %[[GlobalValue:.*]] "dev_global" ; CHECK-DAG: %[[TyI64:.*]] = OpTypeInt 64 0 ; CHECK-DAG: %[[TyStruct:.*]] = OpTypeStruct %[[TyI64]] %[[TyI64]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll index 5a6fe7f6083c66..b4948b66aed86d 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-builtin-vload-type-discrapency.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#INT8:]] = OpTypeInt 8 0 ; CHECK-DAG: %[[#PTRINT8:]] = OpTypePointer CrossWorkgroup %[[#INT8]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll index fba8cf9dcb74ff..a3a730ac67e782 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-addressspace.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#INT:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#PTR1:]] = OpTypePointer Function %[[#INT]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-mismatch.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-mismatch.ll index fc179cbf19f16d..46e315b2dc62a2 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-mismatch.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-mismatch.ll @@ -1,5 +1,4 @@ ; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o - 2>&1 | FileCheck %s -; RUN: not llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Type mismatch {{.*}} diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll index 517683a3ca5241..b74a3449980d97 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-bitcast-to-generic.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#IMAGE:]] = OpTypeImage %2 2D 0 0 0 0 Unknown ReadOnly diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll index 0bb265a7a70fc3..a513d103970663 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type-deduction-no-metadata.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} define spir_kernel void @test(ptr addrspace(1) %srcimg) { ; CHECK: %[[#VOID:]] = OpTypeVoid diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll index 99f4c94db994f8..b8f205a68e5616 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-pointer-type.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#FLOAT32:]] = OpTypeFloat 32 ; CHECK-DAG: %[[#PTR1:]] = OpTypePointer Function %[[#FLOAT32]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll index d988860ba97c85..55bddfdad699b2 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#CHAR:]] = OpTypeInt 8 ; CHECK-DAG: %[[#GLOBAL_PTR_CHAR:]] = OpTypePointer CrossWorkgroup %[[#CHAR]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll index c80b7ddcd3be65..0d2a832c496b1b 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#CHAR:]] = OpTypeInt 8 ; CHECK-DAG: %[[#GLOBAL_PTR_CHAR:]] = OpTypePointer CrossWorkgroup %[[#CHAR]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll b/llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll index 95049bd4e2d065..1667abc51be9fc 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/load-addressspace.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: %[[#INT8:]] = OpTypeInt 8 0 ; CHECK: %[[#PTR1:]] = OpTypePointer CrossWorkgroup %[[#INT8]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll b/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll index 3d1a5f8991dfcd..639906af3a952f 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byref.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} target triple = "spirv64-unknown-unknown" diff --git a/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll b/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll index 43b2c39befe435..6b684bf41bbb09 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/ptr-argument-byval.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#VOID:]] = OpTypeVoid ; CHECK-DAG: %[[#INT32:]] = OpTypeInt 32 0 diff --git a/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll b/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll index 3e0567712a84df..5adaf6f65688df 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#CHAR:]] = OpTypeInt 8 ; CHECK-DAG: %[[#GLOBAL_PTR_CHAR:]] = OpTypePointer CrossWorkgroup %[[#CHAR]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll b/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll index 430009b7de3978..e7ce3ef621e83a 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} define spir_kernel void @foo(ptr addrspace(1) %arg) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !4 { %var = alloca ptr addrspace(1), align 8 diff --git a/llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll b/llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll index b32291ed88e578..83234e3986c84f 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/two-subsequent-bitcasts.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#float:]] = OpTypeFloat 32 ; CHECK-DAG: %[[#pointer:]] = OpTypePointer CrossWorkgroup %[[#float]] diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll index 0741a88162333a..b039f80860daf6 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-by-call-chain.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV-DAG: OpName %[[ArgCum:.*]] "_arg_cum" ; CHECK-SPIRV-DAG: OpName %[[FunTest:.*]] "test" diff --git a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll index e16faf7c43f722..edb31ffeee8e86 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/type-deduce-call-no-bitcast.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV-DAG: OpName %[[Foo:.*]] "foo" ; CHECK-SPIRV-DAG: %[[TyChar:.*]] = OpTypeInt 8 0 diff --git a/llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll b/llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll index 9ac9faf9f42ce7..f144418cf54259 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/typeof-ptr-int.ll @@ -2,9 +2,7 @@ ; definitions, even though their LLVM function types are identical. ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: OpName %[[Fun32:.*]] "tp_arg_i32" ; CHECK-DAG: OpName %[[Fun64:.*]] "tp_arg_i64" diff --git a/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll b/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll index dd0b8d9865aa1f..034feed72dc7bc 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} @Ptr = addrspace(1) global ptr addrspace(1) null @Init = private addrspace(2) constant i32 123 diff --git a/llvm/test/CodeGen/SPIRV/preprocess-metadata.ll b/llvm/test/CodeGen/SPIRV/preprocess-metadata.ll index 1916e39b9f5625..24e0851eb3833c 100644 --- a/llvm/test/CodeGen/SPIRV/preprocess-metadata.ll +++ b/llvm/test/CodeGen/SPIRV/preprocess-metadata.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ;; The purpose of this test is to check that some of OpenCL metadata are consumed ;; even if 'opencl.ocl.version' metadata is missed (i.e. LLVM IR was produced not diff --git a/llvm/test/CodeGen/SPIRV/printf.ll b/llvm/test/CodeGen/SPIRV/printf.ll index 5c8e1a3d890ce6..483fc1f244e57c 100644 --- a/llvm/test/CodeGen/SPIRV/printf.ll +++ b/llvm/test/CodeGen/SPIRV/printf.ll @@ -4,9 +4,6 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} - ; CHECK: %[[#ExtImport:]] = OpExtInstImport "OpenCL.std" ; CHECK: %[[#Char:]] = OpTypeInt 8 0 ; CHECK: %[[#CharPtr:]] = OpTypePointer UniformConstant %[[#Char]] diff --git a/llvm/test/CodeGen/SPIRV/pstruct.ll b/llvm/test/CodeGen/SPIRV/pstruct.ll index ddc3f46fe23daa..fd55e9b69e2609 100644 --- a/llvm/test/CodeGen/SPIRV/pstruct.ll +++ b/llvm/test/CodeGen/SPIRV/pstruct.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; TODO(#60133): Requires updates following opaque pointer migration. ; XFAIL: * diff --git a/llvm/test/CodeGen/SPIRV/read_image.ll b/llvm/test/CodeGen/SPIRV/read_image.ll index 65b3a001409823..ede5994279d2ff 100644 --- a/llvm/test/CodeGen/SPIRV/read_image.ll +++ b/llvm/test/CodeGen/SPIRV/read_image.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: %[[#IntTy:]] = OpTypeInt ; CHECK-SPIRV: %[[#IVecTy:]] = OpTypeVector %[[#IntTy]] diff --git a/llvm/test/CodeGen/SPIRV/select-builtin.ll b/llvm/test/CodeGen/SPIRV/select-builtin.ll index 327ef1e3209151..6717970d160fcf 100644 --- a/llvm/test/CodeGen/SPIRV/select-builtin.ll +++ b/llvm/test/CodeGen/SPIRV/select-builtin.ll @@ -1,8 +1,6 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: OpSelect diff --git a/llvm/test/CodeGen/SPIRV/simple.ll b/llvm/test/CodeGen/SPIRV/simple.ll index 23a53473290d5e..63c15968c72535 100644 --- a/llvm/test/CodeGen/SPIRV/simple.ll +++ b/llvm/test/CodeGen/SPIRV/simple.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; Support of doubles is required. ; CHECK: OpCapability Float64 diff --git a/llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll b/llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll index 717a5f66fd549e..d9145e8d9f0a94 100644 --- a/llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll +++ b/llvm/test/CodeGen/SPIRV/sitofp-with-bool.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#float:]] = OpTypeFloat 32 diff --git a/llvm/test/CodeGen/SPIRV/spec_const_decoration.ll b/llvm/test/CodeGen/SPIRV/spec_const_decoration.ll index 3193ec1802aac4..485da19fd6da0a 100644 --- a/llvm/test/CodeGen/SPIRV/spec_const_decoration.ll +++ b/llvm/test/CodeGen/SPIRV/spec_const_decoration.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpDecorate %[[#SpecConst:]] SpecId 0 ; CHECK: %[[#SpecConst]] = OpSpecConstant %[[#]] 70 diff --git a/llvm/test/CodeGen/SPIRV/spirv-load-store.ll b/llvm/test/CodeGen/SPIRV/spirv-load-store.ll index 83548fa9a121d4..9188617312466d 100644 --- a/llvm/test/CodeGen/SPIRV/spirv-load-store.ll +++ b/llvm/test/CodeGen/SPIRV/spirv-load-store.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; Translate SPIR-V friendly OpLoad and OpStore calls ; CHECK-DAG: %[[#TYLONG:]] = OpTypeInt 32 0 diff --git a/llvm/test/CodeGen/SPIRV/struct.ll b/llvm/test/CodeGen/SPIRV/struct.ll index 51b7d1f06cac82..c3d2694cf929cc 100644 --- a/llvm/test/CodeGen/SPIRV/struct.ll +++ b/llvm/test/CodeGen/SPIRV/struct.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s %struct.ST = type { i32, i32, i32 } diff --git a/llvm/test/CodeGen/SPIRV/switch-no-jump-table.ll b/llvm/test/CodeGen/SPIRV/switch-no-jump-table.ll index 2afde3b0d94802..c9c0f17f0b91ef 100644 --- a/llvm/test/CodeGen/SPIRV/switch-no-jump-table.ll +++ b/llvm/test/CodeGen/SPIRV/switch-no-jump-table.ll @@ -2,7 +2,6 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: OpSwitch %[[#]] %[[Label:]] ; CHECK-4: OpBranch %[[Label]] diff --git a/llvm/test/CodeGen/SPIRV/token/token-type-preallocated-setup-arg.ll b/llvm/test/CodeGen/SPIRV/token/token-type-preallocated-setup-arg.ll index a02872b5a2f89f..42e59c726b6fdc 100644 --- a/llvm/test/CodeGen/SPIRV/token/token-type-preallocated-setup-arg.ll +++ b/llvm/test/CodeGen/SPIRV/token/token-type-preallocated-setup-arg.ll @@ -1,7 +1,6 @@ ; Example of token usage is from https://llvm.org/docs/LangRef.html (Preallocated Operand Bundles) ; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o - 2>&1 | FileCheck %s -; RUN: not llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - 2>&1 | FileCheck %s ; CHECK: A token is encountered but SPIR-V without extensions does not support token type diff --git a/llvm/test/CodeGen/SPIRV/token/token-type-requires-extension.ll b/llvm/test/CodeGen/SPIRV/token/token-type-requires-extension.ll index 490f86320282fa..ee545a77e5d68f 100644 --- a/llvm/test/CodeGen/SPIRV/token/token-type-requires-extension.ll +++ b/llvm/test/CodeGen/SPIRV/token/token-type-requires-extension.ll @@ -1,5 +1,4 @@ ; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o - 2>&1 | FileCheck %s -; RUN: not llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - 2>&1 | FileCheck %s ; CHECK: A token is encountered but SPIR-V without extensions does not support token type diff --git a/llvm/test/CodeGen/SPIRV/transcoding/BitReversePref.ll b/llvm/test/CodeGen/SPIRV/transcoding/BitReversePref.ll index 8de3e34cc0d7d1..11b0578a0c9c07 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/BitReversePref.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/BitReversePref.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: OpDecorate %[[#FUNC_NAME:]] LinkageAttributes "_Z10BitReversei" ; CHECK-NOT: OpBitReverse diff --git a/llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll b/llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll index eb5aaf7347bb7a..65c992c9b28ed3 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll @@ -19,9 +19,7 @@ ;; bash$ $PATH_TO_GEN/bin/clang -cc1 -x cl -cl-std=CL2.0 -triple spir64-unknown-unknown -emit-llvm -include opencl-20.h BuildNDRange_2.cl -o BuildNDRange_2.ll ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; TODO(#60133): Requires updates following opaque pointer migration. ; XFAIL: * diff --git a/llvm/test/CodeGen/SPIRV/transcoding/DecorationAlignment.ll b/llvm/test/CodeGen/SPIRV/transcoding/DecorationAlignment.ll index 28459d9496a13f..d4fc5c3280b714 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/DecorationAlignment.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/DecorationAlignment.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: OpDecorate %[[#ALIGNMENT:]] Alignment 16 ; CHECK-SPIRV: %[[#ALIGNMENT]] = OpFunctionParameter %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpImageQuerySize.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpImageQuerySize.ll index db16c91f5ca01f..0c1f8eaa34a408 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpImageQuerySize.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpImageQuerySize.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ;; Check conversion of get_image_width, get_image_height, get_image_depth, ;; get_image_array_size, and get_image_dim OCL built-ins. diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll index 91947dbec1403a..cb41aad2a0c5fa 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpName %[[#v:]] "v" ; CHECK-SPIRV: OpName %[[#index:]] "index" diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_cmpxchg.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_cmpxchg.ll index 4c1894eae6f1dc..417b89eb36f0f5 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_cmpxchg.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpenCL/atomic_cmpxchg.ll @@ -1,6 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; This test checks that the backend is capable to correctly translate ;; atomic_cmpxchg OpenCL C 1.2 built-in function [1] into corresponding SPIR-V diff --git a/llvm/test/CodeGen/SPIRV/transcoding/SpecConstantComposite.ll b/llvm/test/CodeGen/SPIRV/transcoding/SpecConstantComposite.ll index ddef6deeee8dd6..e6f5c7ddb078d7 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/SpecConstantComposite.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/SpecConstantComposite.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpDecorate %[[#SC3:]] SpecId 3 ; CHECK-SPIRV-DAG: OpDecorate %[[#SC4:]] SpecId 4 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/atomic_flag.ll b/llvm/test/CodeGen/SPIRV/transcoding/atomic_flag.ll index b09e655c7aa04f..20204acb1ef584 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/atomic_flag.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/atomic_flag.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; Types: ; CHECK-DAG: %[[#INT:]] = OpTypeInt 32 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/bitcast.ll b/llvm/test/CodeGen/SPIRV/transcoding/bitcast.ll index a27781c9199fbb..2c0fc393b135a2 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/bitcast.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/bitcast.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; Check the bitcast is translated back to bitcast diff --git a/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_arithmetics.ll b/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_arithmetics.ll index 238559d1c85d63..53883fd1691f5e 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_arithmetics.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_arithmetics.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; The IR was generated from the following source: ;; #include diff --git a/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_opt.ll b/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_opt.ll index 16018d66ac2dbd..3885f070231442 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_opt.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/builtin_vars_opt.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-linux %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; The IR was generated from the following source: ;; #include diff --git a/llvm/test/CodeGen/SPIRV/transcoding/check_ro_qualifier.ll b/llvm/test/CodeGen/SPIRV/transcoding/check_ro_qualifier.ll index 55e31d85bc7ff0..824ca1b2d69249 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/check_ro_qualifier.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/check_ro_qualifier.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: %[[#IMAGE_TYPE:]] = OpTypeImage ; CHECK-SPIRV: %[[#IMAGE_ARG:]] = OpFunctionParameter %[[#IMAGE_TYPE]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fmod.ll b/llvm/test/CodeGen/SPIRV/transcoding/fmod.ll index bd7cf61690cbd2..683b5c24f5b712 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/fmod.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/fmod.ll @@ -2,9 +2,7 @@ ;; { out = fmod( in1, in2 ); } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: %[[#]] = OpExtInst %[[#]] %[[#]] fmod %[[#]] %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/get_image_num_mip_levels.ll b/llvm/test/CodeGen/SPIRV/transcoding/get_image_num_mip_levels.ll index 724e49cce8a739..fd241963d1e98d 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/get_image_num_mip_levels.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/get_image_num_mip_levels.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ;; Types: ; CHECK-DAG: %[[#INT:]] = OpTypeInt 32 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/image_get_size_with_access_qualifiers.ll b/llvm/test/CodeGen/SPIRV/transcoding/image_get_size_with_access_qualifiers.ll index 5597cd851d7d46..a39a3ce038d6ab 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/image_get_size_with_access_qualifiers.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/image_get_size_with_access_qualifiers.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: %[[#IntTyID:]] = OpTypeInt ; CHECK-SPIRV-DAG: %[[#VoidTyID:]] = OpTypeVoid diff --git a/llvm/test/CodeGen/SPIRV/transcoding/isequal.ll b/llvm/test/CodeGen/SPIRV/transcoding/isequal.ll index b1faa86ab3fc6e..c5f3f9e1e2e74c 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/isequal.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/isequal.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV-NOT: OpSConvert diff --git a/llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll b/llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll index 56f0d7a661475d..89fa93b4fcda1c 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll @@ -2,8 +2,6 @@ ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64 -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#i64:]] = OpTypeInt 64 0 ; CHECK-DAG: %[[#i8:]] = OpTypeInt 8 0 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/memory_access.ll b/llvm/test/CodeGen/SPIRV/transcoding/memory_access.ll index 02b3895cf81ec4..fc757112f168c8 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/memory_access.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/memory_access.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-NOT: OpStore %[[#]] %[[#]] Volatile Aligned 8 ; CHECK-SPIRV: OpStore %[[#]] %[[#]] Volatile|Aligned 8 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll index 027571f2e177f4..d44e32141db75b 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; CHECK: OpTypeInt 16 ; CHECK: OpIAdd diff --git a/llvm/test/CodeGen/SPIRV/transcoding/readonly.ll b/llvm/test/CodeGen/SPIRV/transcoding/readonly.ll index 8a14eeb45aee37..051d80319ee04d 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/readonly.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/readonly.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV: OpDecorate %[[#PARAM:]] FuncParamAttr NoWrite ; CHECK-SPIRV: %[[#PARAM]] = OpFunctionParameter %{{.*}} diff --git a/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll b/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll index a883a1d7b63d92..fe0d96f2773ec6 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll @@ -4,9 +4,6 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} - ; CHECK-DAG: %[[#TyEvent:]] = OpTypeEvent ; CHECK-DAG: %[[#TyStruct:]] = OpTypeStruct %[[#TyEvent]] ; CHECK-DAG: %[[#ConstEvent:]] = OpConstantNull %[[#TyEvent]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll b/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll index f9c6ea08032f52..04fb39118034c8 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll @@ -2,8 +2,6 @@ ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-64 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV,CHECK-SPIRV-64 -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV-64-DAG: %[[#i64:]] = OpTypeInt 64 0 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll index a230e74083695f..6cc9e0f3329287 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_ballot.ll @@ -156,7 +156,6 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability GroupNonUniformBallot diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_clustered_reduce.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_clustered_reduce.ll index 35e0b2dfcd2bbd..22bf747490da87 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_clustered_reduce.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_clustered_reduce.ll @@ -174,7 +174,6 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability GroupNonUniformClustered diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll index ee403f612a4b9c..f605d0c42d34f7 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_extended_types.ll @@ -180,7 +180,6 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: %[[#char:]] = OpTypeInt 8 0 ; CHECK-SPIRV-DAG: %[[#short:]] = OpTypeInt 16 0 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll index d7f3bfc61c1a50..8f4910ff512f8d 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll @@ -316,7 +316,6 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability GroupNonUniformArithmetic diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll index 50f089b8215bbb..1073473a224df7 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_vote.ll @@ -62,7 +62,6 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability GroupNonUniformVote diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll index 24a13fc2ecba81..9ed5c78bd0ede6 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle.ll @@ -80,7 +80,6 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability GroupNonUniformShuffle diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll index 8576b22a1337a7..3ad2c2d87549c8 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_shuffle_relative.ll @@ -80,7 +80,6 @@ ;; } ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; CHECK-SPIRV-DAG: OpCapability GroupNonUniformShuffleRelative diff --git a/llvm/test/CodeGen/SPIRV/transcoding/vec_type_hint.ll b/llvm/test/CodeGen/SPIRV/transcoding/vec_type_hint.ll index 9e7f83ec72301c..1d512a894d540a 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/vec_type_hint.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/vec_type_hint.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ;; kernel ;; __attribute__((vec_type_hint(float4))) diff --git a/llvm/test/CodeGen/SPIRV/types/or-i1.ll b/llvm/test/CodeGen/SPIRV/types/or-i1.ll index 8eed7b2b4dc73e..32dc258d85554f 100644 --- a/llvm/test/CodeGen/SPIRV/types/or-i1.ll +++ b/llvm/test/CodeGen/SPIRV/types/or-i1.ll @@ -1,7 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#BOOL:]] = OpTypeBool ; CHECK: %[[#BOOL:]] = OpLogicalOr %[[#BOOL]] %[[#]] %[[#]] diff --git a/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll b/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll index ff0db518dc6075..6f793fc5d030e6 100644 --- a/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll +++ b/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll @@ -1,5 +1,4 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=SPV -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s --check-prefix=SPV ;; The IR was generated from the following source: ;; void __kernel K(global float* A, int B) { diff --git a/llvm/test/CodeGen/SPIRV/unnamed-global.ll b/llvm/test/CodeGen/SPIRV/unnamed-global.ll index 5c35ebeb5b6b69..d2cd4ea8cafc36 100644 --- a/llvm/test/CodeGen/SPIRV/unnamed-global.ll +++ b/llvm/test/CodeGen/SPIRV/unnamed-global.ll @@ -1,6 +1,5 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} ; CHECK: %[[TyInt:.*]] = OpTypeInt 8 0 ; CHECK: %[[ConstInt:.*]] = OpConstant %[[TyInt]] 123 From bdc3eb50a472e8fd7bafc6d5a5b641825c11cfa3 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Thu, 6 Jun 2024 01:51:26 +0100 Subject: [PATCH 13/15] First pass at updating SPIR-V docs to reflect the addition of AMDGCN flavoured SPIR-V. --- llvm/docs/SPIRVUsage.rst | 94 +++++++++++++++++++++------------------- 1 file changed, 50 insertions(+), 44 deletions(-) diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst index de27f6b2372db6..2503fd9d3b2f51 100644 --- a/llvm/docs/SPIRVUsage.rst +++ b/llvm/docs/SPIRVUsage.rst @@ -17,9 +17,9 @@ in `the official SPIR-V specification */``unknown`` Generic SPIR-V target without any vendor-specific settings. + ``amd`` AMDGCN SPIR-V target, with support for target specific + builtins and ASM, meant to be consumed by AMDGCN toolchains. ===================== ============================================================== .. table:: Operating Systems - ===================== ============================================================ + ===================== ============================================================== OS Description - ===================== ============================================================ + ===================== ============================================================== **/``unknown`` Defaults to the OpenCL runtime. ``vulkan`` Vulkan shader runtime. ``vulkan1.2`` Vulkan 1.2 runtime, corresponding to SPIR-V 1.5. ``vulkan1.3`` Vulkan 1.3 runtime, corresponding to SPIR-V 1.6. - ===================== ============================================================ + ``amdhsa`` AMDHSA runtime, meant to be used on HSA compatible runtimes, + corresponding to SPIR-V 1.6. + ===================== ============================================================== .. table:: SPIR-V Environments @@ -114,15 +118,17 @@ Example: ``-target spirv64v1.0`` can be used to compile for SPIR-V version 1.0 with 64-bit pointer width. +``-target spirv64-amd-amdhsa`` can be used to compile for AMDGCN flavoured SPIR-V version 1.6 with 64-bit pointer width + .. _spirv-extensions: Extensions ---------- -The SPIR-V backend supports a variety of `extensions `_ -that enable or enhance features beyond the core SPIR-V specification. -These extensions can be enabled using the ``-spirv-extensions`` option -followed by the name of the extension(s) you wish to enable. Below is a +The SPIR-V backend supports a variety of `extensions `_ +that enable or enhance features beyond the core SPIR-V specification. +These extensions can be enabled using the ``-spirv-extensions`` option +followed by the name of the extension(s) you wish to enable. Below is a list of supported SPIR-V extensions, sorted alphabetically by their extension names: .. list-table:: Supported SPIR-V Extensions @@ -189,14 +195,14 @@ To enable all extensions except specified, specify ``all`` followed by a list of SPIR-V representation in LLVM IR ================================ -SPIR-V is intentionally designed for seamless integration with various Intermediate -Representations (IRs), including LLVM IR, facilitating straightforward mappings for -most of its entities. The development of the SPIR-V backend has been guided by a +SPIR-V is intentionally designed for seamless integration with various Intermediate +Representations (IRs), including LLVM IR, facilitating straightforward mappings for +most of its entities. The development of the SPIR-V backend has been guided by a principle of compatibility with the `Khronos Group SPIR-V LLVM Translator `_. -Consequently, the input representation accepted by the SPIR-V backend aligns closely -with that detailed in `the SPIR-V Representation in LLVM document `_. -This document, along with the sections that follow, delineate the main points and focus -on any differences between the LLVM IR that this backend processes and the conventions +Consequently, the input representation accepted by the SPIR-V backend aligns closely +with that detailed in `the SPIR-V Representation in LLVM document `_. +This document, along with the sections that follow, delineate the main points and focus +on any differences between the LLVM IR that this backend processes and the conventions used by other tools. .. _spirv-special-types: @@ -237,10 +243,10 @@ previous type has the representation Target Intrinsics ----------------- -The SPIR-V backend employs several LLVM IR intrinsics that facilitate various low-level -operations essential for generating correct and efficient SPIR-V code. These intrinsics -cover a range of functionalities from type assignment and memory management to control -flow and atomic operations. Below is a detailed table of selected intrinsics used in the +The SPIR-V backend employs several LLVM IR intrinsics that facilitate various low-level +operations essential for generating correct and efficient SPIR-V code. These intrinsics +cover a range of functionalities from type assignment and memory management to control +flow and atomic operations. Below is a detailed table of selected intrinsics used in the SPIR-V backend, along with their descriptions and argument details. .. list-table:: LLVM IR Intrinsics for SPIR-V @@ -369,80 +375,80 @@ SPIR-V backend, along with their descriptions and argument details. Builtin Functions ----------------- -The following section highlights the representation of SPIR-V builtins in LLVM IR, +The following section highlights the representation of SPIR-V builtins in LLVM IR, emphasizing builtins that do not have direct counterparts in LLVM. Instructions as Function Calls ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -SPIR-V builtins without direct LLVM counterparts are represented as LLVM function calls. -These functions, termed SPIR-V builtin functions, follow an IA64 mangling scheme with -SPIR-V-specific extensions. Parsing non-mangled calls to builtins is supported in some cases, +SPIR-V builtins without direct LLVM counterparts are represented as LLVM function calls. +These functions, termed SPIR-V builtin functions, follow an IA64 mangling scheme with +SPIR-V-specific extensions. Parsing non-mangled calls to builtins is supported in some cases, but not tested extensively. The general format is: .. code-block:: c __spirv_{OpCodeName}{_OptionalPostfixes} -Where `{OpCodeName}` is the SPIR-V opcode name sans the "Op" prefix, and -`{OptionalPostfixes}` are decoration-specific postfixes, if any. The mangling and -postfixes allow for the representation of SPIR-V's rich instruction set within LLVM's +Where `{OpCodeName}` is the SPIR-V opcode name sans the "Op" prefix, and +`{OptionalPostfixes}` are decoration-specific postfixes, if any. The mangling and +postfixes allow for the representation of SPIR-V's rich instruction set within LLVM's framework. Extended Instruction Sets ~~~~~~~~~~~~~~~~~~~~~~~~~ -SPIR-V defines several extended instruction sets for additional functionalities, such as -OpenCL-specific operations. In LLVM IR, these are represented by function calls to +SPIR-V defines several extended instruction sets for additional functionalities, such as +OpenCL-specific operations. In LLVM IR, these are represented by function calls to mangled builtins and selected based on the environment. For example: .. code-block:: c acos_f32 -represents the `acos` function from the OpenCL extended instruction set for a float32 +represents the `acos` function from the OpenCL extended instruction set for a float32 input. Builtin Variables ~~~~~~~~~~~~~~~~~ -SPIR-V builtin variables, which provide access to special hardware or execution model -properties, are mapped to either LLVM function calls or LLVM global variables. The +SPIR-V builtin variables, which provide access to special hardware or execution model +properties, are mapped to either LLVM function calls or LLVM global variables. The representation follows the naming convention: .. code-block:: c __spirv_BuiltIn{VariableName} -For instance, the SPIR-V builtin `GlobalInvocationId` is accessible in LLVM IR as +For instance, the SPIR-V builtin `GlobalInvocationId` is accessible in LLVM IR as `__spirv_BuiltInGlobalInvocationId`. Vector Load and Store Builtins ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -SPIR-V's capabilities for loading and storing vectors are represented in LLVM IR using -functions that mimic the SPIR-V instructions. These builtins handle cases that LLVM's -native instructions do not directly support, enabling fine-grained control over memory +SPIR-V's capabilities for loading and storing vectors are represented in LLVM IR using +functions that mimic the SPIR-V instructions. These builtins handle cases that LLVM's +native instructions do not directly support, enabling fine-grained control over memory operations. Atomic Operations ~~~~~~~~~~~~~~~~~ -SPIR-V's atomic operations, especially those operating on floating-point data, are -represented in LLVM IR with corresponding function calls. These builtins ensure -atomicity in operations where LLVM might not have direct support, essential for parallel +SPIR-V's atomic operations, especially those operating on floating-point data, are +represented in LLVM IR with corresponding function calls. These builtins ensure +atomicity in operations where LLVM might not have direct support, essential for parallel execution and synchronization. Image Operations ~~~~~~~~~~~~~~~~ -SPIR-V provides extensive support for image and sampler operations, which LLVM -represents through function calls to builtins. These include image reads, writes, and +SPIR-V provides extensive support for image and sampler operations, which LLVM +represents through function calls to builtins. These include image reads, writes, and queries, allowing detailed manipulation of image data and parameters. Group and Subgroup Operations ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -For workgroup and subgroup operations, LLVM uses function calls to represent SPIR-V's -group-based instructions. These builtins facilitate group synchronization, data sharing, +For workgroup and subgroup operations, LLVM uses function calls to represent SPIR-V's +group-based instructions. These builtins facilitate group synchronization, data sharing, and collective operations essential for efficient parallel computation. From b088c724efa696e6b89319066c32ccfaeeb47085 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Thu, 6 Jun 2024 13:39:22 +0100 Subject: [PATCH 14/15] Fix erroneous versioning claim. --- llvm/docs/SPIRVUsage.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst index 2503fd9d3b2f51..70865b95cb3932 100644 --- a/llvm/docs/SPIRVUsage.rst +++ b/llvm/docs/SPIRVUsage.rst @@ -118,7 +118,7 @@ Example: ``-target spirv64v1.0`` can be used to compile for SPIR-V version 1.0 with 64-bit pointer width. -``-target spirv64-amd-amdhsa`` can be used to compile for AMDGCN flavoured SPIR-V version 1.6 with 64-bit pointer width +``-target spirv64-amd-amdhsa`` can be used to compile for AMDGCN flavoured SPIR-V with 64-bit pointer width. .. _spirv-extensions: From e85b557f7e5e02e8a80ed3c42930010b1f55e4b3 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Thu, 6 Jun 2024 13:42:43 +0100 Subject: [PATCH 15/15] Remove function pointer tests. --- .../fp_const_amdgcn.ll | 35 ------------------- .../fp_two_calls_amdgcn.ll | 35 ------------------- 2 files changed, 70 deletions(-) delete mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const_amdgcn.ll delete mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls_amdgcn.ll diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const_amdgcn.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const_amdgcn.ll deleted file mode 100644 index 8e1b0574725654..00000000000000 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const_amdgcn.ll +++ /dev/null @@ -1,35 +0,0 @@ -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} - -; CHECK-DAG: OpCapability Int8 -; CHECK-DAG: OpCapability GenericPointer -; CHECK-DAG: OpCapability FunctionPointersINTEL -; CHECK-DAG: OpCapability Int64 -; CHECK: OpExtension "SPV_INTEL_function_pointers" -; CHECK-DAG: %[[TyInt8:.*]] = OpTypeInt 8 0 -; CHECK-DAG: %[[TyVoid:.*]] = OpTypeVoid -; CHECK-DAG: %[[TyInt64:.*]] = OpTypeInt 64 0 -; CHECK-DAG: %[[TyFunFp:.*]] = OpTypeFunction %[[TyVoid]] %[[TyInt64]] -; CHECK-DAG: %[[ConstInt64:.*]] = OpConstant %[[TyInt64]] 42 -; CHECK-DAG: %[[TyPtrFunFp:.*]] = OpTypePointer Generic %[[TyFunFp]] -; CHECK-DAG: %[[ConstFunFp:.*]] = OpConstantFunctionPointerINTEL %[[TyPtrFunFp]] %[[DefFunFp:.*]] -; CHECK: %[[FunPtr1:.*]] = OpBitcast %[[#]] %[[ConstFunFp]] -; CHECK: %[[FunPtr2:.*]] = OpLoad %[[#]] %[[FunPtr1]] -; CHECK: OpFunctionPointerCallINTEL %[[TyInt64]] %[[FunPtr2]] %[[ConstInt64]] -; CHECK: OpReturn -; CHECK: OpFunctionEnd -; CHECK: %[[DefFunFp]] = OpFunction %[[TyVoid]] None %[[TyFunFp]] - -target triple = "spir64-unknown-unknown" - -define spir_kernel void @test() { -entry: - %0 = load ptr addrspace(4), ptr addrspace(4) @foo - %1 = call addrspace(4) i64 %0(i64 42) - ret void -} - -define void @foo(i64 %a) addrspace(4) { -entry: - ret void -} diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls_amdgcn.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls_amdgcn.ll deleted file mode 100644 index 3b9e721668c368..00000000000000 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_two_calls_amdgcn.ll +++ /dev/null @@ -1,35 +0,0 @@ -; RUN: llc -O0 -mtriple=spirv64-amd-amdhsa --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s -; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %} - -; CHECK-DAG: OpCapability Int8 -; CHECK-DAG: OpCapability GenericPointer -; CHECK-DAG: OpCapability FunctionPointersINTEL -; CHECK-DAG: OpCapability Int64 -; CHECK: OpExtension "SPV_INTEL_function_pointers" -; CHECK-DAG: %[[TyInt8:.*]] = OpTypeInt 8 0 -; CHECK-DAG: %[[TyVoid:.*]] = OpTypeVoid -; CHECK-DAG: %[[TyFloat32:.*]] = OpTypeFloat 32 -; CHECK-DAG: %[[TyInt64:.*]] = OpTypeInt 64 0 -; CHECK-DAG: %[[TyPtrInt8:.*]] = OpTypePointer Generic %[[TyInt8]] -; CHECK-DAG: %[[TyFunFp:.*]] = OpTypeFunction %[[TyFloat32]] %[[TyPtrInt8]] -; CHECK-DAG: %[[TyFunBar:.*]] = OpTypeFunction %[[TyInt64]] %[[TyPtrInt8]] %[[TyPtrInt8]] -; CHECK-DAG: %[[TyPtrFunFp:.*]] = OpTypePointer Function %[[TyFunFp]] -; CHECK-DAG: %[[TyPtrFunBar:.*]] = OpTypePointer Function %[[TyFunBar]] -; CHECK-DAG: %[[TyFunTest:.*]] = OpTypeFunction %[[TyVoid]] %[[TyPtrInt8]] %[[TyPtrInt8]] %[[TyPtrInt8]] -; CHECK: %[[FunTest:.*]] = OpFunction %[[TyVoid]] None %[[TyFunTest]] -; CHECK: %[[ArgFp:.*]] = OpFunctionParameter %[[TyPtrInt8]] -; CHECK: %[[ArgData:.*]] = OpFunctionParameter %[[TyPtrInt8]] -; CHECK: %[[ArgBar:.*]] = OpFunctionParameter %[[TyPtrInt8]] -; CHECK: OpFunctionPointerCallINTEL %[[TyFloat32]] %[[ArgFp]] %[[ArgBar]] -; CHECK: OpFunctionPointerCallINTEL %[[TyInt64]] %[[ArgBar]] %[[ArgFp]] %[[ArgData]] -; CHECK: OpReturn -; CHECK: OpFunctionEnd - -target triple = "spir64-unknown-unknown" - -define spir_kernel void @test(ptr addrspace(4) %fp, ptr addrspace(4) %data, ptr addrspace(4) %bar) { -entry: - %0 = call spir_func addrspace(4) float %fp(ptr addrspace(4) %bar) - %1 = call spir_func addrspace(4) i64 %bar(ptr addrspace(4) %fp, ptr addrspace(4) %data) - ret void -}