From 9fbfc1b9cbaf9826256076f114c3a390ffe94681 Mon Sep 17 00:00:00 2001 From: Benoit Jacob Date: Wed, 11 Oct 2023 14:52:13 -0400 Subject: [PATCH] inline-asm-docs --- llvm/docs/LangRef.rst | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 1883e9f6290b1..0e5621f9b650a 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -5282,7 +5282,6 @@ X86: - ``O``: An immediate integer between 0 and 127. - ``e``: An immediate 32-bit signed integer. - ``Z``: An immediate 32-bit unsigned integer. -- ``o``, ``v``: Treated the same as ``m``, at the moment. - ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit ``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d`` registers, and on X86-64, it is all of the integer registers. @@ -5293,10 +5292,13 @@ X86: existed since i386, and can be accessed without the REX prefix. - ``f``: A 32, 64, or 80-bit '387 FPU stack pseudo-register. - ``y``: A 64-bit MMX register, if MMX is enabled. -- ``x``: If SSE is enabled: a 32 or 64-bit scalar operand, or 128-bit vector +- ``v``: If SSE is enabled: a 32 or 64-bit scalar operand, or 128-bit vector operand in a SSE register. If AVX is also enabled, can also be a 256-bit vector operand in an AVX register. If AVX-512 is also enabled, can also be a - 512-bit vector operand in an AVX512 register, Otherwise, an error. + 512-bit vector operand in an AVX512 register. Otherwise, an error. +- ``x``: The same as ``v``, except that when AVX-512 is enabled, the ``x`` code + only allocates into the first 16 AVX-512 registers, while the ``v`` code + allocates into any of the 32 AVX-512 registers. - ``Y``: The same as ``x``, if *SSE2* is enabled, otherwise an error. - ``A``: Special case: allocates EAX first, then EDX, for a single operand (in 32-bit mode, a 64-bit integer operand will get split into two registers). It