diff --git a/llvm/include/llvm/MC/MCAsmBackend.h b/llvm/include/llvm/MC/MCAsmBackend.h index b105a294d875c5..505bd1f59dd439 100644 --- a/llvm/include/llvm/MC/MCAsmBackend.h +++ b/llvm/include/llvm/MC/MCAsmBackend.h @@ -96,6 +96,7 @@ class MCAsmBackend { virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, + const uint64_t Value, const MCSubtargetInfo *STI) { return false; } diff --git a/llvm/lib/MC/MCAssembler.cpp b/llvm/lib/MC/MCAssembler.cpp index 3c18d0832efcc7..3e5e0151d265e2 100644 --- a/llvm/lib/MC/MCAssembler.cpp +++ b/llvm/lib/MC/MCAssembler.cpp @@ -222,7 +222,7 @@ bool MCAssembler::evaluateFixup(const MCFixup &Fixup, const MCFragment *DF, // Let the backend force a relocation if needed. if (IsResolved && - getBackend().shouldForceRelocation(*this, Fixup, Target, STI)) { + getBackend().shouldForceRelocation(*this, Fixup, Target, Value, STI)) { IsResolved = false; WasForced = true; } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp index 3ba0f2a2682855..337b81d68c93a0 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp @@ -98,7 +98,7 @@ class AArch64AsmBackend : public MCAsmBackend { unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t Value, const MCSubtargetInfo *STI) override; }; @@ -520,6 +520,7 @@ bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, bool AArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, + const uint64_t, const MCSubtargetInfo *STI) { unsigned Kind = Fixup.getKind(); if (Kind >= FirstLiteralRelocationKind) diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp index 3172a83e5a1fe0..8c4314e6d6cc4a 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -53,7 +53,7 @@ class AMDGPUAsmBackend : public MCAsmBackend { std::optional getFixupKind(StringRef Name) const override; const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, uint64_t Value, const MCSubtargetInfo *STI) override; }; @@ -196,7 +196,7 @@ const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo( bool AMDGPUAsmBackend::shouldForceRelocation(const MCAssembler &, const MCFixup &Fixup, - const MCValue &, + const MCValue &, const uint64_t, const MCSubtargetInfo *STI) { return Fixup.getKind() >= FirstLiteralRelocationKind; } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index d0e759d3356f10..6e2886a1929230 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -955,7 +955,7 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm, bool ARMAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t, const MCSubtargetInfo *STI) { const MCSymbolRefExpr *A = Target.getSymA(); const MCSymbol *Sym = A ? &A->getSymbol() : nullptr; diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h index f33cd8b7c2425a..2932e68cd98e56 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h @@ -36,7 +36,7 @@ class ARMAsmBackend : public MCAsmBackend { const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t Value, const MCSubtargetInfo *STI) override; unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp index fd35f8fcb8e7b8..fbed25157a44e0 100644 --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp @@ -31,22 +31,6 @@ namespace adjust { using namespace llvm; -static void signed_width(unsigned Width, uint64_t Value, - std::string Description, const MCFixup &Fixup, - MCContext *Ctx) { - if (!isIntN(Width, Value)) { - std::string Diagnostic = "out of range " + Description; - - int64_t Min = minIntN(Width); - int64_t Max = maxIntN(Width); - - Diagnostic += " (expected an integer in the range " + std::to_string(Min) + - " to " + std::to_string(Max) + ")"; - - Ctx->reportError(Fixup.getLoc(), Diagnostic); - } -} - static void unsigned_width(unsigned Width, uint64_t Value, std::string Description, const MCFixup &Fixup, MCContext *Ctx) { @@ -74,8 +58,8 @@ static void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value, } /// Adjusts the value of a relative branch target before fixup application. -static void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup, - uint64_t &Value, MCContext *Ctx) { +static bool adjustRelativeBranch(unsigned Size, const MCFixup &Fixup, + uint64_t &Value, const MCSubtargetInfo *STI) { // Jumps are relative to the current instruction. Value -= 2; @@ -83,8 +67,9 @@ static void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup, // one. Size += 1; - if (!isIntN(Size, Value) && - Ctx->getSubtargetInfo()->hasFeature(AVR::FeatureWrappingRjmp)) { + assert(STI && "STI can not be NULL"); + + if (!isIntN(Size, Value) && STI->hasFeature(AVR::FeatureWrappingRjmp)) { const int32_t FlashSize = 0x2000; int32_t SignedValue = Value; @@ -96,10 +81,14 @@ static void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup, } } - signed_width(Size, Value, std::string("branch target"), Fixup, Ctx); + if (!isIntN(Size, Value)) { + return false; + } // Rightshifts the value by one. AVR::fixups::adjustBranchTarget(Value); + + return true; } /// 22-bit absolute fixup. @@ -126,7 +115,9 @@ static void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value, /// Offset of 0 (so the result is left shifted by 3 bits before application). static void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx) { - adjustRelativeBranch(Size, Fixup, Value, Ctx); + if (!adjustRelativeBranch(Size, Fixup, Value, Ctx->getSubtargetInfo())) { + llvm_unreachable("should've been emitted as a relocation"); + } // Because the value may be negative, we must mask out the sign bits Value &= 0x7f; @@ -140,7 +131,9 @@ static void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value, /// Offset of 0 (so the result isn't left-shifted before application). static void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx) { - adjustRelativeBranch(Size, Fixup, Value, Ctx); + if (!adjustRelativeBranch(Size, Fixup, Value, Ctx->getSubtargetInfo())) { + llvm_unreachable("should've been emitted as a relocation"); + } // Because the value may be negative, we must mask out the sign bits Value &= 0xfff; @@ -181,7 +174,7 @@ static void fixup_port5(const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx) { Value <<= 3; } -/// 6-bit port number fixup on the `IN` family of instructions. +/// 6-bit port number fixup on the IN family of instructions. /// /// Resolves to: /// 1011 0AAd dddd AAAA @@ -512,14 +505,25 @@ bool AVRAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, bool AVRAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, + const uint64_t Value, const MCSubtargetInfo *STI) { switch ((unsigned)Fixup.getKind()) { default: return Fixup.getKind() >= FirstLiteralRelocationKind; + case AVR::fixup_7_pcrel: - case AVR::fixup_13_pcrel: - // Always resolve relocations for PC-relative branches - return false; + case AVR::fixup_13_pcrel: { + uint64_t ValueEx = Value; + uint64_t Size = AVRAsmBackend::getFixupKindInfo(Fixup.getKind()).TargetSize; + + // If the jump is too large to encode it, fall back to a relocation. + // + // Note that trying to actually link that relocation *would* fail, but the + // hopes are that the module we're currently compiling won't be actually + // linked to the final binary. + return !adjust::adjustRelativeBranch(Size, Fixup, ValueEx, STI); + } + case AVR::fixup_call: return true; } diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h index 2337319590324d..1a9ae94f2f49e9 100644 --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h @@ -53,7 +53,7 @@ class AVRAsmBackend : public MCAsmBackend { const MCSubtargetInfo *STI) const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t Value, const MCSubtargetInfo *STI) override; private: diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp index dd06971e1cf976..ebe12fa6afd1fd 100644 --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp @@ -262,6 +262,7 @@ bool CSKYAsmBackend::mayNeedRelaxation(const MCInst &Inst, bool CSKYAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, + const uint64_t /*Value*/, const MCSubtargetInfo * /*STI*/) { if (Fixup.getKind() >= FirstLiteralRelocationKind) return true; diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h index 4b659f401d253a..faa84a6ef71d58 100644 --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h @@ -52,7 +52,7 @@ class CSKYAsmBackend : public MCAsmBackend { const MCSubtargetInfo *STI) const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t Value, const MCSubtargetInfo *STI) override; std::unique_ptr diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index 7864d45d594ac5..98b1dde8fa3fc2 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -201,7 +201,7 @@ class HexagonAsmBackend : public MCAsmBackend { } bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t, const MCSubtargetInfo *STI) override { switch(Fixup.getTargetKind()) { default: diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp index 0c24008301d022..eb4f6edc117a4a 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp @@ -251,6 +251,7 @@ bool LoongArchAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm, bool LoongArchAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, + const uint64_t, const MCSubtargetInfo *STI) { if (Fixup.getKind() >= FirstLiteralRelocationKind) return true; diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h index 9df4ff22625c68..adbfd01410a4e6 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h @@ -57,7 +57,7 @@ class LoongArchAsmBackend : public MCAsmBackend { MCAlignFragment &AF) override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t Value, const MCSubtargetInfo *STI) override; unsigned getNumFixupKinds() const override { diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index 6001d9d51d16ac..4af6768b13cc90 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -542,6 +542,7 @@ bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, bool MipsAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, + const uint64_t, const MCSubtargetInfo *STI) { if (Fixup.getKind() >= FirstLiteralRelocationKind) return true; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h index 799dd569f1ad90..3a2c5e824a53b0 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -55,7 +55,7 @@ class MipsAsmBackend : public MCAsmBackend { const MCSubtargetInfo *STI) const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t Value, const MCSubtargetInfo *STI) override; bool isMicroMips(const MCSymbol *Sym) const override; diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp index ef36af1a5e6660..9077aa7de5a373 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -161,7 +161,7 @@ class PPCAsmBackend : public MCAsmBackend { } bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t, const MCSubtargetInfo *STI) override { MCFixupKind Kind = Fixup.getKind(); switch ((unsigned)Kind) { diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index eab4a5e77d96e5..270c4bb3b72450 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -112,6 +112,7 @@ RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, + const uint64_t, const MCSubtargetInfo *STI) { if (Fixup.getKind() >= FirstLiteralRelocationKind) return true; @@ -567,7 +568,7 @@ bool RISCVAsmBackend::evaluateTargetFixup(const MCAssembler &Asm, Value = Asm.getSymbolOffset(SA) + AUIPCTarget.getConstant(); Value -= Asm.getFragmentOffset(*AUIPCDF) + AUIPCFixup->getOffset(); - if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget, STI)) { + if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget, Value, STI)) { WasForced = true; return false; } diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h index 886e7efe76bcb0..275f5bb9423272 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h @@ -65,7 +65,7 @@ class RISCVAsmBackend : public MCAsmBackend { createObjectTargetWriter() const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t Value, const MCSubtargetInfo *STI) override; bool fixupNeedsRelaxationAdvanced(const MCAssembler &Asm, diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp index 66826fadddd2e3..597b9a779e843d 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -273,7 +273,7 @@ namespace { } bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t, const MCSubtargetInfo *STI) override { if (Fixup.getKind() >= FirstLiteralRelocationKind) return true; diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp index ed174f7ac01fa3..cbf322a94704bc 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp @@ -116,7 +116,7 @@ class SystemZMCAsmBackend : public MCAsmBackend { std::optional getFixupKind(StringRef Name) const override; const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t Value, const MCSubtargetInfo *STI) override; void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef Data, @@ -161,7 +161,7 @@ SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { bool SystemZMCAsmBackend::shouldForceRelocation(const MCAssembler &, const MCFixup &Fixup, - const MCValue &, + const MCValue &, const uint64_t, const MCSubtargetInfo *STI) { return Fixup.getKind() >= FirstLiteralRelocationKind; } diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp index f06a2ab71f241c..2e1ab8d599eead 100644 --- a/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp +++ b/llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp @@ -132,7 +132,7 @@ class VEAsmBackend : public MCAsmBackend { } bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t, const MCSubtargetInfo *STI) override { switch ((VE::Fixups)Fixup.getKind()) { default: diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp index 144a0c99fdf435..e234d320b2a194 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -172,7 +172,7 @@ class X86AsmBackend : public MCAsmBackend { const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, - const MCValue &Target, + const MCValue &Target, const uint64_t Value, const MCSubtargetInfo *STI) override; void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, @@ -659,6 +659,7 @@ const MCFixupKindInfo &X86AsmBackend::getFixupKindInfo(MCFixupKind Kind) const { bool X86AsmBackend::shouldForceRelocation(const MCAssembler &, const MCFixup &Fixup, const MCValue &, + const uint64_t, const MCSubtargetInfo *STI) { return Fixup.getKind() >= FirstLiteralRelocationKind; } diff --git a/llvm/test/CodeGen/AVR/branch-relaxation-long-backward.ll b/llvm/test/CodeGen/AVR/branch-relaxation-long-backward.ll index 7c915e1dc3ef69..18536b1148e7bd 100644 --- a/llvm/test/CodeGen/AVR/branch-relaxation-long-backward.ll +++ b/llvm/test/CodeGen/AVR/branch-relaxation-long-backward.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=avr -mcpu=attiny85 -filetype=obj -o - | llvm-objdump --mcpu=attiny85 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=ATTINY85 %s -; RUN: not llc < %s -mtriple=avr -mcpu=avr25 -filetype=obj -o - 2>&1 | FileCheck --check-prefix=AVR25 %s +; RUN: llc < %s -mtriple=avr -mcpu=avr25 -filetype=obj -o - | llvm-objdump --mcpu=avr25 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=AVR25 %s ; RUN: llc < %s -mtriple=avr -mcpu=avr3 -filetype=obj -o - | llvm-objdump --mcpu=avr3 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=AVR3 %s ; ATTINY85:
: @@ -10,7 +10,14 @@ ; ATTINY85: ldi r24, 0x3 ; ATTINY85-NEXT: ret -; AVR25: error: out of range branch target (expected an integer in the range -4096 to 4095) +; AVR25:
: +; AVR25-NEXT: andi r24, 0x1 +; AVR25: cpi r24, 0x0 +; AVR25-NEXT: breq .+2 +; AVR25-NEXT: rjmp .-2 +; AVR25-NEXT: R_AVR_13_PCREL .text+0x2 +; AVR25: ldi r24, 0x3 +; AVR25-NEXT: ret ; AVR3:
: ; AVR3-NEXT: andi r24, 0x1 diff --git a/llvm/test/CodeGen/AVR/branch-relaxation-long-forward.ll b/llvm/test/CodeGen/AVR/branch-relaxation-long-forward.ll index 24ddb36c68839e..dd9b9b929d6992 100644 --- a/llvm/test/CodeGen/AVR/branch-relaxation-long-forward.ll +++ b/llvm/test/CodeGen/AVR/branch-relaxation-long-forward.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=avr -mcpu=attiny85 -filetype=obj -o - | llvm-objdump --mcpu=attiny85 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=ATTINY85 %s -; RUN: not llc < %s -mtriple=avr -mcpu=avr25 -filetype=obj -o - 2>&1 | FileCheck --check-prefix=AVR25 %s +; RUN: llc < %s -mtriple=avr -mcpu=avr25 -filetype=obj -o - | llvm-objdump --mcpu=avr25 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=AVR25 %s ; RUN: llc < %s -mtriple=avr -mcpu=avr3 -filetype=obj -o - | llvm-objdump --mcpu=avr3 -dr --no-show-raw-insn --no-leading-addr - | FileCheck --check-prefix=AVR3 %s ; ATTINY85:
: @@ -10,7 +10,14 @@ ; ATTINY85: ldi r24, 0x3 ; ATTINY85-NEXT: ret -; AVR25: error: out of range branch target (expected an integer in the range -4096 to 4095) +; AVR25:
: +; AVR25-NEXT: andi r24, 0x1 +; AVR25-NEXT: cpi r24, 0x0 +; AVR25-NEXT: brne .+2 +; AVR25-NEXT: rjmp .-2 +; AVR25-NEXT: R_AVR_13_PCREL .text+0x100c +; AVR25: ldi r24, 0x3 +; AVR25-NEXT: ret ; AVR3:
: ; AVR3-NEXT: andi r24, 0x1