diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def index 521cbc2dc278f9..3fad00e2caf21f 100644 --- a/llvm/include/llvm/IR/VPIntrinsics.def +++ b/llvm/include/llvm/IR/VPIntrinsics.def @@ -129,11 +129,6 @@ #define VP_PROPERTY_MEMOP(POINTERPOS, DATAPOS) #endif -// Map this VP reduction intrinsic to its reduction operand positions. -#ifndef VP_PROPERTY_REDUCTION -#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS) -#endif - // A property to infer VP binary-op SDNode opcodes automatically. #ifndef VP_PROPERTY_BINARYOP #define VP_PROPERTY_BINARYOP @@ -144,13 +139,6 @@ #define VP_PROPERTY_CASTOP #endif -// This VP Intrinsic is a comparison operation -// The condition code arg is at CCPOS and accepts floating-point condition -// codes if ISFP is set, else it accepts integer condition codes. -#ifndef VP_PROPERTY_CMP -#define VP_PROPERTY_CMP(CCPOS, ISFP) -#endif - /// } Property Macros ///// Integer Arithmetic { @@ -567,7 +555,6 @@ END_REGISTER_VP_SDNODE(VP_SETCC) BEGIN_REGISTER_VP_INTRINSIC(vp_fcmp, 3, 4) HELPER_MAP_VPID_TO_VPSD(vp_fcmp, VP_SETCC) VP_PROPERTY_FUNCTIONAL_OPC(FCmp) -VP_PROPERTY_CMP(2, true) VP_PROPERTY_CONSTRAINEDFP(0, 1, experimental_constrained_fcmp) END_REGISTER_VP_INTRINSIC(vp_fcmp) @@ -575,7 +562,6 @@ END_REGISTER_VP_INTRINSIC(vp_fcmp) BEGIN_REGISTER_VP_INTRINSIC(vp_icmp, 3, 4) HELPER_MAP_VPID_TO_VPSD(vp_icmp, VP_SETCC) VP_PROPERTY_FUNCTIONAL_OPC(ICmp) -VP_PROPERTY_CMP(2, false) END_REGISTER_VP_INTRINSIC(vp_icmp) ///// } Comparisons @@ -655,7 +641,6 @@ END_REGISTER_VP(vp_gather, VP_GATHER) BEGIN_REGISTER_VP(VPID, 2, 3, VPSD, 1) \ VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \ VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \ - VP_PROPERTY_REDUCTION(0, 1) \ END_REGISTER_VP(VPID, VPSD) // llvm.vp.reduce.add(start,x,mask,vlen) @@ -725,13 +710,11 @@ HELPER_REGISTER_REDUCTION_VP(vp_reduce_fminimum, VP_REDUCE_FMINIMUM, #define HELPER_REGISTER_REDUCTION_SEQ_VP(VPID, VPSD, SEQ_VPSD, SDOPC, SEQ_SDOPC, INTRIN) \ BEGIN_REGISTER_VP_INTRINSIC(VPID, 2, 3) \ BEGIN_REGISTER_VP_SDNODE(VPSD, 1, VPID, 2, 3) \ - VP_PROPERTY_REDUCTION(0, 1) \ VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \ END_REGISTER_VP_SDNODE(VPSD) \ BEGIN_REGISTER_VP_SDNODE(SEQ_VPSD, 1, VPID, 2, 3) \ HELPER_MAP_VPID_TO_VPSD(VPID, SEQ_VPSD) \ VP_PROPERTY_FUNCTIONAL_SDOPC(SEQ_SDOPC) \ - VP_PROPERTY_REDUCTION(0, 1) \ END_REGISTER_VP_SDNODE(SEQ_VPSD) \ VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \ END_REGISTER_VP_INTRINSIC(VPID) @@ -796,11 +779,9 @@ END_REGISTER_VP(experimental_vp_splat, EXPERIMENTAL_VP_SPLAT) #undef HELPER_MAP_VPID_TO_VPSD #undef VP_PROPERTY_BINARYOP #undef VP_PROPERTY_CASTOP -#undef VP_PROPERTY_CMP #undef VP_PROPERTY_CONSTRAINEDFP #undef VP_PROPERTY_FUNCTIONAL_INTRINSIC #undef VP_PROPERTY_FUNCTIONAL_OPC #undef VP_PROPERTY_FUNCTIONAL_SDOPC #undef VP_PROPERTY_NO_FUNCTIONAL #undef VP_PROPERTY_MEMOP -#undef VP_PROPERTY_REDUCTION diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 9c7a43064ecf62..9efcd3f25797b5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -503,13 +503,26 @@ bool ISD::isVPBinaryOp(unsigned Opcode) { bool ISD::isVPReduction(unsigned Opcode) { switch (Opcode) { default: - break; -#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD: -#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true; -#define END_REGISTER_VP_SDNODE(VPSD) break; -#include "llvm/IR/VPIntrinsics.def" + return false; + case ISD::VP_REDUCE_ADD: + case ISD::VP_REDUCE_MUL: + case ISD::VP_REDUCE_AND: + case ISD::VP_REDUCE_OR: + case ISD::VP_REDUCE_XOR: + case ISD::VP_REDUCE_SMAX: + case ISD::VP_REDUCE_SMIN: + case ISD::VP_REDUCE_UMAX: + case ISD::VP_REDUCE_UMIN: + case ISD::VP_REDUCE_FMAX: + case ISD::VP_REDUCE_FMIN: + case ISD::VP_REDUCE_FMAXIMUM: + case ISD::VP_REDUCE_FMINIMUM: + case ISD::VP_REDUCE_FADD: + case ISD::VP_REDUCE_FMUL: + case ISD::VP_REDUCE_SEQ_FADD: + case ISD::VP_REDUCE_SEQ_FMUL: + return true; } - return false; } /// The operand position of the vector mask. diff --git a/llvm/lib/IR/IntrinsicInst.cpp b/llvm/lib/IR/IntrinsicInst.cpp index 7680fd02562316..966fa62abd94fe 100644 --- a/llvm/lib/IR/IntrinsicInst.cpp +++ b/llvm/lib/IR/IntrinsicInst.cpp @@ -738,14 +738,25 @@ Function *VPIntrinsic::getDeclarationForParams(Module *M, Intrinsic::ID VPID, bool VPReductionIntrinsic::isVPReduction(Intrinsic::ID ID) { switch (ID) { + case Intrinsic::vp_reduce_add: + case Intrinsic::vp_reduce_mul: + case Intrinsic::vp_reduce_and: + case Intrinsic::vp_reduce_or: + case Intrinsic::vp_reduce_xor: + case Intrinsic::vp_reduce_smax: + case Intrinsic::vp_reduce_smin: + case Intrinsic::vp_reduce_umax: + case Intrinsic::vp_reduce_umin: + case Intrinsic::vp_reduce_fmax: + case Intrinsic::vp_reduce_fmin: + case Intrinsic::vp_reduce_fmaximum: + case Intrinsic::vp_reduce_fminimum: + case Intrinsic::vp_reduce_fadd: + case Intrinsic::vp_reduce_fmul: + return true; default: - break; -#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID: -#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true; -#define END_REGISTER_VP_INTRINSIC(VPID) break; -#include "llvm/IR/VPIntrinsics.def" + return false; } - return false; } bool VPCastIntrinsic::isVPCast(Intrinsic::ID ID) { @@ -763,13 +774,11 @@ bool VPCastIntrinsic::isVPCast(Intrinsic::ID ID) { bool VPCmpIntrinsic::isVPCmp(Intrinsic::ID ID) { switch (ID) { default: - break; -#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID: -#define VP_PROPERTY_CMP(CCPOS, ...) return true; -#define END_REGISTER_VP_INTRINSIC(VPID) break; -#include "llvm/IR/VPIntrinsics.def" + return false; + case Intrinsic::vp_fcmp: + case Intrinsic::vp_icmp: + return true; } - return false; } bool VPBinOpIntrinsic::isVPBinOp(Intrinsic::ID ID) { @@ -803,22 +812,10 @@ static ICmpInst::Predicate getIntPredicateFromMD(const Value *Op) { } CmpInst::Predicate VPCmpIntrinsic::getPredicate() const { - bool IsFP = true; - std::optional CCArgIdx; - switch (getIntrinsicID()) { - default: - break; -#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID: -#define VP_PROPERTY_CMP(CCPOS, ISFP) \ - CCArgIdx = CCPOS; \ - IsFP = ISFP; \ - break; -#define END_REGISTER_VP_INTRINSIC(VPID) break; -#include "llvm/IR/VPIntrinsics.def" - } - assert(CCArgIdx && "Unexpected vector-predicated comparison"); - return IsFP ? getFPPredicateFromMD(getArgOperand(*CCArgIdx)) - : getIntPredicateFromMD(getArgOperand(*CCArgIdx)); + assert(isVPCmp(getIntrinsicID())); + return getIntrinsicID() == Intrinsic::vp_fcmp + ? getFPPredicateFromMD(getArgOperand(2)) + : getIntPredicateFromMD(getArgOperand(2)); } unsigned VPReductionIntrinsic::getVectorParamPos() const { @@ -831,27 +828,15 @@ unsigned VPReductionIntrinsic::getStartParamPos() const { std::optional VPReductionIntrinsic::getVectorParamPos(Intrinsic::ID ID) { - switch (ID) { -#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID: -#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS) return VECTORPOS; -#define END_REGISTER_VP_INTRINSIC(VPID) break; -#include "llvm/IR/VPIntrinsics.def" - default: - break; - } + if (isVPReduction(ID)) + return 1; return std::nullopt; } std::optional VPReductionIntrinsic::getStartParamPos(Intrinsic::ID ID) { - switch (ID) { -#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID: -#define VP_PROPERTY_REDUCTION(STARTPOS, VECTORPOS) return STARTPOS; -#define END_REGISTER_VP_INTRINSIC(VPID) break; -#include "llvm/IR/VPIntrinsics.def" - default: - break; - } + if (isVPReduction(ID)) + return 0; return std::nullopt; }