uart04.c

//-------------------------------------------------------------------------
//-------------------------------------------------------------------------

extern void PUT32 ( unsigned int, unsigned int );
extern unsigned int GET32 ( unsigned int );
extern void dummy ( unsigned int );
extern void enable_irq ( void );
extern void enable_fiq ( void );

#define PBASE 0x3F000000

#define GPFSEL1 (PBASE+0x00200004)
#define GPSET0  (PBASE+0x0020001C)
#define GPCLR0  (PBASE+0x00200028)
#define GPPUD       (PBASE+0x00200094)
#define GPPUDCLK0   (PBASE+0x00200098)

#define AUX_ENABLES     (PBASE+0x00215004)
//primary: read/write from/to fifos
//DLAB=1: 7:0 - access to LS 9 bits of baud rate (R/W)
//DLAB=0: 7:0 data writen is put in the trans fifo (if not full) (W)
//DLAB=0: 7:0 data taken from the receive fifo (if not empty)
#define AUX_MU_IO_REG   (PBASE+0x00215040)
#define AUX_MU_IER_REG  (PBASE+0x00215044)
#define AUX_MU_IIR_REG  (PBASE+0x00215048)
#define AUX_MU_LCR_REG  (PBASE+0x0021504C)
#define AUX_MU_MCR_REG  (PBASE+0x00215050)
#define AUX_MU_LSR_REG  (PBASE+0x00215054)
#define AUX_MU_MSR_REG  (PBASE+0x00215058)
#define AUX_MU_SCRATCH  (PBASE+0x0021505C)
#define AUX_MU_CNTL_REG (PBASE+0x00215060)
#define AUX_MU_STAT_REG (PBASE+0x00215064)
#define AUX_MU_BAUD_REG (PBASE+0x00215068)

#define IRQ_BASIC (PBASE+0x0000B200)
#define IRQ_PEND1 (PBASE+0x0000B204)
#define IRQ_PEND2 (PBASE+0x0000B208)
#define IRQ_FIQ_CONTROL (PBASE+0x0000B210)
#define IRQ_ENABLE1 (PBASE+0x0000B210)
#define IRQ_ENABLE2 (PBASE+0x0000B214)
#define IRQ_ENABLE_BASIC (PBASE+0x0000B218)
#define IRQ_DISABLE1 (PBASE+0x0000B21C)
#define IRQ_DISABLE2 (PBASE+0x0000B220)
#define IRQ_DISABLE_BASIC (PBASE+0x0000B224)


//GPIO14  TXD0 and TXD1
//GPIO15  RXD0 and RXD1
//alt function 5 for uart1
//alt function 0 for uart0

//((250,000,000/115200)/8)-1 = 270
//------------------------------------------------------------------------
void uart_init ( void )
{
    unsigned int ra;

    PUT32(AUX_ENABLES,1);//if bit 1 is set, the mini-uart is enable

    //primary used to enable interrupts
    //DLAB is a bit in the control register
    //if DLAB=1 - bits 7:0 give access to the baud rate (R/W)
    //if DLAB=0 - if bit 1 is set - the interrupt line is asserted when the recieve fifo holds at least 1 byte (R)
    //if DLAB=0 - if bit 0 is set - the interrupt line is asserted when the trans fifo  is empty (R)
    PUT32(AUX_MU_IER_REG,0);
    PUT32(AUX_MU_CNTL_REG,0);//
    PUT32(AUX_MU_LCR_REG,3);
    PUT32(AUX_MU_MCR_REG,0);
    PUT32(AUX_MU_IER_REG,0x5); //enable rx interrupts //5=0101
    PUT32(AUX_MU_IIR_REG,0xC6);
    PUT32(AUX_MU_BAUD_REG,270);

    ra=GET32(GPFSEL1);
    ra&=~(7<<12); //gpio14
    ra|=2<<12;    //alt5
    ra&=~(7<<15); //gpio15
    ra|=2<<15;    //alt5
    PUT32(GPFSEL1,ra);

    PUT32(GPPUD,0);
    for(ra=0;ra<150;ra++) dummy(ra);
    PUT32(GPPUDCLK0,(1<<14)|(1<<15));
    for(ra=0;ra<150;ra++) dummy(ra);
    PUT32(GPPUDCLK0,0);

    PUT32(AUX_MU_CNTL_REG,3);
}
//------------------------------------------------------------------------
void uart_putc ( unsigned int c )
{
    while(1)
    {
        if(GET32(AUX_MU_LSR_REG)&0x20) break;
    }
    PUT32(AUX_MU_IO_REG,c);
}
//------------------------------------------------------------------------
void hexstrings ( unsigned int d )
{
    //unsigned int ra;
    unsigned int rb;
    unsigned int rc;

    rb=32;
    while(1)
    {
        rb-=4;
        rc=(d>>rb)&0xF;
        if(rc>9) rc+=0x37; else rc+=0x30;
        uart_putc(rc);
        if(rb==0) break;
    }
    uart_putc(0x20);
}
//------------------------------------------------------------------------
void hexstring ( unsigned int d )
{
    hexstrings(d);
    uart_putc(0x0D);
    uart_putc(0x0A);
}
volatile unsigned int rxhead;
volatile unsigned int rxtail;
#define RXBUFMASK 0xFFF
volatile unsigned char rxbuffer[RXBUFMASK+1];
//-------------------------------------------------------------------------
void c_irq_handler ( void )
{
    unsigned int rb,rc;

    //an interrupt has occurred, find out why
    while(1) //resolve all interrupts to uart
    {
        rb=GET32(AUX_MU_IIR_REG);
        if((rb&1)==1) break; //no more interrupts
        if((rb&6)==4)
        {
            //receiver holds a valid byte
            rc=GET32(AUX_MU_IO_REG); //read byte from rx fifo
            rxbuffer[rxhead]=rc&0xFF;
            rxhead=(rxhead+1)&RXBUFMASK;
        }
    }

}
//------------------------------------------------------------------------
int notmain ( unsigned int earlypc )
{
    unsigned int ra;
    unsigned int rb;
    unsigned int rc;
    unsigned int rx;

    PUT32(IRQ_DISABLE1,1<<29);

    uart_init();

    hexstring(0x12345678);
    for(ra=0;ra<20;ra++) hexstring(ra);
    hexstring(0x12345678);
    hexstring(earlypc);


    PUT32(IRQ_ENABLE1,1<<29);
    for(rx=0;rx<5;)
    {
        ra=GET32(IRQ_PEND1);
        if(ra&(1<<29))
        {
            hexstrings(ra);
            hexstrings(GET32(AUX_MU_IIR_REG));
            hexstring(GET32(AUX_MU_STAT_REG));
            hexstring(GET32(AUX_MU_IO_REG));
            hexstrings(GET32(IRQ_PEND1));
            hexstrings(GET32(AUX_MU_IIR_REG));
            hexstring(GET32(AUX_MU_STAT_REG));
            rx++;
        }
    }
    hexstring(0x12345678);
    rxhead=rxtail;
    for(rx=0;rx<5;)
    {
        while(rxtail!=rxhead)
        {
            uart_putc(rxbuffer[rxtail]);
            rxtail=(rxtail+1)&RXBUFMASK;
            rx++;
        }
        ra=GET32(IRQ_PEND1);
        if(ra&(1<<29))
        {
            //an interrupt has occurred, find out why
            while(1) //resolve all interrupts to uart
            {
                rb=GET32(AUX_MU_IIR_REG);
                if((rb&1)==1) break; //no more interrupts
                if((rb&6)==4)
                {
                    //receiver holds a valid byte
                    rc=GET32(AUX_MU_IO_REG); //read byte from rx fifo
                    rxbuffer[rxhead]=rc&0xFF;
                    rxhead=(rxhead+1)&RXBUFMASK;
                }
            }
        }
    }
    hexstring(0x12345678);
    enable_irq();
    while(1)
    {
        while(rxtail!=rxhead)
        {
            uart_putc(rxbuffer[rxtail]);
            rxtail=(rxtail+1)&RXBUFMASK;
            rx++;
        }
    }
    return(0);
}
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------


//-------------------------------------------------------------------------
//
// Copyright (c) 2012 David Welch dwelch@dwelch.com
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
//
//-------------------------------------------------------------------------