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xedaproject.toml
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xedaproject.toml
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[[design]]
name = "sparkle_vhdl_cc"
rtl.sources = [
"vhdl/util_pkg.vhdl",
"vhdl/SPARKLE_SIPO.vhdl",
"vhdl/SPARKLE_PISO.vhdl",
"vhdl/sparkle.vhdl", #
]
rtl.top = "sparkle"
rtl.clock_port = "clk"
tb.sources = [
"tb/ValidReadyTester.py",
"tb/test_sparkle.py", #
]
tb.top = "tb.test_sparkle"
tb.cocotb = true
language.vhdl.standard = "2008"
[[design]]
name = "sparkle_blang"
rtl.sources = [
"blang/bluelight/CryptoCore.bsv",
"blang/bluelight/Bus/BusDefines.bsv",
"blang/bluelight/Bus/BusFIFO.bsv",
"blang/bluelight/Bus/Bus.bsv",
"blang/bluelight/LwcApi.bsv",
"blang/bluelight/BluelightUtils.bsv",
"blang/Sparkle.bsv",
]
rtl.top = "lwc"
rtl.clock_port = "clk"
tb.sources = ["tb/sparkleTb.py"]
tb.top = "tb.sparkleTb"
tb.cocotb = true
# { module = 'tb.sparkleTb' }
[[design]]
name = "sparkle_blang_v"
rtl.sources = [
"gen_rtl/lwc.v",
]
rtl.top = "lwc"
rtl.clock_port = "clk"
tb.sources = ["tb/sparkleTb.py"]
tb.top = "tb.sparkleTb"
tb.cocotb = true
# { module = 'tb.sparkleTb' }
######################################## Flow Settings ########################################
[flows.ghdl_sim]
# wave = true
clean = true
# dockerized = true
# docker_image = "kammoh/sim"
[flows.yosys]
fpga.device = "xc7a12"
[flows.vivado_prj_synth]
fpga.part = "xc7a12tcsg325-3"
clock_period = 10.3 # ns
# out_of_context = true
synth.strategy = "Flow_PerfOptimized_high"
impl.strategy = "Performance_ExploreWithRemap"
synth.steps.SYNTH_DESIGN.ARGS.no_lc = 0
synth.steps.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY = 'full' # 'full', 'rebuilt'
[flows.vivado_synth]
fpga.part = "xc7a12tcsg325-3"
synth.strategy = "Timing"
impl.strategy = "Timing"
clock_period = 10.2