README.md

Simplified MIPS in Verilog

Implementation of a simplified version of the MIPS Pipeline in Verilog hardware description language.

The pipeline implemented in this repository has 5 stages.

1. Instruction fetch
2. Decode
3. Execution
4. Memory Access
5. WriteBack

Running

You will need Icarus Verilog to run our code. It is a Verilog simulation and synthesis tool.