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ip_upgrade.log
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ip_upgrade.log
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Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Thu Oct 20 12:39:54 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ALUdesign_1_0'
1. Summary
----------
SUCCESS in the upgrade of design_1_ALUdesign_1_0 from user.org:user:ALUdesign:7.0 (Rev. 2) to user.org:user:ALUdesign:8.0 (Rev. 2)
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Thu Oct 20 01:06:33 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ALUdesign_1_0'
1. Summary
----------
SUCCESS in the upgrade of design_1_ALUdesign_1_0 from user.org:user:ALUdesign:6.0 (Rev. 2) to user.org:user:ALUdesign:7.0 (Rev. 2)
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Oct 14 20:48:06 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ALUdesign_1_0'
1. Summary
----------
SUCCESS in the upgrade of design_1_ALUdesign_1_0 from user.org:user:ALUdesign:5.0 (Rev. 2) to user.org:user:ALUdesign:6.0 (Rev. 2)
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Mon Oct 10 22:01:28 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ALUdesign_1_0'
1. Summary
----------
SUCCESS in the upgrade of design_1_ALUdesign_1_0 from user.org:user:ALUdesign:3.0 (Rev. 3) to user.org:user:ALUdesign:5.0 (Rev. 2)
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Mon Oct 10 19:26:15 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ALUdesign_0_1'
1. Summary
----------
SUCCESS in the conversion of design_1_ALUdesign_0_1 (user.org:user:ALUdesign:9.0 (Rev. 2)) to Vivado generation flows.
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Mon Oct 3 20:52:14 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ALUdesign_0_1'
1. Summary
----------
SUCCESS in the upgrade of design_1_ALUdesign_0_1 from user.org:user:ALUdesign:8.0 (Rev. 2) to user.org:user:ALUdesign:9.0 (Rev. 2)
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Mon Oct 3 20:32:55 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ALUdesign_0_1'
1. Summary
----------
SUCCESS in the upgrade of design_1_ALUdesign_0_1 from user.org:user:ALUdesign:7.0 (Rev. 2) to user.org:user:ALUdesign:8.0 (Rev. 2)
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Mon Oct 3 20:24:55 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ALUdesign_0_1'
1. Summary
----------
SUCCESS in the upgrade of design_1_ALUdesign_0_1 from user.org:user:ALUdesign:6.0 (Rev. 2) to user.org:user:ALUdesign:7.0 (Rev. 2)
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Mon Oct 3 20:05:45 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ALUdesign_0_1'
1. Summary
----------
SUCCESS in the upgrade of design_1_ALUdesign_0_1 from user.org:user:ALUdesign:4.0 (Rev. 2) to user.org:user:ALUdesign:6.0 (Rev. 2)
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Mon Oct 3 19:26:50 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ALUdesign_0_1'
1. Summary
----------
SUCCESS in the upgrade of design_1_ALUdesign_0_1 from user.org:user:ALUdesign:3.0 (Rev. 2) to user.org:user:ALUdesign:4.0 (Rev. 2)
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Mon Oct 3 19:03:26 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ALUdesign_0_1'
1. Summary
----------
SUCCESS in the upgrade of design_1_ALUdesign_0_1 from user.org:user:ALUdesign:2.0 (Rev. 2) to user.org:user:ALUdesign:3.0 (Rev. 2)
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 30 15:14:22 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ALUdesign_0_1'
1. Summary
----------
SUCCESS in the upgrade of design_1_ALUdesign_0_1 from user.org:user:ALUdesign:1.0 (Rev. 2) to user.org:user:ALUdesign:2.0 (Rev. 2)
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 16 13:29:09 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_vio_0_0'
1. Summary
----------
SUCCESS in the conversion of design_1_vio_0_0 (xilinx.com:ip:vio:3.0 (Rev. 22)) to Vivado generation flows.
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 16 13:26:41 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_rst_clk_wiz_1_100M_0'
1. Summary
----------
SUCCESS in the conversion of design_1_rst_clk_wiz_1_100M_0 (xilinx.com:ip:proc_sys_reset:5.0 (Rev. 13)) to Vivado generation flows.
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 16 13:26:41 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_microblaze_0_0'
1. Summary
----------
SUCCESS in the conversion of design_1_microblaze_0_0 (xilinx.com:ip:microblaze:11.0 (Rev. 8)) to Vivado generation flows.
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 16 13:26:40 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_mdm_1_0'
1. Summary
----------
SUCCESS in the conversion of design_1_mdm_1_0 (xilinx.com:ip:mdm:3.2 (Rev. 22)) to Vivado generation flows.
2. Upgrade messages
-------------------
Set parameter C_M_AXIS_ID_WIDTH to value 7 (source 'default')
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 16 13:26:40 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_lmb_bram_0'
1. Summary
----------
SUCCESS in the conversion of design_1_lmb_bram_0 (xilinx.com:ip:blk_mem_gen:8.4 (Rev. 5)) to Vivado generation flows.
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 16 13:26:40 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ilmb_v10_0'
1. Summary
----------
SUCCESS in the conversion of design_1_ilmb_v10_0 (xilinx.com:ip:lmb_v10:3.0 (Rev. 11)) to Vivado generation flows.
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 16 13:26:40 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_ilmb_bram_if_cntlr_0'
1. Summary
----------
SUCCESS in the conversion of design_1_ilmb_bram_if_cntlr_0 (xilinx.com:ip:lmb_bram_if_cntlr:4.0 (Rev. 20)) to Vivado generation flows.
2. Upgrade messages
-------------------
Set parameter C_MASK1 to value 0x0000000000800000 (source 'default')
Set parameter C_MASK2 to value 0x0000000000800000 (source 'default')
Set parameter C_MASK3 to value 0x0000000000800000 (source 'default')
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 16 13:26:39 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_dlmb_v10_0'
1. Summary
----------
SUCCESS in the conversion of design_1_dlmb_v10_0 (xilinx.com:ip:lmb_v10:3.0 (Rev. 11)) to Vivado generation flows.
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 16 13:26:39 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_dlmb_bram_if_cntlr_0'
1. Summary
----------
SUCCESS in the conversion of design_1_dlmb_bram_if_cntlr_0 (xilinx.com:ip:lmb_bram_if_cntlr:4.0 (Rev. 20)) to Vivado generation flows.
2. Upgrade messages
-------------------
Set parameter C_MASK1 to value 0x0000000000800000 (source 'default')
Set parameter C_MASK2 to value 0x0000000000800000 (source 'default')
Set parameter C_MASK3 to value 0x0000000000800000 (source 'default')
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 16 13:26:39 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xcku040-ffva1156-2-e
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_clk_wiz_1_0'
1. Summary
----------
CAUTION (success, with warnings) in the conversion of design_1_clk_wiz_1_0 (xilinx.com:ip:clk_wiz:6.0 (Rev. 9)) to Vivado generation flows.
After upgrade, an IP may have parameter differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality.
2. Customization warnings
-------------------------
An attempt to modify the value of disabled parameter 'CLKOUT2_DRIVES' from 'Buffer' to 'BUFG' has been ignored for IP 'design_1_clk_wiz_1_0'
An attempt to modify the value of disabled parameter 'CLKOUT3_DRIVES' from 'Buffer' to 'BUFG' has been ignored for IP 'design_1_clk_wiz_1_0'
An attempt to modify the value of disabled parameter 'CLKOUT4_DRIVES' from 'Buffer' to 'BUFG' has been ignored for IP 'design_1_clk_wiz_1_0'
An attempt to modify the value of disabled parameter 'CLKOUT5_DRIVES' from 'Buffer' to 'BUFG' has been ignored for IP 'design_1_clk_wiz_1_0'
An attempt to modify the value of disabled parameter 'CLKOUT6_DRIVES' from 'Buffer' to 'BUFG' has been ignored for IP 'design_1_clk_wiz_1_0'
An attempt to modify the value of disabled parameter 'CLKOUT7_DRIVES' from 'Buffer' to 'BUFG' has been ignored for IP 'design_1_clk_wiz_1_0'
An attempt to modify the value of disabled parameter 'MMCM_COMPENSATION' from 'AUTO' to 'ZHOLD' has been ignored for IP 'design_1_clk_wiz_1_0'
3. Debug Commands
-----------------
The following debug information can be passed to Vivado as Tcl commands,
in order to validate or debug the output of the upgrade flow.
You may consult any warnings from within this upgrade, and alter or remove
the configuration parameter(s) which caused the warning; then execute the Tcl
commands, and use the IP Customization GUI to verify the IP configuration.
create_ip -vlnv xilinx.com:ip:clk_wiz:6.0 -user_name design_1_clk_wiz_1_0
set_property -dict "\
CONFIG.AUTO_PRIMITIVE {MMCM} \
CONFIG.AXI_DRP {false} \
CONFIG.CALC_DONE {empty} \
CONFIG.CDDCDONE_PORT {cddcdone} \
CONFIG.CDDCREQ_PORT {cddcreq} \
CONFIG.CLKFB_IN_N_PORT {clkfb_in_n} \
CONFIG.CLKFB_IN_PORT {clkfb_in} \
CONFIG.CLKFB_IN_P_PORT {clkfb_in_p} \
CONFIG.CLKFB_IN_SIGNALING {SINGLE} \
CONFIG.CLKFB_OUT_N_PORT {clkfb_out_n} \
CONFIG.CLKFB_OUT_PORT {clkfb_out} \
CONFIG.CLKFB_OUT_P_PORT {clkfb_out_p} \
CONFIG.CLKFB_STOPPED_PORT {clkfb_stopped} \
CONFIG.CLKIN1_JITTER_PS {80.0} \
CONFIG.CLKIN1_UI_JITTER {0.010} \
CONFIG.CLKIN2_JITTER_PS {100.0} \
CONFIG.CLKIN2_UI_JITTER {0.010} \
CONFIG.CLKOUT1_DRIVES {BUFG} \
CONFIG.CLKOUT1_JITTER {119.348} \
CONFIG.CLKOUT1_MATCHED_ROUTING {false} \
CONFIG.CLKOUT1_PHASE_ERROR {96.948} \
CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE {50.000} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000} \
CONFIG.CLKOUT1_REQUESTED_PHASE {0.000} \
CONFIG.CLKOUT1_SEQUENCE_NUMBER {1} \
CONFIG.CLKOUT1_USED {true} \
CONFIG.CLKOUT2_DRIVES {BUFG} \
CONFIG.CLKOUT2_JITTER {0.0} \
CONFIG.CLKOUT2_MATCHED_ROUTING {false} \
CONFIG.CLKOUT2_PHASE_ERROR {0.0} \
CONFIG.CLKOUT2_REQUESTED_DUTY_CYCLE {50.000} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {100.000} \
CONFIG.CLKOUT2_REQUESTED_PHASE {0.000} \
CONFIG.CLKOUT2_SEQUENCE_NUMBER {1} \
CONFIG.CLKOUT2_USED {false} \
CONFIG.CLKOUT3_DRIVES {BUFG} \
CONFIG.CLKOUT3_JITTER {0.0} \
CONFIG.CLKOUT3_MATCHED_ROUTING {false} \
CONFIG.CLKOUT3_PHASE_ERROR {0.0} \
CONFIG.CLKOUT3_REQUESTED_DUTY_CYCLE {50.000} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {100.000} \
CONFIG.CLKOUT3_REQUESTED_PHASE {0.000} \
CONFIG.CLKOUT3_SEQUENCE_NUMBER {1} \
CONFIG.CLKOUT3_USED {false} \
CONFIG.CLKOUT4_DRIVES {BUFG} \
CONFIG.CLKOUT4_JITTER {0.0} \
CONFIG.CLKOUT4_MATCHED_ROUTING {false} \
CONFIG.CLKOUT4_PHASE_ERROR {0.0} \
CONFIG.CLKOUT4_REQUESTED_DUTY_CYCLE {50.000} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {100.000} \
CONFIG.CLKOUT4_REQUESTED_PHASE {0.000} \
CONFIG.CLKOUT4_SEQUENCE_NUMBER {1} \
CONFIG.CLKOUT4_USED {false} \
CONFIG.CLKOUT5_DRIVES {BUFG} \
CONFIG.CLKOUT5_JITTER {0.0} \
CONFIG.CLKOUT5_MATCHED_ROUTING {false} \
CONFIG.CLKOUT5_PHASE_ERROR {0.0} \
CONFIG.CLKOUT5_REQUESTED_DUTY_CYCLE {50.000} \
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {100.000} \
CONFIG.CLKOUT5_REQUESTED_PHASE {0.000} \
CONFIG.CLKOUT5_SEQUENCE_NUMBER {1} \
CONFIG.CLKOUT5_USED {false} \
CONFIG.CLKOUT6_DRIVES {BUFG} \
CONFIG.CLKOUT6_JITTER {0.0} \
CONFIG.CLKOUT6_MATCHED_ROUTING {false} \
CONFIG.CLKOUT6_PHASE_ERROR {0.0} \
CONFIG.CLKOUT6_REQUESTED_DUTY_CYCLE {50.000} \
CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {100.000} \
CONFIG.CLKOUT6_REQUESTED_PHASE {0.000} \
CONFIG.CLKOUT6_SEQUENCE_NUMBER {1} \
CONFIG.CLKOUT6_USED {false} \
CONFIG.CLKOUT7_DRIVES {BUFG} \
CONFIG.CLKOUT7_JITTER {0.0} \
CONFIG.CLKOUT7_MATCHED_ROUTING {false} \
CONFIG.CLKOUT7_PHASE_ERROR {0.0} \
CONFIG.CLKOUT7_REQUESTED_DUTY_CYCLE {50.000} \
CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {100.000} \
CONFIG.CLKOUT7_REQUESTED_PHASE {0.000} \
CONFIG.CLKOUT7_SEQUENCE_NUMBER {1} \
CONFIG.CLKOUT7_USED {false} \
CONFIG.CLKOUTPHY_REQUESTED_FREQ {600.000} \
CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \
CONFIG.CLK_IN2_BOARD_INTERFACE {Custom} \
CONFIG.CLK_IN_SEL_PORT {clk_in_sel} \
CONFIG.CLK_OUT1_PORT {clk_out1} \
CONFIG.CLK_OUT1_USE_FINE_PS_GUI {false} \
CONFIG.CLK_OUT2_PORT {clk_out2} \
CONFIG.CLK_OUT2_USE_FINE_PS_GUI {false} \
CONFIG.CLK_OUT3_PORT {clk_out3} \
CONFIG.CLK_OUT3_USE_FINE_PS_GUI {false} \
CONFIG.CLK_OUT4_PORT {clk_out4} \
CONFIG.CLK_OUT4_USE_FINE_PS_GUI {false} \
CONFIG.CLK_OUT5_PORT {clk_out5} \
CONFIG.CLK_OUT5_USE_FINE_PS_GUI {false} \
CONFIG.CLK_OUT6_PORT {clk_out6} \
CONFIG.CLK_OUT6_USE_FINE_PS_GUI {false} \
CONFIG.CLK_OUT7_PORT {clk_out7} \
CONFIG.CLK_OUT7_USE_FINE_PS_GUI {false} \
CONFIG.CLK_VALID_PORT {CLK_VALID} \
CONFIG.CLOCK_MGR_TYPE {auto} \
CONFIG.Component_Name {design_1_clk_wiz_1_0} \
CONFIG.DADDR_PORT {daddr} \
CONFIG.DCLK_PORT {dclk} \
CONFIG.DEN_PORT {den} \
CONFIG.DIFF_CLK_IN1_BOARD_INTERFACE {Custom} \
CONFIG.DIFF_CLK_IN2_BOARD_INTERFACE {Custom} \
CONFIG.DIN_PORT {din} \
CONFIG.DOUT_PORT {dout} \
CONFIG.DRDY_PORT {drdy} \
CONFIG.DWE_PORT {dwe} \
CONFIG.ENABLE_CDDC {false} \
CONFIG.ENABLE_CLKOUTPHY {false} \
CONFIG.ENABLE_CLOCK_MONITOR {false} \
CONFIG.ENABLE_USER_CLOCK0 {false} \
CONFIG.ENABLE_USER_CLOCK1 {false} \
CONFIG.ENABLE_USER_CLOCK2 {false} \
CONFIG.ENABLE_USER_CLOCK3 {false} \
CONFIG.Enable_PLL0 {false} \
CONFIG.Enable_PLL1 {false} \
CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \
CONFIG.INPUT_CLK_STOPPED_PORT {input_clk_stopped} \
CONFIG.INPUT_MODE {frequency} \
CONFIG.INTERFACE_SELECTION {Enable_AXI} \
CONFIG.IN_FREQ_UNITS {Units_MHz} \
CONFIG.IN_JITTER_UNITS {Units_UI} \
CONFIG.JITTER_OPTIONS {UI} \
CONFIG.JITTER_SEL {No_Jitter} \
CONFIG.LOCKED_PORT {locked} \
CONFIG.MMCM_BANDWIDTH {OPTIMIZED} \
CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} \
CONFIG.MMCM_CLKFBOUT_PHASE {0.000} \
CONFIG.MMCM_CLKFBOUT_USE_FINE_PS {false} \
CONFIG.MMCM_CLKIN1_PERIOD {8.000} \
CONFIG.MMCM_CLKIN2_PERIOD {10.000} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {8.000} \
CONFIG.MMCM_CLKOUT0_DUTY_CYCLE {0.500} \
CONFIG.MMCM_CLKOUT0_PHASE {0.000} \
CONFIG.MMCM_CLKOUT0_USE_FINE_PS {false} \
CONFIG.MMCM_CLKOUT1_DIVIDE {1} \
CONFIG.MMCM_CLKOUT1_DUTY_CYCLE {0.500} \
CONFIG.MMCM_CLKOUT1_PHASE {0.000} \
CONFIG.MMCM_CLKOUT1_USE_FINE_PS {false} \
CONFIG.MMCM_CLKOUT2_DIVIDE {1} \
CONFIG.MMCM_CLKOUT2_DUTY_CYCLE {0.500} \
CONFIG.MMCM_CLKOUT2_PHASE {0.000} \
CONFIG.MMCM_CLKOUT2_USE_FINE_PS {false} \
CONFIG.MMCM_CLKOUT3_DIVIDE {1} \
CONFIG.MMCM_CLKOUT3_DUTY_CYCLE {0.500} \
CONFIG.MMCM_CLKOUT3_PHASE {0.000} \
CONFIG.MMCM_CLKOUT3_USE_FINE_PS {false} \
CONFIG.MMCM_CLKOUT4_CASCADE {false} \
CONFIG.MMCM_CLKOUT4_DIVIDE {1} \
CONFIG.MMCM_CLKOUT4_DUTY_CYCLE {0.500} \
CONFIG.MMCM_CLKOUT4_PHASE {0.000} \
CONFIG.MMCM_CLKOUT4_USE_FINE_PS {false} \
CONFIG.MMCM_CLKOUT5_DIVIDE {1} \
CONFIG.MMCM_CLKOUT5_DUTY_CYCLE {0.500} \
CONFIG.MMCM_CLKOUT5_PHASE {0.000} \
CONFIG.MMCM_CLKOUT5_USE_FINE_PS {false} \
CONFIG.MMCM_CLKOUT6_DIVIDE {1} \
CONFIG.MMCM_CLKOUT6_DUTY_CYCLE {0.500} \
CONFIG.MMCM_CLKOUT6_PHASE {0.000} \
CONFIG.MMCM_CLKOUT6_USE_FINE_PS {false} \
CONFIG.MMCM_CLOCK_HOLD {false} \
CONFIG.MMCM_COMPENSATION {ZHOLD} \
CONFIG.MMCM_DIVCLK_DIVIDE {1} \
CONFIG.MMCM_NOTES {None} \
CONFIG.MMCM_REF_JITTER1 {0.010} \
CONFIG.MMCM_REF_JITTER2 {0.010} \
CONFIG.MMCM_STARTUP_WAIT {false} \
CONFIG.NUM_OUT_CLKS {1} \
CONFIG.OPTIMIZE_CLOCKING_STRUCTURE_EN {false} \
CONFIG.OVERRIDE_MMCM {false} \
CONFIG.OVERRIDE_PLL {false} \
CONFIG.PHASESHIFT_MODE {WAVEFORM} \
CONFIG.PHASE_DUTY_CONFIG {false} \
CONFIG.PLATFORM {UNKNOWN} \
CONFIG.PLL_BANDWIDTH {OPTIMIZED} \
CONFIG.PLL_CLKFBOUT_MULT {4} \
CONFIG.PLL_CLKFBOUT_PHASE {0.000} \
CONFIG.PLL_CLKIN_PERIOD {10.000} \
CONFIG.PLL_CLKOUT0_DIVIDE {1} \
CONFIG.PLL_CLKOUT0_DUTY_CYCLE {0.500} \
CONFIG.PLL_CLKOUT0_PHASE {0.000} \
CONFIG.PLL_CLKOUT1_DIVIDE {1} \
CONFIG.PLL_CLKOUT1_DUTY_CYCLE {0.500} \
CONFIG.PLL_CLKOUT1_PHASE {0.000} \
CONFIG.PLL_CLKOUT2_DIVIDE {1} \
CONFIG.PLL_CLKOUT2_DUTY_CYCLE {0.500} \
CONFIG.PLL_CLKOUT2_PHASE {0.000} \
CONFIG.PLL_CLKOUT3_DIVIDE {1} \
CONFIG.PLL_CLKOUT3_DUTY_CYCLE {0.500} \
CONFIG.PLL_CLKOUT3_PHASE {0.000} \
CONFIG.PLL_CLKOUT4_DIVIDE {1} \
CONFIG.PLL_CLKOUT4_DUTY_CYCLE {0.500} \
CONFIG.PLL_CLKOUT4_PHASE {0.000} \
CONFIG.PLL_CLKOUT5_DIVIDE {1} \
CONFIG.PLL_CLKOUT5_DUTY_CYCLE {0.500} \
CONFIG.PLL_CLKOUT5_PHASE {0.000} \
CONFIG.PLL_CLK_FEEDBACK {CLKFBOUT} \
CONFIG.PLL_COMPENSATION {SYSTEM_SYNCHRONOUS} \
CONFIG.PLL_DIVCLK_DIVIDE {1} \
CONFIG.PLL_NOTES {None} \
CONFIG.PLL_REF_JITTER {0.010} \
CONFIG.POWER_DOWN_PORT {power_down} \
CONFIG.PRECISION {1} \
CONFIG.PRIMARY_PORT {clk_in1} \
CONFIG.PRIMITIVE {MMCM} \
CONFIG.PRIMTYPE_SEL {mmcm_adv} \
CONFIG.PRIM_IN_FREQ {125.000} \
CONFIG.PRIM_IN_JITTER {0.010} \
CONFIG.PRIM_IN_TIMEPERIOD {10.000} \
CONFIG.PRIM_SOURCE {Single_ended_clock_capable_pin} \
CONFIG.PSCLK_PORT {psclk} \
CONFIG.PSDONE_PORT {psdone} \
CONFIG.PSEN_PORT {psen} \
CONFIG.PSINCDEC_PORT {psincdec} \
CONFIG.REF_CLK_FREQ {100.0} \
CONFIG.RELATIVE_INCLK {REL_PRIMARY} \
CONFIG.RESET_BOARD_INTERFACE {Custom} \
CONFIG.RESET_PORT {reset} \
CONFIG.RESET_TYPE {ACTIVE_HIGH} \
CONFIG.SECONDARY_IN_FREQ {100.000} \
CONFIG.SECONDARY_IN_JITTER {0.010} \
CONFIG.SECONDARY_IN_TIMEPERIOD {10.000} \
CONFIG.SECONDARY_PORT {clk_in2} \
CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin} \
CONFIG.SS_MODE {CENTER_HIGH} \
CONFIG.SS_MOD_FREQ {250} \
CONFIG.SS_MOD_TIME {0.004} \
CONFIG.STATUS_PORT {STATUS} \
CONFIG.SUMMARY_STRINGS {empty} \
CONFIG.USER_CLK_FREQ0 {100.0} \
CONFIG.USER_CLK_FREQ1 {100.0} \
CONFIG.USER_CLK_FREQ2 {100.0} \
CONFIG.USER_CLK_FREQ3 {100.0} \
CONFIG.USE_BOARD_FLOW {false} \
CONFIG.USE_CLKFB_STOPPED {false} \
CONFIG.USE_CLK_VALID {false} \
CONFIG.USE_CLOCK_SEQUENCING {false} \
CONFIG.USE_DYN_PHASE_SHIFT {false} \
CONFIG.USE_DYN_RECONFIG {false} \
CONFIG.USE_FREEZE {false} \
CONFIG.USE_FREQ_SYNTH {true} \
CONFIG.USE_INCLK_STOPPED {false} \
CONFIG.USE_INCLK_SWITCHOVER {false} \
CONFIG.USE_LOCKED {true} \
CONFIG.USE_MAX_I_JITTER {false} \
CONFIG.USE_MIN_O_JITTER {false} \
CONFIG.USE_MIN_POWER {false} \
CONFIG.USE_PHASE_ALIGNMENT {true} \
CONFIG.USE_POWER_DOWN {false} \
CONFIG.USE_RESET {true} \
CONFIG.USE_SAFE_CLOCK_STARTUP {false} \
CONFIG.USE_SPREAD_SPECTRUM {false} \
CONFIG.USE_STATUS {false} \
CONFIG.reset.BOARD.ASSOCIATED_PARAM {RESET_BOARD_INTERFACE} \
CONFIG.reset.INSERT_VIP {0} \
CONFIG.reset.POLARITY {ACTIVE_HIGH} " [get_ips design_1_clk_wiz_1_0]
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 16 12:53:21 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xc7k325tffg900-2
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_rst_clk_wiz_1_100M_0'
1. Summary
----------
CAUTION (success, with warnings) in the upgrade of design_1_rst_clk_wiz_1_100M_0 (xilinx.com:ip:proc_sys_reset:5.0) from (Rev. 11) to (Rev. 13)
After upgrade, an IP may have parameter differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality.
2. Warnings
-----------
WARNING: The upgraded user parameter set contained parameters that could not be mapped on to the upgraded IP. When checking the upgrade script, note that parameter names are case sensitive.
3. Customization warnings
-------------------------
The normal upgrade process failed due to validation failures in the given configuration. Attempting partial upgrade to set as many user parameters as possible. Please check the parameters whose values were not applied.
Customization errors found on 'design_1_rst_clk_wiz_1_100M_0'. Restoring to previous valid configuration.
4. Debug Commands
-----------------
The following debug information can be passed to Vivado as Tcl commands,
in order to validate or debug the output of the upgrade flow.
You may consult any warnings from within this upgrade, and alter or remove
the configuration parameter(s) which caused the warning; then execute the Tcl
commands, and use the IP Customization GUI to verify the IP configuration.
create_ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 -user_name design_1_rst_clk_wiz_1_100M_0
set_property -dict "\
CONFIG.C_AUX_RESET_HIGH {0} \
CONFIG.C_AUX_RST_WIDTH {4} \
CONFIG.C_EXT_RESET_HIGH {1} \
CONFIG.C_EXT_RST_WIDTH {4} \
CONFIG.C_NUM_BUS_RST {1} \
CONFIG.C_NUM_INTERCONNECT_ARESETN {1} \
CONFIG.C_NUM_PERP_ARESETN {1} \
CONFIG.C_NUM_PERP_RST {1} \
CONFIG.Component_Name {design_1_rst_clk_wiz_1_100M_0} \
CONFIG.RESET_BOARD_INTERFACE {reset} \
CONFIG.USE_BOARD_FLOW {true} \
CONFIG.aux_reset.POLARITY {ACTIVE_LOW} \
CONFIG.bus_struct_reset.POLARITY {ACTIVE_HIGH} \
CONFIG.bus_struct_reset.TYPE {INTERCONNECT} \
CONFIG.clock.ASSOCIATED_BUSIF {} \
CONFIG.clock.ASSOCIATED_RESET {mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset} \
CONFIG.clock.CLK_DOMAIN {design_1_clk_wiz_1_0_clk_out1} \
CONFIG.clock.FREQ_HZ {100000000} \
CONFIG.clock.PHASE {0.0} \
CONFIG.dbg_reset.POLARITY {ACTIVE_HIGH} \
CONFIG.ext_reset.BOARD.ASSOCIATED_PARAM {RESET_BOARD_INTERFACE} \
CONFIG.ext_reset.POLARITY {ACTIVE_HIGH} \
CONFIG.interconnect_low_rst.POLARITY {ACTIVE_LOW} \
CONFIG.interconnect_low_rst.TYPE {INTERCONNECT} \
CONFIG.mb_rst.POLARITY {ACTIVE_HIGH} \
CONFIG.mb_rst.TYPE {PROCESSOR} \
CONFIG.peripheral_high_rst.POLARITY {ACTIVE_HIGH} \
CONFIG.peripheral_high_rst.TYPE {PERIPHERAL} \
CONFIG.peripheral_low_rst.POLARITY {ACTIVE_LOW} \
CONFIG.peripheral_low_rst.TYPE {PERIPHERAL} " [get_ips design_1_rst_clk_wiz_1_100M_0]
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Fri Sep 16 12:53:21 2022
| Host : carvouno3.ics.forth.gr running 64-bit AlmaLinux release 8.6 (Sky Tiger)
| Command : upgrade_ip
| Device : xc7k325tffg900-2
-----------------------------------------------------------------------------------------
Upgrade Log for IP 'design_1_microblaze_0_0'
1. Summary
----------
CAUTION (success, with warnings) in the upgrade of design_1_microblaze_0_0 from xilinx.com:ip:microblaze:10.0 (Rev. 3) to xilinx.com:ip:microblaze:11.0 (Rev. 8)
After upgrade, an IP may have parameter differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality.
2. Upgrade messages
-------------------
Set parameter C_BASE_VECTORS to value 0x0000000000000000 (source 'default')
3. Customization warnings
-------------------------
An attempt to modify the value of disabled parameter 'C_ICACHE_HIGHADDR' from '0x000000003fffffff' to '0x000000003FFFFFFF' has been ignored for IP 'design_1_microblaze_0_0'
An attempt to modify the value of disabled parameter 'C_ICACHE_ALWAYS_USED' from '1' to '0' has been ignored for IP 'design_1_microblaze_0_0'
An attempt to modify the value of disabled parameter 'C_DCACHE_HIGHADDR' from '0x000000003fffffff' to '0x000000003FFFFFFF' has been ignored for IP 'design_1_microblaze_0_0'
An attempt to modify the value of disabled parameter 'C_DCACHE_ALWAYS_USED' from '1' to '0' has been ignored for IP 'design_1_microblaze_0_0'
4. Debug Commands
-----------------
The following debug information can be passed to Vivado as Tcl commands,
in order to validate or debug the output of the upgrade flow.
You may consult any warnings from within this upgrade, and alter or remove
the configuration parameter(s) which caused the warning; then execute the Tcl
commands, and use the IP Customization GUI to verify the IP configuration.
create_ip -vlnv xilinx.com:ip:microblaze:11.0 -user_name design_1_microblaze_0_0
set_property -dict "\
CONFIG.CLK.CLK.ASSOCIATED_BUSIF {M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC} \
CONFIG.CLK.CLK.ASSOCIATED_RESET {Reset} \
CONFIG.CLK.CLK.CLK_DOMAIN {design_1_clk_wiz_1_0_clk_out1} \
CONFIG.CLK.CLK.FREQ_HZ {100000000} \
CONFIG.CLK.CLK.PHASE {0.0} \
CONFIG.C_ADDR_SIZE {32} \
CONFIG.C_ADDR_TAG_BITS {17} \
CONFIG.C_ALLOW_DCACHE_WR {1} \
CONFIG.C_ALLOW_ICACHE_WR {1} \
CONFIG.C_AREA_OPTIMIZED {0} \
CONFIG.C_ASYNC_INTERRUPT {1} \
CONFIG.C_ASYNC_WAKEUP {3} \
CONFIG.C_AVOID_PRIMITIVES {0} \
CONFIG.C_BASE_VECTORS {0x0000000000000000} \
CONFIG.C_BRANCH_TARGET_CACHE_SIZE {0} \
CONFIG.C_CACHE_BYTE_SIZE {8192} \
CONFIG.C_DATA_SIZE {32} \
CONFIG.C_DCACHE_ADDR_TAG {17} \
CONFIG.C_DCACHE_ALWAYS_USED {0} \
CONFIG.C_DCACHE_BASEADDR {0x0000000000000000} \
CONFIG.C_DCACHE_BYTE_SIZE {8192} \
CONFIG.C_DCACHE_DATA_WIDTH {0} \
CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {0} \
CONFIG.C_DCACHE_HIGHADDR {0x000000003FFFFFFF} \
CONFIG.C_DCACHE_LINE_LEN {4} \
CONFIG.C_DCACHE_USE_WRITEBACK {0} \
CONFIG.C_DCACHE_VICTIMS {0} \
CONFIG.C_DC_AXI_MON {0} \
CONFIG.C_DEBUG_COUNTER_WIDTH {32} \
CONFIG.C_DEBUG_ENABLED {1} \
CONFIG.C_DEBUG_EVENT_COUNTERS {5} \
CONFIG.C_DEBUG_EXTERNAL_TRACE {0} \
CONFIG.C_DEBUG_INTERFACE {0} \
CONFIG.C_DEBUG_LATENCY_COUNTERS {1} \
CONFIG.C_DEBUG_PROFILE_SIZE {0} \
CONFIG.C_DEBUG_TRACE_ASYNC_RESET {0} \
CONFIG.C_DEBUG_TRACE_SIZE {8192} \
CONFIG.C_DIV_ZERO_EXCEPTION {0} \
CONFIG.C_DP_AXI_MON {0} \
CONFIG.C_DYNAMIC_BUS_SIZING {0} \
CONFIG.C_D_AXI {1} \
CONFIG.C_D_LMB {1} \
CONFIG.C_D_LMB_MON {0} \
CONFIG.C_ECC_USE_CE_EXCEPTION {0} \
CONFIG.C_EDGE_IS_POSITIVE {1} \
CONFIG.C_ENABLE_DISCRETE_PORTS {0} \
CONFIG.C_ENDIANNESS {1} \
CONFIG.C_FAULT_TOLERANT {0} \
CONFIG.C_FPU_EXCEPTION {0} \
CONFIG.C_FREQ {100000000} \
CONFIG.C_FSL_EXCEPTION {0} \
CONFIG.C_FSL_LINKS {4} \
CONFIG.C_ICACHE_ALWAYS_USED {0} \
CONFIG.C_ICACHE_BASEADDR {0x0000000000000000} \
CONFIG.C_ICACHE_DATA_WIDTH {0} \
CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {0} \
CONFIG.C_ICACHE_HIGHADDR {0x000000003FFFFFFF} \
CONFIG.C_ICACHE_LINE_LEN {4} \
CONFIG.C_ICACHE_STREAMS {0} \
CONFIG.C_ICACHE_VICTIMS {0} \
CONFIG.C_IC_AXI_MON {0} \
CONFIG.C_ILL_OPCODE_EXCEPTION {0} \
CONFIG.C_IMPRECISE_EXCEPTIONS {0} \
CONFIG.C_INSTANCE {microblaze} \
CONFIG.C_INTERCONNECT {2} \
CONFIG.C_INTERRUPT_IS_EDGE {0} \
CONFIG.C_INTERRUPT_MON {0} \
CONFIG.C_IP_AXI_MON {0} \
CONFIG.C_I_AXI {0} \
CONFIG.C_I_LMB {1} \
CONFIG.C_I_LMB_MON {0} \
CONFIG.C_LOCKSTEP_SELECT {0} \
CONFIG.C_LOCKSTEP_SLAVE {0} \
CONFIG.C_M0_AXIS_DATA_WIDTH {32} \
CONFIG.C_M0_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M10_AXIS_DATA_WIDTH {32} \
CONFIG.C_M10_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M11_AXIS_DATA_WIDTH {32} \
CONFIG.C_M11_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M12_AXIS_DATA_WIDTH {32} \
CONFIG.C_M12_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M13_AXIS_DATA_WIDTH {32} \
CONFIG.C_M13_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M14_AXIS_DATA_WIDTH {32} \
CONFIG.C_M14_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M15_AXIS_DATA_WIDTH {32} \
CONFIG.C_M15_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M1_AXIS_DATA_WIDTH {32} \
CONFIG.C_M1_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M2_AXIS_DATA_WIDTH {32} \
CONFIG.C_M2_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M3_AXIS_DATA_WIDTH {32} \
CONFIG.C_M3_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M4_AXIS_DATA_WIDTH {32} \
CONFIG.C_M4_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M5_AXIS_DATA_WIDTH {32} \
CONFIG.C_M5_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M6_AXIS_DATA_WIDTH {32} \
CONFIG.C_M6_AXIS_PROTOCOL {GENERIC} \
CONFIG.C_M7_AXIS_DATA_WIDTH {32} \
CONFIG.C_M7_AXIS_PROTOCOL {GENERIC} \