Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

PCIe switch not recognized #53

Open
strongtz opened this issue Jun 12, 2023 · 0 comments
Open

PCIe switch not recognized #53

strongtz opened this issue Jun 12, 2023 · 0 comments

Comments

@strongtz
Copy link

Hi. I have a RADXA Rock 3A, and I tried connecting ASM2824 PCIE switch to it. However, the PCIe switch and the NVMe drives behind it are not getting recognized in UEFI. Directly connecting an NVMe drive to the PCIe3 port on the SBC works fine.

Here are some log which might be useful:

PCIe: Segment 2
PCIe: PciExpressBaseAddress 0x380000000
PCIe: ApbBase 0xFE280000
PCIe: DbiBase 0x3C0800000
PCIe: NumLanes 2
PCIe: LinkSpeed 3
PCIe: Reset GPIO 3 17
PCIe: Power GPIO 0 28
GPIO: SetPull     0 1C 0000      0xFDC2002C = 0x03000000
CruSetPpllRate(): Rate = 100000000 Hz
PmuCruGetPllRate(): PllNumber = 0, Rate = 200000000
CruGetPciePhyClockRate(): Index = 2, Sel = 1, Rate = 100000000 Hz
MultiPhySetModePcie(2, ...): Rate = 100000000 Hz
PCIe30: PHY init
PCIe30: PHY init complete
PCIe: Setup clocks
PCIe: Switching to RC mode
PCIe: Enabling DBI access
PCIe: Setup BARs
PCIe: Setup iATU
PCIe: Set link speed
PCIe: SetupBars: Speed change
PCIe: Assert reset
GPIO: SetPull     3 11 0000      0xFDC600A8 = 0x000C0000
PCIe: Start LTSSM
PCIe: Deassert reset
PCIe: Waiting for link up...
PCIe: PciIsLinkUp(): LTSSM_STATUS=0x00030011
PCIe: Link up (x1, 2.5 GT/s)
RootBridge: PcieRoot(0x0)
  Support/Attr: 70069 / 70069
    DmaAbove4G: Yes
NoExtConfSpace: No
     AllocAttr: 3 (CombineMemPMem Mem64Decode)
           Bus: 0 - FF Translation=0
            Io: 0 - FFFF Translation=FFFFFFFC40010000
           Mem: F0000000 - F1FFFFFF Translation=0
    MemAbove4G: 390000000 - 3BFFEFFFF Translation=0
          PMem: FFFFFFFFFFFFFFFF - 0 Translation=0
   PMemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
PCI Bus First Scanning
PciBus: Discovered PPB @ [00|00|00]

PciBus: Discovered PPB @ [00|00|00]

PciHostBridge: SubmitResources for PcieRoot(0x0)
 Mem: Granularity/SpecificFlag = 32 / 00
      Length/Alignment = 0x100000 / 0xFFFFF
PciBus: HostBridge->SubmitResources() - Success
PciHostBridge: NotifyPhase (AllocateResources)
 RootBridge: PcieRoot(0x0)
  Mem: Base/Length/Alignment = F0000000/100000/FFFFF - Success
PciBus: HostBridge->NotifyPhase(AllocateResources) - Success
Process Option ROM: BAR Base/Length = F0000000/10000
PciBus: Resource Map for Root Bridge PcieRoot(0x0)
Type =  Mem32; Base = 0xF0000000;       Length = 0x100000;      Alignment = 0xFFFFF
   Base = 0xF0000000;   Length = 0x10000;       Alignment = 0xFFFF;     Owner = PCI [00|00|00:00]; Type =  OpRom

PciBus: Resource Map for Bridge [00|00|00]
Shell> pci
   Seg  Bus  Dev  Func
   ---  ---  ---  ----
    02   00   00    00 ==> Bridge Device - PCI/PCI bridge
             Vendor 1D87 Device 3566 Prog Interface 0
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant