From 160517436e8da2549124ef638f3491ceb67ad051 Mon Sep 17 00:00:00 2001
From: "Y. Sapir" <yasapir@gmail.com>
Date: Thu, 22 Mar 2018 14:16:58 +0200
Subject: [PATCH] Fix off-by-one for maximum PCLK1 clock rate.

---
 src/rcc.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/rcc.rs b/src/rcc.rs
index b977ced5e..8e27d8d5b 100644
--- a/src/rcc.rs
+++ b/src/rcc.rs
@@ -175,7 +175,7 @@ impl CFGR {
         let ppre1 = 1 << (ppre1_bits - 0b011);
         let pclk1 = hclk / u32(ppre1);
 
-        assert!(pclk1 < 36_000_000);
+        assert!(pclk1 <= 36_000_000);
 
         let ppre2_bits = self.pclk2
             .map(|pclk2| match hclk / pclk2 {