diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h index 369396d7..2ef11ca7 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/GenXIntrinsics.h @@ -1,6 +1,6 @@ /*========================== begin_copyright_notice ============================ -Copyright (C) 2019-2021 Intel Corporation +Copyright (C) 2019-2023 Intel Corporation SPDX-License-Identifier: MIT @@ -86,6 +86,8 @@ enum class LSCCategory : uint8_t { Prefetch2D, Store, Store2D, + Load2DTyped, + Store2DTyped, Fence, LegacyAtomic, Atomic, @@ -475,6 +477,8 @@ inline LSCCategory getLSCCategory(unsigned IntrinID) { return LSCCategory::Load; case GenXIntrinsic::genx_lsc_load2d_stateless: return LSCCategory::Load2D; + case GenXIntrinsic::genx_lsc_load2d_typed_bti: + return LSCCategory::Load2DTyped; case GenXIntrinsic::genx_lsc_prefetch_bti: case GenXIntrinsic::genx_lsc_prefetch_stateless: return LSCCategory::Prefetch; @@ -490,6 +494,8 @@ inline LSCCategory getLSCCategory(unsigned IntrinID) { return LSCCategory::Store; case GenXIntrinsic::genx_lsc_store2d_stateless: return LSCCategory::Store2D; + case GenXIntrinsic::genx_lsc_store2d_typed_bti: + return LSCCategory::Store2DTyped; case GenXIntrinsic::genx_lsc_fence: return LSCCategory::Fence; case GenXIntrinsic::genx_lsc_atomic_bti: @@ -539,6 +545,17 @@ inline bool isLSCLoad2D(const Function *F) { return isLSCLoad2D(getGenXIntrinsicID(F)); } +inline bool isLSCLoad2DTyped(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Load2DTyped; +} + +inline bool isLSCLoad2DTyped(const Value *V) { + return isLSCLoad2DTyped(getGenXIntrinsicID(V)); +} + +inline bool isLSCLoad2DTyped(const Function *F) { + return isLSCLoad2DTyped(getGenXIntrinsicID(F)); +} inline bool isLSCPrefetch(unsigned IntrinID) { return getLSCCategory(IntrinID) == LSCCategory::Prefetch; @@ -588,6 +605,17 @@ inline bool isLSCStore2D(const Function *F) { return isLSCStore2D(getGenXIntrinsicID(F)); } +inline bool isLSCStore2DTyped(unsigned IntrinID) { + return getLSCCategory(IntrinID) == LSCCategory::Store2DTyped; +} + +inline bool isLSCStore2DTyped(const Value *V) { + return isLSCStore2DTyped(getGenXIntrinsicID(V)); +} + +inline bool isLSCStore2DTyped(const Function *F) { + return isLSCStore2DTyped(getGenXIntrinsicID(F)); +} inline bool isLSCFence(unsigned IntrinID) { return getLSCCategory(IntrinID) == LSCCategory::Fence; @@ -642,6 +670,8 @@ inline bool isLSC2D(unsigned IntrinID) { case LSCCategory::Load2D: case LSCCategory::Prefetch2D: case LSCCategory::Store2D: + case LSCCategory::Load2DTyped: + case LSCCategory::Store2DTyped: return true; case LSCCategory::Load: case LSCCategory::Prefetch: @@ -663,6 +693,33 @@ inline bool isLSC2D(const Function *F) { return isLSC2D(getGenXIntrinsicID(F)); } +inline bool isLSCTyped(unsigned IntrinID) { + switch (getLSCCategory(IntrinID)) { + case LSCCategory::Load2DTyped: + case LSCCategory::Store2DTyped: + return true; + case LSCCategory::Store2D: + case LSCCategory::Load: + case LSCCategory::Load2D: + case LSCCategory::Prefetch: + case LSCCategory::Prefetch2D: + case LSCCategory::Store: + case LSCCategory::Fence: + case LSCCategory::LegacyAtomic: + case LSCCategory::Atomic: + case LSCCategory::NotLSC: + return false; + } + llvm_unreachable("Unknown LSC category"); +} + +inline bool isLSCTyped(const Value *V) { + return isLSCTyped(getGenXIntrinsicID(V)); +} + +inline bool isLSCTyped(const Function *F) { + return isLSCTyped(getGenXIntrinsicID(F)); +} // Dependency from visa_igc_common_header. // Converts vector size into LSC-appropriate code. @@ -710,6 +767,8 @@ inline int getLSCVectorSize(LSCCategory Cat) { case LSCCategory::Prefetch2D: case LSCCategory::Load2D: case LSCCategory::Store2D: + case LSCCategory::Load2DTyped: + case LSCCategory::Store2DTyped: case LSCCategory::Fence: case LSCCategory::NotLSC: llvm_unreachable("no such argument"); @@ -736,6 +795,8 @@ inline int getLSCDataSize(LSCCategory Cat) { case LSCCategory::Store2D: return 3; case LSCCategory::Fence: + case LSCCategory::Load2DTyped: + case LSCCategory::Store2DTyped: case LSCCategory::NotLSC: llvm_unreachable("no such argument"); return Invalid; @@ -759,6 +820,8 @@ inline int getLSCImmOffset(LSCCategory Cat) { case LSCCategory::Prefetch2D: case LSCCategory::Load2D: case LSCCategory::Store2D: + case LSCCategory::Load2DTyped: + case LSCCategory::Store2DTyped: case LSCCategory::Fence: case LSCCategory::NotLSC: llvm_unreachable("no such argument"); @@ -786,6 +849,8 @@ inline int getLSCDataOrder(LSCCategory Cat) { case LSCCategory::Store2D: return 4; case LSCCategory::Fence: + case LSCCategory::Load2DTyped: + case LSCCategory::Store2DTyped: case LSCCategory::NotLSC: llvm_unreachable("no such argument"); return Invalid; @@ -809,6 +874,8 @@ inline int getLSCWidth(LSCCategory Cat) { case LSCCategory::Load2D: case LSCCategory::Prefetch2D: case LSCCategory::Store2D: + case LSCCategory::Load2DTyped: + case LSCCategory::Store2DTyped: return 0; case LSCCategory::NotLSC: llvm_unreachable("no such argument"); diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py index 060d5db8..2e4548a7 100644 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsic_definitions.py @@ -1,6 +1,6 @@ # ========================== begin_copyright_notice ============================ # -# Copyright (C) 2019-2022 Intel Corporation +# Copyright (C) 2019-2023 Intel Corporation # # SPDX-License-Identifier: MIT # @@ -1905,6 +1905,7 @@ ### - 4 -> .wt (writethrough) ### - 5 -> .st (streaming) ### - 6 -> .ri (read-invalidate) +### - 7 -> .cc (const-cached) ### ### Only certain combinations of CachingL1 with CachingL3 are valid on hardware. ### @@ -1928,6 +1929,32 @@ ### | .ri | .ca | read-invalidate (e.g. last-use) on L1 loads / cache in L3 | ### +---------+-----+-----------------------------------------------------------------------+ ### +### Xe2 caching combinations +### +### +---------+-----+-----------------------------------------------------------------------+ +### | L1 | L3 | Notes | +### +---------+-----+-----------------------------------------------------------------------+ +### | .df | .df | default behavior on both L1 and L3 (L3 uses MOCS settings) | +### +---------+-----+-----------------------------------------------------------------------+ +### | .uc | .uc | uncached (bypass) both L1 and L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .st | .uc | streaming L1 / bypass L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .uc | .ca | bypass L1 / cache in L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .ca | .uc | cache in L1 / bypass L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .ca | .ca | cache in both L1 and L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .st | .ca | streaming L1 / cache in L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### | .ca | .cc | cache in L1 / L3 cached as constant | +### +---------+-----+-----------------------------------------------------------------------+ +### | .uc | .cc | bypass L1 / L3 cached as constant | +### +---------+-----+-----------------------------------------------------------------------+ +### | .ri | .ri | read-invalidate both L1 and L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### ### Immediate offset. The compiler may be able to fuse this add into the message, otherwise ### additional instructions are generated to honor the semantics. ### @@ -2025,6 +2052,7 @@ ### - 4 -> .wt (writethrough) ### - 5 -> .st (streaming) ### - 6 -> .ri (read-invalidate) +### - 7 -> .cc (const-cached) ### ### Only certain combinations of CachingL1 with CachingL3 are valid on hardware. ### @@ -2048,6 +2076,16 @@ ### | .ri | .ca | read-invalidate (e.g. last-use) on L1 loads / cache in L3 | ### +---------+-----+-----------------------------------------------------------------------+ ### +### Xe2 caching combinations - same as above w/o(".ri.ca") plus next variants: +### +### +---------+-----+-----------------------------------------------------------------------+ +### | .ca | .cc | cache in L1 / L3 cached as constant | +### +---------+-----+-----------------------------------------------------------------------+ +### | .uc | .cc | bypass L1 / L3 cached as constant | +### +---------+-----+-----------------------------------------------------------------------+ +### | .ri | .ri | read-invalidate both L1 and L3 | +### +---------+-----+-----------------------------------------------------------------------+ +### ### Immediate offset. The compiler may be able to fuse this add into the message, otherwise ### additional instructions are generated to honor the semantics. ### Alternative variant for predicated variant of loads - merge destination for disabled @@ -2249,6 +2287,60 @@ "attributes" : "None" }, +### ``llvm.genx.lsc.*.quad.typed.bti...
``: LSC typed load/store/prefetch +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### +### * arg0: vXi1 predicate (overloaded) +### * arg1: i8 Caching behavior for L1, [MBC] +### * arg2: i8 Caching behavior for L3, [MBC] +### * arg3: i8 Channel mask for quad versions, [MBC] +### * arg4: i32 Surface index (BTI) +### * arg5: vxi32 U pixel address (overloaded) +### * arg6: vxi32 V pixel address +### * arg7: vxi32 R pixel address +### * arg8: vxi32 LOD pixel address +### * arg9: vXi32 or vXf32 old value of the data read (load) or data to write (store) +### +### * Return value: the value read or void +### + "lsc_load_merge_quad_typed_bti": { "result": "anyvector", + "arguments": ["anyvector", "char", "char", "char", "int", "anyvector", 2, 2, 2, 0], + "attributes": "ReadMem", + "platforms" : "Xe2+", }, + "lsc_store_quad_typed_bti": { "result": "void", + "arguments": ["anyvector", "char", "char", "char", "int", "anyvector", 1, 1, 1, "anyvector"], + "attributes": "WriteMem", + "platforms" : "Xe2+", }, + "lsc_prefetch_quad_typed_bti": { "result": "void", + "arguments": ["anyvector", "char", "char", "char", "int", "anyvector", 1, 1, 1], + "attributes": "None", + "platforms" : "Xe2+", }, + +### ``llvm.genx.lsc.*2d.typed.bti.[return type/vector type]`` : LSC typed 2d block load/store/prefetch +### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +### * arg0: i8 Caching behavior for L1 +### * arg1: i8 Caching behavior for L3 +### * arg2: i32 Surface +### * arg3: i32 BlockHeight +### * arg4: i32 BlockWidth +### * arg5: i32 XOff +### * arg6: i32 YOff +### * arg7: data to write (store only) +### +### * Return value: the value read or void +### + "lsc_load2d_typed_bti":{ "result" : "anyvector", + "arguments" : ["char", "char", "int", "int", "int", "int", "int"], + "attributes" : "ReadMem", + "platforms" : "Xe2+", }, + "lsc_store2d_typed_bti":{ "result" : "void", + "arguments" : ["char", "char", "int", "int", "int", "int", "int", "anyvector"], + "attributes" : "WriteMem", + "platforms" : "Xe2+", }, + "lsc_prefetch2d_typed_bti":{ "result" : "void", + "arguments" : ["char", "char", "int", "int", "int", "int", "int"], + "attributes" : "ReadMem", + "platforms" : "Xe2+", }, ### ``llvm.genx.lsc.atomic.*...`` : lsc_atomic instructions ### ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -2606,42 +2698,52 @@ "dword_atomic_add" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_sub" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_min" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_max" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_and" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_or" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_xor" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_imin" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_imax" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.dword.atomic2.*..`` : dword atomic with binary operator (variant with no oldval) @@ -2671,42 +2773,52 @@ "dword_atomic2_add" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_sub" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_min" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_max" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_and" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_or" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_xor" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_imin" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_imax" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.dword.atomic.*...`` : dword atomic with fmin/fmax operation @@ -2729,18 +2841,22 @@ "dword_atomic_fmin" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_fmax" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_fadd" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_fsub" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.dword.atomic2.*...`` : dword atomic with fmin/fmax operation (variant with no oldval) @@ -2762,18 +2878,22 @@ "dword_atomic2_fmin" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_fmax" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_fadd" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_fsub" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, @@ -2796,10 +2916,12 @@ "dword_atomic_inc" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic_dec" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.dword.atomic2.*..`` : dword atomic with inc/dec operation (variant with no oldval) @@ -2820,10 +2942,12 @@ "dword_atomic2_inc" : { "result" : "anyvector", "arguments" : ["anyvector","int",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_dec" : { "result" : "anyvector", "arguments" : ["anyvector","int",0], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.dword.atomic.cmpxchg..`` : vISA DWORD_ATOMIC CMPXCHG instruction @@ -2845,6 +2969,7 @@ "dword_atomic_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0,0,0], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.dword.atomic2.cmpxchg..`` : vISA DWORD_ATOMIC CMPXCHG instruction (variant with no oldval) @@ -2865,6 +2990,7 @@ "dword_atomic2_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0,0], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.dword.atomic.fcmpwr...`` : vISA DWORD_ATOMIC FCMPWR instruction @@ -2886,6 +3012,7 @@ "dword_atomic_fcmpwr" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0,0], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.dword.atomic2.fcmpwr...`` : vISA DWORD_ATOMIC FCMPWR instruction (variant with no oldval) @@ -2906,6 +3033,7 @@ "dword_atomic2_fcmpwr" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.typed.atomic.*...`` : atomic typed with binary operator @@ -2937,42 +3065,52 @@ ### "typed_atomic_add" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_sub" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_min" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_max" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_and" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_or" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_xor" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_imin" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_imax" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -2997,18 +3135,22 @@ ### "typed_atomic_fmin" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_fmax" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_fadd" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_fsub" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3032,10 +3174,12 @@ ### "typed_atomic_inc" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, "typed_atomic_dec" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3059,6 +3203,7 @@ ### "typed_atomic_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3082,6 +3227,7 @@ ### "typed_atomic_fcmpwr" : { "result" : "anyvector", "arguments" : ["anyvector","int",0,0,"anyint",2,2,2], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3132,6 +3278,7 @@ "gather_scaled" : { "result" : "anyvector", "arguments" : ["anyvector","int","short","int","int","anyint",0], "attributes" : "ReadMem", + "platforms" : "-Xe2", }, ### ``llvm.genx.gather.scaled2`` : vISA GATHER_SCALED instruction @@ -3158,6 +3305,7 @@ "gather_scaled2" : { "result" : "anyvector", "arguments" : ["int","short","int","int","anyint"], "attributes" : "ReadMem", + "platforms" : "-Xe2", }, ### ``llvm.genx.gather.masked.scaled2`` : vISA GATHER_SCALED instruction @@ -3177,6 +3325,7 @@ "gather_masked_scaled2" : { "result" : "anyvector", "arguments" : ["int","short","int","int","anyint","anyvector"], "attributes" : "ReadMem", + "platforms" : "-Xe2", }, @@ -3208,6 +3357,7 @@ "gather4_scaled" : { "result" : "anyvector", "arguments" : ["anyvector","int","short","int","int","anyint",0], "attributes" : "ReadMem" , + "platforms" : "-Xe2", }, ### ``llvm.genx.gather4.scaled2`` : vISA GATHER4_SCALED instruction @@ -3239,6 +3389,7 @@ "gather4_scaled2" : { "result" : "anyvector", "arguments" : ["int","short","int","int","anyint"], "attributes" : "ReadMem", + "platforms" : "-Xe2", }, ### ``llvm.genx.gather4.masked.scaled2`` : vISA GATHER4_SCALED instruction @@ -3257,6 +3408,7 @@ "gather4_masked_scaled2" : { "result" : "anyvector", "arguments" : ["int","short","int","int","anyint","anyvector"], "attributes" : "ReadMem", + "platforms" : "-Xe2", }, @@ -3288,6 +3440,7 @@ "gather4_typed" : { "result" : "anyvector", "arguments" : ["int","anyvector","int","anyvector",2,2,0], "attributes" : "ReadMem", + "platforms" : "-Xe2", }, ### ``llvm.genx.media.ld.`` : vISA MEDIA_LD instruction @@ -3314,6 +3467,7 @@ "media_ld" : { "result" : "anyvector", "arguments" : ["int","int","int","int","int","int"], "attributes" : "ReadMem", + "platforms" : "-Xe2", }, ### ``llvm.genx.media.st.`` : vISA MEDIA_ST instruction @@ -3339,6 +3493,7 @@ "media_st" : { "result" : "void", "arguments" : ["int","int","int","int","int","int","anyvector"], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.oword.ld*.`` : oword load instruction @@ -3358,10 +3513,12 @@ "oword_ld" : { "result" : "anyvector", "arguments" : ["int","int","int"], "attributes" : "ReadMem", + "platforms" : "-Xe2", }, "oword_ld_unaligned" : { "result" : "anyvector", "arguments" : ["int","int","int"], "attributes" : "ReadMem", + "platforms" : "-Xe2", }, ### ``llvm.genx.oword.st.`` : vISA OWORD_ST instruction @@ -3377,6 +3534,7 @@ "oword_st" : { "result" : "void", "arguments" : ["int","int","anyvector"], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.scatter.private....`` : CM internal, no VISA @@ -3419,6 +3577,7 @@ "scatter_scaled" : { "result" : "void", "arguments" : ["anyvector","int","short","int","int","anyint","anyvector"], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.scatter4.scaled...`` : vISA SCATTER4_SCALED instruction @@ -3448,6 +3607,7 @@ "scatter4_scaled" : { "result" : "void", "arguments" : ["anyvector","int","short","int","int","anyint","anyvector"], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.scatter4.typed...`` : vISA SCATTER4_TYPED instruction @@ -3476,6 +3636,7 @@ "scatter4_typed" : { "result" : "void", "arguments" : ["int","anyvector","int","anyvector",1,1,"anyvector"], "attributes" : "None", + "platforms" : "-Xe2", }, ### ``llvm.genx.transpose.ld.`` : vISA TRANSPOSE_LD instruction @@ -3496,6 +3657,7 @@ ### "transpose_ld" : { "result" : "anyvector", "arguments" : ["int","int","int","int"], + "platforms" : "-Xe2", "attributes" : "ReadMem" }, @@ -3526,42 +3688,52 @@ ### "untyped_atomic_add" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "untyped_atomic_sub" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "untyped_atomic_min" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "untyped_atomic_max" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "untyped_atomic_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "untyped_atomic_and" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "untyped_atomic_or" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "untyped_atomic_xor" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "untyped_atomic_imin" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "untyped_atomic_imax" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3583,10 +3755,12 @@ ### "untyped_atomic_inc" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "untyped_atomic_dec" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3608,6 +3782,7 @@ ### "untyped_atomic_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","int","int",0,0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3628,10 +3803,12 @@ ### "svm_block_ld" : { "result" : "anyvector", "arguments" : ["anyint"], + "platforms" : "-Xe2", "attributes" : "ReadMem" }, "svm_block_ld_unaligned" : { "result" : "anyvector", "arguments" : ["anyint"], + "platforms" : "-Xe2", "attributes" : "ReadMem" }, @@ -3647,6 +3824,7 @@ ### "svm_block_st" : { "result" : "void", "arguments" : ["anyint","anyvector"], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3669,6 +3847,7 @@ ### "svm_gather" : { "result" : "anyvector", "arguments" : ["anyvector","int","anyint",0], + "platforms" : "-Xe2", "attributes" : "ReadMem" }, @@ -3699,6 +3878,7 @@ ### "svm_gather4_scaled" : { "result" : "anyvector", "arguments" : ["anyvector","int","short","long","anyint",0], + "platforms" : "-Xe2", "attributes" : "ReadMem" }, @@ -3719,6 +3899,7 @@ ### "svm_scatter" : { "result" : "void", "arguments" : ["anyvector","int","anyint","anyvector"], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3747,6 +3928,7 @@ ### "svm_scatter4_scaled" : { "result" : "void", "arguments" : ["anyvector","int","short","long","anyint","anyvector"], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3775,42 +3957,52 @@ ### "svm_atomic_add" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "svm_atomic_sub" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "svm_atomic_min" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "svm_atomic_max" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "svm_atomic_xchg" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "svm_atomic_and" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "svm_atomic_or" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "svm_atomic_xor" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "svm_atomic_imin" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "svm_atomic_imax" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3830,10 +4022,12 @@ ### "svm_atomic_inc" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0], + "platforms" : "-Xe2", "attributes" : "None" }, "svm_atomic_dec" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3853,6 +4047,7 @@ ### "svm_atomic_cmpxchg" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3873,10 +4068,12 @@ ### "svm_atomic_fmin" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, "svm_atomic_fmax" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -3896,6 +4093,7 @@ ### "svm_atomic_fcmpwr" : { "result" : "anyvector", "arguments" : ["anyvector","anyint",0,0,0], + "platforms" : "-Xe2", "attributes" : "None" }, @@ -5234,42 +5432,52 @@ "dword_atomic2_add_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_sub_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_min_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_max_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_xchg_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_and_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_or_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_xor_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_imin_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_imax_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, ## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with fmin/fmax operation with predefined surface @@ -5293,18 +5501,22 @@ "dword_atomic2_fmin_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_fmax_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_fadd_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_fsub_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0], "attributes" : "None", + "platforms" : "-Xe2", }, ## ``llvm.genx.dword.atomic2.*.predef.surface`` : dword atomic with inc/dec operation with predefined surface @@ -5325,10 +5537,12 @@ "dword_atomic2_inc_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint"], "attributes" : "None", + "platforms" : "-Xe2", }, "dword_atomic2_dec_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint"], "attributes" : "None", + "platforms" : "-Xe2", }, ## ``llvm.genx.dword.atomic2.cmpxchg.predef.surface`` : vISA DWORD_ATOMIC CMPXCHG instruction with predefined surface @@ -5349,6 +5563,7 @@ "dword_atomic2_cmpxchg_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, ## ``llvm.genx.dword.atomic2.fcmpwr.predef.surface`` : vISA DWORD_ATOMIC FCMPWR instruction with predefined surface @@ -5369,6 +5584,7 @@ "dword_atomic2_fcmpwr_predef_surface" : { "result" : "anyvector", "arguments" : ["anyvector","anyptr","anyint",0,0], "attributes" : "None", + "platforms" : "-Xe2", }, ## ``llvm.genx.gather.masked.scaled2.predef.surface`` : vISA GATHER_SCALED instruction with predefined surface @@ -5387,6 +5603,7 @@ "gather_masked_scaled2_predef_surface" : { "result" : "anyvector", "arguments" : ["int","short","anyptr","int","anyint","anyvector"], "attributes" : "ReadMem", + "platforms" : "-Xe2", }, ## ``llvm.genx.gather4.masked.scaled2.predef.surface`` : vISA GATHER4_SCALED instruction with predefined surface @@ -5405,6 +5622,7 @@ "gather4_masked_scaled2_predef_surface" : { "result" : "anyvector", "arguments" : ["int","short","anyptr","int","anyint","anyvector"], "attributes" : "ReadMem", + "platforms" : "-Xe2", }, ## ``llvm.genx.scatter.scaled.predef.surface`` : vISA SCATTER_SCALED instruction with predefined surface @@ -5430,6 +5648,7 @@ "scatter_scaled_predef_surface" : { "result" : "void", "arguments" : ["anyvector","int","short","anyptr","int","anyint","anyvector"], "attributes" : "None", + "platforms" : "-Xe2", }, ## ``llvm.genx.scatter4.scaled.predef.surface`` : vISA SCATTER4_SCALED instruction with predefined surface @@ -5459,6 +5678,7 @@ "scatter4_scaled_predef_surface" : { "result" : "void", "arguments" : ["anyvector","int","short","anyptr","int","anyint","anyvector"], "attributes" : "None", + "platforms" : "-Xe2", }, ## ``llvm.genx.oword.ld*.predef.surface`` : oword load instruction with predefined surface @@ -5478,11 +5698,13 @@ "oword_ld_predef_surface" : { "result" : "anyvector", "arguments" : ["int", "anyptr", "int"], "attributes": "ReadMem", + "platforms" : "-Xe2", }, "oword_ld_unaligned_predef_surface" : { "result" : "anyvector", "arguments": ["int", "anyptr", "int"], "attributes" : "ReadMem", + "platforms" : "-Xe2", }, ## ``llvm.genx.oword.st.predef.surface`` : vISA OWORD_ST instruction with predefined surface @@ -5498,6 +5720,7 @@ "oword_st_predef_surface" : { "result" : "void", "arguments" : ["anyptr", "int", "anyvector"], "attributes" : "None", + "platforms" : "-Xe2", }, diff --git a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py index d51bec33..646165bf 100755 --- a/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py +++ b/GenXIntrinsics/include/llvm/GenXIntrinsics/Intrinsics.py @@ -2,7 +2,7 @@ # ========================== begin_copyright_notice ============================ # -# Copyright (C) 2019-2022 Intel Corporation +# Copyright (C) 2019-2023 Intel Corporation # # SPDX-License-Identifier: MIT # @@ -87,7 +87,9 @@ "XeHP", "XeHPG", "XeLPG", + "XeLPGPlus", "XeHPC", + "Xe2", ] def getAttributeList(Attrs): diff --git a/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp b/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp index 01fef597..14013f62 100644 --- a/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp +++ b/GenXIntrinsics/unittests/GenXIntrinsics/GenXIntrinsicsTest.cpp @@ -1,6 +1,6 @@ /*========================== begin_copyright_notice ============================ -Copyright (C) 2019-2021 Intel Corporation +Copyright (C) 2019-2023 Intel Corporation SPDX-License-Identifier: MIT @@ -27,5 +27,19 @@ TEST(GenXIntrinsics, OverloadedTypes) { true); EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_simdcf_any, 0), true); + EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_ssdp4a, 0), true); + EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_ssdp4a, 1), true); + EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_ssdp4a, 2), true); + EXPECT_EQ(GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_dpasw_nosrc0, 2), + false); + EXPECT_EQ( + GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_lsc_store_slm, 10), + true); + EXPECT_EQ( + GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_lsc_store_slm, 11), + true); + EXPECT_EQ( + GenXIntrinsic::isOverloadedArg(GenXIntrinsic::genx_lsc_store_slm, 12), + false); } } // namespace