diff --git a/.github/workflows/main-branch-sync.yml b/.github/workflows/main-branch-sync.yml new file mode 100644 index 0000000000000..c8cd4773858b7 --- /dev/null +++ b/.github/workflows/main-branch-sync.yml @@ -0,0 +1,21 @@ +name: main branch sync + +on: + push: + branches: + - 'master' + +jobs: + branch_sync: + runs-on: ubuntu-latest + steps: + - name: Checkout Code + uses: actions/checkout@v2 + with: + fetch-depth: 0 + + - name: Update branch + env: + LLVMBOT_TOKEN: ${{ secrets.LLVMBOT_MAIN_SYNC }} + run: | + git push https://$LLVMBOT_TOKEN@github.com/${{ github.repository }} HEAD:temp-test-main diff --git a/clang-tools-extra/clang-query/QueryParser.cpp b/clang-tools-extra/clang-query/QueryParser.cpp index 2f1965e77ab4b..45a0d425b7c2b 100644 --- a/clang-tools-extra/clang-query/QueryParser.cpp +++ b/clang-tools-extra/clang-query/QueryParser.cpp @@ -134,8 +134,6 @@ QueryRef QueryParser::parseSetTraversalKind( unsigned Value = LexOrCompleteWord(this, ValStr) .Case("AsIs", ast_type_traits::TK_AsIs) - .Case("IgnoreImplicitCastsAndParentheses", - ast_type_traits::TK_IgnoreImplicitCastsAndParentheses) .Case("IgnoreUnlessSpelledInSource", ast_type_traits::TK_IgnoreUnlessSpelledInSource) .Default(~0u); diff --git a/clang-tools-extra/clang-tidy/bugprone/UnusedRaiiCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/UnusedRaiiCheck.cpp index 70ce413d20ff1..5e4a0ba6d5698 100644 --- a/clang-tools-extra/clang-tidy/bugprone/UnusedRaiiCheck.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/UnusedRaiiCheck.cpp @@ -79,12 +79,11 @@ void UnusedRaiiCheck::check(const MatchFinder::MatchResult &Result) { // written type. auto Matches = match(expr(hasDescendant(typeLoc().bind("t"))), *E, *Result.Context); - const auto *TL = selectFirst("t", Matches); - assert(TL); - D << FixItHint::CreateInsertion( - Lexer::getLocForEndOfToken(TL->getEndLoc(), 0, *Result.SourceManager, - getLangOpts()), - Replacement); + if (const auto *TL = selectFirst("t", Matches)) + D << FixItHint::CreateInsertion( + Lexer::getLocForEndOfToken(TL->getEndLoc(), 0, *Result.SourceManager, + getLangOpts()), + Replacement); } } // namespace bugprone diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/MacroUsageCheck.cpp b/clang-tools-extra/clang-tidy/cppcoreguidelines/MacroUsageCheck.cpp index febc295d78e6a..eb21bb44f63d1 100644 --- a/clang-tools-extra/clang-tidy/cppcoreguidelines/MacroUsageCheck.cpp +++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/MacroUsageCheck.cpp @@ -32,8 +32,8 @@ bool isCapsOnly(StringRef Name) { class MacroUsageCallbacks : public PPCallbacks { public: MacroUsageCallbacks(MacroUsageCheck *Check, const SourceManager &SM, - StringRef RegExp, bool CapsOnly, bool IgnoreCommandLine) - : Check(Check), SM(SM), RegExp(RegExp), CheckCapsOnly(CapsOnly), + StringRef RegExpStr, bool CapsOnly, bool IgnoreCommandLine) + : Check(Check), SM(SM), RegExp(RegExpStr), CheckCapsOnly(CapsOnly), IgnoreCommandLineMacros(IgnoreCommandLine) {} void MacroDefined(const Token &MacroNameTok, const MacroDirective *MD) override { @@ -47,7 +47,7 @@ class MacroUsageCallbacks : public PPCallbacks { return; StringRef MacroName = MacroNameTok.getIdentifierInfo()->getName(); - if (!CheckCapsOnly && !llvm::Regex(RegExp).match(MacroName)) + if (!CheckCapsOnly && !RegExp.match(MacroName)) Check->warnMacro(MD, MacroName); if (CheckCapsOnly && !isCapsOnly(MacroName)) @@ -57,7 +57,7 @@ class MacroUsageCallbacks : public PPCallbacks { private: MacroUsageCheck *Check; const SourceManager &SM; - StringRef RegExp; + const llvm::Regex RegExp; bool CheckCapsOnly; bool IgnoreCommandLineMacros; }; diff --git a/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp b/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp index d7160d52750f6..ef8f54913ed92 100644 --- a/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp +++ b/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp @@ -122,14 +122,32 @@ static StringRef const StyleNames[] = { #undef NAMING_KEYS // clang-format on +IdentifierNamingCheck::NamingStyle::NamingStyle( + llvm::Optional Case, + const std::string &Prefix, const std::string &Suffix, + const std::string &IgnoredRegexpStr) + : Case(Case), Prefix(Prefix), Suffix(Suffix), + IgnoredRegexpStr(IgnoredRegexpStr) { + if (!IgnoredRegexpStr.empty()) { + IgnoredRegexp = + llvm::Regex(llvm::SmallString<128>({"^", IgnoredRegexpStr, "$"})); + if (!IgnoredRegexp.isValid()) + llvm::errs() << "Invalid IgnoredRegexp regular expression: " + << IgnoredRegexpStr; + } +} + static IdentifierNamingCheck::FileStyle getFileStyleFromOptions(const ClangTidyCheck::OptionsView &Options) { - SmallVector, 0> Styles( - SK_Count); + SmallVector, 0> Styles; + Styles.resize(SK_Count); SmallString<64> StyleString; for (unsigned I = 0; I < SK_Count; ++I) { StyleString = StyleNames[I]; size_t StyleSize = StyleString.size(); + StyleString.append("IgnoredRegexp"); + std::string IgnoredRegexpStr = Options.get(StyleString, ""); + StyleString.resize(StyleSize); StyleString.append("Prefix"); std::string Prefix(Options.get(StyleString, "")); // Fast replacement of [Pre]fix -> [Suf]fix. @@ -141,9 +159,10 @@ getFileStyleFromOptions(const ClangTidyCheck::OptionsView &Options) { auto CaseOptional = Options.getOptional(StyleString); - if (CaseOptional || !Prefix.empty() || !Postfix.empty()) + if (CaseOptional || !Prefix.empty() || !Postfix.empty() || + !IgnoredRegexpStr.empty()) Styles[I].emplace(std::move(CaseOptional), std::move(Prefix), - std::move(Postfix)); + std::move(Postfix), std::move(IgnoredRegexpStr)); } bool IgnoreMainLike = Options.get("IgnoreMainLikeFunctions", false); return {std::move(Styles), IgnoreMainLike}; @@ -175,6 +194,9 @@ void IdentifierNamingCheck::storeOptions(ClangTidyOptions::OptionMap &Opts) { continue; StyleString = StyleNames[I]; size_t StyleSize = StyleString.size(); + StyleString.append("IgnoredRegexp"); + Options.store(Opts, StyleString, Styles[I]->IgnoredRegexpStr); + StyleString.resize(StyleSize); StyleString.append("Prefix"); Options.store(Opts, StyleString, Styles[I]->Prefix); // Fast replacement of [Pre]fix -> [Suf]fix. @@ -194,7 +216,7 @@ void IdentifierNamingCheck::storeOptions(ClangTidyOptions::OptionMap &Opts) { } static bool matchesStyle(StringRef Name, - IdentifierNamingCheck::NamingStyle Style) { + const IdentifierNamingCheck::NamingStyle &Style) { static llvm::Regex Matchers[] = { llvm::Regex("^.*$"), llvm::Regex("^[a-z][a-z0-9_]*$"), @@ -589,12 +611,10 @@ static StyleKind findStyleKind( // If this method has the same name as any base method, this is likely // necessary even if it's not an override. e.g. CRTP. - auto FindHidden = [&](const CXXBaseSpecifier *S, clang::CXXBasePath &P) { - return CXXRecordDecl::FindOrdinaryMember(S, P, Decl->getDeclName()); - }; - CXXBasePaths UnusedPaths; - if (Decl->getParent()->lookupInBases(FindHidden, UnusedPaths)) - return SK_Invalid; + for (const CXXBaseSpecifier &Base : Decl->getParent()->bases()) + if (const auto *RD = Base.getType()->getAsCXXRecordDecl()) + if (RD->hasMemberName(Decl->getDeclName())) + return SK_Invalid; if (Decl->isConstexpr() && NamingStyles[SK_ConstexprMethod]) return SK_ConstexprMethod; @@ -681,6 +701,9 @@ static llvm::Optional getFailureInfo( return None; const IdentifierNamingCheck::NamingStyle &Style = *NamingStyles[SK]; + if (Style.IgnoredRegexp.isValid() && Style.IgnoredRegexp.match(Name)) + return None; + if (matchesStyle(Name, Style)) return None; diff --git a/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h b/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h index 77c03f77d91db..565eb9d114742 100644 --- a/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h +++ b/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h @@ -52,12 +52,18 @@ class IdentifierNamingCheck final : public RenamerClangTidyCheck { NamingStyle() = default; NamingStyle(llvm::Optional Case, const std::string &Prefix, - const std::string &Suffix) - : Case(Case), Prefix(Prefix), Suffix(Suffix) {} + const std::string &Suffix, const std::string &IgnoredRegexpStr); + NamingStyle(const NamingStyle &O) = delete; + NamingStyle &operator=(NamingStyle &&O) = default; + NamingStyle(NamingStyle &&O) = default; llvm::Optional Case; std::string Prefix; std::string Suffix; + // Store both compiled and non-compiled forms so original value can be + // serialized + llvm::Regex IgnoredRegexp; + std::string IgnoredRegexpStr; }; struct FileStyle { diff --git a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp index 6a25813eb7480..2bb97eca14ab2 100644 --- a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp +++ b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp @@ -10,6 +10,7 @@ #include "ASTUtils.h" #include "clang/AST/CXXInheritance.h" #include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/Basic/CharInfo.h" #include "clang/Frontend/CompilerInstance.h" #include "clang/Lex/PPCallbacks.h" #include "clang/Lex/Preprocessor.h" @@ -463,6 +464,8 @@ void RenamerClangTidyCheck::check(const MatchFinder::MatchResult &Result) { Failure.FixStatus = ShouldFixStatus::ConflictsWithKeyword; else if (Ident->hasMacroDefinition()) Failure.FixStatus = ShouldFixStatus::ConflictsWithMacroDefinition; + } else if (!isValidIdentifier(Info.Fixup)) { + Failure.FixStatus = ShouldFixStatus::FixInvalidIdentifier; } Failure.Info = std::move(Info); @@ -503,7 +506,8 @@ void RenamerClangTidyCheck::expandMacro(const Token &MacroNameTok, static std::string getDiagnosticSuffix(const RenamerClangTidyCheck::ShouldFixStatus FixStatus, const std::string &Fixup) { - if (Fixup.empty()) + if (Fixup.empty() || + FixStatus == RenamerClangTidyCheck::ShouldFixStatus::FixInvalidIdentifier) return "; cannot be fixed automatically"; if (FixStatus == RenamerClangTidyCheck::ShouldFixStatus::ShouldFix) return {}; @@ -517,7 +521,6 @@ getDiagnosticSuffix(const RenamerClangTidyCheck::ShouldFixStatus FixStatus, RenamerClangTidyCheck::ShouldFixStatus::ConflictsWithMacroDefinition) return "; cannot be fixed because '" + Fixup + "' would conflict with a macro definition"; - llvm_unreachable("invalid ShouldFixStatus"); } diff --git a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.h b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.h index aabb80133939f..fd5b32075cbe6 100644 --- a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.h +++ b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.h @@ -59,6 +59,9 @@ class RenamerClangTidyCheck : public ClangTidyCheck { /// automatically. ConflictsWithMacroDefinition, + /// The fixup results in an identifier that is not a valid c/c++ identifier. + FixInvalidIdentifier, + /// Values pass this threshold will be ignored completely /// i.e no message, no fixup. IgnoreFailureThreshold, diff --git a/clang-tools-extra/clangd/CMakeLists.txt b/clang-tools-extra/clangd/CMakeLists.txt index 3fd110e9e135d..919457f216c15 100644 --- a/clang-tools-extra/clangd/CMakeLists.txt +++ b/clang-tools-extra/clangd/CMakeLists.txt @@ -81,6 +81,7 @@ add_clang_library(clangDaemon SemanticSelection.cpp SourceCode.cpp QueryDriverDatabase.cpp + TidyProvider.cpp TUScheduler.cpp URI.cpp XRefs.cpp @@ -97,6 +98,7 @@ add_clang_library(clangDaemon index/IndexAction.cpp index/MemIndex.cpp index/Merge.cpp + index/ProjectAware.cpp index/Ref.cpp index/Relation.cpp index/Serialization.cpp @@ -139,7 +141,6 @@ clang_target_link_libraries(clangDaemon clangTooling clangToolingCore clangToolingInclusions - clangToolingRefactoring clangToolingSyntax ) @@ -168,17 +169,18 @@ if ( CLANGD_BUILD_XPC ) add_subdirectory(xpc) endif () +if (CLANGD_ENABLE_REMOTE) + include(FindGRPC) +endif() + if(CLANG_INCLUDE_TESTS) -add_subdirectory(test) -add_subdirectory(unittests) + add_subdirectory(test) + add_subdirectory(unittests) endif() # FIXME(kirillbobyrev): Document this in the LLVM docs once remote index is stable. option(CLANGD_ENABLE_REMOTE "Use gRPC library to enable remote index support for Clangd" OFF) set(GRPC_INSTALL_PATH "" CACHE PATH "Path to gRPC library manual installation.") -if (CLANGD_ENABLE_REMOTE) - include(FindGRPC) -endif() add_subdirectory(index/remote) add_subdirectory(index/dex/dexp) diff --git a/clang-tools-extra/clangd/ClangdLSPServer.cpp b/clang-tools-extra/clangd/ClangdLSPServer.cpp index e726271fe7cbe..66dee68ec474a 100644 --- a/clang-tools-extra/clangd/ClangdLSPServer.cpp +++ b/clang-tools-extra/clangd/ClangdLSPServer.cpp @@ -604,6 +604,7 @@ void ClangdLSPServer::onInitialize(const InitializeParams &Params, }}, {"declarationProvider", true}, {"definitionProvider", true}, + {"implementationProvider", true}, {"documentHighlightProvider", true}, {"documentLinkProvider", llvm::json::Object{ @@ -624,6 +625,7 @@ void ClangdLSPServer::onInitialize(const InitializeParams &Params, }}, {"typeHierarchyProvider", true}, {"memoryUsageProvider", true}, // clangd extension. + {"callHierarchyProvider", true}, }}}}; if (Opts.Encoding) Result["offsetEncoding"] = *Opts.Encoding; @@ -1223,6 +1225,26 @@ void ClangdLSPServer::onResolveTypeHierarchy( std::move(Reply)); } +void ClangdLSPServer::onPrepareCallHierarchy( + const CallHierarchyPrepareParams &Params, + Callback> Reply) { + Server->prepareCallHierarchy(Params.textDocument.uri.file(), Params.position, + std::move(Reply)); +} + +void ClangdLSPServer::onCallHierarchyIncomingCalls( + const CallHierarchyIncomingCallsParams &Params, + Callback> Reply) { + Server->incomingCalls(Params.item, std::move(Reply)); +} + +void ClangdLSPServer::onCallHierarchyOutgoingCalls( + const CallHierarchyOutgoingCallsParams &Params, + Callback> Reply) { + // FIXME: To be implemented. + Reply(std::vector{}); +} + void ClangdLSPServer::applyConfiguration( const ConfigurationSettings &Settings) { // Per-file update to the compilation database. @@ -1291,6 +1313,22 @@ void ClangdLSPServer::onReference(const ReferenceParams &Params, }); } +void ClangdLSPServer::onGoToImplementation( + const TextDocumentPositionParams &Params, + Callback> Reply) { + Server->findImplementations( + Params.textDocument.uri.file(), Params.position, + [Reply = std::move(Reply)]( + llvm::Expected> Overrides) mutable { + if (!Overrides) + return Reply(Overrides.takeError()); + std::vector Impls; + for (const LocatedSymbol &Sym : *Overrides) + Impls.push_back(Sym.PreferredDeclaration); + return Reply(std::move(Impls)); + }); +} + void ClangdLSPServer::onSymbolInfo(const TextDocumentPositionParams &Params, Callback> Reply) { Server->symbolInfo(Params.textDocument.uri.file(), Params.position, @@ -1431,6 +1469,7 @@ ClangdLSPServer::ClangdLSPServer(class Transport &Transp, MsgHandler->bind("textDocument/signatureHelp", &ClangdLSPServer::onSignatureHelp); MsgHandler->bind("textDocument/definition", &ClangdLSPServer::onGoToDefinition); MsgHandler->bind("textDocument/declaration", &ClangdLSPServer::onGoToDeclaration); + MsgHandler->bind("textDocument/implementation", &ClangdLSPServer::onGoToImplementation); MsgHandler->bind("textDocument/references", &ClangdLSPServer::onReference); MsgHandler->bind("textDocument/switchSourceHeader", &ClangdLSPServer::onSwitchSourceHeader); MsgHandler->bind("textDocument/prepareRename", &ClangdLSPServer::onPrepareRename); @@ -1450,6 +1489,9 @@ ClangdLSPServer::ClangdLSPServer(class Transport &Transp, MsgHandler->bind("textDocument/symbolInfo", &ClangdLSPServer::onSymbolInfo); MsgHandler->bind("textDocument/typeHierarchy", &ClangdLSPServer::onTypeHierarchy); MsgHandler->bind("typeHierarchy/resolve", &ClangdLSPServer::onResolveTypeHierarchy); + MsgHandler->bind("textDocument/prepareCallHierarchy", &ClangdLSPServer::onPrepareCallHierarchy); + MsgHandler->bind("callHierarchy/incomingCalls", &ClangdLSPServer::onCallHierarchyIncomingCalls); + MsgHandler->bind("callHierarchy/outgoingCalls", &ClangdLSPServer::onCallHierarchyOutgoingCalls); MsgHandler->bind("textDocument/selectionRange", &ClangdLSPServer::onSelectionRange); MsgHandler->bind("textDocument/documentLink", &ClangdLSPServer::onDocumentLink); MsgHandler->bind("textDocument/semanticTokens/full", &ClangdLSPServer::onSemanticTokens); diff --git a/clang-tools-extra/clangd/ClangdLSPServer.h b/clang-tools-extra/clangd/ClangdLSPServer.h index b9200f6a2e1b8..e65fc0e8a0064 100644 --- a/clang-tools-extra/clangd/ClangdLSPServer.h +++ b/clang-tools-extra/clangd/ClangdLSPServer.h @@ -115,6 +115,8 @@ class ClangdLSPServer : private ClangdServer::Callbacks { Callback>); void onGoToDefinition(const TextDocumentPositionParams &, Callback>); + void onGoToImplementation(const TextDocumentPositionParams &, + Callback>); void onReference(const ReferenceParams &, Callback>); void onSwitchSourceHeader(const TextDocumentIdentifier &, Callback>); @@ -133,6 +135,14 @@ class ClangdLSPServer : private ClangdServer::Callbacks { Callback>); void onResolveTypeHierarchy(const ResolveTypeHierarchyItemParams &, Callback>); + void onPrepareCallHierarchy(const CallHierarchyPrepareParams &, + Callback>); + void onCallHierarchyIncomingCalls( + const CallHierarchyIncomingCallsParams &, + Callback>); + void onCallHierarchyOutgoingCalls( + const CallHierarchyOutgoingCallsParams &, + Callback>); void onChangeConfiguration(const DidChangeConfigurationParams &); void onSymbolInfo(const TextDocumentPositionParams &, Callback>); diff --git a/clang-tools-extra/clangd/ClangdServer.cpp b/clang-tools-extra/clangd/ClangdServer.cpp index b6f9fcfd23da8..aa19a9485e171 100644 --- a/clang-tools-extra/clangd/ClangdServer.cpp +++ b/clang-tools-extra/clangd/ClangdServer.cpp @@ -114,40 +114,6 @@ struct UpdateIndexCallbacks : public ParsingCallbacks { bool TheiaSemanticHighlighting; }; -// Set of clang-tidy checks that don't work well in clangd, either due to -// crashes or false positives. -// Returns a clang-tidy filter string: -check1,-check2. -llvm::StringRef getUnusableTidyChecks() { - static const std::string FalsePositives = - llvm::join_items(", ", - // Check relies on seeing ifndef/define/endif directives, - // clangd doesn't replay those when using a preamble. - "-llvm-header-guard"); - static const std::string CrashingChecks = - llvm::join_items(", ", - // Check can choke on invalid (intermediate) c++ code, - // which is often the case when clangd tries to build an - // AST. - "-bugprone-use-after-move"); - static const std::string UnusableTidyChecks = - llvm::join_items(", ", FalsePositives, CrashingChecks); - return UnusableTidyChecks; -} - -// Returns a clang-tidy options string: check1,check2. -llvm::StringRef getDefaultTidyChecks() { - // These default checks are chosen for: - // - low false-positive rate - // - providing a lot of value - // - being reasonably efficient - static const std::string DefaultChecks = llvm::join_items( - ",", "readability-misleading-indentation", "readability-deleted-default", - "bugprone-integer-division", "bugprone-sizeof-expression", - "bugprone-suspicious-missing-comma", "bugprone-unused-raii", - "bugprone-unused-return-value", "misc-unused-using-decls", - "misc-unused-alias-decls", "misc-definitions-in-headers"); - return DefaultChecks; -} } // namespace ClangdServer::Options ClangdServer::optsForTest() { @@ -178,7 +144,7 @@ ClangdServer::ClangdServer(const GlobalCompilationDatabase &CDB, ? new FileIndex(Opts.HeavyweightDynamicSymbolIndex, Opts.CollectMainFileRefs) : nullptr), - GetClangTidyOptions(Opts.GetClangTidyOptions), + ClangTidyProvider(Opts.ClangTidyProvider), SuggestMissingIncludes(Opts.SuggestMissingIncludes), BuildRecoveryAST(Opts.BuildRecoveryAST), PreserveRecoveryASTType(Opts.PreserveRecoveryASTType), @@ -236,20 +202,6 @@ void ClangdServer::addDocument(PathRef File, llvm::StringRef Contents, llvm::StringRef Version, WantDiagnostics WantDiags, bool ForceRebuild) { ParseOptions Opts; - Opts.ClangTidyOpts = tidy::ClangTidyOptions::getDefaults(); - // FIXME: call tidy options builder on the worker thread, it can do IO. - if (GetClangTidyOptions) - Opts.ClangTidyOpts = - GetClangTidyOptions(*TFS.view(/*CWD=*/llvm::None), File); - if (Opts.ClangTidyOpts.Checks.hasValue()) { - // If the set of checks was configured, make sure clangd incompatible ones - // are disabled. - Opts.ClangTidyOpts.Checks = llvm::join_items( - ", ", *Opts.ClangTidyOpts.Checks, getUnusableTidyChecks()); - } else { - // Otherwise provide a nice set of defaults. - Opts.ClangTidyOpts.Checks = getDefaultTidyChecks().str(); - } Opts.SuggestMissingIncludes = SuggestMissingIncludes; // Compile command is set asynchronously during update, as it can be slow. @@ -260,6 +212,7 @@ void ClangdServer::addDocument(PathRef File, llvm::StringRef Contents, Inputs.ForceRebuild = ForceRebuild; Inputs.Opts = std::move(Opts); Inputs.Index = Index; + Inputs.ClangTidyProvider = ClangTidyProvider; Inputs.Opts.BuildRecoveryAST = BuildRecoveryAST; Inputs.Opts.PreserveRecoveryASTType = PreserveRecoveryASTType; bool NewFile = WorkScheduler.update(File, Inputs, WantDiags); @@ -674,8 +627,31 @@ void ClangdServer::typeHierarchy(PathRef File, Position Pos, int Resolve, void ClangdServer::resolveTypeHierarchy( TypeHierarchyItem Item, int Resolve, TypeHierarchyDirection Direction, Callback> CB) { - clangd::resolveTypeHierarchy(Item, Resolve, Direction, Index); - CB(Item); + WorkScheduler.run( + "Resolve Type Hierarchy", "", [=, CB = std::move(CB)]() mutable { + clangd::resolveTypeHierarchy(Item, Resolve, Direction, Index); + CB(Item); + }); +} + +void ClangdServer::prepareCallHierarchy( + PathRef File, Position Pos, Callback> CB) { + auto Action = [File = File.str(), Pos, + CB = std::move(CB)](Expected InpAST) mutable { + if (!InpAST) + return CB(InpAST.takeError()); + CB(clangd::prepareCallHierarchy(InpAST->AST, Pos, File)); + }; + WorkScheduler.runWithAST("Call Hierarchy", File, std::move(Action)); +} + +void ClangdServer::incomingCalls( + const CallHierarchyItem &Item, + Callback> CB) { + WorkScheduler.run("Incoming Calls", "", + [CB = std::move(CB), Item, this]() mutable { + CB(clangd::incomingCalls(Item, Index)); + }); } void ClangdServer::onFileEvent(const DidChangeWatchedFilesParams &Params) { @@ -718,6 +694,18 @@ void ClangdServer::foldingRanges(llvm::StringRef File, TUScheduler::InvalidateOnUpdate); } +void ClangdServer::findImplementations( + PathRef File, Position Pos, Callback> CB) { + auto Action = [Pos, CB = std::move(CB), + this](llvm::Expected InpAST) mutable { + if (!InpAST) + return CB(InpAST.takeError()); + CB(clangd::findImplementations(InpAST->AST, Pos, Index)); + }; + + WorkScheduler.runWithAST("Implementations", File, std::move(Action)); +} + void ClangdServer::findReferences(PathRef File, Position Pos, uint32_t Limit, Callback CB) { auto Action = [Pos, Limit, CB = std::move(CB), diff --git a/clang-tools-extra/clangd/ClangdServer.h b/clang-tools-extra/clangd/ClangdServer.h index 0056f5072cca3..35ba4686cc9a5 100644 --- a/clang-tools-extra/clangd/ClangdServer.h +++ b/clang-tools-extra/clangd/ClangdServer.h @@ -41,13 +41,6 @@ namespace clang { namespace clangd { - -/// When set, used by ClangdServer to get clang-tidy options for each particular -/// file. Must be thread-safe. We use this instead of ClangTidyOptionsProvider -/// to allow reading tidy configs from the VFS used for parsing. -using ClangTidyOptionsBuilder = std::function; - /// Manages a collection of source files and derived data (ASTs, indexes), /// and provides language-aware features such as code completion. /// @@ -113,7 +106,7 @@ class ClangdServer { bool BackgroundIndex = false; /// Store refs to main-file symbols in the index. - bool CollectMainFileRefs = false; + bool CollectMainFileRefs = true; /// If set, use this index to augment code completion results. SymbolIndex *StaticIndex = nullptr; @@ -121,12 +114,9 @@ class ClangdServer { /// If set, queried to obtain the configuration to handle each request. config::Provider *ConfigProvider = nullptr; - /// If set, enable clang-tidy in clangd and use to it get clang-tidy - /// configurations for a particular file. - /// Clangd supports only a small subset of ClangTidyOptions, these options - /// (Checks, CheckOptions) are about which clang-tidy checks will be - /// enabled. - ClangTidyOptionsBuilder GetClangTidyOptions; + /// The Options provider to use when running clang-tidy. If null, clang-tidy + /// checks will be disabled. + TidyProviderRef ClangTidyProvider; /// If true, force -frecovery-ast flag. /// If false, respect the value in clang. @@ -242,6 +232,14 @@ class ClangdServer { TypeHierarchyDirection Direction, Callback> CB); + /// Get information about call hierarchy for a given position. + void prepareCallHierarchy(PathRef File, Position Pos, + Callback> CB); + + /// Resolve incoming calls for a given call hierarchy item. + void incomingCalls(const CallHierarchyItem &Item, + Callback>); + /// Retrieve the top symbols from the workspace matching a query. void workspaceSymbols(StringRef Query, int Limit, Callback> CB); @@ -253,6 +251,10 @@ class ClangdServer { /// Retrieve ranges that can be used to fold code within the specified file. void foldingRanges(StringRef File, Callback> CB); + /// Retrieve implementations for virtual method. + void findImplementations(PathRef File, Position Pos, + Callback> CB); + /// Retrieve locations for symbol references. void findReferences(PathRef File, Position Pos, uint32_t Limit, Callback CB); @@ -377,7 +379,7 @@ class ClangdServer { std::vector> MergedIdx; // When set, provides clang-tidy options for a specific file. - ClangTidyOptionsBuilder GetClangTidyOptions; + TidyProviderRef ClangTidyProvider; // If this is true, suggest include insertion fixes for diagnostic errors that // can be caused by missing includes (e.g. member access in incomplete type). diff --git a/clang-tools-extra/clangd/Compiler.h b/clang-tools-extra/clangd/Compiler.h index 740a9c3f6f009..c9c75625727b5 100644 --- a/clang-tools-extra/clangd/Compiler.h +++ b/clang-tools-extra/clangd/Compiler.h @@ -15,8 +15,8 @@ #ifndef LLVM_CLANG_TOOLS_EXTRA_CLANGD_COMPILER_H #define LLVM_CLANG_TOOLS_EXTRA_CLANGD_COMPILER_H -#include "../clang-tidy/ClangTidyOptions.h" #include "GlobalCompilationDatabase.h" +#include "TidyProvider.h" #include "index/Index.h" #include "support/ThreadsafeFS.h" #include "clang/Frontend/CompilerInstance.h" @@ -37,7 +37,6 @@ class IgnoreDiagnostics : public DiagnosticConsumer { // Options to run clang e.g. when parsing AST. struct ParseOptions { - tidy::ClangTidyOptions ClangTidyOpts; bool SuggestMissingIncludes = false; bool BuildRecoveryAST = false; bool PreserveRecoveryASTType = false; @@ -56,6 +55,7 @@ struct ParseInputs { // Used to recover from diagnostics (e.g. find missing includes for symbol). const SymbolIndex *Index = nullptr; ParseOptions Opts = ParseOptions(); + TidyProviderRef ClangTidyProvider = {}; }; /// Builds compiler invocation that could be used to build AST or preamble. diff --git a/clang-tools-extra/clangd/Config.h b/clang-tools-extra/clangd/Config.h index 087dc4fb805df..79e94ef6fe373 100644 --- a/clang-tools-extra/clangd/Config.h +++ b/clang-tools-extra/clangd/Config.h @@ -26,6 +26,8 @@ #include "support/Context.h" #include "llvm/ADT/FunctionExtras.h" +#include "llvm/ADT/Optional.h" +#include "llvm/ADT/StringMap.h" #include #include @@ -57,10 +59,22 @@ struct Config { } CompileFlags; enum class BackgroundPolicy { Build, Skip }; + /// Describes an external index configuration. + struct ExternalIndexSpec { + enum { File, Server } Kind; + /// This is one of: + /// - Address of a clangd-index-server, in the form of "ip:port". + /// - Absolute path to an index produced by clangd-indexer. + std::string Location; + /// Absolute path to source root this index is associated with, uses + /// forward-slashes. + std::string MountPoint; + }; /// Controls background-index behavior. struct { /// Whether this TU should be indexed. BackgroundPolicy Background = BackgroundPolicy::Build; + llvm::Optional External; } Index; /// Style of the codebase. @@ -70,9 +84,37 @@ struct Config { // ::). All nested namespaces are affected as well. std::vector FullyQualifiedNamespaces; } Style; + + /// Configures what clang-tidy checks to run and options to use with them. + struct { + // A comma-seperated list of globs to specify which clang-tidy checks to + // run. + std::string Checks; + llvm::StringMap CheckOptions; + } ClangTidy; }; } // namespace clangd } // namespace clang +namespace llvm { +template <> struct DenseMapInfo { + using ExternalIndexSpec = clang::clangd::Config::ExternalIndexSpec; + static inline ExternalIndexSpec getEmptyKey() { + return {ExternalIndexSpec::File, "", ""}; + } + static inline ExternalIndexSpec getTombstoneKey() { + return {ExternalIndexSpec::File, "TOMB", "STONE"}; + } + static unsigned getHashValue(const ExternalIndexSpec &Val) { + return llvm::hash_combine(Val.Kind, Val.Location, Val.MountPoint); + } + static bool isEqual(const ExternalIndexSpec &LHS, + const ExternalIndexSpec &RHS) { + return std::tie(LHS.Kind, LHS.Location, LHS.MountPoint) == + std::tie(RHS.Kind, RHS.Location, RHS.MountPoint); + } +}; +} // namespace llvm + #endif diff --git a/clang-tools-extra/clangd/ConfigCompile.cpp b/clang-tools-extra/clangd/ConfigCompile.cpp index e2823894dd11c..846c6a170b389 100644 --- a/clang-tools-extra/clangd/ConfigCompile.cpp +++ b/clang-tools-extra/clangd/ConfigCompile.cpp @@ -27,11 +27,19 @@ #include "Config.h" #include "ConfigFragment.h" #include "ConfigProvider.h" +#include "Features.inc" #include "support/Logger.h" #include "support/Trace.h" +#include "llvm/ADT/None.h" +#include "llvm/ADT/Optional.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSwitch.h" +#include "llvm/Support/Error.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/Format.h" +#include "llvm/Support/FormatVariadic.h" #include "llvm/Support/Path.h" #include "llvm/Support/Regex.h" #include "llvm/Support/SMLoc.h" @@ -102,6 +110,27 @@ struct FragmentCompiler { return Result; } + llvm::Optional makeAbsolute(Located Path, + llvm::StringLiteral Description, + llvm::sys::path::Style Style) { + if (llvm::sys::path::is_absolute(*Path)) + return *Path; + if (FragmentDirectory.empty()) { + diag(Error, + llvm::formatv( + "{0} must be an absolute path, because this fragment is not " + "associated with any directory.", + Description) + .str(), + Path.Range); + return llvm::None; + } + llvm::SmallString<256> AbsPath = llvm::StringRef(*Path); + llvm::sys::fs::make_absolute(FragmentDirectory, AbsPath); + llvm::sys::path::native(AbsPath, Style); + return AbsPath.str().str(); + } + // Helper with similar API to StringSwitch, for parsing enum values. template class EnumSwitch { FragmentCompiler &Outer; @@ -157,6 +186,7 @@ struct FragmentCompiler { compile(std::move(F.If)); compile(std::move(F.CompileFlags)); compile(std::move(F.Index)); + compile(std::move(F.ClangTidy)); } void compile(Fragment::IfBlock &&F) { @@ -242,6 +272,59 @@ struct FragmentCompiler { Out.Apply.push_back( [Val](const Params &, Config &C) { C.Index.Background = *Val; }); } + if (F.External) + compile(std::move(**F.External), F.External->Range); + } + + void compile(Fragment::IndexBlock::ExternalBlock &&External, + llvm::SMRange BlockRange) { +#ifndef CLANGD_ENABLE_REMOTE + if (External.Server) { + diag(Error, "Clangd isn't compiled with remote index support, ignoring " + "Server." External.Server->Range); + External.Server.reset(); + } +#endif + // Make sure exactly one of the Sources is set. + unsigned SourceCount = + External.File.hasValue() + External.Server.hasValue(); + if (SourceCount != 1) { + diag(Error, "Exactly one of File or Server must be set.", BlockRange); + return; + } + Config::ExternalIndexSpec Spec; + if (External.Server) { + Spec.Kind = Config::ExternalIndexSpec::Server; + Spec.Location = std::move(**External.Server); + } else if (External.File) { + Spec.Kind = Config::ExternalIndexSpec::File; + auto AbsPath = makeAbsolute(std::move(*External.File), "File", + llvm::sys::path::Style::native); + if (!AbsPath) + return; + Spec.Location = std::move(*AbsPath); + } + // Make sure MountPoint is an absolute path with forward slashes. + if (!External.MountPoint) + External.MountPoint.emplace(FragmentDirectory); + if ((**External.MountPoint).empty()) { + diag(Error, "A mountpoint is required.", BlockRange); + return; + } + auto AbsPath = makeAbsolute(std::move(*External.MountPoint), "MountPoint", + llvm::sys::path::Style::posix); + if (!AbsPath) + return; + Spec.MountPoint = std::move(*AbsPath); + Out.Apply.push_back([Spec(std::move(Spec))](const Params &P, Config &C) { + if (!P.Path.startswith(Spec.MountPoint)) + return; + C.Index.External = Spec; + // Disable background indexing for the files under the mountpoint. + // Note that this will overwrite statements in any previous fragments + // (including the current one). + C.Index.Background = Config::BackgroundPolicy::Skip; + }); } void compile(Fragment::StyleBlock &&F) { @@ -264,6 +347,50 @@ struct FragmentCompiler { } } + void appendTidyCheckSpec(std::string &CurSpec, + const Located &Arg, bool IsPositive) { + StringRef Str = *Arg; + // Don't support negating here, its handled if the item is in the Add or + // Remove list. + if (Str.startswith("-") || Str.contains(',')) { + diag(Error, "Invalid clang-tidy check name", Arg.Range); + return; + } + CurSpec += ','; + if (!IsPositive) + CurSpec += '-'; + CurSpec += Str; + } + + void compile(Fragment::ClangTidyBlock &&F) { + std::string Checks; + for (auto &CheckGlob : F.Add) + appendTidyCheckSpec(Checks, CheckGlob, true); + + for (auto &CheckGlob : F.Remove) + appendTidyCheckSpec(Checks, CheckGlob, false); + + if (!Checks.empty()) + Out.Apply.push_back( + [Checks = std::move(Checks)](const Params &, Config &C) { + C.ClangTidy.Checks.append( + Checks, C.ClangTidy.Checks.empty() ? /*skip comma*/ 1 : 0, + std::string::npos); + }); + if (!F.CheckOptions.empty()) { + std::vector> CheckOptions; + for (auto &Opt : F.CheckOptions) + CheckOptions.emplace_back(std::move(*Opt.first), + std::move(*Opt.second)); + Out.Apply.push_back( + [CheckOptions = std::move(CheckOptions)](const Params &, Config &C) { + for (auto &StringPair : CheckOptions) + C.ClangTidy.CheckOptions.insert_or_assign(StringPair.first, + StringPair.second); + }); + } + } + constexpr static llvm::SourceMgr::DiagKind Error = llvm::SourceMgr::DK_Error; constexpr static llvm::SourceMgr::DiagKind Warning = llvm::SourceMgr::DK_Warning; diff --git a/clang-tools-extra/clangd/ConfigFragment.h b/clang-tools-extra/clangd/ConfigFragment.h index 65772715095f2..0e4ce638fc72f 100644 --- a/clang-tools-extra/clangd/ConfigFragment.h +++ b/clang-tools-extra/clangd/ConfigFragment.h @@ -162,6 +162,22 @@ struct Fragment { /// This is checked for translation units only, not headers they include. /// Legal values are "Build" or "Skip". llvm::Optional> Background; + /// An external index uses data source outside of clangd itself. This is + /// usually prepared using clangd-indexer. + /// Exactly one source (File/Server) should be configured. + struct ExternalBlock { + /// Path to an index file generated by clangd-indexer. Relative paths may + /// be used, if config fragment is associated with a directory. + llvm::Optional> File; + /// Address and port number for a clangd-index-server. e.g. + /// `123.1.1.1:13337`. + llvm::Optional> Server; + /// Source root governed by this index. Default is the directory + /// associated with the config fragment. Absolute in case of user config + /// and relative otherwise. Should always use forward-slashes. + llvm::Optional> MountPoint; + }; + llvm::Optional> External; }; IndexBlock Index; @@ -174,6 +190,29 @@ struct Fragment { std::vector> FullyQualifiedNamespaces; }; StyleBlock Style; + + /// Controls how clang-tidy will run over the code base. + /// + /// The settings are merged with any settings found in .clang-tidy + /// configiration files with these ones taking precedence. + struct ClangTidyBlock { + std::vector> Add; + /// List of checks to disable. + /// Takes precedence over Add. To enable all llvm checks except include + /// order: + /// Add: llvm-* + /// Remove: llvm-include-onder + std::vector> Remove; + + /// A Key-Value pair list of options to pass to clang-tidy checks + /// These take precedence over options specified in clang-tidy configuration + /// files. Example: + /// CheckOptions: + /// readability-braces-around-statements.ShortStatementLines: 2 + std::vector, Located>> + CheckOptions; + }; + ClangTidyBlock ClangTidy; }; } // namespace config diff --git a/clang-tools-extra/clangd/ConfigProvider.cpp b/clang-tools-extra/clangd/ConfigProvider.cpp index 5a00ec5048c01..e020ec04d1d23 100644 --- a/clang-tools-extra/clangd/ConfigProvider.cpp +++ b/clang-tools-extra/clangd/ConfigProvider.cpp @@ -9,6 +9,7 @@ #include "ConfigProvider.h" #include "Config.h" #include "ConfigFragment.h" +#include "support/FileCache.h" #include "support/ThreadsafeFS.h" #include "support/Trace.h" #include "llvm/ADT/ScopeExit.h" @@ -24,89 +25,28 @@ namespace clangd { namespace config { // Threadsafe cache around reading a YAML config file from disk. -class FileConfigCache { - std::mutex Mu; - std::chrono::steady_clock::time_point ValidTime = {}; - llvm::SmallVector CachedValue; - llvm::sys::TimePoint<> MTime = {}; - unsigned Size = -1; - - // Called once we are sure we want to read the file. - // REQUIRES: Cache keys are set. Mutex must be held. - void fillCacheFromDisk(llvm::vfs::FileSystem &FS, DiagnosticCallback DC) { - CachedValue.clear(); - - auto Buf = FS.getBufferForFile(Path); - // If we failed to read (but stat succeeded), don't cache failure. - if (!Buf) { - Size = -1; - MTime = {}; - return; - } - - // If file changed between stat and open, we don't know its mtime. - // For simplicity, don't cache the value in this case (use a bad key). - if (Buf->get()->getBufferSize() != Size) { - Size = -1; - MTime = {}; - } - - // Finally parse and compile the actual fragments. - for (auto &Fragment : - Fragment::parseYAML(Buf->get()->getBuffer(), Path, DC)) { - Fragment.Source.Directory = Directory; - CachedValue.push_back(std::move(Fragment).compile(DC)); - } - } - -public: - // Must be set before the cache is used. Not a constructor param to allow - // computing ancestor-relative paths to be deferred. - std::string Path; - // Directory associated with this fragment. +class FileConfigCache : public FileCache { + mutable llvm::SmallVector CachedValue; std::string Directory; - // Retrieves up-to-date config fragments from disk. - // A cached result may be reused if the mtime and size are unchanged. - // (But several concurrent read()s can miss the cache after a single change). - // Future performance ideas: - // - allow caches to be reused based on short elapsed walltime - // - allow latency-sensitive operations to skip revalidating the cache - void read(const ThreadsafeFS &TFS, DiagnosticCallback DC, - llvm::Optional FreshTime, - std::vector &Out) { - std::lock_guard Lock(Mu); - // We're going to update the cache and return whatever's in it. - auto Return = llvm::make_scope_exit( - [&] { llvm::copy(CachedValue, std::back_inserter(Out)); }); - - // Return any sufficiently recent result without doing any further work. - if (FreshTime && ValidTime >= FreshTime) - return; - - // Ensure we bump the ValidTime at the end to allow for reuse. - auto MarkTime = llvm::make_scope_exit( - [&] { ValidTime = std::chrono::steady_clock::now(); }); - - // Stat is cheaper than opening the file, it's usually unchanged. - assert(llvm::sys::path::is_absolute(Path)); - auto FS = TFS.view(/*CWD=*/llvm::None); - auto Stat = FS->status(Path); - // If there's no file, the result is empty. Ensure we have an invalid key. - if (!Stat || !Stat->isRegularFile()) { - MTime = {}; - Size = -1; - CachedValue.clear(); - return; - } - // If the modified-time and size match, assume the content does too. - if (Size == Stat->getSize() && MTime == Stat->getLastModificationTime()) - return; - - // OK, the file has actually changed. Update cache key, compute new value. - Size = Stat->getSize(); - MTime = Stat->getLastModificationTime(); - fillCacheFromDisk(*FS, DC); +public: + FileConfigCache(llvm::StringRef Path, llvm::StringRef Directory) + : FileCache(Path), Directory(Directory) {} + + void get(const ThreadsafeFS &TFS, DiagnosticCallback DC, + std::chrono::steady_clock::time_point FreshTime, + std::vector &Out) const { + read( + TFS, FreshTime, + [&](llvm::Optional Data) { + CachedValue.clear(); + if (Data) + for (auto &Fragment : Fragment::parseYAML(*Data, path(), DC)) { + Fragment.Source.Directory = Directory; + CachedValue.push_back(std::move(Fragment).compile(DC)); + } + }, + [&]() { llvm::copy(CachedValue, std::back_inserter(Out)); }); } }; @@ -120,17 +60,15 @@ std::unique_ptr Provider::fromYAMLFile(llvm::StringRef AbsPath, std::vector getFragments(const Params &P, DiagnosticCallback DC) const override { std::vector Result; - Cache.read(FS, DC, P.FreshTime, Result); + Cache.get(FS, DC, P.FreshTime, Result); return Result; }; public: AbsFileProvider(llvm::StringRef Path, llvm::StringRef Directory, const ThreadsafeFS &FS) - : FS(FS) { + : Cache(Path, Directory), FS(FS) { assert(llvm::sys::path::is_absolute(Path)); - Cache.Path = Path.str(); - Cache.Directory = Directory.str(); } }; @@ -174,23 +112,21 @@ Provider::fromAncestorRelativeYAMLFiles(llvm::StringRef RelPath, { std::lock_guard Lock(Mu); for (llvm::StringRef Ancestor : Ancestors) { - auto R = Cache.try_emplace(Ancestor); + auto It = Cache.find(Ancestor); // Assemble the actual config file path only once. - if (R.second) { + if (It == Cache.end()) { llvm::SmallString<256> ConfigPath = Ancestor; path::append(ConfigPath, RelPath); - R.first->second.Path = ConfigPath.str().str(); - R.first->second.Directory = Ancestor.str(); + It = Cache.try_emplace(Ancestor, ConfigPath.str(), Ancestor).first; } - Caches.push_back(&R.first->second); + Caches.push_back(&It->second); } } // Finally query each individual file. // This will take a (per-file) lock for each file that actually exists. std::vector Result; - for (FileConfigCache *Cache : Caches) { - Cache->read(FS, DC, P.FreshTime, Result); - } + for (FileConfigCache *Cache : Caches) + Cache->get(FS, DC, P.FreshTime, Result); return Result; }; diff --git a/clang-tools-extra/clangd/ConfigProvider.h b/clang-tools-extra/clangd/ConfigProvider.h index 54f4b14672364..67ab833ee5519 100644 --- a/clang-tools-extra/clangd/ConfigProvider.h +++ b/clang-tools-extra/clangd/ConfigProvider.h @@ -38,8 +38,9 @@ struct Params { llvm::StringRef Path; /// Hint that stale data is OK to improve performance (e.g. avoid IO). /// FreshTime sets a bound for how old the data can be. - /// If not set, providers should validate caches against the data source. - llvm::Optional FreshTime; + /// By default, providers should validate caches against the data source. + std::chrono::steady_clock::time_point FreshTime = + std::chrono::steady_clock::time_point::max(); }; /// Used to report problems in parsing or interpreting a config. diff --git a/clang-tools-extra/clangd/ConfigYAML.cpp b/clang-tools-extra/clangd/ConfigYAML.cpp index bc7d4fdfe85bd..a3bb1eb29adb5 100644 --- a/clang-tools-extra/clangd/ConfigYAML.cpp +++ b/clang-tools-extra/clangd/ConfigYAML.cpp @@ -5,7 +5,6 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// - #include "ConfigFragment.h" #include "llvm/ADT/Optional.h" #include "llvm/ADT/SmallSet.h" @@ -40,6 +39,7 @@ class Parser { Dict.handle("CompileFlags", [&](Node &N) { parse(F.CompileFlags, N); }); Dict.handle("Index", [&](Node &N) { parse(F.Index, N); }); Dict.handle("Style", [&](Node &N) { parse(F.Style, N); }); + Dict.handle("ClangTidy", [&](Node &N) { parse(F.ClangTidy, N); }); Dict.parse(N); return !(N.failed() || HadError); } @@ -47,8 +47,10 @@ class Parser { private: void parse(Fragment::IfBlock &F, Node &N) { DictParser Dict("If", this); - Dict.unrecognized( - [&](llvm::StringRef) { F.HasUnrecognizedCondition = true; }); + Dict.unrecognized([&](Located, Node &) { + F.HasUnrecognizedCondition = true; + return true; // Emit a warning for the unrecognized key. + }); Dict.handle("PathMatch", [&](Node &N) { if (auto Values = scalarValues(N)) F.PathMatch = std::move(*Values); @@ -82,10 +84,48 @@ class Parser { Dict.parse(N); } + void parse(Fragment::ClangTidyBlock &F, Node &N) { + DictParser Dict("ClangTidy", this); + Dict.handle("Add", [&](Node &N) { + if (auto Values = scalarValues(N)) + F.Add = std::move(*Values); + }); + Dict.handle("Remove", [&](Node &N) { + if (auto Values = scalarValues(N)) + F.Remove = std::move(*Values); + }); + Dict.handle("CheckOptions", [&](Node &N) { + DictParser CheckOptDict("CheckOptions", this); + CheckOptDict.unrecognized([&](Located &&Key, Node &Val) { + if (auto Value = scalarValue(Val, *Key)) + F.CheckOptions.emplace_back(std::move(Key), std::move(*Value)); + return false; // Don't emit a warning + }); + CheckOptDict.parse(N); + }); + Dict.parse(N); + } + void parse(Fragment::IndexBlock &F, Node &N) { DictParser Dict("Index", this); Dict.handle("Background", [&](Node &N) { F.Background = scalarValue(N, "Background"); }); + Dict.handle("External", [&](Node &N) { + Fragment::IndexBlock::ExternalBlock External; + parse(External, N); + F.External.emplace(std::move(External)); + F.External->Range = N.getSourceRange(); + }); + Dict.parse(N); + } + + void parse(Fragment::IndexBlock::ExternalBlock &F, Node &N) { + DictParser Dict("External", this); + Dict.handle("File", [&](Node &N) { F.File = scalarValue(N, "File"); }); + Dict.handle("Server", + [&](Node &N) { F.Server = scalarValue(N, "Server"); }); + Dict.handle("MountPoint", + [&](Node &N) { F.MountPoint = scalarValue(N, "MountPoint"); }); Dict.parse(N); } @@ -94,7 +134,7 @@ class Parser { class DictParser { llvm::StringRef Description; std::vector>> Keys; - std::function Unknown; + std::function, Node &)> UnknownHandler; Parser *Outer; public: @@ -112,10 +152,12 @@ class Parser { Keys.emplace_back(Key, std::move(Parse)); } - // Fallback is called when a Key is not matched by any handle(). - // A warning is also automatically emitted. - void unrecognized(std::function Fallback) { - Unknown = std::move(Fallback); + // Handler is called when a Key is not matched by any handle(). + // If this is unset or the Handler returns true, a warning is emitted for + // the unknown key. + void + unrecognized(std::function, Node &)> Handler) { + UnknownHandler = std::move(Handler); } // Process a mapping node and call handlers for each key/value pair. @@ -135,6 +177,8 @@ class Parser { continue; if (!Seen.insert(**Key).second) { Outer->warning("Duplicate key " + **Key + " is ignored", *K); + if (auto *Value = KV.getValue()) + Value->skip(); continue; } auto *Value = KV.getValue(); @@ -149,9 +193,12 @@ class Parser { } } if (!Matched) { - Outer->warning("Unknown " + Description + " key " + **Key, *K); - if (Unknown) - Unknown(**Key); + bool Warn = !UnknownHandler; + if (UnknownHandler) + Warn = UnknownHandler( + Located(**Key, K->getSourceRange()), *Value); + if (Warn) + Outer->warning("Unknown " + Description + " key " + **Key, *K); } } } diff --git a/clang-tools-extra/clangd/DumpAST.cpp b/clang-tools-extra/clangd/DumpAST.cpp index 9ea17e876de7a..12698b42ef3e6 100644 --- a/clang-tools-extra/clangd/DumpAST.cpp +++ b/clang-tools-extra/clangd/DumpAST.cpp @@ -234,6 +234,14 @@ class DumpVisitor : public RecursiveASTVisitor { return UnaryOperator::getOpcodeStr(UO->getOpcode()).str(); if (const auto *CCO = dyn_cast(S)) return CCO->getConstructor()->getNameAsString(); + if (const auto *CTE = dyn_cast(S)) { + bool Const = CTE->getType()->getPointeeType().isLocalConstQualified(); + if (CTE->isImplicit()) + return Const ? "const, implicit" : "implicit"; + if (Const) + return "const"; + return ""; + } if (isa(S) || isa(S) || isa(S) || isa(S) || isa(S) || isa(S)) diff --git a/clang-tools-extra/clangd/ParsedAST.cpp b/clang-tools-extra/clangd/ParsedAST.cpp index d3c14e6f3c87e..228db29b2be3f 100644 --- a/clang-tools-extra/clangd/ParsedAST.cpp +++ b/clang-tools-extra/clangd/ParsedAST.cpp @@ -17,6 +17,7 @@ #include "IncludeFixer.h" #include "Preamble.h" #include "SourceCode.h" +#include "TidyProvider.h" #include "index/CanonicalIncludes.h" #include "index/Index.h" #include "support/Logger.h" @@ -292,13 +293,15 @@ ParsedAST::build(llvm::StringRef Filename, const ParseInputs &Inputs, llvm::Optional CTContext; { trace::Span Tracer("ClangTidyInit"); + tidy::ClangTidyOptions ClangTidyOpts = + getTidyOptionsForFile(Inputs.ClangTidyProvider, Filename); dlog("ClangTidy configuration for file {0}: {1}", Filename, - tidy::configurationAsText(Inputs.Opts.ClangTidyOpts)); + tidy::configurationAsText(ClangTidyOpts)); tidy::ClangTidyCheckFactories CTFactories; for (const auto &E : tidy::ClangTidyModuleRegistry::entries()) E.instantiate()->addCheckFactories(CTFactories); CTContext.emplace(std::make_unique( - tidy::ClangTidyGlobalOptions(), Inputs.Opts.ClangTidyOpts)); + tidy::ClangTidyGlobalOptions(), ClangTidyOpts)); CTContext->setDiagnosticsEngine(&Clang->getDiagnostics()); CTContext->setASTContext(&Clang->getASTContext()); CTContext->setCurrentFile(Filename); diff --git a/clang-tools-extra/clangd/QueryDriverDatabase.cpp b/clang-tools-extra/clangd/QueryDriverDatabase.cpp index 9d731f5563cfe..d59263e739947 100644 --- a/clang-tools-extra/clangd/QueryDriverDatabase.cpp +++ b/clang-tools-extra/clangd/QueryDriverDatabase.cpp @@ -33,6 +33,9 @@ #include "support/Logger.h" #include "support/Path.h" #include "support/Trace.h" +#include "clang/Basic/Diagnostic.h" +#include "clang/Basic/TargetInfo.h" +#include "clang/Basic/TargetOptions.h" #include "clang/Driver/Types.h" #include "clang/Tooling/CompilationDatabase.h" #include "llvm/ADT/DenseMap.h" @@ -56,55 +59,102 @@ namespace clang { namespace clangd { namespace { -std::vector parseDriverOutput(llvm::StringRef Output) { +struct DriverInfo { std::vector SystemIncludes; + std::string Target; +}; + +bool isValidTarget(llvm::StringRef Triple) { + std::shared_ptr TargetOpts(new TargetOptions); + TargetOpts->Triple = Triple.str(); + DiagnosticsEngine Diags(new DiagnosticIDs, new DiagnosticOptions, + new IgnoringDiagConsumer); + IntrusiveRefCntPtr Target = + TargetInfo::CreateTargetInfo(Diags, TargetOpts); + return bool(Target); +} + +llvm::Optional parseDriverOutput(llvm::StringRef Output) { + DriverInfo Info; const char SIS[] = "#include <...> search starts here:"; const char SIE[] = "End of search list."; + const char TS[] = "Target: "; llvm::SmallVector Lines; Output.split(Lines, '\n', /*MaxSplit=*/-1, /*KeepEmpty=*/false); - auto StartIt = llvm::find_if( - Lines, [SIS](llvm::StringRef Line) { return Line.trim() == SIS; }); - if (StartIt == Lines.end()) { + enum { + Initial, // Initial state: searching for target or includes list. + IncludesExtracting, // Includes extracting. + Done // Includes and target extraction done. + } State = Initial; + bool SeenIncludes = false; + bool SeenTarget = false; + for (auto *It = Lines.begin(); State != Done && It != Lines.end(); ++It) { + auto Line = *It; + switch (State) { + case Initial: + if (!SeenIncludes && Line.trim() == SIS) { + SeenIncludes = true; + State = IncludesExtracting; + } else if (!SeenTarget && Line.trim().startswith(TS)) { + SeenTarget = true; + llvm::StringRef TargetLine = Line.trim(); + TargetLine.consume_front(TS); + // Only detect targets that clang understands + if (!isValidTarget(TargetLine)) { + elog("System include extraction: invalid target \"{0}\", ignoring", + TargetLine); + } else { + Info.Target = TargetLine.str(); + vlog("System include extraction: target extracted: \"{0}\"", + TargetLine); + } + } + break; + case IncludesExtracting: + if (Line.trim() == SIE) { + State = SeenTarget ? Done : Initial; + } else { + Info.SystemIncludes.push_back(Line.trim().str()); + vlog("System include extraction: adding {0}", Line); + } + break; + default: + llvm_unreachable("Impossible state of the driver output parser"); + break; + } + } + if (!SeenIncludes) { elog("System include extraction: start marker not found: {0}", Output); - return {}; + return llvm::None; } - ++StartIt; - const auto EndIt = - llvm::find_if(llvm::make_range(StartIt, Lines.end()), - [SIE](llvm::StringRef Line) { return Line.trim() == SIE; }); - if (EndIt == Lines.end()) { + if (State == IncludesExtracting) { elog("System include extraction: end marker missing: {0}", Output); - return {}; + return llvm::None; } - - for (llvm::StringRef Line : llvm::make_range(StartIt, EndIt)) { - SystemIncludes.push_back(Line.trim().str()); - vlog("System include extraction: adding {0}", Line); - } - return SystemIncludes; + return std::move(Info); } -std::vector -extractSystemIncludes(PathRef Driver, llvm::StringRef Lang, - llvm::ArrayRef CommandLine, - const llvm::Regex &QueryDriverRegex) { - trace::Span Tracer("Extract system includes"); +llvm::Optional +extractSystemIncludesAndTarget(PathRef Driver, llvm::StringRef Lang, + llvm::ArrayRef CommandLine, + const llvm::Regex &QueryDriverRegex) { + trace::Span Tracer("Extract system includes and target"); SPAN_ATTACH(Tracer, "driver", Driver); SPAN_ATTACH(Tracer, "lang", Lang); if (!QueryDriverRegex.match(Driver)) { vlog("System include extraction: not allowed driver {0}", Driver); - return {}; + return llvm::None; } if (!llvm::sys::fs::exists(Driver)) { elog("System include extraction: {0} does not exist.", Driver); - return {}; + return llvm::None; } if (!llvm::sys::fs::can_execute(Driver)) { elog("System include extraction: {0} is not executable.", Driver); - return {}; + return llvm::None; } llvm::SmallString<128> StdErrPath; @@ -113,7 +163,7 @@ extractSystemIncludes(PathRef Driver, llvm::StringRef Lang, elog("System include extraction: failed to create temporary file with " "error {0}", EC.message()); - return {}; + return llvm::None; } auto CleanUp = llvm::make_scope_exit( [&StdErrPath]() { llvm::sys::fs::remove(StdErrPath); }); @@ -158,21 +208,24 @@ extractSystemIncludes(PathRef Driver, llvm::StringRef Lang, elog("System include extraction: driver execution failed with return code: " "{0}. Args: ['{1}']", llvm::to_string(RC), llvm::join(Args, "', '")); - return {}; + return llvm::None; } auto BufOrError = llvm::MemoryBuffer::getFile(StdErrPath); if (!BufOrError) { elog("System include extraction: failed to read {0} with error {1}", StdErrPath, BufOrError.getError().message()); - return {}; + return llvm::None; } - auto Includes = parseDriverOutput(BufOrError->get()->getBuffer()); - log("System include extractor: successfully executed {0}, got includes: " - "\"{1}\"", - Driver, llvm::join(Includes, ", ")); - return Includes; + llvm::Optional Info = + parseDriverOutput(BufOrError->get()->getBuffer()); + if (!Info) + return llvm::None; + log("System includes extractor: successfully executed {0}\n\tgot includes: " + "\"{1}\"\n\tgot target: \"{2}\"", + Driver, llvm::join(Info->SystemIncludes, ", "), Info->Target); + return Info; } tooling::CompileCommand & @@ -186,6 +239,19 @@ addSystemIncludes(tooling::CompileCommand &Cmd, return Cmd; } +tooling::CompileCommand &setTarget(tooling::CompileCommand &Cmd, + const std::string &Target) { + if (!Target.empty()) { + // We do not want to override existing target with extracted one. + for (llvm::StringRef Arg : Cmd.CommandLine) { + if (Arg == "-target" || Arg.startswith("--target=")) + return Cmd; + } + Cmd.CommandLine.push_back("--target=" + Target); + } + return Cmd; +} + /// Converts a glob containing only ** or * into a regex. std::string convertGlobToRegex(llvm::StringRef Glob) { std::string RegText; @@ -268,13 +334,14 @@ class QueryDriverDatabase : public GlobalCompilationDatabase { llvm::SmallString<128> Driver(Cmd->CommandLine.front()); llvm::sys::fs::make_absolute(Cmd->Directory, Driver); - std::vector SystemIncludes = - QueriedDrivers.get(/*Key=*/(Driver + ":" + Lang).str(), [&] { - return extractSystemIncludes(Driver, Lang, Cmd->CommandLine, - QueryDriverRegex); - }); - - return addSystemIncludes(*Cmd, SystemIncludes); + if (auto Info = + QueriedDrivers.get(/*Key=*/(Driver + ":" + Lang).str(), [&] { + return extractSystemIncludesAndTarget( + Driver, Lang, Cmd->CommandLine, QueryDriverRegex); + })) { + setTarget(addSystemIncludes(*Cmd, Info->SystemIncludes), Info->Target); + } + return Cmd; } llvm::Optional getProjectInfo(PathRef File) const override { @@ -283,7 +350,7 @@ class QueryDriverDatabase : public GlobalCompilationDatabase { private: // Caches includes extracted from a driver. Key is driver:lang. - Memoize>> QueriedDrivers; + Memoize>> QueriedDrivers; llvm::Regex QueryDriverRegex; std::unique_ptr Base; diff --git a/clang-tools-extra/clangd/SemanticHighlighting.cpp b/clang-tools-extra/clangd/SemanticHighlighting.cpp index a9c885c7275e9..5397d328b0869 100644 --- a/clang-tools-extra/clangd/SemanticHighlighting.cpp +++ b/clang-tools-extra/clangd/SemanticHighlighting.cpp @@ -234,6 +234,10 @@ class HighlightingsBuilder { // with line-based diffing. assert(R.start.line <= R.end.line); for (int Line = R.start.line; Line <= R.end.line; ++Line) { + // If the end of the inactive range is at the beginning + // of a line, that line is not inactive. + if (Line == R.end.line && R.end.character == 0) + continue; // Copy tokens before the inactive line for (; It != NonConflicting.end() && It->R.start.line < Line; ++It) WithInactiveLines.push_back(std::move(*It)); @@ -556,12 +560,12 @@ llvm::StringRef toSemanticTokenType(HighlightingKind Kind) { case HighlightingKind::Function: return "function"; case HighlightingKind::Method: - return "member"; + return "method"; case HighlightingKind::StaticMethod: - // FIXME: better function/member with static modifier? + // FIXME: better method with static modifier? return "function"; case HighlightingKind::Field: - return "member"; + return "property"; case HighlightingKind::Class: return "class"; case HighlightingKind::Enum: diff --git a/clang-tools-extra/clangd/TidyProvider.cpp b/clang-tools-extra/clangd/TidyProvider.cpp new file mode 100644 index 0000000000000..1fb79f3abbce3 --- /dev/null +++ b/clang-tools-extra/clangd/TidyProvider.cpp @@ -0,0 +1,237 @@ +//===--- TidyProvider.cpp - create options for running clang-tidy----------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "TidyProvider.h" +#include "Config.h" +#include "support/Logger.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/Process.h" +#include "llvm/Support/VirtualFileSystem.h" +#include + +namespace clang { +namespace clangd { + +static void mergeCheckList(llvm::Optional &Checks, + llvm::StringRef List) { + if (List.empty()) + return; + if (!Checks || Checks->empty()) { + Checks.emplace(List); + return; + } + *Checks = llvm::join_items(",", *Checks, List); +} + +static llvm::Optional +tryReadConfigFile(llvm::vfs::FileSystem *FS, llvm::StringRef Directory) { + assert(!Directory.empty()); + // We guaranteed that child directories of Directory exist, so this assert + // should hopefully never fail. + assert(FS->exists(Directory)); + + llvm::SmallString<128> ConfigFile(Directory); + llvm::sys::path::append(ConfigFile, ".clang-tidy"); + + llvm::ErrorOr FileStatus = FS->status(ConfigFile); + + if (!FileStatus || !FileStatus->isRegularFile()) + return llvm::None; + + llvm::ErrorOr> Text = + FS->getBufferForFile(ConfigFile); + if (std::error_code EC = Text.getError()) { + elog("Can't read '{0}': {1}", ConfigFile, EC.message()); + return llvm::None; + } + + // Skip empty files, e.g. files opened for writing via shell output + // redirection. + if ((*Text)->getBuffer().empty()) + return llvm::None; + llvm::ErrorOr ParsedOptions = + tidy::parseConfiguration((*Text)->getBuffer()); + if (!ParsedOptions) { + if (ParsedOptions.getError()) + elog("Error parsing clang-tidy configuration in '{0}': {1}", ConfigFile, + ParsedOptions.getError().message()); + return llvm::None; + } + return std::move(*ParsedOptions); +} + +TidyProviderRef provideEnvironment() { + static const llvm::Optional User = [] { + llvm::Optional Ret = llvm::sys::Process::GetEnv("USER"); +#ifdef _WIN32 + if (!Ret) + return llvm::sys::Process::GetEnv("USERNAME"); +#endif + return Ret; + }(); + + if (User) + return + [](tidy::ClangTidyOptions &Opts, llvm::StringRef) { Opts.User = User; }; + // FIXME: Once function_ref and unique_function operator= operators handle + // null values, this can return null. + return [](tidy::ClangTidyOptions &, llvm::StringRef) {}; +} + +TidyProviderRef provideDefaultChecks() { + // These default checks are chosen for: + // - low false-positive rate + // - providing a lot of value + // - being reasonably efficient + static const std::string DefaultChecks = llvm::join_items( + ",", "readability-misleading-indentation", "readability-deleted-default", + "bugprone-integer-division", "bugprone-sizeof-expression", + "bugprone-suspicious-missing-comma", "bugprone-unused-raii", + "bugprone-unused-return-value", "misc-unused-using-decls", + "misc-unused-alias-decls", "misc-definitions-in-headers"); + return [](tidy::ClangTidyOptions &Opts, llvm::StringRef) { + if (!Opts.Checks || Opts.Checks->empty()) + Opts.Checks = DefaultChecks; + }; +} + +TidyProvider addTidyChecks(llvm::StringRef Checks, + llvm::StringRef WarningsAsErrors) { + return [Checks = std::string(Checks), + WarningsAsErrors = std::string(WarningsAsErrors)]( + tidy::ClangTidyOptions &Opts, llvm::StringRef) { + mergeCheckList(Opts.Checks, Checks); + mergeCheckList(Opts.WarningsAsErrors, WarningsAsErrors); + }; +} + +TidyProvider disableUnusableChecks(llvm::ArrayRef ExtraBadChecks) { + constexpr llvm::StringLiteral Seperator(","); + static const std::string BadChecks = + llvm::join_items(Seperator, + // We want this list to start with a seperator to + // simplify appending in the lambda. So including an + // empty string here will force that. + "", + // ----- False Positives ----- + + // Check relies on seeing ifndef/define/endif directives, + // clangd doesn't replay those when using a preamble. + "-llvm-header-guard", + + // ----- Crashing Checks ----- + + // Check can choke on invalid (intermediate) c++ + // code, which is often the case when clangd + // tries to build an AST. + "-bugprone-use-after-move"); + + size_t Size = BadChecks.size(); + for (const std::string &Str : ExtraBadChecks) { + if (Str.empty()) + continue; + Size += Seperator.size(); + if (LLVM_LIKELY(Str.front() != '-')) + ++Size; + Size += Str.size(); + } + std::string DisableGlob; + DisableGlob.reserve(Size); + DisableGlob += BadChecks; + for (const std::string &Str : ExtraBadChecks) { + if (Str.empty()) + continue; + DisableGlob += Seperator; + if (LLVM_LIKELY(Str.front() != '-')) + DisableGlob.push_back('-'); + DisableGlob += Str; + } + + return [DisableList(std::move(DisableGlob))](tidy::ClangTidyOptions &Opts, + llvm::StringRef) { + if (Opts.Checks && !Opts.Checks->empty()) + Opts.Checks->append(DisableList); + }; +} + +TidyProviderRef provideClangdConfig() { + return [](tidy::ClangTidyOptions &Opts, llvm::StringRef) { + const auto &CurTidyConfig = Config::current().ClangTidy; + if (!CurTidyConfig.Checks.empty()) + mergeCheckList(Opts.Checks, CurTidyConfig.Checks); + + for (const auto &CheckOption : CurTidyConfig.CheckOptions) + Opts.CheckOptions.insert_or_assign(CheckOption.getKey(), + tidy::ClangTidyOptions::ClangTidyValue( + CheckOption.getValue(), 10000U)); + }; +} + +TidyProvider provideClangTidyFiles(ThreadsafeFS &TFS) { + return [&TFS](tidy::ClangTidyOptions &Opts, llvm::StringRef Filename) { + llvm::SmallVector OptionStack; + auto FS(TFS.view(llvm::None)); + llvm::SmallString<256> AbsolutePath(Filename); + + assert(llvm::sys::path::is_absolute(AbsolutePath)); + + llvm::sys::path::remove_dots(AbsolutePath, true); + llvm::StringRef Directory = llvm::sys::path::parent_path(AbsolutePath); + { + auto Status = FS->status(Directory); + + if (!Status || !Status->isDirectory()) { + elog("Error reading configuration from {0}: directory doesn't exist", + Directory); + return; + } + } + + // FIXME: Store options in a cache that validates itself against changes + // during the clangd session. + for (llvm::StringRef CurrentDirectory = Directory; + !CurrentDirectory.empty(); + CurrentDirectory = llvm::sys::path::parent_path(CurrentDirectory)) { + auto ConfigFile = tryReadConfigFile(FS.get(), CurrentDirectory); + if (!ConfigFile) + continue; + OptionStack.push_back(std::move(*ConfigFile)); + // Should we search for a parent config to merge + if (!OptionStack.back().InheritParentConfig.getValueOr(false)) + break; + } + unsigned Order = 1U; + for (auto &Option : llvm::reverse(OptionStack)) + Opts.mergeWith(Option, Order++); + }; +} + +TidyProvider combine(std::vector Providers) { + // FIXME: Once function_ref and unique_function operator= operators handle + // null values, we should filter out any Providers that are null. Right now we + // have to ensure we dont pass any providers that are null. + return [Providers(std::move(Providers))](tidy::ClangTidyOptions &Opts, + llvm::StringRef Filename) { + for (const auto &Provider : Providers) + Provider(Opts, Filename); + }; +} + +tidy::ClangTidyOptions getTidyOptionsForFile(TidyProviderRef Provider, + llvm::StringRef Filename) { + tidy::ClangTidyOptions Opts = tidy::ClangTidyOptions::getDefaults(); + Opts.Checks->clear(); + if (Provider) + Provider(Opts, Filename); + return Opts; +} +} // namespace clangd +} // namespace clang diff --git a/clang-tools-extra/clangd/TidyProvider.h b/clang-tools-extra/clangd/TidyProvider.h new file mode 100644 index 0000000000000..f3f679c3f0d53 --- /dev/null +++ b/clang-tools-extra/clangd/TidyProvider.h @@ -0,0 +1,62 @@ +//===--- TidyProvider.h - create options for running clang-tidy------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANGD_TIDYPROVIDER_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANGD_TIDYPROVIDER_H + +#include "../clang-tidy/ClangTidyOptions.h" +#include "support/ThreadsafeFS.h" +#include "llvm/ADT/FunctionExtras.h" +#include "llvm/ADT/STLExtras.h" + +namespace clang { +namespace clangd { + +/// A factory to modify a \ref tidy::ClangTidyOptions. +using TidyProvider = + llvm::unique_function; + +/// A factory to modify a \ref tidy::ClangTidyOptions that doesn't hold any +/// state. +using TidyProviderRef = llvm::function_ref; + +TidyProvider combine(std::vector Providers); + +/// Provider that just sets the defaults. +TidyProviderRef provideEnvironment(); + +/// Provider that will enable a nice set of default checks if none are +/// specified. +TidyProviderRef provideDefaultChecks(); + +/// Provider the enables a specific set of checks and warnings as errors. +TidyProvider addTidyChecks(llvm::StringRef Checks, + llvm::StringRef WarningsAsErrors = {}); + +/// Provider that will disable checks known to not work with clangd. \p +/// ExtraBadChecks specifies any other checks that should be always +/// disabled. +TidyProvider +disableUnusableChecks(llvm::ArrayRef ExtraBadChecks = {}); + +/// Provider that searches for .clang-tidy configuration files in the directory +/// tree. +TidyProvider provideClangTidyFiles(ThreadsafeFS &); + +// Provider that uses clangd configuration files. +TidyProviderRef provideClangdConfig(); + +tidy::ClangTidyOptions getTidyOptionsForFile(TidyProviderRef Provider, + llvm::StringRef Filename); + +} // namespace clangd +} // namespace clang + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANGD_TIDYPROVIDER_H diff --git a/clang-tools-extra/clangd/XRefs.cpp b/clang-tools-extra/clangd/XRefs.cpp index 0cd8695da92d5..8a85507ff14cf 100644 --- a/clang-tools-extra/clangd/XRefs.cpp +++ b/clang-tools-extra/clangd/XRefs.cpp @@ -47,6 +47,7 @@ #include "clang/Index/USRGeneration.h" #include "clang/Tooling/Syntax/Tokens.h" #include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/MapVector.h" #include "llvm/ADT/None.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/ScopeExit.h" @@ -1339,9 +1340,9 @@ llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, const LocatedSymbol &S) { return OS; } -// FIXME(nridge): Reduce duplication between this function and declToSym(). -static llvm::Optional -declToTypeHierarchyItem(ASTContext &Ctx, const NamedDecl &ND) { +template +static llvm::Optional declToHierarchyItem(const NamedDecl &ND) { + ASTContext &Ctx = ND.getASTContext(); auto &SM = Ctx.getSourceManager(); SourceLocation NameLoc = nameLocation(ND, Ctx.getSourceManager()); SourceLocation BeginLoc = SM.getSpellingLoc(SM.getFileLoc(ND.getBeginLoc())); @@ -1365,54 +1366,84 @@ declToTypeHierarchyItem(ASTContext &Ctx, const NamedDecl &ND) { // correctly. SymbolKind SK = indexSymbolKindToSymbolKind(SymInfo.Kind); - TypeHierarchyItem THI; - THI.name = printName(Ctx, ND); - THI.kind = SK; - THI.deprecated = ND.isDeprecated(); - THI.range = Range{sourceLocToPosition(SM, DeclRange->getBegin()), - sourceLocToPosition(SM, DeclRange->getEnd())}; - THI.selectionRange = Range{NameBegin, NameEnd}; - if (!THI.range.contains(THI.selectionRange)) { + HierarchyItem HI; + HI.name = printName(Ctx, ND); + HI.kind = SK; + HI.range = Range{sourceLocToPosition(SM, DeclRange->getBegin()), + sourceLocToPosition(SM, DeclRange->getEnd())}; + HI.selectionRange = Range{NameBegin, NameEnd}; + if (!HI.range.contains(HI.selectionRange)) { // 'selectionRange' must be contained in 'range', so in cases where clang // reports unrelated ranges we need to reconcile somehow. - THI.range = THI.selectionRange; + HI.range = HI.selectionRange; } - THI.uri = URIForFile::canonicalize(*FilePath, *TUPath); + HI.uri = URIForFile::canonicalize(*FilePath, *TUPath); // Compute the SymbolID and store it in the 'data' field. // This allows typeHierarchy/resolve to be used to // resolve children of items returned in a previous request // for parents. if (auto ID = getSymbolID(&ND)) - THI.data = ID.str(); + HI.data = ID.str(); + + return HI; +} + +static llvm::Optional +declToTypeHierarchyItem(const NamedDecl &ND) { + auto Result = declToHierarchyItem(ND); + if (Result) + Result->deprecated = ND.isDeprecated(); + return Result; +} - return THI; +static llvm::Optional +declToCallHierarchyItem(const NamedDecl &ND) { + auto Result = declToHierarchyItem(ND); + if (Result && ND.isDeprecated()) + Result->tags.push_back(SymbolTag::Deprecated); + return Result; } -static Optional -symbolToTypeHierarchyItem(const Symbol &S, const SymbolIndex *Index, - PathRef TUPath) { +template +static llvm::Optional symbolToHierarchyItem(const Symbol &S, + PathRef TUPath) { auto Loc = symbolToLocation(S, TUPath); if (!Loc) { - log("Type hierarchy: {0}", Loc.takeError()); + elog("Failed to convert symbol to hierarchy item: {0}", Loc.takeError()); return llvm::None; } - TypeHierarchyItem THI; - THI.name = std::string(S.Name); - THI.kind = indexSymbolKindToSymbolKind(S.SymInfo.Kind); - THI.deprecated = (S.Flags & Symbol::Deprecated); - THI.selectionRange = Loc->range; + HierarchyItem HI; + HI.name = std::string(S.Name); + HI.kind = indexSymbolKindToSymbolKind(S.SymInfo.Kind); + HI.selectionRange = Loc->range; // FIXME: Populate 'range' correctly // (https://github.com/clangd/clangd/issues/59). - THI.range = THI.selectionRange; - THI.uri = Loc->uri; + HI.range = HI.selectionRange; + HI.uri = Loc->uri; // Store the SymbolID in the 'data' field. The client will - // send this back in typeHierarchy/resolve, allowing us to - // continue resolving additional levels of the type hierarchy. - THI.data = S.ID.str(); + // send this back in requests to resolve additional levels + // of the hierarchy. + HI.data = S.ID.str(); - return std::move(THI); + return HI; +} + +static llvm::Optional +symbolToTypeHierarchyItem(const Symbol &S, PathRef TUPath) { + auto Result = symbolToHierarchyItem(S, TUPath); + if (Result) + Result->deprecated = (S.Flags & Symbol::Deprecated); + return Result; +} + +static llvm::Optional +symbolToCallHierarchyItem(const Symbol &S, PathRef TUPath) { + auto Result = symbolToHierarchyItem(S, TUPath); + if (Result && (S.Flags & Symbol::Deprecated)) + Result->tags.push_back(SymbolTag::Deprecated); + return Result; } static void fillSubTypes(const SymbolID &ID, @@ -1423,7 +1454,7 @@ static void fillSubTypes(const SymbolID &ID, Req.Predicate = RelationKind::BaseOf; Index->relations(Req, [&](const SymbolID &Subject, const Symbol &Object) { if (Optional ChildSym = - symbolToTypeHierarchyItem(Object, Index, TUPath)) { + symbolToTypeHierarchyItem(Object, TUPath)) { if (Levels > 1) { ChildSym->children.emplace(); fillSubTypes(Object.ID, *ChildSym->children, Index, Levels - 1, TUPath); @@ -1452,7 +1483,7 @@ static void fillSuperTypes(const CXXRecordDecl &CXXRD, ASTContext &ASTCtx, for (const CXXRecordDecl *ParentDecl : typeParents(&CXXRD)) { if (Optional ParentSym = - declToTypeHierarchyItem(ASTCtx, *ParentDecl)) { + declToTypeHierarchyItem(*ParentDecl)) { ParentSym->parents.emplace(); fillSuperTypes(*ParentDecl, ASTCtx, *ParentSym->parents, RPSet); SuperTypes.emplace_back(std::move(*ParentSym)); @@ -1522,6 +1553,10 @@ std::vector typeParents(const CXXRecordDecl *CXXRD) { CXXRD = CTSD->getSpecializedTemplate()->getTemplatedDecl(); } + // Can't query bases without a definition. + if (!CXXRD->hasDefinition()) + return Result; + for (auto Base : CXXRD->bases()) { const CXXRecordDecl *ParentDecl = nullptr; @@ -1574,8 +1609,7 @@ getTypeHierarchy(ParsedAST &AST, Position Pos, int ResolveLevels, CXXRD = CTSD->getTemplateInstantiationPattern(); } - Optional Result = - declToTypeHierarchyItem(AST.getASTContext(), *CXXRD); + Optional Result = declToTypeHierarchyItem(*CXXRD); if (!Result) return Result; @@ -1617,6 +1651,83 @@ void resolveTypeHierarchy(TypeHierarchyItem &Item, int ResolveLevels, } } +std::vector +prepareCallHierarchy(ParsedAST &AST, Position Pos, PathRef TUPath) { + std::vector Result; + const auto &SM = AST.getSourceManager(); + auto Loc = sourceLocationInMainFile(SM, Pos); + if (!Loc) { + elog("prepareCallHierarchy failed to convert position to source location: " + "{0}", + Loc.takeError()); + return Result; + } + for (const NamedDecl *Decl : getDeclAtPosition(AST, *Loc, {})) { + if (!Decl->isFunctionOrFunctionTemplate()) + continue; + if (auto CHI = declToCallHierarchyItem(*Decl)) + Result.emplace_back(std::move(*CHI)); + } + return Result; +} + +std::vector +incomingCalls(const CallHierarchyItem &Item, const SymbolIndex *Index) { + std::vector Results; + if (!Index || Item.data.empty()) + return Results; + auto ID = SymbolID::fromStr(Item.data); + if (!ID) { + elog("incomingCalls failed to find symbol: {0}", ID.takeError()); + return Results; + } + // In this function, we find incoming calls based on the index only. + // In principle, the AST could have more up-to-date information about + // occurrences within the current file. However, going from a SymbolID + // to an AST node isn't cheap, particularly when the declaration isn't + // in the main file. + // FIXME: Consider also using AST information when feasible. + RefsRequest Request; + Request.IDs.insert(*ID); + // We could restrict more specifically to calls by introducing a new RefKind, + // but non-call references (such as address-of-function) can still be + // interesting as they can indicate indirect calls. + Request.Filter = RefKind::Reference; + // Initially store the ranges in a map keyed by SymbolID of the caller. + // This allows us to group different calls with the same caller + // into the same CallHierarchyIncomingCall. + llvm::DenseMap> CallsIn; + // We can populate the ranges based on a refs request only. As we do so, we + // also accumulate the container IDs into a lookup request. + LookupRequest ContainerLookup; + Index->refs(Request, [&](const Ref &R) { + auto Loc = indexToLSPLocation(R.Location, Item.uri.file()); + if (!Loc) { + elog("incomingCalls failed to convert location: {0}", Loc.takeError()); + return; + } + auto It = CallsIn.try_emplace(R.Container, std::vector{}).first; + It->second.push_back(Loc->range); + + ContainerLookup.IDs.insert(R.Container); + }); + // Perform the lookup request and combine its results with CallsIn to + // get complete CallHierarchyIncomingCall objects. + Index->lookup(ContainerLookup, [&](const Symbol &Caller) { + auto It = CallsIn.find(Caller.ID); + assert(It != CallsIn.end()); + if (auto CHI = symbolToCallHierarchyItem(Caller, Item.uri.file())) + Results.push_back( + CallHierarchyIncomingCall{std::move(*CHI), std::move(It->second)}); + }); + // Sort results by name of container. + llvm::sort(Results, [](const CallHierarchyIncomingCall &A, + const CallHierarchyIncomingCall &B) { + return A.from.name < B.from.name; + }); + return Results; +} + llvm::DenseSet getNonLocalDeclRefs(ParsedAST &AST, const FunctionDecl *FD) { if (!FD->hasBody()) diff --git a/clang-tools-extra/clangd/XRefs.h b/clang-tools-extra/clangd/XRefs.h index fac1a992a12fe..eca174f59096b 100644 --- a/clang-tools-extra/clangd/XRefs.h +++ b/clang-tools-extra/clangd/XRefs.h @@ -110,6 +110,13 @@ void resolveTypeHierarchy(TypeHierarchyItem &Item, int ResolveLevels, TypeHierarchyDirection Direction, const SymbolIndex *Index); +/// Get call hierarchy information at \p Pos. +std::vector +prepareCallHierarchy(ParsedAST &AST, Position Pos, PathRef TUPath); + +std::vector +incomingCalls(const CallHierarchyItem &Item, const SymbolIndex *Index); + /// Returns all decls that are referenced in the \p FD except local symbols. llvm::DenseSet getNonLocalDeclRefs(ParsedAST &AST, const FunctionDecl *FD); diff --git a/clang-tools-extra/clangd/index/ProjectAware.cpp b/clang-tools-extra/clangd/index/ProjectAware.cpp new file mode 100644 index 0000000000000..63f8f823f3a72 --- /dev/null +++ b/clang-tools-extra/clangd/index/ProjectAware.cpp @@ -0,0 +1,133 @@ +//===--- ProjectAware.h ------------------------------------------*- C++-*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "ProjectAware.h" +#include "Config.h" +#include "index/Index.h" +#include "index/MemIndex.h" +#include "index/Merge.h" +#include "index/Ref.h" +#include "index/Serialization.h" +#include "index/Symbol.h" +#include "index/SymbolID.h" +#include "support/Logger.h" +#include "support/Threading.h" +#include "support/Trace.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/ErrorHandling.h" +#include +#include +#include +#include + +namespace clang { +namespace clangd { +namespace { +class ProjectAwareIndex : public SymbolIndex { +public: + size_t estimateMemoryUsage() const override; + + /// Only queries the associated index with the current context. + void lookup(const LookupRequest &Req, + llvm::function_ref Callback) const override; + + /// Query all indexes while prioritizing the associated one (if any). + bool refs(const RefsRequest &Req, + llvm::function_ref Callback) const override; + + /// Queries only the associates index when Req.RestrictForCodeCompletion is + /// set, otherwise queries all. + bool + fuzzyFind(const FuzzyFindRequest &Req, + llvm::function_ref Callback) const override; + + /// Query all indexes while prioritizing the associated one (if any). + void relations(const RelationsRequest &Req, + llvm::function_ref + Callback) const override; + + ProjectAwareIndex(IndexFactory Gen) : Gen(std::move(Gen)) {} + +private: + // Returns the index associated with current context, if any. + SymbolIndex *getIndex() const; + + // Storage for all the external indexes. + mutable std::mutex Mu; + mutable llvm::DenseMap> + IndexForSpec; + mutable AsyncTaskRunner Tasks; + + const IndexFactory Gen; +}; + +size_t ProjectAwareIndex::estimateMemoryUsage() const { + size_t Total = 0; + std::lock_guard Lock(Mu); + for (auto &Entry : IndexForSpec) + Total += Entry.second->estimateMemoryUsage(); + return Total; +} + +void ProjectAwareIndex::lookup( + const LookupRequest &Req, + llvm::function_ref Callback) const { + trace::Span Tracer("ProjectAwareIndex::lookup"); + if (auto *Idx = getIndex()) + Idx->lookup(Req, Callback); +} + +bool ProjectAwareIndex::refs( + const RefsRequest &Req, + llvm::function_ref Callback) const { + trace::Span Tracer("ProjectAwareIndex::refs"); + if (auto *Idx = getIndex()) + return Idx->refs(Req, Callback); + return false; +} + +bool ProjectAwareIndex::fuzzyFind( + const FuzzyFindRequest &Req, + llvm::function_ref Callback) const { + trace::Span Tracer("ProjectAwareIndex::fuzzyFind"); + if (auto *Idx = getIndex()) + return Idx->fuzzyFind(Req, Callback); + return false; +} + +void ProjectAwareIndex::relations( + const RelationsRequest &Req, + llvm::function_ref Callback) const { + trace::Span Tracer("ProjectAwareIndex::relations"); + if (auto *Idx = getIndex()) + return Idx->relations(Req, Callback); +} + +SymbolIndex *ProjectAwareIndex::getIndex() const { + const auto &C = Config::current(); + if (!C.Index.External) + return nullptr; + const auto &External = *C.Index.External; + std::lock_guard Lock(Mu); + auto Entry = IndexForSpec.try_emplace(External, nullptr); + if (Entry.second) + Entry.first->getSecond() = Gen(External, Tasks); + return Entry.first->second.get(); +} +} // namespace + +std::unique_ptr createProjectAwareIndex(IndexFactory Gen) { + assert(Gen); + return std::make_unique(std::move(Gen)); +} +} // namespace clangd +} // namespace clang diff --git a/clang-tools-extra/clangd/index/ProjectAware.h b/clang-tools-extra/clangd/index/ProjectAware.h new file mode 100644 index 0000000000000..af98ba6127512 --- /dev/null +++ b/clang-tools-extra/clangd/index/ProjectAware.h @@ -0,0 +1,34 @@ +//===--- ProjectAware.h ------------------------------------------*- C++-*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANGD_INDEX_PROJECT_AWARE_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANGD_INDEX_PROJECT_AWARE_H + +#include "Config.h" +#include "index/Index.h" +#include "support/Threading.h" +#include +#include +namespace clang { +namespace clangd { + +/// A functor to create an index for an external index specification. Functor +/// should perform any high latency operation in a separate thread through +/// AsyncTaskRunner. +using IndexFactory = std::function( + const Config::ExternalIndexSpec &, AsyncTaskRunner &)>; + +/// Returns an index that answers queries using external indices. IndexFactory +/// specifies how to generate an index from an external source. +/// IndexFactory must be injected because this code cannot depend on the remote +/// index client. +std::unique_ptr createProjectAwareIndex(IndexFactory); +} // namespace clangd +} // namespace clang + +#endif diff --git a/clang-tools-extra/clangd/index/remote/CMakeLists.txt b/clang-tools-extra/clangd/index/remote/CMakeLists.txt index 8625fa8f351ec..eaa000b745e5d 100644 --- a/clang-tools-extra/clangd/index/remote/CMakeLists.txt +++ b/clang-tools-extra/clangd/index/remote/CMakeLists.txt @@ -3,6 +3,12 @@ if (CLANGD_ENABLE_REMOTE) generate_protos(RemoteIndexServiceProto "Service.proto" DEPENDS "Index.proto" GRPC) + # FIXME: Move this into generate_protos. Currently we only mention proto + # filename as a dependency, but linking requires target name. + target_link_libraries(RemoteIndexServiceProto + PRIVATE + RemoteIndexProto + ) include_directories(${CMAKE_CURRENT_BINARY_DIR}) include_directories(${CMAKE_CURRENT_SOURCE_DIR}/../../) @@ -18,8 +24,8 @@ if (CLANGD_ENABLE_REMOTE) RemoteIndexProto RemoteIndexServiceProto clangdRemoteMarshalling - protobuf - grpc++ + clangBasic + clangDaemon clangdSupport DEPENDS diff --git a/clang-tools-extra/clangd/index/remote/marshalling/CMakeLists.txt b/clang-tools-extra/clangd/index/remote/marshalling/CMakeLists.txt index 7b78ba3bb6903..a5f6ebd179ec9 100644 --- a/clang-tools-extra/clangd/index/remote/marshalling/CMakeLists.txt +++ b/clang-tools-extra/clangd/index/remote/marshalling/CMakeLists.txt @@ -4,7 +4,6 @@ add_clang_library(clangdRemoteMarshalling LINK_LIBS RemoteIndexProto - protobuf clangDaemon clangdSupport diff --git a/clang-tools-extra/clangd/index/remote/server/CMakeLists.txt b/clang-tools-extra/clangd/index/remote/server/CMakeLists.txt index 595c406eff0f1..e6959db6bbd8d 100644 --- a/clang-tools-extra/clangd/index/remote/server/CMakeLists.txt +++ b/clang-tools-extra/clangd/index/remote/server/CMakeLists.txt @@ -17,6 +17,4 @@ target_link_libraries(clangd-index-server RemoteIndexProto RemoteIndexServiceProto clangdRemoteMarshalling - - grpc++ ) diff --git a/clang-tools-extra/clangd/refactor/Rename.cpp b/clang-tools-extra/clangd/refactor/Rename.cpp index 33a9c845beaac..946daaf6d158d 100644 --- a/clang-tools-extra/clangd/refactor/Rename.cpp +++ b/clang-tools-extra/clangd/refactor/Rename.cpp @@ -18,7 +18,6 @@ #include "clang/AST/DeclCXX.h" #include "clang/AST/DeclTemplate.h" #include "clang/Basic/SourceLocation.h" -#include "clang/Tooling/Refactoring/Rename/USRFindingAction.h" #include "clang/Tooling/Syntax/Tokens.h" #include "llvm/ADT/None.h" #include "llvm/ADT/STLExtras.h" @@ -76,6 +75,80 @@ llvm::Optional getOtherRefFile(const Decl &D, StringRef MainFile, return OtherFile; } +// Canonical declarations help simplify the process of renaming. Examples: +// - Template's canonical decl is the templated declaration (i.e. +// ClassTemplateDecl is canonicalized to its child CXXRecordDecl, +// FunctionTemplateDecl - to child FunctionDecl) +// - Given a constructor/destructor, canonical declaration is the parent +// CXXRecordDecl because we want to rename both type name and its ctor/dtor. +// - All specializations are canonicalized to the primary template. For example: +// +// template +// bool Foo = true; (1) +// +// template +// bool Foo = true; (2) +// +// template <> +// bool Foo = true; (3) +// +// Here, both partial (2) and full (3) specializations are canonicalized to (1) +// which ensures all three of them are renamed. +const NamedDecl *canonicalRenameDecl(const NamedDecl *D) { + if (const auto *VarTemplate = dyn_cast(D)) + return canonicalRenameDecl( + VarTemplate->getSpecializedTemplate()->getTemplatedDecl()); + if (const auto *Template = dyn_cast(D)) + if (const NamedDecl *TemplatedDecl = Template->getTemplatedDecl()) + return canonicalRenameDecl(TemplatedDecl); + if (const auto *ClassTemplateSpecialization = + dyn_cast(D)) + return canonicalRenameDecl( + ClassTemplateSpecialization->getSpecializedTemplate() + ->getTemplatedDecl()); + if (const auto *Method = dyn_cast(D)) { + if (Method->getDeclKind() == Decl::Kind::CXXConstructor || + Method->getDeclKind() == Decl::Kind::CXXDestructor) + return canonicalRenameDecl(Method->getParent()); + if (const FunctionDecl *InstantiatedMethod = + Method->getInstantiatedFromMemberFunction()) + Method = cast(InstantiatedMethod); + // FIXME(kirillbobyrev): For virtual methods with + // size_overridden_methods() > 1, this will not rename all functions it + // overrides, because this code assumes there is a single canonical + // declaration. + while (Method->isVirtual() && Method->size_overridden_methods()) + Method = *Method->overridden_methods().begin(); + return dyn_cast(Method->getCanonicalDecl()); + } + if (const auto *Function = dyn_cast(D)) + if (const FunctionTemplateDecl *Template = Function->getPrimaryTemplate()) + return canonicalRenameDecl(Template); + if (const auto *Field = dyn_cast(D)) { + // This is a hacky way to do something like + // CXXMethodDecl::getInstantiatedFromMemberFunction for the field because + // Clang AST does not store relevant information about the field that is + // instantiated. + const auto *FieldParent = dyn_cast(Field->getParent()); + if (!FieldParent) + return Field->getCanonicalDecl(); + FieldParent = FieldParent->getTemplateInstantiationPattern(); + // Field is not instantiation. + if (!FieldParent || Field->getParent() == FieldParent) + return Field->getCanonicalDecl(); + for (const FieldDecl *Candidate : FieldParent->fields()) + if (Field->getDeclName() == Candidate->getDeclName()) + return Candidate->getCanonicalDecl(); + elog("FieldParent should have field with the same name as Field."); + } + if (const auto *VD = dyn_cast(D)) { + if (const VarDecl *OriginalVD = VD->getInstantiatedFromStaticDataMember()) + VD = OriginalVD; + return VD->getCanonicalDecl(); + } + return dyn_cast(D->getCanonicalDecl()); +} + llvm::DenseSet locateDeclAt(ParsedAST &AST, SourceLocation TokenStartLoc) { unsigned Offset = @@ -91,9 +164,7 @@ llvm::DenseSet locateDeclAt(ParsedAST &AST, for (const NamedDecl *D : targetDecl(SelectedNode->ASTNode, DeclRelation::Alias | DeclRelation::TemplatePattern)) { - // Get to CXXRecordDecl from constructor or destructor. - D = tooling::getCanonicalSymbolDeclaration(D); - Result.insert(D); + Result.insert(canonicalRenameDecl(D)); } return Result; } @@ -226,19 +297,8 @@ llvm::Error makeError(ReasonToReject Reason) { std::vector findOccurrencesWithinFile(ParsedAST &AST, const NamedDecl &ND) { trace::Span Tracer("FindOccurrencesWithinFile"); - // If the cursor is at the underlying CXXRecordDecl of the - // ClassTemplateDecl, ND will be the CXXRecordDecl. In this case, we need to - // get the primary template manually. - // getUSRsForDeclaration will find other related symbols, e.g. virtual and its - // overriddens, primary template and all explicit specializations. - // FIXME: Get rid of the remaining tooling APIs. - const auto *RenameDecl = - ND.getDescribedTemplate() ? ND.getDescribedTemplate() : &ND; - std::vector RenameUSRs = - tooling::getUSRsForDeclaration(RenameDecl, AST.getASTContext()); - llvm::DenseSet TargetIDs; - for (auto &USR : RenameUSRs) - TargetIDs.insert(SymbolID(USR)); + assert(canonicalRenameDecl(&ND) == &ND && + "ND should be already canonicalized."); std::vector Results; for (Decl *TopLevelDecl : AST.getLocalTopLevelDecls()) { @@ -246,11 +306,11 @@ std::vector findOccurrencesWithinFile(ParsedAST &AST, if (Ref.Targets.empty()) return; for (const auto *Target : Ref.Targets) { - auto ID = getSymbolID(Target); - if (!ID || TargetIDs.find(ID) == TargetIDs.end()) + if (canonicalRenameDecl(Target) == &ND) { + Results.push_back(Ref.NameLoc); return; + } } - Results.push_back(Ref.NameLoc); }); } @@ -262,6 +322,7 @@ std::vector findOccurrencesWithinFile(ParsedAST &AST, const NamedDecl *lookupSiblingWithName(const ASTContext &Ctx, const NamedDecl &RenamedDecl, llvm::StringRef Name) { + trace::Span Tracer("LookupSiblingWithName"); const auto &II = Ctx.Idents.get(Name); DeclarationName LookupName(&II); DeclContextLookupResult LookupResult; @@ -302,6 +363,15 @@ struct InvalidName { Kind K; std::string Details; }; +std::string toString(InvalidName::Kind K) { + switch (K) { + case InvalidName::Keywords: + return "Keywords"; + case InvalidName::Conflict: + return "Conflict"; + } + llvm_unreachable("unhandled InvalidName kind"); +} llvm::Error makeError(InvalidName Reason) { auto Message = [](InvalidName Reason) { @@ -321,18 +391,26 @@ llvm::Error makeError(InvalidName Reason) { // Return details if the rename would produce a conflict. llvm::Optional checkName(const NamedDecl &RenameDecl, llvm::StringRef NewName) { + trace::Span Tracer("CheckName"); + static constexpr trace::Metric InvalidNameMetric( + "rename_name_invalid", trace::Metric::Counter, "invalid_kind"); auto &ASTCtx = RenameDecl.getASTContext(); + llvm::Optional Result; if (isKeyword(NewName, ASTCtx.getLangOpts())) - return InvalidName{InvalidName::Keywords, NewName.str()}; - // Name conflict detection. - // Function conflicts are subtle (overloading), so ignore them. - if (RenameDecl.getKind() != Decl::Function) { - if (auto *Conflict = lookupSiblingWithName(ASTCtx, RenameDecl, NewName)) - return InvalidName{ - InvalidName::Conflict, - Conflict->getLocation().printToString(ASTCtx.getSourceManager())}; + Result = InvalidName{InvalidName::Keywords, NewName.str()}; + else { + // Name conflict detection. + // Function conflicts are subtle (overloading), so ignore them. + if (RenameDecl.getKind() != Decl::Function) { + if (auto *Conflict = lookupSiblingWithName(ASTCtx, RenameDecl, NewName)) + Result = InvalidName{ + InvalidName::Conflict, + Conflict->getLocation().printToString(ASTCtx.getSourceManager())}; + } } - return llvm::None; + if (Result) + InvalidNameMetric.record(1, toString(Result->K)); + return Result; } // AST-based rename, it renames all occurrences in the main file. @@ -557,8 +635,7 @@ llvm::Expected rename(const RenameInputs &RInputs) { return makeError(ReasonToReject::NoSymbolFound); if (DeclsUnderCursor.size() > 1) return makeError(ReasonToReject::AmbiguousSymbol); - const auto &RenameDecl = - llvm::cast(*(*DeclsUnderCursor.begin())->getCanonicalDecl()); + const auto &RenameDecl = **DeclsUnderCursor.begin(); if (RenameDecl.getName() == RInputs.NewName) return makeError(ReasonToReject::SameName); auto Invalid = checkName(RenameDecl, RInputs.NewName); diff --git a/clang-tools-extra/clangd/refactor/tweaks/AddUsing.cpp b/clang-tools-extra/clangd/refactor/tweaks/AddUsing.cpp index cf8347f312a34..b00c2716005c7 100644 --- a/clang-tools-extra/clangd/refactor/tweaks/AddUsing.cpp +++ b/clang-tools-extra/clangd/refactor/tweaks/AddUsing.cpp @@ -43,10 +43,15 @@ class AddUsing : public Tweak { } private: - // The qualifier to remove. Set by prepare(). + // All of the following are set by prepare(). + // The qualifier to remove. NestedNameSpecifierLoc QualifierToRemove; - // The name following QualifierToRemove. Set by prepare(). + // The name following QualifierToRemove. llvm::StringRef Name; + // If valid, the insertion point for "using" statement must come after this. + // This is relevant when the type is defined in the main file, to make sure + // the type/function is already defined at the point where "using" is added. + SourceLocation MustInsertAfterLoc; }; REGISTER_TWEAK(AddUsing) @@ -119,7 +124,8 @@ struct InsertionPointData { llvm::Expected findInsertionPoint(const Tweak::Selection &Inputs, const NestedNameSpecifierLoc &QualifierToRemove, - const llvm::StringRef Name) { + const llvm::StringRef Name, + const SourceLocation MustInsertAfterLoc) { auto &SM = Inputs.AST->getSourceManager(); // Search for all using decls that affect this point in file. We need this for @@ -131,6 +137,11 @@ findInsertionPoint(const Tweak::Selection &Inputs, SM) .TraverseAST(Inputs.AST->getASTContext()); + auto IsValidPoint = [&](const SourceLocation Loc) { + return MustInsertAfterLoc.isInvalid() || + SM.isBeforeInTranslationUnit(MustInsertAfterLoc, Loc); + }; + bool AlwaysFullyQualify = true; for (auto &U : Usings) { // Only "upgrade" to fully qualified is all relevant using decls are fully @@ -141,19 +152,22 @@ findInsertionPoint(const Tweak::Selection &Inputs, if (SM.isBeforeInTranslationUnit(Inputs.Cursor, U->getUsingLoc())) // "Usings" is sorted, so we're done. break; - if (U->getQualifier()->getAsNamespace()->getCanonicalDecl() == - QualifierToRemove.getNestedNameSpecifier() - ->getAsNamespace() - ->getCanonicalDecl() && - U->getName() == Name) { - return InsertionPointData(); + if (const auto *Namespace = U->getQualifier()->getAsNamespace()) { + if (Namespace->getCanonicalDecl() == + QualifierToRemove.getNestedNameSpecifier() + ->getAsNamespace() + ->getCanonicalDecl() && + U->getName() == Name) { + return InsertionPointData(); + } } + // Insertion point will be before last UsingDecl that affects cursor // position. For most cases this should stick with the local convention of // add using inside or outside namespace. LastUsingLoc = U->getUsingLoc(); } - if (LastUsingLoc.isValid()) { + if (LastUsingLoc.isValid() && IsValidPoint(LastUsingLoc)) { InsertionPointData Out; Out.Loc = LastUsingLoc; Out.AlwaysFullyQualify = AlwaysFullyQualify; @@ -174,7 +188,7 @@ findInsertionPoint(const Tweak::Selection &Inputs, if (Tok == Toks.end() || Tok->endLocation().isInvalid()) { return error("Namespace with no {"); } - if (!Tok->endLocation().isMacroID()) { + if (!Tok->endLocation().isMacroID() && IsValidPoint(Tok->endLocation())) { InsertionPointData Out; Out.Loc = Tok->endLocation(); Out.Suffix = "\n"; @@ -182,15 +196,17 @@ findInsertionPoint(const Tweak::Selection &Inputs, } } // No using, no namespace, no idea where to insert. Try above the first - // top level decl. + // top level decl after MustInsertAfterLoc. auto TLDs = Inputs.AST->getLocalTopLevelDecls(); - if (TLDs.empty()) { - return error("Cannot find place to insert \"using\""); + for (const auto &TLD : TLDs) { + if (!IsValidPoint(TLD->getBeginLoc())) + continue; + InsertionPointData Out; + Out.Loc = SM.getExpansionLoc(TLD->getBeginLoc()); + Out.Suffix = "\n\n"; + return Out; } - InsertionPointData Out; - Out.Loc = SM.getExpansionLoc(TLDs[0]->getBeginLoc()); - Out.Suffix = "\n\n"; - return Out; + return error("Cannot find place to insert \"using\""); } bool isNamespaceForbidden(const Tweak::Selection &Inputs, @@ -206,8 +222,17 @@ bool isNamespaceForbidden(const Tweak::Selection &Inputs, return false; } +std::string getNNSLAsString(NestedNameSpecifierLoc &NNSL, + const PrintingPolicy &Policy) { + std::string Out; + llvm::raw_string_ostream OutStream(Out); + NNSL.getNestedNameSpecifier()->print(OutStream, Policy); + return OutStream.str(); +} + bool AddUsing::prepare(const Selection &Inputs) { auto &SM = Inputs.AST->getSourceManager(); + const auto &TB = Inputs.AST->getTokens(); // Do not suggest "using" in header files. That way madness lies. if (isHeaderFile(SM.getFileEntryForID(SM.getMainFileID())->getName(), @@ -244,13 +269,32 @@ bool AddUsing::prepare(const Selection &Inputs) { if (auto *II = D->getDecl()->getIdentifier()) { QualifierToRemove = D->getQualifierLoc(); Name = II->getName(); + MustInsertAfterLoc = D->getDecl()->getBeginLoc(); } } else if (auto *T = Node->ASTNode.get()) { if (auto E = T->getAs()) { - if (auto *BaseTypeIdentifier = - E.getType().getUnqualifiedType().getBaseTypeIdentifier()) { - Name = BaseTypeIdentifier->getName(); - QualifierToRemove = E.getQualifierLoc(); + QualifierToRemove = E.getQualifierLoc(); + + auto SpelledTokens = + TB.spelledForExpanded(TB.expandedTokens(E.getSourceRange())); + if (!SpelledTokens) + return false; + auto SpelledRange = syntax::Token::range(SM, SpelledTokens->front(), + SpelledTokens->back()); + Name = SpelledRange.text(SM); + + std::string QualifierToRemoveStr = getNNSLAsString( + QualifierToRemove, Inputs.AST->getASTContext().getPrintingPolicy()); + if (!Name.consume_front(QualifierToRemoveStr)) + return false; // What's spelled doesn't match the qualifier. + + if (const auto *ET = E.getTypePtr()) { + if (const auto *TDT = + dyn_cast(ET->getNamedType().getTypePtr())) { + MustInsertAfterLoc = TDT->getDecl()->getBeginLoc(); + } else if (auto *TD = ET->getAsTagDecl()) { + MustInsertAfterLoc = TD->getBeginLoc(); + } } } } @@ -283,24 +327,18 @@ bool AddUsing::prepare(const Selection &Inputs) { Expected AddUsing::apply(const Selection &Inputs) { auto &SM = Inputs.AST->getSourceManager(); - auto &TB = Inputs.AST->getTokens(); - // Determine the length of the qualifier under the cursor, then remove it. - auto SpelledTokens = TB.spelledForExpanded( - TB.expandedTokens(QualifierToRemove.getSourceRange())); - if (!SpelledTokens) { - return error("Could not determine length of the qualifier"); - } - unsigned Length = - syntax::Token::range(SM, SpelledTokens->front(), SpelledTokens->back()) - .length(); + std::string QualifierToRemoveStr = getNNSLAsString( + QualifierToRemove, Inputs.AST->getASTContext().getPrintingPolicy()); tooling::Replacements R; if (auto Err = R.add(tooling::Replacement( - SM, SpelledTokens->front().location(), Length, ""))) { + SM, SM.getSpellingLoc(QualifierToRemove.getBeginLoc()), + QualifierToRemoveStr.length(), ""))) { return std::move(Err); } - auto InsertionPoint = findInsertionPoint(Inputs, QualifierToRemove, Name); + auto InsertionPoint = + findInsertionPoint(Inputs, QualifierToRemove, Name, MustInsertAfterLoc); if (!InsertionPoint) { return InsertionPoint.takeError(); } @@ -313,9 +351,8 @@ Expected AddUsing::apply(const Selection &Inputs) { if (InsertionPoint->AlwaysFullyQualify && !isFullyQualified(QualifierToRemove.getNestedNameSpecifier())) UsingTextStream << "::"; - QualifierToRemove.getNestedNameSpecifier()->print( - UsingTextStream, Inputs.AST->getASTContext().getPrintingPolicy()); - UsingTextStream << Name << ";" << InsertionPoint->Suffix; + UsingTextStream << QualifierToRemoveStr << Name << ";" + << InsertionPoint->Suffix; assert(SM.getFileID(InsertionPoint->Loc) == SM.getMainFileID()); if (auto Err = R.add(tooling::Replacement(SM, InsertionPoint->Loc, 0, diff --git a/clang-tools-extra/clangd/refactor/tweaks/PopulateSwitch.cpp b/clang-tools-extra/clangd/refactor/tweaks/PopulateSwitch.cpp index 852888f6a0433..bae80cdecf590 100644 --- a/clang-tools-extra/clangd/refactor/tweaks/PopulateSwitch.cpp +++ b/clang-tools-extra/clangd/refactor/tweaks/PopulateSwitch.cpp @@ -126,7 +126,7 @@ bool PopulateSwitch::prepare(const Selection &Sel) { return false; EnumD = EnumT->getDecl(); - if (!EnumD) + if (!EnumD || EnumD->isDependentType()) return false; // We trigger if there are any values in the enum that aren't covered by the diff --git a/clang-tools-extra/clangd/support/CMakeLists.txt b/clang-tools-extra/clangd/support/CMakeLists.txt index e3412447142c4..f0fe073eb1361 100644 --- a/clang-tools-extra/clangd/support/CMakeLists.txt +++ b/clang-tools-extra/clangd/support/CMakeLists.txt @@ -19,6 +19,7 @@ include_directories(..) add_clang_library(clangdSupport Cancellation.cpp Context.cpp + FileCache.cpp Logger.cpp Markup.cpp MemoryTree.cpp diff --git a/clang-tools-extra/clangd/support/FileCache.cpp b/clang-tools-extra/clangd/support/FileCache.cpp new file mode 100644 index 0000000000000..4c27950158459 --- /dev/null +++ b/clang-tools-extra/clangd/support/FileCache.cpp @@ -0,0 +1,80 @@ +//===--- FileCache.cpp ----------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "support/FileCache.h" + +namespace clang { +namespace clangd { + +// Sentinel values for the Size cache key. In both cases, a successful stat of +// the file will never result in the cached value being reused. + +// The cached value does not reflect the current content on disk. +static constexpr uint64_t CacheDiskMismatch = + std::numeric_limits::max(); +// The cached value reflects that the file doesn't exist. +static constexpr uint64_t FileNotFound = CacheDiskMismatch - 1; + +FileCache::FileCache(llvm::StringRef Path) + : Path(Path), ValidTime(std::chrono::steady_clock::time_point::min()), + ModifiedTime(), Size(CacheDiskMismatch) { + assert(llvm::sys::path::is_absolute(Path)); +} + +void FileCache::read( + const ThreadsafeFS &TFS, std::chrono::steady_clock::time_point FreshTime, + llvm::function_ref)> Parse, + llvm::function_ref Read) const { + + std::lock_guard Lock(Mu); + // We're going to update the cache and return whatever's in it. + auto Return = llvm::make_scope_exit(Read); + + // Return any sufficiently recent result without doing any further work. + if (ValidTime > FreshTime) + return; + + // Ensure we always bump ValidTime, so that FreshTime imposes a hard limit on + // how often we do IO. + auto BumpValidTime = llvm::make_scope_exit( + [&] { ValidTime = std::chrono::steady_clock::now(); }); + + // stat is cheaper than opening the file. It's usually unchanged. + assert(llvm::sys::path::is_absolute(Path)); + auto FS = TFS.view(/*CWD=*/llvm::None); + auto Stat = FS->status(Path); + if (!Stat || !Stat->isRegularFile()) { + if (Size != FileNotFound) // Allow "not found" value to be cached. + Parse(llvm::None); + // Ensure the cache key won't match any future stat(). + Size = FileNotFound; + return; + } + // If the modified-time and size match, assume the content does too. + if (Size == Stat->getSize() && + ModifiedTime == Stat->getLastModificationTime()) + return; + + // OK, the file has actually changed. Update cache key, compute new value. + Size = Stat->getSize(); + ModifiedTime = Stat->getLastModificationTime(); + // Now read the file from disk. + if (auto Buf = FS->getBufferForFile(Path)) { + Parse(Buf->get()->getBuffer()); + // Result is cacheable if the actual read size matches the new cache key. + // (We can't update the cache key, because we don't know the new mtime). + if (Buf->get()->getBufferSize() != Size) + Size = CacheDiskMismatch; + } else { + // File was unreadable. Keep the old value and try again next time. + Size = CacheDiskMismatch; + } +} + +} // namespace clangd +} // namespace clang diff --git a/clang-tools-extra/clangd/support/FileCache.h b/clang-tools-extra/clangd/support/FileCache.h new file mode 100644 index 0000000000000..ffc5deb7442ba --- /dev/null +++ b/clang-tools-extra/clangd/support/FileCache.h @@ -0,0 +1,81 @@ +//===--- FileCache.h - Revalidating cache of data from disk ------*- C++-*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANGD_SUPPORT_FILECACHE_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANGD_SUPPORT_FILECACHE_H + +#include "Path.h" +#include "ThreadsafeFS.h" +#include "llvm/ADT/ScopeExit.h" +#include "llvm/Support/Chrono.h" +#include "llvm/Support/VirtualFileSystem.h" +#include + +namespace clang { +namespace clangd { + +/// Base class for threadsafe cache of data read from a file on disk. +/// +/// We want configuration files to be "live" as much as possible. +/// Reading them every time is simplest, but caching solves a few problems: +/// - reading and parsing is cheap but not free (and happens on hot paths) +/// - we can ignore invalid data and use the old value (we may see truncated +/// compile_commands.json from non-atomic writers) +/// - we avoid reporting the same errors repeatedly +/// +/// We still read and parse the data synchronously on demand, but skip as much +/// work as possible: +/// - if not enough wall-time has elapsed, assume the data is still up-to-date +/// - if we stat the file and it has the same mtime + size, don't read it +/// - obviously we only have to parse when we re-read the file +/// (Tracking OS change events is an alternative, but difficult to do portably.) +/// +/// Caches for particular data (e.g. compilation databases) should inherit and: +/// - add mutable storage for the cached parsed data +/// - add a public interface implemented on top of read() +class FileCache { +protected: + // Path must be absolute. + FileCache(PathRef Path); + + // Updates the cached value if needed, then provides threadsafe access to it. + // + // Specifically: + // - Parse() may be called (if the cache was not up-to-date) + // The lock is held, so cache storage may be safely written. + // Parse(None) means the file doesn't exist. + // - Read() will always be called, to provide access to the value. + // The lock is again held, so the value can be copied or used. + // + // If the last Parse is newer than FreshTime, we don't check metadata. + // - time_point::min() means we only do IO if we never read the file before + // - time_point::max() means we always at least stat the file + // - steady_clock::now() + seconds(1) means we accept 1 second of staleness + void read(const ThreadsafeFS &TFS, + std::chrono::steady_clock::time_point FreshTime, + llvm::function_ref)> Parse, + llvm::function_ref Read) const; + + PathRef path() const { return Path; } + +private: + std::string Path; + // Members are mutable so read() can present a const interface. + // (It is threadsafe and approximates read-through to TFS). + mutable std::mutex Mu; + // Time when the cache was known valid (reflected disk state). + mutable std::chrono::steady_clock::time_point ValidTime; + // Filesystem metadata corresponding to the currently cached data. + mutable llvm::sys::TimePoint<> ModifiedTime; + mutable uint64_t Size; +}; + +} // namespace clangd +} // namespace clang + +#endif diff --git a/clang-tools-extra/clangd/test/call-hierarchy.test b/clang-tools-extra/clangd/test/call-hierarchy.test new file mode 100644 index 0000000000000..6548ea0068a8d --- /dev/null +++ b/clang-tools-extra/clangd/test/call-hierarchy.test @@ -0,0 +1,39 @@ +# RUN: clangd -lit-test < %s | FileCheck -strict-whitespace %s +{"jsonrpc":"2.0","id":0,"method":"initialize","params":{"processId":123,"rootPath":"clangd","capabilities":{},"trace":"off"}} +--- +{"jsonrpc":"2.0","method":"textDocument/didOpen","params":{"textDocument":{"languageId":"cpp","text":"void callee(int);\nvoid caller1() {\n callee(42);\n}\nvoid caller2() {\n caller1();\n caller1();\n}\nvoid caller3() {\n caller1();\n caller2();\n}\n","uri":"test:///main.cpp","version":1}}} +--- +{"jsonrpc":"2.0","id":1,"method":"textDocument/prepareCallHierarchy","params":{"position":{"character":8,"line":0},"textDocument":{"uri":"test:///main.cpp"}}} +# CHECK: "id": 1, +# CHECK-NEXT: "jsonrpc": "2.0", +# CHECK-NEXT: "result": [ +# CHECK-NEXT: { +# CHECK-NEXT: "data": "{{.*}}", +# CHECK-NEXT: "kind": 12, +# CHECK-NEXT: "name": "callee", +# CHECK-NEXT: "range": { +# CHECK-NEXT: "end": { +# CHECK-NEXT: "character": 16, +# CHECK-NEXT: "line": 0 +# CHECK-NEXT: }, +# CHECK-NEXT: "start": { +# CHECK-NEXT: "character": 0, +# CHECK-NEXT: "line": 0 +# CHECK-NEXT: } +# CHECK-NEXT: }, +# CHECK-NEXT: "selectionRange": { +# CHECK-NEXT: "end": { +# CHECK-NEXT: "character": 11, +# CHECK-NEXT: "line": 0 +# CHECK-NEXT: }, +# CHECK-NEXT: "start": { +# CHECK-NEXT: "character": 5, +# CHECK-NEXT: "line": 0 +# CHECK-NEXT: } +# CHECK-NEXT: }, +# CHECK-NEXT: "uri": "file://{{.*}}/clangd-test/main.cpp" +# CHECK-NEXT: } +--- +{"jsonrpc":"2.0","id":3,"method":"shutdown"} +--- +{"jsonrpc":"2.0","method":"exit"} diff --git a/clang-tools-extra/clangd/test/implementations.test b/clang-tools-extra/clangd/test/implementations.test new file mode 100644 index 0000000000000..cc20d90bab775 --- /dev/null +++ b/clang-tools-extra/clangd/test/implementations.test @@ -0,0 +1,39 @@ +# RUN: clangd -lit-test < %s | FileCheck -strict-whitespace %s +{"jsonrpc":"2.0","id":0,"method":"initialize","params":{"processId":123,"rootPath":"clangd","capabilities":{},"trace":"off"}} +--- +{"jsonrpc":"2.0","method":"textDocument/didOpen","params":{"textDocument":{"uri":"test:///main.cpp","languageId":"cpp","version":1,"text":"struct Parent { virtual void Foo(); };\nstruct Child1 : Parent { void Foo() override(); };\nstruct Child2 : Parent { void Foo() override(); };"}}} +--- +{"jsonrpc":"2.0","id":1,"method":"textDocument/implementation","params":{"textDocument":{"uri":"test:///main.cpp"},"position":{"line":0,"character":32}}} +# CHECK: "id": 1 +# CHECK-NEXT: "jsonrpc": "2.0", +# CHECK-NEXT: "result": [ +# CHECK-NEXT: { +# CHECK-NEXT: "range": { +# CHECK-NEXT: "end": { +# CHECK-NEXT: "character": 33, +# CHECK-NEXT: "line": 1 +# CHECK-NEXT: }, +# CHECK-NEXT: "start": { +# CHECK-NEXT: "character": 30, +# CHECK-NEXT: "line": 1 +# CHECK-NEXT: } +# CHECK-NEXT: }, +# CHECK-NEXT: "uri": "file://{{.*}}/clangd-test/main.cpp" +# CHECK-NEXT: }, +# CHECK-NEXT: { +# CHECK-NEXT: "range": { +# CHECK-NEXT: "end": { +# CHECK-NEXT: "character": 33, +# CHECK-NEXT: "line": 2 +# CHECK-NEXT: }, +# CHECK-NEXT: "start": { +# CHECK-NEXT: "character": 30, +# CHECK-NEXT: "line": 2 +# CHECK-NEXT: } +# CHECK-NEXT: }, +# CHECK-NEXT: "uri": "file://{{.*}}/clangd-test/main.cpp" +# CHECK-NEXT: } +--- +{"jsonrpc":"2.0","id":3,"method":"shutdown"} +--- +{"jsonrpc":"2.0","method":"exit"} diff --git a/clang-tools-extra/clangd/test/initialize-params.test b/clang-tools-extra/clangd/test/initialize-params.test index a08a9b14a317d..e4f4bf18dee46 100644 --- a/clang-tools-extra/clangd/test/initialize-params.test +++ b/clang-tools-extra/clangd/test/initialize-params.test @@ -6,6 +6,7 @@ # CHECK-NEXT: "result": { # CHECK-NEXT: "capabilities": { # CHECK-NEXT: "astProvider": true, +# CHECK-NEXT: "callHierarchyProvider": true, # CHECK-NEXT: "codeActionProvider": true, # CHECK-NEXT: "completionProvider": { # CHECK-NEXT: "allCommitCharacters": [ @@ -67,7 +68,8 @@ # CHECK-NEXT: ] # CHECK-NEXT: }, # CHECK-NEXT: "hoverProvider": true, -# CHECK-NEXT: "memoryUsageProvider": true +# CHECK-NEXT: "implementationProvider": true, +# CHECK-NEXT: "memoryUsageProvider": true, # CHECK-NEXT: "referencesProvider": true, # CHECK-NEXT: "renameProvider": true, # CHECK-NEXT: "selectionRangeProvider": true, diff --git a/clang-tools-extra/clangd/test/system-include-extractor.test b/clang-tools-extra/clangd/test/system-include-extractor.test index 03cb54069d6ec..59989be6ca6c9 100644 --- a/clang-tools-extra/clangd/test/system-include-extractor.test +++ b/clang-tools-extra/clangd/test/system-include-extractor.test @@ -12,6 +12,7 @@ # RUN: echo '[ -z "${args##*"-isysroot=/isysroot"*}" ] || exit' >> %t.dir/my_driver.sh # RUN: echo 'echo " $* " | grep " --sysroot /my/sysroot/path " || exit' >> %t.dir/my_driver.sh # RUN: echo 'echo line to ignore >&2' >> %t.dir/my_driver.sh +# RUN: echo 'printf "Target: arm-linux-gnueabihf\r\n" >&2' >> %t.dir/my_driver.sh # RUN: echo 'printf "#include <...> search starts here:\r\n" >&2' >> %t.dir/my_driver.sh # RUN: echo 'echo %t.dir/my/dir/ >&2' >> %t.dir/my_driver.sh # RUN: echo 'echo %t.dir/my/dir2/ >&2' >> %t.dir/my_driver.sh @@ -45,7 +46,7 @@ "uri": "file://INPUT_DIR/the-file.cpp", "languageId":"cpp", "version":1, - "text":"#include \n#include " + "text":"#include \n#include \n#if !defined(__ARM_ARCH) || !defined(__gnu_linux__)\n#error \"Invalid target\"\n#endif" } } } diff --git a/clang-tools-extra/clangd/tool/Check.cpp b/clang-tools-extra/clangd/tool/Check.cpp index 14ee0fdec9c91..9b40e840478e5 100644 --- a/clang-tools-extra/clangd/tool/Check.cpp +++ b/clang-tools-extra/clangd/tool/Check.cpp @@ -133,8 +133,6 @@ class Checker { return false; } } - Inputs.Opts.ClangTidyOpts = - Opts.GetClangTidyOptions(*TFS.view(llvm::None), File); log("Parsing command..."); Invocation = buildCompilerInvocation(Inputs, CaptureInvocationDiags, &CC1Args); diff --git a/clang-tools-extra/clangd/tool/ClangdMain.cpp b/clang-tools-extra/clangd/tool/ClangdMain.cpp index 08d498f308737..d0eab36507503 100644 --- a/clang-tools-extra/clangd/tool/ClangdMain.cpp +++ b/clang-tools-extra/clangd/tool/ClangdMain.cpp @@ -11,8 +11,12 @@ #include "Features.inc" #include "PathMapping.h" #include "Protocol.h" +#include "TidyProvider.h" #include "Transport.h" #include "index/Background.h" +#include "index/Index.h" +#include "index/Merge.h" +#include "index/ProjectAware.h" #include "index/Serialization.h" #include "index/remote/Client.h" #include "refactor/Rename.h" @@ -40,6 +44,7 @@ #include #include #include +#include #ifndef _WIN32 #include @@ -489,7 +494,7 @@ opt CollectMainFileRefs{ "collect-main-file-refs", cat(Misc), desc("Store references to main-file-only symbols in the index"), - init(false), + init(ClangdServer::Options().CollectMainFileRefs), }; #if CLANGD_ENABLE_REMOTE @@ -551,6 +556,27 @@ const char TestScheme::TestDir[] = "C:\\clangd-test"; const char TestScheme::TestDir[] = "/clangd-test"; #endif +std::unique_ptr +loadExternalIndex(const Config::ExternalIndexSpec &External, + AsyncTaskRunner &Tasks) { + switch (External.Kind) { + case Config::ExternalIndexSpec::Server: + log("Associating {0} with remote index at {1}.", External.MountPoint, + External.Location); + return remote::getClient(External.Location, External.MountPoint); + case Config::ExternalIndexSpec::File: + log("Associating {0} with monolithic index at {1}.", External.MountPoint, + External.Location); + auto NewIndex = std::make_unique(std::make_unique()); + Tasks.runAsync("Load-index:" + External.Location, + [File = External.Location, PlaceHolder = NewIndex.get()] { + if (auto Idx = loadIndex(File, /*UseDex=*/true)) + PlaceHolder->reset(std::move(Idx)); + }); + return std::move(NewIndex); + } + llvm_unreachable("Invalid ExternalIndexKind."); +} } // namespace } // namespace clangd } // namespace clang @@ -726,6 +752,7 @@ clangd accepts flags on the commandline, and in the CLANGD_FLAGS environment var Opts.ResourceDir = ResourceDir; Opts.BuildDynamicSymbolIndex = EnableIndex; Opts.CollectMainFileRefs = CollectMainFileRefs; + std::vector> IdxStack; std::unique_ptr StaticIdx; std::future AsyncIndexLoad; // Block exit while loading the index. if (EnableIndex && !IndexFile.empty()) { @@ -757,7 +784,15 @@ clangd accepts flags on the commandline, and in the CLANGD_FLAGS environment var } #endif Opts.BackgroundIndex = EnableBackgroundIndex; - Opts.StaticIndex = StaticIdx.get(); + auto PAI = createProjectAwareIndex(loadExternalIndex); + if (StaticIdx) { + IdxStack.emplace_back(std::move(StaticIdx)); + IdxStack.emplace_back( + std::make_unique(PAI.get(), IdxStack.back().get())); + Opts.StaticIndex = IdxStack.back().get(); + } else { + Opts.StaticIndex = PAI.get(); + } Opts.AsyncThreadsCount = WorkerThreadsCount; Opts.BuildRecoveryAST = RecoveryAST; Opts.PreserveRecoveryASTType = RecoveryASTType; @@ -803,35 +838,21 @@ clangd accepts flags on the commandline, and in the CLANGD_FLAGS environment var } // Create an empty clang-tidy option. - std::mutex ClangTidyOptMu; - std::unique_ptr - ClangTidyOptProvider; /*GUARDED_BY(ClangTidyOptMu)*/ + TidyProvider ClangTidyOptProvider; if (EnableClangTidy) { - auto EmptyDefaults = tidy::ClangTidyOptions::getDefaults(); - EmptyDefaults.Checks.reset(); // So we can tell if checks were ever set. - EmptyDefaults.User = llvm::sys::Process::GetEnv("USER"); -#ifdef _WIN32 - if (!EmptyDefaults.User) - EmptyDefaults.User = llvm::sys::Process::GetEnv("USERNAME"); -#endif - tidy::ClangTidyOptions OverrideClangTidyOptions; + std::vector Providers; + Providers.reserve(4 + EnableConfig); + Providers.push_back(provideEnvironment()); + Providers.push_back(provideClangTidyFiles(TFS)); + if (EnableConfig) + Providers.push_back(provideClangdConfig()); if (!ClangTidyChecks.empty()) - OverrideClangTidyOptions.Checks = ClangTidyChecks; - ClangTidyOptProvider = std::make_unique( - tidy::ClangTidyGlobalOptions(), - /* Default */ EmptyDefaults, - /* Override */ OverrideClangTidyOptions, TFS.view(/*CWD=*/llvm::None)); - Opts.GetClangTidyOptions = [&](llvm::vfs::FileSystem &, - llvm::StringRef File) { - // This function must be thread-safe and tidy option providers are not. - tidy::ClangTidyOptions Opts; - { - std::lock_guard Lock(ClangTidyOptMu); - // FIXME: use the FS provided to the function. - Opts = ClangTidyOptProvider->getOptions(File); - } - return Opts; - }; + Providers.push_back(addTidyChecks(ClangTidyChecks)); + else + Providers.push_back(provideDefaultChecks()); + Providers.push_back(disableUnusableChecks()); + ClangTidyOptProvider = combine(std::move(Providers)); + Opts.ClangTidyProvider = ClangTidyOptProvider; } Opts.AsyncPreambleBuilds = AsyncPreamble; Opts.SuggestMissingIncludes = SuggestMissingIncludes; diff --git a/clang-tools-extra/clangd/unittests/BackgroundIndexTests.cpp b/clang-tools-extra/clangd/unittests/BackgroundIndexTests.cpp index b25d3fde00025..f4a9b2fa2d139 100644 --- a/clang-tools-extra/clangd/unittests/BackgroundIndexTests.cpp +++ b/clang-tools-extra/clangd/unittests/BackgroundIndexTests.cpp @@ -188,8 +188,10 @@ TEST_F(BackgroundIndexTest, IndexTwoFiles) { size_t CacheHits = 0; MemoryShardStorage MSS(Storage, CacheHits); OverlayCDB CDB(/*Base=*/nullptr); - BackgroundIndex Idx(FS, CDB, [&](llvm::StringRef) { return &MSS; }, - /*Opts=*/{}); + BackgroundIndex::Options Opts; + Opts.CollectMainFileRefs = true; + BackgroundIndex Idx( + FS, CDB, [&](llvm::StringRef) { return &MSS; }, Opts); tooling::CompileCommand Cmd; Cmd.Filename = testPath("root/A.cc"); @@ -201,7 +203,7 @@ TEST_F(BackgroundIndexTest, IndexTwoFiles) { EXPECT_THAT(runFuzzyFind(Idx, ""), UnorderedElementsAre(AllOf(Named("common"), NumReferences(1U)), AllOf(Named("A_CC"), NumReferences(0U)), - AllOf(Named("g"), NumReferences(0U)), + AllOf(Named("g"), NumReferences(1U)), AllOf(Named("f_b"), Declared(), Not(Defined()), NumReferences(0U)))); @@ -214,7 +216,7 @@ TEST_F(BackgroundIndexTest, IndexTwoFiles) { EXPECT_THAT(runFuzzyFind(Idx, ""), UnorderedElementsAre(AllOf(Named("common"), NumReferences(5U)), AllOf(Named("A_CC"), NumReferences(0U)), - AllOf(Named("g"), NumReferences(0U)), + AllOf(Named("g"), NumReferences(1U)), AllOf(Named("f_b"), Declared(), Defined(), NumReferences(1U)))); @@ -238,7 +240,8 @@ TEST_F(BackgroundIndexTest, MainFileRefs) { FS.Files[testPath("root/A.cc")] = "#include \"A.h\"\nstatic void main_sym() { (void)header_sym; }"; - // Check the behaviour with CollectMainFileRefs = false (the default). + // Check the behaviour with CollectMainFileRefs = false (the default + // at the SymbolCollector level). { llvm::StringMap Storage; size_t CacheHits = 0; diff --git a/clang-tools-extra/clangd/unittests/CMakeLists.txt b/clang-tools-extra/clangd/unittests/CMakeLists.txt index e570072783f10..72ce97ed31b61 100644 --- a/clang-tools-extra/clangd/unittests/CMakeLists.txt +++ b/clang-tools-extra/clangd/unittests/CMakeLists.txt @@ -36,6 +36,7 @@ add_unittest(ClangdUnitTests ClangdTests Annotations.cpp ASTTests.cpp BackgroundIndexTests.cpp + CallHierarchyTests.cpp CanonicalIncludesTests.cpp ClangdTests.cpp ClangdLSPServerTests.cpp @@ -74,6 +75,7 @@ add_unittest(ClangdUnitTests ClangdTests PathMappingTests.cpp PreambleTests.cpp PrintASTTests.cpp + ProjectAwareIndexTests.cpp QualityTests.cpp RenameTests.cpp RIFFTests.cpp @@ -144,7 +146,8 @@ target_link_libraries(ClangdTests if (CLANGD_ENABLE_REMOTE) target_link_libraries(ClangdTests PRIVATE - clangdRemoteMarshalling) + clangdRemoteMarshalling + RemoteIndexProto) endif() if (CLANGD_BUILD_XPC) diff --git a/clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp b/clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp new file mode 100644 index 0000000000000..8b5069d8dae80 --- /dev/null +++ b/clang-tools-extra/clangd/unittests/CallHierarchyTests.cpp @@ -0,0 +1,257 @@ +//===-- CallHierarchyTests.cpp ---------------------------*- C++ -*-------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#include "Annotations.h" +#include "Compiler.h" +#include "Matchers.h" +#include "ParsedAST.h" +#include "SyncAPI.h" +#include "TestFS.h" +#include "TestTU.h" +#include "TestWorkspace.h" +#include "XRefs.h" +#include "index/FileIndex.h" +#include "index/SymbolCollector.h" +#include "clang/AST/DeclCXX.h" +#include "clang/AST/DeclTemplate.h" +#include "clang/Index/IndexingAction.h" +#include "llvm/Support/Path.h" +#include "llvm/Support/ScopedPrinter.h" +#include "gmock/gmock.h" +#include "gtest/gtest.h" + +namespace clang { +namespace clangd { +namespace { + +using ::testing::AllOf; +using ::testing::ElementsAre; +using ::testing::Field; +using ::testing::IsEmpty; +using ::testing::Matcher; +using ::testing::UnorderedElementsAre; + +// Helpers for matching call hierarchy data structures. +MATCHER_P(WithName, N, "") { return arg.name == N; } +MATCHER_P(WithSelectionRange, R, "") { return arg.selectionRange == R; } + +template +::testing::Matcher From(ItemMatcher M) { + return Field(&CallHierarchyIncomingCall::from, M); +} +template +::testing::Matcher FromRanges(RangeMatchers... M) { + return Field(&CallHierarchyIncomingCall::fromRanges, + UnorderedElementsAre(M...)); +} + +TEST(CallHierarchy, IncomingOneFile) { + Annotations Source(R"cpp( + void call^ee(int); + void caller1() { + $Callee[[callee]](42); + } + void caller2() { + $Caller1A[[caller1]](); + $Caller1B[[caller1]](); + } + void caller3() { + $Caller1C[[caller1]](); + $Caller2[[caller2]](); + } + )cpp"); + TestTU TU = TestTU::withCode(Source.code()); + auto AST = TU.build(); + auto Index = TU.index(); + + std::vector Items = + prepareCallHierarchy(AST, Source.point(), testPath(TU.Filename)); + ASSERT_THAT(Items, ElementsAre(WithName("callee"))); + auto IncomingLevel1 = incomingCalls(Items[0], Index.get()); + ASSERT_THAT(IncomingLevel1, + ElementsAre(AllOf(From(WithName("caller1")), + FromRanges(Source.range("Callee"))))); + + auto IncomingLevel2 = incomingCalls(IncomingLevel1[0].from, Index.get()); + ASSERT_THAT(IncomingLevel2, + ElementsAre(AllOf(From(WithName("caller2")), + FromRanges(Source.range("Caller1A"), + Source.range("Caller1B"))), + AllOf(From(WithName("caller3")), + FromRanges(Source.range("Caller1C"))))); + + auto IncomingLevel3 = incomingCalls(IncomingLevel2[0].from, Index.get()); + ASSERT_THAT(IncomingLevel3, + ElementsAre(AllOf(From(WithName("caller3")), + FromRanges(Source.range("Caller2"))))); + + auto IncomingLevel4 = incomingCalls(IncomingLevel3[0].from, Index.get()); + EXPECT_THAT(IncomingLevel4, IsEmpty()); +} + +TEST(CallHierarchy, MainFileOnlyRef) { + // In addition to testing that we store refs to main-file only symbols, + // this tests that anonymous namespaces do not interfere with the + // symbol re-identification process in callHierarchyItemToSymbo(). + Annotations Source(R"cpp( + void call^ee(int); + namespace { + void caller1() { + $Callee[[callee]](42); + } + } + void caller2() { + $Caller1[[caller1]](); + } + )cpp"); + TestTU TU = TestTU::withCode(Source.code()); + auto AST = TU.build(); + auto Index = TU.index(); + + std::vector Items = + prepareCallHierarchy(AST, Source.point(), testPath(TU.Filename)); + ASSERT_THAT(Items, ElementsAre(WithName("callee"))); + auto IncomingLevel1 = incomingCalls(Items[0], Index.get()); + ASSERT_THAT(IncomingLevel1, + ElementsAre(AllOf(From(WithName("caller1")), + FromRanges(Source.range("Callee"))))); + + auto IncomingLevel2 = incomingCalls(IncomingLevel1[0].from, Index.get()); + EXPECT_THAT(IncomingLevel2, + ElementsAre(AllOf(From(WithName("caller2")), + FromRanges(Source.range("Caller1"))))); +} + +TEST(CallHierarchy, IncomingQualified) { + Annotations Source(R"cpp( + namespace ns { + struct Waldo { + void find(); + }; + void Waldo::find() {} + void caller1(Waldo &W) { + W.$Caller1[[f^ind]](); + } + void caller2(Waldo &W) { + W.$Caller2[[find]](); + } + } + )cpp"); + TestTU TU = TestTU::withCode(Source.code()); + auto AST = TU.build(); + auto Index = TU.index(); + + std::vector Items = + prepareCallHierarchy(AST, Source.point(), testPath(TU.Filename)); + ASSERT_THAT(Items, ElementsAre(WithName("Waldo::find"))); + auto Incoming = incomingCalls(Items[0], Index.get()); + EXPECT_THAT(Incoming, + ElementsAre(AllOf(From(WithName("caller1")), + FromRanges(Source.range("Caller1"))), + AllOf(From(WithName("caller2")), + FromRanges(Source.range("Caller2"))))); +} + +TEST(CallHierarchy, IncomingMultiFile) { + // The test uses a .hh suffix for header files to get clang + // to parse them in C++ mode. .h files are parsed in C mode + // by default, which causes problems because e.g. symbol + // USRs are different in C mode (do not include function signatures). + + Annotations CalleeH(R"cpp( + void calle^e(int); + )cpp"); + Annotations CalleeC(R"cpp( + #include "callee.hh" + void calle^e(int) {} + )cpp"); + Annotations Caller1H(R"cpp( + void caller1(); + )cpp"); + Annotations Caller1C(R"cpp( + #include "callee.hh" + #include "caller1.hh" + void caller1() { + [[calle^e]](42); + } + )cpp"); + Annotations Caller2H(R"cpp( + void caller2(); + )cpp"); + Annotations Caller2C(R"cpp( + #include "caller1.hh" + #include "caller2.hh" + void caller2() { + $A[[caller1]](); + $B[[caller1]](); + } + )cpp"); + Annotations Caller3C(R"cpp( + #include "caller1.hh" + #include "caller2.hh" + void caller3() { + $Caller1[[caller1]](); + $Caller2[[caller2]](); + } + )cpp"); + + TestWorkspace Workspace; + Workspace.addSource("callee.hh", CalleeH.code()); + Workspace.addSource("caller1.hh", Caller1H.code()); + Workspace.addSource("caller2.hh", Caller2H.code()); + Workspace.addMainFile("callee.cc", CalleeC.code()); + Workspace.addMainFile("caller1.cc", Caller1C.code()); + Workspace.addMainFile("caller2.cc", Caller2C.code()); + Workspace.addMainFile("caller3.cc", Caller3C.code()); + + auto Index = Workspace.index(); + + auto CheckCallHierarchy = [&](ParsedAST &AST, Position Pos, PathRef TUPath) { + std::vector Items = + prepareCallHierarchy(AST, Pos, TUPath); + ASSERT_THAT(Items, ElementsAre(WithName("callee"))); + auto IncomingLevel1 = incomingCalls(Items[0], Index.get()); + ASSERT_THAT(IncomingLevel1, + ElementsAre(AllOf(From(WithName("caller1")), + FromRanges(Caller1C.range())))); + + auto IncomingLevel2 = incomingCalls(IncomingLevel1[0].from, Index.get()); + ASSERT_THAT( + IncomingLevel2, + ElementsAre(AllOf(From(WithName("caller2")), + FromRanges(Caller2C.range("A"), Caller2C.range("B"))), + AllOf(From(WithName("caller3")), + FromRanges(Caller3C.range("Caller1"))))); + + auto IncomingLevel3 = incomingCalls(IncomingLevel2[0].from, Index.get()); + ASSERT_THAT(IncomingLevel3, + ElementsAre(AllOf(From(WithName("caller3")), + FromRanges(Caller3C.range("Caller2"))))); + + auto IncomingLevel4 = incomingCalls(IncomingLevel3[0].from, Index.get()); + EXPECT_THAT(IncomingLevel4, IsEmpty()); + }; + + // Check that invoking from a call site works. + auto AST = Workspace.openFile("caller1.cc"); + ASSERT_TRUE(bool(AST)); + CheckCallHierarchy(*AST, Caller1C.point(), testPath("caller1.cc")); + + // Check that invoking from the declaration site works. + AST = Workspace.openFile("callee.hh"); + ASSERT_TRUE(bool(AST)); + CheckCallHierarchy(*AST, CalleeH.point(), testPath("callee.hh")); + + // Check that invoking from the definition site works. + AST = Workspace.openFile("callee.cc"); + ASSERT_TRUE(bool(AST)); + CheckCallHierarchy(*AST, CalleeC.point(), testPath("callee.cc")); +} + +} // namespace +} // namespace clangd +} // namespace clang diff --git a/clang-tools-extra/clangd/unittests/ClangdLSPServerTests.cpp b/clang-tools-extra/clangd/unittests/ClangdLSPServerTests.cpp index ff3b27d8cf990..8cd8764f3ef43 100644 --- a/clang-tools-extra/clangd/unittests/ClangdLSPServerTests.cpp +++ b/clang-tools-extra/clangd/unittests/ClangdLSPServerTests.cpp @@ -37,6 +37,8 @@ class LSPTest : public ::testing::Test, private clangd::Logger { LSPTest() : LogSession(*this) { ClangdServer::Options &Base = Opts; Base = ClangdServer::optsForTest(); + // This is needed to we can test index-based operations like call hierarchy. + Base.BuildDynamicSymbolIndex = true; } LSPClient &start() { @@ -165,6 +167,33 @@ TEST_F(LSPTest, RecordsLatencies) { stop(); EXPECT_THAT(Tracer.takeMetric("lsp_latency", MethodName), testing::SizeIs(1)); } + +TEST_F(LSPTest, IncomingCalls) { + Annotations Code(R"cpp( + void calle^e(int); + void caller1() { + [[callee]](42); + } + )cpp"); + auto &Client = start(); + Client.didOpen("foo.cpp", Code.code()); + auto Items = Client + .call("textDocument/prepareCallHierarchy", + llvm::json::Object{ + {"textDocument", Client.documentID("foo.cpp")}, + {"position", Code.point()}}) + .takeValue(); + auto FirstItem = (*Items.getAsArray())[0]; + auto Calls = Client + .call("callHierarchy/incomingCalls", + llvm::json::Object{{"item", FirstItem}}) + .takeValue(); + auto FirstCall = *(*Calls.getAsArray())[0].getAsObject(); + EXPECT_EQ(FirstCall["fromRanges"], llvm::json::Value{Code.range()}); + auto From = *FirstCall["from"].getAsObject(); + EXPECT_EQ(From["name"], "caller1"); +} + } // namespace } // namespace clangd } // namespace clang diff --git a/clang-tools-extra/clangd/unittests/ClangdTests.cpp b/clang-tools-extra/clangd/unittests/ClangdTests.cpp index f2d6d6b8192b4..06d761d4fabed 100644 --- a/clang-tools-extra/clangd/unittests/ClangdTests.cpp +++ b/clang-tools-extra/clangd/unittests/ClangdTests.cpp @@ -16,6 +16,7 @@ #include "SyncAPI.h" #include "TestFS.h" #include "TestTU.h" +#include "TidyProvider.h" #include "URI.h" #include "support/MemoryTree.h" #include "support/Path.h" @@ -1215,16 +1216,19 @@ TEST(ClangdServer, TidyOverrideTest) { } DiagConsumer; MockFS FS; + // These checks don't work well in clangd, even if configured they shouldn't + // run. + FS.Files[testPath(".clang-tidy")] = R"( + Checks: -*,bugprone-use-after-move,llvm-header-guard + )"; MockCompilationDatabase CDB; + std::vector Stack; + Stack.push_back(provideClangTidyFiles(FS)); + Stack.push_back(disableUnusableChecks()); + TidyProvider Provider = combine(std::move(Stack)); CDB.ExtraClangFlags = {"-xc++"}; auto Opts = ClangdServer::optsForTest(); - Opts.GetClangTidyOptions = [](llvm::vfs::FileSystem &, llvm::StringRef) { - auto Opts = tidy::ClangTidyOptions::getDefaults(); - // These checks don't work well in clangd, even if configured they shouldn't - // run. - Opts.Checks = "bugprone-use-after-move,llvm-header-guard"; - return Opts; - }; + Opts.ClangTidyProvider = Provider; ClangdServer Server(CDB, FS, Opts, &DiagConsumer); const char *SourceContents = R"cpp( struct Foo { Foo(); Foo(Foo&); Foo(Foo&&); }; diff --git a/clang-tools-extra/clangd/unittests/ConfigCompileTests.cpp b/clang-tools-extra/clangd/unittests/ConfigCompileTests.cpp index f791820f7e450..a2423094b17a9 100644 --- a/clang-tools-extra/clangd/unittests/ConfigCompileTests.cpp +++ b/clang-tools-extra/clangd/unittests/ConfigCompileTests.cpp @@ -9,9 +9,13 @@ #include "Config.h" #include "ConfigFragment.h" #include "ConfigTesting.h" +#include "Features.inc" #include "TestFS.h" +#include "llvm/ADT/None.h" +#include "llvm/ADT/Optional.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/Path.h" +#include "llvm/Support/SourceMgr.h" #include "gmock/gmock.h" #include "gtest/gtest.h" #include @@ -20,6 +24,8 @@ namespace clang { namespace clangd { namespace config { namespace { +using ::testing::AllOf; +using ::testing::Contains; using ::testing::ElementsAre; using ::testing::IsEmpty; using ::testing::SizeIs; @@ -176,6 +182,134 @@ TEST_F(ConfigCompileTests, PathSpecMatch) { ASSERT_THAT(Diags.Diagnostics, IsEmpty()); } } + +TEST_F(ConfigCompileTests, Tidy) { + Frag.ClangTidy.Add.emplace_back("bugprone-use-after-move"); + Frag.ClangTidy.Add.emplace_back("llvm-*"); + Frag.ClangTidy.Remove.emplace_back("llvm-include-order"); + Frag.ClangTidy.Remove.emplace_back("readability-*"); + Frag.ClangTidy.CheckOptions.emplace_back( + std::make_pair(std::string("StrictMode"), std::string("true"))); + Frag.ClangTidy.CheckOptions.emplace_back(std::make_pair( + std::string("example-check.ExampleOption"), std::string("0"))); + EXPECT_TRUE(compileAndApply()); + EXPECT_EQ( + Conf.ClangTidy.Checks, + "bugprone-use-after-move,llvm-*,-llvm-include-order,-readability-*"); + EXPECT_EQ(Conf.ClangTidy.CheckOptions.size(), 2U); + EXPECT_EQ(Conf.ClangTidy.CheckOptions.lookup("StrictMode"), "true"); + EXPECT_EQ(Conf.ClangTidy.CheckOptions.lookup("example-check.ExampleOption"), + "0"); +} + +TEST_F(ConfigCompileTests, ExternalBlockWarnOnMultipleSource) { + Fragment::IndexBlock::ExternalBlock External; + External.File.emplace(""); + External.Server.emplace(""); + Frag.Index.External = std::move(External); + compileAndApply(); + llvm::StringLiteral ExpectedDiag = +#ifdef CLANGD_ENABLE_REMOTE + "Exactly one of File or Server must be set."; +#else + "Clangd isn't compiled with remote index support, ignoring Server."; +#endif + EXPECT_THAT(Diags.Diagnostics, + Contains(AllOf(DiagMessage(ExpectedDiag), + DiagKind(llvm::SourceMgr::DK_Error)))); +} + +TEST_F(ConfigCompileTests, ExternalBlockErrOnNoSource) { + Frag.Index.External.emplace(Fragment::IndexBlock::ExternalBlock{}); + compileAndApply(); + EXPECT_THAT( + Diags.Diagnostics, + Contains(AllOf(DiagMessage("Exactly one of File or Server must be set."), + DiagKind(llvm::SourceMgr::DK_Error)))); +} + +TEST_F(ConfigCompileTests, ExternalBlockDisablesBackgroundIndex) { + auto BazPath = testPath("foo/bar/baz.h", llvm::sys::path::Style::posix); + Parm.Path = BazPath; + Frag.Index.Background.emplace("Build"); + Fragment::IndexBlock::ExternalBlock External; + External.File.emplace(testPath("foo")); + External.MountPoint.emplace( + testPath("foo/bar", llvm::sys::path::Style::posix)); + Frag.Index.External = std::move(External); + compileAndApply(); + EXPECT_EQ(Conf.Index.Background, Config::BackgroundPolicy::Skip); +} + +TEST_F(ConfigCompileTests, ExternalBlockMountPoint) { + auto GetFrag = [](llvm::StringRef Directory, + llvm::Optional MountPoint) { + Fragment Frag; + Frag.Source.Directory = Directory.str(); + Fragment::IndexBlock::ExternalBlock External; + External.File.emplace(testPath("foo")); + if (MountPoint) + External.MountPoint.emplace(*MountPoint); + Frag.Index.External = std::move(External); + return Frag; + }; + + auto BarPath = testPath("foo/bar.h", llvm::sys::path::Style::posix); + BarPath = llvm::sys::path::convert_to_slash(BarPath); + Parm.Path = BarPath; + // Non-absolute MountPoint without a directory raises an error. + Frag = GetFrag("", "foo"); + compileAndApply(); + ASSERT_THAT( + Diags.Diagnostics, + ElementsAre( + AllOf(DiagMessage("MountPoint must be an absolute path, because this " + "fragment is not associated with any directory."), + DiagKind(llvm::SourceMgr::DK_Error)))); + ASSERT_FALSE(Conf.Index.External); + + auto FooPath = testPath("foo/", llvm::sys::path::Style::posix); + FooPath = llvm::sys::path::convert_to_slash(FooPath); + // Ok when relative. + Frag = GetFrag(testRoot(), "foo/"); + compileAndApply(); + ASSERT_THAT(Diags.Diagnostics, IsEmpty()); + ASSERT_TRUE(Conf.Index.External); + EXPECT_THAT(Conf.Index.External->MountPoint, FooPath); + + // None defaults to ".". + Frag = GetFrag(FooPath, llvm::None); + compileAndApply(); + ASSERT_THAT(Diags.Diagnostics, IsEmpty()); + ASSERT_TRUE(Conf.Index.External); + EXPECT_THAT(Conf.Index.External->MountPoint, FooPath); + + // Without a file, external index is empty. + Parm.Path = ""; + Frag = GetFrag("", FooPath.c_str()); + compileAndApply(); + ASSERT_THAT(Diags.Diagnostics, IsEmpty()); + ASSERT_FALSE(Conf.Index.External); + + // File outside MountPoint, no index. + auto BazPath = testPath("bar/baz.h", llvm::sys::path::Style::posix); + BazPath = llvm::sys::path::convert_to_slash(BazPath); + Parm.Path = BazPath; + Frag = GetFrag("", FooPath.c_str()); + compileAndApply(); + ASSERT_THAT(Diags.Diagnostics, IsEmpty()); + ASSERT_FALSE(Conf.Index.External); + + // File under MountPoint, index should be set. + BazPath = testPath("foo/baz.h", llvm::sys::path::Style::posix); + BazPath = llvm::sys::path::convert_to_slash(BazPath); + Parm.Path = BazPath; + Frag = GetFrag("", FooPath.c_str()); + compileAndApply(); + ASSERT_THAT(Diags.Diagnostics, IsEmpty()); + ASSERT_TRUE(Conf.Index.External); + EXPECT_THAT(Conf.Index.External->MountPoint, FooPath); +} } // namespace } // namespace config } // namespace clangd diff --git a/clang-tools-extra/clangd/unittests/ConfigProviderTests.cpp b/clang-tools-extra/clangd/unittests/ConfigProviderTests.cpp index 29ab8f3b36061..d6af5856cc49c 100644 --- a/clang-tools-extra/clangd/unittests/ConfigProviderTests.cpp +++ b/clang-tools-extra/clangd/unittests/ConfigProviderTests.cpp @@ -151,6 +151,7 @@ TEST(ProviderTest, FromAncestorRelativeYAMLFiles) { EXPECT_THAT(getAddedArgs(Cfg), ElementsAre("bar", "baz")); } +// FIXME: delete this test, it's covered by FileCacheTests. TEST(ProviderTest, Staleness) { MockFS FS; diff --git a/clang-tools-extra/clangd/unittests/ConfigYAMLTests.cpp b/clang-tools-extra/clangd/unittests/ConfigYAMLTests.cpp index 27b1c0cfc56dd..1da0f3a1cc716 100644 --- a/clang-tools-extra/clangd/unittests/ConfigYAMLTests.cpp +++ b/clang-tools-extra/clangd/unittests/ConfigYAMLTests.cpp @@ -10,6 +10,7 @@ #include "ConfigFragment.h" #include "ConfigTesting.h" #include "Protocol.h" +#include "llvm/ADT/StringRef.h" #include "llvm/Support/SMLoc.h" #include "llvm/Support/ScopedPrinter.h" #include "llvm/Support/SourceMgr.h" @@ -35,6 +36,14 @@ MATCHER_P(Val, Value, "") { return false; } +MATCHER_P2(PairVal, Value1, Value2, "") { + if (*arg.first == Value1 && *arg.second == Value2) + return true; + *result_listener << "values are [" << *arg.first << ", " << *arg.second + << "]"; + return false; +} + TEST(ParseYAML, SyntacticForms) { CapturedDiags Diags; const char *YAML = R"yaml( @@ -50,10 +59,15 @@ CompileFlags: { Add: [foo, bar] } --- Index: Background: Skip +--- +ClangTidy: + CheckOptions: + IgnoreMacros: true + example-check.ExampleOption: 0 )yaml"; auto Results = Fragment::parseYAML(YAML, "config.yaml", Diags.callback()); EXPECT_THAT(Diags.Diagnostics, IsEmpty()); - ASSERT_EQ(Results.size(), 3u); + ASSERT_EQ(Results.size(), 4u); EXPECT_FALSE(Results[0].If.HasUnrecognizedCondition); EXPECT_THAT(Results[0].If.PathMatch, ElementsAre(Val("abc"))); EXPECT_THAT(Results[0].CompileFlags.Add, ElementsAre(Val("foo"), Val("bar"))); @@ -62,6 +76,9 @@ CompileFlags: { Add: [foo, bar] } ASSERT_TRUE(Results[2].Index.Background); EXPECT_EQ("Skip", *Results[2].Index.Background.getValue()); + EXPECT_THAT(Results[3].ClangTidy.CheckOptions, + ElementsAre(PairVal("IgnoreMacros", "true"), + PairVal("example-check.ExampleOption", "0"))); } TEST(ParseYAML, Locations) { @@ -84,11 +101,11 @@ TEST(ParseYAML, Diagnostics) { CapturedDiags Diags; Annotations YAML(R"yaml( If: - [[UnknownCondition]]: "foo" + $unknown[[UnknownCondition]]: "foo" CompileFlags: Add: 'first' --- -CompileFlags: {^ +CompileFlags: {$unexpected^ )yaml"); auto Results = Fragment::parseYAML(YAML.code(), "config.yaml", Diags.callback()); @@ -97,11 +114,13 @@ CompileFlags: {^ Diags.Diagnostics, ElementsAre(AllOf(DiagMessage("Unknown If key UnknownCondition"), DiagKind(llvm::SourceMgr::DK_Warning), - DiagPos(YAML.range().start), DiagRange(YAML.range())), + DiagPos(YAML.range("unknown").start), + DiagRange(YAML.range("unknown"))), AllOf(DiagMessage("Unexpected token. Expected Key, Flow " "Entry, or Flow Mapping End."), DiagKind(llvm::SourceMgr::DK_Error), - DiagPos(YAML.point()), DiagRange(llvm::None)))); + DiagPos(YAML.point("unexpected")), + DiagRange(llvm::None)))); ASSERT_EQ(Results.size(), 1u); // invalid fragment discarded. EXPECT_THAT(Results.front().CompileFlags.Add, ElementsAre(Val("first"))); @@ -124,6 +143,25 @@ horrible ASSERT_THAT(Results, IsEmpty()); } +TEST(ParseYAML, ExternalBlock) { + CapturedDiags Diags; + Annotations YAML(R"yaml( +Index: + External: + File: "foo" + Server: ^"bar" + MountPoint: "baz" + )yaml"); + auto Results = + Fragment::parseYAML(YAML.code(), "config.yaml", Diags.callback()); + ASSERT_EQ(Results.size(), 1u); + ASSERT_TRUE(Results[0].Index.External); + EXPECT_THAT(*Results[0].Index.External.getValue()->File, Val("foo")); + EXPECT_THAT(*Results[0].Index.External.getValue()->MountPoint, Val("baz")); + ASSERT_THAT(Diags.Diagnostics, IsEmpty()); + EXPECT_THAT(*Results[0].Index.External.getValue()->Server, Val("bar")); +} + } // namespace } // namespace config } // namespace clangd diff --git a/clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp b/clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp index 8f84d0ba4806c..ba7029e54dbb4 100644 --- a/clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp +++ b/clang-tools-extra/clangd/unittests/DiagnosticsTests.cpp @@ -14,6 +14,7 @@ #include "TestFS.h" #include "TestIndex.h" #include "TestTU.h" +#include "TidyProvider.h" #include "index/MemIndex.h" #include "support/Path.h" #include "clang/Basic/Diagnostic.h" @@ -129,7 +130,7 @@ o]](); } )cpp"); auto TU = TestTU::withCode(Test.code()); - TU.ClangTidyChecks = "-*,google-explicit-constructor"; + TU.ClangTidyProvider = addTidyChecks("google-explicit-constructor"); EXPECT_THAT( TU.build().getDiagnostics(), ElementsAre( @@ -201,8 +202,8 @@ TEST(DiagnosticsTest, DeduplicatedClangTidyDiagnostics) { auto TU = TestTU::withCode(Test.code()); // Enable alias clang-tidy checks, these check emits the same diagnostics // (except the check name). - TU.ClangTidyChecks = "-*, readability-uppercase-literal-suffix, " - "hicpp-uppercase-literal-suffix"; + TU.ClangTidyProvider = addTidyChecks("readability-uppercase-literal-suffix," + "hicpp-uppercase-literal-suffix"); // Verify that we filter out the duplicated diagnostic message. EXPECT_THAT( TU.build().getDiagnostics(), @@ -245,9 +246,10 @@ TEST(DiagnosticsTest, ClangTidy) { )cpp"); auto TU = TestTU::withCode(Test.code()); TU.HeaderFilename = "assert.h"; // Suppress "not found" error. - TU.ClangTidyChecks = - "-*, bugprone-sizeof-expression, bugprone-macro-repeated-side-effects, " - "modernize-deprecated-headers, modernize-use-trailing-return-type"; + TU.ClangTidyProvider = addTidyChecks("bugprone-sizeof-expression," + "bugprone-macro-repeated-side-effects," + "modernize-deprecated-headers," + "modernize-use-trailing-return-type"); EXPECT_THAT( TU.build().getDiagnostics(), UnorderedElementsAre( @@ -289,7 +291,7 @@ TEST(DiagnosticsTest, ClangTidyEOF) { auto TU = TestTU::withCode(Test.code()); TU.ExtraArgs = {"-isystem."}; TU.AdditionalFiles["a.h"] = TU.AdditionalFiles["b.h"] = ""; - TU.ClangTidyChecks = "-*, llvm-include-order"; + TU.ClangTidyProvider = addTidyChecks("llvm-include-order"); EXPECT_THAT( TU.build().getDiagnostics(), Contains(AllOf(Diag(Test.range(), "#includes are not sorted properly"), @@ -361,7 +363,7 @@ TEST(DiagnosticTest, NoMultipleDiagnosticInFlight) { } )cpp"); TestTU TU = TestTU::withCode(Main.code()); - TU.ClangTidyChecks = "modernize-loop-convert"; + TU.ClangTidyProvider = addTidyChecks("modernize-loop-convert"); EXPECT_THAT( TU.build().getDiagnostics(), UnorderedElementsAre(::testing::AllOf( @@ -384,7 +386,7 @@ TEST(DiagnosticTest, ClangTidySuppressionComment) { } )cpp"); TestTU TU = TestTU::withCode(Main.code()); - TU.ClangTidyChecks = "bugprone-integer-division"; + TU.ClangTidyProvider = addTidyChecks("bugprone-integer-division"); EXPECT_THAT( TU.build().getDiagnostics(), UnorderedElementsAre(::testing::AllOf( @@ -401,8 +403,8 @@ TEST(DiagnosticTest, ClangTidyWarningAsError) { } )cpp"); TestTU TU = TestTU::withCode(Main.code()); - TU.ClangTidyChecks = "bugprone-integer-division"; - TU.ClangTidyWarningsAsErrors = "bugprone-integer-division"; + TU.ClangTidyProvider = + addTidyChecks("bugprone-integer-division", "bugprone-integer-division"); EXPECT_THAT( TU.build().getDiagnostics(), UnorderedElementsAre(::testing::AllOf( @@ -452,8 +454,8 @@ TEST(DiagnosticTest, ClangTidySuppressionCommentTrumpsWarningAsError) { } )cpp"); TestTU TU = TestTU::withCode(Main.code()); - TU.ClangTidyChecks = "bugprone-integer-division"; - TU.ClangTidyWarningsAsErrors = "bugprone-integer-division"; + TU.ClangTidyProvider = + addTidyChecks("bugprone-integer-division", "bugprone-integer-division"); EXPECT_THAT(TU.build().getDiagnostics(), UnorderedElementsAre()); } @@ -468,7 +470,7 @@ TEST(DiagnosticTest, ClangTidyNoLiteralDataInMacroToken) { } )cpp"); TestTU TU = TestTU::withCode(Main.code()); - TU.ClangTidyChecks = "-*,bugprone-bad-signal-to-kill-thread"; + TU.ClangTidyProvider = addTidyChecks("bugprone-bad-signal-to-kill-thread"); EXPECT_THAT(TU.build().getDiagnostics(), UnorderedElementsAre()); // no-crash } diff --git a/clang-tools-extra/clangd/unittests/DumpASTTests.cpp b/clang-tools-extra/clangd/unittests/DumpASTTests.cpp index 4b524820cb4cb..23c673284f660 100644 --- a/clang-tools-extra/clangd/unittests/DumpASTTests.cpp +++ b/clang-tools-extra/clangd/unittests/DumpASTTests.cpp @@ -76,29 +76,32 @@ declaration: Namespace - root type: Record - S )"}, {R"cpp( -template int root() { - (void)root(); +namespace root { +template int tmpl() { + (void)tmpl(); return T::value; +} } )cpp", R"( -declaration: FunctionTemplate - root - declaration: TemplateTypeParm - T - declaration: Function - root - type: FunctionProto - type: Builtin - int - statement: Compound - expression: CStyleCast - ToVoid - type: Builtin - void - expression: Call - expression: ImplicitCast - FunctionToPointerDecay - expression: DeclRef - root - template argument: Type - type: Builtin - unsigned int - statement: Return - expression: DependentScopeDeclRef - value - specifier: TypeSpec - type: TemplateTypeParm - T +declaration: Namespace - root + declaration: FunctionTemplate - tmpl + declaration: TemplateTypeParm - T + declaration: Function - tmpl + type: FunctionProto + type: Builtin - int + statement: Compound + expression: CStyleCast - ToVoid + type: Builtin - void + expression: Call + expression: ImplicitCast - FunctionToPointerDecay + expression: DeclRef - tmpl + template argument: Type + type: Builtin - unsigned int + statement: Return + expression: DependentScopeDeclRef - value + specifier: TypeSpec + type: TemplateTypeParm - T )"}, {R"cpp( struct Foo { char operator+(int); }; @@ -116,10 +119,28 @@ declaration: Var - root type: Record - Foo expression: IntegerLiteral - 42 )"}, + {R"cpp( +struct Bar { + int x; + int root() const { + return x; + } +}; + )cpp", + R"( +declaration: CXXMethod - root + type: FunctionProto + type: Builtin - int + statement: Compound + statement: Return + expression: ImplicitCast - LValueToRValue + expression: Member - x + expression: CXXThis - const, implicit + )"}, }; for (const auto &Case : Cases) { ParsedAST AST = TestTU::withCode(Case.first).build(); - auto Node = dumpAST(DynTypedNode::create(findDecl(AST, "root")), + auto Node = dumpAST(DynTypedNode::create(findUnqualifiedDecl(AST, "root")), AST.getTokens(), AST.getASTContext()); EXPECT_EQ(llvm::StringRef(Case.second).trim(), llvm::StringRef(llvm::to_string(Node)).trim()); diff --git a/clang-tools-extra/clangd/unittests/ParsedASTTests.cpp b/clang-tools-extra/clangd/unittests/ParsedASTTests.cpp index 3fd7ded2b356b..b3321f5a64792 100644 --- a/clang-tools-extra/clangd/unittests/ParsedASTTests.cpp +++ b/clang-tools-extra/clangd/unittests/ParsedASTTests.cpp @@ -24,6 +24,7 @@ #include "SourceCode.h" #include "TestFS.h" #include "TestTU.h" +#include "TidyProvider.h" #include "clang/AST/DeclTemplate.h" #include "clang/Basic/SourceLocation.h" #include "clang/Basic/SourceManager.h" @@ -250,7 +251,7 @@ TEST(ParsedASTTest, NoCrashOnTokensWithTidyCheck) { TestTU TU; // this check runs the preprocessor, we need to make sure it does not break // our recording logic. - TU.ClangTidyChecks = "modernize-use-trailing-return-type"; + TU.ClangTidyProvider = addTidyChecks("modernize-use-trailing-return-type"); TU.Code = "inline int foo() {}"; auto AST = TU.build(); @@ -406,7 +407,7 @@ TEST(ParsedASTTest, ReplayPreambleForTidyCheckers) { "replay-preamble-module", ""); TestTU TU; // This check records inclusion directives replayed by clangd. - TU.ClangTidyChecks = "replay-preamble-check"; + TU.ClangTidyProvider = addTidyChecks("replay-preamble-check"); llvm::Annotations Test(R"cpp( $hash^#$include[[import]] $filebegin^"$filerange[[bar.h]]" $hash^#$include[[include_next]] $filebegin^"$filerange[[baz.h]]" diff --git a/clang-tools-extra/clangd/unittests/ProjectAwareIndexTests.cpp b/clang-tools-extra/clangd/unittests/ProjectAwareIndexTests.cpp new file mode 100644 index 0000000000000..0d14d2ed5d542 --- /dev/null +++ b/clang-tools-extra/clangd/unittests/ProjectAwareIndexTests.cpp @@ -0,0 +1,86 @@ +//===-- ProjectAwareIndexTests.cpp -------------------*- C++ -*-----------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Config.h" +#include "TestIndex.h" +#include "index/Index.h" +#include "index/MemIndex.h" +#include "index/ProjectAware.h" +#include "index/Ref.h" +#include "index/Relation.h" +#include "support/Context.h" +#include "support/Threading.h" +#include "llvm/ADT/StringRef.h" +#include "gmock/gmock.h" +#include "gtest/gtest.h" +#include +#include + +namespace clang { +namespace clangd { +using testing::ElementsAre; +using testing::IsEmpty; + +std::unique_ptr createIndex() { + SymbolSlab::Builder Builder; + Builder.insert(symbol("1")); + return MemIndex::build(std::move(Builder).build(), RefSlab(), RelationSlab()); +} + +TEST(ProjectAware, Test) { + IndexFactory Gen = [](const Config::ExternalIndexSpec &, AsyncTaskRunner &) { + return createIndex(); + }; + + auto Idx = createProjectAwareIndex(std::move(Gen)); + FuzzyFindRequest Req; + Req.Query = "1"; + Req.AnyScope = true; + + EXPECT_THAT(match(*Idx, Req), IsEmpty()); + + Config C; + C.Index.External.emplace(); + C.Index.External->Location = "test"; + WithContextValue With(Config::Key, std::move(C)); + EXPECT_THAT(match(*Idx, Req), ElementsAre("1")); + return; +} + +TEST(ProjectAware, CreatedOnce) { + unsigned InvocationCount = 0; + IndexFactory Gen = [&](const Config::ExternalIndexSpec &, AsyncTaskRunner &) { + ++InvocationCount; + return createIndex(); + }; + + auto Idx = createProjectAwareIndex(std::move(Gen)); + // No invocation at start. + EXPECT_EQ(InvocationCount, 0U); + FuzzyFindRequest Req; + Req.Query = "1"; + Req.AnyScope = true; + + // Cannot invoke without proper config. + match(*Idx, Req); + EXPECT_EQ(InvocationCount, 0U); + + Config C; + C.Index.External.emplace(); + C.Index.External->Location = "test"; + WithContextValue With(Config::Key, std::move(C)); + match(*Idx, Req); + // Now it should be created. + EXPECT_EQ(InvocationCount, 1U); + match(*Idx, Req); + // It is cached afterwards. + EXPECT_EQ(InvocationCount, 1U); + return; +} +} // namespace clangd +} // namespace clang diff --git a/clang-tools-extra/clangd/unittests/RenameTests.cpp b/clang-tools-extra/clangd/unittests/RenameTests.cpp index 68a6a666a895c..2382dba19659b 100644 --- a/clang-tools-extra/clangd/unittests/RenameTests.cpp +++ b/clang-tools-extra/clangd/unittests/RenameTests.cpp @@ -540,6 +540,94 @@ TEST(RenameTest, WithinFileRename) { } )cpp", + // Fields in classes & partial and full specialiations. + R"cpp( + template + struct Foo { + T [[Vari^able]] = 42; + }; + + void foo() { + Foo f; + f.[[Varia^ble]] = 9000; + } + )cpp", + R"cpp( + template + struct Foo { + T Variable[42]; + U Another; + + void bar() {} + }; + + template + struct Foo { + T [[Var^iable]]; + void bar() { ++[[Var^iable]]; } + }; + + void foo() { + Foo f; + f.[[Var^iable]] = 9000; + } + )cpp", + R"cpp( + template + struct Foo { + T Variable[42]; + U Another; + + void bar() {} + }; + + template + struct Foo { + T Variable; + void bar() { ++Variable; } + }; + + template<> + struct Foo { + unsigned [[Var^iable]]; + void bar() { ++[[Var^iable]]; } + }; + + void foo() { + Foo f; + f.[[Var^iable]] = 9000; + } + )cpp", + // Static fields. + R"cpp( + struct Foo { + static int [[Var^iable]]; + }; + + int Foo::[[Var^iable]] = 42; + + void foo() { + int LocalInt = Foo::[[Var^iable]]; + } + )cpp", + R"cpp( + template + struct Foo { + static T [[Var^iable]]; + }; + + template <> + int Foo::[[Var^iable]] = 42; + + template <> + bool Foo::[[Var^iable]] = true; + + void foo() { + int LocalInt = Foo::[[Var^iable]]; + bool LocalBool = Foo::[[Var^iable]]; + } + )cpp", + // Template parameters. R"cpp( template @@ -1016,6 +1104,7 @@ TEST(RenameTest, PrepareRename) { auto ServerOpts = ClangdServer::optsForTest(); ServerOpts.BuildDynamicSymbolIndex = true; + trace::TestTracer Tracer; MockCompilationDatabase CDB; ClangdServer Server(CDB, FS, ServerOpts); runAddDocument(Server, FooHPath, FooH.code()); @@ -1038,6 +1127,8 @@ TEST(RenameTest, PrepareRename) { EXPECT_FALSE(Results); EXPECT_THAT(llvm::toString(Results.takeError()), testing::HasSubstr("keyword")); + EXPECT_THAT(Tracer.takeMetric("rename_name_invalid", "Keywords"), + ElementsAre(1)); // Single-file rename on global symbols, we should report an error. Results = runPrepareRename(Server, FooCCPath, FooCC.point(), diff --git a/clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp b/clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp index 232be6a783803..79f3af264c0f7 100644 --- a/clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp +++ b/clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp @@ -623,18 +623,23 @@ TEST(SemanticHighlighting, GetsCorrectTokens) { // Code after the preamble. // Code inside inactive blocks does not get regular highlightings // because it's not part of the AST. -$InactiveCode[[#ifdef test]] + #define $Macro[[test2]] +$InactiveCode[[#if defined(test)]] $InactiveCode[[int Inactive2;]] +$InactiveCode[[#elif defined(test2)]] + int $Variable[[Active1]]; +$InactiveCode[[#else]] +$InactiveCode[[int Inactive3;]] $InactiveCode[[#endif]] #ifndef $Macro[[test]] - int $Variable[[Active1]]; + int $Variable[[Active2]]; #endif $InactiveCode[[#ifdef test]] -$InactiveCode[[int Inactive3;]] +$InactiveCode[[int Inactive4;]] $InactiveCode[[#else]] - int $Variable[[Active2]]; + int $Variable[[Active3]]; #endif )cpp", // Argument to 'sizeof...' diff --git a/clang-tools-extra/clangd/unittests/TestTU.cpp b/clang-tools-extra/clangd/unittests/TestTU.cpp index d0f011ef56497..f487cf717f043 100644 --- a/clang-tools-extra/clangd/unittests/TestTU.cpp +++ b/clang-tools-extra/clangd/unittests/TestTU.cpp @@ -59,8 +59,8 @@ ParseInputs TestTU::inputs(MockFS &FS) const { FS.OverlayRealFileSystemForModules = true; Inputs.TFS = &FS; Inputs.Opts = ParseOptions(); - Inputs.Opts.ClangTidyOpts.Checks = ClangTidyChecks; - Inputs.Opts.ClangTidyOpts.WarningsAsErrors = ClangTidyWarningsAsErrors; + if (ClangTidyProvider) + Inputs.ClangTidyProvider = ClangTidyProvider; Inputs.Index = ExternalIndex; if (Inputs.Index) Inputs.Opts.SuggestMissingIncludes = true; @@ -156,7 +156,8 @@ RefSlab TestTU::headerRefs() const { std::unique_ptr TestTU::index() const { auto AST = build(); - auto Idx = std::make_unique(/*UseDex=*/true); + auto Idx = std::make_unique(/*UseDex=*/true, + /*CollectMainFileRefs=*/true); Idx->updatePreamble(testPath(Filename), /*Version=*/"null", AST.getASTContext(), AST.getPreprocessorPtr(), AST.getCanonicalIncludes()); diff --git a/clang-tools-extra/clangd/unittests/TestTU.h b/clang-tools-extra/clangd/unittests/TestTU.h index f383e693408c3..18b490332b1a7 100644 --- a/clang-tools-extra/clangd/unittests/TestTU.h +++ b/clang-tools-extra/clangd/unittests/TestTU.h @@ -17,6 +17,7 @@ #ifndef LLVM_CLANG_TOOLS_EXTRA_UNITTESTS_CLANGD_TESTTU_H #define LLVM_CLANG_TOOLS_EXTRA_UNITTESTS_CLANGD_TESTTU_H +#include "../TidyProvider.h" #include "Compiler.h" #include "ParsedAST.h" #include "TestFS.h" @@ -58,8 +59,7 @@ struct TestTU { // Extra arguments for the compiler invocation. std::vector ExtraArgs; - llvm::Optional ClangTidyChecks; - llvm::Optional ClangTidyWarningsAsErrors; + TidyProvider ClangTidyProvider = {}; // Index to use when building AST. const SymbolIndex *ExternalIndex = nullptr; diff --git a/clang-tools-extra/clangd/unittests/TweakTests.cpp b/clang-tools-extra/clangd/unittests/TweakTests.cpp index 98d797aacd8f5..eefc50d754e2a 100644 --- a/clang-tools-extra/clangd/unittests/TweakTests.cpp +++ b/clang-tools-extra/clangd/unittests/TweakTests.cpp @@ -2520,6 +2520,9 @@ class cc { EXPECT_UNAVAILABLE(Header + "void fun() { ::ban::fo^o(); }"); EXPECT_AVAILABLE(Header + "void fun() { banana::fo^o(); }"); + // Do not offer code action on typo-corrections. + EXPECT_UNAVAILABLE(Header + "/*error-ok*/c^c C;"); + // Check that we do not trigger in header files. FileName = "test.h"; ExtraArgs.push_back("-xc++-header"); // .h file is treated a C by default. @@ -2793,7 +2796,106 @@ using one::two::ff;using one::two::ee; void fun() { ff(); -})cpp"}}; +})cpp"}, + // using alias; insert using for the spelled name. + {R"cpp( +#include "test.hpp" + +void fun() { + one::u^u u; +})cpp", + R"cpp( +#include "test.hpp" + +using one::uu; + +void fun() { + uu u; +})cpp"}, + // using namespace. + {R"cpp( +#include "test.hpp" +using namespace one; +namespace { +two::c^c C; +})cpp", + R"cpp( +#include "test.hpp" +using namespace one; +namespace {using two::cc; + +cc C; +})cpp"}, + // Type defined in main file, make sure using is after that. + {R"cpp( +namespace xx { + struct yy {}; +} + +x^x::yy X; +)cpp", + R"cpp( +namespace xx { + struct yy {}; +} + +using xx::yy; + +yy X; +)cpp"}, + // Type defined in main file via "using", insert after that. + {R"cpp( +#include "test.hpp" + +namespace xx { + using yy = one::two::cc; +} + +x^x::yy X; +)cpp", + R"cpp( +#include "test.hpp" + +namespace xx { + using yy = one::two::cc; +} + +using xx::yy; + +yy X; +)cpp"}, + // Using must come after function definition. + {R"cpp( +namespace xx { + void yy(); +} + +void fun() { + x^x::yy(); +} +)cpp", + R"cpp( +namespace xx { + void yy(); +} + +using xx::yy; + +void fun() { + yy(); +} +)cpp"}, + // Existing using with non-namespace part. + {R"cpp( +#include "test.hpp" +using one::two::ee::ee_one; +one::t^wo::cc c; +)cpp", + R"cpp( +#include "test.hpp" +using one::two::cc;using one::two::ee::ee_one; +cc c; +)cpp"}}; llvm::StringMap EditedFiles; for (const auto &Case : Cases) { for (const auto &SubCase : expandCases(Case.TestSource)) { @@ -2801,7 +2903,7 @@ void fun() { namespace one { void oo() {} namespace two { -enum ee {}; +enum ee {ee_one}; void ff() {} class cc { public: @@ -2809,6 +2911,7 @@ class cc { static void mm() {} }; } +using uu = two::cc; })cpp"; EXPECT_EQ(apply(SubCase, &EditedFiles), Case.ExpectedSource); } @@ -2992,6 +3095,12 @@ TEST_F(PopulateSwitchTest, Test) { R""(enum Enum {A,B,b=B}; ^switch (A) {case A:case B:break;})"", "unavailable", }, + { + // Enum is dependent type + File, + R""(template void f() {enum Enum {A}; ^switch (A) {}})"", + "unavailable", + }, }; for (const auto &Case : Cases) { diff --git a/clang-tools-extra/clangd/unittests/TypeHierarchyTests.cpp b/clang-tools-extra/clangd/unittests/TypeHierarchyTests.cpp index 64831724d1be6..08f936ce8b553 100644 --- a/clang-tools-extra/clangd/unittests/TypeHierarchyTests.cpp +++ b/clang-tools-extra/clangd/unittests/TypeHierarchyTests.cpp @@ -30,6 +30,7 @@ namespace { using ::testing::AllOf; using ::testing::ElementsAre; using ::testing::Field; +using ::testing::IsEmpty; using ::testing::Matcher; using ::testing::UnorderedElementsAre; @@ -318,6 +319,18 @@ struct Child3 : T {}; EXPECT_THAT(typeParents(Child3), ElementsAre()); } +TEST(TypeParents, IncompleteClass) { + Annotations Source(R"cpp( + class Incomplete; + )cpp"); + TestTU TU = TestTU::withCode(Source.code()); + auto AST = TU.build(); + + const CXXRecordDecl *Incomplete = + dyn_cast(&findDecl(AST, "Incomplete")); + EXPECT_THAT(typeParents(Incomplete), IsEmpty()); +} + // Parts of getTypeHierarchy() are tested in more detail by the // FindRecordTypeAt.* and TypeParents.* tests above. This test exercises the // entire operation. diff --git a/clang-tools-extra/clangd/unittests/support/FileCacheTests.cpp b/clang-tools-extra/clangd/unittests/support/FileCacheTests.cpp new file mode 100644 index 0000000000000..1f554806def08 --- /dev/null +++ b/clang-tools-extra/clangd/unittests/support/FileCacheTests.cpp @@ -0,0 +1,83 @@ +//===-- FileCacheTests.cpp ------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "support/FileCache.h" + +#include "TestFS.h" +#include "gmock/gmock.h" +#include "gtest/gtest.h" +#include +#include + +namespace clang { +namespace clangd { +namespace config { +namespace { + +class TestCache : public FileCache { + MockFS FS; + mutable std::string Value; + +public: + TestCache() : FileCache(testPath("foo.cc")) {} + + void setContents(const char *C) { + if (C) + FS.Files[testPath("foo.cc")] = C; + else + FS.Files.erase(testPath("foo.cc")); + } + + std::string get(std::chrono::steady_clock::time_point FreshTime, + bool ExpectParse) const { + bool GotParse = false; + bool GotRead; + std::string Result; + read( + FS, FreshTime, + [&](llvm::Optional Data) { + GotParse = true; + Value = Data.getValueOr("").str(); + }, + [&]() { + GotRead = true; + Result = Value; + }); + EXPECT_EQ(GotParse, ExpectParse); + EXPECT_TRUE(GotRead); + return Result; + } +}; + +TEST(FileCacheTest, Invalidation) { + TestCache C; + + auto StaleOK = std::chrono::steady_clock::now(); + auto MustBeFresh = StaleOK + std::chrono::hours(1); + + C.setContents("a"); + EXPECT_EQ("a", C.get(StaleOK, /*ExpectParse=*/true)) << "Parsed first time"; + EXPECT_EQ("a", C.get(StaleOK, /*ExpectParse=*/false)) << "Cached (time)"; + EXPECT_EQ("a", C.get(MustBeFresh, /*ExpectParse=*/false)) << "Cached (stat)"; + C.setContents("bb"); + EXPECT_EQ("a", C.get(StaleOK, /*ExpectParse=*/false)) << "Cached (time)"; + EXPECT_EQ("bb", C.get(MustBeFresh, /*ExpectParse=*/true)) << "Size changed"; + EXPECT_EQ("bb", C.get(MustBeFresh, /*ExpectParse=*/true)) << "Cached (stat)"; + C.setContents(nullptr); + EXPECT_EQ("bb", C.get(StaleOK, /*ExpectParse=*/false)) << "Cached (time)"; + EXPECT_EQ("", C.get(MustBeFresh, /*ExpectParse=*/true)) << "Stat failed"; + EXPECT_EQ("", C.get(MustBeFresh, /*ExpectParse=*/false)) << "Cached (404)"; + C.setContents("bb"); // Match the previous stat values! + EXPECT_EQ("", C.get(StaleOK, /*ExpectParse=*/false)) << "Cached (time)"; + EXPECT_EQ("bb", C.get(MustBeFresh, /*ExpectParse=*/true)) << "Size changed"; +} + +} // namespace +} // namespace config +} // namespace clangd +} // namespace clang diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 5e78de2b0edc0..46bb36c271d31 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -57,7 +57,7 @@ The improvements are... Improvements to clang-query --------------------------- -The improvements are... +- The IgnoreImplicitCastsAndParentheses traversal mode has been removed. Improvements to clang-rename ---------------------------- @@ -149,6 +149,9 @@ Changes in existing checks Added support for specifying the style of scoped ``enum`` constants. If unspecified, will fall back to the style for regular ``enum`` constants. + Added an option `IgnoredRegexp` per identifier type to suppress identifier + naming checks for names matching a regular expression. + - Removed `google-runtime-references` check because the rule it checks does not exist in the Google Style Guide anymore. diff --git a/clang-tools-extra/docs/clang-tidy/checks/readability-identifier-naming.rst b/clang-tools-extra/docs/clang-tidy/checks/readability-identifier-naming.rst index 036103e7e80e6..68c0abfcbdf61 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/readability-identifier-naming.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/readability-identifier-naming.rst @@ -35,60 +35,60 @@ Options The following options are describe below: - - :option:`AbstractClassCase`, :option:`AbstractClassPrefix`, :option:`AbstractClassSuffix` + - :option:`AbstractClassCase`, :option:`AbstractClassPrefix`, :option:`AbstractClassSuffix`, :option:`AbstractClassIgnoredRegexp` - :option:`AggressiveDependentMemberLookup` - - :option:`ClassCase`, :option:`ClassPrefix`, :option:`ClassSuffix` - - :option:`ClassConstantCase`, :option:`ClassConstantPrefix`, :option:`ClassConstantSuffix` - - :option:`ClassMemberCase`, :option:`ClassMemberPrefix`, :option:`ClassMemberSuffix` - - :option:`ClassMethodCase`, :option:`ClassMethodPrefix`, :option:`ClassMethodSuffix` - - :option:`ConstantCase`, :option:`ConstantPrefix`, :option:`ConstantSuffix` - - :option:`ConstantMemberCase`, :option:`ConstantMemberPrefix`, :option:`ConstantMemberSuffix` - - :option:`ConstantParameterCase`, :option:`ConstantParameterPrefix`, :option:`ConstantParameterSuffix` - - :option:`ConstantPointerParameterCase`, :option:`ConstantPointerParameterPrefix`, :option:`ConstantPointerParameterSuffix` - - :option:`ConstexprFunctionCase`, :option:`ConstexprFunctionPrefix`, :option:`ConstexprFunctionSuffix` - - :option:`ConstexprMethodCase`, :option:`ConstexprMethodPrefix`, :option:`ConstexprMethodSuffix` - - :option:`ConstexprVariableCase`, :option:`ConstexprVariablePrefix`, :option:`ConstexprVariableSuffix` - - :option:`EnumCase`, :option:`EnumPrefix`, :option:`EnumSuffix` - - :option:`EnumConstantCase`, :option:`EnumConstantPrefix`, :option:`EnumConstantSuffix` - - :option:`FunctionCase`, :option:`FunctionPrefix`, :option:`FunctionSuffix` + - :option:`ClassCase`, :option:`ClassPrefix`, :option:`ClassSuffix`, :option:`ClassIgnoredRegexp` + - :option:`ClassConstantCase`, :option:`ClassConstantPrefix`, :option:`ClassConstantSuffix`, :option:`ClassConstantIgnoredRegexp` + - :option:`ClassMemberCase`, :option:`ClassMemberPrefix`, :option:`ClassMemberSuffix`, :option:`ClassMemberIgnoredRegexp` + - :option:`ClassMethodCase`, :option:`ClassMethodPrefix`, :option:`ClassMethodSuffix`, :option:`ClassMethodIgnoredRegexp` + - :option:`ConstantCase`, :option:`ConstantPrefix`, :option:`ConstantSuffix`, :option:`ConstantIgnoredRegexp` + - :option:`ConstantMemberCase`, :option:`ConstantMemberPrefix`, :option:`ConstantMemberSuffix`, :option:`ConstantMemberIgnoredRegexp` + - :option:`ConstantParameterCase`, :option:`ConstantParameterPrefix`, :option:`ConstantParameterSuffix`, :option:`ConstantParameterIgnoredRegexp` + - :option:`ConstantPointerParameterCase`, :option:`ConstantPointerParameterPrefix`, :option:`ConstantPointerParameterSuffix`, :option:`ConstantPointerParameterIgnoredRegexp` + - :option:`ConstexprFunctionCase`, :option:`ConstexprFunctionPrefix`, :option:`ConstexprFunctionSuffix`, :option:`ConstexprFunctionIgnoredRegexp` + - :option:`ConstexprMethodCase`, :option:`ConstexprMethodPrefix`, :option:`ConstexprMethodSuffix`, :option:`ConstexprMethodIgnoredRegexp` + - :option:`ConstexprVariableCase`, :option:`ConstexprVariablePrefix`, :option:`ConstexprVariableSuffix`, :option:`ConstexprVariableIgnoredRegexp` + - :option:`EnumCase`, :option:`EnumPrefix`, :option:`EnumSuffix`, :option:`EnumIgnoredRegexp` + - :option:`EnumConstantCase`, :option:`EnumConstantPrefix`, :option:`EnumConstantSuffix`, :option:`EnumConstantIgnoredRegexp` + - :option:`FunctionCase`, :option:`FunctionPrefix`, :option:`FunctionSuffix`, :option:`FunctionIgnoredRegexp` - :option:`GetConfigPerFile` - - :option:`GlobalConstantCase`, :option:`GlobalConstantPrefix`, :option:`GlobalConstantSuffix` - - :option:`GlobalConstantPointerCase`, :option:`GlobalConstantPointerPrefix`, :option:`GlobalConstantPointerSuffix` - - :option:`GlobalFunctionCase`, :option:`GlobalFunctionPrefix`, :option:`GlobalFunctionSuffix` - - :option:`GlobalPointerCase`, :option:`GlobalPointerPrefix`, :option:`GlobalPointerSuffix` - - :option:`GlobalVariableCase`, :option:`GlobalVariablePrefix`, :option:`GlobalVariableSuffix` + - :option:`GlobalConstantCase`, :option:`GlobalConstantPrefix`, :option:`GlobalConstantSuffix`, :option:`GlobalConstantIgnoredRegexp` + - :option:`GlobalConstantPointerCase`, :option:`GlobalConstantPointerPrefix`, :option:`GlobalConstantPointerSuffix`, :option:`GlobalConstantPointerIgnoredRegexp` + - :option:`GlobalFunctionCase`, :option:`GlobalFunctionPrefix`, :option:`GlobalFunctionSuffix`, :option:`GlobalFunctionIgnoredRegexp` + - :option:`GlobalPointerCase`, :option:`GlobalPointerPrefix`, :option:`GlobalPointerSuffix`, :option:`GlobalPointerIgnoredRegexp` + - :option:`GlobalVariableCase`, :option:`GlobalVariablePrefix`, :option:`GlobalVariableSuffix`, :option:`GlobalVariableIgnoredRegexp` - :option:`IgnoreMainLikeFunctions` - - :option:`InlineNamespaceCase`, :option:`InlineNamespacePrefix`, :option:`InlineNamespaceSuffix` - - :option:`LocalConstantCase`, :option:`LocalConstantPrefix`, :option:`LocalConstantSuffix` - - :option:`LocalConstantPointerCase`, :option:`LocalConstantPointerPrefix`, :option:`LocalConstantPointerSuffix` - - :option:`LocalPointerCase`, :option:`LocalPointerPrefix`, :option:`LocalPointerSuffix` - - :option:`LocalVariableCase`, :option:`LocalVariablePrefix`, :option:`LocalVariableSuffix` - - :option:`MacroDefinitionCase`, :option:`MacroDefinitionPrefix`, :option:`MacroDefinitionSuffix` - - :option:`MemberCase`, :option:`MemberPrefix`, :option:`MemberSuffix` - - :option:`MethodCase`, :option:`MethodPrefix`, :option:`MethodSuffix` - - :option:`NamespaceCase`, :option:`NamespacePrefix`, :option:`NamespaceSuffix` - - :option:`ParameterCase`, :option:`ParameterPrefix`, :option:`ParameterSuffix` - - :option:`ParameterPackCase`, :option:`ParameterPackPrefix`, :option:`ParameterPackSuffix` - - :option:`PointerParameterCase`, :option:`PointerParameterPrefix`, :option:`PointerParameterSuffix` - - :option:`PrivateMemberCase`, :option:`PrivateMemberPrefix`, :option:`PrivateMemberSuffix` - - :option:`PrivateMethodCase`, :option:`PrivateMethodPrefix`, :option:`PrivateMethodSuffix` - - :option:`ProtectedMemberCase`, :option:`ProtectedMemberPrefix`, :option:`ProtectedMemberSuffix` - - :option:`ProtectedMethodCase`, :option:`ProtectedMethodPrefix`, :option:`ProtectedMethodSuffix` - - :option:`PublicMemberCase`, :option:`PublicMemberPrefix`, :option:`PublicMemberSuffix` - - :option:`PublicMethodCase`, :option:`PublicMethodPrefix`, :option:`PublicMethodSuffix` - - :option:`ScopedEnumConstantCase`, :option:`ScopedEnumConstantPrefix`, :option:`ScopedEnumConstantSuffix` - - :option:`StaticConstantCase`, :option:`StaticConstantPrefix`, :option:`StaticConstantSuffix` - - :option:`StaticVariableCase`, :option:`StaticVariablePrefix`, :option:`StaticVariableSuffix` - - :option:`StructCase`, :option:`StructPrefix`, :option:`StructSuffix` - - :option:`TemplateParameterCase`, :option:`TemplateParameterPrefix`, :option:`TemplateParameterSuffix` - - :option:`TemplateTemplateParameterCase`, :option:`TemplateTemplateParameterPrefix`, :option:`TemplateTemplateParameterSuffix` - - :option:`TypeAliasCase`, :option:`TypeAliasPrefix`, :option:`TypeAliasSuffix` - - :option:`TypedefCase`, :option:`TypedefPrefix`, :option:`TypedefSuffix` - - :option:`TypeTemplateParameterCase`, :option:`TypeTemplateParameterPrefix`, :option:`TypeTemplateParameterSuffix` - - :option:`UnionCase`, :option:`UnionPrefix`, :option:`UnionSuffix` - - :option:`ValueTemplateParameterCase`, :option:`ValueTemplateParameterPrefix`, :option:`ValueTemplateParameterSuffix` - - :option:`VariableCase`, :option:`VariablePrefix`, :option:`VariableSuffix` - - :option:`VirtualMethodCase`, :option:`VirtualMethodPrefix`, :option:`VirtualMethodSuffix` + - :option:`InlineNamespaceCase`, :option:`InlineNamespacePrefix`, :option:`InlineNamespaceSuffix`, :option:`InlineNamespaceIgnoredRegexp` + - :option:`LocalConstantCase`, :option:`LocalConstantPrefix`, :option:`LocalConstantSuffix`, :option:`LocalConstantIgnoredRegexp` + - :option:`LocalConstantPointerCase`, :option:`LocalConstantPointerPrefix`, :option:`LocalConstantPointerSuffix`, :option:`LocalConstantPointerIgnoredRegexp` + - :option:`LocalPointerCase`, :option:`LocalPointerPrefix`, :option:`LocalPointerSuffix`, :option:`LocalPointerIgnoredRegexp` + - :option:`LocalVariableCase`, :option:`LocalVariablePrefix`, :option:`LocalVariableSuffix`, :option:`LocalVariableIgnoredRegexp` + - :option:`MacroDefinitionCase`, :option:`MacroDefinitionPrefix`, :option:`MacroDefinitionSuffix`, :option:`MacroDefinitionIgnoredRegexp` + - :option:`MemberCase`, :option:`MemberPrefix`, :option:`MemberSuffix`, :option:`MemberIgnoredRegexp` + - :option:`MethodCase`, :option:`MethodPrefix`, :option:`MethodSuffix`, :option:`MethodIgnoredRegexp` + - :option:`NamespaceCase`, :option:`NamespacePrefix`, :option:`NamespaceSuffix`, :option:`NamespaceIgnoredRegexp` + - :option:`ParameterCase`, :option:`ParameterPrefix`, :option:`ParameterSuffix`, :option:`ParameterIgnoredRegexp` + - :option:`ParameterPackCase`, :option:`ParameterPackPrefix`, :option:`ParameterPackSuffix`, :option:`ParameterPackIgnoredRegexp` + - :option:`PointerParameterCase`, :option:`PointerParameterPrefix`, :option:`PointerParameterSuffix`, :option:`PointerParameterIgnoredRegexp` + - :option:`PrivateMemberCase`, :option:`PrivateMemberPrefix`, :option:`PrivateMemberSuffix`, :option:`PrivateMemberIgnoredRegexp` + - :option:`PrivateMethodCase`, :option:`PrivateMethodPrefix`, :option:`PrivateMethodSuffix`, :option:`PrivateMethodIgnoredRegexp` + - :option:`ProtectedMemberCase`, :option:`ProtectedMemberPrefix`, :option:`ProtectedMemberSuffix`, :option:`ProtectedMemberIgnoredRegexp` + - :option:`ProtectedMethodCase`, :option:`ProtectedMethodPrefix`, :option:`ProtectedMethodSuffix`, :option:`ProtectedMethodIgnoredRegexp` + - :option:`PublicMemberCase`, :option:`PublicMemberPrefix`, :option:`PublicMemberSuffix`, :option:`PublicMemberIgnoredRegexp` + - :option:`PublicMethodCase`, :option:`PublicMethodPrefix`, :option:`PublicMethodSuffix`, :option:`PublicMethodIgnoredRegexp` + - :option:`ScopedEnumConstantCase`, :option:`ScopedEnumConstantPrefix`, :option:`ScopedEnumConstantSuffix`, :option:`ScopedEnumConstantIgnoredRegexp` + - :option:`StaticConstantCase`, :option:`StaticConstantPrefix`, :option:`StaticConstantSuffix`, :option:`StaticConstantIgnoredRegexp` + - :option:`StaticVariableCase`, :option:`StaticVariablePrefix`, :option:`StaticVariableSuffix`, :option:`StaticVariableIgnoredRegexp` + - :option:`StructCase`, :option:`StructPrefix`, :option:`StructSuffix`, :option:`StructIgnoredRegexp` + - :option:`TemplateParameterCase`, :option:`TemplateParameterPrefix`, :option:`TemplateParameterSuffix`, :option:`TemplateParameterIgnoredRegexp` + - :option:`TemplateTemplateParameterCase`, :option:`TemplateTemplateParameterPrefix`, :option:`TemplateTemplateParameterSuffix`, :option:`TemplateTemplateParameterIgnoredRegexp` + - :option:`TypeAliasCase`, :option:`TypeAliasPrefix`, :option:`TypeAliasSuffix`, :option:`TypeAliasIgnoredRegexp` + - :option:`TypedefCase`, :option:`TypedefPrefix`, :option:`TypedefSuffix`, :option:`TypedefIgnoredRegexp` + - :option:`TypeTemplateParameterCase`, :option:`TypeTemplateParameterPrefix`, :option:`TypeTemplateParameterSuffix`, :option:`TypeTemplateParameterIgnoredRegexp` + - :option:`UnionCase`, :option:`UnionPrefix`, :option:`UnionSuffix`, :option:`UnionIgnoredRegexp` + - :option:`ValueTemplateParameterCase`, :option:`ValueTemplateParameterPrefix`, :option:`ValueTemplateParameterSuffix`, :option:`ValueTemplateParameterIgnoredRegexp` + - :option:`VariableCase`, :option:`VariablePrefix`, :option:`VariableSuffix`, :option:`VariableIgnoredRegexp` + - :option:`VirtualMethodCase`, :option:`VirtualMethodPrefix`, :option:`VirtualMethodSuffix`, :option:`VirtualMethodIgnoredRegexp` .. option:: AbstractClassCase @@ -100,6 +100,11 @@ The following options are describe below: When defined, the check will ensure abstract class names will add the prefixed with the given value (regardless of casing). +.. option:: AbstractClassIgnoredRegexp + + Identifier naming checks won't be enforced for abstract class names + matching this regular expression. + .. option:: AbstractClassSuffix When defined, the check will ensure abstract class names will add the @@ -199,6 +204,11 @@ After if AggressiveDependentMemberLookup is ``1``: When defined, the check will ensure class names will add the prefixed with the given value (regardless of casing). +.. option:: ClassIgnoredRegexp + + Identifier naming checks won't be enforced for class names matching + this regular expression. + .. option:: ClassSuffix When defined, the check will ensure class names will add the @@ -242,6 +252,11 @@ After: When defined, the check will ensure class constant names will add the prefixed with the given value (regardless of casing). +.. option:: ClassConstantIgnoredRegexp + + Identifier naming checks won't be enforced for class constant names + matching this regular expression. + .. option:: ClassConstantSuffix When defined, the check will ensure class constant names will add the @@ -283,6 +298,11 @@ After: When defined, the check will ensure class member names will add the prefixed with the given value (regardless of casing). +.. option:: ClassMemberIgnoredRegexp + + Identifier naming checks won't be enforced for class member names + matching this regular expression. + .. option:: ClassMemberSuffix When defined, the check will ensure class member names will add the @@ -324,6 +344,11 @@ After: When defined, the check will ensure class method names will add the prefixed with the given value (regardless of casing). +.. option:: ClassMethodIgnoredRegexp + + Identifier naming checks won't be enforced for class method names + matching this regular expression. + .. option:: ClassMethodSuffix When defined, the check will ensure class method names will add the @@ -365,6 +390,11 @@ After: When defined, the check will ensure constant names will add the prefixed with the given value (regardless of casing). +.. option:: ConstantIgnoredRegexp + + Identifier naming checks won't be enforced for constant names + matching this regular expression. + .. option:: ConstantSuffix When defined, the check will ensure constant names will add the @@ -400,6 +430,11 @@ After: When defined, the check will ensure constant member names will add the prefixed with the given value (regardless of casing). +.. option:: ConstantMemberIgnoredRegexp + + Identifier naming checks won't be enforced for constant member names + matching this regular expression. + .. option:: ConstantMemberSuffix When defined, the check will ensure constant member names will add the @@ -439,6 +474,11 @@ After: When defined, the check will ensure constant parameter names will add the prefixed with the given value (regardless of casing). +.. option:: ConstantParameterIgnoredRegexp + + Identifier naming checks won't be enforced for constant parameter names + matching this regular expression. + .. option:: ConstantParameterSuffix When defined, the check will ensure constant parameter names will add the @@ -474,6 +514,11 @@ After: When defined, the check will ensure constant pointer parameter names will add the prefixed with the given value (regardless of casing). +.. option:: ConstantPointerParameterIgnoredRegexp + + Identifier naming checks won't be enforced for constant pointer parameter + names matching this regular expression. + .. option:: ConstantPointerParameterSuffix When defined, the check will ensure constant pointer parameter names will add the @@ -509,6 +554,11 @@ After: When defined, the check will ensure constexpr function names will add the prefixed with the given value (regardless of casing). +.. option:: ConstexprFunctionIgnoredRegexp + + Identifier naming checks won't be enforced for constexpr function names + matching this regular expression. + .. option:: ConstexprFunctionSuffix When defined, the check will ensure constexpr function names will add the @@ -544,6 +594,11 @@ After: When defined, the check will ensure constexpr method names will add the prefixed with the given value (regardless of casing). +.. option:: ConstexprMethodIgnoredRegexp + + Identifier naming checks won't be enforced for constexpr method names + matching this regular expression. + .. option:: ConstexprMethodSuffix When defined, the check will ensure constexpr method names will add the @@ -585,6 +640,11 @@ After: When defined, the check will ensure constexpr variable names will add the prefixed with the given value (regardless of casing). +.. option:: ConstexprVariableIgnoredRegexp + + Identifier naming checks won't be enforced for constexpr variable names + matching this regular expression. + .. option:: ConstexprVariableSuffix When defined, the check will ensure constexpr variable names will add the @@ -620,6 +680,11 @@ After: When defined, the check will ensure enumeration names will add the prefixed with the given value (regardless of casing). +.. option:: EnumIgnoredRegexp + + Identifier naming checks won't be enforced for enumeration names + matching this regular expression. + .. option:: EnumSuffix When defined, the check will ensure enumeration names will add the @@ -655,6 +720,11 @@ After: When defined, the check will ensure enumeration constant names will add the prefixed with the given value (regardless of casing). +.. option:: EnumConstantIgnoredRegexp + + Identifier naming checks won't be enforced for enumeration constant names + matching this regular expression. + .. option:: EnumConstantSuffix When defined, the check will ensure enumeration constant names will add the @@ -690,6 +760,11 @@ After: When defined, the check will ensure function names will add the prefixed with the given value (regardless of casing). +.. option:: FunctionIgnoredRegexp + + Identifier naming checks won't be enforced for function names + matching this regular expression. + .. option:: FunctionSuffix When defined, the check will ensure function names will add the @@ -732,6 +807,11 @@ After: When defined, the check will ensure global constant names will add the prefixed with the given value (regardless of casing). +.. option:: GlobalConstantIgnoredRegexp + + Identifier naming checks won't be enforced for global constant names + matching this regular expression. + .. option:: GlobalConstantSuffix When defined, the check will ensure global constant names will add the @@ -767,6 +847,11 @@ After: When defined, the check will ensure global constant pointer names will add the prefixed with the given value (regardless of casing). +.. option:: GlobalConstantPointerIgnoredRegexp + + Identifier naming checks won't be enforced for global constant pointer + names matching this regular expression. + .. option:: GlobalConstantPointerSuffix When defined, the check will ensure global constant pointer names will add the @@ -802,6 +887,11 @@ After: When defined, the check will ensure global function names will add the prefixed with the given value (regardless of casing). +.. option:: GlobalFunctionIgnoredRegexp + + Identifier naming checks won't be enforced for global function names + matching this regular expression. + .. option:: GlobalFunctionSuffix When defined, the check will ensure global function names will add the @@ -837,6 +927,11 @@ After: When defined, the check will ensure global pointer names will add the prefixed with the given value (regardless of casing). +.. option:: GlobalPointerIgnoredRegexp + + Identifier naming checks won't be enforced for global pointer names + matching this regular expression. + .. option:: GlobalPointerSuffix When defined, the check will ensure global pointer names will add the @@ -872,6 +967,11 @@ After: When defined, the check will ensure global variable names will add the prefixed with the given value (regardless of casing). +.. option:: GlobalVariableIgnoredRegexp + + Identifier naming checks won't be enforced for global variable names + matching this regular expression. + .. option:: GlobalVariableSuffix When defined, the check will ensure global variable names will add the @@ -913,6 +1013,11 @@ After: When defined, the check will ensure inline namespaces names will add the prefixed with the given value (regardless of casing). +.. option:: InlineNamespaceIgnoredRegexp + + Identifier naming checks won't be enforced for inline namespaces names + matching this regular expression. + .. option:: InlineNamespaceSuffix When defined, the check will ensure inline namespaces names will add the @@ -956,6 +1061,11 @@ After: When defined, the check will ensure local constant names will add the prefixed with the given value (regardless of casing). +.. option:: LocalConstantIgnoredRegexp + + Identifier naming checks won't be enforced for local constant names + matching this regular expression. + .. option:: LocalConstantSuffix When defined, the check will ensure local constant names will add the @@ -991,6 +1101,11 @@ After: When defined, the check will ensure local constant pointer names will add the prefixed with the given value (regardless of casing). +.. option:: LocalConstantPointerIgnoredRegexp + + Identifier naming checks won't be enforced for local constant pointer names + matching this regular expression. + .. option:: LocalConstantPointerSuffix When defined, the check will ensure local constant pointer names will add the @@ -1026,6 +1141,11 @@ After: When defined, the check will ensure local pointer names will add the prefixed with the given value (regardless of casing). +.. option:: LocalPointerIgnoredRegexp + + Identifier naming checks won't be enforced for local pointer names + matching this regular expression. + .. option:: LocalPointerSuffix When defined, the check will ensure local pointer names will add the @@ -1061,6 +1181,19 @@ After: When defined, the check will ensure local variable names will add the prefixed with the given value (regardless of casing). +.. option:: LocalVariableIgnoredRegexp + + Identifier naming checks won't be enforced for local variable names + matching this regular expression. + +For example using values of: + + - LocalVariableCase of ``CamelCase`` + - LocalVariableIgnoredRegexp of ``\w{1,2}`` + +Will exclude variables with a length less than or equal to 2 from the +camel case check applied to other variables. + .. option:: LocalVariableSuffix When defined, the check will ensure local variable names will add the @@ -1096,6 +1229,11 @@ After: When defined, the check will ensure macro definitions will add the prefixed with the given value (regardless of casing). +.. option:: MacroDefinitionIgnoredRegexp + + Identifier naming checks won't be enforced for macro definitions + matching this regular expression. + .. option:: MacroDefinitionSuffix When defined, the check will ensure macro definitions will add the @@ -1134,6 +1272,11 @@ using the ``-D`` flag. When defined, the check will ensure member names will add the prefixed with the given value (regardless of casing). +.. option:: MemberIgnoredRegexp + + Identifier naming checks won't be enforced for member names + matching this regular expression. + .. option:: MemberSuffix When defined, the check will ensure member names will add the @@ -1173,6 +1316,11 @@ After: When defined, the check will ensure method names will add the prefixed with the given value (regardless of casing). +.. option:: MethodIgnoredRegexp + + Identifier naming checks won't be enforced for method names + matching this regular expression. + .. option:: MethodSuffix When defined, the check will ensure method names will add the @@ -1212,6 +1360,11 @@ After: When defined, the check will ensure namespace names will add the prefixed with the given value (regardless of casing). +.. option:: NamespaceIgnoredRegexp + + Identifier naming checks won't be enforced for namespace names + matching this regular expression. + .. option:: NamespaceSuffix When defined, the check will ensure namespace names will add the @@ -1251,6 +1404,11 @@ After: When defined, the check will ensure parameter names will add the prefixed with the given value (regardless of casing). +.. option:: ParameterIgnoredRegexp + + Identifier naming checks won't be enforced for parameter names + matching this regular expression. + .. option:: ParameterSuffix When defined, the check will ensure parameter names will add the @@ -1286,6 +1444,11 @@ After: When defined, the check will ensure parameter pack names will add the prefixed with the given value (regardless of casing). +.. option:: ParameterPackIgnoredRegexp + + Identifier naming checks won't be enforced for parameter pack names + matching this regular expression. + .. option:: ParameterPackSuffix When defined, the check will ensure parameter pack names will add the @@ -1325,6 +1488,11 @@ After: When defined, the check will ensure pointer parameter names will add the prefixed with the given value (regardless of casing). +.. option:: PointerParameterIgnoredRegexp + + Identifier naming checks won't be enforced for pointer parameter names + matching this regular expression. + .. option:: PointerParameterSuffix When defined, the check will ensure pointer parameter names will add the @@ -1360,6 +1528,11 @@ After: When defined, the check will ensure private member names will add the prefixed with the given value (regardless of casing). +.. option:: PrivateMemberIgnoredRegexp + + Identifier naming checks won't be enforced for private member names + matching this regular expression. + .. option:: PrivateMemberSuffix When defined, the check will ensure private member names will add the @@ -1401,6 +1574,11 @@ After: When defined, the check will ensure private method names will add the prefixed with the given value (regardless of casing). +.. option:: PrivateMethodIgnoredRegexp + + Identifier naming checks won't be enforced for private method names + matching this regular expression. + .. option:: PrivateMethodSuffix When defined, the check will ensure private method names will add the @@ -1442,6 +1620,11 @@ After: When defined, the check will ensure protected member names will add the prefixed with the given value (regardless of casing). +.. option:: ProtectedMemberIgnoredRegexp + + Identifier naming checks won't be enforced for protected member names + matching this regular expression. + .. option:: ProtectedMemberSuffix When defined, the check will ensure protected member names will add the @@ -1475,17 +1658,22 @@ After: .. option:: ProtectedMethodCase - When defined, the check will ensure protect method names conform to the + When defined, the check will ensure protected method names conform to the selected casing. .. option:: ProtectedMethodPrefix - When defined, the check will ensure protect method names will add the + When defined, the check will ensure protected method names will add the prefixed with the given value (regardless of casing). +.. option:: ProtectedMethodIgnoredRegexp + + Identifier naming checks won't be enforced for protected method names + matching this regular expression. + .. option:: ProtectedMethodSuffix - When defined, the check will ensure protect method names will add the + When defined, the check will ensure protected method names will add the suffix with the given value (regardless of casing). For example using values of: @@ -1524,6 +1712,11 @@ After: When defined, the check will ensure public member names will add the prefixed with the given value (regardless of casing). +.. option:: PublicMemberIgnoredRegexp + + Identifier naming checks won't be enforced for public member names + matching this regular expression. + .. option:: PublicMemberSuffix When defined, the check will ensure public member names will add the @@ -1565,6 +1758,11 @@ After: When defined, the check will ensure public method names will add the prefixed with the given value (regardless of casing). +.. option:: PublicMethodIgnoredRegexp + + Identifier naming checks won't be enforced for public method names + matching this regular expression. + .. option:: PublicMethodSuffix When defined, the check will ensure public method names will add the @@ -1606,6 +1804,11 @@ After: When defined, the check will ensure scoped enum constant names will add the prefixed with the given value (regardless of casing). +.. option:: ScopedEnumConstantIgnoredRegexp + + Identifier naming checks won't be enforced for scoped enum constant names + matching this regular expression. + .. option:: ScopedEnumConstantSuffix When defined, the check will ensure scoped enum constant names will add the @@ -1641,6 +1844,11 @@ After: When defined, the check will ensure static constant names will add the prefixed with the given value (regardless of casing). +.. option:: StaticConstantIgnoredRegexp + + Identifier naming checks won't be enforced for static constant names + matching this regular expression. + .. option:: StaticConstantSuffix When defined, the check will ensure static constant names will add the @@ -1676,6 +1884,11 @@ After: When defined, the check will ensure static variable names will add the prefixed with the given value (regardless of casing). +.. option:: StaticVariableIgnoredRegexp + + Identifier naming checks won't be enforced for static variable names + matching this regular expression. + .. option:: StaticVariableSuffix When defined, the check will ensure static variable names will add the @@ -1711,6 +1924,11 @@ After: When defined, the check will ensure struct names will add the prefixed with the given value (regardless of casing). +.. option:: StructIgnoredRegexp + + Identifier naming checks won't be enforced for struct names + matching this regular expression. + .. option:: StructSuffix When defined, the check will ensure struct names will add the @@ -1752,6 +1970,11 @@ After: When defined, the check will ensure template parameter names will add the prefixed with the given value (regardless of casing). +.. option:: TemplateParameterIgnoredRegexp + + Identifier naming checks won't be enforced for template parameter names + matching this regular expression. + .. option:: TemplateParameterSuffix When defined, the check will ensure template parameter names will add the @@ -1787,6 +2010,11 @@ After: When defined, the check will ensure template template parameter names will add the prefixed with the given value (regardless of casing). +.. option:: TemplateTemplateParameterIgnoredRegexp + + Identifier naming checks won't be enforced for template template parameter + names matching this regular expression. + .. option:: TemplateTemplateParameterSuffix When defined, the check will ensure template template parameter names will add the @@ -1824,6 +2052,11 @@ After: When defined, the check will ensure type alias names will add the prefixed with the given value (regardless of casing). +.. option:: TypeAliasIgnoredRegexp + + Identifier naming checks won't be enforced for type alias names + matching this regular expression. + .. option:: TypeAliasSuffix When defined, the check will ensure type alias names will add the @@ -1859,6 +2092,11 @@ After: When defined, the check will ensure typedef names will add the prefixed with the given value (regardless of casing). +.. option:: TypedefIgnoredRegexp + + Identifier naming checks won't be enforced for typedef names + matching this regular expression. + .. option:: TypedefSuffix When defined, the check will ensure typedef names will add the @@ -1894,6 +2132,11 @@ After: When defined, the check will ensure type template parameter names will add the prefixed with the given value (regardless of casing). +.. option:: TypeTemplateParameterIgnoredRegexp + + Identifier naming checks won't be enforced for type template names + matching this regular expression. + .. option:: TypeTemplateParameterSuffix When defined, the check will ensure type template parameter names will add the @@ -1931,6 +2174,11 @@ After: When defined, the check will ensure union names will add the prefixed with the given value (regardless of casing). +.. option:: UnionIgnoredRegexp + + Identifier naming checks won't be enforced for union names + matching this regular expression. + .. option:: UnionSuffix When defined, the check will ensure union names will add the @@ -1972,6 +2220,11 @@ After: When defined, the check will ensure value template parameter names will add the prefixed with the given value (regardless of casing). +.. option:: ValueTemplateParameterIgnoredRegexp + + Identifier naming checks won't be enforced for value template parameter + names matching this regular expression. + .. option:: ValueTemplateParameterSuffix When defined, the check will ensure value template parameter names will add the @@ -2009,6 +2262,11 @@ After: When defined, the check will ensure variable names will add the prefixed with the given value (regardless of casing). +.. option:: VariableIgnoredRegexp + + Identifier naming checks won't be enforced for variable names + matching this regular expression. + .. option:: VariableSuffix When defined, the check will ensure variable names will add the @@ -2044,6 +2302,11 @@ After: When defined, the check will ensure virtual method names will add the prefixed with the given value (regardless of casing). +.. option:: VirtualMethodIgnoredRegexp + + Identifier naming checks won't be enforced for virtual method names + matching this regular expression. + .. option:: VirtualMethodSuffix When defined, the check will ensure virtual method names will add the diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability-identifier-naming-bugfix-name-conflicts.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability-identifier-naming-bugfix-name-conflicts.cpp index 12ddcf55c1192..bee93c99976b4 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability-identifier-naming-bugfix-name-conflicts.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability-identifier-naming-bugfix-name-conflicts.cpp @@ -25,3 +25,13 @@ int func2(int Foo) { return 0; } + +int func3(int _0Bad) { + // CHECK-MESSAGES: :[[@LINE-1]]:15: warning: invalid case style for parameter '_0Bad'; cannot be fixed automatically [readability-identifier-naming] + // CHECK-FIXES: {{^}}int func3(int _0Bad) {{{$}} + if (_0Bad == 1) { + // CHECK-FIXES: {{^}} if (_0Bad == 1) {{{$}} + return 2; + } + return 0; +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability-identifier-naming-ignored-regexp.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability-identifier-naming-ignored-regexp.cpp new file mode 100644 index 0000000000000..e99edff5cc21c --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/readability-identifier-naming-ignored-regexp.cpp @@ -0,0 +1,47 @@ +// RUN: %check_clang_tidy %s readability-identifier-naming %t -- \ +// RUN: -config='{CheckOptions: [ \ +// RUN: {key: readability-identifier-naming.ParameterCase, value: CamelCase}, \ +// RUN: {key: readability-identifier-naming.ParameterIgnoredRegexp, value: "^[a-z]{1,2}$"}, \ +// RUN: {key: readability-identifier-naming.ClassCase, value: CamelCase}, \ +// RUN: {key: readability-identifier-naming.ClassIgnoredRegexp, value: "^fo$|^fooo$"}, \ +// RUN: {key: readability-identifier-naming.StructCase, value: CamelCase}, \ +// RUN: {key: readability-identifier-naming.StructIgnoredRegexp, value: "sooo|so|soo|$invalidregex["} \ +// RUN: ]}' + +int testFunc(int a, char **b); +int testFunc(int ab, char **ba); +int testFunc(int abc, char **cba); +// CHECK-MESSAGES: :[[@LINE-1]]:18: warning: invalid case style for parameter 'abc' +// CHECK-MESSAGES: :[[@LINE-2]]:30: warning: invalid case style for parameter 'cba' +// CHECK-FIXES: {{^}}int testFunc(int Abc, char **Cba);{{$}} +int testFunc(int dE, char **eD); +// CHECK-MESSAGES: :[[@LINE-1]]:18: warning: invalid case style for parameter 'dE' +// CHECK-MESSAGES: :[[@LINE-2]]:29: warning: invalid case style for parameter 'eD' +// CHECK-FIXES: {{^}}int testFunc(int DE, char **ED);{{$}} +int testFunc(int Abc, char **Cba); + +class fo { +}; + +class fofo { + // CHECK-MESSAGES: :[[@LINE-1]]:7: warning: invalid case style for class 'fofo' + // CHECK-FIXES: {{^}}class Fofo {{{$}} +}; + +class foo { + // CHECK-MESSAGES: :[[@LINE-1]]:7: warning: invalid case style for class 'foo' + // CHECK-FIXES: {{^}}class Foo {{{$}} +}; + +class fooo { +}; + +class afooo { + // CHECK-MESSAGES: :[[@LINE-1]]:7: warning: invalid case style for class 'afooo' + // CHECK-FIXES: {{^}}class Afooo {{{$}} +}; + +struct soo { + // CHECK-MESSAGES: :[[@LINE-1]]:8: warning: invalid case style for struct 'soo' + // CHECK-FIXES: {{^}}struct Soo {{{$}} +}; diff --git a/clang-tools-extra/unittests/clang-query/QueryParserTest.cpp b/clang-tools-extra/unittests/clang-query/QueryParserTest.cpp index 4a0a80146af4b..78d6f593777db 100644 --- a/clang-tools-extra/unittests/clang-query/QueryParserTest.cpp +++ b/clang-tools-extra/unittests/clang-query/QueryParserTest.cpp @@ -232,14 +232,12 @@ TEST_F(QueryParserTest, Complete) { EXPECT_EQ("dump", Comps[3].DisplayText); Comps = QueryParser::complete("set traversal ", 14, QS); - ASSERT_EQ(3u, Comps.size()); + ASSERT_EQ(2u, Comps.size()); EXPECT_EQ("AsIs ", Comps[0].TypedText); EXPECT_EQ("AsIs", Comps[0].DisplayText); - EXPECT_EQ("IgnoreImplicitCastsAndParentheses ", Comps[1].TypedText); - EXPECT_EQ("IgnoreImplicitCastsAndParentheses", Comps[1].DisplayText); - EXPECT_EQ("IgnoreUnlessSpelledInSource ", Comps[2].TypedText); - EXPECT_EQ("IgnoreUnlessSpelledInSource", Comps[2].DisplayText); + EXPECT_EQ("IgnoreUnlessSpelledInSource ", Comps[1].TypedText); + EXPECT_EQ("IgnoreUnlessSpelledInSource", Comps[1].DisplayText); Comps = QueryParser::complete("match while", 11, QS); ASSERT_EQ(1u, Comps.size()); diff --git a/clang-tools-extra/unittests/clang-tidy/TransformerClangTidyCheckTest.cpp b/clang-tools-extra/unittests/clang-tidy/TransformerClangTidyCheckTest.cpp index 76de7711cee9f..536d6f8ef275e 100644 --- a/clang-tools-extra/unittests/clang-tidy/TransformerClangTidyCheckTest.cpp +++ b/clang-tools-extra/unittests/clang-tidy/TransformerClangTidyCheckTest.cpp @@ -148,7 +148,7 @@ Optional noSkip(const LangOptions &LangOpts, if (Options.get("Skip", "false") == "true") return None; return tooling::makeRule(clang::ast_matchers::functionDecl(), - change(cat("void nothing()")), cat("no message")); + changeTo(cat("void nothing();")), cat("no message")); } class ConfigurableCheck : public TransformerClangTidyCheck { diff --git a/clang/docs/ClangCommandLineReference.rst b/clang/docs/ClangCommandLineReference.rst index 830d3aed0904d..3674f3a62695c 100644 --- a/clang/docs/ClangCommandLineReference.rst +++ b/clang/docs/ClangCommandLineReference.rst @@ -2885,6 +2885,10 @@ Only supported on X86 and RISC-V. Otherwise accepted for compatibility with GCC. .. option:: -municode +.. option:: -mabi=vec-extabi, -mabi=vec-default + +Only supported on AIX. Specify usage of the extended vector ABI on AIX and of non-volatile vector registers. Defaults to '-mabi=default' when Altivec is enabled. + .. option:: -mvx, -mno-vx .. option:: -mwarn-nonportable-cfstrings, -mno-warn-nonportable-cfstrings diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 2dcb496d9b792..0285c2e3680b2 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -3233,8 +3233,9 @@ statements in C). The pragma can also be used with ``off`` which turns FP contraction off for a section of the code. This can be useful when fast contraction is otherwise -enabled for the translation unit with the ``-ffp-contract=fast`` flag. - +enabled for the translation unit with the ``-ffp-contract=fast-honor-pragmas`` flag. +Note that ``-ffp-contract=fast`` will override pragmas to fuse multiply and +addition across statements regardless of any controlling pragmas. ``#pragma clang fp exceptions`` specifies floating point exception behavior. It may take one the the values: ``ignore``, ``maytrap`` or ``strict``. Meaning of diff --git a/clang/docs/LibASTMatchersReference.html b/clang/docs/LibASTMatchersReference.html index fbc53ed743a21..9f14ab9f4c5b9 100644 --- a/clang/docs/LibASTMatchersReference.html +++ b/clang/docs/LibASTMatchersReference.html @@ -5567,7 +5567,7 @@

AST Traversal Matchers

int i = 3.0; } The matcher - traverse(TK_IgnoreImplicitCastsAndParentheses, + traverse(TK_IgnoreUnlessSpelledInSource, varDecl(hasInitializer(floatLiteral().bind("init"))) ) matches the variable declaration with "init" bound to the "3.0". diff --git a/clang/docs/OpenMPSupport.rst b/clang/docs/OpenMPSupport.rst index 427e5d292565b..227b373957eab 100644 --- a/clang/docs/OpenMPSupport.rst +++ b/clang/docs/OpenMPSupport.rst @@ -217,7 +217,7 @@ implementation. +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ | device extension | teams construct on the host device | :part:`worked on` | Clang part is done, r371553. | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ -| device extension | support non-contiguous array sections for target update | :part:`worked on` | | +| device extension | support non-contiguous array sections for target update | :good:`done` | | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ | device extension | pointer attachment | :none:`unclaimed` | | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 8da9490f7b6f3..d62c62dad3d2a 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -234,6 +234,12 @@ AST Matchers has been changed to no longer match on template instantiations or on implicit nodes which are not spelled in the source. +- The TK_IgnoreImplicitCastsAndParentheses traversal kind was removed. It + is recommended to use TK_IgnoreUnlessSpelledInSource instead. + +- The behavior of the forEach() matcher was changed to not internally ignore + implicit and parenthesis nodes. + clang-format ------------ diff --git a/clang/docs/ThinLTO.rst b/clang/docs/ThinLTO.rst index 0da822f498b98..fa6d28e13ba78 100644 --- a/clang/docs/ThinLTO.rst +++ b/clang/docs/ThinLTO.rst @@ -124,9 +124,13 @@ be reduced to ``N`` via: ``/opt:lldltojobs=N`` Other possible values for ``N`` are: -- 0: Use one thread per physical core (default) -- 1: Use a single thread only (disable multi-threading) -- all: Use one thread per logical core (uses all hyper-threads) + +- 0: + Use one thread per physical core (default) +- 1: + Use a single thread only (disable multi-threading) +- all: + Use one thread per logical core (uses all hyper-threads) Incremental ----------- diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index 2c59ba929ef42..27ec7a85599db 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -1336,15 +1336,16 @@ are listed below. The C standard permits intermediate floating-point results within an expression to be computed with more precision than their type would normally allow. This permits operation fusing, and Clang takes advantage - of this by default. This behavior can be controlled with the - ``FP_CONTRACT`` pragma. Please refer to the pragma documentation for a - description of how the pragma interacts with this option. + of this by default. This behavior can be controlled with the ``FP_CONTRACT`` + and ``clang fp contract`` pragmas. Please refer to the pragma documentation + for a description of how the pragmas interact with this option. Valid values are: - * ``fast`` (everywhere) - * ``on`` (according to FP_CONTRACT pragma, default) + * ``fast`` (fuse across statements disregarding pragmas, default for CUDA) + * ``on`` (fuse in the same statement unless dictated by pragmas, default for languages other than CUDA/HIP) * ``off`` (never fuse) + * ``fast-honor-pragmas`` (fuse across statements unless dictated by pragmas, default for HIP) .. _opt_fhonor-infinities: diff --git a/clang/include/clang/APINotes/Types.h b/clang/include/clang/APINotes/Types.h index be2a99ad6fd08..3095bfbf1718e 100644 --- a/clang/include/clang/APINotes/Types.h +++ b/clang/include/clang/APINotes/Types.h @@ -9,6 +9,12 @@ #ifndef LLVM_CLANG_APINOTES_TYPES_H #define LLVM_CLANG_APINOTES_TYPES_H +#include "clang/Basic/Specifiers.h" +#include "llvm/ADT/Optional.h" +#include "llvm/ADT/StringRef.h" +#include +#include + namespace clang { namespace api_notes { enum class RetainCountConventionKind { @@ -34,6 +40,694 @@ enum class SwiftNewTypeKind { Struct, Enum, }; + +/// Describes API notes data for any entity. +/// +/// This is used as the base of all API notes. +class CommonEntityInfo { +public: + /// Message to use when this entity is unavailable. + std::string UnavailableMsg; + + /// Whether this entity is marked unavailable. + unsigned Unavailable : 1; + + /// Whether this entity is marked unavailable in Swift. + unsigned UnavailableInSwift : 1; + +private: + /// Whether SwiftPrivate was specified. + unsigned SwiftPrivateSpecified : 1; + + /// Whether this entity is considered "private" to a Swift overlay. + unsigned SwiftPrivate : 1; + +public: + /// Swift name of this entity. + std::string SwiftName; + + CommonEntityInfo() + : Unavailable(0), UnavailableInSwift(0), SwiftPrivateSpecified(0), + SwiftPrivate(0) {} + + llvm::Optional isSwiftPrivate() const { + return SwiftPrivateSpecified ? llvm::Optional(SwiftPrivate) + : llvm::None; + } + + void setSwiftPrivate(llvm::Optional Private) { + SwiftPrivateSpecified = Private.hasValue(); + SwiftPrivate = Private.hasValue() ? *Private : 0; + } + + friend bool operator==(const CommonEntityInfo &, const CommonEntityInfo &); + + CommonEntityInfo &operator|=(const CommonEntityInfo &RHS) { + // Merge unavailability. + if (RHS.Unavailable) { + Unavailable = true; + if (UnavailableMsg.empty()) + UnavailableMsg = RHS.UnavailableMsg; + } + + if (RHS.UnavailableInSwift) { + UnavailableInSwift = true; + if (UnavailableMsg.empty()) + UnavailableMsg = RHS.UnavailableMsg; + } + + if (!SwiftPrivateSpecified) + setSwiftPrivate(RHS.isSwiftPrivate()); + + if (SwiftName.empty()) + SwiftName = RHS.SwiftName; + + return *this; + } + + LLVM_DUMP_METHOD void dump(llvm::raw_ostream &OS); +}; + +inline bool operator==(const CommonEntityInfo &LHS, + const CommonEntityInfo &RHS) { + return LHS.UnavailableMsg == RHS.UnavailableMsg && + LHS.Unavailable == RHS.Unavailable && + LHS.UnavailableInSwift == RHS.UnavailableInSwift && + LHS.SwiftPrivateSpecified == RHS.SwiftPrivateSpecified && + LHS.SwiftPrivate == RHS.SwiftPrivate && LHS.SwiftName == RHS.SwiftName; +} + +inline bool operator!=(const CommonEntityInfo &LHS, + const CommonEntityInfo &RHS) { + return !(LHS == RHS); +} + +/// Describes API notes for types. +class CommonTypeInfo : public CommonEntityInfo { + /// The Swift type to which a given type is bridged. + /// + /// Reflects the swift_bridge attribute. + llvm::Optional SwiftBridge; + + /// The NS error domain for this type. + llvm::Optional NSErrorDomain; + +public: + CommonTypeInfo() : CommonEntityInfo() {} + + const llvm::Optional &getSwiftBridge() const { + return SwiftBridge; + } + + void setSwiftBridge(const llvm::Optional &SwiftType) { + SwiftBridge = SwiftType; + } + + void setSwiftBridge(const llvm::Optional &SwiftType) { + SwiftBridge = SwiftType + ? llvm::Optional(std::string(*SwiftType)) + : llvm::None; + } + + const llvm::Optional &getNSErrorDomain() const { + return NSErrorDomain; + } + + void setNSErrorDomain(const llvm::Optional &Domain) { + NSErrorDomain = Domain; + } + + void setNSErrorDomain(const llvm::Optional &Domain) { + NSErrorDomain = + Domain ? llvm::Optional(std::string(*Domain)) : llvm::None; + } + + friend bool operator==(const CommonTypeInfo &, const CommonTypeInfo &); + + CommonTypeInfo &operator|=(const CommonTypeInfo &RHS) { + // Merge inherited info. + static_cast(*this) |= RHS; + + if (!SwiftBridge) + setSwiftBridge(RHS.getSwiftBridge()); + if (!NSErrorDomain) + setNSErrorDomain(RHS.getNSErrorDomain()); + + return *this; + } + + LLVM_DUMP_METHOD void dump(llvm::raw_ostream &OS); +}; + +inline bool operator==(const CommonTypeInfo &LHS, const CommonTypeInfo &RHS) { + return static_cast(LHS) == RHS && + LHS.SwiftBridge == RHS.SwiftBridge && + LHS.NSErrorDomain == RHS.NSErrorDomain; +} + +inline bool operator!=(const CommonTypeInfo &LHS, const CommonTypeInfo &RHS) { + return !(LHS == RHS); +} + +/// Describes API notes data for an Objective-C class or protocol. +class ObjCContextInfo : public CommonTypeInfo { + /// Whether this class has a default nullability. + unsigned HasDefaultNullability : 1; + + /// The default nullability. + unsigned DefaultNullability : 2; + + /// Whether this class has designated initializers recorded. + unsigned HasDesignatedInits : 1; + + unsigned SwiftImportAsNonGenericSpecified : 1; + unsigned SwiftImportAsNonGeneric : 1; + + unsigned SwiftObjCMembersSpecified : 1; + unsigned SwiftObjCMembers : 1; + +public: + ObjCContextInfo() + : CommonTypeInfo(), HasDefaultNullability(0), DefaultNullability(0), + HasDesignatedInits(0), SwiftImportAsNonGenericSpecified(false), + SwiftImportAsNonGeneric(false), SwiftObjCMembersSpecified(false), + SwiftObjCMembers(false) {} + + /// Determine the default nullability for properties and methods of this + /// class. + /// + /// eturns the default nullability, if implied, or None if there is no + llvm::Optional getDefaultNullability() const { + return HasDefaultNullability + ? llvm::Optional( + static_cast(DefaultNullability)) + : llvm::None; + } + + /// Set the default nullability for properties and methods of this class. + void setDefaultNullability(NullabilityKind Kind) { + HasDefaultNullability = true; + DefaultNullability = static_cast(Kind); + } + + bool hasDesignatedInits() const { return HasDesignatedInits; } + void setHasDesignatedInits(bool Value) { HasDesignatedInits = Value; } + + llvm::Optional getSwiftImportAsNonGeneric() const { + return SwiftImportAsNonGenericSpecified + ? llvm::Optional(SwiftImportAsNonGeneric) + : llvm::None; + } + void setSwiftImportAsNonGeneric(llvm::Optional Value) { + SwiftImportAsNonGenericSpecified = Value.hasValue(); + SwiftImportAsNonGeneric = Value.hasValue() ? *Value : false; + } + + llvm::Optional getSwiftObjCMembers() const { + return SwiftObjCMembersSpecified ? llvm::Optional(SwiftObjCMembers) + : llvm::None; + } + void setSwiftObjCMembers(llvm::Optional Value) { + SwiftObjCMembersSpecified = Value.hasValue(); + SwiftObjCMembers = Value.hasValue() ? *Value : false; + } + + /// Strip off any information within the class information structure that is + /// module-local, such as 'audited' flags. + void stripModuleLocalInfo() { + HasDefaultNullability = false; + DefaultNullability = 0; + } + + friend bool operator==(const ObjCContextInfo &, const ObjCContextInfo &); + + ObjCContextInfo &operator|=(const ObjCContextInfo &RHS) { + // Merge inherited info. + static_cast(*this) |= RHS; + + // Merge nullability. + if (!getDefaultNullability()) + if (auto Nullability = RHS.getDefaultNullability()) + setDefaultNullability(*Nullability); + + if (!SwiftImportAsNonGenericSpecified) + setSwiftImportAsNonGeneric(RHS.getSwiftImportAsNonGeneric()); + + if (!SwiftObjCMembersSpecified) + setSwiftObjCMembers(RHS.getSwiftObjCMembers()); + + HasDesignatedInits |= RHS.HasDesignatedInits; + + return *this; + } + + LLVM_DUMP_METHOD void dump(llvm::raw_ostream &OS); +}; + +inline bool operator==(const ObjCContextInfo &LHS, const ObjCContextInfo &RHS) { + return static_cast(LHS) == RHS && + LHS.getDefaultNullability() == RHS.getDefaultNullability() && + LHS.HasDesignatedInits == RHS.HasDesignatedInits && + LHS.getSwiftImportAsNonGeneric() == RHS.getSwiftImportAsNonGeneric() && + LHS.getSwiftObjCMembers() == RHS.getSwiftObjCMembers(); +} + +inline bool operator!=(const ObjCContextInfo &LHS, const ObjCContextInfo &RHS) { + return !(LHS == RHS); +} + +/// API notes for a variable/property. +class VariableInfo : public CommonEntityInfo { + /// Whether this property has been audited for nullability. + unsigned NullabilityAudited : 1; + + /// The kind of nullability for this property. Only valid if the nullability + /// has been audited. + unsigned Nullable : 2; + + /// The C type of the variable, as a string. + std::string Type; + +public: + VariableInfo() : CommonEntityInfo(), NullabilityAudited(false), Nullable(0) {} + + llvm::Optional getNullability() const { + return NullabilityAudited ? llvm::Optional( + static_cast(Nullable)) + : llvm::None; + } + + void setNullabilityAudited(NullabilityKind kind) { + NullabilityAudited = true; + Nullable = static_cast(kind); + } + + const std::string &getType() const { return Type; } + void setType(const std::string &type) { Type = type; } + + friend bool operator==(const VariableInfo &, const VariableInfo &); + + VariableInfo &operator|=(const VariableInfo &RHS) { + static_cast(*this) |= RHS; + + if (!NullabilityAudited && RHS.NullabilityAudited) + setNullabilityAudited(*RHS.getNullability()); + if (Type.empty()) + Type = RHS.Type; + + return *this; + } + + LLVM_DUMP_METHOD void dump(llvm::raw_ostream &OS); +}; + +inline bool operator==(const VariableInfo &LHS, const VariableInfo &RHS) { + return static_cast(LHS) == RHS && + LHS.NullabilityAudited == RHS.NullabilityAudited && + LHS.Nullable == RHS.Nullable && LHS.Type == RHS.Type; +} + +inline bool operator!=(const VariableInfo &LHS, const VariableInfo &RHS) { + return !(LHS == RHS); +} + +/// Describes API notes data for an Objective-C property. +class ObjCPropertyInfo : public VariableInfo { + unsigned SwiftImportAsAccessorsSpecified : 1; + unsigned SwiftImportAsAccessors : 1; + +public: + ObjCPropertyInfo() + : VariableInfo(), SwiftImportAsAccessorsSpecified(false), + SwiftImportAsAccessors(false) {} + + llvm::Optional getSwiftImportAsAccessors() const { + return SwiftImportAsAccessorsSpecified + ? llvm::Optional(SwiftImportAsAccessors) + : llvm::None; + } + void setSwiftImportAsAccessors(llvm::Optional Value) { + SwiftImportAsAccessorsSpecified = Value.hasValue(); + SwiftImportAsAccessors = Value.hasValue() ? *Value : false; + } + + friend bool operator==(const ObjCPropertyInfo &, const ObjCPropertyInfo &); + + /// Merge class-wide information into the given property. + ObjCPropertyInfo &operator|=(const ObjCContextInfo &RHS) { + static_cast(*this) |= RHS; + + // Merge nullability. + if (!getNullability()) + if (auto Nullable = RHS.getDefaultNullability()) + setNullabilityAudited(*Nullable); + + return *this; + } + + ObjCPropertyInfo &operator|=(const ObjCPropertyInfo &RHS) { + static_cast(*this) |= RHS; + + if (!SwiftImportAsAccessorsSpecified) + setSwiftImportAsAccessors(RHS.getSwiftImportAsAccessors()); + + return *this; + } + + LLVM_DUMP_METHOD void dump(llvm::raw_ostream &OS); +}; + +inline bool operator==(const ObjCPropertyInfo &LHS, + const ObjCPropertyInfo &RHS) { + return static_cast(LHS) == RHS && + LHS.getSwiftImportAsAccessors() == RHS.getSwiftImportAsAccessors(); +} + +inline bool operator!=(const ObjCPropertyInfo &LHS, + const ObjCPropertyInfo &RHS) { + return !(LHS == RHS); +} + +/// Describes a function or method parameter. +class ParamInfo : public VariableInfo { + /// Whether noescape was specified. + unsigned NoEscapeSpecified : 1; + + /// Whether the this parameter has the 'noescape' attribute. + unsigned NoEscape : 1; + + /// A biased RetainCountConventionKind, where 0 means "unspecified". + /// + /// Only relevant for out-parameters. + unsigned RawRetainCountConvention : 3; + +public: + ParamInfo() + : VariableInfo(), NoEscapeSpecified(false), NoEscape(false), + RawRetainCountConvention() {} + + llvm::Optional isNoEscape() const { + if (!NoEscapeSpecified) + return llvm::None; + return NoEscape; + } + void setNoEscape(llvm::Optional Value) { + NoEscapeSpecified = Value.hasValue(); + NoEscape = Value.hasValue() ? *Value : false; + } + + llvm::Optional getRetainCountConvention() const { + if (!RawRetainCountConvention) + return llvm::None; + return static_cast(RawRetainCountConvention - 1); + } + void + setRetainCountConvention(llvm::Optional Value) { + RawRetainCountConvention = + Value.hasValue() ? static_cast(Value.getValue()) + 1 : 0; + assert(getRetainCountConvention() == Value && "bitfield too small"); + } + + ParamInfo &operator|=(const ParamInfo &RHS) { + static_cast(*this) |= RHS; + + if (!NoEscapeSpecified && RHS.NoEscapeSpecified) { + NoEscapeSpecified = true; + NoEscape = RHS.NoEscape; + } + + if (!RawRetainCountConvention) + RawRetainCountConvention = RHS.RawRetainCountConvention; + + return *this; + } + + friend bool operator==(const ParamInfo &, const ParamInfo &); + + LLVM_DUMP_METHOD void dump(llvm::raw_ostream &OS); +}; + +inline bool operator==(const ParamInfo &LHS, const ParamInfo &RHS) { + return static_cast(LHS) == RHS && + LHS.NoEscapeSpecified == RHS.NoEscapeSpecified && + LHS.NoEscape == RHS.NoEscape && + LHS.RawRetainCountConvention == RHS.RawRetainCountConvention; +} + +inline bool operator!=(const ParamInfo &LHS, const ParamInfo &RHS) { + return !(LHS == RHS); +} + +/// API notes for a function or method. +class FunctionInfo : public CommonEntityInfo { +private: + static constexpr const unsigned NullabilityKindMask = 0x3; + static constexpr const unsigned NullabilityKindSize = 2; + + static constexpr const unsigned ReturnInfoIndex = 0; + +public: + // If yes, we consider all types to be non-nullable unless otherwise noted. + // If this flag is not set, the pointer types are considered to have + // unknown nullability. + + /// Whether the signature has been audited with respect to nullability. + unsigned NullabilityAudited : 1; + + /// Number of types whose nullability is encoded with the NullabilityPayload. + unsigned NumAdjustedNullable : 8; + + /// A biased RetainCountConventionKind, where 0 means "unspecified". + unsigned RawRetainCountConvention : 3; + + // NullabilityKindSize bits are used to encode the nullability. The info + // about the return type is stored at position 0, followed by the nullability + // of the parameters. + + /// Stores the nullability of the return type and the parameters. + uint64_t NullabilityPayload = 0; + + /// The result type of this function, as a C type. + std::string ResultType; + + /// The function parameters. + std::vector Params; + + FunctionInfo() + : CommonEntityInfo(), NullabilityAudited(false), NumAdjustedNullable(0), + RawRetainCountConvention() {} + + static unsigned getMaxNullabilityIndex() { + return ((sizeof(NullabilityPayload) * CHAR_BIT) / NullabilityKindSize); + } + + void addTypeInfo(unsigned index, NullabilityKind kind) { + assert(index <= getMaxNullabilityIndex()); + assert(static_cast(kind) < NullabilityKindMask); + + NullabilityAudited = true; + if (NumAdjustedNullable < index + 1) + NumAdjustedNullable = index + 1; + + // Mask the bits. + NullabilityPayload &= + ~(NullabilityKindMask << (index * NullabilityKindSize)); + + // Set the value. + unsigned kindValue = (static_cast(kind)) + << (index * NullabilityKindSize); + NullabilityPayload |= kindValue; + } + + /// Adds the return type info. + void addReturnTypeInfo(NullabilityKind kind) { + addTypeInfo(ReturnInfoIndex, kind); + } + + /// Adds the parameter type info. + void addParamTypeInfo(unsigned index, NullabilityKind kind) { + addTypeInfo(index + 1, kind); + } + + NullabilityKind getParamTypeInfo(unsigned index) const { + return getTypeInfo(index + 1); + } + + NullabilityKind getReturnTypeInfo() const { return getTypeInfo(0); } + + llvm::Optional getRetainCountConvention() const { + if (!RawRetainCountConvention) + return llvm::None; + return static_cast(RawRetainCountConvention - 1); + } + void + setRetainCountConvention(llvm::Optional Value) { + RawRetainCountConvention = + Value.hasValue() ? static_cast(Value.getValue()) + 1 : 0; + assert(getRetainCountConvention() == Value && "bitfield too small"); + } + + friend bool operator==(const FunctionInfo &, const FunctionInfo &); + +private: + NullabilityKind getTypeInfo(unsigned index) const { + assert(NullabilityAudited && + "Checking the type adjustment on non-audited method."); + + // If we don't have info about this parameter, return the default. + if (index > NumAdjustedNullable) + return NullabilityKind::NonNull; + auto nullability = NullabilityPayload >> (index * NullabilityKindSize); + return static_cast(nullability & NullabilityKindMask); + } + +public: + LLVM_DUMP_METHOD void dump(llvm::raw_ostream &OS); +}; + +inline bool operator==(const FunctionInfo &LHS, const FunctionInfo &RHS) { + return static_cast(LHS) == RHS && + LHS.NullabilityAudited == RHS.NullabilityAudited && + LHS.NumAdjustedNullable == RHS.NumAdjustedNullable && + LHS.NullabilityPayload == RHS.NullabilityPayload && + LHS.ResultType == RHS.ResultType && LHS.Params == RHS.Params && + LHS.RawRetainCountConvention == RHS.RawRetainCountConvention; +} + +inline bool operator!=(const FunctionInfo &LHS, const FunctionInfo &RHS) { + return !(LHS == RHS); +} + +/// Describes API notes data for an Objective-C method. +class ObjCMethodInfo : public FunctionInfo { +public: + /// Whether this is a designated initializer of its class. + unsigned DesignatedInit : 1; + + /// Whether this is a required initializer. + unsigned RequiredInit : 1; + + ObjCMethodInfo() + : FunctionInfo(), DesignatedInit(false), RequiredInit(false) {} + + friend bool operator==(const ObjCMethodInfo &, const ObjCMethodInfo &); + + ObjCMethodInfo &operator|=(const ObjCContextInfo &RHS) { + // Merge Nullability. + if (!NullabilityAudited) { + if (auto Nullable = RHS.getDefaultNullability()) { + NullabilityAudited = true; + addTypeInfo(0, *Nullable); + } + } + return *this; + } + + LLVM_DUMP_METHOD void dump(llvm::raw_ostream &OS); +}; + +inline bool operator==(const ObjCMethodInfo &LHS, const ObjCMethodInfo &RHS) { + return static_cast(LHS) == RHS && + LHS.DesignatedInit == RHS.DesignatedInit && + LHS.RequiredInit == RHS.RequiredInit; +} + +inline bool operator!=(const ObjCMethodInfo &LHS, const ObjCMethodInfo &RHS) { + return !(LHS == RHS); +} + +/// Describes API notes data for a global variable. +class GlobalVariableInfo : public VariableInfo { +public: + GlobalVariableInfo() : VariableInfo() {} +}; + +/// Describes API notes data for a global function. +class GlobalFunctionInfo : public FunctionInfo { +public: + GlobalFunctionInfo() : FunctionInfo() {} +}; + +/// Describes API notes data for an enumerator. +class EnumConstantInfo : public CommonEntityInfo { +public: + EnumConstantInfo() : CommonEntityInfo() {} +}; + +/// Describes API notes data for a tag. +class TagInfo : public CommonTypeInfo { + unsigned HasFlagEnum : 1; + unsigned IsFlagEnum : 1; + +public: + llvm::Optional EnumExtensibility; + + TagInfo() : CommonTypeInfo(), HasFlagEnum(0), IsFlagEnum(0) {} + + llvm::Optional isFlagEnum() const { + if (HasFlagEnum) + return IsFlagEnum; + return llvm::None; + } + void setFlagEnum(llvm::Optional Value) { + HasFlagEnum = Value.hasValue(); + IsFlagEnum = Value.hasValue() ? *Value : false; + } + + TagInfo &operator|=(const TagInfo &RHS) { + static_cast(*this) |= RHS; + + if (!HasFlagEnum && HasFlagEnum) + setFlagEnum(RHS.isFlagEnum()); + + if (!EnumExtensibility.hasValue()) + EnumExtensibility = RHS.EnumExtensibility; + + return *this; + } + + friend bool operator==(const TagInfo &, const TagInfo &); + + LLVM_DUMP_METHOD void dump(llvm::raw_ostream &OS); +}; + +inline bool operator==(const TagInfo &LHS, const TagInfo &RHS) { + return static_cast(LHS) == RHS && + LHS.isFlagEnum() == RHS.isFlagEnum() && + LHS.EnumExtensibility == RHS.EnumExtensibility; +} + +inline bool operator!=(const TagInfo &LHS, const TagInfo &RHS) { + return !(LHS == RHS); +} + +/// Describes API notes data for a typedef. +class TypedefInfo : public CommonTypeInfo { +public: + llvm::Optional SwiftWrapper; + + TypedefInfo() : CommonTypeInfo() {} + + TypedefInfo &operator|=(const TypedefInfo &RHS) { + static_cast(*this) |= RHS; + if (!SwiftWrapper.hasValue()) + SwiftWrapper = RHS.SwiftWrapper; + return *this; + } + + friend bool operator==(const TypedefInfo &, const TypedefInfo &); + + LLVM_DUMP_METHOD void dump(llvm::raw_ostream &OS); +}; + +inline bool operator==(const TypedefInfo &LHS, const TypedefInfo &RHS) { + return static_cast(LHS) == RHS && + LHS.SwiftWrapper == RHS.SwiftWrapper; +} + +inline bool operator!=(const TypedefInfo &LHS, const TypedefInfo &RHS) { + return !(LHS == RHS); +} } // namespace api_notes } // namespace clang diff --git a/clang/include/clang/AST/ASTNodeTraverser.h b/clang/include/clang/AST/ASTNodeTraverser.h index 4f33b0c67e946..6f7affe662733 100644 --- a/clang/include/clang/AST/ASTNodeTraverser.h +++ b/clang/include/clang/AST/ASTNodeTraverser.h @@ -126,9 +126,6 @@ class ASTNodeTraverser switch (Traversal) { case TK_AsIs: break; - case TK_IgnoreImplicitCastsAndParentheses: - S = E->IgnoreParenImpCasts(); - break; case TK_IgnoreUnlessSpelledInSource: S = E->IgnoreUnlessSpelledInSource(); break; diff --git a/clang/include/clang/AST/ASTTypeTraits.h b/clang/include/clang/AST/ASTTypeTraits.h index bd817b75bb84e..034260cc8ed3f 100644 --- a/clang/include/clang/AST/ASTTypeTraits.h +++ b/clang/include/clang/AST/ASTTypeTraits.h @@ -40,10 +40,6 @@ enum TraversalKind { /// Will traverse all child nodes. TK_AsIs, - /// Will not traverse implicit casts and parentheses. - /// Corresponds to Expr::IgnoreParenImpCasts() - TK_IgnoreImplicitCastsAndParentheses, - /// Ignore AST nodes not written in the source TK_IgnoreUnlessSpelledInSource }; @@ -542,8 +538,6 @@ using ASTNodeKind = ::clang::ASTNodeKind; using TraversalKind = ::clang::TraversalKind; constexpr TraversalKind TK_AsIs = ::clang::TK_AsIs; -constexpr TraversalKind TK_IgnoreImplicitCastsAndParentheses = - ::clang::TK_IgnoreImplicitCastsAndParentheses; constexpr TraversalKind TK_IgnoreUnlessSpelledInSource = ::clang::TK_IgnoreUnlessSpelledInSource; } // namespace ast_type_traits diff --git a/clang/include/clang/AST/DeclCXX.h b/clang/include/clang/AST/DeclCXX.h index 36f42c06a300d..568eeb614a761 100644 --- a/clang/include/clang/AST/DeclCXX.h +++ b/clang/include/clang/AST/DeclCXX.h @@ -1622,58 +1622,6 @@ class CXXRecordDecl : public RecordDecl { CXXBasePath &Path, const CXXRecordDecl *BaseRecord); - /// Base-class lookup callback that determines whether there exists - /// a tag with the given name. - /// - /// This callback can be used with \c lookupInBases() to find tag members - /// of the given name within a C++ class hierarchy. - static bool FindTagMember(const CXXBaseSpecifier *Specifier, - CXXBasePath &Path, DeclarationName Name); - - /// Base-class lookup callback that determines whether there exists - /// a member with the given name. - /// - /// This callback can be used with \c lookupInBases() to find members - /// of the given name within a C++ class hierarchy. - static bool FindOrdinaryMember(const CXXBaseSpecifier *Specifier, - CXXBasePath &Path, DeclarationName Name); - - /// Base-class lookup callback that determines whether there exists - /// a member with the given name. - /// - /// This callback can be used with \c lookupInBases() to find members - /// of the given name within a C++ class hierarchy, including dependent - /// classes. - static bool - FindOrdinaryMemberInDependentClasses(const CXXBaseSpecifier *Specifier, - CXXBasePath &Path, DeclarationName Name); - - /// Base-class lookup callback that determines whether there exists - /// an OpenMP declare reduction member with the given name. - /// - /// This callback can be used with \c lookupInBases() to find members - /// of the given name within a C++ class hierarchy. - static bool FindOMPReductionMember(const CXXBaseSpecifier *Specifier, - CXXBasePath &Path, DeclarationName Name); - - /// Base-class lookup callback that determines whether there exists - /// an OpenMP declare mapper member with the given name. - /// - /// This callback can be used with \c lookupInBases() to find members - /// of the given name within a C++ class hierarchy. - static bool FindOMPMapperMember(const CXXBaseSpecifier *Specifier, - CXXBasePath &Path, DeclarationName Name); - - /// Base-class lookup callback that determines whether there exists - /// a member with the given name that can be used in a nested-name-specifier. - /// - /// This callback can be used with \c lookupInBases() to find members of - /// the given name within a C++ class hierarchy that can occur within - /// nested-name-specifiers. - static bool FindNestedNameSpecifierMember(const CXXBaseSpecifier *Specifier, - CXXBasePath &Path, - DeclarationName Name); - /// Retrieve the final overriders for each virtual member /// function in the class hierarchy where this class is the /// most-derived class in the class hierarchy. @@ -1682,12 +1630,20 @@ class CXXRecordDecl : public RecordDecl { /// Get the indirect primary bases for this class. void getIndirectPrimaryBases(CXXIndirectPrimaryBaseSet& Bases) const; + /// Determine whether this class has a member with the given name, possibly + /// in a non-dependent base class. + /// + /// No check for ambiguity is performed, so this should never be used when + /// implementing language semantics, but it may be appropriate for warnings, + /// static analysis, or similar. + bool hasMemberName(DeclarationName N) const; + /// Performs an imprecise lookup of a dependent name in this class. /// /// This function does not follow strict semantic rules and should be used /// only when lookup rules can be relaxed, e.g. indexing. std::vector - lookupDependentName(const DeclarationName &Name, + lookupDependentName(DeclarationName Name, llvm::function_ref Filter); /// Renders and displays an inheritance diagram diff --git a/clang/include/clang/AST/Expr.h b/clang/include/clang/AST/Expr.h index 5bbcbde9f9090..d2bef9eff13db 100644 --- a/clang/include/clang/AST/Expr.h +++ b/clang/include/clang/AST/Expr.h @@ -6395,9 +6395,6 @@ class TypoExpr : public Expr { /// /// One can also reliably suppress all bogus errors on expressions containing /// recovery expressions by examining results of Expr::containsErrors(). -/// -/// FIXME: RecoveryExpr is currently generated by default in C++ mode only, as -/// dependence isn't handled properly on several C-only codepaths. class RecoveryExpr final : public Expr, private llvm::TrailingObjects { public: diff --git a/clang/include/clang/AST/ExprCXX.h b/clang/include/clang/AST/ExprCXX.h index d4e0eb83bcc38..2f89b43267b61 100644 --- a/clang/include/clang/AST/ExprCXX.h +++ b/clang/include/clang/AST/ExprCXX.h @@ -4864,7 +4864,7 @@ class BuiltinBitCastExpr final private llvm::TrailingObjects { friend class ASTStmtReader; friend class CastExpr; - friend class TrailingObjects; + friend TrailingObjects; SourceLocation KWLoc; SourceLocation RParenLoc; diff --git a/clang/include/clang/AST/OperationKinds.def b/clang/include/clang/AST/OperationKinds.def index 6daab1ffcb0a0..7c82ab6e57eff 100644 --- a/clang/include/clang/AST/OperationKinds.def +++ b/clang/include/clang/AST/OperationKinds.def @@ -77,9 +77,10 @@ CAST_OPERATION(LValueToRValueBitCast) CAST_OPERATION(LValueToRValue) /// CK_NoOp - A conversion which does not affect the type other than -/// (possibly) adding qualifiers. +/// (possibly) adding qualifiers or removing noexcept. /// int -> int /// char** -> const char * const * +/// void () noexcept -> void () CAST_OPERATION(NoOp) /// CK_BaseToDerived - A conversion from a C++ class pointer/reference diff --git a/clang/include/clang/ASTMatchers/ASTMatchers.h b/clang/include/clang/ASTMatchers/ASTMatchers.h index d8b049f453417..0da469ea0f789 100644 --- a/clang/include/clang/ASTMatchers/ASTMatchers.h +++ b/clang/include/clang/ASTMatchers/ASTMatchers.h @@ -782,7 +782,7 @@ AST_POLYMORPHIC_MATCHER_P( /// \endcode /// The matcher /// \code -/// traverse(TK_IgnoreImplicitCastsAndParentheses, +/// traverse(TK_IgnoreUnlessSpelledInSource, /// varDecl(hasInitializer(floatLiteral().bind("init"))) /// ) /// \endcode diff --git a/clang/include/clang/ASTMatchers/ASTMatchersInternal.h b/clang/include/clang/ASTMatchers/ASTMatchersInternal.h index 480a12b0dafb3..fdc4f66f5d9c7 100644 --- a/clang/include/clang/ASTMatchers/ASTMatchersInternal.h +++ b/clang/include/clang/ASTMatchers/ASTMatchersInternal.h @@ -679,8 +679,7 @@ class ASTMatchFinder { template bool matchesChildOf(const T &Node, const DynTypedMatcher &Matcher, - BoundNodesTreeBuilder *Builder, TraversalKind Traverse, - BindKind Bind) { + BoundNodesTreeBuilder *Builder, BindKind Bind) { static_assert(std::is_base_of::value || std::is_base_of::value || std::is_base_of::value || @@ -689,7 +688,7 @@ class ASTMatchFinder { std::is_base_of::value, "unsupported type for recursive matching"); return matchesChildOf(DynTypedNode::create(Node), getASTContext(), Matcher, - Builder, Traverse, Bind); + Builder, Bind); } template @@ -730,7 +729,7 @@ class ASTMatchFinder { virtual bool matchesChildOf(const DynTypedNode &Node, ASTContext &Ctx, const DynTypedMatcher &Matcher, BoundNodesTreeBuilder *Builder, - TraversalKind Traverse, BindKind Bind) = 0; + BindKind Bind) = 0; virtual bool matchesDescendantOf(const DynTypedNode &Node, ASTContext &Ctx, const DynTypedMatcher &Matcher, @@ -1367,7 +1366,6 @@ class HasMatcher : public MatcherInterface { bool matches(const T &Node, ASTMatchFinder *Finder, BoundNodesTreeBuilder *Builder) const override { return Finder->matchesChildOf(Node, this->InnerMatcher, Builder, - TraversalKind::TK_AsIs, ASTMatchFinder::BK_First); } }; @@ -1392,7 +1390,6 @@ class ForEachMatcher : public MatcherInterface { BoundNodesTreeBuilder *Builder) const override { return Finder->matchesChildOf( Node, this->InnerMatcher, Builder, - TraversalKind::TK_IgnoreImplicitCastsAndParentheses, ASTMatchFinder::BK_All); } }; diff --git a/clang/include/clang/ASTMatchers/ASTMatchersMacros.h b/clang/include/clang/ASTMatchers/ASTMatchersMacros.h index 45e8b1a88b81a..7e01ab0c6ee93 100644 --- a/clang/include/clang/ASTMatchers/ASTMatchersMacros.h +++ b/clang/include/clang/ASTMatchers/ASTMatchersMacros.h @@ -134,8 +134,9 @@ class matcher_##DefineMatcher##OverloadId##Matcher \ : public ::clang::ast_matchers::internal::MatcherInterface { \ public: \ - explicit matcher_##DefineMatcher##OverloadId##Matcher(ParamType A##Param) \ - : Param(std::move(A##Param)) {} \ + explicit matcher_##DefineMatcher##OverloadId##Matcher( \ + ParamType const &A##Param) \ + : Param(A##Param) {} \ bool matches(const Type &Node, \ ::clang::ast_matchers::internal::ASTMatchFinder *Finder, \ ::clang::ast_matchers::internal::BoundNodesTreeBuilder \ @@ -146,13 +147,12 @@ }; \ } \ inline ::clang::ast_matchers::internal::Matcher DefineMatcher( \ - ParamType Param) { \ + ParamType const &Param) { \ return ::clang::ast_matchers::internal::makeMatcher( \ - new internal::matcher_##DefineMatcher##OverloadId##Matcher( \ - std::move(Param))); \ + new internal::matcher_##DefineMatcher##OverloadId##Matcher(Param)); \ } \ - typedef ::clang::ast_matchers::internal::Matcher ( \ - &DefineMatcher##_Type##OverloadId)(ParamType Param); \ + typedef ::clang::ast_matchers::internal::Matcher( \ + &DefineMatcher##_Type##OverloadId)(ParamType const &Param); \ inline bool internal::matcher_##DefineMatcher##OverloadId##Matcher::matches( \ const Type &Node, \ ::clang::ast_matchers::internal::ASTMatchFinder *Finder, \ @@ -183,9 +183,9 @@ class matcher_##DefineMatcher##OverloadId##Matcher \ : public ::clang::ast_matchers::internal::MatcherInterface { \ public: \ - matcher_##DefineMatcher##OverloadId##Matcher(ParamType1 A##Param1, \ - ParamType2 A##Param2) \ - : Param1(std::move(A##Param1)), Param2(std::move(A##Param2)) {} \ + matcher_##DefineMatcher##OverloadId##Matcher(ParamType1 const &A##Param1, \ + ParamType2 const &A##Param2) \ + : Param1(A##Param1), Param2(A##Param2) {} \ bool matches(const Type &Node, \ ::clang::ast_matchers::internal::ASTMatchFinder *Finder, \ ::clang::ast_matchers::internal::BoundNodesTreeBuilder \ @@ -197,14 +197,14 @@ }; \ } \ inline ::clang::ast_matchers::internal::Matcher DefineMatcher( \ - ParamType1 Param1, ParamType2 Param2) { \ + ParamType1 const &Param1, ParamType2 const &Param2) { \ return ::clang::ast_matchers::internal::makeMatcher( \ - new internal::matcher_##DefineMatcher##OverloadId##Matcher( \ - std::move(Param1), std::move(Param2))); \ + new internal::matcher_##DefineMatcher##OverloadId##Matcher(Param1, \ + Param2)); \ } \ - typedef ::clang::ast_matchers::internal::Matcher ( \ - &DefineMatcher##_Type##OverloadId)(ParamType1 Param1, \ - ParamType2 Param2); \ + typedef ::clang::ast_matchers::internal::Matcher( \ + &DefineMatcher##_Type##OverloadId)(ParamType1 const &Param1, \ + ParamType2 const &Param2); \ inline bool internal::matcher_##DefineMatcher##OverloadId##Matcher::matches( \ const Type &Node, \ ::clang::ast_matchers::internal::ASTMatchFinder *Finder, \ @@ -272,8 +272,9 @@ class matcher_##DefineMatcher##OverloadId##Matcher \ : public ::clang::ast_matchers::internal::MatcherInterface { \ public: \ - explicit matcher_##DefineMatcher##OverloadId##Matcher(ParamType A##Param) \ - : Param(std::move(A##Param)) {} \ + explicit matcher_##DefineMatcher##OverloadId##Matcher( \ + ParamType const &A##Param) \ + : Param(A##Param) {} \ bool matches(const NodeType &Node, \ ::clang::ast_matchers::internal::ASTMatchFinder *Finder, \ ::clang::ast_matchers::internal::BoundNodesTreeBuilder \ @@ -286,14 +287,15 @@ inline ::clang::ast_matchers::internal::PolymorphicMatcherWithParam1< \ internal::matcher_##DefineMatcher##OverloadId##Matcher, ParamType, \ ReturnTypesF> \ - DefineMatcher(ParamType Param) { \ + DefineMatcher(ParamType const &Param) { \ return ::clang::ast_matchers::internal::PolymorphicMatcherWithParam1< \ internal::matcher_##DefineMatcher##OverloadId##Matcher, ParamType, \ - ReturnTypesF>(std::move(Param)); \ + ReturnTypesF>(Param); \ } \ typedef ::clang::ast_matchers::internal::PolymorphicMatcherWithParam1< \ internal::matcher_##DefineMatcher##OverloadId##Matcher, ParamType, \ - ReturnTypesF> (&DefineMatcher##_Type##OverloadId)(ParamType Param); \ + ReturnTypesF>(&DefineMatcher##_Type##OverloadId)( \ + ParamType const &Param); \ template \ bool internal:: \ matcher_##DefineMatcher##OverloadId##Matcher::matches( \ @@ -323,9 +325,9 @@ class matcher_##DefineMatcher##OverloadId##Matcher \ : public ::clang::ast_matchers::internal::MatcherInterface { \ public: \ - matcher_##DefineMatcher##OverloadId##Matcher(ParamType1 A##Param1, \ - ParamType2 A##Param2) \ - : Param1(std::move(A##Param1)), Param2(std::move(A##Param2)) {} \ + matcher_##DefineMatcher##OverloadId##Matcher(ParamType1 const &A##Param1, \ + ParamType2 const &A##Param2) \ + : Param1(A##Param1), Param2(A##Param2) {} \ bool matches(const NodeType &Node, \ ::clang::ast_matchers::internal::ASTMatchFinder *Finder, \ ::clang::ast_matchers::internal::BoundNodesTreeBuilder \ @@ -339,15 +341,15 @@ inline ::clang::ast_matchers::internal::PolymorphicMatcherWithParam2< \ internal::matcher_##DefineMatcher##OverloadId##Matcher, ParamType1, \ ParamType2, ReturnTypesF> \ - DefineMatcher(ParamType1 Param1, ParamType2 Param2) { \ + DefineMatcher(ParamType1 const &Param1, ParamType2 const &Param2) { \ return ::clang::ast_matchers::internal::PolymorphicMatcherWithParam2< \ internal::matcher_##DefineMatcher##OverloadId##Matcher, ParamType1, \ - ParamType2, ReturnTypesF>(std::move(Param1), std::move(Param2)); \ + ParamType2, ReturnTypesF>(Param1, Param2); \ } \ typedef ::clang::ast_matchers::internal::PolymorphicMatcherWithParam2< \ internal::matcher_##DefineMatcher##OverloadId##Matcher, ParamType1, \ - ParamType2, ReturnTypesF> (&DefineMatcher##_Type##OverloadId)( \ - ParamType1 Param1, ParamType2 Param2); \ + ParamType2, ReturnTypesF>(&DefineMatcher##_Type##OverloadId)( \ + ParamType1 const &Param1, ParamType2 const &Param2); \ template \ bool internal::matcher_##DefineMatcher##OverloadId##Matcher< \ NodeType, ParamT1, ParamT2>:: \ diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 53a95c1c8c365..51820842e7e62 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -389,6 +389,9 @@ def TargetELF : TargetSpec { let ObjectFormats = ["ELF"]; } +def TargetSupportsInitPriority : TargetSpec { + let CustomCode = [{ !Target.getTriple().isOSzOS() }]; +} // Attribute subject match rules that are used for #pragma clang attribute. // // A instance of AttrSubjectMatcherRule represents an individual match rule. @@ -2798,7 +2801,7 @@ def WorkGroupSizeHint : InheritableAttr { let Documentation = [Undocumented]; } -def InitPriority : InheritableAttr { +def InitPriority : InheritableAttr, TargetSpecificAttr { let Spellings = [GCC<"init_priority", /*AllowInC*/0>]; let Args = [UnsignedArgument<"Priority">]; let Subjects = SubjectList<[Var], ErrorDiag>; diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index 1f58a1ca1a088..7a180ee646b46 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -79,7 +79,7 @@ relative ordering of values is important. For example: initialization being the opposite. This attribute is only supported for C++ and Objective-C++ and is ignored in -other language modes. +other language modes. Currently, this attribute is not implemented on z/OS. }]; } diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def b/clang/include/clang/Basic/BuiltinsAArch64.def index f07c567053dea..c684105908de9 100644 --- a/clang/include/clang/Basic/BuiltinsAArch64.def +++ b/clang/include/clang/Basic/BuiltinsAArch64.def @@ -153,6 +153,11 @@ TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_acq, "LLiLLiD*LLiLLi", "nh", TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_nf, "LLiLLiD*LLiLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedCompareExchange64_rel, "LLiLLiD*LLiLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") +TARGET_HEADER_BUILTIN(_InterlockedCompareExchange128, "UcLLiD*LLiLLiLLi*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") +TARGET_HEADER_BUILTIN(_InterlockedCompareExchange128_acq,"UcLLiD*LLiLLiLLi*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") +TARGET_HEADER_BUILTIN(_InterlockedCompareExchange128_nf ,"UcLLiD*LLiLLiLLi*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") +TARGET_HEADER_BUILTIN(_InterlockedCompareExchange128_rel,"UcLLiD*LLiLLiLLi*", "nh", "intrin.h", ALL_MS_LANGUAGES, "") + TARGET_HEADER_BUILTIN(_InterlockedOr8_acq, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr8_nf, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_InterlockedOr8_rel, "ccD*c", "nh", "intrin.h", ALL_MS_LANGUAGES, "") diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def index 7cd80aa806db5..d90e403915ed3 100644 --- a/clang/include/clang/Basic/CodeGenOptions.def +++ b/clang/include/clang/Basic/CodeGenOptions.def @@ -49,6 +49,7 @@ CODEGENOPT(UniqueSectionNames, 1, 1) ///< Set for -funique-section-names. CODEGENOPT(UniqueBasicBlockSectionNames, 1, 1) ///< Set for -funique-basic-block-section-names, ///< Produce unique section names with ///< basic block sections. +CODEGENOPT(EnableAIXExtendedAltivecABI, 1, 0) ///< Set for -mabi=vec-extabi. Enables the extended Altivec ABI on AIX. ENUM_CODEGENOPT(FramePointer, FramePointerKind, 2, FramePointerKind::None) /// frame-pointer: all,non-leaf,none CODEGENOPT(DisableFree , 1, 0) ///< Don't free memory. diff --git a/clang/include/clang/Basic/CodeGenOptions.h b/clang/include/clang/Basic/CodeGenOptions.h index 6452d2bb25f63..e710c5792d762 100644 --- a/clang/include/clang/Basic/CodeGenOptions.h +++ b/clang/include/clang/Basic/CodeGenOptions.h @@ -211,9 +211,6 @@ class CodeGenOptions : public CodeGenOptionsBase { /// The name of the relocation model to use. llvm::Reloc::Model RelocationModel; - /// The thread model to use - std::string ThreadModel; - /// If not an empty string, trap intrinsics are lowered to calls to this /// function instead of to trap instructions. std::string TrapFuncName; diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td index 63384f0dc44f5..786545169fb29 100644 --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -554,4 +554,9 @@ def err_drv_invalid_object_mode : Error<"OBJECT_MODE setting %0 is not recognize def err_drv_invalid_sve_vector_bits : Error< "'-msve-vector-bits' is not supported without SVE enabled">; + +def err_aix_default_altivec_abi : Error< + "The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' for the extended Altivec ABI">; + +def err_aix_altivec : Error<"'-mabi=vec-extabi' and '-mabi=vec-default' require '-maltivec'">; } diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index a0eaf8d7bdb3c..b9119ae78de2f 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -8683,6 +8683,8 @@ def err_ambiguous_member_multiple_subobjects : Error< def err_ambiguous_member_multiple_subobject_types : Error< "member %0 found in multiple base classes of different types">; def note_ambiguous_member_found : Note<"member found by ambiguous name lookup">; +def note_ambiguous_member_type_found : Note< + "member type %0 found by ambiguous name lookup">; def err_ambiguous_reference : Error<"reference to %0 is ambiguous">; def note_ambiguous_candidate : Note<"candidate found by name lookup is %q0">; def err_ambiguous_tag_hiding : Error<"a type named %0 is hidden by a " diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def index 68aadd84060a0..60589216e4975 100644 --- a/clang/include/clang/Basic/LangOptions.def +++ b/clang/include/clang/Basic/LangOptions.def @@ -148,8 +148,8 @@ LANGOPT(RelaxedTemplateTemplateArgs, 1, 0, "C++17 relaxed matching of template t LANGOPT(DoubleSquareBracketAttributes, 1, 0, "'[[]]' attributes extension for all language standard modes") -COMPATIBLE_LANGOPT(RecoveryAST, 1, 0, "Preserve expressions in AST when encountering errors") -COMPATIBLE_LANGOPT(RecoveryASTType, 1, 0, "Preserve the type in recovery expressions") +COMPATIBLE_LANGOPT(RecoveryAST, 1, 1, "Preserve expressions in AST when encountering errors") +COMPATIBLE_LANGOPT(RecoveryASTType, 1, 1, "Preserve the type in recovery expressions") BENIGN_LANGOPT(ThreadsafeStatics , 1, 1, "thread-safe static initializers") LANGOPT(POSIXThreads , 1, 0, "POSIX thread support") @@ -183,6 +183,7 @@ VALUE_LANGOPT(AlignDouble , 1, 0, "Controls if doubles should be alig VALUE_LANGOPT(DoubleSize , 32, 0, "width of double") VALUE_LANGOPT(LongDoubleSize , 32, 0, "width of long double") LANGOPT(PPCIEEELongDouble , 1, 0, "use IEEE 754 quadruple-precision for long double") +LANGOPT(EnableAIXExtendedAltivecABI , 1, 0, "__EXTABI__ predefined macro") COMPATIBLE_VALUE_LANGOPT(PICLevel , 2, 0, "__PIC__ level") COMPATIBLE_VALUE_LANGOPT(PIE , 1, 0, "is pie") LANGOPT(ROPI , 1, 0, "Read-only position independence") @@ -342,6 +343,7 @@ VALUE_LANGOPT(TrivialAutoVarInitStopAfter, 32, 0, "stop trivial automatic variable initialization after the specified number of instances. Must be greater than 0.") ENUM_LANGOPT(SignedOverflowBehavior, SignedOverflowBehaviorTy, 2, SOB_Undefined, "signed integer overflow handling") +ENUM_LANGOPT(ThreadModel , ThreadModelKind, 2, ThreadModelKind::POSIX, "Thread Model") BENIGN_LANGOPT(ArrowDepth, 32, 256, "maximum number of operator->s to follow") diff --git a/clang/include/clang/Basic/LangOptions.h b/clang/include/clang/Basic/LangOptions.h index bcbdce1e33e8f..a91431d7eca41 100644 --- a/clang/include/clang/Basic/LangOptions.h +++ b/clang/include/clang/Basic/LangOptions.h @@ -160,7 +160,8 @@ class LangOptions : public LangOptionsBase { /// Attempt to be ABI-compatible with code generated by Clang 11.0.x /// (git 2e10b7a39b93). This causes clang to pass unions with a 256-bit - /// vector member on the stack instead of using registers. + /// vector member on the stack instead of using registers, and to not + /// properly mangle substitutions for template names in some cases. Ver11, /// Conform to the underlying platform's C and C++ ABIs as closely @@ -192,8 +193,11 @@ class LangOptions : public LangOptionsBase { // Enable the floating point pragma FPM_On, - // Aggressively fuse FP ops (E.g. FMA). - FPM_Fast + // Aggressively fuse FP ops (E.g. FMA) disregarding pragmas. + FPM_Fast, + + // Aggressively fuse FP ops and honor pragmas. + FPM_FastHonorPragmas }; /// Alias for RoundingMode::NearestTiesToEven. @@ -237,6 +241,13 @@ class LangOptions : public LangOptionsBase { BKey }; + enum class ThreadModelKind { + /// POSIX Threads. + POSIX, + /// Single Threaded Environment. + Single + }; + public: /// Set of enabled sanitizers. SanitizerSet Sanitize; @@ -418,7 +429,13 @@ class FPOptions { } explicit FPOptions(const LangOptions &LO) { Value = 0; - setFPContractMode(LO.getDefaultFPContractMode()); + // The language fp contract option FPM_FastHonorPragmas has the same effect + // as FPM_Fast in frontend. For simplicity, use FPM_Fast uniformly in + // frontend. + auto LangOptContractMode = LO.getDefaultFPContractMode(); + if (LangOptContractMode == LangOptions::FPM_FastHonorPragmas) + LangOptContractMode = LangOptions::FPM_Fast; + setFPContractMode(LangOptContractMode); setRoundingMode(LO.getFPRoundingMode()); setFPExceptionMode(LO.getFPExceptionMode()); setAllowFPReassociate(LO.AllowFPReassoc); diff --git a/clang/include/clang/Basic/OpenCLOptions.h b/clang/include/clang/Basic/OpenCLOptions.h index 15661154eab54..66dd06db5b837 100644 --- a/clang/include/clang/Basic/OpenCLOptions.h +++ b/clang/include/clang/Basic/OpenCLOptions.h @@ -32,38 +32,71 @@ class OpenCLOptions { }; llvm::StringMap OptMap; public: + /// Check if \c Ext is a recognized OpenCL extension. + /// + /// \param Ext - Extension to look up. + /// \returns \c true if \c Ext is known, \c false otherwise. bool isKnown(llvm::StringRef Ext) const { return OptMap.find(Ext) != OptMap.end(); } + /// Check if \c Ext is an enabled OpenCL extension. + /// + /// \param Ext - Extension to look up. + /// \returns \c true if \c Ext is known and enabled, \c false otherwise. bool isEnabled(llvm::StringRef Ext) const { - return OptMap.find(Ext)->second.Enabled; + auto E = OptMap.find(Ext); + return E != OptMap.end() && E->second.Enabled; } - // Is supported as either an extension or an (optional) core feature for - // OpenCL version \p CLVer. + /// Check if \c Ext is supported as either an extension or an (optional) core + /// feature for the given OpenCL version. + /// + /// \param Ext - Extension to look up. + /// \param LO - \c LangOptions specifying the OpenCL version. + /// \returns \c true if \c Ext is known and supported, \c false otherwise. bool isSupported(llvm::StringRef Ext, const LangOptions &LO) const { + auto E = OptMap.find(Ext); + if (E == OptMap.end()) { + return false; + } // In C++ mode all extensions should work at least as in v2.0. auto CLVer = LO.OpenCLCPlusPlus ? 200 : LO.OpenCLVersion; - auto I = OptMap.find(Ext)->getValue(); + auto I = E->getValue(); return I.Supported && I.Avail <= CLVer; } - // Is supported (optional) OpenCL core features for OpenCL version \p CLVer. - // For supported extension, return false. + /// Check if \c Ext is supported as an (optional) OpenCL core features for + /// the given OpenCL version. + /// + /// \param Ext - Extension to look up. + /// \param LO - \c LangOptions specifying the OpenCL version. + /// \returns \c true if \c Ext is known and supported, \c false otherwise. bool isSupportedCore(llvm::StringRef Ext, const LangOptions &LO) const { + auto E = OptMap.find(Ext); + if (E == OptMap.end()) { + return false; + } // In C++ mode all extensions should work at least as in v2.0. auto CLVer = LO.OpenCLCPlusPlus ? 200 : LO.OpenCLVersion; - auto I = OptMap.find(Ext)->getValue(); + auto I = E->getValue(); return I.Supported && I.Avail <= CLVer && I.Core != ~0U && CLVer >= I.Core; } - // Is supported OpenCL extension for OpenCL version \p CLVer. - // For supported (optional) core feature, return false. + /// Check if \c Ext is a supported OpenCL extension for the given OpenCL + /// version. + /// + /// \param Ext - Extension to look up. + /// \param LO - \c LangOptions specifying the OpenCL version. + /// \returns \c true if \c Ext is known and supported, \c false otherwise. bool isSupportedExtension(llvm::StringRef Ext, const LangOptions &LO) const { + auto E = OptMap.find(Ext); + if (E == OptMap.end()) { + return false; + } // In C++ mode all extensions should work at least as in v2.0. auto CLVer = LO.OpenCLCPlusPlus ? 200 : LO.OpenCLVersion; - auto I = OptMap.find(Ext)->getValue(); + auto I = E->getValue(); return I.Supported && I.Avail <= CLVer && (I.Core == ~0U || CLVer < I.Core); } diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index d2027d5f8e0d2..67c439f5ec75e 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -713,7 +713,8 @@ defm gpu_rdc : OptInFFlag<"gpu-rdc", def : Flag<["-"], "fcuda-rdc">, Alias; def : Flag<["-"], "fno-cuda-rdc">, Alias; defm cuda_short_ptr : OptInFFlag<"cuda-short-ptr", - "Use 32-bit pointers for accessing const/local/shared address spaces">; + "Use 32-bit pointers for accessing const/local/shared address spaces", "", "", + [], "TargetOpts->NVPTXUseShortPointers">; def rocm_path_EQ : Joined<["--"], "rocm-path=">, Group, HelpText<"ROCm installation path, used for finding and automatically linking required bitcode libraries.">; def rocm_device_lib_path_EQ : Joined<["--"], "rocm-device-lib-path=">, Group, @@ -1069,7 +1070,7 @@ def fbracket_depth_EQ : Joined<["-"], "fbracket-depth=">, Group, Flags< def fsignaling_math : Flag<["-"], "fsignaling-math">, Group; def fno_signaling_math : Flag<["-"], "fno-signaling-math">, Group; defm jump_tables : OptOutFFlag<"jump-tables", "Use", "Do not use", " jump tables for lowering switches">; -defm force_enable_int128 : OptInFFlag<"force-enable-int128", "Enable", "Disable", " support for int128_t type">; +defm force_enable_int128 : OptInFFlag<"force-enable-int128", "Enable", "Disable", " support for int128_t type", [], "TargetOpts->ForceEnableInt128">; defm keep_static_consts : OptInFFlag<"keep-static-consts", "Keep", "Don't keep", " static const variables if unused", [NoXarchOption]>; defm fixed_point : OptInFFlag<"fixed-point", "Enable", "Disable", " fixed point types">; defm cxx_static_destructors : OptOutFFlag<"c++-static-destructors", "", @@ -1296,9 +1297,13 @@ def fno_rounding_math : Flag<["-"], "fno-rounding-math">, Group, Flags< def ftrapping_math : Flag<["-"], "ftrapping-math">, Group, Flags<[CC1Option]>; def fno_trapping_math : Flag<["-"], "fno-trapping-math">, Group, Flags<[CC1Option]>; def ffp_contract : Joined<["-"], "ffp-contract=">, Group, - Flags<[CC1Option]>, HelpText<"Form fused FP ops (e.g. FMAs): fast (everywhere)" - " | on (according to FP_CONTRACT pragma) | off (never fuse). Default" - " is 'fast' for CUDA/HIP and 'on' otherwise.">, Values<"fast,on,off">; + Flags<[CC1Option]>, HelpText<"Form fused FP ops (e.g. FMAs):" + " fast (fuses across statements disregarding pragmas)" + " | on (only fuses in the same statement unless dictated by pragmas)" + " | off (never fuses)" + " | fast-honor-pragmas (fuses across statements unless diectated by pragmas)." + " Default is 'fast' for CUDA, 'fast-honor-pragmas' for HIP, and 'on' otherwise.">, + Values<"fast,on,off,fast-honor-pragmas">; defm strict_float_cast_overflow : OptOutFFlag<"strict-float-cast-overflow", "Assume that overflowing float-to-int casts are undefined (default)", @@ -2626,6 +2631,10 @@ def mpcrel: Flag<["-"], "mpcrel">, Group; def mno_pcrel: Flag<["-"], "mno-pcrel">, Group; def mspe : Flag<["-"], "mspe">, Group; def mno_spe : Flag<["-"], "mno-spe">, Group; +def mabi_EQ_vec_extabi : Flag<["-"], "mabi=vec-extabi">, Group, Flags<[CC1Option]>, + HelpText<"Enable the extended Altivec ABI on AIX (AIX only). Uses volatile and nonvolatile vector registers">; +def mabi_EQ_vec_default : Flag<["-"], "mabi=vec-default">, Group, Flags<[CC1Option]>, + HelpText<"Enable the default Altivec ABI on AIX (AIX only). Uses only volatile vector registers.">; def mvsx : Flag<["-"], "mvsx">, Group; def mno_vsx : Flag<["-"], "mno-vsx">, Group; def msecure_plt : Flag<["-"], "msecure-plt">, Group; diff --git a/clang/include/clang/Driver/ToolChain.h b/clang/include/clang/Driver/ToolChain.h index f55251acdc16a..2c6eb51bf80c6 100644 --- a/clang/include/clang/Driver/ToolChain.h +++ b/clang/include/clang/Driver/ToolChain.h @@ -342,7 +342,14 @@ class ToolChain { /// Returns the linker path, respecting the -fuse-ld= argument to determine /// the linker suffix or name. - std::string GetLinkerPath() const; + /// If LinkerIsLLD is non-nullptr, it is set to true if the returned linker + /// is LLD. If it's set, it can be assumed that the linker is LLD built + /// at the same revision as clang, and clang can make assumptions about + /// LLD's supported flags, error output, etc. + /// If LinkerIsLLDDarwinNew is non-nullptr, it's set if the linker is + /// the new version in lld/MachO. + std::string GetLinkerPath(bool *LinkerIsLLD = nullptr, + bool *LinkerIsLLDDarwinNew = nullptr) const; /// Returns the linker path for emitting a static library. std::string GetStaticLibToolPath() const; diff --git a/clang/include/clang/Sema/DeclSpec.h b/clang/include/clang/Sema/DeclSpec.h index d2acafc2e4b31..afcbbaa5cfa7d 100644 --- a/clang/include/clang/Sema/DeclSpec.h +++ b/clang/include/clang/Sema/DeclSpec.h @@ -1748,11 +1748,11 @@ class DecompositionDeclarator { /// Described the kind of function definition (if any) provided for /// a function. -enum FunctionDefinitionKind { - FDK_Declaration, - FDK_Definition, - FDK_Defaulted, - FDK_Deleted +enum class FunctionDefinitionKind { + Declaration, + Definition, + Defaulted, + Deleted }; enum class DeclaratorContext { @@ -1888,7 +1888,8 @@ class Declarator { Declarator(const DeclSpec &ds, DeclaratorContext C) : DS(ds), Range(ds.getSourceRange()), Context(C), InvalidType(DS.getTypeSpecType() == DeclSpec::TST_error), - GroupingParens(false), FunctionDefinition(FDK_Declaration), + GroupingParens(false), FunctionDefinition(static_cast( + FunctionDefinitionKind::Declaration)), Redeclaration(false), Extension(false), ObjCIvar(false), ObjCWeakProperty(false), InlineStorageUsed(false), Attrs(ds.getAttributePool().getFactory()), AsmLabel(nullptr), @@ -2562,11 +2563,11 @@ class Declarator { void setEllipsisLoc(SourceLocation EL) { EllipsisLoc = EL; } void setFunctionDefinitionKind(FunctionDefinitionKind Val) { - FunctionDefinition = Val; + FunctionDefinition = static_cast(Val); } bool isFunctionDefinition() const { - return getFunctionDefinitionKind() != FDK_Declaration; + return getFunctionDefinitionKind() != FunctionDefinitionKind::Declaration; } FunctionDefinitionKind getFunctionDefinitionKind() const { diff --git a/clang/include/clang/Sema/Initialization.h b/clang/include/clang/Sema/Initialization.h index 6976e7c95c8b2..2245c15050017 100644 --- a/clang/include/clang/Sema/Initialization.h +++ b/clang/include/clang/Sema/Initialization.h @@ -840,6 +840,9 @@ class InitializationSequence { /// Perform a qualification conversion, producing an lvalue. SK_QualificationConversionLValue, + /// Perform a function reference conversion, see [dcl.init.ref]p4. + SK_FunctionReferenceConversion, + /// Perform a conversion adding _Atomic to a type. SK_AtomicConversion, @@ -1288,6 +1291,10 @@ class InitializationSequence { void AddQualificationConversionStep(QualType Ty, ExprValueKind Category); + /// Add a new step that performs a function reference conversion to the + /// given type. + void AddFunctionReferenceConversionStep(QualType Ty); + /// Add a new step that performs conversion from non-atomic to atomic /// type. void AddAtomicConversionStep(QualType Ty); diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index cc49a9994b21b..f386fbbe3c097 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -7416,9 +7416,9 @@ class Sema final { /// considered valid results. /// \param AllowDependent Whether unresolved using declarations (that might /// name templates) should be considered valid results. - NamedDecl *getAsTemplateNameDecl(NamedDecl *D, - bool AllowFunctionTemplates = true, - bool AllowDependent = true); + static NamedDecl *getAsTemplateNameDecl(NamedDecl *D, + bool AllowFunctionTemplates = true, + bool AllowDependent = true); enum TemplateNameIsRequiredTag { TemplateNameIsRequired }; /// Whether and why a template name is required in this lookup. diff --git a/clang/include/clang/Tooling/Transformer/RangeSelector.h b/clang/include/clang/Tooling/Transformer/RangeSelector.h index e070c0e7e2e6b..c6ca193123d15 100644 --- a/clang/include/clang/Tooling/Transformer/RangeSelector.h +++ b/clang/include/clang/Tooling/Transformer/RangeSelector.h @@ -61,8 +61,8 @@ inline RangeSelector between(RangeSelector R1, RangeSelector R2) { return enclose(after(std::move(R1)), before(std::move(R2))); } -/// Selects a node, including trailing semicolon (for non-expression -/// statements). \p ID is the node's binding in the match result. +/// Selects a node, including trailing semicolon, if any (for declarations and +/// non-expression statements). \p ID is the node's binding in the match result. RangeSelector node(std::string ID); /// Selects a node, including trailing semicolon (always). Useful for selecting diff --git a/clang/lib/APINotes/APINotesTypes.cpp b/clang/lib/APINotes/APINotesTypes.cpp new file mode 100644 index 0000000000000..f443d90effb30 --- /dev/null +++ b/clang/lib/APINotes/APINotesTypes.cpp @@ -0,0 +1,107 @@ +//===-- APINotesTypes.cpp - API Notes Data Types ----------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "clang/APINotes/Types.h" +#include "llvm/Support/raw_ostream.h" + +namespace clang { +namespace api_notes { +void CommonEntityInfo::dump(llvm::raw_ostream &OS) { + if (Unavailable) + OS << "[Unavailable] (" << UnavailableMsg << ")" << ' '; + if (UnavailableInSwift) + OS << "[UnavailableInSwift] "; + if (SwiftPrivateSpecified) + OS << (SwiftPrivate ? "[SwiftPrivate] " : ""); + if (!SwiftName.empty()) + OS << "Swift Name: " << SwiftName << ' '; + OS << '\n'; +} + +void CommonTypeInfo::dump(llvm::raw_ostream &OS) { + static_cast(*this).dump(OS); + if (SwiftBridge) + OS << "Swift Briged Type: " << *SwiftBridge << ' '; + if (NSErrorDomain) + OS << "NSError Domain: " << *NSErrorDomain << ' '; + OS << '\n'; +} + +void ObjCContextInfo::dump(llvm::raw_ostream &OS) { + static_cast(*this).dump(OS); + if (HasDefaultNullability) + OS << "DefaultNullability: " << DefaultNullability << ' '; + if (HasDesignatedInits) + OS << "[HasDesignatedInits] "; + if (SwiftImportAsNonGenericSpecified) + OS << (SwiftImportAsNonGeneric ? "[SwiftImportAsNonGeneric] " : ""); + if (SwiftObjCMembersSpecified) + OS << (SwiftObjCMembers ? "[SwiftObjCMembers] " : ""); + OS << '\n'; +} + +void VariableInfo::dump(llvm::raw_ostream &OS) { + static_cast(*this).dump(OS); + if (NullabilityAudited) + OS << "Audited Nullability: " << Nullable << ' '; + if (!Type.empty()) + OS << "C Type: " << Type << ' '; + OS << '\n'; +} + +void ObjCPropertyInfo::dump(llvm::raw_ostream &OS) { + static_cast(*this).dump(OS); + if (SwiftImportAsAccessorsSpecified) + OS << (SwiftImportAsAccessors ? "[SwiftImportAsAccessors] " : ""); + OS << '\n'; +} + +void ParamInfo::dump(llvm::raw_ostream &OS) { + static_cast(*this).dump(OS); + if (NoEscapeSpecified) + OS << (NoEscape ? "[NoEscape] " : ""); + OS << "RawRetainCountConvention: " << RawRetainCountConvention << ' '; + OS << '\n'; +} + +void FunctionInfo::dump(llvm::raw_ostream &OS) { + static_cast(*this).dump(OS); + OS << (NullabilityAudited ? "[NullabilityAudited] " : "") + << "RawRetainCountConvention: " << RawRetainCountConvention << ' '; + if (!ResultType.empty()) + OS << "Result Type: " << ResultType << ' '; + if (!Params.empty()) + OS << '\n'; + for (auto &PI : Params) + PI.dump(OS); +} + +void ObjCMethodInfo::dump(llvm::raw_ostream &OS) { + static_cast(*this).dump(OS); + OS << (DesignatedInit ? "[DesignatedInit] " : "") + << (RequiredInit ? "[RequiredInit] " : "") << '\n'; +} + +void TagInfo::dump(llvm::raw_ostream &OS) { + static_cast(*this).dump(OS); + if (HasFlagEnum) + OS << (IsFlagEnum ? "[FlagEnum] " : ""); + if (EnumExtensibility) + OS << "Enum Extensibility: " << static_cast(*EnumExtensibility) + << ' '; + OS << '\n'; +} + +void TypedefInfo::dump(llvm::raw_ostream &OS) { + static_cast(*this).dump(OS); + if (SwiftWrapper) + OS << "Swift Type: " << static_cast(*SwiftWrapper) << ' '; + OS << '\n'; +} +} // namespace api_notes +} // namespace clang diff --git a/clang/lib/APINotes/CMakeLists.txt b/clang/lib/APINotes/CMakeLists.txt index 3ce511a0de223..3fd0e976ab780 100644 --- a/clang/lib/APINotes/CMakeLists.txt +++ b/clang/lib/APINotes/CMakeLists.txt @@ -1,6 +1,7 @@ set(LLVM_LINK_COMPONENTS Support) add_clang_library(clangAPINotes + APINotesTypes.cpp APINotesYAMLCompiler.cpp LINK_LIBS clangBasic) diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index 2147a50ea5fa7..28bbaa3938f27 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -8609,10 +8609,20 @@ bool ASTContext::areLaxCompatibleSveTypes(QualType FirstType, const auto *VecTy = SecondType->getAs(); if (VecTy && - VecTy->getVectorKind() == VectorType::SveFixedLengthDataVector) { + (VecTy->getVectorKind() == VectorType::SveFixedLengthDataVector || + VecTy->getVectorKind() == VectorType::GenericVector)) { const LangOptions::LaxVectorConversionKind LVCKind = getLangOpts().getLaxVectorConversions(); + // If __ARM_FEATURE_SVE_BITS != N do not allow GNU vector lax conversion. + // "Whenever __ARM_FEATURE_SVE_BITS==N, GNUT implicitly + // converts to VLAT and VLAT implicitly converts to GNUT." + // ACLE Spec Version 00bet6, 3.7.3.2. Behavior common to vectors and + // predicates. + if (VecTy->getVectorKind() == VectorType::GenericVector && + getTypeSize(SecondType) != getLangOpts().ArmSveVectorBits) + return false; + // If -flax-vector-conversions=all is specified, the types are // certainly compatible. if (LVCKind == LangOptions::LaxVectorConversionKind::All) diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp index 486529ef9d8d5..c09b3ea493a29 100644 --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -5164,8 +5164,6 @@ ASTNodeImporter::VisitTemplateTypeParmDecl(TemplateTypeParmDecl *D) { // context. This context will be fixed when the actual template declaration // is created. - // FIXME: Import default argument and constraint expression. - ExpectedSLoc BeginLocOrErr = import(D->getBeginLoc()); if (!BeginLocOrErr) return BeginLocOrErr.takeError(); @@ -5212,6 +5210,14 @@ ASTNodeImporter::VisitTemplateTypeParmDecl(TemplateTypeParmDecl *D) { ToIDC); } + if (D->hasDefaultArgument()) { + Expected ToDefaultArgOrErr = + import(D->getDefaultArgumentInfo()); + if (!ToDefaultArgOrErr) + return ToDefaultArgOrErr.takeError(); + ToD->setDefaultArgument(*ToDefaultArgOrErr); + } + return ToD; } @@ -5227,15 +5233,22 @@ ASTNodeImporter::VisitNonTypeTemplateParmDecl(NonTypeTemplateParmDecl *D) { if (Err) return std::move(Err); - // FIXME: Import default argument. - NonTypeTemplateParmDecl *ToD = nullptr; - (void)GetImportedOrCreateDecl( - ToD, D, Importer.getToContext(), - Importer.getToContext().getTranslationUnitDecl(), - ToInnerLocStart, ToLocation, D->getDepth(), - D->getPosition(), ToDeclName.getAsIdentifierInfo(), ToType, - D->isParameterPack(), ToTypeSourceInfo); + if (GetImportedOrCreateDecl(ToD, D, Importer.getToContext(), + Importer.getToContext().getTranslationUnitDecl(), + ToInnerLocStart, ToLocation, D->getDepth(), + D->getPosition(), + ToDeclName.getAsIdentifierInfo(), ToType, + D->isParameterPack(), ToTypeSourceInfo)) + return ToD; + + if (D->hasDefaultArgument()) { + ExpectedExpr ToDefaultArgOrErr = import(D->getDefaultArgument()); + if (!ToDefaultArgOrErr) + return ToDefaultArgOrErr.takeError(); + ToD->setDefaultArgument(*ToDefaultArgOrErr); + } + return ToD; } @@ -5256,15 +5269,22 @@ ASTNodeImporter::VisitTemplateTemplateParmDecl(TemplateTemplateParmDecl *D) { if (!TemplateParamsOrErr) return TemplateParamsOrErr.takeError(); - // FIXME: Import default argument. - TemplateTemplateParmDecl *ToD = nullptr; - (void)GetImportedOrCreateDecl( - ToD, D, Importer.getToContext(), - Importer.getToContext().getTranslationUnitDecl(), *LocationOrErr, - D->getDepth(), D->getPosition(), D->isParameterPack(), - (*NameOrErr).getAsIdentifierInfo(), - *TemplateParamsOrErr); + if (GetImportedOrCreateDecl( + ToD, D, Importer.getToContext(), + Importer.getToContext().getTranslationUnitDecl(), *LocationOrErr, + D->getDepth(), D->getPosition(), D->isParameterPack(), + (*NameOrErr).getAsIdentifierInfo(), *TemplateParamsOrErr)) + return ToD; + + if (D->hasDefaultArgument()) { + Expected ToDefaultArgOrErr = + import(D->getDefaultArgument()); + if (!ToDefaultArgOrErr) + return ToDefaultArgOrErr.takeError(); + ToD->setDefaultArgument(Importer.getToContext(), *ToDefaultArgOrErr); + } + return ToD; } @@ -5429,8 +5449,9 @@ ExpectedDecl ASTNodeImporter::VisitClassTemplateSpecializationDecl( if (PrevDecl) { if (IsStructuralMatch(D, PrevDecl)) { - if (D->isThisDeclarationADefinition() && PrevDecl->getDefinition()) { - Importer.MapImported(D, PrevDecl->getDefinition()); + CXXRecordDecl *PrevDefinition = PrevDecl->getDefinition(); + if (D->isThisDeclarationADefinition() && PrevDefinition) { + Importer.MapImported(D, PrevDefinition); // Import those default field initializers which have been // instantiated in the "From" context, but not in the "To" context. for (auto *FromField : D->fields()) { @@ -5452,7 +5473,7 @@ ExpectedDecl ASTNodeImporter::VisitClassTemplateSpecializationDecl( // // Generally, ASTCommon.h/DeclUpdateKind enum gives a very good hint // what else could be fused during an AST merge. - return PrevDecl; + return PrevDefinition; } } else { // ODR violation. // FIXME HandleNameConflict diff --git a/clang/lib/AST/CXXInheritance.cpp b/clang/lib/AST/CXXInheritance.cpp index 8af97119e3cf9..816b5d10773a6 100644 --- a/clang/lib/AST/CXXInheritance.cpp +++ b/clang/lib/AST/CXXInheritance.cpp @@ -402,54 +402,45 @@ bool CXXRecordDecl::FindVirtualBaseClass(const CXXBaseSpecifier *Specifier, ->getCanonicalDecl() == BaseRecord; } -bool CXXRecordDecl::FindTagMember(const CXXBaseSpecifier *Specifier, - CXXBasePath &Path, - DeclarationName Name) { - RecordDecl *BaseRecord = - Specifier->getType()->castAs()->getDecl(); - - for (Path.Decls = BaseRecord->lookup(Name); - !Path.Decls.empty(); - Path.Decls = Path.Decls.slice(1)) { - if (Path.Decls.front()->isInIdentifierNamespace(IDNS_Tag)) - return true; - } - - return false; +static bool isOrdinaryMember(const NamedDecl *ND) { + return ND->isInIdentifierNamespace(Decl::IDNS_Ordinary | Decl::IDNS_Tag | + Decl::IDNS_Member); } -static bool findOrdinaryMember(RecordDecl *BaseRecord, CXXBasePath &Path, +static bool findOrdinaryMember(const CXXRecordDecl *RD, CXXBasePath &Path, DeclarationName Name) { - const unsigned IDNS = Decl::IDNS_Ordinary | Decl::IDNS_Tag | - Decl::IDNS_Member; - for (Path.Decls = BaseRecord->lookup(Name); - !Path.Decls.empty(); - Path.Decls = Path.Decls.slice(1)) { - if (Path.Decls.front()->isInIdentifierNamespace(IDNS)) + Path.Decls = RD->lookup(Name); + for (NamedDecl *ND : Path.Decls) + if (isOrdinaryMember(ND)) return true; - } return false; } -bool CXXRecordDecl::FindOrdinaryMember(const CXXBaseSpecifier *Specifier, - CXXBasePath &Path, - DeclarationName Name) { - RecordDecl *BaseRecord = - Specifier->getType()->castAs()->getDecl(); - return findOrdinaryMember(BaseRecord, Path, Name); +bool CXXRecordDecl::hasMemberName(DeclarationName Name) const { + CXXBasePath P; + if (findOrdinaryMember(this, P, Name)) + return true; + + CXXBasePaths Paths(false, false, false); + return lookupInBases( + [Name](const CXXBaseSpecifier *Specifier, CXXBasePath &Path) { + return findOrdinaryMember(Specifier->getType()->getAsCXXRecordDecl(), + Path, Name); + }, + Paths); } -bool CXXRecordDecl::FindOrdinaryMemberInDependentClasses( - const CXXBaseSpecifier *Specifier, CXXBasePath &Path, - DeclarationName Name) { +static bool +findOrdinaryMemberInDependentClasses(const CXXBaseSpecifier *Specifier, + CXXBasePath &Path, DeclarationName Name) { const TemplateSpecializationType *TST = Specifier->getType()->getAs(); if (!TST) { auto *RT = Specifier->getType()->getAs(); if (!RT) return false; - return findOrdinaryMember(RT->getDecl(), Path, Name); + return findOrdinaryMember(cast(RT->getDecl()), Path, Name); } TemplateName TN = TST->getTemplateName(); const auto *TD = dyn_cast_or_null(TN.getAsTemplateDecl()); @@ -461,80 +452,32 @@ bool CXXRecordDecl::FindOrdinaryMemberInDependentClasses( return findOrdinaryMember(RD, Path, Name); } -bool CXXRecordDecl::FindOMPReductionMember(const CXXBaseSpecifier *Specifier, - CXXBasePath &Path, - DeclarationName Name) { - RecordDecl *BaseRecord = - Specifier->getType()->castAs()->getDecl(); - - for (Path.Decls = BaseRecord->lookup(Name); !Path.Decls.empty(); - Path.Decls = Path.Decls.slice(1)) { - if (Path.Decls.front()->isInIdentifierNamespace(IDNS_OMPReduction)) - return true; - } - - return false; -} - -bool CXXRecordDecl::FindOMPMapperMember(const CXXBaseSpecifier *Specifier, - CXXBasePath &Path, - DeclarationName Name) { - RecordDecl *BaseRecord = - Specifier->getType()->castAs()->getDecl(); - - for (Path.Decls = BaseRecord->lookup(Name); !Path.Decls.empty(); - Path.Decls = Path.Decls.slice(1)) { - if (Path.Decls.front()->isInIdentifierNamespace(IDNS_OMPMapper)) - return true; - } - - return false; -} - -bool CXXRecordDecl:: -FindNestedNameSpecifierMember(const CXXBaseSpecifier *Specifier, - CXXBasePath &Path, - DeclarationName Name) { - RecordDecl *BaseRecord = - Specifier->getType()->castAs()->getDecl(); - - for (Path.Decls = BaseRecord->lookup(Name); - !Path.Decls.empty(); - Path.Decls = Path.Decls.slice(1)) { - // FIXME: Refactor the "is it a nested-name-specifier?" check - if (isa(Path.Decls.front()) || - Path.Decls.front()->isInIdentifierNamespace(IDNS_Tag)) - return true; - } - - return false; -} - std::vector CXXRecordDecl::lookupDependentName( - const DeclarationName &Name, + DeclarationName Name, llvm::function_ref Filter) { std::vector Results; // Lookup in the class. - DeclContext::lookup_result DirectResult = lookup(Name); - if (!DirectResult.empty()) { - for (const NamedDecl *ND : DirectResult) { - if (Filter(ND)) - Results.push_back(ND); - } - return Results; + bool AnyOrdinaryMembers = false; + for (const NamedDecl *ND : lookup(Name)) { + if (isOrdinaryMember(ND)) + AnyOrdinaryMembers = true; + if (Filter(ND)) + Results.push_back(ND); } + if (AnyOrdinaryMembers) + return Results; + // Perform lookup into our base classes. CXXBasePaths Paths; Paths.setOrigin(this); if (!lookupInBases( [&](const CXXBaseSpecifier *Specifier, CXXBasePath &Path) { - return CXXRecordDecl::FindOrdinaryMemberInDependentClasses( - Specifier, Path, Name); + return findOrdinaryMemberInDependentClasses(Specifier, Path, Name); }, Paths, /*LookupInDependent=*/true)) return Results; for (const NamedDecl *ND : Paths.front().Decls) { - if (Filter(ND)) + if (isOrdinaryMember(ND) && Filter(ND)) Results.push_back(ND); } return Results; diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp index 68fd46547bd5b..36fc798131162 100644 --- a/clang/lib/AST/ItaniumMangle.cpp +++ b/clang/lib/AST/ItaniumMangle.cpp @@ -480,8 +480,6 @@ class CXXNameMangler { const AbiTagList *AdditionalAbiTags); void mangleUnscopedTemplateName(GlobalDecl GD, const AbiTagList *AdditionalAbiTags); - void mangleUnscopedTemplateName(TemplateName, - const AbiTagList *AdditionalAbiTags); void mangleSourceName(const IdentifierInfo *II); void mangleRegCallName(const IdentifierInfo *II); void mangleDeviceStubName(const IdentifierInfo *II); @@ -995,29 +993,6 @@ void CXXNameMangler::mangleUnscopedTemplateName( addSubstitution(ND); } -void CXXNameMangler::mangleUnscopedTemplateName( - TemplateName Template, const AbiTagList *AdditionalAbiTags) { - // ::= - // ::= - if (TemplateDecl *TD = Template.getAsTemplateDecl()) - return mangleUnscopedTemplateName(TD, AdditionalAbiTags); - - if (mangleSubstitution(Template)) - return; - - assert(!AdditionalAbiTags && - "dependent template name cannot have abi tags"); - - DependentTemplateName *Dependent = Template.getAsDependentTemplateName(); - assert(Dependent && "Not a dependent template name?"); - if (const IdentifierInfo *Id = Dependent->getIdentifier()) - mangleSourceName(Id); - else - mangleOperatorName(Dependent->getOperator(), UnknownArity); - - addSubstitution(Template); -} - void CXXNameMangler::mangleFloat(const llvm::APFloat &f) { // ABI: // Floating-point literals are encoded using a fixed-length @@ -1983,21 +1958,28 @@ void CXXNameMangler::mangleTemplatePrefix(TemplateName Template) { if (TemplateDecl *TD = Template.getAsTemplateDecl()) return mangleTemplatePrefix(TD); - if (QualifiedTemplateName *Qualified = Template.getAsQualifiedTemplateName()) - manglePrefix(Qualified->getQualifier()); + DependentTemplateName *Dependent = Template.getAsDependentTemplateName(); + assert(Dependent && "unexpected template name kind"); - if (OverloadedTemplateStorage *Overloaded - = Template.getAsOverloadedTemplate()) { - mangleUnqualifiedName(GlobalDecl(), (*Overloaded->begin())->getDeclName(), - UnknownArity, nullptr); + // Clang 11 and before mangled the substitution for a dependent template name + // after already having emitted (a substitution for) the prefix. + bool Clang11Compat = getASTContext().getLangOpts().getClangABICompat() <= + LangOptions::ClangABI::Ver11; + if (!Clang11Compat && mangleSubstitution(Template)) return; - } - DependentTemplateName *Dependent = Template.getAsDependentTemplateName(); - assert(Dependent && "Unknown template name kind?"); if (NestedNameSpecifier *Qualifier = Dependent->getQualifier()) manglePrefix(Qualifier); - mangleUnscopedTemplateName(Template, /* AdditionalAbiTags */ nullptr); + + if (Clang11Compat && mangleSubstitution(Template)) + return; + + if (const IdentifierInfo *Id = Dependent->getIdentifier()) + mangleSourceName(Id); + else + mangleOperatorName(Dependent->getOperator(), UnknownArity); + + addSubstitution(Template); } void CXXNameMangler::mangleTemplatePrefix(GlobalDecl GD, @@ -2564,6 +2546,12 @@ static bool isTypeSubstitutable(Qualifiers Quals, const Type *Ty, if (Ctx.getLangOpts().getClangABICompat() > LangOptions::ClangABI::Ver6 && isa(Ty)) return false; + // A placeholder type for class template deduction is substitutable with + // its corresponding template name; this is handled specially when mangling + // the type. + if (auto *DeducedTST = Ty->getAs()) + if (DeducedTST->getDeducedType().isNull()) + return false; return true; } @@ -3761,16 +3749,16 @@ void CXXNameMangler::mangleType(const AutoType *T) { void CXXNameMangler::mangleType(const DeducedTemplateSpecializationType *T) { QualType Deduced = T->getDeducedType(); if (!Deduced.isNull()) - mangleType(Deduced); - else if (TemplateDecl *TD = T->getTemplateName().getAsTemplateDecl()) - mangleName(GlobalDecl(TD)); - else { - // For an unresolved template-name, mangle it as if it were a template - // specialization but leave off the template arguments. - Out << 'N'; - mangleTemplatePrefix(T->getTemplateName()); - Out << 'E'; - } + return mangleType(Deduced); + + TemplateDecl *TD = T->getTemplateName().getAsTemplateDecl(); + assert(TD && "shouldn't form deduced TST unless we know we have a template"); + + if (mangleSubstitution(TD)) + return; + + mangleName(GlobalDecl(TD)); + addSubstitution(TD); } void CXXNameMangler::mangleType(const AtomicType *T) { diff --git a/clang/lib/AST/ParentMapContext.cpp b/clang/lib/AST/ParentMapContext.cpp index c80c8bc23e00f..cb4995312efa2 100644 --- a/clang/lib/AST/ParentMapContext.cpp +++ b/clang/lib/AST/ParentMapContext.cpp @@ -36,8 +36,6 @@ Expr *ParentMapContext::traverseIgnored(Expr *E) const { switch (Traversal) { case TK_AsIs: return E; - case TK_IgnoreImplicitCastsAndParentheses: - return E->IgnoreParenImpCasts(); case TK_IgnoreUnlessSpelledInSource: return E->IgnoreUnlessSpelledInSource(); } diff --git a/clang/lib/ASTMatchers/ASTMatchFinder.cpp b/clang/lib/ASTMatchers/ASTMatchFinder.cpp index e43778b4fe8ff..cc95371445242 100644 --- a/clang/lib/ASTMatchers/ASTMatchFinder.cpp +++ b/clang/lib/ASTMatchers/ASTMatchFinder.cpp @@ -95,12 +95,11 @@ class MatchChildASTVisitor // matching the descendants. MatchChildASTVisitor(const DynTypedMatcher *Matcher, ASTMatchFinder *Finder, BoundNodesTreeBuilder *Builder, int MaxDepth, - TraversalKind Traversal, bool IgnoreImplicitChildren, + bool IgnoreImplicitChildren, ASTMatchFinder::BindKind Bind) : Matcher(Matcher), Finder(Finder), Builder(Builder), CurrentDepth(0), - MaxDepth(MaxDepth), Traversal(Traversal), - IgnoreImplicitChildren(IgnoreImplicitChildren), Bind(Bind), - Matches(false) {} + MaxDepth(MaxDepth), IgnoreImplicitChildren(IgnoreImplicitChildren), + Bind(Bind), Matches(false) {} // Returns true if a match is found in the subtree rooted at the // given AST node. This is done via a set of mutually recursive @@ -168,10 +167,6 @@ class MatchChildASTVisitor Finder->getASTContext().getParentMapContext().traverseIgnored( ExprNode); } - if (Traversal == TraversalKind::TK_IgnoreImplicitCastsAndParentheses) { - if (Expr *ExprNode = dyn_cast_or_null(StmtNode)) - StmtToTraverse = ExprNode->IgnoreParenImpCasts(); - } return StmtToTraverse; } @@ -371,7 +366,6 @@ class MatchChildASTVisitor BoundNodesTreeBuilder ResultBindings; int CurrentDepth; const int MaxDepth; - const TraversalKind Traversal; const bool IgnoreImplicitChildren; const ASTMatchFinder::BindKind Bind; bool Matches; @@ -473,11 +467,10 @@ class MatchASTVisitor : public RecursiveASTVisitor, bool memoizedMatchesRecursively(const DynTypedNode &Node, ASTContext &Ctx, const DynTypedMatcher &Matcher, BoundNodesTreeBuilder *Builder, int MaxDepth, - TraversalKind Traversal, BindKind Bind) { + BindKind Bind) { // For AST-nodes that don't have an identity, we can't memoize. if (!Node.getMemoizationData() || !Builder->isComparable()) - return matchesRecursively(Node, Matcher, Builder, MaxDepth, Traversal, - Bind); + return matchesRecursively(Node, Matcher, Builder, MaxDepth, Bind); MatchKey Key; Key.MatcherID = Matcher.getID(); @@ -495,8 +488,8 @@ class MatchASTVisitor : public RecursiveASTVisitor, MemoizedMatchResult Result; Result.Nodes = *Builder; - Result.ResultOfMatch = matchesRecursively(Node, Matcher, &Result.Nodes, - MaxDepth, Traversal, Bind); + Result.ResultOfMatch = + matchesRecursively(Node, Matcher, &Result.Nodes, MaxDepth, Bind); MemoizedMatchResult &CachedResult = ResultCache[Key]; CachedResult = std::move(Result); @@ -509,7 +502,7 @@ class MatchASTVisitor : public RecursiveASTVisitor, bool matchesRecursively(const DynTypedNode &Node, const DynTypedMatcher &Matcher, BoundNodesTreeBuilder *Builder, int MaxDepth, - TraversalKind Traversal, BindKind Bind) { + BindKind Bind) { bool ScopedTraversal = TraversingASTNodeNotSpelledInSource || TraversingASTChildrenNotSpelledInSource; @@ -523,7 +516,7 @@ class MatchASTVisitor : public RecursiveASTVisitor, ASTNodeNotSpelledInSourceScope RAII(this, ScopedTraversal); - MatchChildASTVisitor Visitor(&Matcher, this, Builder, MaxDepth, Traversal, + MatchChildASTVisitor Visitor(&Matcher, this, Builder, MaxDepth, IgnoreImplicitChildren, Bind); return Visitor.findMatch(Node); } @@ -541,12 +534,10 @@ class MatchASTVisitor : public RecursiveASTVisitor, // Implements ASTMatchFinder::matchesChildOf. bool matchesChildOf(const DynTypedNode &Node, ASTContext &Ctx, const DynTypedMatcher &Matcher, - BoundNodesTreeBuilder *Builder, TraversalKind Traversal, - BindKind Bind) override { + BoundNodesTreeBuilder *Builder, BindKind Bind) override { if (ResultCache.size() > MaxMemoizationEntries) ResultCache.clear(); - return memoizedMatchesRecursively(Node, Ctx, Matcher, Builder, 1, Traversal, - Bind); + return memoizedMatchesRecursively(Node, Ctx, Matcher, Builder, 1, Bind); } // Implements ASTMatchFinder::matchesDescendantOf. bool matchesDescendantOf(const DynTypedNode &Node, ASTContext &Ctx, @@ -556,7 +547,7 @@ class MatchASTVisitor : public RecursiveASTVisitor, if (ResultCache.size() > MaxMemoizationEntries) ResultCache.clear(); return memoizedMatchesRecursively(Node, Ctx, Matcher, Builder, INT_MAX, - TraversalKind::TK_AsIs, Bind); + Bind); } // Implements ASTMatchFinder::matchesAncestorOf. bool matchesAncestorOf(const DynTypedNode &Node, ASTContext &Ctx, diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index 8e0fc5fa621e0..37f0212b70018 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -377,8 +377,10 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); - if (Opts.ArmSveVectorBits) + if (Opts.ArmSveVectorBits) { Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.ArmSveVectorBits)); + Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS"); + } } ArrayRef AArch64TargetInfo::getTargetBuiltins() const { diff --git a/clang/lib/Basic/Targets/OSTargets.h b/clang/lib/Basic/Targets/OSTargets.h index 7445dbe727943..60e47bcacbf4f 100644 --- a/clang/lib/Basic/Targets/OSTargets.h +++ b/clang/lib/Basic/Targets/OSTargets.h @@ -674,6 +674,9 @@ class AIXTargetInfo : public OSTargetInfo { Builder.defineMacro("_AIX"); + if (Opts.EnableAIXExtendedAltivecABI) + Builder.defineMacro("__EXTABI__"); + unsigned Major, Minor, Micro; Triple.getOSVersion(Major, Minor, Micro); diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index 5e17b7d51175f..37e688d14b4a1 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -115,8 +115,14 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__riscv_muldiv"); } - if (HasA) + if (HasA) { Builder.defineMacro("__riscv_atomic"); + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); + if (Is64Bit) + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); + } if (HasF || HasD) { Builder.defineMacro("__riscv_flen", HasD ? "64" : "32"); diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index 21bb66bbc8a9a..e7a3c96fa9d12 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -455,10 +455,14 @@ static bool initTargetOptions(DiagnosticsEngine &Diags, const clang::TargetOptions &TargetOpts, const LangOptions &LangOpts, const HeaderSearchOptions &HSOpts) { - Options.ThreadModel = - llvm::StringSwitch(CodeGenOpts.ThreadModel) - .Case("posix", llvm::ThreadModel::POSIX) - .Case("single", llvm::ThreadModel::Single); + switch (LangOpts.getThreadModel()) { + case LangOptions::ThreadModelKind::POSIX: + Options.ThreadModel = llvm::ThreadModel::POSIX; + break; + case LangOptions::ThreadModelKind::Single: + Options.ThreadModel = llvm::ThreadModel::Single; + break; + } // Set float ABI type. assert((CodeGenOpts.FloatABI == "soft" || CodeGenOpts.FloatABI == "softfp" || @@ -479,6 +483,7 @@ static bool initTargetOptions(DiagnosticsEngine &Diags, Options.AllowFPOpFusion = llvm::FPOpFusion::Standard; break; case LangOptions::FPM_On: + case LangOptions::FPM_FastHonorPragmas: Options.AllowFPOpFusion = llvm::FPOpFusion::Standard; break; case LangOptions::FPM_Fast: @@ -551,6 +556,7 @@ static bool initTargetOptions(DiagnosticsEngine &Diags, Options.EmitAddrsig = CodeGenOpts.Addrsig; Options.ForceDwarfFrameSection = CodeGenOpts.ForceDwarfFrameSection; Options.EmitCallSiteInfo = CodeGenOpts.EmitCallSiteInfo; + Options.EnableAIXExtendedAltivecABI = CodeGenOpts.EnableAIXExtendedAltivecABI; Options.ValueTrackingVariableLocations = CodeGenOpts.ValueTrackingVariableLocations; Options.XRayOmitFunctionIndex = CodeGenOpts.XRayOmitFunctionIndex; diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 730fbdbc3c696..5fc879a5b70ce 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -304,6 +304,10 @@ Value *EmitAtomicCmpXchgForMSIntrin(CodeGenFunction &CGF, const CallExpr *E, AtomicOrdering::Monotonic : SuccessOrdering; + // The atomic instruction is marked volatile for consistency with MSVC. This + // blocks the few atomics optimizations that LLVM has. If we want to optimize + // _Interlocked* operations in the future, we will have to remove the volatile + // marker. auto *Result = CGF.Builder.CreateAtomicCmpXchg( Destination, Comparand, Exchange, SuccessOrdering, FailureOrdering); @@ -311,6 +315,68 @@ Value *EmitAtomicCmpXchgForMSIntrin(CodeGenFunction &CGF, const CallExpr *E, return CGF.Builder.CreateExtractValue(Result, 0); } +// 64-bit Microsoft platforms support 128 bit cmpxchg operations. They are +// prototyped like this: +// +// unsigned char _InterlockedCompareExchange128...( +// __int64 volatile * _Destination, +// __int64 _ExchangeHigh, +// __int64 _ExchangeLow, +// __int64 * _ComparandResult); +static Value *EmitAtomicCmpXchg128ForMSIntrin(CodeGenFunction &CGF, + const CallExpr *E, + AtomicOrdering SuccessOrdering) { + assert(E->getNumArgs() == 4); + llvm::Value *Destination = CGF.EmitScalarExpr(E->getArg(0)); + llvm::Value *ExchangeHigh = CGF.EmitScalarExpr(E->getArg(1)); + llvm::Value *ExchangeLow = CGF.EmitScalarExpr(E->getArg(2)); + llvm::Value *ComparandPtr = CGF.EmitScalarExpr(E->getArg(3)); + + assert(Destination->getType()->isPointerTy()); + assert(!ExchangeHigh->getType()->isPointerTy()); + assert(!ExchangeLow->getType()->isPointerTy()); + assert(ComparandPtr->getType()->isPointerTy()); + + // For Release ordering, the failure ordering should be Monotonic. + auto FailureOrdering = SuccessOrdering == AtomicOrdering::Release + ? AtomicOrdering::Monotonic + : SuccessOrdering; + + // Convert to i128 pointers and values. + llvm::Type *Int128Ty = llvm::IntegerType::get(CGF.getLLVMContext(), 128); + llvm::Type *Int128PtrTy = Int128Ty->getPointerTo(); + Destination = CGF.Builder.CreateBitCast(Destination, Int128PtrTy); + Address ComparandResult(CGF.Builder.CreateBitCast(ComparandPtr, Int128PtrTy), + CGF.getContext().toCharUnitsFromBits(128)); + + // (((i128)hi) << 64) | ((i128)lo) + ExchangeHigh = CGF.Builder.CreateZExt(ExchangeHigh, Int128Ty); + ExchangeLow = CGF.Builder.CreateZExt(ExchangeLow, Int128Ty); + ExchangeHigh = + CGF.Builder.CreateShl(ExchangeHigh, llvm::ConstantInt::get(Int128Ty, 64)); + llvm::Value *Exchange = CGF.Builder.CreateOr(ExchangeHigh, ExchangeLow); + + // Load the comparand for the instruction. + llvm::Value *Comparand = CGF.Builder.CreateLoad(ComparandResult); + + auto *CXI = CGF.Builder.CreateAtomicCmpXchg(Destination, Comparand, Exchange, + SuccessOrdering, FailureOrdering); + + // The atomic instruction is marked volatile for consistency with MSVC. This + // blocks the few atomics optimizations that LLVM has. If we want to optimize + // _Interlocked* operations in the future, we will have to remove the volatile + // marker. + CXI->setVolatile(true); + + // Store the result as an outparameter. + CGF.Builder.CreateStore(CGF.Builder.CreateExtractValue(CXI, 0), + ComparandResult); + + // Get the success boolean and zero extend it to i8. + Value *Success = CGF.Builder.CreateExtractValue(CXI, 1); + return CGF.Builder.CreateZExt(Success, CGF.Int8Ty); +} + static Value *EmitAtomicIncrementValue(CodeGenFunction &CGF, const CallExpr *E, AtomicOrdering Ordering = AtomicOrdering::SequentiallyConsistent) { assert(E->getArg(0)->getType()->isPointerType()); @@ -993,6 +1059,10 @@ enum class CodeGenFunction::MSVCIntrin { _InterlockedCompareExchange_acq, _InterlockedCompareExchange_rel, _InterlockedCompareExchange_nf, + _InterlockedCompareExchange128, + _InterlockedCompareExchange128_acq, + _InterlockedCompareExchange128_rel, + _InterlockedCompareExchange128_nf, _InterlockedOr_acq, _InterlockedOr_rel, _InterlockedOr_nf, @@ -1011,16 +1081,352 @@ enum class CodeGenFunction::MSVCIntrin { __fastfail, }; +static Optional +translateArmToMsvcIntrin(unsigned BuiltinID) { + using MSVCIntrin = CodeGenFunction::MSVCIntrin; + switch (BuiltinID) { + default: + return None; + case ARM::BI_BitScanForward: + case ARM::BI_BitScanForward64: + return MSVCIntrin::_BitScanForward; + case ARM::BI_BitScanReverse: + case ARM::BI_BitScanReverse64: + return MSVCIntrin::_BitScanReverse; + case ARM::BI_InterlockedAnd64: + return MSVCIntrin::_InterlockedAnd; + case ARM::BI_InterlockedExchange64: + return MSVCIntrin::_InterlockedExchange; + case ARM::BI_InterlockedExchangeAdd64: + return MSVCIntrin::_InterlockedExchangeAdd; + case ARM::BI_InterlockedExchangeSub64: + return MSVCIntrin::_InterlockedExchangeSub; + case ARM::BI_InterlockedOr64: + return MSVCIntrin::_InterlockedOr; + case ARM::BI_InterlockedXor64: + return MSVCIntrin::_InterlockedXor; + case ARM::BI_InterlockedDecrement64: + return MSVCIntrin::_InterlockedDecrement; + case ARM::BI_InterlockedIncrement64: + return MSVCIntrin::_InterlockedIncrement; + case ARM::BI_InterlockedExchangeAdd8_acq: + case ARM::BI_InterlockedExchangeAdd16_acq: + case ARM::BI_InterlockedExchangeAdd_acq: + case ARM::BI_InterlockedExchangeAdd64_acq: + return MSVCIntrin::_InterlockedExchangeAdd_acq; + case ARM::BI_InterlockedExchangeAdd8_rel: + case ARM::BI_InterlockedExchangeAdd16_rel: + case ARM::BI_InterlockedExchangeAdd_rel: + case ARM::BI_InterlockedExchangeAdd64_rel: + return MSVCIntrin::_InterlockedExchangeAdd_rel; + case ARM::BI_InterlockedExchangeAdd8_nf: + case ARM::BI_InterlockedExchangeAdd16_nf: + case ARM::BI_InterlockedExchangeAdd_nf: + case ARM::BI_InterlockedExchangeAdd64_nf: + return MSVCIntrin::_InterlockedExchangeAdd_nf; + case ARM::BI_InterlockedExchange8_acq: + case ARM::BI_InterlockedExchange16_acq: + case ARM::BI_InterlockedExchange_acq: + case ARM::BI_InterlockedExchange64_acq: + return MSVCIntrin::_InterlockedExchange_acq; + case ARM::BI_InterlockedExchange8_rel: + case ARM::BI_InterlockedExchange16_rel: + case ARM::BI_InterlockedExchange_rel: + case ARM::BI_InterlockedExchange64_rel: + return MSVCIntrin::_InterlockedExchange_rel; + case ARM::BI_InterlockedExchange8_nf: + case ARM::BI_InterlockedExchange16_nf: + case ARM::BI_InterlockedExchange_nf: + case ARM::BI_InterlockedExchange64_nf: + return MSVCIntrin::_InterlockedExchange_nf; + case ARM::BI_InterlockedCompareExchange8_acq: + case ARM::BI_InterlockedCompareExchange16_acq: + case ARM::BI_InterlockedCompareExchange_acq: + case ARM::BI_InterlockedCompareExchange64_acq: + return MSVCIntrin::_InterlockedCompareExchange_acq; + case ARM::BI_InterlockedCompareExchange8_rel: + case ARM::BI_InterlockedCompareExchange16_rel: + case ARM::BI_InterlockedCompareExchange_rel: + case ARM::BI_InterlockedCompareExchange64_rel: + return MSVCIntrin::_InterlockedCompareExchange_rel; + case ARM::BI_InterlockedCompareExchange8_nf: + case ARM::BI_InterlockedCompareExchange16_nf: + case ARM::BI_InterlockedCompareExchange_nf: + case ARM::BI_InterlockedCompareExchange64_nf: + return MSVCIntrin::_InterlockedCompareExchange_nf; + case ARM::BI_InterlockedOr8_acq: + case ARM::BI_InterlockedOr16_acq: + case ARM::BI_InterlockedOr_acq: + case ARM::BI_InterlockedOr64_acq: + return MSVCIntrin::_InterlockedOr_acq; + case ARM::BI_InterlockedOr8_rel: + case ARM::BI_InterlockedOr16_rel: + case ARM::BI_InterlockedOr_rel: + case ARM::BI_InterlockedOr64_rel: + return MSVCIntrin::_InterlockedOr_rel; + case ARM::BI_InterlockedOr8_nf: + case ARM::BI_InterlockedOr16_nf: + case ARM::BI_InterlockedOr_nf: + case ARM::BI_InterlockedOr64_nf: + return MSVCIntrin::_InterlockedOr_nf; + case ARM::BI_InterlockedXor8_acq: + case ARM::BI_InterlockedXor16_acq: + case ARM::BI_InterlockedXor_acq: + case ARM::BI_InterlockedXor64_acq: + return MSVCIntrin::_InterlockedXor_acq; + case ARM::BI_InterlockedXor8_rel: + case ARM::BI_InterlockedXor16_rel: + case ARM::BI_InterlockedXor_rel: + case ARM::BI_InterlockedXor64_rel: + return MSVCIntrin::_InterlockedXor_rel; + case ARM::BI_InterlockedXor8_nf: + case ARM::BI_InterlockedXor16_nf: + case ARM::BI_InterlockedXor_nf: + case ARM::BI_InterlockedXor64_nf: + return MSVCIntrin::_InterlockedXor_nf; + case ARM::BI_InterlockedAnd8_acq: + case ARM::BI_InterlockedAnd16_acq: + case ARM::BI_InterlockedAnd_acq: + case ARM::BI_InterlockedAnd64_acq: + return MSVCIntrin::_InterlockedAnd_acq; + case ARM::BI_InterlockedAnd8_rel: + case ARM::BI_InterlockedAnd16_rel: + case ARM::BI_InterlockedAnd_rel: + case ARM::BI_InterlockedAnd64_rel: + return MSVCIntrin::_InterlockedAnd_rel; + case ARM::BI_InterlockedAnd8_nf: + case ARM::BI_InterlockedAnd16_nf: + case ARM::BI_InterlockedAnd_nf: + case ARM::BI_InterlockedAnd64_nf: + return MSVCIntrin::_InterlockedAnd_nf; + case ARM::BI_InterlockedIncrement16_acq: + case ARM::BI_InterlockedIncrement_acq: + case ARM::BI_InterlockedIncrement64_acq: + return MSVCIntrin::_InterlockedIncrement_acq; + case ARM::BI_InterlockedIncrement16_rel: + case ARM::BI_InterlockedIncrement_rel: + case ARM::BI_InterlockedIncrement64_rel: + return MSVCIntrin::_InterlockedIncrement_rel; + case ARM::BI_InterlockedIncrement16_nf: + case ARM::BI_InterlockedIncrement_nf: + case ARM::BI_InterlockedIncrement64_nf: + return MSVCIntrin::_InterlockedIncrement_nf; + case ARM::BI_InterlockedDecrement16_acq: + case ARM::BI_InterlockedDecrement_acq: + case ARM::BI_InterlockedDecrement64_acq: + return MSVCIntrin::_InterlockedDecrement_acq; + case ARM::BI_InterlockedDecrement16_rel: + case ARM::BI_InterlockedDecrement_rel: + case ARM::BI_InterlockedDecrement64_rel: + return MSVCIntrin::_InterlockedDecrement_rel; + case ARM::BI_InterlockedDecrement16_nf: + case ARM::BI_InterlockedDecrement_nf: + case ARM::BI_InterlockedDecrement64_nf: + return MSVCIntrin::_InterlockedDecrement_nf; + } + llvm_unreachable("must return from switch"); +} + +static Optional +translateAarch64ToMsvcIntrin(unsigned BuiltinID) { + using MSVCIntrin = CodeGenFunction::MSVCIntrin; + switch (BuiltinID) { + default: + return None; + case AArch64::BI_BitScanForward: + case AArch64::BI_BitScanForward64: + return MSVCIntrin::_BitScanForward; + case AArch64::BI_BitScanReverse: + case AArch64::BI_BitScanReverse64: + return MSVCIntrin::_BitScanReverse; + case AArch64::BI_InterlockedAnd64: + return MSVCIntrin::_InterlockedAnd; + case AArch64::BI_InterlockedExchange64: + return MSVCIntrin::_InterlockedExchange; + case AArch64::BI_InterlockedExchangeAdd64: + return MSVCIntrin::_InterlockedExchangeAdd; + case AArch64::BI_InterlockedExchangeSub64: + return MSVCIntrin::_InterlockedExchangeSub; + case AArch64::BI_InterlockedOr64: + return MSVCIntrin::_InterlockedOr; + case AArch64::BI_InterlockedXor64: + return MSVCIntrin::_InterlockedXor; + case AArch64::BI_InterlockedDecrement64: + return MSVCIntrin::_InterlockedDecrement; + case AArch64::BI_InterlockedIncrement64: + return MSVCIntrin::_InterlockedIncrement; + case AArch64::BI_InterlockedExchangeAdd8_acq: + case AArch64::BI_InterlockedExchangeAdd16_acq: + case AArch64::BI_InterlockedExchangeAdd_acq: + case AArch64::BI_InterlockedExchangeAdd64_acq: + return MSVCIntrin::_InterlockedExchangeAdd_acq; + case AArch64::BI_InterlockedExchangeAdd8_rel: + case AArch64::BI_InterlockedExchangeAdd16_rel: + case AArch64::BI_InterlockedExchangeAdd_rel: + case AArch64::BI_InterlockedExchangeAdd64_rel: + return MSVCIntrin::_InterlockedExchangeAdd_rel; + case AArch64::BI_InterlockedExchangeAdd8_nf: + case AArch64::BI_InterlockedExchangeAdd16_nf: + case AArch64::BI_InterlockedExchangeAdd_nf: + case AArch64::BI_InterlockedExchangeAdd64_nf: + return MSVCIntrin::_InterlockedExchangeAdd_nf; + case AArch64::BI_InterlockedExchange8_acq: + case AArch64::BI_InterlockedExchange16_acq: + case AArch64::BI_InterlockedExchange_acq: + case AArch64::BI_InterlockedExchange64_acq: + return MSVCIntrin::_InterlockedExchange_acq; + case AArch64::BI_InterlockedExchange8_rel: + case AArch64::BI_InterlockedExchange16_rel: + case AArch64::BI_InterlockedExchange_rel: + case AArch64::BI_InterlockedExchange64_rel: + return MSVCIntrin::_InterlockedExchange_rel; + case AArch64::BI_InterlockedExchange8_nf: + case AArch64::BI_InterlockedExchange16_nf: + case AArch64::BI_InterlockedExchange_nf: + case AArch64::BI_InterlockedExchange64_nf: + return MSVCIntrin::_InterlockedExchange_nf; + case AArch64::BI_InterlockedCompareExchange8_acq: + case AArch64::BI_InterlockedCompareExchange16_acq: + case AArch64::BI_InterlockedCompareExchange_acq: + case AArch64::BI_InterlockedCompareExchange64_acq: + return MSVCIntrin::_InterlockedCompareExchange_acq; + case AArch64::BI_InterlockedCompareExchange8_rel: + case AArch64::BI_InterlockedCompareExchange16_rel: + case AArch64::BI_InterlockedCompareExchange_rel: + case AArch64::BI_InterlockedCompareExchange64_rel: + return MSVCIntrin::_InterlockedCompareExchange_rel; + case AArch64::BI_InterlockedCompareExchange8_nf: + case AArch64::BI_InterlockedCompareExchange16_nf: + case AArch64::BI_InterlockedCompareExchange_nf: + case AArch64::BI_InterlockedCompareExchange64_nf: + return MSVCIntrin::_InterlockedCompareExchange_nf; + case AArch64::BI_InterlockedCompareExchange128: + return MSVCIntrin::_InterlockedCompareExchange128; + case AArch64::BI_InterlockedCompareExchange128_acq: + return MSVCIntrin::_InterlockedCompareExchange128_acq; + case AArch64::BI_InterlockedCompareExchange128_nf: + return MSVCIntrin::_InterlockedCompareExchange128_nf; + case AArch64::BI_InterlockedCompareExchange128_rel: + return MSVCIntrin::_InterlockedCompareExchange128_rel; + case AArch64::BI_InterlockedOr8_acq: + case AArch64::BI_InterlockedOr16_acq: + case AArch64::BI_InterlockedOr_acq: + case AArch64::BI_InterlockedOr64_acq: + return MSVCIntrin::_InterlockedOr_acq; + case AArch64::BI_InterlockedOr8_rel: + case AArch64::BI_InterlockedOr16_rel: + case AArch64::BI_InterlockedOr_rel: + case AArch64::BI_InterlockedOr64_rel: + return MSVCIntrin::_InterlockedOr_rel; + case AArch64::BI_InterlockedOr8_nf: + case AArch64::BI_InterlockedOr16_nf: + case AArch64::BI_InterlockedOr_nf: + case AArch64::BI_InterlockedOr64_nf: + return MSVCIntrin::_InterlockedOr_nf; + case AArch64::BI_InterlockedXor8_acq: + case AArch64::BI_InterlockedXor16_acq: + case AArch64::BI_InterlockedXor_acq: + case AArch64::BI_InterlockedXor64_acq: + return MSVCIntrin::_InterlockedXor_acq; + case AArch64::BI_InterlockedXor8_rel: + case AArch64::BI_InterlockedXor16_rel: + case AArch64::BI_InterlockedXor_rel: + case AArch64::BI_InterlockedXor64_rel: + return MSVCIntrin::_InterlockedXor_rel; + case AArch64::BI_InterlockedXor8_nf: + case AArch64::BI_InterlockedXor16_nf: + case AArch64::BI_InterlockedXor_nf: + case AArch64::BI_InterlockedXor64_nf: + return MSVCIntrin::_InterlockedXor_nf; + case AArch64::BI_InterlockedAnd8_acq: + case AArch64::BI_InterlockedAnd16_acq: + case AArch64::BI_InterlockedAnd_acq: + case AArch64::BI_InterlockedAnd64_acq: + return MSVCIntrin::_InterlockedAnd_acq; + case AArch64::BI_InterlockedAnd8_rel: + case AArch64::BI_InterlockedAnd16_rel: + case AArch64::BI_InterlockedAnd_rel: + case AArch64::BI_InterlockedAnd64_rel: + return MSVCIntrin::_InterlockedAnd_rel; + case AArch64::BI_InterlockedAnd8_nf: + case AArch64::BI_InterlockedAnd16_nf: + case AArch64::BI_InterlockedAnd_nf: + case AArch64::BI_InterlockedAnd64_nf: + return MSVCIntrin::_InterlockedAnd_nf; + case AArch64::BI_InterlockedIncrement16_acq: + case AArch64::BI_InterlockedIncrement_acq: + case AArch64::BI_InterlockedIncrement64_acq: + return MSVCIntrin::_InterlockedIncrement_acq; + case AArch64::BI_InterlockedIncrement16_rel: + case AArch64::BI_InterlockedIncrement_rel: + case AArch64::BI_InterlockedIncrement64_rel: + return MSVCIntrin::_InterlockedIncrement_rel; + case AArch64::BI_InterlockedIncrement16_nf: + case AArch64::BI_InterlockedIncrement_nf: + case AArch64::BI_InterlockedIncrement64_nf: + return MSVCIntrin::_InterlockedIncrement_nf; + case AArch64::BI_InterlockedDecrement16_acq: + case AArch64::BI_InterlockedDecrement_acq: + case AArch64::BI_InterlockedDecrement64_acq: + return MSVCIntrin::_InterlockedDecrement_acq; + case AArch64::BI_InterlockedDecrement16_rel: + case AArch64::BI_InterlockedDecrement_rel: + case AArch64::BI_InterlockedDecrement64_rel: + return MSVCIntrin::_InterlockedDecrement_rel; + case AArch64::BI_InterlockedDecrement16_nf: + case AArch64::BI_InterlockedDecrement_nf: + case AArch64::BI_InterlockedDecrement64_nf: + return MSVCIntrin::_InterlockedDecrement_nf; + } + llvm_unreachable("must return from switch"); +} + +static Optional +translateX86ToMsvcIntrin(unsigned BuiltinID) { + using MSVCIntrin = CodeGenFunction::MSVCIntrin; + switch (BuiltinID) { + default: + return None; + case clang::X86::BI_BitScanForward: + case clang::X86::BI_BitScanForward64: + return MSVCIntrin::_BitScanForward; + case clang::X86::BI_BitScanReverse: + case clang::X86::BI_BitScanReverse64: + return MSVCIntrin::_BitScanReverse; + case clang::X86::BI_InterlockedAnd64: + return MSVCIntrin::_InterlockedAnd; + case clang::X86::BI_InterlockedCompareExchange128: + return MSVCIntrin::_InterlockedCompareExchange128; + case clang::X86::BI_InterlockedExchange64: + return MSVCIntrin::_InterlockedExchange; + case clang::X86::BI_InterlockedExchangeAdd64: + return MSVCIntrin::_InterlockedExchangeAdd; + case clang::X86::BI_InterlockedExchangeSub64: + return MSVCIntrin::_InterlockedExchangeSub; + case clang::X86::BI_InterlockedOr64: + return MSVCIntrin::_InterlockedOr; + case clang::X86::BI_InterlockedXor64: + return MSVCIntrin::_InterlockedXor; + case clang::X86::BI_InterlockedDecrement64: + return MSVCIntrin::_InterlockedDecrement; + case clang::X86::BI_InterlockedIncrement64: + return MSVCIntrin::_InterlockedIncrement; + } + llvm_unreachable("must return from switch"); +} + +// Emit an MSVC intrinsic. Assumes that arguments have *not* been evaluated. Value *CodeGenFunction::EmitMSVCBuiltinExpr(MSVCIntrin BuiltinID, const CallExpr *E) { switch (BuiltinID) { case MSVCIntrin::_BitScanForward: case MSVCIntrin::_BitScanReverse: { + Address IndexAddress(EmitPointerWithAlignment(E->getArg(0))); Value *ArgValue = EmitScalarExpr(E->getArg(1)); llvm::Type *ArgType = ArgValue->getType(); llvm::Type *IndexType = - EmitScalarExpr(E->getArg(0))->getType()->getPointerElementType(); + IndexAddress.getPointer()->getType()->getPointerElementType(); llvm::Type *ResultType = ConvertType(E->getType()); Value *ArgZero = llvm::Constant::getNullValue(ArgType); @@ -1039,7 +1445,6 @@ Value *CodeGenFunction::EmitMSVCBuiltinExpr(MSVCIntrin BuiltinID, Result->addIncoming(ResZero, Begin); Builder.SetInsertPoint(NotZero); - Address IndexAddress = EmitPointerWithAlignment(E->getArg(0)); if (BuiltinID == MSVCIntrin::_BitScanForward) { Function *F = CGM.getIntrinsic(Intrinsic::cttz, ArgType); @@ -1098,6 +1503,15 @@ Value *CodeGenFunction::EmitMSVCBuiltinExpr(MSVCIntrin BuiltinID, return EmitAtomicCmpXchgForMSIntrin(*this, E, AtomicOrdering::Release); case MSVCIntrin::_InterlockedCompareExchange_nf: return EmitAtomicCmpXchgForMSIntrin(*this, E, AtomicOrdering::Monotonic); + case MSVCIntrin::_InterlockedCompareExchange128: + return EmitAtomicCmpXchg128ForMSIntrin( + *this, E, AtomicOrdering::SequentiallyConsistent); + case MSVCIntrin::_InterlockedCompareExchange128_acq: + return EmitAtomicCmpXchg128ForMSIntrin(*this, E, AtomicOrdering::Acquire); + case MSVCIntrin::_InterlockedCompareExchange128_rel: + return EmitAtomicCmpXchg128ForMSIntrin(*this, E, AtomicOrdering::Release); + case MSVCIntrin::_InterlockedCompareExchange128_nf: + return EmitAtomicCmpXchg128ForMSIntrin(*this, E, AtomicOrdering::Monotonic); case MSVCIntrin::_InterlockedOr_acq: return MakeBinaryAtomicValue(*this, AtomicRMWInst::Or, E, AtomicOrdering::Acquire); @@ -6853,6 +7267,11 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID, AccessKind); } + // Handle MSVC intrinsics before argument evaluation to prevent double + // evaluation. + if (Optional MsvcIntId = translateArmToMsvcIntrin(BuiltinID)) + return EmitMSVCBuiltinExpr(*MsvcIntId, E); + // Deal with MVE builtins if (Value *Result = EmitARMMVEBuiltinExpr(BuiltinID, E, ReturnValue, Arch)) return Result; @@ -7013,143 +7432,6 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID, return Builder.CreateCall(F, {Ops[1], Ops[2], Ops[0], Ops[3], Ops[4], Ops[5]}); } - case ARM::BI_BitScanForward: - case ARM::BI_BitScanForward64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_BitScanForward, E); - case ARM::BI_BitScanReverse: - case ARM::BI_BitScanReverse64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_BitScanReverse, E); - - case ARM::BI_InterlockedAnd64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedAnd, E); - case ARM::BI_InterlockedExchange64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchange, E); - case ARM::BI_InterlockedExchangeAdd64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchangeAdd, E); - case ARM::BI_InterlockedExchangeSub64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchangeSub, E); - case ARM::BI_InterlockedOr64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedOr, E); - case ARM::BI_InterlockedXor64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedXor, E); - case ARM::BI_InterlockedDecrement64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedDecrement, E); - case ARM::BI_InterlockedIncrement64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedIncrement, E); - case ARM::BI_InterlockedExchangeAdd8_acq: - case ARM::BI_InterlockedExchangeAdd16_acq: - case ARM::BI_InterlockedExchangeAdd_acq: - case ARM::BI_InterlockedExchangeAdd64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchangeAdd_acq, E); - case ARM::BI_InterlockedExchangeAdd8_rel: - case ARM::BI_InterlockedExchangeAdd16_rel: - case ARM::BI_InterlockedExchangeAdd_rel: - case ARM::BI_InterlockedExchangeAdd64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchangeAdd_rel, E); - case ARM::BI_InterlockedExchangeAdd8_nf: - case ARM::BI_InterlockedExchangeAdd16_nf: - case ARM::BI_InterlockedExchangeAdd_nf: - case ARM::BI_InterlockedExchangeAdd64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchangeAdd_nf, E); - case ARM::BI_InterlockedExchange8_acq: - case ARM::BI_InterlockedExchange16_acq: - case ARM::BI_InterlockedExchange_acq: - case ARM::BI_InterlockedExchange64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchange_acq, E); - case ARM::BI_InterlockedExchange8_rel: - case ARM::BI_InterlockedExchange16_rel: - case ARM::BI_InterlockedExchange_rel: - case ARM::BI_InterlockedExchange64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchange_rel, E); - case ARM::BI_InterlockedExchange8_nf: - case ARM::BI_InterlockedExchange16_nf: - case ARM::BI_InterlockedExchange_nf: - case ARM::BI_InterlockedExchange64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchange_nf, E); - case ARM::BI_InterlockedCompareExchange8_acq: - case ARM::BI_InterlockedCompareExchange16_acq: - case ARM::BI_InterlockedCompareExchange_acq: - case ARM::BI_InterlockedCompareExchange64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedCompareExchange_acq, E); - case ARM::BI_InterlockedCompareExchange8_rel: - case ARM::BI_InterlockedCompareExchange16_rel: - case ARM::BI_InterlockedCompareExchange_rel: - case ARM::BI_InterlockedCompareExchange64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedCompareExchange_rel, E); - case ARM::BI_InterlockedCompareExchange8_nf: - case ARM::BI_InterlockedCompareExchange16_nf: - case ARM::BI_InterlockedCompareExchange_nf: - case ARM::BI_InterlockedCompareExchange64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedCompareExchange_nf, E); - case ARM::BI_InterlockedOr8_acq: - case ARM::BI_InterlockedOr16_acq: - case ARM::BI_InterlockedOr_acq: - case ARM::BI_InterlockedOr64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedOr_acq, E); - case ARM::BI_InterlockedOr8_rel: - case ARM::BI_InterlockedOr16_rel: - case ARM::BI_InterlockedOr_rel: - case ARM::BI_InterlockedOr64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedOr_rel, E); - case ARM::BI_InterlockedOr8_nf: - case ARM::BI_InterlockedOr16_nf: - case ARM::BI_InterlockedOr_nf: - case ARM::BI_InterlockedOr64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedOr_nf, E); - case ARM::BI_InterlockedXor8_acq: - case ARM::BI_InterlockedXor16_acq: - case ARM::BI_InterlockedXor_acq: - case ARM::BI_InterlockedXor64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedXor_acq, E); - case ARM::BI_InterlockedXor8_rel: - case ARM::BI_InterlockedXor16_rel: - case ARM::BI_InterlockedXor_rel: - case ARM::BI_InterlockedXor64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedXor_rel, E); - case ARM::BI_InterlockedXor8_nf: - case ARM::BI_InterlockedXor16_nf: - case ARM::BI_InterlockedXor_nf: - case ARM::BI_InterlockedXor64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedXor_nf, E); - case ARM::BI_InterlockedAnd8_acq: - case ARM::BI_InterlockedAnd16_acq: - case ARM::BI_InterlockedAnd_acq: - case ARM::BI_InterlockedAnd64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedAnd_acq, E); - case ARM::BI_InterlockedAnd8_rel: - case ARM::BI_InterlockedAnd16_rel: - case ARM::BI_InterlockedAnd_rel: - case ARM::BI_InterlockedAnd64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedAnd_rel, E); - case ARM::BI_InterlockedAnd8_nf: - case ARM::BI_InterlockedAnd16_nf: - case ARM::BI_InterlockedAnd_nf: - case ARM::BI_InterlockedAnd64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedAnd_nf, E); - case ARM::BI_InterlockedIncrement16_acq: - case ARM::BI_InterlockedIncrement_acq: - case ARM::BI_InterlockedIncrement64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedIncrement_acq, E); - case ARM::BI_InterlockedIncrement16_rel: - case ARM::BI_InterlockedIncrement_rel: - case ARM::BI_InterlockedIncrement64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedIncrement_rel, E); - case ARM::BI_InterlockedIncrement16_nf: - case ARM::BI_InterlockedIncrement_nf: - case ARM::BI_InterlockedIncrement64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedIncrement_nf, E); - case ARM::BI_InterlockedDecrement16_acq: - case ARM::BI_InterlockedDecrement_acq: - case ARM::BI_InterlockedDecrement64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedDecrement_acq, E); - case ARM::BI_InterlockedDecrement16_rel: - case ARM::BI_InterlockedDecrement_rel: - case ARM::BI_InterlockedDecrement64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedDecrement_rel, E); - case ARM::BI_InterlockedDecrement16_nf: - case ARM::BI_InterlockedDecrement_nf: - case ARM::BI_InterlockedDecrement64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedDecrement_nf, E); } // Get the last argument, which specifies the vector type. @@ -8955,6 +9237,11 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID, return Builder.CreateCall(F); } + // Handle MSVC intrinsics before argument evaluation to prevent double + // evaluation. + if (Optional MsvcIntId = translateAarch64ToMsvcIntrin(BuiltinID)) + return EmitMSVCBuiltinExpr(*MsvcIntId, E); + // Find out if any arguments are required to be integer constant // expressions. unsigned ICEArguments = 0; @@ -9656,142 +9943,6 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID, return Builder.CreateExtractElement(Ops[0], EmitScalarExpr(E->getArg(1)), "vgetq_lane"); } - case AArch64::BI_BitScanForward: - case AArch64::BI_BitScanForward64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_BitScanForward, E); - case AArch64::BI_BitScanReverse: - case AArch64::BI_BitScanReverse64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_BitScanReverse, E); - case AArch64::BI_InterlockedAnd64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedAnd, E); - case AArch64::BI_InterlockedExchange64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchange, E); - case AArch64::BI_InterlockedExchangeAdd64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchangeAdd, E); - case AArch64::BI_InterlockedExchangeSub64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchangeSub, E); - case AArch64::BI_InterlockedOr64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedOr, E); - case AArch64::BI_InterlockedXor64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedXor, E); - case AArch64::BI_InterlockedDecrement64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedDecrement, E); - case AArch64::BI_InterlockedIncrement64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedIncrement, E); - case AArch64::BI_InterlockedExchangeAdd8_acq: - case AArch64::BI_InterlockedExchangeAdd16_acq: - case AArch64::BI_InterlockedExchangeAdd_acq: - case AArch64::BI_InterlockedExchangeAdd64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchangeAdd_acq, E); - case AArch64::BI_InterlockedExchangeAdd8_rel: - case AArch64::BI_InterlockedExchangeAdd16_rel: - case AArch64::BI_InterlockedExchangeAdd_rel: - case AArch64::BI_InterlockedExchangeAdd64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchangeAdd_rel, E); - case AArch64::BI_InterlockedExchangeAdd8_nf: - case AArch64::BI_InterlockedExchangeAdd16_nf: - case AArch64::BI_InterlockedExchangeAdd_nf: - case AArch64::BI_InterlockedExchangeAdd64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchangeAdd_nf, E); - case AArch64::BI_InterlockedExchange8_acq: - case AArch64::BI_InterlockedExchange16_acq: - case AArch64::BI_InterlockedExchange_acq: - case AArch64::BI_InterlockedExchange64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchange_acq, E); - case AArch64::BI_InterlockedExchange8_rel: - case AArch64::BI_InterlockedExchange16_rel: - case AArch64::BI_InterlockedExchange_rel: - case AArch64::BI_InterlockedExchange64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchange_rel, E); - case AArch64::BI_InterlockedExchange8_nf: - case AArch64::BI_InterlockedExchange16_nf: - case AArch64::BI_InterlockedExchange_nf: - case AArch64::BI_InterlockedExchange64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchange_nf, E); - case AArch64::BI_InterlockedCompareExchange8_acq: - case AArch64::BI_InterlockedCompareExchange16_acq: - case AArch64::BI_InterlockedCompareExchange_acq: - case AArch64::BI_InterlockedCompareExchange64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedCompareExchange_acq, E); - case AArch64::BI_InterlockedCompareExchange8_rel: - case AArch64::BI_InterlockedCompareExchange16_rel: - case AArch64::BI_InterlockedCompareExchange_rel: - case AArch64::BI_InterlockedCompareExchange64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedCompareExchange_rel, E); - case AArch64::BI_InterlockedCompareExchange8_nf: - case AArch64::BI_InterlockedCompareExchange16_nf: - case AArch64::BI_InterlockedCompareExchange_nf: - case AArch64::BI_InterlockedCompareExchange64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedCompareExchange_nf, E); - case AArch64::BI_InterlockedOr8_acq: - case AArch64::BI_InterlockedOr16_acq: - case AArch64::BI_InterlockedOr_acq: - case AArch64::BI_InterlockedOr64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedOr_acq, E); - case AArch64::BI_InterlockedOr8_rel: - case AArch64::BI_InterlockedOr16_rel: - case AArch64::BI_InterlockedOr_rel: - case AArch64::BI_InterlockedOr64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedOr_rel, E); - case AArch64::BI_InterlockedOr8_nf: - case AArch64::BI_InterlockedOr16_nf: - case AArch64::BI_InterlockedOr_nf: - case AArch64::BI_InterlockedOr64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedOr_nf, E); - case AArch64::BI_InterlockedXor8_acq: - case AArch64::BI_InterlockedXor16_acq: - case AArch64::BI_InterlockedXor_acq: - case AArch64::BI_InterlockedXor64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedXor_acq, E); - case AArch64::BI_InterlockedXor8_rel: - case AArch64::BI_InterlockedXor16_rel: - case AArch64::BI_InterlockedXor_rel: - case AArch64::BI_InterlockedXor64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedXor_rel, E); - case AArch64::BI_InterlockedXor8_nf: - case AArch64::BI_InterlockedXor16_nf: - case AArch64::BI_InterlockedXor_nf: - case AArch64::BI_InterlockedXor64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedXor_nf, E); - case AArch64::BI_InterlockedAnd8_acq: - case AArch64::BI_InterlockedAnd16_acq: - case AArch64::BI_InterlockedAnd_acq: - case AArch64::BI_InterlockedAnd64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedAnd_acq, E); - case AArch64::BI_InterlockedAnd8_rel: - case AArch64::BI_InterlockedAnd16_rel: - case AArch64::BI_InterlockedAnd_rel: - case AArch64::BI_InterlockedAnd64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedAnd_rel, E); - case AArch64::BI_InterlockedAnd8_nf: - case AArch64::BI_InterlockedAnd16_nf: - case AArch64::BI_InterlockedAnd_nf: - case AArch64::BI_InterlockedAnd64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedAnd_nf, E); - case AArch64::BI_InterlockedIncrement16_acq: - case AArch64::BI_InterlockedIncrement_acq: - case AArch64::BI_InterlockedIncrement64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedIncrement_acq, E); - case AArch64::BI_InterlockedIncrement16_rel: - case AArch64::BI_InterlockedIncrement_rel: - case AArch64::BI_InterlockedIncrement64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedIncrement_rel, E); - case AArch64::BI_InterlockedIncrement16_nf: - case AArch64::BI_InterlockedIncrement_nf: - case AArch64::BI_InterlockedIncrement64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedIncrement_nf, E); - case AArch64::BI_InterlockedDecrement16_acq: - case AArch64::BI_InterlockedDecrement_acq: - case AArch64::BI_InterlockedDecrement64_acq: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedDecrement_acq, E); - case AArch64::BI_InterlockedDecrement16_rel: - case AArch64::BI_InterlockedDecrement_rel: - case AArch64::BI_InterlockedDecrement64_rel: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedDecrement_rel, E); - case AArch64::BI_InterlockedDecrement16_nf: - case AArch64::BI_InterlockedDecrement_nf: - case AArch64::BI_InterlockedDecrement64_nf: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedDecrement_nf, E); case AArch64::BI_InterlockedAdd: { Value *Arg0 = EmitScalarExpr(E->getArg(0)); @@ -11765,6 +11916,11 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID, if (BuiltinID == X86::BI__builtin_cpu_init) return EmitX86CpuInit(); + // Handle MSVC intrinsics before argument evaluation to prevent double + // evaluation. + if (Optional MsvcIntId = translateX86ToMsvcIntrin(BuiltinID)) + return EmitMSVCBuiltinExpr(*MsvcIntId, E); + SmallVector Ops; bool IsMaskFCmp = false; @@ -13971,65 +14127,6 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID, return Builder.CreateFence(llvm::AtomicOrdering::SequentiallyConsistent, llvm::SyncScope::SingleThread); } - case X86::BI_BitScanForward: - case X86::BI_BitScanForward64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_BitScanForward, E); - case X86::BI_BitScanReverse: - case X86::BI_BitScanReverse64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_BitScanReverse, E); - - case X86::BI_InterlockedAnd64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedAnd, E); - case X86::BI_InterlockedExchange64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchange, E); - case X86::BI_InterlockedExchangeAdd64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchangeAdd, E); - case X86::BI_InterlockedExchangeSub64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedExchangeSub, E); - case X86::BI_InterlockedOr64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedOr, E); - case X86::BI_InterlockedXor64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedXor, E); - case X86::BI_InterlockedDecrement64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedDecrement, E); - case X86::BI_InterlockedIncrement64: - return EmitMSVCBuiltinExpr(MSVCIntrin::_InterlockedIncrement, E); - case X86::BI_InterlockedCompareExchange128: { - // InterlockedCompareExchange128 doesn't directly refer to 128bit ints, - // instead it takes pointers to 64bit ints for Destination and - // ComparandResult, and exchange is taken as two 64bit ints (high & low). - // The previous value is written to ComparandResult, and success is - // returned. - - llvm::Type *Int128Ty = Builder.getInt128Ty(); - llvm::Type *Int128PtrTy = Int128Ty->getPointerTo(); - - Value *Destination = - Builder.CreateBitCast(Ops[0], Int128PtrTy); - Value *ExchangeHigh128 = Builder.CreateZExt(Ops[1], Int128Ty); - Value *ExchangeLow128 = Builder.CreateZExt(Ops[2], Int128Ty); - Address ComparandResult(Builder.CreateBitCast(Ops[3], Int128PtrTy), - getContext().toCharUnitsFromBits(128)); - - Value *Exchange = Builder.CreateOr( - Builder.CreateShl(ExchangeHigh128, 64, "", false, false), - ExchangeLow128); - - Value *Comparand = Builder.CreateLoad(ComparandResult); - - AtomicCmpXchgInst *CXI = - Builder.CreateAtomicCmpXchg(Destination, Comparand, Exchange, - AtomicOrdering::SequentiallyConsistent, - AtomicOrdering::SequentiallyConsistent); - CXI->setVolatile(true); - - // Write the result back to the inout pointer. - Builder.CreateStore(Builder.CreateExtractValue(CXI, 0), ComparandResult); - - // Get the success boolean and zero extend it to i8. - Value *Success = Builder.CreateExtractValue(CXI, 1); - return Builder.CreateZExt(Success, ConvertType(E->getType())); - } case X86::BI_AddressOfReturnAddress: { Function *F = diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index 4760cd8ab7508..c93f73f91f355 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -3162,7 +3162,7 @@ llvm::Value *CodeGenFunction::EmitCMSEClearRecord(llvm::Value *Src, const llvm::DataLayout &DataLayout = CGM.getDataLayout(); int Size = DataLayout.getTypeStoreSize(ITy); SmallVector Bits(Size); - setUsedBits(CGM, QTy->getAs(), 0, Bits); + setUsedBits(CGM, QTy->castAs(), 0, Bits); int CharWidth = CGM.getContext().getCharWidth(); uint64_t Mask = @@ -3179,7 +3179,7 @@ llvm::Value *CodeGenFunction::EmitCMSEClearRecord(llvm::Value *Src, const llvm::DataLayout &DataLayout = CGM.getDataLayout(); int Size = DataLayout.getTypeStoreSize(ATy); SmallVector Bits(Size); - setUsedBits(CGM, QTy->getAs(), 0, Bits); + setUsedBits(CGM, QTy->castAs(), 0, Bits); // Clear each element of the LLVM array. int CharWidth = CGM.getContext().getCharWidth(); diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index 84733369a4a1b..c15f6350b95eb 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -7904,8 +7904,11 @@ class MappableExprsHandler { IsCaptureFirstInfo = false; FirstPointerInComplexData = false; } else if (FirstPointerInComplexData) { - BP = CGF.EmitOMPSharedLValue(I->getAssociatedExpression()) - .getAddress(CGF); + QualType Ty = Components.rbegin() + ->getAssociatedDeclaration() + ->getType() + .getNonReferenceType(); + BP = CGF.EmitLoadOfPointer(BP, Ty->castAs()); FirstPointerInComplexData = false; } } diff --git a/clang/lib/CodeGen/CGVTables.cpp b/clang/lib/CodeGen/CGVTables.cpp index 65b3b0c5f53d0..75afc860cc47a 100644 --- a/clang/lib/CodeGen/CGVTables.cpp +++ b/clang/lib/CodeGen/CGVTables.cpp @@ -1294,8 +1294,16 @@ bool CodeGenModule::HasHiddenLTOVisibility(const CXXRecordDecl *RD) { return !HasLTOVisibilityPublicStd(RD); } -llvm::GlobalObject::VCallVisibility -CodeGenModule::GetVCallVisibilityLevel(const CXXRecordDecl *RD) { +llvm::GlobalObject::VCallVisibility CodeGenModule::GetVCallVisibilityLevel( + const CXXRecordDecl *RD, llvm::DenseSet &Visited) { + // If we have already visited this RD (which means this is a recursive call + // since the initial call should have an empty Visited set), return the max + // visibility. The recursive calls below compute the min between the result + // of the recursive call and the current TypeVis, so returning the max here + // ensures that it will have no effect on the current TypeVis. + if (!Visited.insert(RD).second) + return llvm::GlobalObject::VCallVisibilityTranslationUnit; + LinkageInfo LV = RD->getLinkageAndVisibility(); llvm::GlobalObject::VCallVisibility TypeVis; if (!isExternallyVisible(LV.getLinkage())) @@ -1307,13 +1315,15 @@ CodeGenModule::GetVCallVisibilityLevel(const CXXRecordDecl *RD) { for (auto B : RD->bases()) if (B.getType()->getAsCXXRecordDecl()->isDynamicClass()) - TypeVis = std::min(TypeVis, - GetVCallVisibilityLevel(B.getType()->getAsCXXRecordDecl())); + TypeVis = std::min( + TypeVis, + GetVCallVisibilityLevel(B.getType()->getAsCXXRecordDecl(), Visited)); for (auto B : RD->vbases()) if (B.getType()->getAsCXXRecordDecl()->isDynamicClass()) - TypeVis = std::min(TypeVis, - GetVCallVisibilityLevel(B.getType()->getAsCXXRecordDecl())); + TypeVis = std::min( + TypeVis, + GetVCallVisibilityLevel(B.getType()->getAsCXXRecordDecl(), Visited)); return TypeVis; } @@ -1382,7 +1392,9 @@ void CodeGenModule::EmitVTableTypeMetadata(const CXXRecordDecl *RD, if (getCodeGenOpts().VirtualFunctionElimination || getCodeGenOpts().WholeProgramVTables) { - llvm::GlobalObject::VCallVisibility TypeVis = GetVCallVisibilityLevel(RD); + llvm::DenseSet Visited; + llvm::GlobalObject::VCallVisibility TypeVis = + GetVCallVisibilityLevel(RD, Visited); if (TypeVis != llvm::GlobalObject::VCallVisibilityPublic) VTable->setVCallVisibilityMetadata(TypeVis); } diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 6c50c744b9699..317306e7f2bd2 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -4124,10 +4124,7 @@ class CodeGenFunction : public CodeGenTypeCache { ReturnValueSlot ReturnValue); RValue EmitIntelFPGAMemBuiltin(const CallExpr *E); -private: enum class MSVCIntrin; - -public: llvm::Value *EmitMSVCBuiltinExpr(MSVCIntrin BuiltinID, const CallExpr *E); llvm::Value *EmitBuiltinAvailable(const VersionTuple &Version); diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 6441a71cc84c1..15f2e60ffd3e3 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -436,6 +436,13 @@ static void setVisibilityFromDLLStorageClass(const clang::LangOptions &LO, if (GV.hasAppendingLinkage() || GV.hasLocalLinkage()) continue; + // Reset DSO locality before setting the visibility. This removes + // any effects that visibility options and annotations may have + // had on the DSO locality. Setting the visibility will implicitly set + // appropriate globals to DSO Local; however, this will be pessimistic + // w.r.t. to the normal compiler IRGen. + GV.setDSOLocal(false); + if (GV.isDeclarationForLinker()) { GV.setVisibility(GV.getDLLStorageClass() == llvm::GlobalValue::DLLImportStorageClass diff --git a/clang/lib/CodeGen/CodeGenModule.h b/clang/lib/CodeGen/CodeGenModule.h index 0dd0a3e916cb6..23a8e716b3b56 100644 --- a/clang/lib/CodeGen/CodeGenModule.h +++ b/clang/lib/CodeGen/CodeGenModule.h @@ -1351,8 +1351,11 @@ class CodeGenModule : public CodeGenTypeCache { /// a virtual function call could be made which ends up being dispatched to a /// member function of this class. This scope can be wider than the visibility /// of the class itself when the class has a more-visible dynamic base class. + /// The client should pass in an empty Visited set, which is used to prevent + /// redundant recursive processing. llvm::GlobalObject::VCallVisibility - GetVCallVisibilityLevel(const CXXRecordDecl *RD); + GetVCallVisibilityLevel(const CXXRecordDecl *RD, + llvm::DenseSet &Visited); /// Emit type metadata for the given vtable using the given layout. void EmitVTableTypeMetadata(const CXXRecordDecl *RD, diff --git a/clang/lib/CodeGen/MicrosoftCXXABI.cpp b/clang/lib/CodeGen/MicrosoftCXXABI.cpp index 8046b7afce573..c16c72dc93d5c 100644 --- a/clang/lib/CodeGen/MicrosoftCXXABI.cpp +++ b/clang/lib/CodeGen/MicrosoftCXXABI.cpp @@ -1649,8 +1649,9 @@ void MicrosoftCXXABI::emitVTableTypeMetadata(const VPtrInfo &Info, // TODO: Should VirtualFunctionElimination also be supported here? // See similar handling in CodeGenModule::EmitVTableTypeMetadata. if (CGM.getCodeGenOpts().WholeProgramVTables) { + llvm::DenseSet Visited; llvm::GlobalObject::VCallVisibility TypeVis = - CGM.GetVCallVisibilityLevel(RD); + CGM.GetVCallVisibilityLevel(RD, Visited); if (TypeVis != llvm::GlobalObject::VCallVisibilityPublic) VTable->setVCallVisibilityMetadata(TypeVis); } diff --git a/clang/lib/CodeGen/ObjectFilePCHContainerOperations.cpp b/clang/lib/CodeGen/ObjectFilePCHContainerOperations.cpp index 04bd6680e31c5..de5c1a4c8f029 100644 --- a/clang/lib/CodeGen/ObjectFilePCHContainerOperations.cpp +++ b/clang/lib/CodeGen/ObjectFilePCHContainerOperations.cpp @@ -49,7 +49,7 @@ class PCHContainerGenerator : public ASTConsumer { const PreprocessorOptions &PreprocessorOpts; CodeGenOptions CodeGenOpts; const TargetOptions TargetOpts; - const LangOptions LangOpts; + LangOptions LangOpts; std::unique_ptr VMContext; std::unique_ptr M; std::unique_ptr Builder; @@ -147,7 +147,7 @@ class PCHContainerGenerator : public ASTConsumer { // The debug info output isn't affected by CodeModel and // ThreadModel, but the backend expects them to be nonempty. CodeGenOpts.CodeModel = "default"; - CodeGenOpts.ThreadModel = "single"; + LangOpts.setThreadModel(LangOptions::ThreadModelKind::Single); CodeGenOpts.DebugTypeExtRefs = true; // When building a module MainFileName is the name of the modulemap file. CodeGenOpts.MainFileName = diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp index 2a6297d01845c..2e28a2c7a5ee3 100644 --- a/clang/lib/CodeGen/TargetInfo.cpp +++ b/clang/lib/CodeGen/TargetInfo.cpp @@ -4514,7 +4514,7 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy) const { return ABIArgInfo::getDirect(); if (RetTy->isVectorType()) - llvm::report_fatal_error("vector type is not supported on AIX yet"); + return ABIArgInfo::getDirect(); if (RetTy->isVoidType()) return ABIArgInfo::getIgnore(); @@ -4533,7 +4533,7 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const { return ABIArgInfo::getDirect(); if (Ty->isVectorType()) - llvm::report_fatal_error("vector type is not supported on AIX yet"); + return ABIArgInfo::getDirect(); if (isAggregateTypeForABI(Ty)) { // Records with non-trivial destructors/copy-constructors should not be @@ -4558,7 +4558,7 @@ CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const { Ty = CTy->getElementType(); if (Ty->isVectorType()) - llvm::report_fatal_error("vector type is not supported on AIX yet"); + return CharUnits::fromQuantity(16); // If the structure contains a vector type, the alignment is 16. if (isRecordWithSIMDVectorType(getContext(), Ty)) @@ -4573,7 +4573,8 @@ Address AIXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, llvm::report_fatal_error("complex type is not supported on AIX yet"); if (Ty->isVectorType()) - llvm::report_fatal_error("vector type is not supported on AIX yet"); + llvm::report_fatal_error( + "vector types are not yet supported for variadic functions on AIX"); auto TypeInfo = getContext().getTypeInfoInChars(Ty); TypeInfo.Align = getParamTypeAlignment(Ty); @@ -10394,7 +10395,7 @@ void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const { if (!IsRetIndirect && RetTy->isScalarType() && getContext().getTypeSize(RetTy) > (2 * XLen)) { if (RetTy->isComplexType() && FLen) { - QualType EltTy = RetTy->getAs()->getElementType(); + QualType EltTy = RetTy->castAs()->getElementType(); IsRetIndirect = getContext().getTypeSize(EltTy) > FLen; } else { // This is a normal scalar > 2*XLen, such as fp128 on RV32. diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index b4f8dea01ed51..635d6654d5cf6 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -6961,7 +6961,11 @@ const ToolChain &Driver::getToolChain(const ArgList &Args, break; case llvm::Triple::riscv32: case llvm::Triple::riscv64: - TC = std::make_unique(*this, Target, Args); + if (toolchains::RISCVToolChain::hasGCCToolchain(*this, Args)) + TC = + std::make_unique(*this, Target, Args); + else + TC = std::make_unique(*this, Target, Args); break; case llvm::Triple::ve: TC = std::make_unique(*this, Target, Args); diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp index 504255361caea..384264dc39095 100644 --- a/clang/lib/Driver/ToolChain.cpp +++ b/clang/lib/Driver/ToolChain.cpp @@ -606,7 +606,13 @@ std::string ToolChain::GetProgramPath(const char *Name) const { return D.GetProgramPath(Name, *this); } -std::string ToolChain::GetLinkerPath() const { +std::string ToolChain::GetLinkerPath(bool *LinkerIsLLD, + bool *LinkerIsLLDDarwinNew) const { + if (LinkerIsLLD) + *LinkerIsLLD = false; + if (LinkerIsLLDDarwinNew) + *LinkerIsLLDDarwinNew = false; + // Get -fuse-ld= first to prevent -Wunused-command-line-argument. -fuse-ld= is // considered as the linker flavor, e.g. "bfd", "gold", or "lld". const Arg* A = Args.getLastArg(options::OPT_fuse_ld_EQ); @@ -657,8 +663,14 @@ std::string ToolChain::GetLinkerPath() const { LinkerName.append(UseLinker); std::string LinkerPath(GetProgramPath(LinkerName.c_str())); - if (llvm::sys::fs::can_execute(LinkerPath)) + if (llvm::sys::fs::can_execute(LinkerPath)) { + // FIXME: Remove lld.darwinnew here once it's the only MachO lld. + if (LinkerIsLLD) + *LinkerIsLLD = UseLinker == "lld" || UseLinker == "lld.darwinnew"; + if (LinkerIsLLDDarwinNew) + *LinkerIsLLDDarwinNew = UseLinker == "lld.darwinnew"; return LinkerPath; + } } if (A) diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp b/clang/lib/Driver/ToolChains/BareMetal.cpp index 91e2715404fec..e032d07112eb7 100644 --- a/clang/lib/Driver/ToolChains/BareMetal.cpp +++ b/clang/lib/Driver/ToolChains/BareMetal.cpp @@ -59,8 +59,22 @@ static bool isARMBareMetal(const llvm::Triple &Triple) { return true; } +static bool isRISCVBareMetal(const llvm::Triple &Triple) { + if (Triple.getArch() != llvm::Triple::riscv32 && + Triple.getArch() != llvm::Triple::riscv64) + return false; + + if (Triple.getVendor() != llvm::Triple::UnknownVendor) + return false; + + if (Triple.getOS() != llvm::Triple::UnknownOS) + return false; + + return Triple.getEnvironmentName() == "elf"; +} + bool BareMetal::handlesTarget(const llvm::Triple &Triple) { - return isARMBareMetal(Triple); + return isARMBareMetal(Triple) || isRISCVBareMetal(Triple); } Tool *BareMetal::buildLinker() const { diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 4d4a190713c1f..4e134be6f9719 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -4772,6 +4772,23 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, } } + if (Triple.isOSAIX() && Args.hasArg(options::OPT_maltivec)) { + if (Args.hasArg(options::OPT_mabi_EQ_vec_extabi)) { + CmdArgs.push_back("-mabi=vec-extabi"); + } else { + D.Diag(diag::err_aix_default_altivec_abi); + } + } + + if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ_vec_extabi, + options::OPT_mabi_EQ_vec_default)) { + if (!Triple.isOSAIX()) + D.Diag(diag::err_drv_unsupported_opt_for_target) + << A->getSpelling() << RawTriple.str(); + if (!Args.hasArg(options::OPT_maltivec)) + D.Diag(diag::err_aix_altivec); + } + if (Arg *A = Args.getLastArg(options::OPT_Wframe_larger_than_EQ)) { StringRef v = A->getValue(); CmdArgs.push_back("-mllvm"); diff --git a/clang/lib/Driver/ToolChains/Darwin.cpp b/clang/lib/Driver/ToolChains/Darwin.cpp index c847be9ee266f..db3d57a48098d 100644 --- a/clang/lib/Driver/ToolChains/Darwin.cpp +++ b/clang/lib/Driver/ToolChains/Darwin.cpp @@ -204,15 +204,19 @@ static bool shouldLinkerNotDedup(bool IsLinkerOnlyAction, const ArgList &Args) { void darwin::Linker::AddLinkArgs(Compilation &C, const ArgList &Args, ArgStringList &CmdArgs, const InputInfoList &Inputs, - unsigned Version[5]) const { + unsigned Version[5], bool LinkerIsLLD, + bool LinkerIsLLDDarwinNew) const { const Driver &D = getToolChain().getDriver(); const toolchains::MachO &MachOTC = getMachOToolChain(); // Newer linkers support -demangle. Pass it if supported and not disabled by // the user. - if (Version[0] >= 100 && !Args.hasArg(options::OPT_Z_Xlinker__no_demangle)) + if ((Version[0] >= 100 || LinkerIsLLD) && + !Args.hasArg(options::OPT_Z_Xlinker__no_demangle)) CmdArgs.push_back("-demangle"); + // FIXME: Pass most of the flags below that check Version if LinkerIsLLD too. + if (Args.hasArg(options::OPT_rdynamic) && Version[0] >= 137) CmdArgs.push_back("-export_dynamic"); @@ -249,7 +253,9 @@ void darwin::Linker::AddLinkArgs(Compilation &C, const ArgList &Args, // Since this is passed unconditionally, ld64 will never look for libLTO.dylib // next to it. That's ok since ld64 using a libLTO.dylib not matching the // clang version won't work anyways. - if (Version[0] >= 133) { + // lld is built at the same revision as clang and statically links in + // LLVM libraries, so it doesn't need libLTO.dylib. + if (Version[0] >= 133 && !LinkerIsLLD) { // Search for libLTO in /../lib/libLTO.dylib StringRef P = llvm::sys::path::parent_path(D.Dir); SmallString<128> LibLTOPath(P); @@ -332,7 +338,7 @@ void darwin::Linker::AddLinkArgs(Compilation &C, const ArgList &Args, Args.AddAllArgs(CmdArgs, options::OPT_init); // Add the deployment target. - if (Version[0] >= 520) + if (Version[0] >= 520 || LinkerIsLLDDarwinNew) MachOTC.addPlatformVersionArgs(Args, CmdArgs); else MachOTC.addMinVersionArgs(Args, CmdArgs); @@ -533,9 +539,14 @@ void darwin::Linker::ConstructJob(Compilation &C, const JobAction &JA, << A->getAsString(Args); } + bool LinkerIsLLD, LinkerIsLLDDarwinNew; + const char *Exec = Args.MakeArgString( + getToolChain().GetLinkerPath(&LinkerIsLLD, &LinkerIsLLDDarwinNew)); + // I'm not sure why this particular decomposition exists in gcc, but // we follow suite for ease of comparison. - AddLinkArgs(C, Args, CmdArgs, Inputs, Version); + AddLinkArgs(C, Args, CmdArgs, Inputs, Version, LinkerIsLLD, + LinkerIsLLDDarwinNew); if (willEmitRemarks(Args) && checkRemarksOptions(getToolChain().getDriver(), Args, @@ -693,7 +704,6 @@ void darwin::Linker::ConstructJob(Compilation &C, const JobAction &JA, "-filelist"}; } - const char *Exec = Args.MakeArgString(getToolChain().GetLinkerPath()); std::unique_ptr Cmd = std::make_unique( JA, *this, ResponseSupport, Exec, CmdArgs, Inputs, Output); Cmd->setInputFileList(std::move(InputFileList)); diff --git a/clang/lib/Driver/ToolChains/Darwin.h b/clang/lib/Driver/ToolChains/Darwin.h index c62c344a98da1..25c63fed922a8 100644 --- a/clang/lib/Driver/ToolChains/Darwin.h +++ b/clang/lib/Driver/ToolChains/Darwin.h @@ -63,7 +63,8 @@ class LLVM_LIBRARY_VISIBILITY Linker : public MachOTool { bool NeedsTempPath(const InputInfoList &Inputs) const; void AddLinkArgs(Compilation &C, const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs, - const InputInfoList &Inputs, unsigned Version[5]) const; + const InputInfoList &Inputs, unsigned Version[5], + bool LinkerIsLLD, bool LinkerIsLLDDarwinNew) const; public: Linker(const ToolChain &TC) : MachOTool("darwin::Linker", "linker", TC) {} diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index 1a9d01b9561c5..a4378290b2976 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -2740,7 +2740,13 @@ void Generic_GCC::printVerboseInfo(raw_ostream &OS) const { } bool Generic_GCC::IsUnwindTablesDefault(const ArgList &Args) const { - return getArch() == llvm::Triple::x86_64; + switch (getArch()) { + case llvm::Triple::aarch64: + case llvm::Triple::x86_64: + return true; + default: + return false; + } } bool Generic_GCC::isPICDefault() const { diff --git a/clang/lib/Driver/ToolChains/Linux.cpp b/clang/lib/Driver/ToolChains/Linux.cpp index b36ec27540786..7769cb492f6a8 100644 --- a/clang/lib/Driver/ToolChains/Linux.cpp +++ b/clang/lib/Driver/ToolChains/Linux.cpp @@ -185,17 +185,18 @@ static StringRef getOSLibDir(const llvm::Triple &Triple, const ArgList &Args) { return Triple.isArch32Bit() ? "lib" : "lib64"; } - // It happens that only x86 and PPC use the 'lib32' variant of oslibdir, and - // using that variant while targeting other architectures causes problems - // because the libraries are laid out in shared system roots that can't cope - // with a 'lib32' library search path being considered. So we only enable - // them when we know we may need it. + // It happens that only x86, PPC and SPARC use the 'lib32' variant of + // oslibdir, and using that variant while targeting other architectures causes + // problems because the libraries are laid out in shared system roots that + // can't cope with a 'lib32' library search path being considered. So we only + // enable them when we know we may need it. // // FIXME: This is a bit of a hack. We should really unify this code for // reasoning about oslibdir spellings with the lib dir spellings in the // GCCInstallationDetector, but that is a more significant refactoring. if (Triple.getArch() == llvm::Triple::x86 || - Triple.getArch() == llvm::Triple::ppc) + Triple.getArch() == llvm::Triple::ppc || + Triple.getArch() == llvm::Triple::sparc) return "lib32"; if (Triple.getArch() == llvm::Triple::x86_64 && diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp index 312c8b52c5e83..0dc12c7a84b56 100644 --- a/clang/lib/Driver/ToolChains/RISCVToolchain.cpp +++ b/clang/lib/Driver/ToolChains/RISCVToolchain.cpp @@ -31,6 +31,21 @@ static void addMultilibsFilePaths(const Driver &D, const MultilibSet &Multilibs, addPathIfExists(D, InstallPath + Path, Paths); } +// This function tests whether a gcc installation is present either +// through gcc-toolchain argument or in the same prefix where clang +// is installed. This helps decide whether to instantiate this toolchain +// or Baremetal toolchain. +bool RISCVToolChain::hasGCCToolchain(const Driver &D, + const llvm::opt::ArgList &Args) { + if (Args.getLastArg(options::OPT_gcc_toolchain)) + return true; + + SmallString<128> GCCDir; + llvm::sys::path::append(GCCDir, D.Dir, "..", D.getTargetTriple(), + "lib/crt0.o"); + return llvm::sys::fs::exists(GCCDir); +} + /// RISCV Toolchain RISCVToolChain::RISCVToolChain(const Driver &D, const llvm::Triple &Triple, const ArgList &Args) diff --git a/clang/lib/Driver/ToolChains/RISCVToolchain.h b/clang/lib/Driver/ToolChains/RISCVToolchain.h index 4734aee5f1ab7..62099bee04047 100644 --- a/clang/lib/Driver/ToolChains/RISCVToolchain.h +++ b/clang/lib/Driver/ToolChains/RISCVToolchain.h @@ -21,6 +21,7 @@ class LLVM_LIBRARY_VISIBILITY RISCVToolChain : public Generic_ELF { RISCVToolChain(const Driver &D, const llvm::Triple &Triple, const llvm::opt::ArgList &Args); + static bool hasGCCToolchain(const Driver &D, const llvm::opt::ArgList &Args); bool IsIntegratedAssemblerDefault() const override { return true; } void addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, diff --git a/clang/lib/Format/ContinuationIndenter.cpp b/clang/lib/Format/ContinuationIndenter.cpp index d99107cb8b2c0..d811f0f9e531b 100644 --- a/clang/lib/Format/ContinuationIndenter.cpp +++ b/clang/lib/Format/ContinuationIndenter.cpp @@ -400,7 +400,9 @@ bool ContinuationIndenter::mustBreak(const LineState &State) { return true; if (Current.is(TT_SelectorName) && !Previous.is(tok::at) && State.Stack.back().ObjCSelectorNameFound && - State.Stack.back().BreakBeforeParameter) + State.Stack.back().BreakBeforeParameter && + (Style.ObjCBreakBeforeNestedBlockParam || + !Current.startsSequence(TT_SelectorName, tok::colon, tok::caret))) return true; unsigned NewLineColumn = getNewLineColumn(State); diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 678de43adf46f..553c8a2e0d503 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -1048,12 +1048,6 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK, Opts.StrictVTablePointers = Args.hasArg(OPT_fstrict_vtable_pointers); Opts.ForceEmitVTables = Args.hasArg(OPT_fforce_emit_vtables); Opts.UnwindTables = Args.hasArg(OPT_munwind_tables); - Opts.ThreadModel = - std::string(Args.getLastArgValue(OPT_mthread_model, "posix")); - if (Opts.ThreadModel != "posix" && Opts.ThreadModel != "single") - Diags.Report(diag::err_drv_invalid_value) - << Args.getLastArg(OPT_mthread_model)->getAsString(Args) - << Opts.ThreadModel; Opts.TrapFuncName = std::string(Args.getLastArgValue(OPT_ftrap_function_EQ)); Opts.UseInitArray = !Args.hasArg(OPT_fno_use_init_array); @@ -1444,6 +1438,22 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK, !Args.hasArg(OPT_fvisibility))) Opts.IgnoreXCOFFVisibility = 1; + if (Arg *A = + Args.getLastArg(OPT_mabi_EQ_vec_default, OPT_mabi_EQ_vec_extabi)) { + if (!T.isOSAIX()) + Diags.Report(diag::err_drv_unsupported_opt_for_target) + << A->getSpelling() << T.str(); + + const Option &O = A->getOption(); + if (O.matches(OPT_mabi_EQ_vec_default)) + Diags.Report(diag::err_aix_default_altivec_abi) + << A->getSpelling() << T.str(); + else { + assert(O.matches(OPT_mabi_EQ_vec_extabi)); + Opts.EnableAIXExtendedAltivecABI = 1; + } + } + Opts.DependentLibraries = Args.getAllArgValues(OPT_dependent_lib); Opts.LinkerOptions = Args.getAllArgValues(OPT_linker_option); bool NeedLocTracking = false; @@ -2436,9 +2446,20 @@ void CompilerInvocation::setLangDefaults(LangOptions &Opts, InputKind IK, Opts.HIP = IK.getLanguage() == Language::HIP; Opts.CUDA = IK.getLanguage() == Language::CUDA || Opts.HIP; - if (Opts.CUDA) - // Set default FP_CONTRACT to FAST. + if (Opts.HIP) { + // HIP toolchain does not support 'Fast' FPOpFusion in backends since it + // fuses multiplication/addition instructions without contract flag from + // device library functions in LLVM bitcode, which causes accuracy loss in + // certain math functions, e.g. tan(-1e20) becomes -0.933 instead of 0.8446. + // For device library functions in bitcode to work, 'Strict' or 'Standard' + // FPOpFusion options in backends is needed. Therefore 'fast-honor-pragmas' + // FP contract option is used to allow fuse across statements in frontend + // whereas respecting contract flag in backend. + Opts.setDefaultFPContractMode(LangOptions::FPM_FastHonorPragmas); + } else if (Opts.CUDA) { + // Allow fuse across statements disregarding pragmas. Opts.setDefaultFPContractMode(LangOptions::FPM_Fast); + } Opts.RenderScript = IK.getLanguage() == Language::RenderScript; if (Opts.RenderScript) { @@ -3049,11 +3070,9 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK, !Args.hasArg(OPT_fno_concept_satisfaction_caching); if (Args.hasArg(OPT_fconcepts_ts)) Diags.Report(diag::warn_fe_concepts_ts_flag); - // Recovery AST still heavily relies on dependent-type machinery. - Opts.RecoveryAST = - Args.hasFlag(OPT_frecovery_ast, OPT_fno_recovery_ast, Opts.CPlusPlus); - Opts.RecoveryASTType = Args.hasFlag( - OPT_frecovery_ast_type, OPT_fno_recovery_ast_type, Opts.CPlusPlus); + Opts.RecoveryAST = Args.hasFlag(OPT_frecovery_ast, OPT_fno_recovery_ast); + Opts.RecoveryASTType = + Args.hasFlag(OPT_frecovery_ast_type, OPT_fno_recovery_ast_type); Opts.HeinousExtensions = Args.hasArg(OPT_fheinous_gnu_extensions); Opts.AccessControl = !Args.hasArg(OPT_fno_access_control); Opts.ElideConstructors = !Args.hasArg(OPT_fno_elide_constructors); @@ -3088,6 +3107,7 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK, ? 128 : Args.hasArg(OPT_mlong_double_64) ? 64 : 0; Opts.PPCIEEELongDouble = Args.hasArg(OPT_mabi_EQ_ieeelongdouble); + Opts.EnableAIXExtendedAltivecABI = Args.hasArg(OPT_mabi_EQ_vec_extabi); Opts.PICLevel = getLastArgIntValue(Args, OPT_pic_level, 0, Diags); Opts.ROPI = Args.hasArg(OPT_fropi); Opts.RWPI = Args.hasArg(OPT_frwpi); @@ -3374,6 +3394,8 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK, Opts.setDefaultFPContractMode(LangOptions::FPM_On); else if (Val == "off") Opts.setDefaultFPContractMode(LangOptions::FPM_Off); + else if (Val == "fast-honor-pragmas") + Opts.setDefaultFPContractMode(LangOptions::FPM_FastHonorPragmas); else Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << Val; } @@ -3552,6 +3574,16 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK, Args.hasFlag(OPT_fexperimental_relative_cxx_abi_vtables, OPT_fno_experimental_relative_cxx_abi_vtables, /*default=*/false); + + std::string ThreadModel = + std::string(Args.getLastArgValue(OPT_mthread_model, "posix")); + if (ThreadModel != "posix" && ThreadModel != "single") + Diags.Report(diag::err_drv_invalid_value) + << Args.getLastArg(OPT_mthread_model)->getAsString(Args) << ThreadModel; + Opts.setThreadModel( + llvm::StringSwitch(ThreadModel) + .Case("posix", LangOptions::ThreadModelKind::POSIX) + .Case("single", LangOptions::ThreadModelKind::Single)); } static bool isStrictlyPreprocessorAction(frontend::ActionKind Action) { @@ -3744,9 +3776,6 @@ static void ParseTargetArgs(TargetOptions &Opts, ArgList &Args, Opts.LinkerVersion = std::string(Args.getLastArgValue(OPT_target_linker_version)); Opts.OpenCLExtensionsAsWritten = Args.getAllArgValues(OPT_cl_ext_EQ); - Opts.ForceEnableInt128 = Args.hasArg(OPT_fforce_enable_int128); - Opts.NVPTXUseShortPointers = Args.hasFlag( - options::OPT_fcuda_short_ptr, options::OPT_fno_cuda_short_ptr, false); Opts.AllowAMDGPUUnsafeFPAtomics = Args.hasFlag(options::OPT_munsafe_fp_atomics, options::OPT_mno_unsafe_fp_atomics, false); diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp index 9a332be1e63cf..a303bbc30f465 100644 --- a/clang/lib/Frontend/InitPreprocessor.cpp +++ b/clang/lib/Frontend/InitPreprocessor.cpp @@ -403,6 +403,12 @@ static void InitializeStandardPredefinedMacros(const TargetInfo &TI, Builder.defineMacro("__STDCPP_DEFAULT_NEW_ALIGNMENT__", Twine(TI.getNewAlign() / TI.getCharWidth()) + TI.getTypeConstantSuffix(TI.getSizeType())); + + // -- __STDCPP_­THREADS__ + // Defined, and has the value integer literal 1, if and only if a + // program can have more than one thread of execution. + if (LangOpts.getThreadModel() == LangOptions::ThreadModelKind::POSIX) + Builder.defineMacro("__STDCPP_THREADS__", "1"); } // In C11 these are environment macros. In C++11 they are only defined diff --git a/clang/lib/Headers/intrin.h b/clang/lib/Headers/intrin.h index e7b76a3bb2ed7..a78b96997d186 100644 --- a/clang/lib/Headers/intrin.h +++ b/clang/lib/Headers/intrin.h @@ -214,10 +214,6 @@ unsigned char _interlockedbittestandreset64(__int64 volatile *, __int64); unsigned char _interlockedbittestandset64(__int64 volatile *, __int64); long _InterlockedCompareExchange_np(long volatile *_Destination, long _Exchange, long _Comparand); -unsigned char _InterlockedCompareExchange128(__int64 volatile *_Destination, - __int64 _ExchangeHigh, - __int64 _ExchangeLow, - __int64 *_CompareandResult); unsigned char _InterlockedCompareExchange128_np(__int64 volatile *_Destination, __int64 _ExchangeHigh, __int64 _ExchangeLow, @@ -427,6 +423,26 @@ __int64 _InterlockedCompareExchange64_nf(__int64 volatile *_Destination, __int64 _InterlockedCompareExchange64_rel(__int64 volatile *_Destination, __int64 _Exchange, __int64 _Comparand); #endif +#if defined(__x86_64__) || defined(__aarch64__) +unsigned char _InterlockedCompareExchange128(__int64 volatile *_Destination, + __int64 _ExchangeHigh, + __int64 _ExchangeLow, + __int64 *_ComparandResult); +#endif +#if defined(__aarch64__) +unsigned char _InterlockedCompareExchange128_acq(__int64 volatile *_Destination, + __int64 _ExchangeHigh, + __int64 _ExchangeLow, + __int64 *_ComparandResult); +unsigned char _InterlockedCompareExchange128_nf(__int64 volatile *_Destination, + __int64 _ExchangeHigh, + __int64 _ExchangeLow, + __int64 *_ComparandResult); +unsigned char _InterlockedCompareExchange128_rel(__int64 volatile *_Destination, + __int64 _ExchangeHigh, + __int64 _ExchangeLow, + __int64 *_ComparandResult); +#endif /*----------------------------------------------------------------------------*\ |* movs, stos diff --git a/clang/lib/Parse/ParseCXXInlineMethods.cpp b/clang/lib/Parse/ParseCXXInlineMethods.cpp index 12941f214cbc6..b0335905b6f88 100644 --- a/clang/lib/Parse/ParseCXXInlineMethods.cpp +++ b/clang/lib/Parse/ParseCXXInlineMethods.cpp @@ -108,7 +108,7 @@ NamedDecl *Parser::ParseCXXInlineMethodDef( // or if we are about to parse function member template then consume // the tokens and store them for parsing at the end of the translation unit. if (getLangOpts().DelayedTemplateParsing && - D.getFunctionDefinitionKind() == FDK_Definition && + D.getFunctionDefinitionKind() == FunctionDefinitionKind::Definition && !D.getDeclSpec().hasConstexprSpecifier() && !(FnD && FnD->getAsFunction() && FnD->getAsFunction()->getReturnType()->getContainedAutoType()) && diff --git a/clang/lib/Parse/ParseDeclCXX.cpp b/clang/lib/Parse/ParseDeclCXX.cpp index 0a810fc393a6f..9525c0222b9fd 100644 --- a/clang/lib/Parse/ParseDeclCXX.cpp +++ b/clang/lib/Parse/ParseDeclCXX.cpp @@ -1045,8 +1045,16 @@ void Parser::AnnotateExistingDecltypeSpecifier(const DeclSpec& DS, SourceLocation StartLoc, SourceLocation EndLoc) { // make sure we have a token we can turn into an annotation token - if (PP.isBacktrackEnabled()) + if (PP.isBacktrackEnabled()) { PP.RevertCachedTokens(1); + if (DS.getTypeSpecType() == TST_error) { + // We encountered an error in parsing 'decltype(...)' so lets annotate all + // the tokens in the backtracking cache - that we likely had to skip over + // to get to a token that allows us to resume parsing, such as a + // semi-colon. + EndLoc = PP.getLastCachedTokenLocation(); + } + } else PP.EnterToken(Tok, /*IsReinject*/true); @@ -2707,23 +2715,23 @@ Parser::ParseCXXClassMemberDeclaration(AccessSpecifier AS, if (getLangOpts().MicrosoftExt && DeclaratorInfo.isDeclarationOfFunction()) TryConsumePureSpecifier(/*AllowDefinition*/ true); - FunctionDefinitionKind DefinitionKind = FDK_Declaration; + FunctionDefinitionKind DefinitionKind = FunctionDefinitionKind::Declaration; // function-definition: // // In C++11, a non-function declarator followed by an open brace is a // braced-init-list for an in-class member initialization, not an // erroneous function definition. if (Tok.is(tok::l_brace) && !getLangOpts().CPlusPlus11) { - DefinitionKind = FDK_Definition; + DefinitionKind = FunctionDefinitionKind::Definition; } else if (DeclaratorInfo.isFunctionDeclarator()) { if (Tok.isOneOf(tok::l_brace, tok::colon, tok::kw_try)) { - DefinitionKind = FDK_Definition; + DefinitionKind = FunctionDefinitionKind::Definition; } else if (Tok.is(tok::equal)) { const Token &KW = NextToken(); if (KW.is(tok::kw_default)) - DefinitionKind = FDK_Defaulted; + DefinitionKind = FunctionDefinitionKind::Defaulted; else if (KW.is(tok::kw_delete)) - DefinitionKind = FDK_Deleted; + DefinitionKind = FunctionDefinitionKind::Deleted; else if (KW.is(tok::code_completion)) { Actions.CodeCompleteAfterFunctionEquals(DeclaratorInfo); cutOffParsing(); @@ -2736,13 +2744,14 @@ Parser::ParseCXXClassMemberDeclaration(AccessSpecifier AS, // C++11 [dcl.attr.grammar] p4: If an attribute-specifier-seq appertains // to a friend declaration, that declaration shall be a definition. if (DeclaratorInfo.isFunctionDeclarator() && - DefinitionKind == FDK_Declaration && DS.isFriendSpecified()) { + DefinitionKind == FunctionDefinitionKind::Declaration && + DS.isFriendSpecified()) { // Diagnose attributes that appear before decl specifier: // [[]] friend int foo(); ProhibitAttributes(FnAttrs); } - if (DefinitionKind != FDK_Declaration) { + if (DefinitionKind != FunctionDefinitionKind::Declaration) { if (!DeclaratorInfo.isFunctionDeclarator()) { Diag(DeclaratorInfo.getIdentifierLoc(), diag::err_func_def_no_params); ConsumeBrace(); diff --git a/clang/lib/Parse/ParseExpr.cpp b/clang/lib/Parse/ParseExpr.cpp index d4de0bf202d0e..5cac7c444c881 100644 --- a/clang/lib/Parse/ParseExpr.cpp +++ b/clang/lib/Parse/ParseExpr.cpp @@ -3453,7 +3453,7 @@ void Parser::ParseBlockId(SourceLocation CaretLoc) { // Parse the block-declarator. Declarator DeclaratorInfo(DS, DeclaratorContext::BlockLiteral); - DeclaratorInfo.setFunctionDefinitionKind(FDK_Definition); + DeclaratorInfo.setFunctionDefinitionKind(FunctionDefinitionKind::Definition); ParseDeclarator(DeclaratorInfo); MaybeParseGNUAttributes(DeclaratorInfo); @@ -3492,7 +3492,7 @@ ExprResult Parser::ParseBlockLiteralExpression() { // Parse the return type if present. DeclSpec DS(AttrFactory); Declarator ParamInfo(DS, DeclaratorContext::BlockLiteral); - ParamInfo.setFunctionDefinitionKind(FDK_Definition); + ParamInfo.setFunctionDefinitionKind(FunctionDefinitionKind::Definition); // FIXME: Since the return type isn't actually parsed, it can't be used to // fill ParamInfo with an initial valid range, so do it manually. ParamInfo.SetSourceRange(SourceRange(Tok.getLocation(), Tok.getLocation())); diff --git a/clang/lib/Parse/Parser.cpp b/clang/lib/Parse/Parser.cpp index 825e0045615d0..9b0f921b42692 100644 --- a/clang/lib/Parse/Parser.cpp +++ b/clang/lib/Parse/Parser.cpp @@ -1228,7 +1228,7 @@ Decl *Parser::ParseFunctionDefinition(ParsingDeclarator &D, Scope::CompoundStmtScope); Scope *ParentScope = getCurScope()->getParent(); - D.setFunctionDefinitionKind(FDK_Definition); + D.setFunctionDefinitionKind(FunctionDefinitionKind::Definition); Decl *DP = Actions.HandleDeclarator(ParentScope, D, TemplateParameterLists); D.complete(DP); @@ -1259,7 +1259,7 @@ Decl *Parser::ParseFunctionDefinition(ParsingDeclarator &D, Scope::CompoundStmtScope); Scope *ParentScope = getCurScope()->getParent(); - D.setFunctionDefinitionKind(FDK_Definition); + D.setFunctionDefinitionKind(FunctionDefinitionKind::Definition); Decl *FuncDecl = Actions.HandleDeclarator(ParentScope, D, MultiTemplateParamsArg()); D.complete(FuncDecl); diff --git a/clang/lib/Sema/SemaAttr.cpp b/clang/lib/Sema/SemaAttr.cpp index 920cbf5cab59c..ae6c3ea7313e1 100644 --- a/clang/lib/Sema/SemaAttr.cpp +++ b/clang/lib/Sema/SemaAttr.cpp @@ -966,6 +966,8 @@ void Sema::ActOnPragmaFPContract(SourceLocation Loc, case LangOptions::FPM_Off: NewFPFeatures.setDisallowFPContract(); break; + case LangOptions::FPM_FastHonorPragmas: + llvm_unreachable("Should not happen"); } FpPragmaStack.Act(Loc, Sema::PSK_Set, StringRef(), NewFPFeatures); CurFPFeatures = NewFPFeatures.applyOverrides(getLangOpts()); diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index b83aad11058c6..82468a6cc4303 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -5568,7 +5568,7 @@ static bool RebuildDeclaratorInCurrentInstantiation(Sema &S, Declarator &D, } Decl *Sema::ActOnDeclarator(Scope *S, Declarator &D) { - D.setFunctionDefinitionKind(FDK_Declaration); + D.setFunctionDefinitionKind(FunctionDefinitionKind::Declaration); Decl *Dcl = HandleDeclarator(S, D, MultiTemplateParamsArg()); if (OriginalLexicalContext && OriginalLexicalContext->isObjCContainer() && @@ -9194,17 +9194,17 @@ Sema::ActOnFunctionDeclarator(Scope *S, Declarator &D, DeclContext *DC, // If a function is defined as defaulted or deleted, mark it as such now. // We'll do the relevant checks on defaulted / deleted functions later. switch (D.getFunctionDefinitionKind()) { - case FDK_Declaration: - case FDK_Definition: - break; + case FunctionDefinitionKind::Declaration: + case FunctionDefinitionKind::Definition: + break; - case FDK_Defaulted: - NewFD->setDefaulted(); - break; + case FunctionDefinitionKind::Defaulted: + NewFD->setDefaulted(); + break; - case FDK_Deleted: - NewFD->setDeletedAsWritten(); - break; + case FunctionDefinitionKind::Deleted: + NewFD->setDeletedAsWritten(); + break; } if (isa(NewFD) && DC == CurContext && @@ -9901,17 +9901,17 @@ Sema::ActOnFunctionDeclarator(Scope *S, Declarator &D, DeclContext *DC, // because Sema::ActOnStartOfFunctionDef has not been called yet. if (const auto *NBA = NewFD->getAttr()) switch (D.getFunctionDefinitionKind()) { - case FDK_Defaulted: - case FDK_Deleted: + case FunctionDefinitionKind::Defaulted: + case FunctionDefinitionKind::Deleted: Diag(NBA->getLocation(), diag::err_attribute_no_builtin_on_defaulted_deleted_function) << NBA->getSpelling(); break; - case FDK_Declaration: + case FunctionDefinitionKind::Declaration: Diag(NBA->getLocation(), diag::err_attribute_no_builtin_on_non_definition) << NBA->getSpelling(); break; - case FDK_Definition: + case FunctionDefinitionKind::Definition: break; } @@ -13831,7 +13831,7 @@ Sema::ActOnStartOfFunctionDef(Scope *FnBodyScope, Declarator &D, ActOnStartOfFunctionDefinitionInOpenMPDeclareVariantScope( ParentScope, D, TemplateParameterLists, Bases); - D.setFunctionDefinitionKind(FDK_Definition); + D.setFunctionDefinitionKind(FunctionDefinitionKind::Definition); Decl *DP = HandleDeclarator(ParentScope, D, TemplateParameterLists); Decl *Dcl = ActOnStartOfFunctionDef(FnBodyScope, DP, SkipBody); diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index d35490501a6ff..2cda9874e203a 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -3862,8 +3862,7 @@ ExprResult Sema::ActOnNumericConstant(const Token &Tok, Scope *UDLScope) { if (Ty == Context.DoubleTy) { if (getLangOpts().SinglePrecisionConstants) { - const BuiltinType *BTy = Ty->getAs(); - if (BTy->getKind() != BuiltinType::Float) { + if (Ty->castAs()->getKind() != BuiltinType::Float) { Res = ImpCastExprToType(Res, Context.FloatTy, CK_FloatingCast).get(); } } else if (getLangOpts().OpenCL && @@ -4835,6 +4834,9 @@ void Sema::CheckAddressOfNoDeref(const Expr *E) { } void Sema::CheckSubscriptAccessOfNoDeref(const ArraySubscriptExpr *E) { + if (isUnevaluatedContext()) + return; + QualType ResultTy = E->getType(); ExpressionEvaluationContextRecord &LastRecord = ExprEvalContexts.back(); @@ -14755,7 +14757,8 @@ ExprResult Sema::CreateBuiltinUnaryOp(SourceLocation OpLoc, OpLoc, CanOverflow, CurFPFeatureOverrides()); if (Opc == UO_Deref && UO->getType()->hasAttr(attr::NoDeref) && - !isa(UO->getType().getDesugaredType(Context))) + !isa(UO->getType().getDesugaredType(Context)) && + !isUnevaluatedContext()) ExprEvalContexts.back().PossibleDerefs.insert(UO); // Convert the result back to a half vector. @@ -15251,10 +15254,10 @@ void Sema::ActOnBlockArguments(SourceLocation CaretLoc, Declarator &ParamInfo, CurBlock->TheDecl->setSignatureAsWritten(Sig); CurBlock->FunctionType = T; - const FunctionType *Fn = T->getAs(); + const auto *Fn = T->castAs(); QualType RetTy = Fn->getReturnType(); bool isVariadic = - (isa(Fn) && cast(Fn)->isVariadic()); + (isa(Fn) && cast(Fn)->isVariadic()); CurBlock->TheDecl->setIsVariadic(isVariadic); @@ -17559,7 +17562,11 @@ bool Sema::tryCaptureVariable( if (IsTargetCap || IsOpenMPPrivateDecl == OMPC_private || (IsGlobal && !IsGlobalCap)) { Nested = !IsTargetCap; + bool HasConst = DeclRefType.isConstQualified(); DeclRefType = DeclRefType.getUnqualifiedType(); + // Don't lose diagnostics about assignments to const. + if (HasConst) + DeclRefType.addConst(); CaptureType = Context.getLValueReferenceType(DeclRefType); break; } diff --git a/clang/lib/Sema/SemaExprMember.cpp b/clang/lib/Sema/SemaExprMember.cpp index 93ed756e084bb..23cfae81df461 100644 --- a/clang/lib/Sema/SemaExprMember.cpp +++ b/clang/lib/Sema/SemaExprMember.cpp @@ -1734,6 +1734,9 @@ ExprResult Sema::ActOnMemberAccessExpr(Scope *S, Expr *Base, } void Sema::CheckMemberAccessOfNoDeref(const MemberExpr *E) { + if (isUnevaluatedContext()) + return; + QualType ResultTy = E->getType(); // Do not warn on member accesses to arrays since this returns an array diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp index efc309624ce14..ee478b5ccfb85 100644 --- a/clang/lib/Sema/SemaInit.cpp +++ b/clang/lib/Sema/SemaInit.cpp @@ -3442,6 +3442,7 @@ void InitializationSequence::Step::Destroy() { case SK_QualificationConversionRValue: case SK_QualificationConversionXValue: case SK_QualificationConversionLValue: + case SK_FunctionReferenceConversion: case SK_AtomicConversion: case SK_ListInitialization: case SK_UnwrapInitList: @@ -3620,6 +3621,13 @@ void InitializationSequence::AddQualificationConversionStep(QualType Ty, Steps.push_back(S); } +void InitializationSequence::AddFunctionReferenceConversionStep(QualType Ty) { + Step S; + S.Kind = SK_FunctionReferenceConversion; + S.Type = Ty; + Steps.push_back(S); +} + void InitializationSequence::AddAtomicConversionStep(QualType Ty) { Step S; S.Kind = SK_AtomicConversion; @@ -4653,7 +4661,7 @@ static OverloadingResult TryRefInitWithConversionFunction( else if (RefConv & Sema::ReferenceConversions::ObjC) Sequence.AddObjCObjectConversionStep(cv1T1); else if (RefConv & Sema::ReferenceConversions::Function) - Sequence.AddQualificationConversionStep(cv1T1, VK); + Sequence.AddFunctionReferenceConversionStep(cv1T1); else if (RefConv & Sema::ReferenceConversions::Qualification) { if (!S.Context.hasSameType(cv1T4, cv1T1)) Sequence.AddQualificationConversionStep(cv1T1, VK); @@ -4755,12 +4763,12 @@ static void TryReferenceInitializationCore(Sema &S, Sequence.AddDerivedToBaseCastStep(cv1T1, VK_LValue); else Sequence.AddObjCObjectConversionStep(cv1T1); - } else if (RefConv & (Sema::ReferenceConversions::Qualification | - Sema::ReferenceConversions::Function)) { + } else if (RefConv & Sema::ReferenceConversions::Qualification) { // Perform a (possibly multi-level) qualification conversion. - // FIXME: Should we use a different step kind for function conversions? Sequence.AddQualificationConversionStep(cv1T1, Initializer->getValueKind()); + } else if (RefConv & Sema::ReferenceConversions::Function) { + Sequence.AddFunctionReferenceConversionStep(cv1T1); } // We only create a temporary here when binding a reference to a @@ -8038,6 +8046,7 @@ ExprResult InitializationSequence::Perform(Sema &S, case SK_QualificationConversionLValue: case SK_QualificationConversionXValue: case SK_QualificationConversionRValue: + case SK_FunctionReferenceConversion: case SK_AtomicConversion: case SK_ConversionSequence: case SK_ConversionSequenceNoNarrowing: @@ -8303,6 +8312,13 @@ ExprResult InitializationSequence::Perform(Sema &S, break; } + case SK_FunctionReferenceConversion: + assert(CurInit.get()->isLValue() && + "function reference should be lvalue"); + CurInit = + S.ImpCastExprToType(CurInit.get(), Step->Type, CK_NoOp, VK_LValue); + break; + case SK_AtomicConversion: { assert(CurInit.get()->isRValue() && "cannot convert glvalue to atomic"); CurInit = S.ImpCastExprToType(CurInit.get(), Step->Type, @@ -9573,6 +9589,10 @@ void InitializationSequence::dump(raw_ostream &OS) const { OS << "qualification conversion (lvalue)"; break; + case SK_FunctionReferenceConversion: + OS << "function reference conversion"; + break; + case SK_AtomicConversion: OS << "non-atomic-to-atomic conversion"; break; diff --git a/clang/lib/Sema/SemaLookup.cpp b/clang/lib/Sema/SemaLookup.cpp index ef2e9f156f902..77b82f335a1af 100644 --- a/clang/lib/Sema/SemaLookup.cpp +++ b/clang/lib/Sema/SemaLookup.cpp @@ -2123,47 +2123,6 @@ static bool LookupQualifiedNameInUsingDirectives(Sema &S, LookupResult &R, return Found; } -/// Callback that looks for any member of a class with the given name. -static bool LookupAnyMember(const CXXBaseSpecifier *Specifier, - CXXBasePath &Path, DeclarationName Name) { - RecordDecl *BaseRecord = Specifier->getType()->castAs()->getDecl(); - - Path.Decls = BaseRecord->lookup(Name); - return !Path.Decls.empty(); -} - -/// Determine whether the given set of member declarations contains only -/// static members, nested types, and enumerators. -template -static bool HasOnlyStaticMembers(InputIterator First, InputIterator Last) { - Decl *D = (*First)->getUnderlyingDecl(); - if (isa(D) || isa(D) || isa(D)) - return true; - - if (isa(D)) { - // Determine whether all of the methods are static. - bool AllMethodsAreStatic = true; - for(; First != Last; ++First) { - D = (*First)->getUnderlyingDecl(); - - if (!isa(D)) { - assert(isa(D) && "Non-function must be a tag decl"); - break; - } - - if (!cast(D)->isStatic()) { - AllMethodsAreStatic = false; - break; - } - } - - if (AllMethodsAreStatic) - return true; - } - - return false; -} - /// Perform qualified name lookup into a given context. /// /// Qualified name lookup (C++ [basic.lookup.qual]) is used to find @@ -2241,6 +2200,13 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, if (!LookupRec || !LookupRec->getDefinition()) return false; + // We're done for lookups that can never succeed for C++ classes. + if (R.getLookupKind() == LookupOperatorName || + R.getLookupKind() == LookupNamespaceName || + R.getLookupKind() == LookupObjCProtocolName || + R.getLookupKind() == LookupLabel) + return false; + // If we're performing qualified name lookup into a dependent class, // then we are actually looking into a current instantiation. If we have any // dependent base classes, then we either have to delay lookup until @@ -2253,59 +2219,27 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, } // Perform lookup into our base classes. - CXXBasePaths Paths; - Paths.setOrigin(LookupRec); - - // Look for this member in our base classes - bool (*BaseCallback)(const CXXBaseSpecifier *Specifier, CXXBasePath &Path, - DeclarationName Name) = nullptr; - switch (R.getLookupKind()) { - case LookupObjCImplicitSelfParam: - case LookupOrdinaryName: - case LookupMemberName: - case LookupRedeclarationWithLinkage: - case LookupLocalFriendName: - case LookupDestructorName: - BaseCallback = &CXXRecordDecl::FindOrdinaryMember; - break; - - case LookupTagName: - BaseCallback = &CXXRecordDecl::FindTagMember; - break; - - case LookupAnyName: - BaseCallback = &LookupAnyMember; - break; - - case LookupOMPReductionName: - BaseCallback = &CXXRecordDecl::FindOMPReductionMember; - break; - - case LookupOMPMapperName: - BaseCallback = &CXXRecordDecl::FindOMPMapperMember; - break; - - case LookupUsingDeclName: - // This lookup is for redeclarations only. - - case LookupOperatorName: - case LookupNamespaceName: - case LookupObjCProtocolName: - case LookupLabel: - // These lookups will never find a member in a C++ class (or base class). - return false; - - case LookupNestedNameSpecifierName: - BaseCallback = &CXXRecordDecl::FindNestedNameSpecifierMember; - break; - } DeclarationName Name = R.getLookupName(); - if (!LookupRec->lookupInBases( - [=](const CXXBaseSpecifier *Specifier, CXXBasePath &Path) { - return BaseCallback(Specifier, Path, Name); - }, - Paths)) + unsigned IDNS = R.getIdentifierNamespace(); + + // Look for this member in our base classes. + auto BaseCallback = [Name, IDNS](const CXXBaseSpecifier *Specifier, + CXXBasePath &Path) -> bool { + CXXRecordDecl *BaseRecord = Specifier->getType()->getAsCXXRecordDecl(); + // Drop leading non-matching lookup results from the declaration list so + // we don't need to consider them again below. + for (Path.Decls = BaseRecord->lookup(Name); !Path.Decls.empty(); + Path.Decls = Path.Decls.slice(1)) { + if (Path.Decls.front()->isInIdentifierNamespace(IDNS)) + return true; + } + return false; + }; + + CXXBasePaths Paths; + Paths.setOrigin(LookupRec); + if (!LookupRec->lookupInBases(BaseCallback, Paths)) return false; R.setNamingClass(LookupRec); @@ -2320,6 +2254,85 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, int SubobjectNumber = 0; AccessSpecifier SubobjectAccess = AS_none; + // Check whether the given lookup result contains only static members. + auto HasOnlyStaticMembers = [&](DeclContextLookupResult Result) { + for (NamedDecl *ND : Result) + if (ND->isInIdentifierNamespace(IDNS) && ND->isCXXInstanceMember()) + return false; + return true; + }; + + bool TemplateNameLookup = R.isTemplateNameLookup(); + + // Determine whether two sets of members contain the same members, as + // required by C++ [class.member.lookup]p6. + auto HasSameDeclarations = [&](DeclContextLookupResult A, + DeclContextLookupResult B) { + using Iterator = DeclContextLookupResult::iterator; + using Result = const void *; + + auto Next = [&](Iterator &It, Iterator End) -> Result { + while (It != End) { + NamedDecl *ND = *It++; + if (!ND->isInIdentifierNamespace(IDNS)) + continue; + + // C++ [temp.local]p3: + // A lookup that finds an injected-class-name (10.2) can result in + // an ambiguity in certain cases (for example, if it is found in + // more than one base class). If all of the injected-class-names + // that are found refer to specializations of the same class + // template, and if the name is used as a template-name, the + // reference refers to the class template itself and not a + // specialization thereof, and is not ambiguous. + if (TemplateNameLookup) + if (auto *TD = getAsTemplateNameDecl(ND)) + ND = TD; + + // C++ [class.member.lookup]p3: + // type declarations (including injected-class-names) are replaced by + // the types they designate + if (const TypeDecl *TD = dyn_cast(ND->getUnderlyingDecl())) { + QualType T = Context.getTypeDeclType(TD); + return T.getCanonicalType().getAsOpaquePtr(); + } + + return ND->getUnderlyingDecl()->getCanonicalDecl(); + } + return nullptr; + }; + + // We'll often find the declarations are in the same order. Handle this + // case (and the special case of only one declaration) efficiently. + Iterator AIt = A.begin(), BIt = B.begin(), AEnd = A.end(), BEnd = B.end(); + while (true) { + Result AResult = Next(AIt, AEnd); + Result BResult = Next(BIt, BEnd); + if (!AResult && !BResult) + return true; + if (!AResult || !BResult) + return false; + if (AResult != BResult) { + // Found a mismatch; carefully check both lists, accounting for the + // possibility of declarations appearing more than once. + llvm::SmallDenseMap AResults; + for (; AResult; AResult = Next(AIt, AEnd)) + AResults.insert({AResult, /*FoundInB*/false}); + unsigned Found = 0; + for (; BResult; BResult = Next(BIt, BEnd)) { + auto It = AResults.find(BResult); + if (It == AResults.end()) + return false; + if (!It->second) { + It->second = true; + ++Found; + } + } + return AResults.size() == Found; + } + } + }; + for (CXXBasePaths::paths_iterator Path = Paths.begin(), PathEnd = Paths.end(); Path != PathEnd; ++Path) { const CXXBasePathElement &PathElement = Path->back(); @@ -2336,51 +2349,25 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, continue; } - if (SubobjectType - != Context.getCanonicalType(PathElement.Base->getType())) { + if (SubobjectType != + Context.getCanonicalType(PathElement.Base->getType())) { // We found members of the given name in two subobjects of // different types. If the declaration sets aren't the same, this // lookup is ambiguous. - if (HasOnlyStaticMembers(Path->Decls.begin(), Path->Decls.end())) { - CXXBasePaths::paths_iterator FirstPath = Paths.begin(); - DeclContext::lookup_iterator FirstD = FirstPath->Decls.begin(); - DeclContext::lookup_iterator CurrentD = Path->Decls.begin(); - - // Get the decl that we should use for deduplicating this lookup. - auto GetRepresentativeDecl = [&](NamedDecl *D) -> Decl * { - // C++ [temp.local]p3: - // A lookup that finds an injected-class-name (10.2) can result in - // an ambiguity in certain cases (for example, if it is found in - // more than one base class). If all of the injected-class-names - // that are found refer to specializations of the same class - // template, and if the name is used as a template-name, the - // reference refers to the class template itself and not a - // specialization thereof, and is not ambiguous. - if (R.isTemplateNameLookup()) - if (auto *TD = getAsTemplateNameDecl(D)) - D = TD; - return D->getUnderlyingDecl()->getCanonicalDecl(); - }; - - while (FirstD != FirstPath->Decls.end() && - CurrentD != Path->Decls.end()) { - if (GetRepresentativeDecl(*FirstD) != - GetRepresentativeDecl(*CurrentD)) - break; - - ++FirstD; - ++CurrentD; - } - - if (FirstD == FirstPath->Decls.end() && - CurrentD == Path->Decls.end()) - continue; - } + // + // FIXME: The language rule says that this applies irrespective of + // whether the sets contain only static members. + if (HasOnlyStaticMembers(Path->Decls) && + HasSameDeclarations(Paths.begin()->Decls, Path->Decls)) + continue; R.setAmbiguousBaseSubobjectTypes(Paths); return true; } + // FIXME: This language rule no longer exists. Checking for ambiguous base + // subobjects should be done as part of formation of a class member access + // expression (when converting the object parameter to the member's type). if (SubobjectNumber != PathElement.SubobjectNumber) { // We have a different subobject of the same type. @@ -2388,7 +2375,7 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, // A static member, a nested type or an enumerator defined in // a base class T can unambiguously be found even if an object // has more than one base class subobject of type T. - if (HasOnlyStaticMembers(Path->Decls.begin(), Path->Decls.end())) + if (HasOnlyStaticMembers(Path->Decls)) continue; // We have found a nonstatic member name in multiple, distinct @@ -2403,7 +2390,8 @@ bool Sema::LookupQualifiedName(LookupResult &R, DeclContext *LookupCtx, for (auto *D : Paths.front().Decls) { AccessSpecifier AS = CXXRecordDecl::MergeAccess(SubobjectAccess, D->getAccess()); - R.addDecl(D, AS); + if (NamedDecl *ND = R.getAcceptableDecl(D)) + R.addDecl(ND, AS); } R.resolveKind(); return true; @@ -2559,13 +2547,23 @@ void Sema::DiagnoseAmbiguousLookup(LookupResult &Result) { << Name << LookupRange; CXXBasePaths *Paths = Result.getBasePaths(); - std::set DeclsPrinted; + std::set DeclsPrinted; for (CXXBasePaths::paths_iterator Path = Paths->begin(), PathEnd = Paths->end(); Path != PathEnd; ++Path) { - Decl *D = Path->Decls.front(); - if (DeclsPrinted.insert(D).second) - Diag(D->getLocation(), diag::note_ambiguous_member_found); + const NamedDecl *D = Path->Decls.front(); + if (!D->isInIdentifierNamespace(Result.getIdentifierNamespace())) + continue; + if (DeclsPrinted.insert(D).second) { + if (const auto *TD = dyn_cast(D->getUnderlyingDecl())) + Diag(D->getLocation(), diag::note_ambiguous_member_type_found) + << TD->getUnderlyingType(); + else if (const auto *TD = dyn_cast(D->getUnderlyingDecl())) + Diag(D->getLocation(), diag::note_ambiguous_member_type_found) + << Context.getTypeDeclType(TD); + else + Diag(D->getLocation(), diag::note_ambiguous_member_found); + } } break; } diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index b882eccf5288f..63ea297493ffd 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -5942,7 +5942,7 @@ void Sema::ActOnStartOfFunctionDefinitionInOpenMPDeclareVariantScope( llvm::omp::TraitProperty::implementation_extension_disable_implicit_base); // If no base was found we create a declaration that we use as base. if (Bases.empty() && UseImplicitBase) { - D.setFunctionDefinitionKind(FDK_Declaration); + D.setFunctionDefinitionKind(FunctionDefinitionKind::Declaration); Decl *BaseD = HandleDeclarator(S, D, TemplateParamLists); BaseD->setImplicit(true); if (auto *BaseTemplD = dyn_cast(BaseD)) diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp index 1d3151799a47b..c0b3afa25ea6c 100644 --- a/clang/lib/Sema/SemaType.cpp +++ b/clang/lib/Sema/SemaType.cpp @@ -3604,10 +3604,9 @@ static void warnAboutAmbiguousFunction(Sema &S, Declarator &D, // Only warn if this declarator is declaring a function at block scope, and // doesn't have a storage class (such as 'extern') specified. if (!D.isFunctionDeclarator() || - D.getFunctionDefinitionKind() != FDK_Declaration || + D.getFunctionDefinitionKind() != FunctionDefinitionKind::Declaration || !S.CurContext->isFunctionOrMethod() || - D.getDeclSpec().getStorageClassSpec() - != DeclSpec::SCS_unspecified) + D.getDeclSpec().getStorageClassSpec() != DeclSpec::SCS_unspecified) return; // Inside a condition, a direct initializer is not permitted. We allow one to @@ -5072,7 +5071,8 @@ static TypeSourceInfo *GetFullTypeForDeclarator(TypeProcessingState &state, !(S.getLangOpts().CPlusPlus && (T->isDependentType() || T->isRecordType()))) { if (T->isVoidType() && !S.getLangOpts().CPlusPlus && - D.getFunctionDefinitionKind() == FDK_Definition) { + D.getFunctionDefinitionKind() == + FunctionDefinitionKind::Definition) { // [6.9.1/3] qualified void return is invalid on a C // function definition. Apparently ok on declarations and // in C++ though (!) @@ -5443,7 +5443,8 @@ static TypeSourceInfo *GetFullTypeForDeclarator(TypeProcessingState &state, // The empty list in a function declarator that is not part of a definition // of that function specifies that no information about the number or types // of the parameters is supplied. - if (!LangOpts.CPlusPlus && D.getFunctionDefinitionKind() == FDK_Declaration) { + if (!LangOpts.CPlusPlus && + D.getFunctionDefinitionKind() == FunctionDefinitionKind::Declaration) { bool IsBlock = false; for (const DeclaratorChunk &DeclType : D.type_objects()) { switch (DeclType.Kind) { diff --git a/clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp index b2822e5307f3a..d4901eb0abbb6 100644 --- a/clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/FuchsiaHandleChecker.cpp @@ -53,7 +53,7 @@ // // Note that, the analyzer does not always know for sure if a function failed // or succeeded. In those cases we use the state MaybeAllocated. -// Thus, the diagramm above captures the intent, not implementation details. +// Thus, the diagram above captures the intent, not implementation details. // // Due to the fact that the number of handle related syscalls in Fuchsia // is large, we adopt the annotation attributes to descript syscalls' @@ -226,32 +226,70 @@ static const ExplodedNode *getAcquireSite(const ExplodedNode *N, SymbolRef Sym, return nullptr; } -/// Returns the symbols extracted from the argument or null if it cannot be -/// found. -static SymbolRef getFuchsiaHandleSymbol(QualType QT, SVal Arg, - ProgramStateRef State) { +namespace { +class FuchsiaHandleSymbolVisitor final : public SymbolVisitor { +public: + FuchsiaHandleSymbolVisitor(ProgramStateRef State) : State(std::move(State)) {} + ProgramStateRef getState() const { return State; } + + bool VisitSymbol(SymbolRef S) override { + if (const auto *HandleType = S->getType()->getAs()) + if (HandleType->getDecl()->getName() == HandleTypeName) + Symbols.push_back(S); + return true; + } + + SmallVector GetSymbols() { return Symbols; } + +private: + SmallVector Symbols; + ProgramStateRef State; +}; +} // end anonymous namespace + +/// Returns the symbols extracted from the argument or empty vector if it cannot +/// be found. It is unlikely to have over 1024 symbols in one argument. +static SmallVector +getFuchsiaHandleSymbols(QualType QT, SVal Arg, ProgramStateRef State) { int PtrToHandleLevel = 0; while (QT->isAnyPointerType() || QT->isReferenceType()) { ++PtrToHandleLevel; QT = QT->getPointeeType(); } + if (QT->isStructureType()) { + // If we see a structure, see if there is any handle referenced by the + // structure. + FuchsiaHandleSymbolVisitor Visitor(State); + State->scanReachableSymbols(Arg, Visitor); + return Visitor.GetSymbols(); + } if (const auto *HandleType = QT->getAs()) { if (HandleType->getDecl()->getName() != HandleTypeName) - return nullptr; - if (PtrToHandleLevel > 1) { + return {}; + if (PtrToHandleLevel > 1) // Not supported yet. - return nullptr; - } + return {}; if (PtrToHandleLevel == 0) { - return Arg.getAsSymbol(); + SymbolRef Sym = Arg.getAsSymbol(); + if (Sym) { + return {Sym}; + } else { + return {}; + } } else { assert(PtrToHandleLevel == 1); - if (Optional ArgLoc = Arg.getAs()) - return State->getSVal(*ArgLoc).getAsSymbol(); + if (Optional ArgLoc = Arg.getAs()) { + SymbolRef Sym = State->getSVal(*ArgLoc).getAsSymbol(); + if (Sym) { + return {Sym}; + } else { + return {}; + } + } } } - return nullptr; + return {}; } void FuchsiaHandleChecker::checkPreCall(const CallEvent &Call, @@ -273,30 +311,31 @@ void FuchsiaHandleChecker::checkPreCall(const CallEvent &Call, if (Arg >= FuncDecl->getNumParams()) break; const ParmVarDecl *PVD = FuncDecl->getParamDecl(Arg); - SymbolRef Handle = - getFuchsiaHandleSymbol(PVD->getType(), Call.getArgSVal(Arg), State); - if (!Handle) - continue; + SmallVector Handles = + getFuchsiaHandleSymbols(PVD->getType(), Call.getArgSVal(Arg), State); // Handled in checkPostCall. if (hasFuchsiaAttr(PVD) || hasFuchsiaAttr(PVD)) continue; - const HandleState *HState = State->get(Handle); - if (!HState || HState->isEscaped()) - continue; + for (SymbolRef Handle : Handles) { + const HandleState *HState = State->get(Handle); + if (!HState || HState->isEscaped()) + continue; - if (hasFuchsiaAttr(PVD) || PVD->getType()->isIntegerType()) { - if (HState->isReleased()) { - reportUseAfterFree(Handle, Call.getArgSourceRange(Arg), C); - return; + if (hasFuchsiaAttr(PVD) || + PVD->getType()->isIntegerType()) { + if (HState->isReleased()) { + reportUseAfterFree(Handle, Call.getArgSourceRange(Arg), C); + return; + } + } + if (!hasFuchsiaAttr(PVD) && + PVD->getType()->isIntegerType()) { + // Working around integer by-value escapes. + State = State->set(Handle, HandleState::getEscaped()); } - } - if (!hasFuchsiaAttr(PVD) && - PVD->getType()->isIntegerType()) { - // Working around integer by-value escapes. - State = State->set(Handle, HandleState::getEscaped()); } } C.addTransition(State); @@ -339,63 +378,63 @@ void FuchsiaHandleChecker::checkPostCall(const CallEvent &Call, break; const ParmVarDecl *PVD = FuncDecl->getParamDecl(Arg); unsigned ParamDiagIdx = PVD->getFunctionScopeIndex() + 1; - SymbolRef Handle = - getFuchsiaHandleSymbol(PVD->getType(), Call.getArgSVal(Arg), State); - if (!Handle) - continue; + SmallVector Handles = + getFuchsiaHandleSymbols(PVD->getType(), Call.getArgSVal(Arg), State); - const HandleState *HState = State->get(Handle); - if (HState && HState->isEscaped()) - continue; - if (hasFuchsiaAttr(PVD)) { - if (HState && HState->isReleased()) { - reportDoubleRelease(Handle, Call.getArgSourceRange(Arg), C); - return; - } else { + for (SymbolRef Handle : Handles) { + const HandleState *HState = State->get(Handle); + if (HState && HState->isEscaped()) + continue; + if (hasFuchsiaAttr(PVD)) { + if (HState && HState->isReleased()) { + reportDoubleRelease(Handle, Call.getArgSourceRange(Arg), C); + return; + } else { + Notes.push_back([Handle, ParamDiagIdx](BugReport &BR) -> std::string { + auto *PathBR = static_cast(&BR); + if (auto IsInteresting = PathBR->getInterestingnessKind(Handle)) { + std::string SBuf; + llvm::raw_string_ostream OS(SBuf); + OS << "Handle released through " << ParamDiagIdx + << llvm::getOrdinalSuffix(ParamDiagIdx) << " parameter"; + return OS.str(); + } else + return ""; + }); + State = State->set(Handle, HandleState::getReleased()); + } + } else if (hasFuchsiaAttr(PVD)) { Notes.push_back([Handle, ParamDiagIdx](BugReport &BR) -> std::string { auto *PathBR = static_cast(&BR); if (auto IsInteresting = PathBR->getInterestingnessKind(Handle)) { std::string SBuf; llvm::raw_string_ostream OS(SBuf); - OS << "Handle released through " << ParamDiagIdx + OS << "Handle allocated through " << ParamDiagIdx << llvm::getOrdinalSuffix(ParamDiagIdx) << " parameter"; return OS.str(); } else return ""; }); - State = State->set(Handle, HandleState::getReleased()); + State = State->set( + Handle, HandleState::getMaybeAllocated(ResultSymbol)); } - } else if (hasFuchsiaAttr(PVD)) { - Notes.push_back([Handle, ParamDiagIdx](BugReport &BR) -> std::string { - auto *PathBR = static_cast(&BR); - if (auto IsInteresting = PathBR->getInterestingnessKind(Handle)) { - std::string SBuf; - llvm::raw_string_ostream OS(SBuf); - OS << "Handle allocated through " << ParamDiagIdx - << llvm::getOrdinalSuffix(ParamDiagIdx) << " parameter"; - return OS.str(); - } else - return ""; - }); - State = State->set( - Handle, HandleState::getMaybeAllocated(ResultSymbol)); } } const NoteTag *T = nullptr; if (!Notes.empty()) { T = C.getNoteTag([this, Notes{std::move(Notes)}]( PathSensitiveBugReport &BR) -> std::string { - if (&BR.getBugType() != &UseAfterReleaseBugType && - &BR.getBugType() != &LeakBugType && - &BR.getBugType() != &DoubleReleaseBugType) - return ""; - for (auto &Note : Notes) { - std::string Text = Note(BR); - if (!Text.empty()) - return Text; - } - return ""; - }); + if (&BR.getBugType() != &UseAfterReleaseBugType && + &BR.getBugType() != &LeakBugType && + &BR.getBugType() != &DoubleReleaseBugType) + return ""; + for (auto &Note : Notes) { + std::string Text = Note(BR); + if (!Text.empty()) + return Text; + } + return ""; + }); } C.addTransition(State, T); } @@ -481,13 +520,14 @@ ProgramStateRef FuchsiaHandleChecker::checkPointerEscape( if (Arg >= FuncDecl->getNumParams()) break; const ParmVarDecl *PVD = FuncDecl->getParamDecl(Arg); - SymbolRef Handle = - getFuchsiaHandleSymbol(PVD->getType(), Call->getArgSVal(Arg), State); - if (!Handle) - continue; - if (hasFuchsiaAttr(PVD) || - hasFuchsiaAttr(PVD)) - UnEscaped.insert(Handle); + SmallVector Handles = + getFuchsiaHandleSymbols(PVD->getType(), Call->getArgSVal(Arg), State); + for (SymbolRef Handle : Handles) { + if (hasFuchsiaAttr(PVD) || + hasFuchsiaAttr(PVD)) { + UnEscaped.insert(Handle); + } + } } } diff --git a/clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp b/clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp index 52ba17d59ae07..996d3644e018a 100644 --- a/clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp +++ b/clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp @@ -842,19 +842,7 @@ ExprEngine::mayInlineCallKind(const CallEvent &Call, const ExplodedNode *Pred, static bool hasMember(const ASTContext &Ctx, const CXXRecordDecl *RD, StringRef Name) { const IdentifierInfo &II = Ctx.Idents.get(Name); - DeclarationName DeclName = Ctx.DeclarationNames.getIdentifier(&II); - if (!RD->lookup(DeclName).empty()) - return true; - - CXXBasePaths Paths(false, false, false); - if (RD->lookupInBases( - [DeclName](const CXXBaseSpecifier *Specifier, CXXBasePath &Path) { - return CXXRecordDecl::FindOrdinaryMember(Specifier, Path, DeclName); - }, - Paths)) - return true; - - return false; + return RD->hasMemberName(Ctx.DeclarationNames.getIdentifier(&II)); } /// Returns true if the given C++ class is a container or iterator. diff --git a/clang/lib/Tooling/Transformer/RangeSelector.cpp b/clang/lib/Tooling/Transformer/RangeSelector.cpp index ce6f5fb9b4446..0f3138db218af 100644 --- a/clang/lib/Tooling/Transformer/RangeSelector.cpp +++ b/clang/lib/Tooling/Transformer/RangeSelector.cpp @@ -142,7 +142,8 @@ RangeSelector transformer::node(std::string ID) { Expected Node = getNode(Result.Nodes, ID); if (!Node) return Node.takeError(); - return Node->get() != nullptr && Node->get() == nullptr + return (Node->get() != nullptr || + (Node->get() != nullptr && Node->get() == nullptr)) ? tooling::getExtendedRange(*Node, tok::TokenKind::semi, *Result.Context) : CharSourceRange::getTokenRange(Node->getSourceRange()); diff --git a/clang/test/Analysis/Inputs/system-header-simulator-cxx.h b/clang/test/Analysis/Inputs/system-header-simulator-cxx.h index f2b148cbc692b..87984d02c2f6e 100644 --- a/clang/test/Analysis/Inputs/system-header-simulator-cxx.h +++ b/clang/test/Analysis/Inputs/system-header-simulator-cxx.h @@ -46,7 +46,7 @@ template struct __vector_iterator { __vector_iterator(const Ptr p = 0) : ptr(p) {} __vector_iterator(const iterator &rhs): ptr(rhs.base()) {} - __vector_iterator operator++() { ++ ptr; return *this; } + __vector_iterator& operator++() { ++ ptr; return *this; } __vector_iterator operator++(int) { auto tmp = *this; ++ ptr; @@ -109,7 +109,7 @@ template struct __deque_iterator { __deque_iterator(const Ptr p = 0) : ptr(p) {} __deque_iterator(const iterator &rhs): ptr(rhs.base()) {} - __deque_iterator operator++() { ++ ptr; return *this; } + __deque_iterator& operator++() { ++ ptr; return *this; } __deque_iterator operator++(int) { auto tmp = *this; ++ ptr; @@ -169,7 +169,7 @@ template struct __list_iterator { __list_iterator(T* it = 0) : item(it) {} __list_iterator(const iterator &rhs): item(rhs.item) {} - __list_iterator operator++() { item = item->next; return *this; } + __list_iterator& operator++() { item = item->next; return *this; } __list_iterator operator++(int) { auto tmp = *this; item = item->next; @@ -212,7 +212,7 @@ template struct __fwdl_iterator { __fwdl_iterator(T* it = 0) : item(it) {} __fwdl_iterator(const iterator &rhs): item(rhs.item) {} - __fwdl_iterator operator++() { item = item->next; return *this; } + __fwdl_iterator& operator++() { item = item->next; return *this; } __fwdl_iterator operator++(int) { auto tmp = *this; item = item->next; @@ -1079,7 +1079,7 @@ template< class iterator { public: iterator(Key *key): ptr(key) {} - iterator operator++() { ++ptr; return *this; } + iterator& operator++() { ++ptr; return *this; } bool operator!=(const iterator &other) const { return ptr != other.ptr; } const Key &operator*() const { return *ptr; } private: @@ -1104,7 +1104,7 @@ template< class iterator { public: iterator(Key *key): ptr(key) {} - iterator operator++() { ++ptr; return *this; } + iterator& operator++() { ++ptr; return *this; } bool operator!=(const iterator &other) const { return ptr != other.ptr; } const Key &operator*() const { return *ptr; } private: diff --git a/clang/test/Analysis/fuchsia_handle.cpp b/clang/test/Analysis/fuchsia_handle.cpp index d104b13c77abf..911ab7adaaa9e 100644 --- a/clang/test/Analysis/fuchsia_handle.cpp +++ b/clang/test/Analysis/fuchsia_handle.cpp @@ -9,9 +9,9 @@ typedef unsigned int uint32_t; #define ZX_HANDLE_INVALID 0 #if defined(__clang__) -#define ZX_HANDLE_ACQUIRE __attribute__((acquire_handle("Fuchsia"))) -#define ZX_HANDLE_RELEASE __attribute__((release_handle("Fuchsia"))) -#define ZX_HANDLE_USE __attribute__((use_handle("Fuchsia"))) +#define ZX_HANDLE_ACQUIRE __attribute__((acquire_handle("Fuchsia"))) +#define ZX_HANDLE_RELEASE __attribute__((release_handle("Fuchsia"))) +#define ZX_HANDLE_USE __attribute__((use_handle("Fuchsia"))) #else #define ZX_HANDLE_ACQUIRE #define ZX_HANDLE_RELEASE @@ -31,7 +31,7 @@ zx_handle_t return_handle(); void escape1(zx_handle_t *in); void escape2(zx_handle_t in); -void (*escape3)(zx_handle_t) = escape2; +void (*escape3)(zx_handle_t) = escape2; void use1(const zx_handle_t *in ZX_HANDLE_USE); void use2(zx_handle_t in ZX_HANDLE_USE); @@ -82,8 +82,8 @@ void handleDieBeforeErrorSymbol02() { // expected-note-re@-3 {{Handle allocated through {{(2nd|3rd)}} parameter}} if (status == 0) { // expected-note {{Assuming 'status' is equal to 0}} // expected-note@-1 {{Taking true branch}} - return; // expected-warning {{Potential leak of handle}} - // expected-note@-1 {{Potential leak of handle}} + return; // expected-warning {{Potential leak of handle}} + // expected-note@-1 {{Potential leak of handle}} } __builtin_trap(); } @@ -138,7 +138,7 @@ void checkNoLeak06() { return; zx_handle_close(sa); zx_handle_close(sb); -} +} void checkLeak01(int tag) { zx_handle_t sa, sb; @@ -158,7 +158,7 @@ void checkLeakFromReturn01(int tag) { zx_handle_t sa = return_handle(); // expected-note {{Function 'return_handle' returns an open handle}} (void)sa; } // expected-note {{Potential leak of handle}} - // expected-warning@-1 {{Potential leak of handle}} +// expected-warning@-1 {{Potential leak of handle}} void checkReportLeakOnOnePath(int tag) { zx_handle_t sa, sb; @@ -166,26 +166,26 @@ void checkReportLeakOnOnePath(int tag) { return; // expected-note@-1 {{Assuming the condition is false}} // expected-note@-2 {{Taking false branch}} zx_handle_close(sb); - switch(tag) { // expected-note {{Control jumps to the 'default' case at line}} - case 0: - use2(sa); - return; - case 1: - use2(sa); - return; - case 2: - use2(sa); - return; - case 3: - use2(sa); - return; - case 4: - use2(sa); - return; - default: - use2(sa); - return; // expected-warning {{Potential leak of handle}} - // expected-note@-1 {{Potential leak of handle}} + switch (tag) { // expected-note {{Control jumps to the 'default' case at line}} + case 0: + use2(sa); + return; + case 1: + use2(sa); + return; + case 2: + use2(sa); + return; + case 3: + use2(sa); + return; + case 4: + use2(sa); + return; + default: + use2(sa); + return; // expected-warning {{Potential leak of handle}} + // expected-note@-1 {{Potential leak of handle}} } } @@ -193,7 +193,7 @@ void checkDoubleRelease01(int tag) { zx_handle_t sa, sb; zx_channel_create(0, &sa, &sb); // expected-note@-1 {{Handle allocated through 2nd parameter}} - if (tag) // expected-note {{Assuming 'tag' is not equal to 0}} + if (tag) // expected-note {{Assuming 'tag' is not equal to 0}} zx_handle_close(sa); // expected-note {{Handle released through 1st parameter}} // expected-note@-2 {{Taking true branch}} zx_handle_close(sa); // expected-warning {{Releasing a previously released handle}} @@ -211,12 +211,12 @@ void checkUseAfterFree01(int tag) { if (tag) { // expected-note@-1 {{Assuming 'tag' is not equal to 0}} zx_handle_close(sa); // expected-note {{Handle released through 1st parameter}} - use1(&sa); // expected-warning {{Using a previously released handle}} + use1(&sa); // expected-warning {{Using a previously released handle}} // expected-note@-1 {{Using a previously released handle}} } // expected-note@-6 {{Assuming 'tag' is 0}} zx_handle_close(sb); // expected-note {{Handle released through 1st parameter}} - use2(sb); // expected-warning {{Using a previously released handle}} + use2(sb); // expected-warning {{Using a previously released handle}} // expected-note@-1 {{Using a previously released handle}} } @@ -229,6 +229,92 @@ void checkMemberOperatorIndices() { zx_handle_close(sc); } +struct HandleStruct { + zx_handle_t h; +}; + +void close_handle_struct(HandleStruct hs ZX_HANDLE_RELEASE); + +void use_handle_struct(HandleStruct hs ZX_HANDLE_USE); + +void checkHandleInStructureUseAfterFree() { + zx_handle_t sa, sb; + zx_channel_create(0, &sa, &sb); // expected-note {{Handle allocated through 3rd parameter}} + HandleStruct hs; + hs.h = sb; + use_handle_struct(hs); + close_handle_struct(hs); // expected-note {{Handle released through 1st parameter}} + zx_handle_close(sa); + + use2(sb); // expected-warning {{Using a previously released handle}} + // expected-note@-1 {{Using a previously released handle}} +} + +void checkHandleInStructureUseAfterFree2() { + zx_handle_t sa, sb; + zx_channel_create(0, &sa, &sb); // expected-note {{Handle allocated through 3rd parameter}} + HandleStruct hs; + hs.h = sb; + use_handle_struct(hs); + zx_handle_close(sb); // expected-note {{Handle released through 1st parameter}} + zx_handle_close(sa); + + use_handle_struct(hs); // expected-warning {{Using a previously released handle}} + // expected-note@-1 {{Using a previously released handle}} +} + +void checkHandleInStructureLeak() { + zx_handle_t sa, sb; + zx_channel_create(0, &sa, &sb); // expected-note {{Handle allocated through 3rd parameter}} + HandleStruct hs; + hs.h = sb; + zx_handle_close(sa); // expected-warning {{Potential leak of handle}} + // expected-note@-1 {{Potential leak of handle}} +} + +struct HandlePtrStruct { + zx_handle_t *h; +}; + +void close_handle_struct(HandlePtrStruct hs ZX_HANDLE_RELEASE); + +void use_handle_struct(HandlePtrStruct hs ZX_HANDLE_USE); + +void checkHandlePtrInStructureUseAfterFree() { + zx_handle_t sa, sb; + zx_channel_create(0, &sa, &sb); + HandlePtrStruct hs; + hs.h = &sb; + use_handle_struct(hs); + close_handle_struct(hs); // expected-note {{Handle released through 1st parameter}} + zx_handle_close(sa); + + use2(sb); // expected-warning {{Using a previously released handle}} + // expected-note@-1 {{Using a previously released handle}} +} + +void checkHandlePtrInStructureUseAfterFree2() { + zx_handle_t sa, sb; + zx_channel_create(0, &sa, &sb); + HandlePtrStruct hs; + hs.h = &sb; + use_handle_struct(hs); + zx_handle_close(sb); // expected-note {{Handle released through 1st parameter}} + zx_handle_close(sa); + + use_handle_struct(hs); // expected-warning {{Using a previously released handle}} + // expected-note@-1 {{Using a previously released handle}} +} + +void checkHandlePtrInStructureLeak() { + zx_handle_t sa, sb; + zx_channel_create(0, &sa, &sb); // expected-note {{Handle allocated through 3rd parameter}} + HandlePtrStruct hs; + hs.h = &sb; + zx_handle_close(sa); // expected-warning {{Potential leak of handle}} + // expected-note@-1 {{Potential leak of handle}} +} + // RAII template @@ -239,6 +325,7 @@ struct HandleWrapper { zx_handle_close(handle); } T *get_handle_address() { return &handle; } + private: T handle; }; @@ -259,6 +346,7 @@ struct HandleWrapperUnkonwDtor { zx_handle_close(handle); } T *get_handle_address() { return &handle; } + private: T handle; }; @@ -270,7 +358,7 @@ void doNotWarnOnUnknownDtor() { return; zx_handle_close(sb); } - + // Various escaping scenarios zx_handle_t *get_handle_address(); diff --git a/clang/test/CMakeLists.txt b/clang/test/CMakeLists.txt index f84b378991fd4..f7da1d4fab7dc 100644 --- a/clang/test/CMakeLists.txt +++ b/clang/test/CMakeLists.txt @@ -125,6 +125,8 @@ if( NOT CLANG_BUILT_STANDALONE ) llvm-readobj llvm-symbolizer opt + split-file + yaml2obj ) if(TARGET llvm-lto) diff --git a/clang/test/CXX/cpp/cpp.predefined/p2.cpp b/clang/test/CXX/cpp/cpp.predefined/p2.cpp new file mode 100644 index 0000000000000..0d6352166e5cc --- /dev/null +++ b/clang/test/CXX/cpp/cpp.predefined/p2.cpp @@ -0,0 +1,17 @@ +// RUN: split-file %s %t.dir +// RUN: %clang_cc1 -verify %t.dir/defined.cpp +// RUN: %clang_cc1 -verify -mthread-model posix %t.dir/defined.cpp +// RUN: %clang_cc1 -verify -mthread-model single %t.dir/not-defined.cpp +// RUN: %clang_cc1 -verify -x c %t.dir/not-defined.cpp + +//--- defined.cpp +// expected-no-diagnostics +#ifndef __STDCPP_THREADS__ +#error __STDCPP_THREADS__ is not defined in posix thread model. +#endif + +//--- not-defined.cpp +// expected-no-diagnostics +#ifdef __STDCPP_THREADS__ +#error __STDCPP_THREADS__ is defined in single thread model. +#endif diff --git a/clang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/p4-ast.cpp b/clang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/p4-ast.cpp new file mode 100644 index 0000000000000..4fc0a05ae1eca --- /dev/null +++ b/clang/test/CXX/dcl.decl/dcl.init/dcl.init.ref/p4-ast.cpp @@ -0,0 +1,18 @@ +// RUN: %clang_cc1 -std=c++17 -ast-dump %s | FileCheck %s + +void f() noexcept; + +// CHECK: VarDecl {{.*}} ref 'void (&)()' cinit +// CHECK-NEXT: ImplicitCastExpr {{.*}} 'void ()':'void ()' lvalue +// CHECK-NEXT: DeclRefExpr {{.*}} 'void () noexcept' lvalue Function {{.*}} 'f' 'void () noexcept' +void (&ref)() = f; + +struct X { + typedef void (&ref)() noexcept; + operator ref(); +} x; + +// CHECK: VarDecl {{.*}} xp 'void (&)()' cinit +// CHECK-NEXT: ImplicitCastExpr {{.*}} 'void ()':'void ()' lvalue +// CHECK-NEXT: ImplicitCastExpr {{.*}} 'void () noexcept':'void () noexcept' lvalue +void (&xp)() = x; diff --git a/clang/test/CXX/drs/dr3xx.cpp b/clang/test/CXX/drs/dr3xx.cpp index cec9acf63a9e4..06aa885d236e8 100644 --- a/clang/test/CXX/drs/dr3xx.cpp +++ b/clang/test/CXX/drs/dr3xx.cpp @@ -137,13 +137,17 @@ namespace dr305 { // dr305: no #endif } -namespace dr306 { // dr306: no - // FIXME: dup 39 - // FIXME: This should be accepted. - struct A { struct B {}; }; // expected-note 2{{member}} - struct C { typedef A::B B; }; // expected-note {{member}} +namespace dr306 { // dr306: dup 39 + struct A { struct B {}; }; + struct C { typedef A::B B; }; struct D : A, A::B, C {}; - D::B b; // expected-error {{found in multiple base classes of different types}} + D::B b; + + struct X {}; // expected-note {{member type 'dr306::X' found}} + template struct Y { typedef T X; }; // expected-note {{member type 'const dr306::X' found}} + template struct Z : X, Y {}; + Z::X zx; + Z::X zcx; // expected-error {{member 'X' found in multiple base classes of different types}} } // dr307: na diff --git a/clang/test/CXX/temp/temp.res/temp.local/p3.cpp b/clang/test/CXX/temp/temp.res/temp.local/p3.cpp index 63c40fb576907..ac03c7280828f 100644 --- a/clang/test/CXX/temp/temp.res/temp.local/p3.cpp +++ b/clang/test/CXX/temp/temp.res/temp.local/p3.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -verify %s -template struct Base { // expected-note 4 {{member found by ambiguous name lookup}} +template struct Base { + // expected-note@-1 2{{member type 'Base' found by ambiguous name lookup}} + // expected-note@-2 2{{member type 'Base' found by ambiguous name lookup}} static void f(); }; diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-error.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-error.c index 5fdcb4061850f..77e90b5ad4b84 100644 --- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-error.c +++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-error.c @@ -67,7 +67,7 @@ void test_core(void) { len = __lcbb(cptr, 8192); // expected-error {{no matching function}} // expected-note@vecintrin.h:* {{must be a constant power of 2 from 64 to 4096}} - vsl = vec_permi(vsl, vsl, idx); // expected-error {{no matching function}} + vsl = vec_permi(vsl, vsl, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vpdi' must be a constant integer}} // expected-note@vecintrin.h:* 3 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} vsl = vec_permi(vsl, vsl, -1); // expected-error {{no matching function}} @@ -76,7 +76,7 @@ void test_core(void) { vsl = vec_permi(vsl, vsl, 4); // expected-error {{no matching function}} // expected-note@vecintrin.h:* 3 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vul = vec_permi(vul, vul, idx); // expected-error {{no matching function}} + vul = vec_permi(vul, vul, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vpdi' must be a constant integer}} // expected-note@vecintrin.h:* 2 {{candidate function not viable}} // expected-note@vecintrin.h:* 2 {{must be a constant integer from 0 to 3}} vul = vec_permi(vul, vul, -1); // expected-error {{no matching function}} @@ -85,7 +85,7 @@ void test_core(void) { vul = vec_permi(vul, vul, 4); // expected-error {{no matching function}} // expected-note@vecintrin.h:* 2 {{candidate function not viable}} // expected-note@vecintrin.h:* 2 {{must be a constant integer from 0 to 3}} - vbl = vec_permi(vbl, vbl, idx); // expected-error {{no matching function}} + vbl = vec_permi(vbl, vbl, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vpdi' must be a constant integer}} // expected-note@vecintrin.h:* 2 {{candidate function not viable}} // expected-note@vecintrin.h:* 2 {{must be a constant integer from 0 to 3}} vbl = vec_permi(vbl, vbl, -1); // expected-error {{no matching function}} @@ -94,7 +94,7 @@ void test_core(void) { vbl = vec_permi(vbl, vbl, 4); // expected-error {{no matching function}} // expected-note@vecintrin.h:* 2 {{candidate function not viable}} // expected-note@vecintrin.h:* 2 {{must be a constant integer from 0 to 3}} - vd = vec_permi(vd, vd, idx); // expected-error {{no matching function}} + vd = vec_permi(vd, vd, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vpdi' must be a constant integer}} // expected-note@vecintrin.h:* 3 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} vd = vec_permi(vd, vd, -1); // expected-error {{no matching function}} @@ -232,28 +232,28 @@ void test_core(void) { // expected-note@vecintrin.h:* 6 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 1}} - vsc = vec_load_bndry(cptrsc, idx); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} - vsc = vec_load_bndry(cptrsc, 200); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} - vsc = vec_load_bndry(cptrsc, 32); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} - vsc = vec_load_bndry(cptrsc, 8192); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} - vuc = vec_load_bndry(cptruc, idx); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} - vss = vec_load_bndry(cptrss, idx); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} - vus = vec_load_bndry(cptrus, idx); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} - vsi = vec_load_bndry(cptrsi, idx); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} - vui = vec_load_bndry(cptrui, idx); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} - vsl = vec_load_bndry(cptrsl, idx); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} - vul = vec_load_bndry(cptrul, idx); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} + vsc = vec_load_bndry(cptrsc, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vlbb' must be a constant integer}} + // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} + vsc = vec_load_bndry(cptrsc, 200); // expected-error {{no matching function}} expected-error {{argument value -1 is outside the valid range [0, 15]}} + // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} + vsc = vec_load_bndry(cptrsc, 32); // expected-error {{no matching function}} expected-error {{argument value -1 is outside the valid range [0, 15]}} + // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} + vsc = vec_load_bndry(cptrsc, 8192); // expected-error {{no matching function}} expected-error {{argument value -1 is outside the valid range [0, 15]}} + // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} + vuc = vec_load_bndry(cptruc, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vlbb' must be a constant integer}} + // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} + vss = vec_load_bndry(cptrss, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vlbb' must be a constant integer}} + // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} + vus = vec_load_bndry(cptrus, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vlbb' must be a constant integer}} + // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} + vsi = vec_load_bndry(cptrsi, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vlbb' must be a constant integer}} + // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} + vui = vec_load_bndry(cptrui, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vlbb' must be a constant integer}} + // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} + vsl = vec_load_bndry(cptrsl, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vlbb' must be a constant integer}} + // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} + vul = vec_load_bndry(cptrul, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vlbb' must be a constant integer}} + // expected-note@vecintrin.h:* 9 {{must be a constant power of 2 from 64 to 4096}} vuc = vec_genmask(idx); // expected-error {{no matching function}} // expected-note@vecintrin.h:* {{must be a constant integer}} @@ -420,108 +420,140 @@ void test_core(void) { } void test_integer(void) { - vsc = vec_rl_mask(vsc, vuc, idx); // expected-error {{no matching function}} + vsc = vec_rl_mask(vsc, vuc, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_verimb' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimh' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimf' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimg' must be a constant integer}} // expected-note@vecintrin.h:* 7 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer}} - vuc = vec_rl_mask(vuc, vuc, idx); // expected-error {{no matching function}} + vuc = vec_rl_mask(vuc, vuc, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_verimb' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimh' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimf' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimg' must be a constant integer}} // expected-note@vecintrin.h:* 7 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer}} - vss = vec_rl_mask(vss, vus, idx); // expected-error {{no matching function}} + vss = vec_rl_mask(vss, vus, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_verimb' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimh' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimf' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimg' must be a constant integer}} // expected-note@vecintrin.h:* 7 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer}} - vus = vec_rl_mask(vus, vus, idx); // expected-error {{no matching function}} + vus = vec_rl_mask(vus, vus, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_verimb' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimh' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimf' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimg' must be a constant integer}} // expected-note@vecintrin.h:* 7 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer}} - vsi = vec_rl_mask(vsi, vui, idx); // expected-error {{no matching function}} + vsi = vec_rl_mask(vsi, vui, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_verimb' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimh' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimf' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimg' must be a constant integer}} // expected-note@vecintrin.h:* 7 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer}} - vui = vec_rl_mask(vui, vui, idx); // expected-error {{no matching function}} + vui = vec_rl_mask(vui, vui, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_verimb' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimh' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimf' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimg' must be a constant integer}} // expected-note@vecintrin.h:* 7 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer}} - vsl = vec_rl_mask(vsl, vul, idx); // expected-error {{no matching function}} + vsl = vec_rl_mask(vsl, vul, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_verimb' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimh' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimf' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimg' must be a constant integer}} // expected-note@vecintrin.h:* 7 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer}} - vul = vec_rl_mask(vul, vul, idx); // expected-error {{no matching function}} + vul = vec_rl_mask(vul, vul, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_verimb' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimh' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimf' must be a constant integer}} \ + // expected-error {{argument to '__builtin_s390_verimg' must be a constant integer}} // expected-note@vecintrin.h:* 7 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer}} - vsc = vec_sld(vsc, vsc, idx); // expected-error {{no matching function}} + vsc = vec_sld(vsc, vsc, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 12 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 15}} - vsc = vec_sld(vsc, vsc, -1); // expected-error {{no matching function}} + vsc = vec_sld(vsc, vsc, -1); // expected-error {{no matching function}} expected-error {{argument value -1 is outside the valid range [0, 15]}} // expected-note@vecintrin.h:* 12 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 15}} - vsc = vec_sld(vsc, vsc, 16); // expected-error {{no matching function}} + vsc = vec_sld(vsc, vsc, 16); // expected-error {{no matching function}} expected-error {{argument value 16 is outside the valid range [0, 15]}} // expected-note@vecintrin.h:* 12 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 15}} - vuc = vec_sld(vuc, vuc, idx); // expected-error {{no matching function}} + vuc = vec_sld(vuc, vuc, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 11 {{candidate function not viable}} // expected-note@vecintrin.h:* 2 {{must be a constant integer from 0 to 15}} - vuc = vec_sld(vuc, vuc, -1); // expected-error {{no matching function}} + vuc = vec_sld(vuc, vuc, -1); // expected-error {{no matching function}} expected-error {{argument value -1 is outside the valid range [0, 15]}} // expected-note@vecintrin.h:* 11 {{candidate function not viable}} // expected-note@vecintrin.h:* 2 {{must be a constant integer from 0 to 15}} - vuc = vec_sld(vuc, vuc, 16); // expected-error {{no matching function}} + vuc = vec_sld(vuc, vuc, 16); // expected-error {{no matching function}} expected-error {{argument value 16 is outside the valid range [0, 15]}} // expected-note@vecintrin.h:* 11 {{candidate function not viable}} // expected-note@vecintrin.h:* 2 {{must be a constant integer from 0 to 15}} - vss = vec_sld(vss, vss, idx); // expected-error {{no matching function}} + vss = vec_sld(vss, vss, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 12 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 15}} - vus = vec_sld(vus, vus, idx); // expected-error {{no matching function}} + vus = vec_sld(vus, vus, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 11 {{candidate function not viable}} // expected-note@vecintrin.h:* 2 {{must be a constant integer from 0 to 15}} - vsi = vec_sld(vsi, vsi, idx); // expected-error {{no matching function}} + vsi = vec_sld(vsi, vsi, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 12 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 15}} - vui = vec_sld(vui, vui, idx); // expected-error {{no matching function}} + vui = vec_sld(vui, vui, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 11 {{candidate function not viable}} // expected-note@vecintrin.h:* 2 {{must be a constant integer from 0 to 15}} - vsl = vec_sld(vsl, vsl, idx); // expected-error {{no matching function}} + vsl = vec_sld(vsl, vsl, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 12 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 15}} - vul = vec_sld(vul, vul, idx); // expected-error {{no matching function}} + vul = vec_sld(vul, vul, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 11 {{candidate function not viable}} // expected-note@vecintrin.h:* 2 {{must be a constant integer from 0 to 15}} - vd = vec_sld(vd, vd, idx); // expected-error {{no matching function}} + vd = vec_sld(vd, vd, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 12 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 15}} - vsc = vec_sldw(vsc, vsc, idx); // expected-error {{no matching function}} + vsc = vec_sldw(vsc, vsc, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vsc = vec_sldw(vsc, vsc, -1); // expected-error {{no matching function}} + vsc = vec_sldw(vsc, vsc, -1); // expected-error {{no matching function}} expected-error {{argument value -4 is outside the valid range [0, 15]}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vsc = vec_sldw(vsc, vsc, 4); // expected-error {{no matching function}} + vsc = vec_sldw(vsc, vsc, 4); // expected-error {{no matching function}} expected-error {{argument value 16 is outside the valid range [0, 15]}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vuc = vec_sldw(vuc, vuc, idx); // expected-error {{no matching function}} + vuc = vec_sldw(vuc, vuc, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vuc = vec_sldw(vuc, vuc, -1); // expected-error {{no matching function}} + vuc = vec_sldw(vuc, vuc, -1); // expected-error {{no matching function}} expected-error {{argument value -4 is outside the valid range [0, 15]}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vuc = vec_sldw(vuc, vuc, 4); // expected-error {{no matching function}} + vuc = vec_sldw(vuc, vuc, 4); // expected-error {{no matching function}} expected-error {{argument value 16 is outside the valid range [0, 15]}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vss = vec_sldw(vss, vss, idx); // expected-error {{no matching function}} + vss = vec_sldw(vss, vss, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vus = vec_sldw(vus, vus, idx); // expected-error {{no matching function}} + vus = vec_sldw(vus, vus, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vsi = vec_sldw(vsi, vsi, idx); // expected-error {{no matching function}} + vsi = vec_sldw(vsi, vsi, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vui = vec_sldw(vui, vui, idx); // expected-error {{no matching function}} + vui = vec_sldw(vui, vui, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vsl = vec_sldw(vsl, vsl, idx); // expected-error {{no matching function}} + vsl = vec_sldw(vsl, vsl, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vul = vec_sldw(vul, vul, idx); // expected-error {{no matching function}} + vul = vec_sldw(vul, vul, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} - vd = vec_sldw(vd, vd, idx); // expected-error {{no matching function}} + vd = vec_sldw(vd, vd, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} // expected-note@vecintrin.h:* 8 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 3}} } diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-error.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-error.c index 64fcbc46ba0da..b7e0d77efca6d 100644 --- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-error.c +++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-error.c @@ -119,12 +119,12 @@ void test_core(void) { } void test_integer(void) { - vf = vec_sld(vf, vf, idx); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 13 {{candidate function not viable}} - // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 15}} - vd = vec_sld(vd, vd, idx); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 13 {{candidate function not viable}} - // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 15}} + vf = vec_sld(vf, vf, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} + // expected-note@vecintrin.h:* 13 {{candidate function not viable}} + // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 15}} + vd = vec_sld(vd, vd, idx); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vsldb' must be a constant integer}} + // expected-note@vecintrin.h:* 13 {{candidate function not viable}} + // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 15}} vuc = vec_msum_u128(vul, vul, vuc, idx); // expected-error {{must be a constant integer}} vuc = vec_msum_u128(vul, vul, vuc, -1); // expected-error-re {{argument value {{.*}} is outside the valid range}} @@ -132,22 +132,22 @@ void test_integer(void) { } void test_float(void) { - vbi = vec_fp_test_data_class(vf, idx, &cc); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 1 {{candidate function not viable}} - // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 4095}} - vbi = vec_fp_test_data_class(vf, -1, &cc); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 1 {{candidate function not viable}} - // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 4095}} - vbi = vec_fp_test_data_class(vf, 4096, &cc); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 1 {{candidate function not viable}} - // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 4095}} - vbl = vec_fp_test_data_class(vd, idx, &cc); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 1 {{candidate function not viable}} - // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 4095}} - vbl = vec_fp_test_data_class(vd, -1, &cc); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 1 {{candidate function not viable}} - // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 4095}} - vbl = vec_fp_test_data_class(vd, 4096, &cc); // expected-error {{no matching function}} - // expected-note@vecintrin.h:* 1 {{candidate function not viable}} - // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 4095}} + vbi = vec_fp_test_data_class(vf, idx, &cc); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vftcisb' must be a constant integer}} expected-error {{argument to '__builtin_s390_vftcidb' must be a constant integer}} + // expected-note@vecintrin.h:* 1 {{candidate function not viable}} + // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 4095}} + vbi = vec_fp_test_data_class(vf, -1, &cc); // expected-error {{no matching function}} expected-error 2{{argument value -1 is outside the valid range [0, 4095]}} + // expected-note@vecintrin.h:* 1 {{candidate function not viable}} + // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 4095}} + vbi = vec_fp_test_data_class(vf, 4096, &cc); // expected-error {{no matching function}} expected-error 2{{argument value 4096 is outside the valid range [0, 4095]}} + // expected-note@vecintrin.h:* 1 {{candidate function not viable}} + // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 4095}} + vbl = vec_fp_test_data_class(vd, idx, &cc); // expected-error {{no matching function}} expected-error {{argument to '__builtin_s390_vftcisb' must be a constant integer}} expected-error {{argument to '__builtin_s390_vftcidb' must be a constant integer}} + // expected-note@vecintrin.h:* 1 {{candidate function not viable}} + // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 4095}} + vbl = vec_fp_test_data_class(vd, -1, &cc); // expected-error {{no matching function}} expected-error 2{{argument value -1 is outside the valid range [0, 4095]}} + // expected-note@vecintrin.h:* 1 {{candidate function not viable}} + // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 4095}} + vbl = vec_fp_test_data_class(vd, 4096, &cc); // expected-error {{no matching function}} expected-error 2{{argument value 4096 is outside the valid range [0, 4095]}} + // expected-note@vecintrin.h:* 1 {{candidate function not viable}} + // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 4095}} } diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector3-error.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector3-error.c index 557b9a3a7ec1b..135e586f38aea 100644 --- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector3-error.c +++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector3-error.c @@ -60,66 +60,85 @@ volatile int idx; int cc; void test_integer(void) { - vsc = vec_sldb(vsc, vsc, idx); // expected-error {{no matching function}} + vsc = vec_sldb(vsc, vsc, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsld' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vuc = vec_sldb(vuc, vuc, idx); // expected-error {{no matching function}} + vuc = vec_sldb(vuc, vuc, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsld' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vss = vec_sldb(vss, vss, idx); // expected-error {{no matching function}} + vss = vec_sldb(vss, vss, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsld' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vus = vec_sldb(vus, vus, idx); // expected-error {{no matching function}} + vus = vec_sldb(vus, vus, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsld' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vsi = vec_sldb(vsi, vsi, idx); // expected-error {{no matching function}} + vsi = vec_sldb(vsi, vsi, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsld' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vui = vec_sldb(vui, vui, idx); // expected-error {{no matching function}} + vui = vec_sldb(vui, vui, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsld' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vsl = vec_sldb(vsl, vsl, idx); // expected-error {{no matching function}} + vsl = vec_sldb(vsl, vsl, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsld' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vul = vec_sldb(vul, vul, idx); // expected-error {{no matching function}} + vul = vec_sldb(vul, vul, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsld' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vf = vec_sldb(vf, vf, idx); // expected-error {{no matching function}} + vf = vec_sldb(vf, vf, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsld' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vd = vec_sldb(vd, vd, idx); // expected-error {{no matching function}} + vd = vec_sldb(vd, vd, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsld' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vsc = vec_srdb(vsc, vsc, idx); // expected-error {{no matching function}} + vsc = vec_srdb(vsc, vsc, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsrd' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vuc = vec_srdb(vuc, vuc, idx); // expected-error {{no matching function}} + vuc = vec_srdb(vuc, vuc, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsrd' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vss = vec_srdb(vss, vss, idx); // expected-error {{no matching function}} + vss = vec_srdb(vss, vss, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsrd' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vus = vec_srdb(vus, vus, idx); // expected-error {{no matching function}} + vus = vec_srdb(vus, vus, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsrd' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vsi = vec_srdb(vsi, vsi, idx); // expected-error {{no matching function}} + vsi = vec_srdb(vsi, vsi, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsrd' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vui = vec_srdb(vui, vui, idx); // expected-error {{no matching function}} + vui = vec_srdb(vui, vui, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsrd' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vsl = vec_srdb(vsl, vsl, idx); // expected-error {{no matching function}} + vsl = vec_srdb(vsl, vsl, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsrd' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vul = vec_srdb(vul, vul, idx); // expected-error {{no matching function}} + vul = vec_srdb(vul, vul, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsrd' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vf = vec_srdb(vf, vf, idx); // expected-error {{no matching function}} + vf = vec_srdb(vf, vf, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsrd' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} - vd = vec_srdb(vd, vd, idx); // expected-error {{no matching function}} + vd = vec_srdb(vd, vd, idx); // expected-error {{no matching function}} \ + // expected-error {{argument to '__builtin_s390_vsrd' must be a constant integer}} // expected-note@vecintrin.h:* 9 {{candidate function not viable}} // expected-note@vecintrin.h:* 1 {{must be a constant integer from 0 to 7}} } - diff --git a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c new file mode 100644 index 0000000000000..fed7708c6893c --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c @@ -0,0 +1,117 @@ +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=128 | FileCheck %s -D#VBITS=128 --check-prefixes=CHECK128 +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=256 | FileCheck %s -D#VBITS=256 --check-prefixes=CHECK,CHECK256 +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=512 | FileCheck %s -D#VBITS=512 --check-prefixes=CHECK,CHECK512 +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=1024 | FileCheck %s -D#VBITS=1024 --check-prefixes=CHECK,CHECK1024 +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=2048 | FileCheck %s -D#VBITS=2048 --check-prefixes=CHECK,CHECK2048 +// REQUIRES: aarch64-registered-target + +// Examples taken from section "3.7.3.3 Behavior specific to SVE +// vectors" of the SVE ACLE (Version 00bet6) that can be found at +// https://developer.arm.com/documentation/100987/latest +// +// Example has been expanded to work with mutiple values of +// -msve-vector-bits. + +#include + +// Page 27, item 1 +#if __ARM_FEATURE_SVE_BITS == 256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS +// CHECK256-LABEL: @x256 = local_unnamed_addr global <4 x i64> , align 16 +typedef svint64_t vec256 __attribute__((arm_sve_vector_bits(256))); +vec256 x256 = {0, 1, 2, 3}; +#endif + +#if __ARM_FEATURE_SVE_BITS == 512 && __ARM_FEATURE_SVE_VECTOR_OPERATORS +// CHECK512-LABEL: @x512 = local_unnamed_addr global <8 x i64> , align 16 +typedef svint64_t vec512 __attribute__((arm_sve_vector_bits(512))); +vec512 x512 = {0, 1, 2, 3, 3 , 2 , 1, 0}; +#endif + +#if __ARM_FEATURE_SVE_BITS == 1024 && __ARM_FEATURE_SVE_VECTOR_OPERATORS +// CHECK1024-LABEL: @x1024 = local_unnamed_addr global <16 x i64> , align 16 +typedef svint64_t vec1024 __attribute__((arm_sve_vector_bits(1024))); +vec1024 x1024 = {0, 1, 2, 3, 3 , 2 , 1, 0, 0, 1, 2, 3, 3 , 2 , 1, 0}; +#endif + +#if __ARM_FEATURE_SVE_BITS == 2048 && __ARM_FEATURE_SVE_VECTOR_OPERATORS +// CHECK2048-LABEL: @x2048 = local_unnamed_addr global <32 x i64> , align 16 +typedef svint64_t vec2048 __attribute__((arm_sve_vector_bits(2048))); +vec2048 x2048 = {0, 1, 2, 3, 3 , 2 , 1, 0, 0, 1, 2, 3, 3 , 2 , 1, 0, + 0, 1, 2, 3, 3 , 2 , 1, 0, 0, 1, 2, 3, 3 , 2 , 1, 0}; +#endif + +// Page 27, item 2. We can not change the ABI of existing vector +// types, including vec_int8. That's why in the SVE ACLE, VLST is +// distinct from, but mostly interchangeable with, the corresponding +// GNUT. VLST is treated for ABI purposes like an SVE type but GNUT +// continues to be a normal GNU vector type, with base Armv8-A PCS +// rules. +#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS +#define N __ARM_FEATURE_SVE_BITS +typedef int8_t vec_int8 __attribute__((vector_size(N / 8))); +// CHECK128-LABEL: define <16 x i8> @f2(<16 x i8> %x) +// CHECK128-NEXT: entry: +// CHECK128-NEXT: %x.addr = alloca <16 x i8>, align 16 +// CHECK128-NEXT: %saved-call-rvalue = alloca , align 16 +// CHECK128-NEXT: store <16 x i8> %x, <16 x i8>* %x.addr, align 16 +// CHECK128-NEXT: %0 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) +// CHECK128-NEXT: %1 = bitcast <16 x i8>* %x.addr to * +// CHECK128-NEXT: %2 = load , * %1, align 16 +// CHECK128-NEXT: %3 = call @llvm.aarch64.sve.asrd.nxv16i8( %0, %2, i32 1) +// CHECK128-NEXT: store %3, * %saved-call-rvalue, align 16 +// CHECK128-NEXT: %castFixedSve = bitcast * %saved-call-rvalue to <16 x i8>* +// CHECK128-NEXT: %4 = load <16 x i8>, <16 x i8>* %castFixedSve, align 16 +// CHECK128-NEXT: ret <16 x i8> %4 + +// CHECK-LABEL: define void @f2( +// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noalias nocapture sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, <[[#div(VBITS,8)]] x i8>* nocapture readonly %0) +// CHECK-NEXT: entry: +// CHECK-NEXT: %x.addr = alloca <[[#div(VBITS,8)]] x i8>, align 16 +// CHECK-NEXT: %saved-call-rvalue = alloca , align 16 +// CHECK-NEXT: %x = load <[[#div(VBITS,8)]] x i8>, <[[#div(VBITS,8)]] x i8>* %0, align 16 +// CHECK-NEXT: store <[[#div(VBITS,8)]] x i8> %x, <[[#div(VBITS,8)]] x i8>* %x.addr, align 16 +// CHECK-NEXT: %1 = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) +// CHECK-NEXT: %2 = bitcast <[[#div(VBITS,8)]] x i8>* %x.addr to * +// CHECK-NEXT: %3 = load , * %2, align 16 +// CHECK-NEXT: %4 = call @llvm.aarch64.sve.asrd.nxv16i8( %1, %3, i32 1) +// CHECK-NEXT: store %4, * %saved-call-rvalue, align 16 +// CHECK-NEXT: %castFixedSve = bitcast * %saved-call-rvalue to <[[#div(VBITS,8)]] x i8>* +// CHECK-NEXT: %5 = load <[[#div(VBITS,8)]] x i8>, <[[#div(VBITS,8)]] x i8>* %castFixedSve, align 16 +// CHECK-NEXT: store <[[#div(VBITS,8)]] x i8> %5, <[[#div(VBITS,8)]] x i8>* %agg.result, align 16 +// CHECK-NEXT: ret void +vec_int8 f2(vec_int8 x) { return svasrd_x(svptrue_b8(), x, 1); } +#endif + +// Page 27, item 3. +#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS +#define N __ARM_FEATURE_SVE_BITS +typedef int8_t vec1 __attribute__((vector_size(N / 8))); +void f3(vec1); +typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(N))); + +// CHECK128-LABEL: define void @g( %x.coerce) +// CHECK128-NEXT: entry: +// CHECK128-NEXT: %x = alloca <16 x i8>, align 16 +// CHECK128-NEXT: %0 = bitcast <16 x i8>* %x to * +// CHECK128-NEXT: store %x.coerce, * %0, align 16 +// CHECK128-NEXT: %x1 = load <16 x i8>, <16 x i8>* %x, align 16, +// CHECK128-NEXT: call void @f3(<16 x i8> %x1) #4 +// CHECK128-NEXT: ret void + +// CHECK-LABEL: define void @g( %x.coerce) +// CHECK-NEXT: entry: +// CHECK-NEXT: %x = alloca <[[#div(VBITS,8)]] x i8>, align 16 +// CHECK-NEXT: %indirect-arg-temp = alloca <[[#div(VBITS,8)]] x i8>, align 16 +// CHECK-NEXT: %0 = bitcast <[[#div(VBITS,8)]] x i8>* %x to * +// CHECK-NEXT: store %x.coerce, * %0 +// CHECK-NEXT: %x1 = load <[[#div(VBITS,8)]] x i8>, <[[#div(VBITS,8)]] x i8>* %x, align 16 +// CHECK-NEXT: store <[[#div(VBITS,8)]] x i8> %x1, <[[#div(VBITS,8)]] x i8>* %indirect-arg-temp +// CHECK-NEXT: call void @f3(<[[#div(VBITS,8)]] x i8>* nonnull %indirect-arg-temp) +// CHECK-NEXT: ret void + +// CHECK128-LABEL: declare void @f3(<16 x i8>) + +// CHECK-LABEL: declare void @f3( +// CHECK-SAME: <[[#div(VBITS,8)]] x i8>*) +void g(vec2 x) { f3(x); } // OK +#endif diff --git a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp new file mode 100644 index 0000000000000..d739ca57b7461 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp @@ -0,0 +1,94 @@ +// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=128 | FileCheck %s -D#VBITS=128 --check-prefixes=CHECK,CHECK128 +// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=256 | FileCheck %s -D#VBITS=256 --check-prefixes=CHECK,CHECKWIDE +// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=512 | FileCheck %s -D#VBITS=512 --check-prefixes=CHECK,CHECKWIDE +// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=1024 | FileCheck %s -D#VBITS=1024 --check-prefixes=CHECK,CHECKWIDE +// RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -msve-vector-bits=2048 | FileCheck %s -D#VBITS=2048 --check-prefixes=CHECK,CHECKWIDE +// REQUIRES: aarch64-registered-target + +// Examples taken from section "3.7.3.3 Behavior specific to SVE +// vectors" of the SVE ACLE (Version 00bet6) that can be found at +// https://developer.arm.com/documentation/100987/latest +// +// Example has been expanded to work with mutiple values of +// -msve-vector-bits. + +#include + +// Page 26, first paragraph of 3.7.3.3: sizeof and alignof +#if __ARM_FEATURE_SVE_BITS +#define N __ARM_FEATURE_SVE_BITS +typedef svfloat32_t fixed_svfloat __attribute__((arm_sve_vector_bits(N))); +void test01() { + static_assert(alignof(fixed_svfloat) == 16, + "Invalid align of Vector Length Specific Type."); + static_assert(sizeof(fixed_svfloat) == N / 8, + "Invalid size of Vector Length Specific Type."); +} +#endif + +// Page 26, items 1 and 2 of 3.7.3.3: how VLST and GNUT are related. +#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS +#define N __ARM_FEATURE_SVE_BITS +typedef svfloat64_t fixed_svfloat64 __attribute__((arm_sve_vector_bits(N))); +typedef float64_t gnufloat64 __attribute__((vector_size(N / 8))); +void test02() { + static_assert(alignof(fixed_svfloat64) == alignof(gnufloat64), + "Align of Vector Length Specific Type and GNU Vector Types " + "should be the same."); + static_assert(sizeof(fixed_svfloat64) == sizeof(gnufloat64), + "Size of Vector Length Specific Type and GNU Vector Types " + "should be the same."); +} +#endif + +// Page 27, item 1. +#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS +#define N __ARM_FEATURE_SVE_BITS +// CHECK-LABEL: define @_Z1f9__SVE_VLSIu11__SVInt32_tLj +// CHECK-SAME: [[#VBITS]] +// CHECK-SAME: EES_( %x.coerce, %y.coerce) +// CHECK-NEXT: entry: +// CHECK-NEXT: %x = alloca <[[#div(VBITS,32)]] x i32>, align 16 +// CHECK-NEXT: %y = alloca <[[#div(VBITS,32)]] x i32>, align 16 +// CHECK-NEXT: %retval.coerce = alloca , align 16 +// CHECK-NEXT: %0 = bitcast <[[#div(VBITS,32)]] x i32>* %x to * +// CHECK-NEXT: store %x.coerce, * %0, align 16 +// CHECK-NEXT: %x1 = load <[[#div(VBITS,32)]] x i32>, <[[#div(VBITS,32)]] x i32>* %x, align 16 +// CHECK-NEXT: %1 = bitcast <[[#div(VBITS,32)]] x i32>* %y to * +// CHECK-NEXT: store %y.coerce, * %1, align 16 +// CHECK-NEXT: %y2 = load <[[#div(VBITS,32)]] x i32>, <[[#div(VBITS,32)]] x i32>* %y, align 16 +// CHECK-NEXT: %add = add <[[#div(VBITS,32)]] x i32> %y2, %x1 +// CHECK-NEXT: %retval.0..sroa_cast = bitcast * %retval.coerce to <[[#div(VBITS,32)]] x i32>* +// CHECK-NEXT: store <[[#div(VBITS,32)]] x i32> %add, <[[#div(VBITS,32)]] x i32>* %retval.0..sroa_cast, align 16 +// CHECK-NEXT: %2 = load , * %retval.coerce, align 16 +// CHECK-NEXT: ret %2 +typedef svint32_t vec __attribute__((arm_sve_vector_bits(N))); +auto f(vec x, vec y) { return x + y; } // Returns a vec. +#endif + +// Page 27, item 3, adapted for a generic value of __ARM_FEATURE_SVE_BITS +#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS +#define N __ARM_FEATURE_SVE_BITS +typedef int16_t vec1 __attribute__((vector_size(N / 8))); +void f(vec1); +typedef svint16_t vec2 __attribute__((arm_sve_vector_bits(N))); +// CHECK-LABEL: define void @_Z1g9__SVE_VLSIu11__SVInt16_tLj +// CHECK-SAME: [[#VBITS]] +// CHECK-SAME: EE( %x.coerce) +// CHECK-NEXT: entry: +// CHECK128-NEXT: %x = alloca <[[#div(VBITS,16)]] x i16>, align 16 +// CHECK128-NEXT: %0 = bitcast <[[#div(VBITS,16)]] x i16>* %x to * +// CHECK128-NEXT: store %x.coerce, * %0, align 16 +// CHECK128-NEXT: %x1 = load <[[#div(VBITS,16)]] x i16>, <[[#div(VBITS,16)]] x i16>* %x, align 16 +// CHECK128-NEXT: call void @_Z1fDv[[#div(VBITS,16)]]_s(<[[#div(VBITS,16)]] x i16> %x1) +// CHECK128-NEXT: ret void +// CHECKWIDE-NEXT: %x = alloca <[[#div(VBITS,16)]] x i16>, align 16 +// CHECKWIDE-NEXT: %indirect-arg-temp = alloca <[[#div(VBITS,16)]] x i16>, align 16 +// CHECKWIDE-NEXT: %0 = bitcast <[[#div(VBITS,16)]] x i16>* %x to * +// CHECKWIDE-NEXT: store %x.coerce, * %0, align 16 +// CHECKWIDE-NEXT: %x1 = load <[[#div(VBITS,16)]] x i16>, <[[#div(VBITS,16)]] x i16>* %x, align 16 +// CHECKWIDE-NEXT: store <[[#div(VBITS,16)]] x i16> %x1, <[[#div(VBITS,16)]] x i16>* %indirect-arg-temp, align 16 +// CHECKWIDE-NEXT: call void @_Z1fDv[[#div(VBITS,16)]]_s(<[[#div(VBITS,16)]] x i16>* nonnull %indirect-arg-temp) +// CHECKWIDE-NEXT: ret void +void g(vec2 x) { f(x); } // OK +#endif diff --git a/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c b/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c index 7ebb7eb650573..3f88b6ed1db51 100644 --- a/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c +++ b/clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-constrained.c @@ -69,10 +69,9 @@ float16x8_t test_vfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c) { // COMMON-LABEL: test_vfms_f16 // COMMONIR: [[SUB:%.*]] = fneg <4 x half> %b -// CHECK-ASM: fneg v{{[0-9]+}}.4h, v{{[0-9]+}}.4h // UNCONSTRAINED: [[ADD:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[SUB]], <4 x half> %c, <4 x half> %a) // CONSTRAINED: [[ADD:%.*]] = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> [[SUB]], <4 x half> %c, <4 x half> %a, metadata !"round.tonearest", metadata !"fpexcept.maytrap") -// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h +// CHECK-ASM: fmls v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h // COMMONIR: ret <4 x half> [[ADD]] float16x4_t test_vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c) { return vfms_f16(a, b, c); @@ -80,10 +79,9 @@ float16x4_t test_vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c) { // COMMON-LABEL: test_vfmsq_f16 // COMMONIR: [[SUB:%.*]] = fneg <8 x half> %b -// CHECK-ASM: fneg v{{[0-9]+}}.8h, v{{[0-9]+}}.8h // UNCONSTRAINED: [[ADD:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[SUB]], <8 x half> %c, <8 x half> %a) // CONSTRAINED: [[ADD:%.*]] = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> [[SUB]], <8 x half> %c, <8 x half> %a, metadata !"round.tonearest", metadata !"fpexcept.maytrap") -// CHECK-ASM: fmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h +// CHECK-ASM: fmls v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h // COMMONIR: ret <8 x half> [[ADD]] float16x8_t test_vfmsq_f16(float16x8_t a, float16x8_t b, float16x8_t c) { return vfmsq_f16(a, b, c); diff --git a/clang/test/CodeGen/aix-altivec.c b/clang/test/CodeGen/aix-altivec.c new file mode 100644 index 0000000000000..011aa47b63177 --- /dev/null +++ b/clang/test/CodeGen/aix-altivec.c @@ -0,0 +1,44 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-feature +altivec -target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-feature +altivec -target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s +vector float foo1(vector float x) { return x; } +// CHECK: define <4 x float> @foo1(<4 x float> %x) [[ATTR:#[0-9]+]] { +// CHECK: entry: +// CHECK: %x.addr = alloca <4 x float>, align 16 +// CHECK: store <4 x float> %x, <4 x float>* %x.addr, align 16 +// CHECK: %0 = load <4 x float>, <4 x float>* %x.addr, align 16 +// CHECK: ret <4 x float> %0 +// CHECK: } +vector double foo2(vector double x) { return x; } +// CHECK: define <2 x double> @foo2(<2 x double> %x) [[ATTR]] { +// CHECK: entry: +// CHECK: %x.addr = alloca <2 x double>, align 16 +// CHECK: store <2 x double> %x, <2 x double>* %x.addr, align 16 +// CHECK: %0 = load <2 x double>, <2 x double>* %x.addr, align 16 +// CHECK: ret <2 x double> %0 +// CHECK: } +vector int foo3(vector int x) { return x; } +// CHECK: define <4 x i32> @foo3(<4 x i32> %x) [[ATTR]] { +// CHECK: entry: +// CHECK: %x.addr = alloca <4 x i32>, align 16 +// CHECK: store <4 x i32> %x, <4 x i32>* %x.addr, align 16 +// CHECK: %0 = load <4 x i32>, <4 x i32>* %x.addr, align 16 +// CHECK: ret <4 x i32> %0 +// CHECK: } +vector short int foo4(vector short int x) { return x; } +// CHECK: define <8 x i16> @foo4(<8 x i16> %x) [[ATTR]] { +// CHECK: entry: +// CHECK: %x.addr = alloca <8 x i16>, align 16 +// CHECK: store <8 x i16> %x, <8 x i16>* %x.addr, align 16 +// CHECK: %0 = load <8 x i16>, <8 x i16>* %x.addr, align 16 +// CHECK: ret <8 x i16> %0 +// CHECK: } +vector char foo5(vector char x) { return x; } +// CHECK: define <16 x i8> @foo5(<16 x i8> %x) [[ATTR]] { +// CHECK: entry: +// CHECK: %x.addr = alloca <16 x i8>, align 16 +// CHECK: store <16 x i8> %x, <16 x i8>* %x.addr, align 16 +// CHECK: %0 = load <16 x i8>, <16 x i8>* %x.addr, align 16 +// CHECK: ret <16 x i8> %0 +// CHECK: } + diff --git a/clang/test/CodeGen/aix-vector.c b/clang/test/CodeGen/aix-vector.c deleted file mode 100644 index 79a1fe4344db6..0000000000000 --- a/clang/test/CodeGen/aix-vector.c +++ /dev/null @@ -1,10 +0,0 @@ -// REQUIRES: powerpc-registered-target -// RUN: not %clang_cc1 -triple powerpc-unknown-aix -target-feature +altivec \ -// RUN: -emit-llvm -o - %s 2>&1 | FileCheck %s -// RUN: not %clang_cc1 -triple powerpc64-unknown-aix -target-feature +altivec \ -// RUN: -emit-llvm -o - %s 2>&1 | FileCheck %s - -// CHECK: fatal error: error in backend: vector type is not supported on AIX yet -vector signed int retVector(vector signed int x) { - return x; -} diff --git a/clang/test/CodeGen/altivec.c b/clang/test/CodeGen/altivec.c index a4d38fa23b75c..20baa29b2b227 100644 --- a/clang/test/CodeGen/altivec.c +++ b/clang/test/CodeGen/altivec.c @@ -1,5 +1,21 @@ // RUN: %clang_cc1 -target-feature +altivec -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s - +// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -triple powerpc-unknown-aix -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -target-feature +altivec -mabi=vec-extabi -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s +// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -triple powerpc-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR +// RUN: not %clang_cc1 -target-feature +altivec -mabi=vec-default -triple powerpc64-unknown-aix -emit-llvm %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR + +// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -target powerpc-unknown-aix %s -o - | FileCheck %s +// RUN: not %clang -S -emit-llvm -maltivec -target powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR +// RUN: not %clang -S -emit-llvm -maltivec -target powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ERROR +// RUN: not %clang -S -emit-llvm -mabi=vec-default -target powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ATVER +// RUN: not %clang -S -emit-llvm -mabi=vec-extabi -target powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ATVER +// RUN: %clang -S -emit-llvm -maltivec -mabi=vec-extabi -target powerpc64-unknown-aix %s -o - | FileCheck %s +// RUN: not %clang -S -emit-llvm -mabi=vec-default -target powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ATVER +// RUN: not %clang -S -emit-llvm -mabi=vec-extabi -target powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ATVER +// RUN: not %clang -S -mabi=vec-default -target powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ATVER +// RUN: not %clang -S -mabi=vec-extabi -target powerpc-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ATVER +// RUN: not %clang -S -mabi=vec-default -target powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ATVER +// RUN: not %clang -S -mabi=vec-extabi -target powerpc64-unknown-aix %s 2>&1 | FileCheck %s --check-prefix=AIX-ATVER // Check initialization vector int test0 = (vector int)(1); // CHECK: @test0 = global <4 x i32> @@ -38,3 +54,6 @@ void test3() { vector float vf; vf++; // CHECK: fadd <4 x float> {{.*}} } + +// AIX-ERROR: error: The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' for the extended Altivec ABI +// AIX-ATVER: error: '-mabi=vec-extabi' and '-mabi=vec-default' require '-maltivec' diff --git a/clang/test/CodeGen/builtins-ppc-error.c b/clang/test/CodeGen/builtins-ppc-error.c index 6557565938b0c..7f52521d14dfc 100644 --- a/clang/test/CodeGen/builtins-ppc-error.c +++ b/clang/test/CodeGen/builtins-ppc-error.c @@ -48,8 +48,8 @@ void testXXSLDWI(int index) { } void testCTF(int index) { - vec_ctf(vsi, index); //expected-error {{argument to '__builtin_altivec_vcfsx' must be a constant integer}} - vec_ctf(vui, index); //expected-error {{argument to '__builtin_altivec_vcfsx' must be a constant integer}} + vec_ctf(vsi, index); //expected-error {{argument to '__builtin_altivec_vcfsx' must be a constant integer}} expected-error {{argument to '__builtin_altivec_vcfux' must be a constant integer}} + vec_ctf(vui, index); //expected-error {{argument to '__builtin_altivec_vcfsx' must be a constant integer}} expected-error {{argument to '__builtin_altivec_vcfux' must be a constant integer}} } void testVCFSX(int index) { diff --git a/clang/test/CodeGen/ms-intrinsics.c b/clang/test/CodeGen/ms-intrinsics.c index 5182ae4039849..90a97b5cb0469 100644 --- a/clang/test/CodeGen/ms-intrinsics.c +++ b/clang/test/CodeGen/ms-intrinsics.c @@ -6,10 +6,10 @@ // RUN: | FileCheck %s --check-prefixes CHECK,CHECK-ARM,CHECK-ARM-ARM64,CHECK-ARM-X64 // RUN: %clang_cc1 -ffreestanding -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ // RUN: -triple x86_64--windows -Oz -emit-llvm -target-feature +cx16 %s -o - \ -// RUN: | FileCheck %s --check-prefixes CHECK,CHECK-X64,CHECK-ARM-X64,CHECK-INTEL +// RUN: | FileCheck %s --check-prefixes CHECK,CHECK-X64,CHECK-ARM-X64,CHECK-INTEL,CHECK-64 // RUN: %clang_cc1 -ffreestanding -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \ // RUN: -triple aarch64-windows -Oz -emit-llvm %s -o - \ -// RUN: | FileCheck %s --check-prefixes CHECK-ARM-ARM64,CHECK-ARM-X64,CHECK-ARM64 +// RUN: | FileCheck %s --check-prefixes CHECK-ARM-ARM64,CHECK-ARM-X64,CHECK-ARM64,CHECK-64 // intrin.h needs size_t, but -ffreestanding prevents us from getting it from // stddef.h. Work around it with this typedef. @@ -147,7 +147,7 @@ void *test_AddressOfReturnAddress() { #endif unsigned char test_BitScanForward(unsigned long *Index, unsigned long Mask) { - return _BitScanForward(Index, Mask); + return _BitScanForward(++Index, Mask); } // CHECK: define{{.*}}i8 @test_BitScanForward(i32* {{[a-z_ ]*}}%Index, i32 {{[a-z_ ]*}}%Mask){{.*}}{ // CHECK: [[ISNOTZERO:%[a-z0-9._]+]] = icmp eq i32 %Mask, 0 @@ -156,12 +156,13 @@ unsigned char test_BitScanForward(unsigned long *Index, unsigned long Mask) { // CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ] // CHECK: ret i8 [[RESULT]] // CHECK: [[ISNOTZERO_LABEL]]: +// CHECK: [[IDXGEP:%[a-z0-9._]+]] = getelementptr inbounds i32, i32* %Index, {{i64|i32}} 1 // CHECK: [[INDEX:%[0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %Mask, i1 true) -// CHECK: store i32 [[INDEX]], i32* %Index, align 4 +// CHECK: store i32 [[INDEX]], i32* [[IDXGEP]], align 4 // CHECK: br label %[[END_LABEL]] unsigned char test_BitScanReverse(unsigned long *Index, unsigned long Mask) { - return _BitScanReverse(Index, Mask); + return _BitScanReverse(++Index, Mask); } // CHECK: define{{.*}}i8 @test_BitScanReverse(i32* {{[a-z_ ]*}}%Index, i32 {{[a-z_ ]*}}%Mask){{.*}}{ // CHECK: [[ISNOTZERO:%[0-9]+]] = icmp eq i32 %Mask, 0 @@ -170,9 +171,10 @@ unsigned char test_BitScanReverse(unsigned long *Index, unsigned long Mask) { // CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ] // CHECK: ret i8 [[RESULT]] // CHECK: [[ISNOTZERO_LABEL]]: +// CHECK: [[IDXGEP:%[a-z0-9._]+]] = getelementptr inbounds i32, i32* %Index, {{i64|i32}} 1 // CHECK: [[REVINDEX:%[0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %Mask, i1 true) // CHECK: [[INDEX:%[0-9]+]] = xor i32 [[REVINDEX]], 31 -// CHECK: store i32 [[INDEX]], i32* %Index, align 4 +// CHECK: store i32 [[INDEX]], i32* [[IDXGEP]], align 4 // CHECK: br label %[[END_LABEL]] #if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) @@ -430,48 +432,77 @@ __int64 test_InterlockedCompareExchange64(__int64 volatile *Destination, __int64 // CHECK: ret i64 [[RESULT]] // CHECK: } -#if defined(__x86_64__) +#if defined(__x86_64__) || defined(__aarch64__) unsigned char test_InterlockedCompareExchange128( __int64 volatile *Destination, __int64 ExchangeHigh, __int64 ExchangeLow, __int64 *ComparandResult) { return _InterlockedCompareExchange128(++Destination, ++ExchangeHigh, ++ExchangeLow, ++ComparandResult); } -// CHECK-X64: define{{.*}}i8 @test_InterlockedCompareExchange128(i64*{{[a-z_ ]*}}%Destination, i64{{[a-z_ ]*}}%ExchangeHigh, i64{{[a-z_ ]*}}%ExchangeLow, i64*{{[a-z_ ]*}}%ComparandResult){{.*}}{ -// CHECK-X64: %incdec.ptr = getelementptr inbounds i64, i64* %Destination, i64 1 -// CHECK-X64: %inc = add nsw i64 %ExchangeHigh, 1 -// CHECK-X64: %inc1 = add nsw i64 %ExchangeLow, 1 -// CHECK-X64: %incdec.ptr2 = getelementptr inbounds i64, i64* %ComparandResult, i64 1 -// CHECK-X64: [[DST:%[0-9]+]] = bitcast i64* %incdec.ptr to i128* -// CHECK-X64: [[EH:%[0-9]+]] = zext i64 %inc to i128 -// CHECK-X64: [[EL:%[0-9]+]] = zext i64 %inc1 to i128 -// CHECK-X64: [[CNR:%[0-9]+]] = bitcast i64* %incdec.ptr2 to i128* -// CHECK-X64: [[EHS:%[0-9]+]] = shl nuw i128 [[EH]], 64 -// CHECK-X64: [[EXP:%[0-9]+]] = or i128 [[EHS]], [[EL]] -// CHECK-X64: [[ORG:%[0-9]+]] = load i128, i128* [[CNR]], align 16 -// CHECK-X64: [[RES:%[0-9]+]] = cmpxchg volatile i128* [[DST]], i128 [[ORG]], i128 [[EXP]] seq_cst seq_cst -// CHECK-X64: [[OLD:%[0-9]+]] = extractvalue { i128, i1 } [[RES]], 0 -// CHECK-X64: store i128 [[OLD]], i128* [[CNR]], align 16 -// CHECK-X64: [[SUC1:%[0-9]+]] = extractvalue { i128, i1 } [[RES]], 1 -// CHECK-X64: [[SUC8:%[0-9]+]] = zext i1 [[SUC1]] to i8 -// CHECK-X64: ret i8 [[SUC8]] -// CHECK-X64: } +// CHECK-64: define{{.*}}i8 @test_InterlockedCompareExchange128(i64*{{[a-z_ ]*}}%Destination, i64{{[a-z_ ]*}}%ExchangeHigh, i64{{[a-z_ ]*}}%ExchangeLow, i64*{{[a-z_ ]*}}%ComparandResult){{.*}}{ +// CHECK-64: %incdec.ptr = getelementptr inbounds i64, i64* %Destination, i64 1 +// CHECK-64: %inc = add nsw i64 %ExchangeHigh, 1 +// CHECK-64: %inc1 = add nsw i64 %ExchangeLow, 1 +// CHECK-64: %incdec.ptr2 = getelementptr inbounds i64, i64* %ComparandResult, i64 1 +// CHECK-64: [[DST:%[0-9]+]] = bitcast i64* %incdec.ptr to i128* +// CHECK-64: [[CNR:%[0-9]+]] = bitcast i64* %incdec.ptr2 to i128* +// CHECK-64: [[EH:%[0-9]+]] = zext i64 %inc to i128 +// CHECK-64: [[EL:%[0-9]+]] = zext i64 %inc1 to i128 +// CHECK-64: [[EHS:%[0-9]+]] = shl nuw i128 [[EH]], 64 +// CHECK-64: [[EXP:%[0-9]+]] = or i128 [[EHS]], [[EL]] +// CHECK-64: [[ORG:%[0-9]+]] = load i128, i128* [[CNR]], align 16 +// CHECK-64: [[RES:%[0-9]+]] = cmpxchg volatile i128* [[DST]], i128 [[ORG]], i128 [[EXP]] seq_cst seq_cst +// CHECK-64: [[OLD:%[0-9]+]] = extractvalue { i128, i1 } [[RES]], 0 +// CHECK-64: store i128 [[OLD]], i128* [[CNR]], align 16 +// CHECK-64: [[SUC1:%[0-9]+]] = extractvalue { i128, i1 } [[RES]], 1 +// CHECK-64: [[SUC8:%[0-9]+]] = zext i1 [[SUC1]] to i8 +// CHECK-64: ret i8 [[SUC8]] +// CHECK-64: } +#endif + +#if defined(__aarch64__) +unsigned char test_InterlockedCompareExchange128_acq( + __int64 volatile *Destination, __int64 ExchangeHigh, + __int64 ExchangeLow, __int64 *ComparandResult) { + return _InterlockedCompareExchange128_acq(Destination, ExchangeHigh, + ExchangeLow, ComparandResult); +} +unsigned char test_InterlockedCompareExchange128_nf( + __int64 volatile *Destination, __int64 ExchangeHigh, + __int64 ExchangeLow, __int64 *ComparandResult) { + return _InterlockedCompareExchange128_nf(Destination, ExchangeHigh, + ExchangeLow, ComparandResult); +} +unsigned char test_InterlockedCompareExchange128_rel( + __int64 volatile *Destination, __int64 ExchangeHigh, + __int64 ExchangeLow, __int64 *ComparandResult) { + return _InterlockedCompareExchange128_rel(Destination, ExchangeHigh, + ExchangeLow, ComparandResult); +} +// CHECK-ARM64: define{{.*}}i8 @test_InterlockedCompareExchange128_acq({{.*}}) +// CHECK-ARM64: cmpxchg volatile i128* %{{.*}}, i128 %{{.*}}, i128 %{{.*}} acquire acquire +// CHECK-ARM64: define{{.*}}i8 @test_InterlockedCompareExchange128_nf({{.*}}) +// CHECK-ARM64: cmpxchg volatile i128* %{{.*}}, i128 %{{.*}}, i128 %{{.*}} monotonic monotonic +// CHECK-ARM64: define{{.*}}i8 @test_InterlockedCompareExchange128_rel({{.*}}) +// CHECK-ARM64: cmpxchg volatile i128* %{{.*}}, i128 %{{.*}}, i128 %{{.*}} release monotonic #endif short test_InterlockedIncrement16(short volatile *Addend) { - return _InterlockedIncrement16(Addend); + return _InterlockedIncrement16(++Addend); } // CHECK: define{{.*}}i16 @test_InterlockedIncrement16(i16*{{[a-z_ ]*}}%Addend){{.*}}{ -// CHECK: [[TMP:%[0-9]+]] = atomicrmw add i16* %Addend, i16 1 seq_cst +// CHECK: %incdec.ptr = getelementptr inbounds i16, i16* %Addend, {{i64|i32}} 1 +// CHECK: [[TMP:%[0-9]+]] = atomicrmw add i16* %incdec.ptr, i16 1 seq_cst // CHECK: [[RESULT:%[0-9]+]] = add i16 [[TMP]], 1 // CHECK: ret i16 [[RESULT]] // CHECK: } long test_InterlockedIncrement(long volatile *Addend) { - return _InterlockedIncrement(Addend); + return _InterlockedIncrement(++Addend); } // CHECK: define{{.*}}i32 @test_InterlockedIncrement(i32*{{[a-z_ ]*}}%Addend){{.*}}{ -// CHECK: [[TMP:%[0-9]+]] = atomicrmw add i32* %Addend, i32 1 seq_cst +// CHECK: %incdec.ptr = getelementptr inbounds i32, i32* %Addend, {{i64|i32}} 1 +// CHECK: [[TMP:%[0-9]+]] = atomicrmw add i32* %incdec.ptr, i32 1 seq_cst // CHECK: [[RESULT:%[0-9]+]] = add i32 [[TMP]], 1 // CHECK: ret i32 [[RESULT]] // CHECK: } diff --git a/clang/test/CodeGen/thinlto-distributed-cfi-devirt.ll b/clang/test/CodeGen/thinlto-distributed-cfi-devirt.ll index 5c753ba6f93c3..0a330a53e9487 100644 --- a/clang/test/CodeGen/thinlto-distributed-cfi-devirt.ll +++ b/clang/test/CodeGen/thinlto-distributed-cfi-devirt.ll @@ -40,8 +40,16 @@ ; CHECK-DIS: ^2 = typeid: (name: "_ZTS1A", summary: (typeTestRes: (kind: allOnes, sizeM1BitWidth: 7), wpdResolutions: ((offset: 0, wpdRes: (kind: branchFunnel)), (offset: 8, wpdRes: (kind: singleImpl, singleImplName: "_ZN1A1nEi"))))) ; guid = 7004155349499253778 ; RUN: %clang_cc1 -triple x86_64-grtev4-linux-gnu \ -; RUN: -emit-obj -fthinlto-index=%t.o.thinlto.bc -O2 \ -; RUN: -emit-llvm -o - -x ir %t.o | FileCheck %s --check-prefixes=CHECK-IR +; RUN: -emit-obj -fthinlto-index=%t.o.thinlto.bc -O2 -Rpass=wholeprogramdevirt \ +; RUN: -emit-llvm -o - -x ir %t.o 2>&1 | FileCheck %s --check-prefixes=CHECK-IR --check-prefixes=REMARKS + +; Check that the devirtualization is suppressed via -wholeprogramdevirt-skip +; RUN: %clang_cc1 -triple x86_64-grtev4-linux-gnu -mllvm -wholeprogramdevirt-skip=_ZN1A1nEi \ +; RUN: -emit-obj -fthinlto-index=%t.o.thinlto.bc -O2 -Rpass=wholeprogramdevirt \ +; RUN: -emit-llvm -o - -x ir %t.o 2>&1 | FileCheck %s --check-prefixes=SKIP-IR --check-prefixes=SKIP-REMARKS + +; REMARKS: single-impl: devirtualized a call to _ZN1A1nEi +; SKIP-REMARKS-NOT: single-impl ; Check that backend does not fail generating native code. ; RUN: %clang_cc1 -triple x86_64-grtev4-linux-gnu \ @@ -78,6 +86,7 @@ cont: ; Check that the call was devirtualized. ; CHECK-IR: %call = tail call i32 @_ZN1A1nEi + ; SKIP-IR-NOT: %call = tail call i32 @_ZN1A1nEi %call = tail call i32 %4(%struct.A* nonnull %obj, i32 %a) %vtable16 = load i8*, i8** %0 %5 = tail call { i8*, i1 } @llvm.type.checked.load(i8* %vtable16, i32 0, metadata !"_ZTS1A") diff --git a/clang/test/CodeGen/thinlto_embed_bitcode.ll b/clang/test/CodeGen/thinlto_embed_bitcode.ll index 6c7e36e7226ba..590cadbfd418b 100644 --- a/clang/test/CodeGen/thinlto_embed_bitcode.ll +++ b/clang/test/CodeGen/thinlto_embed_bitcode.ll @@ -18,7 +18,7 @@ ; RUN: %clang -target x86_64-unknown-linux-gnu -O2 -o %t.o -x ir %t1.bc -c -fthinlto-index=%t.o.thinlto.bc -mllvm -lto-embed-bitcode=post-merge-pre-opt ; RUN: llvm-readelf -S %t.o | FileCheck %s --check-prefixes=CHECK-ELF,CHECK-ELF-CMD ; RUN: llvm-objcopy --dump-section=.llvmcmd=%t-embedded.cmd %t.o /dev/null -; RUN: grep x86_64-unknown-linux-gnu %t-embedded.cmd | count 1 +; RUN: FileCheck %s --check-prefixes=CHECK-EMBEDDED-CMD <%t-embedded.cmd ; RUN: llvm-objcopy --dump-section=.llvmbc=%t-embedded.bc %t.o /dev/null ; RUN: llvm-dis %t-embedded.bc -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NOOPT ; We should only need the index and the post-thinlto merged module to generate @@ -43,3 +43,6 @@ ; CHECK-NOOPT-NEXT: call void @bar() ; CHECK-NOOPT: define available_externally void @bar() ; CHECK-NOOPT-NEXT: ret void + +; CHECK-EMBEDDED-CMD: x86_64-unknown-linux-gnu{{.*$}} +; CHECK-EMBEDDED-CMD-NOT: x86_64-unknown-linux-gnu diff --git a/clang/test/CodeGenCUDA/fp-contract.cu b/clang/test/CodeGenCUDA/fp-contract.cu index 96de5c451b02f..d466affded132 100644 --- a/clang/test/CodeGenCUDA/fp-contract.cu +++ b/clang/test/CodeGenCUDA/fp-contract.cu @@ -1,32 +1,298 @@ -// REQUIRES: x86-registered-target -// REQUIRES: nvptx-registered-target +// REQUIRES: x86-registered-target, nvptx-registered-target, amdgpu-registered-target -// By default we should fuse multiply/add into fma instruction. +// By default CUDA uses -ffp-contract=fast, HIP uses -ffp-contract=fast-honor-pragmas. +// we should fuse multiply/add into fma instruction. +// In IR, fmul/fadd instructions with contract flag are emitted. +// In backend +// nvptx - assumes fast fp fuse option, which fuses +// mult/add insts disregarding contract flag and +// llvm.fmuladd intrinsics. +// amdgcn - assumes standard fp fuse option, which only +// fuses mult/add insts with contract flag and +// llvm.fmuladd intrinsics. + +// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ +// RUN: -disable-llvm-passes -o - %s \ +// RUN: | FileCheck -check-prefixes=COMMON,NV-ON %s +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \ +// RUN: -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-ON %s // RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ -// RUN: -disable-llvm-passes -o - %s | FileCheck -check-prefix ENABLED %s +// RUN: -O3 -o - %s \ +// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-FAST %s +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \ +// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s + +// Check separate compile/backend steps corresponding to -save-temps. + +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \ +// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s +// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-FAST-IR %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \ +// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s // Explicit -ffp-contract=fast +// In IR, fmul/fadd instructions with contract flag are emitted. +// In backend +// nvptx/amdgcn - assumes fast fp fuse option, which fuses +// mult/add insts disregarding contract flag and +// llvm.fmuladd intrinsics. + // RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ // RUN: -ffp-contract=fast -disable-llvm-passes -o - %s \ -// RUN: | FileCheck -check-prefix ENABLED %s +// RUN: | FileCheck -check-prefixes=COMMON,NV-ON %s +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \ +// RUN: -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \ +// RUN: -ffp-contract=fast \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-ON %s +// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ +// RUN: -O3 -o - %s \ +// RUN: -ffp-contract=fast \ +// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-FAST %s +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \ +// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \ +// RUN: -ffp-contract=fast \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FAST %s + +// Check separate compile/backend steps corresponding to -save-temps. +// When input is IR, -ffp-contract has no effect. Backend uses default +// default FP fuse option. + +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \ +// RUN: -ffp-contract=fast \ +// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s +// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-FAST-IR %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \ +// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s + +// Explicit -ffp-contract=fast-honor-pragmas +// In IR, fmul/fadd instructions with contract flag are emitted. +// In backend +// nvptx/amdgcn - assumes standard fp fuse option, which only +// fuses mult/add insts with contract flag or +// llvm.fmuladd intrinsics. + +// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ +// RUN: -ffp-contract=fast-honor-pragmas -disable-llvm-passes -o - %s \ +// RUN: | FileCheck -check-prefixes=COMMON,NV-ON %s +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \ +// RUN: -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \ +// RUN: -ffp-contract=fast-honor-pragmas \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-ON %s +// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ +// RUN: -O3 -o - %s \ +// RUN: -ffp-contract=fast-honor-pragmas \ +// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-FASTSTD %s +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \ +// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \ +// RUN: -ffp-contract=fast-honor-pragmas \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s + +// Check separate compile/backend steps corresponding to -save-temps. +// When input is IR, -ffp-contract has no effect. Backend uses default +// default FP fuse option. + +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \ +// RUN: -ffp-contract=fast-honor-pragmas \ +// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s +// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-FAST-IR %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \ +// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-FASTSTD %s // Explicit -ffp-contract=on -- fusing by front-end. +// In IR, +// mult/add in the same statement - llvm.fmuladd instrinsic emitted +// mult/add in different statement - fmul/fadd instructions without +// contract flag are emitted. +// In backend +// nvptx/amdgcn - assumes standard fp fuse option, which only +// fuses mult/add insts with contract flag or +// llvm.fmuladd intrinsics. + // RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ // RUN: -ffp-contract=on -disable-llvm-passes -o - %s \ -// RUN: | FileCheck -check-prefix ENABLED %s +// RUN: | FileCheck -check-prefixes=COMMON,NV-ON %s +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \ +// RUN: -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \ +// RUN: -ffp-contract=on \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-ON %s +// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ +// RUN: -O3 -o - %s \ +// RUN: -ffp-contract=on \ +// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-ON %s +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \ +// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \ +// RUN: -ffp-contract=on \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-ON %s + +// Check separate compile/backend steps corresponding to -save-temps. + +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \ +// RUN: -ffp-contract=on \ +// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s +// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-ON-IR %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \ +// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-ON %s // Explicit -ffp-contract=off should disable instruction fusing. +// In IR, fmul/fadd instructions without contract flag are emitted. +// In backend +// nvptx/amdgcn - assumes standard fp fuse option, which only +// fuses mult/add insts with contract flag or +// llvm.fmuladd intrinsics. + // RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ // RUN: -ffp-contract=off -disable-llvm-passes -o - %s \ -// RUN: | FileCheck -check-prefix DISABLED %s +// RUN: | FileCheck -check-prefixes=COMMON,NV-OFF %s +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \ +// RUN: -target-cpu gfx906 -disable-llvm-passes -o - -x hip %s \ +// RUN: -ffp-contract=off \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-OFF %s +// RUN: %clang_cc1 -fcuda-is-device -triple nvptx-nvidia-cuda -S \ +// RUN: -O3 -o - %s \ +// RUN: -ffp-contract=off \ +// RUN: | FileCheck -check-prefixes=COMMON,NV-OPT-OFF %s +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -S \ +// RUN: -O3 -target-cpu gfx906 -o - -x hip %s \ +// RUN: -ffp-contract=off \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-OFF %s + +// Check separate compile/backend steps corresponding to -save-temps. +// RUN: %clang_cc1 -fcuda-is-device -triple amdgcn-amd-amdhsa -emit-llvm \ +// RUN: -ffp-contract=off \ +// RUN: -O3 -disable-llvm-passes -target-cpu gfx906 -o %t.ll -x hip %s +// RUN: cat %t.ll | FileCheck -check-prefixes=COMMON,AMD-OPT-OFF-IR %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -S \ +// RUN: -O3 -target-cpu gfx906 -o - -x ir %t.ll \ +// RUN: | FileCheck -check-prefixes=COMMON,AMD-OPT-OFF %s #include "Inputs/cuda.h" +// Test multiply/add in the same statement, which can be emitted as FMA when +// fp-contract is on or fast. __host__ __device__ float func(float a, float b, float c) { return a + b * c; } -// ENABLED: fma.rn.f32 -// ENABLED-NEXT: st.param.f32 +// COMMON-LABEL: _Z4funcfff +// NV-ON: fma.rn.f32 +// NV-ON-NEXT: st.param.f32 +// AMD-ON: v_fmac_f32_e64 +// AMD-ON-NEXT: s_setpc_b64 + +// NV-OFF: mul.rn.f32 +// NV-OFF-NEXT: add.rn.f32 +// NV-OFF-NEXT: st.param.f32 +// AMD-OFF: v_mul_f32_e64 +// AMD-OFF-NEXT: v_add_f32_e64 +// AMD-OFF-NEXT: s_setpc_b64 + +// NV-OPT-FAST: fma.rn.f32 +// NV-OPT-FAST-NEXT: st.param.f32 +// NV-OPT-FASTSTD: fma.rn.f32 +// NV-OPT-FASTSTD-NEXT: st.param.f32 +// NV-OPT-ON: fma.rn.f32 +// NV-OPT-ON-NEXT: st.param.f32 +// NV-OPT-OFF: mul.rn.f32 +// NV-OPT-OFF-NEXT: add.rn.f32 +// NV-OPT-OFF-NEXT: st.param.f32 + +// AMD-OPT-FAST-IR: fmul contract float +// AMD-OPT-FAST-IR: fadd contract float +// AMD-OPT-ON-IR: @llvm.fmuladd.f32 +// AMD-OPT-OFF-IR: fmul float +// AMD-OPT-OFF-IR: fadd float + +// AMD-OPT-FAST: v_fmac_f32_e32 +// AMD-OPT-FAST-NEXT: s_setpc_b64 +// AMD-OPT-FASTSTD: v_fmac_f32_e32 +// AMD-OPT-FASTSTD-NEXT: s_setpc_b64 +// AMD-OPT-ON: v_fmac_f32_e32 +// AMD-OPT-ON-NEXT: s_setpc_b64 +// AMD-OPT-OFF: v_mul_f32_e32 +// AMD-OPT-OFF-NEXT: v_add_f32_e32 +// AMD-OPT-OFF-NEXT: s_setpc_b64 + +// Test multiply/add in the different statements, which can be emitted as +// FMA when fp-contract is fast but not on. +__host__ __device__ float func2(float a, float b, float c) { + float t = b * c; + return t + a; +} +// COMMON-LABEL: _Z5func2fff +// NV-OPT-FAST: fma.rn.f32 +// NV-OPT-FAST-NEXT: st.param.f32 +// NV-OPT-FASTSTD: fma.rn.f32 +// NV-OPT-FASTSTD-NEXT: st.param.f32 +// NV-OPT-ON: mul.rn.f32 +// NV-OPT-ON: add.rn.f32 +// NV-OPT-ON-NEXT: st.param.f32 +// NV-OPT-OFF: mul.rn.f32 +// NV-OPT-OFF: add.rn.f32 +// NV-OPT-OFF-NEXT: st.param.f32 + +// AMD-OPT-FAST-IR: fmul contract float +// AMD-OPT-FAST-IR: fadd contract float +// AMD-OPT-ON-IR: fmul float +// AMD-OPT-ON-IR: fadd float +// AMD-OPT-OFF-IR: fmul float +// AMD-OPT-OFF-IR: fadd float + +// AMD-OPT-FAST: v_fmac_f32_e32 +// AMD-OPT-FAST-NEXT: s_setpc_b64 +// AMD-OPT-FASTSTD: v_fmac_f32_e32 +// AMD-OPT-FASTSTD-NEXT: s_setpc_b64 +// AMD-OPT-ON: v_mul_f32_e32 +// AMD-OPT-ON-NEXT: v_add_f32_e32 +// AMD-OPT-ON-NEXT: s_setpc_b64 +// AMD-OPT-OFF: v_mul_f32_e32 +// AMD-OPT-OFF-NEXT: v_add_f32_e32 +// AMD-OPT-OFF-NEXT: s_setpc_b64 + +// Test multiply/add in the different statements, which is forced +// to be compiled with fp contract on. fmul/fadd without contract +// flags are emitted in IR. In nvptx, they are emitted as FMA in +// fp-contract is fast but not on, as nvptx backend uses the same +// fp fuse option as front end, whereas fast fp fuse option in +// backend fuses fadd/fmul disregarding contract flag. In amdgcn +// they are not fused as amdgcn always use standard fp fusion +// option which respects contract flag. + __host__ __device__ float func3(float a, float b, float c) { +#pragma clang fp contract(on) + float t = b * c; + return t + a; +} +// COMMON-LABEL: _Z5func3fff +// NV-OPT-FAST: fma.rn.f32 +// NV-OPT-FAST-NEXT: st.param.f32 +// NV-OPT-FASTSTD: mul.rn.f32 +// NV-OPT-FASTSTD: add.rn.f32 +// NV-OPT-FASTSTD-NEXT: st.param.f32 +// NV-OPT-ON: mul.rn.f32 +// NV-OPT-ON: add.rn.f32 +// NV-OPT-ON-NEXT: st.param.f32 +// NV-OPT-OFF: mul.rn.f32 +// NV-OPT-OFF: add.rn.f32 +// NV-OPT-OFF-NEXT: st.param.f32 + +// AMD-OPT-FAST-IR: fmul float +// AMD-OPT-FAST-IR: fadd float +// AMD-OPT-ON-IR: fmul float +// AMD-OPT-ON-IR: fadd float +// AMD-OPT-OFF-IR: fmul float +// AMD-OPT-OFF-IR: fadd float -// DISABLED: mul.rn.f32 -// DISABLED-NEXT: add.rn.f32 -// DISABLED-NEXT: st.param.f32 +// AMD-OPT-FAST: v_fmac_f32_e32 +// AMD-OPT-FAST-NEXT: s_setpc_b64 +// AMD-OPT-FASTSTD: v_mul_f32_e32 +// AMD-OPT-FASTSTD-NEXT: v_add_f32_e32 +// AMD-OPT-FASTSTD-NEXT: s_setpc_b64 +// AMD-OPT-ON: v_mul_f32_e32 +// AMD-OPT-ON-NEXT: v_add_f32_e32 +// AMD-OPT-ON-NEXT: s_setpc_b64 +// AMD-OPT-OFF: v_mul_f32_e32 +// AMD-OPT-OFF-NEXT: v_add_f32_e32 +// AMD-OPT-OFF-NEXT: s_setpc_b64 diff --git a/clang/test/CodeGenCXX/clang-abi-compat.cpp b/clang/test/CodeGenCXX/clang-abi-compat.cpp index 409c72108f641..7943cad004e12 100644 --- a/clang/test/CodeGenCXX/clang-abi-compat.cpp +++ b/clang/test/CodeGenCXX/clang-abi-compat.cpp @@ -1,9 +1,10 @@ -// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=3.0 %s -emit-llvm -o - | FileCheck --check-prefix=PRE39 --check-prefix=PRE5 %s -// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=3.8 %s -emit-llvm -o - | FileCheck --check-prefix=PRE39 --check-prefix=PRE5 %s -// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=3.9 %s -emit-llvm -o - | FileCheck --check-prefix=V39 --check-prefix=PRE5 %s -// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=4.0 %s -emit-llvm -o - | FileCheck --check-prefix=V39 --check-prefix=PRE5 %s -// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=5 %s -emit-llvm -o - | FileCheck --check-prefix=V39 --check-prefix=V5 %s -// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=latest %s -emit-llvm -o - | FileCheck --check-prefix=V39 --check-prefix=V5 %s +// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=3.0 %s -emit-llvm -o - | FileCheck --check-prefixes=PRE39,PRE5,PRE12 %s +// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=3.8 %s -emit-llvm -o - | FileCheck --check-prefixes=PRE39,PRE5,PRE12 %s +// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=3.9 %s -emit-llvm -o - | FileCheck --check-prefixes=V39,PRE5,PRE12 %s +// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=4.0 %s -emit-llvm -o - | FileCheck --check-prefixes=V39,PRE5,PRE12 %s +// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=5 %s -emit-llvm -o - | FileCheck --check-prefixes=V39,V5,PRE12 %s +// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=11 %s -emit-llvm -o - | FileCheck --check-prefixes=V11,V5,PRE12 %s +// RUN: %clang_cc1 -std=c++17 -triple x86_64-linux-gnu -fclang-abi-compat=latest %s -emit-llvm -o - | FileCheck --check-prefixes=V39,V5,V12 %s typedef __attribute__((vector_size(8))) long long v1xi64; void clang39(v1xi64) {} @@ -17,3 +18,12 @@ struct A { void clang5(A) {} // PRE5: @_Z6clang51A() // V5: @_Z6clang51A(%{{.*}}* + +namespace mangle_template_prefix { + // PRE12: @_ZN22mangle_template_prefix1fINS_1TEEEvNT_1UIiE1VIiEENS4_S5_IfEE( + // V12: @_ZN22mangle_template_prefix1fINS_1TEEEvNT_1UIiE1VIiEENS5_IfEE( + template void f(typename T::template U::template V, typename T::template U::template V); + struct T { template struct U { template using V = int; }; }; + void g() { f(1, 2); } +} + diff --git a/clang/test/CodeGenCXX/cxx1z-class-deduction.cpp b/clang/test/CodeGenCXX/cxx1z-class-deduction.cpp index 8edab748338e2..bf436e7ec9802 100644 --- a/clang/test/CodeGenCXX/cxx1z-class-deduction.cpp +++ b/clang/test/CodeGenCXX/cxx1z-class-deduction.cpp @@ -29,9 +29,9 @@ struct X { template struct C { C(T); }; }; -// CHECK: @_Z1gIiEDaT_DTcv1AfL0p_E1AIS0_E( +// CHECK: @_Z1gIiEDaT_DTcv1AfL0p_ES1_IS0_E template auto g(T x, decltype(A(x)), A) {} -// CHECK: @_Z1hIiEDaT_DTcvN1N1BEfL0p_ENS1_1BIS0_EE( +// CHECK: @_Z1hIiEDaT_DTcvN1N1BEfL0p_ENS2_IS0_EE template auto h(T x, decltype(B(x)), B) {} // CHECK: @_Z1iI1XiEDaT0_DTcvNT_1CEfL0p_ENS2_1CIS1_EE( template auto i(T x, decltype(typename U::C(x)), typename U::template C) {} diff --git a/clang/test/CodeGenCXX/implicit-function-conversion.cpp b/clang/test/CodeGenCXX/implicit-function-conversion.cpp deleted file mode 100644 index bc4b2bc8d15c3..0000000000000 --- a/clang/test/CodeGenCXX/implicit-function-conversion.cpp +++ /dev/null @@ -1,7 +0,0 @@ -// RUN: %clang_cc1 -emit-llvm %s -o - -triple=x86_64-unknown-linux -std=c++17 | FileCheck %s - -double a(double) noexcept; -int b(double (&)(double)); - -// CHECK: call i32 @_Z1bRFddE(double (double)* nonnull @_Z1ad) -int c = b(a); diff --git a/clang/test/CodeGenCXX/mangle-template.cpp b/clang/test/CodeGenCXX/mangle-template.cpp index 23134693de5c0..45868f51f5e81 100644 --- a/clang/test/CodeGenCXX/mangle-template.cpp +++ b/clang/test/CodeGenCXX/mangle-template.cpp @@ -212,3 +212,12 @@ __make_integer_seq make() {} template __make_integer_seq make<5>(); // CHECK: define weak_odr {{.*}} @_ZN6test154makeILi5EEE18__make_integer_seqISt16integer_sequenceiXT_EEv( } + +namespace test16 { + // Ensure we properly form substitutions for template names in prefixes. + // CHECK: @_ZN6test161fINS_1TEEEvNT_1UIiE1VIiEENS5_IfEE + template void f(typename T::template U::template V, typename T::template U::template V); + struct T { template struct U { template using V = int; }; }; + void g() { f(1, 2); } +} + diff --git a/clang/test/CodeGenCXX/visibility-dllstorageclass.cpp b/clang/test/CodeGenCXX/visibility-dllstorageclass.cpp index 9003909f3ee0e..c4dddcec2eb09 100644 --- a/clang/test/CodeGenCXX/visibility-dllstorageclass.cpp +++ b/clang/test/CodeGenCXX/visibility-dllstorageclass.cpp @@ -5,12 +5,14 @@ // RUN: %clang_cc1 -triple x86_64-unknown-windows-itanium -fdeclspec \ // RUN: -fvisibility hidden \ +// RUN: -fapply-global-visibility-to-externs \ // RUN: -fvisibility-from-dllstorageclass \ // RUN: -x c++ %s -S -emit-llvm -o - | \ -// RUN: FileCheck %s --check-prefixes=DEFAULT +// RUN: FileCheck %s --check-prefixes=DEFAULTS // RUN: %clang_cc1 -triple x86_64-unknown-windows-itanium -fdeclspec \ // RUN: -fvisibility hidden \ +// RUN: -fapply-global-visibility-to-externs \ // RUN: -fvisibility-from-dllstorageclass \ // RUN: -fvisibility-dllexport=hidden \ // RUN: -fvisibility-nodllstorageclass=protected \ @@ -19,45 +21,78 @@ // RUN: -x c++ %s -S -emit-llvm -o - | \ // RUN: FileCheck %s --check-prefixes=EXPLICIT +// RUN: %clang_cc1 -triple x86_64-unknown-windows-itanium -fdeclspec \ +// RUN: -fvisibility hidden \ +// RUN: -fapply-global-visibility-to-externs \ +// RUN: -fvisibility-from-dllstorageclass \ +// RUN: -fvisibility-dllexport=default \ +// RUN: -fvisibility-nodllstorageclass=default \ +// RUN: -fvisibility-externs-dllimport=default \ +// RUN: -fvisibility-externs-nodllstorageclass=default \ +// RUN: -x c++ %s -S -emit-llvm -o - | \ +// RUN: FileCheck %s --check-prefixes=ALL_DEFAULT + // Local static void l() {} void use_locals(){l();} -// DEFAULT-DAG: define internal void @_ZL1lv() +// DEFAULTS-DAG: define internal void @_ZL1lv() // EXPLICIT-DAG: define internal void @_ZL1lv() +// ALL_DEFAULT-DAG: define internal void @_ZL1lv() // Function void f() {} void __declspec(dllexport) exported_f() {} -// DEFAULT-DAG: define hidden void @_Z1fv() -// DEFAULT-DAG: define dso_local void @_Z10exported_fv() +// DEFAULTS-DAG: define hidden void @_Z1fv() +// DEFAULTS-DAG: define void @_Z10exported_fv() // EXPLICIT-DAG: define protected void @_Z1fv() // EXPLICIT-DAG: define hidden void @_Z10exported_fv() +// ALL_DEFAULT-DAG: define void @_Z1fv() +// ALL_DEFAULT-DAG: define void @_Z10exported_fv() // Variable int d = 123; __declspec(dllexport) int exported_d = 123; -// DEFAULT-DAG: @d = hidden global -// DEFAULT-DAG: @exported_d = dso_local global +// DEFAULTS-DAG: @d = hidden global +// DEFAULTS-DAG: @exported_d = global // EXPLICIT-DAG: @d = protected global // EXPLICIT-DAG: @exported_d = hidden global +// ALL_DEFAULT-DAG: @d = global +// ALL_DEFAULT-DAG: @exported_d = global // Alias extern "C" void aliased() {} void a() __attribute__((alias("aliased"))); void __declspec(dllexport) a_exported() __attribute__((alias("aliased"))); -// DEFAULT-DAG: @_Z1av = hidden alias -// DEFAULT-DAG: @_Z10a_exportedv = dso_local alias +// DEFAULTS-DAG: @_Z1av = hidden alias +// DEFAULTS-DAG: @_Z10a_exportedv = alias // EXPLICIT-DAG: @_Z1av = protected alias // EXPLICIT-DAG: @_Z10a_exportedv = hidden alias +// ALL_DEFAULT-DAG: @_Z1av = alias +// ALL_DEFAULT-DAG: @_Z10a_exportedv = alias // Declaration extern void e(); extern void __declspec(dllimport) imported_e(); -void use_declarations(){e(); imported_e();} -// DEFAULT-DAG: declare hidden void @_Z1ev() -// DEFAULT-DAG: declare void @_Z10imported_ev() +// DEFAULTS-DAG: declare hidden void @_Z1ev() +// DEFAULTS-DAG: declare void @_Z10imported_ev() // EXPLICIT-DAG: declare protected void @_Z1ev() // EXPLICIT-DAG: declare hidden void @_Z10imported_ev() +// ALL_DEFAULT-DAG: declare void @_Z1ev() +// ALL_DEFAULT-DAG: declare void @_Z10imported_ev() + +// Weak Declaration +__attribute__((weak)) +extern void w(); +__attribute__((weak)) +extern void __declspec(dllimport) imported_w(); +// DEFAULTS-DAG: declare extern_weak hidden void @_Z1wv() +// DEFAULTS-DAG: declare extern_weak void @_Z10imported_wv() +// EXPLICIT-DAG: declare extern_weak protected void @_Z1wv() +// EXPLICIT-DAG: declare extern_weak hidden void @_Z10imported_wv() +// ALL_DEFAULT-DAG: declare extern_weak void @_Z1wv() +// ALL_DEFAULT-DAG: declare extern_weak void @_Z10imported_wv() + +void use_declarations(){e(); imported_e(); w(); imported_w();} // Show that -fvisibility-from-dllstorageclass overrides the effect of visibility annotations. @@ -65,12 +100,12 @@ struct __attribute__((type_visibility("protected"))) t { virtual void foo(); }; void t::foo() {} -// DEFAULT-DAG: @_ZTV1t = hidden unnamed_addr constant +// DEFAULTS-DAG: @_ZTV1t = hidden unnamed_addr constant int v __attribute__ ((__visibility__ ("protected"))) = 123; -// DEFAULT-DAG: @v = hidden global +// DEFAULTS-DAG: @v = hidden global #pragma GCC visibility push(protected) int p = 345; #pragma GCC visibility pop -// DEFAULT-DAG: @p = hidden global +// DEFAULTS-DAG: @p = hidden global diff --git a/clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/lib/sparc64-linux-gnu/crti.o b/clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/lib/sparc64-linux-gnu/crti.o deleted file mode 100644 index e69de29bb2d1d..0000000000000 diff --git a/clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/lib/sparc64-linux-gnu/crtn.o b/clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/lib/sparc64-linux-gnu/crtn.o deleted file mode 100644 index e69de29bb2d1d..0000000000000 diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/gcc/sparc-linux-gnu/4.9/64/crtend.o b/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/gcc/sparc-linux-gnu/4.9/64/crtend.o deleted file mode 100644 index e69de29bb2d1d..0000000000000 diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/gcc/sparc-linux-gnu/4.9/crtbegin.o b/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/gcc/sparc-linux-gnu/4.9/crtbegin.o deleted file mode 100644 index e69de29bb2d1d..0000000000000 diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/gcc/sparc-linux-gnu/4.9/crtend.o b/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/gcc/sparc-linux-gnu/4.9/crtend.o deleted file mode 100644 index e69de29bb2d1d..0000000000000 diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/sparc-linux-gnu/crt1.o b/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/sparc-linux-gnu/crt1.o deleted file mode 100644 index e69de29bb2d1d..0000000000000 diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/sparc-linux-gnu/crti.o b/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/sparc-linux-gnu/crti.o deleted file mode 100644 index e69de29bb2d1d..0000000000000 diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/sparc-linux-gnu/crtn.o b/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/sparc-linux-gnu/crtn.o deleted file mode 100644 index e69de29bb2d1d..0000000000000 diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib64/crt1.o b/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib64/crt1.o deleted file mode 100644 index e69de29bb2d1d..0000000000000 diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib64/crti.o b/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib64/crti.o deleted file mode 100644 index e69de29bb2d1d..0000000000000 diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib64/crtn.o b/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib64/crtn.o deleted file mode 100644 index e69de29bb2d1d..0000000000000 diff --git a/clang/test/Driver/Inputs/debian_8_sparc64_tree/lib/sparc64-linux-gnu/.keep b/clang/test/Driver/Inputs/debian_multiarch_tree/lib/sparc-linux-gnu/.keep similarity index 100% rename from clang/test/Driver/Inputs/debian_8_sparc64_tree/lib/sparc64-linux-gnu/.keep rename to clang/test/Driver/Inputs/debian_multiarch_tree/lib/sparc-linux-gnu/.keep diff --git a/clang/test/Driver/Inputs/debian_8_sparc64_tree/lib64/.keep b/clang/test/Driver/Inputs/debian_multiarch_tree/lib/sparc64-linux-gnu/.keep similarity index 100% rename from clang/test/Driver/Inputs/debian_8_sparc64_tree/lib64/.keep rename to clang/test/Driver/Inputs/debian_multiarch_tree/lib/sparc64-linux-gnu/.keep diff --git a/clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/include/c++/4.9/.keep b/clang/test/Driver/Inputs/debian_multiarch_tree/usr/include/c++/4.5/sparc-linux-gnu/.keep similarity index 100% rename from clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/include/c++/4.9/.keep rename to clang/test/Driver/Inputs/debian_multiarch_tree/usr/include/c++/4.5/sparc-linux-gnu/.keep diff --git a/clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/include/sparc64-linux-gnu/c++/4.9/.keep b/clang/test/Driver/Inputs/debian_multiarch_tree/usr/include/c++/4.5/sparc64-linux-gnu/.keep similarity index 100% rename from clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/include/sparc64-linux-gnu/c++/4.9/.keep rename to clang/test/Driver/Inputs/debian_multiarch_tree/usr/include/c++/4.5/sparc64-linux-gnu/.keep diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/lib/sparc-linux-gnu/.keep b/clang/test/Driver/Inputs/debian_multiarch_tree/usr/include/sparc-linux-gnu/.keep similarity index 100% rename from clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/lib/sparc-linux-gnu/.keep rename to clang/test/Driver/Inputs/debian_multiarch_tree/usr/include/sparc-linux-gnu/.keep diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/lib64/.keep b/clang/test/Driver/Inputs/debian_multiarch_tree/usr/include/sparc64-linux-gnu/.keep similarity index 100% rename from clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/lib64/.keep rename to clang/test/Driver/Inputs/debian_multiarch_tree/usr/include/sparc64-linux-gnu/.keep diff --git a/clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/lib/gcc/sparc64-linux-gnu/4.9/crtbegin.o b/clang/test/Driver/Inputs/debian_multiarch_tree/usr/lib/gcc/sparc-linux-gnu/4.5/crtbegin.o similarity index 100% rename from clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/lib/gcc/sparc64-linux-gnu/4.9/crtbegin.o rename to clang/test/Driver/Inputs/debian_multiarch_tree/usr/lib/gcc/sparc-linux-gnu/4.5/crtbegin.o diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/gcc/sparc-linux-gnu/4.9/64/crtbegin.o b/clang/test/Driver/Inputs/debian_multiarch_tree/usr/lib/gcc/sparc64-linux-gnu/4.5/crtbegin.o similarity index 100% rename from clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/lib/gcc/sparc-linux-gnu/4.9/64/crtbegin.o rename to clang/test/Driver/Inputs/debian_multiarch_tree/usr/lib/gcc/sparc64-linux-gnu/4.5/crtbegin.o diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/include/c++/4.9/backward/.keep b/clang/test/Driver/Inputs/debian_multiarch_tree/usr/lib/sparc-linux-gnu/.keep similarity index 100% rename from clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/include/c++/4.9/backward/.keep rename to clang/test/Driver/Inputs/debian_multiarch_tree/usr/lib/sparc-linux-gnu/.keep diff --git a/clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/include/sparc-linux-gnu/c++/4.9/64/.keep b/clang/test/Driver/Inputs/debian_multiarch_tree/usr/lib/sparc64-linux-gnu/.keep similarity index 100% rename from clang/test/Driver/Inputs/debian_8_sparc_multilib_tree/usr/include/sparc-linux-gnu/c++/4.9/64/.keep rename to clang/test/Driver/Inputs/debian_multiarch_tree/usr/lib/sparc64-linux-gnu/.keep diff --git a/clang/test/Driver/Inputs/empty-x86_64-apple-darwin.yaml b/clang/test/Driver/Inputs/empty-x86_64-apple-darwin.yaml new file mode 100644 index 0000000000000..c4561050b8b62 --- /dev/null +++ b/clang/test/Driver/Inputs/empty-x86_64-apple-darwin.yaml @@ -0,0 +1,44 @@ +# Created by `clang -target x86_64-apple-darwin10 -c -x c /dev/null -o - | obj2yaml`. +--- !mach-o +FileHeader: + magic: 0xFEEDFACF + cputype: 0x1000007 + cpusubtype: 0x3 + filetype: 0x1 + ncmds: 2 + sizeofcmds: 176 + flags: 0x2000 + reserved: 0x0 +LoadCommands: + - cmd: LC_SEGMENT_64 + cmdsize: 152 + segname: '' + vmaddr: 0 + vmsize: 0 + fileoff: 208 + filesize: 0 + maxprot: 7 + initprot: 7 + nsects: 1 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x0 + size: 0 + offset: 0xD0 + align: 0 + reloff: 0x0 + nreloc: 0 + flags: 0x80000000 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: '' + - cmd: LC_BUILD_VERSION + cmdsize: 24 + platform: 1 + minos: 720896 + sdk: 720896 + ntools: 0 +... diff --git a/clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/lib/gcc/sparc64-linux-gnu/4.9/crtend.o b/clang/test/Driver/Inputs/lld/ld64.lld old mode 100644 new mode 100755 similarity index 100% rename from clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/lib/gcc/sparc64-linux-gnu/4.9/crtend.o rename to clang/test/Driver/Inputs/lld/ld64.lld diff --git a/clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/lib/sparc64-linux-gnu/crt1.o b/clang/test/Driver/Inputs/lld/ld64.lld.darwinnew old mode 100644 new mode 100755 similarity index 100% rename from clang/test/Driver/Inputs/debian_8_sparc64_tree/usr/lib/sparc64-linux-gnu/crt1.o rename to clang/test/Driver/Inputs/lld/ld64.lld.darwinnew diff --git a/clang/test/Driver/aarch64-cpus.c b/clang/test/Driver/aarch64-cpus.c index 139746823660a..131a57940b4c4 100644 --- a/clang/test/Driver/aarch64-cpus.c +++ b/clang/test/Driver/aarch64-cpus.c @@ -752,6 +752,9 @@ // RUN: %clang -target aarch64 -march=armv8-a+ras -### -c %s 2>&1 | FileCheck -check-prefix=V8ARAS -check-prefix=GENERIC %s // V8ARAS: "-target-feature" "+ras" +// RUN: %clang -target aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N2 %s +// NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n2" + // ================== Check whether -march accepts mixed-case values. // RUN: %clang -target aarch64_be -march=ARMV8.1A -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s // RUN: %clang -target aarch64_be -march=ARMV8.1-A -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV81A-BE %s diff --git a/clang/test/Driver/aarch64-features.c b/clang/test/Driver/aarch64-features.c index 7c3f8754049a2..8d8cc3c68afec 100644 --- a/clang/test/Driver/aarch64-features.c +++ b/clang/test/Driver/aarch64-features.c @@ -1,6 +1,8 @@ // RUN: %clang -target aarch64-none-linux-gnu -### %s -fsyntax-only 2>&1 | FileCheck %s // RUN: %clang -target arm64-none-linux-gnu -### %s -fsyntax-only 2>&1 | FileCheck %s +// CHECK: "-munwind-tables" + // The AArch64 PCS states that chars should be unsigned. // CHECK: fno-signed-char diff --git a/clang/test/Driver/aix-vec-extabi.c b/clang/test/Driver/aix-vec-extabi.c new file mode 100644 index 0000000000000..ccc3b0732e4ba --- /dev/null +++ b/clang/test/Driver/aix-vec-extabi.c @@ -0,0 +1,10 @@ +// RUN: %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-extabi %s 2>&1 | \ +// RUN: FileCheck %s + +// CHECK: "-cc1" +// CHECK-SAME: "-mabi=vec-extabi" + +// RUN: %clang -### -target powerpc-unknown-aix -S -maltivec -mabi=vec-default %s 2>&1 | \ +// RUN: FileCheck %s --check-prefix=ERROR + +// ERROR: The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' for the extended Altivec ABI diff --git a/clang/test/Driver/arm-cortex-cpus.c b/clang/test/Driver/arm-cortex-cpus.c index 5df872358a7a1..a312ccfda5a15 100644 --- a/clang/test/Driver/arm-cortex-cpus.c +++ b/clang/test/Driver/arm-cortex-cpus.c @@ -879,6 +879,9 @@ // RUN: %clang -target arm -mcpu=cortex-m55 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-M55 %s // CHECK-CORTEX-M55: "-cc1"{{.*}} "-triple" "thumbv8.1m.main-{{.*}} "-target-cpu" "cortex-m55" +// RUN: %clang -target arm -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NEOVERSE-N2 %s +// CHECK-NEOVERSE-N2: "-cc1"{{.*}} "-triple" "armv8.5a-{{.*}}" "-target-cpu" "neoverse-n2" + // ================== Check whether -mcpu accepts mixed-case values. // RUN: %clang -target arm-linux-gnueabi -mcpu=Cortex-a5 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s // RUN: %clang -target arm-linux-gnueabi -mcpu=cortex-A7 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s diff --git a/clang/test/Driver/autocomplete.c b/clang/test/Driver/autocomplete.c index 89f7c6e761257..85bf6c7912a45 100644 --- a/clang/test/Driver/autocomplete.c +++ b/clang/test/Driver/autocomplete.c @@ -68,6 +68,7 @@ // FNOSANICOVERALL-NEXT: trace-pc-guard // RUN: %clang --autocomplete=-ffp-contract= | FileCheck %s -check-prefix=FFPALL // FFPALL: fast +// FFPALL-NEXT: fast-honor-pragmas // FFPALL-NEXT: off // FFPALL-NEXT: on // RUN: %clang --autocomplete=-flto= | FileCheck %s -check-prefix=FLTOALL diff --git a/clang/test/Driver/baremetal.cpp b/clang/test/Driver/baremetal.cpp index f9d48e46e639a..7dd213ee56b47 100644 --- a/clang/test/Driver/baremetal.cpp +++ b/clang/test/Driver/baremetal.cpp @@ -92,3 +92,140 @@ // RUN: %clang -### -target arm-none-eabi -rtlib=libgcc -v %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=CHECK-RTLIB-GCC // CHECK-RTLIB-GCC: -lgcc + +// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target riscv64-unknown-elf \ +// RUN: -L some/directory/user/asked/for \ +// RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \ +// RUN: | FileCheck --check-prefix=CHECK-RV64 %s +// CHECK-RV64: "[[PREFIX_DIR:.*]]{{[/\\]+}}{{[^/^\\]+}}{{[/\\]+}}clang{{.*}}" "-cc1" "-triple" "riscv64-unknown-unknown-elf" +// CHECK-RV64-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-RV64-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-RV64-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1" +// CHECk-RV64-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}include" +// CHECK-RV64-SAME: "-x" "c++" "{{.*}}baremetal.cpp" +// CHECK-RV64-NEXT: "{{[^"]*}}ld{{(\.(lld|bfd|gold))?}}{{(\.exe)?}}" "{{.*}}.o" "-Bstatic" +// CHECK-RV64-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal" +// CHECK-RV64-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}lib" +// CHECK-RV64-SAME: "-Lsome{{[/\\]+}}directory{{[/\\]+}}user{{[/\\]+}}asked{{[/\\]+}}for" +// CHECK-RV64-SAME: "-lc" "-lm" "-lclang_rt.builtins-riscv64" +// CHECK-RV64-SAME: "-o" "{{.*}}.o" + +// RUN: %clangxx -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target riscv64-unknown-elf \ +// RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \ +// RUN: | FileCheck --check-prefix=CHECK-RV64-DEFAULTCXX %s +// CHECK-RV64-DEFAULTCXX: "{{[^"]*}}ld{{(\.(lld|bfd|gold))?}}{{(\.exe)?}}" "{{.*}}.o" "-Bstatic" +// CHECK-RV64-DEFAULTCXX-SAME: "-L{{[^"]*}}{{[/\\]+}}lib{{(64)?}}{{[/\\]+}}clang{{[/\\]+}}{{.*}}{{[/\\]+}}lib{{[/\\]+}}baremetal" +// CHECK-RV64-DEFAULTCXX-SAME: "-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf{{[/\\]+}}lib" +// CHECK-RV64-DEFAULTCXX-SAME: "-lc++" "-lc++abi" "-lunwind" +// CHECK-RV64-DEFAULTCXX-SAME: "-lc" "-lm" "-lclang_rt.builtins-riscv64" +// CHECK-RV64-DEFAULTCXX-SAME: "-o" "{{.*}}.o" + +// RUN: %clangxx -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target riscv64-unknown-elf \ +// RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \ +// RUN: -stdlib=libc++ \ +// RUN: | FileCheck --check-prefix=CHECK-RV64-LIBCXX %s +// CHECK-RV64-LIBCXX-NOT: "-internal-isystem" "{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}{{[^v].*}}" +// CHECK-RV64-LIBCXX: "-internal-isystem" "{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1" +// CHECK-RV64-LIBCXX: "{{[^"]*}}ld{{(\.(lld|bfd|gold))?}}{{(\.exe)?}}" "{{.*}}.o" "-Bstatic" +// CHECK-RV64-LIBCXX-SAME: "-L{{[^"]*}}{{[/\\]+}}lib{{(64)?}}{{[/\\]+}}clang{{[/\\]+}}{{.*}}{{[/\\]+}}lib{{[/\\]+}}baremetal" +// CHECK-RV64-LIBCXX-SAME: "-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf{{[/\\]+}}lib" +// CHECK-RV64-LIBCXX-SAME: "-lc++" "-lc++abi" "-lunwind" +// CHECK-RV64-LIBCXX-SAME: "-lc" "-lm" "-lclang_rt.builtins-riscv64" +// CHECK-RV64-LIBCXX-SAME: "-o" "{{.*}}.o" + +// RUN: %clangxx -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target riscv64-unknown-elf \ +// RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \ +// RUN: -stdlib=libstdc++ \ +// RUN: | FileCheck --check-prefix=CHECK-RV64-LIBSTDCXX %s +// CHECK-RV64-LIBSTDCXX-NOT: "-internal-isystem" "{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1" +// CHECK-RV64-LIBSTDCXX: "-internal-isystem" "{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}8.0.1" +// CHECK-RV64-LIBSTDCXX: "{{[^"]*}}ld{{(\.(lld|bfd|gold))?}}{{(\.exe)?}}" "{{.*}}.o" "-Bstatic" +// CHECK-RV64-LIBSTDCXX-SAME: "-L{{[^"]*}}{{[/\\]+}}lib{{(64)?}}{{[/\\]+}}clang{{[/\\]+}}{{.*}}{{[/\\]+}}lib{{[/\\]+}}baremetal" +// CHECK-RV64-LIBSTDCXX-SAME: "-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf{{[/\\]+}}lib" +// CHECK-RV64-LIBSTDCXX-SAME: "-lstdc++" "-lsupc++" "-lunwind" +// CHECK-RV64-LIBSTDCXX-SAME: "-lc" "-lm" "-lclang_rt.builtins-riscv64" +// CHECK-RV64-LIBSTDCXX-SAME: "-o" "{{.*}}.o" + +// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target riscv32-unknown-elf \ +// RUN: -L some/directory/user/asked/for \ +// RUN: --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf \ +// RUN: | FileCheck --check-prefix=CHECK-RV32 %s +// CHECK-RV32: "[[PREFIX_DIR:.*]]{{[/\\]+}}{{[^/^\\]+}}{{[/\\]+}}clang{{.*}}" "-cc1" "-triple" "riscv32-unknown-unknown-elf" +// CHECK-RV32-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-RV32-SAME: "-isysroot" "[[SYSROOT:[^"]*]]" +// CHECK-RV32-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1" +// CHECK-RV32-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}include" +// CHECK-RV32-SAME: "-x" "c++" "{{.*}}baremetal.cpp" +// CHECK-RV32-NEXT: "{{[^"]*}}ld{{(\.(lld|bfd|gold))?}}{{(\.exe)?}}" "{{.*}}.o" "-Bstatic" +// CHECK-RV32-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal" +// CHECK-RV32-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}lib" +// CHECK-RV32-SAME: "-Lsome{{[/\\]+}}directory{{[/\\]+}}user{{[/\\]+}}asked{{[/\\]+}}for" +// CHECK-RV32-SAME: "-lc" "-lm" "-lclang_rt.builtins-riscv32" +// CHECK-RV32-SAME: "-o" "{{.*}}.o" + +// RUN: %clangxx -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target riscv32-unknown-elf \ +// RUN: --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf \ +// RUN: | FileCheck --check-prefix=CHECK-RV32-DEFAULTCXX %s +// CHECK-RV32-DEFAULTCXX: "{{[^"]*}}ld{{(\.(lld|bfd|gold))?}}{{(\.exe)?}}" "{{.*}}.o" "-Bstatic" +// CHECK-RV32-DEFAULTCXX-SAME: "-L{{[^"]*}}{{[/\\]+}}lib{{(64)?}}{{[/\\]+}}clang{{[/\\]+}}{{.*}}{{[/\\]+}}lib{{[/\\]+}}baremetal" +// CHECK-RV32-DEFAULTCXX-SAME: "-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv32_tree{{[/\\]+}}riscv32-unknown-elf{{[/\\]+}}lib" +// CHECK-RV32-DEFAULTCXX-SAME: "-lc++" "-lc++abi" "-lunwind" +// CHECK-RV32-DEFAULTCXX-SAME: "-lc" "-lm" "-lclang_rt.builtins-riscv32" +// CHECK-RV32-DEFAULTCXX-SAME: "-o" "{{.*}}.o" + +// RUN: %clangxx -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target riscv32-unknown-elf \ +// RUN: --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf \ +// RUN: -stdlib=libc++ \ +// RUN: | FileCheck --check-prefix=CHECK-RV32-LIBCXX %s +// CHECK-RV32-LIBCXX-NOT: "-internal-isystem" "{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}{{[^v].*}}" +// CHECK-RV32-LIBCXX: "-internal-isystem" "{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1" +// CHECK-RV32-LIBCXX: "{{[^"]*}}ld{{(\.(lld|bfd|gold))?}}{{(\.exe)?}}" "{{.*}}.o" "-Bstatic" +// CHECK-RV32-LIBCXX-SAME: "-L{{[^"]*}}{{[/\\]+}}lib{{(64)?}}{{[/\\]+}}clang{{[/\\]+}}{{.*}}{{[/\\]+}}lib{{[/\\]+}}baremetal" +// CHECK-RV32-LIBCXX-SAME: "-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv32_tree{{[/\\]+}}riscv32-unknown-elf{{[/\\]+}}lib" +// CHECK-RV32-LIBCXX-SAME: "-lc++" "-lc++abi" "-lunwind" +// CHECK-RV32-LIBCXX-SAME: "-lc" "-lm" "-lclang_rt.builtins-riscv32" +// CHECK-RV32-LIBCXX-SAME: "-o" "{{.*}}.o" + +// RUN: %clangxx -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target riscv32-unknown-elf \ +// RUN: --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf \ +// RUN: -stdlib=libstdc++ \ +// RUN: | FileCheck --check-prefix=CHECK-RV32-LIBSTDCXX %s +// CHECK-RV32-LIBSTDCXX-NOT: "-internal-isystem" "{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1" +// CHECK-RV32-LIBSTDCXX: "-internal-isystem" "{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}8.0.1" +// CHECK-RV32-LIBSTDCXX: "{{[^"]*}}ld{{(\.(lld|bfd|gold))?}}{{(\.exe)?}}" "{{.*}}.o" "-Bstatic" +// CHECK-RV32-LIBSTDCXX-SAME: "-L{{[^"]*}}{{[/\\]+}}lib{{(64)?}}{{[/\\]+}}clang{{[/\\]+}}{{.*}}{{[/\\]+}}lib{{[/\\]+}}baremetal" +// CHECK-RV32-LIBSTDCXX-SAME: "-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv32_tree{{[/\\]+}}riscv32-unknown-elf{{[/\\]+}}lib" +// CHECK-RV32-LIBSTDCXX-SAME: "-lstdc++" "-lsupc++" "-lunwind" +// CHECK-RV32-LIBSTDCXX-SAME: "-lc" "-lm" "-lclang_rt.builtins-riscv32" +// CHECK-RV32-LIBSTDCXX-SAME: "-o" "{{.*}}.o" + +// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target riscv64-unknown-elf \ +// RUN: -nostdlibinc -nobuiltininc \ +// RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \ +// RUN: | FileCheck --check-prefix=CHECK-RV64-LIBINC %s + +// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target riscv64-unknown-elf \ +// RUN: -nostdinc \ +// RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \ +// RUN: | FileCheck --check-prefix=CHECK-RV64-LIBINC %s +// CHECK-RV64-LIBINC-NOT: "-internal-isystem" + +// RUN: %clangxx -no-canonical-prefixes %s -### -o %t.o 2>&1 \ +// RUN: -target riscv64-unknown-elf \ +// RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \ +// RUN: -nodefaultlibs \ +// RUN: | FileCheck --check-prefix=CHECK-RV64-NDL %s +// CHECK-RV64-NDL: "{{[^"]*}}ld{{(\.(lld|bfd|gold))?}}{{(\.exe)?}}" "{{.*}}.o" "-Bstatic" +// CHECK-RV64-NDL-SAME: "-L{{[^"]*}}{{[/\\]+}}lib{{(64)?}}{{[/\\]+}}clang{{[/\\]+}}{{.*}}{{[/\\]+}}lib{{[/\\]+}}baremetal" +// CHECK-RV64-NDL-SAME: "-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf{{[/\\]+}}lib" +// CHECK-RV64-NDL-SAME: "-o" "{{.*}}.o" diff --git a/clang/test/Driver/clang_f_opts.c b/clang/test/Driver/clang_f_opts.c index 27380413b7fe7..123ad7e2aa99f 100644 --- a/clang/test/Driver/clang_f_opts.c +++ b/clang/test/Driver/clang_f_opts.c @@ -541,6 +541,12 @@ // CHECK-NO-RECORD-GCC-SWITCHES-NOT: "-record-command-line" // CHECK-RECORD-GCC-SWITCHES-ERROR: error: unsupported option '-frecord-command-line' for target // Test when clang is in a path containing a space. +// The initial `rm` is a workaround for https://openradar.appspot.com/FB8914243 +// (Scenario: Run tests once, `clang` gets copied and run at new location and signature +// is cached at the new clang's inode, then clang is changed, tests run again, old signature +// is still cached with old clang's inode, so it won't execute this time. Removing the dir +// first guarantees a new inode without old cache entries.) +// RUN: rm -rf "%t.r/with spaces" // RUN: mkdir -p "%t.r/with spaces" // RUN: cp %clang "%t.r/with spaces/clang" // RUN: "%t.r/with spaces/clang" -### -S -target x86_64-unknown-linux -frecord-gcc-switches %s 2>&1 | FileCheck -check-prefix=CHECK-RECORD-GCC-SWITCHES-ESCAPED %s diff --git a/clang/test/Driver/darwin-ld-dedup.c b/clang/test/Driver/darwin-ld-dedup.c index a06ca7bebe57a..1d866f40291ab 100644 --- a/clang/test/Driver/darwin-ld-dedup.c +++ b/clang/test/Driver/darwin-ld-dedup.c @@ -29,7 +29,7 @@ // Do *not* add -no_deduplicate when no -O option is specified and this is just a link // (since we can't imply -O0) // RUN: rm -f %t.o %t.bin -// RUN: %clang -target x86_64-apple-darwin10 -c -o %t.o %s +// RUN: yaml2obj %S/Inputs/empty-x86_64-apple-darwin.yaml -o %t.o // RUN: %clang -target x86_64-apple-darwin10 %t.o -### -mlinker-version=262 \ // RUN: -o %t.bin 2>&1 | FileCheck -check-prefix=LINK_DEDUP %s // RUN: %clang -target x86_64-apple-darwin10 %t.o -### -mlinker-version=262 \ diff --git a/clang/test/Driver/darwin-ld-demangle-lld.c b/clang/test/Driver/darwin-ld-demangle-lld.c new file mode 100644 index 0000000000000..84facc8d1539b --- /dev/null +++ b/clang/test/Driver/darwin-ld-demangle-lld.c @@ -0,0 +1,12 @@ +// With -fuse-ld=lld, -demangle is always passed to the linker on Darwin. +// REQUIRES: shell + +// RUN: %clang --target=x86_64-apple-darwin -### \ +// RUN: -fuse-ld=lld -B%S/Inputs/lld -mlinker-version=0 %s 2>&1 \ +// RUN: | FileCheck %s +// FIXME: Remove ld.darwinnew once it's the default (and only) mach-o lld. +// RUN: %clang --target=x86_64-apple-darwin -### \ +// RUN: -fuse-ld=lld.darwinnew -B%S/Inputs/lld -mlinker-version=0 %s 2>&1 \ +// RUN: | FileCheck %s + +// CHECK: "-demangle" diff --git a/clang/test/Driver/darwin-ld-platform-version-ios.c b/clang/test/Driver/darwin-ld-platform-version-ios.c index 05698032a3267..d03e46b5776de 100644 --- a/clang/test/Driver/darwin-ld-platform-version-ios.c +++ b/clang/test/Driver/darwin-ld-platform-version-ios.c @@ -1,12 +1,28 @@ // RUN: touch %t.o -// RUN: %clang -target arm64-apple-ios12.3 -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=0 -### %t.o 2>&1 \ +// RUN: %clang -target arm64-apple-ios12.3 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=0 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=LINKER-OLD %s -// RUN: %clang -target arm64-apple-ios12.3 -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=400 -### %t.o 2>&1 \ +// RUN: %clang -target arm64-apple-ios12.3 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=400 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=LINKER-OLD %s -// RUN: %clang -target arm64-apple-ios12.3 -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=520 -### %t.o 2>&1 \ +// RUN: %clang -target arm64-apple-ios12.3 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=520 \ +// RUN: -### %t.o 2>&1 \ +// RUN: | FileCheck --check-prefix=LINKER-NEW %s +// RUN: %clang -target arm64-apple-ios12.3 -fuse-ld=lld.darwinnew \ +// RUN: -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=0 \ +// RUN: -### %t.o -B%S/Inputs/lld 2>&1 \ // RUN: | FileCheck --check-prefix=LINKER-NEW %s -// RUN: %clang -target x86_64-apple-ios13-simulator -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=520 -### %t.o 2>&1 \ +// RUN: %clang -target x86_64-apple-ios13-simulator -fuse-ld= \ +// RUN: -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=520 \ +// RUN: -### %t.o 2>&1 \ +// RUN: | FileCheck --check-prefix=SIMUL %s +// RUN: %clang -target x86_64-apple-ios13-simulator -fuse-ld=lld.darwinnew \ +// RUN: -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=0 \ +// RUN: -### %t.o -B%S/Inputs/lld 2>&1 \ // RUN: | FileCheck --check-prefix=SIMUL %s // LINKER-OLD: "-iphoneos_version_min" "12.3.0" diff --git a/clang/test/Driver/darwin-ld-platform-version-macos.c b/clang/test/Driver/darwin-ld-platform-version-macos.c index d3f49093ef868..1954deea7b93d 100644 --- a/clang/test/Driver/darwin-ld-platform-version-macos.c +++ b/clang/test/Driver/darwin-ld-platform-version-macos.c @@ -1,20 +1,42 @@ // RUN: touch %t.o -// RUN: %clang -target x86_64-apple-macos10.13 -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=0 -### %t.o 2>&1 \ +// RUN: %clang -target x86_64-apple-macos10.13 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=0 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=LINKER-OLD %s -// RUN: %clang -target x86_64-apple-macos10.13 -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=400 -### %t.o 2>&1 \ +// RUN: %clang -target x86_64-apple-macos10.13 -fuse-ld=lld.darwinnew \ +// RUN: -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=0 \ +// RUN: -### %t.o -B%S/Inputs/lld 2>&1 \ +// RUN: | FileCheck --check-prefix=LINKER-NEW %s +// RUN: %clang -target x86_64-apple-macos10.13 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=400 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=LINKER-OLD %s -// RUN: env SDKROOT=%S/Inputs/MacOSX10.14.sdk %clang -target x86_64-apple-macos10.13.0.1 -mlinker-version=520 -### %t.o 2>&1 \ +// RUN: env SDKROOT=%S/Inputs/MacOSX10.14.sdk %clang \ +// RUN: -target x86_64-apple-macos10.13.0.1 -mlinker-version=520 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=LINKER-NEW %s -// RUN: %clang -target arm64-apple-macos10.13 -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=520 -### %t.o 2>&1 \ +// RUN: %clang -target arm64-apple-macos10.13 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=400 \ +// RUN: -### %t.o 2>&1 \ +// RUN: | FileCheck --check-prefix=ARM64_OLD %s +// RUN: %clang -target arm64-apple-macos10.13 -fuse-ld=lld.darwinnew \ +// RUN: -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=400 \ +// RUN: -### %t.o -B%S/Inputs/lld 2>&1 \ // RUN: | FileCheck --check-prefix=ARM64_NEW %s -// RUN: %clang -target arm64-apple-darwin19 -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=520 -### %t.o 2>&1 \ +// RUN: %clang -target arm64-apple-macos10.13 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=520 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=ARM64_NEW %s -// RUN: %clang -target arm64-apple-macos11.1 -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=520 -### %t.o 2>&1 \ +// RUN: %clang -target arm64-apple-darwin19 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=520 \ +// RUN: -### %t.o 2>&1 \ +// RUN: | FileCheck --check-prefix=ARM64_NEW %s +// RUN: %clang -target arm64-apple-macos11.1 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=520 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=ARM64_NEW_1 %s -// RUN: %clang -target arm64-apple-macos10.13 -isysroot %S/Inputs/MacOSX10.14.sdk -mlinker-version=400 -### %t.o 2>&1 \ -// RUN: | FileCheck --check-prefix=ARM64_OLD %s // LINKER-OLD: "-macosx_version_min" "10.13.0" // LINKER-NEW: "-platform_version" "macos" "10.13.0" "10.14" @@ -23,6 +45,7 @@ // ARM64_NEW_1: "-platform_version" "macos" "11.1.0" "10.14" // ARM64_OLD: "-macosx_version_min" "11.0.0" -// RUN: %clang -target x86_64-apple-macos10.13 -mlinker-version=520 -### %t.o 2>&1 \ +// RUN: %clang -target x86_64-apple-macos10.13 -mlinker-version=520 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=NOSDK %s // NOSDK: "-platform_version" "macos" "10.13.0" "0.0.0" diff --git a/clang/test/Driver/darwin-ld-platform-version-tvos.c b/clang/test/Driver/darwin-ld-platform-version-tvos.c index 39a2020cbb202..beaa46b32f6f2 100644 --- a/clang/test/Driver/darwin-ld-platform-version-tvos.c +++ b/clang/test/Driver/darwin-ld-platform-version-tvos.c @@ -1,12 +1,24 @@ // RUN: touch %t.o -// RUN: %clang -target arm64-apple-tvos12.3 -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=0 -### %t.o 2>&1 \ +// RUN: %clang -target arm64-apple-tvos12.3 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=0 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=LINKER-OLD %s -// RUN: %clang -target arm64-apple-tvos12.3 -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=400 -### %t.o 2>&1 \ +// RUN: %clang -target arm64-apple-tvos12.3 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=400 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=LINKER-OLD %s -// RUN: %clang -target arm64-apple-tvos12.3 -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=520 -### %t.o 2>&1 \ +// RUN: %clang -target arm64-apple-tvos12.3 -fuse-ld=lld.darwinnew \ +// RUN: -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=0 \ +// RUN: -### %t.o -B%S/Inputs/lld 2>&1 \ // RUN: | FileCheck --check-prefix=LINKER-NEW %s -// RUN: %clang -target x86_64-apple-tvos13-simulator -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=520 -### %t.o 2>&1 \ +// RUN: %clang -target arm64-apple-tvos12.3 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=520 \ +// RUN: -### %t.o 2>&1 \ +// RUN: | FileCheck --check-prefix=LINKER-NEW %s +// RUN: %clang -target x86_64-apple-tvos13-simulator -fuse-ld= \ +// RUN: -isysroot %S/Inputs/iPhoneOS13.0.sdk -mlinker-version=520 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=SIMUL %s // LINKER-OLD: "-tvos_version_min" "12.3.0" diff --git a/clang/test/Driver/darwin-ld-platform-version-watchos.c b/clang/test/Driver/darwin-ld-platform-version-watchos.c index db565ddbb5927..ab03fefce6964 100644 --- a/clang/test/Driver/darwin-ld-platform-version-watchos.c +++ b/clang/test/Driver/darwin-ld-platform-version-watchos.c @@ -1,12 +1,24 @@ // RUN: touch %t.o -// RUN: %clang -target arm64_32-apple-watchos5.2 -isysroot %S/Inputs/WatchOS6.0.sdk -mlinker-version=0 -### %t.o 2>&1 \ +// RUN: %clang -target arm64_32-apple-watchos5.2 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/WatchOS6.0.sdk -mlinker-version=0 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=LINKER-OLD %s -// RUN: %clang -target arm64_32-apple-watchos5.2 -isysroot %S/Inputs/WatchOS6.0.sdk -mlinker-version=400 -### %t.o 2>&1 \ +// RUN: %clang -target arm64_32-apple-watchos5.2 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/WatchOS6.0.sdk -mlinker-version=400 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=LINKER-OLD %s -// RUN: %clang -target arm64_32-apple-watchos5.2 -isysroot %S/Inputs/WatchOS6.0.sdk -mlinker-version=520 -### %t.o 2>&1 \ +// RUN: %clang -target arm64_32-apple-watchos5.2 -fuse-ld=lld.darwinnew \ +// RUN: -isysroot %S/Inputs/WatchOS6.0.sdk -mlinker-version=0 \ +// RUN: -### %t.o -B%S/Inputs/lld 2>&1 \ // RUN: | FileCheck --check-prefix=LINKER-NEW %s -// RUN: %clang -target x86_64-apple-watchos6-simulator -isysroot %S/Inputs/WatchOS6.0.sdk -mlinker-version=520 -### %t.o 2>&1 \ +// RUN: %clang -target arm64_32-apple-watchos5.2 -fuse-ld= \ +// RUN: -isysroot %S/Inputs/WatchOS6.0.sdk -mlinker-version=520 \ +// RUN: -### %t.o 2>&1 \ +// RUN: | FileCheck --check-prefix=LINKER-NEW %s +// RUN: %clang -target x86_64-apple-watchos6-simulator -fuse-ld= \ +// RUN: -isysroot %S/Inputs/WatchOS6.0.sdk -mlinker-version=520 \ +// RUN: -### %t.o 2>&1 \ // RUN: | FileCheck --check-prefix=SIMUL %s // LINKER-OLD: "-watchos_version_min" "5.2.0" diff --git a/clang/test/Driver/darwin-ld.c b/clang/test/Driver/darwin-ld.c index 82cd36d59f80d..15e5d100afcbc 100644 --- a/clang/test/Driver/darwin-ld.c +++ b/clang/test/Driver/darwin-ld.c @@ -11,9 +11,9 @@ // Check linker changes that came with new linkedit format. // RUN: touch %t.o -// RUN: %clang -target i386-apple-darwin9 -mlinker-version=400 -### -arch armv6 -miphoneos-version-min=3.0 %t.o 2> %t.log -// RUN: %clang -target i386-apple-darwin9 -mlinker-version=400 -### -arch armv6 -miphoneos-version-min=3.0 -dynamiclib %t.o 2>> %t.log -// RUN: %clang -target i386-apple-darwin9 -mlinker-version=400 -### -arch armv6 -miphoneos-version-min=3.0 -bundle %t.o 2>> %t.log +// RUN: %clang -target i386-apple-darwin9 -fuse-ld= -mlinker-version=400 -### -arch armv6 -miphoneos-version-min=3.0 %t.o 2> %t.log +// RUN: %clang -target i386-apple-darwin9 -fuse-ld= -mlinker-version=400 -### -arch armv6 -miphoneos-version-min=3.0 -dynamiclib %t.o 2>> %t.log +// RUN: %clang -target i386-apple-darwin9 -fuse-ld= -mlinker-version=400 -### -arch armv6 -miphoneos-version-min=3.0 -bundle %t.o 2>> %t.log // RUN: FileCheck -check-prefix=LINK_IPHONE_3_0 %s < %t.log // LINK_IPHONE_3_0: {{ld(.exe)?"}} @@ -30,9 +30,9 @@ // LINK_IPHONE_3_0: -lbundle1.o // LINK_IPHONE_3_0: -lSystem -// RUN: %clang -target i386-apple-darwin9 -mlinker-version=400 -### -arch armv7 -miphoneos-version-min=3.1 %t.o 2> %t.log -// RUN: %clang -target i386-apple-darwin9 -mlinker-version=400 -### -arch armv7 -miphoneos-version-min=3.1 -dynamiclib %t.o 2>> %t.log -// RUN: %clang -target i386-apple-darwin9 -mlinker-version=400 -### -arch armv7 -miphoneos-version-min=3.1 -bundle %t.o 2>> %t.log +// RUN: %clang -target i386-apple-darwin9 -fuse-ld= -mlinker-version=400 -### -arch armv7 -miphoneos-version-min=3.1 %t.o 2> %t.log +// RUN: %clang -target i386-apple-darwin9 -fuse-ld= -mlinker-version=400 -### -arch armv7 -miphoneos-version-min=3.1 -dynamiclib %t.o 2>> %t.log +// RUN: %clang -target i386-apple-darwin9 -fuse-ld= -mlinker-version=400 -### -arch armv7 -miphoneos-version-min=3.1 -bundle %t.o 2>> %t.log // RUN: FileCheck -check-prefix=LINK_IPHONE_3_1 %s < %t.log // LINK_IPHONE_3_1: {{ld(.exe)?"}} @@ -49,9 +49,9 @@ // LINK_IPHONE_3_1-NOT: -lbundle1.o // LINK_IPHONE_3_1: -lSystem -// RUN: %clang -target i386-apple-darwin9 -mlinker-version=400 -### -arch i386 -mios-simulator-version-min=3.0 %t.o 2> %t.log -// RUN: %clang -target i386-apple-darwin9 -mlinker-version=400 -### -arch i386 -mios-simulator-version-min=3.0 -dynamiclib %t.o 2>> %t.log -// RUN: %clang -target i386-apple-darwin9 -mlinker-version=400 -### -arch i386 -mios-simulator-version-min=3.0 -bundle %t.o 2>> %t.log +// RUN: %clang -target i386-apple-darwin9 -fuse-ld= -mlinker-version=400 -### -arch i386 -mios-simulator-version-min=3.0 %t.o 2> %t.log +// RUN: %clang -target i386-apple-darwin9 -fuse-ld= -mlinker-version=400 -### -arch i386 -mios-simulator-version-min=3.0 -dynamiclib %t.o 2>> %t.log +// RUN: %clang -target i386-apple-darwin9 -fuse-ld= -mlinker-version=400 -### -arch i386 -mios-simulator-version-min=3.0 -bundle %t.o 2>> %t.log // RUN: FileCheck -check-prefix=LINK_IOSSIM_3_0 %s < %t.log // LINK_IOSSIM_3_0: {{ld(.exe)?"}} @@ -80,14 +80,14 @@ // LINK_EXPLICIT_NO_PIE: "-no_pie" // RUN: %clang -target x86_64-apple-darwin10 -### %t.o \ -// RUN: -mlinker-version=100 2> %t.log +// RUN: -fuse-ld= -mlinker-version=100 2> %t.log // RUN: FileCheck -check-prefix=LINK_NEWER_DEMANGLE %s < %t.log // // LINK_NEWER_DEMANGLE: {{ld(.exe)?"}} // LINK_NEWER_DEMANGLE: "-demangle" // RUN: %clang -target x86_64-apple-darwin10 -### %t.o \ -// RUN: -mlinker-version=100 -Wl,--no-demangle 2> %t.log +// RUN: -fuse-ld= -mlinker-version=100 -Wl,--no-demangle 2> %t.log // RUN: FileCheck -check-prefix=LINK_NEWER_NODEMANGLE %s < %t.log // // LINK_NEWER_NODEMANGLE: {{ld(.exe)?"}} @@ -95,7 +95,7 @@ // LINK_NEWER_NODEMANGLE: "-lSystem" // RUN: %clang -target x86_64-apple-darwin10 -### %t.o \ -// RUN: -mlinker-version=95 2> %t.log +// RUN: -fuse-ld= -mlinker-version=95 2> %t.log // RUN: FileCheck -check-prefix=LINK_OLDER_NODEMANGLE %s < %t.log // // LINK_OLDER_NODEMANGLE: {{ld(.exe)?"}} @@ -103,7 +103,7 @@ // LINK_OLDER_NODEMANGLE: "-lSystem" // RUN: %clang -target x86_64-apple-darwin10 -### %s \ -// RUN: -mlinker-version=117 -flto 2> %t.log +// RUN: -fuse-ld= -mlinker-version=117 -flto 2> %t.log // RUN: cat %t.log // RUN: FileCheck -check-prefix=LINK_OBJECT_LTO_PATH %s < %t.log // @@ -132,8 +132,8 @@ // LINK_LAZY_LIBRARY: {{ld(.exe)?"}} // LINK_LAZY_LIBRARY: "-lazy_library" "Library" -// RUN: %clang -target x86_64-apple-darwin10 -mlinker-version=400 -### %t.o 2> %t.log -// RUN: %clang -target x86_64-apple-macosx10.7 -mlinker-version=400 -### %t.o 2>> %t.log +// RUN: %clang -target x86_64-apple-darwin10 -fuse-ld= -mlinker-version=400 -### %t.o 2> %t.log +// RUN: %clang -target x86_64-apple-macosx10.7 -fuse-ld= -mlinker-version=400 -### %t.o 2>> %t.log // RUN: FileCheck -check-prefix=LINK_VERSION_MIN %s < %t.log // LINK_VERSION_MIN: {{ld(.exe)?"}} // LINK_VERSION_MIN: "-macosx_version_min" "10.6.0" @@ -158,7 +158,7 @@ // LINK_IOSSIM_PROFILE: libclang_rt.profile_iossim.a // LINK_IOSSIM_PROFILE: libclang_rt.iossim.a -// RUN: %clang -target arm64-apple-tvos8.3 -mlinker-version=400 -mtvos-version-min=8.3 -resource-dir=%S/Inputs/resource_dir -### %t.o 2> %t.log +// RUN: %clang -target arm64-apple-tvos8.3 -fuse-ld= -mlinker-version=400 -mtvos-version-min=8.3 -resource-dir=%S/Inputs/resource_dir -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=LINK_TVOS_ARM64 %s < %t.log // LINK_TVOS_ARM64: {{ld(.exe)?"}} // LINK_TVOS_ARM64: -tvos_version_min @@ -166,19 +166,19 @@ // LINK_TVOS_ARM64-NOT: lgcc_s.1 // LINK_TVOS_ARM64: libclang_rt.tvos.a -// RUN: %clang -target arm64-apple-tvos8.3 -mlinker-version=400 -mtvos-version-min=8.3 -fprofile-instr-generate -resource-dir=%S/Inputs/resource_dir -### %t.o 2> %t.log +// RUN: %clang -target arm64-apple-tvos8.3 -fuse-ld= -mlinker-version=400 -mtvos-version-min=8.3 -fprofile-instr-generate -resource-dir=%S/Inputs/resource_dir -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=LINK_TVOS_PROFILE %s < %t.log // LINK_TVOS_PROFILE: {{ld(.exe)?"}} // LINK_TVOS_PROFILE: libclang_rt.profile_tvos.a // LINK_TVOS_PROFILE: libclang_rt.tvos.a -// RUN: %clang -target arm64-apple-tvos8.3 -mlinker-version=400 -mtvos-version-min=8.3 -resource-dir=%S/Inputs/resource_dir -### %t.o -lcc_kext 2> %t.log +// RUN: %clang -target arm64-apple-tvos8.3 -fuse-ld= -mlinker-version=400 -mtvos-version-min=8.3 -resource-dir=%S/Inputs/resource_dir -### %t.o -lcc_kext 2> %t.log // RUN: FileCheck -check-prefix=LINK_TVOS_KEXT %s < %t.log // LINK_TVOS_KEXT: {{ld(.exe)?"}} // LINK_TVOS_KEXT: libclang_rt.cc_kext_tvos.a // LINK_TVOS_KEXT: libclang_rt.tvos.a -// RUN: %clang -target armv7k-apple-watchos2.0 -mlinker-version=400 -mwatchos-version-min=2.0 -resource-dir=%S/Inputs/resource_dir -### %t.o 2> %t.log +// RUN: %clang -target armv7k-apple-watchos2.0 -fuse-ld= -mlinker-version=400 -mwatchos-version-min=2.0 -resource-dir=%S/Inputs/resource_dir -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=LINK_WATCHOS_ARM %s < %t.log // LINK_WATCHOS_ARM: {{ld(.exe)?"}} // LINK_WATCHOS_ARM: -watchos_version_min @@ -186,13 +186,13 @@ // LINK_WATCHOS_ARM-NOT: lgcc_s.1 // LINK_WATCHOS_ARM: libclang_rt.watchos.a -// RUN: %clang -target armv7k-apple-watchos2.0 -mlinker-version=400 -mwatchos-version-min=2.0 -resource-dir=%S/Inputs/resource_dir -fprofile-instr-generate -### %t.o 2> %t.log +// RUN: %clang -target armv7k-apple-watchos2.0 -fuse-ld= -mlinker-version=400 -mwatchos-version-min=2.0 -resource-dir=%S/Inputs/resource_dir -fprofile-instr-generate -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=LINK_WATCHOS_PROFILE %s < %t.log // LINK_WATCHOS_PROFILE: {{ld(.exe)?"}} // LINK_WATCHOS_PROFILE: libclang_rt.profile_watchos.a // LINK_WATCHOS_PROFILE: libclang_rt.watchos.a -// RUN: %clang -target armv7k-apple-watchos2.0 -mlinker-version=400 -mwatchos-version-min=2.0 -resource-dir=%S/Inputs/resource_dir -### %t.o -lcc_kext 2> %t.log +// RUN: %clang -target armv7k-apple-watchos2.0 -fuse-ld= -mlinker-version=400 -mwatchos-version-min=2.0 -resource-dir=%S/Inputs/resource_dir -### %t.o -lcc_kext 2> %t.log // RUN: FileCheck -check-prefix=LINK_WATCHOS_KEXT %s < %t.log // LINK_WATCHOS_KEXT: {{ld(.exe)?"}} // LINK_WATCHOS_KEXT: libclang_rt.cc_kext_watchos.a @@ -221,13 +221,13 @@ // LINK_NO_IOS_ARM64_LIBGCC_S-NOT: lgcc_s.1 // RUN: %clang -target x86_64-apple-darwin12 -rdynamic -### %t.o \ -// RUN: -mlinker-version=100 2> %t.log +// RUN: -fuse-ld= -mlinker-version=100 2> %t.log // RUN: FileCheck -check-prefix=LINK_NO_EXPORT_DYNAMIC %s < %t.log // LINK_NO_EXPORT_DYNAMIC: {{ld(.exe)?"}} // LINK_NO_EXPORT_DYNAMIC-NOT: "-export_dynamic" // RUN: %clang -target x86_64-apple-darwin12 -rdynamic -### %t.o \ -// RUN: -mlinker-version=137 2> %t.log +// RUN: -fuse-ld= -mlinker-version=137 2> %t.log // RUN: FileCheck -check-prefix=LINK_EXPORT_DYNAMIC %s < %t.log // LINK_EXPORT_DYNAMIC: {{ld(.exe)?"}} // LINK_EXPORT_DYNAMIC: "-export_dynamic" @@ -251,30 +251,30 @@ // IPHONEOS_DEPLOYMENT_TARGET variable is used instead of the command-line // deployment target options. // RUN: env IPHONEOS_DEPLOYMENT_TARGET=7.0 \ -// RUN: %clang -target arm64-apple-darwin -mlinker-version=400 -### %t.o 2> %t.log +// RUN: %clang -target arm64-apple-darwin -fuse-ld= -mlinker-version=400 -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=LINK_IPHONEOS_VERSION_MIN %s < %t.log // RUN: env IPHONEOS_DEPLOYMENT_TARGET=7.0 \ -// RUN: %clang -target i386-apple-darwin -mlinker-version=400 -### %t.o 2> %t.log +// RUN: %clang -target i386-apple-darwin -fuse-ld= -mlinker-version=400 -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=LINK_IOS_SIMULATOR_VERSION_MIN %s < %t.log // LINK_IPHONEOS_VERSION_MIN: -iphoneos_version_min // LINK_IOS_SIMULATOR_VERSION_MIN: -ios_simulator_version_min // Ditto for tvOS.... // RUN: env TVOS_DEPLOYMENT_TARGET=7.0 \ -// RUN: %clang -target armv7-apple-darwin -mlinker-version=400 -### %t.o 2> %t.log +// RUN: %clang -target armv7-apple-darwin -fuse-ld= -mlinker-version=400 -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=LINK_TVOS_VERSION_MIN %s < %t.log // RUN: env TVOS_DEPLOYMENT_TARGET=7.0 \ -// RUN: %clang -target x86_64-apple-darwin -mlinker-version=400 -### %t.o 2> %t.log +// RUN: %clang -target x86_64-apple-darwin -fuse-ld= -mlinker-version=400 -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=LINK_TVOS_SIMULATOR_VERSION_MIN %s < %t.log // LINK_TVOS_VERSION_MIN: -tvos_version_min // LINK_TVOS_SIMULATOR_VERSION_MIN: -tvos_simulator_version_min // ...and for watchOS. // RUN: env WATCHOS_DEPLOYMENT_TARGET=2.0 \ -// RUN: %clang -target armv7k-apple-darwin -mlinker-version=400 -### %t.o 2> %t.log +// RUN: %clang -target armv7k-apple-darwin -fuse-ld= -mlinker-version=400 -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=LINK_WATCHOS_VERSION_MIN %s < %t.log // RUN: env WATCHOS_DEPLOYMENT_TARGET=2.0 \ -// RUN: %clang -target i386-apple-darwin -mlinker-version=400 -### %t.o 2> %t.log +// RUN: %clang -target i386-apple-darwin -fuse-ld= -mlinker-version=400 -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=LINK_WATCHOS_SIMULATOR_VERSION_MIN %s < %t.log // LINK_WATCHOS_VERSION_MIN: -watchos_version_min // LINK_WATCHOS_SIMULATOR_VERSION_MIN: -watchos_simulator_version_min @@ -287,19 +287,19 @@ // Check ld64 accepts up to 5 digits with no extra characters // RUN: %clang -target x86_64-apple-darwin12 %s -### -o %t \ -// RUN: -mlinker-version=133.3 2> %t.log +// RUN: -fuse-ld= -mlinker-version=133.3 2> %t.log // RUN: %clang -target x86_64-apple-darwin12 %s -### -o %t \ -// RUN: -mlinker-version=133.3.0 2>> %t.log +// RUN: -fuse-ld= -mlinker-version=133.3.0 2>> %t.log // RUN: %clang -target x86_64-apple-darwin12 %s -### -o %t \ -// RUN: -mlinker-version=133.3.0.1 2>> %t.log +// RUN: -fuse-ld= -mlinker-version=133.3.0.1 2>> %t.log // RUN: %clang -target x86_64-apple-darwin12 %s -### -o %t \ -// RUN: -mlinker-version=133.3.0.1.2 2>> %t.log +// RUN: -fuse-ld= -mlinker-version=133.3.0.1.2 2>> %t.log // RUN: %clang -target x86_64-apple-darwin12 %s -### -o %t \ -// RUN: -mlinker-version=133.3.0.1.2.6 2>> %t.log +// RUN: -fuse-ld= -mlinker-version=133.3.0.1.2.6 2>> %t.log // RUN: %clang -target x86_64-apple-darwin12 %s -### -o %t \ -// RUN: -mlinker-version=133.3.0.1.a 2>> %t.log +// RUN: -fuse-ld= -mlinker-version=133.3.0.1.a 2>> %t.log // RUN: %clang -target x86_64-apple-darwin12 %s -### -o %t \ -// RUN: -mlinker-version=133.3.0.1a 2>> %t.log +// RUN: -fuse-ld= -mlinker-version=133.3.0.1a 2>> %t.log // RUN: FileCheck -check-prefix=LINK_VERSION_DIGITS %s < %t.log // LINK_VERSION_DIGITS-NOT: invalid version number in '-mlinker-version=133.3' // LINK_VERSION_DIGITS-NOT: invalid version number in '-mlinker-version=133.3.0' diff --git a/clang/test/Driver/darwin-sdk-version.c b/clang/test/Driver/darwin-sdk-version.c index 9c1eec0ee43ff..e95103b7cfb58 100644 --- a/clang/test/Driver/darwin-sdk-version.c +++ b/clang/test/Driver/darwin-sdk-version.c @@ -30,8 +30,8 @@ // RUN: | FileCheck --check-prefixes=NO_VERSION,ERROR %s // CHECK: -target-sdk-version=10.14 -// INFER_SDK_VERSION: "-triple" "x86_64-apple-macosx10.10.0" +// INFER_SDK_VERSION: "-triple" "{{arm64|x86_64}}-apple-macosx10.10.0" // INFER_SDK_VERSION-SAME: -target-sdk-version=10.10 -// INFER_DEPLOYMENT_TARGET_VERSION: "-triple" "x86_64-apple-macosx10.8.0" +// INFER_DEPLOYMENT_TARGET_VERSION: "-triple" "{{arm64|x86_64}}-apple-macosx10.8.0" // NO_VERSION-NOT: target-sdk-version // ERROR: warning: SDK settings were ignored as 'SDKSettings.json' could not be parsed diff --git a/clang/test/Driver/linux-header-search.cpp b/clang/test/Driver/linux-header-search.cpp index 03502423c15a7..077e6ed9b4a95 100644 --- a/clang/test/Driver/linux-header-search.cpp +++ b/clang/test/Driver/linux-header-search.cpp @@ -257,6 +257,38 @@ // CHECK-DEBIAN-PPC64: "-internal-externc-isystem" "[[SYSROOT]]/usr/include/powerpc64-linux-gnu" // CHECK-DEBIAN-PPC64: "-internal-externc-isystem" "[[SYSROOT]]/include" // CHECK-DEBIAN-PPC64: "-internal-externc-isystem" "[[SYSROOT]]/usr/include" +// RUN: %clang -no-canonical-prefixes %s -### -fsyntax-only 2>&1 \ +// RUN: -target sparc-linux-gnu -stdlib=libstdc++ \ +// RUN: --sysroot=%S/Inputs/debian_multiarch_tree \ +// RUN: --gcc-toolchain="" \ +// RUN: | FileCheck --check-prefix=CHECK-DEBIAN-SPARC %s +// CHECK-DEBIAN-SPARC: "{{[^"]*}}clang{{[^"]*}}" "-cc1" +// CHECK-DEBIAN-SPARC-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-DEBIAN-SPARC-SAME: "-isysroot" "[[SYSROOT:[^"]+]]" +// CHECK-DEBIAN-SPARC-SAME: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.5/../../../../include/c++/4.5" +// CHECK-DEBIAN-SPARC-SAME: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.5/../../../../include/c++/4.5/sparc-linux-gnu" +// CHECK-DEBIAN-SPARC-SAME: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.5/../../../../include/c++/4.5/backward" +// CHECK-DEBIAN-SPARC-SAME: "-internal-isystem" "[[SYSROOT]]/usr/local/include" +// CHECK-DEBIAN-SPARC-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{/|\\\\}}include" +// CHECK-DEBIAN-SPARC-SAME: "-internal-externc-isystem" "[[SYSROOT]]/usr/include/sparc-linux-gnu" +// CHECK-DEBIAN-SPARC-SAME: "-internal-externc-isystem" "[[SYSROOT]]/include" +// CHECK-DEBIAN-SPARC-SAME: "-internal-externc-isystem" "[[SYSROOT]]/usr/include" +// RUN: %clang -no-canonical-prefixes %s -### -fsyntax-only 2>&1 \ +// RUN: -target sparc64-linux-gnu -stdlib=libstdc++ \ +// RUN: --sysroot=%S/Inputs/debian_multiarch_tree \ +// RUN: --gcc-toolchain="" \ +// RUN: | FileCheck --check-prefix=CHECK-DEBIAN-SPARC64 %s +// CHECK-DEBIAN-SPARC64: "{{[^"]*}}clang{{[^"]*}}" "-cc1" +// CHECK-DEBIAN-SPARC64-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" +// CHECK-DEBIAN-SPARC64-SAME: "-isysroot" "[[SYSROOT:[^"]+]]" +// CHECK-DEBIAN-SPARC64-SAME: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.5/../../../../include/c++/4.5" +// CHECK-DEBIAN-SPARC64-SAME: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.5/../../../../include/c++/4.5/sparc64-linux-gnu" +// CHECK-DEBIAN-SPARC64-SAME: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.5/../../../../include/c++/4.5/backward" +// CHECK-DEBIAN-SPARC64-SAME: "-internal-isystem" "[[SYSROOT]]/usr/local/include" +// CHECK-DEBIAN-SPARC64-SAME: "-internal-isystem" "[[RESOURCE_DIR]]{{/|\\\\}}include" +// CHECK-DEBIAN-SPARC64-SAME: "-internal-externc-isystem" "[[SYSROOT]]/usr/include/sparc64-linux-gnu" +// CHECK-DEBIAN-SPARC64-SAME: "-internal-externc-isystem" "[[SYSROOT]]/include" +// CHECK-DEBIAN-SPARC64-SAME: "-internal-externc-isystem" "[[SYSROOT]]/usr/include" // // Test Gentoo's weirdness both before and after they changed it in their GCC // 4.6.4 release. @@ -437,62 +469,6 @@ // CHECK-MIPS64EL-GNUABI: "-internal-externc-isystem" "[[SYSROOT]]/include" // CHECK-MIPS64EL-GNUABI: "-internal-externc-isystem" "[[SYSROOT]]/usr/include" -// Check header search on Debian 8 / Sparc -// RUN: %clang -no-canonical-prefixes %s -### -fsyntax-only 2>&1 \ -// RUN: -target sparc-unknown-linux-gnu -stdlib=libstdc++ \ -// RUN: --sysroot=%S/Inputs/debian_8_sparc_multilib_tree \ -// RUN: --gcc-toolchain="" \ -// RUN: | FileCheck --check-prefix=CHECK-DEBIAN-SPARC32 %s -// CHECK-DEBIAN-SPARC32: "{{[^"]*}}clang{{[^"]*}}" "-cc1" -// CHECK-DEBIAN-SPARC32: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" -// CHECK-DEBIAN-SPARC32: "-isysroot" "[[SYSROOT:[^"]+]]" -// CHECK-DEBIAN-SPARC32: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../../include/c++/4.9" -// CHECK-DEBIAN-SPARC32: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../../include/sparc-linux-gnu/c++/4.9" -// CHECK-DEBIAN-SPARC32: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../../include/c++/4.9/backward" -// CHECK-DEBIAN-SPARC32: "-internal-isystem" "[[SYSROOT]]/usr/local/include" -// CHECK-DEBIAN-SPARC32: "-internal-isystem" "[[RESOURCE_DIR]]{{/|\\\\}}include" -// CHECK-DEBIAN-SPARC32: "-internal-externc-isystem" "[[SYSROOT]]/usr/include/sparc-linux-gnu" -// CHECK-DEBIAN-SPARC32: "-internal-externc-isystem" "[[SYSROOT]]/include" -// CHECK-DEBIAN-SPARC32: "-internal-externc-isystem" "[[SYSROOT]]/usr/include" - -// Check header search on Debian 8 / Sparc, with the oldstyle multilib packages -// RUN: %clang -no-canonical-prefixes -m64 %s -### -fsyntax-only 2>&1 \ -// RUN: -target sparc-unknown-linux-gnu -stdlib=libstdc++ \ -// RUN: --sysroot=%S/Inputs/debian_8_sparc_multilib_tree \ -// RUN: --gcc-toolchain="" \ -// RUN: | FileCheck --check-prefix=CHECK-DEBIAN-SPARC32-LIB64 %s -// CHECK-DEBIAN-SPARC32-LIB64: "{{[^"]*}}clang{{[^"]*}}" "-cc1" -// CHECK-DEBIAN-SPARC32-LIB64: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" -// CHECK-DEBIAN-SPARC32-LIB64: "-isysroot" "[[SYSROOT:[^"]+]]" -// CHECK-DEBIAN-SPARC32-LIB64: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../../include/c++/4.9" -// CHECK-DEBIAN-SPARC32-LIB64: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../../include/sparc-linux-gnu/c++/4.9/64" -// CHECK-DEBIAN-SPARC32-LIB64: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../../include/c++/4.9/backward" -// CHECK-DEBIAN-SPARC32-LIB64: "-internal-isystem" "[[SYSROOT]]/usr/local/include" -// CHECK-DEBIAN-SPARC32-LIB64: "-internal-isystem" "[[RESOURCE_DIR]]{{/|\\\\}}include" -/* TODO: GCC 4.9 includes the following dir in its search path, which - seems questionable. Clang doesn't. Not sure if clang should be - doing that too. */ -// CHECK-DEBIAN-SPARC32-LIB64-todo: "-internal-externc-isystem" "[[SYSROOT]]/usr/include/sparc-linux-gnu" -// CHECK-DEBIAN-SPARC32-LIB64: "-internal-externc-isystem" "[[SYSROOT]]/include" -// CHECK-DEBIAN-SPARC32-LIB64: "-internal-externc-isystem" "[[SYSROOT]]/usr/include" - -// Check header search on Debian 8 / Sparc64 -// RUN: %clang -no-canonical-prefixes %s -### -fsyntax-only 2>&1 \ -// RUN: -target sparc64-unknown-linux-gnu -stdlib=libstdc++ \ -// RUN: --sysroot=%S/Inputs/debian_8_sparc64_tree \ -// RUN: --gcc-toolchain="" \ -// RUN: | FileCheck --check-prefix=CHECK-DEBIAN-SPARC64 %s -// CHECK-DEBIAN-SPARC64: "{{[^"]*}}clang{{[^"]*}}" "-cc1" -// CHECK-DEBIAN-SPARC64: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]" -// CHECK-DEBIAN-SPARC64: "-isysroot" "[[SYSROOT:[^"]+]]" -// CHECK-DEBIAN-SPARC64: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.9/../../../../include/c++/4.9" -// CHECK-DEBIAN-SPARC64: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.9/../../../../include/sparc64-linux-gnu/c++/4.9" -// CHECK-DEBIAN-SPARC64: "-internal-isystem" "[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.9/../../../../include/c++/4.9/backward" -// CHECK-DEBIAN-SPARC64: "-internal-isystem" "[[SYSROOT]]/usr/local/include" -// CHECK-DEBIAN-SPARC64: "-internal-isystem" "[[RESOURCE_DIR]]{{/|\\\\}}include" -// CHECK-DEBIAN-SPARC64: "-internal-externc-isystem" "[[SYSROOT]]/usr/include/sparc64-linux-gnu" -// CHECK-DEBIAN-SPARC64: "-internal-externc-isystem" "[[SYSROOT]]/include" -// CHECK-DEBIAN-SPARC64: "-internal-externc-isystem" "[[SYSROOT]]/usr/include" // Check header search on OpenEmbedded ARM. // RUN: %clang -no-canonical-prefixes %s -### -fsyntax-only 2>&1 \ diff --git a/clang/test/Driver/linux-ld.c b/clang/test/Driver/linux-ld.c index ec539522c25dc..fd5fb993cfe3b 100644 --- a/clang/test/Driver/linux-ld.c +++ b/clang/test/Driver/linux-ld.c @@ -1282,67 +1282,32 @@ // CHECK-DEBIAN-MIPS64EL-N32: "-L[[SYSROOT]]/usr/lib/gcc/mipsel-linux-gnu/4.5/../../.." // CHECK-DEBIAN-MIPS64EL-N32: "-L[[SYSROOT]]/lib" // CHECK-DEBIAN-MIPS64EL-N32: "-L[[SYSROOT]]/usr/lib" -// -// Check linker paths on Debian 8 / Sparc // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ // RUN: --target=sparc-linux-gnu -rtlib=platform \ // RUN: --gcc-toolchain="" \ -// RUN: --sysroot=%S/Inputs/debian_8_sparc_multilib_tree \ -// RUN: | FileCheck --check-prefix=CHECK-DEBIAN-SPARC32 %s -// CHECK-DEBIAN-SPARC32: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" -// CHECK-DEBIAN-SPARC32: "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../sparc-linux-gnu{{/|\\\\}}crt1.o" -// CHECK-DEBIAN-SPARC32: "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../sparc-linux-gnu{{/|\\\\}}crti.o" -// CHECK-DEBIAN-SPARC32: "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9{{/|\\\\}}crtbegin.o" -// CHECK-DEBIAN-SPARC32: "-L[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9" -// CHECK-DEBIAN-SPARC32: "-L[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../sparc-linux-gnu" -// CHECK-DEBIAN-SPARC32: "-L[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../../lib" -// CHECK-DEBIAN-SPARC32: "-L[[SYSROOT]]/lib/sparc-linux-gnu" -// CHECK-DEBIAN-SPARC32: "-L[[SYSROOT]]/usr/lib/sparc-linux-gnu" -// CHECK-DEBIAN-SPARC32: "-L[[SYSROOT]]/lib" -// CHECK-DEBIAN-SPARC32: "-L[[SYSROOT]]/usr/lib" -// CHECK-DEBIAN-SPARC32: "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9{{/|\\\\}}crtend.o" -// CHECK-DEBIAN-SPARC32: "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../sparc-linux-gnu{{/|\\\\}}crtn.o" -// -// Check linker paths on Debian 8 / Sparc, with the oldstyle multilib packages -// RUN: %clang -no-canonical-prefixes -m64 %s -### -o %t.o 2>&1 \ -// RUN: --target=sparc-linux-gnu -rtlib=platform \ -// RUN: --gcc-toolchain="" \ -// RUN: --sysroot=%S/Inputs/debian_8_sparc_multilib_tree \ -// RUN: | FileCheck --check-prefix=CHECK-DEBIAN-SPARC32-LIB64 %s -// CHECK-DEBIAN-SPARC32-LIB64: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" -// CHECK-DEBIAN-SPARC32-LIB64: "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../../lib64{{/|\\\\}}crt1.o" -// CHECK-DEBIAN-SPARC32-LIB64: "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../../lib64{{/|\\\\}}crti.o" -// CHECK-DEBIAN-SPARC32-LIB64: "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/64{{/|\\\\}}crtbegin.o" -// CHECK-DEBIAN-SPARC32-LIB64: "-L[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/64" -// CHECK-DEBIAN-SPARC32-LIB64: "-L[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../../lib64" -// CHECK-DEBIAN-SPARC32-LIB64: "-L[[SYSROOT]]/lib/../lib64" -// CHECK-DEBIAN-SPARC32-LIB64: "-L[[SYSROOT]]/usr/lib/../lib64" -// CHECK-DEBIAN-SPARC32-LIB64: "-L[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9" -// CHECK-DEBIAN-SPARC32-LIB64: "-L[[SYSROOT]]/lib" -// CHECK-DEBIAN-SPARC32-LIB64: "-L[[SYSROOT]]/usr/lib" -// CHECK-DEBIAN-SPARC32-LIB64: "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/64{{/|\\\\}}crtend.o" -// CHECK-DEBIAN-SPARC32-LIB64: "[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.9/../../../../lib64{{/|\\\\}}crtn.o" -// -// Check linker paths on Debian 8 / Sparc64 +// RUN: --sysroot=%S/Inputs/debian_multiarch_tree \ +// RUN: | FileCheck --check-prefix=CHECK-DEBIAN-SPARC %s +// CHECK-DEBIAN-SPARC: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" +// CHECK-DEBIAN-SPARC-SAME: "{{.*}}/usr/lib/gcc/sparc-linux-gnu/4.5{{/|\\\\}}crtbegin.o" +// CHECK-DEBIAN-SPARC-SAME: "-L[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.5" +// CHECK-DEBIAN-SPARC-SAME: "-L[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.5/../../../sparc-linux-gnu" +// CHECK-DEBIAN-SPARC-SAME: "-L[[SYSROOT]]/usr/lib/sparc-linux-gnu" +// CHECK-DEBIAN-SPARC-SAME: "-L[[SYSROOT]]/usr/lib/gcc/sparc-linux-gnu/4.5/../../.." +// CHECK-DEBIAN-SPARC-SAME: "-L[[SYSROOT]]/lib" +// CHECK-DEBIAN-SPARC-SAME: "-L[[SYSROOT]]/usr/lib" // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ // RUN: --target=sparc64-linux-gnu -rtlib=platform \ // RUN: --gcc-toolchain="" \ -// RUN: --sysroot=%S/Inputs/debian_8_sparc64_tree \ +// RUN: --sysroot=%S/Inputs/debian_multiarch_tree \ // RUN: | FileCheck --check-prefix=CHECK-DEBIAN-SPARC64 %s -// CHECK-DEBIAN-SPARC64: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" -// CHECK-DEBIAN-SPARC64: "[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.9/../../../sparc64-linux-gnu{{/|\\\\}}crt1.o" -// CHECK-DEBIAN-SPARC64: "[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.9/../../../sparc64-linux-gnu{{/|\\\\}}crti.o" -// CHECK-DEBIAN-SPARC64: "[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.9{{/|\\\\}}crtbegin.o" -// CHECK-DEBIAN-SPARC64: "-L[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.9" -// CHECK-DEBIAN-SPARC64: "-L[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.9/../../../sparc64-linux-gnu" -// CHECK-DEBIAN-SPARC64: "-L[[SYSROOT]]/lib/sparc64-linux-gnu" -// CHECK-DEBIAN-SPARC64: "-L[[SYSROOT]]/lib/../lib64" -// CHECK-DEBIAN-SPARC64: "-L[[SYSROOT]]/usr/lib/sparc64-linux-gnu" -// CHECK-DEBIAN-SPARC64: "-L[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.9/../../.." -// CHECK-DEBIAN-SPARC64: "-L[[SYSROOT]]/lib" -// CHECK-DEBIAN-SPARC64: "-L[[SYSROOT]]/usr/lib" -// CHECK-DEBIAN-SPARC64: "[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.9{{/|\\\\}}crtend.o" -// CHECK-DEBIAN-SPARC64: "[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.9/../../../sparc64-linux-gnu{{/|\\\\}}crtn.o" +// CHECK-DEBIAN-SPARC64: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" +// CHECK-DEBIAN-SPARC64-SAME: "{{.*}}/usr/lib/gcc/sparc64-linux-gnu/4.5{{/|\\\\}}crtbegin.o" +// CHECK-DEBIAN-SPARC64-SAME: "-L[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.5" +// CHECK-DEBIAN-SPARC64-SAME: "-L[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.5/../../../sparc64-linux-gnu" +// CHECK-DEBIAN-SPARC64-SAME: "-L[[SYSROOT]]/usr/lib/sparc64-linux-gnu" +// CHECK-DEBIAN-SPARC64-SAME: "-L[[SYSROOT]]/usr/lib/gcc/sparc64-linux-gnu/4.5/../../.." +// CHECK-DEBIAN-SPARC64-SAME: "-L[[SYSROOT]]/lib" +// CHECK-DEBIAN-SPARC64-SAME: "-L[[SYSROOT]]/usr/lib" // // Test linker invocation on Android. // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \ diff --git a/clang/test/Driver/ppc-cpus.c b/clang/test/Driver/ppc-cpus.c new file mode 100644 index 0000000000000..9f23d86e41efa --- /dev/null +++ b/clang/test/Driver/ppc-cpus.c @@ -0,0 +1,21 @@ +// RUN: %clang -### -c -target powerpc64 %s -mcpu=ppc64 2>&1 | FileCheck --check-prefix=MCPU_PPC64 %s +// MCPU_PPC64: "-target-cpu" "ppc64" + +/// We cannot check much for -mcpu=native, but it should be replaced by a CPU name. +// RUN: %clang -### -c -target powerpc64 %s -mcpu=native 2>&1 | FileCheck --check-prefix=MCPU_NATIVE %s +// MCPU_NATIVE-NOT: "-target-cpu" "native" + +// RUN: %clang -### -c -target powerpc64 %s -mcpu=7400 2>&1 | FileCheck --check-prefix=MCPU_7400 %s +// MCPU_7400: "-target-cpu" "7400" + +/// The following -mcpu= have their own -target-cpu values. +// RUN: %clang -### -c -target powerpc64 %s -mcpu=G4 2>&1 | FileCheck %s --check-prefix=NO_PPC64 +// RUN: %clang -### -c -target powerpc64 %s -mcpu=7450 2>&1 | FileCheck %s --check-prefix=NO_PPC64 +// RUN: %clang -### -c -target powerpc64 %s -mcpu=G4+ 2>&1 | FileCheck %s --check-prefix=NO_PPC64 +// RUN: %clang -### -c -target powerpc64 %s -mcpu=970 2>&1 | FileCheck %s --check-prefix=NO_PPC64 +// RUN: %clang -### -c -target powerpc64 %s -mcpu=G5 2>&1 | FileCheck %s --check-prefix=NO_PPC64 +// RUN: %clang -### -c -target powerpc64 %s -mcpu=pwr6 2>&1 | FileCheck %s --check-prefix=NO_PPC64 +// RUN: %clang -### -c -target powerpc64 %s -mcpu=pwr7 2>&1 | FileCheck %s --check-prefix=NO_PPC64 +// RUN: %clang -### -c -target powerpc64 %s -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=NO_PPC64 + +// NO_PPC64-NOT: "-target-cpu" "ppc64" diff --git a/clang/test/Driver/ppc-features.cpp b/clang/test/Driver/ppc-features.cpp index a1affba61ee44..de176c9d59422 100644 --- a/clang/test/Driver/ppc-features.cpp +++ b/clang/test/Driver/ppc-features.cpp @@ -1,3 +1,9 @@ +/// Check default CC1 and linker options for ppc32. +// RUN: %clang -### -target powerpc-unknown-linux-gnu %s 2>&1 | FileCheck --check-prefix=PPC32 %s +// PPC32: "-mfloat-abi" "hard" + +// PPC32: "-m" "elf32ppclinux" + // check -msoft-float option for ppc32 // RUN: %clang -target powerpc-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT %s // CHECK-SOFTFLOAT: "-target-feature" "-hard-float" @@ -30,6 +36,15 @@ // RUN: %clang -target powerpc-unknown-linux-gnu %s -mfloat-abi=x -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-ERRMSG %s // CHECK-ERRMSG: error: invalid float ABI '-mfloat-abi=x' + +/// Check default CC1 and linker options for ppc64. +// RUN: %clang -### -target powerpc64le-unknown-linux-gnu %s 2>&1 | FileCheck --check-prefix=PPC64 %s +// RUN: %clang -### -target powerpc64-unknown-linux-gnu %s 2>&1 | FileCheck -check-prefix=PPC64BE %s +// PPC64: "-mfloat-abi" "hard" + +// PPC64: "-m" "elf64lppc" +// PPC64BE: "-m" "elf64ppc" + // check -msoft-float option for ppc64 // RUN: %clang -target powerpc64-unknown-linux-gnu %s -msoft-float -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-SOFTFLOAT64 %s // CHECK-SOFTFLOAT64: "-target-feature" "-hard-float" @@ -48,53 +63,11 @@ // Check that -mno-altivec correctly disables the altivec target feature on powerpc. -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-1 %s -// CHECK-1: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-2 %s -// CHECK-2: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -maltivec -mno-altivec -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-3 %s -// CHECK-3: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -maltivec -mno-altivec -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-4 %s -// CHECK-4: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -maltivec -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-5 %s -// CHECK-5-NOT: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -maltivec -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-6 %s -// CHECK-6-NOT: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -mcpu=7400 -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-7 %s -// CHECK-7: "-target-feature" "-altivec" +// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -maltivec -### -o %t.o 2>&1 | FileCheck --check-prefix=ALTIVEC %s +// ALTIVEC: "-target-feature" "+altivec" -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -mcpu=g4 -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-8 %s -// CHECK-8: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -mcpu=7450 -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-9 %s -// CHECK-9: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -mcpu=g4+ -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-10 %s -// CHECK-10: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -mcpu=970 -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-11 %s -// CHECK-11: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -mcpu=g5 -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-12 %s -// CHECK-12: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -mcpu=pwr6 -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-13 %s -// CHECK-13: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -mcpu=pwr7 -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-14 %s -// CHECK-14: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -mcpu=pwr8 -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-15 %s -// CHECK-15: "-target-feature" "-altivec" - -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-altivec -mcpu=ppc64 -### -o %t.o 2>&1 | FileCheck --check-prefix=CHECK-16 %s -// CHECK-16: "-target-feature" "-altivec" +// RUN: %clang -### -c -target powerpc64-unknown-linux-gnu %s -maltivec -mno-altivec 2>&1 | FileCheck --check-prefix=NO_ALTIVEC %s +// NO_ALTIVEC: "-target-feature" "-altivec" // RUN: %clang -target powerpc64-unknown-linux-gnu %s -mno-qpx -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOQPX %s // CHECK-NOQPX: "-target-feature" "-qpx" @@ -190,13 +163,6 @@ // CHECK_LE_AS_ARGS: "-mlittle-endian" // CHECK_LE_AS_ARGS: "-mpower8" -// linker features -// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK_BE_LD_ARGS %s -// CHECK_BE_LD_ARGS: "elf64ppc" - -// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -o %t.o 2>&1 | FileCheck -check-prefix=CHECK_LE_LD_ARGS %s -// CHECK_LE_LD_ARGS: "elf64lppc" - // OpenMP features // RUN: %clang -target powerpc-unknown-linux-gnu %s -### -fopenmp=libomp -o %t.o 2>&1 | FileCheck -check-prefix=CHECK_OPENMP_TLS %s // RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -fopenmp=libomp -o %t.o 2>&1 | FileCheck -check-prefix=CHECK_OPENMP_TLS %s diff --git a/clang/test/Driver/riscv-gnutools.c b/clang/test/Driver/riscv-gnutools.c index b5ea737ba7836..5aad7079fa43f 100644 --- a/clang/test/Driver/riscv-gnutools.c +++ b/clang/test/Driver/riscv-gnutools.c @@ -5,15 +5,15 @@ // 32-bit checks // Check default on riscv32-unknown-elf -// RUN: %clang -target riscv32-unknown-elf -fno-integrated-as %s -### -c \ +// RUN: %clang -target riscv32-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv32_tree -fno-integrated-as %s -### -c \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32IMAC-ILP32 %s // Check default on riscv32-unknown-linux-gnu -// RUN: %clang -target riscv32-unknown-linux-gnu -fno-integrated-as %s -### -c \ +// RUN: %clang -target riscv32-unknown-linux-gnu --gcc-toolchain=%S/Inputs/basic_riscv32_tree -fno-integrated-as %s -### -c \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32IMAFDC-ILP32D %s // Check default when -march=rv32g specified -// RUN: %clang -target riscv32 -fno-integrated-as %s -### -c -march=rv32g \ +// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -fno-integrated-as %s -### -c -march=rv32g \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac" @@ -24,15 +24,15 @@ // 64-bit checks // Check default on riscv64-unknown-elf -// RUN: %clang -target riscv64-unknown-elf -fno-integrated-as %s -### -c \ +// RUN: %clang -target riscv64-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64IMAC-LP64 %s // Check default on riscv64-unknown-linux-gnu -// RUN: %clang -target riscv64-unknown-linux-gnu -fno-integrated-as %s -### -c \ +// RUN: %clang -target riscv64-unknown-linux-gnu --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64IMAFDC-LP64D %s // Check default when -march=rv64g specified -// RUN: %clang -target riscv64 -fno-integrated-as %s -### -c -march=rv64g \ +// RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c -march=rv64g \ // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac" diff --git a/clang/test/Driver/riscv32-toolchain-extra.c b/clang/test/Driver/riscv32-toolchain-extra.c index 8103e55b9aa50..64ff6a913e247 100644 --- a/clang/test/Driver/riscv32-toolchain-extra.c +++ b/clang/test/Driver/riscv32-toolchain-extra.c @@ -22,6 +22,10 @@ // RUN: -target riscv32-unknown-elf --rtlib=platform 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32-NOGCC %s +// RUN: %T/testroot-riscv32-baremetal-nogcc/bin/clang %s -### -no-canonical-prefixes \ +// RUN: -target riscv32-unknown-elf --rtlib=platform 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32-NOGCC %s + // C-RV32-BAREMETAL-ILP32-NOGCC: "-internal-isystem" "{{.*}}Output/testroot-riscv32-baremetal-nogcc/bin/../riscv32-unknown-elf/include" // C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}Output/testroot-riscv32-baremetal-nogcc/bin/riscv32-unknown-elf-ld" // C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}Output/testroot-riscv32-baremetal-nogcc/bin/../riscv32-unknown-elf/lib/crt0.o" diff --git a/clang/test/Driver/riscv32-toolchain.c b/clang/test/Driver/riscv32-toolchain.c index b83c9aafcbfc6..59865af311ab5 100644 --- a/clang/test/Driver/riscv32-toolchain.c +++ b/clang/test/Driver/riscv32-toolchain.c @@ -1,11 +1,15 @@ // A basic clang -cc1 command-line, and simple environment check. // REQUIRES: platform-linker -// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 2>&1 | FileCheck -check-prefix=CC1 %s +// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \ +// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree 2>&1 \ +// RUN: | FileCheck -check-prefix=CC1 %s // CC1: clang{{.*}} "-cc1" "-triple" "riscv32" // Test interaction with -fuse-ld=lld, if lld is available. -// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 -fuse-ld=lld 2>&1 | FileCheck -check-prefix=LLD %s +// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 \ +// RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree -fuse-ld=lld 2>&1 \ +// RUN: | FileCheck -check-prefix=LLD %s // LLD: {{(error: invalid linker name in argument '-fuse-ld=lld')|(ld.lld)}} // In the below tests, --rtlib=platform is used so that the driver ignores @@ -177,6 +181,7 @@ // Check that --rtlib can be used to override the used runtime library // RUN: %clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk \ // RUN: -target riscv32-unknown-elf --rtlib=libgcc 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV32-RTLIB-LIBGCC-ILP32 %s // C-RV32-RTLIB-LIBGCC-ILP32: "{{.*}}crt0.o" @@ -185,6 +190,7 @@ // C-RV32-RTLIB-LIBGCC-ILP32: "{{.*}}crtend.o" // RUN: %clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk \ // RUN: -target riscv32-unknown-elf --rtlib=compiler-rt 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV32-RTLIB-COMPILERRT-ILP32 %s // C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}crt0.o" diff --git a/clang/test/Driver/riscv64-toolchain-extra.c b/clang/test/Driver/riscv64-toolchain-extra.c index d11f92275f4ea..09922a013c915 100644 --- a/clang/test/Driver/riscv64-toolchain-extra.c +++ b/clang/test/Driver/riscv64-toolchain-extra.c @@ -22,6 +22,10 @@ // RUN: -target riscv64-unknown-elf --rtlib=platform 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV64-BAREMETAL-LP64-NOGCC %s +// RUN: %T/testroot-riscv64-baremetal-nogcc/bin/clang %s -### -no-canonical-prefixes \ +// RUN: -target riscv64-unknown-elf --rtlib=platform 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV64-BAREMETAL-LP64-NOGCC %s + // C-RV64-BAREMETAL-LP64-NOGCC: "-internal-isystem" "{{.*}}Output/testroot-riscv64-baremetal-nogcc/bin/../riscv64-unknown-elf/include" // C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}Output/testroot-riscv64-baremetal-nogcc/bin/riscv64-unknown-elf-ld" // C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}Output/testroot-riscv64-baremetal-nogcc/bin/../riscv64-unknown-elf/lib/crt0.o" diff --git a/clang/test/Driver/riscv64-toolchain.c b/clang/test/Driver/riscv64-toolchain.c index 5df069eb9fd54..b479d7002522f 100644 --- a/clang/test/Driver/riscv64-toolchain.c +++ b/clang/test/Driver/riscv64-toolchain.c @@ -1,11 +1,15 @@ // A basic clang -cc1 command-line, and simple environment check. // REQUIRES: platform-linker -// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 2>&1 | FileCheck -check-prefix=CC1 %s +// RUN: %clang %s -### -no-canonical-prefixes -target riscv64 \ +// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \ +// RUN: | FileCheck -check-prefix=CC1 %s // CC1: clang{{.*}} "-cc1" "-triple" "riscv64" // Test interaction with -fuse-ld=lld, if lld is available. -// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 -fuse-ld=lld 2>&1 | FileCheck -check-prefix=LLD %s +// RUN: %clang %s -### -no-canonical-prefixes -target riscv32 -fuse-ld=lld \ +// RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree 2>&1 \ +// RUN: | FileCheck -check-prefix=LLD %s // LLD: {{(error: invalid linker name in argument '-fuse-ld=lld')|(ld.lld)}} // In the below tests, --rtlib=platform is used so that the driver ignores @@ -133,6 +137,7 @@ // Check that --rtlib can be used to override the used runtime library // RUN: %clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk \ // RUN: -target riscv64-unknown-elf --rtlib=libgcc 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV64-RTLIB-LIBGCC-LP64 %s // C-RV64-RTLIB-LIBGCC-LP64: "{{.*}}crt0.o" @@ -141,6 +146,7 @@ // C-RV64-RTLIB-LIBGCC-LP64: "{{.*}}crtend.o" // RUN: %clang %s -### -no-canonical-prefixes \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk \ // RUN: -target riscv64-unknown-elf --rtlib=compiler-rt 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV64-RTLIB-COMPILERRT-LP64 %s // C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}crt0.o" diff --git a/clang/test/Frontend/noderef.c b/clang/test/Frontend/noderef.c index b072b995fcf64..3388f2a399924 100644 --- a/clang/test/Frontend/noderef.c +++ b/clang/test/Frontend/noderef.c @@ -57,12 +57,19 @@ int test() { p = &*(p + 1); // Struct member access - struct S NODEREF *s; // expected-note 2 {{s declared here}} + struct S NODEREF *s; // expected-note 3 {{s declared here}} x = s->a; // expected-warning{{dereferencing s; was declared with a 'noderef' type}} x = (*s).b; // expected-warning{{dereferencing s; was declared with a 'noderef' type}} p = &s->a; p = &(*s).b; + // Most things in sizeof() can't actually access memory + x = sizeof(s->a); // ok + x = sizeof(*s); // ok + x = sizeof(s[0]); // ok + x = sizeof(s->a + (s->b)); // ok + x = sizeof(int[++s->a]); // expected-warning{{dereferencing s; was declared with a 'noderef' type}} + // Nested struct access struct S2 NODEREF *s2_noderef; // expected-note 5 {{s2_noderef declared here}} p = s2_noderef->a; // ok since result is an array in a struct diff --git a/clang/test/Frontend/noderef.cpp b/clang/test/Frontend/noderef.cpp index 32d5ca34d1b1b..68342a8e6467b 100644 --- a/clang/test/Frontend/noderef.cpp +++ b/clang/test/Frontend/noderef.cpp @@ -6,6 +6,11 @@ #define NODEREF __attribute__((noderef)) +// Stub out types for 'typeid' to work. +namespace std { +class type_info {}; +} // namespace std + void Normal() { int NODEREF i; // expected-warning{{'noderef' can only be used on an array or pointer type}} int NODEREF *i_ptr; // expected-note 2 {{i_ptr declared here}} @@ -102,6 +107,18 @@ int ChildCall(NODEREF Child *child) { // expected-note{{child declared here}} return child->func(); // expected-warning{{dereferencing child; was declared with a 'noderef' type}} } +std::type_info TypeIdPolymorphic(NODEREF A *a) { // expected-note{{a declared here}} + return typeid(*a); // expected-warning{{dereferencing a; was declared with a 'noderef' type}} +} + +class SimpleClass { + int a; +}; + +std::type_info TypeIdNonPolymorphic(NODEREF SimpleClass *simple) { + return typeid(*simple); +} + template class B { Ty NODEREF *member; diff --git a/clang/test/Index/complete-switch.c b/clang/test/Index/complete-switch.c index 9a9438c28d31f..4a78854595543 100644 --- a/clang/test/Index/complete-switch.c +++ b/clang/test/Index/complete-switch.c @@ -6,5 +6,5 @@ void f() { } } -// RUN: not %clang_cc1 -fsyntax-only -code-completion-at=%s:4:10 %s | FileCheck %s -allow-empty +// RUN: not %clang_cc1 -fsyntax-only -fno-recovery-ast -code-completion-at=%s:4:10 %s | FileCheck %s -allow-empty // CHECK-NOT: COMPLETION: foo diff --git a/clang/test/OpenMP/begin_declare_variant_messages.c b/clang/test/OpenMP/begin_declare_variant_messages.c index 63aee2799b784..a6ed043de1023 100644 --- a/clang/test/OpenMP/begin_declare_variant_messages.c +++ b/clang/test/OpenMP/begin_declare_variant_messages.c @@ -80,7 +80,7 @@ const int var; #pragma omp end declare variant #pragma omp begin declare variant match(device={kind(score cpu)}) // expected-error {{expected '(' after 'score'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score (''); score ignored}} #pragma omp end declare variant -#pragma omp begin declare variant match(device={kind(score( ibm)}) // expected-error {{use of undeclared identifier 'ibm'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score (''); score ignored}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} expected-note {{to match this '('}} +#pragma omp begin declare variant match(device = {kind(score(ibm) }) // expected-error {{use of undeclared identifier 'ibm'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('()'); score ignored}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} expected-note {{to match this '('}} #pragma omp end declare variant #pragma omp begin declare variant match(device={kind(score(2 gpu)}) // expected-error {{expected ')'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('2'); score ignored}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{to match this '('}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} expected-note {{to match this '('}} #pragma omp end declare variant diff --git a/clang/test/OpenMP/declare_variant_messages.c b/clang/test/OpenMP/declare_variant_messages.c index 2c63ca206fbbc..18bb7e331f27c 100644 --- a/clang/test/OpenMP/declare_variant_messages.c +++ b/clang/test/OpenMP/declare_variant_messages.c @@ -10,7 +10,7 @@ int foo(void); #pragma omp declare variant // expected-error {{expected '(' after 'declare variant'}} #pragma omp declare variant( // expected-error {{expected expression}} expected-error {{expected ')'}} expected-note {{to match this '('}} #pragma omp declare variant(foo // expected-error {{expected ')'}} expected-error {{expected 'match' clause on 'omp declare variant' directive}} expected-note {{to match this '('}} -#pragma omp declare variant(x) // expected-error {{use of undeclared identifier 'x'}} +#pragma omp declare variant(x) // expected-error {{use of undeclared identifier 'x'}} expected-error {{expected 'match' clause on}} #pragma omp declare variant(foo) // expected-error {{expected 'match' clause on 'omp declare variant' directive}} #pragma omp declare variant(foo) // expected-error {{expected 'match' clause on 'omp declare variant' directive}} #pragma omp declare variant(foo) xxx // expected-error {{expected 'match' clause on 'omp declare variant' directive}} @@ -41,7 +41,7 @@ int foo(void); #pragma omp declare variant(foo) match(device={kind(}) // expected-error {{expected ')'}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} expected-note {{to match this '('}} #pragma omp declare variant(foo) match(device={kind()}) // expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} #pragma omp declare variant(foo) match(device={kind(score cpu)}) // expected-error {{expected '(' after 'score'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score (''); score ignored}} -#pragma omp declare variant(foo) match(device={kind(score( ibm)}) // expected-error {{use of undeclared identifier 'ibm'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score (''); score ignored}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} expected-note {{to match this '('}} +#pragma omp declare variant(foo) match(device = {kind(score(ibm) }) // expected-error {{use of undeclared identifier 'ibm'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('()'); score ignored}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} expected-note {{to match this '('}} #pragma omp declare variant(foo) match(device={kind(score(2 gpu)}) // expected-error {{expected ')'}} expected-error {{expected ')'}} expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('2'); score ignored}} expected-warning {{expected identifier or string literal describing a context property; property skipped}} expected-note {{to match this '('}} expected-note {{context property options are: 'host' 'nohost' 'cpu' 'gpu' 'fpga' 'any'}} expected-note {{to match this '('}} #pragma omp declare variant(foo) match(device={kind(score(foo()) ibm)}) // expected-warning {{expected '':'' after the score expression; '':'' assumed}} expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('foo()'); score ignored}} expected-warning {{'ibm' is not a valid context property for the context selector 'kind' and the context set 'device'; property ignored}} expected-note {{try 'match(implementation={vendor(ibm)})'}} expected-note {{the ignored property spans until here}} #pragma omp declare variant(foo) match(device={kind(score(5): host), kind(llvm)}) // expected-warning {{the context selector 'kind' in the context set 'device' cannot have a score ('5'); score ignored}} expected-warning {{the context selector 'kind' was used already in the same 'omp declare variant' directive; selector ignored}} expected-note {{the previous context selector 'kind' used here}} expected-note {{the ignored selector spans until here}} diff --git a/clang/test/OpenMP/distribute_firstprivate_messages.cpp b/clang/test/OpenMP/distribute_firstprivate_messages.cpp index 346d1a834a866..25a5e9db0eb8b 100644 --- a/clang/test/OpenMP/distribute_firstprivate_messages.cpp +++ b/clang/test/OpenMP/distribute_firstprivate_messages.cpp @@ -28,8 +28,8 @@ class S3 { S3 &operator=(const S3 &s3); public: - S3() : a(0) {} // expected-note {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} - S3(S3 &s3) : a(s3.a) {} // expected-note {{candidate constructor not viable: 1st argument ('const S3') would lose const qualifier}} + S3() : a(0) {} // expected-note 2 {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} + S3(S3 &s3) : a(s3.a) {} // expected-note 2 {{candidate constructor not viable: 1st argument ('const S3') would lose const qualifier}} }; const S3 c; const S3 ca[5]; @@ -95,7 +95,7 @@ int main(int argc, char **argv) { for (i = 0; i < argc; ++i) foo(); #pragma omp target #pragma omp teams - #pragma omp distribute firstprivate (a, b, c, d, f) // expected-error {{firstprivate variable with incomplete type 'S1'}} expected-warning {{Type 'const S2' is not trivially copyable and not guaranteed to be mapped correctly}} expected-warning {{Type 'const S3' is not trivially copyable and not guaranteed to be mapped correctly}} expected-error {{incomplete type 'S1' where a complete type is required}} + #pragma omp distribute firstprivate (a, b, c, d, f) // expected-error {{firstprivate variable with incomplete type 'S1'}} expected-warning {{Type 'const S2' is not trivially copyable and not guaranteed to be mapped correctly}} expected-warning {{Type 'const S3' is not trivially copyable and not guaranteed to be mapped correctly}} expected-error {{incomplete type 'S1' where a complete type is required}} expected-error {{no matching constructor for initialization of 'S3'}} for (i = 0; i < argc; ++i) foo(); #pragma omp target #pragma omp teams diff --git a/clang/test/OpenMP/openmp_capture_const_var_ast_print.cpp b/clang/test/OpenMP/openmp_capture_const_var_ast_print.cpp new file mode 100644 index 0000000000000..4d4b0b00cbafe --- /dev/null +++ b/clang/test/OpenMP/openmp_capture_const_var_ast_print.cpp @@ -0,0 +1,49 @@ +// RUN: %clang_cc1 -verify -fopenmp -ast-print %s | FileCheck %s +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s + +// RUN: %clang_cc1 -verify -fopenmp-simd -ast-print %s | FileCheck %s +// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp-simd -std=c++11 -include-pch %t -fsyntax-only -verify %s -ast-print | FileCheck %s +// expected-no-diagnostics + +#ifndef HEADER +#define HEADER + +struct vector { + vector() = default; + int at(int) { return 0; } + int at(int) const { return 1; } +}; + +// CHECK: template void test(const vector begin_vec) { +// CHECK: #pragma omp parallel for collapse(2) +// CHECK: for (int n = begin_vec.at(0); n < 0; n++) { +// CHECK: for (int h = begin_vec.at(1); h < 1; h++) { +// CHECK: ; +// CHECK: } +// CHECK: } +// CHECK: } +// CHECK: template<> void test(const vector begin_vec) { +// CHECK: #pragma omp parallel for collapse(2) +// CHECK: for (int n = begin_vec.at(0); n < 0; n++) { +// CHECK: for (int h = begin_vec.at(1); h < 1; h++) { +// CHECK: ; +// CHECK: } +// CHECK: } +// CHECK: } +template +void test(const vector begin_vec) { +#pragma omp parallel for collapse(2) + for (int n = begin_vec.at(0); n < 0; n++) { + for (int h = begin_vec.at(1); h < 1; h++) { + ; + } + } +} + +int main() { + vector v; + test(v); +} +#endif diff --git a/clang/test/OpenMP/target_data_map_pointer_array_subscript_codegen.cpp b/clang/test/OpenMP/target_data_map_pointer_array_subscript_codegen.cpp index 14960191af03b..77d416a685aaa 100644 --- a/clang/test/OpenMP/target_data_map_pointer_array_subscript_codegen.cpp +++ b/clang/test/OpenMP/target_data_map_pointer_array_subscript_codegen.cpp @@ -38,10 +38,17 @@ MyObject *objects; // CHECK-DAG: [[MAPS1:@.+]] = private unnamed_addr constant [2 x i64] [i64 32, i64 281474976710673] // CHECK: @main int main(void) { +// CHECK: [[BPTR0:%.+]] = getelementptr inbounds [1 x i8*], [1 x i8*]* %{{.+}}, i32 0, i32 0 +// CHECK: [[BPTRC0:%.+]] = bitcast i8** [[BPTR0]] to %struct.MyObject*** +// CHECK: store %struct.MyObject** @objects, %struct.MyObject*** [[BPTRC0]], // CHECK: call void @__tgt_target_data_begin_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 1, i8** %{{.+}}, i8** %{{.+}}, i64* getelementptr inbounds ([1 x i64], [1 x i64]* [[SIZES0]], i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* [[MAPS0]], i32 0, i32 0), i8** null, i8** null) -#pragma omp target enter data map(to : objects [0:1]) +#pragma omp target enter data map(to : objects [1:1]) +// CHECK: [[OBJ:%.+]] = load %struct.MyObject*, %struct.MyObject** @objects, +// CHECK: [[BPTR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* %{{.+}}, i32 0, i32 0 +// CHECK: [[BPTRC0:%.+]] = bitcast i8** [[BPTR0]] to %struct.MyObject** +// CHECK: store %struct.MyObject* [[OBJ]], %struct.MyObject** [[BPTRC0]], // CHECK: call void @__tgt_target_data_begin_mapper(%struct.ident_t* @{{.+}}, i64 -1, i32 2, i8** %{{.+}}, i8** %{{.+}}, i64* %{{.+}}, i64* getelementptr inbounds ([2 x i64], [2 x i64]* [[MAPS1]], i32 0, i32 0), i8** null, i8** null) -#pragma omp target enter data map(to : objects[0].arr [0:1]) +#pragma omp target enter data map(to : objects[1].arr [0:1]) return 0; } diff --git a/clang/test/OpenMP/teams_distribute_firstprivate_messages.cpp b/clang/test/OpenMP/teams_distribute_firstprivate_messages.cpp index b845a23d847d3..c65e1f4096958 100644 --- a/clang/test/OpenMP/teams_distribute_firstprivate_messages.cpp +++ b/clang/test/OpenMP/teams_distribute_firstprivate_messages.cpp @@ -37,8 +37,8 @@ class S3 { S3 &operator=(const S3 &s3); public: - S3() : a(0) {} // expected-note {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} - S3(S3 &s3) : a(s3.a) {} // expected-note {{candidate constructor not viable: 1st argument ('const S3') would lose const qualifier}} + S3() : a(0) {} // expected-note 2 {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} + S3(S3 &s3) : a(s3.a) {} // expected-note 2 {{candidate constructor not viable: 1st argument ('const S3') would lose const qualifier}} }; const S3 c; const S3 ca[5]; @@ -108,7 +108,7 @@ int main(int argc, char **argv) { for (i = 0; i < argc; ++i) foo(); #pragma omp target -#pragma omp teams distribute firstprivate (a, b, c, d, f) // expected-error {{firstprivate variable with incomplete type 'S1'}} expected-error {{incomplete type 'S1' where a complete type is required}} +#pragma omp teams distribute firstprivate (a, b, c, d, f) // expected-error {{firstprivate variable with incomplete type 'S1'}} expected-error {{incomplete type 'S1' where a complete type is required}} expected-error {{no matching constructor for initialization of 'S3'}} for (i = 0; i < argc; ++i) foo(); #pragma omp target diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_messages.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_messages.cpp index 0509391b313e3..fa323b6e73191 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_messages.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_messages.cpp @@ -37,8 +37,8 @@ class S3 { S3 &operator=(const S3 &s3); public: - S3() : a(0) {} // expected-note {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} - S3(S3 &s3) : a(s3.a) {} // expected-note {{candidate constructor not viable: 1st argument ('const S3') would lose const qualifier}} + S3() : a(0) {} // expected-note 2 {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} + S3(S3 &s3) : a(s3.a) {} // expected-note 2 {{candidate constructor not viable: 1st argument ('const S3') would lose const qualifier}} }; const S3 c; const S3 ca[5]; @@ -108,7 +108,7 @@ int main(int argc, char **argv) { for (i = 0; i < argc; ++i) foo(); #pragma omp target -#pragma omp teams distribute parallel for firstprivate (a, b, c, d, f) // expected-error {{firstprivate variable with incomplete type 'S1'}} expected-error {{incomplete type 'S1' where a complete type is required}} +#pragma omp teams distribute parallel for firstprivate (a, b, c, d, f) // expected-error {{firstprivate variable with incomplete type 'S1'}} expected-error {{incomplete type 'S1' where a complete type is required}} expected-error {{no matching constructor for initialization of 'S3'}} for (i = 0; i < argc; ++i) foo(); #pragma omp target diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_messages.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_messages.cpp index 9d8137b1962ba..9b117c8b397da 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_messages.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_messages.cpp @@ -38,8 +38,8 @@ class S3 { S3 &operator=(const S3 &s3); public: - S3() : a(0) {} // expected-note {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} - S3(S3 &s3) : a(s3.a) {} // expected-note {{candidate constructor not viable: 1st argument ('const S3') would lose const qualifier}} + S3() : a(0) {} // expected-note 2 {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} + S3(S3 &s3) : a(s3.a) {} // expected-note 2 {{candidate constructor not viable: 1st argument ('const S3') would lose const qualifier}} }; const S3 c; const S3 ca[5]; @@ -109,7 +109,7 @@ int main(int argc, char **argv) { for (i = 0; i < argc; ++i) foo(); #pragma omp target -#pragma omp teams distribute parallel for simd firstprivate (a, b, c, d, f) // expected-error {{firstprivate variable with incomplete type 'S1'}} expected-error {{incomplete type 'S1' where a complete type is required}} +#pragma omp teams distribute parallel for simd firstprivate (a, b, c, d, f) // expected-error {{firstprivate variable with incomplete type 'S1'}} expected-error {{incomplete type 'S1' where a complete type is required}} expected-error {{no matching constructor for initialization of 'S3'}} for (i = 0; i < argc; ++i) foo(); #pragma omp target diff --git a/clang/test/OpenMP/teams_distribute_simd_firstprivate_messages.cpp b/clang/test/OpenMP/teams_distribute_simd_firstprivate_messages.cpp index c8a95c2f1553e..855d045e02b92 100644 --- a/clang/test/OpenMP/teams_distribute_simd_firstprivate_messages.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_firstprivate_messages.cpp @@ -39,8 +39,8 @@ class S3 { S3 &operator=(const S3 &s3); public: - S3() : a(0) {} // expected-note {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} - S3(S3 &s3) : a(s3.a) {} // expected-note {{candidate constructor not viable: 1st argument ('const S3') would lose const qualifier}} + S3() : a(0) {} // expected-note 2 {{candidate constructor not viable: requires 0 arguments, but 1 was provided}} + S3(S3 &s3) : a(s3.a) {} // expected-note 2 {{candidate constructor not viable: 1st argument ('const S3') would lose const qualifier}} }; const S3 c; const S3 ca[5]; @@ -110,7 +110,7 @@ int main(int argc, char **argv) { for (i = 0; i < argc; ++i) foo(); #pragma omp target -#pragma omp teams distribute simd firstprivate (k, a, b, c, d, f) // expected-error {{firstprivate variable with incomplete type 'S1'}} expected-error {{incomplete type 'S1' where a complete type is required}} +#pragma omp teams distribute simd firstprivate (k, a, b, c, d, f) // expected-error {{firstprivate variable with incomplete type 'S1'}} expected-error {{incomplete type 'S1' where a complete type is required}} expected-error {{no matching constructor for initialization of 'S3'}} for (i = 0; i < argc; ++i) foo(); #pragma omp target diff --git a/clang/test/Parser/objc-foreach-syntax.m b/clang/test/Parser/objc-foreach-syntax.m index 5d83dc69fcd9c..0f4a14f2b7856 100644 --- a/clang/test/Parser/objc-foreach-syntax.m +++ b/clang/test/Parser/objc-foreach-syntax.m @@ -21,5 +21,8 @@ - (void)compilerTestAgainst { static int test7(id keys) { - for (id key; in keys) ; // expected-error {{use of undeclared identifier 'in'}} + // FIXME: would be nice to suppress the secondary diagnostics. + for (id key; in keys) ; // expected-error {{use of undeclared identifier 'in'}} \ + // expected-error {{expected ';' in 'for' statement specifier}} \ + // expected-warning {{expression result unused}} } diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index 0529a3a3d534b..af4f6a1c0e0e7 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -440,14 +440,10 @@ // CHECK-BFLOAT: __ARM_FEATURE_BF16_VECTOR_ARITHMETIC 1 // ================== Check sve-vector-bits flag. -// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=128 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS-128 %s -// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=256 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS-256 %s -// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=512 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS-512 %s -// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=1024 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS-1024 %s -// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=2048 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS-2048 %s -// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=2048 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS-2048 %s -// CHECK-SVE-VECTOR-BITS-128: __ARM_FEATURE_SVE_BITS 128 -// CHECK-SVE-VECTOR-BITS-256: __ARM_FEATURE_SVE_BITS 256 -// CHECK-SVE-VECTOR-BITS-512: __ARM_FEATURE_SVE_BITS 512 -// CHECK-SVE-VECTOR-BITS-1024: __ARM_FEATURE_SVE_BITS 1024 -// CHECK-SVE-VECTOR-BITS-2048: __ARM_FEATURE_SVE_BITS 2048 +// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=128 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS -D#VBITS=128 %s +// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=256 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS -D#VBITS=256 %s +// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=512 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS -D#VBITS=512 %s +// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=1024 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS -D#VBITS=1024 %s +// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve -msve-vector-bits=2048 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-SVE-VECTOR-BITS -D#VBITS=2048 %s +// CHECK-SVE-VECTOR-BITS: __ARM_FEATURE_SVE_BITS [[#VBITS:]] +// CHECK-SVE-VECTOR-BITS: __ARM_FEATURE_SVE_VECTOR_OPERATORS 1 diff --git a/clang/test/Preprocessor/aix-vec_extabi.c b/clang/test/Preprocessor/aix-vec_extabi.c new file mode 100644 index 0000000000000..b87b992d8d45d --- /dev/null +++ b/clang/test/Preprocessor/aix-vec_extabi.c @@ -0,0 +1,12 @@ +// RUN: %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-extabi %s -o - 2>&1 \ +// RUN: | FileCheck %s -check-prefix=EXTABI +// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-extabi %s -o - 2>&1 \ +// RUN: | FileCheck %s -check-prefix=EXTABI +// RUN: not %clang -target powerpc-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \ +// RUN: | FileCheck %s -check-prefix=DFLTABI +// RUN: not %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -E -dM -maltivec -mabi=vec-default %s 2>&1 \ +// RUN: | FileCheck %s -check-prefix=DFLTABI + + +// EXTABI: #define __EXTABI__ +// DFLTABI: The default Altivec ABI on AIX is not yet supported, use '-mabi=vec-extabi' for the extended Altivec ABI diff --git a/clang/test/Preprocessor/init-aarch64.c b/clang/test/Preprocessor/init-aarch64.c index df2a6128989bd..7f9ae3a5cf5ba 100644 --- a/clang/test/Preprocessor/init-aarch64.c +++ b/clang/test/Preprocessor/init-aarch64.c @@ -233,6 +233,7 @@ // AARCH64-NEXT: #define __SIZE_TYPE__ long unsigned int // AARCH64-NEXT: #define __SIZE_WIDTH__ 64 // AARCH64_CXX: #define __STDCPP_DEFAULT_NEW_ALIGNMENT__ 16UL +// AARCH64_CXX: #define __STDCPP_THREADS__ 1 // AARCH64-NEXT: #define __STDC_HOSTED__ 1 // AARCH64-NEXT: #define __STDC_UTF_16__ 1 // AARCH64-NEXT: #define __STDC_UTF_32__ 1 diff --git a/clang/test/Sema/__try.c b/clang/test/Sema/__try.c index f7c5c97da1044..1953c61613456 100644 --- a/clang/test/Sema/__try.c +++ b/clang/test/Sema/__try.c @@ -50,9 +50,9 @@ void TEST() { } // expected-error{{expected '__except' or '__finally' block}} void TEST() { - __except ( FilterExpression() ) { // expected-warning{{implicit declaration of function '__except' is invalid in C99}} \ - // expected-error{{too few arguments to function call, expected 1, have 0}} - + __except (FilterExpression()) { // expected-warning{{implicit declaration of function '__except' is invalid in C99}} \ + // expected-error{{too few arguments to function call, expected 1, have 0}} \ + // expected-error{{expected ';' after expression}} } } diff --git a/clang/test/Sema/aarch64-sve-lax-vector-conversions.c b/clang/test/Sema/aarch64-sve-lax-vector-conversions.c index e2fe87f7dd208..1a1addcf1c1ba 100644 --- a/clang/test/Sema/aarch64-sve-lax-vector-conversions.c +++ b/clang/test/Sema/aarch64-sve-lax-vector-conversions.c @@ -7,32 +7,61 @@ #include #define N __ARM_FEATURE_SVE_BITS -#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N))) +#define SVE_FIXED_ATTR __attribute__((arm_sve_vector_bits(N))) +#define GNU_FIXED_ATTR __attribute__((vector_size(N / 8))) -typedef svfloat32_t fixed_float32_t FIXED_ATTR; -typedef svint32_t fixed_int32_t FIXED_ATTR; +typedef svfloat32_t sve_fixed_float32_t SVE_FIXED_ATTR; +typedef svint32_t sve_fixed_int32_t SVE_FIXED_ATTR; +typedef float gnu_fixed_float32_t GNU_FIXED_ATTR; +typedef int gnu_fixed_int32_t GNU_FIXED_ATTR; -void allowed_with_integer_lax_conversions() { - fixed_int32_t fi32; +void sve_allowed_with_integer_lax_conversions() { + sve_fixed_int32_t fi32; svint64_t si64; // The implicit cast here should fail if -flax-vector-conversions=none, but pass if // -flax-vector-conversions={integer,all}. fi32 = si64; - // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}} + // lax-vector-none-error@-1 {{assigning to 'sve_fixed_int32_t' (vector of 16 'int' values) from incompatible type}} si64 = fi32; // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}} } -void allowed_with_all_lax_conversions() { - fixed_float32_t ff32; +void sve_allowed_with_all_lax_conversions() { + sve_fixed_float32_t ff32; svfloat64_t sf64; // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if // -flax-vector-conversions=all. ff32 = sf64; - // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}} - // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}} + // lax-vector-none-error@-1 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}} + // lax-vector-integer-error@-2 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}} + sf64 = ff32; + // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}} + // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}} +} + +void gnu_allowed_with_integer_lax_conversions() { + gnu_fixed_int32_t fi32; + svint64_t si64; + + // The implicit cast here should fail if -flax-vector-conversions=none, but pass if + // -flax-vector-conversions={integer,all}. + fi32 = si64; + // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_int32_t' (vector of 16 'int' values) from incompatible type}} + si64 = fi32; + // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}} +} + +void gnu_allowed_with_all_lax_conversions() { + gnu_fixed_float32_t ff32; + svfloat64_t sf64; + + // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if + // -flax-vector-conversions=all. + ff32 = sf64; + // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}} + // lax-vector-integer-error@-2 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}} sf64 = ff32; // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}} // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}} diff --git a/clang/test/Sema/attr-arm-sve-vector-bits.c b/clang/test/Sema/attr-arm-sve-vector-bits.c index 667a49b0d76b2..60f9e57357b9e 100644 --- a/clang/test/Sema/attr-arm-sve-vector-bits.c +++ b/clang/test/Sema/attr-arm-sve-vector-bits.c @@ -272,9 +272,6 @@ TEST_CAST_COMMON(bool) // Test the implicit conversion only applies to valid types fixed_bool_t to_fixed_bool_t__from_svint32_t(svint32_t x) { return x; } // expected-error-re {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'fixed_bool_t' (vector of {{[0-9]+}} 'unsigned char' values)}} -svint64_t to_svint64_t__from_gnu_int32_t(gnu_int32_t x) { return x; } // expected-error-re {{returning 'gnu_int32_t' (vector of {{[0-9]+}} 'int32_t' values) from a function with incompatible result type 'svint64_t' (aka '__SVInt64_t')}} -gnu_int32_t from_svint64_t__to_gnu_int32_t(svint64_t x) { return x; } // expected-error-re {{returning 'svint64_t' (aka '__SVInt64_t') from a function with incompatible result type 'gnu_int32_t' (vector of {{[0-9]+}} 'int32_t' values)}} - // Test implicit conversion between SVE and GNU vector is invalid when // __ARM_FEATURE_SVE_BITS != N #if defined(__ARM_FEATURE_SVE_BITS) && __ARM_FEATURE_SVE_BITS == 512 diff --git a/clang/test/Sema/enum.c b/clang/test/Sema/enum.c index 7681ebccd4fa8..c5ff13a0e6eb7 100644 --- a/clang/test/Sema/enum.c +++ b/clang/test/Sema/enum.c @@ -100,7 +100,8 @@ int CheckPR4515[PR4515b==0?1:-1]; // PR7911 extern enum PR7911T PR7911V; // expected-warning{{ISO C forbids forward references to 'enum' types}} void PR7911F() { - switch (PR7911V); // expected-error {{statement requires expression of integer type}} + switch (PR7911V) // expected-error {{statement requires expression of integer type}} + ; } char test5[__has_feature(enumerator_attributes) ? 1 : -1]; diff --git a/clang/test/Sema/sizeless-1.c b/clang/test/Sema/sizeless-1.c index dd6492c44b622..e1d9265448947 100644 --- a/clang/test/Sema/sizeless-1.c +++ b/clang/test/Sema/sizeless-1.c @@ -290,4 +290,10 @@ void test_generic(void) { int a3[_Generic(0, svint8_t : 1, svint16_t : 2, default : 3) == 3 ? 1 : -1]; (void)_Generic(0, svint8_t : 1, svint8_t : 2, default : 3); // expected-error {{type 'svint8_t' (aka '__SVInt8_t') in generic association compatible with previously specified type 'svint8_t'}} expected-note {{compatible type}} } + +void test_compound_literal(void) { + svint8_t local_int8; + + (void)(svint8_t){local_int8}; +} #endif diff --git a/clang/test/Sema/typo-correction.c b/clang/test/Sema/typo-correction.c index 73ba265509e4c..f70eb8b5cf15b 100644 --- a/clang/test/Sema/typo-correction.c +++ b/clang/test/Sema/typo-correction.c @@ -14,9 +14,9 @@ a = b ? : 0; // expected-warning {{type specifier missing, defaults to 'int'}} // expected-error {{use of undeclared identifier 'b'}} int foobar; // expected-note {{'foobar' declared here}} -a = goobar ?: 4; // expected-warning {{type specifier missing, defaults to 'int'}} \ - // expected-error {{use of undeclared identifier 'goobar'; did you mean 'foobar'?}} \ - // expected-error {{initializer element is not a compile-time constant}} +new_a = goobar ?: 4; // expected-warning {{type specifier missing, defaults to 'int'}} \ + // expected-error {{use of undeclared identifier 'goobar'; did you mean 'foobar'?}} \ + // expected-error {{initializer element is not a compile-time constant}} struct ContainerStuct { enum { SOME_ENUM }; // expected-note {{'SOME_ENUM' declared here}} @@ -50,10 +50,10 @@ void fn1() { cabs(errij); // expected-error {{use of undeclared identifier 'errij'}} } -extern long afunction(int); // expected-note {{'afunction' declared here}} +extern long afunction(int); void fn2() { - f(THIS_IS_AN_ERROR, // expected-error {{use of undeclared identifier 'THIS_IS_AN_ERROR'}} - afunction(afunction_)); // expected-error {{use of undeclared identifier 'afunction_'; did you mean 'afunction'?}} + f(THIS_IS_AN_ERROR, // expected-error {{use of undeclared identifier 'THIS_IS_AN_ERROR'}} + afunction(afunction_)); // expected-error {{use of undeclared identifier 'afunction_'}} } int d = X ? d : L; // expected-error 2 {{use of undeclared identifier}} diff --git a/clang/test/Sema/wchar.c b/clang/test/Sema/wchar.c index 3170e363ff773..83ea6372168d6 100644 --- a/clang/test/Sema/wchar.c +++ b/clang/test/Sema/wchar.c @@ -6,7 +6,14 @@ typedef __WCHAR_TYPE__ wchar_t; #if defined(_WIN32) || defined(_M_IX86) || defined(__CYGWIN__) \ || defined(_M_X64) || defined(__ORBIS__) || defined(SHORT_WCHAR) #define WCHAR_T_TYPE unsigned short -#elif defined(__arm) || defined(__aarch64__) || defined(__MVS__) +#elif defined(__aarch64__) + // See AArch64TargetInfo constructor -- unsigned on non-darwin non-OpenBSD non-NetBSD. + #if defined(__OpenBSD__) || defined(__APPLE__) || defined(__NetBSD__) + #define WCHAR_T_TYPE int + #else + #define WCHAR_T_TYPE unsigned int + #endif +#elif defined(__arm) || defined(__MVS__) #define WCHAR_T_TYPE unsigned int #elif defined(__sun) #if defined(__LP64__) @@ -14,7 +21,7 @@ typedef __WCHAR_TYPE__ wchar_t; #else #define WCHAR_T_TYPE long #endif -#else /* Solaris. */ +#else /* Solaris, Linux, non-arm64 macOS, ... */ #define WCHAR_T_TYPE int #endif diff --git a/clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp b/clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp index e2fe87f7dd208..1a1addcf1c1ba 100644 --- a/clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp +++ b/clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp @@ -7,32 +7,61 @@ #include #define N __ARM_FEATURE_SVE_BITS -#define FIXED_ATTR __attribute__((arm_sve_vector_bits(N))) +#define SVE_FIXED_ATTR __attribute__((arm_sve_vector_bits(N))) +#define GNU_FIXED_ATTR __attribute__((vector_size(N / 8))) -typedef svfloat32_t fixed_float32_t FIXED_ATTR; -typedef svint32_t fixed_int32_t FIXED_ATTR; +typedef svfloat32_t sve_fixed_float32_t SVE_FIXED_ATTR; +typedef svint32_t sve_fixed_int32_t SVE_FIXED_ATTR; +typedef float gnu_fixed_float32_t GNU_FIXED_ATTR; +typedef int gnu_fixed_int32_t GNU_FIXED_ATTR; -void allowed_with_integer_lax_conversions() { - fixed_int32_t fi32; +void sve_allowed_with_integer_lax_conversions() { + sve_fixed_int32_t fi32; svint64_t si64; // The implicit cast here should fail if -flax-vector-conversions=none, but pass if // -flax-vector-conversions={integer,all}. fi32 = si64; - // lax-vector-none-error@-1 {{assigning to 'fixed_int32_t' (vector of 16 'int' values) from incompatible type}} + // lax-vector-none-error@-1 {{assigning to 'sve_fixed_int32_t' (vector of 16 'int' values) from incompatible type}} si64 = fi32; // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}} } -void allowed_with_all_lax_conversions() { - fixed_float32_t ff32; +void sve_allowed_with_all_lax_conversions() { + sve_fixed_float32_t ff32; svfloat64_t sf64; // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if // -flax-vector-conversions=all. ff32 = sf64; - // lax-vector-none-error@-1 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}} - // lax-vector-integer-error@-2 {{assigning to 'fixed_float32_t' (vector of 16 'float' values) from incompatible type}} + // lax-vector-none-error@-1 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}} + // lax-vector-integer-error@-2 {{assigning to 'sve_fixed_float32_t' (vector of 16 'float' values) from incompatible type}} + sf64 = ff32; + // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}} + // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}} +} + +void gnu_allowed_with_integer_lax_conversions() { + gnu_fixed_int32_t fi32; + svint64_t si64; + + // The implicit cast here should fail if -flax-vector-conversions=none, but pass if + // -flax-vector-conversions={integer,all}. + fi32 = si64; + // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_int32_t' (vector of 16 'int' values) from incompatible type}} + si64 = fi32; + // lax-vector-none-error@-1 {{assigning to 'svint64_t' (aka '__SVInt64_t') from incompatible type}} +} + +void gnu_allowed_with_all_lax_conversions() { + gnu_fixed_float32_t ff32; + svfloat64_t sf64; + + // The implicit cast here should fail if -flax-vector-conversions={none,integer}, but pass if + // -flax-vector-conversions=all. + ff32 = sf64; + // lax-vector-none-error@-1 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}} + // lax-vector-integer-error@-2 {{assigning to 'gnu_fixed_float32_t' (vector of 16 'float' values) from incompatible type}} sf64 = ff32; // lax-vector-none-error@-1 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}} // lax-vector-integer-error@-2 {{assigning to 'svfloat64_t' (aka '__SVFloat64_t') from incompatible type}} diff --git a/clang/test/SemaCXX/init-priority-attr.cpp b/clang/test/SemaCXX/init-priority-attr.cpp index 5b5e3b9eb940e..8c0a17682bb02 100644 --- a/clang/test/SemaCXX/init-priority-attr.cpp +++ b/clang/test/SemaCXX/init-priority-attr.cpp @@ -1,5 +1,7 @@ -// RUN: %clang_cc1 -fsyntax-only -verify %s -// RUN: %clang_cc1 -fsyntax-only -DSYSTEM -verify %s +// RUN: %clang_cc1 -triple=x86_64-unknown-unknown -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple=x86_64-unknown-unknown -fsyntax-only -DSYSTEM -verify %s +// RUN: %clang_cc1 -triple=s390x-none-zos -fsyntax-only -verify=unknown %s +// RUN: %clang_cc1 -triple=s390x-none-zos -fsyntax-only -DSYSTEM -verify=unknown-system %s #if defined(SYSTEM) #5 "init-priority-attr.cpp" 3 // system header @@ -23,25 +25,35 @@ extern Two coo[]; extern Two koo[]; Two foo __attribute__((init_priority(101))) ( 5, 6 ); + // unknown-system-no-diagnostics + // unknown-warning@-2 {{unknown attribute 'init_priority' ignored}} Two goo __attribute__((init_priority(2,3))) ( 5, 6 ); // expected-error {{'init_priority' attribute takes one argument}} +// unknown-warning@-1 {{unknown attribute 'init_priority' ignored}} Two coo[2] __attribute__((init_priority(100))); #if !defined(SYSTEM) -// expected-error@-2 {{'init_priority' attribute requires integer constant between 101 and 65535 inclusive}} + // expected-error@-2 {{'init_priority' attribute requires integer constant between 101 and 65535 inclusive}} + // unknown-warning@-3 {{unknown attribute 'init_priority' ignored}} #endif Two boo[2] __attribute__((init_priority(65536))); #if !defined(SYSTEM) -// expected-error@-2 {{'init_priority' attribute requires integer constant between 101 and 65535 inclusive}} + // expected-error@-2 {{'init_priority' attribute requires integer constant between 101 and 65535 inclusive}} + // unknown-warning@-3 {{unknown attribute 'init_priority' ignored}} #endif Two koo[4] __attribute__((init_priority(1.13))); // expected-error {{'init_priority' attribute requires an integer constant}} +// unknown-warning@-1 {{unknown attribute 'init_priority' ignored}} Two func() __attribute__((init_priority(1001))); // expected-error {{'init_priority' attribute only applies to variables}} +// unknown-warning@-1 {{unknown attribute 'init_priority' ignored}} + int i __attribute__((init_priority(1001))); // expected-error {{can only use 'init_priority' attribute on file-scope definitions of objects of class type}} +// unknown-warning@-1 {{unknown attribute 'init_priority' ignored}} int main() { - Two foo __attribute__((init_priority(1001))); // expected-error {{can only use 'init_priority' attribute on file-scope definitions of objects of class type}} + Two foo __attribute__((init_priority(1001))); // expected-error {{can only use 'init_priority' attribute on file-scope definitions of objects of class type}} +// unknown-warning@-1 {{unknown attribute 'init_priority' ignored}} } diff --git a/clang/test/SemaCXX/lookup-member.cpp b/clang/test/SemaCXX/lookup-member.cpp index a2256a89d11cf..46ba74aeddd44 100644 --- a/clang/test/SemaCXX/lookup-member.cpp +++ b/clang/test/SemaCXX/lookup-member.cpp @@ -11,3 +11,29 @@ class String; // expected-error {{conflicts with target of using declaration}} union value { char *String; }; + +namespace UnambiguousStaticMemberTemplate { + // A static member template is not ambiguous if found in multiple base class + // subobjects. + struct A { template static void f(T); static void g(); }; + struct B : A { using A::f; using A::g; }; + struct C : A { using A::f; using A::g; }; + struct D : B, C {}; + void f(D d) { d.f(0); d.g(); } +} + +namespace UnambiguousReorderedMembers { + // Static members are not ambiguous if we find them in a different order in + // multiple base classes. + struct A { static void f(); }; + struct B { static void f(int); }; + struct C : A, B { using A::f; using B::f; }; // expected-note {{found}} + struct D : B, A { using B::f; using A::f; }; + struct E : C, D {}; + void f(E e) { e.f(0); } + + // But a different declaration set in different base classes does result in ambiguity. + struct X : B, A { using B::f; using A::f; static void f(int, int); }; // expected-note {{found}} + struct Y : C, X {}; + void g(Y y) { y.f(0); } // expected-error {{found in multiple base classes of different types}} +} diff --git a/clang/test/SemaCXX/member-name-lookup.cpp b/clang/test/SemaCXX/member-name-lookup.cpp index 01491693deac7..cfd00b35421e7 100644 --- a/clang/test/SemaCXX/member-name-lookup.cpp +++ b/clang/test/SemaCXX/member-name-lookup.cpp @@ -20,14 +20,14 @@ struct B : A { enum E2 { enumerator2 }; - enum E3 { enumerator3 }; // expected-note 2{{member found by ambiguous name lookup}} + enum E3 { enumerator3 }; // expected-note 2{{member type 'B::E3' found by ambiguous name lookup}} }; struct C : A { int c; // expected-note 2{{member found by ambiguous name lookup}} int d; // expected-note 2{{member found by ambiguous name lookup}} - enum E3 { enumerator3_2 }; // expected-note 2{{member found by ambiguous name lookup}} + enum E3 { enumerator3_2 }; // expected-note 2{{member type 'C::E3' found by ambiguous name lookup}} }; struct D : B, C { @@ -71,14 +71,14 @@ struct B2 : virtual A { enum E2 { enumerator2 }; - enum E3 { enumerator3 }; // expected-note 2 {{member found by ambiguous name lookup}} + enum E3 { enumerator3 }; // expected-note 2 {{member type 'B2::E3' found by ambiguous name lookup}} }; struct C2 : virtual A { int c; int d; // expected-note 2{{member found by ambiguous name lookup}} - enum E3 { enumerator3_2 }; // expected-note 2{{member found by ambiguous name lookup}} + enum E3 { enumerator3_2 }; // expected-note 2{{member type 'C2::E3' found by ambiguous name lookup}} }; struct D2 : B2, C2 { @@ -132,11 +132,11 @@ void G::test_virtual_lookup() { struct HasMemberType1 { - struct type { }; // expected-note{{member found by ambiguous name lookup}} + struct type { }; // expected-note{{member type 'HasMemberType1::type' found by ambiguous name lookup}} }; struct HasMemberType2 { - struct type { }; // expected-note{{member found by ambiguous name lookup}} + struct type { }; // expected-note{{member type 'HasMemberType2::type' found by ambiguous name lookup}} }; struct HasAnotherMemberType : HasMemberType1, HasMemberType2 { diff --git a/clang/test/SemaCXX/sizeless-1.cpp b/clang/test/SemaCXX/sizeless-1.cpp index 46a183f7ad0c0..96a3ce7542a75 100644 --- a/clang/test/SemaCXX/sizeless-1.cpp +++ b/clang/test/SemaCXX/sizeless-1.cpp @@ -379,6 +379,8 @@ extern array_alias *array_alias_int_ptr; extern array_alias *array_alias_int8_ptr; // expected-note {{in instantiation of template type alias 'array_alias' requested here}} #endif +extern "C" svint8_t c_return_int8(); + void cxx_only(int sel) { svint8_t local_int8; svint16_t local_int16; diff --git a/clang/test/SemaOpenCL/invalid-kernel-parameters.cl b/clang/test/SemaOpenCL/invalid-kernel-parameters.cl index 48de39d0f87ec..26859ee62cae8 100644 --- a/clang/test/SemaOpenCL/invalid-kernel-parameters.cl +++ b/clang/test/SemaOpenCL/invalid-kernel-parameters.cl @@ -1,9 +1,21 @@ // RUN: %clang_cc1 -fsyntax-only -verify %s -triple spir-unknown-unknown +// RUN: %clang_cc1 -fsyntax-only -verify %s -triple spir-unknown-unknown -cl-std=CL2.0 kernel void half_arg(half x) { } // expected-error{{declaring function parameter of type '__private half' is not allowed; did you forget * ?}} #pragma OPENCL EXTENSION cl_khr_fp16 : enable +// expected-error@+1{{kernel parameter cannot be declared as a pointer to a pointer}} +kernel void no_ptrptr(global int * global *i) { } + +// expected-error@+1{{pointer arguments to kernel functions must reside in '__global', '__constant' or '__local' address space}} +__kernel void no_privateptr(__private int *i) { } + +// expected-error@+1{{pointer arguments to kernel functions must reside in '__global', '__constant' or '__local' address space}} +__kernel void no_privatearray(__private int i[]) { } + +// expected-error@+1{{pointer arguments to kernel functions must reside in '__global', '__constant' or '__local' address space}} +__kernel void no_addrsp_ptr(int *ptr) { } // Disallowed: parameters with type // bool, half, size_t, ptrdiff_t, intptr_t, and uintptr_t @@ -65,14 +77,14 @@ kernel void image_in_struct_arg(FooImage2D arg) { } // expected-error{{struct ke typedef struct Foo // expected-note{{within field of type 'Foo' declared here}} { - int* ptrField; // expected-note{{field of illegal pointer type '__private int *' declared here}} + int* ptrField; // expected-note-re{{field of illegal pointer type '__{{private|generic}} int *' declared here}} } Foo; kernel void pointer_in_struct_arg(Foo arg) { } // expected-error{{struct kernel parameters may not contain pointers}} typedef union FooUnion // expected-note{{within field of type 'FooUnion' declared here}} { - int* ptrField; // expected-note{{field of illegal pointer type '__private int *' declared here}} + int* ptrField; // expected-note-re{{field of illegal pointer type '__{{private|generic}} int *' declared here}} } FooUnion; kernel void pointer_in_union_arg(FooUnion arg) { }// expected-error{{union kernel parameters may not contain pointers}} @@ -82,7 +94,7 @@ typedef struct NestedPointer // expected-note 2 {{within field of type 'NestedPo int x; struct InnerNestedPointer { - int* ptrField; // expected-note 3 {{field of illegal pointer type '__private int *' declared here}} + int* ptrField; // expected-note-re 3 {{field of illegal pointer type '__{{private|generic}} int *' declared here}} } inner; // expected-note 3 {{within field of type 'struct InnerNestedPointer' declared here}} } NestedPointer; @@ -96,7 +108,7 @@ struct NestedPointerComplex // expected-note{{within field of type 'NestedPointe struct InnerNestedPointerComplex { int innerFoo; - int* innerPtrField; // expected-note{{field of illegal pointer type '__private int *' declared here}} + int* innerPtrField; // expected-note-re{{field of illegal pointer type '__{{private|generic}} int *' declared here}} } inner; // expected-note{{within field of type 'struct InnerNestedPointerComplex' declared here}} float y; @@ -167,8 +179,7 @@ kernel void pointer_in_nested_struct_arg_2(struct Valid valid, struct NestedPoin struct ArrayOfPtr // expected-note{{within field of type 'ArrayOfPtr' declared here}} { - float *arr[3]; // expected-note{{field of illegal type '__private float *[3]' declared here}} - // expected-note@-1{{field of illegal type '__private float *[3]' declared here}} + float *arr[3]; // expected-note-re 2{{field of illegal type '__{{private|generic}} float *[3]' declared here}} }; kernel void array_of_ptr(struct ArrayOfPtr arr) {} // expected-error{{struct kernel parameters may not contain pointers}} diff --git a/clang/test/SemaOpenCL/invalid-kernel.cl b/clang/test/SemaOpenCL/invalid-kernel.cl index 031f6061a3b96..fd9cd6def00e8 100644 --- a/clang/test/SemaOpenCL/invalid-kernel.cl +++ b/clang/test/SemaOpenCL/invalid-kernel.cl @@ -1,12 +1,6 @@ // RUN: %clang_cc1 -verify %s // RUN: %clang_cc1 -cl-std=CL2.0 -verify %s -kernel void no_ptrptr(global int * global *i) { } // expected-error{{kernel parameter cannot be declared as a pointer to a pointer}} - -__kernel void no_privateptr(__private int *i) { } // expected-error {{pointer arguments to kernel functions must reside in '__global', '__constant' or '__local' address space}} - -__kernel void no_privatearray(__private int i[]) { } // expected-error {{pointer arguments to kernel functions must reside in '__global', '__constant' or '__local' address space}} - kernel int bar() { // expected-error {{kernel must have void return type}} return 6; } @@ -30,6 +24,3 @@ int* local x(int* x) { // expected-error {{return value cannot be qualified with int* constant x(int* x) { // expected-error {{return value cannot be qualified with address space}} return x + 1; } - -__kernel void testKernel(int *ptr) { // expected-error {{pointer arguments to kernel functions must reside in '__global', '__constant' or '__local' address space}} -} diff --git a/clang/test/SemaTemplate/dependent-base-classes.cpp b/clang/test/SemaTemplate/dependent-base-classes.cpp index f8f36b2a077d4..09f475f8bde91 100644 --- a/clang/test/SemaTemplate/dependent-base-classes.cpp +++ b/clang/test/SemaTemplate/dependent-base-classes.cpp @@ -64,11 +64,11 @@ namespace PR6031 { namespace Ambig { template struct Base1 { - typedef int type; // expected-note{{member found by ambiguous name lookup}} + typedef int type; // expected-note{{member type 'int' found by ambiguous name lookup}} }; struct Base2 { - typedef float type; // expected-note{{member found by ambiguous name lookup}} + typedef float type; // expected-note{{member type 'float' found by ambiguous name lookup}} }; template diff --git a/clang/test/SemaTemplate/ms-lookup-template-base-classes.cpp b/clang/test/SemaTemplate/ms-lookup-template-base-classes.cpp index cb497176ff0ee..14e43868e83d9 100644 --- a/clang/test/SemaTemplate/ms-lookup-template-base-classes.cpp +++ b/clang/test/SemaTemplate/ms-lookup-template-base-classes.cpp @@ -304,8 +304,8 @@ static_assert(sizeof(B) == sizeof(A::NameFromBase), ""); } namespace two_types_in_base { -template struct A { typedef T NameFromBase; }; // expected-note {{member found by ambiguous name lookup}} -template struct B { struct NameFromBase { T m; }; }; // expected-note {{member found by ambiguous name lookup}} +template struct A { typedef T NameFromBase; }; // expected-note {{member type 'int' found by ambiguous name lookup}} +template struct B { struct NameFromBase { T m; }; }; // expected-note {{member type 'two_types_in_base::B::NameFromBase' found by ambiguous name lookup}} template struct C : A, B { NameFromBase m; // expected-error {{member 'NameFromBase' found in multiple base classes of different types}} expected-warning {{use of identifier 'NameFromBase' found via unqualified lookup into dependent bases of class templates is a Microsoft extension}} }; diff --git a/clang/test/SemaTemplate/temp.cpp b/clang/test/SemaTemplate/temp.cpp index a8a2daeac31b4..ae0f0174d9d4e 100644 --- a/clang/test/SemaTemplate/temp.cpp +++ b/clang/test/SemaTemplate/temp.cpp @@ -8,8 +8,8 @@ namespace test0 { // PR7252 namespace test1 { - namespace A { template struct Base { typedef T t; }; } // expected-note 3{{member}} - namespace B { template struct Base { typedef T t; }; } // expected-note {{member found}} + namespace A { template struct Base { typedef T t; }; } // expected-note {{member type 'test1::A::Base' found}} expected-note 2{{declared here}} + namespace B { template struct Base { typedef T t; }; } // expected-note {{member type 'test1::B::Base' found}} template struct Derived : A::Base, B::Base { typename Derived::Base::t x; // expected-error {{found in multiple base classes of different types}} diff --git a/clang/test/SemaTemplate/typename-specifier-4.cpp b/clang/test/SemaTemplate/typename-specifier-4.cpp index 2856c99b6ddf4..7aa2b8da51081 100644 --- a/clang/test/SemaTemplate/typename-specifier-4.cpp +++ b/clang/test/SemaTemplate/typename-specifier-4.cpp @@ -107,8 +107,8 @@ namespace PR6268 { } namespace PR6463 { - struct B { typedef int type; }; // expected-note 2{{member found by ambiguous name lookup}} - struct C { typedef int type; }; // expected-note 2{{member found by ambiguous name lookup}} + struct B { typedef int type; }; // expected-note 2{{member type 'int' found by ambiguous name lookup}} + struct C { typedef const int type; }; // expected-note 2{{member type 'const int' found by ambiguous name lookup}} template struct A : B, C { diff --git a/clang/test/lit.cfg.py b/clang/test/lit.cfg.py index 1a6e73ed97839..863ab444fb023 100644 --- a/clang/test/lit.cfg.py +++ b/clang/test/lit.cfg.py @@ -64,7 +64,7 @@ tools = [ 'apinotes-test', 'c-index-test', 'clang-diff', 'clang-format', - 'clang-tblgen', 'opt', 'llvm-ifs', + 'clang-tblgen', 'opt', 'llvm-ifs', 'yaml2obj', ToolSubst('%clang_extdef_map', command=FindTool( 'clang-extdef-mapping'), unresolved='ignore'), ] diff --git a/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp b/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp index 17ce40b5b1b6f..4adb6eb39d09e 100644 --- a/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp +++ b/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp @@ -107,11 +107,16 @@ static std::string OptLLVM(const std::string &IR, CodeGenOpt::Level OLvl) { std::string E; const Target *TheTarget = TargetRegistry::lookupTarget(codegen::getMArch(), ModuleTriple, E); - TargetMachine *Machine = TheTarget->createTargetMachine( + if (!TheTarget) + ErrorAndExit(E); + + std::unique_ptr TM(TheTarget->createTargetMachine( M->getTargetTriple(), codegen::getCPUStr(), codegen::getFeaturesStr(), Options, codegen::getExplicitRelocModel(), - codegen::getExplicitCodeModel(), OLvl); - std::unique_ptr TM(Machine); + codegen::getExplicitCodeModel(), OLvl)); + if (!TM) + ErrorAndExit("Could not create target machine"); + codegen::setFunctionAttributes(codegen::getCPUStr(), codegen::getFeaturesStr(), *M); diff --git a/clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp b/clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp index ec6cfb965b4f8..f5cb030237844 100644 --- a/clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp +++ b/clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp @@ -44,7 +44,7 @@ #include #include #include -#include +#include #include #include #include @@ -434,7 +434,7 @@ class TempFileHandlerRAII { if (std::error_code EC = sys::fs::createTemporaryFile("clang-offload-bundler", "tmp", File)) return createFileError(File, EC); - Files.push_back(File); + Files.push_front(File); if (Contents) { std::error_code EC; @@ -443,11 +443,11 @@ class TempFileHandlerRAII { return createFileError(File, EC); OS.write(Contents->data(), Contents->size()); } - return Files.back(); + return Files.front(); } private: - SmallVector, 4u> Files; + std::forward_list> Files; }; } // end anonymous namespace diff --git a/clang/tools/driver/cc1as_main.cpp b/clang/tools/driver/cc1as_main.cpp index 07dddc6dc85b0..de71026fbffe4 100644 --- a/clang/tools/driver/cc1as_main.cpp +++ b/clang/tools/driver/cc1as_main.cpp @@ -428,8 +428,11 @@ static bool ExecuteAssembler(AssemblerInvocation &Opts, std::unique_ptr Str; std::unique_ptr MCII(TheTarget->createMCInstrInfo()); + assert(MCII && "Unable to create instruction info!"); + std::unique_ptr STI( TheTarget->createMCSubtargetInfo(Opts.Triple, Opts.CPU, FS)); + assert(STI && "Unable to create subtarget info!"); raw_pwrite_stream *Out = FDOS.get(); std::unique_ptr BOS; @@ -468,6 +471,8 @@ static bool ExecuteAssembler(AssemblerInvocation &Opts, TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx)); std::unique_ptr MAB( TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions)); + assert(MAB && "Unable to create asm backend!"); + std::unique_ptr OW = DwoOS ? MAB->createDwoObjectWriter(*Out, *DwoOS) : MAB->createObjectWriter(*Out); diff --git a/clang/unittests/AST/ASTImporterTest.cpp b/clang/unittests/AST/ASTImporterTest.cpp index f869e492c90ac..81a92a10f48de 100644 --- a/clang/unittests/AST/ASTImporterTest.cpp +++ b/clang/unittests/AST/ASTImporterTest.cpp @@ -880,6 +880,25 @@ TEST_P(ImportExpr, DependentSizedArrayType) { has(fieldDecl(hasType(dependentSizedArrayType()))))))); } +TEST_P(ASTImporterOptionSpecificTestBase, TemplateTypeParmDeclNoDefaultArg) { + Decl *FromTU = getTuDecl("template struct X {};", Lang_CXX03); + auto From = FirstDeclMatcher().match( + FromTU, templateTypeParmDecl(hasName("T"))); + TemplateTypeParmDecl *To = Import(From, Lang_CXX03); + ASSERT_FALSE(To->hasDefaultArgument()); +} + +TEST_P(ASTImporterOptionSpecificTestBase, TemplateTypeParmDeclDefaultArg) { + Decl *FromTU = + getTuDecl("template struct X {};", Lang_CXX03); + auto From = FirstDeclMatcher().match( + FromTU, templateTypeParmDecl(hasName("T"))); + TemplateTypeParmDecl *To = Import(From, Lang_CXX03); + ASSERT_TRUE(To->hasDefaultArgument()); + QualType ToArg = To->getDefaultArgument(); + ASSERT_EQ(ToArg, QualType(To->getASTContext().IntTy)); +} + TEST_P(ASTImporterOptionSpecificTestBase, ImportBeginLocOfDeclRefExpr) { Decl *FromTU = getTuDecl("class A { public: static int X; }; void f() { (void)A::X; }", @@ -901,6 +920,60 @@ TEST_P(ASTImporterOptionSpecificTestBase, ImportBeginLocOfDeclRefExpr) { .isValid()); } +TEST_P(ASTImporterOptionSpecificTestBase, + TemplateTemplateParmDeclNoDefaultArg) { + Decl *FromTU = getTuDecl(R"( + template typename TT> struct Y {}; + )", + Lang_CXX17); + auto From = FirstDeclMatcher().match( + FromTU, templateTemplateParmDecl(hasName("TT"))); + TemplateTemplateParmDecl *To = Import(From, Lang_CXX17); + ASSERT_FALSE(To->hasDefaultArgument()); +} + +TEST_P(ASTImporterOptionSpecificTestBase, TemplateTemplateParmDeclDefaultArg) { + Decl *FromTU = getTuDecl(R"( + template struct X {}; + template typename TT = X> struct Y {}; + )", + Lang_CXX17); + auto From = FirstDeclMatcher().match( + FromTU, templateTemplateParmDecl(hasName("TT"))); + TemplateTemplateParmDecl *To = Import(From, Lang_CXX17); + ASSERT_TRUE(To->hasDefaultArgument()); + const TemplateArgument &ToDefaultArg = To->getDefaultArgument().getArgument(); + ASSERT_TRUE(To->isTemplateDecl()); + TemplateDecl *ToTemplate = ToDefaultArg.getAsTemplate().getAsTemplateDecl(); + + // Find the default argument template 'X' in the AST and compare it against + // the default argument we got. + auto ToExpectedDecl = FirstDeclMatcher().match( + To->getTranslationUnitDecl(), classTemplateDecl(hasName("X"))); + ASSERT_EQ(ToTemplate, ToExpectedDecl); +} + +TEST_P(ASTImporterOptionSpecificTestBase, NonTypeTemplateParmDeclNoDefaultArg) { + Decl *FromTU = getTuDecl("template struct X {};", Lang_CXX03); + auto From = FirstDeclMatcher().match( + FromTU, nonTypeTemplateParmDecl(hasName("N"))); + NonTypeTemplateParmDecl *To = Import(From, Lang_CXX03); + ASSERT_FALSE(To->hasDefaultArgument()); +} + +TEST_P(ASTImporterOptionSpecificTestBase, NonTypeTemplateParmDeclDefaultArg) { + Decl *FromTU = getTuDecl("template struct X {};", Lang_CXX03); + auto From = FirstDeclMatcher().match( + FromTU, nonTypeTemplateParmDecl(hasName("S"))); + NonTypeTemplateParmDecl *To = Import(From, Lang_CXX03); + ASSERT_TRUE(To->hasDefaultArgument()); + Stmt *ToArg = To->getDefaultArgument(); + ASSERT_TRUE(isa(ToArg)); + ToArg = *ToArg->child_begin(); + ASSERT_TRUE(isa(ToArg)); + ASSERT_EQ(cast(ToArg)->getValue().getLimitedValue(), 1U); +} + TEST_P(ASTImporterOptionSpecificTestBase, ImportOfTemplatedDeclOfClassTemplateDecl) { Decl *FromTU = getTuDecl("template struct S{};", Lang_CXX03); @@ -3104,6 +3177,25 @@ TEST_P(ASTImporterOptionSpecificTestBase, EXPECT_TRUE(ToFun->hasBody()); } +TEST_P(ASTImporterOptionSpecificTestBase, MergeTemplateSpecWithForwardDecl) { + std::string ClassTemplate = + R"( + template + struct X { int m; }; + template<> + struct X { int m; }; + )"; + // Append a forward decl for our template specialization. + getToTuDecl(ClassTemplate + "template<> struct X;", Lang_CXX11); + Decl *FromTU = getTuDecl(ClassTemplate, Lang_CXX11); + auto *FromSpec = FirstDeclMatcher().match( + FromTU, classTemplateSpecializationDecl(hasName("X"), isDefinition())); + auto *ImportedSpec = Import(FromSpec, Lang_CXX11); + // Check that our definition got merged with the existing definition. + EXPECT_TRUE(FromSpec->isThisDeclarationADefinition()); + EXPECT_TRUE(ImportedSpec->isThisDeclarationADefinition()); +} + TEST_P(ASTImporterOptionSpecificTestBase, ODRViolationOfClassTemplateSpecializationsShouldBeReported) { std::string ClassTemplate = diff --git a/clang/unittests/ASTMatchers/ASTMatchersInternalTest.cpp b/clang/unittests/ASTMatchers/ASTMatchersInternalTest.cpp index 2354f45de4096..6fec0d2e73694 100644 --- a/clang/unittests/ASTMatchers/ASTMatchersInternalTest.cpp +++ b/clang/unittests/ASTMatchers/ASTMatchersInternalTest.cpp @@ -70,7 +70,6 @@ AST_POLYMORPHIC_MATCHER_P(polymorphicHas, internal::Matcher, AMatcher) { return Finder->matchesChildOf( Node, AMatcher, Builder, - TraversalKind::TK_IgnoreImplicitCastsAndParentheses, ASTMatchFinder::BK_First); } diff --git a/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp b/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp index 60668af89e97e..b0ec1719daaf9 100644 --- a/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp +++ b/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp @@ -1873,8 +1873,8 @@ void foo() auto Matcher = varDecl(hasInitializer(floatLiteral())); EXPECT_TRUE(notMatches(VarDeclCode, traverse(TK_AsIs, Matcher))); - EXPECT_TRUE(matches(VarDeclCode, - traverse(TK_IgnoreImplicitCastsAndParentheses, Matcher))); + EXPECT_TRUE( + matches(VarDeclCode, traverse(TK_IgnoreUnlessSpelledInSource, Matcher))); auto ParentMatcher = floatLiteral(hasParent(varDecl(hasName("i")))); @@ -2715,14 +2715,14 @@ void foo() )cpp"; EXPECT_TRUE( - matches(Code, traverse(TK_IgnoreImplicitCastsAndParentheses, + matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, callExpr(has(callExpr(traverse( TK_AsIs, callExpr(has(implicitCastExpr( has(floatLiteral()))))))))))); EXPECT_TRUE(matches( Code, - traverse(TK_IgnoreImplicitCastsAndParentheses, + traverse(TK_IgnoreUnlessSpelledInSource, traverse(TK_AsIs, implicitCastExpr(has(floatLiteral())))))); } @@ -2738,8 +2738,7 @@ void constructImplicit() { } )cpp"; - auto Matcher = - traverse(TK_IgnoreImplicitCastsAndParentheses, implicitCastExpr()); + auto Matcher = traverse(TK_IgnoreUnlessSpelledInSource, implicitCastExpr()); // Verfiy that it does not segfault EXPECT_FALSE(matches(Code, Matcher)); @@ -2766,7 +2765,7 @@ void foo() EXPECT_TRUE(matches( Code, functionDecl(anyOf(hasDescendant(Matcher), - traverse(TK_IgnoreImplicitCastsAndParentheses, + traverse(TK_IgnoreUnlessSpelledInSource, functionDecl(hasDescendant(Matcher))))))); } @@ -3370,6 +3369,38 @@ TEST(ForEach, BindsRecursiveCombinations) { std::make_unique>("f", 4))); } +TEST(ForEach, DoesNotIgnoreImplicit) { + StringRef Code = R"cpp( +void foo() +{ + int i = 0; + int b = 4; + i < b; +} +)cpp"; + EXPECT_TRUE(matchAndVerifyResultFalse( + Code, binaryOperator(forEach(declRefExpr().bind("dre"))), + std::make_unique>("dre", 0))); + + EXPECT_TRUE(matchAndVerifyResultTrue( + Code, + binaryOperator(forEach( + implicitCastExpr(hasSourceExpression(declRefExpr().bind("dre"))))), + std::make_unique>("dre", 2))); + + EXPECT_TRUE(matchAndVerifyResultTrue( + Code, + binaryOperator( + forEach(expr(ignoringImplicit(declRefExpr().bind("dre"))))), + std::make_unique>("dre", 2))); + + EXPECT_TRUE(matchAndVerifyResultTrue( + Code, + traverse(TK_IgnoreUnlessSpelledInSource, + binaryOperator(forEach(declRefExpr().bind("dre")))), + std::make_unique>("dre", 2))); +} + TEST(ForEachDescendant, BindsOneNode) { EXPECT_TRUE(matchAndVerifyResultTrue("class C { class D { int x; }; };", recordDecl(hasName("C"), diff --git a/clang/unittests/Format/FormatTestObjC.cpp b/clang/unittests/Format/FormatTestObjC.cpp index a34a0832286b8..c33f93bcf99df 100644 --- a/clang/unittests/Format/FormatTestObjC.cpp +++ b/clang/unittests/Format/FormatTestObjC.cpp @@ -18,6 +18,7 @@ #define DEBUG_TYPE "format-test" using clang::tooling::ReplacementTest; +using testing::internal::ScopedTrace; namespace clang { namespace format { @@ -51,18 +52,24 @@ class FormatTestObjC : public ::testing::Test { return *Result; } - void verifyFormat(StringRef Code) { + void _verifyFormat(const char *File, int Line, StringRef Code) { + ScopedTrace t(File, Line, ::testing::Message() << Code.str()); EXPECT_EQ(Code.str(), format(Code)) << "Expected code is not stable"; EXPECT_EQ(Code.str(), format(test::messUp(Code))); } - void verifyIncompleteFormat(StringRef Code) { + void _verifyIncompleteFormat(const char *File, int Line, StringRef Code) { + ScopedTrace t(File, Line, ::testing::Message() << Code.str()); EXPECT_EQ(Code.str(), format(test::messUp(Code), SC_ExpectIncomplete)); } FormatStyle Style; }; +#define verifyIncompleteFormat(...) \ + _verifyIncompleteFormat(__FILE__, __LINE__, __VA_ARGS__) +#define verifyFormat(...) _verifyFormat(__FILE__, __LINE__, __VA_ARGS__) + TEST(FormatTestObjCStyle, DetectsObjCInHeaders) { auto Style = getStyle("LLVM", "a.h", "none", "@interface\n" @@ -1453,6 +1460,39 @@ TEST_F(FormatTestObjC, BreakLineBeforeNestedBlockParam) { " callback:^(typeof(self) self, NSNumber *u, NSNumber *v) {\n" " u = v;\n" " }]"); + + verifyFormat("[self block:^(void) {\n" + " doStuff();\n" + "} completionHandler:^(void) {\n" + " doStuff();\n" + " [self block:^(void) {\n" + " doStuff();\n" + " } completionHandler:^(void) {\n" + " doStuff();\n" + " }];\n" + "}];"); + + Style.ColumnLimit = 0; + verifyFormat("[[SessionService sharedService] " + "loadWindowWithCompletionBlock:^(SessionWindow *window) {\n" + " if (window) {\n" + " [self windowDidLoad:window];\n" + " } else {\n" + " [self errorLoadingWindow];\n" + " }\n" + "}];"); + verifyFormat("[controller test:^{\n" + " doStuff();\n" + "} withTimeout:5 completionHandler:^{\n" + " doStuff();\n" + "}];"); + verifyFormat( + "[self setupTextFieldSignals:@[\n" + " self.documentWidthField,\n" + " self.documentHeightField,\n" + "] solver:^(NSTextField *textField) {\n" + " return [self.representedObject solveEquationForTextField:textField];\n" + "}];"); } TEST_F(FormatTestObjC, IfNotUnlikely) { diff --git a/clang/unittests/Tooling/TransformerTest.cpp b/clang/unittests/Tooling/TransformerTest.cpp index 773420c015cde..e4fcc210782f9 100644 --- a/clang/unittests/Tooling/TransformerTest.cpp +++ b/clang/unittests/Tooling/TransformerTest.cpp @@ -1353,7 +1353,7 @@ void instantiate() // Changes the 'int' in 'S', but not the 'T' in 'TemplStruct': testRule(makeRule(traverse(TK_IgnoreUnlessSpelledInSource, MatchedField), - changeTo(cat("safe_int ", name("theField")))), + changeTo(cat("safe_int ", name("theField"), ";"))), NonTemplatesInput + TemplatesInput, NonTemplatesExpected + TemplatesInput); @@ -1378,7 +1378,7 @@ void instantiate() // Changes the 'int' in 'S', and (incorrectly) the 'T' in 'TemplStruct': testRule(makeRule(traverse(TK_AsIs, MatchedField), - changeTo(cat("safe_int ", name("theField")))), + changeTo(cat("safe_int ", name("theField"), ";"))), NonTemplatesInput + TemplatesInput, NonTemplatesExpected + IncorrectTemplatesExpected); @@ -1589,7 +1589,7 @@ TEST_F(TransformerTest, MultipleFiles) { Changes[0].getReplacements()); ASSERT_TRUE(static_cast(UpdatedCode)) << "Could not update code: " << llvm::toString(UpdatedCode.takeError()); - EXPECT_EQ(format(*UpdatedCode), format(R"cc(;)cc")); + EXPECT_EQ(format(*UpdatedCode), ""); ASSERT_EQ(Changes[1].getFilePath(), "input.cc"); EXPECT_THAT(Changes[1].getInsertedHeaders(), IsEmpty()); @@ -1598,8 +1598,7 @@ TEST_F(TransformerTest, MultipleFiles) { Source, Changes[1].getReplacements()); ASSERT_TRUE(static_cast(UpdatedCode)) << "Could not update code: " << llvm::toString(UpdatedCode.takeError()); - EXPECT_EQ(format(*UpdatedCode), format(R"cc(#include "input.h" - ;)cc")); + EXPECT_EQ(format(*UpdatedCode), format("#include \"input.h\"\n")); } TEST_F(TransformerTest, AddIncludeMultipleFiles) { diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index 89e4fe0f7dc90..f7e4e98ccf4a5 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -1877,7 +1877,7 @@

C++ defect report implementation status

306 CD1 Ambiguity by class name injection - No + Duplicate of 39 307 diff --git a/compiler-rt/cmake/builtin-config-ix.cmake b/compiler-rt/cmake/builtin-config-ix.cmake index 8c6243a832ccf..16d82b1278785 100644 --- a/compiler-rt/cmake/builtin-config-ix.cmake +++ b/compiler-rt/cmake/builtin-config-ix.cmake @@ -22,13 +22,6 @@ int foo(int x, int y) { } ") -builtin_check_c_compiler_source(COMPILER_RT_HAS_FLOAT16 -" -_Float16 foo(_Float16 x) { - return x; -} -" -) set(ARM64 aarch64) set(ARM32 arm armhf armv6m armv7m armv7em armv7 armv7s armv7k) diff --git a/compiler-rt/include/sanitizer/hwasan_interface.h b/compiler-rt/include/sanitizer/hwasan_interface.h index 4c9ad13aa0cb1..14035c05c6353 100644 --- a/compiler-rt/include/sanitizer/hwasan_interface.h +++ b/compiler-rt/include/sanitizer/hwasan_interface.h @@ -73,6 +73,9 @@ extern "C" { * accessed through the pointer in x, or -1 if the whole range is good. */ intptr_t __hwasan_test_shadow(const volatile void *x, size_t size); + /* Sets the callback function to be called during HWASan error reporting. */ + void __hwasan_set_error_report_callback(void (*callback)(const char *)); + int __sanitizer_posix_memalign(void **memptr, size_t alignment, size_t size); void * __sanitizer_memalign(size_t alignment, size_t size); void * __sanitizer_aligned_alloc(size_t alignment, size_t size); diff --git a/compiler-rt/lib/builtins/CMakeLists.txt b/compiler-rt/lib/builtins/CMakeLists.txt index 8b70c1e827810..3c29bba612e15 100644 --- a/compiler-rt/lib/builtins/CMakeLists.txt +++ b/compiler-rt/lib/builtins/CMakeLists.txt @@ -179,7 +179,6 @@ set(GENERIC_TF_SOURCES divtc3.c divtf3.c extenddftf2.c - extendhftf2.c extendsftf2.c fixtfdi.c fixtfsi.c @@ -198,7 +197,6 @@ set(GENERIC_TF_SOURCES powitf2.c subtf3.c trunctfdf2.c - trunctfhf2.c trunctfsf2.c ) @@ -630,8 +628,6 @@ if (APPLE) else () set(BUILTIN_CFLAGS "") - append_list_if(COMPILER_RT_HAS_FLOAT16 -DCOMPILER_RT_HAS_FLOAT16 BUILTIN_CFLAGS) - append_list_if(COMPILER_RT_HAS_STD_C11_FLAG -std=c11 BUILTIN_CFLAGS) # These flags would normally be added to CMAKE_C_FLAGS by the llvm diff --git a/compiler-rt/lib/builtins/extendhfsf2.c b/compiler-rt/lib/builtins/extendhfsf2.c index 0159ab09d3ebb..7c1a76eb58517 100644 --- a/compiler-rt/lib/builtins/extendhfsf2.c +++ b/compiler-rt/lib/builtins/extendhfsf2.c @@ -12,15 +12,15 @@ // Use a forwarding definition and noinline to implement a poor man's alias, // as there isn't a good cross-platform way of defining one. -COMPILER_RT_ABI NOINLINE float __extendhfsf2(src_t a) { +COMPILER_RT_ABI NOINLINE float __extendhfsf2(uint16_t a) { return __extendXfYf2__(a); } -COMPILER_RT_ABI float __gnu_h2f_ieee(src_t a) { return __extendhfsf2(a); } +COMPILER_RT_ABI float __gnu_h2f_ieee(uint16_t a) { return __extendhfsf2(a); } #if defined(__ARM_EABI__) #if defined(COMPILER_RT_ARMHF_TARGET) -AEABI_RTABI float __aeabi_h2f(src_t a) { return __extendhfsf2(a); } +AEABI_RTABI float __aeabi_h2f(uint16_t a) { return __extendhfsf2(a); } #else COMPILER_RT_ALIAS(__extendhfsf2, __aeabi_h2f) #endif diff --git a/compiler-rt/lib/builtins/extendhftf2.c b/compiler-rt/lib/builtins/extendhftf2.c deleted file mode 100644 index aefe9737d34f9..0000000000000 --- a/compiler-rt/lib/builtins/extendhftf2.c +++ /dev/null @@ -1,23 +0,0 @@ -//===-- lib/extendhftf2.c - half -> quad conversion ---------------*- C -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#define QUAD_PRECISION -#include "fp_lib.h" - -#if defined(CRT_HAS_128BIT) && defined(CRT_LDBL_128BIT) && \ - defined(COMPILER_RT_HAS_FLOAT16) -#define SRC_HALF -#define DST_QUAD -#include "fp_extend_impl.inc" - -COMPILER_RT_ABI long double __extendhftf2(_Float16 a) { - return __extendXfYf2__(a); -} - -#endif diff --git a/compiler-rt/lib/builtins/fp_extend.h b/compiler-rt/lib/builtins/fp_extend.h index aad4436730dd4..fb512672e35ed 100644 --- a/compiler-rt/lib/builtins/fp_extend.h +++ b/compiler-rt/lib/builtins/fp_extend.h @@ -40,11 +40,7 @@ static __inline int src_rep_t_clz(src_rep_t a) { } #elif defined SRC_HALF -#ifdef COMPILER_RT_HAS_FLOAT16 -typedef _Float16 src_t; -#else typedef uint16_t src_t; -#endif typedef uint16_t src_rep_t; #define SRC_REP_C UINT16_C static const int srcSigBits = 10; diff --git a/compiler-rt/lib/builtins/fp_trunc.h b/compiler-rt/lib/builtins/fp_trunc.h index 00595edd5e018..aca4c9b6e6777 100644 --- a/compiler-rt/lib/builtins/fp_trunc.h +++ b/compiler-rt/lib/builtins/fp_trunc.h @@ -50,11 +50,7 @@ typedef uint32_t dst_rep_t; static const int dstSigBits = 23; #elif defined DST_HALF -#ifdef COMPILER_RT_HAS_FLOAT16 -typedef _Float16 dst_t; -#else typedef uint16_t dst_t; -#endif typedef uint16_t dst_rep_t; #define DST_REP_C UINT16_C static const int dstSigBits = 10; diff --git a/compiler-rt/lib/builtins/truncdfhf2.c b/compiler-rt/lib/builtins/truncdfhf2.c index 24c6e62f715f5..90c418a4387ff 100644 --- a/compiler-rt/lib/builtins/truncdfhf2.c +++ b/compiler-rt/lib/builtins/truncdfhf2.c @@ -10,11 +10,11 @@ #define DST_HALF #include "fp_trunc_impl.inc" -COMPILER_RT_ABI dst_t __truncdfhf2(double a) { return __truncXfYf2__(a); } +COMPILER_RT_ABI uint16_t __truncdfhf2(double a) { return __truncXfYf2__(a); } #if defined(__ARM_EABI__) #if defined(COMPILER_RT_ARMHF_TARGET) -AEABI_RTABI dst_t __aeabi_d2h(double a) { return __truncdfhf2(a); } +AEABI_RTABI uint16_t __aeabi_d2h(double a) { return __truncdfhf2(a); } #else COMPILER_RT_ALIAS(__truncdfhf2, __aeabi_d2h) #endif diff --git a/compiler-rt/lib/builtins/truncsfhf2.c b/compiler-rt/lib/builtins/truncsfhf2.c index 379e7cb6f7845..1f17194c38e59 100644 --- a/compiler-rt/lib/builtins/truncsfhf2.c +++ b/compiler-rt/lib/builtins/truncsfhf2.c @@ -12,15 +12,15 @@ // Use a forwarding definition and noinline to implement a poor man's alias, // as there isn't a good cross-platform way of defining one. -COMPILER_RT_ABI NOINLINE dst_t __truncsfhf2(float a) { +COMPILER_RT_ABI NOINLINE uint16_t __truncsfhf2(float a) { return __truncXfYf2__(a); } -COMPILER_RT_ABI dst_t __gnu_f2h_ieee(float a) { return __truncsfhf2(a); } +COMPILER_RT_ABI uint16_t __gnu_f2h_ieee(float a) { return __truncsfhf2(a); } #if defined(__ARM_EABI__) #if defined(COMPILER_RT_ARMHF_TARGET) -AEABI_RTABI dst_t __aeabi_f2h(float a) { return __truncsfhf2(a); } +AEABI_RTABI uint16_t __aeabi_f2h(float a) { return __truncsfhf2(a); } #else COMPILER_RT_ALIAS(__truncsfhf2, __aeabi_f2h) #endif diff --git a/compiler-rt/lib/builtins/trunctfhf2.c b/compiler-rt/lib/builtins/trunctfhf2.c deleted file mode 100644 index 7ed8ea9645fa6..0000000000000 --- a/compiler-rt/lib/builtins/trunctfhf2.c +++ /dev/null @@ -1,23 +0,0 @@ -//===-- lib/trunctfhf2.c - quad -> half conversion ----------------*- C -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is dual licensed under the MIT and the University of Illinois Open -// Source Licenses. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#define QUAD_PRECISION -#include "fp_lib.h" - -#if defined(CRT_HAS_128BIT) && defined(CRT_LDBL_128BIT) && \ - defined(COMPILER_RT_HAS_FLOAT16) -#define SRC_QUAD -#define DST_HALF -#include "fp_trunc_impl.inc" - -COMPILER_RT_ABI _Float16 __trunctfhf2(long double a) { - return __truncXfYf2__(a); -} - -#endif diff --git a/compiler-rt/lib/hwasan/hwasan_interface_internal.h b/compiler-rt/lib/hwasan/hwasan_interface_internal.h index aedda317497b6..25c0f94fe51f5 100644 --- a/compiler-rt/lib/hwasan/hwasan_interface_internal.h +++ b/compiler-rt/lib/hwasan/hwasan_interface_internal.h @@ -222,6 +222,9 @@ SANITIZER_INTERFACE_ATTRIBUTE void *__hwasan_memset(void *s, int c, uptr n); SANITIZER_INTERFACE_ATTRIBUTE void *__hwasan_memmove(void *dest, const void *src, uptr n); + +SANITIZER_INTERFACE_ATTRIBUTE +void __hwasan_set_error_report_callback(void (*callback)(const char *)); } // extern "C" #endif // HWASAN_INTERFACE_INTERNAL_H diff --git a/compiler-rt/lib/hwasan/hwasan_report.cpp b/compiler-rt/lib/hwasan/hwasan_report.cpp index 894a149775f29..4448d9243767a 100644 --- a/compiler-rt/lib/hwasan/hwasan_report.cpp +++ b/compiler-rt/lib/hwasan/hwasan_report.cpp @@ -43,12 +43,16 @@ class ScopedReport { } ~ScopedReport() { + void (*report_cb)(const char *); { BlockingMutexLock lock(&error_message_lock_); - if (fatal) - SetAbortMessage(error_message_.data()); + report_cb = error_report_callback_; error_message_ptr_ = nullptr; } + if (report_cb) + report_cb(error_message_.data()); + if (fatal) + SetAbortMessage(error_message_.data()); if (common_flags()->print_module_map >= 2 || (fatal && common_flags()->print_module_map)) DumpProcessMap(); @@ -66,6 +70,12 @@ class ScopedReport { // overwrite old trailing '\0', keep new trailing '\0' untouched. internal_memcpy(&(*error_message_ptr_)[old_size - 1], msg, len); } + + static void SetErrorReportCallback(void (*callback)(const char *)) { + BlockingMutexLock lock(&error_message_lock_); + error_report_callback_ = callback; + } + private: ScopedErrorReportLock error_report_lock_; InternalMmapVector error_message_; @@ -73,10 +83,12 @@ class ScopedReport { static InternalMmapVector *error_message_ptr_; static BlockingMutex error_message_lock_; + static void (*error_report_callback_)(const char *); }; InternalMmapVector *ScopedReport::error_message_ptr_; BlockingMutex ScopedReport::error_message_lock_; +void (*ScopedReport::error_report_callback_)(const char *); // If there is an active ScopedReport, append to its error message. void AppendToErrorMessageBuffer(const char *buffer) { @@ -650,3 +662,7 @@ void ReportRegisters(uptr *frame, uptr pc) { } } // namespace __hwasan + +void __hwasan_set_error_report_callback(void (*callback)(const char *)) { + __hwasan::ScopedReport::SetErrorReportCallback(callback); +} diff --git a/compiler-rt/lib/profile/InstrProfilingFile.c b/compiler-rt/lib/profile/InstrProfilingFile.c index bd1ec44fc77e1..42ffdae826222 100644 --- a/compiler-rt/lib/profile/InstrProfilingFile.c +++ b/compiler-rt/lib/profile/InstrProfilingFile.c @@ -420,14 +420,12 @@ static void truncateCurrentFile(void) { fclose(File); } -#ifndef _MSC_VER +#if !defined(__Fuchsia__) && !defined(_WIN32) static void assertIsZero(int *i) { if (*i) PROF_WARN("Expected flag to be 0, but got: %d\n", *i); } -#endif -#if !defined(__Fuchsia__) && !defined(_WIN32) /* Write a partial profile to \p Filename, which is required to be backed by * the open file object \p File. */ static int writeProfileWithFileObject(const char *Filename, FILE *File) { diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc index 729eead43c04c..d4b9ea5f7f067 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc +++ b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc @@ -5978,6 +5978,9 @@ void unpoison_file(__sanitizer_FILE *fp) { if (fp->_IO_read_base && fp->_IO_read_base < fp->_IO_read_end) COMMON_INTERCEPTOR_INITIALIZE_RANGE(fp->_IO_read_base, fp->_IO_read_end - fp->_IO_read_base); + if (fp->_IO_write_base && fp->_IO_write_base < fp->_IO_write_end) + COMMON_INTERCEPTOR_INITIALIZE_RANGE(fp->_IO_write_base, + fp->_IO_write_end - fp->_IO_write_base); #endif #endif // SANITIZER_HAS_STRUCT_FILE } @@ -6204,6 +6207,8 @@ INTERCEPTOR(void, _obstack_newchunk, __sanitizer_obstack *obstack, int length) { INTERCEPTOR(int, fflush, __sanitizer_FILE *fp) { void *ctx; COMMON_INTERCEPTOR_ENTER(ctx, fflush, fp); + if (fp) + unpoison_file(fp); int res = REAL(fflush)(fp); // FIXME: handle fp == NULL if (fp) { @@ -6223,6 +6228,8 @@ INTERCEPTOR(int, fclose, __sanitizer_FILE *fp) { COMMON_INTERCEPTOR_ENTER(ctx, fclose, fp); COMMON_INTERCEPTOR_FILE_CLOSE(ctx, fp); const FileMetadata *m = GetInterceptorMetadata(fp); + if (fp) + unpoison_file(fp); int res = REAL(fclose)(fp); if (m) { COMMON_INTERCEPTOR_INITIALIZE_RANGE(*m->addr, *m->size); diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp index 0f1cadfeae395..2ecf87b096a13 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp @@ -513,6 +513,8 @@ static constexpr uptr kExtraRegs[] = {0}; #elif SANITIZER_RISCV64 typedef struct user_regs_struct regs_struct; +// sys/ucontext.h already defines REG_SP as 2. Undefine it first. +#undef REG_SP #define REG_SP sp static constexpr uptr kExtraRegs[] = {0}; #define ARCH_IOVEC_FOR_GETREGSET diff --git a/compiler-rt/test/builtins/CMakeLists.txt b/compiler-rt/test/builtins/CMakeLists.txt index a20a22c66b09c..e3796f840a648 100644 --- a/compiler-rt/test/builtins/CMakeLists.txt +++ b/compiler-rt/test/builtins/CMakeLists.txt @@ -44,9 +44,6 @@ foreach(arch ${BUILTIN_TEST_ARCH}) string(REPLACE ";" " " BUILTINS_TEST_TARGET_CFLAGS "${BUILTINS_TEST_TARGET_CFLAGS}") endif() - append_list_if(COMPILER_RT_HAS_FLOAT16 -DCOMPILER_RT_HAS_FLOAT16 BUILTINS_TEST_TARGET_CFLAGS) - string(REPLACE ";" " " BUILTINS_TEST_TARGET_CFLAGS "${BUILTINS_TEST_TARGET_CFLAGS}") - # Compute builtins available in library and add them as lit features. if(APPLE) # TODO: Support other Apple platforms. diff --git a/compiler-rt/test/builtins/Unit/extendhfsf2_test.c b/compiler-rt/test/builtins/Unit/extendhfsf2_test.c index 86150e8fb0d77..9a5258b2b46f8 100644 --- a/compiler-rt/test/builtins/Unit/extendhfsf2_test.c +++ b/compiler-rt/test/builtins/Unit/extendhfsf2_test.c @@ -5,83 +5,99 @@ #include "fp_test.h" -float __extendhfsf2(TYPE_FP16 a); +float __extendhfsf2(uint16_t a); -int test__extendhfsf2(TYPE_FP16 a, uint32_t expected) +int test__extendhfsf2(uint16_t a, float expected) { float x = __extendhfsf2(a); - int ret = compareResultF(x, expected); + int ret = compareResultH(x, expected); if (ret){ printf("error in test__extendhfsf2(%#.4x) = %f, " - "expected %f\n", toRep16(a), x, fromRep32(expected)); + "expected %f\n", a, x, expected); } return ret; } -char assumption_1[sizeof(TYPE_FP16) * CHAR_BIT == 16] = {0}; +char assumption_1[sizeof(__fp16) * CHAR_BIT == 16] = {0}; int main() { // qNaN - if (test__extendhfsf2(fromRep16(0x7e00), - UINT32_C(0x7fc00000))) + if (test__extendhfsf2(UINT16_C(0x7e00), + makeQNaN32())) return 1; // NaN - if (test__extendhfsf2(fromRep16(0x7f80), - UINT32_C(0x7ff00000))) + if (test__extendhfsf2(UINT16_C(0x7e00), + makeNaN32(UINT32_C(0x8000)))) return 1; // inf - if (test__extendhfsf2(fromRep16(0x7c00), - UINT32_C(0x7f800000))) + if (test__extendhfsf2(UINT16_C(0x7c00), + makeInf32())) return 1; - // -inf - if (test__extendhfsf2(fromRep16(0xfc00), - UINT32_C(0xff800000))) + if (test__extendhfsf2(UINT16_C(0xfc00), + -makeInf32())) return 1; // zero - if (test__extendhfsf2(fromRep16(0x0), - UINT32_C(0x00000000))) + if (test__extendhfsf2(UINT16_C(0x0), + 0.0f)) return 1; - // -zero - if (test__extendhfsf2(fromRep16(0x8000), - UINT32_C(0x80000000))) + if (test__extendhfsf2(UINT16_C(0x8000), + -0.0f)) return 1; - if (test__extendhfsf2(fromRep16(0x4248), - UINT32_C(0x40490000))) + + if (test__extendhfsf2(UINT16_C(0x4248), + 3.1415926535f)) + return 1; + if (test__extendhfsf2(UINT16_C(0xc248), + -3.1415926535f)) return 1; - if (test__extendhfsf2(fromRep16(0xc248), - UINT32_C(0xc0490000))) + if (test__extendhfsf2(UINT16_C(0x7c00), + 0x1.987124876876324p+100f)) return 1; - if (test__extendhfsf2(fromRep16(0x6e62), - UINT32_C(0x45cc4000))) + if (test__extendhfsf2(UINT16_C(0x6e62), + 0x1.988p+12f)) return 1; - if (test__extendhfsf2(fromRep16(0x3c00), - UINT32_C(0x3f800000))) + if (test__extendhfsf2(UINT16_C(0x3c00), + 0x1.0p+0f)) return 1; - if (test__extendhfsf2(fromRep16(0x0400), - UINT32_C(0x38800000))) + if (test__extendhfsf2(UINT16_C(0x0400), + 0x1.0p-14f)) return 1; // denormal - if (test__extendhfsf2(fromRep16(0x0010), - UINT32_C(0x35800000))) + if (test__extendhfsf2(UINT16_C(0x0010), + 0x1.0p-20f)) + return 1; + if (test__extendhfsf2(UINT16_C(0x0001), + 0x1.0p-24f)) return 1; - if (test__extendhfsf2(fromRep16(0x0001), - UINT32_C(0x33800000))) + if (test__extendhfsf2(UINT16_C(0x8001), + -0x1.0p-24f)) return 1; - if (test__extendhfsf2(fromRep16(0x8001), - UINT32_C(0xb3800000))) + if (test__extendhfsf2(UINT16_C(0x0001), + 0x1.5p-25f)) return 1; - if (test__extendhfsf2(fromRep16(0x0001), - UINT32_C(0x33800000))) + // and back to zero + if (test__extendhfsf2(UINT16_C(0x0000), + 0x1.0p-25f)) + return 1; + if (test__extendhfsf2(UINT16_C(0x8000), + -0x1.0p-25f)) return 1; // max (precise) - if (test__extendhfsf2(fromRep16(0x7bff), - UINT32_C(0x477fe000))) + if (test__extendhfsf2(UINT16_C(0x7bff), + 65504.0f)) return 1; // max (rounded) - if (test__extendhfsf2(fromRep16(0x7bff), - UINT32_C(0x477fe000))) + if (test__extendhfsf2(UINT16_C(0x7bff), + 65504.0f)) + return 1; + // max (to +inf) + if (test__extendhfsf2(UINT16_C(0x7c00), + makeInf32())) + return 1; + if (test__extendhfsf2(UINT16_C(0xfc00), + -makeInf32())) return 1; return 0; } diff --git a/compiler-rt/test/builtins/Unit/extendhftf2_test.c b/compiler-rt/test/builtins/Unit/extendhftf2_test.c deleted file mode 100644 index 7d3ea3049e8a1..0000000000000 --- a/compiler-rt/test/builtins/Unit/extendhftf2_test.c +++ /dev/null @@ -1,95 +0,0 @@ -// RUN: %clang_builtins %s %librt -o %t && %run %t -// REQUIRES: librt_has_extendhftf2 - -#include "int_lib.h" -#include - -#if __LDBL_MANT_DIG__ == 113 && defined(COMPILER_RT_HAS_FLOAT16) - -#include "fp_test.h" - -COMPILER_RT_ABI long double __extendhftf2(TYPE_FP16 a); - -int test__extendhftf2(TYPE_FP16 a, uint64_t expectedHi, uint64_t expectedLo) { - long double x = __extendhftf2(a); - int ret = compareResultLD(x, expectedHi, expectedLo); - - if (ret) { - printf("error in test__extendhftf2(%#.4x) = %.20Lf, " - "expected %.20Lf\n", - toRep16(a), x, - fromRep128(expectedHi, expectedLo)); - } - return ret; -} - -char assumption_1[sizeof(TYPE_FP16) * CHAR_BIT == 16] = {0}; - -#endif - -int main() { -#if __LDBL_MANT_DIG__ == 113 && defined(COMPILER_RT_HAS_FLOAT16) - // qNaN - if (test__extendhftf2(makeQNaN16(), - UINT64_C(0x7fff800000000000), - UINT64_C(0x0))) - return 1; - // NaN - if (test__extendhftf2(makeNaN16(UINT16_C(0x0100)), - UINT64_C(0x7fff400000000000), - UINT64_C(0x0))) - return 1; - // inf - if (test__extendhftf2(makeInf16(), - UINT64_C(0x7fff000000000000), - UINT64_C(0x0))) - return 1; - if (test__extendhftf2(-makeInf16(), - UINT64_C(0xffff000000000000), - UINT64_C(0x0))) - return 1; - // zero - if (test__extendhftf2(fromRep16(0x0U), - UINT64_C(0x0), UINT64_C(0x0))) - return 1; - if (test__extendhftf2(fromRep16(0x8000U), - UINT64_C(0x8000000000000000), - UINT64_C(0x0))) - return 1; - // denormal - if (test__extendhftf2(fromRep16(0x0010U), - UINT64_C(0x3feb000000000000), - UINT64_C(0x0000000000000000))) - return 1; - if (test__extendhftf2(fromRep16(0x0001U), - UINT64_C(0x3fe7000000000000), - UINT64_C(0x0000000000000000))) - return 1; - if (test__extendhftf2(fromRep16(0x8001U), - UINT64_C(0xbfe7000000000000), - UINT64_C(0x0000000000000000))) - return 1; - - // pi - if (test__extendhftf2(fromRep16(0x4248U), - UINT64_C(0x4000920000000000), - UINT64_C(0x0000000000000000))) - return 1; - if (test__extendhftf2(fromRep16(0xc248U), - UINT64_C(0xc000920000000000), - UINT64_C(0x0000000000000000))) - return 1; - - if (test__extendhftf2(fromRep16(0x508cU), - UINT64_C(0x4004230000000000), - UINT64_C(0x0))) - return 1; - if (test__extendhftf2(fromRep16(0x1bb7U), - UINT64_C(0x3ff6edc000000000), - UINT64_C(0x0))) - return 1; -#else - printf("skipped\n"); -#endif - return 0; -} diff --git a/compiler-rt/test/builtins/Unit/fp_test.h b/compiler-rt/test/builtins/Unit/fp_test.h index 7c5d5111f4e70..59d4ae5cf9db2 100644 --- a/compiler-rt/test/builtins/Unit/fp_test.h +++ b/compiler-rt/test/builtins/Unit/fp_test.h @@ -3,25 +3,13 @@ #include #include -#ifdef COMPILER_RT_HAS_FLOAT16 -#define TYPE_FP16 _Float16 -#else -#define TYPE_FP16 uint16_t -#endif - enum EXPECTED_RESULT { LESS_0, LESS_EQUAL_0, EQUAL_0, GREATER_0, GREATER_EQUAL_0, NEQUAL_0 }; -static inline TYPE_FP16 fromRep16(uint16_t x) +static inline uint16_t fromRep16(uint16_t x) { -#ifdef COMPILER_RT_HAS_FLOAT16 - TYPE_FP16 ret; - memcpy(&ret, &x, sizeof(ret)); - return ret; -#else return x; -#endif } static inline float fromRep32(uint32_t x) @@ -48,15 +36,9 @@ static inline long double fromRep128(uint64_t hi, uint64_t lo) } #endif -static inline uint16_t toRep16(TYPE_FP16 x) +static inline uint16_t toRep16(uint16_t x) { -#ifdef COMPILER_RT_HAS_FLOAT16 - uint16_t ret; - memcpy(&ret, &x, sizeof(ret)); - return ret; -#else return x; -#endif } static inline uint32_t toRep32(float x) @@ -82,7 +64,7 @@ static inline __uint128_t toRep128(long double x) } #endif -static inline int compareResultH(TYPE_FP16 result, +static inline int compareResultH(uint16_t result, uint16_t expected) { uint16_t rep = toRep16(result); @@ -217,7 +199,7 @@ static inline char *expectedStr(enum EXPECTED_RESULT expected) return ""; } -static inline TYPE_FP16 makeQNaN16(void) +static inline uint16_t makeQNaN16(void) { return fromRep16(0x7e00U); } @@ -239,7 +221,7 @@ static inline long double makeQNaN128(void) } #endif -static inline TYPE_FP16 makeNaN16(uint16_t rand) +static inline uint16_t makeNaN16(uint16_t rand) { return fromRep16(0x7c00U | (rand & 0x7fffU)); } @@ -261,7 +243,7 @@ static inline long double makeNaN128(uint64_t rand) } #endif -static inline TYPE_FP16 makeInf16(void) +static inline uint16_t makeInf16(void) { return fromRep16(0x7c00U); } diff --git a/compiler-rt/test/builtins/Unit/truncdfhf2_test.c b/compiler-rt/test/builtins/Unit/truncdfhf2_test.c index 1990ec9503a7a..74e975eef60b9 100644 --- a/compiler-rt/test/builtins/Unit/truncdfhf2_test.c +++ b/compiler-rt/test/builtins/Unit/truncdfhf2_test.c @@ -5,16 +5,16 @@ #include "fp_test.h" -TYPE_FP16 __truncdfhf2(double a); +uint16_t __truncdfhf2(double a); int test__truncdfhf2(double a, uint16_t expected) { - TYPE_FP16 x = __truncdfhf2(a); + uint16_t x = __truncdfhf2(a); int ret = compareResultH(x, expected); if (ret){ - printf("error in test__truncdfhf2(%lf) = %#.4x, " - "expected %#.4x\n", a, toRep16(x), expected); + printf("error in test__truncdfhf2(%f) = %#.4x, " + "expected %#.4x\n", a, x, fromRep16(expected)); } return ret; } diff --git a/compiler-rt/test/builtins/Unit/truncsfhf2_test.c b/compiler-rt/test/builtins/Unit/truncsfhf2_test.c index c7c8063d52187..7fcccf1a4e69e 100644 --- a/compiler-rt/test/builtins/Unit/truncsfhf2_test.c +++ b/compiler-rt/test/builtins/Unit/truncsfhf2_test.c @@ -5,16 +5,16 @@ #include "fp_test.h" -TYPE_FP16 __truncsfhf2(float a); +uint16_t __truncsfhf2(float a); int test__truncsfhf2(float a, uint16_t expected) { - TYPE_FP16 x = __truncsfhf2(a); + uint16_t x = __truncsfhf2(a); int ret = compareResultH(x, expected); if (ret){ printf("error in test__truncsfhf2(%f) = %#.4x, " - "expected %#.4x\n", a, toRep16(x), expected); + "expected %#.4x\n", a, x, fromRep16(expected)); } return ret; } diff --git a/compiler-rt/test/builtins/Unit/trunctfhf2_test.c b/compiler-rt/test/builtins/Unit/trunctfhf2_test.c deleted file mode 100644 index 9c8c4afd1b835..0000000000000 --- a/compiler-rt/test/builtins/Unit/trunctfhf2_test.c +++ /dev/null @@ -1,125 +0,0 @@ -// RUN: %clang_builtins %s %librt -o %t && %run %t -// REQUIRES: librt_has_trunctfhf2 - -#include "int_lib.h" -#include - -#if __LDBL_MANT_DIG__ == 113 && defined(COMPILER_RT_HAS_FLOAT16) - -#include "fp_test.h" - -TYPE_FP16 __trunctfhf2(long double a); - -int test__trunctfhf2(long double a, uint16_t expected) { - TYPE_FP16 x = __trunctfhf2(a); - int ret = compareResultH(x, expected); - - if (ret) { - printf("error in test__trunctfhf2(%.20Lf) = %#.4x, " - "expected %#.4x\n", - a, toRep16(x), expected); - } - return ret; -} - -char assumption_1[sizeof(TYPE_FP16) * CHAR_BIT == 16] = {0}; - -#endif - -int main() { -#if __LDBL_MANT_DIG__ == 113 && defined(COMPILER_RT_HAS_FLOAT16) - // qNaN - if (test__trunctfhf2(makeQNaN128(), - UINT16_C(0x7e00))) - return 1; - // NaN - if (test__trunctfhf2(makeNaN128(UINT64_C(0x810000000000)), - UINT16_C(0x7e00))) - return 1; - // inf - if (test__trunctfhf2(makeInf128(), - UINT16_C(0x7c00))) - return 1; - if (test__trunctfhf2(-makeInf128(), - UINT16_C(0xfc00))) - return 1; - // zero - if (test__trunctfhf2(0.0L, UINT16_C(0x0))) - return 1; - if (test__trunctfhf2(-0.0L, UINT16_C(0x8000))) - return 1; - - if (test__trunctfhf2(3.1415926535L, - UINT16_C(0x4248))) - return 1; - if (test__trunctfhf2(-3.1415926535L, - UINT16_C(0xc248))) - return 1; - if (test__trunctfhf2(0x1.987124876876324p+100L, - UINT16_C(0x7c00))) - return 1; - if (test__trunctfhf2(0x1.987124876876324p+12L, - UINT16_C(0x6e62))) - return 1; - if (test__trunctfhf2(0x1.0p+0L, - UINT16_C(0x3c00))) - return 1; - if (test__trunctfhf2(0x1.0p-14L, - UINT16_C(0x0400))) - return 1; - // denormal - if (test__trunctfhf2(0x1.0p-20L, - UINT16_C(0x0010))) - return 1; - if (test__trunctfhf2(0x1.0p-24L, - UINT16_C(0x0001))) - return 1; - if (test__trunctfhf2(-0x1.0p-24L, - UINT16_C(0x8001))) - return 1; - if (test__trunctfhf2(0x1.5p-25L, - UINT16_C(0x0001))) - return 1; - // and back to zero - if (test__trunctfhf2(0x1.0p-25L, - UINT16_C(0x0000))) - return 1; - if (test__trunctfhf2(-0x1.0p-25L, - UINT16_C(0x8000))) - return 1; - // max (precise) - if (test__trunctfhf2(65504.0L, - UINT16_C(0x7bff))) - return 1; - // max (rounded) - if (test__trunctfhf2(65519.0L, - UINT16_C(0x7bff))) - return 1; - // max (to +inf) - if (test__trunctfhf2(65520.0L, - UINT16_C(0x7c00))) - return 1; - if (test__trunctfhf2(65536.0L, - UINT16_C(0x7c00))) - return 1; - if (test__trunctfhf2(-65520.0L, - UINT16_C(0xfc00))) - return 1; - - if (test__trunctfhf2(0x1.23a2abb4a2ddee355f36789abcdep+5L, - UINT16_C(0x508f))) - return 1; - if (test__trunctfhf2(0x1.e3d3c45bd3abfd98b76a54cc321fp-9L, - UINT16_C(0x1b8f))) - return 1; - if (test__trunctfhf2(0x1.234eebb5faa678f4488693abcdefp+453L, - UINT16_C(0x7c00))) - return 1; - if (test__trunctfhf2(0x1.edcba9bb8c76a5a43dd21f334634p-43L, - UINT16_C(0x0))) - return 1; -#else - printf("skipped\n"); -#endif - return 0; -} diff --git a/compiler-rt/test/hwasan/TestCases/set-error-report-callback.cpp b/compiler-rt/test/hwasan/TestCases/set-error-report-callback.cpp new file mode 100644 index 0000000000000..736f8a8b923d8 --- /dev/null +++ b/compiler-rt/test/hwasan/TestCases/set-error-report-callback.cpp @@ -0,0 +1,31 @@ +// RUN: %clangxx_hwasan %s -o %t && not %run %t 2>&1 | FileCheck %s + +#include +#include + +#include + +#include "utils.h" + +__attribute__((no_sanitize("hwaddress"))) extern "C" void callback(const char *msg) { + untag_fprintf(stderr, "== error start\n%s\n== error end\n", msg); +} + +int main() { + __hwasan_enable_allocator_tagging(); + __hwasan_set_error_report_callback(&callback); + char *volatile p = (char *)malloc(16); + p[16] = 1; + free(p); + // CHECK: ERROR: HWAddressSanitizer: + // CHECK: WRITE of size 1 at + // CHECK: allocated here: + // CHECK: Memory tags around the buggy address + + // CHECK: == error start + // CHECK: ERROR: HWAddressSanitizer: + // CHECK: WRITE of size 1 at + // CHECK: allocated here: + // CHECK: Memory tags around the buggy address + // CHECK: == error end +} diff --git a/compiler-rt/test/hwasan/TestCases/sizes.cpp b/compiler-rt/test/hwasan/TestCases/sizes.cpp index f397256e52e42..1bfc760e1f9e8 100644 --- a/compiler-rt/test/hwasan/TestCases/sizes.cpp +++ b/compiler-rt/test/hwasan/TestCases/sizes.cpp @@ -49,8 +49,6 @@ int main(int argc, char **argv) { if (!untag_strcmp(argv[1], "malloc")) { void *p = malloc(MallocSize); assert(!p); - p = malloc(kMaxAllowedMallocSize - kChunkHeaderSize); - assert(!p); } else if (!untag_strcmp(argv[1], "calloc")) { // Trigger an overflow in calloc. size_t size = std::numeric_limits::max(); diff --git a/compiler-rt/test/msan/Linux/file.cpp b/compiler-rt/test/msan/Linux/file.cpp new file mode 100644 index 0000000000000..ff1d334e8cbe1 --- /dev/null +++ b/compiler-rt/test/msan/Linux/file.cpp @@ -0,0 +1,29 @@ +// RUN: %clangxx_msan -std=c++11 -O0 %s -o %t && %run %t +// RUN: %clangxx_msan -std=c++11 -fsanitize-memory-track-origins -O0 %s -o %t && %run %t + +#include +#include + +#include + +int main(int argc, char *argv[]) { + FILE *f = fopen(argv[0], "r"); + assert(f); + char buf[50]; + fread(buf, 1, 1, f); + fflush(f); + + assert(f->_IO_read_end > f->_IO_read_base); + __msan_check_mem_is_initialized(f->_IO_read_end, f->_IO_read_end - f->_IO_read_base); + + char tmp_file[1000]; + sprintf(tmp_file, "%s.write.tmp", argv[0]); + + f = fopen(tmp_file, "w+"); + assert(f); + fwrite(buf, 1, 1, f); + fflush(f); + + assert(f->_IO_write_end > f->_IO_write_base); + __msan_check_mem_is_initialized(f->_IO_write_end, f->_IO_write_end - f->_IO_write_base); +} diff --git a/flang/docs/GettingInvolved.md b/flang/docs/GettingInvolved.md index a244fbcee56a0..c8dbbf106fac7 100644 --- a/flang/docs/GettingInvolved.md +++ b/flang/docs/GettingInvolved.md @@ -52,21 +52,36 @@ To understand the status of various developments in Flang please join the respec ### Flang Community Technical Biweekly Call - Technical topics call. -- Join [Flang Community Technical Biweekly Call](https://bluejeans.com/625064848?src=join_info) +- Join [Flang Community Technical Biweekly Call](https://bluejeans.com/284530575) - Time: On Mondays 8:30 Pacific Time, on the weeks alternating with regular Flang Community Biweekly Call. - The agenda is in this [Google Doc](https://docs.google.com/document/d/1Z2U5UAtJ-Dag5wlMaLaW1KRmNgENNAYynJqLW2j2AZQ/). ### LLVM Alias Analysis Technical Call - For people working on improvements to LLVM alias analysis. -- Join [LLVM Alias Analysis Technical Call](https://bluejeans.com/101176001?src=join_info) +- Join [LLVM Alias Analysis Technical Call](https://bluejeans.com/316886064) - Time: Tuesdays 10:00 AM Pacific Time, every 4 weeks. - The agenda is in this [Google Doc](https://docs.google.com/document/d/1ybwEKDVtIbhIhK50qYtwKsL50K-NvB6LfuBsfepBZ9Y/). -### OpenMP Technical Call +### OpenMP in Flang Technical Call - Development updates on OpenMP and OpenACC in the Flang Project. -- Join [OpenMP Technical Call](https://bit.ly/39eQW3o) +- Join [OpenMP in Flang Technical Call](https://bit.ly/39eQW3o) - Time: Weekly call on every Thursdays 8:00 AM Pacific time. - Meeting minutes are [here](https://docs.google.com/document/d/1yA-MeJf6RYY-ZXpdol0t7YoDoqtwAyBhFLr5thu5pFI). - Status tracking [page](https://docs.google.com/spreadsheets/d/1FvHPuSkGbl4mQZRAwCIndvQx9dQboffiD-xD0oqxgU0/edit#gid=0). + +### OpenMP in LLVM Technical Call + +- Development updates on OpenMP (and OpenACC) in the LLVM Project, including Clang, optimization, and runtime work. +- Join [OpenMP in LLVM Technical Call](https://bluejeans.com/544112769//webrtc) +- Time: Weekly call on every Wednesday 7:00 AM Pacific time. +- Meeting minutes are [here](https://docs.google.com/document/d/1Tz8WFN13n7yJ-SCE0Qjqf9LmjGUw0dWO9Ts1ss4YOdg/edit). +- Status tracking [page](https://openmp.llvm.org/docs). + +### Classic Flang Biweekly Technical Call + +- For people working on Classic Flang, the original Flang Fortran 2003/2008 compiler. +- Join [Classic Flang Biweekly Technical Call](https://teams.microsoft.com/l/meetup-join/19%3ameeting_YjM5YjlmNGEtMjA0MS00MTRlLTg5ZjUtOTM1ZGIxOTU2NWQy%40thread.v2) +- The call is held every other Wednesday in the same week as the LLVM Flang Technical call (alternate week with the Flang Community Biweekly call). +- The agenda is available [here](https://docs.google.com/document/d/1-OuiKx4d7O6eLEJDBDKSRnSiUO2rgRR-c2Ga4AkrzOI) diff --git a/flang/docs/OptionComparison.md b/flang/docs/OptionComparison.md index 347a1d6000ee2..1b2525b9200cd 100644 --- a/flang/docs/OptionComparison.md +++ b/flang/docs/OptionComparison.md @@ -8,18 +8,13 @@ # Compiler options comparison -```eval_rst -.. contents:: - :local: -``` - This document catalogs the options processed by F18's peers/competitors. Much of the document is taken up by a set of tables that list the options categorized into different topics. Some of the table headings link to more information about the contents of the tables. For example, the table on **Standards conformance** options links to [notes on Standards conformance](#standards). **There's also important information in the ___[Appendix section](#appendix)___ near the end of the document on how this data was gathered and what ___is___ and ___is not___ included in this document.** Note that compilers may support language features without having an option for them. Such cases are frequently, but not always noted in this document. -## Categorisation of Options +## Categorization of Options @@ -1302,9 +1297,7 @@ GNU is the only compiler with options governing the use of non-standard intrinsi ### What is and is not included -This document focuses on options relevant to the Fortran language. This includes some features (such as recursion) that are only indirectly related. Options related to the following areas are not included: - - +This document focuses on options relevant to the Fortran language definition. This includes some features (such as recursion) that are only indirectly related to the Fortran language definition. Options related to the following areas are not included: * Input/Output * Optimization @@ -1323,13 +1316,11 @@ This document focuses on options relevant to the Fortran language. This include * Threads or parallelization * Profiling and code coverage - ### Data sources Here's the list of compilers surveyed, hot linked to the source of data on it. Note that this is the only mention of the Oracle and NAG compilers in this document. - * [Cray Fortran Reference Manual version 8.7](https://pubs.cray.com/content/S-3901/8.7/cray-fortran-reference-manual/compiler-command-line-options) * IBM (XLF) version 14.1 -- [Compiler Referenc](https://www-01.ibm.com/support/docview.wss?uid=swg27024803&aid=1#page=93)e, [Language Reference](https://www-01.ibm.com/support/docview.wss?uid=swg27024776&aid=1) * [Intel Fortran version 19.0](https://software.intel.com/en-us/fortran-compiler-developer-guide-and-reference-alphabetical-list-of-compiler-options) diff --git a/flang/include/flang/Parser/dump-parse-tree.h b/flang/include/flang/Parser/dump-parse-tree.h index e05c5d5e527e2..61c5bddc0afba 100644 --- a/flang/include/flang/Parser/dump-parse-tree.h +++ b/flang/include/flang/Parser/dump-parse-tree.h @@ -548,7 +548,7 @@ class ParseTreeDumper { NODE(parser, OpenMPDeclareReductionConstruct) NODE(parser, OpenMPDeclareSimdConstruct) NODE(parser, OpenMPDeclareTargetConstruct) - NODE(parser, OmpFlushMemoryClause) + NODE(parser, OmpMemoryOrderClause) NODE(parser, OpenMPFlushConstruct) NODE(parser, OpenMPLoopConstruct) NODE(parser, OpenMPSimpleStandaloneConstruct) diff --git a/flang/include/flang/Parser/parse-tree.h b/flang/include/flang/Parser/parse-tree.h index a64ca06f1b3b4..2dcb92b4a725f 100644 --- a/flang/include/flang/Parser/parse-tree.h +++ b/flang/include/flang/Parser/parse-tree.h @@ -3701,8 +3701,8 @@ struct OpenMPCancelConstruct { // memory-order-clause -> acq_rel // release // acquire -struct OmpFlushMemoryClause { - WRAPPER_CLASS_BOILERPLATE(OmpFlushMemoryClause, llvm::omp::Clause); +struct OmpMemoryOrderClause { + WRAPPER_CLASS_BOILERPLATE(OmpMemoryOrderClause, OmpClause); CharBlock source; }; @@ -3710,7 +3710,7 @@ struct OmpFlushMemoryClause { struct OpenMPFlushConstruct { TUPLE_CLASS_BOILERPLATE(OpenMPFlushConstruct); CharBlock source; - std::tuple, + std::tuple, std::optional> t; }; diff --git a/flang/lib/Lower/OpenMP.cpp b/flang/lib/Lower/OpenMP.cpp index 5b69800176ea7..780aea9664fc0 100644 --- a/flang/lib/Lower/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP.cpp @@ -109,9 +109,9 @@ genOMP(Fortran::lower::AbstractConverter &converter, std::get>( flushConstruct.t)) genObjectList(*ompObjectList, converter, operandRange); - if (std::get>( + if (std::get>( flushConstruct.t)) - TODO("Handle OmpFlushMemoryClause"); + TODO("Handle OmpMemoryOrderClause"); converter.getFirOpBuilder().create( converter.getCurrentLocation(), operandRange); }, diff --git a/flang/lib/Parser/openmp-parsers.cpp b/flang/lib/Parser/openmp-parsers.cpp index 5a7fd3d9c3533..da10f9ffb0a8b 100644 --- a/flang/lib/Parser/openmp-parsers.cpp +++ b/flang/lib/Parser/openmp-parsers.cpp @@ -184,7 +184,8 @@ TYPE_PARSER( parenthesized(Parser{}))) || "GRAINSIZE" >> construct(construct( parenthesized(scalarIntExpr))) || - "HINT" >> construct(parenthesized(constantExpr)) || + "HINT" >> construct( + construct(parenthesized(constantExpr))) || "IF" >> construct(parenthesized(Parser{})) || "INBRANCH" >> construct(construct()) || "IS_DEVICE_PTR" >> construct(construct( @@ -301,18 +302,22 @@ TYPE_PARSER(sourced(construct( TYPE_PARSER(sourced(construct(verbatim("CANCEL"_tok), Parser{}, maybe("IF" >> parenthesized(scalarLogicalExpr))))) -// 2.17.8 Flush construct [OpenMP 5.0] -// flush -> FLUSH [memory-order-clause] [(variable-name-list)] -// memory-order-clause -> acq_rel +// 2.17.7 Atomic construct/2.17.8 Flush construct [OpenMP 5.0] +// memory-order-clause -> +// seq_cst +// acq_rel // release // acquire -TYPE_PARSER(sourced(construct( - "ACQ_REL" >> pure(llvm::omp::Clause::OMPC_acq_rel) || - "RELEASE" >> pure(llvm::omp::Clause::OMPC_release) || - "ACQUIRE" >> pure(llvm::omp::Clause::OMPC_acquire)))) +// relaxed +TYPE_PARSER(sourced(construct( + sourced("SEQ_CST" >> construct(construct()) || + "ACQ_REL" >> construct(construct()) || + "RELEASE" >> construct(construct()) || + "ACQUIRE" >> construct(construct()) || + "RELAXED" >> construct(construct()))))) TYPE_PARSER(sourced(construct(verbatim("FLUSH"_tok), - maybe(Parser{}), + maybe(Parser{}), maybe(parenthesized(Parser{}))))) // Simple Standalone Directives diff --git a/flang/lib/Parser/unparse.cpp b/flang/lib/Parser/unparse.cpp index 2a6b0a6490e4a..56f09f97d98ef 100644 --- a/flang/lib/Parser/unparse.cpp +++ b/flang/lib/Parser/unparse.cpp @@ -2419,25 +2419,11 @@ class UnparseVisitor { Put("\n"); EndOpenMP(); } - void Unparse(const OmpFlushMemoryClause &x) { - switch (x.v) { - case llvm::omp::Clause::OMPC_acq_rel: - Word("ACQ_REL "); - break; - case llvm::omp::Clause::OMPC_release: - Word("RELEASE "); - break; - case llvm::omp::Clause::OMPC_acquire: - Word("ACQUIRE "); - break; - default: - break; - } - } + void Unparse(const OmpMemoryOrderClause &x) { Walk(x.v); } void Unparse(const OpenMPFlushConstruct &x) { BeginOpenMP(); Word("!$OMP FLUSH "); - Walk(std::get>(x.t)); + Walk(std::get>(x.t)); Walk(" (", std::get>(x.t), ")"); Put("\n"); EndOpenMP(); diff --git a/flang/lib/Semantics/check-acc-structure.cpp b/flang/lib/Semantics/check-acc-structure.cpp index 8c05b585dda53..edcb41eae0c51 100644 --- a/flang/lib/Semantics/check-acc-structure.cpp +++ b/flang/lib/Semantics/check-acc-structure.cpp @@ -238,6 +238,15 @@ void AccStructureChecker::Leave(const parser::OpenACCAtomicConstruct &x) { dirContext_.pop_back(); } +void AccStructureChecker::Enter(const parser::OpenACCCacheConstruct &x) { + const auto &verbatim = std::get(x.t); + PushContextAndClauseSets(verbatim.source, llvm::acc::Directive::ACCD_cache); + SetContextDirectiveSource(verbatim.source); +} +void AccStructureChecker::Leave(const parser::OpenACCCacheConstruct &x) { + dirContext_.pop_back(); +} + // Clause checkers CHECK_REQ_SCALAR_INT_CONSTANT_CLAUSE(Collapse, ACCC_collapse) diff --git a/flang/lib/Semantics/check-acc-structure.h b/flang/lib/Semantics/check-acc-structure.h index 04c08b14598c5..e2ea3899c98bf 100644 --- a/flang/lib/Semantics/check-acc-structure.h +++ b/flang/lib/Semantics/check-acc-structure.h @@ -59,6 +59,8 @@ class AccStructureChecker void Leave(const parser::OpenACCWaitConstruct &); void Enter(const parser::OpenACCAtomicConstruct &); void Leave(const parser::OpenACCAtomicConstruct &); + void Enter(const parser::OpenACCCacheConstruct &); + void Leave(const parser::OpenACCCacheConstruct &); // Clauses void Leave(const parser::AccClauseList &); diff --git a/flang/lib/Semantics/check-omp-structure.cpp b/flang/lib/Semantics/check-omp-structure.cpp index 93787672b4440..636471da78d1d 100644 --- a/flang/lib/Semantics/check-omp-structure.cpp +++ b/flang/lib/Semantics/check-omp-structure.cpp @@ -9,6 +9,7 @@ #include "check-omp-structure.h" #include "flang/Parser/parse-tree.h" #include "flang/Semantics/tools.h" +#include namespace Fortran::semantics { @@ -160,8 +161,8 @@ void OmpStructureChecker::Enter(const parser::OmpEndSectionsDirective &x) { switch (dir.v) { // 2.7.2 end-sections -> END SECTIONS [nowait-clause] case llvm::omp::Directive::OMPD_sections: - SetContextDirectiveEnum(llvm::omp::Directive::OMPD_end_sections); - SetContextAllowedOnce(OmpClauseSet{llvm::omp::Clause::OMPC_nowait}); + PushContextAndClauseSets( + dir.source, llvm::omp::Directive::OMPD_end_sections); break; default: // no clauses are allowed @@ -183,8 +184,7 @@ void OmpStructureChecker::Enter(const parser::OpenMPDeclareTargetConstruct &x) { PushContext(dir.source, llvm::omp::Directive::OMPD_declare_target); const auto &spec{std::get(x.t)}; if (std::holds_alternative(spec.u)) { - SetContextAllowed( - OmpClauseSet{llvm::omp::Clause::OMPC_to, llvm::omp::Clause::OMPC_link}); + SetClauseSets(llvm::omp::Directive::OMPD_declare_target); } } @@ -248,17 +248,13 @@ void OmpStructureChecker::Enter(const parser::OmpEndBlockDirective &x) { switch (dir.v) { // 2.7.3 end-single-clause -> copyprivate-clause | // nowait-clause - case llvm::omp::Directive::OMPD_single: { - SetContextDirectiveEnum(llvm::omp::Directive::OMPD_end_single); - OmpClauseSet allowed{llvm::omp::Clause::OMPC_copyprivate}; - SetContextAllowed(allowed); - OmpClauseSet allowedOnce{llvm::omp::Clause::OMPC_nowait}; - SetContextAllowedOnce(allowedOnce); - } break; + case llvm::omp::Directive::OMPD_single: + PushContextAndClauseSets(dir.source, llvm::omp::Directive::OMPD_end_single); + break; // 2.7.4 end-workshare -> END WORKSHARE [nowait-clause] case llvm::omp::Directive::OMPD_workshare: - SetContextDirectiveEnum(llvm::omp::Directive::OMPD_end_workshare); - SetContextAllowed(OmpClauseSet{llvm::omp::Clause::OMPC_nowait}); + PushContextAndClauseSets( + dir.source, llvm::omp::Directive::OMPD_end_workshare); break; default: // no clauses are allowed @@ -300,11 +296,8 @@ void OmpStructureChecker::Leave(const parser::OmpClauseList &) { std::get(clause->u)}; if (orderedClause.v) { - if (FindClause(llvm::omp::Clause::OMPC_linear)) { - context_.Say(clause->source, - "A loop directive may not have both a LINEAR clause and " - "an ORDERED clause with a parameter"_err_en_US); - } + CheckNotAllowedIfClause( + llvm::omp::Clause::OMPC_ordered, {llvm::omp::Clause::OMPC_linear}); if (auto *clause2{FindClause(llvm::omp::Clause::OMPC_collapse)}) { const auto &collapseClause{ @@ -347,19 +340,13 @@ void OmpStructureChecker::Leave(const parser::OmpClauseList &) { } } } - // TODO: A list-item cannot appear in more than one aligned clause } // SIMD // 2.7.3 Single Construct Restriction if (GetContext().directive == llvm::omp::Directive::OMPD_end_single) { - if (auto *clause{FindClause(llvm::omp::Clause::OMPC_copyprivate)}) { - if (FindClause(llvm::omp::Clause::OMPC_nowait)) { - context_.Say(clause->source, - "The COPYPRIVATE clause must not be used with " - "the NOWAIT clause"_err_en_US); - } - } + CheckNotAllowedIfClause( + llvm::omp::Clause::OMPC_copyprivate, {llvm::omp::Clause::OMPC_nowait}); } GetContext().requiredClauses.IterateOverMembers( @@ -385,12 +372,15 @@ CHECK_SIMPLE_CLAUSE(Link, OMPC_link) CHECK_SIMPLE_CLAUSE(Mergeable, OMPC_mergeable) CHECK_SIMPLE_CLAUSE(Nogroup, OMPC_nogroup) CHECK_SIMPLE_CLAUSE(Notinbranch, OMPC_notinbranch) -CHECK_SIMPLE_CLAUSE(Private, OMPC_private) -CHECK_SIMPLE_CLAUSE(Shared, OMPC_shared) CHECK_SIMPLE_CLAUSE(To, OMPC_to) CHECK_SIMPLE_CLAUSE(Uniform, OMPC_uniform) CHECK_SIMPLE_CLAUSE(Untied, OMPC_untied) CHECK_SIMPLE_CLAUSE(UseDevicePtr, OMPC_use_device_ptr) +CHECK_SIMPLE_CLAUSE(AcqRel, OMPC_acq_rel) +CHECK_SIMPLE_CLAUSE(Acquire, OMPC_acquire) +CHECK_SIMPLE_CLAUSE(SeqCst, OMPC_seq_cst) +CHECK_SIMPLE_CLAUSE(Release, OMPC_release) +CHECK_SIMPLE_CLAUSE(Relaxed, OMPC_relaxed) CHECK_REQ_SCALAR_INT_CLAUSE(Grainsize, OMPC_grainsize) CHECK_REQ_SCALAR_INT_CLAUSE(NumTasks, OMPC_num_tasks) @@ -410,7 +400,6 @@ void OmpStructureChecker::Enter(const parser::OmpClause::Ordered &x) { // the parameter of ordered clause is optional if (const auto &expr{x.v}) { RequiresConstantPositiveParameter(llvm::omp::Clause::OMPC_ordered, *expr); - // 2.8.3 Loop SIMD Construct Restriction if (llvm::omp::doSimdSet.test(GetContext().directive)) { context_.Say(GetContext().clauseSource, @@ -421,6 +410,37 @@ void OmpStructureChecker::Enter(const parser::OmpClause::Ordered &x) { } } +void OmpStructureChecker::Enter(const parser::OmpClause::Shared &x) { + CheckAllowed(llvm::omp::Clause::OMPC_shared); + CheckIsVarPartOfAnotherVar(x.v); +} +void OmpStructureChecker::Enter(const parser::OmpClause::Private &x) { + CheckAllowed(llvm::omp::Clause::OMPC_private); + CheckIsVarPartOfAnotherVar(x.v); +} + +void OmpStructureChecker::CheckIsVarPartOfAnotherVar( + const parser::OmpObjectList &objList) { + + for (const auto &ompObject : objList.v) { + std::visit( + common::visitors{ + [&](const parser::Designator &designator) { + if (std::get_if(&designator.u)) { + if ((parser::Unwrap(ompObject)) || + (parser::Unwrap(ompObject))) { + context_.Say(GetContext().clauseSource, + "A variable that is part of another variable (as an " + "array or structure element)" + " cannot appear in a PRIVATE or SHARED clause."_err_en_US); + } + } + }, + [&](const parser::Name &name) {}, + }, + ompObject.u); + } +} // Following clauses have a seperate node in parse-tree.h. CHECK_SIMPLE_PARSER_CLAUSE(OmpAllocateClause, OMPC_allocate) CHECK_SIMPLE_PARSER_CLAUSE(OmpDefaultClause, OMPC_default) @@ -436,13 +456,7 @@ void OmpStructureChecker::Enter(const parser::OmpAlignedClause &x) { if (const auto &expr{ std::get>(x.t)}) { - if (const auto v{GetIntValue(*expr)}) { - if (*v <= 0) { - context_.Say(GetContext().clauseSource, - "The ALIGNMENT parameter of the ALIGNED clause must be " - "a constant positive integer expression"_err_en_US); - } - } + RequiresConstantPositiveParameter(llvm::omp::Clause::OMPC_aligned, *expr); } // 2.8.1 TODO: list-item attribute check } @@ -501,6 +515,28 @@ void OmpStructureChecker::Enter(const parser::OmpLinearClause &x) { } } } + +void OmpStructureChecker::CheckAllowedMapTypes( + const parser::OmpMapType::Type &type, + const std::list &allowedMapTypeList) { + const auto found{std::find( + std::begin(allowedMapTypeList), std::end(allowedMapTypeList), type)}; + if (found == std::end(allowedMapTypeList)) { + std::string commaSeperatedMapTypes; + llvm::interleave( + allowedMapTypeList.begin(), allowedMapTypeList.end(), + [&](const parser::OmpMapType::Type &mapType) { + commaSeperatedMapTypes.append(parser::ToUpperCaseLetters( + parser::OmpMapType::EnumToString(mapType))); + }, + [&] { commaSeperatedMapTypes.append(", "); }); + context_.Say(GetContext().clauseSource, + "Only the %s map types are permitted " + "for MAP clauses on the %s directive"_err_en_US, + commaSeperatedMapTypes, ContextDirectiveAsFortran()); + } +} + void OmpStructureChecker::Enter(const parser::OmpMapClause &x) { CheckAllowed(llvm::omp::Clause::OMPC_map); if (const auto &maptype{std::get>(x.t)}) { @@ -513,31 +549,16 @@ void OmpStructureChecker::Enter(const parser::OmpMapClause &x) { case llvm::omp::Directive::OMPD_target_teams_distribute_simd: case llvm::omp::Directive::OMPD_target_teams_distribute_parallel_do: case llvm::omp::Directive::OMPD_target_teams_distribute_parallel_do_simd: - case llvm::omp::Directive::OMPD_target_data: { - if (type != Type::To && type != Type::From && type != Type::Tofrom && - type != Type::Alloc) { - context_.Say(GetContext().clauseSource, - "Only the TO, FROM, TOFROM, or ALLOC map types are permitted " - "for MAP clauses on the %s directive"_err_en_US, - ContextDirectiveAsFortran()); - } - } break; - case llvm::omp::Directive::OMPD_target_enter_data: { - if (type != Type::To && type != Type::Alloc) { - context_.Say(GetContext().clauseSource, - "Only the TO or ALLOC map types are permitted " - "for MAP clauses on the %s directive"_err_en_US, - ContextDirectiveAsFortran()); - } - } break; - case llvm::omp::Directive::OMPD_target_exit_data: { - if (type != Type::Delete && type != Type::Release && type != Type::From) { - context_.Say(GetContext().clauseSource, - "Only the FROM, RELEASE, or DELETE map types are permitted " - "for MAP clauses on the %s directive"_err_en_US, - ContextDirectiveAsFortran()); - } - } break; + case llvm::omp::Directive::OMPD_target_data: + CheckAllowedMapTypes( + type, {Type::To, Type::From, Type::Tofrom, Type::Alloc}); + break; + case llvm::omp::Directive::OMPD_target_enter_data: + CheckAllowedMapTypes(type, {Type::To, Type::Alloc}); + break; + case llvm::omp::Directive::OMPD_target_exit_data: + CheckAllowedMapTypes(type, {Type::From, Type::Release, Type::Delete}); + break; default: break; } diff --git a/flang/lib/Semantics/check-omp-structure.h b/flang/lib/Semantics/check-omp-structure.h index fbb319f30f9f9..5539ca2566f27 100644 --- a/flang/lib/Semantics/check-omp-structure.h +++ b/flang/lib/Semantics/check-omp-structure.h @@ -150,6 +150,12 @@ class OmpStructureChecker void Enter(const parser::OmpClause::Uniform &); void Enter(const parser::OmpClause::UseDevicePtr &); void Enter(const parser::OmpClause::IsDevicePtr &); + // Memory-order-clause + void Enter(const parser::OmpClause::SeqCst &); + void Enter(const parser::OmpClause::AcqRel &); + void Enter(const parser::OmpClause::Release &); + void Enter(const parser::OmpClause::Acquire &); + void Enter(const parser::OmpClause::Relaxed &); void Enter(const parser::OmpAlignedClause &); void Enter(const parser::OmpAllocateClause &); @@ -171,13 +177,16 @@ class OmpStructureChecker // specific clause related bool ScheduleModifierHasType(const parser::OmpScheduleClause &, const parser::OmpScheduleModifierType::ModType &); - + void CheckAllowedMapTypes(const parser::OmpMapType::Type &, + const std::list &); llvm::StringRef getClauseName(llvm::omp::Clause clause) override; llvm::StringRef getDirectiveName(llvm::omp::Directive directive) override; void CheckDependList(const parser::DataRef &); void CheckDependArraySection( const common::Indirection &, const parser::Name &); + + void CheckIsVarPartOfAnotherVar(const parser::OmpObjectList &objList); }; } // namespace Fortran::semantics #endif // FORTRAN_SEMANTICS_CHECK_OMP_STRUCTURE_H_ diff --git a/flang/lib/Semantics/resolve-directives.cpp b/flang/lib/Semantics/resolve-directives.cpp index 2c0a4c730a98d..f34cb69beca91 100644 --- a/flang/lib/Semantics/resolve-directives.cpp +++ b/flang/lib/Semantics/resolve-directives.cpp @@ -140,6 +140,9 @@ class AccAttributeVisitor : DirectiveAttributeVisitor { GetContext().withinConstruct = true; } + bool Pre(const parser::OpenACCCacheConstruct &); + void Post(const parser::OpenACCCacheConstruct &) { PopContext(); } + void Post(const parser::AccDefaultClause &); bool Pre(const parser::AccClause::Copy &x) { @@ -209,6 +212,7 @@ class AccAttributeVisitor : DirectiveAttributeVisitor { Symbol *DeclareOrMarkOtherAccessEntity(Symbol &, Symbol::Flag); void CheckMultipleAppearances( const parser::Name &, const Symbol &, Symbol::Flag); + void AllowOnlyArrayAndSubArray(const parser::AccObjectList &objectList); }; // Data-sharing and Data-mapping attributes for data-refs in OpenMP construct @@ -305,6 +309,12 @@ class OmpAttributeVisitor : DirectiveAttributeVisitor { } void Post(const parser::Name &); + const parser::OmpClause *associatedClause{nullptr}; + void SetAssociatedClause(const parser::OmpClause &c) { + associatedClause = &c; + } + const parser::OmpClause *GetAssociatedClause() { return associatedClause; } + private: std::int64_t GetAssociatedLoopLevelFromClauses(const parser::OmpClauseList &); @@ -344,7 +354,8 @@ class OmpAttributeVisitor : DirectiveAttributeVisitor { } // Predetermined DSA rules - void PrivatizeAssociatedLoopIndex(const parser::OpenMPLoopConstruct &); + void PrivatizeAssociatedLoopIndexAndCheckLoopLevel( + const parser::OpenMPLoopConstruct &); void ResolveSeqLoopIndexInParallelOrTaskConstruct(const parser::Name &); void ResolveOmpObjectList(const parser::OmpObjectList &, Symbol::Flag); @@ -362,6 +373,8 @@ class OmpAttributeVisitor : DirectiveAttributeVisitor { void CheckDataCopyingClause( const parser::Name &, const Symbol &, Symbol::Flag); + + void CheckAssocLoopLevel(std::int64_t level, const parser::OmpClause *clause); }; template @@ -441,7 +454,6 @@ bool AccAttributeVisitor::Pre(const parser::OpenACCLoopConstruct &x) { bool AccAttributeVisitor::Pre(const parser::OpenACCStandaloneConstruct &x) { const auto &standaloneDir{std::get(x.t)}; switch (standaloneDir.v) { - case llvm::acc::Directive::ACCD_cache: case llvm::acc::Directive::ACCD_enter_data: case llvm::acc::Directive::ACCD_exit_data: case llvm::acc::Directive::ACCD_init: @@ -474,6 +486,64 @@ bool AccAttributeVisitor::Pre(const parser::OpenACCCombinedConstruct &x) { return true; } +static bool IsLastNameArray(const parser::Designator &designator) { + const auto &name{GetLastName(designator)}; + const evaluate::DataRef dataRef{*(name.symbol)}; + return std::visit( + common::visitors{ + [](const evaluate::SymbolRef &ref) { return ref->Rank() > 0; }, + [](const evaluate::ArrayRef &aref) { + return aref.base().IsSymbol() || + aref.base().GetComponent().base().Rank() == 0; + }, + [](const auto &) { return false; }, + }, + dataRef.u); +} + +void AccAttributeVisitor::AllowOnlyArrayAndSubArray( + const parser::AccObjectList &objectList) { + for (const auto &accObject : objectList.v) { + std::visit( + common::visitors{ + [&](const parser::Designator &designator) { + if (!IsLastNameArray(designator)) + context_.Say(designator.source, + "Only array element or subarray are allowed in %s directive"_err_en_US, + parser::ToUpperCaseLetters( + llvm::acc::getOpenACCDirectiveName( + GetContext().directive) + .str())); + }, + [&](const auto &name) { + context_.Say(name.source, + "Only array element or subarray are allowed in %s directive"_err_en_US, + parser::ToUpperCaseLetters( + llvm::acc::getOpenACCDirectiveName(GetContext().directive) + .str())); + }, + }, + accObject.u); + } +} + +bool AccAttributeVisitor::Pre(const parser::OpenACCCacheConstruct &x) { + const auto &verbatim{std::get(x.t)}; + PushContext(verbatim.source, llvm::acc::Directive::ACCD_cache); + ClearDataSharingAttributeObjects(); + + const auto &objectListWithModifier = + std::get(x.t); + const auto &objectList = + std::get(objectListWithModifier.t); + + // 2.10 Cache directive restriction: A var in a cache directive must be a + // single array element or a simple subarray. + AllowOnlyArrayAndSubArray(objectList); + + return true; +} + std::int64_t AccAttributeVisitor::GetAssociatedLoopLevelFromClauses( const parser::AccClauseList &x) { std::int64_t collapseLevel{0}; @@ -777,7 +847,7 @@ bool OmpAttributeVisitor::Pre(const parser::OpenMPLoopConstruct &x) { } ClearDataSharingAttributeObjects(); SetContextAssociatedLoopLevel(GetAssociatedLoopLevelFromClauses(clauseList)); - PrivatizeAssociatedLoopIndex(x); + PrivatizeAssociatedLoopIndexAndCheckLoopLevel(x); return true; } @@ -824,24 +894,32 @@ std::int64_t OmpAttributeVisitor::GetAssociatedLoopLevelFromClauses( const parser::OmpClauseList &x) { std::int64_t orderedLevel{0}; std::int64_t collapseLevel{0}; + + const parser::OmpClause *ordClause{nullptr}; + const parser::OmpClause *collClause{nullptr}; + for (const auto &clause : x.v) { if (const auto *orderedClause{ std::get_if(&clause.u)}) { if (const auto v{EvaluateInt64(context_, orderedClause->v)}) { orderedLevel = *v; } + ordClause = &clause; } if (const auto *collapseClause{ std::get_if(&clause.u)}) { if (const auto v{EvaluateInt64(context_, collapseClause->v)}) { collapseLevel = *v; } + collClause = &clause; } } if (orderedLevel && (!collapseLevel || orderedLevel >= collapseLevel)) { + SetAssociatedClause(*ordClause); return orderedLevel; } else if (!orderedLevel && collapseLevel) { + SetAssociatedClause(*collClause); return collapseLevel; } // orderedLevel < collapseLevel is an error handled in structural checks return 1; // default is outermost loop @@ -855,10 +933,7 @@ std::int64_t OmpAttributeVisitor::GetAssociatedLoopLevelFromClauses( // increment of the associated do-loop. // - The loop iteration variables in the associated do-loops of a simd // construct with multiple associated do-loops are lastprivate. -// -// TODO: revisit after semantics checks are completed for do-loop association of -// collapse and ordered -void OmpAttributeVisitor::PrivatizeAssociatedLoopIndex( +void OmpAttributeVisitor::PrivatizeAssociatedLoopIndexAndCheckLoopLevel( const parser::OpenMPLoopConstruct &x) { std::int64_t level{GetContext().associatedLoopLevel}; if (level <= 0) { @@ -887,7 +962,16 @@ void OmpAttributeVisitor::PrivatizeAssociatedLoopIndex( const auto it{block.begin()}; loop = it != block.end() ? GetDoConstructIf(*it) : nullptr; } - CHECK(level == 0); + CheckAssocLoopLevel(level, GetAssociatedClause()); +} +void OmpAttributeVisitor::CheckAssocLoopLevel( + std::int64_t level, const parser::OmpClause *clause) { + if (clause && level != 0) { + context_.Say(clause->source, + "The value of the parameter in the COLLAPSE or ORDERED clause must" + " not be larger than the number of nested loops" + " following the construct."_err_en_US); + } } bool OmpAttributeVisitor::Pre(const parser::OpenMPSectionsConstruct &x) { diff --git a/flang/test/Semantics/acc-clause-validity.f90 b/flang/test/Semantics/acc-clause-validity.f90 index 3bc36cbe78f30..b2fb57796f3f3 100644 --- a/flang/test/Semantics/acc-clause-validity.f90 +++ b/flang/test/Semantics/acc-clause-validity.f90 @@ -11,6 +11,7 @@ ! 2.14.3 Set ! 2.14.4 Update ! 2.15.1 Routine +! 2.10 Cache ! 2.11 Parallel Loop ! 2.11 Kernels Loop ! 2.11 Serial Loop @@ -21,14 +22,23 @@ program openacc_clause_validity implicit none + type atype + real(8), dimension(10) :: arr + real(8) :: s + end type atype + integer :: i, j, b, gang_size, vector_size, worker_size integer, parameter :: N = 256 integer, dimension(N) :: c logical, dimension(N) :: d, e + integer :: async1 + integer :: wait1, wait2 real :: reduction_r logical :: reduction_l - real(8), dimension(N, N) :: aa + real(8), dimension(N, N) :: aa, bb, cc logical :: ifCondition = .TRUE. + type(atype) :: t + type(atype), dimension(10) :: ta !ERROR: At least one clause is required on the DECLARE directive !$acc declare @@ -99,6 +109,21 @@ program openacc_clause_validity !$acc host_data !$acc end host_data + !$acc host_data use_device(aa) + !$acc end host_data + + !$acc host_data use_device(aa) if(.true.) + !$acc end host_data + + !$acc host_data use_device(aa) if(ifCondition) + !$acc end host_data + + !$acc host_data use_device(aa, bb) if_present + !$acc end host_data + + !$acc host_data use_device(aa, bb) if(.true.) if_present + !$acc end host_data + !ERROR: At least one of DEFAULT_ASYNC, DEVICE_NUM, DEVICE_TYPE clause must appear on the SET directive !$acc set @@ -304,6 +329,107 @@ program openacc_clause_validity end do !$acc end parallel + !$acc parallel async + !$acc end parallel + + !$acc parallel async(1) + !$acc end parallel + + !$acc parallel async(async1) + !$acc end parallel + + !$acc parallel wait + !$acc end parallel + + !$acc parallel wait(1) + !$acc end parallel + + !$acc parallel wait(wait1) + !$acc end parallel + + !$acc parallel wait(1,2) + !$acc end parallel + + !$acc parallel wait(wait1, wait2) + !$acc end parallel + + !$acc parallel num_gangs(8) + !$acc end parallel + + !$acc parallel num_workers(8) + !$acc end parallel + + !$acc parallel vector_length(128) + !$acc end parallel + + !$acc parallel if(.true.) + !$acc end parallel + + !$acc parallel if(ifCondition) + !$acc end parallel + + !$acc parallel self + !$acc end parallel + + !$acc parallel self(.true.) + !$acc end parallel + + !$acc parallel self(ifCondition) + !$acc end parallel + + !$acc parallel copy(aa) copyin(bb) copyout(cc) + !$acc end parallel + + !$acc parallel copy(aa, bb) copyout(zero: cc) + !$acc end parallel + + !$acc parallel present(aa, bb) create(cc) + !$acc end parallel + + !$acc parallel copyin(readonly: aa, bb) create(zero: cc) + !$acc end parallel + + !$acc parallel deviceptr(aa, bb) no_create(cc) + !$acc end parallel + + !$acc parallel attach(aa, bb, cc) + !$acc end parallel + + !$acc parallel private(aa) firstprivate(bb, cc) + !$acc end parallel + + !$acc parallel default(none) + !$acc end parallel + + !$acc parallel default(present) + !$acc end parallel + + !$acc parallel device_type(*) + !$acc end parallel + + !$acc parallel device_type(1) + !$acc end parallel + + !$acc parallel device_type(1, 3) + !$acc end parallel + + !ERROR: Clause PRIVATE is not allowed after clause DEVICE_TYPE on the PARALLEL directive + !ERROR: Clause FIRSTPRIVATE is not allowed after clause DEVICE_TYPE on the PARALLEL directive + !$acc parallel device_type(*) private(aa) firstprivate(bb) + !$acc end parallel + + !$acc parallel device_type(*) async + !$acc end parallel + + !$acc parallel device_type(*) wait + !$acc end parallel + + !$acc parallel device_type(*) num_gangs(8) + !$acc end parallel + + !$acc parallel device_type(1) async device_type(2) wait + !$acc end parallel + !$acc parallel !ERROR: The parameter of the COLLAPSE clause must be a constant positive integer expression !$acc loop collapse(-1) @@ -528,6 +654,28 @@ program openacc_clause_validity i = i + 1 !$acc end atomic !$acc end parallel + t%arr(i) = 2.0 + + !$acc cache(a(i)) + !$acc cache(a(1:2,3:4)) + !$acc cache(a) + !$acc cache(readonly: a, aa) + !$acc cache(readonly: a(i), aa(i, i)) + !$acc cache(t%arr) + !$acc cache(ta(1:2)%arr) + !$acc cache(ta(1:2)%arr(1:4)) + + !ERROR: Only array element or subarray are allowed in CACHE directive + !$acc cache(ta(1:2)%s) + + !ERROR: Only array element or subarray are allowed in CACHE directive + !$acc cache(i) + + !ERROR: Only array element or subarray are allowed in CACHE directive + !$acc cache(t%s) + + !ERROR: Only array element or subarray are allowed in CACHE directive + !$acc cache(/i/) contains diff --git a/flang/test/Semantics/omp-clause-validity01.f90 b/flang/test/Semantics/omp-clause-validity01.f90 index aa51dfd9dcbb0..601e39021e44b 100644 --- a/flang/test/Semantics/omp-clause-validity01.f90 +++ b/flang/test/Semantics/omp-clause-validity01.f90 @@ -62,7 +62,7 @@ a = 3.14 enddo !$omp end parallel - + !$omp task private(b) allocate(b) do i = 1, N z = 2 @@ -80,7 +80,7 @@ z = 2 end do !$omp end target - + !ERROR: ALLOCATE clause is not allowed on the TARGET DATA directive !$omp target data map(from: b) allocate(b) do i = 1, N @@ -214,8 +214,9 @@ a = 3.14 enddo + !ERROR: Clause LINEAR is not allowed if clause ORDERED appears on the DO directive + !ERROR: Clause LINEAR is not allowed if clause ORDERED appears on the DO directive !ERROR: The parameter of the ORDERED clause must be a constant positive integer expression - !ERROR: A loop directive may not have both a LINEAR clause and an ORDERED clause with a parameter !$omp do ordered(1-1) private(b) linear(b) linear(a) do i = 1, N a = 3.14 @@ -319,7 +320,7 @@ !ERROR: LASTPRIVATE clause is not allowed on the SINGLE directive !$omp single private(a) lastprivate(c) a = 3.14 - !ERROR: The COPYPRIVATE clause must not be used with the NOWAIT clause + !ERROR: Clause NOWAIT is not allowed if clause COPYPRIVATE appears on the END SINGLE directive !ERROR: At most one NOWAIT clause can appear on the END SINGLE directive !$omp end single copyprivate(a) nowait nowait c = 2 @@ -365,7 +366,7 @@ a = 3.14 enddo - !ERROR: The ALIGNMENT parameter of the ALIGNED clause must be a constant positive integer expression + !ERROR: The parameter of the ALIGNED clause must be a constant positive integer expression !$omp simd aligned(b:-2) do i = 1, N a = 3.14 @@ -487,6 +488,11 @@ !$omp flush release !$omp flush acquire !$omp flush release (c) + !ERROR: SEQ_CST clause is not allowed on the FLUSH directive + !$omp flush seq_cst + !ERROR: RELAXED clause is not allowed on the FLUSH directive + !$omp flush relaxed + !$omp cancel DO !$omp cancellation point parallel @@ -552,7 +558,7 @@ enddo !ERROR: The parameter of the SIMDLEN clause must be a constant positive integer expression - !ERROR: The ALIGNMENT parameter of the ALIGNED clause must be a constant positive integer expression + !ERROR: The parameter of the ALIGNED clause must be a constant positive integer expression !$omp taskloop simd simdlen(-1) aligned(a:-2) do i = 1, N a = 3.14 diff --git a/flang/test/Semantics/omp-combined-constructs.f90 b/flang/test/Semantics/omp-combined-constructs.f90 index 78821cf0e06cb..afb70b7eda66f 100644 --- a/flang/test/Semantics/omp-combined-constructs.f90 +++ b/flang/test/Semantics/omp-combined-constructs.f90 @@ -205,7 +205,7 @@ program main enddo !$omp end target teams - !ERROR: Only the TO, FROM, TOFROM, or ALLOC map types are permitted for MAP clauses on the TARGET TEAMS directive + !ERROR: Only the TO, FROM, TOFROM, ALLOC map types are permitted for MAP clauses on the TARGET TEAMS directive !$omp target teams map(delete:a) do i = 1, N a(i) = 3.14 @@ -305,7 +305,7 @@ program main enddo !$omp end target teams distribute - !ERROR: Only the TO, FROM, TOFROM, or ALLOC map types are permitted for MAP clauses on the TARGET TEAMS DISTRIBUTE directive + !ERROR: Only the TO, FROM, TOFROM, ALLOC map types are permitted for MAP clauses on the TARGET TEAMS DISTRIBUTE directive !$omp target teams distribute map(delete:a) do i = 1, N a(i) = 3.14 @@ -398,7 +398,7 @@ program main enddo !$omp end target teams distribute parallel do - !ERROR: Only the TO, FROM, TOFROM, or ALLOC map types are permitted for MAP clauses on the TARGET TEAMS DISTRIBUTE PARALLEL DO directive + !ERROR: Only the TO, FROM, TOFROM, ALLOC map types are permitted for MAP clauses on the TARGET TEAMS DISTRIBUTE PARALLEL DO directive !$omp target teams distribute parallel do map(delete:a) do i = 1, N a(i) = 3.14 @@ -498,7 +498,7 @@ program main enddo !$omp end target teams distribute parallel do simd - !ERROR: Only the TO, FROM, TOFROM, or ALLOC map types are permitted for MAP clauses on the TARGET TEAMS DISTRIBUTE PARALLEL DO SIMD directive + !ERROR: Only the TO, FROM, TOFROM, ALLOC map types are permitted for MAP clauses on the TARGET TEAMS DISTRIBUTE PARALLEL DO SIMD directive !$omp target teams distribute parallel do simd map(delete:a) do i = 1, N a(i) = 3.14 diff --git a/flang/test/Semantics/omp-device-constructs.f90 b/flang/test/Semantics/omp-device-constructs.f90 index 7b3eef22524f0..8386744571d2f 100644 --- a/flang/test/Semantics/omp-device-constructs.f90 +++ b/flang/test/Semantics/omp-device-constructs.f90 @@ -109,7 +109,7 @@ program main enddo !$omp end target - !ERROR: Only the TO, FROM, TOFROM, or ALLOC map types are permitted for MAP clauses on the TARGET directive + !ERROR: Only the TO, FROM, TOFROM, ALLOC map types are permitted for MAP clauses on the TARGET directive !$omp target map(delete:a) do i = 1, N a = 3.14 @@ -132,7 +132,7 @@ program main !ERROR: At most one IF clause can appear on the TARGET ENTER DATA directive !$omp target enter data map(to:a) if(.true.) if(.false.) - !ERROR: Only the TO or ALLOC map types are permitted for MAP clauses on the TARGET ENTER DATA directive + !ERROR: Only the TO, ALLOC map types are permitted for MAP clauses on the TARGET ENTER DATA directive !$omp target enter data map(from:a) !$omp target exit data map(delete:a) @@ -140,7 +140,7 @@ program main !ERROR: At most one DEVICE clause can appear on the TARGET EXIT DATA directive !$omp target exit data map(from:a) device(0) device(1) - !ERROR: Only the FROM, RELEASE, or DELETE map types are permitted for MAP clauses on the TARGET EXIT DATA directive + !ERROR: Only the FROM, RELEASE, DELETE map types are permitted for MAP clauses on the TARGET EXIT DATA directive !$omp target exit data map(to:a) !$omp target diff --git a/flang/test/Semantics/omp-do-collapse-positivecases.f90 b/flang/test/Semantics/omp-do-collapse-positivecases.f90 new file mode 100644 index 0000000000000..231d2487f9761 --- /dev/null +++ b/flang/test/Semantics/omp-do-collapse-positivecases.f90 @@ -0,0 +1,36 @@ +!RUN: %S/test_errors.sh %s %t %f18 -fopenmp +! OpenMP Version 4.5 +! 2.7.1 Collapse Clause Positive cases + +!DEF: /omp_docollapse MainProgram +program omp_docollapse + !DEF: /omp_docollapse/i ObjectEntity INTEGER(4) + !DEF: /omp_docollapse/j ObjectEntity INTEGER(4) + !DEF: /omp_docollapse/k ObjectEntity INTEGER(4) + integer i, j, k + !$omp do collapse(2) + !DEF: /omp_docollapse/Block1/i (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) + do i=1,10 + !DEF: /omp_docollapse/Block1/j (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) + do j=1,10 + !REF: /omp_docollapse/k + do k=1,10 + print *, "hello" + end do + end do + end do + !$omp end do + + !REF: /omp_docollapse/i + do i=1,10 + !$omp do collapse(2) + !DEF: /omp_docollapse/Block1/j (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) + do j=1,10 + !DEF: /omp_docollapse/Block1/k (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) + do k=1,10 + print *, "hello" + end do + end do + !$omp end do + end do +end program omp_docollapse diff --git a/flang/test/Semantics/omp-do-collapse.f90 b/flang/test/Semantics/omp-do-collapse.f90 new file mode 100644 index 0000000000000..1db1d56bfca88 --- /dev/null +++ b/flang/test/Semantics/omp-do-collapse.f90 @@ -0,0 +1,26 @@ +!RUN: %S/test_errors.sh %s %t %f18 -fopenmp +! OpenMP Version 4.5 +! 2.7.1 Collapse Clause +program omp_doCollapse + integer:: i,j + !ERROR: The value of the parameter in the COLLAPSE or ORDERED clause must not be larger than the number of nested loops following the construct. + !$omp do collapse(3) + do i = 1,10 + do j = 1, 10 + print *, "hello" + end do + end do + !$omp end do + + do i = 1,10 + do j = 1, 10 + !ERROR: The value of the parameter in the COLLAPSE or ORDERED clause must not be larger than the number of nested loops following the construct. + !$omp do collapse(2) + do k = 1, 10 + print *, "hello" + end do + !$omp end do + end do + end do +end program omp_doCollapse + diff --git a/flang/test/Semantics/omp-do-ordered-positivecases.f90 b/flang/test/Semantics/omp-do-ordered-positivecases.f90 new file mode 100644 index 0000000000000..faed7f3194398 --- /dev/null +++ b/flang/test/Semantics/omp-do-ordered-positivecases.f90 @@ -0,0 +1,67 @@ +!RUN: %S/test_errors.sh %s %t %f18 -fopenmp +! OpenMP Version 4.5 +! 2.7.1 Ordered Clause positive cases. + +!DEF: /omp_doordered MainProgram +program omp_doordered + !DEF: /omp_doordered/i ObjectEntity INTEGER(4) + !DEF: /omp_doordered/j ObjectEntity INTEGER(4) + integer i, j + !$omp do ordered(2) + !DEF: /omp_doordered/Block1/i (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) + do i=1,10 + !DEF: /omp_doordered/Block1/j (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) + do j=1,10 + print *, "hello" + end do + end do + !$omp end do + + !REF: /omp_doordered/i + do i=1,10 + !REF: /omp_doordered/j + do j=1,10 + !$omp do ordered(1) + !DEF: /omp_doordered/Block2/k (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) + do k=1,10 + print *, "hello" + end do + !$omp end do + end do + end do + + !$omp do ordered(1) + !DEF: /omp_doordered/Block3/i (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) + do i=1,10 + !$omp ordered + !REF: /omp_doordered/j + do j=1,10 + print *, "hello" + end do + !$omp end ordered + end do + !$omp end do + + !$omp do collapse(1) ordered(2) + !DEF: /omp_doordered/Block4/i (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) + do i=1,10 + !DEF: /omp_doordered/Block4/j (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) + do j=1,10 + print *, "hello" + end do + end do + !$omp end do + + !$omp parallel num_threads(4) + !$omp do ordered(1) collapse(1) + !DEF: /omp_doordered/Block5/Block1/i (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) + do i=1,10 + !$omp ordered + !DEF: /omp_doordered/Block5/j (OmpPrivate, OmpPreDetermined) HostAssoc INTEGER(4) + do j=1,10 + print *, "hello" + end do + !$omp end ordered + end do + !$omp end parallel +end program omp_doordered diff --git a/flang/test/Semantics/omp-do-ordered.f90 b/flang/test/Semantics/omp-do-ordered.f90 new file mode 100644 index 0000000000000..66c3bc606b314 --- /dev/null +++ b/flang/test/Semantics/omp-do-ordered.f90 @@ -0,0 +1,58 @@ +!RUN: %S/test_errors.sh %s %t %f18 -fopenmp +! OpenMP Version 4.5 +! 2.7.1 Ordered Clause + +program omp_doOrdered + integer:: i,j + !ERROR: The value of the parameter in the COLLAPSE or ORDERED clause must not be larger than the number of nested loops following the construct. + !$omp do ordered(3) + do i = 1,10 + do j = 1, 10 + print *, "hello" + end do + end do + !$omp end do + + do i = 1,10 + do j = 1, 10 + !ERROR: The value of the parameter in the COLLAPSE or ORDERED clause must not be larger than the number of nested loops following the construct. + !$omp do ordered(2) + do k = 1, 10 + print *, "hello" + end do + !$omp end do + end do + end do + + !ERROR: The value of the parameter in the COLLAPSE or ORDERED clause must not be larger than the number of nested loops following the construct. + !$omp do ordered(2) + do i = 1,10 + !$omp ordered + do j = 1, 10 + print *, "hello" + end do + !$omp end ordered + end do + !$omp end do + + !ERROR: The value of the parameter in the COLLAPSE or ORDERED clause must not be larger than the number of nested loops following the construct. + !$omp do collapse(1) ordered(3) + do i = 1,10 + do j = 1, 10 + print *, "hello" + end do + end do + !$omp end do + + !$omp parallel num_threads(4) + !ERROR: The value of the parameter in the COLLAPSE or ORDERED clause must not be larger than the number of nested loops following the construct. + !$omp do ordered(2) collapse(1) + do i = 1,10 + !$omp ordered + do j = 1, 10 + print *, "hello" + end do + !$omp end ordered + end do + !$omp end parallel +end program omp_doOrdered diff --git a/flang/test/Semantics/omp-parallel-private01.f90 b/flang/test/Semantics/omp-parallel-private01.f90 new file mode 100644 index 0000000000000..029c36ffeeb55 --- /dev/null +++ b/flang/test/Semantics/omp-parallel-private01.f90 @@ -0,0 +1,20 @@ +!RUN: %S/test_errors.sh %s %t %f18 -fopenmp +! OpenMP Version 4.5 +! 2.15.3.3 parallel private Clause +program omp_parallel_private + integer :: i, j, a(10), b(10), c(10) + integer :: k = 10 + type my_type + integer :: array(10) + end type my_type + + type(my_type) :: my_var + + !ERROR: A variable that is part of another variable (as an array or structure element) cannot appear in a PRIVATE or SHARED clause. + !$omp parallel private(my_var%array) + do i = 1, 10 + c(i) = a(i) + b(i) + k + my_var%array(i) = k + end do + !$omp end parallel +end program omp_parallel_private diff --git a/flang/test/Semantics/omp-parallel-private02.f90 b/flang/test/Semantics/omp-parallel-private02.f90 new file mode 100644 index 0000000000000..b452b0eb7501d --- /dev/null +++ b/flang/test/Semantics/omp-parallel-private02.f90 @@ -0,0 +1,20 @@ +!RUN: %S/test_errors.sh %s %t %f18 -fopenmp +! OpenMP Version 4.5 +! 2.15.3.3 parallel private Clause +program omp_parallel_private + integer :: i, j, a(10), b(10), c(10) + integer :: k = 10 + integer :: array(10) + + do i = 1, 10 + array(i) = i + end do + + !ERROR: A variable that is part of another variable (as an array or structure element) cannot appear in a PRIVATE or SHARED clause. + !$omp parallel private(array(i)) + do i = 1, 10 + c(i) = a(i) + b(i) + k + array(i) = k + end do + !$omp end parallel +end program omp_parallel_private diff --git a/flang/test/Semantics/omp-parallel-private03.f90 b/flang/test/Semantics/omp-parallel-private03.f90 new file mode 100644 index 0000000000000..18d5bc171027f --- /dev/null +++ b/flang/test/Semantics/omp-parallel-private03.f90 @@ -0,0 +1,28 @@ +!RUN: %S/test_errors.sh %s %t %f18 -fopenmp +! OpenMP Version 4.5 +! 2.15.3.3 parallel private Clause +program omp_parallel_private + integer :: i, j, a(10), b(10), c(10) + integer :: k = 10 + type my_type + integer :: array(10) + end type my_type + + type(my_type) :: my_var + + real :: arr(10) + integer :: intx = 10 + + do i = 1, 10 + arr(i) = 0.0 + end do + + !ERROR: A variable that is part of another variable (as an array or structure element) cannot appear in a PRIVATE or SHARED clause. + !$omp parallel private(arr(i),intx) + do i = 1, 10 + c(i) = a(i) + b(i) + k + my_var%array(i) = k+intx + arr(i) = k + end do + !$omp end parallel +end program omp_parallel_private diff --git a/flang/test/Semantics/omp-parallel-private04.f90 b/flang/test/Semantics/omp-parallel-private04.f90 new file mode 100644 index 0000000000000..9a8765b126354 --- /dev/null +++ b/flang/test/Semantics/omp-parallel-private04.f90 @@ -0,0 +1,28 @@ +!RUN: %S/test_errors.sh %s %t %f18 -fopenmp +! OpenMP Version 4.5 +! 2.15.3.3 parallel private Clause +program omp_parallel_private + integer :: i, j, a(10), b(10), c(10) + integer :: k = 10 + type my_type + integer :: array(10) + end type my_type + + type(my_type) :: my_var + + real :: arr(10) + integer :: intx = 10 + + do i = 1, 10 + arr(i) = 0.0 + end do + + !ERROR: A variable that is part of another variable (as an array or structure element) cannot appear in a PRIVATE or SHARED clause. + !$omp parallel private(arr,intx,my_var%array(1)) + do i = 1, 10 + c(i) = a(i) + b(i) + k + my_var%array(i) = k+intx + arr(i) = k + end do + !$omp end parallel +end program omp_parallel_private diff --git a/flang/test/Semantics/omp-parallel-shared01.f90 b/flang/test/Semantics/omp-parallel-shared01.f90 new file mode 100644 index 0000000000000..7dda194d0e290 --- /dev/null +++ b/flang/test/Semantics/omp-parallel-shared01.f90 @@ -0,0 +1,20 @@ +!RUN: %S/test_errors.sh %s %t %f18 -fopenmp +! OpenMP Version 4.5 +! 2.15.3.2 parallel shared Clause +program omp_parallel_shared + integer :: i, j, a(10), b(10), c(10) + integer :: k = 10 + type my_type + integer :: array(10) + end type my_type + + type(my_type) :: my_var + + !ERROR: A variable that is part of another variable (as an array or structure element) cannot appear in a PRIVATE or SHARED clause. + !$omp parallel shared(my_var%array) + do i = 1, 10 + c(i) = a(i) + b(i) + k + my_var%array(i) = k + end do + !$omp end parallel +end program omp_parallel_shared diff --git a/flang/test/Semantics/omp-parallel-shared02.f90 b/flang/test/Semantics/omp-parallel-shared02.f90 new file mode 100644 index 0000000000000..50b2ece0c0582 --- /dev/null +++ b/flang/test/Semantics/omp-parallel-shared02.f90 @@ -0,0 +1,20 @@ +!RUN: %S/test_errors.sh %s %t %f18 -fopenmp +! OpenMP Version 4.5 +! 2.15.3.2 parallel shared Clause +program omp_parallel_shared + integer :: i, j, a(10), b(10), c(10) + integer :: k = 10 + integer :: array(10) + + do i = 1, 10 + array(i) = i + end do + + !ERROR: A variable that is part of another variable (as an array or structure element) cannot appear in a PRIVATE or SHARED clause. + !$omp parallel shared(array(i)) + do i = 1, 10 + c(i) = a(i) + b(i) + k + array(i) = k + end do + !$omp end parallel +end program omp_parallel_shared diff --git a/flang/test/Semantics/omp-parallel-shared03.f90 b/flang/test/Semantics/omp-parallel-shared03.f90 new file mode 100644 index 0000000000000..386023e452f9f --- /dev/null +++ b/flang/test/Semantics/omp-parallel-shared03.f90 @@ -0,0 +1,28 @@ +!RUN: %S/test_errors.sh %s %t %f18 -fopenmp +! OpenMP Version 4.5 +! 2.15.3.2 parallel shared Clause +program omp_parallel_shared + integer :: i, j, a(10), b(10), c(10) + integer :: k = 10 + type my_type + integer :: array(10) + end type my_type + + type(my_type) :: my_var + + real :: arr(10) + integer :: intx = 10 + + do i = 1, 10 + arr(i) = 0.0 + end do + + !ERROR: A variable that is part of another variable (as an array or structure element) cannot appear in a PRIVATE or SHARED clause. + !$omp parallel shared(arr(i),intx) + do i = 1, 10 + c(i) = a(i) + b(i) + k + my_var%array(i) = k+intx + arr(i) = k + end do + !$omp end parallel +end program omp_parallel_shared diff --git a/flang/test/Semantics/omp-parallel-shared04.f90 b/flang/test/Semantics/omp-parallel-shared04.f90 new file mode 100644 index 0000000000000..3a7c3f940e2af --- /dev/null +++ b/flang/test/Semantics/omp-parallel-shared04.f90 @@ -0,0 +1,28 @@ +!RUN: %S/test_errors.sh %s %t %f18 -fopenmp +! OpenMP Version 4.5 +! 2.15.3.2 parallel shared Clause +program omp_parallel_shared + integer :: i, j, a(10), b(10), c(10) + integer :: k = 10 + type my_type + integer :: array(10) + end type my_type + + type(my_type) :: my_var + + real :: arr(10) + integer :: intx = 10 + + do i = 1, 10 + arr(i) = 0.0 + end do + + !ERROR: A variable that is part of another variable (as an array or structure element) cannot appear in a PRIVATE or SHARED clause. + !$omp parallel shared(arr,intx,my_var%array(1)) + do i = 1, 10 + c(i) = a(i) + b(i) + k + my_var%array(i) = k+intx + arr(i) = k + end do + !$omp end parallel +end program omp_parallel_shared diff --git a/flang/tools/flang-driver/CMakeLists.txt b/flang/tools/flang-driver/CMakeLists.txt index 35b598aa60a4f..4c7ad220d223a 100644 --- a/flang/tools/flang-driver/CMakeLists.txt +++ b/flang/tools/flang-driver/CMakeLists.txt @@ -25,7 +25,6 @@ clang_target_link_libraries(flang-new PRIVATE clangDriver clangBasic - clangFrontend ) install(TARGETS flang-new DESTINATION bin) diff --git a/flang/unittests/Frontend/CMakeLists.txt b/flang/unittests/Frontend/CMakeLists.txt index 42e0c084291e9..8ecdaf3ba9c70 100644 --- a/flang/unittests/Frontend/CMakeLists.txt +++ b/flang/unittests/Frontend/CMakeLists.txt @@ -7,7 +7,6 @@ add_flang_unittest(FlangFrontendTests target_link_libraries(FlangFrontendTests PRIVATE clangBasic - clangFrontend flangFrontend flangFrontendTool FortranParser diff --git a/libc/benchmarks/MemorySizeDistributions.cpp b/libc/benchmarks/MemorySizeDistributions.cpp index 02c3d6414a66e..02c8103d69808 100644 --- a/libc/benchmarks/MemorySizeDistributions.cpp +++ b/libc/benchmarks/MemorySizeDistributions.cpp @@ -28,7 +28,7 @@ static constexpr double kMemsetGoogleQ[] = {0, 0, 0.0043, 0.0055, 0.0033, 0.0025 static constexpr double kMemsetGoogleU[] = {0.1064, 0.0986, 0.0201, 0.0042, 0.1506, 0.0276, 0.0028, 0.0033, 0.3233, 0.1282, 0.011, 0.0035, 0.0015, 0.0019, 0.0005, 0.0007, 0.0143, 0.0152, 0.0005, 0.0146, 0.0013, 0.0001, 0.0001, 0.0067, 0.0054, 0, 0.0001, 0, 0.0006, 0, 0.0002, 0.0062, 0.0005, 0, 0, 0, 0.0004, 0, 0, 0.0001, 0.0003, 0, 0.0001, 0, 0.0001, 0.0001, 0, 0.0021, 0.0002, 0, 0, 0.0001, 0.0001, 0.0001, 0, 0, 0.0001, 0.0001, 0, 0.0001, 0.0001, 0, 0.0001, 0, 0.0092, 0, 0, 0, 0.0002, 0, 0, 0, 0.007, 0, 0, 0, 0, 0, 0, 0.0015, 0.0001, 0.0001, 0, 0, 0.0001, 0, 0, 0, 0.0001, 0, 0, 0.0001, 0, 0, 0, 0.0001, 0.0001, 0, 0, 0.0001, 0, 0, 0, 0, 0.0001, 0.0001, 0.0053, 0, 0.0001, 0, 0, 0, 0.0002, 0, 0, 0, 0.0001, 0, 0, 0.0001, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0.0001, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0.0001, 0, 0.0012, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0003, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0002, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0.0006, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0136, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0002, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0.0002, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0.0002, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0.0001}; // clang-format on -ArrayRef GetMemcpySizeDistributions() { +ArrayRef getMemcpySizeDistributions() { static constexpr MemorySizeDistribution kDistributions[] = { {"memcpy Google A", kMemcpyGoogleA}, {"memcpy Google B", kMemcpyGoogleB}, {"memcpy Google D", kMemcpyGoogleD}, {"memcpy Google L", kMemcpyGoogleL}, @@ -39,7 +39,7 @@ ArrayRef GetMemcpySizeDistributions() { return kDistributions; } -ArrayRef GetMemsetSizeDistributions() { +ArrayRef getMemsetSizeDistributions() { static constexpr MemorySizeDistribution kDistributions[] = { {"memset Google B", kMemsetGoogleB}, {"memset Google D", kMemsetGoogleD}, @@ -49,7 +49,7 @@ ArrayRef GetMemsetSizeDistributions() { return kDistributions; } -ArrayRef GetMemcmpSizeDistributions() { +ArrayRef getMemcmpSizeDistributions() { static constexpr MemorySizeDistribution kDistributions[] = { {"memcmp Google A", kMemcmpGoogleA}, {"memcmp Google B", kMemcmpGoogleB}, {"memcmp Google D", kMemcmpGoogleD}, {"memcmp Google L", kMemcmpGoogleL}, diff --git a/libc/src/math/cosf.cpp b/libc/src/math/cosf.cpp index f02e38bee1338..762e931870a55 100644 --- a/libc/src/math/cosf.cpp +++ b/libc/src/math/cosf.cpp @@ -9,8 +9,8 @@ #include "math_utils.h" #include "sincosf_utils.h" -#include "include/math.h" #include "src/__support/common.h" +#include #include diff --git a/libc/src/math/exp2f.cpp b/libc/src/math/exp2f.cpp index 3d7423d0210b7..38db872f652e0 100644 --- a/libc/src/math/exp2f.cpp +++ b/libc/src/math/exp2f.cpp @@ -9,8 +9,8 @@ #include "exp_utils.h" #include "math_utils.h" -#include "include/math.h" #include "src/__support/common.h" +#include #include diff --git a/libc/src/math/expf.cpp b/libc/src/math/expf.cpp index beda61456b3a5..61c861366cccc 100644 --- a/libc/src/math/expf.cpp +++ b/libc/src/math/expf.cpp @@ -9,8 +9,8 @@ #include "exp_utils.h" #include "math_utils.h" -#include "include/math.h" #include "src/__support/common.h" +#include #include diff --git a/libc/src/math/math_utils.h b/libc/src/math/math_utils.h index 69028b02bb4e2..8d4cf37472d38 100644 --- a/libc/src/math/math_utils.h +++ b/libc/src/math/math_utils.h @@ -9,11 +9,11 @@ #ifndef LLVM_LIBC_SRC_MATH_MATH_UTILS_H #define LLVM_LIBC_SRC_MATH_MATH_UTILS_H -#include "include/errno.h" -#include "include/math.h" #include "src/__support/common.h" #include "src/errno/llvmlibc_errno.h" #include "utils/CPP/TypeTraits.h" +#include +#include #include diff --git a/libc/src/math/sincosf.cpp b/libc/src/math/sincosf.cpp index 710d7b4ffa066..a52af1709123c 100644 --- a/libc/src/math/sincosf.cpp +++ b/libc/src/math/sincosf.cpp @@ -9,8 +9,8 @@ #include "math_utils.h" #include "sincosf_utils.h" -#include "include/math.h" #include "src/__support/common.h" +#include #include diff --git a/libc/src/math/sinf.cpp b/libc/src/math/sinf.cpp index ea15c474ecd52..49496f3173f23 100644 --- a/libc/src/math/sinf.cpp +++ b/libc/src/math/sinf.cpp @@ -9,8 +9,8 @@ #include "math_utils.h" #include "sincosf_utils.h" -#include "include/math.h" #include "src/__support/common.h" +#include #include diff --git a/libc/src/string/strcat.h b/libc/src/string/strcat.h index 517088af8ef03..20e966c675df1 100644 --- a/libc/src/string/strcat.h +++ b/libc/src/string/strcat.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_STRING_STRCAT_H #define LLVM_LIBC_SRC_STRING_STRCAT_H -#include "include/string.h" +#include namespace __llvm_libc { diff --git a/libc/src/string/strcpy.h b/libc/src/string/strcpy.h index 03de39dfac42f..2d2af21c70449 100644 --- a/libc/src/string/strcpy.h +++ b/libc/src/string/strcpy.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_STRING_STRCPY_H #define LLVM_LIBC_SRC_STRING_STRCPY_H -#include "include/string.h" +#include namespace __llvm_libc { diff --git a/libc/src/string/strlen.h b/libc/src/string/strlen.h index 923d1340d26b7..b3ad03f612d0a 100644 --- a/libc/src/string/strlen.h +++ b/libc/src/string/strlen.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_STRING_STRLEN_H #define LLVM_LIBC_SRC_STRING_STRLEN_H -#include "include/string.h" +#include namespace __llvm_libc { diff --git a/libc/test/src/math/FDimTest.h b/libc/test/src/math/FDimTest.h index 5ebe7d38ebe93..f052dc382f163 100644 --- a/libc/test/src/math/FDimTest.h +++ b/libc/test/src/math/FDimTest.h @@ -6,11 +6,11 @@ // //===---------------------------------------------------------------------===// -#include "include/math.h" #include "utils/FPUtil/BasicOperations.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include template class FDimTestTemplate : public __llvm_libc::testing::Test { diff --git a/libc/test/src/math/ILogbTest.h b/libc/test/src/math/ILogbTest.h index 001b419de6cdb..2483907ca8e6b 100644 --- a/libc/test/src/math/ILogbTest.h +++ b/libc/test/src/math/ILogbTest.h @@ -9,10 +9,10 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_ILOGBTEST_H #define LLVM_LIBC_TEST_SRC_MATH_ILOGBTEST_H -#include "include/math.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/ManipulationFunctions.h" #include "utils/UnitTest/Test.h" +#include #include diff --git a/libc/test/src/math/ceil_test.cpp b/libc/test/src/math/ceil_test.cpp index c42bdb99d45b5..0e17b0a7984b4 100644 --- a/libc/test/src/math/ceil_test.cpp +++ b/libc/test/src/math/ceil_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/ceil.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/ceilf_test.cpp b/libc/test/src/math/ceilf_test.cpp index bfd4d52399983..3d7db68eea3b8 100644 --- a/libc/test/src/math/ceilf_test.cpp +++ b/libc/test/src/math/ceilf_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/ceilf.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/ceill_test.cpp b/libc/test/src/math/ceill_test.cpp index ce0cc472eac24..950a976220233 100644 --- a/libc/test/src/math/ceill_test.cpp +++ b/libc/test/src/math/ceill_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/ceill.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/copysign_test.cpp b/libc/test/src/math/copysign_test.cpp index 2bcadbcb7571e..09067fa10b568 100644 --- a/libc/test/src/math/copysign_test.cpp +++ b/libc/test/src/math/copysign_test.cpp @@ -6,11 +6,11 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/copysign.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/copysignf_test.cpp b/libc/test/src/math/copysignf_test.cpp index 4f98c5682f2ac..e43055041dc31 100644 --- a/libc/test/src/math/copysignf_test.cpp +++ b/libc/test/src/math/copysignf_test.cpp @@ -6,11 +6,11 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/copysignf.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/copysignl_test.cpp b/libc/test/src/math/copysignl_test.cpp index e84bc8ddbec6d..47f439f10ca2c 100644 --- a/libc/test/src/math/copysignl_test.cpp +++ b/libc/test/src/math/copysignl_test.cpp @@ -6,11 +6,11 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/copysignl.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/cosf_test.cpp b/libc/test/src/math/cosf_test.cpp index a8c5213676c16..7e7d8df930e0f 100644 --- a/libc/test/src/math/cosf_test.cpp +++ b/libc/test/src/math/cosf_test.cpp @@ -7,7 +7,6 @@ //===----------------------------------------------------------------------===// #include "include/errno.h" -#include "include/math.h" #include "src/errno/llvmlibc_errno.h" #include "src/math/cosf.h" #include "test/src/math/sdcomp26094.h" @@ -18,6 +17,7 @@ #include "utils/FPUtil/FloatProperties.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include #include diff --git a/libc/test/src/math/exp2f_test.cpp b/libc/test/src/math/exp2f_test.cpp index 1204de4770a0f..c7480c390699c 100644 --- a/libc/test/src/math/exp2f_test.cpp +++ b/libc/test/src/math/exp2f_test.cpp @@ -7,7 +7,6 @@ //===----------------------------------------------------------------------===// #include "include/errno.h" -#include "include/math.h" #include "src/errno/llvmlibc_errno.h" #include "src/math/exp2f.h" #include "utils/FPUtil/BitPatterns.h" @@ -16,6 +15,7 @@ #include "utils/FPUtil/FloatProperties.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include #include diff --git a/libc/test/src/math/expf_test.cpp b/libc/test/src/math/expf_test.cpp index e7951a3082787..1243186e94a6b 100644 --- a/libc/test/src/math/expf_test.cpp +++ b/libc/test/src/math/expf_test.cpp @@ -7,7 +7,6 @@ //===----------------------------------------------------------------------===// #include "include/errno.h" -#include "include/math.h" #include "src/errno/llvmlibc_errno.h" #include "src/math/expf.h" #include "utils/FPUtil/BitPatterns.h" @@ -16,6 +15,7 @@ #include "utils/FPUtil/FloatProperties.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include #include diff --git a/libc/test/src/math/fabs_test.cpp b/libc/test/src/math/fabs_test.cpp index 1dff39b07801d..0e1dc48ccfe7b 100644 --- a/libc/test/src/math/fabs_test.cpp +++ b/libc/test/src/math/fabs_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/fabs.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/fabsf_test.cpp b/libc/test/src/math/fabsf_test.cpp index 2243e263a5521..256748c6b87b0 100644 --- a/libc/test/src/math/fabsf_test.cpp +++ b/libc/test/src/math/fabsf_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/fabsf.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/fabsl_test.cpp b/libc/test/src/math/fabsl_test.cpp index 51edd4cea0b7c..fd3a8825c0fa7 100644 --- a/libc/test/src/math/fabsl_test.cpp +++ b/libc/test/src/math/fabsl_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/fabsl.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/fdim_test.cpp b/libc/test/src/math/fdim_test.cpp index a30a1abab9c15..35466640e945e 100644 --- a/libc/test/src/math/fdim_test.cpp +++ b/libc/test/src/math/fdim_test.cpp @@ -8,11 +8,11 @@ #include "FDimTest.h" -#include "include/math.h" #include "src/math/fdim.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using FDimTest = FDimTestTemplate; diff --git a/libc/test/src/math/fdimf_test.cpp b/libc/test/src/math/fdimf_test.cpp index 1a6d640789fe3..f2647e01e150e 100644 --- a/libc/test/src/math/fdimf_test.cpp +++ b/libc/test/src/math/fdimf_test.cpp @@ -8,11 +8,11 @@ #include "FDimTest.h" -#include "include/math.h" #include "src/math/fdimf.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using FDimTest = FDimTestTemplate; diff --git a/libc/test/src/math/fdiml_test.cpp b/libc/test/src/math/fdiml_test.cpp index 3453f7cd92fb2..8e19a77990da5 100644 --- a/libc/test/src/math/fdiml_test.cpp +++ b/libc/test/src/math/fdiml_test.cpp @@ -8,11 +8,11 @@ #include "FDimTest.h" -#include "include/math.h" #include "src/math/fdiml.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using FDimTest = FDimTestTemplate; diff --git a/libc/test/src/math/floor_test.cpp b/libc/test/src/math/floor_test.cpp index d0e26541d1117..588b2a3dd56b3 100644 --- a/libc/test/src/math/floor_test.cpp +++ b/libc/test/src/math/floor_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/floor.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/floorf_test.cpp b/libc/test/src/math/floorf_test.cpp index 8de4ab24fd9fe..5a8e8cf635060 100644 --- a/libc/test/src/math/floorf_test.cpp +++ b/libc/test/src/math/floorf_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/floorf.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/floorl_test.cpp b/libc/test/src/math/floorl_test.cpp index 9f70cadc25db2..3ab5d5f8201bf 100644 --- a/libc/test/src/math/floorl_test.cpp +++ b/libc/test/src/math/floorl_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/floorl.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/fmax_test.cpp b/libc/test/src/math/fmax_test.cpp index 5579bb67e7dd8..1114307e60a82 100644 --- a/libc/test/src/math/fmax_test.cpp +++ b/libc/test/src/math/fmax_test.cpp @@ -6,11 +6,11 @@ // //===---------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/fmax.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/fmaxf_test.cpp b/libc/test/src/math/fmaxf_test.cpp index d4d92bf2a30dc..3e81c9979114f 100644 --- a/libc/test/src/math/fmaxf_test.cpp +++ b/libc/test/src/math/fmaxf_test.cpp @@ -6,11 +6,11 @@ // //===---------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/fmaxf.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/fmaxl_test.cpp b/libc/test/src/math/fmaxl_test.cpp index be9b0c830b148..ce48b5dce76ff 100644 --- a/libc/test/src/math/fmaxl_test.cpp +++ b/libc/test/src/math/fmaxl_test.cpp @@ -6,11 +6,11 @@ // //===---------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/fmaxl.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/fmin_test.cpp b/libc/test/src/math/fmin_test.cpp index 67d75506b1fc1..89a25beba8d75 100644 --- a/libc/test/src/math/fmin_test.cpp +++ b/libc/test/src/math/fmin_test.cpp @@ -6,11 +6,11 @@ // //===---------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/fmin.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/fminf_test.cpp b/libc/test/src/math/fminf_test.cpp index a40bf021c9b06..6772fb5e96a3d 100644 --- a/libc/test/src/math/fminf_test.cpp +++ b/libc/test/src/math/fminf_test.cpp @@ -6,11 +6,11 @@ // //===---------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/fminf.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/fminl_test.cpp b/libc/test/src/math/fminl_test.cpp index 274ef296ce410..20c88d410a47a 100644 --- a/libc/test/src/math/fminl_test.cpp +++ b/libc/test/src/math/fminl_test.cpp @@ -6,11 +6,11 @@ // //===---------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/fminl.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/frexp_test.cpp b/libc/test/src/math/frexp_test.cpp index 360bbf237560e..ce118753cf85d 100644 --- a/libc/test/src/math/frexp_test.cpp +++ b/libc/test/src/math/frexp_test.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/frexp.h" #include "utils/FPUtil/BasicOperations.h" #include "utils/FPUtil/BitPatterns.h" @@ -16,6 +15,7 @@ #include "utils/FPUtil/FloatProperties.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; using __llvm_libc::fputil::valueAsBits; diff --git a/libc/test/src/math/frexpf_test.cpp b/libc/test/src/math/frexpf_test.cpp index 1bf0c36cf165f..ba9fedad3b445 100644 --- a/libc/test/src/math/frexpf_test.cpp +++ b/libc/test/src/math/frexpf_test.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/frexpf.h" #include "utils/FPUtil/BasicOperations.h" #include "utils/FPUtil/BitPatterns.h" @@ -16,6 +15,7 @@ #include "utils/FPUtil/FloatProperties.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; using __llvm_libc::fputil::valueAsBits; diff --git a/libc/test/src/math/frexpl_test.cpp b/libc/test/src/math/frexpl_test.cpp index 9846bb84ae279..34d3b1b47e0e9 100644 --- a/libc/test/src/math/frexpl_test.cpp +++ b/libc/test/src/math/frexpl_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/frexpl.h" #include "utils/FPUtil/BasicOperations.h" #include "utils/FPUtil/FPBits.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/hypotf_test.cpp b/libc/test/src/math/hypotf_test.cpp index eb06c799fee3a..1769307099a9c 100644 --- a/libc/test/src/math/hypotf_test.cpp +++ b/libc/test/src/math/hypotf_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/hypotf.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; using UIntType = FPBits::UIntType; diff --git a/libc/test/src/math/ilogb_test.cpp b/libc/test/src/math/ilogb_test.cpp index b17feb8a10157..7fb3b70f8fb42 100644 --- a/libc/test/src/math/ilogb_test.cpp +++ b/libc/test/src/math/ilogb_test.cpp @@ -8,12 +8,12 @@ #include "ILogbTest.h" -#include "include/math.h" #include "src/math/ilogb.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/ManipulationFunctions.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include TEST_F(ILogbTest, SpecialNumbers_ilogb) { testSpecialNumbers(&__llvm_libc::ilogb); diff --git a/libc/test/src/math/ilogbf_test.cpp b/libc/test/src/math/ilogbf_test.cpp index e449b8dfa4dc2..5917a8ca8ea47 100644 --- a/libc/test/src/math/ilogbf_test.cpp +++ b/libc/test/src/math/ilogbf_test.cpp @@ -8,12 +8,12 @@ #include "ILogbTest.h" -#include "include/math.h" #include "src/math/ilogbf.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/ManipulationFunctions.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include TEST_F(ILogbTest, SpecialNumbers_ilogbf) { testSpecialNumbers(&__llvm_libc::ilogbf); diff --git a/libc/test/src/math/ilogbl_test.cpp b/libc/test/src/math/ilogbl_test.cpp index bae9061cb1621..349c2a71ead98 100644 --- a/libc/test/src/math/ilogbl_test.cpp +++ b/libc/test/src/math/ilogbl_test.cpp @@ -8,12 +8,12 @@ #include "ILogbTest.h" -#include "include/math.h" #include "src/math/ilogbl.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/ManipulationFunctions.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/UnitTest/Test.h" +#include using RunContext = __llvm_libc::testing::RunContext; diff --git a/libc/test/src/math/logb_test.cpp b/libc/test/src/math/logb_test.cpp index 5f8e753874897..0f9d4d07cdef6 100644 --- a/libc/test/src/math/logb_test.cpp +++ b/libc/test/src/math/logb_test.cpp @@ -6,13 +6,13 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/logb.h" #include "utils/FPUtil/BitPatterns.h" #include "utils/FPUtil/FloatOperations.h" #include "utils/FPUtil/FloatProperties.h" #include "utils/FPUtil/ManipulationFunctions.h" #include "utils/UnitTest/Test.h" +#include using __llvm_libc::fputil::valueAsBits; using __llvm_libc::fputil::valueFromBits; diff --git a/libc/test/src/math/logbf_test.cpp b/libc/test/src/math/logbf_test.cpp index 7cd690ce38690..41ffac5c7b9e0 100644 --- a/libc/test/src/math/logbf_test.cpp +++ b/libc/test/src/math/logbf_test.cpp @@ -6,13 +6,13 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/logbf.h" #include "utils/FPUtil/BitPatterns.h" #include "utils/FPUtil/FloatOperations.h" #include "utils/FPUtil/FloatProperties.h" #include "utils/FPUtil/ManipulationFunctions.h" #include "utils/UnitTest/Test.h" +#include using __llvm_libc::fputil::valueAsBits; using __llvm_libc::fputil::valueFromBits; diff --git a/libc/test/src/math/logbl_test.cpp b/libc/test/src/math/logbl_test.cpp index 4cdc6ce61d9a2..4a12ec6a0f370 100644 --- a/libc/test/src/math/logbl_test.cpp +++ b/libc/test/src/math/logbl_test.cpp @@ -6,11 +6,11 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/logbl.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/ManipulationFunctions.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/modf_test.cpp b/libc/test/src/math/modf_test.cpp index 774ad8b63f860..e9d1572e93914 100644 --- a/libc/test/src/math/modf_test.cpp +++ b/libc/test/src/math/modf_test.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/modf.h" #include "utils/FPUtil/BasicOperations.h" #include "utils/FPUtil/BitPatterns.h" @@ -14,6 +13,7 @@ #include "utils/FPUtil/FloatProperties.h" #include "utils/FPUtil/NearestIntegerOperations.h" #include "utils/UnitTest/Test.h" +#include using __llvm_libc::fputil::valueAsBits; using __llvm_libc::fputil::valueFromBits; diff --git a/libc/test/src/math/modff_test.cpp b/libc/test/src/math/modff_test.cpp index 66244b8ac8927..2fd15f7df90d0 100644 --- a/libc/test/src/math/modff_test.cpp +++ b/libc/test/src/math/modff_test.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/modff.h" #include "utils/FPUtil/BasicOperations.h" #include "utils/FPUtil/BitPatterns.h" @@ -14,6 +13,7 @@ #include "utils/FPUtil/FloatProperties.h" #include "utils/FPUtil/NearestIntegerOperations.h" #include "utils/UnitTest/Test.h" +#include using __llvm_libc::fputil::valueAsBits; using __llvm_libc::fputil::valueFromBits; diff --git a/libc/test/src/math/modfl_test.cpp b/libc/test/src/math/modfl_test.cpp index 2e47880d1ea89..d20cb4f741393 100644 --- a/libc/test/src/math/modfl_test.cpp +++ b/libc/test/src/math/modfl_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/modfl.h" #include "utils/FPUtil/BasicOperations.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/NearestIntegerOperations.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/remquo_test.cpp b/libc/test/src/math/remquo_test.cpp index 44812f1c1d533..197d970690017 100644 --- a/libc/test/src/math/remquo_test.cpp +++ b/libc/test/src/math/remquo_test.cpp @@ -6,13 +6,13 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/remquo.h" #include "utils/FPUtil/BasicOperations.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; using UIntType = FPBits::UIntType; diff --git a/libc/test/src/math/remquof_test.cpp b/libc/test/src/math/remquof_test.cpp index 81c262f5320c2..4ede7fb3feeca 100644 --- a/libc/test/src/math/remquof_test.cpp +++ b/libc/test/src/math/remquof_test.cpp @@ -6,13 +6,13 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/remquof.h" #include "utils/FPUtil/BasicOperations.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; using UIntType = FPBits::UIntType; diff --git a/libc/test/src/math/remquol_test.cpp b/libc/test/src/math/remquol_test.cpp index 63500cb519a32..1539aabead95c 100644 --- a/libc/test/src/math/remquol_test.cpp +++ b/libc/test/src/math/remquol_test.cpp @@ -6,13 +6,13 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/remquol.h" #include "utils/FPUtil/BasicOperations.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; using UIntType = FPBits::UIntType; diff --git a/libc/test/src/math/round_test.cpp b/libc/test/src/math/round_test.cpp index 8d9114544383a..bc611d4559a11 100644 --- a/libc/test/src/math/round_test.cpp +++ b/libc/test/src/math/round_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/round.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/roundf_test.cpp b/libc/test/src/math/roundf_test.cpp index 93252da9efe34..4a49c095b8827 100644 --- a/libc/test/src/math/roundf_test.cpp +++ b/libc/test/src/math/roundf_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/roundf.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/roundl_test.cpp b/libc/test/src/math/roundl_test.cpp index 424dd78a0ab51..7b2eb6f90c8eb 100644 --- a/libc/test/src/math/roundl_test.cpp +++ b/libc/test/src/math/roundl_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/roundl.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/sincosf_test.cpp b/libc/test/src/math/sincosf_test.cpp index 9e5ee062cc8d6..9a73dc74ae428 100644 --- a/libc/test/src/math/sincosf_test.cpp +++ b/libc/test/src/math/sincosf_test.cpp @@ -7,7 +7,6 @@ //===----------------------------------------------------------------------===// #include "include/errno.h" -#include "include/math.h" #include "src/errno/llvmlibc_errno.h" #include "src/math/sincosf.h" #include "test/src/math/sdcomp26094.h" @@ -18,6 +17,7 @@ #include "utils/FPUtil/FloatProperties.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include #include diff --git a/libc/test/src/math/sinf_test.cpp b/libc/test/src/math/sinf_test.cpp index 67dca0072deb4..1ec5636e6db57 100644 --- a/libc/test/src/math/sinf_test.cpp +++ b/libc/test/src/math/sinf_test.cpp @@ -7,7 +7,6 @@ //===----------------------------------------------------------------------===// #include "include/errno.h" -#include "include/math.h" #include "src/errno/llvmlibc_errno.h" #include "src/math/sinf.h" #include "test/src/math/sdcomp26094.h" @@ -18,6 +17,7 @@ #include "utils/FPUtil/FloatProperties.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include #include diff --git a/libc/test/src/math/sqrt_test.cpp b/libc/test/src/math/sqrt_test.cpp index 1fda63e169082..beec7adcb7f93 100644 --- a/libc/test/src/math/sqrt_test.cpp +++ b/libc/test/src/math/sqrt_test.cpp @@ -6,11 +6,11 @@ // //===---------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/sqrt.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" +#include using FPBits = __llvm_libc::fputil::FPBits; using UIntType = typename FPBits::UIntType; diff --git a/libc/test/src/math/sqrtf_test.cpp b/libc/test/src/math/sqrtf_test.cpp index 1e9eda048bf7d..b64b0d0376230 100644 --- a/libc/test/src/math/sqrtf_test.cpp +++ b/libc/test/src/math/sqrtf_test.cpp @@ -6,11 +6,11 @@ // //===---------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/sqrtf.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" +#include using FPBits = __llvm_libc::fputil::FPBits; using UIntType = typename FPBits::UIntType; diff --git a/libc/test/src/math/sqrtl_test.cpp b/libc/test/src/math/sqrtl_test.cpp index 36b3030355ba2..4fe03df57eb65 100644 --- a/libc/test/src/math/sqrtl_test.cpp +++ b/libc/test/src/math/sqrtl_test.cpp @@ -6,11 +6,11 @@ // //===---------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/sqrtl.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" +#include using FPBits = __llvm_libc::fputil::FPBits; using UIntType = typename FPBits::UIntType; diff --git a/libc/test/src/math/trunc_test.cpp b/libc/test/src/math/trunc_test.cpp index 0a322facab39b..981a729b4e297 100644 --- a/libc/test/src/math/trunc_test.cpp +++ b/libc/test/src/math/trunc_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/trunc.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/truncf_test.cpp b/libc/test/src/math/truncf_test.cpp index 0732614f74401..416eb7c7d212e 100644 --- a/libc/test/src/math/truncf_test.cpp +++ b/libc/test/src/math/truncf_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/truncf.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/math/truncl_test.cpp b/libc/test/src/math/truncl_test.cpp index ab05d01905c4a..1220b7a7cc884 100644 --- a/libc/test/src/math/truncl_test.cpp +++ b/libc/test/src/math/truncl_test.cpp @@ -6,12 +6,12 @@ // //===----------------------------------------------------------------------===// -#include "include/math.h" #include "src/math/truncl.h" #include "utils/FPUtil/FPBits.h" #include "utils/FPUtil/TestHelpers.h" #include "utils/MPFRWrapper/MPFRUtils.h" #include "utils/UnitTest/Test.h" +#include using FPBits = __llvm_libc::fputil::FPBits; diff --git a/libc/test/src/string/strnlen_test.cpp b/libc/test/src/string/strnlen_test.cpp index 9d8616bc8bd7d..b15ec2f8cef2e 100644 --- a/libc/test/src/string/strnlen_test.cpp +++ b/libc/test/src/string/strnlen_test.cpp @@ -1,4 +1,4 @@ -//===-- Unittests for strnlen----------------------------------------------===// +//===-- Unittests for strnlen ---------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/libc/utils/UnitTest/CMakeLists.txt b/libc/utils/UnitTest/CMakeLists.txt index 9c7b48aea4f94..1c9753e62a593 100644 --- a/libc/utils/UnitTest/CMakeLists.txt +++ b/libc/utils/UnitTest/CMakeLists.txt @@ -2,7 +2,6 @@ add_llvm_library( LibcUnitTest Test.cpp Test.h - LINK_COMPONENTS Support ) target_include_directories(LibcUnitTest PUBLIC ${LIBC_SOURCE_DIR}) add_dependencies(LibcUnitTest libc.utils.CPP.standalone_cpp) diff --git a/libc/utils/buildbot/README.txt b/libc/utils/buildbot/README.txt index 3edec0e416c33..40c2cb5b87763 100644 --- a/libc/utils/buildbot/README.txt +++ b/libc/utils/buildbot/README.txt @@ -1,5 +1,5 @@ This folder contains resources needed to create a docker container for -llvm-libc builbot worker. +llvm-libc buildbot worker. Dockerfile: Sets up the docker image with all pre-requisites. diff --git a/libc/utils/testutils/CMakeLists.txt b/libc/utils/testutils/CMakeLists.txt index 80c23f4b07694..70237ddc1f8d5 100644 --- a/libc/utils/testutils/CMakeLists.txt +++ b/libc/utils/testutils/CMakeLists.txt @@ -11,6 +11,4 @@ add_llvm_library( ExecuteFunction.h ${FDReaderFile} FDReader.h - LINK_COMPONENTS - Support ) diff --git a/libc/utils/testutils/ExecuteFunctionUnix.cpp b/libc/utils/testutils/ExecuteFunctionUnix.cpp index 60e367a40cb68..4050a0ca8a6ec 100644 --- a/libc/utils/testutils/ExecuteFunctionUnix.cpp +++ b/libc/utils/testutils/ExecuteFunctionUnix.cpp @@ -7,9 +7,10 @@ //===----------------------------------------------------------------------===// #include "ExecuteFunction.h" -#include "llvm/Support/raw_ostream.h" #include #include +#include +#include #include #include #include @@ -41,8 +42,8 @@ ProcessStatus invokeInSubprocess(FunctionCaller *Func, unsigned timeoutMS) { return ProcessStatus::Error("pipe(2) failed"); // Don't copy the buffers into the child process and print twice. - llvm::outs().flush(); - llvm::errs().flush(); + std::cout.flush(); + std::cerr.flush(); pid_t Pid = ::fork(); if (Pid == -1) return ProcessStatus::Error("fork(2) failed"); diff --git a/libc/utils/testutils/FDReaderUnix.cpp b/libc/utils/testutils/FDReaderUnix.cpp index c54a1a423d863..db1f63f0dcc38 100644 --- a/libc/utils/testutils/FDReaderUnix.cpp +++ b/libc/utils/testutils/FDReaderUnix.cpp @@ -7,17 +7,19 @@ //===----------------------------------------------------------------------===// #include "FDReader.h" -#include "llvm/Support/MemoryBuffer.h" #include #include +#include #include namespace __llvm_libc { namespace testutils { FDReader::FDReader() { - if (::pipe(pipefd)) - llvm::report_fatal_error("pipe(2) failed"); + if (::pipe(pipefd)) { + std::cerr << "pipe(2) failed"; + abort(); + } } FDReader::~FDReader() { @@ -26,15 +28,25 @@ FDReader::~FDReader() { } bool FDReader::matchWritten(const char *str) { - llvm::ErrorOr> bufOrErr = - llvm::MemoryBuffer::getOpenFile(pipefd[0], "", - /* FileSize (irrelevant) */ 0); - if (!bufOrErr) { - assert(0 && "Error reading from pipe"); - return false; + + ::close(pipefd[1]); + + constexpr ssize_t ChunkSize = 4096 * 4; + + char Buffer[ChunkSize]; + std::string PipeStr; + std::string InputStr(str); + + for (int BytesRead; (BytesRead = ::read(pipefd[0], Buffer, ChunkSize));) { + if (BytesRead > 0) { + PipeStr.insert(PipeStr.size(), Buffer, BytesRead); + } else { + assert(0 && "Error reading from pipe"); + return false; + } } - const llvm::MemoryBuffer &buf = **bufOrErr; - return !std::strncmp(buf.getBufferStart(), str, buf.getBufferSize()); + + return PipeStr == InputStr; } } // namespace testutils diff --git a/libc/utils/testutils/StreamWrapper.cpp b/libc/utils/testutils/StreamWrapper.cpp index f6318a9934018..9071ebca245cc 100644 --- a/libc/utils/testutils/StreamWrapper.cpp +++ b/libc/utils/testutils/StreamWrapper.cpp @@ -7,19 +7,19 @@ //===----------------------------------------------------------------------===// #include "StreamWrapper.h" -#include "llvm/Support/raw_ostream.h" #include +#include #include #include namespace __llvm_libc { namespace testutils { -StreamWrapper outs() { return {std::addressof(llvm::outs())}; } +StreamWrapper outs() { return {std::addressof(std::cout)}; } template StreamWrapper &StreamWrapper::operator<<(T t) { assert(OS); - llvm::raw_ostream &Stream = *reinterpret_cast(OS); + std::ostream &Stream = *reinterpret_cast(OS); Stream << t; return *this; } diff --git a/libcxx/CMakeLists.txt b/libcxx/CMakeLists.txt index dd4c93b59d330..f4c7e9992f714 100644 --- a/libcxx/CMakeLists.txt +++ b/libcxx/CMakeLists.txt @@ -514,11 +514,11 @@ remove_flags(-Wno-pedantic -pedantic-errors -pedantic) # Required flags ============================================================== function(cxx_add_basic_build_flags target) - # Require C++17 for all targets. C++17 is needed to use aligned allocation - # in the dylib. + # Require C++20 for all targets. C++17 is needed to use aligned allocation + # in the dylib. C++20 is needed to use char8_t. set_target_properties(${target} PROPERTIES - CXX_STANDARD 17 - CXX_STANDARD_REQUIRED YES + CXX_STANDARD 20 + CXX_STANDARD_REQUIRED NO CXX_EXTENSIONS NO) # When building the dylib, don't warn for unavailable aligned allocation diff --git a/libcxx/NOTES.TXT b/libcxx/NOTES.TXT index 24d245d437cc8..16366a580f18f 100644 --- a/libcxx/NOTES.TXT +++ b/libcxx/NOTES.TXT @@ -14,7 +14,6 @@ an LLVM release. 1. Update _LIBCPP_VERSION in `__config` 2. Update the __libcpp_version file. 3. Update the version number in `docs/conf.py` -4. Create ABI lists for the previous release under `lib/abi` //===---------------------------------------------------------------------===// // Adding a new header TODO diff --git a/libcxx/docs/Cxx1yStatus.rst b/libcxx/docs/Cxx1yStatus.rst new file mode 100644 index 0000000000000..91744a7eee0c5 --- /dev/null +++ b/libcxx/docs/Cxx1yStatus.rst @@ -0,0 +1,50 @@ +.. _cxx1y-status: + +================================ +libc++ C++14 Status +================================ + +.. include:: Helpers/Styles.rst + +.. contents:: + :local: + + +Overview +================================ + +In April 2013, the C++ standard committee approved the draft for the next version of the C++ standard, initially known as "C++1y". + +The draft standard includes papers and issues that were voted on at the previous three meetings (Kona, Portland, and Bristol). + +In August 2014, this draft was approved by ISO as C++14. + +This page shows the status of libc++; the status of clang's support of the language features is `here `__. + +The groups that have contributed papers: + +- CWG - Core Language Working group +- LWG - Library working group +- SG1 - Study group #1 (Concurrency working group) + + +.. _paper-status-cxx1y: + +Paper Status +==================================== + +.. csv-table:: + :file: Cxx1yStatusPaperStatus.csv + :widths: auto + + +.. _issues-status-cxx1y: + +Library Working Group Issues Status +==================================== + +.. csv-table:: + :file: Cxx1yStatusIssuesStatus.csv + :widths: auto + +Last Updated: 25-Mar-2014 diff --git a/libcxx/docs/Cxx1yStatusIssuesStatus.csv b/libcxx/docs/Cxx1yStatusIssuesStatus.csv new file mode 100644 index 0000000000000..02da3e71be1f7 --- /dev/null +++ b/libcxx/docs/Cxx1yStatusIssuesStatus.csv @@ -0,0 +1,157 @@ +"Issue #","Issue Name","Meeting","Status" +"`1214 `__","Insufficient/inconsistent key immutability requirements for associative containers","Kona","|Complete|" +"`2009 `__","Reporting out-of-bound values on numeric string conversions","Kona","|Complete|" +"`2010 `__","``is_*``\ traits for binding operations can't be meaningfully specialized","Kona","|Complete|" +"`2015 `__","Incorrect pre-conditions for some type traits","Kona","|Complete|" +"`2021 `__","Further incorrect usages of result_of","Kona","|Complete|" +"`2028 `__","messages_base::catalog overspecified","Kona","|Complete|" +"`2033 `__","Preconditions of reserve, shrink_to_fit, and resize functions","Kona","|Complete|" +"`2039 `__","Issues with std::reverse and std::copy_if","Kona","|Complete|" +"`2044 `__","No definition of ""Stable"" for copy algorithms","Kona","|Complete|" +"`2045 `__","forward_list::merge and forward_list::splice_after with unequal allocators","Kona","|Complete|" +"`2047 `__","Incorrect ""mixed"" move-assignment semantics of unique_ptr","Kona","|Complete|" +"`2050 `__","Unordered associative containers do not use allocator_traits to define member types","Kona","|Complete|" +"`2053 `__","Errors in regex bitmask types","Kona","|Complete|" +"`2061 `__","make_move_iterator and arrays","Kona","|Complete|" +"`2064 `__","More noexcept issues in basic_string","Kona","|Complete|" +"`2065 `__","Minimal allocator interface","Kona","|Complete|" +"`2067 `__","packaged_task should have deleted copy c'tor with const parameter","Kona","|Complete|" +"`2069 `__","Inconsistent exception spec for basic_string move constructor","Kona","|Complete|" +"`2096 `__","Incorrect constraints of future::get in regard to MoveAssignable","Kona","|Complete|" +"`2102 `__","Why is std::launch an implementation-defined type?","Kona","|Complete|" +"","","","" +"`2071 `__","std::valarray move-assignment","Portland","|Complete|" +"`2074 `__","Off by one error in std::reverse_copy","Portland","|Complete|" +"`2081 `__","Allocator requirements should include CopyConstructible","Portland","|Complete|" +"`2083 `__","const-qualification on weak_ptr::owner_before","Portland","|Complete|" +"`2086 `__","Overly generic type support for math functions","Portland","|Complete|" +"`2099 `__","Unnecessary constraints of va_start() usage","Portland","|Complete|" +"`2103 `__","std::allocator_traits>::propagate_on_container_move_assignment","Portland","|Complete|" +"`2105 `__","Inconsistent requirements on ``const_iterator``'s value_type","Portland","|Complete|" +"`2110 `__","remove can't swap but note says it might","Portland","|Complete|" +"`2123 `__","merge() allocator requirements for lists versus forward lists","Portland","|Complete|" +"`2005 `__","unordered_map::insert(T&&) protection should apply to map too","Portland","|Complete|" +"`2011 `__","Unexpected output required of strings","Portland","|Complete|" +"`2048 `__","Unnecessary mem_fn overloads","Portland","|Complete|" +"`2049 `__","``is_destructible``\ is underspecified","Portland","|Complete|" +"`2056 `__","future_errc enums start with value 0 (invalid value for broken_promise)","Portland","|Complete|" +"`2058 `__","valarray and begin/end","Portland","|Complete|" +"","","","" +"`2091 `__","Misplaced effect in m.try_lock_for()","Bristol","|Complete|" +"`2092 `__","Vague Wording for condition_variable_any","Bristol","|Complete|" +"`2093 `__","Throws clause of condition_variable::wait with predicate","Bristol","|Complete|" +"`2094 `__","duration conversion overflow shouldn't participate in overload resolution","Bristol","|Complete|" +"`2122 `__","merge() stability for lists versus forward lists","Bristol","|Complete|" +"`2128 `__","Absence of global functions cbegin/cend","Bristol","|Complete|" +"`2145 `__","error_category default constructor","Bristol","|Complete|" +"`2147 `__","Unclear hint type in Allocator's allocate function","Bristol","|Complete|" +"`2148 `__","Hashing enums should be supported directly by std::hash","Bristol","|Complete|" +"`2149 `__","Concerns about 20.8/5","Bristol","|Complete|" +"`2162 `__","allocator_traits::max_size missing noexcept","Bristol","|Complete|" +"`2163 `__","nth_element requires inconsistent post-conditions","Bristol","|Complete|" +"`2169 `__","Missing reset() requirements in unique_ptr specialization","Bristol","|Complete|" +"`2172 `__","Does ``atomic_compare_exchange_*``\ accept v == nullptr arguments?","Bristol","|Complete|" +"`2080 `__","Specify when once_flag becomes invalid","Bristol","|Complete|" +"`2098 `__","promise throws clauses","Bristol","|Complete|" +"`2109 `__","Incorrect requirements for hash specializations","Bristol","|Complete|" +"`2130 `__","missing ordering constraints for fences","Bristol","|Complete|" +"`2138 `__","atomic_flag::clear ordering constraints","Bristol","|Complete|" +"`2140 `__","notify_all_at_thread_exit synchronization","Bristol","|Complete|" +"`2144 `__","Missing noexcept specification in type_index","Bristol","|Complete|" +"`2174 `__","wstring_convert::converted() should be noexcept","Bristol","|Complete|" +"`2175 `__","string_convert and wbuffer_convert validity","Bristol","|Complete|" +"`2176 `__","Special members for wstring_convert and wbuffer_convert","Bristol","|Complete|" +"`2177 `__","Requirements on Copy/MoveInsertable","Bristol","|Complete|" +"`2185 `__","Missing throws clause for future/shared_future::wait_for/wait_until","Bristol","|Complete|" +"`2187 `__","vector is missing emplace and emplace_back member functions","Bristol","|Complete|" +"`2190 `__","ordering of condition variable operations, reflects Posix discussion","Bristol","|Complete|" +"`2196 `__","Specification of ``is_*[copy/move]_[constructible/assignable]``\ unclear for non-referencable types","Bristol","|Complete|" +"`2197 `__","Specification of ``is_[un]signed``\ unclear for non-arithmetic types","Bristol","|Complete|" +"`2200 `__","Data race avoidance for all containers, not only for sequences","Bristol","|Complete|" +"`2203 `__","scoped_allocator_adaptor uses wrong argument types for piecewise construction","Bristol","|Complete|" +"`2207 `__","basic_string::at should not have a Requires clause","Bristol","|Complete|" +"`2209 `__","assign() overspecified for sequence containers","Bristol","|Complete|" +"`2210 `__","Missing allocator-extended constructor for allocator-aware containers","Bristol","|Complete|" +"`2211 `__","Replace ambiguous use of ""Allocator"" in container requirements","Bristol","|Complete|" +"`2222 `__","Inconsistency in description of forward_list::splice_after single-element overload","Bristol","|Complete|" +"`2225 `__","Unrealistic header inclusion checks required","Bristol","|Complete|" +"`2229 `__","Standard code conversion facets underspecified","Bristol","|Complete|" +"`2231 `__","DR 704 removes complexity guarantee for clear()","Bristol","|Complete|" +"`2235 `__","Undefined behavior without proper requirements on basic_string constructors","Bristol","|Complete|" +"","","","" +"`2141 `__","common_type trait produces reference types","Chicago","|Complete|" +"`2246 `__","unique_ptr assignment effects w.r.t. deleter","Chicago","|Complete|" +"`2247 `__","Type traits and std::nullptr_t","Chicago","|Complete|" +"`2085 `__","Wrong description of effect 1 of basic_istream::ignore","Chicago","|Complete|" +"`2087 `__","iostream_category() and noexcept","Chicago","|Complete|" +"`2143 `__","ios_base::xalloc should be thread-safe","Chicago","|Complete|" +"`2150 `__","Unclear specification of find_end","Chicago","|Complete|" +"`2180 `__","Exceptions from std::seed_seq operations","Chicago","|Complete|" +"`2194 `__","Impossible container requirements for adaptor types","Chicago","|Complete|" +"`2013 `__","Do library implementers have the freedom to add constexpr?","Chicago","|Complete|" +"`2018 `__","regex_traits::isctype Returns clause is wrong","Chicago","|Complete|" +"`2078 `__","Throw specification of async() incomplete","Chicago","|Complete|" +"`2097 `__","packaged_task constructors should be constrained","Chicago","|Complete|" +"`2100 `__","Timed waiting functions cannot timeout if launch::async policy used","Chicago","|Complete|" +"`2120 `__","What should async do if neither 'async' nor 'deferred' is set in policy?","Chicago","|Complete|" +"`2159 `__","atomic_flag initialization","Chicago","|Complete|" +"`2275 `__","Why is forward_as_tuple not constexpr?","Chicago","|Complete|" +"`2284 `__","Inconsistency in allocator_traits::max_size","Chicago","|Complete|" +"`2298 `__","``is_nothrow_constructible``\ is always false because of create<>","Chicago","|Complete|" +"`2300 `__","Redundant sections for map and multimap members should be removed","Chicago","|Complete|" +"NB comment: GB9","Remove gets from C++14","Chicago","|Complete|" +"","","","" +"`2135 `__","Unclear requirement for exceptions thrown in condition_variable::wait()","Issaquah","|Complete|" +"`2291 `__","std::hash is vulnerable to collision DoS attack","Issaquah","|Complete|" +"`2142 `__","packaged_task::operator() synchronization too broad?","Issaquah","|Complete|" +"`2240 `__","Probable misuse of term ""function scope"" in [thread.condition]","Issaquah","|Complete|" +"`2252 `__","Strong guarantee on vector::push_back() still broken with C++11?","Issaquah","|Complete|" +"`2257 `__","Simplify container requirements with the new algorithms","Issaquah","|Complete|" +"`2268 `__","Setting a default argument in the declaration of a member function assign of std::basic_string","Issaquah","|Complete|" +"`2271 `__","regex_traits::lookup_classname specification unclear","Issaquah","|Complete|" +"`2272 `__","quoted should use char_traits::eq for character comparison","Issaquah","|Complete|" +"`2278 `__","User-defined literals for Standard Library types","Issaquah","|Complete|" +"`2280 `__","begin / end for arrays should be constexpr and noexcept","Issaquah","|Complete|" +"`2285 `__","make_reverse_iterator","Issaquah","|Complete|" +"`2299 `__","Effects of inaccessible ``key_compare::is_transparent``\ type are not clear","Issaquah","|Complete|" +"`1450 `__","Contradiction in regex_constants","Issaquah","|Complete|" +"`2003 `__","String exception inconsistency in erase.","Issaquah","|Complete|" +"`2112 `__","User-defined classes that cannot be derived from","Issaquah","|Complete|" +"`2132 `__","std::function ambiguity","Issaquah","|Complete|" +"`2182 `__","``Container::[const_]reference`` types are misleadingly specified","Issaquah","|Complete|" +"`2188 `__","Reverse iterator does not fully support targets that overload operator&","Issaquah","|Complete|" +"`2193 `__","Default constructors for standard library containers are explicit","Issaquah","|Complete|" +"`2205 `__","Problematic postconditions of regex_match and regex_search","Issaquah","|Complete|" +"`2213 `__","Return value of std::regex_replace","Issaquah","|Complete|" +"`2258 `__","a.erase(q1, q2) unable to directly return q2","Issaquah","|Complete|" +"`2263 `__","Comparing iterators and allocator pointers with different const-character","Issaquah","|Complete|" +"`2293 `__","Wrong facet used by num_put::do_put","Issaquah","|Complete|" +"`2301 `__","Why is std::tie not constexpr?","Issaquah","|Complete|" +"`2304 `__","Complexity of count in unordered associative containers","Issaquah","|Complete|" +"`2306 `__","match_results::reference should be value_type&, not const value_type&","Issaquah","|Complete|" +"`2308 `__","Clarify container destructor requirements w.r.t. std::array","Issaquah","|Complete|" +"`2313 `__","tuple_size should always derive from integral_constant","Issaquah","|Complete|" +"`2314 `__","apply() should return decltype(auto) and use decay_t before tuple_size","Issaquah","|Complete|" +"`2315 `__","weak_ptr should be movable","Issaquah","|Complete|" +"`2316 `__","weak_ptr::lock() should be atomic","Issaquah","|Complete|" +"`2317 `__","The type property queries should be UnaryTypeTraits returning size_t","Issaquah","|Complete|" +"`2320 `__","select_on_container_copy_construction() takes allocators, not containers","Issaquah","|Complete|" +"`2322 `__","Associative(initializer_list, stuff) constructors are underspecified","Issaquah","|Complete|" +"`2323 `__","vector::resize(n, t)'s specification should be simplified","Issaquah","|Complete|" +"`2324 `__","Insert iterator constructors should use addressof()","Issaquah","|Complete|" +"`2329 `__","regex_match()/regex_search() with match_results should forbid temporary strings","Issaquah","|Complete|" +"`2330 `__","regex(""meow"", regex::icase) is technically forbidden but should be permitted","Issaquah","|Complete|" +"`2332 `__","regex_iterator/regex_token_iterator should forbid temporary regexes","Issaquah","|Complete|" +"`2339 `__","Wording issue in nth_element","Issaquah","|Complete|" +"`2341 `__","Inconsistency between basic_ostream::seekp(pos) and basic_ostream::seekp(off, dir)","Issaquah","|Complete|" +"`2344 `__","quoted()'s interaction with padding is unclear","Issaquah","|Complete|" +"`2346 `__","integral_constant's member functions should be marked noexcept","Issaquah","|Complete|" +"`2350 `__","min, max, and minmax should be constexpr","Issaquah","|Complete|" +"`2356 `__","Stability of erasure in unordered associative containers","Issaquah","|Complete|" +"`2357 `__","Remaining ""Assignable"" requirement","Issaquah","|Complete|" +"`2359 `__","How does regex_constants::nosubs affect basic_regex::mark_count()?","Issaquah","|Complete|" +"`2360 `__","``reverse_iterator::operator*()``\ is unimplementable","Issaquah","|Complete|" +"`2104 `__","unique_lock move-assignment should not be noexcept","Issaquah","|Complete|" +"`2186 `__","Incomplete action on async/launch::deferred","Issaquah","|Complete|" +"`2075 `__","Progress guarantees, lock-free property, and scheduling assumptions","Issaquah","|Complete|" +"`2288 `__","Inconsistent requirements for shared mutexes","Issaquah","|Complete|" diff --git a/libcxx/docs/Cxx1yStatusPaperStatus.csv b/libcxx/docs/Cxx1yStatusPaperStatus.csv new file mode 100644 index 0000000000000..0e5ba7f991f48 --- /dev/null +++ b/libcxx/docs/Cxx1yStatusPaperStatus.csv @@ -0,0 +1,32 @@ +"Paper #","Group","Paper Name","Meeting","Status","First released version" +"`3346 `__","LWG","Terminology for Container Element Requirements - Rev 1","Kona","|Complete|","3.4" +"","","","","","" +"`3421 `__","LWG","Making Operator Functors greater<>","Portland","|Complete|","3.4" +"`3462 `__","LWG","std::result_of and SFINAE","Portland","|Complete|","3.4" +"`3469 `__","LWG","Constexpr Library Additions: chrono, v3","Portland","|Complete|","3.4" +"`3470 `__","LWG","Constexpr Library Additions: containers, v2","Portland","|Complete|","3.4" +"`3471 `__","LWG","Constexpr Library Additions: utilities, v3","Portland","|Complete|","3.4" +"`3302 `__","LWG","Constexpr Library Additions: complex, v2","Portland","|Complete|","3.4" +"","","","","","" +"`3545 `__","LWG","An Incremental Improvement to integral_constant","Bristol","|Complete|","3.4" +"`3644 `__","LWG","Null Forward Iterators","Bristol","|Complete|","3.4" +"`3668 `__","LWG","std::exchange()","Bristol","|Complete|","3.4" +"`3658 `__","LWG","Compile-time integer sequences","Bristol","|Complete|","3.4" +"`3670 `__","LWG","Addressing Tuples by Type","Bristol","|Complete|","3.4" +"`3671 `__","LWG","Making non-modifying sequence operations more robust","Bristol","|Complete|","3.4" +"`3656 `__","LWG","make_unique","Bristol","|Complete|","3.4" +"`3654 `__","LWG","Quoted Strings","Bristol","|Complete|","3.4" +"`3642 `__","LWG","User-defined Literals","Bristol","|Complete|","3.4" +"`3655 `__","LWG","TransformationTraits Redux (excluding part 4)","Bristol","|Complete|","3.4" +"`3657 `__","LWG","Adding heterogeneous comparison lookup to associative containers","Bristol","|Complete|","3.4" +"`3672 `__","LWG","A proposal to add a utility class to represent optional objects","Bristol","*Removed from Draft Standard*","n/a" +"`3669 `__","LWG","Fixing constexpr member functions without const","Bristol","|Complete|","3.4" +"`3662 `__","LWG","C++ Dynamic Arrays (dynarray)","Bristol","*Removed from Draft Standard*","n/a" +"`3659 `__","SG1","Shared Locking in C++","Bristol","|Complete|","3.4" +"","","","","","" +"`3779 `__","LWG","User-defined Literals for std::complex","Chicago","|Complete|","3.4" +"`3789 `__","LWG","Constexpr Library Additions: functional","Chicago","|Complete|","3.4" +"","","","","","" +"`3924 `__","LWG","Discouraging rand() in C++14","Issaquah","|Complete|","3.5" +"`3887 `__","LWG","Consistent Metafunction Aliases","Issaquah","|Complete|","3.5" +"`3891 `__","SG1","A proposal to rename shared_mutex to shared_timed_mutex","Issaquah","|Complete|","3.5" diff --git a/libcxx/docs/Cxx1zStatus.rst b/libcxx/docs/Cxx1zStatus.rst new file mode 100644 index 0000000000000..54a1629209a90 --- /dev/null +++ b/libcxx/docs/Cxx1zStatus.rst @@ -0,0 +1,55 @@ +.. _cxx1z-status: + +================================ +libc++ C++17 Status +================================ + +.. include:: Helpers/Styles.rst + +.. contents:: + :local: + + +Overview +================================ + +In November 2014, the C++ standard committee created a draft for the next version of the C++ standard, initially known as "C++1z". +In February 2017, the C++ standard committee approved this draft, and sent it to ISO for approval as C++17. + +This page shows the status of libc++; the status of clang's support of the language features is `here `__. + +.. attention:: Features in unreleased drafts of the standard are subject to change. + +The groups that have contributed papers: + +- CWG - Core Language Working group +- LWG - Library working group +- SG1 - Study group #1 (Concurrency working group) + +.. note:: "Nothing to do" means that no library changes were needed to implement this change. + +.. _paper-status-cxx1z: + +Paper Status +==================================== + +.. csv-table:: + :file: Cxx1zStatusPaperStatus.csv + :widths: auto + +.. note:: + + .. [#note-P0433] P0433: So far, only the ````, sequence containers, container adaptors and ```` portions of P0433 have been implemented. + .. [#note-P0607] P0607: The parts of P0607 that are not done are the ```` bits. + + +.. _issues-status-cxx1z: + +Library Working Group Issues Status +==================================== + +.. csv-table:: + :file: Cxx1zStatusIssuesStatus.csv + :widths: auto + +Last Updated: 17-Nov-2020 diff --git a/libcxx/docs/Cxx1zStatusIssuesStatus.csv b/libcxx/docs/Cxx1zStatusIssuesStatus.csv new file mode 100644 index 0000000000000..d5c43103b4bd1 --- /dev/null +++ b/libcxx/docs/Cxx1zStatusIssuesStatus.csv @@ -0,0 +1,318 @@ +"Issue #","Issue Name","Meeting","Status" +"`2016 `__","Allocators must be no-throw swappable","Urbana","|Complete|" +"`2118 `__","``unique_ptr``\ for array does not support cv qualification conversion of actual argument","Urbana","|Complete|" +"`2170 `__","Aggregates cannot be ``DefaultConstructible``\ ","Urbana","|Complete|" +"`2308 `__","Clarify container destructor requirements w.r.t. ``std::array``\ ","Urbana","|Complete|" +"`2340 `__","Replacement allocation functions declared as inline","Urbana","|Complete|" +"`2354 `__","Unnecessary copying when inserting into maps with braced-init syntax","Urbana","|Complete|" +"`2377 `__","``std::align``\ requirements overly strict","Urbana","|Complete|" +"`2396 `__","``underlying_type``\ doesn't say what to do for an incomplete enumeration type","Urbana","|Complete|" +"`2399 `__","``shared_ptr``\ 's constructor from ``unique_ptr``\ should be constrained","Urbana","|Complete|" +"`2400 `__","``shared_ptr``\ 's ``get_deleter()``\ should use ``addressof()``\ ","Urbana","|Complete|" +"`2401 `__","``std::function``\ needs more noexcept","Urbana","|Complete|" +"`2404 `__","``mismatch()``\ 's complexity needs to be updated","Urbana","|Complete|" +"`2408 `__","SFINAE-friendly ``common_type``\ / ``iterator_traits``\ is missing in C++14","Urbana","|Complete|" +"","","","" +"`2106 `__","``move_iterator``\ wrapping iterators returning prvalues","Urbana","|Complete|" +"`2129 `__","User specializations of ``std::initializer_list``\ ","Urbana","|Complete|" +"`2212 `__","``tuple_size``\ for ``const pair``\ request header","Urbana","|Complete|" +"`2217 `__","``operator==(sub_match, string)``\ slices on embedded '\0's","Urbana","|Complete|" +"`2230 `__","""see below"" for ``initializer_list``\ constructors of unordered containers","Urbana","|Complete|" +"`2233 `__","``bad_function_call::what()``\ unhelpful","Urbana","|Complete|" +"`2266 `__","``vector``\ and ``deque``\ have incorrect insert requirements","Urbana","|Complete|" +"`2325 `__","``minmax_element()``\ 's behavior differing from ``max_element()``\ 's should be noted","Urbana","|Complete|" +"`2361 `__","Apply 2299 resolution throughout library","Urbana","|Complete|" +"`2365 `__","Missing noexcept in ``shared_ptr::shared_ptr(nullptr_t)``\ ","Urbana","|Complete|" +"`2376 `__","``bad_weak_ptr::what()``\ overspecified","Urbana","|Complete|" +"`2387 `__","More nested types that must be accessible and unambiguous","Urbana","|Complete|" +"","","","" +"`2059 `__","C++0x ambiguity problem with map::erase","Lenexa","|Complete|" +"`2063 `__","Contradictory requirements for string move assignment","Lenexa","|Complete|" +"`2076 `__","Bad CopyConstructible requirement in set constructors","Lenexa","|Complete|" +"`2160 `__","Unintended destruction ordering-specification of resize","Lenexa","|Complete|" +"`2168 `__","Inconsistent specification of uniform_real_distribution constructor","Lenexa","|Complete|" +"`2239 `__","min/max/minmax requirements","Lenexa","|Complete|" +"`2364 `__","deque and vector pop_back don't specify iterator invalidation requirements","Lenexa","|Complete|" +"`2369 `__","constexpr max(initializer_list) vs max_element","Lenexa","|Complete|" +"`2378 `__","Behaviour of standard exception types","Lenexa","|Complete|" +"`2403 `__","stof() should call strtof() and wcstof()","Lenexa","|Complete|" +"`2406 `__","negative_binomial_distribution should reject p == 1","Lenexa","|Complete|" +"`2407 `__","packaged_task(allocator_arg_t, const Allocator&, F&&) should neither be constrained nor explicit","Lenexa","|Complete|" +"`2411 `__","shared_ptr is only contextually convertible to bool","Lenexa","|Complete|" +"`2415 `__","Inconsistency between unique_ptr and shared_ptr","Lenexa","|Complete|" +"`2420 `__","function does not discard the return value of the target object","Lenexa","|Complete|" +"`2425 `__","``operator delete(void*, size_t)``\ doesn't invalidate pointers sufficiently","Lenexa","|Complete|" +"`2427 `__","Container adaptors as sequence containers, redux","Lenexa","|Complete|" +"`2428 `__","""External declaration"" used without being defined","Lenexa","|Complete|" +"`2433 `__","``uninitialized_copy()``\ /etc. should tolerate overloaded operator&","Lenexa","|Complete|" +"`2434 `__","``shared_ptr::use_count()``\ is efficient","Lenexa","|Complete|" +"`2437 `__","``iterator_traits::reference``\ can and can't be void","Lenexa","|Complete|" +"`2438 `__","``std::iterator``\ inheritance shouldn't be mandated","Lenexa","|Complete|" +"`2439 `__","``unique_copy()``\ sometimes can't fall back to reading its output","Lenexa","|Complete|" +"`2440 `__","``seed_seq::size()``\ should be noexcept","Lenexa","|Complete|" +"`2442 `__","``call_once()``\ shouldn't DECAY_COPY()","Lenexa","|Complete|" +"`2448 `__","Non-normative Container destructor specification","Lenexa","|Complete|" +"`2454 `__","Add ``raw_storage_iterator::base()``\ member","Lenexa","|Complete|" +"`2455 `__","Allocator default construction should be allowed to throw","Lenexa","|Complete|" +"`2458 `__","N3778 and new library deallocation signatures","Lenexa","|Complete|" +"`2459 `__","``std::polar``\ should require a non-negative rho","Lenexa","|Complete|" +"`2464 `__","``try_emplace``\ and ``insert_or_assign``\ misspecified","Lenexa","|Complete|" +"`2467 `__","``is_always_equal``\ has slightly inconsistent default","Lenexa","|Complete|" +"`2470 `__","Allocator's destroy function should be allowed to fail to instantiate","Lenexa","|Complete|" +"`2482 `__","[c.strings] Table 73 mentions nonexistent functions","Lenexa","|Complete|" +"`2488 `__","Placeholders should be allowed and encouraged to be constexpr","Lenexa","|Complete|" +"","","","" +"`1169 `__","``num_get``\ not fully compatible with ``strto*``\ ","Kona","|Complete|" +"`2072 `__","Unclear wording about capacity of temporary buffers","Kona","|Complete|" +"`2101 `__","Some transformation types can produce impossible types","Kona","|Complete|" +"`2111 `__","Which ``unexpected``\ /``terminate``\ handler is called from the exception handling runtime?","Kona","|Complete|" +"`2119 `__","Missing ``hash``\ specializations for extended integer types","Kona","|Complete|" +"`2127 `__","Move-construction with ``raw_storage_iterator``\ ","Kona","|Complete|" +"`2133 `__","Attitude to overloaded comma for iterators","Kona","|Complete|" +"`2156 `__","Unordered containers' ``reserve(n)``\ reserves for ``n-1``\ elements","Kona","|Complete|" +"`2218 `__","Unclear how containers use ``allocator_traits::construct()``\ ","Kona","|Complete|" +"`2219 `__","``*INVOKE*``\ -ing a pointer to member with a ``reference_wrapper``\ as the object expression","Kona","|Complete|" +"`2224 `__","Ambiguous status of access to non-live objects","Kona","|Complete|" +"`2234 `__","``assert()``\ should allow usage in constant expressions","Kona","|Complete|" +"`2244 `__","Issue on ``basic_istream::seekg``\ ","Kona","|Complete|" +"`2250 `__","Follow-up On Library Issue 2207","Kona","|Complete|" +"`2259 `__","Issues in 17.6.5.5 rules for member functions","Kona","|Complete|" +"`2273 `__","``regex_match``\ ambiguity","Kona","|Complete|" +"`2336 `__","``is_trivially_constructible``\ /``is_trivially_assignable``\ traits are always false","Kona","|Complete|" +"`2353 `__","``std::next``\ is over-constrained","Kona","|Complete|" +"`2367 `__","``pair``\ and ``tuple``\ are not correctly implemented for ``is_constructible``\ with no args","Kona","|Complete|" +"`2380 `__","May ````\ provide ``long ::abs(long)``\ and ``long long ::abs(long long)``\ ?","Kona","|Complete|" +"`2384 `__","Allocator's ``deallocate``\ function needs better specification","Kona","|Complete|" +"`2385 `__","``function::assign``\ allocator argument doesn't make sense","Kona","|Complete|" +"`2435 `__","``reference_wrapper::operator()``\ 's Remark should be deleted","Kona","|Complete|" +"`2447 `__","Allocators and ``volatile``\ -qualified value types","Kona","|Complete|" +"`2462 `__","``std::ios_base::failure``\ is overspecified","Kona","|Complete|" +"`2466 `__","``allocator_traits::max_size()``\ default behavior is incorrect","Kona","|Complete|" +"`2469 `__","Wrong specification of Requires clause of ``operator[]``\ for ``map``\ and ``unordered_map``\ ","Kona","|Complete|" +"`2473 `__","``basic_filebuf``\ 's relation to C ``FILE``\ semantics","Kona","|Complete|" +"`2476 `__","``scoped_allocator_adaptor``\ is not assignable","Kona","|Complete|" +"`2477 `__","Inconsistency of wordings in ``std::vector::erase()``\ and ``std::deque::erase()``\ ","Kona","|Complete|" +"`2483 `__","``throw_with_nested()``\ should use ``is_final``\ ","Kona","|Complete|" +"`2484 `__","``rethrow_if_nested()``\ is doubly unimplementable","Kona","|Complete|" +"`2485 `__","``get()``\ should be overloaded for ``const tuple&&``\ ","Kona","|Complete|" +"`2486 `__","``mem_fn()``\ should be required to use perfect forwarding","Kona","|Complete|" +"`2487 `__","``bind()``\ should be ``const``\ -overloaded, not *cv*-overloaded","Kona","|Complete|" +"`2489 `__","``mem_fn()``\ should be ``noexcept``\ ","Kona","|Complete|" +"`2492 `__","Clarify requirements for ``comp``\ ","Kona","|Complete|" +"`2495 `__","There is no such thing as an Exception Safety element","Kona","|Complete|" +"","","","" +"`2192 `__","Validity and return type of ``std::abs(0u)``\ is unclear","Jacksonville","|Complete|" +"`2276 `__","Missing requirement on ``std::promise::set_exception``\ ","Jacksonville","|Complete|" +"`2296 `__","``std::addressof``\ should be ``constexpr``\ ","Jacksonville","Complete (Clang Only)" +"`2450 `__","``(greater|less|greater_equal|less_equal)``\ do not yield a total order for pointers","Jacksonville","|Complete|" +"`2520 `__","N4089 broke initializing ``unique_ptr``\ from a ``nullptr``\ ","Jacksonville","|Complete|" +"`2522 `__","[fund.ts.v2] Contradiction in ``set_default_resource``\ specification","Jacksonville","|Complete|" +"`2523 `__","``std::promise``\ synopsis shows two ``set_value_at_thread_exit()``\ 's for no apparent reason","Jacksonville","|Complete|" +"`2537 `__","Constructors for ``priority_queue``\ taking allocators should call ``make_heap``\ ","Jacksonville","|Complete|" +"`2539 `__","[fund.ts.v2] ``invocation_trait``\ definition definition doesn't work for surrogate call functions","Jacksonville","" +"`2545 `__","Simplify wording for ``bind``\ without explicitly specified return type","Jacksonville","|Complete|" +"`2557 `__","Logical operator traits are broken in the zero-argument case","Jacksonville","|Complete|" +"`2558 `__","[fund.ts.v2] Logical operator traits are broken in the zero-argument case","Jacksonville","|Complete|" +"`2559 `__","Error in LWG 2234's resolution","Jacksonville","|Complete|" +"`2560 `__","``is_constructible``\ underspecified when applied to a function type","Jacksonville","Broken in 3.6; See r261653." +"`2565 `__","``std::function``\ 's move constructor should guarantee nothrow for ``reference_wrapper``\ s and function pointers","Jacksonville","|Complete|" +"`2566 `__","Requirements on the first template parameter of container adaptors","Jacksonville","|Complete|" +"`2571 `__","|sect|\ [map.modifiers]/2 imposes nonsensical requirement on ``insert(InputIterator, InputIterator)``\ ","Jacksonville","|Complete|" +"`2572 `__","The remarks for ``shared_ptr::operator*``\ should apply to *cv*-qualified ``void``\ as well","Jacksonville","|Complete|" +"`2574 `__","[fund.ts.v2] ``std::experimental::function::operator=(F&&)``\ should be constrained","Jacksonville","|Complete|" +"`2575 `__","[fund.ts.v2] ``experimental::function::assign``\ should be removed","Jacksonville","" +"`2576 `__","``istream_iterator``\ and ``ostream_iterator``\ should use ``std::addressof``\ ","Jacksonville","|Complete|" +"`2577 `__","``{shared,unique}_lock``\ should use ``std::addressof``\ ","Jacksonville","|Complete|" +"`2579 `__","Inconsistency wrt Allocators in ``basic_string``\ assignment vs. ``basic_string::assign``\ ","Jacksonville","|Complete|" +"`2581 `__","Specialization of ````\ variable templates should be prohibited","Jacksonville","|Complete|" +"`2582 `__","|sect|\ [res.on.functions]/2's prohibition against incomplete types shouldn't apply to type traits","Jacksonville","|Complete|" +"`2583 `__","There is no way to supply an allocator for ``basic_string(str, pos)``\ ","Jacksonville","|Complete|" +"`2585 `__","``forward_list::resize(size_type, const value_type&)``\ effects incorrect","Jacksonville","|Complete|" +"`2586 `__","Wrong value category used in ``scoped_allocator_adaptor::construct()``\ ","Jacksonville","|Complete|" +"`2590 `__","Aggregate initialization for ``std::array``\ ","Jacksonville","|Complete|" +"","","","" +"`2181 `__","Exceptions from seed sequence operations","Oulu","|Complete|" +"`2309 `__","mutex::lock() should not throw device_or_resource_busy","Oulu","|Complete|" +"`2310 `__","Public exposition only member in std::array","Oulu","|Complete|" +"`2312 `__","tuple's constructor constraints need to be phrased more precisely","Oulu","|Complete|" +"`2328 `__","Rvalue stream extraction should use perfect forwarding","Oulu","|Complete|" +"`2393 `__","std::function's Callable definition is broken","Oulu","|Complete|" +"`2422 `__","``std::numeric_limits::is_modulo``\ description: ""most machines"" errata","Oulu","|Complete|" +"`2426 `__","Issue about compare_exchange","Oulu","" +"`2436 `__","Comparators for associative containers should always be CopyConstructible","Oulu","|Complete|" +"`2441 `__","Exact-width atomic typedefs should be provided","Oulu","|Complete|" +"`2451 `__","[fund.ts.v2] optional should 'forward' T's implicit conversions","Oulu","|Nothing To Do|" +"`2509 `__","[fund.ts.v2] any_cast doesn't work with rvalue reference targets and cannot move with a value target","Oulu","|Complete|" +"`2516 `__","[fund.ts.v2] Public ""exposition only"" members in observer_ptr","Oulu","" +"`2542 `__","Missing const requirements for associative containers","Oulu","" +"`2549 `__","Tuple EXPLICIT constructor templates that take tuple parameters end up taking references to temporaries and will create dangling references","Oulu","|Complete|" +"`2550 `__","Wording of unordered container's clear() method complexity","Oulu","|Complete|" +"`2551 `__","[fund.ts.v2] ""Exception safety"" cleanup in library fundamentals required","Oulu","|Complete|" +"`2555 `__","[fund.ts.v2] No handling for over-aligned types in optional","Oulu","|Complete|" +"`2573 `__","[fund.ts.v2] std::hash does not work for arrays","Oulu","" +"`2596 `__","vector::data() should use addressof","Oulu","|Complete|" +"`2667 `__","path::root_directory() description is confusing","Oulu","|Complete|" +"`2669 `__","recursive_directory_iterator effects refers to non-existent functions","Oulu","|Complete|" +"`2670 `__","system_complete refers to undefined variable 'base'","Oulu","|Complete|" +"`2671 `__","Errors in Copy","Oulu","|Complete|" +"`2673 `__","status() effects cannot be implemented as specified","Oulu","|Complete|" +"`2674 `__","Bidirectional iterator requirement on path::iterator is very expensive","Oulu","|Complete|" +"`2683 `__","filesystem::copy() says ""no effects""","Oulu","|Complete|" +"`2684 `__","priority_queue lacking comparator typedef","Oulu","|Complete|" +"`2685 `__","shared_ptr deleters must not throw on move construction","Oulu","|Complete|" +"`2687 `__","{inclusive,exclusive}_scan misspecified","Oulu","" +"`2688 `__","clamp misses preconditions and has extraneous condition on result","Oulu","|Complete|" +"`2689 `__","Parallel versions of std::copy and std::move shouldn't be in order","Oulu","" +"`2698 `__","Effect of assign() on iterators/pointers/references","Oulu","|Complete|" +"`2704 `__","recursive_directory_iterator's members should require '``*this`` is dereferenceable'","Oulu","|Complete|" +"`2706 `__","Error reporting for recursive_directory_iterator::pop() is under-specified","Oulu","|Complete|" +"`2707 `__","path construction and assignment should have ""string_type&&"" overloads","Oulu","|Complete|" +"`2709 `__","offsetof is unnecessarily imprecise","Oulu","" +"`2710 `__","""Effects: Equivalent to ..."" doesn't count ""Synchronization:"" as determined semantics","Oulu","|Complete|" +"`2711 `__","path is convertible from approximately everything under the sun","Oulu","|Complete|" +"`2716 `__","Specification of shuffle and sample disallows lvalue URNGs","Oulu","|Complete|" +"`2718 `__","Parallelism bug in [algorithms.parallel.exec] p2","Oulu","" +"`2719 `__","permissions function should not be noexcept due to narrow contract","Oulu","|Complete|" +"`2720 `__","permissions function incorrectly specified for symlinks","Oulu","|Complete|" +"`2721 `__","remove_all has incorrect post conditions","Oulu","|Complete|" +"`2723 `__","Do directory_iterator and recursive_directory_iterator become the end iterator upon error?","Oulu","|Complete|" +"`2724 `__","The protected virtual member functions of memory_resource should be private","Oulu","" +"`2725 `__","filesystem::exists(const path&, error_code&) error reporting","Oulu","|Complete|" +"`2726 `__","``[recursive_]directory_iterator::increment(error_code&)`` is underspecified","Oulu","|Complete|" +"`2727 `__","Parallel algorithms with constexpr specifier","Oulu","" +"`2728 `__","status(p).permissions() and symlink_status(p).permissions() are not specified","Oulu","|Complete|" +"","","","" +"`2062 `__","Effect contradictions w/o no-throw guarantee of std::function swaps","Issaquah","|Complete|" +"`2166 `__","Heap property underspecified?","Issaquah","" +"`2221 `__","No formatted output operator for nullptr","Issaquah","|Complete|" +"`2223 `__","shrink_to_fit effect on iterator validity","Issaquah","|Complete|" +"`2261 `__","Are containers required to use their 'pointer' type internally?","Issaquah","" +"`2394 `__","locale::name specification unclear - what is implementation-defined?","Issaquah","|Complete|" +"`2460 `__","LWG issue 2408 and value categories","Issaquah","|Complete|" +"`2468 `__","Self-move-assignment of library types","Issaquah","" +"`2475 `__","Allow overwriting of std::basic_string terminator with charT() to allow cleaner interoperation with legacy APIs","Issaquah","|Complete|" +"`2503 `__","multiline option should be added to syntax_option_type","Issaquah","|Complete|" +"`2510 `__","Tag types should not be DefaultConstructible","Issaquah","|Complete|" +"`2514 `__","Type traits must not be final","Issaquah","|Complete|" +"`2518 `__","[fund.ts.v2] Non-member swap for propagate_const should call member swap","Issaquah","|Complete|" +"`2519 `__","Iterator operator-= has gratuitous undefined behaviour","Issaquah","|Complete|" +"`2521 `__","[fund.ts.v2] weak_ptr's converting move constructor should be modified as well for array support","Issaquah","" +"`2525 `__","[fund.ts.v2] get_memory_resource should be const and noexcept","Issaquah","" +"`2527 `__","[fund.ts.v2] ALLOCATOR_OF for function::operator= has incorrect default","Issaquah","" +"`2531 `__","future::get should explicitly state that the shared state is released","Issaquah","" +"`2534 `__","Constrain rvalue stream operators","Issaquah","" +"`2536 `__","What should do?","Issaquah","|Complete|" +"`2540 `__","unordered_multimap::insert hint iterator","Issaquah","|Complete|" +"`2543 `__","LWG 2148 (hash support for enum types) seems under-specified","Issaquah","|Complete|" +"`2544 `__","``istreambuf_iterator(basic_streambuf* s)``\ effects unclear when s is 0","Issaquah","|Complete|" +"`2556 `__","Wide contract for future::share()","Issaquah","|Complete|" +"`2562 `__","Consistent total ordering of pointers by comparison functors","Issaquah","" +"`2567 `__","Specification of logical operator traits uses BaseCharacteristic, which is defined only for UnaryTypeTraits and BinaryTypeTraits","Issaquah","|Complete|" +"`2568 `__","[fund.ts.v2] Specification of logical operator traits uses BaseCharacteristic, which is defined only for UnaryTypeTraits and BinaryTypeTraits","Issaquah","" +"`2569 `__","conjunction and disjunction requirements are too strict","Issaquah","|Complete|" +"`2570 `__","[fund.ts.v2] conjunction and disjunction requirements are too strict","Issaquah","" +"`2578 `__","Iterator requirements should reference iterator traits","Issaquah","|Complete|" +"`2584 `__"," ECMAScript IdentityEscape is ambiguous","Issaquah","" +"`2587 `__","""Convertible to bool"" requirement in conjunction and disjunction","Issaquah","Resolved by 2567" +"`2588 `__","[fund.ts.v2] ""Convertible to bool"" requirement in conjunction and disjunction","Issaquah","" +"`2589 `__","match_results can't satisfy the requirements of a container","Issaquah","|Complete|" +"`2591 `__","std::function's member template target() should not lead to undefined behaviour","Issaquah","|Complete|" +"`2598 `__","addressof works on temporaries","Issaquah","|Complete|" +"`2664 `__","operator/ (and other append) semantics not useful if argument has root","Issaquah","|Complete|" +"`2665 `__","remove_filename() post condition is incorrect","Issaquah","|Complete|" +"`2672 `__","Should ``is_empty``\ use error_code in its specification?","Issaquah","|Complete|" +"`2678 `__","std::filesystem enum classes overspecified","Issaquah","|Complete|" +"`2679 `__","Inconsistent Use of Effects and Equivalent To","Issaquah","|Complete|" +"`2680 `__","Add ""Equivalent to"" to filesystem","Issaquah","|Complete|" +"`2681 `__","filesystem::copy() cannot copy symlinks","Issaquah","|Complete|" +"`2682 `__","filesystem::copy() won't create a symlink to a directory","Issaquah","|Complete|" +"`2686 `__","Why is std::hash specialized for error_code, but not error_condition?","Issaquah","|Complete|" +"`2694 `__","Application of LWG 436 accidentally deleted definition of ""facet""","Issaquah","|Complete|" +"`2696 `__","Interaction between make_shared and enable_shared_from_this is underspecified","Issaquah","|Nothing To Do|" +"`2699 `__","Missing restriction in [numeric.requirements]","Issaquah","|Complete|" +"`2712 `__","copy_file(from, to, ...) has a number of unspecified error conditions","Issaquah","|Complete|" +"`2722 `__","equivalent incorrectly specifies throws clause","Issaquah","|Complete|" +"`2729 `__","Missing SFINAE on std::pair::operator=","Issaquah","" +"`2732 `__","Questionable specification of path::operator/= and path::append","Issaquah","|Complete|" +"`2733 `__","[fund.ts.v2] gcd / lcm and bool","Issaquah","|Complete|" +"`2735 `__","std::abs(short), std::abs(signed char) and others should return int instead of double in order to be compatible with C++98 and C","Issaquah","|Complete|" +"`2736 `__","nullopt_t insufficiently constrained","Issaquah","|Complete|" +"`2738 `__","``is_constructible``\ with void types","Issaquah","|Complete|" +"`2739 `__","Issue with time_point non-member subtraction with an unsigned duration","Issaquah","|Complete|" +"`2740 `__","constexpr optional::operator->","Issaquah","|Complete|" +"`2742 `__","Inconsistent string interface taking string_view","Issaquah","|Complete|" +"`2744 `__","any's in_place constructors","Issaquah","|Complete|" +"`2745 `__","[fund.ts.v2] Implementability of LWG 2451","Issaquah","|Complete|" +"`2747 `__","Possibly redundant std::move in [alg.foreach]","Issaquah","|Complete|" +"`2748 `__","swappable traits for optionals","Issaquah","|Complete|" +"`2749 `__","swappable traits for variants","Issaquah","|Complete|" +"`2750 `__","[fund.ts.v2] LWG 2451 conversion constructor constraint","Issaquah","|Nothing To Do|" +"`2752 `__","""Throws:"" clauses of async and packaged_task are unimplementable","Issaquah","" +"`2755 `__","[string.view.io] uses non-existent basic_string_view::to_string function","Issaquah","|Complete|" +"`2756 `__","C++ WP optional should 'forward' T's implicit conversions","Issaquah","|Complete|" +"`2758 `__","std::string{}.assign(""ABCDE"", 0, 1) is ambiguous","Issaquah","|Complete|" +"`2759 `__","gcd / lcm and bool for the WP","Issaquah","|Complete|" +"`2760 `__","non-const basic_string::data should not invalidate iterators","Issaquah","|Complete|" +"`2765 `__","Did LWG 1123 go too far?","Issaquah","|Complete|" +"`2767 `__","not_fn call_wrapper can form invalid types","Issaquah","|Complete|" +"`2769 `__","Redundant const in the return type of any_cast(const any&)","Issaquah","|Complete|" +"`2771 `__","Broken Effects of some basic_string::compare functions in terms of basic_string_view","Issaquah","|Complete|" +"`2773 `__","Making std::ignore constexpr","Issaquah","|Complete|" +"`2777 `__","basic_string_view::copy should use char_traits::copy","Issaquah","|Complete|" +"`2778 `__","basic_string_view is missing constexpr","Issaquah","|Complete|" +"","","","" +"`2260 `__","Missing requirement for Allocator::pointer","Kona","|Complete|" +"`2676 `__","Provide filesystem::path overloads for File-based streams","Kona","|Complete|" +"`2768 `__","any_cast and move semantics","Kona","|Complete|" +"`2769 `__","Redundant const in the return type of any_cast(const any&)","Kona","|Complete|" +"`2781 `__","Contradictory requirements for std::function and std::reference_wrapper","Kona","|Complete|" +"`2782 `__","scoped_allocator_adaptor constructors must be constrained","Kona","|Complete|" +"`2784 `__","Resolution to LWG 2484 is missing ""otherwise, no effects"" and is hard to parse","Kona","|Complete|" +"`2785 `__","quoted should work with basic_string_view","Kona","|Complete|" +"`2786 `__","Annex C should mention shared_ptr changes for array support","Kona","|Complete|" +"`2787 `__","|sect|\ [file_status.cons] doesn't match class definition","Kona","|Complete|" +"`2788 `__","basic_string range mutators unintentionally require a default constructible allocator","Kona","|Complete|" +"`2789 `__","Equivalence of contained objects","Kona","|Complete|" +"`2790 `__","Missing specification of istreambuf_iterator::operator->","Kona","|Complete|" +"`2794 `__","Missing requirements for allocator pointers","Kona","|Nothing To Do|" +"`2795 `__","|sect|\ [global.functions] provides incorrect example of ADL use","Kona","|Complete|" +"`2796 `__","tuple should be a literal type","Kona","|Complete|" +"`2801 `__","Default-constructibility of unique_ptr","Kona","|Complete|" +"`2802 `__","shared_ptr constructor requirements for a deleter","Kona","" +"`2804 `__","Unconditional constexpr default constructor for istream_iterator","Kona","|Complete|" +"`2806 `__","Base class of bad_optional_access","Kona","|Complete|" +"`2807 `__","std::invoke should use ``std::is_nothrow_callable``\ ","Kona","|Complete|" +"`2812 `__","Range access is available with ","Kona","|Complete|" +"`2824 `__","list::sort should say that the order of elements is unspecified if an exception is thrown","Kona","|Complete|" +"`2826 `__","string_view iterators use old wording","Kona","|Complete|" +"`2834 `__","Resolution LWG 2223 is missing wording about end iterators","Kona","|Complete|" +"`2835 `__","LWG 2536 seems to misspecify ","Kona","|Complete|" +"`2837 `__","gcd and lcm should support a wider range of input values","Kona","|Complete|" +"`2838 `__","is_literal_type specification needs a little cleanup","Kona","|Complete|" +"`2842 `__","in_place_t check for optional::optional(U&&) should decay U","Kona","|Complete|" +"`2850 `__","std::function move constructor does unnecessary work","Kona","|Complete|" +"`2853 `__","Possible inconsistency in specification of erase in [vector.modifiers]","Kona","|Complete|" +"`2855 `__","std::throw_with_nested(""string_literal"")","Kona","|Complete|" +"`2857 `__","{variant,optional,any}::emplace should return the constructed value","Kona","|Complete|" +"`2861 `__","basic_string should require that charT match traits::char_type","Kona","|Complete|" +"`2866 `__","Incorrect derived classes constraints","Kona","|Nothing To Do|" +"`2868 `__","Missing specification of bad_any_cast::what()","Kona","|Complete|" +"`2872 `__","Add definition for direct-non-list-initialization","Kona","|Complete|" +"`2873 `__","Add noexcept to several shared_ptr related functions","Kona","|Complete|" +"`2874 `__","Constructor ``shared_ptr::shared_ptr(Y*)``\ should be constrained","Kona","" +"`2875 `__","shared_ptr::shared_ptr(Y\*, D, [|hellip|\ ]) constructors should be constrained","Kona","" +"`2876 `__","``shared_ptr::shared_ptr(const weak_ptr&)``\ constructor should be constrained","Kona","" +"`2878 `__","Missing DefaultConstructible requirement for istream_iterator default constructor","Kona","|Complete|" +"`2890 `__","The definition of 'object state' applies only to class types","Kona","|Complete|" +"`2900 `__","The copy and move constructors of optional are not constexpr","Kona","|Complete|" +"`2903 `__","The form of initialization for the emplace-constructors is not specified","Kona","|Complete|" +"`2904 `__","Make variant move-assignment more exception safe","Kona","|Complete|" +"`2905 `__","is_constructible_v, P, D const &> should be false when D is not copy constructible","Kona","|Complete|" +"`2908 `__","The less-than operator for shared pointers could do more","Kona","|Complete|" +"`2911 `__","An is_aggregate type trait is needed","Kona","|Complete|" +"`2921 `__","packaged_task and type-erased allocators","Kona","|Complete|" +"`2934 `__","optional doesn't compare with T","Kona","|Complete|" +"","","","" +"`2901 `__","Variants cannot properly support allocators","Toronto","|Complete|" +"`2955 `__","``to_chars / from_chars``\ depend on ``std::string``\ ","Toronto","Resolved by `P0682R1 `__" +"`2956 `__","``filesystem::canonical()``\ still defined in terms of ``absolute(p, base)``\ ","Toronto","|Complete|" diff --git a/libcxx/docs/Cxx1zStatusPaperStatus.csv b/libcxx/docs/Cxx1zStatusPaperStatus.csv new file mode 100644 index 0000000000000..a015529feed06 --- /dev/null +++ b/libcxx/docs/Cxx1zStatusPaperStatus.csv @@ -0,0 +1,113 @@ +"Paper #","Group","Paper Name","Meeting","Status","First released version" +"`N3911 `__","LWG","TransformationTrait Alias ``void_t``\ .","Urbana","|Complete|","3.6" +"`N4089 `__","LWG","Safe conversions in ``unique_ptr``\ .","Urbana","|In Progress|","3.9" +"`N4169 `__","LWG","A proposal to add invoke function template","Urbana","|Complete|","3.7" +"`N4190 `__","LWG","Removing auto_ptr, random_shuffle(), And Old Stuff.","Urbana","|In Progress|","" +"`N4258 `__","LWG","Cleaning-up noexcept in the Library.","Urbana","|In Progress|","3.7" +"`N4259 `__","CWG","Wording for std::uncaught_exceptions","Urbana","|Complete|","3.7" +"`N4277 `__","LWG","TriviallyCopyable ``reference_wrapper``\ .","Urbana","|Complete|","3.2" +"`N4279 `__","LWG","Improved insertion interface for unique-key maps.","Urbana","|Complete|","3.7" +"`N4280 `__","LWG","Non-member size() and more","Urbana","|Complete|","3.6" +"`N4284 `__","LWG","Contiguous Iterators.","Urbana","|Complete|","3.6" +"`N4285 `__","CWG","Cleanup for exception-specification and throw-expression.","Urbana","|Complete|","4.0" +"","","","","","" +"`N4387 `__","LWG","improving pair and tuple","Lenexa","|Complete|","4.0" +"`N4389 `__","LWG","bool_constant","Lenexa","|Complete|","3.7" +"`N4508 `__","LWG","shared_mutex for C++17","Lenexa","|Complete|","3.7" +"`N4366 `__","LWG","LWG 2228 missing SFINAE rule","Lenexa","|Complete|","3.1" +"`N4510 `__","LWG","Minimal incomplete type support for standard containers, revision 4","Lenexa","|Complete|","3.6" +"","","","","","" +"`P0004R1 `__","LWG","Remove Deprecated iostreams aliases.","Kona","|Complete|","3.8" +"`P0006R0 `__","LWG","Adopt Type Traits Variable Templates for C++17.","Kona","|Complete|","3.8" +"`P0092R1 `__","LWG","Polishing ","Kona","|Complete|","3.8" +"`P0007R1 `__","LWG","Constant View: A proposal for a ``std::as_const``\ helper function template.","Kona","|Complete|","3.8" +"`P0156R0 `__","LWG","Variadic lock_guard(rev 3).","Kona","*Reverted in Kona*","3.9" +"`P0074R0 `__","LWG","Making ``std::owner_less``\ more flexible","Kona","|Complete|","3.8" +"`P0013R1 `__","LWG","Logical type traits rev 2","Kona","|Complete|","3.8" +"","","","","","" +"`P0024R2 `__","LWG","The Parallelism TS Should be Standardized","Jacksonville","","" +"`P0226R1 `__","LWG","Mathematical Special Functions for C++17","Jacksonville","","" +"`P0220R1 `__","LWG","Adopt Library Fundamentals V1 TS Components for C++17","Jacksonville","|In Progress|","" +"`P0218R1 `__","LWG","Adopt the File System TS for C++17","Jacksonville","|Complete|","7.0" +"`P0033R1 `__","LWG","Re-enabling shared_from_this","Jacksonville","|Complete|","3.9" +"`P0005R4 `__","LWG","Adopt not_fn from Library Fundamentals 2 for C++17","Jacksonville","|Complete|","3.9" +"`P0152R1 `__","LWG","constexpr ``atomic::is_always_lock_free``\ ","Jacksonville","|Complete|","3.9" +"`P0185R1 `__","LWG","Adding [nothrow-]swappable traits","Jacksonville","|Complete|","3.9" +"`P0253R1 `__","LWG","Fixing a design mistake in the searchers interface","Jacksonville","|Complete|","3.9" +"`P0025R0 `__","LWG","An algorithm to ""clamp"" a value between a pair of boundary values","Jacksonville","|Complete|","3.9" +"`P0154R1 `__","LWG","constexpr std::hardware_{constructive,destructive}_interference_size","Jacksonville","","" +"`P0030R1 `__","LWG","Proposal to Introduce a 3-Argument Overload to std::hypot","Jacksonville","|Complete|","3.9" +"`P0031R0 `__","LWG","A Proposal to Add Constexpr Modifiers to reverse_iterator, move_iterator, array and Range Access","Jacksonville","|Complete|","4.0" +"`P0272R1 `__","LWG","Give ``std::string``\ a non-const ``.data()``\ member function","Jacksonville","|Complete|","3.9" +"`P0077R2 `__","LWG","``is_callable``\ , the missing INVOKE related trait","Jacksonville","|Complete|","3.9" +"","","","","","" +"`p0032r3 `__","LWG","Homogeneous interface for variant, any and optional","Oulu","|Complete|","4.0" +"`p0040r3 `__","LWG","Extending memory management tools","Oulu","|Complete|","4.0" +"`p0063r3 `__","LWG","C++17 should refer to C11 instead of C99","Oulu","|Complete|","7.0" +"`p0067r3 `__","LWG","Elementary string conversions","Oulu","Now `P0067R5 `__","n/a" +"`p0083r3 `__","LWG","Splicing Maps and Sets","Oulu","|Complete|","8.0" +"`p0084r2 `__","LWG","Emplace Return Type","Oulu","|Complete|","4.0" +"`p0088r3 `__","LWG","Variant: a type-safe union for C++17","Oulu","|Complete|","4.0" +"`p0137r1 `__","CWG","Core Issue 1776: Replacement of class objects containing reference members","Oulu","|Complete|","6.0" +"`p0163r0 `__","LWG","shared_ptr::weak_type","Oulu","|Complete|","3.9" +"`p0174r2 `__","LWG","Deprecating Vestigial Library Parts in C++17","Oulu","|Partial|","" +"`p0175r1 `__","LWG","Synopses for the C library","Oulu","","" +"`p0180r2 `__","LWG","Reserve a New Library Namespace for Future Standardization","Oulu","|Nothing To Do|","n/a" +"`p0181r1 `__","LWG","Ordered by Default","Oulu","*Removed in Kona*","n/a" +"`p0209r2 `__","LWG","make_from_tuple: apply for construction","Oulu","|Complete|","3.9" +"`p0219r1 `__","LWG","Relative Paths for Filesystem","Oulu","|Complete|","7.0" +"`p0254r2 `__","LWG","Integrating std::string_view and std::string","Oulu","|Complete|","4.0" +"`p0258r2 `__","LWG","has_unique_object_representations","Oulu","|Complete|","6.0" +"`p0295r0 `__","LWG","Adopt Selected Library Fundamentals V2 Components for C++17","Oulu","|Complete|","4.0" +"`p0302r1 `__","LWG","Removing Allocator Support in std::function","Oulu","|Complete|","4.0" +"`p0307r2 `__","LWG","Making Optional Greater Equal Again","Oulu","|Complete|","4.0" +"`p0336r1 `__","LWG","Better Names for Parallel Execution Policies in C++17","Oulu","","" +"`p0337r0 `__","LWG","Delete ``operator=``\ for polymorphic_allocator","Oulu","|Complete|","3.9" +"`p0346r1 `__","LWG","A Nomenclature Tweak","Oulu","|Complete|","3.9" +"`p0358r1 `__","LWG","Fixes for not_fn","Oulu","|Complete|","3.9" +"`p0371r1 `__","LWG","Temporarily discourage memory_order_consume","Oulu","|Nothing To Do|","n/a" +"`p0392r0 `__","LWG","Adapting string_view by filesystem paths","Oulu","|Complete|","4.0" +"`p0393r3 `__","LWG","Making Variant Greater Equal","Oulu","|Complete|","4.0" +"`P0394r4 `__","LWG","Hotel Parallelifornia: terminate() for Parallel Algorithms Exception Handling","Oulu","","" +"","","","","","" +"`P0003R5 `__","LWG","Removing Deprecated Exception Specifications from C++17","Issaquah","|Complete|","5.0" +"`P0067R5 `__","LWG","Elementary string conversions, revision 5","Issaquah","|Partial|","" +"`P0403R1 `__","LWG","Literal suffixes for ``basic_string_view``\ ","Issaquah","|Complete|","4.0" +"`P0414R2 `__","LWG","Merging shared_ptr changes from Library Fundamentals to C++17","Issaquah","|Complete|","11.0" +"`P0418R2 `__","LWG","Fail or succeed: there is no atomic lattice","Issaquah","","" +"`P0426R1 `__","LWG","Constexpr for ``std::char_traits``\ ","Issaquah","|Complete|","4.0" +"`P0435R1 `__","LWG","Resolving LWG Issues re ``common_type``\ ","Issaquah","|Complete|","4.0" +"`P0502R0 `__","LWG","Throwing out of a parallel algorithm terminates - but how?","Issaquah","","" +"`P0503R0 `__","LWG","Correcting library usage of ""literal type""","Issaquah","|Complete|","4.0" +"`P0504R0 `__","LWG","Revisiting in-place tag types for any/optional/variant","Issaquah","|Complete|","4.0" +"`P0505R0 `__","LWG","Wording for GB 50 - constexpr for chrono","Issaquah","|Complete|","4.0" +"`P0508R0 `__","LWG","Wording for GB 58 - structured bindings for node_handles","Issaquah","","" +"`P0509R1 `__","LWG","Updating ""Restrictions on exception handling""","Issaquah","|Nothing To Do|","n/a" +"`P0510R0 `__","LWG","Disallowing references, incomplete types, arrays, and empty variants","Issaquah","|Complete|","4.0" +"`P0513R0 `__","LWG","Poisoning the Hash","Issaquah","|Complete|","5.0" +"`P0516R0 `__","LWG","Clarify That shared_future's Copy Operations have Wide Contracts","Issaquah","|Complete|","4.0" +"`P0517R0 `__","LWG","Make future_error Constructible","Issaquah","|Complete|","4.0" +"`P0521R0 `__","LWG","Proposed Resolution for CA 14 (shared_ptr use_count/unique)","Issaquah","|Nothing To Do|","n/a" +"","","","","","" +"`P0156R2 `__","LWG","Variadic Lock guard(rev 5)","Kona","|Complete|","5.0" +"`P0270R3 `__","CWG","Removing C dependencies from signal handler wording","Kona","","" +"`P0298R3 `__","CWG","A byte type definition","Kona","|Complete|","5.0" +"`P0317R1 `__","LWG","Directory Entry Caching for Filesystem","Kona","|Complete|","7.0" +"`P0430R2 `__","LWG","File system library on non-POSIX-like operating systems","Kona","|Complete|","7.0" +"`P0433R2 `__","LWG","Toward a resolution of US7 and US14: Integrating template deduction for class templates into the standard library","Kona","|In Progress| [#note-P0433]_","7.0" +"`P0452R1 `__","LWG","Unifying Parallel Algorithms","Kona","","" +"`P0467R2 `__","LWG","Iterator Concerns for Parallel Algorithms","Kona","","" +"`P0492R2 `__","LWG","Proposed Resolution of C++17 National Body Comments for Filesystems","Kona","|Complete|","7.0" +"`P0518R1 `__","LWG","Allowing copies as arguments to function objects given to parallel algorithms in response to CH11","Kona","","" +"`P0523R1 `__","LWG","Wording for CH 10: Complexity of parallel algorithms","Kona","","" +"`P0548R1 `__","LWG","common_type and duration","Kona","|Complete|","5.0" +"`P0558R1 `__","LWG","Resolving atomic named base class inconsistencies","Kona","","" +"`P0574R1 `__","LWG","Algorithm Complexity Constraints and Parallel Overloads","Kona","","" +"`P0599R1 `__","LWG","noexcept for hash functions","Kona","|Complete|","5.0" +"`P0604R0 `__","LWG","Resolving GB 55, US 84, US 85, US 86","Kona","|Complete|","" +"`P0607R0 `__","LWG","Inline Variables for the Standard Library","Kona","|In Progress| [#note-P0607]_","6.0" +"`P0618R0 `__","LWG","Deprecating ","Kona","","" +"`P0623R0 `__","LWG","Final C++17 Parallel Algorithms Fixes","Kona","","" +"","","","","","" +"`P0682R1 `__","LWG","Repairing elementary string conversions","Toronto","","" +"`P0739R0 `__","LWG","Some improvements to class template argument deduction integration into the standard library","Toronto","|Complete|","5.0" diff --git a/libcxx/docs/Cxx2aStatus.rst b/libcxx/docs/Cxx2aStatus.rst new file mode 100644 index 0000000000000..fc5b779aecc98 --- /dev/null +++ b/libcxx/docs/Cxx2aStatus.rst @@ -0,0 +1,57 @@ +.. _cxx2a-status: + +================================ +libc++ C++2a Status +================================ + +.. include:: Helpers/Styles.rst + +.. contents:: + :local: + + +Overview +================================ + +In July 2017, the C++ standard committee created a draft for the next version of the C++ standard, known here as "C++2a" (probably to be C++20). + +This page shows the status of libc++; the status of clang's support of the language features is `here `__. + +.. attention:: Features in unreleased drafts of the standard are subject to change. + +The groups that have contributed papers: + +- CWG - Core Language Working group +- LWG - Library working group +- SG1 - Study group #1 (Concurrency working group) + +.. note:: "Nothing to do" means that no library changes were needed to implement this change. + +.. _paper-status-cxx2a: + +Paper Status +==================================== + +.. csv-table:: + :file: Cxx2aStatusPaperStatus.csv + :widths: auto + +.. note:: + + .. [#note-P0202] P0202: The missing bits in P0202 are in ``copy`` and ``copy_backwards`` (and the ones that call them: ``copy_n``, ``set_union``, ``set_difference``, and ``set_symmetric_difference``). This is because the first two algorithms have specializations that call ``memmove`` which is not constexpr. See `Bug 25165 `__ + .. [#note-P0600] P0600: The missing bits in P0600 are in |sect|\ [mem.res.class], |sect|\ [mem.poly.allocator.class], and |sect|\ [container.node.overview]. + .. [#note-P0966] P0966: It was previously erroneously marked as complete in version 8.0. See `bug 45368 `__. + + .. [#note-P0619] P0619: Only ``std::allocator`` part is implemented. + + +.. _issues-status-cxx2a: + +Library Working Group Issues Status +==================================== + +.. csv-table:: + :file: Cxx2aStatusIssuesStatus.csv + :widths: auto + +Last Updated: 24-Nov-2020 diff --git a/libcxx/docs/Cxx2aStatusIssuesStatus.csv b/libcxx/docs/Cxx2aStatusIssuesStatus.csv new file mode 100644 index 0000000000000..8fc666717987b --- /dev/null +++ b/libcxx/docs/Cxx2aStatusIssuesStatus.csv @@ -0,0 +1,299 @@ +"Issue #","Issue Name","Meeting","Status" +"`2070 `__","``allocate_shared``\ should use ``allocator_traits::construct``\ ","Toronto","Resolved by `P0674R1 `__" +"`2444 `__","Inconsistent complexity for ``std::sort_heap``\ ","Toronto","" +"`2593 `__","Moved-from state of Allocators","Toronto","" +"`2597 `__","``std::log``\ misspecified for complex numbers","Toronto","" +"`2783 `__","``stack::emplace()``\ and ``queue::emplace()``\ should return ``decltype(auto)``\ ","Toronto","|Complete|" +"`2932 `__","Constraints on parallel algorithm implementations are underspecified","Toronto","" +"`2937 `__","Is ``equivalent(""existing_thing"", ""not_existing_thing"")``\ an error","Toronto","|Complete|" +"`2940 `__","``result_of``\ specification also needs a little cleanup","Toronto","" +"`2942 `__","LWG 2873's resolution missed ``weak_ptr::owner_before``\ ","Toronto","|Complete|" +"`2954 `__","Specialization of the convenience variable templates should be prohibited","Toronto","|Complete|" +"`2961 `__","Bad postcondition for ``set_default_resource``\ ","Toronto","" +"`2966 `__","Incomplete resolution of US 74","Toronto","|Nothing To Do|" +"`2974 `__","Diagnose out of bounds ``tuple_element/variant_alternative``\ ","Toronto","|Complete|" +"","","","" +"`2779 `__","[networking.ts] Relax requirements on buffer sequence iterators","Albuquerque","" +"`2870 `__","Default value of parameter theta of polar should be dependent","Albuquerque","|Complete|" +"`2935 `__","What should create_directories do when p already exists but is not a directory?","Albuquerque","" +"`2941 `__","[thread.req.timing] wording should apply to both member and namespace-level functions","Albuquerque","|Nothing To Do|" +"`2944 `__","LWG 2905 accidentally removed requirement that construction of the deleter doesn't throw an exception","Albuquerque","|Nothing To Do|" +"`2945 `__","Order of template parameters in optional comparisons","Albuquerque","|Complete|" +"`2948 `__","unique_ptr does not define operator<< for stream output","Albuquerque","|Complete|" +"`2950 `__","std::byte operations are misspecified","Albuquerque","|Complete|" +"`2952 `__","iterator_traits should work for pointers to cv T","Albuquerque","|Complete|" +"`2953 `__","LWG 2853 should apply to deque::erase too","Albuquerque","|Complete|" +"`2958 `__","Moves improperly defined as deleted","Albuquerque","*We already do this*" +"`2964 `__","Apparently redundant requirement for dynamic_pointer_cast","Albuquerque","" +"`2965 `__","Non-existing path::native_string() in filesystem_error::what() specification","Albuquerque","|Nothing To Do|" +"`2972 `__","What is ``is_trivially_destructible_v``\ ?","Albuquerque","|Complete|" +"`2976 `__","Dangling uses_allocator specialization for packaged_task","Albuquerque","|Complete|" +"`2977 `__","unordered_meow::merge() has incorrect Throws: clause","Albuquerque","|Nothing To Do|" +"`2978 `__","Hash support for pmr::string and friends","Albuquerque","" +"`2979 `__","aligned_union should require complete object types","Albuquerque","|Complete|" +"`2980 `__","Cannot compare_exchange empty pointers","Albuquerque","" +"`2981 `__","Remove redundant deduction guides from standard library","Albuquerque","" +"`2982 `__","Making size_type consistent in associative container deduction guides","Albuquerque","" +"`2988 `__","Clause 32 cleanup missed one typename","Albuquerque","" +"`2993 `__","reference_wrapper conversion from T&&","Albuquerque","" +"`2998 `__","Requirements on function objects passed to {``forward_``,}list-specific algorithms","Albuquerque","|Nothing To Do|" +"`3001 `__","weak_ptr::element_type needs remove_extent_t","Albuquerque","" +"`3024 `__","variant's copies must be deleted instead of disabled via SFINAE","Albuquerque","|Complete|" +"","","","" +"`2164 `__","What are the semantics of ``vector.emplace(vector.begin(), vector.back())``\ ?","Jacksonville","|Complete|" +"`2243 `__","``istream::putback``\ problem","Jacksonville","|Complete|" +"`2816 `__","``resize_file``\ has impossible postcondition","Jacksonville","|Nothing To Do|" +"`2843 `__","Unclear behavior of ``std::pmr::memory_resource::do_allocate()``\ ","Jacksonville","|Complete|" +"`2849 `__","Why does ``!is_regular_file(from)``\ cause ``copy_file``\ to report a ""file already exists"" error?","Jacksonville","|Nothing To Do|" +"`2851 `__","``std::filesystem``\ enum classes are now underspecified","Jacksonville","|Nothing To Do|" +"`2946 `__","LWG 2758's resolution missed further corrections","Jacksonville","|Complete|" +"`2969 `__","``polymorphic_allocator::construct()``\ shouldn't pass ``resource()``\ ","Jacksonville","|Complete|" +"`2975 `__","Missing case for ``pair``\ construction in scoped and polymorphic allocators","Jacksonville","" +"`2989 `__","``path``\ 's stream insertion operator lets you insert everything under the sun","Jacksonville","|Complete|" +"`3000 `__","``monotonic_memory_resource::do_is_equal``\ uses ``dynamic_cast``\ unnecessarily","Jacksonville","" +"`3002 `__","[networking.ts] ``basic_socket_acceptor::is_open()``\ isn't ``noexcept``\ ","Jacksonville","" +"`3004 `__","|sect|\ [string.capacity] and |sect|\ [vector.capacity] should specify time complexity for ``capacity()``\ ","Jacksonville","|Nothing To Do|" +"`3005 `__","Destruction order of arrays by ``make_shared/allocate_shared``\ only recommended?","Jacksonville","" +"`3007 `__","``allocate_shared``\ should rebind allocator to *cv*-unqualified ``value_type``\ for construction","Jacksonville","" +"`3009 `__","Including ````\ doesn't provide ``std::size/empty/data``\ ","Jacksonville","|Complete|" +"`3010 `__","[networking.ts] ``uses_executor``\ says ""if a type ``T::executor_type``\ exists""","Jacksonville","" +"`3013 `__","``(recursive_)directory_iterator``\ construction and traversal should not be ``noexcept``\ ","Jacksonville","|Complete|" +"`3014 `__","More ``noexcept``\ issues with filesystem operations","Jacksonville","|Complete|" +"`3015 `__","``copy_options::*unspecified*``\ underspecified","Jacksonville","|Nothing To Do|" +"`3017 `__","``list splice``\ functions should use ``addressof``\ ","Jacksonville","|Complete|" +"`3020 `__","[networking.ts] Remove spurious nested ``value_type``\ buffer sequence requirement","Jacksonville","" +"`3026 `__","``filesystem::weakly_canonical``\ still defined in terms of ``canonical(p, base)``\ ","Jacksonville","|Complete|" +"`3030 `__","Who shall meet the requirements of ``try_lock``\ ?","Jacksonville","|Nothing To Do|" +"`3034 `__","P0767R1 breaks previously-standard-layout types","Jacksonville","|Complete|" +"`3035 `__","``std::allocator``\ 's constructors should be ``constexpr``\ ","Jacksonville","|Complete|" +"`3039 `__","Unnecessary ``decay``\ in ``thread``\ and ``packaged_task``\ ","Jacksonville","|Complete|" +"`3041 `__","Unnecessary ``decay``\ in ``reference_wrapper``\ ","Jacksonville","|Complete|" +"`3042 `__","``is_literal_type_v``\ should be inline","Jacksonville","|Complete|" +"`3043 `__","Bogus postcondition for ``filesystem_error``\ constructor","Jacksonville","|Complete|" +"`3045 `__","``atomic<*floating-point*>``\ doesn't have ``value_type``\ or ``difference_type``\ ","Jacksonville","" +"`3048 `__","``transform_reduce(exec, first1, last1, first2, init)``\ discards execution policy","Jacksonville","" +"`3051 `__","Floating point classifications were inadvertently changed in P0175","Jacksonville","|Nothing To Do|" +"`3075 `__","``basic_string``\ needs deduction guides from ``basic_string_view``\ ","Jacksonville","|Complete|" +"","","","" +"`2139 `__","What is a user-defined type?","Rapperswil","" +"`2970 `__","Return type of std::visit misspecified","Rapperswil","" +"`3058 `__","Parallel adjacent_difference shouldn't require creating temporaries","Rapperswil","" +"`3062 `__","Unnecessary decay_t in is_execution_policy_v should be remove_cvref_t","Rapperswil","" +"`3067 `__","recursive_directory_iterator::pop must invalidate","Rapperswil","|Nothing To Do|" +"`3071 `__","[networking.ts] read_until still refers to ""input sequence""","Rapperswil","|Nothing To Do|" +"`3074 `__","Non-member functions for valarray should only deduce from the valarray","Rapperswil","" +"`3076 `__","basic_string CTAD ambiguity","Rapperswil","|Complete|" +"`3079 `__","LWG 2935 forgot to fix the existing_p overloads of create_directory","Rapperswil","" +"`3080 `__","Floating point from_chars pattern specification breaks round-tripping","Rapperswil","" +"`3083 `__","What should ios::iword(-1) do?","Rapperswil","|Nothing To Do|" +"`3094 `__","[time.duration.io]p4 makes surprising claims about encoding","Rapperswil","" +"`3100 `__","Unnecessary and confusing ""empty span"" wording","Rapperswil","|Nothing To Do|" +"`3102 `__","Clarify span iterator and ``const_iterator`` behavior","Rapperswil","|Complete|" +"`3104 `__","Fixing duration division","Rapperswil","|Complete|" +"","","","" +"`2183 `__","Muddled allocator requirements for ``match_results``\ constructors","San Diego","|Complete|" +"`2184 `__","Muddled allocator requirements for ``match_results``\ assignments","San Diego","|Complete|" +"`2412 `__","``promise::set_value()``\ and ``promise::get_future()``\ should not race","San Diego","" +"`2499 `__","``operator>>(basic_istream&, CharT*)``\ makes it hard to avoid buffer overflows","San Diego","Resolved by P0487R1" +"`2682 `__","``filesystem::copy()``\ won't create a symlink to a directory","San Diego","|Nothing To Do|" +"`2697 `__","[concurr.ts] Behavior of ``future/shared_future``\ unwrapping constructor when given an invalid ``future``\ ","San Diego","" +"`2797 `__","Trait precondition violations","San Diego","Resolved by 1285R0" +"`2936 `__","Path comparison is defined in terms of the generic format","San Diego","|Complete|" +"`2943 `__","Problematic specification of the wide version of ``basic_filebuf::open``\ ","San Diego","|Nothing To Do|" +"`2960 `__","[fund.ts.v3] ``nonesuch``\ is insufficiently useless","San Diego","|Complete|" +"`2995 `__","``basic_stringbuf``\ default constructor forbids it from using SSO capacity","San Diego","" +"`2996 `__","Missing rvalue overloads for ``shared_ptr``\ operations","San Diego","" +"`3008 `__","``make_shared``\ (sub)object destruction semantics are not specified","San Diego","" +"`3022 `__","``is_convertible``\ may lead to ODR","San Diego","Resolved by 1285R0" +"`3025 `__","Map-like container deduction guides should use ``pair``\ , not ``pair``\ ","San Diego","|Complete|" +"`3031 `__","Algorithms and predicates with non-const reference arguments","San Diego","" +"`3037 `__","``polymorphic_allocator``\ and incomplete types","San Diego","" +"`3038 `__","``polymorphic_allocator::allocate``\ should not allow integer overflow to create vulnerabilities","San Diego","" +"`3054 `__","``uninitialized_copy``\ appears to not be able to meet its exception-safety guarantee","San Diego","" +"`3065 `__","LWG 2989 missed that all ``path``\ 's other operators should be hidden friends as well","San Diego","|Complete|" +"`3096 `__","``path::lexically_relative``\ is confused by trailing slashes","San Diego","|Complete|" +"`3116 `__","``*OUTERMOST_ALLOC_TRAITS*``\ needs ``remove_reference_t``\ ","San Diego","" +"`3122 `__","``__cpp_lib_chrono_udls``\ was accidentally dropped","San Diego","|Complete|" +"`3127 `__","``basic_osyncstream::rdbuf``\ needs a ````const_cast````\ ","San Diego","" +"`3128 `__","``strstream::rdbuf``\ needs a ````const_cast````\ ","San Diego","|Nothing To Do|" +"`3129 `__","``regex_token_iterator``\ constructor uses wrong pointer arithmetic","San Diego","" +"`3130 `__","|sect|\ [input.output] needs many ``addressof``\ ","San Diego","" +"`3131 `__","``addressof``\ all the things","San Diego","" +"`3132 `__","Library needs to ban macros named ``expects``\ or ``ensures``\ ","San Diego","|Nothing To Do|" +"`3134 `__","[fund.ts.v3] LFTSv3 contains extraneous [meta] variable templates that should have been deleted by P09961","San Diego","Resolved by P1210R0" +"`3137 `__","Header for ``__cpp_lib_to_chars``\ ","San Diego","|Complete|" +"`3145 `__","``file_clock``\ breaks ABI for C++17 implementations","San Diego","|Complete|" +"`3147 `__","Definitions of ""likely"" and ""unlikely"" are likely to cause problems","San Diego","" +"`3148 `__","````\ should be freestanding","San Diego","" +"`3153 `__","``Common``\ and ``common_type``\ have too little in common","San Diego","" +"`3154 `__","``Common``\ and ``CommonReference``\ have a common defect","San Diego","" +"","","","" +"`3012 `__","``atomic``\ is unimplementable for non-``is_trivially_copy_constructible T``\ ","Kona","" +"`3040 `__","``basic_string_view::starts_with``\ *Effects* are incorrect","Kona","|Complete|" +"`3077 `__","``(push|emplace)_back``\ should invalidate the ``end``\ iterator","Kona","|Nothing To Do|" +"`3087 `__","One final ``&x``\ in |sect|\ [list.ops]","Kona","|Nothing To Do|" +"`3101 `__","``span``\ 's ``Container``\ constructors need another constraint","Kona","|Complete|" +"`3112 `__","``system_error``\ and ``filesystem_error``\ constructors taking a ``string``\ may not be able to meet their postconditions","Kona","" +"`3119 `__","Program-definedness of closure types","Kona","|Nothing To Do|" +"`3133 `__","Modernizing numeric type requirements","Kona","" +"`3144 `__","``span``\ does not have a ````const_pointer````\ typedef","Kona","|Complete|" +"`3173 `__","Enable CTAD for *``ref-view``*\ ","Kona","" +"`3179 `__","``subrange``\ should always model ``Range``\ ","Kona","" +"`3180 `__","Inconsistently named return type for ``ranges::minmax_element``\ ","Kona","" +"`3182 `__","Specification of ``Same``\ could be clearer","Kona","" +"","","","" +"`2899 `__","``is_(nothrow_)move_constructible``\ and ``tuple``\ , ``optional``\ and ``unique_ptr``\ ","Cologne","" +"`3055 `__","``path::operator+=(*single-character*)``\ misspecified","Cologne","" +"`3158 `__","``tuple(allocator_arg_t, const Alloc&)``\ should be conditionally explicit","Cologne","" +"`3169 `__","``ranges``\ permutation generators discard useful information","Cologne","" +"`3183 `__","Normative permission to specialize Ranges variable templates","Cologne","" +"`3184 `__","Inconsistencies in ``bind_front``\ wording","Cologne","" +"`3185 `__","Uses-allocator construction functions missing ``constexpr``\ and ``noexcept``\ ","Cologne","" +"`3186 `__","``ranges``\ removal, partition, and ``partial_sort_copy``\ algorithms discard useful information","Cologne","" +"`3187 `__","`P0591R4 `__ reverted DR 2586 fixes to ``scoped_allocator_adaptor::construct()``\ ","Cologne","" +"`3191 `__","``std::ranges::shuffle``\ synopsis does not match algorithm definition","Cologne","" +"`3196 `__","``std::optional``\ is ill-formed is ``T``\ is an array","Cologne","|Complete|" +"`3198 `__","Bad constraint on ``std::span::span()``\ ","Cologne","|Complete|" +"`3199 `__","``istream >> bitset<0>``\ fails","Cologne","" +"`3202 `__","P0318R1 was supposed to be revised","Cologne","|Complete|" +"`3206 `__","``year_month_day``\ conversion to ``sys_days``\ uses not-existing member function","Cologne","|Complete|" +"`3208 `__","``Boolean``\ 's expression requirements are ordered inconsistently","Cologne","|Nothing To Do|" +"`3209 `__","Expression in ``year::ok()``\ returns clause is ill-formed","Cologne","|Complete|" +"","","","" +"`3231 `__","``year_month_day_last::day``\ specification does not cover ``!ok()``\ values","Belfast","|Nothing To Do|" +"`3225 `__","``zoned_time``\ converting constructor shall not be ``noexcept``\ ","Belfast","" +"`3190 `__","``std::allocator::allocate``\ sometimes returns too little storage","Belfast","" +"`3218 `__","Modifier for ``%d``\ parse flag does not match POSIX and ``format``\ specification","Belfast","" +"`3224 `__","``zoned_time``\ constructor from ``TimeZonePtr``\ does not specify initialization of ``tp_``\ ","Belfast","" +"`3230 `__","Format specifier ``%y/%Y``\ is missing locale alternative versions","Belfast","" +"`3232 `__","Inconsistency in ``zoned_time``\ deduction guides","Belfast","" +"`3222 `__","P0574R1 introduced preconditions on non-existent parameters","Belfast","" +"`3221 `__","Result of ``year_month``\ arithmetic with ``months``\ is ambiguous","Belfast","" +"`3235 `__","``parse``\ manipulator without abbreviation is not callable","Belfast","" +"`3246 `__","What are the constraints on the template parameter of ``basic_format_arg``\ ?","Belfast","" +"`3253 `__","``basic_syncbuf::basic_syncbuf()``\ should not be explicit","Belfast","" +"`3245 `__","Unnecessary restriction on ``'%p'``\ parse specifier","Belfast","" +"`3244 `__","Constraints for ``Source``\ in |sect|\ [fs.path.req] insufficiently constrainty","Belfast","" +"`3241 `__","``chrono-spec``\ grammar ambiguity in |sect|\ [time.format]","Belfast","" +"`3257 `__","Missing feature testing macro update from P0858","Belfast","" +"`3256 `__","Feature testing macro for ``constexpr``\ algorithms","Belfast","" +"`3273 `__","Specify ``weekday_indexed``\ to range of ``[0, 7]``\ ","Belfast","" +"`3070 `__","``path::lexically_relative``\ causes surprising results if a filename can also be a *root-name*","Belfast","" +"`3266 `__","``to_chars(bool)``\ should be deleted","Belfast","" +"`3272 `__","``%I%p``\ should parse/format ``duration``\ since midnight","Belfast","" +"`3259 `__","The definition of *constexpr iterators* should be adjusted","Belfast","" +"`3103 `__","Errors in taking subview of ``span``\ should be ill-formed where possible","Belfast","" +"`3274 `__","Missing feature test macro for ````\ ","Belfast","" +"`3276 `__","Class ``split_view::outer_iterator::value_type``\ should inherit from ``view_interface``\ ","Belfast","" +"`3277 `__","Pre-increment on prvalues is not a requirement of ``weakly_incrementable``\ ","Belfast","" +"`3149 `__","``DefaultConstructible``\ should require default initialization","Belfast","" +"","","","" +"`1203 `__","More useful rvalue stream insertion","Prague","12.0" +"`2859 `__","Definition of *reachable* in [ptr.launder] misses pointer arithmetic from pointer-interconvertible object","Prague","" +"`3018 `__","``shared_ptr``\ of function type","Prague","" +"`3050 `__","Conversion specification problem in ``chrono::duration``\ constructor","Prague","" +"`3141 `__","``CopyConstructible``\ doesn't preserve source values","Prague","" +"`3150 `__","``UniformRandomBitGenerator``\ should validate ``min``\ and ``max``\ ","Prague","" +"`3175 `__","The ``CommonReference``\ requirement of concept ``SwappableWith``\ is not satisfied in the example","Prague","" +"`3194 `__","``ConvertibleTo``\ prose does not match code","Prague","" +"`3200 `__","``midpoint``\ should not constrain ``T``\ is complete","Prague","" +"`3201 `__","``lerp``\ should be marked as ``noexcept``\ ","Prague","|Complete|" +"`3226 `__","``zoned_time``\ constructor from ``string_view``\ should accept ``zoned_time``\ ","Prague","" +"`3233 `__","Broken requirements for ``shared_ptr``\ converting constructors","Prague","" +"`3237 `__","LWG 3038 and 3190 have inconsistent PRs","Prague","" +"`3238 `__","Insufficiently-defined behavior of ``std::function``\ deduction guides","Prague","" +"`3242 `__","``std::format``\ : missing rules for ``arg-id``\ in ``width``\ and ``precision``\ ","Prague","" +"`3243 `__","``std::format``\ and negative zeroes","Prague","" +"`3247 `__","``ranges::iter_move``\ should perform ADL-only lookup of ``iter_move``\ ","Prague","" +"`3248 `__","``std::format``\ ``#b``\ , ``#B``\ , ``#o``\ , ``#x``\ , and ``#X``\ presentation types misformat negative numbers","Prague","" +"`3250 `__","``std::format``\ : ``#``\ (alternate form) for NaN and inf","Prague","" +"`3251 `__","Are ``std::format``\ alignment specifiers applied to string arguments?","Prague","" +"`3252 `__","Parse locale's aware modifiers for commands are not consistent with POSIX spec","Prague","" +"`3254 `__","Strike ``stop_token``\ 's ``operator!=``\ ","Prague","" +"`3255 `__","``span``\ 's ``array``\ constructor is too strict","Prague","|Complete|" +"`3260 `__","``year_month*``\ arithmetic rejects durations convertible to years","Prague","" +"`3262 `__","Formatting of negative durations is not specified","Prague","" +"`3264 `__","``sized_range``\ and ``ranges::size``\ redundantly use ``disable_sized_range``\ ","Prague","" +"`3269 `__","Parse manipulators do not specify the result of the extraction from stream","Prague","" +"`3270 `__","Parsing and formatting ``%j``\ with ``duration``\ s","Prague","" +"`3280 `__","View converting constructors can cause constraint recursion and are unneeded","Prague","" +"`3281 `__","Conversion from ``*pair-like*``\ types to ``subrange``\ is a silent semantic promotion","Prague","" +"`3282 `__","``subrange``\ converting constructor should disallow derived to base conversions","Prague","" +"`3284 `__","``random_access_iterator``\ semantic constraints accidentally promote difference type using unary negate","Prague","" +"`3285 `__","The type of a customization point object shall satisfy ``semiregular``\ ","Prague","" +"`3286 `__","``ranges::size``\ is not required to be valid after a call to ``ranges::begin``\ on an input range","Prague","" +"`3291 `__","``iota_view::iterator``\ has the wrong ``iterator_category``\ ","Prague","" +"`3292 `__","``iota_view``\ is under-constrained","Prague","" +"`3294 `__","``zoned_time``\ deduction guides misinterprets ``string``\ /``char*``\ ","Prague","" +"`3296 `__","Inconsistent default argument for ``basic_regex<>::assign``\ ","Prague","|Complete|" +"`3299 `__","Pointers don't need customized iterator behavior","Prague","" +"`3300 `__","Non-array ``ssize``\ overload is underconstrained","Prague","" +"`3301 `__","``transform_view::iterator``\ has incorrect ``iterator_category``\ ","Prague","" +"`3302 `__","Range adaptor objects ``keys``\ and ``values``\ are unspecified","Prague","" +"`3303 `__","Bad ""``constexpr``\ "" marker for ``destroy/destroy_n``\ ","Prague","" +"`3304 `__","Allocate functions of ``std::polymorphic_allocator``\ should require ``[[nodiscard]]``\ ","Prague","" +"`3307 `__","``std::allocator().allocate(n)``\ ","Prague","" +"`3310 `__","Replace ``SIZE_MAX``\ with ``numeric_limits::max()``\ ","Prague","" +"`3313 `__","``join_view::iterator::operator--``\ is incorrectly constrained","Prague","" +"`3314 `__","Is stream insertion behavior locale dependent when ``Period::type``\ is ``micro``\ ?","Prague","" +"`3315 `__","Correct Allocator Default Behavior","Prague","" +"`3316 `__","Correctly define epoch for ``utc_clock``\ / ``utc_timepoint``\ ","Prague","" +"`3317 `__","Incorrect ``operator<<``\ for floating-point durations","Prague","" +"`3318 `__","Clarify whether clocks can represent time before their epoch","Prague","" +"`3319 `__","Properly reference specification of IANA time zone database","Prague","" +"`3320 `__","``span::cbegin/cend``\ methods produce different results than ``std::[ranges::]cbegin/cend``\ ","Prague","|Complete|" +"`3321 `__","``uninitialized_construct_using_allocator``\ should use ``construct_at``\ ","Prague","" +"`3323 `__","``*has-tuple-element*``\ helper concept needs ``convertible_to``\ ","Prague","" +"`3324 `__","Special-case ``std::strong/weak/partial_order``\ for pointers","Prague","" +"`3325 `__","Constrain return type of transformation function for ``transform_view``\ ","Prague","" +"`3326 `__","``enable_view``\ has false positives","Prague","" +"`3327 `__","Format alignment specifiers vs. text direction","Prague","" +"`3328 `__","Clarify that ``std::string``\ is not good for UTF-8","Prague","" +"`3329 `__","``totally_ordered_with``\ both directly and indirectly requires ``common_reference_with``\ ","Prague","" +"`3330 `__","Include ````\ from most library headers","Prague","" +"`3331 `__","Define ``totally_ordered/_with``\ in terms of ``*partially-ordered-with*``\ ","Prague","" +"`3332 `__","Issue in |sect|\ [time.format]","Prague","" +"`3334 `__","``basic_osyncstream``\ move assignment and destruction calls ``basic_syncbuf::emit()``\ twice","Prague","" +"`3335 `__","Resolve C++20 NB comments US 273 and GB 274","Prague","" +"`3338 `__","Rename ``default_constructible``\ to ``default_initializable``\ ","Prague","" +"`3340 `__","Formatting functions should throw on argument/format string mismatch in |sect|\ [format.functions]","Prague","" +"`3346 `__","``pair``\ and ``tuple``\ copy and move constructor have backwards specification","Prague","" +"`3347 `__","``std::pair``\ now requires ``T``\ and ``U``\ to be less-than-comparable","Prague","" +"`3348 `__","``__cpp_lib_unwrap_ref``\ in wrong header","Prague","" +"`3349 `__","Missing ``__cpp_lib_constexpr_complex``\ for P0415R1","Prague","" +"`3350 `__","Simplify return type of ``lexicographical_compare_three_way``\ ","Prague","" +"`3351 `__","``ranges::enable_safe_range``\ should not be constrained","Prague","" +"`3352 `__","``strong_equality``\ isn't a thing","Prague","" +"`3354 `__","``has_strong_structural_equality``\ has a meaningless definition","Prague","" +"`3355 `__","The memory algorithms should support move-only input iterators introduced by P1207","Prague","" +"`3356 `__","``__cpp_lib_nothrow_convertible``\ should be ``__cpp_lib_is_nothrow_convertible``\ ","Prague","" +"`3358 `__","|sect|\ [span.cons] is mistaken that ``to_address``\ can throw","Prague","" +"`3359 `__","````\ leap second support should allow for negative leap seconds","Prague","" +"`3360 `__","``three_way_comparable_with``\ is inconsistent with similar concepts","Prague","" +"`3362 `__","Strike ``stop_source``\ 's ``operator!=``\ ","Prague","" +"`3363 `__","``drop_while_view``\ should opt-out of ``sized_range``\ ","Prague","" +"`3364 `__","Initialize data members of ranges and their iterators","Prague","" +"`3367 `__","Integer-class conversions should not throw","Prague","" +"`3369 `__","``span``\ 's deduction-guide for built-in arrays doesn't work","Prague","" +"`3371 `__","``visit_format_arg``\ and ``make_format_args``\ are not hidden friends","Prague","" +"`3372 `__","``vformat_to``\ should not try to deduce ``Out``\ twice","Prague","" +"`3373 `__","``{to,from}_chars_result``\ and ``format_to_n_result``\ need the ""we really mean what we say"" wording","Prague","" +"`3374 `__","P0653 + P1006 should have made the other ``std::to_address``\ overload ``constexpr``\ ","Prague","" +"`3375 `__","``decay``\ in ``viewable_range``\ should be ``remove_cvref``\ ","Prague","" +"`3377 `__","``elements_view::iterator``\ befriends a specialization of itself","Prague","" +"`3379 `__","""``safe``\ "" in several library names is misleading","Prague","" +"`3380 `__","``common_type``\ and comparison categories","Prague","" +"`3381 `__","``begin``\ and ``data``\ must agree for ``contiguous_range``\ ","Prague","" +"`3382 `__","NTTP for ``pair``\ and ``array``\ ","Prague","" +"`3383 `__","|sect|\ [time.zone.leap.nonmembers] ``sys_seconds``\ should be replaced with ``seconds``\ ","Prague","" +"`3384 `__","``transform_view::*sentinel*``\ has an incorrect ``operator-``\ ","Prague","" +"`3385 `__","``common_iterator``\ is not sufficiently constrained for non-copyable iterators","Prague","" +"`3387 `__","|sect|\ [range.reverse.view] ``reverse_view``\ unintentionally requires ``range``\ ","Prague","" +"`3388 `__","``view``\ iterator types have ill-formed ``<=>``\ operators","Prague","" +"`3389 `__","A move-only iterator still does not have a ``counted_iterator``\ ","Prague","" +"`3390 `__","``make_move_iterator()``\ cannot be used to construct a ``move_iterator``\ for a move-only iterator","Prague","" +"`3393 `__","Missing/incorrect feature test macro for coroutines","Prague","" +"`3395 `__","Definition for three-way comparison needs to be updated (US 152)","Prague","" +"`3396 `__","Clarify point of reference for ``source_location::current()``\ (DE 169)","Prague","" +"`3397 `__","``ranges::basic_istream_view::iterator``\ should not provide ``iterator_category``\ ","Prague","" +"`3398 `__","``tuple_element_t``\ is also wrong for ``const subrange``\ ","Prague","" diff --git a/libcxx/docs/Cxx2aStatusPaperStatus.csv b/libcxx/docs/Cxx2aStatusPaperStatus.csv new file mode 100644 index 0000000000000..cf476c87a1306 --- /dev/null +++ b/libcxx/docs/Cxx2aStatusPaperStatus.csv @@ -0,0 +1,195 @@ +"Paper #","Group","Paper Name","Meeting","Status","First released version" +"`P0463R1 `__","LWG","Endian just Endian","Toronto","|Complete|","7.0" +"`P0674R1 `__","LWG","Extending make_shared to Support Arrays","Toronto","","" +"","","","","","" +"`P0020R6 `__","LWG","Floating Point Atomic","Albuquerque","","" +"`P0053R7 `__","LWG","C++ Synchronized Buffered Ostream","Albuquerque","","" +"`P0202R3 `__","LWG","Add constexpr modifiers to functions in and Headers","Albuquerque","|In Progress| [#note-P0202]_","7.0" +"`P0415R1 `__","LWG","Constexpr for ``std::complex``\ ","Albuquerque","|In Progress|","7.0" +"`P0439R0 `__","LWG","Make ``std::memory_order``\ a scoped enumeration","Albuquerque","|Complete|","" +"`P0457R2 `__","LWG","String Prefix and Suffix Checking","Albuquerque","|Complete|","6.0" +"`P0550R2 `__","LWG","Transformation Trait ``remove_cvref``\ ","Albuquerque","|Complete|","6.0" +"`P0600R1 `__","LWG","nodiscard in the Library","Albuquerque","|In Progress| [#note-P0600]_","7.0" +"`P0616R0 `__","LWG","de-pessimize legacy algorithms with std::move","Albuquerque","","" +"`P0653R2 `__","LWG","Utility to convert a pointer to a raw pointer","Albuquerque","|Complete|","6.0" +"`P0718R2 `__","LWG","Atomic shared_ptr","Albuquerque","","" +"`P0767R1 `__","CWG","Deprecate POD","Albuquerque","|Complete|","7.0" +"`P0768R1 `__","CWG","Library Support for the Spaceship (Comparison) Operator","Albuquerque","|Complete|","" +"`P0777R1 `__","LWG","Treating Unnecessary ``decay``\ ","Albuquerque","|Complete|","7.0" +"`P0122R7 `__","LWG","","Jacksonville","|Complete|","7.0" +"`P0355R7 `__","LWG","Extending chrono to Calendars and Time Zones","Jacksonville","|In Progress|","" +"`P0551R3 `__","LWG","Thou Shalt Not Specialize ``std``\ Function Templates!","Jacksonville","|Complete|","11.0" +"`P0753R2 `__","LWG","Manipulators for C++ Synchronized Buffered Ostream","Jacksonville","","" +"`P0754R2 `__","LWG","","Jacksonville","|Complete|","7.0" +"`P0809R0 `__","LWG","Comparing Unordered Containers","Jacksonville","","" +"`P0858R0 `__","LWG","Constexpr iterator requirements","Jacksonville","","" +"`P0905R1 `__","CWG","Symmetry for spaceship","Jacksonville","","" +"`P0966R1 `__","LWG","``string::reserve``\ Should Not Shrink","Jacksonville","|Complete| [#note-P0966]_","12.0" +"","","","","","" +"`P0019R8 `__","LWG","Atomic Ref","Rapperswil","","" +"`P0458R2 `__","LWG","Checking for Existence of an Element in Associative Containers","Rapperswil","|Complete|","" +"`P0475R1 `__","LWG","LWG 2511: guaranteed copy elision for piecewise construction","Rapperswil","","" +"`P0476R2 `__","LWG","Bit-casting object representations","Rapperswil","","" +"`P0528R3 `__","CWG","The Curious Case of Padding Bits, Featuring Atomic Compare-and-Exchange","Rapperswil","","" +"`P0542R5 `__","CWG","Support for contract based programming in C++","Rapperswil","","" +"`P0556R3 `__","LWG","Integral power-of-2 operations","Rapperswil","|Complete|","9.0" +"`P0619R4 `__","LWG","Reviewing Deprecated Facilities of C++17 for C++20","Rapperswil","|Partial| [#note-P0619]_","" +"`P0646R1 `__","LWG","Improving the Return Value of Erase-Like Algorithms","Rapperswil","|Complete|","10.0" +"`P0722R3 `__","CWG","Efficient sized delete for variable sized classes","Rapperswil","|Complete|","9.0" +"`P0758R1 `__","LWG","Implicit conversion traits and utility functions","Rapperswil","|Complete|","" +"`P0759R1 `__","LWG","fpos Requirements","Rapperswil","|Complete|","11.0" +"`P0769R2 `__","LWG","Add shift to ","Rapperswil","","" +"`P0788R3 `__","LWG","Standard Library Specification in a Concepts and Contracts World","Rapperswil","","" +"`P0879R0 `__","LWG","Constexpr for swap and swap related functions Also resolves LWG issue 2800.","Rapperswil","","" +"`P0887R1 `__","LWG","The identity metafunction","Rapperswil","|Complete|","8.0" +"`P0892R2 `__","CWG","explicit(bool)","Rapperswil","","" +"`P0898R3 `__","LWG","Standard Library Concepts","Rapperswil","","" +"`P0935R0 `__","LWG","Eradicating unnecessarily explicit default constructors from the standard library","Rapperswil","","" +"`P0941R2 `__","CWG","Integrating feature-test macros into the C++ WD","Rapperswil","|In Progress|","" +"`P1023R0 `__","LWG","constexpr comparison operators for std::array","Rapperswil","|Complete|","8.0" +"`P1025R1 `__","CWG","Update The Reference To The Unicode Standard","Rapperswil","","" +"`P1120R0 `__","CWG","Consistency improvements for <=> and other comparison operators","Rapperswil","","" +"","","","","","" +"`P0318R1 `__","LWG","unwrap_ref_decay and unwrap_reference","San Diego","|Complete|","8.0" +"`P0356R5 `__","LWG","Simplified partial function application","San Diego","* *","" +"`P0357R3 `__","LWG","reference_wrapper for incomplete types","San Diego","|Complete|","8.0" +"`P0482R6 `__","CWG","char8_t: A type for UTF-8 characters and strings","San Diego","|In Progress|","" +"`P0487R1 `__","LWG","Fixing ``operator>>(basic_istream&, CharT*)``\ (LWG 2499)","San Diego","|Complete|","8.0" +"`P0591R4 `__","LWG","Utility functions to implement uses-allocator construction","San Diego","* *","" +"`P0595R2 `__","CWG","P0595R2 std::is_constant_evaluated()","San Diego","|Complete|","9.0" +"`P0602R4 `__","LWG","variant and optional should propagate copy/move triviality","San Diego","|Complete|","8.0" +"`P0608R3 `__","LWG","A sane variant converting constructor","San Diego","|Complete|","9.0" +"`P0655R1 `__","LWG","visit: Explicit Return Type for visit","San Diego","* *","" +"`P0771R1 `__","LWG","std::function move constructor should be noexcept","San Diego","|Complete|","6.0" +"`P0896R4 `__","LWG","The One Ranges Proposal","San Diego","* *","" +"`P0899R1 `__","LWG","P0899R1 - LWG 3016 is not a defect","San Diego","|Nothing To Do|","" +"`P0919R3 `__","LWG","Heterogeneous lookup for unordered containers","San Diego","|Complete|","12.0" +"`P0972R0 `__","LWG"," ``zero()``\ , ``min()``\ , and ``max()``\ should be noexcept","San Diego","|Complete|","8.0" +"`P1006R1 `__","LWG","Constexpr in std::pointer_traits","San Diego","|Complete|","8.0" +"`P1007R3 `__","LWG","``std::assume_aligned``\ ","San Diego","* *","" +"`P1020R1 `__","LWG","Smart pointer creation with default initialization","San Diego","* *","" +"`P1032R1 `__","LWG","Misc constexpr bits","San Diego","* *","" +"`P1085R2 `__","LWG","Should Span be Regular?","San Diego","|Complete|","8.0" +"`P1123R0 `__","LWG","Editorial Guidance for merging P0019r8 and P0528r3","San Diego","* *","" +"`P1148R0 `__","LWG","Cleaning up Clause 20","San Diego","* *","" +"`P1165R1 `__","LWG","Make stateful allocator propagation more consistent for ``operator+(basic_string)``\ ","San Diego","* *","" +"`P1209R0 `__","LWG","Adopt Consistent Container Erasure from Library Fundamentals 2 for C++20","San Diego","|Complete|","8.0" +"`P1210R0 `__","LWG","Completing the Rebase of Library Fundamentals, Version 3, Working Draft","San Diego","* *","" +"`P1236R1 `__","CWG","Alternative Wording for P0907R4 Signed Integers are Two's Complement","San Diego","* *","" +"`P1248R1 `__","LWG","Remove CommonReference requirement from StrictWeakOrdering (a.k.a Fixing Relations)","San Diego","* *","" +"`P1285R0 `__","LWG","Improving Completeness Requirements for Type Traits","San Diego","* *","" +"`P1353R0 `__","CWG","Missing feature test macros","San Diego","* *","" +"","","","","","" +"`P0339R6 `__","LWG","polymorphic_allocator<> as a vocabulary type","Kona","","" +"`P0340R3 `__","LWG","Making std::underlying_type SFINAE-friendly","Kona","|Complete|","9.0" +"`P0738R2 `__","LWG","I Stream, You Stream, We All Stream for istream_iterator","Kona","","" +"`P0811R3 `__","LWG","Well-behaved interpolation for numbers and pointers","Kona","|Complete|","9.0" +"`P0920R2 `__","LWG","Precalculated hash values in lookup","Kona","Reverted by `P1661 `__","" +"`P1001R2 `__","LWG","Target Vectorization Policies from Parallelism V2 TS to C++20","Kona","","" +"`P1024R3 `__","LWG","Usability Enhancements for std::span","Kona","|Complete|","9.0" +"`P1164R1 `__","LWG","Make create_directory() Intuitive","Kona","","" +"`P1227R2 `__","LWG","Signed ssize() functions, unsigned size() functions","Kona","|Complete|","9.0" +"`P1252R2 `__","LWG","Ranges Design Cleanup","Kona","","" +"`P1286R2 `__","CWG","Contra CWG DR1778","Kona","","" +"`P1357R1 `__","LWG","Traits for [Un]bounded Arrays","Kona","|Complete|","9.0" +"`P1458R1 `__","LWG","Mandating the Standard Library: Clause 16 - Language support library","Kona","|Complete|","9.0" +"`P1459R1 `__","LWG","Mandating the Standard Library: Clause 18 - Diagnostics library","Kona","|Complete|","9.0" +"`P1462R1 `__","LWG","Mandating the Standard Library: Clause 20 - Strings library","Kona","|Complete|","9.0" +"`P1463R1 `__","LWG","Mandating the Standard Library: Clause 21 - Containers library","Kona","","" +"`P1464R1 `__","LWG","Mandating the Standard Library: Clause 22 - Iterators library","Kona","|Complete|","9.0" +"","","","","","" +"`P0325 `__","LWG","to_array from LFTS with updates","Cologne","|Complete|","10.0" +"`P0408 `__","LWG","Efficient Access to basic_stringbuf's Buffer","Cologne","","" +"`P0466 `__","LWG","Layout-compatibility and Pointer-interconvertibility Traits","Cologne","","" +"`P0553 `__","LWG","Bit operations","Cologne","|Complete|","9.0" +"`P0631 `__","LWG","Math Constants","Cologne","|Complete|","11.0" +"`P0645 `__","LWG","Text Formatting","Cologne","","" +"`P0660 `__","LWG","Stop Token and Joining Thread, Rev 10","Cologne","","" +"`P0784 `__","CWG","More constexpr containers","Cologne","|Complete|","12.0" +"`P0980 `__","LWG","Making std::string constexpr","Cologne","","" +"`P1004 `__","LWG","Making std::vector constexpr","Cologne","","" +"`P1035 `__","LWG","Input Range Adaptors","Cologne","","" +"`P1065 `__","LWG","Constexpr INVOKE","Cologne","","" +"`P1135 `__","LWG","The C++20 Synchronization Library","Cologne","|Complete|","" +"`P1207 `__","LWG","Movability of Single-pass Iterators","Cologne","","" +"`P1208 `__","LWG","Adopt source_location for C++20","Cologne","","" +"`P1355 `__","LWG","Exposing a narrow contract for ceil2","Cologne","|Complete|","9.0" +"`P1361 `__","LWG","Integration of chrono with text formatting","Cologne","","" +"`P1423 `__","LWG","char8_t backward compatibility remediation","Cologne","","" +"`P1424 `__","LWG","'constexpr' feature macro concerns","Cologne","","" +"`P1466 `__","LWG","Miscellaneous minor fixes for chrono","Cologne","","" +"`P1474 `__","LWG","Helpful pointers for ContiguousIterator","Cologne","","" +"`P1502 `__","LWG","Standard library header units for C++20","Cologne","","" +"`P1522 `__","LWG","Iterator Difference Type and Integer Overflow","Cologne","","" +"`P1523 `__","LWG","Views and Size Types","Cologne","","" +"`P1612 `__","LWG","Relocate Endian's Specification","Cologne","|Complete|","10.0" +"`P1614 `__","LWG","The Mothership has Landed","Cologne","|In Progress|","" +"`P1638 `__","LWG","basic_istream_view::iterator should not be copyable","Cologne","","" +"`P1643 `__","LWG","Add wait/notify to atomic_ref","Cologne","","" +"`P1644 `__","LWG","Add wait/notify to atomic","Cologne","","" +"`P1650 `__","LWG","Output std::chrono::days with 'd' suffix","Cologne","","" +"`P1651 `__","LWG","bind_front should not unwrap reference_wrapper","Cologne","","" +"`P1652 `__","LWG","Printf corner cases in std::format","Cologne","","" +"`P1661 `__","LWG","Remove dedicated precalculated hash lookup interface","Cologne","|Nothing To Do|","" +"`P1754 `__","LWG","Rename concepts to standard_case for C++20, while we still can","Cologne","","" +"","","","","","" +"`P0883 `__","LWG","Fixing Atomic Initialization","Belfast","* *","" +"`P1391 `__","LWG","Range constructor for std::string_view","Belfast","* *","" +"`P1394 `__","LWG","Range constructor for std::span","Belfast","* *","" +"`P1456 `__","LWG","Move-only views","Belfast","* *","" +"`P1622 `__","LWG","Mandating the Standard Library: Clause 32 - Thread support library","Belfast","* *","" +"`P1645 `__","LWG","constexpr for numeric algorithms","Belfast","* *","" +"`P1664 `__","LWG","reconstructible_range - a concept for putting ranges back together","Belfast","* *","" +"`P1686 `__","LWG","Mandating the Standard Library: Clause 27 - Time library","Belfast","* *","" +"`P1690 `__","LWG","Refinement Proposal for P0919 Heterogeneous lookup for unordered containers","Belfast","|Complete|","12.0" +"`P1716 `__","LWG","ranges compare algorithm are over-constrained","Belfast","* *","" +"`P1718 `__","LWG","Mandating the Standard Library: Clause 25 - Algorithms library","Belfast","* *","" +"`P1719 `__","LWG","Mandating the Standard Library: Clause 26 - Numerics library","Belfast","* *","" +"`P1720 `__","LWG","Mandating the Standard Library: Clause 28 - Localization library","Belfast","* *","" +"`P1721 `__","LWG","Mandating the Standard Library: Clause 29 - Input/Output library","Belfast","* *","" +"`P1722 `__","LWG","Mandating the Standard Library: Clause 30 - Regular Expression library","Belfast","* *","" +"`P1723 `__","LWG","Mandating the Standard Library: Clause 31 - Atomics library","Belfast","* *","" +"`P1855 `__","LWG","Make ````\ freestanding","Belfast","* *","" +"`P1862 `__","LWG","Ranges adaptors for non-copyable iterators","Belfast","* *","" +"`P1865 `__","LWG","Add max() to latch and barrier","Belfast","* *","" +"`P1869 `__","LWG","Rename 'condition_variable_any' interruptible wait methods","Belfast","* *","" +"`P1870 `__","LWG","forwarding-range is too subtle","Belfast","* *","" +"`P1871 `__","LWG","Should concepts be enabled or disabled?","Belfast","* *","" +"`P1872 `__","LWG","span should have size_type, not index_type","Belfast","|Complete|","10.0" +"`P1878 `__","LWG","Constraining Readable Types","Belfast","* *","" +"`P1892 `__","LWG","Extended locale-specific presentation specifiers for std::format","Belfast","* *","" +"`P1902 `__","LWG","Missing feature-test macros 2018-2019","Belfast","* *","" +"`P1959 `__","LWG","Remove std::weak_equality and std::strong_equality","Belfast","* *","" +"`P1960 `__","LWG","NB Comment Changes Reviewed by SG1","Belfast","* *","" +"`P1961 `__","LWG","Harmonizing the definitions of total order for pointers","Belfast","* *","" +"`P1965 `__","LWG","Blanket Wording for Specifying ""Hidden Friends""","Belfast","* *","" +"","","","","","" +"`P0586 `__","LWG","Safe integral comparisons","Prague","* *","" +"`P0593 `__","CWG","Implicit creation of objects for low-level object manipulation","Prague","* *","" +"`P1115 `__","LWG","Improving the Return Value of Erase-Like Algorithms II: Free erase/erase if","Prague","|Complete|","11.0" +"`P1243 `__","LWG","Rangify New Algorithms","Prague","* *","" +"`P1460 `__","LWG","Mandating the Standard Library: Clause 20 - Utilities library","Prague","* *","" +"`P1739 `__","LWG","Avoid template bloat for safe_ranges in combination with ""subrange-y"" view adaptors","Prague","* *","" +"`P1831 `__","LWG","Deprecating volatile: library","Prague","* *","" +"`P1868 `__","LWG","width: clarifying units of width and precision in std::format","Prague","* *","" +"`P1908 `__","CWG","Reserving Attribute Namespaces for Future Use","Prague","* *","" +"`P1937 `__","CWG","Fixing inconsistencies between constexpr and consteval functions","Prague","* *","" +"`P1956 `__","LWG","On the names of low-level bit manipulation functions","Prague","|Complete|","12.0" +"`P1957 `__","CWG","Converting from ``T*``\ to bool should be considered narrowing (re: US 212)","Prague","* *","" +"`P1963 `__","LWG","Fixing US 313","Prague","* *","" +"`P1964 `__","LWG","Wording for boolean-testable","Prague","* *","" +"`P1970 `__","LWG","Consistency for size() functions: Add ranges::ssize","Prague","* *","" +"`P1973 `__","LWG","Rename ""_default_init"" Functions, Rev1","Prague","* *","" +"`P1976 `__","LWG","Fixed-size span construction from dynamic range","Prague","|Complete|","11.0" +"`P1981 `__","LWG","Rename leap to leap_second","Prague","* *","" +"`P1982 `__","LWG","Rename link to time_zone_link","Prague","* *","" +"`P1983 `__","LWG","Wording for GB301, US296, US292, US291, and US283","Prague","* *","" +"`P1994 `__","LWG","elements_view needs its own sentinel","Prague","* *","" +"`P2002 `__","CWG","Defaulted comparison specification cleanups","Prague","* *","" +"`P2045 `__","LWG","Missing Mandates for the standard library","Prague","* *","" +"`P2085 `__","CWG","Consistent defaulted comparisons","Prague","* *","" +"`P2091 `__","LWG","Issues with range access CPOs","Prague","* *","" +"`P2101 `__","LWG","'Models' subsumes 'satisfies' (Wording for US298 and US300)","Prague","* *","" +"`P2102 `__","LWG","Make 'implicit expression variations' more explicit (Wording for US185)","Prague","* *","" +"`P2106 `__","LWG","Alternative wording for GB315 and GB316","Prague","* *","" +"`P2116 `__","LWG","Remove tuple-like protocol support from fixed-extent span","Prague","|Complete|","11.0" diff --git a/libcxx/docs/FeatureTestMacroTable.rst b/libcxx/docs/FeatureTestMacroTable.rst index 8d7bfd45fc56d..637a4849e471f 100644 --- a/libcxx/docs/FeatureTestMacroTable.rst +++ b/libcxx/docs/FeatureTestMacroTable.rst @@ -208,6 +208,8 @@ Status ------------------------------------------------- ----------------- ``__cpp_lib_generic_unordered_lookup`` ``201811L`` ------------------------------------------------- ----------------- + ``__cpp_lib_int_pow2`` ``202002L`` + ------------------------------------------------- ----------------- ``__cpp_lib_interpolate`` ``201902L`` ------------------------------------------------- ----------------- ``__cpp_lib_is_constant_evaluated`` ``201811L`` diff --git a/libcxx/docs/Helpers/Styles.rst b/libcxx/docs/Helpers/Styles.rst new file mode 100644 index 0000000000000..9bba3bf69db29 --- /dev/null +++ b/libcxx/docs/Helpers/Styles.rst @@ -0,0 +1,31 @@ +.. raw:: html + + + +.. role:: nothingtodo +.. role:: inprogress +.. role:: partial +.. role:: complete + + +.. |Nothing To Do| replace:: :nothingtodo:`Nothing To Do` +.. |In Progress| replace:: :inprogress:`In Progress` +.. |Partial| replace:: :partial:`Partial` +.. |Complete| replace:: :complete:`Complete` + +.. |sect| unicode:: U+00A7 +.. |hellip| unicode:: U+2026 diff --git a/libcxx/docs/ReleaseNotes.rst b/libcxx/docs/ReleaseNotes.rst index 6079b6fa47be4..719115fded672 100644 --- a/libcxx/docs/ReleaseNotes.rst +++ b/libcxx/docs/ReleaseNotes.rst @@ -49,3 +49,10 @@ API Changes in both libc++ and libc++abi, which is technically an ODR violation. Also note that we couldn't decide to put the operators in libc++ only, because they are needed from libc++abi (which would create a circular dependency). +- During the C++20 standardization process some new low-level bit functions + have been renamed. Libc++ has renamed these functions to match the C++20 + Standard. + - ``ispow2`` has been renamed to ``has_single_bit`` + - ``ceil2`` has been renamed to ``bit_ceil`` + - ``floor2`` has been renamed to ``bit_floor`` + - ``log2p1`` has been renamed to ``bit_width`` diff --git a/libcxx/docs/conf.py b/libcxx/docs/conf.py index 797a4d80f512c..95cd98bc471cf 100644 --- a/libcxx/docs/conf.py +++ b/libcxx/docs/conf.py @@ -40,7 +40,7 @@ # General information about the project. project = u'libc++' -copyright = u'2011-2018, LLVM Project' +copyright = u'2011-2020, LLVM Project' # The version info for the project you're documenting, acts as replacement for # |version| and |release|, also used in various other places throughout the @@ -63,7 +63,7 @@ # List of patterns, relative to source directory, that match files and # directories to ignore when looking for source files. -exclude_patterns = ['_build'] +exclude_patterns = ['_build', 'Helpers'] # The reST default role (used for this markup: `text`) to use for all documents. #default_role = None diff --git a/libcxx/docs/index.rst b/libcxx/docs/index.rst index 27abe5724d10a..926cd102d71ff 100644 --- a/libcxx/docs/index.rst +++ b/libcxx/docs/index.rst @@ -38,6 +38,9 @@ Getting Started with libc++ UsingLibcxx BuildingLibcxx TestingLibcxx + Cxx1yStatus + Cxx1zStatus + Cxx2aStatus .. toctree:: @@ -132,8 +135,9 @@ C++ Dialect Support --------------------- * C++11 - Complete -* `C++14 - Complete `__ -* `C++17 - In Progress `__ +* :ref:`C++14 - Complete ` +* :ref:`C++17 - In Progress ` +* :ref:`C++20 - In Progress ` * `Post C++14 Technical Specifications - In Progress `__ * :ref:`C++ Feature Test Macro Status ` diff --git a/libcxx/include/__config b/libcxx/include/__config index 413931a7a897f..de40ffc3162eb 100644 --- a/libcxx/include/__config +++ b/libcxx/include/__config @@ -991,6 +991,12 @@ typedef unsigned int char32_t; # define _LIBCPP_DEPRECATED_IN_CXX17 #endif +#if _LIBCPP_STD_VER > 17 +# define _LIBCPP_DEPRECATED_IN_CXX20 _LIBCPP_DEPRECATED +#else +# define _LIBCPP_DEPRECATED_IN_CXX20 +#endif + // Macros to enter and leave a state where deprecation warnings are suppressed. #if !defined(_LIBCPP_SUPPRESS_DEPRECATED_PUSH) && \ (defined(_LIBCPP_COMPILER_CLANG) || defined(_LIBCPP_COMPILER_GCC)) @@ -1029,14 +1035,6 @@ typedef unsigned int char32_t; # define _LIBCPP_CONSTEXPR_AFTER_CXX17 #endif -#if _LIBCPP_STD_VER > 17 && \ - !defined(_LIBCPP_HAS_NO_CXX14_CONSTEXPR) && \ - !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) -# define _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED constexpr -#else -# define _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED -#endif - // The _LIBCPP_NODISCARD_ATTRIBUTE should only be used to define other // NODISCARD macros to the correct attribute. #if __has_cpp_attribute(nodiscard) || defined(_LIBCPP_COMPILER_MSVC) @@ -1421,6 +1419,12 @@ _LIBCPP_FUNC_VIS extern "C" void __sanitizer_annotate_contiguous_container( #define _LIBCPP_HAS_NO_FGETPOS_FSETPOS #endif +#if __has_attribute(init_priority) +# define _LIBCPP_INIT_PRIORITY_MAX __attribute__((init_priority(101))) +#else +# define _LIBCPP_INIT_PRIORITY_MAX +#endif + #endif // __cplusplus #endif // _LIBCPP_CONFIG diff --git a/libcxx/include/__hash_table b/libcxx/include/__hash_table index 4e615d4fac018..a004d59a4a08d 100644 --- a/libcxx/include/__hash_table +++ b/libcxx/include/__hash_table @@ -2728,9 +2728,9 @@ __hash_table<_Tp, _Hash, _Equal, _Alloc>::swap(__hash_table& __u) __u.__bucket_list_.reset(__npp); } _VSTD::swap(__bucket_list_.get_deleter().size(), __u.__bucket_list_.get_deleter().size()); - __swap_allocator(__bucket_list_.get_deleter().__alloc(), + _VSTD::__swap_allocator(__bucket_list_.get_deleter().__alloc(), __u.__bucket_list_.get_deleter().__alloc()); - __swap_allocator(__node_alloc(), __u.__node_alloc()); + _VSTD::__swap_allocator(__node_alloc(), __u.__node_alloc()); _VSTD::swap(__p1_.first().__next_, __u.__p1_.first().__next_); __p2_.swap(__u.__p2_); __p3_.swap(__u.__p3_); diff --git a/libcxx/include/__locale b/libcxx/include/__locale index fd09206b6c5d5..23ad424e3c0fc 100644 --- a/libcxx/include/__locale +++ b/libcxx/include/__locale @@ -628,7 +628,7 @@ class _LIBCPP_TYPE_VIS ctype public: typedef char char_type; - explicit ctype(const mask* __tab = 0, bool __del = false, size_t __refs = 0); + explicit ctype(const mask* __tab = nullptr, bool __del = false, size_t __refs = 0); _LIBCPP_INLINE_VISIBILITY bool is(mask __m, char_type __c) const diff --git a/libcxx/include/__split_buffer b/libcxx/include/__split_buffer index d2128049efa04..b1fbddcc6093a 100644 --- a/libcxx/include/__split_buffer +++ b/libcxx/include/__split_buffer @@ -279,7 +279,7 @@ void __split_buffer<_Tp, _Allocator>::__destruct_at_begin(pointer __new_begin, false_type) { while (__begin_ != __new_begin) - __alloc_traits::destroy(__alloc(), __to_address(__begin_++)); + __alloc_traits::destroy(__alloc(), _VSTD::__to_address(__begin_++)); } template @@ -296,7 +296,7 @@ void __split_buffer<_Tp, _Allocator>::__destruct_at_end(pointer __new_last, false_type) _NOEXCEPT { while (__new_last != __end_) - __alloc_traits::destroy(__alloc(), __to_address(--__end_)); + __alloc_traits::destroy(__alloc(), _VSTD::__to_address(--__end_)); } template @@ -416,7 +416,7 @@ __split_buffer<_Tp, _Allocator>::swap(__split_buffer& __x) _VSTD::swap(__begin_, __x.__begin_); _VSTD::swap(__end_, __x.__end_); _VSTD::swap(__end_cap(), __x.__end_cap()); - __swap_allocator(__alloc(), __x.__alloc()); + _VSTD::__swap_allocator(__alloc(), __x.__alloc()); } template diff --git a/libcxx/include/__sso_allocator b/libcxx/include/__sso_allocator index 117b728f1499a..c50ae24c92125 100644 --- a/libcxx/include/__sso_allocator +++ b/libcxx/include/__sso_allocator @@ -48,7 +48,7 @@ public: private: __sso_allocator& operator=(const __sso_allocator&); public: - _LIBCPP_INLINE_VISIBILITY pointer allocate(size_type __n, typename __sso_allocator::const_pointer = 0) + _LIBCPP_INLINE_VISIBILITY pointer allocate(size_type __n, typename __sso_allocator::const_pointer = nullptr) { if (!__allocated_ && __n <= _Np) { diff --git a/libcxx/include/__string b/libcxx/include/__string index 9060bf98ad89f..08be8f1a7641e 100644 --- a/libcxx/include/__string +++ b/libcxx/include/__string @@ -268,7 +268,7 @@ char_traits<_CharT>::find(const char_type* __s, size_t __n, const char_type& __a return __s; ++__s; } - return 0; + return nullptr; } template @@ -318,7 +318,7 @@ char_traits<_CharT>::assign(char_type* __s, size_t __n, char_type __a) // constexpr versions of move/copy/assign. template -static inline _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED +static inline _LIBCPP_CONSTEXPR_AFTER_CXX17 _CharT* __move_constexpr(_CharT* __s1, const _CharT* __s2, size_t __n) _NOEXCEPT { if (__n == 0) return __s1; @@ -331,7 +331,7 @@ _CharT* __move_constexpr(_CharT* __s1, const _CharT* __s2, size_t __n) _NOEXCEPT } template -static inline _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED +static inline _LIBCPP_CONSTEXPR_AFTER_CXX17 _CharT* __copy_constexpr(_CharT* __s1, const _CharT* __s2, size_t __n) _NOEXCEPT { _VSTD::copy_n(__s2, __n, __s1); @@ -339,7 +339,7 @@ _CharT* __copy_constexpr(_CharT* __s1, const _CharT* __s2, size_t __n) _NOEXCEPT } template -static inline _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED +static inline _LIBCPP_CONSTEXPR_AFTER_CXX17 _CharT* __assign_constexpr(_CharT* __s, size_t __n, _CharT __a) _NOEXCEPT { _VSTD::fill_n(__s, __n, __a); @@ -370,14 +370,14 @@ struct _LIBCPP_TEMPLATE_VIS char_traits length(const char_type* __s) _NOEXCEPT {return __builtin_strlen(__s);} static _LIBCPP_CONSTEXPR_AFTER_CXX14 const char_type* find(const char_type* __s, size_t __n, const char_type& __a) _NOEXCEPT; - static inline _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED + static inline _LIBCPP_CONSTEXPR_AFTER_CXX17 char_type* move(char_type* __s1, const char_type* __s2, size_t __n) _NOEXCEPT { return __libcpp_is_constant_evaluated() ? __move_constexpr(__s1, __s2, __n) : __n == 0 ? __s1 : (char_type*)memmove(__s1, __s2, __n); } - static inline _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED + static inline _LIBCPP_CONSTEXPR_AFTER_CXX17 char_type* copy(char_type* __s1, const char_type* __s2, size_t __n) _NOEXCEPT { _LIBCPP_ASSERT(__s2 < __s1 || __s2 >= __s1+__n, "char_traits::copy overlapped range"); @@ -385,7 +385,7 @@ struct _LIBCPP_TEMPLATE_VIS char_traits ? __copy_constexpr(__s1, __s2, __n) : __n == 0 ? __s1 : (char_type*)memcpy(__s1, __s2, __n); } - static inline _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED + static inline _LIBCPP_CONSTEXPR_AFTER_CXX17 char_type* assign(char_type* __s, size_t __n, char_type __a) _NOEXCEPT { return __libcpp_is_constant_evaluated() @@ -473,14 +473,14 @@ struct _LIBCPP_TEMPLATE_VIS char_traits size_t length(const char_type* __s) _NOEXCEPT; static _LIBCPP_CONSTEXPR_AFTER_CXX14 const char_type* find(const char_type* __s, size_t __n, const char_type& __a) _NOEXCEPT; - static inline _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED + static inline _LIBCPP_CONSTEXPR_AFTER_CXX17 char_type* move(char_type* __s1, const char_type* __s2, size_t __n) _NOEXCEPT { return __libcpp_is_constant_evaluated() ? __move_constexpr(__s1, __s2, __n) : __n == 0 ? __s1 : wmemmove(__s1, __s2, __n); } - static inline _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED + static inline _LIBCPP_CONSTEXPR_AFTER_CXX17 char_type* copy(char_type* __s1, const char_type* __s2, size_t __n) _NOEXCEPT { _LIBCPP_ASSERT(__s2 < __s1 || __s2 >= __s1+__n, "char_traits::copy overlapped range"); @@ -488,7 +488,7 @@ struct _LIBCPP_TEMPLATE_VIS char_traits ? __copy_constexpr(__s1, __s2, __n) : __n == 0 ? __s1 : wmemcpy(__s1, __s2, __n); } - static inline _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED + static inline _LIBCPP_CONSTEXPR_AFTER_CXX17 char_type* assign(char_type* __s, size_t __n, char_type __a) _NOEXCEPT { return __libcpp_is_constant_evaluated() @@ -606,7 +606,7 @@ struct _LIBCPP_TEMPLATE_VIS char_traits _LIBCPP_INLINE_VISIBILITY static constexpr const char_type* find(const char_type* __s, size_t __n, const char_type& __a) _NOEXCEPT; - static _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED + static _LIBCPP_CONSTEXPR_AFTER_CXX17 char_type* move(char_type* __s1, const char_type* __s2, size_t __n) _NOEXCEPT { return __libcpp_is_constant_evaluated() @@ -614,7 +614,7 @@ struct _LIBCPP_TEMPLATE_VIS char_traits : __n == 0 ? __s1 : (char_type*)memmove(__s1, __s2, __n); } - static _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED + static _LIBCPP_CONSTEXPR_AFTER_CXX17 char_type* copy(char_type* __s1, const char_type* __s2, size_t __n) _NOEXCEPT { _LIBCPP_ASSERT(__s2 < __s1 || __s2 >= __s1+__n, "char_traits::copy overlapped range"); @@ -623,7 +623,7 @@ struct _LIBCPP_TEMPLATE_VIS char_traits : __n == 0 ? __s1 : (char_type*)memcpy(__s1, __s2, __n); } - static _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED + static _LIBCPP_CONSTEXPR_AFTER_CXX17 char_type* assign(char_type* __s, size_t __n, char_type __a) _NOEXCEPT { return __libcpp_is_constant_evaluated() @@ -683,7 +683,7 @@ char_traits::find(const char_type* __s, size_t __n, const char_type& __ return __s; ++__s; } - return 0; + return nullptr; } #endif // #_LIBCPP_NO_HAS_CHAR8_T @@ -765,7 +765,7 @@ char_traits::find(const char_type* __s, size_t __n, const char_type& _ return __s; ++__s; } - return 0; + return nullptr; } inline _LIBCPP_CONSTEXPR_AFTER_CXX17 @@ -885,7 +885,7 @@ char_traits::find(const char_type* __s, size_t __n, const char_type& _ return __s; ++__s; } - return 0; + return nullptr; } inline _LIBCPP_CONSTEXPR_AFTER_CXX17 @@ -943,7 +943,7 @@ __str_find(const _CharT *__p, _SizeT __sz, if (__pos >= __sz) return __npos; const _CharT* __r = _Traits::find(__p + __pos, __sz - __pos, __c); - if (__r == 0) + if (__r == nullptr) return __npos; return static_cast<_SizeT>(__r - __p); } @@ -972,7 +972,7 @@ __search_substring(const _CharT *__first1, const _CharT *__last1, // Find __f2 the first byte matching in __first1. __first1 = _Traits::find(__first1, __len1 - __len2 + 1, __f2); - if (__first1 == 0) + if (__first1 == nullptr) return __last1; // It is faster to compare from the first byte of __first1 even if we @@ -1095,7 +1095,7 @@ __str_find_first_not_of(const _CharT *__p, _SizeT __sz, { const _CharT* __pe = __p + __sz; for (const _CharT* __ps = __p + __pos; __ps != __pe; ++__ps) - if (_Traits::find(__s, __n, *__ps) == 0) + if (_Traits::find(__s, __n, *__ps) == nullptr) return static_cast<_SizeT>(__ps - __p); } return __npos; @@ -1129,7 +1129,7 @@ __str_find_last_not_of(const _CharT *__p, _SizeT __sz, else __pos = __sz; for (const _CharT* __ps = __p + __pos; __ps != __p;) - if (_Traits::find(__s, __n, *--__ps) == 0) + if (_Traits::find(__s, __n, *--__ps) == nullptr) return static_cast<_SizeT>(__ps - __p); return __npos; } diff --git a/libcxx/include/__threading_support b/libcxx/include/__threading_support index 85bb96bdc6baf..2d0ccf5cb2449 100644 --- a/libcxx/include/__threading_support +++ b/libcxx/include/__threading_support @@ -497,13 +497,13 @@ bool __libcpp_thread_id_less(__libcpp_thread_id t1, __libcpp_thread_id t2) // Thread bool __libcpp_thread_isnull(const __libcpp_thread_t *__t) { - return *__t == 0; + return *__t == __libcpp_thread_t(); } int __libcpp_thread_create(__libcpp_thread_t *__t, void *(*__func)(void *), void *__arg) { - return pthread_create(__t, 0, __func, __arg); + return pthread_create(__t, nullptr, __func, __arg); } __libcpp_thread_id __libcpp_thread_get_current_id() @@ -518,7 +518,7 @@ __libcpp_thread_id __libcpp_thread_get_id(const __libcpp_thread_t *__t) int __libcpp_thread_join(__libcpp_thread_t *__t) { - return pthread_join(*__t, 0); + return pthread_join(*__t, nullptr); } int __libcpp_thread_detach(__libcpp_thread_t *__t) diff --git a/libcxx/include/__tree b/libcxx/include/__tree index 4e131a165f7ea..404351b4bd888 100644 --- a/libcxx/include/__tree +++ b/libcxx/include/__tree @@ -1819,7 +1819,7 @@ __tree<_Tp, _Compare, _Allocator>::swap(__tree& __t) using _VSTD::swap; swap(__begin_node_, __t.__begin_node_); swap(__pair1_.first(), __t.__pair1_.first()); - __swap_allocator(__node_alloc(), __t.__node_alloc()); + _VSTD::__swap_allocator(__node_alloc(), __t.__node_alloc()); __pair3_.swap(__t.__pair3_); if (size() == 0) __begin_node() = __end_node(); diff --git a/libcxx/include/algorithm b/libcxx/include/algorithm index 5d09b6c3c0150..f047ae1b1dee9 100644 --- a/libcxx/include/algorithm +++ b/libcxx/include/algorithm @@ -1727,7 +1727,7 @@ __copy(_Tp* __first, _Tp* __last, _Up* __result) } template -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED +inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17 _OutputIterator copy(_InputIterator __first, _InputIterator __last, _OutputIterator __result) { @@ -1780,7 +1780,7 @@ __copy_backward(_Tp* __first, _Tp* __last, _Up* __result) } template -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED +inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17 _BidirectionalIterator2 copy_backward(_BidirectionalIterator1 __first, _BidirectionalIterator1 __last, _BidirectionalIterator2 __result) @@ -1818,7 +1818,7 @@ copy_if(_InputIterator __first, _InputIterator __last, // copy_n template -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED +inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17 typename enable_if < __is_cpp17_input_iterator<_InputIterator>::value && @@ -1844,7 +1844,7 @@ copy_n(_InputIterator __first, _Size __orig_n, _OutputIterator __result) } template -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17_WITH_IS_CONSTANT_EVALUATED +inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17 typename enable_if < __is_cpp17_random_access_iterator<_InputIterator>::value, @@ -3405,7 +3405,7 @@ __stable_partition(_ForwardIterator __first, _ForwardIterator __last, _Predicate // Update __first to always point to the end of the trues value_type* __t = __p.first; ::new(__t) value_type(_VSTD::move(*__first)); - __d.__incr((value_type*)0); + __d.template __incr(); ++__t; _ForwardIterator __i = __first; while (++__i != __last) @@ -3418,7 +3418,7 @@ __stable_partition(_ForwardIterator __first, _ForwardIterator __last, _Predicate else { ::new(__t) value_type(_VSTD::move(*__i)); - __d.__incr((value_type*)0); + __d.template __incr(); ++__t; } } @@ -3535,7 +3535,7 @@ __stable_partition(_BidirectionalIterator __first, _BidirectionalIterator __last // Update __first to always point to the end of the trues value_type* __t = __p.first; ::new(__t) value_type(_VSTD::move(*__first)); - __d.__incr((value_type*)0); + __d.template __incr(); ++__t; _BidirectionalIterator __i = __first; while (++__i != __last) @@ -3548,7 +3548,7 @@ __stable_partition(_BidirectionalIterator __first, _BidirectionalIterator __last else { ::new(__t) value_type(_VSTD::move(*__i)); - __d.__incr((value_type*)0); + __d.template __incr(); ++__t; } } @@ -3923,7 +3923,7 @@ __insertion_sort_move(_BirdirectionalIterator __first1, _BirdirectionalIterator unique_ptr __h(__first2, __d); value_type* __last2 = __first2; ::new(__last2) value_type(_VSTD::move(*__first1)); - __d.__incr((value_type*)0); + __d.template __incr(); for (++__last2; ++__first1 != __last1; ++__last2) { value_type* __j2 = __last2; @@ -3931,7 +3931,7 @@ __insertion_sort_move(_BirdirectionalIterator __first1, _BirdirectionalIterator if (__comp(*__first1, *--__i2)) { ::new(__j2) value_type(_VSTD::move(*__i2)); - __d.__incr((value_type*)0); + __d.template __incr(); for (--__j2; __i2 != __first2 && __comp(*__first1, *--__i2); --__j2) *__j2 = _VSTD::move(*__i2); *__j2 = _VSTD::move(*__first1); @@ -3939,7 +3939,7 @@ __insertion_sort_move(_BirdirectionalIterator __first1, _BirdirectionalIterator else { ::new(__j2) value_type(_VSTD::move(*__first1)); - __d.__incr((value_type*)0); + __d.template __incr(); } } __h.release(); @@ -4481,14 +4481,14 @@ __buffered_inplace_merge(_BidirectionalIterator __first, _BidirectionalIterator if (__len1 <= __len2) { value_type* __p = __buff; - for (_BidirectionalIterator __i = __first; __i != __middle; __d.__incr((value_type*)0), (void) ++__i, (void) ++__p) + for (_BidirectionalIterator __i = __first; __i != __middle; __d.template __incr(), (void) ++__i, (void) ++__p) ::new(__p) value_type(_VSTD::move(*__i)); __half_inplace_merge(__buff, __p, __middle, __last, __first, __comp); } else { value_type* __p = __buff; - for (_BidirectionalIterator __i = __middle; __i != __last; __d.__incr((value_type*)0), (void) ++__i, (void) ++__p) + for (_BidirectionalIterator __i = __middle; __i != __last; __d.template __incr(), (void) ++__i, (void) ++__p) ::new(__p) value_type(_VSTD::move(*__i)); typedef reverse_iterator<_BidirectionalIterator> _RBi; typedef reverse_iterator _Rv; @@ -4628,14 +4628,14 @@ __merge_move_construct(_InputIterator1 __first1, _InputIterator1 __last1, { if (__first1 == __last1) { - for (; __first2 != __last2; ++__first2, ++__result, (void) __d.__incr((value_type*)0)) + for (; __first2 != __last2; ++__first2, ++__result, (void)__d.template __incr()) ::new (__result) value_type(_VSTD::move(*__first2)); __h.release(); return; } if (__first2 == __last2) { - for (; __first1 != __last1; ++__first1, ++__result, (void) __d.__incr((value_type*)0)) + for (; __first1 != __last1; ++__first1, ++__result, (void)__d.template __incr()) ::new (__result) value_type(_VSTD::move(*__first1)); __h.release(); return; @@ -4643,13 +4643,13 @@ __merge_move_construct(_InputIterator1 __first1, _InputIterator1 __last1, if (__comp(*__first2, *__first1)) { ::new (__result) value_type(_VSTD::move(*__first2)); - __d.__incr((value_type*)0); + __d.template __incr(); ++__first2; } else { ::new (__result) value_type(_VSTD::move(*__first1)); - __d.__incr((value_type*)0); + __d.template __incr(); ++__first1; } } @@ -4710,14 +4710,14 @@ __stable_sort_move(_RandomAccessIterator __first1, _RandomAccessIterator __last1 if (__comp(*--__last1, *__first1)) { ::new(__first2) value_type(_VSTD::move(*__last1)); - __d.__incr((value_type*)0); + __d.template __incr(); ++__first2; ::new(__first2) value_type(_VSTD::move(*__first1)); } else { ::new(__first2) value_type(_VSTD::move(*__first1)); - __d.__incr((value_type*)0); + __d.template __incr(); ++__first2; ::new(__first2) value_type(_VSTD::move(*__last1)); } @@ -4772,9 +4772,9 @@ __stable_sort(_RandomAccessIterator __first, _RandomAccessIterator __last, _Comp __destruct_n __d(0); unique_ptr __h2(__buff, __d); __stable_sort_move<_Compare>(__first, __m, __comp, __l2, __buff); - __d.__set(__l2, (value_type*)0); + __d.__set(__l2, (value_type*)nullptr); __stable_sort_move<_Compare>(__m, __last, __comp, __len - __l2, __buff + __l2); - __d.__set(__len, (value_type*)0); + __d.__set(__len, (value_type*)nullptr); __merge_move_assign<_Compare>(__buff, __buff + __l2, __buff + __l2, __buff + __len, __first, __comp); // __merge<_Compare>(move_iterator(__buff), // move_iterator(__buff + __l2), diff --git a/libcxx/include/atomic b/libcxx/include/atomic index 70f17699c224b..26522560f47d5 100644 --- a/libcxx/include/atomic +++ b/libcxx/include/atomic @@ -48,6 +48,7 @@ template T kill_dependency(T y) noexcept; #define ATOMIC_BOOL_LOCK_FREE unspecified #define ATOMIC_CHAR_LOCK_FREE unspecified +#define ATOMIC_CHAR8_T_LOCK_FREE unspecified // C++20 #define ATOMIC_CHAR16_T_LOCK_FREE unspecified #define ATOMIC_CHAR32_T_LOCK_FREE unspecified #define ATOMIC_WCHAR_T_LOCK_FREE unspecified @@ -465,6 +466,7 @@ typedef atomic atomic_long; typedef atomic atomic_ulong; typedef atomic atomic_llong; typedef atomic atomic_ullong; +typedef atomic atomic_char8_t; // C++20 typedef atomic atomic_char16_t; typedef atomic atomic_char32_t; typedef atomic atomic_wchar_t; @@ -1125,6 +1127,9 @@ _Tp kill_dependency(_Tp __y) _NOEXCEPT #if defined(__CLANG_ATOMIC_BOOL_LOCK_FREE) # define ATOMIC_BOOL_LOCK_FREE __CLANG_ATOMIC_BOOL_LOCK_FREE # define ATOMIC_CHAR_LOCK_FREE __CLANG_ATOMIC_CHAR_LOCK_FREE +#ifndef _LIBCPP_NO_HAS_CHAR8_T +# define ATOMIC_CHAR8_T_LOCK_FREE __CLANG_ATOMIC_CHAR8_T_LOCK_FREE +#endif # define ATOMIC_CHAR16_T_LOCK_FREE __CLANG_ATOMIC_CHAR16_T_LOCK_FREE # define ATOMIC_CHAR32_T_LOCK_FREE __CLANG_ATOMIC_CHAR32_T_LOCK_FREE # define ATOMIC_WCHAR_T_LOCK_FREE __CLANG_ATOMIC_WCHAR_T_LOCK_FREE @@ -1136,6 +1141,9 @@ _Tp kill_dependency(_Tp __y) _NOEXCEPT #elif defined(__GCC_ATOMIC_BOOL_LOCK_FREE) # define ATOMIC_BOOL_LOCK_FREE __GCC_ATOMIC_BOOL_LOCK_FREE # define ATOMIC_CHAR_LOCK_FREE __GCC_ATOMIC_CHAR_LOCK_FREE +#ifndef _LIBCPP_NO_HAS_CHAR8_T +# define ATOMIC_CHAR8_T_LOCK_FREE __GCC_ATOMIC_CHAR8_T_LOCK_FREE +#endif # define ATOMIC_CHAR16_T_LOCK_FREE __GCC_ATOMIC_CHAR16_T_LOCK_FREE # define ATOMIC_CHAR32_T_LOCK_FREE __GCC_ATOMIC_CHAR32_T_LOCK_FREE # define ATOMIC_WCHAR_T_LOCK_FREE __GCC_ATOMIC_WCHAR_T_LOCK_FREE @@ -1450,6 +1458,9 @@ template<> struct __cxx_is_always_lock_free { enum { __value = 2 == ATOMIC template<> struct __cxx_is_always_lock_free { enum { __value = 2 == ATOMIC_CHAR_LOCK_FREE }; }; template<> struct __cxx_is_always_lock_free { enum { __value = 2 == ATOMIC_CHAR_LOCK_FREE }; }; template<> struct __cxx_is_always_lock_free { enum { __value = 2 == ATOMIC_CHAR_LOCK_FREE }; }; +#ifndef _LIBCPP_NO_HAS_CHAR8_T +template<> struct __cxx_is_always_lock_free { enum { __value = 2 == ATOMIC_CHAR8_T_LOCK_FREE }; }; +#endif template<> struct __cxx_is_always_lock_free { enum { __value = 2 == ATOMIC_CHAR16_T_LOCK_FREE }; }; template<> struct __cxx_is_always_lock_free { enum { __value = 2 == ATOMIC_CHAR32_T_LOCK_FREE }; }; template<> struct __cxx_is_always_lock_free { enum { __value = 2 == ATOMIC_WCHAR_T_LOCK_FREE }; }; @@ -2721,6 +2732,9 @@ typedef atomic atomic_long; typedef atomic atomic_ulong; typedef atomic atomic_llong; typedef atomic atomic_ullong; +#ifndef _LIBCPP_NO_HAS_CHAR8_T +typedef atomic atomic_char8_t; +#endif typedef atomic atomic_char16_t; typedef atomic atomic_char32_t; typedef atomic atomic_wchar_t; diff --git a/libcxx/include/bit b/libcxx/include/bit index ae4605b191666..a720b2e6513f9 100644 --- a/libcxx/include/bit +++ b/libcxx/include/bit @@ -17,13 +17,13 @@ namespace std { // [bit.pow.two], integral powers of 2 template - constexpr bool ispow2(T x) noexcept; // C++20 + constexpr bool has_single_bit(T x) noexcept; // C++20 template - constexpr T ceil2(T x); // C++20 + constexpr T bit_ceil(T x); // C++20 template - constexpr T floor2(T x) noexcept; // C++20 + constexpr T bit_floor(T x) noexcept; // C++20 template - constexpr T log2p1(T x) noexcept; // C++20 + constexpr T bit_width(T x) noexcept; // C++20 // [bit.rotate], rotating template @@ -348,9 +348,9 @@ unsigned __bit_log2(_Tp __t) _NOEXCEPT template _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR -bool __ispow2(_Tp __t) _NOEXCEPT +bool __has_single_bit(_Tp __t) _NOEXCEPT { - static_assert(__bitop_unsigned_integer<_Tp>::value, "__ispow2 requires unsigned"); + static_assert(__bitop_unsigned_integer<_Tp>::value, "__has_single_bit requires unsigned"); return __t != 0 && (((__t & (__t - 1)) == 0)); } @@ -399,7 +399,7 @@ _LIBCPP_INLINE_VISIBILITY constexpr enable_if_t<__bitop_unsigned_integer<_Tp>::value, int> countr_zero(_Tp __t) noexcept { - return __countr_zero(__t); + return __countr_zero(__t); } @@ -424,15 +424,15 @@ popcount(_Tp __t) noexcept template _LIBCPP_INLINE_VISIBILITY constexpr enable_if_t<__bitop_unsigned_integer<_Tp>::value, bool> -ispow2(_Tp __t) noexcept +has_single_bit(_Tp __t) noexcept { - return __ispow2(__t); + return __has_single_bit(__t); } template _LIBCPP_INLINE_VISIBILITY constexpr enable_if_t<__bitop_unsigned_integer<_Tp>::value, _Tp> -floor2(_Tp __t) noexcept +bit_floor(_Tp __t) noexcept { return __t == 0 ? 0 : _Tp{1} << __bit_log2(__t); } @@ -440,11 +440,11 @@ floor2(_Tp __t) noexcept template _LIBCPP_INLINE_VISIBILITY constexpr enable_if_t<__bitop_unsigned_integer<_Tp>::value, _Tp> -ceil2(_Tp __t) noexcept +bit_ceil(_Tp __t) noexcept { if (__t < 2) return 1; const unsigned __n = numeric_limits<_Tp>::digits - countl_zero((_Tp)(__t - 1u)); - _LIBCPP_DEBUG_ASSERT(__libcpp_is_constant_evaluated() || __n != numeric_limits<_Tp>::digits, "Bad input to ceil2"); + _LIBCPP_DEBUG_ASSERT(__libcpp_is_constant_evaluated() || __n != numeric_limits<_Tp>::digits, "Bad input to bit_ceil"); if constexpr (sizeof(_Tp) >= sizeof(unsigned)) return _Tp{1} << __n; @@ -459,12 +459,11 @@ ceil2(_Tp __t) noexcept template _LIBCPP_INLINE_VISIBILITY constexpr enable_if_t<__bitop_unsigned_integer<_Tp>::value, _Tp> -log2p1(_Tp __t) noexcept +bit_width(_Tp __t) noexcept { return __t == 0 ? 0 : __bit_log2(__t) + 1; } - enum class endian { little = 0xDEAD, diff --git a/libcxx/include/bitset b/libcxx/include/bitset index 4755fbeb2152c..0096989eaf43c 100644 --- a/libcxx/include/bitset +++ b/libcxx/include/bitset @@ -625,13 +625,13 @@ protected: explicit _LIBCPP_CONSTEXPR __bitset(unsigned long long) _NOEXCEPT; _LIBCPP_INLINE_VISIBILITY reference __make_ref(size_t) _NOEXCEPT - {return reference(0, 1);} + {return reference(nullptr, 1);} _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR const_reference __make_ref(size_t) const _NOEXCEPT - {return const_reference(0, 1);} + {return const_reference(nullptr, 1);} _LIBCPP_INLINE_VISIBILITY iterator __make_iter(size_t) _NOEXCEPT - {return iterator(0, 0);} + {return iterator(nullptr, 0);} _LIBCPP_INLINE_VISIBILITY const_iterator __make_iter(size_t) const _NOEXCEPT - {return const_iterator(0, 0);} + {return const_iterator(nullptr, 0);} _LIBCPP_INLINE_VISIBILITY void operator&=(const __bitset&) _NOEXCEPT {} _LIBCPP_INLINE_VISIBILITY void operator|=(const __bitset&) _NOEXCEPT {} diff --git a/libcxx/include/chrono b/libcxx/include/chrono index 7b53a0d489656..53e4546010cd8 100644 --- a/libcxx/include/chrono +++ b/libcxx/include/chrono @@ -1077,7 +1077,7 @@ public: is_convertible<_Rep2, rep>::value && (treat_as_floating_point::value || !treat_as_floating_point<_Rep2>::value) - >::type* = 0) + >::type* = nullptr) : __rep_(__r) {} // conversions @@ -1090,7 +1090,7 @@ public: treat_as_floating_point::value || (__no_overflow<_Period2, period>::type::den == 1 && !treat_as_floating_point<_Rep2>::value)) - >::type* = 0) + >::type* = nullptr) : __rep_(_VSTD::chrono::duration_cast(__d).count()) {} // observer @@ -1376,7 +1376,7 @@ public: typename enable_if < is_convertible<_Duration2, duration>::value - >::type* = 0) + >::type* = nullptr) : __d_(t.time_since_epoch()) {} // observer diff --git a/libcxx/include/deque b/libcxx/include/deque index c2ea5f2dbe6de..c66b10225bc07 100644 --- a/libcxx/include/deque +++ b/libcxx/include/deque @@ -1237,7 +1237,7 @@ __deque_base<_Tp, _Allocator>::swap(__deque_base& __c) __map_.swap(__c.__map_); _VSTD::swap(__start_, __c.__start_); _VSTD::swap(size(), __c.size()); - __swap_allocator(__alloc(), __c.__alloc()); + _VSTD::__swap_allocator(__alloc(), __c.__alloc()); } template @@ -2376,7 +2376,7 @@ deque<_Tp, _Allocator>::__append(_ForIter __f, _ForIter __l, for (__deque_block_range __br : __deque_range(__base::end(), __base::end() + __n)) { _ConstructTransaction __tx(this, __br); for (; __tx.__pos_ != __tx.__end_; ++__tx.__pos_, (void)++__f) { - __alloc_traits::construct(__a, std::__to_address(__tx.__pos_), *__f); + __alloc_traits::construct(__a, _VSTD::__to_address(__tx.__pos_), *__f); } } } @@ -2393,7 +2393,7 @@ deque<_Tp, _Allocator>::__append(size_type __n) for (__deque_block_range __br : __deque_range(__base::end(), __base::end() + __n)) { _ConstructTransaction __tx(this, __br); for (; __tx.__pos_ != __tx.__end_; ++__tx.__pos_) { - __alloc_traits::construct(__a, std::__to_address(__tx.__pos_)); + __alloc_traits::construct(__a, _VSTD::__to_address(__tx.__pos_)); } } } @@ -2410,7 +2410,7 @@ deque<_Tp, _Allocator>::__append(size_type __n, const value_type& __v) for (__deque_block_range __br : __deque_range(__base::end(), __base::end() + __n)) { _ConstructTransaction __tx(this, __br); for (; __tx.__pos_ != __tx.__end_; ++__tx.__pos_) { - __alloc_traits::construct(__a, std::__to_address(__tx.__pos_), __v); + __alloc_traits::construct(__a, _VSTD::__to_address(__tx.__pos_), __v); } } @@ -2708,7 +2708,7 @@ void deque<_Tp, _Allocator>::pop_front() { allocator_type& __a = __base::__alloc(); - __alloc_traits::destroy(__a, __to_address(*(__base::__map_.begin() + + __alloc_traits::destroy(__a, _VSTD::__to_address(*(__base::__map_.begin() + __base::__start_ / __base::__block_size) + __base::__start_ % __base::__block_size)); --__base::size(); @@ -2723,7 +2723,7 @@ deque<_Tp, _Allocator>::pop_back() _LIBCPP_ASSERT(!empty(), "deque::pop_back called for empty deque"); allocator_type& __a = __base::__alloc(); size_type __p = __base::size() + __base::__start_ - 1; - __alloc_traits::destroy(__a, __to_address(*(__base::__map_.begin() + + __alloc_traits::destroy(__a, _VSTD::__to_address(*(__base::__map_.begin() + __p / __base::__block_size) + __p % __base::__block_size)); --__base::size(); diff --git a/libcxx/include/experimental/memory_resource b/libcxx/include/experimental/memory_resource index f999fb9befdac..816d21f513681 100644 --- a/libcxx/include/experimental/memory_resource +++ b/libcxx/include/experimental/memory_resource @@ -116,7 +116,7 @@ public: { return do_is_equal(__other); } // 8.5.3, memory.resource.priv -protected: +private: virtual void* do_allocate(size_t, size_t) = 0; virtual void do_deallocate(void*, size_t, size_t) = 0; virtual bool do_is_equal(memory_resource const &) const _NOEXCEPT = 0; @@ -381,7 +381,7 @@ public: { return __alloc_; } // 8.7.3, memory.resource.adaptor.mem -protected: +private: virtual void * do_allocate(size_t __bytes, size_t) { if (__bytes > __max_size()) { @@ -407,7 +407,6 @@ protected: return __p ? __alloc_ == __p->__alloc_ : false; } -private: _LIBCPP_INLINE_VISIBILITY size_t __max_size() const _NOEXCEPT { return numeric_limits::max() - _MaxAlign; diff --git a/libcxx/include/forward_list b/libcxx/include/forward_list index 3bd8db8b7d4d3..96b537c751b12 100644 --- a/libcxx/include/forward_list +++ b/libcxx/include/forward_list @@ -603,7 +603,7 @@ __forward_list_base<_Tp, _Alloc>::swap(__forward_list_base& __x) __is_nothrow_swappable<__node_allocator>::value) #endif { - __swap_allocator(__alloc(), __x.__alloc(), + _VSTD::__swap_allocator(__alloc(), __x.__alloc(), integral_constant()); using _VSTD::swap; swap(__before_begin()->__next_, __x.__before_begin()->__next_); diff --git a/libcxx/include/fstream b/libcxx/include/fstream index 1e2d6072e8fed..af8476c6d451b 100644 --- a/libcxx/include/fstream +++ b/libcxx/include/fstream @@ -287,13 +287,13 @@ private: template basic_filebuf<_CharT, _Traits>::basic_filebuf() - : __extbuf_(0), - __extbufnext_(0), - __extbufend_(0), + : __extbuf_(nullptr), + __extbufnext_(nullptr), + __extbufend_(nullptr), __ebs_(0), - __intbuf_(0), + __intbuf_(nullptr), __ibs_(0), - __file_(0), + __file_(nullptr), __cv_(nullptr), __st_(), __st_last_(), @@ -308,7 +308,7 @@ basic_filebuf<_CharT, _Traits>::basic_filebuf() __cv_ = &use_facet >(this->getloc()); __always_noconv_ = __cv_->always_noconv(); } - setbuf(0, 4096); + setbuf(nullptr, 4096); } #ifndef _LIBCPP_CXX03_LANG @@ -360,13 +360,13 @@ basic_filebuf<_CharT, _Traits>::basic_filebuf(basic_filebuf&& __rhs) (char_type*)__extbuf_ + (__rhs.gptr() - __rhs.eback()), (char_type*)__extbuf_ + (__rhs.egptr() - __rhs.eback())); } - __rhs.__extbuf_ = 0; - __rhs.__extbufnext_ = 0; - __rhs.__extbufend_ = 0; + __rhs.__extbuf_ = nullptr; + __rhs.__extbufnext_ = nullptr; + __rhs.__extbufend_ = nullptr; __rhs.__ebs_ = 0; __rhs.__intbuf_ = 0; __rhs.__ibs_ = 0; - __rhs.__file_ = 0; + __rhs.__file_ = nullptr; __rhs.__st_ = state_type(); __rhs.__st_last_ = state_type(); __rhs.__om_ = 0; @@ -500,7 +500,7 @@ inline bool basic_filebuf<_CharT, _Traits>::is_open() const { - return __file_ != 0; + return __file_ != nullptr; } template @@ -548,8 +548,8 @@ template basic_filebuf<_CharT, _Traits>* basic_filebuf<_CharT, _Traits>::open(const char* __s, ios_base::openmode __mode) { - basic_filebuf<_CharT, _Traits>* __rt = 0; - if (__file_ == 0) + basic_filebuf<_CharT, _Traits>* __rt = nullptr; + if (__file_ == nullptr) { if (const char* __mdstr = __make_mdstring(__mode)) { __rt = this; @@ -559,12 +559,12 @@ basic_filebuf<_CharT, _Traits>::open(const char* __s, ios_base::openmode __mode) if (__mode & ios_base::ate) { if (fseek(__file_, 0, SEEK_END)) { fclose(__file_); - __file_ = 0; - __rt = 0; + __file_ = nullptr; + __rt = nullptr; } } } else - __rt = 0; + __rt = nullptr; } } return __rt; @@ -574,8 +574,8 @@ template inline _LIBCPP_INLINE_VISIBILITY basic_filebuf<_CharT, _Traits>* basic_filebuf<_CharT, _Traits>::__open(int __fd, ios_base::openmode __mode) { - basic_filebuf<_CharT, _Traits>* __rt = 0; - if (__file_ == 0) { + basic_filebuf<_CharT, _Traits>* __rt = nullptr; + if (__file_ == nullptr) { if (const char* __mdstr = __make_mdstring(__mode)) { __rt = this; __file_ = fdopen(__fd, __mdstr); @@ -584,12 +584,12 @@ basic_filebuf<_CharT, _Traits>::__open(int __fd, ios_base::openmode __mode) { if (__mode & ios_base::ate) { if (fseek(__file_, 0, SEEK_END)) { fclose(__file_); - __file_ = 0; - __rt = 0; + __file_ = nullptr; + __rt = nullptr; } } } else - __rt = 0; + __rt = nullptr; } } return __rt; @@ -602,8 +602,8 @@ template basic_filebuf<_CharT, _Traits>* basic_filebuf<_CharT, _Traits>::open(const wchar_t* __s, ios_base::openmode __mode) { - basic_filebuf<_CharT, _Traits>* __rt = 0; - if (__file_ == 0) + basic_filebuf<_CharT, _Traits>* __rt = nullptr; + if (__file_ == nullptr) { __rt = this; const wchar_t* __mdstr; @@ -652,7 +652,7 @@ basic_filebuf<_CharT, _Traits>::open(const wchar_t* __s, ios_base::openmode __mo __mdstr = L"a+b"; break; default: - __rt = 0; + __rt = nullptr; break; } if (__rt) @@ -666,13 +666,13 @@ basic_filebuf<_CharT, _Traits>::open(const wchar_t* __s, ios_base::openmode __mo if (fseek(__file_, 0, SEEK_END)) { fclose(__file_); - __file_ = 0; - __rt = 0; + __file_ = nullptr; + __rt = nullptr; } } } else - __rt = 0; + __rt = nullptr; } } return __rt; @@ -692,16 +692,16 @@ template basic_filebuf<_CharT, _Traits>* basic_filebuf<_CharT, _Traits>::close() { - basic_filebuf<_CharT, _Traits>* __rt = 0; + basic_filebuf<_CharT, _Traits>* __rt = nullptr; if (__file_) { __rt = this; unique_ptr __h(__file_, fclose); if (sync()) - __rt = 0; + __rt = nullptr; if (fclose(__h.release())) - __rt = 0; - __file_ = 0; + __rt = nullptr; + __file_ = nullptr; setbuf(0, 0); } return __rt; @@ -711,11 +711,11 @@ template typename basic_filebuf<_CharT, _Traits>::int_type basic_filebuf<_CharT, _Traits>::underflow() { - if (__file_ == 0) + if (__file_ == nullptr) return traits_type::eof(); bool __initial = __read_mode(); char_type __1buf; - if (this->gptr() == 0) + if (this->gptr() == nullptr) this->setg(&__1buf, &__1buf+1, &__1buf+1); const size_t __unget_sz = __initial ? 0 : min((this->egptr() - this->eback()) / 2, 4); int_type __c = traits_type::eof(); @@ -773,7 +773,7 @@ basic_filebuf<_CharT, _Traits>::underflow() else __c = traits_type::to_int_type(*this->gptr()); if (this->eback() == &__1buf) - this->setg(0, 0, 0); + this->setg(nullptr, nullptr, nullptr); return __c; } @@ -803,7 +803,7 @@ template typename basic_filebuf<_CharT, _Traits>::int_type basic_filebuf<_CharT, _Traits>::overflow(int_type __c) { - if (__file_ == 0) + if (__file_ == nullptr) return traits_type::eof(); __write_mode(); char_type __1buf; @@ -811,7 +811,7 @@ basic_filebuf<_CharT, _Traits>::overflow(int_type __c) char_type* __epb_save = this->epptr(); if (!traits_type::eq_int_type(__c, traits_type::eof())) { - if (this->pptr() == 0) + if (this->pptr() == nullptr) this->setp(&__1buf, &__1buf+1); *this->pptr() = traits_type::to_char_type(__c); this->pbump(1); @@ -868,8 +868,8 @@ template basic_streambuf<_CharT, _Traits>* basic_filebuf<_CharT, _Traits>::setbuf(char_type* __s, streamsize __n) { - this->setg(0, 0, 0); - this->setp(0, 0); + this->setg(nullptr, nullptr, nullptr); + this->setp(nullptr, nullptr); if (__owns_eb_) delete [] __extbuf_; if (__owns_ib_) @@ -911,7 +911,7 @@ basic_filebuf<_CharT, _Traits>::setbuf(char_type* __s, streamsize __n) else { __ibs_ = 0; - __intbuf_ = 0; + __intbuf_ = nullptr; __owns_ib_ = false; } return this; @@ -926,7 +926,7 @@ basic_filebuf<_CharT, _Traits>::seekoff(off_type __off, ios_base::seekdir __way, __throw_bad_cast(); int __width = __cv_->encoding(); - if (__file_ == 0 || (__width <= 0 && __off != 0) || sync()) + if (__file_ == nullptr || (__width <= 0 && __off != 0) || sync()) return pos_type(off_type(-1)); // __width > 0 || __off == 0 int __whence; @@ -961,7 +961,7 @@ template typename basic_filebuf<_CharT, _Traits>::pos_type basic_filebuf<_CharT, _Traits>::seekpos(pos_type __sp, ios_base::openmode) { - if (__file_ == 0 || sync()) + if (__file_ == nullptr || sync()) return pos_type(off_type(-1)); #if defined(_LIBCPP_HAS_NO_OFF_T_FUNCTIONS) if (fseek(__file_, __sp, SEEK_SET)) @@ -978,7 +978,7 @@ template int basic_filebuf<_CharT, _Traits>::sync() { - if (__file_ == 0) + if (__file_ == nullptr) return 0; if (!__cv_) __throw_bad_cast(); @@ -1037,7 +1037,7 @@ basic_filebuf<_CharT, _Traits>::sync() if (__update_st) __st_ = __state; __extbufnext_ = __extbufend_ = __extbuf_; - this->setg(0, 0, 0); + this->setg(nullptr, nullptr, nullptr); __cm_ = 0; } return 0; @@ -1053,8 +1053,8 @@ basic_filebuf<_CharT, _Traits>::imbue(const locale& __loc) __always_noconv_ = __cv_->always_noconv(); if (__old_anc != __always_noconv_) { - this->setg(0, 0, 0); - this->setp(0, 0); + this->setg(nullptr, nullptr, nullptr); + this->setp(nullptr, nullptr); // invariant, char_type is char, else we couldn't get here if (__always_noconv_) // need to dump __intbuf_ { @@ -1064,7 +1064,7 @@ basic_filebuf<_CharT, _Traits>::imbue(const locale& __loc) __ebs_ = __ibs_; __extbuf_ = (char*)__intbuf_; __ibs_ = 0; - __intbuf_ = 0; + __intbuf_ = nullptr; __owns_ib_ = false; } else // need to obtain an __intbuf_. @@ -1093,7 +1093,7 @@ basic_filebuf<_CharT, _Traits>::__read_mode() { if (!(__cm_ & ios_base::in)) { - this->setp(0, 0); + this->setp(nullptr, nullptr); if (__always_noconv_) this->setg((char_type*)__extbuf_, (char_type*)__extbuf_ + __ebs_, @@ -1112,7 +1112,7 @@ basic_filebuf<_CharT, _Traits>::__write_mode() { if (!(__cm_ & ios_base::out)) { - this->setg(0, 0, 0); + this->setg(nullptr, nullptr, nullptr); if (__ebs_ > sizeof(__extbuf_min_)) { if (__always_noconv_) @@ -1122,7 +1122,7 @@ basic_filebuf<_CharT, _Traits>::__write_mode() this->setp(__intbuf_, __intbuf_ + (__ibs_ - 1)); } else - this->setp(0, 0); + this->setp(nullptr, nullptr); __cm_ = ios_base::out; } } @@ -1208,7 +1208,7 @@ inline basic_ifstream<_CharT, _Traits>::basic_ifstream(const char* __s, ios_base::openmode __mode) : basic_istream(&__sb_) { - if (__sb_.open(__s, __mode | ios_base::in) == 0) + if (__sb_.open(__s, __mode | ios_base::in) == nullptr) this->setstate(ios_base::failbit); } @@ -1218,7 +1218,7 @@ inline basic_ifstream<_CharT, _Traits>::basic_ifstream(const wchar_t* __s, ios_base::openmode __mode) : basic_istream(&__sb_) { - if (__sb_.open(__s, __mode | ios_base::in) == 0) + if (__sb_.open(__s, __mode | ios_base::in) == nullptr) this->setstate(ios_base::failbit); } #endif @@ -1228,7 +1228,7 @@ inline basic_ifstream<_CharT, _Traits>::basic_ifstream(const string& __s, ios_base::openmode __mode) : basic_istream(&__sb_) { - if (__sb_.open(__s, __mode | ios_base::in) == 0) + if (__sb_.open(__s, __mode | ios_base::in) == nullptr) this->setstate(ios_base::failbit); } #endif @@ -1421,7 +1421,7 @@ inline basic_ofstream<_CharT, _Traits>::basic_ofstream(const char* __s, ios_base::openmode __mode) : basic_ostream(&__sb_) { - if (__sb_.open(__s, __mode | ios_base::out) == 0) + if (__sb_.open(__s, __mode | ios_base::out) == nullptr) this->setstate(ios_base::failbit); } @@ -1431,7 +1431,7 @@ inline basic_ofstream<_CharT, _Traits>::basic_ofstream(const wchar_t* __s, ios_base::openmode __mode) : basic_ostream(&__sb_) { - if (__sb_.open(__s, __mode | ios_base::out) == 0) + if (__sb_.open(__s, __mode | ios_base::out) == nullptr) this->setstate(ios_base::failbit); } #endif @@ -1441,7 +1441,7 @@ inline basic_ofstream<_CharT, _Traits>::basic_ofstream(const string& __s, ios_base::openmode __mode) : basic_ostream(&__sb_) { - if (__sb_.open(__s, __mode | ios_base::out) == 0) + if (__sb_.open(__s, __mode | ios_base::out) == nullptr) this->setstate(ios_base::failbit); } #endif @@ -1550,7 +1550,7 @@ inline void basic_ofstream<_CharT, _Traits>::close() { - if (__sb_.close() == 0) + if (__sb_.close() == nullptr) this->setstate(ios_base::failbit); } @@ -1634,7 +1634,7 @@ inline basic_fstream<_CharT, _Traits>::basic_fstream(const char* __s, ios_base::openmode __mode) : basic_iostream(&__sb_) { - if (__sb_.open(__s, __mode) == 0) + if (__sb_.open(__s, __mode) == nullptr) this->setstate(ios_base::failbit); } @@ -1644,7 +1644,7 @@ inline basic_fstream<_CharT, _Traits>::basic_fstream(const wchar_t* __s, ios_base::openmode __mode) : basic_iostream(&__sb_) { - if (__sb_.open(__s, __mode) == 0) + if (__sb_.open(__s, __mode) == nullptr) this->setstate(ios_base::failbit); } #endif @@ -1654,7 +1654,7 @@ inline basic_fstream<_CharT, _Traits>::basic_fstream(const string& __s, ios_base::openmode __mode) : basic_iostream(&__sb_) { - if (__sb_.open(__s, __mode) == 0) + if (__sb_.open(__s, __mode) == nullptr) this->setstate(ios_base::failbit); } #endif @@ -1754,7 +1754,7 @@ inline void basic_fstream<_CharT, _Traits>::close() { - if (__sb_.close() == 0) + if (__sb_.close() == nullptr) this->setstate(ios_base::failbit); } diff --git a/libcxx/include/functional b/libcxx/include/functional index 9a0ca96c4611b..0979e7d2bd1d7 100644 --- a/libcxx/include/functional +++ b/libcxx/include/functional @@ -1735,7 +1735,7 @@ __func<_Fp, _Alloc, _Rp(_ArgTypes...)>::target(const type_info& __ti) const _NOE { if (__ti == typeid(_Fp)) return &__f_.__target(); - return (const void*)0; + return nullptr; } template @@ -1765,11 +1765,11 @@ template class __value_func<_Rp(_ArgTypes...)> public: _LIBCPP_INLINE_VISIBILITY - __value_func() _NOEXCEPT : __f_(0) {} + __value_func() _NOEXCEPT : __f_(nullptr) {} template _LIBCPP_INLINE_VISIBILITY __value_func(_Fp&& __f, const _Alloc& __a) - : __f_(0) + : __f_(nullptr) { typedef allocator_traits<_Alloc> __alloc_traits; typedef __function::__func<_Fp, _Alloc, _Rp(_ArgTypes...)> _Fun; @@ -1804,8 +1804,8 @@ template class __value_func<_Rp(_ArgTypes...)> _LIBCPP_INLINE_VISIBILITY __value_func(const __value_func& __f) { - if (__f.__f_ == 0) - __f_ = 0; + if (__f.__f_ == nullptr) + __f_ = nullptr; else if ((void*)__f.__f_ == &__f.__buf_) { __f_ = __as_base(&__buf_); @@ -1818,8 +1818,8 @@ template class __value_func<_Rp(_ArgTypes...)> _LIBCPP_INLINE_VISIBILITY __value_func(__value_func&& __f) _NOEXCEPT { - if (__f.__f_ == 0) - __f_ = 0; + if (__f.__f_ == nullptr) + __f_ = nullptr; else if ((void*)__f.__f_ == &__f.__buf_) { __f_ = __as_base(&__buf_); @@ -1828,7 +1828,7 @@ template class __value_func<_Rp(_ArgTypes...)> else { __f_ = __f.__f_; - __f.__f_ = 0; + __f.__f_ = nullptr; } } @@ -1845,8 +1845,8 @@ template class __value_func<_Rp(_ArgTypes...)> __value_func& operator=(__value_func&& __f) { *this = nullptr; - if (__f.__f_ == 0) - __f_ = 0; + if (__f.__f_ == nullptr) + __f_ = nullptr; else if ((void*)__f.__f_ == &__f.__buf_) { __f_ = __as_base(&__buf_); @@ -1855,7 +1855,7 @@ template class __value_func<_Rp(_ArgTypes...)> else { __f_ = __f.__f_; - __f.__f_ = 0; + __f.__f_ = nullptr; } return *this; } @@ -1864,7 +1864,7 @@ template class __value_func<_Rp(_ArgTypes...)> __value_func& operator=(nullptr_t) { __func* __f = __f_; - __f_ = 0; + __f_ = nullptr; if ((void*)__f == &__buf_) __f->destroy(); else if (__f) @@ -1875,7 +1875,7 @@ template class __value_func<_Rp(_ArgTypes...)> _LIBCPP_INLINE_VISIBILITY _Rp operator()(_ArgTypes&&... __args) const { - if (__f_ == 0) + if (__f_ == nullptr) __throw_bad_function_call(); return (*__f_)(_VSTD::forward<_ArgTypes>(__args)...); } @@ -1891,10 +1891,10 @@ template class __value_func<_Rp(_ArgTypes...)> __func* __t = __as_base(&__tempbuf); __f_->__clone(__t); __f_->destroy(); - __f_ = 0; + __f_ = nullptr; __f.__f_->__clone(__as_base(&__buf_)); __f.__f_->destroy(); - __f.__f_ = 0; + __f.__f_ = nullptr; __f_ = __as_base(&__buf_); __t->__clone(__as_base(&__f.__buf_)); __t->destroy(); @@ -1919,13 +1919,13 @@ template class __value_func<_Rp(_ArgTypes...)> } _LIBCPP_INLINE_VISIBILITY - _LIBCPP_EXPLICIT operator bool() const _NOEXCEPT { return __f_ != 0; } + _LIBCPP_EXPLICIT operator bool() const _NOEXCEPT { return __f_ != nullptr; } #ifndef _LIBCPP_NO_RTTI _LIBCPP_INLINE_VISIBILITY const std::type_info& target_type() const _NOEXCEPT { - if (__f_ == 0) + if (__f_ == nullptr) return typeid(void); return __f_->target_type(); } @@ -1933,8 +1933,8 @@ template class __value_func<_Rp(_ArgTypes...)> template _LIBCPP_INLINE_VISIBILITY const _Tp* target() const _NOEXCEPT { - if (__f_ == 0) - return 0; + if (__f_ == nullptr) + return nullptr; return (const _Tp*)__f_->target(typeid(_Tp)); } #endif // _LIBCPP_NO_RTTI diff --git a/libcxx/include/ios b/libcxx/include/ios index ae758ddb35ef7..653e3a95fc7ee 100644 --- a/libcxx/include/ios +++ b/libcxx/include/ios @@ -710,7 +710,7 @@ void basic_ios<_CharT, _Traits>::init(basic_streambuf* __sb) { ios_base::init(__sb); - __tie_ = 0; + __tie_ = nullptr; __fill_ = traits_type::eof(); } @@ -821,7 +821,7 @@ basic_ios<_CharT, _Traits>::move(basic_ios& __rhs) { ios_base::move(__rhs); __tie_ = __rhs.__tie_; - __rhs.__tie_ = 0; + __rhs.__tie_ = nullptr; __fill_ = __rhs.__fill_; } diff --git a/libcxx/include/istream b/libcxx/include/istream index c541905b2ea23..5e984909f8783 100644 --- a/libcxx/include/istream +++ b/libcxx/include/istream @@ -1142,7 +1142,7 @@ basic_istream<_CharT, _Traits>::putback(char_type __c) try { #endif // _LIBCPP_NO_EXCEPTIONS - if (this->rdbuf() == 0 || this->rdbuf()->sputbackc(__c) == traits_type::eof()) + if (this->rdbuf() == nullptr || this->rdbuf()->sputbackc(__c) == traits_type::eof()) __state |= ios_base::badbit; #ifndef _LIBCPP_NO_EXCEPTIONS } @@ -1179,7 +1179,7 @@ basic_istream<_CharT, _Traits>::unget() try { #endif // _LIBCPP_NO_EXCEPTIONS - if (this->rdbuf() == 0 || this->rdbuf()->sungetc() == traits_type::eof()) + if (this->rdbuf() == nullptr || this->rdbuf()->sungetc() == traits_type::eof()) __state |= ios_base::badbit; #ifndef _LIBCPP_NO_EXCEPTIONS } @@ -1215,7 +1215,7 @@ basic_istream<_CharT, _Traits>::sync() try { #endif // _LIBCPP_NO_EXCEPTIONS - if (this->rdbuf() == 0) + if (this->rdbuf() == nullptr) return -1; if (this->rdbuf()->pubsync() == -1) { diff --git a/libcxx/include/iterator b/libcxx/include/iterator index 99f9b8173dbfe..d4667d39ddb88 100644 --- a/libcxx/include/iterator +++ b/libcxx/include/iterator @@ -512,9 +512,9 @@ struct __has_iterator_category private: struct __two {char __lx; char __lxx;}; template static __two __test(...); - template static char __test(typename _Up::iterator_category* = 0); + template static char __test(typename _Up::iterator_category* = nullptr); public: - static const bool value = sizeof(__test<_Tp>(0)) == 1; + static const bool value = sizeof(__test<_Tp>(nullptr)) == 1; }; template struct __iterator_traits_impl {}; @@ -995,11 +995,11 @@ private: istream_type* __in_stream_; _Tp __value_; public: - _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR istream_iterator() : __in_stream_(0), __value_() {} + _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR istream_iterator() : __in_stream_(nullptr), __value_() {} _LIBCPP_INLINE_VISIBILITY istream_iterator(istream_type& __s) : __in_stream_(_VSTD::addressof(__s)) { if (!(*__in_stream_ >> __value_)) - __in_stream_ = 0; + __in_stream_ = nullptr; } _LIBCPP_INLINE_VISIBILITY const _Tp& operator*() const {return __value_;} @@ -1007,7 +1007,7 @@ public: _LIBCPP_INLINE_VISIBILITY istream_iterator& operator++() { if (!(*__in_stream_ >> __value_)) - __in_stream_ = 0; + __in_stream_ = nullptr; return *this; } _LIBCPP_INLINE_VISIBILITY istream_iterator operator++(int) @@ -1067,7 +1067,7 @@ private: const char_type* __delim_; public: _LIBCPP_INLINE_VISIBILITY ostream_iterator(ostream_type& __s) _NOEXCEPT - : __out_stream_(_VSTD::addressof(__s)), __delim_(0) {} + : __out_stream_(_VSTD::addressof(__s)), __delim_(nullptr) {} _LIBCPP_INLINE_VISIBILITY ostream_iterator(ostream_type& __s, const _CharT* __delimiter) _NOEXCEPT : __out_stream_(_VSTD::addressof(__s)), __delim_(__delimiter) {} _LIBCPP_INLINE_VISIBILITY ostream_iterator& operator=(const _Tp& __value_) @@ -1113,11 +1113,11 @@ private: bool __test_for_eof() const { if (__sbuf_ && traits_type::eq_int_type(__sbuf_->sgetc(), traits_type::eof())) - __sbuf_ = 0; - return __sbuf_ == 0; + __sbuf_ = nullptr; + return __sbuf_ == nullptr; } public: - _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR istreambuf_iterator() _NOEXCEPT : __sbuf_(0) {} + _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR istreambuf_iterator() _NOEXCEPT : __sbuf_(nullptr) {} _LIBCPP_INLINE_VISIBILITY istreambuf_iterator(istream_type& __s) _NOEXCEPT : __sbuf_(__s.rdbuf()) {} _LIBCPP_INLINE_VISIBILITY istreambuf_iterator(streambuf_type* __s) _NOEXCEPT @@ -1182,13 +1182,13 @@ public: _LIBCPP_INLINE_VISIBILITY ostreambuf_iterator& operator=(_CharT __c) { if (__sbuf_ && traits_type::eq_int_type(__sbuf_->sputc(__c), traits_type::eof())) - __sbuf_ = 0; + __sbuf_ = nullptr; return *this; } _LIBCPP_INLINE_VISIBILITY ostreambuf_iterator& operator*() {return *this;} _LIBCPP_INLINE_VISIBILITY ostreambuf_iterator& operator++() {return *this;} _LIBCPP_INLINE_VISIBILITY ostreambuf_iterator& operator++(int) {return *this;} - _LIBCPP_INLINE_VISIBILITY bool failed() const _NOEXCEPT {return __sbuf_ == 0;} + _LIBCPP_INLINE_VISIBILITY bool failed() const _NOEXCEPT {return __sbuf_ == nullptr;} template friend @@ -1441,7 +1441,7 @@ public: } template _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_IF_NODEBUG __wrap_iter(const __wrap_iter<_Up>& __u, - typename enable_if::value>::type* = 0) _NOEXCEPT + typename enable_if::value>::type* = nullptr) _NOEXCEPT : __i(__u.base()) { #if _LIBCPP_DEBUG_LEVEL == 2 diff --git a/libcxx/include/list b/libcxx/include/list index 1c085b4e6dfa2..7e4c76ddb8d3c 100644 --- a/libcxx/include/list +++ b/libcxx/include/list @@ -783,7 +783,7 @@ __list_imp<_Tp, _Alloc>::swap(__list_imp& __c) "list::swap: Either propagate_on_container_swap must be true" " or the allocators must compare equal"); using _VSTD::swap; - __swap_allocator(__node_alloc(), __c.__node_alloc()); + _VSTD::__swap_allocator(__node_alloc(), __c.__node_alloc()); swap(__sz(), __c.__sz()); swap(__end_, __c.__end_); if (__sz() == 0) diff --git a/libcxx/include/locale b/libcxx/include/locale index 2723c0cfea666..80a5134fdb2e6 100644 --- a/libcxx/include/locale +++ b/libcxx/include/locale @@ -257,11 +257,11 @@ __scan_keyword(_InputIterator& __b, _InputIterator __e, const unsigned char __does_match = '\2'; unsigned char __statbuf[100]; unsigned char* __status = __statbuf; - unique_ptr __stat_hold(0, free); + unique_ptr __stat_hold(nullptr, free); if (__nkw > sizeof(__statbuf)) { __status = (unsigned char*)malloc(__nkw); - if (__status == 0) + if (__status == nullptr) __throw_bad_alloc(); __stat_hold.reset(__status); } @@ -1560,14 +1560,14 @@ num_put<_CharT, _OutputIterator>::do_put(iter_type __s, ios_base& __iob, (int)__iob.precision(), __v); else __nc = __libcpp_snprintf_l(__nb, __nbuf, _LIBCPP_GET_C_LOCALE, __fmt, __v); - unique_ptr __nbh(0, free); + unique_ptr __nbh(nullptr, free); if (__nc > static_cast(__nbuf-1)) { if (__specify_precision) __nc = __libcpp_asprintf_l(&__nb, _LIBCPP_GET_C_LOCALE, __fmt, (int)__iob.precision(), __v); else __nc = __libcpp_asprintf_l(&__nb, _LIBCPP_GET_C_LOCALE, __fmt, __v); - if (__nb == 0) + if (__nb == nullptr) __throw_bad_alloc(); __nbh.reset(__nb); } @@ -1611,14 +1611,14 @@ num_put<_CharT, _OutputIterator>::do_put(iter_type __s, ios_base& __iob, (int)__iob.precision(), __v); else __nc = __libcpp_snprintf_l(__nb, __nbuf, _LIBCPP_GET_C_LOCALE, __fmt, __v); - unique_ptr __nbh(0, free); + unique_ptr __nbh(nullptr, free); if (__nc > static_cast(__nbuf-1)) { if (__specify_precision) __nc = __libcpp_asprintf_l(&__nb, _LIBCPP_GET_C_LOCALE, __fmt, (int)__iob.precision(), __v); else __nc = __libcpp_asprintf_l(&__nb, _LIBCPP_GET_C_LOCALE, __fmt, __v); - if (__nb == 0) + if (__nb == nullptr) __throw_bad_alloc(); __nbh.reset(__nb); } @@ -3104,11 +3104,11 @@ money_get<_CharT, _InputIterator>::do_get(iter_type __b, iter_type __e, __ct.widen(__src, __src + (sizeof(__src)-1), __atoms); char __nbuf[__bz]; char* __nc = __nbuf; - unique_ptr __h(0, free); + unique_ptr __h(nullptr, free); if (__wn - __wb.get() > __bz-2) { __h.reset((char*)malloc(static_cast(__wn - __wb.get() + 2))); - if (__h.get() == 0) + if (__h.get() == nullptr) __throw_bad_alloc(); __nc = __h.get(); } @@ -3393,13 +3393,13 @@ money_put<_CharT, _OutputIterator>::do_put(iter_type __s, bool __intl, char_type __digits[__bs]; char_type* __db = __digits; size_t __n = static_cast(snprintf(__bb, __bs, "%.0Lf", __units)); - unique_ptr __hn(0, free); + unique_ptr __hn(nullptr, free); unique_ptr __hd(0, free); // secure memory for digit storage if (__n > __bs-1) { __n = static_cast(__libcpp_asprintf_l(&__bb, _LIBCPP_GET_C_LOCALE, "%.0Lf", __units)); - if (__bb == 0) + if (__bb == nullptr) __throw_bad_alloc(); __hn.reset(__bb); __hd.reset((char_type*)malloc(__n * sizeof(char_type))); @@ -3919,7 +3919,7 @@ private: wbuffer_convert(const wbuffer_convert&); wbuffer_convert& operator=(const wbuffer_convert&); public: - _LIBCPP_EXPLICIT_AFTER_CXX11 wbuffer_convert(streambuf* __bytebuf = 0, + _LIBCPP_EXPLICIT_AFTER_CXX11 wbuffer_convert(streambuf* __bytebuf = nullptr, _Codecvt* __pcvt = new _Codecvt, state_type __state = state_type()); ~wbuffer_convert(); @@ -3957,9 +3957,9 @@ private: template wbuffer_convert<_Codecvt, _Elem, _Tr>:: wbuffer_convert(streambuf* __bytebuf, _Codecvt* __pcvt, state_type __state) - : __extbuf_(0), - __extbufnext_(0), - __extbufend_(0), + : __extbuf_(nullptr), + __extbufnext_(nullptr), + __extbufend_(nullptr), __ebs_(0), __intbuf_(0), __ibs_(0), @@ -4332,12 +4332,12 @@ template wbuffer_convert<_Codecvt, _Elem, _Tr>* wbuffer_convert<_Codecvt, _Elem, _Tr>::__close() { - wbuffer_convert* __rt = 0; - if (__cv_ != 0 && __bufptr_ != 0) + wbuffer_convert* __rt = nullptr; + if (__cv_ != nullptr && __bufptr_ != nullptr) { __rt = this; if ((__cm_ & ios_base::out) && sync()) - __rt = 0; + __rt = nullptr; } return __rt; } diff --git a/libcxx/include/memory b/libcxx/include/memory index eee0bdf8f975a..f42f03f53f803 100644 --- a/libcxx/include/memory +++ b/libcxx/include/memory @@ -1912,7 +1912,7 @@ public: _LIBCPP_INLINE_VISIBILITY _Tp* release() _NOEXCEPT { _Tp* __t = __ptr_; - __ptr_ = 0; + __ptr_ = nullptr; return __t; } _LIBCPP_INLINE_VISIBILITY void reset(_Tp* __p = 0) _NOEXCEPT @@ -2853,7 +2853,7 @@ public: : __size_(__s) {} template - _LIBCPP_INLINE_VISIBILITY void __incr(_Tp*) _NOEXCEPT + _LIBCPP_INLINE_VISIBILITY void __incr() _NOEXCEPT {__incr(integral_constant::value>());} template @@ -3545,7 +3545,7 @@ public: _LIBCPP_INLINE_VISIBILITY bool unique() const _NOEXCEPT {return use_count() == 1;} _LIBCPP_INLINE_VISIBILITY - _LIBCPP_EXPLICIT operator bool() const _NOEXCEPT {return get() != 0;} + _LIBCPP_EXPLICIT operator bool() const _NOEXCEPT {return get() != nullptr;} template _LIBCPP_INLINE_VISIBILITY bool owner_before(shared_ptr<_Up> const& __p) const _NOEXCEPT @@ -3649,8 +3649,8 @@ template inline _LIBCPP_CONSTEXPR shared_ptr<_Tp>::shared_ptr() _NOEXCEPT - : __ptr_(0), - __cntrl_(0) + : __ptr_(nullptr), + __cntrl_(nullptr) { } @@ -3658,8 +3658,8 @@ template inline _LIBCPP_CONSTEXPR shared_ptr<_Tp>::shared_ptr(nullptr_t) _NOEXCEPT - : __ptr_(0), - __cntrl_(0) + : __ptr_(nullptr), + __cntrl_(nullptr) { } @@ -3704,7 +3704,7 @@ shared_ptr<_Tp>::shared_ptr(_Yp* __p, _Dp __d, template template shared_ptr<_Tp>::shared_ptr(nullptr_t __p, _Dp __d) - : __ptr_(0) + : __ptr_(nullptr) { #ifndef _LIBCPP_NO_EXCEPTIONS try @@ -3755,7 +3755,7 @@ shared_ptr<_Tp>::shared_ptr(_Yp* __p, _Dp __d, _Alloc __a, template template shared_ptr<_Tp>::shared_ptr(nullptr_t __p, _Dp __d, _Alloc __a) - : __ptr_(0) + : __ptr_(nullptr) { #ifndef _LIBCPP_NO_EXCEPTIONS try @@ -3819,8 +3819,8 @@ shared_ptr<_Tp>::shared_ptr(shared_ptr&& __r) _NOEXCEPT : __ptr_(__r.__ptr_), __cntrl_(__r.__cntrl_) { - __r.__ptr_ = 0; - __r.__cntrl_ = 0; + __r.__ptr_ = nullptr; + __r.__cntrl_ = nullptr; } template @@ -3832,8 +3832,8 @@ shared_ptr<_Tp>::shared_ptr(shared_ptr<_Yp>&& __r, : __ptr_(__r.__ptr_), __cntrl_(__r.__cntrl_) { - __r.__ptr_ = 0; - __r.__cntrl_ = 0; + __r.__ptr_ = nullptr; + __r.__cntrl_ = nullptr; } #if _LIBCPP_STD_VER <= 14 || defined(_LIBCPP_ENABLE_CXX17_REMOVED_AUTO_PTR) @@ -4368,7 +4368,7 @@ public: {return __cntrl_ ? __cntrl_->use_count() : 0;} _LIBCPP_INLINE_VISIBILITY bool expired() const _NOEXCEPT - {return __cntrl_ == 0 || __cntrl_->use_count() == 0;} + {return __cntrl_ == nullptr || __cntrl_->use_count() == 0;} shared_ptr<_Tp> lock() const _NOEXCEPT; template _LIBCPP_INLINE_VISIBILITY @@ -4392,8 +4392,8 @@ template inline _LIBCPP_CONSTEXPR weak_ptr<_Tp>::weak_ptr() _NOEXCEPT - : __ptr_(0), - __cntrl_(0) + : __ptr_(nullptr), + __cntrl_(nullptr) { } @@ -4439,8 +4439,8 @@ weak_ptr<_Tp>::weak_ptr(weak_ptr&& __r) _NOEXCEPT : __ptr_(__r.__ptr_), __cntrl_(__r.__cntrl_) { - __r.__ptr_ = 0; - __r.__cntrl_ = 0; + __r.__ptr_ = nullptr; + __r.__cntrl_ = nullptr; } template @@ -4452,8 +4452,8 @@ weak_ptr<_Tp>::weak_ptr(weak_ptr<_Yp>&& __r, : __ptr_(__r.__ptr_), __cntrl_(__r.__cntrl_) { - __r.__ptr_ = 0; - __r.__cntrl_ = 0; + __r.__ptr_ = nullptr; + __r.__cntrl_ = nullptr; } template @@ -4555,7 +4555,7 @@ shared_ptr<_Tp>::shared_ptr(const weak_ptr<_Yp>& __r, : __ptr_(__r.__ptr_), __cntrl_(__r.__cntrl_ ? __r.__cntrl_->lock() : __r.__cntrl_) { - if (__cntrl_ == 0) + if (__cntrl_ == nullptr) __throw_bad_weak_ptr(); } @@ -4890,35 +4890,35 @@ _LIBCPP_FUNC_VIS void* align(size_t __align, size_t __sz, void*& __ptr, size_t& // --- Helper for container swap -- template -inline _LIBCPP_INLINE_VISIBILITY -void __swap_allocator(_Alloc & __a1, _Alloc & __a2) +_LIBCPP_INLINE_VISIBILITY +void __swap_allocator(_Alloc & __a1, _Alloc & __a2, true_type) #if _LIBCPP_STD_VER >= 14 _NOEXCEPT #else _NOEXCEPT_(__is_nothrow_swappable<_Alloc>::value) #endif { - __swap_allocator(__a1, __a2, - integral_constant::propagate_on_container_swap::value>()); + using _VSTD::swap; + swap(__a1, __a2); } template -_LIBCPP_INLINE_VISIBILITY -void __swap_allocator(_Alloc & __a1, _Alloc & __a2, true_type) +inline _LIBCPP_INLINE_VISIBILITY +void __swap_allocator(_Alloc &, _Alloc &, false_type) _NOEXCEPT {} + +template +inline _LIBCPP_INLINE_VISIBILITY +void __swap_allocator(_Alloc & __a1, _Alloc & __a2) #if _LIBCPP_STD_VER >= 14 _NOEXCEPT #else _NOEXCEPT_(__is_nothrow_swappable<_Alloc>::value) #endif { - using _VSTD::swap; - swap(__a1, __a2); + _VSTD::__swap_allocator(__a1, __a2, + integral_constant::propagate_on_container_swap::value>()); } -template -inline _LIBCPP_INLINE_VISIBILITY -void __swap_allocator(_Alloc &, _Alloc &, false_type) _NOEXCEPT {} - template > struct __noexcept_move_assign_container : public integral_constant #include <__availability> +#include +#include #include #include -#include #include -#ifdef _LIBCPP_NO_EXCEPTIONS -#include -#endif #if defined(_LIBCPP_ABI_VCRUNTIME) #include @@ -303,6 +301,36 @@ inline _LIBCPP_INLINE_VISIBILITY void __libcpp_deallocate_unsized(void* __ptr, s #endif } +#if !defined(_LIBCPP_HAS_NO_LIBRARY_ALIGNED_ALLOCATION) +// Low-level helpers to call the aligned allocation and deallocation functions +// on the target platform. This is used to implement libc++'s own memory +// allocation routines -- if you need to allocate memory inside the library, +// chances are that you want to use `__libcpp_allocate` instead. +// +// Returns the allocated memory, or `nullptr` on failure. +inline _LIBCPP_INLINE_VISIBILITY +void* __libcpp_aligned_alloc(std::size_t __alignment, std::size_t __size) { +#if defined(_LIBCPP_MSVCRT_LIKE) + return ::_aligned_malloc(__size, __alignment); +#else + void* __result = nullptr; + ::posix_memalign(&__result, __alignment, __size); + // If posix_memalign fails, __result is unmodified so we still return `nullptr`. + return __result; +#endif +} + +inline _LIBCPP_INLINE_VISIBILITY +void __libcpp_aligned_free(void* __ptr) { +#if defined(_LIBCPP_MSVCRT_LIKE) + ::_aligned_free(__ptr); +#else + ::free(__ptr); +#endif +} +#endif // !_LIBCPP_HAS_NO_ALIGNED_ALLOCATION + + template _LIBCPP_NODISCARD_AFTER_CXX17 inline _LIBCPP_CONSTEXPR _Tp* __launder(_Tp* __p) _NOEXCEPT diff --git a/libcxx/include/numeric b/libcxx/include/numeric index 5ceadc17755ee..50070ded8fed2 100644 --- a/libcxx/include/numeric +++ b/libcxx/include/numeric @@ -336,7 +336,7 @@ _OutputIterator inclusive_scan(_InputIterator __first, _InputIterator __last, for (; __first != __last; ++__first, (void) ++__result) { __init = __b(__init, *__first); *__result = __init; - } + } return __result; } @@ -349,7 +349,7 @@ _OutputIterator inclusive_scan(_InputIterator __first, _InputIterator __last, *__result++ = __init; if (++__first != __last) return _VSTD::inclusive_scan(__first, __last, __result, __b, __init); - } + } return __result; } @@ -404,7 +404,7 @@ _OutputIterator transform_inclusive_scan(_InputIterator __first, _InputIterator *__result++ = __init; if (++__first != __last) return _VSTD::transform_inclusive_scan(__first, __last, __result, __b, __u, __init); - } + } return __result; } @@ -467,9 +467,9 @@ struct __ct_abs<_Result, _Source, true> { _LIBCPP_CONSTEXPR _LIBCPP_INLINE_VISIBILITY _Result operator()(_Source __t) const noexcept { - if (__t >= 0) return __t; - if (__t == numeric_limits<_Source>::min()) return -static_cast<_Result>(__t); - return -__t; + if (__t >= 0) return __t; + if (__t == numeric_limits<_Source>::min()) return -static_cast<_Result>(__t); + return -__t; } }; diff --git a/libcxx/include/regex b/libcxx/include/regex index e4868af92f5fe..028831d72e0b7 100644 --- a/libcxx/include/regex +++ b/libcxx/include/regex @@ -2574,12 +2574,12 @@ public: _LIBCPP_INLINE_VISIBILITY basic_regex() : __flags_(regex_constants::ECMAScript), __marked_count_(0), __loop_count_(0), __open_count_(0), - __end_(0) + __end_(nullptr) {} _LIBCPP_INLINE_VISIBILITY explicit basic_regex(const value_type* __p, flag_type __f = regex_constants::ECMAScript) : __flags_(__f), __marked_count_(0), __loop_count_(0), __open_count_(0), - __end_(0) + __end_(nullptr) { __init(__p, __p + __traits_.length(__p)); } @@ -2587,7 +2587,7 @@ public: _LIBCPP_INLINE_VISIBILITY basic_regex(const value_type* __p, size_t __len, flag_type __f = regex_constants::ECMAScript) : __flags_(__f), __marked_count_(0), __loop_count_(0), __open_count_(0), - __end_(0) + __end_(nullptr) { __init(__p, __p + __len); } @@ -2599,7 +2599,7 @@ public: explicit basic_regex(const basic_string& __p, flag_type __f = regex_constants::ECMAScript) : __flags_(__f), __marked_count_(0), __loop_count_(0), __open_count_(0), - __end_(0) + __end_(nullptr) { __init(__p.begin(), __p.end()); } @@ -2609,7 +2609,7 @@ public: basic_regex(_ForwardIterator __first, _ForwardIterator __last, flag_type __f = regex_constants::ECMAScript) : __flags_(__f), __marked_count_(0), __loop_count_(0), __open_count_(0), - __end_(0) + __end_(nullptr) { __init(__first, __last); } @@ -2618,7 +2618,7 @@ public: basic_regex(initializer_list __il, flag_type __f = regex_constants::ECMAScript) : __flags_(__f), __marked_count_(0), __loop_count_(0), __open_count_(0), - __end_(0) + __end_(nullptr) { __init(__il.begin(), __il.end()); } diff --git a/libcxx/include/sstream b/libcxx/include/sstream index 1439d9c4ab9c9..22cc0c3503844 100644 --- a/libcxx/include/sstream +++ b/libcxx/include/sstream @@ -210,13 +210,13 @@ public: // 27.8.1.1 Constructors: _LIBCPP_INLINE_VISIBILITY explicit basic_stringbuf(ios_base::openmode __wch = ios_base::in | ios_base::out) - : __hm_(0), __mode_(__wch) + : __hm_(nullptr), __mode_(__wch) { } _LIBCPP_INLINE_VISIBILITY explicit basic_stringbuf(const string_type& __s, ios_base::openmode __wch = ios_base::in | ios_base::out) - : __str_(__s.get_allocator()), __hm_(0), __mode_(__wch) + : __str_(__s.get_allocator()), __hm_(nullptr), __mode_(__wch) { str(__s); } @@ -440,7 +440,7 @@ void basic_stringbuf<_CharT, _Traits, _Allocator>::str(const string_type& __s) { __str_ = __s; - __hm_ = 0; + __hm_ = nullptr; if (__mode_ & ios_base::in) { __hm_ = const_cast(__str_.data()) + __str_.size(); @@ -587,9 +587,9 @@ basic_stringbuf<_CharT, _Traits, _Allocator>::seekoff(off_type __off, return pos_type(-1); if (__noff != 0) { - if ((__wch & ios_base::in) && this->gptr() == 0) + if ((__wch & ios_base::in) && this->gptr() == nullptr) return pos_type(-1); - if ((__wch & ios_base::out) && this->pptr() == 0) + if ((__wch & ios_base::out) && this->pptr() == nullptr) return pos_type(-1); } if (__wch & ios_base::in) diff --git a/libcxx/include/streambuf b/libcxx/include/streambuf index 193b7e5ae8a61..0dfa31449b908 100644 --- a/libcxx/include/streambuf +++ b/libcxx/include/streambuf @@ -308,12 +308,12 @@ basic_streambuf<_CharT, _Traits>::~basic_streambuf() template basic_streambuf<_CharT, _Traits>::basic_streambuf() - : __binp_(0), - __ninp_(0), - __einp_(0), - __bout_(0), - __nout_(0), - __eout_(0) + : __binp_(nullptr), + __ninp_(nullptr), + __einp_(nullptr), + __bout_(nullptr), + __nout_(nullptr), + __eout_(nullptr) { } diff --git a/libcxx/include/string b/libcxx/include/string index c900d9609ed40..1f3f444727fd7 100644 --- a/libcxx/include/string +++ b/libcxx/include/string @@ -153,7 +153,8 @@ public: void resize(size_type n, value_type c); void resize(size_type n); - void reserve(size_type res_arg = 0); + void reserve(size_type res_arg); + void reserve(); // deprecated in C++20 void shrink_to_fit(); void clear() noexcept; bool empty() const noexcept; @@ -448,15 +449,15 @@ typedef basic_string wstring; typedef basic_string u16string; typedef basic_string u32string; -int stoi (const string& str, size_t* idx = 0, int base = 10); -long stol (const string& str, size_t* idx = 0, int base = 10); -unsigned long stoul (const string& str, size_t* idx = 0, int base = 10); -long long stoll (const string& str, size_t* idx = 0, int base = 10); -unsigned long long stoull(const string& str, size_t* idx = 0, int base = 10); +int stoi (const string& str, size_t* idx = nullptr, int base = 10); +long stol (const string& str, size_t* idx = nullptr, int base = 10); +unsigned long stoul (const string& str, size_t* idx = nullptr, int base = 10); +long long stoll (const string& str, size_t* idx = nullptr, int base = 10); +unsigned long long stoull(const string& str, size_t* idx = nullptr, int base = 10); -float stof (const string& str, size_t* idx = 0); -double stod (const string& str, size_t* idx = 0); -long double stold(const string& str, size_t* idx = 0); +float stof (const string& str, size_t* idx = nullptr); +double stod (const string& str, size_t* idx = nullptr); +long double stold(const string& str, size_t* idx = nullptr); string to_string(int val); string to_string(unsigned val); @@ -468,15 +469,15 @@ string to_string(float val); string to_string(double val); string to_string(long double val); -int stoi (const wstring& str, size_t* idx = 0, int base = 10); -long stol (const wstring& str, size_t* idx = 0, int base = 10); -unsigned long stoul (const wstring& str, size_t* idx = 0, int base = 10); -long long stoll (const wstring& str, size_t* idx = 0, int base = 10); -unsigned long long stoull(const wstring& str, size_t* idx = 0, int base = 10); +int stoi (const wstring& str, size_t* idx = nullptr, int base = 10); +long stol (const wstring& str, size_t* idx = nullptr, int base = 10); +unsigned long stoul (const wstring& str, size_t* idx = nullptr, int base = 10); +long long stoll (const wstring& str, size_t* idx = nullptr, int base = 10); +unsigned long long stoull(const wstring& str, size_t* idx = nullptr, int base = 10); -float stof (const wstring& str, size_t* idx = 0); -double stod (const wstring& str, size_t* idx = 0); -long double stold(const wstring& str, size_t* idx = 0); +float stof (const wstring& str, size_t* idx = nullptr); +double stod (const wstring& str, size_t* idx = nullptr); +long double stold(const wstring& str, size_t* idx = nullptr); wstring to_wstring(int val); wstring to_wstring(unsigned val); @@ -954,13 +955,13 @@ public: void resize(size_type __n, value_type __c); _LIBCPP_INLINE_VISIBILITY void resize(size_type __n) {resize(__n, value_type());} - void reserve(size_type __res_arg); + void reserve(size_type __requested_capacity); _LIBCPP_INLINE_VISIBILITY void __resize_default_init(size_type __n); + _LIBCPP_DEPRECATED_IN_CXX20 _LIBCPP_INLINE_VISIBILITY + void reserve() _NOEXCEPT {shrink_to_fit();} _LIBCPP_INLINE_VISIBILITY - void reserve() _NOEXCEPT {reserve(0);} - _LIBCPP_INLINE_VISIBILITY - void shrink_to_fit() _NOEXCEPT {reserve();} + void shrink_to_fit() _NOEXCEPT; _LIBCPP_INLINE_VISIBILITY void clear() _NOEXCEPT; _LIBCPP_NODISCARD_AFTER_CXX17 _LIBCPP_INLINE_VISIBILITY @@ -1418,6 +1419,8 @@ public: _LIBCPP_INLINE_VISIBILITY void __clear_and_shrink() _NOEXCEPT; + _LIBCPP_INLINE_VISIBILITY void __shrink_or_extend(size_type __target_capacity); + _LIBCPP_INLINE_VISIBILITY bool __is_long() const _NOEXCEPT {return bool(__r_.first().__s.__size_ & __short_mask);} @@ -3262,65 +3265,88 @@ basic_string<_CharT, _Traits, _Allocator>::max_size() const _NOEXCEPT template void -basic_string<_CharT, _Traits, _Allocator>::reserve(size_type __res_arg) +basic_string<_CharT, _Traits, _Allocator>::reserve(size_type __requested_capacity) { - if (__res_arg > max_size()) + if (__requested_capacity > max_size()) this->__throw_length_error(); + +#if _LIBCPP_STD_VER > 17 + // Reserve never shrinks as of C++20. + if (__requested_capacity <= capacity()) return; +#endif + + size_type __target_capacity = _VSTD::max(__requested_capacity, size()); + __target_capacity = __recommend(__target_capacity); + if (__target_capacity == capacity()) return; + + __shrink_or_extend(__target_capacity); +} + +template +void +basic_string<_CharT, _Traits, _Allocator>::shrink_to_fit() _NOEXCEPT +{ + size_type __target_capacity = __recommend(size()); + if (__target_capacity == capacity()) return; + + __shrink_or_extend(__target_capacity); +} + +template +void +basic_string<_CharT, _Traits, _Allocator>::__shrink_or_extend(size_type __target_capacity) +{ size_type __cap = capacity(); size_type __sz = size(); - __res_arg = _VSTD::max(__res_arg, __sz); - __res_arg = __recommend(__res_arg); - if (__res_arg != __cap) + + pointer __new_data, __p; + bool __was_long, __now_long; + if (__target_capacity == __min_cap - 1) { - pointer __new_data, __p; - bool __was_long, __now_long; - if (__res_arg == __min_cap - 1) - { - __was_long = true; - __now_long = false; - __new_data = __get_short_pointer(); - __p = __get_long_pointer(); - } + __was_long = true; + __now_long = false; + __new_data = __get_short_pointer(); + __p = __get_long_pointer(); + } + else + { + if (__target_capacity > __cap) + __new_data = __alloc_traits::allocate(__alloc(), __target_capacity+1); else { - if (__res_arg > __cap) - __new_data = __alloc_traits::allocate(__alloc(), __res_arg+1); - else + #ifndef _LIBCPP_NO_EXCEPTIONS + try { - #ifndef _LIBCPP_NO_EXCEPTIONS - try - { - #endif // _LIBCPP_NO_EXCEPTIONS - __new_data = __alloc_traits::allocate(__alloc(), __res_arg+1); - #ifndef _LIBCPP_NO_EXCEPTIONS - } - catch (...) - { - return; - } - #else // _LIBCPP_NO_EXCEPTIONS - if (__new_data == nullptr) - return; - #endif // _LIBCPP_NO_EXCEPTIONS + #endif // _LIBCPP_NO_EXCEPTIONS + __new_data = __alloc_traits::allocate(__alloc(), __target_capacity+1); + #ifndef _LIBCPP_NO_EXCEPTIONS } - __now_long = true; - __was_long = __is_long(); - __p = __get_pointer(); - } - traits_type::copy(_VSTD::__to_address(__new_data), - _VSTD::__to_address(__p), size()+1); - if (__was_long) - __alloc_traits::deallocate(__alloc(), __p, __cap+1); - if (__now_long) - { - __set_long_cap(__res_arg+1); - __set_long_size(__sz); - __set_long_pointer(__new_data); + catch (...) + { + return; + } + #else // _LIBCPP_NO_EXCEPTIONS + if (__new_data == nullptr) + return; + #endif // _LIBCPP_NO_EXCEPTIONS } - else - __set_short_size(__sz); - __invalidate_all_iterators(); + __now_long = true; + __was_long = __is_long(); + __p = __get_pointer(); + } + traits_type::copy(_VSTD::__to_address(__new_data), + _VSTD::__to_address(__p), size()+1); + if (__was_long) + __alloc_traits::deallocate(__alloc(), __p, __cap+1); + if (__now_long) + { + __set_long_cap(__target_capacity+1); + __set_long_size(__sz); + __set_long_pointer(__new_data); } + else + __set_short_size(__sz); + __invalidate_all_iterators(); } template @@ -3438,7 +3464,7 @@ basic_string<_CharT, _Traits, _Allocator>::swap(basic_string& __str) __alloc_traits::is_always_equal::value || __alloc() == __str.__alloc(), "swapping non-equal allocators"); _VSTD::swap(__r_.first(), __str.__r_.first()); - __swap_allocator(__alloc(), __str.__alloc()); + _VSTD::__swap_allocator(__alloc(), __str.__alloc()); } // find @@ -3939,7 +3965,7 @@ basic_string<_CharT, _Traits, _Allocator>::__invariants() const return false; if (capacity() < __min_cap - 1) return false; - if (data() == 0) + if (data() == nullptr) return false; if (data()[size()] != value_type()) return false; @@ -4310,15 +4336,15 @@ typedef basic_string u16string; typedef basic_string u32string; #endif // _LIBCPP_HAS_NO_UNICODE_CHARS -_LIBCPP_FUNC_VIS int stoi (const string& __str, size_t* __idx = 0, int __base = 10); -_LIBCPP_FUNC_VIS long stol (const string& __str, size_t* __idx = 0, int __base = 10); -_LIBCPP_FUNC_VIS unsigned long stoul (const string& __str, size_t* __idx = 0, int __base = 10); -_LIBCPP_FUNC_VIS long long stoll (const string& __str, size_t* __idx = 0, int __base = 10); -_LIBCPP_FUNC_VIS unsigned long long stoull(const string& __str, size_t* __idx = 0, int __base = 10); +_LIBCPP_FUNC_VIS int stoi (const string& __str, size_t* __idx = nullptr, int __base = 10); +_LIBCPP_FUNC_VIS long stol (const string& __str, size_t* __idx = nullptr, int __base = 10); +_LIBCPP_FUNC_VIS unsigned long stoul (const string& __str, size_t* __idx = nullptr, int __base = 10); +_LIBCPP_FUNC_VIS long long stoll (const string& __str, size_t* __idx = nullptr, int __base = 10); +_LIBCPP_FUNC_VIS unsigned long long stoull(const string& __str, size_t* __idx = nullptr, int __base = 10); -_LIBCPP_FUNC_VIS float stof (const string& __str, size_t* __idx = 0); -_LIBCPP_FUNC_VIS double stod (const string& __str, size_t* __idx = 0); -_LIBCPP_FUNC_VIS long double stold(const string& __str, size_t* __idx = 0); +_LIBCPP_FUNC_VIS float stof (const string& __str, size_t* __idx = nullptr); +_LIBCPP_FUNC_VIS double stod (const string& __str, size_t* __idx = nullptr); +_LIBCPP_FUNC_VIS long double stold(const string& __str, size_t* __idx = nullptr); _LIBCPP_FUNC_VIS string to_string(int __val); _LIBCPP_FUNC_VIS string to_string(unsigned __val); @@ -4330,15 +4356,15 @@ _LIBCPP_FUNC_VIS string to_string(float __val); _LIBCPP_FUNC_VIS string to_string(double __val); _LIBCPP_FUNC_VIS string to_string(long double __val); -_LIBCPP_FUNC_VIS int stoi (const wstring& __str, size_t* __idx = 0, int __base = 10); -_LIBCPP_FUNC_VIS long stol (const wstring& __str, size_t* __idx = 0, int __base = 10); -_LIBCPP_FUNC_VIS unsigned long stoul (const wstring& __str, size_t* __idx = 0, int __base = 10); -_LIBCPP_FUNC_VIS long long stoll (const wstring& __str, size_t* __idx = 0, int __base = 10); -_LIBCPP_FUNC_VIS unsigned long long stoull(const wstring& __str, size_t* __idx = 0, int __base = 10); +_LIBCPP_FUNC_VIS int stoi (const wstring& __str, size_t* __idx = nullptr, int __base = 10); +_LIBCPP_FUNC_VIS long stol (const wstring& __str, size_t* __idx = nullptr, int __base = 10); +_LIBCPP_FUNC_VIS unsigned long stoul (const wstring& __str, size_t* __idx = nullptr, int __base = 10); +_LIBCPP_FUNC_VIS long long stoll (const wstring& __str, size_t* __idx = nullptr, int __base = 10); +_LIBCPP_FUNC_VIS unsigned long long stoull(const wstring& __str, size_t* __idx = nullptr, int __base = 10); -_LIBCPP_FUNC_VIS float stof (const wstring& __str, size_t* __idx = 0); -_LIBCPP_FUNC_VIS double stod (const wstring& __str, size_t* __idx = 0); -_LIBCPP_FUNC_VIS long double stold(const wstring& __str, size_t* __idx = 0); +_LIBCPP_FUNC_VIS float stof (const wstring& __str, size_t* __idx = nullptr); +_LIBCPP_FUNC_VIS double stod (const wstring& __str, size_t* __idx = nullptr); +_LIBCPP_FUNC_VIS long double stold(const wstring& __str, size_t* __idx = nullptr); _LIBCPP_FUNC_VIS wstring to_wstring(int __val); _LIBCPP_FUNC_VIS wstring to_wstring(unsigned __val); diff --git a/libcxx/include/strstream b/libcxx/include/strstream index 31999bbae14b2..6b893eebd00bc 100644 --- a/libcxx/include/strstream +++ b/libcxx/include/strstream @@ -19,12 +19,12 @@ class strstreambuf public: explicit strstreambuf(streamsize alsize_arg = 0); strstreambuf(void* (*palloc_arg)(size_t), void (*pfree_arg)(void*)); - strstreambuf(char* gnext_arg, streamsize n, char* pbeg_arg = 0); + strstreambuf(char* gnext_arg, streamsize n, char* pbeg_arg = nullptr); strstreambuf(const char* gnext_arg, streamsize n); - strstreambuf(signed char* gnext_arg, streamsize n, signed char* pbeg_arg = 0); + strstreambuf(signed char* gnext_arg, streamsize n, signed char* pbeg_arg = nullptr); strstreambuf(const signed char* gnext_arg, streamsize n); - strstreambuf(unsigned char* gnext_arg, streamsize n, unsigned char* pbeg_arg = 0); + strstreambuf(unsigned char* gnext_arg, streamsize n, unsigned char* pbeg_arg = nullptr); strstreambuf(const unsigned char* gnext_arg, streamsize n); strstreambuf(strstreambuf&& rhs); @@ -142,12 +142,12 @@ class _LIBCPP_TYPE_VIS strstreambuf public: explicit strstreambuf(streamsize __alsize = 0); strstreambuf(void* (*__palloc)(size_t), void (*__pfree)(void*)); - strstreambuf(char* __gnext, streamsize __n, char* __pbeg = 0); + strstreambuf(char* __gnext, streamsize __n, char* __pbeg = nullptr); strstreambuf(const char* __gnext, streamsize __n); - strstreambuf(signed char* __gnext, streamsize __n, signed char* __pbeg = 0); + strstreambuf(signed char* __gnext, streamsize __n, signed char* __pbeg = nullptr); strstreambuf(const signed char* __gnext, streamsize __n); - strstreambuf(unsigned char* __gnext, streamsize __n, unsigned char* __pbeg = 0); + strstreambuf(unsigned char* __gnext, streamsize __n, unsigned char* __pbeg = nullptr); strstreambuf(const unsigned char* __gnext, streamsize __n); #ifndef _LIBCPP_CXX03_LANG diff --git a/libcxx/include/system_error b/libcxx/include/system_error index 74e889aa9ac74..b714e1d4263d1 100644 --- a/libcxx/include/system_error +++ b/libcxx/include/system_error @@ -253,7 +253,7 @@ public: template _LIBCPP_INLINE_VISIBILITY error_condition(_Ep __e, - typename enable_if::value>::type* = 0 + typename enable_if::value>::type* = nullptr ) _NOEXCEPT {*this = make_error_condition(__e);} @@ -325,7 +325,7 @@ public: template _LIBCPP_INLINE_VISIBILITY error_code(_Ep __e, - typename enable_if::value>::type* = 0 + typename enable_if::value>::type* = nullptr ) _NOEXCEPT {*this = make_error_code(__e);} diff --git a/libcxx/include/valarray b/libcxx/include/valarray index 4bbd5ed323af9..aaae6fbd5b3fb 100644 --- a/libcxx/include/valarray +++ b/libcxx/include/valarray @@ -802,7 +802,7 @@ private: public: // construct/destroy: _LIBCPP_INLINE_VISIBILITY - valarray() : __begin_(0), __end_(0) {} + valarray() : __begin_(nullptr), __end_(nullptr) {} inline _LIBCPP_HIDE_FROM_ABI_AFTER_V1 explicit valarray(size_t __n); _LIBCPP_INLINE_VISIBILITY @@ -2750,8 +2750,8 @@ __val_expr<_ValExpr>::operator valarray<__val_expr::result_type>() const template inline valarray<_Tp>::valarray(size_t __n) - : __begin_(0), - __end_(0) + : __begin_(nullptr), + __end_(nullptr) { if (__n) { @@ -2776,16 +2776,16 @@ valarray<_Tp>::valarray(size_t __n) template inline valarray<_Tp>::valarray(const value_type& __x, size_t __n) - : __begin_(0), - __end_(0) + : __begin_(nullptr), + __end_(nullptr) { resize(__n, __x); } template valarray<_Tp>::valarray(const value_type* __p, size_t __n) - : __begin_(0), - __end_(0) + : __begin_(nullptr), + __end_(nullptr) { if (__n) { @@ -2809,8 +2809,8 @@ valarray<_Tp>::valarray(const value_type* __p, size_t __n) template valarray<_Tp>::valarray(const valarray& __v) - : __begin_(0), - __end_(0) + : __begin_(nullptr), + __end_(nullptr) { if (__v.size()) { @@ -2845,8 +2845,8 @@ valarray<_Tp>::valarray(valarray&& __v) _NOEXCEPT template valarray<_Tp>::valarray(initializer_list __il) - : __begin_(0), - __end_(0) + : __begin_(nullptr), + __end_(nullptr) { const size_t __n = __il.size(); if (__n) @@ -2874,8 +2874,8 @@ valarray<_Tp>::valarray(initializer_list __il) template valarray<_Tp>::valarray(const slice_array& __sa) - : __begin_(0), - __end_(0) + : __begin_(nullptr), + __end_(nullptr) { const size_t __n = __sa.__size_; if (__n) @@ -2901,8 +2901,8 @@ valarray<_Tp>::valarray(const slice_array& __sa) template valarray<_Tp>::valarray(const gslice_array& __ga) - : __begin_(0), - __end_(0) + : __begin_(nullptr), + __end_(nullptr) { const size_t __n = __ga.__1d_.size(); if (__n) @@ -2930,8 +2930,8 @@ valarray<_Tp>::valarray(const gslice_array& __ga) template valarray<_Tp>::valarray(const mask_array& __ma) - : __begin_(0), - __end_(0) + : __begin_(nullptr), + __end_(nullptr) { const size_t __n = __ma.__1d_.size(); if (__n) @@ -2959,8 +2959,8 @@ valarray<_Tp>::valarray(const mask_array& __ma) template valarray<_Tp>::valarray(const indirect_array& __ia) - : __begin_(0), - __end_(0) + : __begin_(nullptr), + __end_(nullptr) { const size_t __n = __ia.__1d_.size(); if (__n) diff --git a/libcxx/include/variant b/libcxx/include/variant index cb92a69d14d18..3621f2c68f521 100644 --- a/libcxx/include/variant +++ b/libcxx/include/variant @@ -491,7 +491,7 @@ private: template inline _LIBCPP_INLINE_VISIBILITY static constexpr decltype(auto) __dispatch(_Fp __f, _Vs... __vs) { - return __invoke_constexpr( + return _VSTD::__invoke_constexpr( static_cast<_Fp>(__f), __access::__base::__get_alt<_Is>(static_cast<_Vs>(__vs))...); } @@ -599,7 +599,7 @@ private: __std_visit_exhaustive_visitor_check< _Visitor, decltype((_VSTD::forward<_Alts>(__alts).__value))...>(); - return __invoke_constexpr(_VSTD::forward<_Visitor>(__visitor), + return _VSTD::__invoke_constexpr(_VSTD::forward<_Visitor>(__visitor), _VSTD::forward<_Alts>(__alts).__value...); } _Visitor&& __visitor; diff --git a/libcxx/include/vector b/libcxx/include/vector index f425774413c72..bc83656db12ac 100644 --- a/libcxx/include/vector +++ b/libcxx/include/vector @@ -951,7 +951,7 @@ vector<_Tp, _Allocator>::__swap_out_circular_buffer(__split_buffer__alloc(), this->__begin_, this->__end_, __v.__begin_); + _VSTD::__construct_backward_with_exception_guarantees(this->__alloc(), this->__begin_, this->__end_, __v.__begin_); _VSTD::swap(this->__begin_, __v.__begin_); _VSTD::swap(this->__end_, __v.__end_); _VSTD::swap(this->__end_cap(), __v.__end_cap()); @@ -966,8 +966,8 @@ vector<_Tp, _Allocator>::__swap_out_circular_buffer(__split_buffer__alloc(), this->__begin_, __p, __v.__begin_); - __construct_forward_with_exception_guarantees(this->__alloc(), __p, this->__end_, __v.__end_); + _VSTD::__construct_backward_with_exception_guarantees(this->__alloc(), this->__begin_, __p, __v.__begin_); + _VSTD::__construct_forward_with_exception_guarantees(this->__alloc(), __p, this->__end_, __v.__end_); _VSTD::swap(this->__begin_, __v.__begin_); _VSTD::swap(this->__end_, __v.__end_); _VSTD::swap(this->__end_cap(), __v.__end_cap()); @@ -1074,7 +1074,7 @@ typename enable_if vector<_Tp, _Allocator>::__construct_at_end(_ForwardIterator __first, _ForwardIterator __last, size_type __n) { _ConstructTransaction __tx(*this, __n); - __construct_range_forward(this->__alloc(), __first, __last, __tx.__pos_); + _VSTD::__construct_range_forward(this->__alloc(), __first, __last, __tx.__pos_); } // Default constructs __n objects starting at __end_ @@ -2054,7 +2054,7 @@ vector<_Tp, _Allocator>::swap(vector& __x) _VSTD::swap(this->__begin_, __x.__begin_); _VSTD::swap(this->__end_, __x.__end_); _VSTD::swap(this->__end_cap(), __x.__end_cap()); - __swap_allocator(this->__alloc(), __x.__alloc(), + _VSTD::__swap_allocator(this->__alloc(), __x.__alloc(), integral_constant()); #if _LIBCPP_DEBUG_LEVEL == 2 __get_db()->swap(this, &__x); @@ -3232,7 +3232,7 @@ vector::swap(vector& __x) _VSTD::swap(this->__begin_, __x.__begin_); _VSTD::swap(this->__size_, __x.__size_); _VSTD::swap(this->__cap(), __x.__cap()); - __swap_allocator(this->__alloc(), __x.__alloc(), + _VSTD::__swap_allocator(this->__alloc(), __x.__alloc(), integral_constant()); } diff --git a/libcxx/include/version b/libcxx/include/version index 1f05f3a851ccf..58f676548fe7a 100644 --- a/libcxx/include/version +++ b/libcxx/include/version @@ -66,6 +66,7 @@ __cpp_lib_hardware_interference_size 201703L __cpp_lib_has_unique_object_representations 201606L __cpp_lib_hypot 201603L __cpp_lib_incomplete_container_elements 201505L +__cpp_lib_int_pow2 202002L __cpp_lib_integer_sequence 201304L __cpp_lib_integral_constant_callable 201304L __cpp_lib_interpolate 201902L @@ -261,6 +262,7 @@ __cpp_lib_void_t 201411L # define __cpp_lib_endian 201907L # define __cpp_lib_erase_if 202002L # define __cpp_lib_generic_unordered_lookup 201811L +# define __cpp_lib_int_pow2 202002L # define __cpp_lib_interpolate 201902L # if !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) # define __cpp_lib_is_constant_evaluated 201811L diff --git a/libcxx/lib/abi/3.9/x86_64-apple-darwin16.abilist b/libcxx/lib/abi/3.9/x86_64-apple-darwin16.abilist deleted file mode 100644 index ea361e9fc44b3..0000000000000 --- a/libcxx/lib/abi/3.9/x86_64-apple-darwin16.abilist +++ /dev/null @@ -1,2448 +0,0 @@ -{'type': 'U', 'name': '__DefaultRuneLocale'} -{'type': 'U', 'name': '__Unwind_Resume'} -{'type': 'I', 'name': '__ZNKSt10bad_typeid4whatEv'} -{'type': 'U', 'name': '__ZNKSt10bad_typeid4whatEv'} -{'type': 'I', 'name': '__ZNKSt11logic_error4whatEv'} -{'type': 'U', 'name': '__ZNKSt11logic_error4whatEv'} -{'type': 'FUNC', 'name': '__ZNKSt12experimental15fundamentals_v112bad_any_cast4whatEv'} -{'type': 'I', 'name': '__ZNKSt13bad_exception4whatEv'} -{'type': 'U', 'name': '__ZNKSt13bad_exception4whatEv'} -{'type': 'I', 'name': '__ZNKSt13runtime_error4whatEv'} -{'type': 'U', 'name': '__ZNKSt13runtime_error4whatEv'} -{'type': 'I', 'name': '__ZNKSt16bad_array_length4whatEv'} -{'type': 'U', 'name': '__ZNKSt16bad_array_length4whatEv'} -{'type': 'FUNC', 'name': '__ZNKSt16nested_exception14rethrow_nestedEv'} -{'type': 'I', 'name': '__ZNKSt20bad_array_new_length4whatEv'} -{'type': 'U', 'name': '__ZNKSt20bad_array_new_length4whatEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110__time_put8__do_putEPcRS1_PK2tmcc'} -{'type': 'FUNC', 'name': '__ZNKSt3__110__time_put8__do_putEPwRS1_PK2tmcc'} -{'type': 'FUNC', 'name': '__ZNKSt3__110error_code7messageEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb0EE11do_groupingEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb0EE13do_neg_formatEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb0EE13do_pos_formatEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb0EE14do_curr_symbolEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb0EE14do_frac_digitsEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb0EE16do_decimal_pointEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb0EE16do_negative_signEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb0EE16do_positive_signEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb0EE16do_thousands_sepEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb1EE11do_groupingEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb1EE13do_neg_formatEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb1EE13do_pos_formatEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb1EE14do_curr_symbolEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb1EE14do_frac_digitsEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb1EE16do_decimal_pointEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb1EE16do_negative_signEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb1EE16do_positive_signEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIcLb1EE16do_thousands_sepEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb0EE11do_groupingEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb0EE13do_neg_formatEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb0EE13do_pos_formatEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb0EE14do_curr_symbolEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb0EE14do_frac_digitsEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb0EE16do_decimal_pointEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb0EE16do_negative_signEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb0EE16do_positive_signEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb0EE16do_thousands_sepEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb1EE11do_groupingEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb1EE13do_neg_formatEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb1EE13do_pos_formatEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb1EE14do_curr_symbolEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb1EE14do_frac_digitsEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb1EE16do_decimal_pointEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb1EE16do_negative_signEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb1EE16do_positive_signEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__110moneypunctIwLb1EE16do_thousands_sepEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__111__libcpp_db15__decrementableEPKv'} -{'type': 'FUNC', 'name': '__ZNKSt3__111__libcpp_db15__find_c_from_iEPv'} -{'type': 'FUNC', 'name': '__ZNKSt3__111__libcpp_db15__subscriptableEPKvl'} -{'type': 'FUNC', 'name': '__ZNKSt3__111__libcpp_db17__dereferenceableEPKv'} -{'type': 'FUNC', 'name': '__ZNKSt3__111__libcpp_db17__find_c_and_lockEPv'} -{'type': 'FUNC', 'name': '__ZNKSt3__111__libcpp_db22__less_than_comparableEPKvS2_'} -{'type': 'FUNC', 'name': '__ZNKSt3__111__libcpp_db6unlockEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__111__libcpp_db8__find_cEPv'} -{'type': 'FUNC', 'name': '__ZNKSt3__111__libcpp_db9__addableEPKvl'} -{'type': 'FUNC', 'name': '__ZNKSt3__112bad_weak_ptr4whatEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE12find_last_ofEPKcmm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE13find_first_ofEPKcmm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE16find_last_not_ofEPKcmm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE17find_first_not_ofEPKcmm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE2atEm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4copyEPcmm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4findEPKcmm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE4findEcm'} -{'type': 'FUNC', 'name': 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'__ZNKSt3__112basic_stringIwNS_11char_traitsIwEENS_9allocatorIwEEE17find_first_not_ofEPKwmm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIwNS_11char_traitsIwEENS_9allocatorIwEEE2atEm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIwNS_11char_traitsIwEENS_9allocatorIwEEE4copyEPwmm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIwNS_11char_traitsIwEENS_9allocatorIwEEE4findEPKwmm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIwNS_11char_traitsIwEENS_9allocatorIwEEE4findEwm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIwNS_11char_traitsIwEENS_9allocatorIwEEE5rfindEPKwmm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIwNS_11char_traitsIwEENS_9allocatorIwEEE5rfindEwm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIwNS_11char_traitsIwEENS_9allocatorIwEEE7compareEPKw'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIwNS_11char_traitsIwEENS_9allocatorIwEEE7compareEmmPKw'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIwNS_11char_traitsIwEENS_9allocatorIwEEE7compareEmmPKwm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112basic_stringIwNS_11char_traitsIwEENS_9allocatorIwEEE7compareEmmRKS5_mm'} -{'type': 'FUNC', 'name': '__ZNKSt3__112ctype_bynameIcE10do_tolowerEPcPKc'} -{'type': 'FUNC', 'name': '__ZNKSt3__112ctype_bynameIcE10do_tolowerEc'} -{'type': 'FUNC', 'name': '__ZNKSt3__112ctype_bynameIcE10do_toupperEPcPKc'} -{'type': 'FUNC', 'name': '__ZNKSt3__112ctype_bynameIcE10do_toupperEc'} -{'type': 'FUNC', 'name': '__ZNKSt3__112ctype_bynameIwE10do_scan_isEjPKwS3_'} -{'type': 'FUNC', 'name': '__ZNKSt3__112ctype_bynameIwE10do_tolowerEPwPKw'} -{'type': 'FUNC', 'name': '__ZNKSt3__112ctype_bynameIwE10do_tolowerEw'} -{'type': 'FUNC', 'name': '__ZNKSt3__112ctype_bynameIwE10do_toupperEPwPKw'} -{'type': 'FUNC', 'name': '__ZNKSt3__112ctype_bynameIwE10do_toupperEw'} -{'type': 'FUNC', 'name': '__ZNKSt3__112ctype_bynameIwE11do_scan_notEjPKwS3_'} -{'type': 'FUNC', 'name': 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-{'type': 'FUNC', 'name': '__ZNKSt3__17num_putIcNS_19ostreambuf_iteratorIcNS_11char_traitsIcEEEEE6do_putES4_RNS_8ios_baseEcy'} -{'type': 'FUNC', 'name': '__ZNKSt3__17num_putIwNS_19ostreambuf_iteratorIwNS_11char_traitsIwEEEEE6do_putES4_RNS_8ios_baseEwPKv'} -{'type': 'FUNC', 'name': '__ZNKSt3__17num_putIwNS_19ostreambuf_iteratorIwNS_11char_traitsIwEEEEE6do_putES4_RNS_8ios_baseEwb'} -{'type': 'FUNC', 'name': '__ZNKSt3__17num_putIwNS_19ostreambuf_iteratorIwNS_11char_traitsIwEEEEE6do_putES4_RNS_8ios_baseEwd'} -{'type': 'FUNC', 'name': '__ZNKSt3__17num_putIwNS_19ostreambuf_iteratorIwNS_11char_traitsIwEEEEE6do_putES4_RNS_8ios_baseEwe'} -{'type': 'FUNC', 'name': '__ZNKSt3__17num_putIwNS_19ostreambuf_iteratorIwNS_11char_traitsIwEEEEE6do_putES4_RNS_8ios_baseEwl'} -{'type': 'FUNC', 'name': '__ZNKSt3__17num_putIwNS_19ostreambuf_iteratorIwNS_11char_traitsIwEEEEE6do_putES4_RNS_8ios_baseEwm'} -{'type': 'FUNC', 'name': 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-{'type': 'FUNC', 'name': '__ZNKSt3__18numpunctIcE11do_truenameEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__18numpunctIcE12do_falsenameEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__18numpunctIcE16do_decimal_pointEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__18numpunctIcE16do_thousands_sepEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__18numpunctIwE11do_groupingEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__18numpunctIwE11do_truenameEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__18numpunctIwE12do_falsenameEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__18numpunctIwE16do_decimal_pointEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__18numpunctIwE16do_thousands_sepEv'} -{'type': 'FUNC', 'name': '__ZNKSt3__18time_getIcNS_19istreambuf_iteratorIcNS_11char_traitsIcEEEEE10__get_hourERiRS4_S4_RjRKNS_5ctypeIcEE'} -{'type': 'FUNC', 'name': '__ZNKSt3__18time_getIcNS_19istreambuf_iteratorIcNS_11char_traitsIcEEEEE10__get_yearERiRS4_S4_RjRKNS_5ctypeIcEE'} -{'type': 'FUNC', 'name': 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'FUNC', 'name': '__ZNKSt3__18time_getIwNS_19istreambuf_iteratorIwNS_11char_traitsIwEEEEE6do_getES4_S4_RNS_8ios_baseERjP2tmcc'} -{'type': 'FUNC', 'name': '__ZNKSt3__18time_getIwNS_19istreambuf_iteratorIwNS_11char_traitsIwEEEEE9__get_dayERiRS4_S4_RjRKNS_5ctypeIwEE'} -{'type': 'FUNC', 'name': '__ZNKSt3__18time_putIcNS_19ostreambuf_iteratorIcNS_11char_traitsIcEEEEE3putES4_RNS_8ios_baseEcPK2tmPKcSC_'} -{'type': 'FUNC', 'name': '__ZNKSt3__18time_putIcNS_19ostreambuf_iteratorIcNS_11char_traitsIcEEEEE6do_putES4_RNS_8ios_baseEcPK2tmcc'} -{'type': 'FUNC', 'name': '__ZNKSt3__18time_putIwNS_19ostreambuf_iteratorIwNS_11char_traitsIwEEEEE3putES4_RNS_8ios_baseEwPK2tmPKwSC_'} -{'type': 'FUNC', 'name': '__ZNKSt3__18time_putIwNS_19ostreambuf_iteratorIwNS_11char_traitsIwEEEEE6do_putES4_RNS_8ios_baseEwPK2tmcc'} -{'type': 'FUNC', 'name': '__ZNKSt3__19money_getIcNS_19istreambuf_iteratorIcNS_11char_traitsIcEEEEE6do_getES4_S4_bRNS_8ios_baseERjRNS_12basic_stringIcS3_NS_9allocatorIcEEEE'} -{'type': 'FUNC', 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-{'type': 'FUNC', 'name': '_ZNKSt3__18ios_base6getlocEv'} -{'type': 'FUNC', 'name': '_ZNKSt3__18messagesIcE6do_getEliiRKNS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEE'} -{'type': 'FUNC', 'name': '_ZNKSt3__18messagesIcE7do_openERKNS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEERKNS_6localeE'} -{'type': 'FUNC', 'name': '_ZNKSt3__18messagesIcE8do_closeEl'} -{'type': 'FUNC', 'name': '_ZNKSt3__18messagesIwE6do_getEliiRKNS_12basic_stringIwNS_11char_traitsIwEENS_9allocatorIwEEEE'} -{'type': 'FUNC', 'name': '_ZNKSt3__18messagesIwE7do_openERKNS_12basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEEERKNS_6localeE'} -{'type': 'FUNC', 'name': '_ZNKSt3__18messagesIwE8do_closeEl'} -{'type': 'FUNC', 'name': '_ZNKSt3__18numpunctIcE11do_groupingEv'} -{'type': 'FUNC', 'name': '_ZNKSt3__18numpunctIcE11do_truenameEv'} -{'type': 'FUNC', 'name': '_ZNKSt3__18numpunctIcE12do_falsenameEv'} -{'type': 'FUNC', 'name': '_ZNKSt3__18numpunctIcE16do_decimal_pointEv'} -{'type': 'FUNC', 'name': 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b/libcxx/lib/abi/CHANGELOG.TXT @@ -7,8 +7,8 @@ Each entry should start with the revision number followed by a description of the change. The entry should contain a summary of the ABI changes made, including what symbols were added, removed, or changed. -To generate a summary use "sym_diff.py" diffing against the appropriate ABI list. -Afterwards the ABI list should be updated to include the new changes. +To generate a summary, re-generate the new ABI list using the +`generate-cxx-abilist` target, and look at the diff. New entries should be added directly below the "Version" header. diff --git a/libcxx/lib/abi/CMakeLists.txt b/libcxx/lib/abi/CMakeLists.txt index 98cfe8bf1e140..e25c09b7a348c 100644 --- a/libcxx/lib/abi/CMakeLists.txt +++ b/libcxx/lib/abi/CMakeLists.txt @@ -1,43 +1,75 @@ -if (DEFINED TARGET_TRIPLE) - if (TARGET_TRIPLE MATCHES "darwin") - # Ignore the major, minor, and patchlevel versions of darwin targets. - string(REGEX REPLACE "darwin[0-9]+\\.[0-9]+\\.[0-9]+" "darwin" - GENERIC_TARGET_TRIPLE "${TARGET_TRIPLE}") - elseif(TARGET_TRIPLE MATCHES "freebsd") - # Ignore the major and minor versions of freebsd targets. - string(REGEX REPLACE "freebsd[0-9]+\\.[0-9]+" "freebsd" - GENERIC_TARGET_TRIPLE "${TARGET_TRIPLE}") - else() - set(GENERIC_TARGET_TRIPLE "${TARGET_TRIPLE}") - endif() -endif() +# This function generates a "unique" identifier based on various properties +# given as arguments. The idea is to encode all ABI-affecting properties +# in that identifier, so that we can store ABI information and associate it +# to a specific ABI configuration. +# +# Right now, this is done by using the ABI identifier as the filename containing +# the list of symbols exported by libc++ for that configuration, however we could +# make it more sophisticated if the number of ABI-affecting parameters grew. +function(cxx_abi_list_identifier result triple abi_library abi_version unstable exceptions new_delete_in_libcxx) + set(abi_properties) + + if ("${triple}" MATCHES "darwin") + # Ignore the major, minor, and patchlevel versions of darwin targets. + string(REGEX REPLACE "darwin[0-9]+\\.[0-9]+\\.[0-9]+" "darwin" triple "${triple}") + elseif("${triple}" MATCHES "freebsd") + # Ignore the major and minor versions of freebsd targets. + string(REGEX REPLACE "freebsd[0-9]+\\.[0-9]+" "freebsd" triple "${triple}") + endif() + list(APPEND abi_properties "${triple}") + list(APPEND abi_properties "${abi_library}") + list(APPEND abi_properties "v${abi_version}") + if (${unstable}) + list(APPEND abi_properties "unstable") + else() + list(APPEND abi_properties "stable") + endif() + if (${exceptions}) + list(APPEND abi_properties "exceptions") + else() + list(APPEND abi_properties "noexceptions") + endif() + if (${new_delete_in_libcxx}) + list(APPEND abi_properties "new_in_libcxx") + else() + list(APPEND abi_properties "no_new_in_libcxx") + endif() + + list(JOIN abi_properties "." tmp) + set(${result} "${tmp}" PARENT_SCOPE) +endfunction() + +cxx_abi_list_identifier(abi_list_identifier + "${TARGET_TRIPLE}" + "${LIBCXX_CXX_ABI_LIBNAME}" + "${LIBCXX_ABI_VERSION}" + "${LIBCXX_ABI_UNSTABLE}" + "${LIBCXX_ENABLE_EXCEPTIONS}" + "${LIBCXX_ENABLE_NEW_DELETE_DEFINITIONS}" +) + +if (TARGET cxx_shared) + set(abi_list_file "${CMAKE_CURRENT_SOURCE_DIR}/${abi_list_identifier}.abilist") -# Detect if we are building in the same configuration used to generate -# the abilist files. -set(ABILIST_FILE "${CMAKE_CURRENT_LIST_DIR}/${GENERIC_TARGET_TRIPLE}.v${LIBCXX_ABI_VERSION}.abilist") -if (EXISTS "${ABILIST_FILE}" - AND TARGET cxx_shared - AND ("${LIBCXX_CXX_ABI_LIBNAME}" STREQUAL "libcxxabi" OR - (APPLE AND "${LIBCXX_CXX_ABI_LIBNAME}" STREQUAL "default")) - AND NOT LIBCXX_ABI_UNSTABLE - AND LIBCXX_ENABLE_EXCEPTIONS - AND NOT LIBCXX_ENABLE_NEW_DELETE_DEFINITIONS) + if (EXISTS "${abi_list_file}") add_custom_target(check-cxx-abilist - ${Python3_EXECUTABLE} "${LIBCXX_SOURCE_DIR}/utils/sym_diff.py" - --only-stdlib-symbols - --strict ${ABILIST_FILE} - $ - DEPENDS cxx_shared - COMMENT "Testing ABI compatibility...") + "${Python3_EXECUTABLE}" "${LIBCXX_SOURCE_DIR}/utils/sym_diff.py" + --only-stdlib-symbols + --strict "${abi_list_file}" + $ + DEPENDS cxx_shared + COMMENT "Testing libc++'s exported symbols against the ABI list") + else() + message(STATUS "ABI list file not generated for configuration ${abi_list_identifier}, `check-cxx-abilist` will not be available.") + endif() - add_custom_target(generate-cxx-abilist - COMMAND ${Python3_EXECUTABLE} "${LIBCXX_SOURCE_DIR}/utils/generate_abi_list.py" - --output "${ABILIST_FILE}" - "$" - DEPENDS cxx_shared - COMMENT "Generating the ABI list for the current configuration") + add_custom_target(generate-cxx-abilist + COMMAND "${Python3_EXECUTABLE}" "${LIBCXX_SOURCE_DIR}/utils/generate_abi_list.py" + --output "${abi_list_file}" + "$" + DEPENDS cxx_shared + COMMENT "Generating the ABI list file for configuration ${abi_list_identifier}") else() - message(STATUS "there is no pre-generated ABI list for the requested libc++ configuration. " - "check-cxx-abilist target is not supported") + message(STATUS "Not building a shared library for libc++ -- the ABI list targets will not be available.") endif() diff --git a/libcxx/lib/abi/x86_64-apple-darwin.v1.abilist b/libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist similarity index 100% rename from libcxx/lib/abi/x86_64-apple-darwin.v1.abilist rename to libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist diff --git a/libcxx/lib/abi/x86_64-unknown-linux-gnu.v1.abilist b/libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist similarity index 100% rename from libcxx/lib/abi/x86_64-unknown-linux-gnu.v1.abilist rename to libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist diff --git a/libcxx/src/experimental/memory_resource.cpp b/libcxx/src/experimental/memory_resource.cpp index 68c5bc99cc72a..1304ef3df78f4 100644 --- a/libcxx/src/experimental/memory_resource.cpp +++ b/libcxx/src/experimental/memory_resource.cpp @@ -76,16 +76,6 @@ union ResourceInitHelper { ~ResourceInitHelper() {} }; -// Detect if the init_priority attribute is supported. -#if (defined(_LIBCPP_COMPILER_GCC) && defined(__APPLE__)) \ - || defined(_LIBCPP_COMPILER_MSVC) -// GCC on Apple doesn't support the init priority attribute, -// and MSVC doesn't support any GCC attributes. -# define _LIBCPP_INIT_PRIORITY_MAX -#else -# define _LIBCPP_INIT_PRIORITY_MAX __attribute__((init_priority(101))) -#endif - // When compiled in C++14 this initialization should be a constant expression. // Only in C++11 is "init_priority" needed to ensure initialization order. #if _LIBCPP_STD_VER > 11 diff --git a/libcxx/src/iostream.cpp b/libcxx/src/iostream.cpp index d088593c4feda..ea95534c7667a 100644 --- a/libcxx/src/iostream.cpp +++ b/libcxx/src/iostream.cpp @@ -77,7 +77,7 @@ __asm__("?wclog@" _LIBCPP_ABI_NAMESPACE_STR "@std@@3V?$basic_ostream@_WU?$char_t #endif ; -_LIBCPP_HIDDEN ios_base::Init __start_std_streams __attribute__((init_priority(101))); +_LIBCPP_HIDDEN ios_base::Init __start_std_streams _LIBCPP_INIT_PRIORITY_MAX; // On Windows the TLS storage for locales needs to be initialized before we create // the standard streams, otherwise it may not be alive during program termination diff --git a/libcxx/src/new.cpp b/libcxx/src/new.cpp index ec60ca64815f5..8bdaf13cf9532 100644 --- a/libcxx/src/new.cpp +++ b/libcxx/src/new.cpp @@ -64,7 +64,7 @@ operator new(std::size_t size) _THROW_BAD_ALLOC if (size == 0) size = 1; void* p; - while ((p = ::malloc(size)) == 0) + while ((p = ::malloc(size)) == nullptr) { // If malloc fails and there is a new_handler, // call it to try free up memory. @@ -85,7 +85,7 @@ _LIBCPP_WEAK void* operator new(size_t size, const std::nothrow_t&) _NOEXCEPT { - void* p = 0; + void* p = nullptr; #ifndef _LIBCPP_NO_EXCEPTIONS try { @@ -111,7 +111,7 @@ _LIBCPP_WEAK void* operator new[](size_t size, const std::nothrow_t&) _NOEXCEPT { - void* p = 0; + void* p = nullptr; #ifndef _LIBCPP_NO_EXCEPTIONS try { @@ -179,15 +179,16 @@ operator new(std::size_t size, std::align_val_t alignment) _THROW_BAD_ALLOC size = 1; if (static_cast(alignment) < sizeof(void*)) alignment = std::align_val_t(sizeof(void*)); + + // Try allocating memory. If allocation fails and there is a new_handler, + // call it to try free up memory, and try again until it succeeds, or until + // the new_handler decides to terminate. + // + // If allocation fails and there is no new_handler, we throw bad_alloc + // (or return nullptr if exceptions are disabled). void* p; -#if defined(_LIBCPP_MSVCRT_LIKE) - while ((p = _aligned_malloc(size, static_cast(alignment))) == nullptr) -#else - while (::posix_memalign(&p, static_cast(alignment), size) != 0) -#endif + while ((p = std::__libcpp_aligned_alloc(static_cast(alignment), size)) == nullptr) { - // If posix_memalign fails and there is a new_handler, - // call it to try free up memory. std::new_handler nh = std::get_new_handler(); if (nh) nh(); @@ -195,7 +196,6 @@ operator new(std::size_t size, std::align_val_t alignment) _THROW_BAD_ALLOC #ifndef _LIBCPP_NO_EXCEPTIONS throw std::bad_alloc(); #else - p = nullptr; // posix_memalign doesn't initialize 'p' on failure break; #endif } @@ -207,7 +207,7 @@ _LIBCPP_WEAK void* operator new(size_t size, std::align_val_t alignment, const std::nothrow_t&) _NOEXCEPT { - void* p = 0; + void* p = nullptr; #ifndef _LIBCPP_NO_EXCEPTIONS try { @@ -233,7 +233,7 @@ _LIBCPP_WEAK void* operator new[](size_t size, std::align_val_t alignment, const std::nothrow_t&) _NOEXCEPT { - void* p = 0; + void* p = nullptr; #ifndef _LIBCPP_NO_EXCEPTIONS try { @@ -252,12 +252,9 @@ _LIBCPP_WEAK void operator delete(void* ptr, std::align_val_t) _NOEXCEPT { - if (ptr) -#if defined(_LIBCPP_MSVCRT_LIKE) - ::_aligned_free(ptr); -#else - ::free(ptr); -#endif + if (ptr) { + std::__libcpp_aligned_free(ptr); + } } _LIBCPP_WEAK diff --git a/libcxx/src/thread.cpp b/libcxx/src/thread.cpp index e1dc972cba7f9..5959d8b71103f 100644 --- a/libcxx/src/thread.cpp +++ b/libcxx/src/thread.cpp @@ -15,20 +15,8 @@ #include "future" #include "limits" -#if __has_include() -# include -#endif - -#if __has_include() -# include -#endif - -#if __has_include() -# include -#endif - #if __has_include() -# include +# include // for sysconf #endif #if defined(__NetBSD__) @@ -84,13 +72,7 @@ thread::detach() unsigned thread::hardware_concurrency() _NOEXCEPT { -#if defined(CTL_HW) && defined(HW_NCPU) - unsigned n; - int mib[2] = {CTL_HW, HW_NCPU}; - std::size_t s = sizeof(n); - sysctl(mib, 2, &n, &s, 0, 0); - return n; -#elif defined(_SC_NPROCESSORS_ONLN) +#if defined(_SC_NPROCESSORS_ONLN) long result = sysconf(_SC_NPROCESSORS_ONLN); // sysconf returns -1 if the name is invalid, the option does not exist or // does not have a definite limit. diff --git a/libcxx/test/libcxx/containers/sequences/vector/robust_against_adl.pass.cpp b/libcxx/test/libcxx/containers/sequences/vector/robust_against_adl.pass.cpp new file mode 100644 index 0000000000000..585ebc0858159 --- /dev/null +++ b/libcxx/test/libcxx/containers/sequences/vector/robust_against_adl.pass.cpp @@ -0,0 +1,41 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03 + +// + +#include + +#include "test_macros.h" + +struct Incomplete; +template struct Holder { T t; }; + +template> +struct MyAlloc { + using value_type = T; + T *allocate(int n) { return std::allocator().allocate(n); } + void deallocate(T *p, int n) { return std::allocator().deallocate(p, n); } +}; + +int main(int, char**) +{ + std::vector> v; + std::vector> w; + v.push_back(1); + v.insert(v.end(), 2); + v.insert(v.end(), w.begin(), w.end()); + v.pop_back(); + v.erase(v.begin()); + v.erase(v.begin(), v.end()); +#if TEST_STD_VER >= 14 + v.swap(w); +#endif + return 0; +} diff --git a/libcxx/test/libcxx/numerics/bit.ops.pass.cpp b/libcxx/test/libcxx/numerics/bit.ops.pass.cpp index 084728971e45e..3850ba65c7c50 100644 --- a/libcxx/test/libcxx/numerics/bit.ops.pass.cpp +++ b/libcxx/test/libcxx/numerics/bit.ops.pass.cpp @@ -32,7 +32,7 @@ int main(int, char **) static_assert( std::__libcpp_popcount(v) == 7, ""); static_assert( std::__bit_log2(v) == 12, ""); - static_assert(!std::__ispow2(v), ""); + static_assert(!std::__has_single_bit(v), ""); } #endif @@ -49,7 +49,7 @@ int main(int, char **) ASSERT_SAME_TYPE(int, decltype(std::__libcpp_popcount(v))); ASSERT_SAME_TYPE(unsigned, decltype(std::__bit_log2(v))); - ASSERT_SAME_TYPE(bool, decltype(std::__ispow2(v))); + ASSERT_SAME_TYPE(bool, decltype(std::__has_single_bit(v))); assert( std::__rotl(v, 3) == 0x91a2b3c0U); @@ -62,7 +62,7 @@ int main(int, char **) assert( std::__libcpp_popcount(v) == 13); assert( std::__bit_log2(v) == 28); - assert(!std::__ispow2(v)); + assert(!std::__has_single_bit(v)); } return 0; diff --git a/libcxx/test/libcxx/strings/basic.string/string.capacity/reserve.pass.cpp b/libcxx/test/libcxx/strings/basic.string/string.capacity/reserve.pass.cpp new file mode 100644 index 0000000000000..358f51fd6e4cf --- /dev/null +++ b/libcxx/test/libcxx/strings/basic.string/string.capacity/reserve.pass.cpp @@ -0,0 +1,50 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// void reserve(); // Deprecated in C++20. + +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS + +#include +#include +#include + +#include "test_macros.h" +#include "min_allocator.h" + +template +void +test() +{ + // Tests that a call to reserve() on a long string is equivalent to shrink_to_fit(). + S s(1000, 'a'); + typename S::size_type old_cap = s.capacity(); + s.resize(20); + assert(s.capacity() == old_cap); + s.reserve(); + assert(s.capacity() < old_cap); +} + +int main(int, char**) +{ + { + typedef std::string S; + test(); + } +#if TEST_STD_VER >= 11 + { + typedef min_allocator A; + typedef std::basic_string, A> S; + test(); + } +#endif + + return 0; +} diff --git a/libcxx/test/libcxx/utilities/memory/util.smartptr/race_condition.pass.cpp b/libcxx/test/libcxx/utilities/memory/util.smartptr/race_condition.pass.cpp index 0f7096d5f17e4..5ea05cd20d5ee 100644 --- a/libcxx/test/libcxx/utilities/memory/util.smartptr/race_condition.pass.cpp +++ b/libcxx/test/libcxx/utilities/memory/util.smartptr/race_condition.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" typedef std::shared_ptr Ptr; @@ -51,7 +52,7 @@ void run_test(Ptr p) { assert(p.use_count() == 2); TestRunner r(p); assert(p.use_count() == 3); - std::thread t1(r); // Start the test thread. + std::thread t1 = support::make_test_thread(r); // Start the test thread. assert(p.use_count() == 4); Start = true; // Run until we witness 25 use count changes via both diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy.pass.cpp index ab6aaa241b1e9..32c42b6caf3a3 100644 --- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy.pass.cpp +++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// UNSUPPORTED: clang-8 + // // template OutIter> @@ -79,7 +81,7 @@ int main(int, char**) { test(); -#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) +#if TEST_STD_VER > 17 static_assert(test()); #endif diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_backward.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_backward.pass.cpp index 11eb21f202d35..6f1743cb221a5 100644 --- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_backward.pass.cpp +++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_backward.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// UNSUPPORTED: clang-8 + // // template @@ -58,7 +60,7 @@ int main(int, char**) { test(); -#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) +#if TEST_STD_VER > 17 static_assert(test()); #endif diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_n.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_n.pass.cpp index 8c4900fe33b41..48c2fd7c9ff0e 100644 --- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_n.pass.cpp +++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.copy/copy_n.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// UNSUPPORTED: clang-8 + // // template OutIter> @@ -82,7 +84,7 @@ int main(int, char**) { test(); -#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) +#if TEST_STD_VER > 17 static_assert(test()); #endif diff --git a/libcxx/test/std/atomics/atomics.lockfree/isalwayslockfree.pass.cpp b/libcxx/test/std/atomics/atomics.lockfree/isalwayslockfree.pass.cpp index d9e09641dc4b8..d9ec69eebbe29 100644 --- a/libcxx/test/std/atomics/atomics.lockfree/isalwayslockfree.pass.cpp +++ b/libcxx/test/std/atomics/atomics.lockfree/isalwayslockfree.pass.cpp @@ -74,6 +74,9 @@ void run() CHECK_ALWAYS_LOCK_FREE(char); CHECK_ALWAYS_LOCK_FREE(signed char); CHECK_ALWAYS_LOCK_FREE(unsigned char); +#if TEST_STD_VER > 17 && defined(__cpp_char8_t) + CHECK_ALWAYS_LOCK_FREE(char8_t); +#endif CHECK_ALWAYS_LOCK_FREE(char16_t); CHECK_ALWAYS_LOCK_FREE(char32_t); CHECK_ALWAYS_LOCK_FREE(wchar_t); @@ -122,6 +125,9 @@ void run() static_assert(std::atomic::is_always_lock_free == (2 == ATOMIC_CHAR_LOCK_FREE), ""); static_assert(std::atomic::is_always_lock_free == (2 == ATOMIC_CHAR_LOCK_FREE), ""); static_assert(std::atomic::is_always_lock_free == (2 == ATOMIC_CHAR_LOCK_FREE), ""); +#if TEST_STD_VER > 17 && defined(__cpp_char8_t) + static_assert(std::atomic::is_always_lock_free == (2 == ATOMIC_CHAR8_T_LOCK_FREE), ""); +#endif static_assert(std::atomic::is_always_lock_free == (2 == ATOMIC_CHAR16_T_LOCK_FREE), ""); static_assert(std::atomic::is_always_lock_free == (2 == ATOMIC_CHAR32_T_LOCK_FREE), ""); static_assert(std::atomic::is_always_lock_free == (2 == ATOMIC_WCHAR_T_LOCK_FREE), ""); diff --git a/libcxx/test/std/atomics/atomics.lockfree/lockfree.pass.cpp b/libcxx/test/std/atomics/atomics.lockfree/lockfree.pass.cpp index 064afcaa7ed67..e36e46815e5f0 100644 --- a/libcxx/test/std/atomics/atomics.lockfree/lockfree.pass.cpp +++ b/libcxx/test/std/atomics/atomics.lockfree/lockfree.pass.cpp @@ -12,6 +12,7 @@ // #define ATOMIC_BOOL_LOCK_FREE unspecified // #define ATOMIC_CHAR_LOCK_FREE unspecified +// #define ATOMIC_CHAR8_T_LOCK_FREE unspecified // C++20 // #define ATOMIC_CHAR16_T_LOCK_FREE unspecified // #define ATOMIC_CHAR32_T_LOCK_FREE unspecified // #define ATOMIC_WCHAR_T_LOCK_FREE unspecified @@ -34,6 +35,11 @@ int main(int, char**) assert(ATOMIC_CHAR_LOCK_FREE == 0 || ATOMIC_CHAR_LOCK_FREE == 1 || ATOMIC_CHAR_LOCK_FREE == 2); +#if TEST_STD_VER > 17 && defined(__cpp_char8_t) + assert(ATOMIC_CHAR8_T_LOCK_FREE == 0 || + ATOMIC_CHAR8_T_LOCK_FREE == 1 || + ATOMIC_CHAR8_T_LOCK_FREE == 2); +#endif assert(ATOMIC_CHAR16_T_LOCK_FREE == 0 || ATOMIC_CHAR16_T_LOCK_FREE == 1 || ATOMIC_CHAR16_T_LOCK_FREE == 2); diff --git a/libcxx/test/std/atomics/atomics.types.generic/integral.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/integral.pass.cpp index 62ef06bcc16eb..12edd299a1ac7 100644 --- a/libcxx/test/std/atomics/atomics.types.generic/integral.pass.cpp +++ b/libcxx/test/std/atomics/atomics.types.generic/integral.pass.cpp @@ -180,6 +180,9 @@ int main(int, char**) test(); test(); test(); +#if TEST_STD_VER > 17 && defined(__cpp_char8_t) + test(); +#endif #ifndef _LIBCPP_HAS_NO_UNICODE_CHARS test(); test(); diff --git a/libcxx/test/std/atomics/atomics.types.generic/integral_typedefs.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/integral_typedefs.pass.cpp index dd59c301a8e09..74827ecdef337 100644 --- a/libcxx/test/std/atomics/atomics.types.generic/integral_typedefs.pass.cpp +++ b/libcxx/test/std/atomics/atomics.types.generic/integral_typedefs.pass.cpp @@ -21,6 +21,7 @@ // typedef atomic atomic_ulong; // typedef atomic atomic_llong; // typedef atomic atomic_ullong; +// typedef atomic atomic_char8_t; // C++20 // typedef atomic atomic_char16_t; // typedef atomic atomic_char32_t; // typedef atomic atomic_wchar_t; @@ -56,6 +57,9 @@ int main(int, char**) static_assert((std::is_same, std::atomic_llong>::value), ""); static_assert((std::is_same, std::atomic_ullong>::value), ""); static_assert((std::is_same, std::atomic_wchar_t>::value), ""); +#if TEST_STD_VER > 17 && defined(__cpp_char8_t) + static_assert((std::is_same, std::atomic_char8_t>::value), ""); +#endif #ifndef _LIBCPP_HAS_NO_UNICODE_CHARS static_assert((std::is_same, std::atomic_char16_t>::value), ""); static_assert((std::is_same, std::atomic_char32_t>::value), ""); diff --git a/libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.req/atomic_helpers.h b/libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.req/atomic_helpers.h index cab2264aaecd7..9c21ada4da7eb 100644 --- a/libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.req/atomic_helpers.h +++ b/libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.req/atomic_helpers.h @@ -83,6 +83,9 @@ struct TestEachIntegralType { TestFunctor()(); TestFunctor()(); TestFunctor(); +#if TEST_STD_VER > 17 && defined(__cpp_char8_t) + TestFunctor()(); +#endif #ifndef _LIBCPP_HAS_NO_UNICODE_CHARS TestFunctor()(); TestFunctor()(); diff --git a/libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.wait/atomic_wait.pass.cpp b/libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.wait/atomic_wait.pass.cpp index b5a345d7fbe25..32929bd4bc7d7 100644 --- a/libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.wait/atomic_wait.pass.cpp +++ b/libcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.wait/atomic_wait.pass.cpp @@ -27,6 +27,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" #include "../atomics.types.operations.req/atomic_helpers.h" @@ -39,23 +40,23 @@ struct TestFn { std::atomic_init(&t, T(1)); assert(std::atomic_load(&t) == T(1)); std::atomic_wait(&t, T(0)); - std::thread t_([&](){ + std::thread t1 = support::make_test_thread([&](){ std::atomic_store(&t, T(3)); std::atomic_notify_one(&t); }); std::atomic_wait(&t, T(1)); - t_.join(); + t1.join(); volatile A vt; std::atomic_init(&vt, T(2)); assert(std::atomic_load(&vt) == T(2)); std::atomic_wait(&vt, T(1)); - std::thread t2_([&](){ + std::thread t2 = support::make_test_thread([&](){ std::atomic_store(&vt, T(4)); std::atomic_notify_one(&vt); }); std::atomic_wait(&vt, T(2)); - t2_.join(); + t2.join(); } }; diff --git a/libcxx/test/std/atomics/types.pass.cpp b/libcxx/test/std/atomics/types.pass.cpp index 4fc2c6c22a7be..ed6cbef33aeb8 100644 --- a/libcxx/test/std/atomics/types.pass.cpp +++ b/libcxx/test/std/atomics/types.pass.cpp @@ -112,6 +112,9 @@ int main(int, char**) test (); test (); test (); +#if TEST_STD_VER > 17 && defined(__cpp_char8_t) + test (); +#endif test (); test (); test (); diff --git a/libcxx/test/std/experimental/memory/memory.resource/memory.resource.priv/protected_members.fail.cpp b/libcxx/test/std/experimental/memory/memory.resource/memory.resource.priv/private_members.fail.cpp similarity index 73% rename from libcxx/test/std/experimental/memory/memory.resource/memory.resource.priv/protected_members.fail.cpp rename to libcxx/test/std/experimental/memory/memory.resource/memory.resource.priv/private_members.fail.cpp index 85c4ce4ee91ce..a0c84b0fa83cc 100644 --- a/libcxx/test/std/experimental/memory/memory.resource/memory.resource.priv/protected_members.fail.cpp +++ b/libcxx/test/std/experimental/memory/memory.resource/memory.resource.priv/private_members.fail.cpp @@ -10,9 +10,9 @@ // -// memory_resource::do_allocate(size_t, size_t); /* protected */ -// memory_resource::do_deallocate(void*, size_t, size_t); /* protected */ -// memory_resource::do_is_equal(memory_resource const&); /* protected */ +// memory_resource::do_allocate(size_t, size_t); /* private */ +// memory_resource::do_deallocate(void*, size_t, size_t); /* private */ +// memory_resource::do_is_equal(memory_resource const&); /* private */ #include @@ -20,9 +20,9 @@ namespace ex = std::experimental::pmr; int main(int, char**) { ex::memory_resource *m = ex::new_delete_resource(); - m->do_allocate(0, 0); // expected-error{{'do_allocate' is a protected member}} - m->do_deallocate(nullptr, 0, 0); // expected-error{{'do_deallocate' is a protected member}} - m->do_is_equal(*m); // expected-error{{'do_is_equal' is a protected member}} + m->do_allocate(0, 0); // expected-error{{'do_allocate' is a private member}} + m->do_deallocate(nullptr, 0, 0); // expected-error{{'do_deallocate' is a private member}} + m->do_is_equal(*m); // expected-error{{'do_is_equal' is a private member}} return 0; } diff --git a/libcxx/test/std/experimental/simd/simd.access/default.pass.cpp b/libcxx/test/std/experimental/simd/simd.access/default.pass.cpp index 1bc1500ea6a73..2ca5ec4482bf8 100644 --- a/libcxx/test/std/experimental/simd/simd.access/default.pass.cpp +++ b/libcxx/test/std/experimental/simd/simd.access/default.pass.cpp @@ -40,12 +40,12 @@ void test_access() { assert(a[0] % b[0] == 42 % 4); assert(a[0] << b[0] == (42 << 4)); assert(a[0] >> b[0] == (42 >> 4)); - assert(a[0] < b[0] == false); - assert(a[0] <= b[0] == false); - assert(a[0] > b[0] == true); - assert(a[0] >= b[0] == true); - assert(a[0] == b[0] == false); - assert(a[0] != b[0] == true); + assert((a[0] < b[0]) == false); + assert((a[0] <= b[0]) == false); + assert((a[0] > b[0]) == true); + assert((a[0] >= b[0]) == true); + assert((a[0] == b[0]) == false); + assert((a[0] != b[0]) == true); assert((a[0] & b[0]) == (42 & 4)); assert((a[0] | b[0]) == (42 | 4)); assert((a[0] ^ b[0]) == (42 ^ 4)); @@ -198,12 +198,12 @@ void test_access() { assert(a[0] % b[0] == 42 % 4); assert(a[0] << b[0] == (42 << 4)); assert(a[0] >> b[0] == (42 >> 4)); - assert(a[0] < b[0] == false); - assert(a[0] <= b[0] == false); - assert(a[0] > b[0] == true); - assert(a[0] >= b[0] == true); - assert(a[0] == b[0] == false); - assert(a[0] != b[0] == true); + assert((a[0] < b[0]) == false); + assert((a[0] <= b[0]) == false); + assert((a[0] > b[0]) == true); + assert((a[0] >= b[0]) == true); + assert((a[0] == b[0]) == false); + assert((a[0] != b[0]) == true); assert((a[0] & b[0]) == (42 & 4)); assert((a[0] | b[0]) == (42 | 4)); assert((a[0] ^ b[0]) == (42 ^ 4)); diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/bit.version.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/bit.version.pass.cpp index 4f99d8d86a723..92a8ada73febd 100644 --- a/libcxx/test/std/language.support/support.limits/support.limits.general/bit.version.pass.cpp +++ b/libcxx/test/std/language.support/support.limits/support.limits.general/bit.version.pass.cpp @@ -16,6 +16,7 @@ /* Constant Value __cpp_lib_bit_cast 201806L [C++2a] __cpp_lib_endian 201907L [C++2a] + __cpp_lib_int_pow2 202002L [C++2a] */ #include @@ -31,6 +32,10 @@ # error "__cpp_lib_endian should not be defined before c++2a" # endif +# ifdef __cpp_lib_int_pow2 +# error "__cpp_lib_int_pow2 should not be defined before c++2a" +# endif + #elif TEST_STD_VER == 14 # ifdef __cpp_lib_bit_cast @@ -41,6 +46,10 @@ # error "__cpp_lib_endian should not be defined before c++2a" # endif +# ifdef __cpp_lib_int_pow2 +# error "__cpp_lib_int_pow2 should not be defined before c++2a" +# endif + #elif TEST_STD_VER == 17 # ifdef __cpp_lib_bit_cast @@ -51,6 +60,10 @@ # error "__cpp_lib_endian should not be defined before c++2a" # endif +# ifdef __cpp_lib_int_pow2 +# error "__cpp_lib_int_pow2 should not be defined before c++2a" +# endif + #elif TEST_STD_VER > 17 # if !defined(_LIBCPP_VERSION) @@ -73,6 +86,13 @@ # error "__cpp_lib_endian should have the value 201907L in c++2a" # endif +# ifndef __cpp_lib_int_pow2 +# error "__cpp_lib_int_pow2 should be defined in c++2a" +# endif +# if __cpp_lib_int_pow2 != 202002L +# error "__cpp_lib_int_pow2 should have the value 202002L in c++2a" +# endif + #endif // TEST_STD_VER > 17 int main(int, char**) { return 0; } diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp index c625753ca2bda..efb8416924ce7 100644 --- a/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp +++ b/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp @@ -58,6 +58,7 @@ __cpp_lib_has_unique_object_representations 201606L [C++17] __cpp_lib_hypot 201603L [C++17] __cpp_lib_incomplete_container_elements 201505L [C++17] + __cpp_lib_int_pow2 202002L [C++2a] __cpp_lib_integer_sequence 201304L [C++14] __cpp_lib_integral_constant_callable 201304L [C++14] __cpp_lib_interpolate 201902L [C++2a] @@ -290,6 +291,10 @@ # error "__cpp_lib_incomplete_container_elements should not be defined before c++17" # endif +# ifdef __cpp_lib_int_pow2 +# error "__cpp_lib_int_pow2 should not be defined before c++2a" +# endif + # ifdef __cpp_lib_integer_sequence # error "__cpp_lib_integer_sequence should not be defined before c++14" # endif @@ -684,6 +689,10 @@ # error "__cpp_lib_incomplete_container_elements should not be defined before c++17" # endif +# ifdef __cpp_lib_int_pow2 +# error "__cpp_lib_int_pow2 should not be defined before c++2a" +# endif + # ifndef __cpp_lib_integer_sequence # error "__cpp_lib_integer_sequence should be defined in c++14" # endif @@ -1228,6 +1237,10 @@ # error "__cpp_lib_incomplete_container_elements should have the value 201505L in c++17" # endif +# ifdef __cpp_lib_int_pow2 +# error "__cpp_lib_int_pow2 should not be defined before c++2a" +# endif + # ifndef __cpp_lib_integer_sequence # error "__cpp_lib_integer_sequence should be defined in c++17" # endif @@ -2039,6 +2052,13 @@ # error "__cpp_lib_incomplete_container_elements should have the value 201505L in c++2a" # endif +# ifndef __cpp_lib_int_pow2 +# error "__cpp_lib_int_pow2 should be defined in c++2a" +# endif +# if __cpp_lib_int_pow2 != 202002L +# error "__cpp_lib_int_pow2 should have the value 202002L in c++2a" +# endif + # ifndef __cpp_lib_integer_sequence # error "__cpp_lib_integer_sequence should be defined in c++2a" # endif diff --git a/libcxx/test/std/localization/locale.categories/category.monetary/locale.money.get/locale.money.get.members/get_long_double_fr_FR.pass.cpp b/libcxx/test/std/localization/locale.categories/category.monetary/locale.money.get/locale.money.get.members/get_long_double_fr_FR.pass.cpp index 862bc9018cbf9..f7041f96675d1 100644 --- a/libcxx/test/std/localization/locale.categories/category.monetary/locale.money.get/locale.money.get.members/get_long_double_fr_FR.pass.cpp +++ b/libcxx/test/std/localization/locale.categories/category.monetary/locale.money.get/locale.money.get.members/get_long_double_fr_FR.pass.cpp @@ -49,14 +49,15 @@ class my_facetw : Fw(refs) {} }; - // GLIBC 2.27 and newer use U2027 (narrow non-breaking space) as a thousands sep. // this function converts the spaces in string inputs to that character if need -// be. +// be. FreeBSD's locale data also uses U2027 since 2018. static std::wstring convert_thousands_sep(std::wstring const& in) { +#if defined(_CS_GNU_LIBC_VERSION) || defined(__FreeBSD__) #if defined(_CS_GNU_LIBC_VERSION) if (glibc_version_less_than("2.27")) return in; +#endif std::wstring out; unsigned I = 0; bool seen_decimal = false; diff --git a/libcxx/test/std/localization/locale.categories/category.monetary/locale.money.put/locale.money.put.members/put_long_double_fr_FR.pass.cpp b/libcxx/test/std/localization/locale.categories/category.monetary/locale.money.put/locale.money.put.members/put_long_double_fr_FR.pass.cpp index e35bc2573d8cd..837f542a9e621 100644 --- a/libcxx/test/std/localization/locale.categories/category.monetary/locale.money.put/locale.money.put.members/put_long_double_fr_FR.pass.cpp +++ b/libcxx/test/std/localization/locale.categories/category.monetary/locale.money.put/locale.money.put.members/put_long_double_fr_FR.pass.cpp @@ -49,14 +49,15 @@ class my_facetw : Fw(refs) {} }; - // GLIBC 2.27 and newer use U2027 (narrow non-breaking space) as a thousands sep. // this function converts the spaces in string inputs to that character if need -// be. +// be. FreeBSD's locale data also uses U2027 since 2018. static std::wstring convert_thousands_sep(std::wstring const& in) { +#if defined(_CS_GNU_LIBC_VERSION) || defined(__FreeBSD__) #if defined(_CS_GNU_LIBC_VERSION) if (glibc_version_less_than("2.27")) return in; +#endif std::wstring out; unsigned I = 0; bool seen_num_start = false; diff --git a/libcxx/test/std/numerics/bit/bit.pow.two/ceil2.fail.cpp b/libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.fail.cpp similarity index 96% rename from libcxx/test/std/numerics/bit/bit.pow.two/ceil2.fail.cpp rename to libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.fail.cpp index d1257672f126a..ff6f29e8817fe 100644 --- a/libcxx/test/std/numerics/bit/bit.pow.two/ceil2.fail.cpp +++ b/libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.fail.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // template -// constexpr T ceil2(T x) noexcept; +// constexpr T bit_ceil(T x) noexcept; // Remarks: This function shall not participate in overload resolution unless // T is an unsigned integer type @@ -28,7 +28,7 @@ enum class E2 : unsigned char { red }; template constexpr bool toobig() { - return 0 == std::ceil2(std::numeric_limits::max()); + return 0 == std::bit_ceil(std::numeric_limits::max()); } int main(int, char**) diff --git a/libcxx/test/std/numerics/bit/bit.pow.two/ceil2.pass.cpp b/libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.pass.cpp similarity index 77% rename from libcxx/test/std/numerics/bit/bit.pow.two/ceil2.pass.cpp rename to libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.pass.cpp index 1959eb05580c3..3945c07449194 100644 --- a/libcxx/test/std/numerics/bit/bit.pow.two/ceil2.pass.cpp +++ b/libcxx/test/std/numerics/bit/bit.pow.two/bit_ceil.pass.cpp @@ -9,9 +9,9 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // template -// constexpr T ceil2(T x) noexcept; +// constexpr T bit_ceil(T x) noexcept; -// Returns: The minimal value y such that ispow2(y) is true and y >= x; +// Returns: The minimal value y such that has_single_bit(y) is true and y >= x; // if y is not representable as a value of type T, the result is an unspecified value. // Remarks: This function shall not participate in overload resolution unless // T is an unsigned integer type @@ -30,16 +30,16 @@ enum class E2 : unsigned char { red }; template constexpr bool constexpr_test() { - return std::ceil2(T(0)) == T(1) - && std::ceil2(T(1)) == T(1) - && std::ceil2(T(2)) == T(2) - && std::ceil2(T(3)) == T(4) - && std::ceil2(T(4)) == T(4) - && std::ceil2(T(5)) == T(8) - && std::ceil2(T(6)) == T(8) - && std::ceil2(T(7)) == T(8) - && std::ceil2(T(8)) == T(8) - && std::ceil2(T(9)) == T(16) + return std::bit_ceil(T(0)) == T(1) + && std::bit_ceil(T(1)) == T(1) + && std::bit_ceil(T(2)) == T(2) + && std::bit_ceil(T(3)) == T(4) + && std::bit_ceil(T(4)) == T(4) + && std::bit_ceil(T(5)) == T(8) + && std::bit_ceil(T(6)) == T(8) + && std::bit_ceil(T(7)) == T(8) + && std::bit_ceil(T(8)) == T(8) + && std::bit_ceil(T(9)) == T(16) ; } @@ -47,26 +47,26 @@ constexpr bool constexpr_test() template void runtime_test() { - ASSERT_SAME_TYPE(T, decltype(std::ceil2(T(0)))); - LIBCPP_ASSERT_NOEXCEPT( std::ceil2(T(0))); - - assert( std::ceil2(T(60)) == T( 64)); - assert( std::ceil2(T(61)) == T( 64)); - assert( std::ceil2(T(62)) == T( 64)); - assert( std::ceil2(T(63)) == T( 64)); - assert( std::ceil2(T(64)) == T( 64)); - assert( std::ceil2(T(65)) == T(128)); - assert( std::ceil2(T(66)) == T(128)); - assert( std::ceil2(T(67)) == T(128)); - assert( std::ceil2(T(68)) == T(128)); - assert( std::ceil2(T(69)) == T(128)); + ASSERT_SAME_TYPE(T, decltype(std::bit_ceil(T(0)))); + LIBCPP_ASSERT_NOEXCEPT( std::bit_ceil(T(0))); + + assert( std::bit_ceil(T(60)) == T( 64)); + assert( std::bit_ceil(T(61)) == T( 64)); + assert( std::bit_ceil(T(62)) == T( 64)); + assert( std::bit_ceil(T(63)) == T( 64)); + assert( std::bit_ceil(T(64)) == T( 64)); + assert( std::bit_ceil(T(65)) == T(128)); + assert( std::bit_ceil(T(66)) == T(128)); + assert( std::bit_ceil(T(67)) == T(128)); + assert( std::bit_ceil(T(68)) == T(128)); + assert( std::bit_ceil(T(69)) == T(128)); } int main(int, char**) { { - auto lambda = [](auto x) -> decltype(std::ceil2(x)) {}; + auto lambda = [](auto x) -> decltype(std::bit_ceil(x)) {}; using L = decltype(lambda); static_assert( std::is_invocable_v, ""); diff --git a/libcxx/test/std/numerics/bit/bit.pow.two/floor2.pass.cpp b/libcxx/test/std/numerics/bit/bit.pow.two/bit_floor.pass.cpp similarity index 73% rename from libcxx/test/std/numerics/bit/bit.pow.two/floor2.pass.cpp rename to libcxx/test/std/numerics/bit/bit.pow.two/bit_floor.pass.cpp index 83afdf92f0662..3b7e245d979a2 100644 --- a/libcxx/test/std/numerics/bit/bit.pow.two/floor2.pass.cpp +++ b/libcxx/test/std/numerics/bit/bit.pow.two/bit_floor.pass.cpp @@ -9,9 +9,9 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // template -// constexpr T floor2(T x) noexcept; +// constexpr T bit_floor(T x) noexcept; -// Returns: If x == 0, 0; otherwise the maximal value y such that floor2(y) is true and y <= x. +// Returns: If x == 0, 0; otherwise the maximal value y such that bit_floor(y) is true and y <= x. // Remarks: This function shall not participate in overload resolution unless // T is an unsigned integer type @@ -29,16 +29,16 @@ enum class E2 : unsigned char { red }; template constexpr bool constexpr_test() { - return std::floor2(T(0)) == T(0) - && std::floor2(T(1)) == T(1) - && std::floor2(T(2)) == T(2) - && std::floor2(T(3)) == T(2) - && std::floor2(T(4)) == T(4) - && std::floor2(T(5)) == T(4) - && std::floor2(T(6)) == T(4) - && std::floor2(T(7)) == T(4) - && std::floor2(T(8)) == T(8) - && std::floor2(T(9)) == T(8) + return std::bit_floor(T(0)) == T(0) + && std::bit_floor(T(1)) == T(1) + && std::bit_floor(T(2)) == T(2) + && std::bit_floor(T(3)) == T(2) + && std::bit_floor(T(4)) == T(4) + && std::bit_floor(T(5)) == T(4) + && std::bit_floor(T(6)) == T(4) + && std::bit_floor(T(7)) == T(4) + && std::bit_floor(T(8)) == T(8) + && std::bit_floor(T(9)) == T(8) ; } @@ -46,26 +46,26 @@ constexpr bool constexpr_test() template void runtime_test() { - ASSERT_SAME_TYPE(T, decltype(std::floor2(T(0)))); - ASSERT_NOEXCEPT( std::floor2(T(0))); - - assert( std::floor2(T(121)) == T(64)); - assert( std::floor2(T(122)) == T(64)); - assert( std::floor2(T(123)) == T(64)); - assert( std::floor2(T(124)) == T(64)); - assert( std::floor2(T(125)) == T(64)); - assert( std::floor2(T(126)) == T(64)); - assert( std::floor2(T(127)) == T(64)); - assert( std::floor2(T(128)) == T(128)); - assert( std::floor2(T(129)) == T(128)); - assert( std::floor2(T(130)) == T(128)); + ASSERT_SAME_TYPE(T, decltype(std::bit_floor(T(0)))); + ASSERT_NOEXCEPT( std::bit_floor(T(0))); + + assert( std::bit_floor(T(121)) == T(64)); + assert( std::bit_floor(T(122)) == T(64)); + assert( std::bit_floor(T(123)) == T(64)); + assert( std::bit_floor(T(124)) == T(64)); + assert( std::bit_floor(T(125)) == T(64)); + assert( std::bit_floor(T(126)) == T(64)); + assert( std::bit_floor(T(127)) == T(64)); + assert( std::bit_floor(T(128)) == T(128)); + assert( std::bit_floor(T(129)) == T(128)); + assert( std::bit_floor(T(130)) == T(128)); } int main(int, char**) { { - auto lambda = [](auto x) -> decltype(std::floor2(x)) {}; + auto lambda = [](auto x) -> decltype(std::bit_floor(x)) {}; using L = decltype(lambda); static_assert( std::is_invocable_v, ""); @@ -147,17 +147,17 @@ int main(int, char**) { __uint128_t val = 128; val <<= 32; - assert( std::floor2(val-1) == val/2); - assert( std::floor2(val) == val); - assert( std::floor2(val+1) == val); + assert( std::bit_floor(val-1) == val/2); + assert( std::bit_floor(val) == val); + assert( std::bit_floor(val+1) == val); val <<= 2; - assert( std::floor2(val-1) == val/2); - assert( std::floor2(val) == val); - assert( std::floor2(val+1) == val); + assert( std::bit_floor(val-1) == val/2); + assert( std::bit_floor(val) == val); + assert( std::bit_floor(val+1) == val); val <<= 3; - assert( std::floor2(val-1) == val/2); - assert( std::floor2(val) == val); - assert( std::floor2(val+1) == val); + assert( std::bit_floor(val-1) == val/2); + assert( std::bit_floor(val) == val); + assert( std::bit_floor(val+1) == val); } #endif diff --git a/libcxx/test/std/numerics/bit/bit.pow.two/log2p1.pass.cpp b/libcxx/test/std/numerics/bit/bit.pow.two/bit_width.pass.cpp similarity index 69% rename from libcxx/test/std/numerics/bit/bit.pow.two/log2p1.pass.cpp rename to libcxx/test/std/numerics/bit/bit.pow.two/bit_width.pass.cpp index ffa57196fd6a5..71587988abf65 100644 --- a/libcxx/test/std/numerics/bit/bit.pow.two/log2p1.pass.cpp +++ b/libcxx/test/std/numerics/bit/bit.pow.two/bit_width.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // template -// constexpr T log2p1(T x) noexcept; +// constexpr T bit_width(T x) noexcept; // If x == 0, 0; otherwise one plus the base-2 logarithm of x, with any fractional part discarded. @@ -29,16 +29,16 @@ enum class E2 : unsigned char { red }; template constexpr bool constexpr_test() { - return std::log2p1(T(0)) == T(0) - && std::log2p1(T(1)) == T(1) - && std::log2p1(T(2)) == T(2) - && std::log2p1(T(3)) == T(2) - && std::log2p1(T(4)) == T(3) - && std::log2p1(T(5)) == T(3) - && std::log2p1(T(6)) == T(3) - && std::log2p1(T(7)) == T(3) - && std::log2p1(T(8)) == T(4) - && std::log2p1(T(9)) == T(4) + return std::bit_width(T(0)) == T(0) + && std::bit_width(T(1)) == T(1) + && std::bit_width(T(2)) == T(2) + && std::bit_width(T(3)) == T(2) + && std::bit_width(T(4)) == T(3) + && std::bit_width(T(5)) == T(3) + && std::bit_width(T(6)) == T(3) + && std::bit_width(T(7)) == T(3) + && std::bit_width(T(8)) == T(4) + && std::bit_width(T(9)) == T(4) ; } @@ -46,38 +46,38 @@ constexpr bool constexpr_test() template void runtime_test() { - ASSERT_SAME_TYPE(T, decltype(std::log2p1(T(0)))); - ASSERT_NOEXCEPT( std::log2p1(T(0))); - - assert( std::log2p1(T(0)) == T(0)); - assert( std::log2p1(T(1)) == T(1)); - assert( std::log2p1(T(2)) == T(2)); - assert( std::log2p1(T(3)) == T(2)); - assert( std::log2p1(T(4)) == T(3)); - assert( std::log2p1(T(5)) == T(3)); - assert( std::log2p1(T(6)) == T(3)); - assert( std::log2p1(T(7)) == T(3)); - assert( std::log2p1(T(8)) == T(4)); - assert( std::log2p1(T(9)) == T(4)); - - - assert( std::log2p1(T(121)) == T(7)); - assert( std::log2p1(T(122)) == T(7)); - assert( std::log2p1(T(123)) == T(7)); - assert( std::log2p1(T(124)) == T(7)); - assert( std::log2p1(T(125)) == T(7)); - assert( std::log2p1(T(126)) == T(7)); - assert( std::log2p1(T(127)) == T(7)); - assert( std::log2p1(T(128)) == T(8)); - assert( std::log2p1(T(129)) == T(8)); - assert( std::log2p1(T(130)) == T(8)); + ASSERT_SAME_TYPE(T, decltype(std::bit_width(T(0)))); + ASSERT_NOEXCEPT( std::bit_width(T(0))); + + assert( std::bit_width(T(0)) == T(0)); + assert( std::bit_width(T(1)) == T(1)); + assert( std::bit_width(T(2)) == T(2)); + assert( std::bit_width(T(3)) == T(2)); + assert( std::bit_width(T(4)) == T(3)); + assert( std::bit_width(T(5)) == T(3)); + assert( std::bit_width(T(6)) == T(3)); + assert( std::bit_width(T(7)) == T(3)); + assert( std::bit_width(T(8)) == T(4)); + assert( std::bit_width(T(9)) == T(4)); + + + assert( std::bit_width(T(121)) == T(7)); + assert( std::bit_width(T(122)) == T(7)); + assert( std::bit_width(T(123)) == T(7)); + assert( std::bit_width(T(124)) == T(7)); + assert( std::bit_width(T(125)) == T(7)); + assert( std::bit_width(T(126)) == T(7)); + assert( std::bit_width(T(127)) == T(7)); + assert( std::bit_width(T(128)) == T(8)); + assert( std::bit_width(T(129)) == T(8)); + assert( std::bit_width(T(130)) == T(8)); } int main(int, char**) { { - auto lambda = [](auto x) -> decltype(std::log2p1(x)) {}; + auto lambda = [](auto x) -> decltype(std::bit_width(x)) {}; using L = decltype(lambda); static_assert( std::is_invocable_v, ""); @@ -160,17 +160,17 @@ int main(int, char**) { __uint128_t val = 128; val <<= 32; - assert( std::log2p1(val-1) == 39); - assert( std::log2p1(val) == 40); - assert( std::log2p1(val+1) == 40); + assert( std::bit_width(val-1) == 39); + assert( std::bit_width(val) == 40); + assert( std::bit_width(val+1) == 40); val <<= 2; - assert( std::log2p1(val-1) == 41); - assert( std::log2p1(val) == 42); - assert( std::log2p1(val+1) == 42); + assert( std::bit_width(val-1) == 41); + assert( std::bit_width(val) == 42); + assert( std::bit_width(val+1) == 42); val <<= 3; - assert( std::log2p1(val-1) == 44); - assert( std::log2p1(val) == 45); - assert( std::log2p1(val+1) == 45); + assert( std::bit_width(val-1) == 44); + assert( std::bit_width(val) == 45); + assert( std::bit_width(val+1) == 45); } #endif diff --git a/libcxx/test/std/numerics/bit/bit.pow.two/ispow2.pass.cpp b/libcxx/test/std/numerics/bit/bit.pow.two/has_single_bit.pass.cpp similarity index 75% rename from libcxx/test/std/numerics/bit/bit.pow.two/ispow2.pass.cpp rename to libcxx/test/std/numerics/bit/bit.pow.two/has_single_bit.pass.cpp index 52e3e5f299eee..8816fc9a16260 100644 --- a/libcxx/test/std/numerics/bit/bit.pow.two/ispow2.pass.cpp +++ b/libcxx/test/std/numerics/bit/bit.pow.two/has_single_bit.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 // template -// constexpr bool ispow2(T x) noexcept; +// constexpr bool has_single_bit(T x) noexcept; // Remarks: This function shall not participate in overload resolution unless // T is an unsigned integer type @@ -28,15 +28,15 @@ enum class E2 : unsigned char { red }; template constexpr bool constexpr_test() { - return std::ispow2(T(1)) - && std::ispow2(T(2)) - && !std::ispow2(T(3)) - && std::ispow2(T(4)) - && !std::ispow2(T(5)) - && !std::ispow2(T(6)) - && !std::ispow2(T(7)) - && std::ispow2(T(8)) - && !std::ispow2(T(9)) + return std::has_single_bit(T(1)) + && std::has_single_bit(T(2)) + && !std::has_single_bit(T(3)) + && std::has_single_bit(T(4)) + && !std::has_single_bit(T(5)) + && !std::has_single_bit(T(6)) + && !std::has_single_bit(T(7)) + && std::has_single_bit(T(8)) + && !std::has_single_bit(T(9)) ; } @@ -44,26 +44,26 @@ constexpr bool constexpr_test() template void runtime_test() { - ASSERT_SAME_TYPE(bool, decltype(std::ispow2(T(0)))); - ASSERT_NOEXCEPT( std::ispow2(T(0))); - - assert(!std::ispow2(T(121))); - assert(!std::ispow2(T(122))); - assert(!std::ispow2(T(123))); - assert(!std::ispow2(T(124))); - assert(!std::ispow2(T(125))); - assert(!std::ispow2(T(126))); - assert(!std::ispow2(T(127))); - assert( std::ispow2(T(128))); - assert(!std::ispow2(T(129))); - assert(!std::ispow2(T(130))); + ASSERT_SAME_TYPE(bool, decltype(std::has_single_bit(T(0)))); + ASSERT_NOEXCEPT( std::has_single_bit(T(0))); + + assert(!std::has_single_bit(T(121))); + assert(!std::has_single_bit(T(122))); + assert(!std::has_single_bit(T(123))); + assert(!std::has_single_bit(T(124))); + assert(!std::has_single_bit(T(125))); + assert(!std::has_single_bit(T(126))); + assert(!std::has_single_bit(T(127))); + assert( std::has_single_bit(T(128))); + assert(!std::has_single_bit(T(129))); + assert(!std::has_single_bit(T(130))); } int main(int, char**) { { - auto lambda = [](auto x) -> decltype(std::ispow2(x)) {}; + auto lambda = [](auto x) -> decltype(std::has_single_bit(x)) {}; using L = decltype(lambda); static_assert( std::is_invocable_v, ""); @@ -145,17 +145,17 @@ int main(int, char**) { __uint128_t val = 128; val <<= 32; - assert(!std::ispow2(val-1)); - assert( std::ispow2(val)); - assert(!std::ispow2(val+1)); + assert(!std::has_single_bit(val-1)); + assert( std::has_single_bit(val)); + assert(!std::has_single_bit(val+1)); val <<= 2; - assert(!std::ispow2(val-1)); - assert( std::ispow2(val)); - assert(!std::ispow2(val+1)); + assert(!std::has_single_bit(val-1)); + assert( std::has_single_bit(val)); + assert(!std::has_single_bit(val+1)); val <<= 3; - assert(!std::ispow2(val-1)); - assert( std::ispow2(val)); - assert(!std::ispow2(val+1)); + assert(!std::has_single_bit(val-1)); + assert( std::has_single_bit(val)); + assert(!std::has_single_bit(val+1)); } #endif diff --git a/libcxx/test/std/strings/basic.string/string.capacity/reserve.deprecated_in_cxx20.verify.cpp b/libcxx/test/std/strings/basic.string/string.capacity/reserve.deprecated_in_cxx20.verify.cpp new file mode 100644 index 0000000000000..1b8a5da964587 --- /dev/null +++ b/libcxx/test/std/strings/basic.string/string.capacity/reserve.deprecated_in_cxx20.verify.cpp @@ -0,0 +1,22 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// void reserve(); // Deprecated in C++20 + +// UNSUPPORTED: c++03, c++11, c++14, c++17 + +#include + +int main(int, char**) +{ + std::string s; + s.reserve(); // expected-warning {{'reserve' is deprecated}} + return 0; +} diff --git a/libcxx/test/std/strings/basic.string/string.capacity/reserve.pass.cpp b/libcxx/test/std/strings/basic.string/string.capacity/reserve.pass.cpp index f49125cec98ea..a200a6357257e 100644 --- a/libcxx/test/std/strings/basic.string/string.capacity/reserve.pass.cpp +++ b/libcxx/test/std/strings/basic.string/string.capacity/reserve.pass.cpp @@ -8,9 +8,9 @@ // -// Split into two calls for C++20 -// void reserve(); -// void reserve(size_type res_arg); +// void reserve(); // Deprecated in C++20. + +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS #include #include @@ -21,8 +21,13 @@ template void -test(S s) +test(typename S::size_type min_cap, typename S::size_type erased_index) { + S s(min_cap, 'a'); + s.erase(erased_index); + assert(s.size() == erased_index); + assert(s.capacity() >= min_cap); // Check that we really have at least this capacity. + typename S::size_type old_cap = s.capacity(); S s0 = s; s.reserve(); @@ -32,102 +37,23 @@ test(S s) assert(s.capacity() >= s.size()); } -template -void -test(S s, typename S::size_type res_arg) -{ - typename S::size_type old_cap = s.capacity(); - ((void)old_cap); // Prevent unused warning - S s0 = s; - if (res_arg <= s.max_size()) - { - s.reserve(res_arg); - assert(s == s0); - assert(s.capacity() >= res_arg); - assert(s.capacity() >= s.size()); -#if TEST_STD_VER > 17 - assert(s.capacity() >= old_cap); // resize never shrinks as of P0966 -#endif - } -#ifndef TEST_HAS_NO_EXCEPTIONS - else - { - try - { - s.reserve(res_arg); - assert(false); - } - catch (std::length_error&) - { - assert(res_arg > s.max_size()); - } - } -#endif -} - int main(int, char**) { { typedef std::string S; { - S s; - test(s); - - s.assign(10, 'a'); - s.erase(5); - test(s); - - s.assign(100, 'a'); - s.erase(50); - test(s); - } - { - S s; - test(s, 5); - test(s, 10); - test(s, 50); - } - { - S s(100, 'a'); - s.erase(50); - test(s, 5); - test(s, 10); - test(s, 50); - test(s, 100); - test(s, 1000); - test(s, S::npos); + test(0, 0); + test(10, 5); + test(100, 50); } } #if TEST_STD_VER >= 11 { typedef std::basic_string, min_allocator> S; { - S s; - test(s); - - s.assign(10, 'a'); - s.erase(5); - test(s); - - s.assign(100, 'a'); - s.erase(50); - test(s); - } - { - S s; - test(s, 5); - test(s, 10); - test(s, 50); - } - { - S s(100, 'a'); - s.erase(50); - test(s, 5); - test(s, 10); - test(s, 50); - test(s, 100); - test(s, 1000); - test(s, S::npos); + test(0, 0); + test(10, 5); + test(100, 50); } } #endif diff --git a/libcxx/test/std/strings/basic.string/string.capacity/reserve_size.pass.cpp b/libcxx/test/std/strings/basic.string/string.capacity/reserve_size.pass.cpp new file mode 100644 index 0000000000000..8820ad5a14b00 --- /dev/null +++ b/libcxx/test/std/strings/basic.string/string.capacity/reserve_size.pass.cpp @@ -0,0 +1,110 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// void reserve(size_type res_arg); + +// This test relies on https://llvm.org/PR45368 being fixed, which isn't in +// older Apple dylibs +// +// XFAIL: with_system_cxx_lib=macosx10.15 +// XFAIL: with_system_cxx_lib=macosx10.14 +// XFAIL: with_system_cxx_lib=macosx10.13 +// XFAIL: with_system_cxx_lib=macosx10.12 +// XFAIL: with_system_cxx_lib=macosx10.11 +// XFAIL: with_system_cxx_lib=macosx10.10 +// XFAIL: with_system_cxx_lib=macosx10.9 + +#include +#include +#include + +#include "test_macros.h" +#include "min_allocator.h" + +template +void +test(typename S::size_type min_cap, typename S::size_type erased_index, typename S::size_type res_arg) +{ + S s(min_cap, 'a'); + s.erase(erased_index); + assert(s.size() == erased_index); + assert(s.capacity() >= min_cap); // Check that we really have at least this capacity. + +#if TEST_STD_VER > 17 + typename S::size_type old_cap = s.capacity(); +#endif + S s0 = s; + if (res_arg <= s.max_size()) + { + s.reserve(res_arg); + LIBCPP_ASSERT(s.__invariants()); + assert(s == s0); + assert(s.capacity() >= res_arg); + assert(s.capacity() >= s.size()); +#if TEST_STD_VER > 17 + assert(s.capacity() >= old_cap); // reserve never shrinks as of P0966 (C++20) +#endif + } +#ifndef TEST_HAS_NO_EXCEPTIONS + else + { + try + { + s.reserve(res_arg); + LIBCPP_ASSERT(s.__invariants()); + assert(false); + } + catch (std::length_error&) + { + assert(res_arg > s.max_size()); + } + } +#endif +} + +int main(int, char**) +{ + { + typedef std::string S; + { + test(0, 0, 5); + test(0, 0, 10); + test(0, 0, 50); + } + { + test(100, 50, 5); + test(100, 50, 10); + test(100, 50, 50); + test(100, 50, 100); + test(100, 50, 1000); + test(100, 50, S::npos); + } + } +#if TEST_STD_VER >= 11 + { + typedef std::basic_string, min_allocator> S; + { + test(0, 0, 5); + test(0, 0, 10); + test(0, 0, 50); + } + { + test(100, 50, 5); + test(100, 50, 10); + test(100, 50, 50); + test(100, 50, 100); + test(100, 50, 1000); + test(100, 50, S::npos); + } + } +#endif + + return 0; +} diff --git a/libcxx/test/std/strings/basic.string/string.cons/string_view_deduction.fail.cpp b/libcxx/test/std/strings/basic.string/string.cons/string_view_deduction.fail.cpp index 1fa2ee0efb1b2..aa4c4559696ca 100644 --- a/libcxx/test/std/strings/basic.string/string.cons/string_view_deduction.fail.cpp +++ b/libcxx/test/std/strings/basic.string/string.cons/string_view_deduction.fail.cpp @@ -8,6 +8,7 @@ // // UNSUPPORTED: c++03, c++11, c++14 +// UNSUPPORTED: gcc-7 // XFAIL: libcpp-no-deduction-guides // template diff --git a/libcxx/test/std/strings/basic.string/string.cons/string_view_size_size_deduction.fail.cpp b/libcxx/test/std/strings/basic.string/string.cons/string_view_size_size_deduction.fail.cpp index 07c9002b5b7da..d7a8868977c84 100644 --- a/libcxx/test/std/strings/basic.string/string.cons/string_view_size_size_deduction.fail.cpp +++ b/libcxx/test/std/strings/basic.string/string.cons/string_view_size_size_deduction.fail.cpp @@ -8,6 +8,7 @@ // // UNSUPPORTED: c++03, c++11, c++14 +// UNSUPPORTED: gcc-7 // XFAIL: libcpp-no-deduction-guides // template diff --git a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/assign3.pass.cpp b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/assign3.pass.cpp index d7a1753daf692..3d27bdc2366eb 100644 --- a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/assign3.pass.cpp +++ b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/assign3.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// UNSUPPORTED: clang-8 + // // template<> struct char_traits @@ -33,7 +35,7 @@ int main(int, char**) { test(); -#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) +#if TEST_STD_VER > 17 static_assert(test()); #endif diff --git a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/copy.pass.cpp b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/copy.pass.cpp index 3ac53897ebaa2..50f029b6f45cc 100644 --- a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/copy.pass.cpp +++ b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/copy.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// UNSUPPORTED: clang-8 + // // template<> struct char_traits @@ -35,7 +37,7 @@ int main(int, char**) { test(); -#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) +#if TEST_STD_VER > 17 static_assert(test()); #endif diff --git a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/move.pass.cpp b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/move.pass.cpp index 94f10aab7717a..74a11f7aeb93b 100644 --- a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/move.pass.cpp +++ b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char/move.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// UNSUPPORTED: clang-8 + // // template<> struct char_traits @@ -39,7 +41,7 @@ int main(int, char**) { test(); -#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) +#if TEST_STD_VER > 17 static_assert(test()); #endif diff --git a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char8_t/assign3.pass.cpp b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char8_t/assign3.pass.cpp index 2ebba1a6d0148..50544298a0e58 100644 --- a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char8_t/assign3.pass.cpp +++ b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char8_t/assign3.pass.cpp @@ -5,7 +5,9 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: clang-8 // @@ -36,7 +38,7 @@ int main(int, char**) { test(); -#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) +#if TEST_STD_VER > 17 static_assert(test()); #endif diff --git a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char8_t/copy.pass.cpp b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char8_t/copy.pass.cpp index 1dfeb1d42d542..3acc866d07e54 100644 --- a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char8_t/copy.pass.cpp +++ b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char8_t/copy.pass.cpp @@ -5,7 +5,9 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: clang-8 // @@ -38,7 +40,7 @@ int main(int, char**) { test(); -#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) +#if TEST_STD_VER > 17 static_assert(test()); #endif diff --git a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char8_t/move.pass.cpp b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char8_t/move.pass.cpp index f055e65abba39..8733dbd29e89c 100644 --- a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char8_t/move.pass.cpp +++ b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.char8_t/move.pass.cpp @@ -5,7 +5,9 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + // UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: clang-8 // @@ -42,7 +44,7 @@ int main(int, char**) { test(); -#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) +#if TEST_STD_VER > 17 static_assert(test()); #endif diff --git a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.wchar.t/assign3.pass.cpp b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.wchar.t/assign3.pass.cpp index 9997770e1ab17..36ef3b01af6ba 100644 --- a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.wchar.t/assign3.pass.cpp +++ b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.wchar.t/assign3.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// UNSUPPORTED: clang-8 + // // template<> struct char_traits @@ -33,7 +35,7 @@ int main(int, char**) { test(); -#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) +#if TEST_STD_VER > 17 static_assert(test()); #endif diff --git a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.wchar.t/copy.pass.cpp b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.wchar.t/copy.pass.cpp index 1eb2bd51320ff..4a97e6e9aedaa 100644 --- a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.wchar.t/copy.pass.cpp +++ b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.wchar.t/copy.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// UNSUPPORTED: clang-8 + // // template<> struct char_traits @@ -35,7 +37,7 @@ int main(int, char**) { test(); -#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) +#if TEST_STD_VER > 17 static_assert(test()); #endif diff --git a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.wchar.t/move.pass.cpp b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.wchar.t/move.pass.cpp index f459f287ce6ff..c8613e9268af6 100644 --- a/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.wchar.t/move.pass.cpp +++ b/libcxx/test/std/strings/char.traits/char.traits.specializations/char.traits.specializations.wchar.t/move.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// UNSUPPORTED: clang-8 + // // template<> struct char_traits @@ -39,7 +41,7 @@ int main(int, char**) { test(); -#if TEST_STD_VER > 17 && !defined(_LIBCPP_HAS_NO_BUILTIN_IS_CONSTANT_EVALUATED) +#if TEST_STD_VER > 17 static_assert(test()); #endif diff --git a/libcxx/test/std/thread/futures/futures.promise/set_exception_at_thread_exit.pass.cpp b/libcxx/test/std/thread/futures/futures.promise/set_exception_at_thread_exit.pass.cpp index 8c877531670c9..ab666641d139a 100644 --- a/libcxx/test/std/thread/futures/futures.promise/set_exception_at_thread_exit.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.promise/set_exception_at_thread_exit.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" void func(std::promise p) @@ -32,7 +33,7 @@ int main(int, char**) typedef int T; std::promise p; std::future f = p.get_future(); - std::thread(func, std::move(p)).detach(); + support::make_test_thread(func, std::move(p)).detach(); try { f.get(); diff --git a/libcxx/test/std/thread/futures/futures.promise/set_lvalue_at_thread_exit.pass.cpp b/libcxx/test/std/thread/futures/futures.promise/set_lvalue_at_thread_exit.pass.cpp index 1589493f37389..d3e1da2197a9a 100644 --- a/libcxx/test/std/thread/futures/futures.promise/set_lvalue_at_thread_exit.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.promise/set_lvalue_at_thread_exit.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int i = 0; @@ -34,7 +35,7 @@ int main(int, char**) { std::promise p; std::future f = p.get_future(); - std::thread(func, std::move(p)).detach(); + support::make_test_thread(func, std::move(p)).detach(); assert(f.get() == 4); } diff --git a/libcxx/test/std/thread/futures/futures.promise/set_rvalue_at_thread_exit.pass.cpp b/libcxx/test/std/thread/futures/futures.promise/set_rvalue_at_thread_exit.pass.cpp index f0ac893b6de60..5a982eabab8de 100644 --- a/libcxx/test/std/thread/futures/futures.promise/set_rvalue_at_thread_exit.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.promise/set_rvalue_at_thread_exit.pass.cpp @@ -18,6 +18,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" void func(std::promise> p) @@ -30,7 +31,7 @@ int main(int, char**) { std::promise> p; std::future> f = p.get_future(); - std::thread(func, std::move(p)).detach(); + support::make_test_thread(func, std::move(p)).detach(); assert(*f.get() == 5); } diff --git a/libcxx/test/std/thread/futures/futures.promise/set_value_at_thread_exit_const.pass.cpp b/libcxx/test/std/thread/futures/futures.promise/set_value_at_thread_exit_const.pass.cpp index 55f7764e52067..da9b7a8d8d0dd 100644 --- a/libcxx/test/std/thread/futures/futures.promise/set_value_at_thread_exit_const.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.promise/set_value_at_thread_exit_const.pass.cpp @@ -18,6 +18,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" void func(std::promise p) @@ -31,7 +32,7 @@ int main(int, char**) { std::promise p; std::future f = p.get_future(); - std::thread(func, std::move(p)).detach(); + support::make_test_thread(func, std::move(p)).detach(); assert(f.get() == 5); } diff --git a/libcxx/test/std/thread/futures/futures.promise/set_value_at_thread_exit_void.pass.cpp b/libcxx/test/std/thread/futures/futures.promise/set_value_at_thread_exit_void.pass.cpp index 0ba0d60940883..9786973c0c6c4 100644 --- a/libcxx/test/std/thread/futures/futures.promise/set_value_at_thread_exit_void.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.promise/set_value_at_thread_exit_void.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int i = 0; @@ -34,7 +35,7 @@ int main(int, char**) { std::promise p; std::future f = p.get_future(); - std::thread(func, std::move(p)).detach(); + support::make_test_thread(func, std::move(p)).detach(); f.get(); assert(i == 1); } diff --git a/libcxx/test/std/thread/futures/futures.shared_future/get.pass.cpp b/libcxx/test/std/thread/futures/futures.shared_future/get.pass.cpp index 4b2c8979c9391..61835df782cd8 100644 --- a/libcxx/test/std/thread/futures/futures.shared_future/get.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.shared_future/get.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" void func1(std::promise p) @@ -68,7 +69,7 @@ int main(int, char**) { std::promise p; std::shared_future f = p.get_future(); - std::thread(func1, std::move(p)).detach(); + support::make_test_thread(func1, std::move(p)).detach(); assert(f.valid()); assert(f.get() == 3); assert(f.valid()); @@ -77,7 +78,7 @@ int main(int, char**) { std::promise p; std::shared_future f = p.get_future(); - std::thread(func2, std::move(p)).detach(); + support::make_test_thread(func2, std::move(p)).detach(); try { assert(f.valid()); @@ -97,7 +98,7 @@ int main(int, char**) { std::promise p; std::shared_future f = p.get_future(); - std::thread(func3, std::move(p)).detach(); + support::make_test_thread(func3, std::move(p)).detach(); assert(f.valid()); assert(f.get() == 5); assert(f.valid()); @@ -106,7 +107,7 @@ int main(int, char**) { std::promise p; std::shared_future f = p.get_future(); - std::thread(func4, std::move(p)).detach(); + support::make_test_thread(func4, std::move(p)).detach(); try { assert(f.valid()); @@ -126,7 +127,7 @@ int main(int, char**) { std::promise p; std::shared_future f = p.get_future(); - std::thread(func5, std::move(p)).detach(); + support::make_test_thread(func5, std::move(p)).detach(); assert(f.valid()); f.get(); assert(f.valid()); @@ -135,7 +136,7 @@ int main(int, char**) { std::promise p; std::shared_future f = p.get_future(); - std::thread(func6, std::move(p)).detach(); + support::make_test_thread(func6, std::move(p)).detach(); try { assert(f.valid()); diff --git a/libcxx/test/std/thread/futures/futures.shared_future/wait.pass.cpp b/libcxx/test/std/thread/futures/futures.shared_future/wait.pass.cpp index 485d0050de627..4be8c1bd70158 100644 --- a/libcxx/test/std/thread/futures/futures.shared_future/wait.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.shared_future/wait.pass.cpp @@ -18,6 +18,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" void func1(std::promise p) @@ -49,7 +50,7 @@ int main(int, char**) typedef int T; std::promise p; std::shared_future f = p.get_future(); - std::thread(func1, std::move(p)).detach(); + support::make_test_thread(func1, std::move(p)).detach(); assert(f.valid()); f.wait(); assert(f.valid()); @@ -63,7 +64,7 @@ int main(int, char**) typedef int& T; std::promise p; std::shared_future f = p.get_future(); - std::thread(func3, std::move(p)).detach(); + support::make_test_thread(func3, std::move(p)).detach(); assert(f.valid()); f.wait(); assert(f.valid()); @@ -77,7 +78,7 @@ int main(int, char**) typedef void T; std::promise p; std::shared_future f = p.get_future(); - std::thread(func5, std::move(p)).detach(); + support::make_test_thread(func5, std::move(p)).detach(); assert(f.valid()); f.wait(); assert(f.valid()); diff --git a/libcxx/test/std/thread/futures/futures.shared_future/wait_for.pass.cpp b/libcxx/test/std/thread/futures/futures.shared_future/wait_for.pass.cpp index 8f58f1f46c86c..d8b0ce3457bc5 100644 --- a/libcxx/test/std/thread/futures/futures.shared_future/wait_for.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.shared_future/wait_for.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" typedef std::chrono::milliseconds ms; @@ -56,7 +57,7 @@ int main(int, char**) typedef int T; std::promise p; std::shared_future f = p.get_future(); - std::thread(func1, std::move(p)).detach(); + support::make_test_thread(func1, std::move(p)).detach(); assert(f.valid()); assert(f.wait_for(ms(1)) == std::future_status::timeout); assert(f.valid()); @@ -69,7 +70,7 @@ int main(int, char**) typedef int& T; std::promise p; std::shared_future f = p.get_future(); - std::thread(func3, std::move(p)).detach(); + support::make_test_thread(func3, std::move(p)).detach(); assert(f.valid()); assert(f.wait_for(ms(1)) == std::future_status::timeout); assert(f.valid()); @@ -82,7 +83,7 @@ int main(int, char**) typedef void T; std::promise p; std::shared_future f = p.get_future(); - std::thread(func5, std::move(p)).detach(); + support::make_test_thread(func5, std::move(p)).detach(); assert(f.valid()); assert(f.wait_for(ms(1)) == std::future_status::timeout); assert(f.valid()); @@ -97,7 +98,7 @@ int main(int, char**) std::promise p; std::shared_future f = p.get_future(); Clock::time_point t0 = Clock::now(); - std::thread(func1, std::move(p)).detach(); + support::make_test_thread(func1, std::move(p)).detach(); assert(f.valid()); assert(f.wait_for(ms(1)) == std::future_status::timeout); assert(f.valid()); @@ -113,7 +114,7 @@ int main(int, char**) std::promise p; std::shared_future f = p.get_future(); Clock::time_point t0 = Clock::now(); - std::thread(func3, std::move(p)).detach(); + support::make_test_thread(func3, std::move(p)).detach(); assert(f.valid()); assert(f.wait_for(ms(1)) == std::future_status::timeout); assert(f.valid()); @@ -129,7 +130,7 @@ int main(int, char**) std::promise p; std::shared_future f = p.get_future(); Clock::time_point t0 = Clock::now(); - std::thread(func5, std::move(p)).detach(); + support::make_test_thread(func5, std::move(p)).detach(); assert(f.valid()); assert(f.wait_for(ms(1)) == std::future_status::timeout); assert(f.valid()); diff --git a/libcxx/test/std/thread/futures/futures.shared_future/wait_until.pass.cpp b/libcxx/test/std/thread/futures/futures.shared_future/wait_until.pass.cpp index a9e0dbdba5388..1d58dc25f2185 100644 --- a/libcxx/test/std/thread/futures/futures.shared_future/wait_until.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.shared_future/wait_until.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" enum class WorkerThreadState { Uninitialized, AllowedToRun, Exiting }; @@ -71,7 +72,7 @@ int main(int, char**) typedef int T; std::promise p; std::shared_future f = p.get_future(); - std::thread(func1, std::move(p)).detach(); + support::make_test_thread(func1, std::move(p)).detach(); assert(f.valid()); assert(f.wait_until(Clock::now() + ms(10)) == std::future_status::timeout); assert(f.valid()); @@ -89,7 +90,7 @@ int main(int, char**) typedef int& T; std::promise p; std::shared_future f = p.get_future(); - std::thread(func3, std::move(p)).detach(); + support::make_test_thread(func3, std::move(p)).detach(); assert(f.valid()); assert(f.wait_until(Clock::now() + ms(10)) == std::future_status::timeout); assert(f.valid()); @@ -107,7 +108,7 @@ int main(int, char**) typedef void T; std::promise p; std::shared_future f = p.get_future(); - std::thread(func5, std::move(p)).detach(); + support::make_test_thread(func5, std::move(p)).detach(); assert(f.valid()); assert(f.wait_until(Clock::now() + ms(10)) == std::future_status::timeout); assert(f.valid()); diff --git a/libcxx/test/std/thread/futures/futures.task/futures.task.members/dtor.pass.cpp b/libcxx/test/std/thread/futures/futures.task/futures.task.members/dtor.pass.cpp index 65bc94cf413a8..d626f74244437 100644 --- a/libcxx/test/std/thread/futures/futures.task/futures.task.members/dtor.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.task/futures.task.members/dtor.pass.cpp @@ -18,6 +18,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class A @@ -45,7 +46,7 @@ int main(int, char**) { std::packaged_task p(A(5)); std::future f = p.get_future(); - std::thread(func, std::move(p)).detach(); + support::make_test_thread(func, std::move(p)).detach(); try { double i = f.get(); @@ -61,7 +62,7 @@ int main(int, char**) { std::packaged_task p(A(5)); std::future f = p.get_future(); - std::thread(func2, std::move(p)).detach(); + support::make_test_thread(func2, std::move(p)).detach(); assert(f.get() == 105.0); } diff --git a/libcxx/test/std/thread/futures/futures.task/futures.task.members/make_ready_at_thread_exit.pass.cpp b/libcxx/test/std/thread/futures/futures.task/futures.task.members/make_ready_at_thread_exit.pass.cpp index 571a1bf3684a0..b42a632ace75a 100644 --- a/libcxx/test/std/thread/futures/futures.task/futures.task.members/make_ready_at_thread_exit.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.task/futures.task.members/make_ready_at_thread_exit.pass.cpp @@ -18,6 +18,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class A @@ -85,14 +86,14 @@ int main(int, char**) { std::packaged_task p(A(5)); std::future f = p.get_future(); - std::thread(func0, std::move(p)).detach(); + support::make_test_thread(func0, std::move(p)).detach(); assert(f.get() == 105.0); } #ifndef TEST_HAS_NO_EXCEPTIONS { std::packaged_task p(A(5)); std::future f = p.get_future(); - std::thread(func1, std::move(p)).detach(); + support::make_test_thread(func1, std::move(p)).detach(); try { f.get(); @@ -106,12 +107,12 @@ int main(int, char**) { std::packaged_task p(A(5)); std::future f = p.get_future(); - std::thread(func2, std::move(p)).detach(); + support::make_test_thread(func2, std::move(p)).detach(); assert(f.get() == 105.0); } { std::packaged_task p; - std::thread t(func3, std::move(p)); + std::thread t = support::make_test_thread(func3, std::move(p)); t.join(); } #endif diff --git a/libcxx/test/std/thread/futures/futures.task/futures.task.members/operator.pass.cpp b/libcxx/test/std/thread/futures/futures.task/futures.task.members/operator.pass.cpp index 5a9f2a6290be0..886deb78cb8a6 100644 --- a/libcxx/test/std/thread/futures/futures.task/futures.task.members/operator.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.task/futures.task.members/operator.pass.cpp @@ -18,6 +18,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class A @@ -85,14 +86,14 @@ int main(int, char**) { std::packaged_task p(A(5)); std::future f = p.get_future(); - std::thread(func0, std::move(p)).detach(); + support::make_test_thread(func0, std::move(p)).detach(); assert(f.get() == 105.0); } #ifndef TEST_HAS_NO_EXCEPTIONS { std::packaged_task p(A(5)); std::future f = p.get_future(); - std::thread(func1, std::move(p)).detach(); + support::make_test_thread(func1, std::move(p)).detach(); try { f.get(); @@ -106,13 +107,13 @@ int main(int, char**) { std::packaged_task p(A(5)); std::future f = p.get_future(); - std::thread t(func2, std::move(p)); + std::thread t = support::make_test_thread(func2, std::move(p)); assert(f.get() == 105.0); t.join(); } { std::packaged_task p; - std::thread t(func3, std::move(p)); + std::thread t = support::make_test_thread(func3, std::move(p)); t.join(); } #endif diff --git a/libcxx/test/std/thread/futures/futures.unique_future/get.pass.cpp b/libcxx/test/std/thread/futures/futures.unique_future/get.pass.cpp index cb188fa908bcd..3262a2b7ce57c 100644 --- a/libcxx/test/std/thread/futures/futures.unique_future/get.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.unique_future/get.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" void func1(std::promise p) @@ -68,7 +69,7 @@ int main(int, char**) { std::promise p; std::future f = p.get_future(); - std::thread(func1, std::move(p)).detach(); + support::make_test_thread(func1, std::move(p)).detach(); assert(f.valid()); assert(f.get() == 3); assert(!f.valid()); @@ -77,7 +78,7 @@ int main(int, char**) { std::promise p; std::future f = p.get_future(); - std::thread(func2, std::move(p)).detach(); + support::make_test_thread(func2, std::move(p)).detach(); try { assert(f.valid()); @@ -97,7 +98,7 @@ int main(int, char**) { std::promise p; std::future f = p.get_future(); - std::thread(func3, std::move(p)).detach(); + support::make_test_thread(func3, std::move(p)).detach(); assert(f.valid()); assert(f.get() == 5); assert(!f.valid()); @@ -106,7 +107,7 @@ int main(int, char**) { std::promise p; std::future f = p.get_future(); - std::thread(func4, std::move(p)).detach(); + support::make_test_thread(func4, std::move(p)).detach(); try { assert(f.valid()); @@ -126,7 +127,7 @@ int main(int, char**) { std::promise p; std::future f = p.get_future(); - std::thread(func5, std::move(p)).detach(); + support::make_test_thread(func5, std::move(p)).detach(); assert(f.valid()); f.get(); assert(!f.valid()); @@ -135,7 +136,7 @@ int main(int, char**) { std::promise p; std::future f = p.get_future(); - std::thread(func6, std::move(p)).detach(); + support::make_test_thread(func6, std::move(p)).detach(); try { assert(f.valid()); diff --git a/libcxx/test/std/thread/futures/futures.unique_future/wait.pass.cpp b/libcxx/test/std/thread/futures/futures.unique_future/wait.pass.cpp index ee550545fbbc8..712ee3b9b4a15 100644 --- a/libcxx/test/std/thread/futures/futures.unique_future/wait.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.unique_future/wait.pass.cpp @@ -18,6 +18,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" void func1(std::promise p) @@ -48,7 +49,7 @@ void test(F func) { std::promise p; std::future f = p.get_future(); - std::thread(func, std::move(p)).detach(); + support::make_test_thread(func, std::move(p)).detach(); assert(f.valid()); f.wait(); assert(f.valid()); diff --git a/libcxx/test/std/thread/futures/futures.unique_future/wait_for.pass.cpp b/libcxx/test/std/thread/futures/futures.unique_future/wait_for.pass.cpp index 9ba4cd262ea89..2a04ade2592e1 100644 --- a/libcxx/test/std/thread/futures/futures.unique_future/wait_for.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.unique_future/wait_for.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" typedef std::chrono::milliseconds ms; @@ -54,7 +55,7 @@ void test(F func, bool waitFirst) { std::promise p; std::future f = p.get_future(); Clock::time_point t1, t0 = Clock::now(); - std::thread(func, std::move(p)).detach(); + support::make_test_thread(func, std::move(p)).detach(); assert(f.valid()); assert(f.wait_for(ms(1)) == std::future_status::timeout); assert(f.valid()); diff --git a/libcxx/test/std/thread/futures/futures.unique_future/wait_until.pass.cpp b/libcxx/test/std/thread/futures/futures.unique_future/wait_until.pass.cpp index 0581028128118..e5171e5f9f1f5 100644 --- a/libcxx/test/std/thread/futures/futures.unique_future/wait_until.pass.cpp +++ b/libcxx/test/std/thread/futures/futures.unique_future/wait_until.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" enum class WorkerThreadState { Uninitialized, AllowedToRun, Exiting }; @@ -70,7 +71,7 @@ int main(int, char**) typedef int T; std::promise p; std::future f = p.get_future(); - std::thread(func1, std::move(p)).detach(); + support::make_test_thread(func1, std::move(p)).detach(); assert(f.valid()); assert(f.wait_until(Clock::now() + ms(10)) == std::future_status::timeout); assert(f.valid()); @@ -88,7 +89,7 @@ int main(int, char**) typedef int& T; std::promise p; std::future f = p.get_future(); - std::thread(func3, std::move(p)).detach(); + support::make_test_thread(func3, std::move(p)).detach(); assert(f.valid()); assert(f.wait_until(Clock::now() + ms(10)) == std::future_status::timeout); assert(f.valid()); @@ -106,7 +107,7 @@ int main(int, char**) typedef void T; std::promise p; std::future f = p.get_future(); - std::thread(func5, std::move(p)).detach(); + support::make_test_thread(func5, std::move(p)).detach(); assert(f.valid()); assert(f.wait_until(Clock::now() + ms(10)) == std::future_status::timeout); assert(f.valid()); diff --git a/libcxx/test/std/thread/thread.barrier/arrive.pass.cpp b/libcxx/test/std/thread/thread.barrier/arrive.pass.cpp index 59a219797a53f..c4956b611c688 100644 --- a/libcxx/test/std/thread/thread.barrier/arrive.pass.cpp +++ b/libcxx/test/std/thread/thread.barrier/arrive.pass.cpp @@ -25,6 +25,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int main(int, char**) @@ -32,7 +33,7 @@ int main(int, char**) std::barrier<> b(2); auto tok = b.arrive(); - std::thread t([&](){ + std::thread t = support::make_test_thread([&](){ (void)b.arrive(); }); b.wait(std::move(tok)); diff --git a/libcxx/test/std/thread/thread.barrier/arrive_and_drop.pass.cpp b/libcxx/test/std/thread/thread.barrier/arrive_and_drop.pass.cpp index 00f8dfa97b987..b8bcbc993bd4e 100644 --- a/libcxx/test/std/thread/thread.barrier/arrive_and_drop.pass.cpp +++ b/libcxx/test/std/thread/thread.barrier/arrive_and_drop.pass.cpp @@ -26,13 +26,14 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int main(int, char**) { std::barrier<> b(2); - std::thread t([&](){ + std::thread t = support::make_test_thread([&](){ b.arrive_and_drop(); }); diff --git a/libcxx/test/std/thread/thread.barrier/arrive_and_wait.pass.cpp b/libcxx/test/std/thread/thread.barrier/arrive_and_wait.pass.cpp index b3da00eb6e343..8fc5469347330 100644 --- a/libcxx/test/std/thread/thread.barrier/arrive_and_wait.pass.cpp +++ b/libcxx/test/std/thread/thread.barrier/arrive_and_wait.pass.cpp @@ -25,13 +25,14 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int main(int, char**) { std::barrier<> b(2); - std::thread t([&](){ + std::thread t = support::make_test_thread([&](){ for(int i = 0; i < 10; ++i) b.arrive_and_wait(); }); diff --git a/libcxx/test/std/thread/thread.barrier/completion.pass.cpp b/libcxx/test/std/thread/thread.barrier/completion.pass.cpp index 7d4e8119790d0..d9200729d97e1 100644 --- a/libcxx/test/std/thread/thread.barrier/completion.pass.cpp +++ b/libcxx/test/std/thread/thread.barrier/completion.pass.cpp @@ -26,6 +26,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int main(int, char**) @@ -34,7 +35,7 @@ int main(int, char**) auto comp = [&]() { x += 1; }; std::barrier b(2, comp); - std::thread t([&](){ + std::thread t = support::make_test_thread([&](){ for(int i = 0; i < 10; ++i) b.arrive_and_wait(); }); diff --git a/libcxx/test/std/thread/thread.condition/notify_all_at_thread_exit.pass.cpp b/libcxx/test/std/thread/thread.condition/notify_all_at_thread_exit.pass.cpp index 8ef869b66a96a..48a077455b368 100644 --- a/libcxx/test/std/thread/thread.condition/notify_all_at_thread_exit.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/notify_all_at_thread_exit.pass.cpp @@ -23,6 +23,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::condition_variable cv; @@ -41,7 +42,7 @@ void func() int main(int, char**) { std::unique_lock lk(mut); - std::thread t(func); + std::thread t = support::make_test_thread(func); Clock::time_point t0 = Clock::now(); cv.wait(lk); Clock::time_point t1 = Clock::now(); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/destructor.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/destructor.pass.cpp index 1c4eeb94d01b4..6f2d6b97fb700 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/destructor.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/destructor.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::condition_variable* cv; @@ -48,12 +49,12 @@ void g() int main(int, char**) { cv = new std::condition_variable; - std::thread th2(g); + std::thread th2 = support::make_test_thread(g); Lock lk(m); while (!g_ready) cv->wait(lk); lk.unlock(); - std::thread th1(f); + std::thread th1 = support::make_test_thread(f); th1.join(); th2.join(); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/notify_all.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/notify_all.pass.cpp index f0f614d1c24ed..b095cd06e4e4f 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/notify_all.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/notify_all.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::condition_variable cv; @@ -50,8 +51,8 @@ void f2() int main(int, char**) { - std::thread t1(f1); - std::thread t2(f2); + std::thread t1 = support::make_test_thread(f1); + std::thread t2 = support::make_test_thread(f2); std::this_thread::sleep_for(std::chrono::milliseconds(100)); { std::unique_locklk(mut); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/notify_one.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/notify_one.pass.cpp index b373050565177..821fbdda5b62c 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/notify_one.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/notify_one.pass.cpp @@ -41,6 +41,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" @@ -78,8 +79,8 @@ void f2() int main(int, char**) { - std::thread t1(f1); - std::thread t2(f2); + std::thread t1 = support::make_test_thread(f1); + std::thread t2 = support::make_test_thread(f2); { while (ready > 0) std::this_thread::yield(); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait.pass.cpp index e89bb313b47c4..a2dc4466f0d69 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::condition_variable cv; @@ -40,8 +41,8 @@ void f() int main(int, char**) { - std::unique_locklk(mut); - std::thread t(f); + std::unique_lock lk(mut); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_for.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_for.pass.cpp index 3bead1b6ff892..a58e15f7b009d 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_for.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_for.pass.cpp @@ -25,6 +25,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::condition_variable cv; @@ -64,8 +65,8 @@ void f() int main(int, char**) { { - std::unique_locklk(mut); - std::thread t(f); + std::unique_lock lk(mut); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); @@ -78,8 +79,8 @@ int main(int, char**) test1 = 0; test2 = 0; { - std::unique_locklk(mut); - std::thread t(f); + std::unique_lock lk(mut); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_for_pred.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_for_pred.pass.cpp index f3322b9b7c041..d6a1bb9224089 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_for_pred.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_for_pred.pass.cpp @@ -24,6 +24,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class Pred @@ -72,7 +73,7 @@ int main(int, char**) { { std::unique_locklk(mut); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); @@ -86,7 +87,7 @@ int main(int, char**) test2 = 0; { std::unique_locklk(mut); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_pred.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_pred.pass.cpp index c4034fc2b215d..041333e2b6338 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_pred.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_pred.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::condition_variable cv; @@ -51,7 +52,7 @@ void f() int main(int, char**) { std::unique_locklk(mut); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_until.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_until.pass.cpp index e5c77f28eb84e..c41bc5ce9132b 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_until.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_until.pass.cpp @@ -23,6 +23,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" struct TestClock @@ -83,7 +84,7 @@ void run_test() test2 = 0; { std::unique_locklk(mut); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); @@ -97,7 +98,7 @@ void run_test() test2 = 0; { std::unique_locklk(mut); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_until_pred.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_until_pred.pass.cpp index ab43bdb1a02a0..23b42daaac54d 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_until_pred.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvar/wait_until_pred.pass.cpp @@ -26,6 +26,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" struct Clock @@ -90,8 +91,8 @@ void f() int main(int, char**) { { - std::unique_locklk(mut); - std::thread t(f); + std::unique_lock lk(mut); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); @@ -104,8 +105,8 @@ int main(int, char**) test1 = 0; test2 = 0; { - std::unique_locklk(mut); - std::thread t(f); + std::unique_lock lk(mut); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/destructor.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/destructor.pass.cpp index 4b9d719ec5d77..7ac99550b11c1 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/destructor.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/destructor.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::condition_variable_any* cv; @@ -49,12 +50,12 @@ void g() int main(int, char**) { cv = new std::condition_variable_any; - std::thread th2(g); + std::thread th2 = support::make_test_thread(g); m.lock(); while (!g_ready) cv->wait(m); m.unlock(); - std::thread th1(f); + std::thread th1 = support::make_test_thread(f); th1.join(); th2.join(); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/notify_all.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/notify_all.pass.cpp index 36428bc7fc507..05825ea26c946 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/notify_all.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/notify_all.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::condition_variable_any cv; @@ -46,7 +47,7 @@ int main(int, char**) notReady = threadCount; std::vector threads(threadCount); for (unsigned i = 0; i < threadCount; i++) - threads[i] = std::thread(helper); + threads[i] = support::make_test_thread(helper); { while (notReady > 0) std::this_thread::yield(); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/notify_one.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/notify_one.pass.cpp index 60a7dd7f10f7c..66ce0fefd5537 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/notify_one.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/notify_one.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::condition_variable_any cv; @@ -56,8 +57,8 @@ void f2() int main(int, char**) { - std::thread t1(f1); - std::thread t2(f2); + std::thread t1 = support::make_test_thread(f1); + std::thread t2 = support::make_test_thread(f2); std::this_thread::sleep_for(std::chrono::milliseconds(100)); { L1 lk(m0); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait.pass.cpp index 291fcad827d98..a29fd9d7bd7c4 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::condition_variable_any cv; @@ -46,7 +47,7 @@ void f() int main(int, char**) { L1 lk(m0); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_for.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_for.pass.cpp index d89d54ace951c..26535e8a07e15 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_for.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_for.pass.cpp @@ -24,6 +24,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::condition_variable_any cv; @@ -68,7 +69,7 @@ int main(int, char**) { { L1 lk(m0); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); @@ -82,7 +83,7 @@ int main(int, char**) test2 = 0; { L1 lk(m0); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_for_pred.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_for_pred.pass.cpp index 7b91efaa950bc..75d709d36af8f 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_for_pred.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_for_pred.pass.cpp @@ -23,6 +23,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class Pred @@ -77,7 +78,7 @@ int main(int, char**) { expect_result = true; L1 lk(m0); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); @@ -92,7 +93,7 @@ int main(int, char**) { expect_result = false; L1 lk(m0); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_pred.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_pred.pass.cpp index 41bcd80794edb..d32848e3087c2 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_pred.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_pred.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::condition_variable_any cv; @@ -55,7 +56,7 @@ void f() int main(int, char**) { L1 lk(m0); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_terminates.sh.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_terminates.sh.cpp index f4bb2b71bc796..c507917b53173 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_terminates.sh.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_terminates.sh.cpp @@ -63,6 +63,8 @@ #include #include +#include "make_test_thread.h" + void my_terminate() { std::_Exit(0); // Use _Exit to prevent cleanup from taking place. } @@ -118,7 +120,7 @@ int main(int argc, char **argv) { try { mut.lock(); assert(pred == false); - std::thread(signal_me).detach(); + support::make_test_thread(signal_me).detach(); switch (id) { case 1: cv.wait(mut); break; case 2: cv.wait(mut, pred_function); break; diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_until.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_until.pass.cpp index de48880c7683c..8054f0248e8cb 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_until.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_until.pass.cpp @@ -22,6 +22,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" struct Clock @@ -81,7 +82,7 @@ int main(int, char**) { { L1 lk(m0); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); @@ -95,7 +96,7 @@ int main(int, char**) test2 = 0; { L1 lk(m0); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); diff --git a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_until_pred.pass.cpp b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_until_pred.pass.cpp index 1c3e5814d0935..74d18d0d7e0cb 100644 --- a/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_until_pred.pass.cpp +++ b/libcxx/test/std/thread/thread.condition/thread.condition.condvarany/wait_until_pred.pass.cpp @@ -26,6 +26,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" struct Clock @@ -95,7 +96,7 @@ int main(int, char**) { { L1 lk(m0); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); @@ -109,7 +110,7 @@ int main(int, char**) test2 = 0; { L1 lk(m0); - std::thread t(f); + std::thread t = support::make_test_thread(f); assert(test1 == 0); while (test1 == 0) cv.wait(lk); diff --git a/libcxx/test/std/thread/thread.latch/arrive_and_wait.pass.cpp b/libcxx/test/std/thread/thread.latch/arrive_and_wait.pass.cpp index c4c4b2ea04320..b11d46bbffd97 100644 --- a/libcxx/test/std/thread/thread.latch/arrive_and_wait.pass.cpp +++ b/libcxx/test/std/thread/thread.latch/arrive_and_wait.pass.cpp @@ -25,13 +25,14 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int main(int, char**) { std::latch l(2); - std::thread t([&](){ + std::thread t = support::make_test_thread([&](){ l.arrive_and_wait(); }); l.arrive_and_wait(); diff --git a/libcxx/test/std/thread/thread.latch/count_down.pass.cpp b/libcxx/test/std/thread/thread.latch/count_down.pass.cpp index 336b32102cd27..9043dc145599a 100644 --- a/libcxx/test/std/thread/thread.latch/count_down.pass.cpp +++ b/libcxx/test/std/thread/thread.latch/count_down.pass.cpp @@ -25,6 +25,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int main(int, char**) @@ -32,7 +33,7 @@ int main(int, char**) std::latch l(2); l.count_down(); - std::thread t([&](){ + std::thread t = support::make_test_thread([&](){ l.count_down(); }); l.wait(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex.pass.cpp index cfffafdce822f..3e3560c7e9831 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex.pass.cpp @@ -31,6 +31,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" typedef std::chrono::system_clock Clock; @@ -82,7 +83,7 @@ int main(int, char**) { m.lock(); for (int i = 0; i < 5; ++i) - v.push_back(std::thread(f)); + v.push_back(support::make_test_thread(f)); std::this_thread::sleep_for(WaitTime); m.unlock(); for (auto& t : v) @@ -91,8 +92,8 @@ int main(int, char**) { m.lock_shared(); for (auto& t : v) - t = std::thread(g); - std::thread q(f); + t = support::make_test_thread(g); + std::thread q = support::make_test_thread(f); std::this_thread::sleep_for(WaitTime); m.unlock_shared(); for (auto& t : v) diff --git a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_duration.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_duration.pass.cpp index 31643071f1fd6..811f4727c9bb4 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_duration.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_duration.pass.cpp @@ -27,6 +27,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -75,7 +76,7 @@ int main(int, char**) m.lock(); std::vector v; for (unsigned i = 0; i < Threads; ++i) - v.push_back(std::thread(f1)); + v.push_back(support::make_test_thread(f1)); while (CountDown > 0) std::this_thread::yield(); // Give one more chance for threads to block and wait for the mutex. @@ -89,7 +90,7 @@ int main(int, char**) m.lock(); std::vector v; for (unsigned i = 0; i < Threads; ++i) - v.push_back(std::thread(f2)); + v.push_back(support::make_test_thread(f2)); for (auto& t : v) t.join(); m.unlock(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_time_point.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_time_point.pass.cpp index f0081c2c2dd85..eb31b2572287c 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_time_point.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_time_point.pass.cpp @@ -27,6 +27,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -69,7 +70,7 @@ int main(int, char**) m.lock(); std::vector v; for (unsigned i = 0; i < Threads; ++i) - v.push_back(std::thread(f1)); + v.push_back(support::make_test_thread(f1)); while (CountDown > 0) std::this_thread::yield(); std::this_thread::sleep_for(ShortTime); @@ -81,7 +82,7 @@ int main(int, char**) m.lock(); std::vector v; for (unsigned i = 0; i < Threads; ++i) - v.push_back(std::thread(f2)); + v.push_back(support::make_test_thread(f2)); for (auto& t : v) t.join(); m.unlock(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_try_to_lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_try_to_lock.pass.cpp index d13eeb860fc34..c12a548281689 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_try_to_lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_try_to_lock.pass.cpp @@ -28,6 +28,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -69,7 +70,7 @@ int main(int, char**) m.lock(); std::vector v; for (int i = 0; i < 5; ++i) - v.push_back(std::thread(f)); + v.push_back(support::make_test_thread(f)); std::this_thread::sleep_for(ms(250)); m.unlock(); for (auto& t : v) diff --git a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.locking/lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.locking/lock.pass.cpp index 6db3a44c71f51..591b828a2b381 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.locking/lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.locking/lock.pass.cpp @@ -28,6 +28,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -90,7 +91,7 @@ int main(int, char**) m.lock(); std::vector v; for (int i = 0; i < 5; ++i) - v.push_back(std::thread(f)); + v.push_back(support::make_test_thread(f)); std::this_thread::sleep_for(WaitTime); m.unlock(); for (auto& t : v) diff --git a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex.pass.cpp index c9e0c671fb74e..bd25d02cfe10b 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex.pass.cpp @@ -24,6 +24,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::mutex m; @@ -49,7 +50,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex_duration.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex_duration.pass.cpp index fdc3c8b065b5e..1f4e03299417f 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex_duration.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex_duration.pass.cpp @@ -22,6 +22,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::timed_mutex m; @@ -56,14 +57,14 @@ int main(int, char**) { { m.lock(); - std::thread t(f1); + std::thread t = support::make_test_thread(f1); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); } { m.lock(); - std::thread t(f2); + std::thread t = support::make_test_thread(f2); std::this_thread::sleep_for(ms(300)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex_time_point.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex_time_point.pass.cpp index 2bac8784dbfbc..5231c593fd3c2 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex_time_point.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex_time_point.pass.cpp @@ -22,6 +22,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::timed_mutex m; @@ -56,14 +57,14 @@ int main(int, char**) { { m.lock(); - std::thread t(f1); + std::thread t = support::make_test_thread(f1); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); } { m.lock(); - std::thread t(f2); + std::thread t = support::make_test_thread(f2); std::this_thread::sleep_for(ms(300)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex_try_to_lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex_try_to_lock.pass.cpp index 7aaf5a2955a4c..1ebbb6b7e7ea2 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex_try_to_lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.cons/mutex_try_to_lock.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::mutex m; @@ -59,7 +60,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.locking/lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.locking/lock.pass.cpp index b5425a79de365..26f82520a89de 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.locking/lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.unique/thread.lock.unique.locking/lock.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::mutex m; @@ -69,7 +70,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.class/lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.class/lock.pass.cpp index 3c2d15dfd5b8a..f375b6fb7d175 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.class/lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.class/lock.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::mutex m; @@ -44,7 +45,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.class/try_lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.class/try_lock.pass.cpp index 5a6715c0c5c46..dc9d6c3ef6d9d 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.class/try_lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.class/try_lock.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::mutex m; @@ -48,7 +49,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.recursive/lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.recursive/lock.pass.cpp index 2225432aa3676..1ce9a4cde192e 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.recursive/lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.recursive/lock.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::recursive_mutex m; @@ -45,7 +46,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.recursive/try_lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.recursive/try_lock.pass.cpp index c0ab6ff5c5c5a..60a4da7864709 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.recursive/try_lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.mutex.requirements.mutex/thread.mutex.recursive/try_lock.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::recursive_mutex m; @@ -50,7 +51,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/lock.pass.cpp index aed7f6516f118..82715ace50ad2 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/lock.pass.cpp @@ -27,6 +27,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_mutex m; @@ -61,7 +62,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(WaitTime); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/lock_shared.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/lock_shared.pass.cpp index c2e7fd9bcb385..6c69c2eaa48f7 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/lock_shared.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/lock_shared.pass.cpp @@ -28,6 +28,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_mutex m; @@ -75,15 +76,15 @@ int main(int, char**) m.lock(); std::vector v; for (int i = 0; i < 5; ++i) - v.push_back(std::thread(f)); + v.push_back(support::make_test_thread(f)); std::this_thread::sleep_for(WaitTime); m.unlock(); for (auto& t : v) t.join(); m.lock_shared(); for (auto& t : v) - t = std::thread(g); - std::thread q(f); + t = support::make_test_thread(g); + std::thread q = support::make_test_thread(f); std::this_thread::sleep_for(WaitTime); m.unlock_shared(); for (auto& t : v) diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/try_lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/try_lock.pass.cpp index 9c9f09fd799f2..6f39ae442e044 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/try_lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/try_lock.pass.cpp @@ -27,6 +27,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_mutex m; @@ -54,7 +55,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/try_lock_shared.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/try_lock_shared.pass.cpp index c4e18ebb1552a..fda9485d659a3 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/try_lock_shared.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.shared_mutex.requirements/thread.shared_mutex.class/try_lock_shared.pass.cpp @@ -28,6 +28,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_mutex m; @@ -58,7 +59,7 @@ int main(int, char**) m.lock(); std::vector v; for (int i = 0; i < 5; ++i) - v.push_back(std::thread(f)); + v.push_back(support::make_test_thread(f)); std::this_thread::sleep_for(ms(250)); m.unlock(); for (auto& t : v) diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/lock.pass.cpp index e17547228f445..2b05c8c7f7d3e 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/lock.pass.cpp @@ -25,6 +25,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -54,7 +55,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); while (!ready) std::this_thread::yield(); start = Clock::now(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/lock_shared.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/lock_shared.pass.cpp index 5b711708abf5c..0d77585a12d5b 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/lock_shared.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/lock_shared.pass.cpp @@ -26,6 +26,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -76,7 +77,7 @@ int main(int, char**) m.lock(); std::vector v; for (int i = 0; i < threads; ++i) - v.push_back(std::thread(readerMustWait)); + v.push_back(support::make_test_thread(readerMustWait)); while (countDown > 0) std::this_thread::yield(); readerStart = Clock::now(); @@ -88,8 +89,8 @@ int main(int, char**) countDown.store(threads + 1); m.lock_shared(); for (auto& t : v) - t = std::thread(reader); - std::thread q(writerMustWait); + t = support::make_test_thread(reader); + std::thread q = support::make_test_thread(writerMustWait); while (countDown > 0) std::this_thread::yield(); writerStart = Clock::now(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock.pass.cpp index 910f92fdc9f4f..97fef9b67d8e5 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock.pass.cpp @@ -27,6 +27,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -54,7 +55,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_for.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_for.pass.cpp index 40b840128859f..c981f075f604c 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_for.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_for.pass.cpp @@ -28,6 +28,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -73,14 +74,14 @@ int main(int, char**) { { m.lock(); - std::thread t(f1); + std::thread t = support::make_test_thread(f1); std::this_thread::sleep_for(WaitTime); m.unlock(); t.join(); } { m.lock(); - std::thread t(f2); + std::thread t = support::make_test_thread(f2); std::this_thread::sleep_for(WaitTime + Tolerance); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_shared.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_shared.pass.cpp index 24aee00a07235..adef56ca3757a 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_shared.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_shared.pass.cpp @@ -28,6 +28,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -64,7 +65,7 @@ int main(int, char**) m.lock(); std::vector v; for (int i = 0; i < 5; ++i) - v.push_back(std::thread(f)); + v.push_back(support::make_test_thread(f)); std::this_thread::sleep_for(ms(250)); m.unlock(); for (auto& t : v) diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_shared_for.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_shared_for.pass.cpp index 77ef92663288d..06966c33c7cf4 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_shared_for.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_shared_for.pass.cpp @@ -29,6 +29,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -75,7 +76,7 @@ int main(int, char**) m.lock(); std::vector v; for (int i = 0; i < 5; ++i) - v.push_back(std::thread(f1)); + v.push_back(support::make_test_thread(f1)); std::this_thread::sleep_for(WaitTime); m.unlock(); for (auto& t : v) @@ -85,7 +86,7 @@ int main(int, char**) m.lock(); std::vector v; for (int i = 0; i < 5; ++i) - v.push_back(std::thread(f2)); + v.push_back(support::make_test_thread(f2)); std::this_thread::sleep_for(WaitTime + Tolerance); m.unlock(); for (auto& t : v) diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_shared_until.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_shared_until.pass.cpp index a9513c83cf1f0..a80fb7405c728 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_shared_until.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_shared_until.pass.cpp @@ -29,6 +29,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -72,7 +73,7 @@ int main(int, char**) m.lock(); std::vector v; for (int i = 0; i < threads; ++i) - v.push_back(std::thread(f1)); + v.push_back(support::make_test_thread(f1)); while (countDown > 0) std::this_thread::yield(); m.unlock(); @@ -83,7 +84,7 @@ int main(int, char**) m.lock(); std::vector v; for (int i = 0; i < threads; ++i) - v.push_back(std::thread(f2)); + v.push_back(support::make_test_thread(f2)); for (auto& t : v) t.join(); m.unlock(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_until.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_until.pass.cpp index edf826827c042..4413a2218e0c4 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_until.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_until.pass.cpp @@ -28,6 +28,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -73,14 +74,14 @@ int main(int, char**) { { m.lock(); - std::thread t(f1); + std::thread t = support::make_test_thread(f1); std::this_thread::sleep_for(WaitTime); m.unlock(); t.join(); } { m.lock(); - std::thread t(f2); + std::thread t = support::make_test_thread(f2); std::this_thread::sleep_for(WaitTime + Tolerance); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_until_deadlock_bug.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_until_deadlock_bug.pass.cpp index e99bb9720ddbe..7300dad7d5a28 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_until_deadlock_bug.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.sharedtimedmutex.requirements/thread.sharedtimedmutex.class/try_lock_until_deadlock_bug.pass.cpp @@ -26,6 +26,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::shared_timed_mutex m; @@ -59,10 +60,10 @@ int main(int, char**) typedef std::chrono::steady_clock Clock; m.lock_shared(); - std::thread t1(writer_one); + std::thread t1 = support::make_test_thread(writer_one); // create some readers - std::thread t2(blocked_reader); - std::thread t3(blocked_reader); + std::thread t2 = support::make_test_thread(blocked_reader); + std::thread t3 = support::make_test_thread(blocked_reader); // Kill the test after 10 seconds if it hasn't completed. auto end_point = Clock::now() + std::chrono::seconds(10); while (readers_finished != total_readers && Clock::now() < end_point) { diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/lock.pass.cpp index 782bf057ebb9c..a61fd99368f32 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/lock.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::timed_mutex m; @@ -43,7 +44,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/try_lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/try_lock.pass.cpp index 5e5eb1df82f18..30cfcaccf9dfb 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/try_lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/try_lock.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::timed_mutex m; @@ -47,7 +48,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/try_lock_for.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/try_lock_for.pass.cpp index 4eb435f4dd38e..fc757def0bbff 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/try_lock_for.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/try_lock_for.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::timed_mutex m; @@ -54,14 +55,14 @@ int main(int, char**) { { m.lock(); - std::thread t(f1); + std::thread t = support::make_test_thread(f1); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); } { m.lock(); - std::thread t(f2); + std::thread t = support::make_test_thread(f2); std::this_thread::sleep_for(ms(300)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/try_lock_until.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/try_lock_until.pass.cpp index 02bc366e9aac6..85649041c948a 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/try_lock_until.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.class/try_lock_until.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::timed_mutex m; @@ -54,14 +55,14 @@ int main(int, char**) { { m.lock(); - std::thread t(f1); + std::thread t = support::make_test_thread(f1); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); } { m.lock(); - std::thread t(f2); + std::thread t = support::make_test_thread(f2); std::this_thread::sleep_for(ms(300)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/lock.pass.cpp index 98e34370206ef..d58cee5d4a9b3 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/lock.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::recursive_timed_mutex m; @@ -45,7 +46,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/try_lock.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/try_lock.pass.cpp index 0045414ba4a26..6e36056a736d7 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/try_lock.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/try_lock.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::recursive_timed_mutex m; @@ -49,7 +50,7 @@ void f() int main(int, char**) { m.lock(); - std::thread t(f); + std::thread t = support::make_test_thread(f); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/try_lock_for.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/try_lock_for.pass.cpp index c1072432d84f2..4a9fd3ec522e0 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/try_lock_for.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/try_lock_for.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::recursive_timed_mutex m; @@ -56,14 +57,14 @@ int main(int, char**) { { m.lock(); - std::thread t(f1); + std::thread t = support::make_test_thread(f1); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); } { m.lock(); - std::thread t(f2); + std::thread t = support::make_test_thread(f2); std::this_thread::sleep_for(ms(300)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/try_lock_until.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/try_lock_until.pass.cpp index a2734d229eb6c..37e4410c0af98 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/try_lock_until.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.mutex.requirements/thread.timedmutex.requirements/thread.timedmutex.recursive/try_lock_until.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::recursive_timed_mutex m; @@ -56,14 +57,14 @@ int main(int, char**) { { m.lock(); - std::thread t(f1); + std::thread t = support::make_test_thread(f1); std::this_thread::sleep_for(ms(250)); m.unlock(); t.join(); } { m.lock(); - std::thread t(f2); + std::thread t = support::make_test_thread(f2); std::this_thread::sleep_for(ms(300)); m.unlock(); t.join(); diff --git a/libcxx/test/std/thread/thread.mutex/thread.once/thread.once.callonce/call_once.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.once/thread.once.callonce/call_once.pass.cpp index 398ee058c128e..bcc19eaed1c0f 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.once/thread.once.callonce/call_once.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.once/thread.once.callonce/call_once.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" typedef std::chrono::milliseconds ms; @@ -190,8 +191,8 @@ int main(int, char**) { // check basic functionality { - std::thread t0(f0); - std::thread t1(f0); + std::thread t0 = support::make_test_thread(f0); + std::thread t1 = support::make_test_thread(f0); t0.join(); t1.join(); assert(init0_called == 1); @@ -199,8 +200,8 @@ int main(int, char**) #ifndef TEST_HAS_NO_EXCEPTIONS // check basic exception safety { - std::thread t0(f3); - std::thread t1(f3); + std::thread t0 = support::make_test_thread(f3); + std::thread t1 = support::make_test_thread(f3); t0.join(); t1.join(); assert(init3_called == 2); @@ -209,8 +210,8 @@ int main(int, char**) #endif // check deadlock avoidance { - std::thread t0(f41); - std::thread t1(f42); + std::thread t0 = support::make_test_thread(f41); + std::thread t1 = support::make_test_thread(f42); t0.join(); t1.join(); assert(init41_called == 1); @@ -219,16 +220,16 @@ int main(int, char**) #if TEST_STD_VER >= 11 // check functors with 1 arg { - std::thread t0(f1); - std::thread t1(f1); + std::thread t0 = support::make_test_thread(f1); + std::thread t1 = support::make_test_thread(f1); t0.join(); t1.join(); assert(init1::called == 1); } // check functors with 2 args { - std::thread t0(f2); - std::thread t1(f2); + std::thread t0 = support::make_test_thread(f2); + std::thread t1 = support::make_test_thread(f2); t0.join(); t1.join(); assert(init2::called == 5); diff --git a/libcxx/test/std/thread/thread.mutex/thread.once/thread.once.callonce/race.pass.cpp b/libcxx/test/std/thread/thread.mutex/thread.once/thread.once.callonce/race.pass.cpp index 4ff0274c17a45..54d29aec3a938 100644 --- a/libcxx/test/std/thread/thread.mutex/thread.once/thread.once.callonce/race.pass.cpp +++ b/libcxx/test/std/thread/thread.mutex/thread.once/thread.once.callonce/race.pass.cpp @@ -23,6 +23,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::once_flag flg0; @@ -41,8 +42,8 @@ void f0() int main(int, char**) { - std::thread t0(f0); - std::thread t1(f0); + std::thread t0 = support::make_test_thread(f0); + std::thread t1 = support::make_test_thread(f0); t0.join(); t1.join(); assert(global == 1); diff --git a/libcxx/test/std/thread/thread.semaphore/acquire.pass.cpp b/libcxx/test/std/thread/thread.semaphore/acquire.pass.cpp index f8466ba8a9ee4..aea01f32d36b2 100644 --- a/libcxx/test/std/thread/thread.semaphore/acquire.pass.cpp +++ b/libcxx/test/std/thread/thread.semaphore/acquire.pass.cpp @@ -25,13 +25,14 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int main(int, char**) { std::counting_semaphore<> s(2); - std::thread t([&](){ + std::thread t = support::make_test_thread([&](){ s.acquire(); }); t.join(); diff --git a/libcxx/test/std/thread/thread.semaphore/binary.pass.cpp b/libcxx/test/std/thread/thread.semaphore/binary.pass.cpp index 5ef65f381eca9..55816858876c0 100644 --- a/libcxx/test/std/thread/thread.semaphore/binary.pass.cpp +++ b/libcxx/test/std/thread/thread.semaphore/binary.pass.cpp @@ -26,6 +26,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int main(int, char**) @@ -40,7 +41,7 @@ int main(int, char**) } }; - std::thread t(l); + std::thread t = support::make_test_thread(l); l(); t.join(); diff --git a/libcxx/test/std/thread/thread.semaphore/release.pass.cpp b/libcxx/test/std/thread/thread.semaphore/release.pass.cpp index 268514ce342e3..b49747b09601a 100644 --- a/libcxx/test/std/thread/thread.semaphore/release.pass.cpp +++ b/libcxx/test/std/thread/thread.semaphore/release.pass.cpp @@ -25,6 +25,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int main(int, char**) @@ -34,7 +35,7 @@ int main(int, char**) s.release(); s.acquire(); - std::thread t([&](){ + std::thread t = support::make_test_thread([&](){ s.acquire(); }); s.release(2); diff --git a/libcxx/test/std/thread/thread.semaphore/timed.pass.cpp b/libcxx/test/std/thread/thread.semaphore/timed.pass.cpp index c46dae5f9052d..281e3b47ccef2 100644 --- a/libcxx/test/std/thread/thread.semaphore/timed.pass.cpp +++ b/libcxx/test/std/thread/thread.semaphore/timed.pass.cpp @@ -26,6 +26,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int main(int, char**) @@ -37,7 +38,7 @@ int main(int, char**) assert(!s.try_acquire_until(start + std::chrono::milliseconds(250))); assert(!s.try_acquire_for(std::chrono::milliseconds(250))); - std::thread t([&](){ + std::thread t = support::make_test_thread([&](){ std::this_thread::sleep_for(std::chrono::milliseconds(250)); s.release(); std::this_thread::sleep_for(std::chrono::milliseconds(250)); diff --git a/libcxx/test/std/thread/thread.semaphore/try_acquire.pass.cpp b/libcxx/test/std/thread/thread.semaphore/try_acquire.pass.cpp index 45cdcd48e2ea1..9b387c95e3af5 100644 --- a/libcxx/test/std/thread/thread.semaphore/try_acquire.pass.cpp +++ b/libcxx/test/std/thread/thread.semaphore/try_acquire.pass.cpp @@ -25,6 +25,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" int main(int, char**) @@ -35,7 +36,7 @@ int main(int, char**) s.release(); assert(s.try_acquire()); s.release(2); - std::thread t([&](){ + std::thread t = support::make_test_thread([&](){ assert(s.try_acquire()); }); t.join(); diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.algorithm/swap.pass.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.algorithm/swap.pass.cpp index f2cbba6bda5a7..332754ae2a524 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.algorithm/swap.pass.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.algorithm/swap.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class G @@ -47,7 +48,7 @@ int main(int, char**) { { G g; - std::thread t0(g); + std::thread t0 = support::make_test_thread(g); std::thread::id id0 = t0.get_id(); std::thread t1; std::thread::id id1 = t1.get_id(); diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.assign/copy.compile.fail.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.assign/copy.compile.fail.cpp index e67ceea5db619..9d7e1044be296 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.assign/copy.compile.fail.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.assign/copy.compile.fail.cpp @@ -13,40 +13,11 @@ // thread& operator=(thread&& t); #include -#include -#include -#include - -class G -{ - int alive_; -public: - static int n_alive; - static bool op_run; - - G() : alive_(1) {++n_alive;} - G(const G& g) : alive_(g.alive_) {++n_alive;} - ~G() {alive_ = 0; --n_alive;} - - void operator()() - { - assert(alive_ == 1); - assert(n_alive >= 1); - op_run = true; - } - -}; - -int G::n_alive = 0; -bool G::op_run = false; int main(int, char**) { - { - std::thread t0(G()); - std::thread t1; - t1 = t0; - } - - return 0; + std::thread t0; + std::thread t1; + t0 = t1; + return 0; } diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.assign/move.pass.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.assign/move.pass.cpp index c2104752d0abb..371d8266dc2a7 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.assign/move.pass.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.assign/move.pass.cpp @@ -18,6 +18,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class G @@ -51,7 +52,7 @@ int main(int, char**) assert(G::n_alive == 1); assert(!G::op_run); - std::thread t0(g); + std::thread t0 = support::make_test_thread(g); std::thread::id id = t0.get_id(); std::thread t1; diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.assign/move2.pass.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.assign/move2.pass.cpp index 27cbf3a466939..ccae438018c22 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.assign/move2.pass.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.assign/move2.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" struct G @@ -37,7 +38,7 @@ int main(int, char**) std::set_terminate(f1); { G g; - std::thread t0(g); + std::thread t0 = support::make_test_thread(g); std::thread t1; t0 = std::move(t1); assert(false); diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/constr.compile.fail.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/constr.compile.fail.cpp index 26231373f80c3..dd472f0790445 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/constr.compile.fail.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/constr.compile.fail.cpp @@ -16,12 +16,10 @@ #include -#include int main(int, char**) { volatile std::thread t1; std::thread t2 ( t1, 1, 2.0 ); - - return 0; + return 0; } diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/copy.compile.fail.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/copy.compile.fail.cpp index 2a3632cd42fb6..f0e288b3c19c4 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/copy.compile.fail.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/copy.compile.fail.cpp @@ -13,55 +13,10 @@ // thread(const thread&) = delete; #include -#include -#include -#include - -class G -{ - int alive_; -public: - static int n_alive; - static bool op_run; - - G() : alive_(1) {++n_alive;} - G(const G& g) : alive_(g.alive_) {++n_alive;} - ~G() {alive_ = 0; --n_alive;} - - void operator()() - { - assert(alive_ == 1); - assert(n_alive >= 1); - op_run = true; - } - - void operator()(int i, double j) - { - assert(alive_ == 1); - assert(n_alive >= 1); - assert(i == 5); - assert(j == 5.5); - op_run = true; - } -}; - -int G::n_alive = 0; -bool G::op_run = false; int main(int, char**) { - { - assert(G::n_alive == 0); - assert(!G::op_run); - std::thread t0(G(), 5, 5.5); - std::thread::id id = t0.get_id(); - std::thread t1 = t0; - assert(t1.get_id() == id); - assert(t0.get_id() == std::thread::id()); - t1.join(); - assert(G::n_alive == 0); - assert(G::op_run); - } - - return 0; + std::thread t0; (void)t0; + std::thread t1(t0); (void)t1; + return 0; } diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/move.pass.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/move.pass.cpp index 55265cce9f933..3611fc623d141 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/move.pass.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr/move.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class G @@ -52,7 +53,7 @@ int main(int, char**) assert(G::n_alive == 1); assert(!G::op_run); - std::thread t0(g); + std::thread t0 = support::make_test_thread(g); std::thread::id id = t0.get_id(); std::thread t1 = std::move(t0); diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.destr/dtor.pass.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.destr/dtor.pass.cpp index 34e0e51b1200a..1af063c02e07c 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.destr/dtor.pass.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.destr/dtor.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class G @@ -57,7 +58,7 @@ int main(int, char**) assert(!G::op_run); G g; { - std::thread t(g); + std::thread t = support::make_test_thread(g); std::this_thread::sleep_for(std::chrono::milliseconds(250)); } } diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/detach.pass.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/detach.pass.cpp index bf72e3437a473..ea82d5392aeb6 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/detach.pass.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/detach.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" std::atomic_bool done(false); @@ -65,7 +66,7 @@ int main(int, char**) { { G g; - std::thread t0(g); + std::thread t0 = support::make_test_thread(g); assert(t0.joinable()); t0.detach(); assert(!t0.joinable()); @@ -76,7 +77,7 @@ int main(int, char**) assert(G::n_alive == 0); #ifndef TEST_HAS_NO_EXCEPTIONS { - std::thread t0(foo); + std::thread t0 = support::make_test_thread(foo); assert(t0.joinable()); t0.detach(); assert(!t0.joinable()); diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/get_id.pass.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/get_id.pass.cpp index 676666c342623..314b1e072deb9 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/get_id.pass.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/get_id.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class G @@ -47,7 +48,7 @@ int main(int, char**) { { G g; - std::thread t0(g); + std::thread t0 = support::make_test_thread(g); std::thread::id id0 = t0.get_id(); std::thread t1; std::thread::id id1 = t1.get_id(); diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/join.pass.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/join.pass.cpp index b64a111c6be74..184b931dff84d 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/join.pass.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/join.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class G @@ -50,7 +51,7 @@ int main(int, char**) { { G g; - std::thread t0(g); + std::thread t0 = support::make_test_thread(g); assert(t0.joinable()); t0.join(); assert(!t0.joinable()); @@ -64,7 +65,7 @@ int main(int, char**) } #ifndef TEST_HAS_NO_EXCEPTIONS { - std::thread t0(foo); + std::thread t0 = support::make_test_thread(foo); t0.detach(); try { t0.join(); diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/joinable.pass.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/joinable.pass.cpp index a2ffe8bb19a26..d3c1405c5a153 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/joinable.pass.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/joinable.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class G @@ -47,7 +48,7 @@ int main(int, char**) { { G g; - std::thread t0(g); + std::thread t0 = support::make_test_thread(g); assert(t0.joinable()); t0.join(); assert(!t0.joinable()); diff --git a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/swap.pass.cpp b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/swap.pass.cpp index a1ab4781d95a2..f390899aa5d33 100644 --- a/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/swap.pass.cpp +++ b/libcxx/test/std/thread/thread.threads/thread.thread.class/thread.thread.member/swap.pass.cpp @@ -19,6 +19,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" class G @@ -47,7 +48,7 @@ int main(int, char**) { { G g; - std::thread t0(g); + std::thread t0 = support::make_test_thread(g); std::thread::id id0 = t0.get_id(); std::thread t1; std::thread::id id1 = t1.get_id(); diff --git a/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate.pass.cpp b/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate.pass.cpp index ab354f42a1d82..e42277828750c 100644 --- a/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate.pass.cpp +++ b/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// UNSUPPORTED: gcc-8, gcc-9 + // // template diff --git a/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate_hint.pass.cpp b/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate_hint.pass.cpp index 5cdb5e070bed9..0960285ed5438 100644 --- a/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate_hint.pass.cpp +++ b/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate_hint.pass.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: clang-8 +// UNSUPPORTED: gcc-8, gcc-9 // diff --git a/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/construct.pass.cpp b/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/construct.pass.cpp index a3465ff22d66f..6015a6150b4b0 100644 --- a/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/construct.pass.cpp +++ b/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/construct.pass.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: clang-8 +// UNSUPPORTED: gcc-8, gcc-9 // diff --git a/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/deallocate.pass.cpp b/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/deallocate.pass.cpp index 2f153eedc6fcd..a23345942db7d 100644 --- a/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/deallocate.pass.cpp +++ b/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/deallocate.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// UNSUPPORTED: gcc-8, gcc-9 + // // template diff --git a/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/destroy.pass.cpp b/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/destroy.pass.cpp index 6d7b0bd5c44c8..e85813b3ebf29 100644 --- a/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/destroy.pass.cpp +++ b/libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/destroy.pass.cpp @@ -7,6 +7,8 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: clang-8 +// constexpr destructors are only supported starting with gcc 10 +// UNSUPPORTED: gcc-8, gcc-9 // diff --git a/libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.pass.cpp b/libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.pass.cpp index a528bf20273a8..2f6bd0a830682 100644 --- a/libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.pass.cpp +++ b/libcxx/test/std/utilities/memory/default.allocator/allocator.members/allocate.pass.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: clang-8 +// UNSUPPORTED: gcc-8, gcc-9 // diff --git a/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/destroy.pass.cpp b/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/destroy.pass.cpp index bac1da6b2b0d0..d9998c7d0429d 100644 --- a/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/destroy.pass.cpp +++ b/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/destroy.pass.cpp @@ -9,6 +9,8 @@ // UNSUPPORTED: c++03, c++11, c++14 // constexpr destructors are only supported starting with clang 10 // UNSUPPORTED: clang-5, clang-6, clang-7, clang-8, clang-9 +// constexpr destructors are only supported starting with gcc 10 +// UNSUPPORTED: gcc-8, gcc-9 // diff --git a/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/destroy_at.pass.cpp b/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/destroy_at.pass.cpp index e15bf757f04c0..50c43a10dfbc3 100644 --- a/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/destroy_at.pass.cpp +++ b/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/destroy_at.pass.cpp @@ -9,6 +9,8 @@ // UNSUPPORTED: c++03, c++11, c++14 // constexpr destructors are only supported starting with clang 10 // UNSUPPORTED: clang-5, clang-6, clang-7, clang-8, clang-9 +// constexpr destructors are only supported starting with gcc 10 +// UNSUPPORTED: gcc-8, gcc-9 // diff --git a/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/destroy_n.pass.cpp b/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/destroy_n.pass.cpp index 33dd1910bf8ea..54b1633d096fe 100644 --- a/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/destroy_n.pass.cpp +++ b/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.destroy/destroy_n.pass.cpp @@ -9,6 +9,8 @@ // UNSUPPORTED: c++03, c++11, c++14 // constexpr destructors are only supported starting with clang 10 // UNSUPPORTED: clang-5, clang-6, clang-7, clang-8, clang-9 +// constexpr destructors are only supported starting with gcc 10 +// UNSUPPORTED: gcc-8, gcc-9 // diff --git a/libcxx/test/std/utilities/meta/meta.trans/meta.trans.other/result_of11.pass.cpp b/libcxx/test/std/utilities/meta/meta.trans/meta.trans.other/result_of11.pass.cpp index c9123fe18881a..844e11eef7bbf 100644 --- a/libcxx/test/std/utilities/meta/meta.trans/meta.trans.other/result_of11.pass.cpp +++ b/libcxx/test/std/utilities/meta/meta.trans/meta.trans.other/result_of11.pass.cpp @@ -19,7 +19,7 @@ // Ignore warnings about volatile in parameters being deprecated. // We know it is, but we still have to test it. -#if defined(__GNUC__) && !defined(__clang__) +#if defined(__GNUC__) && (__GNUC__ >= 10) && !defined(__clang__) # pragma GCC diagnostic ignored "-Wvolatile" #endif diff --git a/libcxx/test/std/utilities/variant/variant.visit/robust_against_adl.pass.cpp b/libcxx/test/std/utilities/variant/variant.visit/robust_against_adl.pass.cpp new file mode 100644 index 0000000000000..af3cd759dbefd --- /dev/null +++ b/libcxx/test/std/utilities/variant/variant.visit/robust_against_adl.pass.cpp @@ -0,0 +1,46 @@ +// -*- C++ -*- +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14 + +// Throwing bad_variant_access is supported starting in macosx10.13 +// XFAIL: with_system_cxx_lib=macosx10.12 && !no-exceptions +// XFAIL: with_system_cxx_lib=macosx10.11 && !no-exceptions +// XFAIL: with_system_cxx_lib=macosx10.10 && !no-exceptions +// XFAIL: with_system_cxx_lib=macosx10.9 && !no-exceptions + +// +// template +// constexpr see below visit(Visitor&& vis, Variants&&... vars); + +#include + +#include "test_macros.h" + +struct Incomplete; +template struct Holder { T t; }; + +constexpr bool test(bool do_it) +{ + if (do_it) { + std::variant*, int> v = nullptr; + std::visit([](auto){}, v); + std::visit([](auto) -> Holder* { return nullptr; }, v); + } + return true; +} + +int main(int, char**) +{ + test(true); +#if TEST_STD_VER > 17 + static_assert(test(true)); +#endif + return 0; +} diff --git a/libcxx/test/support/filesystem_test_helper.h b/libcxx/test/support/filesystem_test_helper.h index 840c6aa3ce518..81366580db89d 100644 --- a/libcxx/test/support/filesystem_test_helper.h +++ b/libcxx/test/support/filesystem_test_helper.h @@ -184,7 +184,9 @@ struct scoped_test_env filename = sanitize_path(std::move(filename)); - if (size > std::numeric_limits::max()) { + if (size > + static_cast::type>( + std::numeric_limits::max())) { fprintf(stderr, "create_file(%s, %ju) too large\n", filename.c_str(), size); abort(); diff --git a/libcxx/test/support/make_test_thread.h b/libcxx/test/support/make_test_thread.h new file mode 100644 index 0000000000000..3366d126ae220 --- /dev/null +++ b/libcxx/test/support/make_test_thread.h @@ -0,0 +1,23 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#ifndef TEST_SUPPORT_MAKE_TEST_THREAD_H +#define TEST_SUPPORT_MAKE_TEST_THREAD_H + +#include +#include + +namespace support { + +template +std::thread make_test_thread(F&& f, Args&& ...args) { + return std::thread(std::forward(f), std::forward(args)...); +} + +} // end namespace support + +#endif // TEST_SUPPORT_MAKE_TEST_THREAD_H diff --git a/libcxx/utils/ci/Dockerfile b/libcxx/utils/ci/Dockerfile index d9cd5d9b206a0..21fb7ff535e8d 100644 --- a/libcxx/utils/ci/Dockerfile +++ b/libcxx/utils/ci/Dockerfile @@ -45,7 +45,7 @@ ENV DEBIAN_FRONTEND=noninteractive RUN apt-get update && apt-get install -y bash curl # Install various tools used by the build or the test suite -RUN apt-get update && apt-get install -y ninja-build python3 python3-sphinx git gdb +RUN apt-get update && apt-get install -y ninja-build python3 python3-sphinx python3-distutils git gdb # Install the most recently released LLVM RUN apt-get update && apt-get install -y lsb-release wget software-properties-common diff --git a/libcxx/utils/ci/macos-ci-setup b/libcxx/utils/ci/macos-ci-setup index ac9f5951b2f00..fbd596c10fa84 100755 --- a/libcxx/utils/ci/macos-ci-setup +++ b/libcxx/utils/ci/macos-ci-setup @@ -10,7 +10,7 @@ source secrets.env /bin/bash -c "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/master/install.sh)" # Install the required tools to run CI -brew install sphinx-doc python3 buildkite-agent ninja cmake +brew install sphinx-doc python3 ninja cmake buildkite/buildkite/buildkite-agent CFG_DIR="$(brew --prefix)/etc/buildkite-agent" diff --git a/libcxx/utils/ci/run-buildbot b/libcxx/utils/ci/run-buildbot index 5a6ea64db62ac..a9b49d4384e3e 100755 --- a/libcxx/utils/ci/run-buildbot +++ b/libcxx/utils/ci/run-buildbot @@ -88,6 +88,13 @@ function check-cxx-cxxabi() { ninja -C "${BUILD_DIR}" install-cxx install-cxxabi } +# TODO: The goal is to test this against all configurations. We should also move +# this to the Lit test suite instead of being a separate CMake target. +function check-abi-list() { + echo "+++ Running the libc++ ABI list test" + ninja -C "${BUILD_DIR}" check-cxx-abilist +} + function check-cxx-benchmarks() { echo "--- Running the benchmarks" ninja -C "${BUILD_DIR}" check-cxx-benchmarks @@ -100,6 +107,7 @@ generic-cxx03) clean generate-cmake -C "${MONOREPO_ROOT}/libcxx/cmake/caches/Generic-cxx03.cmake" check-cxx-cxxabi + check-abi-list ;; generic-cxx11) export CC=clang @@ -107,6 +115,7 @@ generic-cxx11) clean generate-cmake -C "${MONOREPO_ROOT}/libcxx/cmake/caches/Generic-cxx11.cmake" check-cxx-cxxabi + check-abi-list ;; generic-cxx14) export CC=clang @@ -114,6 +123,7 @@ generic-cxx14) clean generate-cmake -C "${MONOREPO_ROOT}/libcxx/cmake/caches/Generic-cxx14.cmake" check-cxx-cxxabi + check-abi-list ;; generic-cxx17) export CC=clang @@ -121,6 +131,7 @@ generic-cxx17) clean generate-cmake -C "${MONOREPO_ROOT}/libcxx/cmake/caches/Generic-cxx17.cmake" check-cxx-cxxabi + check-abi-list ;; generic-cxx2a) export CC=clang @@ -128,6 +139,7 @@ generic-cxx2a) clean generate-cmake -C "${MONOREPO_ROOT}/libcxx/cmake/caches/Generic-cxx2a.cmake" check-cxx-cxxabi + check-abi-list ;; generic-noexceptions) export CC=clang diff --git a/libcxx/utils/generate_feature_test_macro_components.py b/libcxx/utils/generate_feature_test_macro_components.py index 06eb57d8b3fc2..22389f85f4ad9 100755 --- a/libcxx/utils/generate_feature_test_macro_components.py +++ b/libcxx/utils/generate_feature_test_macro_components.py @@ -410,6 +410,10 @@ def add_version_header(tc): "unimplemented": True, "depends": "!defined(_LIBCPP_HAS_NO_THREADS)", "internal_depends": "!defined(_LIBCPP_HAS_NO_THREADS)", + }, { + "name": "__cpp_lib_int_pow2", + "values": { "c++2a": int(202002) }, + "headers": ["bit"], }, { "name": "__cpp_lib_interpolate", "values": { "c++2a": int(201902) }, diff --git a/libcxx/utils/libcxx/test/features.py b/libcxx/utils/libcxx/test/features.py index f78db66f49ad4..3023caeea5d3e 100644 --- a/libcxx/utils/libcxx/test/features.py +++ b/libcxx/utils/libcxx/test/features.py @@ -40,13 +40,23 @@ Feature(name='has-fobjc-arc', when=lambda cfg: hasCompileFlag(cfg, '-xobjective-c++ -fobjc-arc') and sys.platform.lower().strip() == 'darwin'), # TODO: this doesn't handle cross-compiling to Apple platforms. Feature(name='objective-c++', when=lambda cfg: hasCompileFlag(cfg, '-xobjective-c++ -fobjc-arc')), - Feature(name='modules-support', when=lambda cfg: hasCompileFlag(cfg, '-fmodules')), - Feature(name='non-lockfree-atomics', when=lambda cfg: sourceBuilds(cfg, """ - #include - struct Large { int storage[100]; }; - std::atomic x; - int main(int, char**) { return x.load(), x.is_lock_free(); } - """)), + + # Note: We use a custom modules cache path to make sure that we don't reuse + # the default one, which can be shared across builds. This is important + # because we define macros in headers files, and a change in these macros + # doesn't seem to invalidate modules cache entries, which means we could + # build against now-invalid cached headers from a previous build. + Feature(name='modules-support', + when=lambda cfg: hasCompileFlag(cfg, '-fmodules'), + actions=lambda cfg: [AddCompileFlag('-fmodules-cache-path=%t/ModuleCache')]), + + Feature(name='non-lockfree-atomics', + when=lambda cfg: sourceBuilds(cfg, """ + #include + struct Large { int storage[100]; }; + std::atomic x; + int main(int, char**) { return x.load(), x.is_lock_free(); } + """)), Feature(name='apple-clang', when=_isAppleClang), Feature(name=lambda cfg: 'apple-clang-{__clang_major__}'.format(**compilerMacros(cfg)), when=_isAppleClang), diff --git a/libcxx/www/cxx1y_status.html b/libcxx/www/cxx1y_status.html index 7c62dc5ec5462..5370b14babea6 100644 --- a/libcxx/www/cxx1y_status.html +++ b/libcxx/www/cxx1y_status.html @@ -1,277 +1,14 @@ - - - + + - - libc++ C++14 Status - - + + + + libc++ C++14 Status - - - -
- -

libc++ C++14 Status

- - -

In April 2013, the C++ standard committee approved the draft for the next version of the C++ standard, initially known as "C++1y".

-

The draft standard includes papers and issues that were voted on at the previous three meetings (Kona, Portland, and Bristol)

-

In August 2014, this draft was approved by ISO as C++14

-

This page shows the status of libc++; the status of clang's support of the language features is here.

- -

The groups that have contributed papers: -

    -
  • CWG - Core Language Working group
    • -
  • LWG - Library working group
    • -
  • SG1 - Study group #1 (Concurrency working group)
    • -
-

- -

Paper Status

-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Paper #GroupPaper NameMeetingStatusFirst released version
3346LWGTerminology for Container Element Requirements - Rev 1KonaComplete3.4
3421LWGMaking Operator Functors greater<>PortlandComplete3.4
3462LWGstd::result_of and SFINAEPortlandComplete3.4
3469LWGConstexpr Library Additions: chrono, v3PortlandComplete3.4
3470LWGConstexpr Library Additions: containers, v2PortlandComplete3.4
3471LWGConstexpr Library Additions: utilities, v3PortlandComplete3.4
3302LWGConstexpr Library Additions: complex, v2PortlandComplete3.4
3545LWGAn Incremental Improvement to integral_constantBristolComplete3.4
3644LWGNull Forward IteratorsBristolComplete3.4
3668LWGstd::exchange()BristolComplete3.4
3658LWGCompile-time integer sequencesBristolComplete3.4
3670LWGAddressing Tuples by TypeBristolComplete3.4
3671LWGMaking non-modifying sequence operations more robustBristolComplete3.4
3656LWGmake_uniqueBristolComplete3.4
3654LWGQuoted StringsBristolComplete3.4
3642LWGUser-defined LiteralsBristolComplete3.4
3655LWGTransformationTraits Redux (excluding part 4)BristolComplete3.4
3657LWGAdding heterogeneous comparison lookup to associative containersBristolComplete3.4
3672LWGA proposal to add a utility class to represent optional objectsBristolRemoved from Draft Standardn/a
3669LWGFixing constexpr member functions without constBristolComplete3.4
3662LWGC++ Dynamic Arrays (dynarray)BristolRemoved from Draft Standardn/a
3659SG1Shared Locking in C++BristolComplete3.4
3779LWGUser-defined Literals for std::complexChicagoComplete3.4
3789LWGConstexpr Library Additions: functionalChicagoComplete3.4
3924LWGDiscouraging rand() in C++14IssaquahComplete3.5
3887LWGConsistent Metafunction AliasesIssaquahComplete3.5
3891SG1A proposal to rename shared_mutex to shared_timed_mutexIssaquahComplete3.5
- -

Library Working group Issues Status

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Issue #Issue NameMeetingStatus
1214Insufficient/inconsistent key immutability requirements for associative containersKonaComplete
2009Reporting out-of-bound values on numeric string conversionsKonaComplete
2010is_* traits for binding operations can't be meaningfully specializedKonaComplete
2015Incorrect pre-conditions for some type traitsKonaComplete
2021Further incorrect usages of result_ofKonaComplete
2028messages_base::catalog overspecifiedKonaComplete
2033Preconditions of reserve, shrink_to_fit, and resize functionsKonaComplete
2039Issues with std::reverse and std::copy_ifKonaComplete
2044No definition of "Stable" for copy algorithmsKonaComplete
2045forward_list::merge and forward_list::splice_after with unequal allocatorsKonaComplete
2047Incorrect "mixed" move-assignment semantics of unique_ptrKonaComplete
2050Unordered associative containers do not use allocator_traits to define member typesKonaComplete
2053Errors in regex bitmask typesKonaComplete
2061make_move_iterator and arraysKonaComplete
2064More noexcept issues in basic_stringKonaComplete
2065Minimal allocator interfaceKonaComplete
2067packaged_task should have deleted copy c'tor with const parameterKonaComplete
2069Inconsistent exception spec for basic_string move constructorKonaComplete
2096Incorrect constraints of future::get in regard to MoveAssignableKonaComplete
2102Why is std::launch an implementation-defined type?KonaComplete
2071std::valarray move-assignmentPortlandComplete
2074Off by one error in std::reverse_copyPortlandComplete
2081Allocator requirements should include CopyConstructiblePortlandComplete
2083const-qualification on weak_ptr::owner_beforePortlandComplete
2086Overly generic type support for math functionsPortlandComplete
2099Unnecessary constraints of va_start() usagePortlandComplete
2103std::allocator_traits<std::allocator<T>>::propagate_on_container_move_assignmentPortlandComplete
2105Inconsistent requirements on const_iterator's value_typePortlandComplete
2110remove can't swap but note says it mightPortlandComplete
2123merge() allocator requirements for lists versus forward listsPortlandComplete
2005unordered_map::insert(T&&) protection should apply to map tooPortlandComplete
2011Unexpected output required of stringsPortlandComplete
2048Unnecessary mem_fn overloadsPortlandComplete
2049is_destructible is underspecifiedPortlandComplete
2056future_errc enums start with value 0 (invalid value for broken_promise)PortlandComplete
2058valarray and begin/endPortlandComplete
2091Misplaced effect in m.try_lock_for()BristolComplete
2092Vague Wording for condition_variable_anyBristolComplete
2093Throws clause of condition_variable::wait with predicateBristolComplete
2094duration conversion overflow shouldn't participate in overload resolutionBristolComplete
2122merge() stability for lists versus forward listsBristolComplete
2128Absence of global functions cbegin/cendBristolComplete
2145error_category default constructorBristolComplete
2147Unclear hint type in Allocator's allocate functionBristolComplete
2148Hashing enums should be supported directly by std::hashBristolComplete
2149Concerns about 20.8/5BristolComplete
2162allocator_traits::max_size missing noexceptBristolComplete
2163nth_element requires inconsistent post-conditionsBristolComplete
2169Missing reset() requirements in unique_ptr specializationBristolComplete
2172Does atomic_compare_exchange_* accept v == nullptr arguments?BristolComplete
2080Specify when once_flag becomes invalidBristolComplete
2098promise throws clausesBristolComplete
2109Incorrect requirements for hash specializationsBristolComplete
2130missing ordering constraints for fencesBristolComplete
2138atomic_flag::clear ordering constraintsBristolComplete
2140notify_all_at_thread_exit synchronizationBristolComplete
2144Missing noexcept specification in type_indexBristolComplete
2174wstring_convert::converted() should be noexceptBristolComplete
2175string_convert and wbuffer_convert validityBristolComplete
2176Special members for wstring_convert and wbuffer_convertBristolComplete
2177Requirements on Copy/MoveInsertableBristolComplete
2185Missing throws clause for future/shared_future::wait_for/wait_untilBristolComplete
2187vector<bool> is missing emplace and emplace_back member functionsBristolComplete
2190ordering of condition variable operations, reflects Posix discussionBristolComplete
2196Specification of is_*[copy/move]_[constructible/assignable] unclear for non-referencable typesBristolComplete
2197Specification of is_[un]signed unclear for non-arithmetic typesBristolComplete
2200Data race avoidance for all containers, not only for sequencesBristolComplete
2203scoped_allocator_adaptor uses wrong argument types for piecewise constructionBristolComplete
2207basic_string::at should not have a Requires clauseBristolComplete
2209assign() overspecified for sequence containersBristolComplete
2210Missing allocator-extended constructor for allocator-aware containersBristolComplete
2211Replace ambiguous use of "Allocator" in container requirementsBristolComplete
2222Inconsistency in description of forward_list::splice_after single-element overloadBristolComplete
2225Unrealistic header inclusion checks requiredBristolComplete
2229Standard code conversion facets underspecifiedBristolComplete
2231DR 704 removes complexity guarantee for clear()BristolComplete
2235Undefined behavior without proper requirements on basic_string constructorsBristolComplete
2141common_type trait produces reference typesChicagoComplete
2246unique_ptr assignment effects w.r.t. deleterChicagoComplete
2247Type traits and std::nullptr_tChicagoComplete
2085Wrong description of effect 1 of basic_istream::ignoreChicagoComplete
2087iostream_category() and noexceptChicagoComplete
2143ios_base::xalloc should be thread-safeChicagoComplete
2150Unclear specification of find_endChicagoComplete
2180Exceptions from std::seed_seq operationsChicagoComplete
2194Impossible container requirements for adaptor typesChicagoComplete
2013Do library implementers have the freedom to add constexpr?ChicagoComplete
2018regex_traits::isctype Returns clause is wrongChicagoComplete
2078Throw specification of async() incompleteChicagoComplete
2097packaged_task constructors should be constrainedChicagoComplete
2100Timed waiting functions cannot timeout if launch::async policy usedChicagoComplete
2120What should async do if neither 'async' nor 'deferred' is set in policy?ChicagoComplete
2159atomic_flag initializationChicagoComplete
2275Why is forward_as_tuple not constexpr?ChicagoComplete
2284Inconsistency in allocator_traits::max_sizeChicagoComplete
2298is_nothrow_constructible is always false because of create<>ChicagoComplete
2300Redundant sections for map and multimap members should be removedChicagoComplete
NB comment: GB9 Remove gets from C++14ChicagoComplete
2135Unclear requirement for exceptions thrown in condition_variable::wait()IssaquahComplete
2291std::hash is vulnerable to collision DoS attackIssaquahComplete
2142packaged_task::operator() synchronization too broad?IssaquahComplete
2240Probable misuse of term "function scope" in [thread.condition]IssaquahComplete
2252Strong guarantee on vector::push_back() still broken with C++11?IssaquahComplete
2257Simplify container requirements with the new algorithmsIssaquahComplete
2268Setting a default argument in the declaration of a member function assign of std::basic_stringIssaquahComplete
2271regex_traits::lookup_classname specification unclearIssaquahComplete
2272quoted should use char_traits::eq for character comparisonIssaquahComplete
2278User-defined literals for Standard Library typesIssaquahComplete
2280begin / end for arrays should be constexpr and noexceptIssaquahComplete
2285make_reverse_iteratorIssaquahComplete
2299Effects of inaccessible key_compare::is_transparent type are not clearIssaquahComplete
1450Contradiction in regex_constantsIssaquahComplete
2003String exception inconsistency in erase.IssaquahComplete
2112User-defined classes that cannot be derived fromIssaquahComplete
2132std::function ambiguityIssaquahComplete
2182Container::[const_]reference types are misleadingly specifiedIssaquahComplete
2188Reverse iterator does not fully support targets that overload operator&IssaquahComplete
2193Default constructors for standard library containers are explicitIssaquahComplete
2205Problematic postconditions of regex_match and regex_searchIssaquahComplete
2213Return value of std::regex_replaceIssaquahComplete
2258a.erase(q1, q2) unable to directly return q2IssaquahComplete
2263Comparing iterators and allocator pointers with different const-characterIssaquahComplete
2293Wrong facet used by num_put::do_putIssaquahComplete
2301Why is std::tie not constexpr?IssaquahComplete
2304Complexity of count in unordered associative containersIssaquahComplete
2306match_results::reference should be value_type&, not const value_type&IssaquahComplete
2308Clarify container destructor requirements w.r.t. std::arrayIssaquahComplete
2313tuple_size should always derive from integral_constantIssaquahComplete
2314apply() should return decltype(auto) and use decay_t before tuple_sizeIssaquahComplete
2315weak_ptr should be movableIssaquahComplete
2316weak_ptr::lock() should be atomicIssaquahComplete
2317The type property queries should be UnaryTypeTraits returning size_tIssaquahComplete
2320select_on_container_copy_construction() takes allocators, not containersIssaquahComplete
2322Associative(initializer_list, stuff) constructors are underspecifiedIssaquahComplete
2323vector::resize(n, t)'s specification should be simplifiedIssaquahComplete
2324Insert iterator constructors should use addressof()IssaquahComplete
2329regex_match()/regex_search() with match_results should forbid temporary stringsIssaquahComplete
2330regex("meow", regex::icase) is technically forbidden but should be permittedIssaquahComplete
2332regex_iterator/regex_token_iterator should forbid temporary regexesIssaquahComplete
2339Wording issue in nth_elementIssaquahComplete
2341Inconsistency between basic_ostream::seekp(pos) and basic_ostream::seekp(off, dir)IssaquahComplete
2344quoted()'s interaction with padding is unclearIssaquahComplete
2346integral_constant's member functions should be marked noexceptIssaquahComplete
2350min, max, and minmax should be constexprIssaquahComplete
2356Stability of erasure in unordered associative containersIssaquahComplete
2357Remaining "Assignable" requirementIssaquahComplete
2359How does regex_constants::nosubs affect basic_regex::mark_count()?IssaquahComplete
2360reverse_iterator::operator*() is unimplementableIssaquahComplete
2104unique_lock move-assignment should not be noexceptIssaquahComplete
2186Incomplete action on async/launch::deferredIssaquahComplete
2075Progress guarantees, lock-free property, and scheduling assumptionsIssaquahComplete
2288Inconsistent requirements for shared mutexesIssaquahComplete
- -

Last Updated: 25-Mar-2014

- + If you are not redirected automatically, follow this link to new documentation. diff --git a/libcxx/www/cxx1z_status.html b/libcxx/www/cxx1z_status.html index e5130c0ae2f7a..20e717be35fde 100644 --- a/libcxx/www/cxx1z_status.html +++ b/libcxx/www/cxx1z_status.html @@ -1,509 +1,14 @@ - - - + + - - libc++ C++17 Status - - + + + + libc++ C++17 Status - - - -
- -

libc++ C++17 Status

- - -

In November 2014, the C++ standard committee created a draft for the next version of the C++ standard, initially known as "C++1z".

-

In February 2017, the C++ standard committee approved this draft, and sent it to ISO for approval as C++17

-

This page shows the status of libc++; the status of clang's support of the language features is here.

- -

Reminder: Features in unreleased drafts of the standard are subject to change.

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The groups that have contributed papers: -

    -
  • LWG - Library working group
    • -
  • CWG - Core Language Working group
    • -
  • SG1 - Study group #1 (Concurrency working group)
    • -
-

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Paper Status

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Paper #GroupPaper NameMeetingStatusFirst released version
N3911LWGTransformationTrait Alias void_t.UrbanaComplete3.6
N4089LWGSafe conversions in unique_ptr<T[]>.UrbanaIn progress3.9
N4169LWGA proposal to add invoke function templateUrbanaComplete3.7
N4190LWGRemoving auto_ptr, random_shuffle(), And Old Stuff.UrbanaIn progress
N4258LWGCleaning-up noexcept in the Library.UrbanaIn progress3.7
N4259CWGWording for std::uncaught_exceptionsUrbanaComplete3.7
N4277LWGTriviallyCopyable reference_wrapper.UrbanaComplete3.2
N4279LWGImproved insertion interface for unique-key maps.UrbanaComplete3.7
N4280LWGNon-member size() and moreUrbanaComplete3.6
N4284LWGContiguous Iterators.UrbanaComplete3.6
N4285CWGCleanup for exception-specification and throw-expression.UrbanaComplete4.0
N4387LWGimproving pair and tupleLenexaComplete4.0
N4389LWGbool_constantLenexaComplete3.7
N4508LWGshared_mutex for C++17LenexaComplete3.7
N4366LWGLWG 2228 missing SFINAE ruleLenexaComplete3.1
N4510LWGMinimal incomplete type support for standard containers, revision 4LenexaComplete3.6
P0004R1LWGRemove Deprecated iostreams aliases.KonaComplete3.8
P0006R0LWGAdopt Type Traits Variable Templates for C++17.KonaComplete3.8
P0092R1LWGPolishing <chrono>KonaComplete3.8
P0007R1LWGConstant View: A proposal for a std::as_const helper function template.KonaComplete3.8
P0156R0LWGVariadic lock_guard(rev 3).KonaReverted in Kona3.9
P0074R0LWGMaking std::owner_less more flexibleKonaComplete3.8
P0013R1LWGLogical type traits rev 2KonaComplete3.8
P0024R2LWGThe Parallelism TS Should be StandardizedJacksonville
P0226R1LWGMathematical Special Functions for C++17Jacksonville
P0220R1LWGAdopt Library Fundamentals V1 TS Components for C++17JacksonvilleIn Progress
P0218R1LWGAdopt the File System TS for C++17JacksonvilleComplete7.0
P0033R1LWGRe-enabling shared_from_thisJacksonvilleComplete3.9
P0005R4LWGAdopt not_fn from Library Fundamentals 2 for C++17JacksonvilleComplete3.9
P0152R1LWGconstexpr atomic::is_always_lock_freeJacksonvilleComplete3.9
P0185R1LWGAdding [nothrow-]swappable traitsJacksonvilleComplete3.9
P0253R1LWGFixing a design mistake in the searchers interfaceJacksonvilleComplete3.9
P0025R0LWGAn algorithm to "clamp" a value between a pair of boundary valuesJacksonvilleComplete3.9
P0154R1LWGconstexpr std::hardware_{constructive,destructive}_interference_sizeJacksonville
P0030R1LWGProposal to Introduce a 3-Argument Overload to std::hypotJacksonvilleComplete3.9
P0031R0LWGA Proposal to Add Constexpr Modifiers to reverse_iterator, move_iterator, array and Range AccessJacksonvilleComplete4.0
P0272R1LWGGive std::string a non-const .data() member functionJacksonvilleComplete3.9
P0077R2LWGis_callable, the missing INVOKE related traitJacksonvilleComplete3.9
p0032r3LWGHomogeneous interface for variant, any and optionalOuluComplete4.0
p0040r3LWGExtending memory management toolsOuluComplete4.0
p0063r3LWGC++17 should refer to C11 instead of C99OuluComplete7.0
p0067r3LWGElementary string conversionsOuluNow P0067R5n/a
p0083r3LWGSplicing Maps and SetsOuluComplete8.0
p0084r2LWGEmplace Return TypeOuluComplete4.0
p0088r3LWGVariant: a type-safe union for C++17OuluComplete4.0
p0137r1CWGCore Issue 1776: Replacement of class objects containing reference membersOuluComplete6.0
p0163r0LWGshared_ptr::weak_typeOuluComplete3.9
p0174r2LWGDeprecating Vestigial Library Parts in C++17OuluPartial
p0175r1LWGSynopses for the C libraryOulu
p0180r2LWGReserve a New Library Namespace for Future StandardizationOuluNothing to don/a
p0181r1LWGOrdered by DefaultOuluRemoved in Konan/a
p0209r2LWGmake_from_tuple: apply for constructionOuluComplete3.9
p0219r1LWGRelative Paths for FilesystemOuluComplete7.0
p0254r2LWGIntegrating std::string_view and std::stringOuluComplete4.0
p0258r2LWGhas_unique_object_representationsOuluComplete6.0
p0295r0LWGAdopt Selected Library Fundamentals V2 Components for C++17OuluComplete4.0
p0302r1LWGRemoving Allocator Support in std::functionOuluComplete4.0
p0307r2LWGMaking Optional Greater Equal AgainOuluComplete4.0
p0336r1LWGBetter Names for Parallel Execution Policies in C++17Oulu
p0337r0LWGDelete operator= for polymorphic_allocatorOuluComplete3.9
p0346r1LWGA <random> Nomenclature TweakOuluComplete3.9
p0358r1LWGFixes for not_fnOuluComplete3.9
p0371r1LWGTemporarily discourage memory_order_consumeOuluNothing to don/a
p0392r0LWGAdapting string_view by filesystem pathsOuluComplete4.0
p0393r3LWGMaking Variant Greater EqualOuluComplete4.0
P0394r4LWGHotel Parallelifornia: terminate() for Parallel Algorithms Exception HandlingOulu
P0003R5LWGRemoving Deprecated Exception Specifications from C++17IssaquahComplete5.0
P0067R5LWGElementary string conversions, revision 5IssaquahPartially done
P0403R1LWGLiteral suffixes for basic_string_viewIssaquahComplete4.0
P0414R2LWGMerging shared_ptr changes from Library Fundamentals to C++17IssaquahComplete11.0
P0418R2LWGFail or succeed: there is no atomic latticeIssaquah
P0426R1LWGConstexpr for std::char_traitsIssaquahComplete4.0
P0435R1LWGResolving LWG Issues re common_typeIssaquahComplete4.0
P0502R0LWGThrowing out of a parallel algorithm terminates - but how?Issaquah
P0503R0LWGCorrecting library usage of "literal type"IssaquahComplete4.0
P0504R0LWGRevisiting in-place tag types for any/optional/variantIssaquahComplete4.0
P0505R0LWGWording for GB 50 - constexpr for chronoIssaquahComplete4.0
P0508R0LWGWording for GB 58 - structured bindings for node_handlesIssaquah
P0509R1LWGUpdating “Restrictions on exception handling”IssaquahNothing to don/a
P0510R0LWGDisallowing references, incomplete types, arrays, and empty variantsIssaquahComplete4.0
P0513R0LWGPoisoning the HashIssaquahComplete5.0
P0516R0LWGClarify That shared_future’s Copy Operations have Wide ContractsIssaquahComplete4.0
P0517R0LWGMake future_error ConstructibleIssaquahComplete4.0
P0521R0LWGProposed Resolution for CA 14 (shared_ptr use_count/unique)IssaquahNothing to don/a
P0156R2LWGVariadic Lock guard(rev 5)KonaComplete5.0
P0270R3CWGRemoving C dependencies from signal handler wordingKona
P0298R3CWGA byte type definitionKonaComplete5.0
P0317R1LWGDirectory Entry Caching for FilesystemKonaComplete7.0
P0430R2LWGFile system library on non-POSIX-like operating systemsKonaComplete7.0
P0433R2LWGToward a resolution of US7 and US14: Integrating template deduction for class templates into the standard libraryKonaIn progress7.0
P0452R1LWGUnifying <numeric> Parallel AlgorithmsKona
P0467R2LWGIterator Concerns for Parallel AlgorithmsKona
P0492R2LWGProposed Resolution of C++17 National Body Comments for FilesystemsKonaComplete7.0
P0518R1LWGAllowing copies as arguments to function objects given to parallel algorithms in response to CH11Kona
P0523R1LWGWording for CH 10: Complexity of parallel algorithmsKona
P0548R1LWGcommon_type and durationKonaComplete5.0
P0558R1LWGResolving atomic<T> named base class inconsistenciesKona
P0574R1LWGAlgorithm Complexity Constraints and Parallel OverloadsKona
P0599R1LWGnoexcept for hash functionsKonaComplete5.0
P0604R0LWGResolving GB 55, US 84, US 85, US 86KonaComplete
P0607R0LWGInline Variables for the Standard LibraryKonaIn Progress6.0
P0618R0LWGDeprecating <codecvt>Kona
P0623R0LWGFinal C++17 Parallel Algorithms FixesKona
P0682R1LWGRepairing elementary string conversionsToronto
P0739R0LWGSome improvements to class template argument deduction integration into the standard libraryTorontoComplete5.0
- -

The parts of P0607 that are not done are the <regex> bits.

-

So far, only the <string>, sequence containers, container adaptors and <regex> portions of P0433 have been implemented.

- -

[ Note: "Nothing to do" means that no library changes were needed to implement this change -- end note]

- -

Library Working group Issues Status

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Issue #Issue NameMeetingStatus
2016Allocators must be no-throw swappableUrbanaComplete
2118unique_ptr for array does not support cv qualification conversion of actual argumentUrbanaComplete
2170Aggregates cannot be DefaultConstructibleUrbanaComplete
2308Clarify container destructor requirements w.r.t. std::arrayUrbanaComplete
2340Replacement allocation functions declared as inlineUrbanaComplete
2354Unnecessary copying when inserting into maps with braced-init syntaxUrbanaComplete
2377std::align requirements overly strictUrbanaComplete
2396underlying_type doesn't say what to do for an incomplete enumeration typeUrbanaComplete
2399shared_ptr's constructor from unique_ptr should be constrainedUrbanaComplete
2400shared_ptr's get_deleter() should use addressof()UrbanaComplete
2401std::function needs more noexceptUrbanaComplete
2404mismatch()'s complexity needs to be updatedUrbanaComplete
2408SFINAE-friendly common_type / iterator_traits is missing in C++14UrbanaComplete
2106move_iterator wrapping iterators returning prvaluesUrbanaComplete
2129User specializations of std::initializer_listUrbanaComplete
2212tuple_size for const pair request headerUrbanaComplete
2217operator==(sub_match, string) slices on embedded '\0'sUrbanaComplete
2230"see below" for initializer_list constructors of unordered containersUrbanaComplete
2233bad_function_call::what() unhelpfulUrbanaComplete
2266vector and deque have incorrect insert requirementsUrbanaComplete
2325minmax_element()'s behavior differing from max_element()'s should be notedUrbanaComplete
2361Apply 2299 resolution throughout libraryUrbanaComplete
2365Missing noexcept in shared_ptr::shared_ptr(nullptr_t)UrbanaComplete
2376bad_weak_ptr::what() overspecifiedUrbanaComplete
2387More nested types that must be accessible and unambiguousUrbanaComplete
2059C++0x ambiguity problem with map::eraseLenexaComplete
2063Contradictory requirements for string move assignmentLenexaComplete
2076Bad CopyConstructible requirement in set constructorsLenexaComplete
2160Unintended destruction ordering-specification of resizeLenexaComplete
2168Inconsistent specification of uniform_real_distribution constructorLenexaComplete
2239min/max/minmax requirementsLenexaComplete
2364deque and vector pop_back don't specify iterator invalidation requirementsLenexaComplete
2369constexpr max(initializer_list) vs max_elementLenexaComplete
2378Behaviour of standard exception typesLenexaComplete
2403stof() should call strtof() and wcstof()LenexaComplete
2406negative_binomial_distribution should reject p == 1LenexaComplete
2407packaged_task(allocator_arg_t, const Allocator&, F&&) should neither be constrained nor explicitLenexaComplete
2411shared_ptr is only contextually convertible to boolLenexaComplete
2415Inconsistency between unique_ptr and shared_ptrLenexaComplete
2420function does not discard the return value of the target objectLenexaComplete
2425operator delete(void*, size_t) doesn't invalidate pointers sufficientlyLenexaComplete
2427Container adaptors as sequence containers, reduxLenexaComplete
2428"External declaration" used without being definedLenexaComplete
2433uninitialized_copy()/etc. should tolerate overloaded operator&LenexaComplete
2434shared_ptr::use_count() is efficientLenexaComplete
2437iterator_traits::reference can and can't be voidLenexaComplete
2438std::iterator inheritance shouldn't be mandatedLenexaComplete
2439unique_copy() sometimes can't fall back to reading its outputLenexaComplete
2440seed_seq::size() should be noexceptLenexaComplete
2442call_once() shouldn't DECAY_COPY()LenexaComplete
2448Non-normative Container destructor specificationLenexaComplete
2454Add raw_storage_iterator::base() memberLenexaComplete
2455Allocator default construction should be allowed to throwLenexaComplete
2458N3778 and new library deallocation signaturesLenexaComplete
2459std::polar should require a non-negative rhoLenexaComplete
2464try_emplace and insert_or_assign misspecifiedLenexaComplete
2467is_always_equal has slightly inconsistent defaultLenexaComplete
2470Allocator's destroy function should be allowed to fail to instantiateLenexaComplete
2482[c.strings] Table 73 mentions nonexistent functionsLenexaComplete
2488Placeholders should be allowed and encouraged to be constexprLenexaComplete
1169num_get not fully compatible with strto*KonaComplete
2072Unclear wording about capacity of temporary buffersKonaComplete
2101Some transformation types can produce impossible typesKonaComplete
2111Which unexpected/terminate handler is called from the exception handling runtime?KonaComplete
2119Missing hash specializations for extended integer typesKonaComplete
2127Move-construction with raw_storage_iteratorKonaComplete
2133Attitude to overloaded comma for iteratorsKonaComplete
2156Unordered containers' reserve(n) reserves for n-1 elementsKonaComplete
2218Unclear how containers use allocator_traits::construct()KonaComplete
2219INVOKE-ing a pointer to member with a reference_wrapper as the object expressionKonaComplete
2224Ambiguous status of access to non-live objectsKonaComplete
2234assert() should allow usage in constant expressionsKonaComplete
2244Issue on basic_istream::seekgKonaComplete
2250Follow-up On Library Issue 2207KonaComplete
2259Issues in 17.6.5.5 rules for member functionsKonaComplete
2273regex_match ambiguityKonaComplete
2336is_trivially_constructible/is_trivially_assignable traits are always falseKonaComplete
2353std::next is over-constrainedKonaComplete
2367pair and tuple are not correctly implemented for is_constructible with no argsKonaComplete
2380May <cstdlib> provide long ::abs(long) and long long ::abs(long long)?KonaComplete
2384Allocator's deallocate function needs better specificationKonaComplete
2385function::assign allocator argument doesn't make senseKonaComplete
2435reference_wrapper::operator()'s Remark should be deletedKonaComplete
2447Allocators and volatile-qualified value typesKonaComplete
2462std::ios_base::failure is overspecifiedKonaComplete
2466allocator_traits::max_size() default behavior is incorrectKonaComplete
2469Wrong specification of Requires clause of operator[] for map and unordered_mapKonaComplete
2473basic_filebuf's relation to C FILE semanticsKonaComplete
2476scoped_allocator_adaptor is not assignableKonaComplete
2477Inconsistency of wordings in std::vector::erase() and std::deque::erase()KonaComplete
2483throw_with_nested() should use is_finalKonaComplete
2484rethrow_if_nested() is doubly unimplementableKonaComplete
2485get() should be overloaded for const tuple&&KonaComplete
2486mem_fn() should be required to use perfect forwardingKonaComplete
2487bind() should be const-overloaded, not cv-overloadedKonaComplete
2489mem_fn() should be noexceptKonaComplete
2492Clarify requirements for compKonaComplete
2495There is no such thing as an Exception Safety elementKonaComplete
2192Validity and return type of std::abs(0u) is unclearJacksonvilleComplete
2276Missing requirement on std::promise::set_exceptionJacksonvilleComplete
2296std::addressof should be constexprJacksonvilleComplete (Clang Only)
2450(greater|less|greater_equal|less_equal)<void> do not yield a total order for pointersJacksonvilleComplete
2520N4089 broke initializing unique_ptr<T[]> from a nullptrJacksonvilleComplete
2522[fund.ts.v2] Contradiction in set_default_resource specificationJacksonvilleComplete
2523std::promise synopsis shows two set_value_at_thread_exit()'s for no apparent reasonJacksonvilleComplete
2537Constructors for priority_queue taking allocators should call make_heapJacksonvilleComplete
2539[fund.ts.v2] invocation_trait definition definition doesn't work for surrogate call functionsJacksonville
2545Simplify wording for bind without explicitly specified return typeJacksonvilleComplete
2557Logical operator traits are broken in the zero-argument caseJacksonvilleComplete
2558[fund.ts.v2] Logical operator traits are broken in the zero-argument caseJacksonvilleComplete
2559Error in LWG 2234's resolutionJacksonvilleComplete
2560is_constructible underspecified when applied to a function typeJacksonvilleBroken in 3.6; See r261653.
2565std::function's move constructor should guarantee nothrow for reference_wrappers and function pointersJacksonvilleComplete
2566Requirements on the first template parameter of container adaptorsJacksonvilleComplete
2571§[map.modifiers]/2 imposes nonsensical requirement on insert(InputIterator, InputIterator)JacksonvilleComplete
2572The remarks for shared_ptr::operator* should apply to cv-qualified void as wellJacksonvilleComplete
2574[fund.ts.v2] std::experimental::function::operator=(F&&) should be constrainedJacksonvilleComplete
2575[fund.ts.v2] experimental::function::assign should be removedJacksonville
2576istream_iterator and ostream_iterator should use std::addressofJacksonvilleComplete
2577{shared,unique}_lock should use std::addressofJacksonvilleComplete
2579Inconsistency wrt Allocators in basic_string assignment vs. basic_string::assignJacksonvilleComplete
2581Specialization of <type_traits> variable templates should be prohibitedJacksonvilleComplete
2582§[res.on.functions]/2's prohibition against incomplete types shouldn't apply to type traitsJacksonvilleComplete
2583There is no way to supply an allocator for basic_string(str, pos)JacksonvilleComplete
2585forward_list::resize(size_type, const value_type&) effects incorrectJacksonvilleComplete
2586Wrong value category used in scoped_allocator_adaptor::construct()JacksonvilleComplete
2590Aggregate initialization for std::arrayJacksonvilleComplete
2181Exceptions from seed sequence operationsOuluComplete
2309mutex::lock() should not throw device_or_resource_busyOuluComplete
2310Public exposition only member in std::arrayOuluComplete
2312tuple's constructor constraints need to be phrased more preciselyOuluComplete
2328Rvalue stream extraction should use perfect forwardingOuluComplete
2393std::function's Callable definition is brokenOuluComplete
2422std::numeric_limits<T>::is_modulo description: "most machines" errataOuluComplete
2426Issue about compare_exchangeOulu
2436Comparators for associative containers should always be CopyConstructibleOuluComplete
2441Exact-width atomic typedefs should be providedOuluComplete
2451[fund.ts.v2] optional should 'forward' T's implicit conversionsOuluNothing to do
2509[fund.ts.v2] any_cast doesn't work with rvalue reference targets and cannot move with a value targetOuluComplete
2516[fund.ts.v2] Public "exposition only" members in observer_ptrOulu
2542Missing const requirements for associative containersOulu
2549Tuple EXPLICIT constructor templates that take tuple parameters end up taking references to temporaries and will create dangling referencesOuluComplete
2550Wording of unordered container's clear() method complexityOuluComplete
2551[fund.ts.v2] "Exception safety" cleanup in library fundamentals requiredOuluComplete
2555[fund.ts.v2] No handling for over-aligned types in optionalOuluComplete
2573[fund.ts.v2] std::hash<std::experimental::shared_ptr> does not work for arraysOulu
2596vector::data() should use addressofOuluComplete
2667path::root_directory() description is confusingOuluComplete
2669recursive_directory_iterator effects refers to non-existent functionsOuluComplete
2670system_complete refers to undefined variable 'base'OuluComplete
2671Errors in CopyOuluComplete
2673status() effects cannot be implemented as specifiedOuluComplete
2674Bidirectional iterator requirement on path::iterator is very expensiveOuluComplete
2683filesystem::copy() says "no effects"OuluComplete
2684priority_queue lacking comparator typedefOuluComplete
2685shared_ptr deleters must not throw on move constructionOuluComplete
2687{inclusive,exclusive}_scan misspecifiedOulu
2688clamp misses preconditions and has extraneous condition on resultOuluComplete
2689Parallel versions of std::copy and std::move shouldn't be in orderOulu
2698Effect of assign() on iterators/pointers/referencesOuluComplete
2704recursive_directory_iterator's members should require '*this is dereferenceable'OuluComplete
2706Error reporting for recursive_directory_iterator::pop() is under-specifiedOuluComplete
2707path construction and assignment should have "string_type&&" overloadsOuluComplete
2709offsetof is unnecessarily impreciseOulu
2710"Effects: Equivalent to ..." doesn't count "Synchronization:" as determined semanticsOuluComplete
2711path is convertible from approximately everything under the sunOuluComplete
2716Specification of shuffle and sample disallows lvalue URNGsOuluComplete
2718Parallelism bug in [algorithms.parallel.exec] p2Oulu
2719permissions function should not be noexcept due to narrow contractOuluComplete
2720permissions function incorrectly specified for symlinksOuluComplete
2721remove_all has incorrect post conditionsOuluComplete
2723Do directory_iterator and recursive_directory_iterator become the end iterator upon error?OuluComplete
2724The protected virtual member functions of memory_resource should be privateOulu
2725filesystem::exists(const path&, error_code&) error reportingOuluComplete
2726[recursive_]directory_iterator::increment(error_code&) is underspecifiedOuluComplete
2727Parallel algorithms with constexpr specifierOulu
2728status(p).permissions() and symlink_status(p).permissions() are not specifiedOuluComplete
2062Effect contradictions w/o no-throw guarantee of std::function swapsIssaquahComplete
2166Heap property underspecified?Issaquah
2221No formatted output operator for nullptrIssaquahComplete
2223shrink_to_fit effect on iterator validityIssaquahComplete
2261Are containers required to use their 'pointer' type internally?Issaquah
2394locale::name specification unclear - what is implementation-defined?IssaquahComplete
2460LWG issue 2408 and value categoriesIssaquahComplete
2468Self-move-assignment of library typesIssaquah
2475Allow overwriting of std::basic_string terminator with charT() to allow cleaner interoperation with legacy APIsIssaquahComplete
2503multiline option should be added to syntax_option_typeIssaquahComplete
2510Tag types should not be DefaultConstructibleIssaquahComplete
2514Type traits must not be finalIssaquahComplete
2518[fund.ts.v2] Non-member swap for propagate_const should call member swapIssaquahComplete
2519Iterator operator-= has gratuitous undefined behaviourIssaquahComplete
2521[fund.ts.v2] weak_ptr's converting move constructor should be modified as well for array supportIssaquah
2525[fund.ts.v2] get_memory_resource should be const and noexceptIssaquah
2527[fund.ts.v2] ALLOCATOR_OF for function::operator= has incorrect defaultIssaquah
2531future::get should explicitly state that the shared state is releasedIssaquah
2534Constrain rvalue stream operatorsIssaquah
2536What should <complex.h> do?IssaquahComplete
2540unordered_multimap::insert hint iteratorIssaquahComplete
2543LWG 2148 (hash support for enum types) seems under-specifiedIssaquahComplete
2544istreambuf_iterator(basic_streambuf* s) effects unclear when s is 0IssaquahComplete
2556Wide contract for future::share()IssaquahComplete
2562Consistent total ordering of pointers by comparison functorsIssaquah
2567Specification of logical operator traits uses BaseCharacteristic, which is defined only for UnaryTypeTraits and BinaryTypeTraitsIssaquahComplete
2568[fund.ts.v2] Specification of logical operator traits uses BaseCharacteristic, which is defined only for UnaryTypeTraits and BinaryTypeTraitsIssaquah
2569conjunction and disjunction requirements are too strictIssaquahComplete
2570[fund.ts.v2] conjunction and disjunction requirements are too strictIssaquah
2578Iterator requirements should reference iterator traitsIssaquahComplete
2584 ECMAScript IdentityEscape is ambiguousIssaquah
2587"Convertible to bool" requirement in conjunction and disjunctionIssaquahResolved by 2567
2588[fund.ts.v2] "Convertible to bool" requirement in conjunction and disjunctionIssaquah
2589match_results can't satisfy the requirements of a containerIssaquahComplete
2591std::function's member template target() should not lead to undefined behaviourIssaquahComplete
2598addressof works on temporariesIssaquahComplete
2664operator/ (and other append) semantics not useful if argument has rootIssaquahComplete
2665remove_filename() post condition is incorrectIssaquahComplete
2672Should is_empty use error_code in its specification?IssaquahComplete
2678std::filesystem enum classes overspecifiedIssaquahComplete
2679Inconsistent Use of Effects and Equivalent ToIssaquahComplete
2680Add "Equivalent to" to filesystemIssaquahComplete
2681filesystem::copy() cannot copy symlinksIssaquahComplete
2682filesystem::copy() won't create a symlink to a directoryIssaquahComplete
2686Why is std::hash specialized for error_code, but not error_condition?IssaquahComplete
2694Application of LWG 436 accidentally deleted definition of "facet"IssaquahComplete
2696Interaction between make_shared and enable_shared_from_this is underspecifiedIssaquahNothing to do
2699Missing restriction in [numeric.requirements]IssaquahComplete
2712copy_file(from, to, ...) has a number of unspecified error conditionsIssaquahComplete
2722equivalent incorrectly specifies throws clauseIssaquahComplete
2729Missing SFINAE on std::pair::operator=Issaquah
2732Questionable specification of path::operator/= and path::appendIssaquahComplete
2733[fund.ts.v2] gcd / lcm and boolIssaquahComplete
2735std::abs(short), std::abs(signed char) and others should return int instead of double in order to be compatible with C++98 and CIssaquahComplete
2736nullopt_t insufficiently constrainedIssaquahComplete
2738is_constructible with void typesIssaquahComplete
2739Issue with time_point non-member subtraction with an unsigned durationIssaquahComplete
2740constexpr optional::operator->IssaquahComplete
2742Inconsistent string interface taking string_viewIssaquahComplete
2744any's in_place constructorsIssaquahComplete
2745[fund.ts.v2] Implementability of LWG 2451IssaquahComplete
2747Possibly redundant std::move in [alg.foreach]IssaquahComplete
2748swappable traits for optionalsIssaquahComplete
2749swappable traits for variantsIssaquahComplete
2750[fund.ts.v2] LWG 2451 conversion constructor constraintIssaquahNothing to do
2752"Throws:" clauses of async and packaged_task are unimplementableIssaquah
2755[string.view.io] uses non-existent basic_string_view::to_string functionIssaquahComplete
2756C++ WP optional should 'forward' T's implicit conversionsIssaquahComplete
2758std::string{}.assign("ABCDE", 0, 1) is ambiguousIssaquahComplete
2759gcd / lcm and bool for the WPIssaquahComplete
2760non-const basic_string::data should not invalidate iteratorsIssaquahComplete
2765Did LWG 1123 go too far?IssaquahComplete
2767not_fn call_wrapper can form invalid typesIssaquahComplete
2769Redundant const in the return type of any_cast(const any&)IssaquahComplete
2771Broken Effects of some basic_string::compare functions in terms of basic_string_viewIssaquahComplete
2773Making std::ignore constexprIssaquahComplete
2777basic_string_view::copy should use char_traits::copyIssaquahComplete
2778basic_string_view is missing constexprIssaquahComplete
2260Missing requirement for Allocator::pointerKonaComplete
2676Provide filesystem::path overloads for File-based streamsKonaComplete
2768any_cast and move semanticsKonaComplete
2769Redundant const in the return type of any_cast(const any&)KonaComplete
2781Contradictory requirements for std::function and std::reference_wrapperKonaComplete
2782scoped_allocator_adaptor constructors must be constrainedKonaComplete
2784Resolution to LWG 2484 is missing "otherwise, no effects" and is hard to parseKonaComplete
2785quoted should work with basic_string_viewKonaComplete
2786Annex C should mention shared_ptr changes for array supportKonaComplete
2787§[file_status.cons] doesn't match class definitionKonaComplete
2788basic_string range mutators unintentionally require a default constructible allocatorKonaComplete
2789Equivalence of contained objectsKonaComplete
2790Missing specification of istreambuf_iterator::operator->KonaComplete
2794Missing requirements for allocator pointersKonaNothing to do
2795§[global.functions] provides incorrect example of ADL useKonaComplete
2796tuple should be a literal typeKonaComplete
2801Default-constructibility of unique_ptrKonaComplete
2802shared_ptr constructor requirements for a deleterKona
2804Unconditional constexpr default constructor for istream_iteratorKonaComplete
2806Base class of bad_optional_accessKonaComplete
2807std::invoke should use std::is_nothrow_callableKonaComplete
2812Range access is available with <string_view>KonaComplete
2824list::sort should say that the order of elements is unspecified if an exception is thrownKonaComplete
2826string_view iterators use old wordingKonaComplete
2834Resolution LWG 2223 is missing wording about end iteratorsKonaComplete
2835LWG 2536 seems to misspecify <tgmath.h>KonaComplete
2837gcd and lcm should support a wider range of input valuesKonaComplete
2838is_literal_type specification needs a little cleanupKonaComplete
2842in_place_t check for optional::optional(U&&) should decay UKonaComplete
2850std::function move constructor does unnecessary workKonaComplete
2853Possible inconsistency in specification of erase in [vector.modifiers]KonaComplete
2855std::throw_with_nested("string_literal")KonaComplete
2857{variant,optional,any}::emplace should return the constructed valueKonaComplete
2861basic_string should require that charT match traits::char_typeKonaComplete
2866Incorrect derived classes constraintsKonaNothing to do
2868Missing specification of bad_any_cast::what()KonaComplete
2872Add definition for direct-non-list-initializationKonaComplete
2873Add noexcept to several shared_ptr related functionsKonaComplete
2874Constructor shared_ptr::shared_ptr(Y*) should be constrainedKona
2875shared_ptr::shared_ptr(Y*, D, […]) constructors should be constrainedKona
2876shared_ptr::shared_ptr(const weak_ptr<Y>&) constructor should be constrainedKona
2878Missing DefaultConstructible requirement for istream_iterator default constructorKonaComplete
2890The definition of 'object state' applies only to class typesKonaComplete
2900The copy and move constructors of optional are not constexprKonaComplete
2903The form of initialization for the emplace-constructors is not specifiedKonaComplete
2904Make variant move-assignment more exception safeKonaComplete
2905is_constructible_v<unique_ptr<P, D>, P, D const &> should be false when D is not copy constructibleKonaComplete
2908The less-than operator for shared pointers could do moreKonaComplete
2911An is_aggregate type trait is neededKonaComplete
2921packaged_task and type-erased allocatorsKonaComplete
2934optional<const T> doesn't compare with TKonaComplete
2901Variants cannot properly support allocatorsTorontoComplete
2955to_chars / from_chars depend on std::stringTorontoResolved by P0682R1
2956filesystem::canonical() still defined in terms of absolute(p, base)TorontoComplete
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Last Updated: 17-Nov-2020

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+ If you are not redirected automatically, follow this link to new documentation. diff --git a/libcxx/www/cxx2a_status.html b/libcxx/www/cxx2a_status.html index f0d1acfccdf57..4637d07de938a 100644 --- a/libcxx/www/cxx2a_status.html +++ b/libcxx/www/cxx2a_status.html @@ -1,586 +1,14 @@ - - - + + - - libc++ C++2a Status - - + + + + libc++ C++20 Status - - - -
- -

libc++ C++2a Status

- - -

In July 2017, the C++ standard committee created a draft for the next version of the C++ standard, known here as "C++2a" (probably to be C++20).

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This page shows the status of libc++; the status of clang's support of the language features is here.

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Reminder: Features in unreleased drafts of the standard are subject to change.

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The groups that have contributed papers: -

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  • LWG - Library working group
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  • CWG - Core Language Working group
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  • SG1 - Study group #1 (Concurrency working group)
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-

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Paper Status

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Paper #GroupPaper NameMeetingStatusFirst released version
P0463R1LWGEndian just EndianTorontoComplete7.0
P0674R1LWGExtending make_shared to Support ArraysToronto
P0020R6LWGFloating Point AtomicAlbuquerque
P0053R7LWGC++ Synchronized Buffered OstreamAlbuquerque
P0202R3LWGAdd constexpr modifiers to functions in <algorithm> and <utility> HeadersAlbuquerqueIn Progress7.0
P0415R1LWGConstexpr for std::complexAlbuquerqueIn Progress7.0
P0439R0LWGMake std::memory_order a scoped enumerationAlbuquerqueComplete
P0457R2LWGString Prefix and Suffix CheckingAlbuquerqueComplete6.0
P0550R2LWGTransformation Trait remove_cvrefAlbuquerqueComplete6.0
P0600R1LWGnodiscard in the LibraryAlbuquerqueIn Progress7.0
P0616R0LWGde-pessimize legacy algorithms with std::moveAlbuquerque
P0653R2LWGUtility to convert a pointer to a raw pointerAlbuquerqueComplete6.0
P0718R2LWGAtomic shared_ptrAlbuquerque
P0767R1CWGDeprecate PODAlbuquerqueComplete7.0
P0768R1CWGLibrary Support for the Spaceship (Comparison) OperatorAlbuquerqueComplete
P0777R1LWGTreating Unnecessary decayAlbuquerqueComplete7.0
P0122R7LWG<span>JacksonvilleComplete7.0
P0355R7LWGExtending chrono to Calendars and Time ZonesJacksonvilleIn progress
P0551R3LWGThou Shalt Not Specialize std Function Templates!JacksonvilleComplete11.0
P0753R2LWGManipulators for C++ Synchronized Buffered OstreamJacksonville
P0754R2LWG<version>JacksonvilleComplete7.0
P0809R0LWGComparing Unordered ContainersJacksonville
P0858R0LWGConstexpr iterator requirementsJacksonville
P0905R1CWGSymmetry for spaceshipJacksonville
P0966R1LWGstring::reserve Should Not ShrinkJacksonvilleComplete8.0
P0019R8LWGAtomic RefRapperswil
P0458R2LWGChecking for Existence of an Element in Associative ContainersRapperswilComplete
P0475R1LWGLWG 2511: guaranteed copy elision for piecewise constructionRapperswil
P0476R2LWGBit-casting object representationsRapperswil
P0528R3CWGThe Curious Case of Padding Bits, Featuring Atomic Compare-and-ExchangeRapperswil
P0542R5CWGSupport for contract based programming in C++Rapperswil
P0556R3LWGIntegral power-of-2 operationsRapperswilComplete9.0
P0619R4LWGReviewing Deprecated Facilities of C++17 for C++20RapperswilPartial
(only std::allocator part is implemented)
P0646R1LWGImproving the Return Value of Erase-Like AlgorithmsRapperswilComplete10.0
P0722R3CWGEfficient sized delete for variable sized classesRapperswilComplete9.0
P0758R1LWGImplicit conversion traits and utility functionsRapperswilComplete
P0759R1LWGfpos RequirementsRapperswilComplete11.0
P0769R2LWGAdd shift to <algorithm>Rapperswil
P0788R3LWGStandard Library Specification in a Concepts and Contracts WorldRapperswil
P0879R0LWGConstexpr for swap and swap related functions Also resolves LWG issue 2800.Rapperswil
P0887R1LWGThe identity metafunctionRapperswilComplete8.0
P0892R2CWGexplicit(bool)Rapperswil
P0898R3LWGStandard Library ConceptsRapperswil
P0935R0LWGEradicating unnecessarily explicit default constructors from the standard libraryRapperswil
P0941R2CWGIntegrating feature-test macros into the C++ WDRapperswilIn progress
P1023R0LWGconstexpr comparison operators for std::arrayRapperswilComplete8.0
P1025R1CWGUpdate The Reference To The Unicode StandardRapperswil
P1120R0CWGConsistency improvements for <=> and other comparison operatorsRapperswil
P0318R1LWGunwrap_ref_decay and unwrap_referenceSan DiegoComplete8.0
P0356R5LWGSimplified partial function applicationSan Diego
P0357R3LWGreference_wrapper for incomplete typesSan DiegoComplete8.0
P0482R6CWGchar8_t: A type for UTF-8 characters and stringsSan Diego
P0487R1LWGFixing operator>>(basic_istream&, CharT*) (LWG 2499)San DiegoComplete8.0
P0591R4LWGUtility functions to implement uses-allocator constructionSan Diego
P0595R2CWGP0595R2 std::is_constant_evaluated()San DiegoComplete9.0
P0602R4LWGvariant and optional should propagate copy/move trivialitySan DiegoComplete8.0
P0608R3LWGA sane variant converting constructorSan DiegoComplete9.0
P0655R1LWGvisit<R>: Explicit Return Type for visitSan Diego
P0771R1LWGstd::function move constructor should be noexceptSan DiegoComplete6.0
P0896R4LWGThe One Ranges ProposalSan Diego
P0899R1LWGP0899R1 - LWG 3016 is not a defectSan DiegoNothing to do
P0919R3LWGHeterogeneous lookup for unordered containersSan DiegoComplete12.0
P0972R0LWG<chrono> zero(), min(), and max() should be noexceptSan DiegoComplete8.0
P1006R1LWGConstexpr in std::pointer_traitsSan DiegoComplete8.0
P1007R3LWGstd::assume_alignedSan Diego
P1020R1LWGSmart pointer creation with default initializationSan Diego
P1032R1LWGMisc constexpr bitsSan Diego
P1085R2LWGShould Span be Regular?San DiegoComplete8.0
P1123R0LWGEditorial Guidance for merging P0019r8 and P0528r3San Diego
P1148R0LWGCleaning up Clause 20San Diego
P1165R1LWGMake stateful allocator propagation more consistent for operator+(basic_string)San Diego
P1209R0LWGAdopt Consistent Container Erasure from Library Fundamentals 2 for C++20San DiegoComplete8.0
P1210R0LWGCompleting the Rebase of Library Fundamentals, Version 3, Working DraftSan Diego
P1236R1CWGAlternative Wording for P0907R4 Signed Integers are Two's ComplementSan Diego
P1248R1LWGRemove CommonReference requirement from StrictWeakOrdering (a.k.a Fixing Relations)San Diego
P1285R0LWGImproving Completeness Requirements for Type TraitsSan Diego
P1353R0CWGMissing feature test macrosSan Diego
P0339R6LWGpolymorphic_allocator<> as a vocabulary typeKona
P0340R3LWGMaking std::underlying_type SFINAE-friendlyKonaComplete9.0
P0738R2LWGI Stream, You Stream, We All Stream for istream_iteratorKona
P0811R3LWGWell-behaved interpolation for numbers and pointersKonaComplete9.0
P0920R2LWGPrecalculated hash values in lookupKonaReverted by P1661
P1001R2LWGTarget Vectorization Policies from Parallelism V2 TS to C++20Kona
P1024R3LWGUsability Enhancements for std::spanKonaComplete9.0
P1164R1LWGMake create_directory() IntuitiveKona
P1227R2LWGSigned ssize() functions, unsigned size() functions KonaComplete9.0
P1252R2LWGRanges Design CleanupKona
P1286R2CWGContra CWG DR1778Kona
P1357R1LWGTraits for [Un]bounded ArraysKonaComplete9.0
P1458R1LWGMandating the Standard Library: Clause 16 - Language support libraryKonaComplete9.0
P1459R1LWGMandating the Standard Library: Clause 18 - Diagnostics libraryKonaComplete9.0
P1462R1LWGMandating the Standard Library: Clause 20 - Strings libraryKonaComplete9.0
P1463R1LWGMandating the Standard Library: Clause 21 - Containers libraryKona
P1464R1LWGMandating the Standard Library: Clause 22 - Iterators libraryKonaComplete9.0
P0325LWGto_array from LFTS with updatesCologneComplete10.0
P0408LWGEfficient Access to basic_stringbuf ’s BufferCologne
P0466LWGLayout-compatibility and Pointer-interconvertibility TraitsCologne
P0553LWGBit operationsCologneComplete9.0
P0631LWGMath ConstantsCologneComplete11.0
P0645LWGText FormattingCologne
P0660LWGStop Token and Joining Thread, Rev 10Cologne
P0784CWGMore constexpr containersCologneComplete12.0
P0980LWGMaking std::string constexprCologne
P1004LWGMaking std::vector constexprCologne
P1035LWGInput Range AdaptorsCologne
P1065LWGConstexpr INVOKECologne
P1135LWGThe C++20 Synchronization LibraryCologneComplete
P1207LWGMovability of Single-pass IteratorsCologne
P1208LWGAdopt source_location for C++20Cologne
P1355LWGExposing a narrow contract for ceil2CologneComplete9.0
P1361LWGIntegration of chrono with text formattingCologne
P1423LWGchar8_t backward compatibility remediationCologne
P1424LWG'constexpr' feature macro concernsCologne
P1466LWGMiscellaneous minor fixes for chronoCologne
P1474LWGHelpful pointers for ContiguousIteratorCologne
P1502LWGStandard library header units for C++20Cologne
P1522LWGIterator Difference Type and Integer OverflowCologne
P1523LWGViews and Size TypesCologne
P1612LWGRelocate Endian’s SpecificationCologneComplete10.0
P1614LWGThe Mothership has LandedCologneIn progress
P1638LWGbasic_istream_view::iterator should not be copyableCologne
P1643LWGAdd wait/notify to atomic_refCologne
P1644LWGAdd wait/notify to atomicCologne
P1650LWGOutput std::chrono::days with 'd' suffixCologne
P1651LWGbind_front should not unwrap reference_wrapperCologne
P1652LWGPrintf corner cases in std::formatCologne
P1661LWGRemove dedicated precalculated hash lookup interfaceCologneNothing to do
P1754LWGRename concepts to standard_case for C++20, while we still canCologne
P0883LWGFixing Atomic Initialization Belfast
P1391LWGRange constructor for std::string_view Belfast
P1394LWGRange constructor for std::span Belfast
P1456LWGMove-only views Belfast
P1622LWGMandating the Standard Library: Clause 32 - Thread support library Belfast
P1645LWGconstexpr for numeric algorithms Belfast
P1664LWGreconstructible_range - a concept for putting ranges back together Belfast
P1686LWGMandating the Standard Library: Clause 27 - Time library Belfast
P1690LWGRefinement Proposal for P0919 Heterogeneous lookup for unordered containers BelfastComplete12.0
P1716LWGranges compare algorithm are over-constrained Belfast
P1718LWGMandating the Standard Library: Clause 25 - Algorithms library Belfast
P1719LWGMandating the Standard Library: Clause 26 - Numerics library Belfast
P1720LWGMandating the Standard Library: Clause 28 - Localization library Belfast
P1721LWGMandating the Standard Library: Clause 29 - Input/Output library Belfast
P1722LWGMandating the Standard Library: Clause 30 - Regular Expression library Belfast
P1723LWGMandating the Standard Library: Clause 31 - Atomics library Belfast
P1855LWGMake <compare> freestandingBelfast
P1862LWGRanges adaptors for non-copyable iterators Belfast
P1865LWGAdd max() to latch and barrier Belfast
P1869LWGRename 'condition_variable_any' interruptible wait methods Belfast
P1870LWGforwarding-range is too subtle Belfast
P1871LWGShould concepts be enabled or disabled? Belfast
P1872LWGspan should have size_type, not index_type BelfastComplete10.0
P1878LWGConstraining Readable Types Belfast
P1892LWGExtended locale-specific presentation specifiers for std::format Belfast
P1902LWGMissing feature-test macros 2018-2019 Belfast
P1959LWGRemove std::weak_equality and std::strong_equalityBelfast
P1960LWGNB Comment Changes Reviewed by SG1Belfast
P1961LWGHarmonizing the definitions of total order for pointersBelfast
P1965LWGBlanket Wording for Specifying “Hidden Friends”Belfast
P0586LWGSafe integral comparisonsPrague
P0593CWGImplicit creation of objects for low-level object manipulationPrague
P1115LWGImproving the Return Value of Erase-Like Algorithms II: Free erase/erase ifPragueComplete11.0
P1243LWGRangify New AlgorithmsPrague
P1460LWGMandating the Standard Library: Clause 20 - Utilities libraryPrague
P1739LWGAvoid template bloat for safe_ranges in combination with "subrange-y" view adaptorsPrague
P1831LWGDeprecating volatile: libraryPrague
P1868LWGwidth: clarifying units of width and precision in std::formatPrague
P1908CWGReserving Attribute Namespaces for Future UsePrague
P1937CWGFixing inconsistencies between constexpr and consteval functionsPrague
P1956LWGOn the names of low-level bit manipulation functionsPrague
P1957CWGConverting from T* to bool should be considered narrowing (re: US 212)Prague
P1963LWGFixing US 313Prague
P1964LWGWording for boolean-testablePrague
P1970LWGConsistency for size() functions: Add ranges::ssizePrague
P1973LWGRename "_default_init" Functions, Rev1Prague
P1976LWGFixed-size span construction from dynamic rangePragueComplete11.0
P1981LWGRename leap to leap_secondPrague
P1982LWGRename link to time_zone_linkPrague
P1983LWGWording for GB301, US296, US292, US291, and US283Prague
P1994LWGelements_view needs its own sentinelPrague
P2002CWGDefaulted comparison specification cleanupsPrague
P2045LWGMissing Mandates for the standard libraryPrague
P2085CWGConsistent defaulted comparisonsPrague
P2091LWGIssues with range access CPOsPrague
P2101LWG'Models' subsumes 'satisfies' (Wording for US298 and US300)Prague
P2102LWGMake 'implicit expression variations' more explicit (Wording for US185)Prague
P2106LWGAlternative wording for GB315 and GB316Prague
P2116LWGRemove tuple-like protocol support from fixed-extent spanPragueComplete11.0
- -

[ Note: "Nothing to do" means that no library changes were needed to implement this change -- end note]

- -

The missing bits in P0600 are in [mem.res.class], [mem.poly.allocator.class], and [container.node.overview]

- -

The missing bits in P0202 are in copy and copy_backwards (and the ones that call them: copy_n, set_union, set_difference, and set_symmetric_difference). This is because the first two algorithms have specializations that call memmove which is not constexpr. See Bug 25165

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Library Working group Issues Status

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Issue #Issue NameMeetingStatus
2070allocate_shared should use allocator_traits<A>::constructTorontoResolved by P0674R1
2444Inconsistent complexity for std::sort_heapToronto
2593Moved-from state of AllocatorsToronto
2597std::log misspecified for complex numbersToronto
2783stack::emplace() and queue::emplace() should return decltype(auto)TorontoComplete
2932Constraints on parallel algorithm implementations are underspecifiedToronto
2937Is equivalent("existing_thing", "not_existing_thing") an errorTorontoComplete
2940result_of specification also needs a little cleanupToronto
2942LWG 2873's resolution missed weak_ptr::owner_beforeTorontoComplete
2954Specialization of the convenience variable templates should be prohibitedTorontoComplete
2961Bad postcondition for set_default_resourceToronto
2966Incomplete resolution of US 74TorontoNothing to do
2974Diagnose out of bounds tuple_element/variant_alternativeTorontoComplete
2779[networking.ts] Relax requirements on buffer sequence iteratorsAlbuquerque
2870Default value of parameter theta of polar should be dependentAlbuquerqueComplete
2935What should create_directories do when p already exists but is not a directory?Albuquerque
2941[thread.req.timing] wording should apply to both member and namespace-level functionsAlbuquerqueNothing to do
2944LWG 2905 accidentally removed requirement that construction of the deleter doesn't throw an exceptionAlbuquerqueNothing to do
2945Order of template parameters in optional comparisonsAlbuquerqueComplete
2948unique_ptr does not define operator<< for stream outputAlbuquerqueComplete
2950std::byte operations are misspecifiedAlbuquerqueComplete
2952iterator_traits should work for pointers to cv TAlbuquerqueComplete
2953LWG 2853 should apply to deque::erase tooAlbuquerqueComplete
2958Moves improperly defined as deletedAlbuquerqueWe already do this
2964Apparently redundant requirement for dynamic_pointer_castAlbuquerque
2965Non-existing path::native_string() in filesystem_error::what() specificationAlbuquerqueNothing to do
2972What is is_trivially_destructible_v<int>?AlbuquerqueComplete
2976Dangling uses_allocator specialization for packaged_taskAlbuquerqueComplete
2977unordered_meow::merge() has incorrect Throws: clauseAlbuquerqueNothing to do
2978Hash support for pmr::string and friendsAlbuquerque
2979aligned_union should require complete object typesAlbuquerqueComplete
2980Cannot compare_exchange empty pointersAlbuquerque
2981Remove redundant deduction guides from standard libraryAlbuquerque
2982Making size_type consistent in associative container deduction guidesAlbuquerque
2988Clause 32 cleanup missed one typenameAlbuquerque
2993reference_wrapper conversion from T&&Albuquerque
2998Requirements on function objects passed to {forward_,}list-specific algorithmsAlbuquerqueNothing to do
3001weak_ptr::element_type needs remove_extent_tAlbuquerque
3024variant's copies must be deleted instead of disabled via SFINAEAlbuquerqueComplete
2164What are the semantics of vector.emplace(vector.begin(), vector.back())?JacksonvilleComplete
2243istream::putback problemJacksonvilleComplete
2816resize_file has impossible postconditionJacksonvilleNothing to do
2843Unclear behavior of std::pmr::memory_resource::do_allocate()JacksonvilleComplete
2849Why does !is_regular_file(from) cause copy_file to report a "file already exists" error?JacksonvilleNothing to do
2851std::filesystem enum classes are now underspecifiedJacksonvilleNothing to do
2946LWG 2758's resolution missed further correctionsJacksonvilleComplete
2969polymorphic_allocator::construct() shouldn't pass resource()JacksonvilleComplete
2975Missing case for pair construction in scoped and polymorphic allocatorsJacksonville
2989path's stream insertion operator lets you insert everything under the sunJacksonvilleCompleted
3000monotonic_memory_resource::do_is_equal uses dynamic_cast unnecessarilyJacksonville
3002[networking.ts] basic_socket_acceptor::is_open() isn't noexceptJacksonville
3004§[string.capacity] and §[vector.capacity] should specify time complexity for capacity()JacksonvilleNothing to do
3005Destruction order of arrays by make_shared/allocate_shared only recommended?Jacksonville
3007allocate_shared should rebind allocator to cv-unqualified value_type for constructionJacksonville
3009Including <string_view> doesn't provide std::size/empty/dataJacksonvilleComplete
3010[networking.ts] uses_executor says "if a type T::executor_type exists"Jacksonville
3013(recursive_)directory_iterator construction and traversal should not be noexceptJacksonvilleComplete
3014More noexcept issues with filesystem operationsJacksonvilleComplete
3015copy_options::unspecified underspecifiedJacksonvilleNothing to do
3017list splice functions should use addressofJacksonvilleComplete
3020[networking.ts] Remove spurious nested value_type buffer sequence requirementJacksonville
3026filesystem::weakly_canonical still defined in terms of canonical(p, base)JacksonvilleComplete
3030Who shall meet the requirements of try_lock?JacksonvilleNothing to do
3034P0767R1 breaks previously-standard-layout typesJacksonvilleComplete
3035std::allocator's constructors should be constexprJacksonvilleComplete
3039Unnecessary decay in thread and packaged_taskJacksonvilleComplete
3041Unnecessary decay in reference_wrapperJacksonvilleComplete
3042is_literal_type_v should be inlineJacksonvilleComplete
3043Bogus postcondition for filesystem_error constructorJacksonvilleComplete
3045atomic<floating-point> doesn't have value_type or difference_typeJacksonville
3048transform_reduce(exec, first1, last1, first2, init) discards execution policyJacksonville
3051Floating point classifications were inadvertently changed in P0175JacksonvilleNothing to do
3075basic_string needs deduction guides from basic_string_viewJacksonvilleComplete
2139What is a user-defined type?Rapperswil
2970Return type of std::visit misspecifiedRapperswil
3058Parallel adjacent_difference shouldn't require creating temporariesRapperswil
3062Unnecessary decay_t in is_execution_policy_v should be remove_cvref_tRapperswil
3067recursive_directory_iterator::pop must invalidateRapperswilNothing to do
3071[networking.ts] read_until still refers to "input sequence"RapperswilNothing to do
3074Non-member functions for valarray should only deduce from the valarrayRapperswil
3076basic_string CTAD ambiguityRapperswilComplete
3079LWG 2935 forgot to fix the existing_p overloads of create_directoryRapperswil
3080Floating point from_chars pattern specification breaks round-trippingRapperswil
3083What should ios::iword(-1) do?RapperswilNothing to do
3094[time.duration.io]p4 makes surprising claims about encodingRapperswil
3100Unnecessary and confusing "empty span" wordingRapperswilNothing to do
3102Clarify span iterator and const_iterator behaviorRapperswilComplete
3104Fixing duration divisionRapperswilComplete
2183Muddled allocator requirements for match_results constructorsSan DiegoComplete
2184Muddled allocator requirements for match_results assignmentsSan DiegoComplete
2412promise::set_value() and promise::get_future() should not raceSan Diego
2499operator>>(basic_istream&, CharT*) makes it hard to avoid buffer overflowsSan DiegoResolved by P0487R1
2682filesystem::copy() won't create a symlink to a directorySan DiegoNothing to do
2697[concurr.ts] Behavior of future/shared_future unwrapping constructor when given an invalid futureSan Diego
2797Trait precondition violationsSan DiegoResolved by 1285R0
2936Path comparison is defined in terms of the generic formatSan DiegoComplete
2943Problematic specification of the wide version of basic_filebuf::openSan DiegoNothing to do
2960[fund.ts.v3] nonesuch is insufficiently uselessSan DiegoComplete
2995basic_stringbuf default constructor forbids it from using SSO capacitySan Diego
2996Missing rvalue overloads for shared_ptr operationsSan Diego
3008make_shared (sub)object destruction semantics are not specifiedSan Diego
3022is_convertible<derived*, base*> may lead to ODRSan DiegoResolved by 1285R0
3025Map-like container deduction guides should use pair<Key, T>, not pair<const Key, T>San DiegoComplete
3031Algorithms and predicates with non-const reference argumentsSan Diego
3037polymorphic_allocator and incomplete typesSan Diego
3038polymorphic_allocator::allocate should not allow integer overflow to create vulnerabilitiesSan Diego
3054uninitialized_copy appears to not be able to meet its exception-safety guaranteeSan Diego
3065LWG 2989 missed that all path's other operators should be hidden friends as wellSan DiegoComplete
3096path::lexically_relative is confused by trailing slashesSan DiegoComplete
3116OUTERMOST_ALLOC_TRAITS needs remove_reference_tSan Diego
3122__cpp_lib_chrono_udls was accidentally droppedSan DiegoComplete
3127basic_osyncstream::rdbuf needs a const_castSan Diego
3128strstream::rdbuf needs a const_castSan DiegoNothing to do
3129regex_token_iterator constructor uses wrong pointer arithmeticSan Diego
3130§[input.output] needs many addressofSan Diego
3131addressof all the thingsSan Diego
3132Library needs to ban macros named expects or ensuresSan DiegoNothing to do
3134[fund.ts.v3] LFTSv3 contains extraneous [meta] variable templates that should have been deleted by P09961San DiegoResolved by P1210R0
3137Header for __cpp_lib_to_charsSan DiegoComplete
3145file_clock breaks ABI for C++17 implementationsSan DiegoComplete
3147Definitions of "likely" and "unlikely" are likely to cause problemsSan Diego
3148<concepts> should be freestandingSan Diego
3153Common and common_type have too little in commonSan Diego
3154Common and CommonReference have a common defectSan Diego
3012atomic<T> is unimplementable for non-is_trivially_copy_constructible TKona
3040basic_string_view::starts_with Effects are incorrectKonaComplete
3077(push|emplace)_back should invalidate the end iteratorKonaNothing to do
3087One final &x in §[list.ops]KonaNothing to do
3101span's Container constructors need another constraintKonaComplete
3112system_error and filesystem_error constructors taking a string may not be able to meet their postconditionsKona
3119Program-definedness of closure typesKonaNothing to do
3133Modernizing numeric type requirementsKona
3144span does not have a const_pointer typedefKonaComplete
3173Enable CTAD for ref-viewKona
3179subrange should always model RangeKona
3180Inconsistently named return type for ranges::minmax_elementKona
3182Specification of Same could be clearerKona
2899is_(nothrow_)move_constructible and tuple, optional and unique_ptrCologne
3055path::operator+=(single-character) misspecifiedCologne
3158tuple(allocator_arg_t, const Alloc&) should be conditionally explicitCologne
3169ranges permutation generators discard useful informationCologne
3183Normative permission to specialize Ranges variable templatesCologne
3184Inconsistencies in bind_front wordingCologne
3185Uses-allocator construction functions missing constexpr and noexceptCologne
3186ranges removal, partition, and partial_sort_copy algorithms discard useful informationCologne
3187P0591R4 reverted DR 2586 fixes to scoped_allocator_adaptor::construct()Cologne
3191std::ranges::shuffle synopsis does not match algorithm definitionCologne
3196std::optional<T> is ill-formed is T is an arrayCologneComplete
3198Bad constraint on std::span::span()CologneComplete
3199istream >> bitset<0> failsCologne
3202P0318R1 was supposed to be revisedCologneComplete
3206year_month_day conversion to sys_days uses not-existing member functionCologneComplete
3208Boolean's expression requirements are ordered inconsistentlyCologneNothing to do
3209Expression in year::ok() returns clause is ill-formedCologneComplete
3231year_month_day_last::day specification does not cover !ok() valuesBelfastNothing to do
3225zoned_time converting constructor shall not be noexceptBelfast
3190std::allocator::allocate sometimes returns too little storageBelfast
3218Modifier for %d parse flag does not match POSIX and format specificationBelfast
3224zoned_time constructor from TimeZonePtr does not specify initialization of tp_Belfast
3230Format specifier %y/%Y is missing locale alternative versionsBelfast
3232Inconsistency in zoned_time deduction guidesBelfast
3222P0574R1 introduced preconditions on non-existent parametersBelfast
3221Result of year_month arithmetic with months is ambiguousBelfast
3235parse manipulator without abbreviation is not callableBelfast
3246What are the constraints on the template parameter of basic_format_arg?Belfast
3253basic_syncbuf::basic_syncbuf() should not be explicitBelfast
3245Unnecessary restriction on '%p' parse specifierBelfast
3244Constraints for Source in §[fs.path.req] insufficiently constraintyBelfast
3241chrono-spec grammar ambiguity in §[time.format]Belfast
3257Missing feature testing macro update from P0858Belfast
3256Feature testing macro for constexpr algorithmsBelfast
3273Specify weekday_indexed to range of [0, 7]Belfast
3070path::lexically_relative causes surprising results if a filename can also be a root-nameBelfast
3266to_chars(bool) should be deletedBelfast
3272%I%p should parse/format duration since midnightBelfast
3259The definition of constexpr iterators should be adjustedBelfast
3103Errors in taking subview of span should be ill-formed where possibleBelfast
3274Missing feature test macro for <span>Belfast
3276Class split_view::outer_iterator::value_type should inherit from view_interfaceBelfast
3277Pre-increment on prvalues is not a requirement of weakly_incrementableBelfast
3149DefaultConstructible should require default initializationBelfast
1203More useful rvalue stream insertionPrague12.0
2859Definition of reachable in [ptr.launder] misses pointer arithmetic from pointer-interconvertible objectPrague
3018shared_ptr of function typePrague
3050Conversion specification problem in chrono::duration constructorPrague
3141CopyConstructible doesn't preserve source valuesPrague
3150UniformRandomBitGenerator should validate min and maxPrague
3175The CommonReference requirement of concept SwappableWith is not satisfied in the examplePrague
3194ConvertibleTo prose does not match codePrague
3200midpoint should not constrain T is completePrague
3201lerp should be marked as noexceptPragueComplete
3226zoned_time constructor from string_view should accept zoned_time<Duration2, TimeZonePtr2>Prague
3233Broken requirements for shared_ptr converting constructorsPrague
3237LWG 3038 and 3190 have inconsistent PRsPrague
3238Insufficiently-defined behavior of std::function deduction guidesPrague
3242std::format: missing rules for arg-id in width and precisionPrague
3243std::format and negative zeroesPrague
3247ranges::iter_move should perform ADL-only lookup of iter_movePrague
3248std::format #b, #B, #o, #x, and #X presentation types misformat negative numbersPrague
3250std::format: # (alternate form) for NaN and infPrague
3251Are std::format alignment specifiers applied to string arguments?Prague
3252Parse locale's aware modifiers for commands are not consistent with POSIX specPrague
3254Strike stop_token's operator!=Prague
3255span's array constructor is too strictPragueComplete
3260year_month* arithmetic rejects durations convertible to yearsPrague
3262Formatting of negative durations is not specifiedPrague
3264sized_range and ranges::size redundantly use disable_sized_rangePrague
3269Parse manipulators do not specify the result of the extraction from streamPrague
3270Parsing and formatting %j with durationsPrague
3280View converting constructors can cause constraint recursion and are unneededPrague
3281Conversion from pair-like types to subrange is a silent semantic promotionPrague
3282subrange converting constructor should disallow derived to base conversionsPrague
3284random_access_iterator semantic constraints accidentally promote difference type using unary negatePrague
3285The type of a customization point object shall satisfy semiregularPrague
3286ranges::size is not required to be valid after a call to ranges::begin on an input rangePrague
3291iota_view::iterator has the wrong iterator_categoryPrague
3292iota_view is under-constrainedPrague
3294zoned_time deduction guides misinterprets string/char*Prague
3296Inconsistent default argument for basic_regex<>::assignPrague
3299Pointers don't need customized iterator behaviorPrague
3300Non-array ssize overload is underconstrainedPrague
3301transform_view::iterator has incorrect iterator_categoryPrague
3302Range adaptor objects keys and values are unspecifiedPrague
3303Bad "constexpr" marker for destroy/destroy_nPrague
3304Allocate functions of std::polymorphic_allocator should require [[nodiscard]]Prague
3307std::allocator<void>().allocate(n)Prague
3310Replace SIZE_MAX with numeric_limits<size_t>::max()Prague
3313join_view::iterator::operator-- is incorrectly constrainedPrague
3314Is stream insertion behavior locale dependent when Period::type is micro?Prague
3315Correct Allocator Default BehaviorPrague
3316Correctly define epoch for utc_clock / utc_timepointPrague
3317Incorrect operator<< for floating-point durationsPrague
3318Clarify whether clocks can represent time before their epochPrague
3319Properly reference specification of IANA time zone databasePrague
3320span::cbegin/cend methods produce different results than std::[ranges::]cbegin/cendPragueComplete
3321uninitialized_construct_using_allocator should use construct_atPrague
3323has-tuple-element helper concept needs convertible_toPrague
3324Special-case std::strong/weak/partial_order for pointersPrague
3325Constrain return type of transformation function for transform_viewPrague
3326enable_view has false positivesPrague
3327Format alignment specifiers vs. text directionPrague
3328Clarify that std::string is not good for UTF-8Prague
3329totally_ordered_with both directly and indirectly requires common_reference_withPrague
3330Include <compare> from most library headersPrague
3331Define totally_ordered/_with in terms of partially-ordered-withPrague
3332Issue in §[time.format]Prague
3334basic_osyncstream move assignment and destruction calls basic_syncbuf::emit() twicePrague
3335Resolve C++20 NB comments US 273 and GB 274Prague
3338Rename default_constructible to default_initializablePrague
3340Formatting functions should throw on argument/format string mismatch in §[format.functions]Prague
3346pair and tuple copy and move constructor have backwards specificationPrague
3347std::pair<T, U> now requires T and U to be less-than-comparablePrague
3348__cpp_lib_unwrap_ref in wrong headerPrague
3349Missing __cpp_lib_constexpr_complex for P0415R1Prague
3350Simplify return type of lexicographical_compare_three_wayPrague
3351ranges::enable_safe_range should not be constrainedPrague
3352strong_equality isn't a thingPrague
3354has_strong_structural_equality has a meaningless definitionPrague
3355The memory algorithms should support move-only input iterators introduced by P1207Prague
3356__cpp_lib_nothrow_convertible should be __cpp_lib_is_nothrow_convertiblePrague
3358§[span.cons] is mistaken that to_address can throwPrague
3359<chrono> leap second support should allow for negative leap secondsPrague
3360three_way_comparable_with is inconsistent with similar conceptsPrague
3362Strike stop_source's operator!=Prague
3363drop_while_view should opt-out of sized_rangePrague
3364Initialize data members of ranges and their iteratorsPrague
3367Integer-class conversions should not throwPrague
3369span's deduction-guide for built-in arrays doesn't workPrague
3371visit_format_arg and make_format_args are not hidden friendsPrague
3372vformat_to should not try to deduce Out twicePrague
3373{to,from}_chars_result and format_to_n_result need the "we really mean what we say" wordingPrague
3374P0653 + P1006 should have made the other std::to_address overload constexprPrague
3375decay in viewable_range should be remove_cvrefPrague
3377elements_view::iterator befriends a specialization of itselfPrague
3379"safe" in several library names is misleadingPrague
3380common_type and comparison categoriesPrague
3381begin and data must agree for contiguous_rangePrague
3382NTTP for pair and arrayPrague
3383§[time.zone.leap.nonmembers] sys_seconds should be replaced with secondsPrague
3384transform_view::sentinel has an incorrect operator-Prague
3385common_iterator is not sufficiently constrained for non-copyable iteratorsPrague
3387§[range.reverse.view] reverse_view<V> unintentionally requires range<const V>Prague
3388view iterator types have ill-formed <=> operatorsPrague
3389A move-only iterator still does not have a counted_iteratorPrague
3390make_move_iterator() cannot be used to construct a move_iterator for a move-only iteratorPrague
3393Missing/incorrect feature test macro for coroutinesPrague
3395Definition for three-way comparison needs to be updated (US 152)Prague
3396Clarify point of reference for source_location::current() (DE 169)Prague
3397ranges::basic_istream_view::iterator should not provide iterator_categoryPrague
3398tuple_element_t is also wrong for const subrangePrague
- -

Last Updated: 16-Feb-2020

-
+ If you are not redirected automatically, follow this link to new documentation. diff --git a/libcxxabi/src/CMakeLists.txt b/libcxxabi/src/CMakeLists.txt index 7353c2086b944..a8e12aa36e643 100644 --- a/libcxxabi/src/CMakeLists.txt +++ b/libcxxabi/src/CMakeLists.txt @@ -174,9 +174,9 @@ if (LIBCXXABI_ENABLE_SHARED) CXX_EXTENSIONS OFF CXX_STANDARD - 17 + 20 CXX_STANDARD_REQUIRED - ON + OFF COMPILE_FLAGS "${LIBCXXABI_COMPILE_FLAGS}" LINK_FLAGS @@ -241,9 +241,9 @@ if (LIBCXXABI_ENABLE_STATIC) CXX_EXTENSIONS OFF CXX_STANDARD - 17 + 20 CXX_STANDARD_REQUIRED - ON + OFF COMPILE_FLAGS "${LIBCXXABI_COMPILE_FLAGS}" LINK_FLAGS diff --git a/libcxxabi/src/demangle/ItaniumDemangle.h b/libcxxabi/src/demangle/ItaniumDemangle.h index fd6e5cf0fe580..6bfc02d153796 100644 --- a/libcxxabi/src/demangle/ItaniumDemangle.h +++ b/libcxxabi/src/demangle/ItaniumDemangle.h @@ -82,6 +82,7 @@ X(PostfixExpr) \ X(ConditionalExpr) \ X(MemberExpr) \ + X(SubobjectExpr) \ X(EnclosingExpr) \ X(CastExpr) \ X(SizeofParamPackExpr) \ @@ -91,6 +92,7 @@ X(PrefixExpr) \ X(FunctionParam) \ X(ConversionExpr) \ + X(PointerToMemberConversionExpr) \ X(InitListExpr) \ X(FoldExpr) \ X(ThrowExpr) \ @@ -1656,6 +1658,40 @@ class MemberExpr : public Node { } }; +class SubobjectExpr : public Node { + const Node *Type; + const Node *SubExpr; + StringView Offset; + NodeArray UnionSelectors; + bool OnePastTheEnd; + +public: + SubobjectExpr(const Node *Type_, const Node *SubExpr_, StringView Offset_, + NodeArray UnionSelectors_, bool OnePastTheEnd_) + : Node(KSubobjectExpr), Type(Type_), SubExpr(SubExpr_), Offset(Offset_), + UnionSelectors(UnionSelectors_), OnePastTheEnd(OnePastTheEnd_) {} + + template void match(Fn F) const { + F(Type, SubExpr, Offset, UnionSelectors, OnePastTheEnd); + } + + void printLeft(OutputStream &S) const override { + SubExpr->print(S); + S += ".<"; + Type->print(S); + S += " at offset "; + if (Offset.empty()) { + S += "0"; + } else if (Offset[0] == 'n') { + S += "-"; + S += Offset.dropFront(); + } else { + S += Offset; + } + S += ">"; + } +}; + class EnclosingExpr : public Node { const StringView Prefix; const Node *Infix; @@ -1843,6 +1879,28 @@ class ConversionExpr : public Node { } }; +class PointerToMemberConversionExpr : public Node { + const Node *Type; + const Node *SubExpr; + StringView Offset; + +public: + PointerToMemberConversionExpr(const Node *Type_, const Node *SubExpr_, + StringView Offset_) + : Node(KPointerToMemberConversionExpr), Type(Type_), SubExpr(SubExpr_), + Offset(Offset_) {} + + template void match(Fn F) const { F(Type, SubExpr, Offset); } + + void printLeft(OutputStream &S) const override { + S += "("; + Type->print(S); + S += ")("; + SubExpr->print(S); + S += ")"; + } +}; + class InitListExpr : public Node { const Node *Ty; NodeArray Inits; @@ -2437,6 +2495,8 @@ template struct AbstractManglingParser { Node *parseConversionExpr(); Node *parseBracedExpr(); Node *parseFoldExpr(); + Node *parsePointerToMemberConversionExpr(); + Node *parseSubobjectExpr(); /// Parse the production. Node *parseType(); @@ -4404,6 +4464,50 @@ Node *AbstractManglingParser::parseFoldExpr() { return make(IsLeftFold, OperatorName, Pack, Init); } +// ::= mc [] E +// +// Not yet in the spec: https://github.com/itanium-cxx-abi/cxx-abi/issues/47 +template +Node *AbstractManglingParser::parsePointerToMemberConversionExpr() { + Node *Ty = getDerived().parseType(); + if (!Ty) + return nullptr; + Node *Expr = getDerived().parseExpr(); + if (!Expr) + return nullptr; + StringView Offset = getDerived().parseNumber(true); + if (!consumeIf('E')) + return nullptr; + return make(Ty, Expr, Offset); +} + +// ::= so [] * [p] E +// ::= _ [] +// +// Not yet in the spec: https://github.com/itanium-cxx-abi/cxx-abi/issues/47 +template +Node *AbstractManglingParser::parseSubobjectExpr() { + Node *Ty = getDerived().parseType(); + if (!Ty) + return nullptr; + Node *Expr = getDerived().parseExpr(); + if (!Expr) + return nullptr; + StringView Offset = getDerived().parseNumber(true); + size_t SelectorsBegin = Names.size(); + while (consumeIf('_')) { + Node *Selector = make(parseNumber()); + if (!Selector) + return nullptr; + Names.push_back(Selector); + } + bool OnePastTheEnd = consumeIf('p'); + if (!consumeIf('E')) + return nullptr; + return make( + Ty, Expr, Offset, popTrailingNodeArray(SelectorsBegin), OnePastTheEnd); +} + // ::= // ::= // ::= @@ -4661,6 +4765,9 @@ Node *AbstractManglingParser::parseExpr() { return nullptr; case 'm': switch (First[1]) { + case 'c': + First += 2; + return parsePointerToMemberConversionExpr(); case 'i': First += 2; return getDerived().parseBinaryExpr("-"); @@ -4808,6 +4915,9 @@ Node *AbstractManglingParser::parseExpr() { return Ex; return make("static_cast", T, Ex); } + case 'o': + First += 2; + return parseSubobjectExpr(); case 'p': { First += 2; Node *Child = getDerived().parseExpr(); @@ -4975,6 +5085,16 @@ Node *AbstractManglingParser::parseSpecialName() { switch (look()) { case 'T': switch (look(1)) { + // TA # template parameter object + // + // Not yet in the spec: https://github.com/itanium-cxx-abi/cxx-abi/issues/63 + case 'A': { + First += 2; + Node *Arg = getDerived().parseTemplateArg(); + if (Arg == nullptr) + return nullptr; + return make("template parameter object for ", Arg); + } // TV # virtual table case 'V': { First += 2; diff --git a/libcxxabi/src/demangle/Utility.h b/libcxxabi/src/demangle/Utility.h index 04e1936ebbe78..846a5f0818e7e 100644 --- a/libcxxabi/src/demangle/Utility.h +++ b/libcxxabi/src/demangle/Utility.h @@ -52,7 +52,7 @@ class OutputStream { char *TempPtr = std::end(Temp); while (N) { - *--TempPtr = '0' + char(N % 10); + *--TempPtr = char('0' + N % 10); N /= 10; } diff --git a/libcxxabi/src/fallback_malloc.cpp b/libcxxabi/src/fallback_malloc.cpp index 75c01efebed22..78720187affca 100644 --- a/libcxxabi/src/fallback_malloc.cpp +++ b/libcxxabi/src/fallback_malloc.cpp @@ -17,6 +17,7 @@ #include // for malloc, calloc, free #include // for memset +#include // for std::__libcpp_aligned_{alloc,free} // A small, simple heap manager based (loosely) on // the startup heap manager from FreeBSD, optimized for space. @@ -204,7 +205,7 @@ struct __attribute__((aligned)) __aligned_type {}; void* __aligned_malloc_with_fallback(size_t size) { #if defined(_WIN32) - if (void* dest = _aligned_malloc(size, alignof(__aligned_type))) + if (void* dest = std::__libcpp_aligned_alloc(alignof(__aligned_type), size)) return dest; #elif defined(_LIBCPP_HAS_NO_LIBRARY_ALIGNED_ALLOCATION) if (void* dest = ::malloc(size)) @@ -212,8 +213,7 @@ void* __aligned_malloc_with_fallback(size_t size) { #else if (size == 0) size = 1; - void* dest; - if (::posix_memalign(&dest, __alignof(__aligned_type), size) == 0) + if (void* dest = std::__libcpp_aligned_alloc(__alignof(__aligned_type), size)) return dest; #endif return fallback_malloc(size); @@ -234,11 +234,7 @@ void __aligned_free_with_fallback(void* ptr) { if (is_fallback_ptr(ptr)) fallback_free(ptr); else { -#if defined(_WIN32) - ::_aligned_free(ptr); -#else - ::free(ptr); -#endif + std::__libcpp_aligned_free(ptr); } } diff --git a/libcxxabi/src/stdlib_new_delete.cpp b/libcxxabi/src/stdlib_new_delete.cpp index 58f181eb357ff..9df84548ea3ec 100644 --- a/libcxxabi/src/stdlib_new_delete.cpp +++ b/libcxxabi/src/stdlib_new_delete.cpp @@ -27,7 +27,7 @@ operator new(std::size_t size) _THROW_BAD_ALLOC if (size == 0) size = 1; void* p; - while ((p = ::malloc(size)) == 0) + while ((p = ::malloc(size)) == nullptr) { // If malloc fails and there is a new_handler, // call it to try free up memory. @@ -48,7 +48,7 @@ _LIBCXXABI_WEAK void* operator new(size_t size, const std::nothrow_t&) _NOEXCEPT { - void* p = 0; + void* p = nullptr; #ifndef _LIBCXXABI_NO_EXCEPTIONS try { @@ -74,7 +74,7 @@ _LIBCXXABI_WEAK void* operator new[](size_t size, const std::nothrow_t&) _NOEXCEPT { - void* p = 0; + void* p = nullptr; #ifndef _LIBCXXABI_NO_EXCEPTIONS try { @@ -142,15 +142,16 @@ operator new(std::size_t size, std::align_val_t alignment) _THROW_BAD_ALLOC size = 1; if (static_cast(alignment) < sizeof(void*)) alignment = std::align_val_t(sizeof(void*)); + + // Try allocating memory. If allocation fails and there is a new_handler, + // call it to try free up memory, and try again until it succeeds, or until + // the new_handler decides to terminate. + // + // If allocation fails and there is no new_handler, we throw bad_alloc + // (or return nullptr if exceptions are disabled). void* p; -#if defined(_LIBCPP_WIN32API) - while ((p = _aligned_malloc(size, static_cast(alignment))) == nullptr) -#else - while (::posix_memalign(&p, static_cast(alignment), size) != 0) -#endif + while ((p = std::__libcpp_aligned_alloc(static_cast(alignment), size)) == nullptr) { - // If posix_memalign fails and there is a new_handler, - // call it to try free up memory. std::new_handler nh = std::get_new_handler(); if (nh) nh(); @@ -158,7 +159,6 @@ operator new(std::size_t size, std::align_val_t alignment) _THROW_BAD_ALLOC #ifndef _LIBCXXABI_NO_EXCEPTIONS throw std::bad_alloc(); #else - p = nullptr; // posix_memalign doesn't initialize 'p' on failure break; #endif } @@ -170,7 +170,7 @@ _LIBCXXABI_WEAK void* operator new(size_t size, std::align_val_t alignment, const std::nothrow_t&) _NOEXCEPT { - void* p = 0; + void* p = nullptr; #ifndef _LIBCXXABI_NO_EXCEPTIONS try { @@ -196,7 +196,7 @@ _LIBCXXABI_WEAK void* operator new[](size_t size, std::align_val_t alignment, const std::nothrow_t&) _NOEXCEPT { - void* p = 0; + void* p = nullptr; #ifndef _LIBCXXABI_NO_EXCEPTIONS try { @@ -215,12 +215,9 @@ _LIBCXXABI_WEAK void operator delete(void* ptr, std::align_val_t) _NOEXCEPT { - if (ptr) -#if defined(_LIBCPP_WIN32API) - ::_aligned_free(ptr); -#else - ::free(ptr); -#endif + if (ptr) { + std::__libcpp_aligned_free(ptr); + } } _LIBCXXABI_WEAK diff --git a/libcxxabi/test/dynamic_cast.pass.cpp b/libcxxabi/test/dynamic_cast.pass.cpp index 49ecddb4177ba..c1a5980d552b0 100644 --- a/libcxxabi/test/dynamic_cast.pass.cpp +++ b/libcxxabi/test/dynamic_cast.pass.cpp @@ -6,13 +6,15 @@ // //===----------------------------------------------------------------------===// +// XFAIL: gcc-7, gcc-8, gcc-9 + #include // This test explicitly tests dynamic cast with types that have inaccessible // bases. #if defined(__clang__) # pragma clang diagnostic ignored "-Winaccessible-base" -#elif defined(__GNUC__) +#elif defined(__GNUC__) && (__GNUC__ >= 10) # pragma GCC diagnostic ignored "-Winaccessible-base" #endif diff --git a/libcxxabi/test/dynamic_cast3.pass.cpp b/libcxxabi/test/dynamic_cast3.pass.cpp index 9c25cac865b9a..2364f4c1b5bd7 100644 --- a/libcxxabi/test/dynamic_cast3.pass.cpp +++ b/libcxxabi/test/dynamic_cast3.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// XFAIL: gcc-7, gcc-8, gcc-9 + #include #include "support/timer.h" @@ -13,7 +15,7 @@ // bases. #if defined(__clang__) # pragma clang diagnostic ignored "-Winaccessible-base" -#elif defined(__GNUC__) +#elif defined(__GNUC__) && (__GNUC__ >= 10) # pragma GCC diagnostic ignored "-Winaccessible-base" #endif diff --git a/libcxxabi/test/dynamic_cast5.pass.cpp b/libcxxabi/test/dynamic_cast5.pass.cpp index 0a9689c23d6b0..357bb804766ee 100644 --- a/libcxxabi/test/dynamic_cast5.pass.cpp +++ b/libcxxabi/test/dynamic_cast5.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// XFAIL: gcc-7, gcc-8, gcc-9 + #include #include "support/timer.h" @@ -13,7 +15,7 @@ // bases. #if defined(__clang__) # pragma clang diagnostic ignored "-Winaccessible-base" -#elif defined(__GNUC__) +#elif defined(__GNUC__) && (__GNUC__ >= 10) # pragma GCC diagnostic ignored "-Winaccessible-base" #endif diff --git a/libcxxabi/test/guard_threaded_test.pass.cpp b/libcxxabi/test/guard_threaded_test.pass.cpp index 7e5e0de8c7903..798d11b15d1ab 100644 --- a/libcxxabi/test/guard_threaded_test.pass.cpp +++ b/libcxxabi/test/guard_threaded_test.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include "make_test_thread.h" #include "test_macros.h" @@ -349,21 +350,21 @@ void test_futex_syscall() { int lock1 = 0; int lock2 = 0; int lock3 = 0; - std::thread waiter1([&]() { + std::thread waiter1 = support::make_test_thread([&]() { int expect = 0; PlatformFutexWait(&lock1, expect); assert(lock1 == 1); }); - std::thread waiter2([&]() { + std::thread waiter2 = support::make_test_thread([&]() { int expect = 0; PlatformFutexWait(&lock2, expect); assert(lock2 == 2); }); - std::thread waiter3([&]() { + std::thread waiter3 = support::make_test_thread([&]() { int expect = 42; // not the value PlatformFutexWait(&lock3, expect); // doesn't block }); - std::thread waker([&]() { + std::thread waker = support::make_test_thread([&]() { lock1 = 1; PlatformFutexWake(&lock1); lock2 = 2; diff --git a/libcxxabi/test/test_demangle.pass.cpp b/libcxxabi/test/test_demangle.pass.cpp index cbbccb14feed8..3954fdba048e4 100644 --- a/libcxxabi/test/test_demangle.pass.cpp +++ b/libcxxabi/test/test_demangle.pass.cpp @@ -29800,6 +29800,21 @@ const char* cases[][2] = {"_ZN1XIZ1fIiEvOT_EUlS2_DpT0_E_EclIJEEEvDpT_", "void X(int&&)::'lambda'(int&&, auto...)>::operator()<>()"}, {"_ZZZZN6abcdef9abcdefghi29abcdefabcdefabcdefabcefabcdef27xxxxxxxxxxxxxxxxxxxxxxxxxxxEN4absl8DurationERKNSt3__u12basic_stringIcNS4_11char_traitsIcEENS4_9allocatorIcEEEEPNS1_19yyyyyyyyyyyyyyyyyyyEENK3$_5clEvENKUlvE_clEvE6zzzzzz", "abcdef::abcdefghi::abcdefabcdefabcdefabcefabcdef::xxxxxxxxxxxxxxxxxxxxxxxxxxx(absl::Duration, std::__u::basic_string, std::__u::allocator > const&, abcdef::abcdefghi::abcdefabcdefabcdefabcefabcdef::yyyyyyyyyyyyyyyyyyy*)::$_5::operator()() const::'lambda'()::operator()() const::zzzzzz"}, + // C++2a class type non-type template parameters: + {"_Z1fIXtl1BLPi0ELi1EEEEvv", "void f()"}, + {"_Z1fIXtl1BLPi32EEEEvv", "void f()"}, + {"_Z1fIXtl1BrcPiLi0EEEEvv", "void f(0)}>()"}, + {"_Z1fIXtl1BadsoiL_Z6nestedE_EEEEvv", "void f)}>()"}, + {"_Z1fIXtl1BadsoiL_Z6nestedE16_0pEEEEvv", "void f)}>()"}, + {"_Z1fIXtl2BRsoiL_Z7derivedE4EEEEvv", "void f}>()"}, + {"_Z1fIXtl1BcvPiplcvPcadL_Z7derivedELl16EEEEvv", "void f()"}, + {"_Z1fIXtl1CadsoKiL_Z7derivedE4EEEEvv", "void f)}>()"}, + {"_Z1fIXtl1DLM7DerivedKi0ELi1EEEEvv", "void f()"}, + // FIXME: This is not valid pointer-to-member syntax. + {"_Z1fIXtl1DmcM7DerivedKiadL_ZN11MoreDerived1zEEn8EEEEvv", "void f()"}, + {"_Z1fIXtl1Edi1nLi42EEEEvv", "void f()"}, + {"_ZTAXtl1StlA32_cLc104ELc101ELc108ELc108ELc111ELc32ELc119ELc111ELc114ELc108ELc100EEEE", "template parameter object for S{char [32]{(char)104, (char)101, (char)108, (char)108, (char)111, (char)32, (char)119, (char)111, (char)114, (char)108, (char)100}}"}, + // FIXME: This is wrong; the S2_ backref should expand to OT_ and then to // "double&&". But we can't cope with a substitution that represents a // different type the node it is a substitute for. diff --git a/libcxxabi/test/test_guard.pass.cpp b/libcxxabi/test/test_guard.pass.cpp index 2168986c455e6..82370c5a82c91 100644 --- a/libcxxabi/test/test_guard.pass.cpp +++ b/libcxxabi/test/test_guard.pass.cpp @@ -12,6 +12,7 @@ #ifndef _LIBCXXABI_HAS_NO_THREADS #include +#include "make_test_thread.h" #endif #include "test_macros.h" @@ -97,7 +98,8 @@ namespace test4 { } void test() { - std::thread t1(helper), t2(helper); + std::thread t1 = support::make_test_thread(helper); + std::thread t2 = support::make_test_thread(helper); t1.join(); t2.join(); assert(run_count == 1); @@ -124,12 +126,12 @@ namespace test5 { void helper() { static int a = one(); ((void)a); - std::thread t(another_helper); + std::thread t = support::make_test_thread(another_helper); t.join(); } void test() { - std::thread t(helper); + std::thread t = support::make_test_thread(helper); t.join(); assert(run_count == 1); } diff --git a/libcxxabi/test/thread_local_destruction_order.pass.cpp b/libcxxabi/test/thread_local_destruction_order.pass.cpp index eeb90b820b871..a01f9848a2778 100644 --- a/libcxxabi/test/thread_local_destruction_order.pass.cpp +++ b/libcxxabi/test/thread_local_destruction_order.pass.cpp @@ -25,6 +25,8 @@ #include #include +#include "make_test_thread.h" + int seq = 0; class OrderChecker { @@ -59,7 +61,7 @@ void thread_fn() { int main(int, char**) { static OrderChecker fn_static{6}; - std::thread{thread_fn}.join(); + support::make_test_thread(thread_fn).join(); assert(seq == 3); thread_local OrderChecker fn_thread_local{4}; diff --git a/libcxxabi/test/unwind_06.pass.cpp b/libcxxabi/test/unwind_06.pass.cpp index 0c34c49493762..f8e9f8953aa9c 100644 --- a/libcxxabi/test/unwind_06.pass.cpp +++ b/libcxxabi/test/unwind_06.pass.cpp @@ -14,7 +14,7 @@ #include // Suppress diagnostics about deprecated volatile operations -#if defined(__GNUC__) && !defined(__clang__) +#if defined(__GNUC__) && (__GNUC__ >= 10) && !defined(__clang__) # pragma GCC diagnostic ignored "-Wvolatile" #endif diff --git a/libunwind/src/Registers.hpp b/libunwind/src/Registers.hpp index 4d963b4156d1c..e0cb84f00e7ff 100644 --- a/libunwind/src/Registers.hpp +++ b/libunwind/src/Registers.hpp @@ -1514,12 +1514,12 @@ inline void Registers_ppc64::setFloatRegister(int regNum, double value) { } inline bool Registers_ppc64::validVectorRegister(int regNum) const { -#ifdef PPC64_HAS_VMX +#if defined(__VSX__) if (regNum >= UNW_PPC64_VS0 && regNum <= UNW_PPC64_VS31) return true; if (regNum >= UNW_PPC64_VS32 && regNum <= UNW_PPC64_VS63) return true; -#else +#elif defined(__ALTIVEC__) if (regNum >= UNW_PPC64_V0 && regNum <= UNW_PPC64_V31) return true; #endif diff --git a/libunwind/src/UnwindLevel1.c b/libunwind/src/UnwindLevel1.c index 3e75b5f13cd63..68e5e48b8c057 100644 --- a/libunwind/src/UnwindLevel1.c +++ b/libunwind/src/UnwindLevel1.c @@ -39,8 +39,7 @@ unwind_phase1(unw_context_t *uc, unw_cursor_t *cursor, _Unwind_Exception *except __unw_init_local(cursor, uc); // Walk each frame looking for a place to stop. - bool handlerNotFound = true; - while (handlerNotFound) { + while (true) { // Ask libunwind to get next frame (skip over first which is // _Unwind_RaiseException). int stepResult = __unw_step(cursor); @@ -102,7 +101,6 @@ unwind_phase1(unw_context_t *uc, unw_cursor_t *cursor, _Unwind_Exception *except case _URC_HANDLER_FOUND: // found a catch clause or locals that need destructing in this frame // stop search and remember stack pointer at the frame - handlerNotFound = false; __unw_get_reg(cursor, UNW_REG_SP, &sp); exception_object->private_2 = (uintptr_t)sp; _LIBUNWIND_TRACE_UNWINDING( diff --git a/libunwind/src/UnwindRegistersRestore.S b/libunwind/src/UnwindRegistersRestore.S index d817e6dae9482..289afe98b0b2a 100644 --- a/libunwind/src/UnwindRegistersRestore.S +++ b/libunwind/src/UnwindRegistersRestore.S @@ -170,7 +170,7 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_ppc646jumptoEv) PPC64_LR(30) PPC64_LR(31) -#ifdef PPC64_HAS_VMX +#if defined(__VSX__) // restore VS registers // (note that this also restores floating point registers and V registers, @@ -312,6 +312,7 @@ PPC64_CLVS_BOTTOM(n) PPC64_LF(30) PPC64_LF(31) +#if defined(__ALTIVEC__) // restore vector registers if any are in use ld %r5, PPC64_OFFS_VRSAVE(%r3) // test VRsave cmpwi %r5, 0 @@ -373,6 +374,7 @@ PPC64_CLV_UNALIGNED_BOTTOM(n) PPC64_CLV_UNALIGNEDh(31) #endif +#endif Lnovec: ld %r0, PPC64_OFFS_CR(%r3) @@ -431,6 +433,7 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv) lwz %r30,128(%r3) lwz %r31,132(%r3) +#ifndef __NO_FPRS__ // restore float registers lfd %f0, 160(%r3) lfd %f1, 168(%r3) @@ -464,7 +467,9 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv) lfd %f29,392(%r3) lfd %f30,400(%r3) lfd %f31,408(%r3) +#endif +#if defined(__ALTIVEC__) // restore vector registers if any are in use lwz %r5, 156(%r3) // test VRsave cmpwi %r5, 0 @@ -537,6 +542,7 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv) LOAD_VECTOR_UNALIGNEDh(29) LOAD_VECTOR_UNALIGNEDh(30) LOAD_VECTOR_UNALIGNEDh(31) +#endif Lnovec: lwz %r0, 136(%r3) // __cr diff --git a/libunwind/src/UnwindRegistersSave.S b/libunwind/src/UnwindRegistersSave.S index 51bb9b0688fd0..94fc8365455df 100644 --- a/libunwind/src/UnwindRegistersSave.S +++ b/libunwind/src/UnwindRegistersSave.S @@ -384,7 +384,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) mfvrsave %r0 std %r0, PPC64_OFFS_VRSAVE(%r3) -#ifdef PPC64_HAS_VMX +#if defined(__VSX__) // save VS registers // (note that this also saves floating point registers and V registers, // because part of VS is mapped to these registers) @@ -501,6 +501,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) PPC64_STF(30) PPC64_STF(31) +#if defined(__ALTIVEC__) // save vector registers // Use 16-bytes below the stack pointer as an @@ -548,6 +549,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) PPC64_STV_UNALIGNED(30) PPC64_STV_UNALIGNED(31) +#endif #endif li %r3, 0 // return UNW_ESUCCESS @@ -608,6 +610,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) mfctr %r0 stw %r0, 148(%r3) +#if !defined(__NO_FPRS__) // save float registers stfd %f0, 160(%r3) stfd %f1, 168(%r3) @@ -641,8 +644,9 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) stfd %f29,392(%r3) stfd %f30,400(%r3) stfd %f31,408(%r3) +#endif - +#if defined(__ALTIVEC__) // save vector registers subi %r4, %r1, 16 @@ -692,6 +696,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) SAVE_VECTOR_UNALIGNED(%v29, 424+0x1D0) SAVE_VECTOR_UNALIGNED(%v30, 424+0x1E0) SAVE_VECTOR_UNALIGNED(%v31, 424+0x1F0) +#endif li %r3, 0 // return UNW_ESUCCESS blr diff --git a/libunwind/src/assembly.h b/libunwind/src/assembly.h index 3b1e6e6d01d7a..f2f7c848307e2 100644 --- a/libunwind/src/assembly.h +++ b/libunwind/src/assembly.h @@ -25,9 +25,6 @@ #define PPC64_OFFS_VRSAVE 304 #define PPC64_OFFS_FP 312 #define PPC64_OFFS_V 824 -#ifdef _ARCH_PWR8 -#define PPC64_HAS_VMX -#endif #elif defined(__APPLE__) && defined(__aarch64__) #define SEPARATOR %% #else diff --git a/libunwind/src/config.h b/libunwind/src/config.h index e20d51a20212f..9efed05405c6a 100644 --- a/libunwind/src/config.h +++ b/libunwind/src/config.h @@ -116,10 +116,6 @@ #endif #endif -#if defined(__powerpc64__) && defined(_ARCH_PWR8) -#define PPC64_HAS_VMX -#endif - #ifndef _LIBUNWIND_REMEMBER_HEAP_ALLOC #if defined(_LIBUNWIND_REMEMBER_STACK_ALLOC) || defined(__APPLE__) || \ defined(__linux__) || defined(__ANDROID__) || defined(__MINGW32__) || \ diff --git a/lld/COFF/DriverUtils.cpp b/lld/COFF/DriverUtils.cpp index 7de73f2cfe491..f289e66dc6d5e 100644 --- a/lld/COFF/DriverUtils.cpp +++ b/lld/COFF/DriverUtils.cpp @@ -852,7 +852,7 @@ opt::InputArgList ArgParser::parse(ArrayRef argv) { handleColorDiagnostics(args); - for (auto *arg : args.filtered(OPT_UNKNOWN)) { + for (opt::Arg *arg : args.filtered(OPT_UNKNOWN)) { std::string nearest; if (optTable.findNearest(arg->getAsString(args), nearest) > 1) warn("ignoring unknown argument '" + arg->getAsString(args) + "'"); diff --git a/lld/COFF/InputFiles.h b/lld/COFF/InputFiles.h index f657d8f0a808d..3fa6819157a91 100644 --- a/lld/COFF/InputFiles.h +++ b/lld/COFF/InputFiles.h @@ -358,7 +358,7 @@ class ImportFile : public InputFile { const coff_import_header *hdr; Chunk *location = nullptr; - // We want to eliminate dllimported symbols if no one actually refers them. + // We want to eliminate dllimported symbols if no one actually refers to them. // These "Live" bits are used to keep track of which import library members // are actually in use. // diff --git a/lld/COFF/MinGW.cpp b/lld/COFF/MinGW.cpp index f7f45464bcf54..5bb7467afe5e9 100644 --- a/lld/COFF/MinGW.cpp +++ b/lld/COFF/MinGW.cpp @@ -238,6 +238,19 @@ void lld::coff::wrapSymbols(ArrayRef wrapped) { for (const WrappedSymbol &w : wrapped) { map[w.sym] = w.wrap; map[w.real] = w.sym; + if (Defined *d = dyn_cast(w.wrap)) { + Symbol *imp = symtab->find(("__imp_" + w.sym->getName()).str()); + // Create a new defined local import for the wrap symbol. If + // no imp prefixed symbol existed, there's no need for it. + // (We can't easily distinguish whether any object file actually + // referenced it or not, though.) + if (imp) { + DefinedLocalImport *wrapimp = make( + saver.save("__imp_" + w.wrap->getName()), d); + symtab->localImportChunks.push_back(wrapimp->getChunk()); + map[imp] = wrapimp; + } + } } // Update pointers in input files. diff --git a/lld/COFF/PDB.cpp b/lld/COFF/PDB.cpp index 5e65eca5b9fe4..36526de7796c4 100644 --- a/lld/COFF/PDB.cpp +++ b/lld/COFF/PDB.cpp @@ -500,6 +500,9 @@ void PDBLinker::mergeSymbolRecords(TpiSource *source, cantFail(symData.readBytes(0, symData.getLength(), symsBuffer)); SmallVector scopes; + if (symsBuffer.empty()) + warn("empty symbols subsection in " + file->getName()); + // Iterate every symbol to check if any need to be realigned, and if so, how // much space we need to allocate for them. bool needsRealignment = false; diff --git a/lld/Common/Strings.cpp b/lld/Common/Strings.cpp index 17c2c207491ff..e3148d3d974dc 100644 --- a/lld/Common/Strings.cpp +++ b/lld/Common/Strings.cpp @@ -21,12 +21,11 @@ using namespace lld; // Returns the demangled C++ symbol name for name. std::string lld::demangleItanium(StringRef name) { - // itaniumDemangle can be used to demangle strings other than symbol - // names which do not necessarily start with "_Z". Name can be - // either a C or C++ symbol. Don't call demangle if the name - // does not look like a C++ symbol name to avoid getting unexpected - // result for a C symbol that happens to match a mangled type name. - if (!name.startswith("_Z")) + // demangleItanium() can be called for all symbols. Only demangle C++ symbols, + // to avoid getting unexpected result for a C symbol that happens to match a + // mangled type name such as "Pi" (which would demangle to "int*"). + if (!name.startswith("_Z") && !name.startswith("__Z") && + !name.startswith("___Z") && !name.startswith("____Z")) return std::string(name); return demangle(std::string(name)); diff --git a/lld/ELF/Arch/AArch64.cpp b/lld/ELF/Arch/AArch64.cpp index 637046e90bbd3..e612519030594 100644 --- a/lld/ELF/Arch/AArch64.cpp +++ b/lld/ELF/Arch/AArch64.cpp @@ -46,8 +46,7 @@ class AArch64 : public TargetInfo { bool usesOnlyLowPageBits(RelType type) const override; void relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const override; - RelExpr adjustRelaxExpr(RelType type, const uint8_t *data, - RelExpr expr) const override; + RelExpr adjustTlsExpr(RelType type, RelExpr expr) const override; void relaxTlsGdToLe(uint8_t *loc, const Relocation &rel, uint64_t val) const override; void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel, @@ -159,8 +158,7 @@ RelExpr AArch64::getRelExpr(RelType type, const Symbol &s, } } -RelExpr AArch64::adjustRelaxExpr(RelType type, const uint8_t *data, - RelExpr expr) const { +RelExpr AArch64::adjustTlsExpr(RelType type, RelExpr expr) const { if (expr == R_RELAX_TLS_GD_TO_IE) { if (type == R_AARCH64_TLSDESC_ADR_PAGE21) return R_AARCH64_RELAX_TLS_GD_TO_IE_PAGE_PC; diff --git a/lld/ELF/Arch/PPC.cpp b/lld/ELF/Arch/PPC.cpp index a004cf74ddd88..88a1b2143b8e0 100644 --- a/lld/ELF/Arch/PPC.cpp +++ b/lld/ELF/Arch/PPC.cpp @@ -45,8 +45,7 @@ class PPC final : public TargetInfo { bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override; void relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const override; - RelExpr adjustRelaxExpr(RelType type, const uint8_t *data, - RelExpr expr) const override; + RelExpr adjustTlsExpr(RelType type, RelExpr expr) const override; int getTlsGdRelaxSkip(RelType type) const override; void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel, uint64_t val) const override; @@ -360,8 +359,7 @@ void PPC::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { } } -RelExpr PPC::adjustRelaxExpr(RelType type, const uint8_t *data, - RelExpr expr) const { +RelExpr PPC::adjustTlsExpr(RelType type, RelExpr expr) const { if (expr == R_RELAX_TLS_GD_TO_IE) return R_RELAX_TLS_GD_TO_IE_GOT_OFF; if (expr == R_RELAX_TLS_LD_TO_LE) diff --git a/lld/ELF/Arch/PPC64.cpp b/lld/ELF/Arch/PPC64.cpp index 8a3de2b3cbb29..65652b1c471f7 100644 --- a/lld/ELF/Arch/PPC64.cpp +++ b/lld/ELF/Arch/PPC64.cpp @@ -382,8 +382,9 @@ class PPC64 final : public TargetInfo { int64_t a) const override; uint32_t getThunkSectionSpacing() const override; bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override; - RelExpr adjustRelaxExpr(RelType type, const uint8_t *data, - RelExpr expr) const override; + RelExpr adjustTlsExpr(RelType type, RelExpr expr) const override; + RelExpr adjustGotPcExpr(RelType type, int64_t addend, + const uint8_t *loc) const override; void relaxGot(uint8_t *loc, const Relocation &rel, uint64_t val) const override; void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel, @@ -1390,22 +1391,24 @@ bool PPC64::inBranchRange(RelType type, uint64_t src, uint64_t dst) const { llvm_unreachable("unsupported relocation type used in branch"); } -RelExpr PPC64::adjustRelaxExpr(RelType type, const uint8_t *data, - RelExpr expr) const { +RelExpr PPC64::adjustTlsExpr(RelType type, RelExpr expr) const { + if (type != R_PPC64_GOT_TLSGD_PCREL34 && expr == R_RELAX_TLS_GD_TO_IE) + return R_RELAX_TLS_GD_TO_IE_GOT_OFF; + if (expr == R_RELAX_TLS_LD_TO_LE) + return R_RELAX_TLS_LD_TO_LE_ABS; + return expr; +} + +RelExpr PPC64::adjustGotPcExpr(RelType type, int64_t addend, + const uint8_t *loc) const { if ((type == R_PPC64_GOT_PCREL34 || type == R_PPC64_PCREL_OPT) && config->pcRelOptimize) { // It only makes sense to optimize pld since paddi means that the address // of the object in the GOT is required rather than the object itself. - assert(data && "Expecting an instruction encoding here"); - if ((readPrefixedInstruction(data) & 0xfc000000) == 0xe4000000) + if ((readPrefixedInstruction(loc) & 0xfc000000) == 0xe4000000) return R_PPC64_RELAX_GOT_PC; } - - if (type != R_PPC64_GOT_TLSGD_PCREL34 && expr == R_RELAX_TLS_GD_TO_IE) - return R_RELAX_TLS_GD_TO_IE_GOT_OFF; - if (expr == R_RELAX_TLS_LD_TO_LE) - return R_RELAX_TLS_LD_TO_LE_ABS; - return expr; + return R_GOT_PC; } // Reference: 3.7.4.1 of the 64-bit ELF V2 abi supplement. diff --git a/lld/ELF/Arch/X86.cpp b/lld/ELF/Arch/X86.cpp index 8c8824d53cce3..1e10bd3e685ae 100644 --- a/lld/ELF/Arch/X86.cpp +++ b/lld/ELF/Arch/X86.cpp @@ -37,8 +37,7 @@ class X86 : public TargetInfo { void relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const override; - RelExpr adjustRelaxExpr(RelType type, const uint8_t *data, - RelExpr expr) const override; + RelExpr adjustTlsExpr(RelType type, RelExpr expr) const override; void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel, uint64_t val) const override; void relaxTlsGdToLe(uint8_t *loc, const Relocation &rel, @@ -161,8 +160,7 @@ RelExpr X86::getRelExpr(RelType type, const Symbol &s, } } -RelExpr X86::adjustRelaxExpr(RelType type, const uint8_t *data, - RelExpr expr) const { +RelExpr X86::adjustTlsExpr(RelType type, RelExpr expr) const { switch (expr) { default: return expr; diff --git a/lld/ELF/Arch/X86_64.cpp b/lld/ELF/Arch/X86_64.cpp index 93fd8ecb7c8e1..618922844238c 100644 --- a/lld/ELF/Arch/X86_64.cpp +++ b/lld/ELF/Arch/X86_64.cpp @@ -40,8 +40,8 @@ class X86_64 : public TargetInfo { void applyJumpInstrMod(uint8_t *loc, JumpModType type, unsigned size) const override; - RelExpr adjustRelaxExpr(RelType type, const uint8_t *data, - RelExpr expr) const override; + RelExpr adjustGotPcExpr(RelType type, int64_t addend, + const uint8_t *loc) const override; void relaxGot(uint8_t *loc, const Relocation &rel, uint64_t val) const override; void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel, @@ -728,12 +728,12 @@ void X86_64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { } } -RelExpr X86_64::adjustRelaxExpr(RelType type, const uint8_t *data, - RelExpr relExpr) const { +RelExpr X86_64::adjustGotPcExpr(RelType type, int64_t addend, + const uint8_t *loc) const { if (type != R_X86_64_GOTPCRELX && type != R_X86_64_REX_GOTPCRELX) - return relExpr; - const uint8_t op = data[-2]; - const uint8_t modRm = data[-1]; + return R_GOT_PC; + const uint8_t op = loc[-2]; + const uint8_t modRm = loc[-1]; // FIXME: When PIC is disabled and foo is defined locally in the // lower 32 bit address space, memory operand in mov can be converted into @@ -748,11 +748,11 @@ RelExpr X86_64::adjustRelaxExpr(RelType type, const uint8_t *data, // We don't support test/binop instructions without a REX prefix. if (type == R_X86_64_GOTPCRELX) - return relExpr; + return R_GOT_PC; // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor. // If PIC then no relaxation is available. - return config->isPic ? relExpr : R_RELAX_GOT_PC_NOPIC; + return config->isPic ? R_GOT_PC : R_RELAX_GOT_PC_NOPIC; } // A subset of relaxations can only be applied for no-PIC. This method diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp index 783b85e7e27a6..c3f3d88b5d2d4 100644 --- a/lld/ELF/Driver.cpp +++ b/lld/ELF/Driver.cpp @@ -990,7 +990,8 @@ static void readConfigs(opt::InputArgList &args) { config->ltoNewPassManager = args.hasArg(OPT_lto_new_pass_manager); config->ltoNewPmPasses = args.getLastArgValue(OPT_lto_newpm_passes); config->ltoWholeProgramVisibility = - args.hasArg(OPT_lto_whole_program_visibility); + args.hasFlag(OPT_lto_whole_program_visibility, + OPT_no_lto_whole_program_visibility, false); config->ltoo = args::getInteger(args, OPT_lto_O, 2); config->ltoObjPath = args.getLastArgValue(OPT_lto_obj_path_eq); config->ltoPartitions = args::getInteger(args, OPT_lto_partitions, 1); diff --git a/lld/ELF/DriverUtils.cpp b/lld/ELF/DriverUtils.cpp index 03173565e5782..8ce9853c57afa 100644 --- a/lld/ELF/DriverUtils.cpp +++ b/lld/ELF/DriverUtils.cpp @@ -133,7 +133,7 @@ opt::InputArgList ELFOptTable::parse(ArrayRef argv) { if (missingCount) error(Twine(args.getArgString(missingIndex)) + ": missing argument"); - for (auto *arg : args.filtered(OPT_UNKNOWN)) { + for (opt::Arg *arg : args.filtered(OPT_UNKNOWN)) { std::string nearest; if (findNearest(arg->getAsString(args), nearest) > 1) error("unknown argument '" + arg->getAsString(args) + "'"); diff --git a/lld/ELF/Options.td b/lld/ELF/Options.td index 5171c08a8291f..db1c5d9698423 100644 --- a/lld/ELF/Options.td +++ b/lld/ELF/Options.td @@ -539,8 +539,9 @@ def lto_cs_profile_file: JJ<"lto-cs-profile-file=">, def lto_obj_path_eq: JJ<"lto-obj-path=">; def lto_sample_profile: JJ<"lto-sample-profile=">, HelpText<"Sample profile file path">; -def lto_whole_program_visibility: FF<"lto-whole-program-visibility">, - HelpText<"Asserts that the LTO link has whole program visibility">; +defm lto_whole_program_visibility: BB<"lto-whole-program-visibility", + "Asserts that the LTO link has whole program visibility", + "Asserts that the LTO link does not have whole program visibility">; def disable_verify: F<"disable-verify">; defm mllvm: Eq<"mllvm", "Additional arguments to forward to LLVM's option processing">; def opt_remarks_filename: Separate<["--"], "opt-remarks-filename">, diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp index abb21f1d72743..7860aeeefcc33 100644 --- a/lld/ELF/Relocations.cpp +++ b/lld/ELF/Relocations.cpp @@ -230,8 +230,8 @@ handleTlsRelocation(RelType type, Symbol &sym, InputSectionBase &c, // Local-Dynamic relocs can be relaxed to Local-Exec. if (toExecRelax) { c.relocations.push_back( - {target->adjustRelaxExpr(type, nullptr, R_RELAX_TLS_LD_TO_LE), type, - offset, addend, &sym}); + {target->adjustTlsExpr(type, R_RELAX_TLS_LD_TO_LE), type, offset, + addend, &sym}); return target->getTlsGdRelaxSkip(type); } if (expr == R_TLSLD_HINT) @@ -250,9 +250,8 @@ handleTlsRelocation(RelType type, Symbol &sym, InputSectionBase &c, // Local-Dynamic relocs can be relaxed to Local-Exec. if (expr == R_DTPREL && toExecRelax) { - c.relocations.push_back( - {target->adjustRelaxExpr(type, nullptr, R_RELAX_TLS_LD_TO_LE), type, - offset, addend, &sym}); + c.relocations.push_back({target->adjustTlsExpr(type, R_RELAX_TLS_LD_TO_LE), + type, offset, addend, &sym}); return 1; } @@ -300,8 +299,8 @@ handleTlsRelocation(RelType type, Symbol &sym, InputSectionBase &c, // depending on the symbol being locally defined or not. if (sym.isPreemptible) { c.relocations.push_back( - {target->adjustRelaxExpr(type, nullptr, R_RELAX_TLS_GD_TO_IE), type, - offset, addend, &sym}); + {target->adjustTlsExpr(type, R_RELAX_TLS_GD_TO_IE), type, offset, + addend, &sym}); if (!sym.isInGot()) { in.got->addEntry(sym); mainPart->relaDyn->addReloc(target->tlsGotRel, in.got, sym.getGotOffset(), @@ -309,8 +308,8 @@ handleTlsRelocation(RelType type, Symbol &sym, InputSectionBase &c, } } else { c.relocations.push_back( - {target->adjustRelaxExpr(type, nullptr, R_RELAX_TLS_GD_TO_LE), type, - offset, addend, &sym}); + {target->adjustTlsExpr(type, R_RELAX_TLS_GD_TO_LE), type, offset, + addend, &sym}); } return target->getTlsGdRelaxSkip(type); } @@ -1361,9 +1360,7 @@ static void scanReloc(InputSectionBase &sec, OffsetGetter &getOffset, RelTy *&i, // runtime, because the main executable is always at the beginning of a search // list. We can leverage that fact. if (!sym.isPreemptible && (!sym.isGnuIFunc() || config->zIfuncNoplt)) { - if (expr == R_GOT_PC && !isAbsoluteValue(sym)) { - expr = target->adjustRelaxExpr(type, relocatedAddr, expr); - } else { + if (expr != R_GOT_PC) { // The 0x8000 bit of r_addend of R_PPC_PLTREL24 is used to choose call // stub type. It should be ignored if optimized to R_PC. if (config->emachine == EM_PPC && expr == R_PPC32_PLTREL) @@ -1375,6 +1372,8 @@ static void scanReloc(InputSectionBase &sec, OffsetGetter &getOffset, RelTy *&i, type == R_HEX_GD_PLT_B22_PCREL_X || type == R_HEX_GD_PLT_B32_PCREL_X))) expr = fromPlt(expr); + } else if (!isAbsoluteValue(sym)) { + expr = target->adjustGotPcExpr(type, addend, relocatedAddr); } } diff --git a/lld/ELF/Target.cpp b/lld/ELF/Target.cpp index 6abd8b452e238..cb816d8ed12d1 100644 --- a/lld/ELF/Target.cpp +++ b/lld/ELF/Target.cpp @@ -150,11 +150,15 @@ bool TargetInfo::inBranchRange(RelType type, uint64_t src, uint64_t dst) const { return true; } -RelExpr TargetInfo::adjustRelaxExpr(RelType type, const uint8_t *data, - RelExpr expr) const { +RelExpr TargetInfo::adjustTlsExpr(RelType type, RelExpr expr) const { return expr; } +RelExpr TargetInfo::adjustGotPcExpr(RelType type, int64_t addend, + const uint8_t *data) const { + return R_GOT_PC; +} + void TargetInfo::relaxGot(uint8_t *loc, const Relocation &rel, uint64_t val) const { llvm_unreachable("Should not have claimed to be relaxable"); diff --git a/lld/ELF/Target.h b/lld/ELF/Target.h index 9399ecf526f4f..68b6c5d2ca351 100644 --- a/lld/ELF/Target.h +++ b/lld/ELF/Target.h @@ -148,8 +148,9 @@ class TargetInfo { // non-split-stack callee this will return true. Otherwise returns false. bool needsMoreStackNonSplit = true; - virtual RelExpr adjustRelaxExpr(RelType type, const uint8_t *data, - RelExpr expr) const; + virtual RelExpr adjustTlsExpr(RelType type, RelExpr expr) const; + virtual RelExpr adjustGotPcExpr(RelType type, int64_t addend, + const uint8_t *loc) const; virtual void relaxGot(uint8_t *loc, const Relocation &rel, uint64_t val) const; virtual void relaxTlsGdToIe(uint8_t *loc, const Relocation &rel, diff --git a/lld/MachO/Config.h b/lld/MachO/Config.h index 633dbb0184fca..82c017063d449 100644 --- a/lld/MachO/Config.h +++ b/lld/MachO/Config.h @@ -43,6 +43,7 @@ struct Configuration { uint32_t headerPad; llvm::StringRef installName; llvm::StringRef outputFile; + bool demangle = false; llvm::MachO::Architecture arch; PlatformInfo platform; llvm::MachO::HeaderFileType outputType; diff --git a/lld/MachO/Driver.cpp b/lld/MachO/Driver.cpp index 3b1daadf9f0a3..0f5da218e80d4 100644 --- a/lld/MachO/Driver.cpp +++ b/lld/MachO/Driver.cpp @@ -584,6 +584,7 @@ bool macho::link(llvm::ArrayRef argsArr, bool canExitEarly, config->runtimePaths = args::getStrings(args, OPT_rpath); config->allLoad = args.hasArg(OPT_all_load); config->forceLoadObjC = args.hasArg(OPT_ObjC); + config->demangle = args.hasArg(OPT_demangle); if (const opt::Arg *arg = args.getLastArg(OPT_static, OPT_dynamic)) config->staticLink = (arg->getOption().getID() == OPT_static); diff --git a/lld/MachO/DriverUtils.cpp b/lld/MachO/DriverUtils.cpp index 3899348666b4c..0322c20fcb693 100644 --- a/lld/MachO/DriverUtils.cpp +++ b/lld/MachO/DriverUtils.cpp @@ -75,8 +75,14 @@ opt::InputArgList MachOOptTable::parse(ArrayRef argv) { handleColorDiagnostics(args); - for (opt::Arg *arg : args.filtered(OPT_UNKNOWN)) - error("unknown argument: " + arg->getSpelling()); + for (opt::Arg *arg : args.filtered(OPT_UNKNOWN)) { + std::string nearest; + if (findNearest(arg->getAsString(args), nearest) > 1) + error("unknown argument '" + arg->getAsString(args) + "'"); + else + error("unknown argument '" + arg->getAsString(args) + + "', did you mean '" + nearest + "'"); + } return args; } diff --git a/lld/MachO/Options.td b/lld/MachO/Options.td index 3695bd1e2868e..4aa999826fb65 100644 --- a/lld/MachO/Options.td +++ b/lld/MachO/Options.td @@ -1107,9 +1107,7 @@ def debug_snapshot : Flag<["-"], "debug_snapshot">, Flags<[HelpHidden]>, Group; def demangle : Flag<["-"], "demangle">, - HelpText<"This option is undocumented in ld64">, - Flags<[HelpHidden]>, - Group; + HelpText<"Demangle symbol names in diagnostics">; def dyld_env : Flag<["-"], "dyld_env">, HelpText<"This option is undocumented in ld64">, Flags<[HelpHidden]>, diff --git a/lld/MachO/Symbols.cpp b/lld/MachO/Symbols.cpp index 75c699781a619..87bbab00901f7 100644 --- a/lld/MachO/Symbols.cpp +++ b/lld/MachO/Symbols.cpp @@ -33,8 +33,8 @@ void LazySymbol::fetchArchiveMember() { file->fetch(sym); } // Returns a symbol for an error message. std::string lld::toString(const Symbol &sym) { - if (Optional s = demangleItanium(sym.getName())) - return *s; + if (config->demangle) + return demangleItanium(sym.getName()); return std::string(sym.getName()); } diff --git a/lld/MachO/Writer.cpp b/lld/MachO/Writer.cpp index c5239469ff2db..fa42c1c7e61c3 100644 --- a/lld/MachO/Writer.cpp +++ b/lld/MachO/Writer.cpp @@ -379,7 +379,7 @@ void Writer::scanRelocations() { for (Reloc &r : isec->relocs) { if (auto *s = r.referent.dyn_cast()) { if (isa(s)) - error("undefined symbol " + s->getName() + ", referenced from " + + error("undefined symbol " + toString(*s) + ", referenced from " + sys::path::filename(isec->file->getName())); else target->prepareSymbolRelocation(s, isec, r); diff --git a/lld/test/COFF/empty-subsection.s b/lld/test/COFF/empty-subsection.s new file mode 100644 index 0000000000000..e573d5b57bdd7 --- /dev/null +++ b/lld/test/COFF/empty-subsection.s @@ -0,0 +1,20 @@ +# REQUIRES: x86 +# RUN: llvm-mc -triple=x86_64-windows-msvc -filetype=obj -o %t.obj %s +# RUN: lld-link /entry:main /debug /out:%t.exe %t.obj 2>&1 | FileCheck %s + +# CHECK: warning: empty symbols subsection + +.globl main +.Lfunc_begin0: +main: + xorl %eax, %eax + retq +.Lfunc_end0: + +.section .debug$S,"dr" + .p2align 2 + .long 4 # Debug section magic + .long 241 # Symbol subsection for globals + .long .Ltmp5-.Ltmp4 # Subsection size +.Ltmp4: +.Ltmp5: diff --git a/lld/test/COFF/wrap-dllimport.s b/lld/test/COFF/wrap-dllimport.s new file mode 100644 index 0000000000000..d7662b29fdc78 --- /dev/null +++ b/lld/test/COFF/wrap-dllimport.s @@ -0,0 +1,42 @@ +// REQUIRES: x86 + +// Check that we can wrap a dllimported symbol, so that references to +// __imp_ gets redirected to a defined local import instead. + +// RUN: split-file %s %t.dir +// RUN: llvm-mc -filetype=obj -triple=i686-win32-gnu %t.dir/main.s -o %t.main.obj +// RUN: llvm-mc -filetype=obj -triple=i686-win32-gnu %t.dir/other.s -o %t.other.obj + +// RUN: lld-link -dll -out:%t.dll %t.other.obj -noentry -safeseh:no -export:foo -implib:%t.lib +// RUN: lld-link -out:%t.exe %t.main.obj %t.lib -entry:entry -subsystem:console -debug:symtab -safeseh:no -wrap:foo -lldmap:%t.map +// RUN: llvm-objdump -s -d --print-imm-hex %t.exe | FileCheck %s + +// CHECK: Contents of section .rdata: +// CHECK-NEXT: 402000 06104000 + +// CHECK: Disassembly of section .text: +// CHECK-EMPTY: +// CHECK: 00401000 <_entry>: +// CHECK-NEXT: 401000: ff 25 00 20 40 00 jmpl *0x402000 +// CHECK-EMPTY: +// CHECK-NEXT: 00401006 <___wrap_foo>: +// CHECK-NEXT: 401006: c3 retl + +// The jmpl instruction in _entry points at an address in 0x402000, +// which is the first 4 bytes of the .rdata section (above), which is a +// pointer that points at ___wrap_foo. + +#--- main.s +.global _entry +_entry: + jmpl *__imp__foo + +.global ___wrap_foo +___wrap_foo: + ret + +#--- other.s +.global _foo + +_foo: + ret diff --git a/lld/test/COFF/wrap-import.ll b/lld/test/COFF/wrap-import.ll index c9a72de36e32b..e03af1e9c7f08 100644 --- a/lld/test/COFF/wrap-import.ll +++ b/lld/test/COFF/wrap-import.ll @@ -1,7 +1,8 @@ // REQUIRES: x86 // Check that wrapping works when the wrapped symbol is imported from a -// different DLL. +// different DLL, redirecting references that used to point at the import +// thunk, towards the local wrap function instead. // RUN: split-file %s %t.dir // RUN: llc %t.dir/main.ll -o %t.main.obj --filetype=obj diff --git a/lld/test/ELF/lto/devirt_vcall_vis_public.ll b/lld/test/ELF/lto/devirt_vcall_vis_public.ll index 0d344ec9483df..46e23537d4fa5 100644 --- a/lld/test/ELF/lto/devirt_vcall_vis_public.ll +++ b/lld/test/ELF/lto/devirt_vcall_vis_public.ll @@ -1,6 +1,9 @@ ; REQUIRES: x86 ; Test that --lto-whole-program-visibility enables devirtualization. +; Note that the --export-dynamic used below is simply to ensure symbols are +; retained during linking. + ; Index based WPD ; Generate unsplit module with summary for ThinLTO index-based WPD. ; RUN: opt --thinlto-bc -o %t2.o %s @@ -31,6 +34,10 @@ ; RUN: ld.lld %t2.o -o %t3 -save-temps \ ; RUN: -mllvm -pass-remarks=. --export-dynamic 2>&1 | FileCheck %s --implicit-check-not single-impl --allow-empty ; RUN: llvm-dis %t2.o.4.opt.bc -o - | FileCheck %s --check-prefix=CHECK-NODEVIRT-IR +; Ensure --no-lto-whole-program-visibility overrides explicit --lto-whole-program-visibility. +; RUN: ld.lld %t2.o -o %t3 -save-temps --lto-whole-program-visibility --no-lto-whole-program-visibility \ +; RUN: -mllvm -pass-remarks=. --export-dynamic 2>&1 | FileCheck %s --implicit-check-not single-impl --allow-empty +; RUN: llvm-dis %t2.o.4.opt.bc -o - | FileCheck %s --check-prefix=CHECK-NODEVIRT-IR ; Hybrid WPD ; RUN: ld.lld %t.o -o %t3 -save-temps \ diff --git a/lld/test/ELF/undef.s b/lld/test/ELF/undef.s index 4f39d20dd6a05..931a482e1810b 100644 --- a/lld/test/ELF/undef.s +++ b/lld/test/ELF/undef.s @@ -27,9 +27,7 @@ # CHECK-NEXT: >>> {{.*}}:(.text+0x15) # CHECK-NEXT: >>> the vtable symbol may be undefined because the class is missing its key function (see https://lld.llvm.org/missingkeyfunction) -# Check that this symbol isn't demangled - -# CHECK: error: undefined symbol: __Z3fooi +# CHECK: error: undefined symbol: foo(int) # CHECK-NEXT: >>> referenced by undef.s # CHECK-NEXT: >>> {{.*}}:(.text+0x1A) diff --git a/lld/test/MachO/color-diagnostics.test b/lld/test/MachO/color-diagnostics.test index 3bf757b7b7158..b3c496f3b32d0 100644 --- a/lld/test/MachO/color-diagnostics.test +++ b/lld/test/MachO/color-diagnostics.test @@ -6,7 +6,7 @@ # RUN: not %lld -xyz --color-diagnostics=always /nosuchfile 2>&1 \ # RUN: | FileCheck -check-prefix=COLOR %s -# COLOR: {{lld: .\[0;31merror: .\[0munknown argument: -xyz}} +# COLOR: {{lld: .\[0;31merror: .\[0munknown argument '-xyz'}} # COLOR: {{lld: .\[0;31merror: .\[0mcannot open /nosuchfile}} # RUN: not %lld --color-diagnostics=foobar 2>&1 | FileCheck -check-prefix=ERR %s diff --git a/lld/test/MachO/demangle.s b/lld/test/MachO/demangle.s new file mode 100644 index 0000000000000..c3ff999a468d9 --- /dev/null +++ b/lld/test/MachO/demangle.s @@ -0,0 +1,15 @@ +# REQUIRES: x86 + +# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t.o + +# RUN: not %lld %t.o -o /dev/null 2>&1 | FileCheck %s +# RUN: not %lld -demangle %t.o -o /dev/null 2>&1 | \ +# RUN: FileCheck --check-prefix=DEMANGLE %s + +# CHECK: undefined symbol __Z1fv +# DEMANGLE: undefined symbol f() + +.globl _main +_main: + callq __Z1fv + ret diff --git a/lld/test/MachO/driver.test b/lld/test/MachO/driver.test new file mode 100644 index 0000000000000..229ec3ef69639 --- /dev/null +++ b/lld/test/MachO/driver.test @@ -0,0 +1,5 @@ +# RUN: not %lld ---help 2>&1 | FileCheck -check-prefix=SPELLHELP %s + +SPELLHELP: error: unknown argument '---help', did you mean '--help' +# FIXME: This should say "no input files" instead +SPELLHELP: error: undefined symbol: _main diff --git a/lld/test/MachO/silent-ignore.test b/lld/test/MachO/silent-ignore.test index 9e997d73aa971..2d11748357286 100644 --- a/lld/test/MachO/silent-ignore.test +++ b/lld/test/MachO/silent-ignore.test @@ -1,5 +1,4 @@ RUN: %lld -v \ -RUN: -demangle \ RUN: -dynamic \ RUN: -no_deduplicate \ RUN: -lto_library /lib/foo \ @@ -10,4 +9,4 @@ RUN: -objc_abi_version 2 \ RUN: -ios_simulator_version_min 9.0.0 \ RUN: -sdk_version 13.2 RUN: not %lld -v --not-an-ignored-argument 2>&1 | FileCheck %s -CHECK: error: unknown argument: --not-an-ignored-argument +CHECK: error: unknown argument '--not-an-ignored-argument' diff --git a/lld/test/wasm/debug-removed-fn.ll b/lld/test/wasm/debug-removed-fn.ll index 89a55a3d41878..7444171f1e2f5 100644 --- a/lld/test/wasm/debug-removed-fn.ll +++ b/lld/test/wasm/debug-removed-fn.ll @@ -3,7 +3,7 @@ ; RUN: llvm-dwarfdump -debug-line -debug-ranges %t.wasm | FileCheck %s ; CHECK: Address -; CHECK: 0x0000000000000005 +; CHECK: 0x0000000000000003 ; CHECK: 0x0000000000000000 ; CHECK: .debug_ranges contents: diff --git a/lld/test/wasm/weak-undefined-pic.s b/lld/test/wasm/weak-undefined-pic.s new file mode 100644 index 0000000000000..c12ef235d85f2 --- /dev/null +++ b/lld/test/wasm/weak-undefined-pic.s @@ -0,0 +1,90 @@ +# Checks handling of undefined weak external functions. When the +# static linker decides they are undefined, check GOT relocations +# resolve to zero (i.e. a global that contains zero.). +# +# RUN: llvm-mc -filetype=obj -triple=wasm32-unknown-unknown -o %t.o %s +# RUN: wasm-ld %t.o -o %t1.wasm +# RUN: obj2yaml %t1.wasm | FileCheck %s +# +# With `--unresolved-symbols=ignore-all` the behaviour should be the same +# as the default.> +# +# RUN: wasm-ld --unresolved-symbols=ignore-all %t.o -o %t2.wasm +# RUN: obj2yaml %t2.wasm | FileCheck %s + +.globl get_foo_addr +get_foo_addr: + .functype get_foo_addr () -> (i32) + global.get foo@GOT + end_function + +.globl _start +_start: + .functype _start () -> () + call get_foo_addr + end_function + +.weak foo +.functype foo () -> (i32) + +# Verify that we do not generate dynamnic relocations for the GOT entry. + +# CHECK-NOT: __wasm_apply_relocs + +# Verify that we do not generate an import for foo + +# CHECK-NOT: - Type: IMPORT + +# CHECK: - Type: GLOBAL +# CHECK-NEXT: Globals: +# CHECK-NEXT: - Index: 0 +# CHECK-NEXT: Type: I32 +# CHECK-NEXT: Mutable: true +# CHECK-NEXT: InitExpr: +# CHECK-NEXT: Opcode: I32_CONST +# CHECK-NEXT: Value: 66560 +# Global 'undefined_weak:foo' representing the GOT entry for foo +# Unlike other internal GOT entries that need to be mutable this one +# is immutable and not updated by `__wasm_apply_relocs` +# CHECK-NEXT: - Index: 1 +# CHECK-NEXT: Type: I32 +# CHECK-NEXT: Mutable: false +# CHECK-NEXT: InitExpr: +# CHECK-NEXT: Opcode: I32_CONST +# CHECK-NEXT: Value: 0 + +# CHECK: - Type: CUSTOM +# CHECK-NEXT: Name: name +# CHECK-NEXT: FunctionNames: +# CHECK-NEXT: - Index: 0 +# CHECK-NEXT: Name: 'undefined_weak:foo' +# CHECK-NEXT: - Index: 1 +# CHECK-NEXT: Name: get_foo_addr +# CHECK-NEXT: - Index: 2 +# CHECK-NEXT: Name: _start +# CHECK-NEXT: GlobalNames: +# CHECK-NEXT: - Index: 0 +# CHECK-NEXT: Name: __stack_pointer +# CHECK-NEXT: - Index: 1 +# CHECK-NEXT: Name: 'undefined_weak:foo' + +# With `-pie` or `-shared` the resolution should is defered to the dynamic +# linker and the function address should be imported as GOT.func.foo. +# +# RUN: wasm-ld --experimental-pic -pie %t.o -o %t3.wasm +# RUN: obj2yaml %t3.wasm | FileCheck %s --check-prefix=IMPORT + +# IMPORT: - Type: IMPORT +# IMPORT: - Module: GOT.func +# IMPORT-NEXT: Field: foo +# IMPORT-NEXT: Kind: GLOBAL +# IMPORT-NEXT: GlobalType: I32 +# IMPORT-NEXT: GlobalMutable: true + +# IMPORT: GlobalNames: +# IMPORT-NEXT: - Index: 0 +# IMPORT-NEXT: Name: __memory_base +# IMPORT-NEXT: - Index: 1 +# IMPORT-NEXT: Name: __table_base +# IMPORT-NEXT: - Index: 2 +# IMPORT-NEXT: Name: foo diff --git a/lld/tools/lld/CMakeLists.txt b/lld/tools/lld/CMakeLists.txt index e6f72fcd3488d..5cff736ff57fe 100644 --- a/lld/tools/lld/CMakeLists.txt +++ b/lld/tools/lld/CMakeLists.txt @@ -24,7 +24,8 @@ install(TARGETS lld RUNTIME DESTINATION bin) if(NOT LLD_SYMLINKS_TO_CREATE) - set(LLD_SYMLINKS_TO_CREATE lld-link ld.lld ld64.lld wasm-ld) + set(LLD_SYMLINKS_TO_CREATE + lld-link ld.lld ld64.lld ld64.lld.darwinnew wasm-ld) endif() foreach(link ${LLD_SYMLINKS_TO_CREATE}) diff --git a/lld/wasm/Driver.cpp b/lld/wasm/Driver.cpp index 8aa124795f6fe..f26b190b6058a 100644 --- a/lld/wasm/Driver.cpp +++ b/lld/wasm/Driver.cpp @@ -973,7 +973,7 @@ void LinkerDriver::link(ArrayRef argsArr) { warn(Twine("symbol exported via --export not found: ") + arg->getValue()); } - if (!config->relocatable) { + if (!config->relocatable && !config->isPic) { // Add synthetic dummies for weak undefined functions. Must happen // after LTO otherwise functions may not yet have signatures. symtab->handleWeakUndefines(); diff --git a/lld/wasm/MarkLive.cpp b/lld/wasm/MarkLive.cpp index 4bce688770400..235936e4ef3ec 100644 --- a/lld/wasm/MarkLive.cpp +++ b/lld/wasm/MarkLive.cpp @@ -142,7 +142,7 @@ void MarkLive::mark() { reloc.Type == R_WASM_TABLE_INDEX_I32 || reloc.Type == R_WASM_TABLE_INDEX_I64) { auto *funcSym = cast(sym); - if (funcSym->hasTableIndex() && funcSym->getTableIndex() == 0) + if (funcSym->isStub) continue; } diff --git a/lld/wasm/Relocations.cpp b/lld/wasm/Relocations.cpp index 5b131d4f23f40..bd07c0410dc57 100644 --- a/lld/wasm/Relocations.cpp +++ b/lld/wasm/Relocations.cpp @@ -62,7 +62,9 @@ static void reportUndefined(Symbol *sym) { << "ignoring undefined symbol: " + toString(*sym) + "\n"); f->stubFunction = symtab->createUndefinedStub(*f->getSignature()); f->stubFunction->markLive(); - f->setTableIndex(0); + // Mark the function itself as a stub which prevents it from being + // assigned a table entry. + f->isStub = true; } } break; diff --git a/lld/wasm/SymbolTable.cpp b/lld/wasm/SymbolTable.cpp index fc92020d07ddc..d8a070c3c2f23 100644 --- a/lld/wasm/SymbolTable.cpp +++ b/lld/wasm/SymbolTable.cpp @@ -673,9 +673,9 @@ InputFunction *SymbolTable::replaceWithUnreachable(Symbol *sym, // to be exported outside the object file. replaceSymbol(sym, debugName, WASM_SYMBOL_BINDING_LOCAL, nullptr, func); - // Ensure it compares equal to the null pointer, and so that table relocs - // don't pull in the stub body (only call-operand relocs should do that). - func->setTableIndex(0); + // Ensure the stub function doesn't get a table entry. Its address + // should always compare equal to the null pointer. + sym->isStub = true; return func; } diff --git a/lld/wasm/Symbols.h b/lld/wasm/Symbols.h index 865a9e7fee99f..90fb5194edcd9 100644 --- a/lld/wasm/Symbols.h +++ b/lld/wasm/Symbols.h @@ -124,7 +124,7 @@ class Symbol { Symbol(StringRef name, Kind k, uint32_t flags, InputFile *f) : name(name), file(f), symbolKind(k), referenced(!config->gcSections), requiresGOT(false), isUsedInRegularObj(false), forceExport(false), - canInline(false), traced(false), flags(flags) {} + canInline(false), traced(false), isStub(false), flags(flags) {} StringRef name; InputFile *file; @@ -157,6 +157,11 @@ class Symbol { // True if this symbol is specified by --trace-symbol option. bool traced : 1; + // True if this symbol is a linker-synthesized stub function (traps when + // called) and should otherwise be treated as missing/undefined. See + // SymbolTable::replaceWithUndefined. + bool isStub : 1; + uint32_t flags; }; diff --git a/lld/wasm/SyntheticSections.cpp b/lld/wasm/SyntheticSections.cpp index 407eb8084d0e5..f141e37b49881 100644 --- a/lld/wasm/SyntheticSections.cpp +++ b/lld/wasm/SyntheticSections.cpp @@ -223,7 +223,7 @@ void TableSection::writeBody() { limits = {0, tableSize, 0}; else limits = {WASM_LIMITS_FLAG_HAS_MAX, tableSize, tableSize}; - writeTableType(os, WasmTable{0, WASM_TYPE_FUNCREF, limits}); + writeTableType(os, WasmTableType{WASM_TYPE_FUNCREF, limits}); } void MemorySection::writeBody() { @@ -303,6 +303,8 @@ void GlobalSection::generateRelocationCode(raw_ostream &os) const { writeU8(os, opcode_ptr_const, "CONST"); writeSleb128(os, d->getVirtualAddress(), "offset"); } else if (auto *f = dyn_cast(sym)) { + if (f->isStub) + continue; // Get __table_base writeU8(os, WASM_OPCODE_GLOBAL_GET, "GLOBAL_GET"); writeUleb128(os, WasmSym::tableBase->getGlobalIndex(), "__table_base"); @@ -329,12 +331,16 @@ void GlobalSection::writeBody() { // TODO(wvo): when do these need I64_CONST? for (const Symbol *sym : internalGotSymbols) { WasmGlobal global; - global.Type = {WASM_TYPE_I32, config->isPic}; + // In the case of dynamic linking, internal GOT entries + // need to be mutable since they get updated to the correct + // runtime value during `__wasm_apply_relocs`. + bool mutable_ = config->isPic & !sym->isStub; + global.Type = {WASM_TYPE_I32, mutable_}; global.InitExpr.Opcode = WASM_OPCODE_I32_CONST; if (auto *d = dyn_cast(sym)) global.InitExpr.Value.Int32 = d->getVirtualAddress(); else if (auto *f = dyn_cast(sym)) - global.InitExpr.Value.Int32 = f->getTableIndex(); + global.InitExpr.Value.Int32 = f->isStub ? 0 : f->getTableIndex(); else { assert(isa(sym)); global.InitExpr.Value.Int32 = 0; @@ -375,7 +381,10 @@ void StartSection::writeBody() { } void ElemSection::addEntry(FunctionSymbol *sym) { - if (sym->hasTableIndex()) + // Don't add stub functions to the wasm table. The address of all stub + // functions should be zero and they should they don't appear in the table. + // They only exist so that the calls to missing functions can validate. + if (sym->hasTableIndex() || sym->isStub) return; sym->setTableIndex(config->tableBase + indirectFunctions.size()); indirectFunctions.emplace_back(sym); diff --git a/lld/wasm/WriterUtils.cpp b/lld/wasm/WriterUtils.cpp index cd221855a12bf..81fcee4e68fed 100644 --- a/lld/wasm/WriterUtils.cpp +++ b/lld/wasm/WriterUtils.cpp @@ -195,7 +195,7 @@ void writeEvent(raw_ostream &os, const WasmEvent &event) { writeEventType(os, event.Type); } -void writeTableType(raw_ostream &os, const llvm::wasm::WasmTable &type) { +void writeTableType(raw_ostream &os, const WasmTableType &type) { writeU8(os, WASM_TYPE_FUNCREF, "table type"); writeLimits(os, type.Limits); } diff --git a/lld/wasm/WriterUtils.h b/lld/wasm/WriterUtils.h index 86df768af5c60..98f5ab1fbf3b1 100644 --- a/lld/wasm/WriterUtils.h +++ b/lld/wasm/WriterUtils.h @@ -54,7 +54,7 @@ void writeEventType(raw_ostream &os, const llvm::wasm::WasmEventType &type); void writeEvent(raw_ostream &os, const llvm::wasm::WasmEvent &event); -void writeTableType(raw_ostream &os, const llvm::wasm::WasmTable &type); +void writeTableType(raw_ostream &os, const llvm::wasm::WasmTableType &type); void writeImport(raw_ostream &os, const llvm::wasm::WasmImport &import); diff --git a/lldb/include/lldb/Target/Process.h b/lldb/include/lldb/Target/Process.h index 7f1e1e8765568..744deab276c49 100644 --- a/lldb/include/lldb/Target/Process.h +++ b/lldb/include/lldb/Target/Process.h @@ -537,7 +537,8 @@ class Process : public std::enable_shared_from_this, static lldb::ProcessSP FindPlugin(lldb::TargetSP target_sp, llvm::StringRef plugin_name, lldb::ListenerSP listener_sp, - const FileSpec *crash_file_path); + const FileSpec *crash_file_path, + bool can_connect); /// Static function that can be used with the \b host function /// Host::StartMonitoringChildProcess (). diff --git a/lldb/include/lldb/Target/ProcessTrace.h b/lldb/include/lldb/Target/ProcessTrace.h index f947fbe8cdb42..53b3e704c17b0 100644 --- a/lldb/include/lldb/Target/ProcessTrace.h +++ b/lldb/include/lldb/Target/ProcessTrace.h @@ -77,7 +77,8 @@ class ProcessTrace : public PostMortemProcess { private: static lldb::ProcessSP CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, - const FileSpec *crash_file_path); + const FileSpec *crash_file_path, + bool can_connect); }; } // namespace lldb_private diff --git a/lldb/include/lldb/Target/Target.h b/lldb/include/lldb/Target/Target.h index f77917a8812f7..47568c9e44299 100644 --- a/lldb/include/lldb/Target/Target.h +++ b/lldb/include/lldb/Target/Target.h @@ -573,7 +573,8 @@ class Target : public std::enable_shared_from_this, // used. const lldb::ProcessSP &CreateProcess(lldb::ListenerSP listener_sp, llvm::StringRef plugin_name, - const FileSpec *crash_file); + const FileSpec *crash_file, + bool can_connect); const lldb::ProcessSP &GetProcessSP() const; diff --git a/lldb/include/lldb/lldb-private-interfaces.h b/lldb/include/lldb/lldb-private-interfaces.h index 1a4eaba7cc5e7..df33f8af0e142 100644 --- a/lldb/include/lldb/lldb-private-interfaces.h +++ b/lldb/include/lldb/lldb-private-interfaces.h @@ -76,7 +76,7 @@ typedef lldb::PlatformSP (*PlatformCreateInstance)(bool force, const ArchSpec *arch); typedef lldb::ProcessSP (*ProcessCreateInstance)( lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, - const FileSpec *crash_file_path); + const FileSpec *crash_file_path, bool can_connect); typedef lldb::ScriptInterpreterSP (*ScriptInterpreterCreateInstance)( Debugger &debugger); typedef SymbolFile *(*SymbolFileCreateInstance)(lldb::ObjectFileSP objfile_sp); diff --git a/lldb/source/API/SBTarget.cpp b/lldb/source/API/SBTarget.cpp index 34cab6217565c..2a305159bbb58 100644 --- a/lldb/source/API/SBTarget.cpp +++ b/lldb/source/API/SBTarget.cpp @@ -267,7 +267,7 @@ SBProcess SBTarget::LoadCore(const char *core_file, lldb::SBError &error) { FileSpec filespec(core_file); FileSystem::Instance().Resolve(filespec); ProcessSP process_sp(target_sp->CreateProcess( - target_sp->GetDebugger().GetListener(), "", &filespec)); + target_sp->GetDebugger().GetListener(), "", &filespec, false)); if (process_sp) { error.SetError(process_sp->LoadCore()); if (error.Success()) @@ -567,10 +567,11 @@ lldb::SBProcess SBTarget::ConnectRemote(SBListener &listener, const char *url, std::lock_guard guard(target_sp->GetAPIMutex()); if (listener.IsValid()) process_sp = - target_sp->CreateProcess(listener.m_opaque_sp, plugin_name, nullptr); + target_sp->CreateProcess(listener.m_opaque_sp, plugin_name, nullptr, + true); else process_sp = target_sp->CreateProcess( - target_sp->GetDebugger().GetListener(), plugin_name, nullptr); + target_sp->GetDebugger().GetListener(), plugin_name, nullptr, true); if (process_sp) { sb_process.SetSP(process_sp); diff --git a/lldb/source/Commands/CommandObjectTarget.cpp b/lldb/source/Commands/CommandObjectTarget.cpp index 98285289e3a98..eba129c461b39 100644 --- a/lldb/source/Commands/CommandObjectTarget.cpp +++ b/lldb/source/Commands/CommandObjectTarget.cpp @@ -401,7 +401,8 @@ class CommandObjectTargetCreate : public CommandObjectParsed { target_sp->AppendExecutableSearchPaths(core_file_dir); ProcessSP process_sp(target_sp->CreateProcess( - GetDebugger().GetListener(), llvm::StringRef(), &core_file)); + GetDebugger().GetListener(), llvm::StringRef(), &core_file, + false)); if (process_sp) { // Seems weird that we Launch a core file, but that is what we diff --git a/lldb/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp b/lldb/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp index 7f6cbd7fab587..47f62a9ca04fc 100644 --- a/lldb/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp +++ b/lldb/source/Plugins/Platform/POSIX/PlatformPOSIX.cpp @@ -388,7 +388,8 @@ lldb::ProcessSP PlatformPOSIX::Attach(ProcessAttachInfo &attach_info, process_sp = target->CreateProcess(attach_info.GetListenerForProcess(debugger), - attach_info.GetProcessPluginName(), nullptr); + attach_info.GetProcessPluginName(), nullptr, + false); if (process_sp) { ListenerSP listener_sp = attach_info.GetHijackListener(); @@ -468,7 +469,8 @@ PlatformPOSIX::DebugProcess(ProcessLaunchInfo &launch_info, Debugger &debugger, // Now create the gdb-remote process. LLDB_LOG(log, "having target create process with gdb-remote plugin"); process_sp = - target->CreateProcess(launch_info.GetListener(), "gdb-remote", nullptr); + target->CreateProcess(launch_info.GetListener(), "gdb-remote", nullptr, + true); if (!process_sp) { error.SetErrorString("CreateProcess() failed for gdb-remote process"); diff --git a/lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp b/lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp index 167a92118fdad..0ef4dcb7b9f64 100644 --- a/lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp +++ b/lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp @@ -233,7 +233,8 @@ ProcessSP PlatformWindows::DebugProcess(ProcessLaunchInfo &launch_info, return Attach(attach_info, debugger, target, error); } else { ProcessSP process_sp = target->CreateProcess( - launch_info.GetListener(), launch_info.GetProcessPluginName(), nullptr); + launch_info.GetListener(), launch_info.GetProcessPluginName(), nullptr, + false); // We need to launch and attach to the process. launch_info.GetFlags().Set(eLaunchFlagDebug); @@ -275,7 +276,7 @@ lldb::ProcessSP PlatformWindows::Attach(ProcessAttachInfo &attach_info, const char *plugin_name = attach_info.GetProcessPluginName(); process_sp = target->CreateProcess( - attach_info.GetListenerForProcess(debugger), plugin_name, nullptr); + attach_info.GetListenerForProcess(debugger), plugin_name, nullptr, false); process_sp->HijackProcessEvents(attach_info.GetHijackListener()); if (process_sp) diff --git a/lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp b/lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp index e8bfbd889299f..b3774b9c226c2 100644 --- a/lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp +++ b/lldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp @@ -500,7 +500,7 @@ lldb::ProcessSP PlatformRemoteGDBServer::DebugProcess( // The darwin always currently uses the GDB remote debugger plug-in // so even when debugging locally we are debugging remotely! process_sp = target->CreateProcess(launch_info.GetListener(), - "gdb-remote", nullptr); + "gdb-remote", nullptr, true); if (process_sp) { error = process_sp->ConnectRemote(connect_url.c_str()); @@ -587,7 +587,7 @@ lldb::ProcessSP PlatformRemoteGDBServer::Attach( // so even when debugging locally we are debugging remotely! process_sp = target->CreateProcess(attach_info.GetListenerForProcess(debugger), - "gdb-remote", nullptr); + "gdb-remote", nullptr, true); if (process_sp) { error = process_sp->ConnectRemote(connect_url.c_str()); if (error.Success()) { diff --git a/lldb/source/Plugins/Process/FreeBSD/POSIXStopInfo.h b/lldb/source/Plugins/Process/FreeBSD/POSIXStopInfo.h index 88fb7f31fe06b..5a022c485b682 100644 --- a/lldb/source/Plugins/Process/FreeBSD/POSIXStopInfo.h +++ b/lldb/source/Plugins/Process/FreeBSD/POSIXStopInfo.h @@ -34,13 +34,13 @@ class POSIXLimboStopInfo : public POSIXStopInfo { ~POSIXLimboStopInfo(); - lldb::StopReason GetStopReason() const; + lldb::StopReason GetStopReason() const override; - const char *GetDescription(); + const char *GetDescription() override; - bool ShouldStop(lldb_private::Event *event_ptr); + bool ShouldStop(lldb_private::Event *event_ptr) override; - bool ShouldNotify(lldb_private::Event *event_ptr); + bool ShouldNotify(lldb_private::Event *event_ptr) override; }; //===----------------------------------------------------------------------===// @@ -54,13 +54,13 @@ class POSIXNewThreadStopInfo : public POSIXStopInfo { ~POSIXNewThreadStopInfo(); - lldb::StopReason GetStopReason() const; + lldb::StopReason GetStopReason() const override; - const char *GetDescription(); + const char *GetDescription() override; - bool ShouldStop(lldb_private::Event *event_ptr); + bool ShouldStop(lldb_private::Event *event_ptr) override; - bool ShouldNotify(lldb_private::Event *event_ptr); + bool ShouldNotify(lldb_private::Event *event_ptr) override; }; #endif diff --git a/lldb/source/Plugins/Process/FreeBSD/ProcessFreeBSD.cpp b/lldb/source/Plugins/Process/FreeBSD/ProcessFreeBSD.cpp index 67a18bd8de13b..ed134d8f2a369 100644 --- a/lldb/source/Plugins/Process/FreeBSD/ProcessFreeBSD.cpp +++ b/lldb/source/Plugins/Process/FreeBSD/ProcessFreeBSD.cpp @@ -70,9 +70,10 @@ UnixSignalsSP &GetFreeBSDSignals() { lldb::ProcessSP ProcessFreeBSD::CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, - const FileSpec *crash_file_path) { + const FileSpec *crash_file_path, + bool can_connect) { lldb::ProcessSP process_sp; - if (crash_file_path == NULL) + if (crash_file_path == NULL && !can_connect) process_sp.reset( new ProcessFreeBSD(target_sp, listener_sp, GetFreeBSDSignals())); return process_sp; diff --git a/lldb/source/Plugins/Process/FreeBSD/ProcessFreeBSD.h b/lldb/source/Plugins/Process/FreeBSD/ProcessFreeBSD.h index 536da0c0aa70e..dbb2acb1cd3f7 100644 --- a/lldb/source/Plugins/Process/FreeBSD/ProcessFreeBSD.h +++ b/lldb/source/Plugins/Process/FreeBSD/ProcessFreeBSD.h @@ -26,7 +26,8 @@ class ProcessFreeBSD : public lldb_private::Process { // Static functions. static lldb::ProcessSP CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, - const lldb_private::FileSpec *crash_file_path); + const lldb_private::FileSpec *crash_file_path, + bool can_connect); static void Initialize(); diff --git a/lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp b/lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp index 035bf59cc9c9a..39ae0b9b9e7f2 100644 --- a/lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp +++ b/lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp @@ -25,7 +25,7 @@ RegisterContextPOSIXProcessMonitor_arm64:: lldb_private::Thread &thread, std::unique_ptr register_info) : RegisterContextPOSIX_arm64(thread, std::move(register_info)) { - ::memset(&m_fpr, 0, sizeof m_gpr_arm64); + ::memset(&m_gpr_arm64, 0, sizeof m_gpr_arm64); ::memset(&m_fpr, 0, sizeof m_fpr); } diff --git a/lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp b/lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp index ea2494dabf276..8f1ba2eb41378 100644 --- a/lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp +++ b/lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp @@ -215,9 +215,9 @@ static const RegisterSet g_reg_sets_i386[k_num_register_sets] = { {"Floating Point Registers", "fpu", k_num_fpr_registers_i386, g_fpu_regnums_i386}, {"Debug Registers", "dbr", k_num_dbr_registers_i386, g_dbr_regnums_i386}, - {"Extended AVX registers", "avx", k_num_avx_registers_i386, + {"Advanced Vector Extensions", "avx", k_num_avx_registers_i386, g_avx_regnums_i386}, - {"Extended MPX registers", "mpx", k_num_mpx_registers_i386, + {"Memory Protection Extensions", "mpx", k_num_mpx_registers_i386, g_mpx_regnums_i386}, }; @@ -229,9 +229,9 @@ static const RegisterSet g_reg_sets_x86_64[k_num_register_sets] = { g_fpu_regnums_x86_64}, {"Debug Registers", "dbr", k_num_dbr_registers_x86_64, g_dbr_regnums_x86_64}, - {"Extended AVX registers", "avx", k_num_avx_registers_x86_64, + {"Advanced Vector Extensions", "avx", k_num_avx_registers_x86_64, g_avx_regnums_x86_64}, - {"Extended MPX registers", "mpx", k_num_mpx_registers_x86_64, + {"Memory Protection Extensions", "mpx", k_num_mpx_registers_x86_64, g_mpx_regnums_x86_64}, }; @@ -451,10 +451,16 @@ NativeRegisterContextFreeBSD_x86_64::ReadRegister(const RegisterInfo *reg_info, switch (set) { case GPRegSet: case FPRegSet: - case DBRegSet: - reg_value.SetBytes(GetOffsetRegSetData(set, reg_info->byte_offset), - reg_info->byte_size, endian::InlHostByteOrder()); + case DBRegSet: { + void *data = GetOffsetRegSetData(set, reg_info->byte_offset); + FXSAVE *fpr = reinterpret_cast(m_fpr.data()); + if (data == &fpr->ftag) // ftag + reg_value.SetUInt16( + AbridgedToFullTagWord(fpr->ftag, fpr->fstat, fpr->stmm)); + else + reg_value.SetBytes(data, reg_info->byte_size, endian::InlHostByteOrder()); break; + } case YMMRegSet: { llvm::Optional ymm_reg = GetYMMSplitReg(reg); if (!ymm_reg) { @@ -511,10 +517,15 @@ Status NativeRegisterContextFreeBSD_x86_64::WriteRegister( switch (set) { case GPRegSet: case FPRegSet: - case DBRegSet: - ::memcpy(GetOffsetRegSetData(set, reg_info->byte_offset), - reg_value.GetBytes(), reg_value.GetByteSize()); + case DBRegSet: { + void *data = GetOffsetRegSetData(set, reg_info->byte_offset); + FXSAVE *fpr = reinterpret_cast(m_fpr.data()); + if (data == &fpr->ftag) // ftag + fpr->ftag = FullToAbridgedTagWord(reg_value.GetAsUInt16()); + else + ::memcpy(data, reg_value.GetBytes(), reg_value.GetByteSize()); break; + } case YMMRegSet: { llvm::Optional ymm_reg = GetYMMSplitReg(reg); if (!ymm_reg) { diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp index 20cd5e3f62ff7..6462441249c04 100644 --- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp +++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp @@ -530,6 +530,13 @@ NativeRegisterContextLinux_x86_64::ReadRegister(const RegisterInfo *reg_info, assert((reg_info->byte_offset - m_fctrl_offset_in_userarea) < sizeof(FPR)); uint8_t *src = (uint8_t *)m_xstate.get() + reg_info->byte_offset - m_fctrl_offset_in_userarea; + + if (src == reinterpret_cast(&m_xstate->fxsave.ftag)) { + reg_value.SetUInt16(AbridgedToFullTagWord( + m_xstate->fxsave.ftag, m_xstate->fxsave.fstat, m_xstate->fxsave.stmm)); + return error; + } + switch (reg_info->byte_size) { case 1: reg_value.SetUInt8(*(uint8_t *)src); @@ -639,23 +646,28 @@ Status NativeRegisterContextLinux_x86_64::WriteRegister( sizeof(FPR)); uint8_t *dst = (uint8_t *)m_xstate.get() + reg_info->byte_offset - m_fctrl_offset_in_userarea; - switch (reg_info->byte_size) { - case 1: - *(uint8_t *)dst = reg_value.GetAsUInt8(); - break; - case 2: - *(uint16_t *)dst = reg_value.GetAsUInt16(); - break; - case 4: - *(uint32_t *)dst = reg_value.GetAsUInt32(); - break; - case 8: - *(uint64_t *)dst = reg_value.GetAsUInt64(); - break; - default: - assert(false && "Unhandled data size."); - return Status("unhandled register data size %" PRIu32, - reg_info->byte_size); + + if (dst == reinterpret_cast(&m_xstate->fxsave.ftag)) + m_xstate->fxsave.ftag = FullToAbridgedTagWord(reg_value.GetAsUInt16()); + else { + switch (reg_info->byte_size) { + case 1: + *(uint8_t *)dst = reg_value.GetAsUInt8(); + break; + case 2: + *(uint16_t *)dst = reg_value.GetAsUInt16(); + break; + case 4: + *(uint32_t *)dst = reg_value.GetAsUInt32(); + break; + case 8: + *(uint64_t *)dst = reg_value.GetAsUInt64(); + break; + default: + assert(false && "Unhandled data size."); + return Status("unhandled register data size %" PRIu32, + reg_info->byte_size); + } } } diff --git a/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp b/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp index 6e394eac6f9e6..c3f1d019d66cd 100644 --- a/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp +++ b/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp @@ -111,7 +111,8 @@ void ProcessKDP::Terminate() { lldb::ProcessSP ProcessKDP::CreateInstance(TargetSP target_sp, ListenerSP listener_sp, - const FileSpec *crash_file_path) { + const FileSpec *crash_file_path, + bool can_connect) { lldb::ProcessSP process_sp; if (crash_file_path == NULL) process_sp = std::make_shared(target_sp, listener_sp); diff --git a/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.h b/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.h index 52af56134404c..137b67809a632 100644 --- a/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.h +++ b/lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.h @@ -32,7 +32,8 @@ class ProcessKDP : public lldb_private::Process { // Constructors and Destructors static lldb::ProcessSP CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, - const lldb_private::FileSpec *crash_file_path); + const lldb_private::FileSpec *crash_file_path, + bool can_connect); static void Initialize(); diff --git a/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp b/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp index 917693884681f..038dc125c853e 100644 --- a/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp +++ b/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86_64.cpp @@ -607,9 +607,13 @@ NativeRegisterContextNetBSD_x86_64::ReadRegister(const RegisterInfo *reg_info, case lldb_fstat_x86_64: reg_value = (uint16_t)m_xstate.xs_fxsave.fx_sw; break; - case lldb_ftag_x86_64: - reg_value = (uint16_t)m_xstate.xs_fxsave.fx_tw; + case lldb_ftag_x86_64: { + llvm::ArrayRef st_regs{ + reinterpret_cast(m_xstate.xs_fxsave.fx_87_ac), 8}; + reg_value = (uint16_t)AbridgedToFullTagWord( + m_xstate.xs_fxsave.fx_tw, m_xstate.xs_fxsave.fx_sw, st_regs); break; + } case lldb_fop_x86_64: reg_value = (uint64_t)m_xstate.xs_fxsave.fx_opcode; break; @@ -905,7 +909,7 @@ Status NativeRegisterContextNetBSD_x86_64::WriteRegister( m_xstate.xs_fxsave.fx_sw = reg_value.GetAsUInt16(); break; case lldb_ftag_x86_64: - m_xstate.xs_fxsave.fx_tw = reg_value.GetAsUInt16(); + m_xstate.xs_fxsave.fx_tw = FullToAbridgedTagWord(reg_value.GetAsUInt16()); break; case lldb_fop_x86_64: m_xstate.xs_fxsave.fx_opcode = reg_value.GetAsUInt16(); diff --git a/lldb/source/Plugins/Process/Utility/CMakeLists.txt b/lldb/source/Plugins/Process/Utility/CMakeLists.txt index 2fcbe977dcc12..9965d89f4c4ba 100644 --- a/lldb/source/Plugins/Process/Utility/CMakeLists.txt +++ b/lldb/source/Plugins/Process/Utility/CMakeLists.txt @@ -12,6 +12,7 @@ add_lldb_library(lldbPluginProcessUtility NativeRegisterContextRegisterInfo.cpp NativeRegisterContextWatchpoint_x86.cpp NetBSDSignals.cpp + RegisterContext_x86.cpp RegisterContextDarwin_arm.cpp RegisterContextDarwin_arm64.cpp RegisterContextDarwin_i386.cpp diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.cpp index bf9282d8c0ccf..2c7f63503d7c8 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.cpp +++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.cpp @@ -286,6 +286,74 @@ uint32_t RegisterContextPOSIX_x86::g_invalidate_fip[] = { uint32_t RegisterContextPOSIX_x86::g_invalidate_fdp[] = { lldb_fdp_x86_64, lldb_fooff_x86_64, lldb_foseg_x86_64, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st0_32[] = {lldb_st0_i386, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st1_32[] = {lldb_st1_i386, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st2_32[] = {lldb_st2_i386, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st3_32[] = {lldb_st3_i386, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st4_32[] = {lldb_st4_i386, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st5_32[] = {lldb_st5_i386, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st6_32[] = {lldb_st6_i386, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st7_32[] = {lldb_st7_i386, + LLDB_INVALID_REGNUM}; + +uint32_t RegisterContextPOSIX_x86::g_invalidate_st0_32[] = { + lldb_st0_i386, lldb_mm0_i386, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st1_32[] = { + lldb_st1_i386, lldb_mm1_i386, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st2_32[] = { + lldb_st2_i386, lldb_mm2_i386, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st3_32[] = { + lldb_st3_i386, lldb_mm3_i386, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st4_32[] = { + lldb_st4_i386, lldb_mm4_i386, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st5_32[] = { + lldb_st5_i386, lldb_mm5_i386, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st6_32[] = { + lldb_st6_i386, lldb_mm6_i386, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st7_32[] = { + lldb_st7_i386, lldb_mm7_i386, LLDB_INVALID_REGNUM}; + +uint32_t RegisterContextPOSIX_x86::g_contained_st0_64[] = {lldb_st0_x86_64, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st1_64[] = {lldb_st1_x86_64, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st2_64[] = {lldb_st2_x86_64, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st3_64[] = {lldb_st3_x86_64, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st4_64[] = {lldb_st4_x86_64, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st5_64[] = {lldb_st5_x86_64, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st6_64[] = {lldb_st6_x86_64, + LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_contained_st7_64[] = {lldb_st7_x86_64, + LLDB_INVALID_REGNUM}; + +uint32_t RegisterContextPOSIX_x86::g_invalidate_st0_64[] = { + lldb_st0_x86_64, lldb_mm0_x86_64, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st1_64[] = { + lldb_st1_x86_64, lldb_mm1_x86_64, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st2_64[] = { + lldb_st2_x86_64, lldb_mm2_x86_64, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st3_64[] = { + lldb_st3_x86_64, lldb_mm3_x86_64, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st4_64[] = { + lldb_st4_x86_64, lldb_mm4_x86_64, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st5_64[] = { + lldb_st5_x86_64, lldb_mm5_x86_64, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st6_64[] = { + lldb_st6_x86_64, lldb_mm6_x86_64, LLDB_INVALID_REGNUM}; +uint32_t RegisterContextPOSIX_x86::g_invalidate_st7_64[] = { + lldb_st7_x86_64, lldb_mm7_x86_64, LLDB_INVALID_REGNUM}; + // Number of register sets provided by this context. enum { k_num_extended_register_sets = 1, k_num_register_sets = 3 }; diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.h b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.h index 7ccf0a94faae2..d6672835b4a81 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.h +++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.h @@ -112,6 +112,42 @@ class RegisterContextPOSIX_x86 : public lldb_private::RegisterContext { static uint32_t g_invalidate_fip[]; static uint32_t g_invalidate_fdp[]; + static uint32_t g_contained_st0_32[]; + static uint32_t g_contained_st1_32[]; + static uint32_t g_contained_st2_32[]; + static uint32_t g_contained_st3_32[]; + static uint32_t g_contained_st4_32[]; + static uint32_t g_contained_st5_32[]; + static uint32_t g_contained_st6_32[]; + static uint32_t g_contained_st7_32[]; + + static uint32_t g_invalidate_st0_32[]; + static uint32_t g_invalidate_st1_32[]; + static uint32_t g_invalidate_st2_32[]; + static uint32_t g_invalidate_st3_32[]; + static uint32_t g_invalidate_st4_32[]; + static uint32_t g_invalidate_st5_32[]; + static uint32_t g_invalidate_st6_32[]; + static uint32_t g_invalidate_st7_32[]; + + static uint32_t g_contained_st0_64[]; + static uint32_t g_contained_st1_64[]; + static uint32_t g_contained_st2_64[]; + static uint32_t g_contained_st3_64[]; + static uint32_t g_contained_st4_64[]; + static uint32_t g_contained_st5_64[]; + static uint32_t g_contained_st6_64[]; + static uint32_t g_contained_st7_64[]; + + static uint32_t g_invalidate_st0_64[]; + static uint32_t g_invalidate_st1_64[]; + static uint32_t g_invalidate_st2_64[]; + static uint32_t g_invalidate_st3_64[]; + static uint32_t g_invalidate_st4_64[]; + static uint32_t g_invalidate_st5_64[]; + static uint32_t g_invalidate_st6_64[]; + static uint32_t g_invalidate_st7_64[]; + protected: struct RegInfo { uint32_t num_registers; diff --git a/lldb/source/Plugins/Process/Utility/RegisterContext_x86.cpp b/lldb/source/Plugins/Process/Utility/RegisterContext_x86.cpp new file mode 100644 index 0000000000000..b21c72bd96214 --- /dev/null +++ b/lldb/source/Plugins/Process/Utility/RegisterContext_x86.cpp @@ -0,0 +1,58 @@ +//===-- RegisterContext_x86.cpp ---------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "RegisterContext_x86.h" + +using namespace lldb_private; + +// Convert the 8-bit abridged FPU Tag Word (as found in FXSAVE) to the full +// 16-bit FPU Tag Word (as found in FSAVE, and used by gdb protocol). This +// requires knowing the values of the ST(i) registers and the FPU Status Word. +uint16_t lldb_private::AbridgedToFullTagWord(uint8_t abridged_tw, uint16_t sw, + llvm::ArrayRef st_regs) { + // Tag word is using internal FPU register numbering rather than ST(i). + // Mapping to ST(i): i = FPU regno - TOP (Status Word, bits 11:13). + // Here we start with FPU reg 7 and go down. + int st = 7 - ((sw >> 11) & 7); + uint16_t tw = 0; + for (uint8_t mask = 0x80; mask != 0; mask >>= 1) { + tw <<= 2; + if (abridged_tw & mask) { + // The register is non-empty, so we need to check the value of ST(i). + uint16_t exp = + st_regs[st].comp.sign_exp & 0x7fff; // Discard the sign bit. + if (exp == 0) { + if (st_regs[st].comp.mantissa == 0) + tw |= 1; // Zero + else + tw |= 2; // Denormal + } else if (exp == 0x7fff) + tw |= 2; // Infinity or NaN + // 0 if normal number + } else + tw |= 3; // Empty register + + // Rotate ST down. + st = (st - 1) & 7; + } + + return tw; +} + +// Convert the 16-bit FPU Tag Word to the abridged 8-bit value, to be written +// into FXSAVE. +uint8_t lldb_private::FullToAbridgedTagWord(uint16_t tw) { + uint8_t abridged_tw = 0; + for (uint16_t mask = 0xc000; mask != 0; mask >>= 2) { + abridged_tw <<= 1; + // full TW uses 11 for empty registers, aTW uses 0 + if ((tw & mask) != mask) + abridged_tw |= 1; + } + return abridged_tw; +} diff --git a/lldb/source/Plugins/Process/Utility/RegisterContext_x86.h b/lldb/source/Plugins/Process/Utility/RegisterContext_x86.h index 27a1bad4d53fa..76e004ce0ceb1 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterContext_x86.h +++ b/lldb/source/Plugins/Process/Utility/RegisterContext_x86.h @@ -12,6 +12,7 @@ #include #include +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/BitmaskEnum.h" #include "llvm/Support/Compiler.h" @@ -239,10 +240,23 @@ enum { // Generic floating-point registers +LLVM_PACKED_START +struct MMSRegComp { + uint64_t mantissa; + uint16_t sign_exp; +}; + struct MMSReg { - uint8_t bytes[10]; + union { + uint8_t bytes[10]; + MMSRegComp comp; + }; uint8_t pad[6]; }; +LLVM_PACKED_END + +static_assert(sizeof(MMSRegComp) == 10, "MMSRegComp is not 10 bytes of size"); +static_assert(sizeof(MMSReg) == 16, "MMSReg is not 16 bytes of size"); struct XMMReg { uint8_t bytes[16]; // 128-bits for each XMM register @@ -369,6 +383,10 @@ inline void YMMToXState(const YMMReg& input, void* xmm_bytes, void* ymmh_bytes) ::memcpy(ymmh_bytes, input.bytes + sizeof(XMMReg), sizeof(YMMHReg)); } +uint16_t AbridgedToFullTagWord(uint8_t abridged_tw, uint16_t sw, + llvm::ArrayRef st_regs); +uint8_t FullToAbridgedTagWord(uint16_t tw); + } // namespace lldb_private #endif diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_i386.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_i386.h index 343579cd26578..15c7cac544a11 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterInfos_i386.h +++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_i386.h @@ -87,15 +87,14 @@ nullptr, nullptr, nullptr, 0 \ } -#define DEFINE_FP_MM(reg, i) \ +#define DEFINE_FP_MM(reg, i, streg) \ { \ - #reg #i, nullptr, sizeof(uint64_t), \ - LLVM_EXTENSION FPR_OFFSET( \ - stmm[i]), eEncodingUint, eFormatHex, \ - {ehframe_mm##i##_i386, dwarf_mm##i##_i386, \ - LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ - lldb_mm##i##_i386 }, \ - nullptr, nullptr, nullptr, 0 \ + #reg #i, nullptr, sizeof(uint64_t), LLVM_EXTENSION FPR_OFFSET(stmm[i]), \ + eEncodingUint, eFormatHex, \ + {dwarf_mm##i##_i386, dwarf_mm##i##_i386, LLDB_INVALID_REGNUM, \ + LLDB_INVALID_REGNUM, lldb_mm##i##_i386 }, \ + RegisterContextPOSIX_x86::g_contained_##streg##_32, \ + RegisterContextPOSIX_x86::g_invalidate_##streg##_32, nullptr, 0 \ } #define DEFINE_XMM(reg, i) \ @@ -251,10 +250,12 @@ static RegisterInfo g_register_infos_i386[] = { // FP registers. DEFINE_FP_ST(st, 0), DEFINE_FP_ST(st, 1), DEFINE_FP_ST(st, 2), DEFINE_FP_ST(st, 3), DEFINE_FP_ST(st, 4), DEFINE_FP_ST(st, 5), - DEFINE_FP_ST(st, 6), DEFINE_FP_ST(st, 7), DEFINE_FP_MM(mm, 0), - DEFINE_FP_MM(mm, 1), DEFINE_FP_MM(mm, 2), DEFINE_FP_MM(mm, 3), - DEFINE_FP_MM(mm, 4), DEFINE_FP_MM(mm, 5), DEFINE_FP_MM(mm, 6), - DEFINE_FP_MM(mm, 7), + DEFINE_FP_ST(st, 6), DEFINE_FP_ST(st, 7), + + DEFINE_FP_MM(mm, 0, st0), DEFINE_FP_MM(mm, 1, st1), + DEFINE_FP_MM(mm, 2, st2), DEFINE_FP_MM(mm, 3, st3), + DEFINE_FP_MM(mm, 4, st4), DEFINE_FP_MM(mm, 5, st5), + DEFINE_FP_MM(mm, 6, st6), DEFINE_FP_MM(mm, 7, st7), // XMM registers DEFINE_XMM(xmm, 0), DEFINE_XMM(xmm, 1), DEFINE_XMM(xmm, 2), diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64.h index 466248cc1d475..41c04b20f3917 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64.h +++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64.h @@ -88,15 +88,14 @@ nullptr, nullptr, nullptr, 0 \ } -#define DEFINE_FP_MM(reg, i) \ +#define DEFINE_FP_MM(reg, i, streg) \ { \ - #reg #i, nullptr, sizeof(uint64_t), \ - LLVM_EXTENSION FPR_OFFSET( \ - stmm[i]), eEncodingUint, eFormatHex, \ - {dwarf_mm##i##_x86_64, dwarf_mm##i##_x86_64, \ - LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ - lldb_mm##i##_x86_64 }, \ - nullptr, nullptr, nullptr, 0 \ + #reg #i, nullptr, sizeof(uint64_t), LLVM_EXTENSION FPR_OFFSET(stmm[i]), \ + eEncodingUint, eFormatHex, \ + {dwarf_mm##i##_x86_64, dwarf_mm##i##_x86_64, LLDB_INVALID_REGNUM, \ + LLDB_INVALID_REGNUM, lldb_mm##i##_x86_64 }, \ + RegisterContextPOSIX_x86::g_contained_##streg##_64, \ + RegisterContextPOSIX_x86::g_invalidate_##streg##_64, nullptr, 0 \ } #define DEFINE_XMM(reg, i) \ @@ -277,10 +276,12 @@ static RegisterInfo g_register_infos_x86_64[] = { // FP registers. DEFINE_FP_ST(st, 0), DEFINE_FP_ST(st, 1), DEFINE_FP_ST(st, 2), DEFINE_FP_ST(st, 3), DEFINE_FP_ST(st, 4), DEFINE_FP_ST(st, 5), - DEFINE_FP_ST(st, 6), DEFINE_FP_ST(st, 7), DEFINE_FP_MM(mm, 0), - DEFINE_FP_MM(mm, 1), DEFINE_FP_MM(mm, 2), DEFINE_FP_MM(mm, 3), - DEFINE_FP_MM(mm, 4), DEFINE_FP_MM(mm, 5), DEFINE_FP_MM(mm, 6), - DEFINE_FP_MM(mm, 7), + DEFINE_FP_ST(st, 6), DEFINE_FP_ST(st, 7), + + DEFINE_FP_MM(mm, 0, st0), DEFINE_FP_MM(mm, 1, st1), + DEFINE_FP_MM(mm, 2, st2), DEFINE_FP_MM(mm, 3, st3), + DEFINE_FP_MM(mm, 4, st4), DEFINE_FP_MM(mm, 5, st5), + DEFINE_FP_MM(mm, 6, st6), DEFINE_FP_MM(mm, 7, st7), // XMM registers DEFINE_XMM(xmm, 0), DEFINE_XMM(xmm, 1), DEFINE_XMM(xmm, 2), diff --git a/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp b/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp index 96e2603b993ea..11bfc7c897d54 100644 --- a/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp +++ b/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp @@ -79,7 +79,8 @@ namespace lldb_private { ProcessSP ProcessWindows::CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, - const FileSpec *) { + const FileSpec *, + bool can_connect) { return ProcessSP(new ProcessWindows(target_sp, listener_sp)); } diff --git a/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h b/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h index a1085df022c91..7d1443176d3b5 100644 --- a/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h +++ b/lldb/source/Plugins/Process/Windows/Common/ProcessWindows.h @@ -25,7 +25,8 @@ class ProcessWindows : public Process, public ProcessDebugger { // Static functions. static lldb::ProcessSP CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, - const FileSpec *); + const FileSpec *, + bool can_connect); static void Initialize(); diff --git a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp index dbc1a01814322..3bcf560c4f07e 100644 --- a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp +++ b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp @@ -52,9 +52,10 @@ void ProcessElfCore::Terminate() { lldb::ProcessSP ProcessElfCore::CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, - const FileSpec *crash_file) { + const FileSpec *crash_file, + bool can_connect) { lldb::ProcessSP process_sp; - if (crash_file) { + if (crash_file && !can_connect) { // Read enough data for a ELF32 header or ELF64 header Note: Here we care // about e_type field only, so it is safe to ignore possible presence of // the header extension. diff --git a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h index 9f796d69b90b2..793f3cda126f6 100644 --- a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h +++ b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h @@ -33,7 +33,8 @@ class ProcessElfCore : public lldb_private::PostMortemProcess { // Constructors and Destructors static lldb::ProcessSP CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, - const lldb_private::FileSpec *crash_file_path); + const lldb_private::FileSpec *crash_file_path, + bool can_connect); static void Initialize(); diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp index 0cd97abc3f4ff..4c00e9a4c6733 100644 --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp @@ -205,7 +205,8 @@ void ProcessGDBRemote::Terminate() { lldb::ProcessSP ProcessGDBRemote::CreateInstance(lldb::TargetSP target_sp, ListenerSP listener_sp, - const FileSpec *crash_file_path) { + const FileSpec *crash_file_path, + bool can_connect) { lldb::ProcessSP process_sp; if (crash_file_path == nullptr) process_sp = std::make_shared(target_sp, listener_sp); diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h index e47300fac2d0a..5efe8b757af82 100644 --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h @@ -55,7 +55,8 @@ class ProcessGDBRemote : public Process, static lldb::ProcessSP CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, - const FileSpec *crash_file_path); + const FileSpec *crash_file_path, + bool can_connect); static void Initialize(); diff --git a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp index c1a8d167be356..6f03825cd6cdd 100644 --- a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp +++ b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp @@ -61,9 +61,10 @@ void ProcessMachCore::Terminate() { lldb::ProcessSP ProcessMachCore::CreateInstance(lldb::TargetSP target_sp, ListenerSP listener_sp, - const FileSpec *crash_file) { + const FileSpec *crash_file, + bool can_connect) { lldb::ProcessSP process_sp; - if (crash_file) { + if (crash_file && !can_connect) { const size_t header_size = sizeof(llvm::MachO::mach_header); auto data_sp = FileSystem::Instance().CreateDataBuffer( crash_file->GetPath(), header_size, 0); diff --git a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h index 9c85139c78464..60463bc44d417 100644 --- a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h +++ b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h @@ -28,7 +28,8 @@ class ProcessMachCore : public lldb_private::PostMortemProcess { static lldb::ProcessSP CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener, - const lldb_private::FileSpec *crash_file_path); + const lldb_private::FileSpec *crash_file_path, + bool can_connect); static void Initialize(); diff --git a/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp b/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp index 1850a36f27723..c001547eefd63 100644 --- a/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp +++ b/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp @@ -200,8 +200,9 @@ const char *ProcessMinidump::GetPluginDescriptionStatic() { lldb::ProcessSP ProcessMinidump::CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, - const FileSpec *crash_file) { - if (!crash_file) + const FileSpec *crash_file, + bool can_connect) { + if (!crash_file || can_connect) return nullptr; lldb::ProcessSP process_sp; diff --git a/lldb/source/Plugins/Process/minidump/ProcessMinidump.h b/lldb/source/Plugins/Process/minidump/ProcessMinidump.h index 1d4d535d697a4..9a68bd43551aa 100644 --- a/lldb/source/Plugins/Process/minidump/ProcessMinidump.h +++ b/lldb/source/Plugins/Process/minidump/ProcessMinidump.h @@ -30,7 +30,8 @@ class ProcessMinidump : public PostMortemProcess { public: static lldb::ProcessSP CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, - const FileSpec *crash_file_path); + const FileSpec *crash_file_path, + bool can_connect); static void Initialize(); diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp index 37ad7ff035c0d..77470486dd451 100644 --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp @@ -6541,8 +6541,10 @@ size_t TypeSystemClang::GetIndexOfChildMemberWithName( if (cxx_record_decl->lookupInBases( [decl_name](const clang::CXXBaseSpecifier *specifier, clang::CXXBasePath &path) { - return clang::CXXRecordDecl::FindOrdinaryMember( - specifier, path, decl_name); + path.Decls = + specifier->getType()->getAsCXXRecordDecl()->lookup( + decl_name); + return !path.Decls.empty(); }, paths)) { clang::CXXBasePaths::const_paths_iterator path, diff --git a/lldb/source/Symbol/CMakeLists.txt b/lldb/source/Symbol/CMakeLists.txt index 2ce0b6887e5fe..95bf156ff538b 100644 --- a/lldb/source/Symbol/CMakeLists.txt +++ b/lldb/source/Symbol/CMakeLists.txt @@ -39,9 +39,6 @@ add_lldb_library(lldbSymbol ${PLATFORM_SOURCES} - DEPENDS - intrinsics_gen - LINK_LIBS lldbCore lldbExpression diff --git a/lldb/source/Target/Platform.cpp b/lldb/source/Target/Platform.cpp index 685dd9515e1bf..b5b673a33e44b 100644 --- a/lldb/source/Target/Platform.cpp +++ b/lldb/source/Target/Platform.cpp @@ -1834,7 +1834,7 @@ lldb::ProcessSP Platform::DoConnectProcess(llvm::StringRef connect_url, debugger.GetTargetList().SetSelectedTarget(target); lldb::ProcessSP process_sp = - target->CreateProcess(debugger.GetListener(), plugin_name, nullptr); + target->CreateProcess(debugger.GetListener(), plugin_name, nullptr, true); if (!process_sp) return nullptr; diff --git a/lldb/source/Target/Process.cpp b/lldb/source/Target/Process.cpp index c2effda3bdcb7..14f8326cfcec4 100644 --- a/lldb/source/Target/Process.cpp +++ b/lldb/source/Target/Process.cpp @@ -479,7 +479,8 @@ llvm::ArrayRef ProcessLaunchCommandOptions::GetDefinitions() { ProcessSP Process::FindPlugin(lldb::TargetSP target_sp, llvm::StringRef plugin_name, ListenerSP listener_sp, - const FileSpec *crash_file_path) { + const FileSpec *crash_file_path, + bool can_connect) { static uint32_t g_process_unique_id = 0; ProcessSP process_sp; @@ -489,7 +490,8 @@ ProcessSP Process::FindPlugin(lldb::TargetSP target_sp, create_callback = PluginManager::GetProcessCreateCallbackForPluginName(const_plugin_name); if (create_callback) { - process_sp = create_callback(target_sp, listener_sp, crash_file_path); + process_sp = create_callback(target_sp, listener_sp, crash_file_path, + can_connect); if (process_sp) { if (process_sp->CanDebug(target_sp, true)) { process_sp->m_process_unique_id = ++g_process_unique_id; @@ -502,7 +504,8 @@ ProcessSP Process::FindPlugin(lldb::TargetSP target_sp, (create_callback = PluginManager::GetProcessCreateCallbackAtIndex(idx)) != nullptr; ++idx) { - process_sp = create_callback(target_sp, listener_sp, crash_file_path); + process_sp = create_callback(target_sp, listener_sp, crash_file_path, + can_connect); if (process_sp) { if (process_sp->CanDebug(target_sp, false)) { process_sp->m_process_unique_id = ++g_process_unique_id; diff --git a/lldb/source/Target/ProcessTrace.cpp b/lldb/source/Target/ProcessTrace.cpp index 85e5380fe70b8..4f7a5766c35dd 100644 --- a/lldb/source/Target/ProcessTrace.cpp +++ b/lldb/source/Target/ProcessTrace.cpp @@ -34,7 +34,10 @@ void ProcessTrace::Terminate() { ProcessSP ProcessTrace::CreateInstance(TargetSP target_sp, ListenerSP listener_sp, - const FileSpec *crash_file) { + const FileSpec *crash_file, + bool can_connect) { + if (can_connect) + return nullptr; return std::make_shared(target_sp, listener_sp); } diff --git a/lldb/source/Target/Target.cpp b/lldb/source/Target/Target.cpp index 9bed2035bf854..c6bb989c132e1 100644 --- a/lldb/source/Target/Target.cpp +++ b/lldb/source/Target/Target.cpp @@ -199,12 +199,13 @@ void Target::DeleteCurrentProcess() { const lldb::ProcessSP &Target::CreateProcess(ListenerSP listener_sp, llvm::StringRef plugin_name, - const FileSpec *crash_file) { + const FileSpec *crash_file, + bool can_connect) { if (!listener_sp) listener_sp = GetDebugger().GetListener(); DeleteCurrentProcess(); m_process_sp = Process::FindPlugin(shared_from_this(), plugin_name, - listener_sp, crash_file); + listener_sp, crash_file, can_connect); return m_process_sp; } @@ -2975,7 +2976,7 @@ Status Target::Launch(ProcessLaunchInfo &launch_info, Stream *stream) { } else { // Use a Process plugin to construct the process. const char *plugin_name = launch_info.GetProcessPluginName(); - CreateProcess(launch_info.GetListener(), plugin_name, nullptr); + CreateProcess(launch_info.GetListener(), plugin_name, nullptr, false); } // Since we didn't have a platform launch the process, launch it here. @@ -3103,7 +3104,7 @@ Status Target::Attach(ProcessAttachInfo &attach_info, Stream *stream) { const char *plugin_name = attach_info.GetProcessPluginName(); process_sp = CreateProcess(attach_info.GetListenerForProcess(GetDebugger()), - plugin_name, nullptr); + plugin_name, nullptr, false); if (process_sp == nullptr) { error.SetErrorStringWithFormat( "failed to create process using plugin %s", diff --git a/lldb/source/Target/TargetProperties.td b/lldb/source/Target/TargetProperties.td index c624bc35d16e4..627ed087384e5 100644 --- a/lldb/source/Target/TargetProperties.td +++ b/lldb/source/Target/TargetProperties.td @@ -36,7 +36,7 @@ let Definition = "target" in { Desc<"Skip function prologues when setting breakpoints by name.">; def SourceMap: Property<"source-map", "PathMap">, DefaultStringValue<"">, - Desc<"Source path remappings are used to track the change of location between a source file when built, and where it exists on the current system. It consists of an array of duples, the first element of each duple is some part (starting at the root) of the path to the file when it was built, and the second is where the remainder of the original build hierarchy is rooted on the local system. Each element of the array is checked in order and the first one that results in a match wins.">; + Desc<"Source path remappings apply substitutions to the paths of source files, typically needed to debug from a different host than the one that built the target. The source-map property consists of an array of pairs, the first element is a path prefix, and the second is its replacement. The syntax is `prefix1 replacement1 prefix2 replacement2...`. The pairs are checked in order, the first prefix that matches is used, and that prefix is substituted with the replacement. A common pattern is to use source-map in conjunction with the clang -fdebug-prefix-map flag. In the build, use `-fdebug-prefix-map=/path/to/build_dir=.` to rewrite the host specific build directory to `.`. Then for debugging, use `settings set target.source-map . /path/to/local_dir` to convert `.` to a valid local path.">; def ExecutableSearchPaths: Property<"exec-search-paths", "FileSpecList">, DefaultStringValue<"">, Desc<"Executable search paths to use when locating executable files whose paths don't match the local file system.">; diff --git a/lldb/source/Target/TraceSessionFileParser.cpp b/lldb/source/Target/TraceSessionFileParser.cpp index bf6b6204e1e0b..1cef818309893 100644 --- a/lldb/source/Target/TraceSessionFileParser.cpp +++ b/lldb/source/Target/TraceSessionFileParser.cpp @@ -127,7 +127,8 @@ TraceSessionFileParser::ParseProcess(const JSONProcess &process) { ProcessSP process_sp = target_sp->CreateProcess( /*listener*/ nullptr, "trace", - /*crash_file*/ nullptr); + /*crash_file*/ nullptr, + /*can_connect*/ false); process_sp->SetID(static_cast(process.pid)); diff --git a/lldb/test/API/commands/expression/import-std-module/deque-basic/TestDequeFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/deque-basic/TestDequeFromStdModule.py index 18bd8ae37ff95..0eaa50a127279 100644 --- a/lldb/test/API/commands/expression/import-std-module/deque-basic/TestDequeFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/deque-basic/TestDequeFromStdModule.py @@ -22,7 +22,7 @@ def test(self): self.runCmd("settings set target.import-std-module true") - deque_type = "std::deque >" + deque_type = "std::deque" size_type = deque_type + "::size_type" value_type = "std::__deque_base >::value_type" iterator = deque_type + "::iterator" diff --git a/lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/TestDbgInfoContentDequeFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/TestDbgInfoContentDequeFromStdModule.py index e014f08d8509e..5a1f1fc4d6ac3 100644 --- a/lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/TestDbgInfoContentDequeFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/deque-dbg-info-content/TestDbgInfoContentDequeFromStdModule.py @@ -22,7 +22,7 @@ def test(self): self.runCmd("settings set target.import-std-module true") - deque_type = "std::deque >" + deque_type = "std::deque" size_type = deque_type + "::size_type" value_type = "std::__deque_base >::value_type" diff --git a/lldb/test/API/commands/expression/import-std-module/forward_list-dbg-info-content/TestDbgInfoContentForwardListFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/forward_list-dbg-info-content/TestDbgInfoContentForwardListFromStdModule.py index 704cbc8168fa5..b1f206d72197d 100644 --- a/lldb/test/API/commands/expression/import-std-module/forward_list-dbg-info-content/TestDbgInfoContentForwardListFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/forward_list-dbg-info-content/TestDbgInfoContentForwardListFromStdModule.py @@ -22,7 +22,7 @@ def test(self): self.runCmd("settings set target.import-std-module true") - list_type = "std::forward_list >" + list_type = "std::forward_list" value_type = list_type + "::value_type" # FIXME: This has three elements in it but the formatter seems to diff --git a/lldb/test/API/commands/expression/import-std-module/forward_list/TestForwardListFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/forward_list/TestForwardListFromStdModule.py index 12d9a9930890f..9c4bf83cfcb8f 100644 --- a/lldb/test/API/commands/expression/import-std-module/forward_list/TestForwardListFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/forward_list/TestForwardListFromStdModule.py @@ -22,7 +22,7 @@ def test(self): self.runCmd("settings set target.import-std-module true") - list_type = "std::forward_list >" + list_type = "std::forward_list" value_type = list_type + "::value_type" # FIXME: This has three elements in it but the formatter seems to diff --git a/lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/TestDbgInfoContentListFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/TestDbgInfoContentListFromStdModule.py index fea6caaadf716..94d9ca72b2203 100644 --- a/lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/TestDbgInfoContentListFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/list-dbg-info-content/TestDbgInfoContentListFromStdModule.py @@ -23,7 +23,7 @@ def test(self): self.runCmd("settings set target.import-std-module true") - list_type = "std::list >" + list_type = "std::list" size_type = list_type + "::size_type" value_type = list_type + "::value_type" diff --git a/lldb/test/API/commands/expression/import-std-module/list/TestListFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/list/TestListFromStdModule.py index 9382c800ec76e..0d7d915fcaa5f 100644 --- a/lldb/test/API/commands/expression/import-std-module/list/TestListFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/list/TestListFromStdModule.py @@ -22,7 +22,7 @@ def test(self): self.runCmd("settings set target.import-std-module true") - list_type = "std::list >" + list_type = "std::list" size_type = list_type + "::size_type" value_type = list_type + "::value_type" diff --git a/lldb/test/API/commands/expression/import-std-module/queue/TestQueueFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/queue/TestQueueFromStdModule.py index 75cc98c150553..06f77ba5a9e72 100644 --- a/lldb/test/API/commands/expression/import-std-module/queue/TestQueueFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/queue/TestQueueFromStdModule.py @@ -22,7 +22,7 @@ def test(self): self.runCmd("settings set target.import-std-module true") - queue_type = "std::queue > >" + queue_type = "std::queue" size_type = queue_type + "::size_type" value_type = "std::__deque_base >::value_type" @@ -54,9 +54,9 @@ def test(self): result_value="5") # Test std::queue functionality with a std::list. - queue_type = "std::queue > >" + queue_type = "std::queue >" size_type = queue_type + "::size_type" - value_type = "std::list >::value_type" + value_type = "std::list::value_type" self.expect_expr( "q_list", result_type=queue_type, diff --git a/lldb/test/API/commands/expression/import-std-module/stack/TestStackFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/stack/TestStackFromStdModule.py index d9a7e186fa6f0..4486768e2909e 100644 --- a/lldb/test/API/commands/expression/import-std-module/stack/TestStackFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/stack/TestStackFromStdModule.py @@ -22,7 +22,7 @@ def test(self): self.runCmd("settings set target.import-std-module true") # Test std::stack functionality with a std::deque. - stack_type = "std::stack > >" + stack_type = "std::stack" size_type = stack_type + "::size_type" self.expect_expr("s_deque", result_type=stack_type) @@ -40,7 +40,7 @@ def test(self): result_value="5") # Test std::stack functionality with a std::vector. - stack_type = "std::stack > >" + stack_type = "std::stack >" size_type = stack_type + "::size_type" self.expect_expr("s_vector", result_type=stack_type) @@ -58,7 +58,7 @@ def test(self): result_value="5") # Test std::stack functionality with a std::list. - stack_type = "std::stack > >" + stack_type = "std::stack >" size_type = stack_type + "::size_type" self.expect_expr("s_list", result_type=stack_type) self.expect("expr s_list.pop()") diff --git a/lldb/test/API/commands/expression/import-std-module/unique_ptr-dbg-info-content/TestUniquePtrDbgInfoContent.py b/lldb/test/API/commands/expression/import-std-module/unique_ptr-dbg-info-content/TestUniquePtrDbgInfoContent.py index 9f698af7e1b4a..abc9c1931489f 100644 --- a/lldb/test/API/commands/expression/import-std-module/unique_ptr-dbg-info-content/TestUniquePtrDbgInfoContent.py +++ b/lldb/test/API/commands/expression/import-std-module/unique_ptr-dbg-info-content/TestUniquePtrDbgInfoContent.py @@ -25,7 +25,7 @@ def test(self): self.expect_expr( "s", - result_type="std::unique_ptr >", + result_type="std::unique_ptr", result_children=[ValueCheck(children=[ValueCheck(value="3")])]) self.expect_expr("s->a", result_type="int", result_value="3") self.expect_expr("s->a = 5", result_type="int", result_value="5") diff --git a/lldb/test/API/commands/expression/import-std-module/unique_ptr/TestUniquePtrFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/unique_ptr/TestUniquePtrFromStdModule.py index a3761ade04e30..878315b8eafdc 100644 --- a/lldb/test/API/commands/expression/import-std-module/unique_ptr/TestUniquePtrFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/unique_ptr/TestUniquePtrFromStdModule.py @@ -25,7 +25,7 @@ def test(self): self.expect_expr( "s", - result_type="std::unique_ptr >", + result_type="std::unique_ptr", result_summary="3", result_children=[ValueCheck(name="__value_")]) self.expect_expr("*s", result_type="int", result_value="3") diff --git a/lldb/test/API/commands/expression/import-std-module/vector-bool/TestVectorBoolFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/vector-bool/TestVectorBoolFromStdModule.py index 0f0279e4c017c..79e7478e485e3 100644 --- a/lldb/test/API/commands/expression/import-std-module/vector-bool/TestVectorBoolFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/vector-bool/TestVectorBoolFromStdModule.py @@ -20,7 +20,7 @@ def test(self): "// Set break point at this line.", lldb.SBFileSpec("main.cpp")) - vector_type = "std::vector >" + vector_type = "std::vector" size_type = vector_type + "::size_type" self.runCmd("settings set target.import-std-module true") diff --git a/lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/TestDbgInfoContentVectorFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/TestDbgInfoContentVectorFromStdModule.py index 6537178e03e63..d53a9bfb59014 100644 --- a/lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/TestDbgInfoContentVectorFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/vector-dbg-info-content/TestDbgInfoContentVectorFromStdModule.py @@ -23,7 +23,7 @@ def test(self): self.runCmd("settings set target.import-std-module true") - vector_type = "std::vector >" + vector_type = "std::vector" size_type = vector_type + "::size_type" value_type = vector_type + "::value_type" iterator = vector_type + "::iterator" diff --git a/lldb/test/API/commands/expression/import-std-module/vector-of-vectors/TestVectorOfVectorsFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/vector-of-vectors/TestVectorOfVectorsFromStdModule.py index bb1d736689caa..e0b511c91bd0f 100644 --- a/lldb/test/API/commands/expression/import-std-module/vector-of-vectors/TestVectorOfVectorsFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/vector-of-vectors/TestVectorOfVectorsFromStdModule.py @@ -20,13 +20,9 @@ def test(self): "// Set break point at this line.", lldb.SBFileSpec("main.cpp")) - vector_type = "std::vector >" - vector_of_vector_type = "std::vector<" + vector_type + \ - ", std::allocator > > >" - size_type = ( - "std::vector >, " + - "std::allocator > >" + - " >::size_type") + vector_type = "std::vector" + vector_of_vector_type = "std::vector<" + vector_type + " >" + size_type = vector_of_vector_type + "::size_type" value_type = "std::__vector_base >::value_type" self.runCmd("settings set target.import-std-module true") @@ -35,13 +31,13 @@ def test(self): "a", result_type=vector_of_vector_type, result_children=[ - ValueCheck(type="std::vector >", + ValueCheck(type="std::vector", children=[ ValueCheck(value='1'), ValueCheck(value='2'), ValueCheck(value='3'), ]), - ValueCheck(type="std::vector >", + ValueCheck(type="std::vector", children=[ ValueCheck(value='3'), ValueCheck(value='2'), diff --git a/lldb/test/API/commands/expression/import-std-module/vector/TestVectorFromStdModule.py b/lldb/test/API/commands/expression/import-std-module/vector/TestVectorFromStdModule.py index c9e1c94eb4159..9a186e7a22435 100644 --- a/lldb/test/API/commands/expression/import-std-module/vector/TestVectorFromStdModule.py +++ b/lldb/test/API/commands/expression/import-std-module/vector/TestVectorFromStdModule.py @@ -22,7 +22,7 @@ def test(self): self.runCmd("settings set target.import-std-module true") - vector_type = "std::vector >" + vector_type = "std::vector" size_type = vector_type + "::size_type" value_type = "std::__vector_base >::value_type" iterator = vector_type + "::iterator" diff --git a/lldb/test/API/commands/register/register/register_command/TestRegisters.py b/lldb/test/API/commands/register/register/register_command/TestRegisters.py index 4c326912c89bc..5e26f3317b416 100644 --- a/lldb/test/API/commands/register/register/register_command/TestRegisters.py +++ b/lldb/test/API/commands/register/register/register_command/TestRegisters.py @@ -190,6 +190,11 @@ def write_and_read(self, frame, register, new_value, must_exist=True): ' = ', new_value]) + # This test relies on ftag containing the 'abridged' value. Linux + # and *BSD targets have been ported to report the full value instead + # consistently with GDB. They are covered by the new-style + # lldb/test/Shell/Register/x86*-fp-read.test. + @skipUnlessDarwin def fp_special_purpose_register_read(self): exe = self.getBuildArtifact("a.out") @@ -399,7 +404,12 @@ def fp_register_write(self): for registerSet in registerSets: if 'advanced vector extensions' in registerSet.GetName().lower(): has_avx = True - if 'memory protection extension' in registerSet.GetName().lower(): + # FreeBSD/NetBSD reports missing register sets differently + # at the moment and triggers false positive here. + # TODO: remove FreeBSD/NetBSD exception when we make unsupported + # register groups correctly disappear. + if ('memory protection extension' in registerSet.GetName().lower() + and self.getPlatform() not in ["freebsd", "netbsd"]): has_mpx = True if has_avx: diff --git a/lldb/test/API/functionalities/gdb_remote_client/TestProcessConnect.py b/lldb/test/API/functionalities/gdb_remote_client/TestProcessConnect.py index 5e98e3b028d03..80b83fbe29191 100644 --- a/lldb/test/API/functionalities/gdb_remote_client/TestProcessConnect.py +++ b/lldb/test/API/functionalities/gdb_remote_client/TestProcessConnect.py @@ -11,7 +11,6 @@ class TestProcessConnect(GDBRemoteTestBase): NO_DEBUG_INFO_TESTCASE = True - @skipIfWindows def test_gdb_remote_sync(self): """Test the gdb-remote command in synchronous mode""" try: @@ -21,7 +20,6 @@ def test_gdb_remote_sync(self): finally: self.dbg.GetSelectedPlatform().DisconnectRemote() - @skipIfWindows @skipIfReproducer # Reproducer don't support async. def test_gdb_remote_async(self): """Test the gdb-remote command in asynchronous mode""" @@ -36,11 +34,12 @@ def test_gdb_remote_async(self): self.dbg.GetSelectedPlatform().DisconnectRemote() @skipIfWindows - @expectedFailureAll(oslist=["freebsd"]) def test_process_connect_sync(self): """Test the gdb-remote command in synchronous mode""" try: self.dbg.SetAsync(False) + self.expect("platform select remote-gdb-server", + substrs=['Platform: remote-gdb-server', 'Connected: no']) self.expect("process connect connect://" + self.server.get_connect_address(), substrs=['Process', 'stopped']) @@ -48,12 +47,13 @@ def test_process_connect_sync(self): self.dbg.GetSelectedPlatform().DisconnectRemote() @skipIfWindows - @expectedFailureAll(oslist=["freebsd"]) @skipIfReproducer # Reproducer don't support async. def test_process_connect_async(self): """Test the gdb-remote command in asynchronous mode""" try: self.dbg.SetAsync(True) + self.expect("platform select remote-gdb-server", + substrs=['Platform: remote-gdb-server', 'Connected: no']) self.expect("process connect connect://" + self.server.get_connect_address(), matching=False, diff --git a/lldb/test/API/functionalities/thread/step_out/TestThreadStepOut.py b/lldb/test/API/functionalities/thread/step_out/TestThreadStepOut.py index eb2d264ec2e3c..ae46530f4ab50 100644 --- a/lldb/test/API/functionalities/thread/step_out/TestThreadStepOut.py +++ b/lldb/test/API/functionalities/thread/step_out/TestThreadStepOut.py @@ -70,12 +70,8 @@ def setUp(self): self.bkpt_string = '// Set breakpoint here' self.breakpoint = line_number('main.cpp', self.bkpt_string) - if "gcc" in self.getCompiler() or self.isIntelCompiler(): - self.step_out_destination = line_number( - 'main.cpp', '// Expect to stop here after step-out (icc and gcc)') - else: - self.step_out_destination = line_number( - 'main.cpp', '// Expect to stop here after step-out (clang)') + self.step_out_destination = line_number( + 'main.cpp', '// Expect to stop here after step-out.') def step_out_single_thread_with_cmd(self): self.step_out_with_cmd("this-thread") diff --git a/lldb/test/API/functionalities/thread/step_out/main.cpp b/lldb/test/API/functionalities/thread/step_out/main.cpp index 14d84010de8aa..e7dd230d239ce 100644 --- a/lldb/test/API/functionalities/thread/step_out/main.cpp +++ b/lldb/test/API/functionalities/thread/step_out/main.cpp @@ -19,10 +19,10 @@ thread_func () pseudo_barrier_wait(g_barrier); // Do something - step_out_of_here(); // Expect to stop here after step-out (clang) + step_out_of_here(); // Return - return NULL; // Expect to stop here after step-out (icc and gcc) + return NULL; // Expect to stop here after step-out. } int main () diff --git a/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py b/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py index 13fe9c3c0398a..609931e1f8926 100644 --- a/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py +++ b/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py @@ -433,7 +433,7 @@ def qRegisterInfo_contains_avx_registers(self): "Advanced Vector Extensions" in register_sets) @expectedFailureAll(oslist=["windows"]) # no avx for now. - @expectedFailureAll(oslist=["freebsd", "netbsd"]) + @expectedFailureAll(oslist=["netbsd"]) @llgs_test def test_qRegisterInfo_contains_avx_registers_llgs(self): self.init_llgs_test() @@ -585,9 +585,15 @@ def p_returns_correct_data_size_for_each_qRegisterInfo(self): p_response = context.get("p_response") self.assertIsNotNone(p_response) + # Skip erraneous (unsupported) registers. + # TODO: remove this once we make unsupported registers disappear. + if p_response.startswith("E") and len(p_response) == 3: + continue + if "dynamic_size_dwarf_expr_bytes" in reg_info: self.updateRegInfoBitsize(reg_info, byte_order) - self.assertEqual(len(p_response), 2 * int(reg_info["bitsize"]) / 8) + self.assertEqual(len(p_response), 2 * int(reg_info["bitsize"]) / 8, + reg_info) # Increment loop reg_index += 1 @@ -601,7 +607,7 @@ def test_p_returns_correct_data_size_for_each_qRegisterInfo_launch_debugserver( self.set_inferior_startup_launch() self.p_returns_correct_data_size_for_each_qRegisterInfo() - @expectedFailureAll(oslist=["freebsd", "netbsd"]) + @expectedFailureAll(oslist=["netbsd"]) @llgs_test def test_p_returns_correct_data_size_for_each_qRegisterInfo_launch_llgs( self): @@ -619,7 +625,7 @@ def test_p_returns_correct_data_size_for_each_qRegisterInfo_attach_debugserver( self.set_inferior_startup_attach() self.p_returns_correct_data_size_for_each_qRegisterInfo() - @expectedFailureAll(oslist=["freebsd", "netbsd"]) + @expectedFailureAll(oslist=["netbsd"]) @llgs_test def test_p_returns_correct_data_size_for_each_qRegisterInfo_attach_llgs( self): diff --git a/lldb/test/Shell/Commands/command-process-connect.test b/lldb/test/Shell/Commands/command-process-connect.test deleted file mode 100644 index 415cda123b358..0000000000000 --- a/lldb/test/Shell/Commands/command-process-connect.test +++ /dev/null @@ -1,12 +0,0 @@ -# UNSUPPORTED: system-windows -# XFAIL: system-freebsd - -# Synchronous -# RUN: %lldb -o 'platform select remote-gdb-server' -o 'process connect connect://localhost:4321' 2>&1 | FileCheck %s - -# Asynchronous -# RUN: echo -e 'platform select remote-gdb-server\nprocess connect connect://localhost:4321' | %lldb 2>&1 | FileCheck %s - -# CHECK: Platform: remote-gdb-server -# CHECK: Connected: no -# CHECK: error: Failed to connect port diff --git a/lldb/test/Shell/Register/x86-64-fp-read.test b/lldb/test/Shell/Register/x86-64-fp-read.test index 2be85a6c3b358..39fdaf170f3f2 100644 --- a/lldb/test/Shell/Register/x86-64-fp-read.test +++ b/lldb/test/Shell/Register/x86-64-fp-read.test @@ -1,4 +1,6 @@ # XFAIL: system-windows +# Darwin uses the legacy behavior of reporting abridged ftag value, +# it is covered by TestRegisters.py::fp_special_purpose_register_read. # XFAIL: system-darwin # REQUIRES: native && target-x86_64 # RUN: %clangxx_host -g %p/Inputs/x86-fp-read.cpp -o %t @@ -15,9 +17,7 @@ print &zero register read --all # CHECK-DAG: fctrl = 0x037b # CHECK-DAG: fstat = 0x8084 -# TODO: the following value is incorrect, it's a bug in the way -# FXSAVE/XSAVE is interpreted -# CHECK-DAG: ftag = 0x007f +# CHECK-DAG: ftag = 0xea58 # CHECK-DAG: fop = 0x0033 # CHECK-DAG: fip = [[FDIV]] # CHECK-DAG: fdp = [[ZERO]] diff --git a/lldb/test/Shell/Register/x86-64-fp-write.test b/lldb/test/Shell/Register/x86-64-fp-write.test index ad7cfe7a7ee4b..cbfb6c6cdbe0f 100644 --- a/lldb/test/Shell/Register/x86-64-fp-write.test +++ b/lldb/test/Shell/Register/x86-64-fp-write.test @@ -1,4 +1,6 @@ # XFAIL: system-windows +# Darwin uses the legacy behavior of reporting abridged ftag value, +# it is covered by TestRegisters.py::fp_special_purpose_register_read. # XFAIL: system-darwin # REQUIRES: native && target-x86_64 # RUN: %clangxx_host %p/Inputs/x86-fp-write.cpp -o %t @@ -8,8 +10,7 @@ process launch register write fctrl 0x037b register write fstat 0x8884 # note: this needs to enable all registers for writes to be effective -# TODO: fix it to use proper ftag values instead of 'abridged' -register write ftag 0x00ff +register write ftag 0x2a58 register write fop 0x0033 # the exact addresses do not matter, we want just to verify FXSAVE # note: fxrstor64 apparently truncates this to 48 bits, and sign extends diff --git a/lldb/test/Shell/Register/x86-fp-read.test b/lldb/test/Shell/Register/x86-fp-read.test index 3c676c1d21189..566157b938367 100644 --- a/lldb/test/Shell/Register/x86-fp-read.test +++ b/lldb/test/Shell/Register/x86-fp-read.test @@ -1,4 +1,7 @@ # XFAIL: system-windows +# Darwin uses the legacy behavior of reporting abridged ftag value, +# it is covered by TestRegisters.py::fp_special_purpose_register_read. +# XFAIL: system-darwin # REQUIRES: native && target-x86 # RUN: %clangxx_host -g %p/Inputs/x86-fp-read.cpp -o %t # RUN: %lldb -b -s %s %t | FileCheck %s @@ -14,9 +17,7 @@ print &zero register read --all # CHECK-DAG: fctrl = 0x037b # CHECK-DAG: fstat = 0x8084 -# TODO: the following value is incorrect, it's a bug in the way -# FXSAVE/XSAVE is interpreted -# CHECK-DAG: ftag = 0x007f +# CHECK-DAG: ftag = 0xea58 # CHECK-DAG: fop = 0x0033 # CHECK-DAG: fioff = [[FDIV]] # CHECK-DAG: fooff = [[ZERO]] diff --git a/lldb/test/Shell/Register/x86-fp-write.test b/lldb/test/Shell/Register/x86-fp-write.test index ecc593e6d64d0..2040c2763307a 100644 --- a/lldb/test/Shell/Register/x86-fp-write.test +++ b/lldb/test/Shell/Register/x86-fp-write.test @@ -1,4 +1,6 @@ # XFAIL: system-windows +# Darwin uses the legacy behavior of reporting abridged ftag value, +# it is covered by TestRegisters.py::fp_special_purpose_register_read. # XFAIL: system-darwin # REQUIRES: native && (target-x86 || target-x86_64) # RUN: %clangxx_host %p/Inputs/x86-fp-write.cpp -o %t @@ -8,8 +10,7 @@ process launch register write fctrl 0x037b register write fstat 0x8884 # note: this needs to enable all registers for writes to be effective -# TODO: fix it to use proper ftag values instead of 'abridged' -register write ftag 0x00ff +register write ftag 0x2a58 register write fop 0x0033 # the exact addresses do not matter, we want just to verify FXSAVE # note: segment registers are not supported on all CPUs diff --git a/lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp b/lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp index 8d101ba280e8e..d5365f1832fbe 100644 --- a/lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp +++ b/lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp @@ -28,9 +28,9 @@ int main(int argc, char **argv) { // CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+17>: mov dword ptr [rsp + 0x24], ecx // CHECK: ** 15 foo(); // CHECK: disassembly.cpp.tmp.exe[{{.*}}] <+21>: call {{.*}} ; foo at disassembly.cpp:12 -// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+26>: xor eax, eax // CHECK: ** 16 return 0; // CHECK-NEXT: 17 } // CHECK-NEXT: 18 -// CHECK: disassembly.cpp.tmp.exe[{{.*}}] <+28>: add rsp, 0x38 +// CHECK: disassembly.cpp.tmp.exe[{{.*}}] <+26>: xor eax, eax +// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+28>: add rsp, 0x38 // CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+32>: ret diff --git a/lldb/test/Shell/SymbolFile/NativePDB/load-pdb.cpp b/lldb/test/Shell/SymbolFile/NativePDB/load-pdb.cpp index 2ffcece075b06..8840a1242a044 100644 --- a/lldb/test/Shell/SymbolFile/NativePDB/load-pdb.cpp +++ b/lldb/test/Shell/SymbolFile/NativePDB/load-pdb.cpp @@ -22,7 +22,7 @@ int main(int argc, char** argv) { // CHECK: (lldb) target symbols add {{.*}}bar.pdb // CHECK: symbol file '{{.*}}bar.pdb' has been added to '{{.*}}foo.exe' // CHECK: (lldb) b main -// CHECK: Breakpoint 1: where = foo.exe`main + 23 at load-pdb.cpp:19, address = 0x0000000140001017 +// CHECK: Breakpoint 1: where = foo.exe`main + 21 at load-pdb.cpp:19, address = 0x0000000140001015 // CHECK: (lldb) image dump symfile // CHECK: Types: // CHECK: {{.*}}: Type{0x00010024} , size = 0, compiler_type = {{.*}} int (int, char **) diff --git a/lldb/unittests/Process/Utility/CMakeLists.txt b/lldb/unittests/Process/Utility/CMakeLists.txt index 9d827582b3cf9..78e29ed262c90 100644 --- a/lldb/unittests/Process/Utility/CMakeLists.txt +++ b/lldb/unittests/Process/Utility/CMakeLists.txt @@ -1,4 +1,5 @@ add_lldb_unittest(ProcessUtilityTests + RegisterContextTest.cpp RegisterContextFreeBSDTest.cpp LinuxProcMapsTest.cpp diff --git a/lldb/unittests/Process/Utility/RegisterContextTest.cpp b/lldb/unittests/Process/Utility/RegisterContextTest.cpp new file mode 100644 index 0000000000000..f0aa6076d8f2c --- /dev/null +++ b/lldb/unittests/Process/Utility/RegisterContextTest.cpp @@ -0,0 +1,73 @@ +//===-- RegisterContextTest.cpp -------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "gtest/gtest.h" + +#include "Plugins/Process/Utility/RegisterContext_x86.h" + +#include "llvm/ADT/STLExtras.h" +#include "llvm/Support/FormatVariadic.h" + +#include + +using namespace lldb_private; + +struct TagWordTestVector { + uint16_t sw; + uint16_t tw; + uint8_t tw_abridged; + int st_reg_num; +}; + +constexpr MMSReg st_from_comp(uint64_t mantissa, uint16_t sign_exp) { + MMSReg ret = {}; + ret.comp.mantissa = mantissa; + ret.comp.sign_exp = sign_exp; + return ret; +} + +const std::array st_regs = { + st_from_comp(0x8000000000000000, 0x4000), // +2.0 + st_from_comp(0x3f00000000000000, 0x0000), // 1.654785e-4932 + st_from_comp(0x0000000000000000, 0x0000), // +0 + st_from_comp(0x0000000000000000, 0x8000), // -0 + st_from_comp(0x8000000000000000, 0x7fff), // +inf + st_from_comp(0x8000000000000000, 0xffff), // -inf + st_from_comp(0xc000000000000000, 0xffff), // nan + st_from_comp(0x8000000000000000, 0xc000), // -2.0 +}; + +const std::array tag_word_test_vectors{ + TagWordTestVector{0x3800, 0x3fff, 0x80, 1}, + TagWordTestVector{0x3000, 0x2fff, 0xc0, 2}, + TagWordTestVector{0x2800, 0x27ff, 0xe0, 3}, + TagWordTestVector{0x2000, 0x25ff, 0xf0, 4}, + TagWordTestVector{0x1800, 0x25bf, 0xf8, 5}, + TagWordTestVector{0x1000, 0x25af, 0xfc, 6}, + TagWordTestVector{0x0800, 0x25ab, 0xfe, 7}, + TagWordTestVector{0x0000, 0x25a8, 0xff, 8}, +}; + +TEST(RegisterContext_x86Test, AbridgedToFullTagWord) { + for (const auto &x : llvm::enumerate(tag_word_test_vectors)) { + SCOPED_TRACE(llvm::formatv("tag_word_test_vectors[{0}]", x.index())); + std::array test_regs; + for (int i = 0; i < x.value().st_reg_num; ++i) + test_regs[i] = st_regs[x.value().st_reg_num - i - 1]; + EXPECT_EQ( + AbridgedToFullTagWord(x.value().tw_abridged, x.value().sw, test_regs), + x.value().tw); + } +} + +TEST(RegisterContext_x86Test, FullToAbridgedTagWord) { + for (const auto &x : llvm::enumerate(tag_word_test_vectors)) { + SCOPED_TRACE(llvm::formatv("tag_word_test_vectors[{0}]", x.index())); + EXPECT_EQ(FullToAbridgedTagWord(x.value().tw), x.value().tw_abridged); + } +} diff --git a/llvm-spirv/.github/workflows/check-in-tree-build.yml b/llvm-spirv/.github/workflows/check-in-tree-build.yml new file mode 100644 index 0000000000000..514a1660a0409 --- /dev/null +++ b/llvm-spirv/.github/workflows/check-in-tree-build.yml @@ -0,0 +1,175 @@ +# This workflow is intended to check that in-tree build of the translator is +# healthy and all tests pass. It is used in pre-commits and nightly builds. +# +# Documentation for GitHub Actions: +# [workflow-syntax]: https://docs.github.com/en/free-pro-team@latest/actions/reference/workflow-syntax-for-github-actions +# [context-and-expression-syntax]: https://docs.github.com/en/free-pro-team@latest/actions/reference/context-and-expression-syntax-for-github-actions +name: In-tree build & tests + +on: + push: + branches: + - master + - llvm_release_* + paths-ignore: # no need to check build for documentation changes + - 'docs/**' + - '**.md' + pull_request: + branches: + - master + - llvm_release_* + paths-ignore: # no need to check build for documentation changes + - 'docs/**' + - '**.md' + schedule: + # Ideally, we might want to simplify our regular nightly build as we + # probably don't need every configuration to be built every day: most of + # them are only necessary in pre-commits to avoid breakages + - cron: 0 0 * * * + +env: + LLVM_VERSION: 12 + +jobs: + build_and_test_linux: + name: Linux + strategy: + matrix: + build_type: [Release, Debug] + shared_libs: [NoSharedLibs] + include: + - build_type: Release + shared_libs: EnableSharedLibs + fail-fast: false + runs-on: ubuntu-18.04 + steps: + - name: Install dependencies + run: | + curl -L "https://apt.llvm.org/llvm-snapshot.gpg.key" | sudo apt-key add - + curl -L "https://packages.lunarg.com/lunarg-signing-key-pub.asc" | sudo apt-key add - + echo "deb https://apt.llvm.org/bionic/ llvm-toolchain-bionic main" | sudo tee -a /etc/apt/sources.list + echo "deb https://packages.lunarg.com/vulkan bionic main" | sudo tee -a /etc/apt/sources.list + sudo apt-get update + # Linux systems in GitHub Actions already have a pre-installed clang + # that is not needed for the translator as we rely on newer version + sudo apt-get --purge remove clang-8 clang-9 + sudo apt-get -yq --no-install-suggests --no-install-recommends install \ + clang-${{ env.LLVM_VERSION }} \ + spirv-tools + sudo update-alternatives --install /usr/bin/clang clang /usr/bin/clang-${{ env.LLVM_VERSION }} 1000 + - name: Checkout LLVM sources + uses: actions/checkout@v2 + with: + repository: llvm/llvm-project + ref: master + path: llvm-project + - name: Checkout the translator sources + uses: actions/checkout@v2 + with: + path: llvm-project/llvm/projects/SPIRV-LLVM-Translator + - name: Configure + run: | + mkdir build && cd build + # ON/OFF specifically weren't used as a values for shared_libs matrix + # field to improve usability of PR page: instead of (Release, ON) a + # job will be displayed as (Release, EnableSharedLibs) + SHARED_LIBS=OFF + if [[ "${{ matrix.shared_libs }}" == "EnableSharedLibs" ]]; then + SHARED_LIBS=ON + fi + cmake ${{ github.workspace }}/llvm-project/llvm \ + -DCMAKE_BUILD_TYPE=${{ matrix.build_type }} \ + -DBUILD_SHARED_LIBS=${SHARED_LIBS} \ + -DLLVM_TARGETS_TO_BUILD="X86" \ + -DSPIRV_SKIP_CLANG_BUILD=ON \ + -DSPIRV_SKIP_DEBUG_INFO_TESTS=ON \ + -DLLVM_LIT_ARGS="-sv --no-progress-bar" \ + -G "Unix Makefiles" + - name: Build + run: | + cd build + make llvm-spirv -j2 + - name: Build tests & test + run: | + cd build + make check-llvm-spirv -j2 + + build_windows: + name: Windows + strategy: + matrix: + build_type: [Release] + fail-fast: false + runs-on: windows-latest + steps: + - name: Checkout LLVM sources + uses: actions/checkout@v2 + with: + repository: llvm/llvm-project + ref: master + path: llvm-project + - name: Checkout the translator sources + uses: actions/checkout@v2 + with: + path: llvm-project\\llvm\\projects\\SPIRV-LLVM-Translator + - name: Configure + shell: bash + run: | + mkdir build && cd build + cmake ..\\llvm-project\\llvm \ + -Thost=x64 \ + -DCMAKE_BUILD_TYPE=Release \ + -DLLVM_TARGETS_TO_BUILD="X86" \ + -DSPIRV_SKIP_CLANG_BUILD=ON \ + -DSPIRV_SKIP_DEBUG_INFO_TESTS=ON \ + -DLLVM_LIT_ARGS="-sv --no-progress-bar" + - name: Build + shell: bash + run: | + cd build + cmake --build . --config ${{ matrix.build_type }} --target llvm-spirv -j2 + # FIXME: Testing is disabled at the moment as it requires clang to be present + # - name: Build tests & test + # shell: bash + # run: | + # cd build + # cmake --build . --config Release --target check-llvm-spirv -j2 + + build_and_test_macosx: + name: macOS + strategy: + matrix: + build_type: [Release] + fail-fast: false + runs-on: macos-latest + continue-on-error: true + steps: + - name: Checkout LLVM sources + uses: actions/checkout@v2 + with: + repository: llvm/llvm-project + ref: master + path: llvm-project + - name: Checkout the translator sources + uses: actions/checkout@v2 + with: + path: llvm-project/llvm/projects/SPIRV-LLVM-Translator + - name: Configure + run: | + mkdir build && cd build + cmake ${{ github.workspace }}/llvm-project/llvm \ + -DCMAKE_BUILD_TYPE=${{ matrix.build_type }} \ + -DLLVM_TARGETS_TO_BUILD="X86" \ + -DSPIRV_SKIP_CLANG_BUILD=ON \ + -DSPIRV_SKIP_DEBUG_INFO_TESTS=ON \ + -DLLVM_LIT_ARGS="-sv --no-progress-bar" \ + -G "Unix Makefiles" + - name: Build + run: | + cd build + make llvm-spirv -j2 + # FIXME: Testing is disabled at the moment as it requires clang to be present + # - name: Build tests & test + # run: | + # cd build + # make check-llvm-spirv -j2 diff --git a/llvm-spirv/.github/workflows/check-out-of-tree-build.yml b/llvm-spirv/.github/workflows/check-out-of-tree-build.yml new file mode 100644 index 0000000000000..2ce2c48e76869 --- /dev/null +++ b/llvm-spirv/.github/workflows/check-out-of-tree-build.yml @@ -0,0 +1,72 @@ +# This workflow is intended to check that out-of-tree build of the translator is +# healthy and all tests pass. It is used in pre-commits and nightly builds. +# +# Documentation for GitHub Actions: +# [workflow-syntax]: https://docs.github.com/en/free-pro-team@latest/actions/reference/workflow-syntax-for-github-actions +# [context-and-expression-syntax]: https://docs.github.com/en/free-pro-team@latest/actions/reference/context-and-expression-syntax-for-github-actions +name: Out-of-tree build & tests + +on: + push: + branches: + - master + - llvm_release_* + paths-ignore: # no need to check build for documentation changes + - 'docs/**' + - '**.md' + pull_request: + branches: + - master + - llvm_release_* + paths-ignore: # no need to check build for documentation changes + - 'docs/**' + - '**.md' + schedule: + - cron: 0 0 * * * + +env: + LLVM_VERSION: 12 + +jobs: + build_and_test: + name: Linux + strategy: + matrix: + build_type: [Release, Debug] + fail-fast: false + runs-on: ubuntu-18.04 + steps: + - name: Install dependencies + run: | + curl -L "https://apt.llvm.org/llvm-snapshot.gpg.key" | sudo apt-key add - + curl -L "https://packages.lunarg.com/lunarg-signing-key-pub.asc" | sudo apt-key add - + echo "deb https://apt.llvm.org/bionic/ llvm-toolchain-bionic main" | sudo tee -a /etc/apt/sources.list + echo "deb https://packages.lunarg.com/vulkan bionic main" | sudo tee -a /etc/apt/sources.list + sudo apt-get update + # Linux systems in GitHub Actions already have a pre-installed clang + # that is not needed for the translator as we rely on newer version + sudo apt-get --purge remove clang-8 clang-9 + sudo apt-get -yq --no-install-suggests --no-install-recommends install \ + clang-${{ env.LLVM_VERSION }} \ + llvm-${{ env.LLVM_VERSION }}-dev \ + llvm-${{ env.LLVM_VERSION }}-tools \ + spirv-tools + sudo update-alternatives --install /usr/bin/clang clang /usr/bin/clang-${{ env.LLVM_VERSION }} 1000 + - name: Checkout the translator sources + uses: actions/checkout@v2 + - name: Configure + run: | + mkdir build && cd build + cmake ${{ github.workspace }} \ + -DCMAKE_BUILD_TYPE=${{ matrix.build_type }} \ + -DLLVM_INCLUDE_TESTS=ON \ + -DLLVM_EXTERNAL_LIT="/usr/lib/llvm-${{ env.LLVM_VERSION }}/build/utils/lit/lit.py" \ + -G "Unix Makefiles" + - name: Build + run: | + cd build + make llvm-spirv -j2 + - name: Build tests & test + run: | + cd build + make check-llvm-spirv -j2 diff --git a/llvm-spirv/README.md b/llvm-spirv/README.md index 59fc6dbe0f930..7b8e93a2ac574 100644 --- a/llvm-spirv/README.md +++ b/llvm-spirv/README.md @@ -2,6 +2,9 @@ [![Build Status](https://travis-ci.org/KhronosGroup/SPIRV-LLVM-Translator.svg?branch=master)](https://travis-ci.org/KhronosGroup/SPIRV-LLVM-Translator) +![Out-of-tree build & tests](https://github.com/KhronosGroup/SPIRV-LLVM-Translator/workflows/Out-of-tree%20build%20&%20tests/badge.svg?branch=master&event=schedule) +![In-tree build & tests](https://github.com/KhronosGroup/SPIRV-LLVM-Translator/workflows/In-tree%20build%20&%20tests/badge.svg?branch=master&event=schedule) + This repository contains source code for the LLVM/SPIR-V Bi-Directional Translator, a library and tool for translation between LLVM IR and [SPIR-V](https://www.khronos.org/registry/spir-v/). The LLVM/SPIR-V Bi-Directional Translator is open source software. You may freely distribute it under the terms of the license agreement found in LICENSE.txt. @@ -82,7 +85,7 @@ on `clang` binary, which makes clang a required dependency (search for Building clang from sources takes time and resources and it can be avoided: - if you are not interested in launching unit-tests for the translator after build, you can disable generation of test targets by passing - `-DLLVM_INCLUDE_TESTS=OFF` option. + `-DLLVM_SPIRV_INCLUDE_TESTS=OFF` option. - if you are interested in launching unit-tests, but don't want to build clang you can pass `-DSPIRV_SKIP_CLANG_BUILD` cmake option to avoid adding `clang` as dependency for `check-llvm-spirv` target. However, LIT will search for @@ -102,12 +105,13 @@ Execute the following command inside the build directory to run translator tests ``` make test ``` -This requires that the `-DLLVM_INCLUDE_TESTS=ON` and -`-DLLVM_EXTERNAL_LIT="/usr/lib/llvm-12/build/utils/lit/lit.py"` arguments were -passed to CMake during the build step. +This requires that the `-DLLVM_SPIRV_INCLUDE_TESTS=ON` argument is +passed to CMake during the build step. Additionally, +`-DLLVM_EXTERNAL_LIT="/usr/lib/llvm-12/build/utils/lit/lit.py"` is +needed when building with a pre-installed version of LLVM. The translator test suite can be disabled by passing -`-DLLVM_SPIRV_INCLUDE_TESTS=OFF` to cmake. +`-DLLVM_SPIRV_INCLUDE_TESTS=OFF` to CMake. ## Run Instructions for `llvm-spirv` diff --git a/llvm-spirv/include/LLVMSPIRVExtensions.inc b/llvm-spirv/include/LLVMSPIRVExtensions.inc index e9370fd75b97b..a2c544ebcc0cd 100644 --- a/llvm-spirv/include/LLVMSPIRVExtensions.inc +++ b/llvm-spirv/include/LLVMSPIRVExtensions.inc @@ -3,6 +3,7 @@ #error "EXT macro must be defined" #endif +EXT(SPV_EXT_shader_atomic_float_add) EXT(SPV_KHR_no_integer_wrap_decoration) EXT(SPV_KHR_float_controls) EXT(SPV_INTEL_subgroups) @@ -27,3 +28,4 @@ EXT(SPV_INTEL_fpga_buffer_location) EXT(SPV_INTEL_arbitrary_precision_fixed_point) EXT(SPV_INTEL_arbitrary_precision_floating_point) EXT(SPV_INTEL_variable_length_array) +EXT(SPV_INTEL_fp_fast_math_mode) diff --git a/llvm-spirv/lib/SPIRV/PreprocessMetadata.cpp b/llvm-spirv/lib/SPIRV/PreprocessMetadata.cpp index 160d7bd166cd4..5843afff4900e 100644 --- a/llvm-spirv/lib/SPIRV/PreprocessMetadata.cpp +++ b/llvm-spirv/lib/SPIRV/PreprocessMetadata.cpp @@ -316,6 +316,12 @@ void PreprocessMetadata::preprocessVectorComputeMetadata(Module *M, .add(SLMSize) .done(); } + if (Attrs.hasFnAttribute(kVCMetadata::VCFCEntry)) { + EM.addOp() + .add(&F) + .add(spv::ExecutionModeVectorComputeFastCompositeKernelINTEL) + .done(); + } } } diff --git a/llvm-spirv/lib/SPIRV/SPIRVLowerSPIRBlocks.cpp b/llvm-spirv/lib/SPIRV/SPIRVLowerSPIRBlocks.cpp index 7a9594b983f90..c060491e61bc7 100644 --- a/llvm-spirv/lib/SPIRV/SPIRVLowerSPIRBlocks.cpp +++ b/llvm-spirv/lib/SPIRV/SPIRVLowerSPIRBlocks.cpp @@ -209,6 +209,7 @@ class SPIRVLowerSPIRBlocks : public ModulePass { Value *CtxAlign = nullptr; getBlockInvokeFuncAndContext(CallBlkBind, &InvF, &Ctx, &CtxLen, &CtxAlign); + assert(Ctx && "Invalid context"); for (auto II = CallBlkBind->user_begin(), EE = CallBlkBind->user_end(); II != EE;) { auto BlkUser = *II++; @@ -247,6 +248,7 @@ class SPIRVLowerSPIRBlocks : public ModulePass { if (!Ctx) getBlockInvokeFuncAndContext(CallGetBlkCtx->getArgOperand(0), nullptr, &Ctx); + assert(Ctx && "Invalid context"); CallGetBlkCtx->replaceAllUsesWith(Ctx); LLVM_DEBUG(dbgs() << " [lowerGetBlockContext] " << *CallGetBlkCtx << " => " << *Ctx << "\n\n"); diff --git a/llvm-spirv/lib/SPIRV/SPIRVReader.cpp b/llvm-spirv/lib/SPIRV/SPIRVReader.cpp index 9c42dbe6bbb22..a8761aa18b700 100644 --- a/llvm-spirv/lib/SPIRV/SPIRVReader.cpp +++ b/llvm-spirv/lib/SPIRV/SPIRVReader.cpp @@ -748,16 +748,14 @@ void SPIRVToLLVM::setLLVMLoopMetadata(const LoopInstType *LM, if (LC & LoopControlDependencyInfiniteMask) Metadata.push_back(getMetadataFromName("llvm.loop.ivdep.enable")); if (LC & LoopControlDependencyLengthMask) { - if (!LoopControlParameters.empty()) { - Metadata.push_back(llvm::MDNode::get( - *Context, - getMetadataFromNameAndParameter("llvm.loop.ivdep.safelen", - LoopControlParameters[NumParam]))); - ++NumParam; - // TODO: Fix the increment/assertion logic in all of the conditions - assert(NumParam <= LoopControlParameters.size() && - "Missing loop control parameter!"); - } + Metadata.push_back(llvm::MDNode::get( + *Context, + getMetadataFromNameAndParameter("llvm.loop.ivdep.safelen", + LoopControlParameters[NumParam]))); + ++NumParam; + // TODO: Fix the increment/assertion logic in all of the conditions + assert(NumParam <= LoopControlParameters.size() && + "Missing loop control parameter!"); } // Placeholder for LoopControls added in SPIR-V 1.4 spec (see 3.23) if (LC & LoopControlMinIterationsMask) { @@ -835,6 +833,8 @@ void SPIRVToLLVM::setLLVMLoopMetadata(const LoopInstType *LM, continue; Value *AccessedPointer = GEP->getPointerOperand(); + if (auto *LI = dyn_cast(AccessedPointer)) + AccessedPointer = LI->getPointerOperand(); auto PointerSflnIt = PointerSflnMap.find(AccessedPointer); if (PointerSflnIt != PointerSflnMap.end()) { ArrayGEPMap[AccessedPointer].push_back(GEP); @@ -932,16 +932,17 @@ void SPIRVToLLVM::setLLVMLoopMetadata(const LoopInstType *LM, "Missing loop control parameter!"); } if (LC & LoopControlLoopCoalesceINTELMask) { - // If LoopCoalesce has no parameters - if (LoopControlParameters.empty()) { + // If LoopCoalesce has a parameter of '0' + if (!LoopControlParameters[NumParam]) { Metadata.push_back(llvm::MDNode::get( *Context, getMetadataFromName("llvm.loop.coalesce.enable"))); } else { Metadata.push_back(llvm::MDNode::get( *Context, getMetadataFromNameAndParameter("llvm.loop.coalesce.count", - LoopControlParameters[NumParam++]))); + LoopControlParameters[NumParam]))); } + ++NumParam; assert(NumParam <= LoopControlParameters.size() && "Missing loop control parameter!"); } @@ -961,6 +962,8 @@ void SPIRVToLLVM::setLLVMLoopMetadata(const LoopInstType *LM, assert(NumParam <= LoopControlParameters.size() && "Missing loop control parameter!"); } + if (LC & LoopControlNoFusionINTELMask) + Metadata.push_back(getMetadataFromName("llvm.loop.fusion.disable")); llvm::MDNode *Node = llvm::MDNode::get(*Context, Metadata); // Set the first operand to refer itself @@ -1124,6 +1127,10 @@ static void applyFPFastMathModeDecorations(const SPIRVValue *BV, FMF.setNoSignedZeros(); if (V & FPFastMathModeAllowRecipMask) FMF.setAllowReciprocal(); + if (V & FPFastMathModeAllowContractINTELMask) + FMF.setAllowContract(); + if (V & FPFastMathModeAllowReassocINTELMask) + FMF.setAllowReassoc(); if (V & FPFastMathModeFastMask) FMF.setFast(); Inst->setFastMathFlags(FMF); @@ -2882,7 +2889,16 @@ Function *SPIRVToLLVM::transFunction(SPIRVFunction *BF) { BA->foreachAttr([&](SPIRVFuncParamAttrKind Kind) { if (Kind == FunctionParameterAttributeNoWrite) return; - F->addAttribute(I->getArgNo() + 1, SPIRSPIRVFuncParamAttrMap::rmap(Kind)); + Attribute::AttrKind LLVMKind = SPIRSPIRVFuncParamAttrMap::rmap(Kind); + Type *AttrTy = nullptr; + if (LLVMKind == Attribute::AttrKind::ByVal) + AttrTy = cast(I->getType())->getElementType(); + else if (LLVMKind == Attribute::AttrKind::StructRet) + AttrTy = I->getType(); + // Make sure to use a correct constructor for a typed/typeless attribute + auto A = AttrTy ? Attribute::get(*Context, LLVMKind, AttrTy) + : Attribute::get(*Context, LLVMKind); + I->addAttr(A); }); SPIRVWord MaxOffset = 0; @@ -4034,6 +4050,9 @@ bool SPIRVToLLVM::transVectorComputeMetadata(SPIRVFunction *BF) { F->addFnAttr(kVCMetadata::VCSIMTCall, std::to_string(SIMTMode)); if (BF->hasDecorate(DecorationVectorComputeCallableFunctionINTEL)) F->addFnAttr(kVCMetadata::VCCallable); + if (isKernel(BF) && + BF->getExecutionMode(ExecutionModeVectorComputeFastCompositeKernelINTEL)) + F->addFnAttr(kVCMetadata::VCFCEntry); auto SEVAttr = Attribute::get(*Context, kVCMetadata::VCSingleElementVector); if (BF->hasDecorate(DecorationSingleElementVectorINTEL)) diff --git a/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp b/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp index debf43f45c177..cd9afc301f149 100644 --- a/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp +++ b/llvm-spirv/lib/SPIRV/SPIRVWriter.cpp @@ -1077,6 +1077,8 @@ LLVMToSPIRV::getLoopControl(const BranchInst *Branch, } else if (S == "llvm.loop.coalesce.enable") { BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls); BM->addCapability(CapabilityFPGALoopControlsINTEL); + ParametersToSort.emplace_back(spv::LoopControlLoopCoalesceINTELMask, + 0); LoopControl |= spv::LoopControlLoopCoalesceINTELMask; } else if (S == "llvm.loop.coalesce.count") { BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls); @@ -1099,6 +1101,10 @@ LLVMToSPIRV::getLoopControl(const BranchInst *Branch, ParametersToSort.emplace_back( spv::LoopControlSpeculatedIterationsINTELMask, I); LoopControl |= spv::LoopControlSpeculatedIterationsINTELMask; + } else if (S == "llvm.loop.fusion.disable") { + BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls); + BM->addCapability(CapabilityFPGALoopControlsINTEL); + LoopControl |= spv::LoopControlNoFusionINTELMask; } } } @@ -1133,6 +1139,32 @@ LLVMToSPIRV::getLoopControl(const BranchInst *Branch, return static_cast(LoopControl); } +static int transAtomicOrdering(llvm::AtomicOrdering Ordering) { + return OCLMemOrderMap::map( + static_cast(llvm::toCABI(Ordering))); +} + +SPIRVValue *LLVMToSPIRV::transAtomicStore(StoreInst *ST, SPIRVBasicBlock *BB) { + std::vector Ops{ST->getPointerOperand(), + getUInt32(M, spv::ScopeDevice), + getUInt32(M, transAtomicOrdering(ST->getOrdering())), + ST->getValueOperand()}; + std::vector SPIRVOps = transValue(Ops, BB); + + return mapValue(ST, BM->addInstTemplate(OpAtomicStore, BM->getIds(SPIRVOps), + BB, nullptr)); +} + +SPIRVValue *LLVMToSPIRV::transAtomicLoad(LoadInst *LD, SPIRVBasicBlock *BB) { + std::vector Ops{ + LD->getPointerOperand(), getUInt32(M, spv::ScopeDevice), + getUInt32(M, transAtomicOrdering(LD->getOrdering()))}; + std::vector SPIRVOps = transValue(Ops, BB); + + return mapValue(LD, BM->addInstTemplate(OpAtomicLoad, BM->getIds(SPIRVOps), + BB, transType(LD->getType()))); +} + /// An instruction may use an instruction from another BB which has not been /// translated. SPIRVForward should be created as place holder for these /// instructions and replaced later by the real instructions. @@ -1277,6 +1309,9 @@ SPIRVValue *LLVMToSPIRV::transValueWithoutDecoration(Value *V, return mapValue(V, BM->addForward(transType(V->getType()))); if (StoreInst *ST = dyn_cast(V)) { + if (ST->isAtomic()) + return transAtomicStore(ST, BB); + std::vector MemoryAccess(1, 0); if (ST->isVolatile()) MemoryAccess[0] |= MemoryAccessVolatileMask; @@ -1297,6 +1332,9 @@ SPIRVValue *LLVMToSPIRV::transValueWithoutDecoration(Value *V, } if (LoadInst *LD = dyn_cast(V)) { + if (LD->isAtomic()) + return transAtomicLoad(LD, BB); + std::vector MemoryAccess(1, 0); if (LD->isVolatile()) MemoryAccess[0] |= MemoryAccessVolatileMask; @@ -1478,14 +1516,19 @@ SPIRVValue *LLVMToSPIRV::transValueWithoutDecoration(Value *V, std::vector Indices; for (unsigned I = 0, E = GEP->getNumIndices(); I != E; ++I) Indices.push_back(transValue(GEP->getOperand(I + 1), BB)); - auto *TransPointerOperand = transValue(GEP->getPointerOperand(), BB); + auto *PointerOperand = GEP->getPointerOperand(); + auto *TransPointerOperand = transValue(PointerOperand, BB); // Certain array-related optimization hints can be expressed via // LLVM metadata. For the purpose of linking this metadata with // the accessed array variables, our GEP may have been marked into // a so-called index group, an MDNode by itself. if (MDNode *IndexGroup = GEP->getMetadata("llvm.index.group")) { - SPIRVId AccessedArrayId = TransPointerOperand->getId(); + SPIRVValue *ActualMemoryPtr = TransPointerOperand; + if (auto *Load = dyn_cast(PointerOperand)) { + ActualMemoryPtr = transValue(Load->getPointerOperand(), BB); + } + SPIRVId AccessedArrayId = ActualMemoryPtr->getId(); unsigned NumOperands = IndexGroup->getNumOperands(); // When we're working with embedded loops, it's natural that // the outer loop's hints apply to all code contained within. @@ -1663,6 +1706,17 @@ bool LLVMToSPIRV::transDecoration(Value *V, SPIRVValue *BV) { M |= FPFastMathModeNSZMask; if (FMF.allowReciprocal()) M |= FPFastMathModeAllowRecipMask; + if (BM->isAllowedToUseExtension( + ExtensionID::SPV_INTEL_fp_fast_math_mode)) { + if (FMF.allowContract()) { + M |= FPFastMathModeAllowContractINTELMask; + BM->addCapability(CapabilityFPFastMathModeINTEL); + } + if (FMF.allowReassoc()) { + M |= FPFastMathModeAllowReassocINTELMask; + BM->addCapability(CapabilityFPFastMathModeINTEL); + } + } } if (M != 0) BV->setFPFastMathMode(M); @@ -3004,6 +3058,10 @@ SPIRVValue *LLVMToSPIRV::transBuiltinToConstant(StringRef DemangledName, Op OC = getSPIRVFuncOC(DemangledName); if (!isSpecConstantOpCode(OC)) return nullptr; + if (OC == spv::OpSpecConstantComposite) { + return BM->addSpecConstantComposite(transType(CI->getType()), + transValue(getArguments(CI), nullptr)); + } Value *V = CI->getArgOperand(1); Type *Ty = V->getType(); assert(Ty == CI->getType() && "Type mismatch!"); @@ -3174,6 +3232,11 @@ bool LLVMToSPIRV::transExecutionMode() { BF->addExecutionMode(BM->add(new SPIRVExecutionMode( BF, static_cast(EMode), TargetWidth))); } break; + case spv::ExecutionModeVectorComputeFastCompositeKernelINTEL: { + if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_vector_compute)) + BF->addExecutionMode(BM->add( + new SPIRVExecutionMode(BF, static_cast(EMode)))); + } break; default: llvm_unreachable("invalid execution mode"); } diff --git a/llvm-spirv/lib/SPIRV/SPIRVWriter.h b/llvm-spirv/lib/SPIRV/SPIRVWriter.h index c8f48a04638e4..f4496426a670a 100644 --- a/llvm-spirv/lib/SPIRV/SPIRVWriter.h +++ b/llvm-spirv/lib/SPIRV/SPIRVWriter.h @@ -173,6 +173,9 @@ class LLVMToSPIRV : public ModulePass { SPIRVInstruction *transLifetimeIntrinsicInst(Op OC, IntrinsicInst *Intrinsic, SPIRVBasicBlock *BB); + SPIRVValue *transAtomicStore(StoreInst *ST, SPIRVBasicBlock *BB); + SPIRVValue *transAtomicLoad(LoadInst *LD, SPIRVBasicBlock *BB); + void dumpUsers(Value *V); template diff --git a/llvm-spirv/lib/SPIRV/VectorComputeUtil.h b/llvm-spirv/lib/SPIRV/VectorComputeUtil.h index 4ab23ee01c0b2..efe280f04c2d4 100755 --- a/llvm-spirv/lib/SPIRV/VectorComputeUtil.h +++ b/llvm-spirv/lib/SPIRV/VectorComputeUtil.h @@ -112,6 +112,7 @@ const static char VCArgumentKind[] = "VCArgumentKind"; const static char VCArgumentDesc[] = "VCArgumentDesc"; const static char VCCallable[] = "VCCallable"; const static char VCSingleElementVector[] = "VCSingleElementVector"; +const static char VCFCEntry[] = "VCFCEntry"; } // namespace kVCMetadata namespace kVCType { diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h index baf06a5b6b2e8..f13299c3726f7 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h @@ -252,6 +252,8 @@ template <> inline void SPIRVMap::init() { {CapabilityFloatingPointModeINTEL}); ADD_VEC_INIT(ExecutionModeSharedLocalMemorySizeINTEL, {CapabilityVectorComputeINTEL}); + ADD_VEC_INIT(ExecutionModeVectorComputeFastCompositeKernelINTEL, + {CapabilityVectorComputeINTEL}); } template <> inline void SPIRVMap::init() { diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h index b4f333905c85f..1b445704a3e8b 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h @@ -2721,15 +2721,32 @@ _SPIRV_OP(PowN, true, 10) class SPIRVAtomicInstBase : public SPIRVInstTemplateBase { public: + llvm::Optional getRequiredExtension() const override { + if (getOpCode() == OpAtomicFAddEXT) + return ExtensionID::SPV_EXT_shader_atomic_float_add; + return {}; + } + SPIRVCapVec getRequiredCapability() const override { SPIRVCapVec CapVec; - // Most of atomic instructions do not require any capabilities - // ... unless they operate on 64-bit integers. - if (hasType() && getType()->isTypeInt(64)) { + if (!hasType()) + return CapVec; + + // Most atomic instructionsrequire a specific capability when + // operating on 64-bit integers. + if (getType()->isTypeInt(64)) { // In SPIRV 1.2 spec only 2 atomic instructions have no result type: // 1. OpAtomicStore - need to check type of the Value operand // 2. OpAtomicFlagClear - doesn't require Int64Atomics capability. CapVec.push_back(CapabilityInt64Atomics); + } else if (getOpCode() == OpAtomicFAddEXT) { + if (getType()->isTypeFloat(32)) + CapVec.push_back(CapabilityAtomicFloat32AddEXT); + else if (getType()->isTypeFloat(64)) + CapVec.push_back(CapabilityAtomicFloat64AddEXT); + else + llvm_unreachable( + "AtomicFAddEXT can only be generated for f32 or f64 types"); } // Per the spec OpAtomicCompareExchangeWeak, OpAtomicFlagTestAndSet and // OpAtomicFlagClear instructions require kernel capability. But this @@ -2737,14 +2754,18 @@ class SPIRVAtomicInstBase : public SPIRVInstTemplateBase { return CapVec; } - // Overriding the following method only because of OpAtomicStore. - // We have to declare Int64Atomics capability if the Value operand is int64. + // Overriding the following method because of particular OpAtomic* + // instructions. We may have to declare additional capabilities, + // e.g. based on operand types. void setOpWords(const std::vector &TheOps) override { SPIRVInstTemplateBase::setOpWords(TheOps); static const unsigned ValueOperandIndex = 3; if (getOpCode() == OpAtomicStore && getOperand(ValueOperandIndex)->getType()->isTypeInt(64)) Module->addCapability(CapabilityInt64Atomics); + if (getOpCode() == OpAtomicFAddEXT) + for (auto RC : getRequiredCapability()) + Module->addCapability(RC); } }; @@ -2769,6 +2790,7 @@ _SPIRV_OP(AtomicSMax, true, 7) _SPIRV_OP(AtomicAnd, true, 7) _SPIRV_OP(AtomicOr, true, 7) _SPIRV_OP(AtomicXor, true, 7) +_SPIRV_OP(AtomicFAddEXT, true, 7) _SPIRV_OP(MemoryBarrier, false, 3) #undef _SPIRV_OP diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp index 33fc3c698570b..cea47e925f3cd 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp @@ -259,6 +259,9 @@ class SPIRVModuleImpl : public SPIRVModule { SPIRVBasicBlock *) override; SPIRVValue *addCompositeConstant(SPIRVType *, const std::vector &) override; + SPIRVValue * + addSpecConstantComposite(SPIRVType *Ty, + const std::vector &Elements) override; SPIRVValue *addConstFunctionPointerINTEL(SPIRVType *Ty, SPIRVFunction *F) override; SPIRVValue *addConstant(SPIRVValue *) override; @@ -1069,6 +1072,12 @@ SPIRVValue *SPIRVModuleImpl::addCompositeConstant( return addConstant(new SPIRVConstantComposite(this, Ty, getId(), Elements)); } +SPIRVValue *SPIRVModuleImpl::addSpecConstantComposite( + SPIRVType *Ty, const std::vector &Elements) { + return addConstant( + new SPIRVSpecConstantComposite(this, Ty, getId(), Elements)); +} + SPIRVValue *SPIRVModuleImpl::addConstFunctionPointerINTEL(SPIRVType *Ty, SPIRVFunction *F) { return addConstant(new SPIRVConstFunctionPointerINTEL(getId(), Ty, F, this)); diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h index 1903c7992ea12..27e5f70ce9804 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h @@ -252,6 +252,9 @@ class SPIRVModule { // Constants creation functions virtual SPIRVValue * addCompositeConstant(SPIRVType *, const std::vector &) = 0; + virtual SPIRVValue * + addSpecConstantComposite(SPIRVType *Ty, + const std::vector &Elements) = 0; virtual SPIRVValue *addConstFunctionPointerINTEL(SPIRVType *Ty, SPIRVFunction *F) = 0; virtual SPIRVValue *addConstant(SPIRVValue *) = 0; diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h index 2c5b0f2cc4d5b..bb2ba3fb9c0d0 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h @@ -454,6 +454,8 @@ template <> inline void SPIRVMap::init() { "PhysicalStorageBufferAddresses"); add(CapabilityPhysicalStorageBufferAddressesEXT, "PhysicalStorageBufferAddressesEXT"); + add(CapabilityAtomicFloat32AddEXT, "AtomicFloat32AddEXT"); + add(CapabilityAtomicFloat64AddEXT, "AtomicFloat64AddEXT"); add(CapabilityComputeDerivativeGroupLinearNV, "ComputeDerivativeGroupLinearNV"); add(CapabilityCooperativeMatrixNV, "CooperativeMatrixNV"); @@ -488,6 +490,7 @@ template <> inline void SPIRVMap::init() { add(CapabilityVariableLengthArrayINTEL, "VariableLengthArrayINTEL"); add(CapabilityFunctionFloatControlINTEL, "FunctionFloatControlINTEL"); add(CapabilityFPGAMemoryAttributesINTEL, "FPGAMemoryAttributesINTEL"); + add(CapabilityFPFastMathModeINTEL, "FPFastMathModeINTEL"); add(CapabilityArbitraryPrecisionIntegersINTEL, "ArbitraryPrecisionIntegersINTEL"); add(CapabilityArbitraryPrecisionFloatingPointINTEL, diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h index a61165e5fdde4..e98338d2aa431 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h @@ -528,4 +528,5 @@ _SPIRV_OP(CrossWorkgroupCastToPtrINTEL, 5938) _SPIRV_OP(ReadPipeBlockingINTEL, 5946) _SPIRV_OP(WritePipeBlockingINTEL, 5947) _SPIRV_OP(FPGARegINTEL, 5949) +_SPIRV_OP(AtomicFAddEXT, 6035) _SPIRV_OP(TypeBufferSurfaceINTEL, 6086) diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVValue.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVValue.h index 15134f9dbcd20..a0885a93a2347 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVValue.h +++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVValue.h @@ -290,13 +290,12 @@ template class SPIRVConstantCompositeBase : public SPIRVValue { // Complete constructor for composite constant SPIRVConstantCompositeBase(SPIRVModule *M, SPIRVType *TheType, SPIRVId TheId, const std::vector TheElements) - : SPIRVValue(M, TheElements.size() + 3, OpConstantComposite, TheType, - TheId) { + : SPIRVValue(M, TheElements.size() + 3, OC, TheType, TheId) { Elements = getIds(TheElements); validate(); } // Incomplete constructor - SPIRVConstantCompositeBase() : SPIRVValue(OpConstantComposite) {} + SPIRVConstantCompositeBase() : SPIRVValue(OC) {} std::vector getElements() const { return getValues(Elements); } std::vector getNonLiteralOperands() const override { std::vector Elements = getElements(); diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp b/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp index 1b82ea0f81671..ed3980e6eb9f2 100644 --- a/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp +++ b/llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp @@ -172,6 +172,7 @@ enum ExecutionMode { ExecutionModeMaxWorkDimINTEL = 5894, ExecutionModeNoGlobalOffsetINTEL = 5895, ExecutionModeNumSIMDWorkitemsINTEL = 5896, + ExecutionModeVectorComputeFastCompositeKernelINTEL = 8088, ExecutionModeMax = 0x7fffffff, }; @@ -376,6 +377,8 @@ enum FPFastMathModeMask { FPFastMathModeNotInfMask = 0x00000002, FPFastMathModeNSZMask = 0x00000004, FPFastMathModeAllowRecipMask = 0x00000008, + FPFastMathModeAllowContractINTELMask = 0x00010000, + FPFastMathModeAllowReassocINTELMask = 0x00020000, FPFastMathModeFastMask = 0x00000010, }; @@ -677,6 +680,7 @@ enum LoopControlMask { LoopControlLoopCoalesceINTELMask = 0x100000, LoopControlMaxInterleavingINTELMask = 0x200000, LoopControlSpeculatedIterationsINTELMask = 0x400000, + LoopControlNoFusionINTELMask = 0x800000, }; enum FunctionControlShift { @@ -973,6 +977,7 @@ enum Capability { CapabilityVariableLengthArrayINTEL = 5817, CapabilityFunctionFloatControlINTEL = 5821, CapabilityFPGAMemoryAttributesINTEL = 5824, + CapabilityFPFastMathModeINTEL = 5837, CapabilityArbitraryPrecisionIntegersINTEL = 5844, CapabilityArbitraryPrecisionFloatingPointINTEL = 5845, CapabilityUnstructuredLoopControlsINTEL = 5886, @@ -986,6 +991,8 @@ enum Capability { CapabilityUSMStorageClassesINTEL = 5935, CapabilityFPGAMemoryAccessesINTEL = 5898, CapabilityIOPipeINTEL = 5943, + CapabilityAtomicFloat32AddEXT = 6033, + CapabilityAtomicFloat64AddEXT = 6034, CapabilityMax = 0x7fffffff, }; @@ -1584,6 +1591,7 @@ enum Op { OpReadPipeBlockingINTEL = 5946, OpWritePipeBlockingINTEL = 5947, OpFPGARegINTEL = 5949, + OpAtomicFAddEXT = 6035, OpTypeBufferSurfaceINTEL = 6086, OpMax = 0x7fffffff, }; @@ -1984,6 +1992,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case OpSubgroupImageMediaBlockWriteINTEL: *hasResult = false; *hasResultType = false; break; case OpUCountLeadingZerosINTEL: *hasResult = true; *hasResultType = true; break; case OpUCountTrailingZerosINTEL: *hasResult = true; *hasResultType = true; break; + case OpAtomicFAddEXT: *hasResult = true; *hasResultType = true; break; case OpAbsISubINTEL: *hasResult = true; *hasResultType = true; break; case OpAbsUSubINTEL: *hasResult = true; *hasResultType = true; break; case OpIAddSatINTEL: *hasResult = true; *hasResultType = true; break; diff --git a/llvm-spirv/test/AtomicFAddExt.ll b/llvm-spirv/test/AtomicFAddExt.ll new file mode 100644 index 0000000000000..58e9f57605399 --- /dev/null +++ b/llvm-spirv/test/AtomicFAddExt.ll @@ -0,0 +1,119 @@ +; RUN: llvm-as %s -o %t.bc +; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_EXT_shader_atomic_float_add -o %t.spv +; RUN: llvm-spirv -to-text %t.spv -o %t.spt +; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV + +; RUN: llvm-spirv -r %t.spv -o %t.rev.bc +; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefix=CHECK-LLVM + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64" +target triple = "spir64-unknown-unknown-sycldevice" + +%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" = type { %"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" } +%"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" = type { [1 x i64] } +%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" = type { %"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" } + +$_ZTSZZ3addIfEvvENKUlRN2cl4sycl7handlerEE19_14clES3_EUlNS1_4itemILi1ELb1EEEE23_37 = comdat any + +$_ZTSZZ3addIdEvvENKUlRN2cl4sycl7handlerEE19_14clES3_EUlNS1_4itemILi1ELb1EEEE23_37 = comdat any + +@__spirv_BuiltInGlobalInvocationId = external dso_local local_unnamed_addr addrspace(1) constant <3 x i64>, align 32 + +; CHECK-SPIRV: Capability AtomicFloat32AddEXT +; CHECK-SPIRV: Capability AtomicFloat64AddEXT +; CHECK-SPIRV: Extension "SPV_EXT_shader_atomic_float_add" +; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_32:[0-9]+]] 32 +; CHECK-SPIRV: TypeFloat [[TYPE_FLOAT_64:[0-9]+]] 64 + +; Function Attrs: convergent norecurse mustprogress +define weak_odr dso_local spir_kernel void @_ZTSZZ3addIfEvvENKUlRN2cl4sycl7handlerEE19_14clES3_EUlNS1_4itemILi1ELb1EEEE23_37(float addrspace(1)* %_arg_, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_1, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_2, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_3, float addrspace(1)* %_arg_4, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_6, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_7, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_8) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !4 { +entry: + %0 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_3, i64 0, i32 0, i32 0, i64 0 + %1 = load i64, i64* %0, align 8 + %add.ptr.i29 = getelementptr inbounds float, float addrspace(1)* %_arg_, i64 %1 + %2 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_8, i64 0, i32 0, i32 0, i64 0 + %3 = load i64, i64* %2, align 8 + %add.ptr.i = getelementptr inbounds float, float addrspace(1)* %_arg_4, i64 %3 + %4 = load <3 x i64>, <3 x i64> addrspace(4)* addrspacecast (<3 x i64> addrspace(1)* @__spirv_BuiltInGlobalInvocationId to <3 x i64> addrspace(4)*), align 32, !noalias !5 + %5 = extractelement <3 x i64> %4, i64 0 + ; CHECK-SPIRV: 7 AtomicFAddEXT [[TYPE_FLOAT_32]] + ; CHECK-LLVM: call spir_func float @[[FLOAT_FUNC_NAME:_Z21__spirv_AtomicFAddEXT[[:alnum:]]+]]({{.*}}) + %call3.i.i.i.i = tail call spir_func float @_Z21__spirv_AtomicFAddEXTPU3AS1fN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEf(float addrspace(1)* %add.ptr.i29, i32 1, i32 896, float 1.000000e+00) #2 + %add.i.i = fadd float %call3.i.i.i.i, 1.000000e+00 + %sext.i = shl i64 %5, 32 + %conv5.i = ashr exact i64 %sext.i, 32 + %ptridx.i.i = getelementptr inbounds float, float addrspace(1)* %add.ptr.i, i64 %conv5.i + %ptridx.ascast.i.i = addrspacecast float addrspace(1)* %ptridx.i.i to float addrspace(4)* + store float %add.i.i, float addrspace(4)* %ptridx.ascast.i.i, align 4, !tbaa !14 + ret void +} + +; Function Attrs: convergent +; CHECK-LLVM: declare {{.*}}spir_func float @[[FLOAT_FUNC_NAME]](float addrspace(1)*, i32, i32, float) +declare dso_local spir_func float @_Z21__spirv_AtomicFAddEXTPU3AS1fN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEf(float addrspace(1)*, i32, i32, float) local_unnamed_addr #1 + +; Function Attrs: convergent norecurse mustprogress +define weak_odr dso_local spir_kernel void @_ZTSZZ3addIdEvvENKUlRN2cl4sycl7handlerEE19_14clES3_EUlNS1_4itemILi1ELb1EEEE23_37(double addrspace(1)* %_arg_, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_1, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_2, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_3, double addrspace(1)* %_arg_4, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_6, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_7, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_8) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !4 { +entry: + %0 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_3, i64 0, i32 0, i32 0, i64 0 + %1 = load i64, i64* %0, align 8 + %add.ptr.i29 = getelementptr inbounds double, double addrspace(1)* %_arg_, i64 %1 + %2 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_8, i64 0, i32 0, i32 0, i64 0 + %3 = load i64, i64* %2, align 8 + %add.ptr.i = getelementptr inbounds double, double addrspace(1)* %_arg_4, i64 %3 + %4 = load <3 x i64>, <3 x i64> addrspace(4)* addrspacecast (<3 x i64> addrspace(1)* @__spirv_BuiltInGlobalInvocationId to <3 x i64> addrspace(4)*), align 32, !noalias !18 + %5 = extractelement <3 x i64> %4, i64 0 + ; CHECK-SPIRV: 7 AtomicFAddEXT [[TYPE_FLOAT_64]] + ; CHECK-LLVM: call spir_func double @[[DOUBLE_FUNC_NAME:_Z21__spirv_AtomicFAddEXT[[:alnum:]]+]]({{.*}}) + %call3.i.i.i.i = tail call spir_func double @_Z21__spirv_AtomicFAddEXTPU3AS1dN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEd(double addrspace(1)* %add.ptr.i29, i32 1, i32 896, double 1.000000e+00) #2 + %add.i.i = fadd double %call3.i.i.i.i, 1.000000e+00 + %sext.i = shl i64 %5, 32 + %conv5.i = ashr exact i64 %sext.i, 32 + %ptridx.i.i = getelementptr inbounds double, double addrspace(1)* %add.ptr.i, i64 %conv5.i + %ptridx.ascast.i.i = addrspacecast double addrspace(1)* %ptridx.i.i to double addrspace(4)* + store double %add.i.i, double addrspace(4)* %ptridx.ascast.i.i, align 8, !tbaa !27 + ret void +} + +; Function Attrs: convergent +; CHECK-LLVM: declare {{.*}}spir_func double @[[DOUBLE_FUNC_NAME]](double addrspace(1)*, i32, i32, double) +declare dso_local spir_func double @_Z21__spirv_AtomicFAddEXTPU3AS1dN5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagEd(double addrspace(1)*, i32, i32, double) local_unnamed_addr #1 + +attributes #0 = { convergent norecurse mustprogress "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "sycl-module-id"="fadd.cpp" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { convergent "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { convergent nounwind } + +!llvm.module.flags = !{!0} +!opencl.spir.version = !{!1} +!spirv.Source = !{!2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, i32 2} +!2 = !{i32 4, i32 100000} +!3 = !{!"clang version 12.0.0"} +!4 = !{i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1} +!5 = !{!6, !8, !10, !12} +!6 = distinct !{!6, !7, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv: %agg.result"} +!7 = distinct !{!7, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv"} +!8 = distinct !{!8, !9, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v: %agg.result"} +!9 = distinct !{!9, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v"} +!10 = distinct !{!10, !11, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv: %agg.result"} +!11 = distinct !{!11, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv"} +!12 = distinct !{!12, !13, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE: %agg.result"} +!13 = distinct !{!13, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE"} +!14 = !{!15, !15, i64 0} +!15 = !{!"float", !16, i64 0} +!16 = !{!"omnipotent char", !17, i64 0} +!17 = !{!"Simple C++ TBAA"} +!18 = !{!19, !21, !23, !25} +!19 = distinct !{!19, !20, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv: %agg.result"} +!20 = distinct !{!20, !"_ZN7__spirv29InitSizesSTGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEE8initSizeEv"} +!21 = distinct !{!21, !22, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v: %agg.result"} +!22 = distinct !{!22, !"_ZN7__spirvL22initGlobalInvocationIdILi1EN2cl4sycl2idILi1EEEEET0_v"} +!23 = distinct !{!23, !24, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv: %agg.result"} +!24 = distinct !{!24, !"_ZN2cl4sycl6detail7Builder7getItemILi1ELb1EEENSt9enable_ifIXT0_EKNS0_4itemIXT_EXT0_EEEE4typeEv"} +!25 = distinct !{!25, !26, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE: %agg.result"} +!26 = distinct !{!26, !"_ZN2cl4sycl6detail7Builder10getElementILi1ELb1EEEDTcl7getItemIXT_EXT0_EEEEPNS0_4itemIXT_EXT0_EEE"} +!27 = !{!28, !28, i64 0} +!28 = !{!"double", !16, i64 0} diff --git a/llvm-spirv/test/DebugInfo/Generic/2010-10-01-crash.ll b/llvm-spirv/test/DebugInfo/Generic/2010-10-01-crash.ll index d6203e39f2c4c..ce69880c79099 100644 --- a/llvm-spirv/test/DebugInfo/Generic/2010-10-01-crash.ll +++ b/llvm-spirv/test/DebugInfo/Generic/2010-10-01-crash.ll @@ -7,7 +7,7 @@ target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64" target triple = "spir64-unknown-unknown" -define void @CGRectStandardize(i32* sret %agg.result, i32* byval %rect) nounwind ssp !dbg !0 { +define void @CGRectStandardize(i32* sret(i32*) %agg.result, i32* byval(i32) %rect) nounwind ssp !dbg !0 { entry: call void @llvm.dbg.declare(metadata i32* %rect, metadata !23, metadata !DIExpression()), !dbg !24 ret void diff --git a/llvm-spirv/test/DebugInfo/UnknownBaseType.ll b/llvm-spirv/test/DebugInfo/UnknownBaseType.ll index 116c58ea6fa56..f3d6bb5e2ed40 100644 --- a/llvm-spirv/test/DebugInfo/UnknownBaseType.ll +++ b/llvm-spirv/test/DebugInfo/UnknownBaseType.ll @@ -17,7 +17,7 @@ target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:2 target triple = "spir-unknown-unknown" ; Function Attrs: convergent nounwind -define spir_func void @foo({ float, float }* byval align 4 %f) #0 !dbg !7 { +define spir_func void @foo({ float, float }* byval({ float, float }) align 4 %f) #0 !dbg !7 { entry: call void @llvm.dbg.declare(metadata { float, float }* %f, metadata !13, metadata !DIExpression()), !dbg !14 ret void, !dbg !14 diff --git a/llvm-spirv/test/DebugInfo/X86/dbg-byval-parameter.ll b/llvm-spirv/test/DebugInfo/X86/dbg-byval-parameter.ll index 002043006e600..e7989ac3dfa86 100644 --- a/llvm-spirv/test/DebugInfo/X86/dbg-byval-parameter.ll +++ b/llvm-spirv/test/DebugInfo/X86/dbg-byval-parameter.ll @@ -11,7 +11,7 @@ target triple = "spir64-unknown-unknown" %struct.Pt = type { double, double } %struct.Rect = type { %struct.Pt, %struct.Pt } -define double @foo(%struct.Rect* byval %my_r0) nounwind ssp !dbg !1 { +define double @foo(%struct.Rect* byval(%struct.Rect) %my_r0) nounwind ssp !dbg !1 { entry: %retval = alloca double ; [#uses=2] %0 = alloca double ; [#uses=2] diff --git a/llvm-spirv/test/DebugInfo/X86/dbg-declare-arg.ll b/llvm-spirv/test/DebugInfo/X86/dbg-declare-arg.ll index 43a172d7b06e0..981fd752c2919 100644 --- a/llvm-spirv/test/DebugInfo/X86/dbg-declare-arg.ll +++ b/llvm-spirv/test/DebugInfo/X86/dbg-declare-arg.ll @@ -29,7 +29,7 @@ target triple = "spir64-unknown-unknown" %class.A = type { i32, i32, i32, i32 } -define void @_Z3fooi(%class.A* sret %agg.result, i32 %i) ssp !dbg !19 { +define void @_Z3fooi(%class.A* sret(%class.A) %agg.result, i32 %i) ssp !dbg !19 { entry: %i.addr = alloca i32, align 4 %j = alloca i32, align 4 diff --git a/llvm-spirv/test/DebugInfo/X86/double-declare.ll b/llvm-spirv/test/DebugInfo/X86/double-declare.ll index 4bfde0045ef90..75cc05da9b407 100644 --- a/llvm-spirv/test/DebugInfo/X86/double-declare.ll +++ b/llvm-spirv/test/DebugInfo/X86/double-declare.ll @@ -15,7 +15,7 @@ target triple = "spir64-unknown-unknown" declare void @llvm.dbg.declare(metadata, metadata, metadata) -define void @f(i32* byval %p, i1 %c) !dbg !5 { +define void @f(i32* byval(i32) %p, i1 %c) !dbg !5 { br i1 %c, label %x, label %y x: diff --git a/llvm-spirv/test/EnqueueEmptyKernel.ll b/llvm-spirv/test/EnqueueEmptyKernel.ll index 432ac34e1a864..30dc8da714785 100644 --- a/llvm-spirv/test/EnqueueEmptyKernel.ll +++ b/llvm-spirv/test/EnqueueEmptyKernel.ll @@ -38,7 +38,7 @@ define spir_kernel void @test_enqueue_empty() #0 !kernel_arg_addr_space !0 !kern entry: %tmp = alloca %struct.ndrange_t, align 8 %call = call spir_func %opencl.queue_t* @_Z17get_default_queuev() #4 - call spir_func void @_Z10ndrange_1Dm(%struct.ndrange_t* sret %tmp, i64 1) #4 + call spir_func void @_Z10ndrange_1Dm(%struct.ndrange_t* sret(%struct.ndrange_t*) %tmp, i64 1) #4 %0 = call i32 @__enqueue_kernel_basic_events(%opencl.queue_t* %call, i32 1, %struct.ndrange_t* %tmp, i32 0, %opencl.clk_event_t* addrspace(4)* null, %opencl.clk_event_t* addrspace(4)* null, i8 addrspace(4)* addrspacecast (i8* bitcast (void (i8 addrspace(4)*)* @__test_enqueue_empty_block_invoke_kernel to i8*) to i8 addrspace(4)*), i8 addrspace(4)* addrspacecast (i8 addrspace(1)* bitcast ({ i32, i32 } addrspace(1)* @__block_literal_global to i8 addrspace(1)*) to i8 addrspace(4)*)) ret void ; CHECK-SPIRV: Bitcast [[Int8Ptr]] [[Int8PtrBlock:[0-9]+]] [[Block]] @@ -50,7 +50,7 @@ entry: declare spir_func %opencl.queue_t* @_Z17get_default_queuev() #1 ; Function Attrs: convergent -declare spir_func void @_Z10ndrange_1Dm(%struct.ndrange_t* sret, i64) #1 +declare spir_func void @_Z10ndrange_1Dm(%struct.ndrange_t* sret(%struct.ndrange_t*), i64) #1 ; Function Attrs: convergent nounwind define internal spir_func void @__test_enqueue_empty_block_invoke(i8 addrspace(4)* %.block_descriptor) #2 { diff --git a/llvm-spirv/test/OpSpecConstantComposite.spvasm b/llvm-spirv/test/OpSpecConstantComposite.spvasm new file mode 100644 index 0000000000000..3943494c94e1d --- /dev/null +++ b/llvm-spirv/test/OpSpecConstantComposite.spvasm @@ -0,0 +1,124 @@ +; REQUIRES: spirv-as +; RUN: spirv-as --target-env spv1.0 -o %t.spv %s + +; RUN: llvm-spirv -spec-const-info %t.spv | FileCheck %s --check-prefix=CHECK-INFO +; CHECK-INFO: Number of scalar specialization constants in the module = 6 +; CHECK-INFO: Spec const id = 3, size in bytes = 4 +; CHECK-INFO: Spec const id = 6, size in bytes = 4 +; CHECK-INFO: Spec const id = 10, size in bytes = 4 +; CHECK-INFO: Spec const id = 11, size in bytes = 4 +; CHECK-INFO: Spec const id = 4, size in bytes = 4 +; CHECK-INFO: Spec const id = 7, size in bytes = 4 + +; RUN: llvm-spirv -r -o - %t.spv | llvm-dis -o %t.default.ll +; RUN: FileCheck < %t.default.ll %s --check-prefixes=CHECK-COMMON,CHECK-DEFAULT +; RUN: llvm-spirv -r -spec-const "3:i32:42 4:f32:2.71 6:i32:43 7:f32:3.14 10:i32:44 11:i32:55" -o - %t.spv | llvm-dis -o %t.spec.ll +; RUN: FileCheck < %t.spec.ll %s --check-prefixes=CHECK-COMMON,CHECK-SPEC + + +; CHECK-COMMON: %struct._ZTS3POD.POD = type { [2 x %struct._ZTS1A.A], %"class._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec" } +; CHECK-COMMON: %struct._ZTS1A.A = type { i32, float } +; CHECK-COMMON: %"class._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec" = type { <2 x i32> } + +; CHECK-DEFAULT: store %struct._ZTS3POD.POD { [2 x %struct._ZTS1A.A] [%struct._ZTS1A.A { i32 1, float 0.000000e+00 }, %struct._ZTS1A.A { i32 35, float 0.000000e+00 }], %"class._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec" { <2 x i32> } }, %struct._ZTS3POD.POD addrspace(4)* %[[#]] + +; CHECK-SPEC: store %struct._ZTS3POD.POD { [2 x %struct._ZTS1A.A] [%struct._ZTS1A.A { i32 42, float 0x4005AE1480000000 }, %struct._ZTS1A.A { i32 43, float 0x40091EB860000000 }], %"class._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec" { <2 x i32> } }, %struct._ZTS3POD.POD addrspace(4)* %3 + +; SPIR-V +; Version: 1.1 +; Generator: Khronos LLVM/SPIR-V Translator; 14 +; Bound: 57 +; Schema: 0 + OpCapability Addresses + OpCapability Kernel + OpCapability Int64 + OpCapability GenericPointer + OpCapability Int8 + %1 = OpExtInstImport "OpenCL.std" + OpMemoryModel Physical64 OpenCL + OpEntryPoint Kernel %21 "_ZTS4Test" + OpSource OpenCL_CPP 100000 + OpName %struct__ZTS3POD_POD "struct._ZTS3POD.POD" + OpName %struct__ZTS1A_A "struct._ZTS1A.A" + OpName %class__ZTSN2cl4sycl3vecIiLi2EEE_cl__sycl__vec "class._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec" + OpName %class__ZTSN2cl4sycl5rangeILi1EEE_cl__sycl__range "class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" + OpName %class__ZTSN2cl4sycl6detail5arrayILi1EEE_cl__sycl__detail__array "class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" + OpName %class__ZTSN2cl4sycl2idILi1EEE_cl__sycl__id "class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" + OpName %_arg_ "_arg_" + OpName %_arg_1 "_arg_1" + OpName %_arg_2 "_arg_2" + OpName %_arg_3 "_arg_3" + OpName %entry "entry" + OpName %ref_tmp_i "ref.tmp.i" + OpName %add_ptr_i "add.ptr.i" + OpDecorate %40 SpecId 3 + OpDecorate %41 SpecId 4 + OpDecorate %43 SpecId 6 + OpDecorate %44 SpecId 7 + OpDecorate %47 SpecId 10 + OpDecorate %48 SpecId 11 + OpDecorate %_arg_1 FuncParamAttr ByVal + OpDecorate %_arg_2 FuncParamAttr ByVal + OpDecorate %_arg_3 FuncParamAttr ByVal + OpDecorate %ref_tmp_i Alignment 8 + %uint = OpTypeInt 32 0 + %ulong = OpTypeInt 64 0 + %uchar = OpTypeInt 8 0 + %ulong_2 = OpConstant %ulong 2 + %ulong_1 = OpConstant %ulong 1 + %ulong_0 = OpConstant %ulong 0 + %uint_0 = OpConstant %uint 0 + %40 = OpSpecConstant %uint 1 + %43 = OpSpecConstant %uint 35 + %47 = OpSpecConstant %uint 45 + %48 = OpSpecConstant %uint 55 + %ulong_24 = OpConstant %ulong 24 + %void = OpTypeVoid + %float = OpTypeFloat 32 +%struct__ZTS1A_A = OpTypeStruct %uint %float +%_arr_struct__ZTS1A_A_ulong_2 = OpTypeArray %struct__ZTS1A_A %ulong_2 + %v2uint = OpTypeVector %uint 2 +%class__ZTSN2cl4sycl3vecIiLi2EEE_cl__sycl__vec = OpTypeStruct %v2uint +%struct__ZTS3POD_POD = OpTypeStruct %_arr_struct__ZTS1A_A_ulong_2 %class__ZTSN2cl4sycl3vecIiLi2EEE_cl__sycl__vec +%_ptr_CrossWorkgroup_struct__ZTS3POD_POD = OpTypePointer CrossWorkgroup %struct__ZTS3POD_POD +%_arr_ulong_ulong_1 = OpTypeArray %ulong %ulong_1 +%class__ZTSN2cl4sycl6detail5arrayILi1EEE_cl__sycl__detail__array = OpTypeStruct %_arr_ulong_ulong_1 +%class__ZTSN2cl4sycl5rangeILi1EEE_cl__sycl__range = OpTypeStruct %class__ZTSN2cl4sycl6detail5arrayILi1EEE_cl__sycl__detail__array +%_ptr_Function_class__ZTSN2cl4sycl5rangeILi1EEE_cl__sycl__range = OpTypePointer Function %class__ZTSN2cl4sycl5rangeILi1EEE_cl__sycl__range +%class__ZTSN2cl4sycl2idILi1EEE_cl__sycl__id = OpTypeStruct %class__ZTSN2cl4sycl6detail5arrayILi1EEE_cl__sycl__detail__array +%_ptr_Function_class__ZTSN2cl4sycl2idILi1EEE_cl__sycl__id = OpTypePointer Function %class__ZTSN2cl4sycl2idILi1EEE_cl__sycl__id + %20 = OpTypeFunction %void %_ptr_CrossWorkgroup_struct__ZTS3POD_POD %_ptr_Function_class__ZTSN2cl4sycl5rangeILi1EEE_cl__sycl__range %_ptr_Function_class__ZTSN2cl4sycl5rangeILi1EEE_cl__sycl__range %_ptr_Function_class__ZTSN2cl4sycl2idILi1EEE_cl__sycl__id +%_ptr_Function_struct__ZTS3POD_POD = OpTypePointer Function %struct__ZTS3POD_POD +%_ptr_Function_ulong = OpTypePointer Function %ulong +%_ptr_Function_uchar = OpTypePointer Function %uchar +%_ptr_Generic_struct__ZTS3POD_POD = OpTypePointer Generic %struct__ZTS3POD_POD +%_ptr_CrossWorkgroup_uchar = OpTypePointer CrossWorkgroup %uchar +%_ptr_Generic_uchar = OpTypePointer Generic %uchar + %41 = OpSpecConstant %float 0 + %42 = OpSpecConstantComposite %struct__ZTS1A_A %40 %41 + %44 = OpSpecConstant %float 0 + %45 = OpSpecConstantComposite %struct__ZTS1A_A %43 %44 + %46 = OpSpecConstantComposite %_arr_struct__ZTS1A_A_ulong_2 %42 %45 + %49 = OpSpecConstantComposite %v2uint %47 %48 + %50 = OpSpecConstantComposite %class__ZTSN2cl4sycl3vecIiLi2EEE_cl__sycl__vec %49 + %51 = OpSpecConstantComposite %struct__ZTS3POD_POD %46 %50 + %21 = OpFunction %void None %20 + %_arg_ = OpFunctionParameter %_ptr_CrossWorkgroup_struct__ZTS3POD_POD + %_arg_1 = OpFunctionParameter %_ptr_Function_class__ZTSN2cl4sycl5rangeILi1EEE_cl__sycl__range + %_arg_2 = OpFunctionParameter %_ptr_Function_class__ZTSN2cl4sycl5rangeILi1EEE_cl__sycl__range + %_arg_3 = OpFunctionParameter %_ptr_Function_class__ZTSN2cl4sycl2idILi1EEE_cl__sycl__id + %entry = OpLabel + %ref_tmp_i = OpVariable %_ptr_Function_struct__ZTS3POD_POD Function + %32 = OpInBoundsPtrAccessChain %_ptr_Function_ulong %_arg_3 %ulong_0 %uint_0 %uint_0 %ulong_0 + %33 = OpLoad %ulong %32 Aligned 8 + %add_ptr_i = OpInBoundsPtrAccessChain %_ptr_CrossWorkgroup_struct__ZTS3POD_POD %_arg_ %33 + %37 = OpBitcast %_ptr_Function_uchar %ref_tmp_i + OpLifetimeStart %37 24 + %39 = OpPtrCastToGeneric %_ptr_Generic_struct__ZTS3POD_POD %ref_tmp_i + OpStore %39 %51 Aligned 8 + %53 = OpBitcast %_ptr_CrossWorkgroup_uchar %add_ptr_i + %55 = OpPtrCastToGeneric %_ptr_Generic_uchar %53 + OpCopyMemorySized %55 %37 %ulong_24 Aligned 8 + OpLifetimeStop %37 24 + OpReturn + OpFunctionEnd diff --git a/llvm-spirv/test/atomic-load-store.ll b/llvm-spirv/test/atomic-load-store.ll new file mode 100644 index 0000000000000..26cbabd33871e --- /dev/null +++ b/llvm-spirv/test/atomic-load-store.ll @@ -0,0 +1,35 @@ +; RUN: llvm-as < %s -o %t.bc +; RUN: llvm-spirv %t.bc -o %t.spv +; RUN: spirv-val %t.spv +; RUN: llvm-spirv -to-text %t.spv -o - | FileCheck %s + +; CHECK-DAG: Constant [[#]] [[#Relaxed:]] 0 +; CHECK-DAG: Constant [[#]] [[#DeviceScope:]] 1 +; CHECK-DAG: Constant [[#]] [[#Acquire:]] 2 +; CHECK-DAG: Constant [[#]] [[#Release:]] 4 +; CHECK-DAG: Constant [[#]] [[#SequentiallyConsistent:]] 16 + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" +target triple = "spir64" + +; Function Attrs: nounwind +define dso_local spir_func void @test() { +entry: +; CHECK: Variable [[#]] [[#PTR:]] + %0 = alloca i32 + +; CHECK: AtomicStore [[#PTR]] [[#DeviceScope]] [[#Relaxed]] [[#]] + store atomic i32 0, i32* %0 monotonic, align 4 +; CHECK: AtomicStore [[#PTR]] [[#DeviceScope]] [[#Release]] [[#]] + store atomic i32 0, i32* %0 release, align 4 +; CHECK: AtomicStore [[#PTR]] [[#DeviceScope]] [[#SequentiallyConsistent]] [[#]] + store atomic i32 0, i32* %0 seq_cst, align 4 + +; CHECK: AtomicLoad [[#]] [[#]] [[#PTR]] [[#DeviceScope]] [[#Relaxed]] + %1 = load atomic i32, i32* %0 monotonic, align 4 +; CHECK: AtomicLoad [[#]] [[#]] [[#PTR]] [[#DeviceScope]] [[#Acquire]] + %2 = load atomic i32, i32* %0 acquire, align 4 +; CHECK: AtomicLoad [[#]] [[#]] [[#PTR]] [[#DeviceScope]] [[#SequentiallyConsistent]] + %3 = load atomic i32, i32* %0 seq_cst, align 4 + ret void +} diff --git a/llvm-spirv/test/fast-composit-entry.ll b/llvm-spirv/test/fast-composit-entry.ll new file mode 100644 index 0000000000000..46ebbdda92a56 --- /dev/null +++ b/llvm-spirv/test/fast-composit-entry.ll @@ -0,0 +1,40 @@ +; RUN: llvm-as %s -o %t.bc +; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_INTEL_vector_compute +; RUN: llvm-spirv %t.spv -o %t.spt --to-text +; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV +; RUN: llvm-spirv %t.spv -o %t.bc -r +; RUN: llvm-dis %t.bc -o %t.ll +; RUN: FileCheck < %t.ll %s --check-prefix=CHECK-LLVM + +target triple = "spir64-unknown-unknown" + + +; CHECK-SPIRV: {{[0-9]+}} EntryPoint {{[0-9]+}} [[#FOO_ID:]] "foo" +; CHECK-SPIRV: {{[0-9]+}} EntryPoint {{[0-9]+}} [[#BAR_ID:]] "bar" +; CHECK-SPIRV: 3 ExecutionMode [[#FOO_ID]] 8088 +; CHECK-SPIRV-NOT: 3 ExecutionMode [[#BAR_ID]] 8088 + +; CHECK-LLVM: define spir_kernel void @foo +; CHECK-LLVM-SAME: #[[#FOO_ATTR_ID:]] +; CHECK-LLVM: define spir_kernel void @bar +; CHECK-LLVM-SAME: #[[#BAR_ATTR_ID:]] + +; CHECK-LLVM: attributes #[[#FOO_ATTR_ID]] +; CHECK-LLVM-SAME: "VCFCEntry" +; CHECK-LLVM: attributes #[[#BAR_ATTR_ID]] +; CHECK-LLVM-NOT: "VCFCEntry" + + +define spir_kernel void @foo(<4 x i32> %a, <4 x i32> %b) #0 { +entry: + ret void +} + +define spir_kernel void @bar(<4 x i32> %a, <4 x i32> %b) #1 { +entry: + ret void +} + +attributes #0 = { noinline nounwind "VCFCEntry" "VCFloatControl"="0" "VCFunction" } +attributes #1 = { noinline nounwind "VCFloatControl"="48" "VCFunction" } + diff --git a/llvm-spirv/test/llvm-intrinsics/memcpy.align.ll b/llvm-spirv/test/llvm-intrinsics/memcpy.align.ll index a836383aa0d08..d102ba2fc9cff 100644 --- a/llvm-spirv/test/llvm-intrinsics/memcpy.align.ll +++ b/llvm-spirv/test/llvm-intrinsics/memcpy.align.ll @@ -41,7 +41,7 @@ target triple = "spir" @__const.bar.a = private unnamed_addr addrspace(2) constant %struct.A { i64 0, %struct.B { [2 x i32] [i32 1, i32 2] } }, align 8 ; Function Attrs: convergent nounwind -define spir_func void @foo(%struct.A* noalias sret %agg.result) #0 { +define spir_func void @foo(%struct.A* noalias sret(%struct.A*) %agg.result) #0 { entry: %b = alloca %struct.B, align 4 %0 = bitcast %struct.B* %b to i8* @@ -73,7 +73,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture r declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 ; Function Attrs: convergent nounwind -define spir_func void @bar(%struct.B* noalias sret %agg.result) #0 { +define spir_func void @bar(%struct.B* noalias sret(%struct.B*) %agg.result) #0 { entry: %a = alloca %struct.A, align 8 %0 = bitcast %struct.A* %a to i8* diff --git a/llvm-spirv/test/llvm-intrinsics/memset.ll b/llvm-spirv/test/llvm-intrinsics/memset.ll index 950928c845892..1f7baa9702736 100644 --- a/llvm-spirv/test/llvm-intrinsics/memset.ll +++ b/llvm-spirv/test/llvm-intrinsics/memset.ll @@ -63,7 +63,7 @@ target triple = "spir" ; CHECK-LLVM: internal unnamed_addr addrspace(2) constant [4 x i8] c"\15\15\15\15" ; Function Attrs: nounwind -define spir_func void @_Z5foo11v(%struct.S1 addrspace(4)* noalias nocapture sret %agg.result, i32 %s1, i64 %s2, i8 %v) #0 { +define spir_func void @_Z5foo11v(%struct.S1 addrspace(4)* noalias nocapture sret(%struct.S1 addrspace(4)*) %agg.result, i32 %s1, i64 %s2, i8 %v) #0 { %x = alloca [4 x i8] %x.bc = bitcast [4 x i8]* %x to i8* %1 = bitcast %struct.S1 addrspace(4)* %agg.result to i8 addrspace(4)* diff --git a/llvm-spirv/test/transcoding/BuildNDRange.ll b/llvm-spirv/test/transcoding/BuildNDRange.ll index 49c7e8adc7834..f03c679170334 100644 --- a/llvm-spirv/test/transcoding/BuildNDRange.ll +++ b/llvm-spirv/test/transcoding/BuildNDRange.ll @@ -22,11 +22,11 @@ target triple = "spir" ; Function Attrs: nounwind define spir_kernel void @test() #0 !kernel_arg_addr_space !0 !kernel_arg_access_qual !0 !kernel_arg_type !0 !kernel_arg_base_type !0 !kernel_arg_type_qual !0 { %ndrange = alloca %struct.ndrange_t, align 4 - call spir_func void @_Z10ndrange_1Djj(%struct.ndrange_t* sret %ndrange, i32 123, i32 456) + call spir_func void @_Z10ndrange_1Djj(%struct.ndrange_t* sret(%struct.ndrange_t*) %ndrange, i32 123, i32 456) ret void } -declare spir_func void @_Z10ndrange_1Djj(%struct.ndrange_t* sret, i32, i32) #1 +declare spir_func void @_Z10ndrange_1Djj(%struct.ndrange_t* sret(%struct.ndrange_t*), i32, i32) #1 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm-spirv/test/transcoding/BuildNDRange_2.ll b/llvm-spirv/test/transcoding/BuildNDRange_2.ll index b630bdb9f75ab..c9db8a14efcfe 100644 --- a/llvm-spirv/test/transcoding/BuildNDRange_2.ll +++ b/llvm-spirv/test/transcoding/BuildNDRange_2.ll @@ -71,28 +71,28 @@ entry: %0 = bitcast [2 x i64]* %lsize2 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %0, i8* align 8 bitcast ([2 x i64]* @test_ndrange_2D3D.lsize2 to i8*), i64 16, i1 false) %arraydecay = getelementptr inbounds [2 x i64], [2 x i64]* %lsize2, i64 0, i64 0 - call spir_func void @_Z10ndrange_2DPKm(%struct.ndrange_t* sret %tmp, i64* %arraydecay) #2 + call spir_func void @_Z10ndrange_2DPKm(%struct.ndrange_t* sret(%struct.ndrange_t*) %tmp, i64* %arraydecay) #2 %1 = bitcast [3 x i64]* %lsize3 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %1, i8* align 8 bitcast ([3 x i64]* @test_ndrange_2D3D.lsize3 to i8*), i64 24, i1 false) %arraydecay2 = getelementptr inbounds [3 x i64], [3 x i64]* %lsize3, i64 0, i64 0 - call spir_func void @_Z10ndrange_3DPKm(%struct.ndrange_t* sret %tmp3, i64* %arraydecay2) #2 + call spir_func void @_Z10ndrange_3DPKm(%struct.ndrange_t* sret(%struct.ndrange_t*) %tmp3, i64* %arraydecay2) #2 ret void } ; Function Attrs: nounwind declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) #2 -declare spir_func void @_Z10ndrange_2DPKm(%struct.ndrange_t* sret, i64*) #1 +declare spir_func void @_Z10ndrange_2DPKm(%struct.ndrange_t* sret(%struct.ndrange_t*), i64*) #1 -declare spir_func void @_Z10ndrange_3DPKm(%struct.ndrange_t* sret, i64*) #1 +declare spir_func void @_Z10ndrange_3DPKm(%struct.ndrange_t* sret(%struct.ndrange_t*), i64*) #1 ; Function Attrs: nounwind define spir_func void @test_ndrange_const_2D3D() #0 { entry: %tmp = alloca %struct.ndrange_t, align 8 %tmp1 = alloca %struct.ndrange_t, align 8 - call spir_func void @_Z10ndrange_2DPKm(%struct.ndrange_t* sret %tmp, i64* getelementptr inbounds ([2 x i64], [2 x i64]* @test_ndrange_2D3D.lsize2, i64 0, i64 0)) #2 - call spir_func void @_Z10ndrange_3DPKm(%struct.ndrange_t* sret %tmp1, i64* getelementptr inbounds ([3 x i64], [3 x i64]* @test_ndrange_2D3D.lsize3, i64 0, i64 0)) #2 + call spir_func void @_Z10ndrange_2DPKm(%struct.ndrange_t* sret(%struct.ndrange_t*) %tmp, i64* getelementptr inbounds ([2 x i64], [2 x i64]* @test_ndrange_2D3D.lsize2, i64 0, i64 0)) #2 + call spir_func void @_Z10ndrange_3DPKm(%struct.ndrange_t* sret(%struct.ndrange_t*) %tmp1, i64* getelementptr inbounds ([3 x i64], [3 x i64]* @test_ndrange_2D3D.lsize3, i64 0, i64 0)) #2 ret void } diff --git a/llvm-spirv/test/transcoding/FPGAIVDepLoopAttrOnClosure.ll b/llvm-spirv/test/transcoding/SPV_INTEL_fpga_loop_controls/FPGAIVDepLoopAttrOnClosure.ll similarity index 50% rename from llvm-spirv/test/transcoding/FPGAIVDepLoopAttrOnClosure.ll rename to llvm-spirv/test/transcoding/SPV_INTEL_fpga_loop_controls/FPGAIVDepLoopAttrOnClosure.ll index 439f04bd28f2c..454aa708ea291 100644 --- a/llvm-spirv/test/transcoding/FPGAIVDepLoopAttrOnClosure.ll +++ b/llvm-spirv/test/transcoding/SPV_INTEL_fpga_loop_controls/FPGAIVDepLoopAttrOnClosure.ll @@ -13,21 +13,23 @@ ; const int c = 42; ; ; kernel([=]() mutable { -; [[intelfpga::ivdep(buf1, 3)]] +; [[intel::ivdep(buf1, 3)]] ; for (int i = 0; i < 6; ++i) { ; buf1[i] *= (buf2[i + 4] + c); -; [[intelfpga::ivdep(2)]] +; [[intel::ivdep(2)]] ; for (int j = 0; j < 7; ++j) ; buf2[i] *= (buf1[i] + buf2[i + 3]); ; } ; }); ; -; kernel([=]() mutable { -; [[intelfpga::ivdep(buf1, 3)]] -; [[intelfpga::ivdep(buf2, 2)]] +; int *ptr1 = buf1; +; int *ptr2 = buf2; +; kernel([=]() mutable { +; [[intel::ivdep(ptr1, 3)]] +; [[intel::ivdep(ptr2, 2)]] ; for (int i = 0; i < 6; ++i) { -; buf1[i] *= (buf2[i + 4] + c); -; buf2[i] *= (buf1[i] + buf2[i + 3]); +; ptr1[i] *= (ptr2[i + 4] + c); +; ptr2[i] *= (ptr1[i] + ptr2[i + 3]); ; } ; }); ; @@ -66,134 +68,68 @@ ; CHECK-SPIRV: TypeFunction [[TYPE_EMB_FUNC:[0-9]+]] {{[0-9]+}} [[TYPE_EMB_CLOSURE_PTR]] ; CHECK-SPIRV: TypePointer [[TYPE_EMB_CLOSURE_PARAM_PTR:[0-9]+]] {{[0-9]+}} [[TYPE_EMB_CLOSURE_PTR]] ; CHECK-SPIRV: TypePointer [[TYPE_PTR:[0-9]+]] {{[0-9]+}} [[TYPE_ARRAY]] -; CHECK-SPIRV: TypeStruct [[TYPE_SFLN_CLOSURE_STRUCT:[0-9]+]] [[TYPE_ARRAY]] [[TYPE_ARRAY]] +; CHECK-SPIRV: TypePointer [[TYPE_INT_PTR:[0-9]+]] {{[0-9]+}} [[TYPE_INT_32]] +; CHECK-SPIRV: TypeStruct [[TYPE_SFLN_CLOSURE_STRUCT:[0-9]+]] [[TYPE_INT_PTR]] [[TYPE_INT_PTR]] ; The next type is only used when initializing the memory fields ; CHECK-SPIRV: TypePointer [[TYPE_CLOSURE_INIT_PTR:[0-9]+]] {{[0-9]+}} [[TYPE_SFLN_CLOSURE_STRUCT]] ; This is the type used in the kernel function ; CHECK-SPIRV: TypePointer [[TYPE_SFLN_CLOSURE_PTR:[0-9]+]] {{[0-9]+}} [[TYPE_SFLN_CLOSURE_STRUCT]] ; CHECK-SPIRV: TypeFunction [[TYPE_SFLN_FUNC:[0-9]+]] {{[0-9]+}} [[TYPE_SFLN_CLOSURE_PTR]] ; CHECK-SPIRV: TypePointer [[TYPE_SFLN_CLOSURE_PARAM_PTR:[0-9]+]] {{[0-9]+}} [[TYPE_SFLN_CLOSURE_PTR]] +; CHECK-SPIRV: TypePointer [[TYPE_SFLN_INT_PTR:[0-9]+]] {{[0-9]+}} [[TYPE_INT_PTR]] target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64" target triple = "spir64-unknown-unknown-sycldevice" +%struct._ZTS15__wrapper_class.__wrapper_class = type { [10 x i32] } +%struct._ZTS15__wrapper_class.__wrapper_class.0 = type { [10 x i32] } ; CHECK-LLVM: %[[CLOSURE_NAME_EMB:"class.*"]] = type { [10 x i32], [10 x i32] } -; CHECK-LLVM: %[[CLOSURE_NAME_SFLN:"class.*"]] = type { [10 x i32], [10 x i32] } +; CHECK-LLVM: %[[CLOSURE_NAME_SFLN:"class.*"]] = type { i32 addrspace(4)*, i32 addrspace(4)* } %"class._ZTSZ4mainE3$_0.anon" = type { [10 x i32], [10 x i32] } -%"class._ZTSZ4mainE3$_0.anon.0" = type { [10 x i32], [10 x i32] } +%"class._ZTSZ4mainE3$_0.anon.0" = type { i32 addrspace(4)*, i32 addrspace(4)* } -; Function Attrs: convergent norecurse -define dso_local spir_kernel void @_ZTSZ4mainE16EmbeddedLoopTest(i32 %_arg_, i32 %_arg_1, i32 %_arg_3, i32 %_arg_5, i32 %_arg_7, i32 %_arg_9, i32 %_arg_11, i32 %_arg_13, i32 %_arg_15, i32 %_arg_17, i32 %_arg_19, i32 %_arg_21, i32 %_arg_23, i32 %_arg_25, i32 %_arg_27, i32 %_arg_29, i32 %_arg_31, i32 %_arg_33, i32 %_arg_35, i32 %_arg_37) #0 !kernel_arg_buffer_location !4 { +; Function Attrs: convergent norecurse uwtable +define dso_local spir_kernel void @_ZTSZ4mainE16EmbeddedLoopTest(%struct._ZTS15__wrapper_class.__wrapper_class* byval(%struct._ZTS15__wrapper_class.__wrapper_class) align 4 %_arg_, %struct._ZTS15__wrapper_class.__wrapper_class.0* byval(%struct._ZTS15__wrapper_class.__wrapper_class.0) align 4 %_arg_1) #0 !kernel_arg_buffer_location !4 { entry: - %_arg_.addr = alloca i32, align 4 - %_arg_.addr2 = alloca i32, align 4 - %_arg_.addr4 = alloca i32, align 4 - %_arg_.addr6 = alloca i32, align 4 - %_arg_.addr8 = alloca i32, align 4 - %_arg_.addr10 = alloca i32, align 4 - %_arg_.addr12 = alloca i32, align 4 - %_arg_.addr14 = alloca i32, align 4 - %_arg_.addr16 = alloca i32, align 4 - %_arg_.addr18 = alloca i32, align 4 - %_arg_.addr20 = alloca i32, align 4 - %_arg_.addr22 = alloca i32, align 4 - %_arg_.addr24 = alloca i32, align 4 - %_arg_.addr26 = alloca i32, align 4 - %_arg_.addr28 = alloca i32, align 4 - %_arg_.addr30 = alloca i32, align 4 - %_arg_.addr32 = alloca i32, align 4 - %_arg_.addr34 = alloca i32, align 4 - %_arg_.addr36 = alloca i32, align 4 - %_arg_.addr38 = alloca i32, align 4 %0 = alloca %"class._ZTSZ4mainE3$_0.anon", align 4 - store i32 %_arg_, i32* %_arg_.addr, align 4, !tbaa !5 - store i32 %_arg_1, i32* %_arg_.addr2, align 4, !tbaa !5 - store i32 %_arg_3, i32* %_arg_.addr4, align 4, !tbaa !5 - store i32 %_arg_5, i32* %_arg_.addr6, align 4, !tbaa !5 - store i32 %_arg_7, i32* %_arg_.addr8, align 4, !tbaa !5 - store i32 %_arg_9, i32* %_arg_.addr10, align 4, !tbaa !5 - store i32 %_arg_11, i32* %_arg_.addr12, align 4, !tbaa !5 - store i32 %_arg_13, i32* %_arg_.addr14, align 4, !tbaa !5 - store i32 %_arg_15, i32* %_arg_.addr16, align 4, !tbaa !5 - store i32 %_arg_17, i32* %_arg_.addr18, align 4, !tbaa !5 - store i32 %_arg_19, i32* %_arg_.addr20, align 4, !tbaa !5 - store i32 %_arg_21, i32* %_arg_.addr22, align 4, !tbaa !5 - store i32 %_arg_23, i32* %_arg_.addr24, align 4, !tbaa !5 - store i32 %_arg_25, i32* %_arg_.addr26, align 4, !tbaa !5 - store i32 %_arg_27, i32* %_arg_.addr28, align 4, !tbaa !5 - store i32 %_arg_29, i32* %_arg_.addr30, align 4, !tbaa !5 - store i32 %_arg_31, i32* %_arg_.addr32, align 4, !tbaa !5 - store i32 %_arg_33, i32* %_arg_.addr34, align 4, !tbaa !5 - store i32 %_arg_35, i32* %_arg_.addr36, align 4, !tbaa !5 - store i32 %_arg_37, i32* %_arg_.addr38, align 4, !tbaa !5 %1 = bitcast %"class._ZTSZ4mainE3$_0.anon"* %0 to i8* call void @llvm.lifetime.start.p0i8(i64 80, i8* %1) #3 %2 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon", %"class._ZTSZ4mainE3$_0.anon"* %0, i32 0, i32 0 + %3 = getelementptr inbounds %struct._ZTS15__wrapper_class.__wrapper_class, %struct._ZTS15__wrapper_class.__wrapper_class* %_arg_, i32 0, i32 0 %arrayinit.begin = getelementptr inbounds [10 x i32], [10 x i32]* %2, i64 0, i64 0 - %3 = load i32, i32* %_arg_.addr, align 4, !tbaa !5 - store i32 %3, i32* %arrayinit.begin, align 4, !tbaa !5 - %arrayinit.element = getelementptr inbounds i32, i32* %arrayinit.begin, i64 1 - %4 = load i32, i32* %_arg_.addr2, align 4, !tbaa !5 - store i32 %4, i32* %arrayinit.element, align 4, !tbaa !5 - %arrayinit.element39 = getelementptr inbounds i32, i32* %arrayinit.element, i64 1 - %5 = load i32, i32* %_arg_.addr4, align 4, !tbaa !5 - store i32 %5, i32* %arrayinit.element39, align 4, !tbaa !5 - %arrayinit.element40 = getelementptr inbounds i32, i32* %arrayinit.element39, i64 1 - %6 = load i32, i32* %_arg_.addr6, align 4, !tbaa !5 - store i32 %6, i32* %arrayinit.element40, align 4, !tbaa !5 - %arrayinit.element41 = getelementptr inbounds i32, i32* %arrayinit.element40, i64 1 - %7 = load i32, i32* %_arg_.addr8, align 4, !tbaa !5 - store i32 %7, i32* %arrayinit.element41, align 4, !tbaa !5 - %arrayinit.element42 = getelementptr inbounds i32, i32* %arrayinit.element41, i64 1 - %8 = load i32, i32* %_arg_.addr10, align 4, !tbaa !5 - store i32 %8, i32* %arrayinit.element42, align 4, !tbaa !5 - %arrayinit.element43 = getelementptr inbounds i32, i32* %arrayinit.element42, i64 1 - %9 = load i32, i32* %_arg_.addr12, align 4, !tbaa !5 - store i32 %9, i32* %arrayinit.element43, align 4, !tbaa !5 - %arrayinit.element44 = getelementptr inbounds i32, i32* %arrayinit.element43, i64 1 - %10 = load i32, i32* %_arg_.addr14, align 4, !tbaa !5 - store i32 %10, i32* %arrayinit.element44, align 4, !tbaa !5 - %arrayinit.element45 = getelementptr inbounds i32, i32* %arrayinit.element44, i64 1 - %11 = load i32, i32* %_arg_.addr16, align 4, !tbaa !5 - store i32 %11, i32* %arrayinit.element45, align 4, !tbaa !5 - %arrayinit.element46 = getelementptr inbounds i32, i32* %arrayinit.element45, i64 1 - %12 = load i32, i32* %_arg_.addr18, align 4, !tbaa !5 - store i32 %12, i32* %arrayinit.element46, align 4, !tbaa !5 - %13 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon", %"class._ZTSZ4mainE3$_0.anon"* %0, i32 0, i32 1 - %arrayinit.begin47 = getelementptr inbounds [10 x i32], [10 x i32]* %13, i64 0, i64 0 - %14 = load i32, i32* %_arg_.addr20, align 4, !tbaa !5 - store i32 %14, i32* %arrayinit.begin47, align 4, !tbaa !5 - %arrayinit.element48 = getelementptr inbounds i32, i32* %arrayinit.begin47, i64 1 - %15 = load i32, i32* %_arg_.addr22, align 4, !tbaa !5 - store i32 %15, i32* %arrayinit.element48, align 4, !tbaa !5 - %arrayinit.element49 = getelementptr inbounds i32, i32* %arrayinit.element48, i64 1 - %16 = load i32, i32* %_arg_.addr24, align 4, !tbaa !5 - store i32 %16, i32* %arrayinit.element49, align 4, !tbaa !5 - %arrayinit.element50 = getelementptr inbounds i32, i32* %arrayinit.element49, i64 1 - %17 = load i32, i32* %_arg_.addr26, align 4, !tbaa !5 - store i32 %17, i32* %arrayinit.element50, align 4, !tbaa !5 - %arrayinit.element51 = getelementptr inbounds i32, i32* %arrayinit.element50, i64 1 - %18 = load i32, i32* %_arg_.addr28, align 4, !tbaa !5 - store i32 %18, i32* %arrayinit.element51, align 4, !tbaa !5 - %arrayinit.element52 = getelementptr inbounds i32, i32* %arrayinit.element51, i64 1 - %19 = load i32, i32* %_arg_.addr30, align 4, !tbaa !5 - store i32 %19, i32* %arrayinit.element52, align 4, !tbaa !5 - %arrayinit.element53 = getelementptr inbounds i32, i32* %arrayinit.element52, i64 1 - %20 = load i32, i32* %_arg_.addr32, align 4, !tbaa !5 - store i32 %20, i32* %arrayinit.element53, align 4, !tbaa !5 - %arrayinit.element54 = getelementptr inbounds i32, i32* %arrayinit.element53, i64 1 - %21 = load i32, i32* %_arg_.addr34, align 4, !tbaa !5 - store i32 %21, i32* %arrayinit.element54, align 4, !tbaa !5 - %arrayinit.element55 = getelementptr inbounds i32, i32* %arrayinit.element54, i64 1 - %22 = load i32, i32* %_arg_.addr36, align 4, !tbaa !5 - store i32 %22, i32* %arrayinit.element55, align 4, !tbaa !5 - %arrayinit.element56 = getelementptr inbounds i32, i32* %arrayinit.element55, i64 1 - %23 = load i32, i32* %_arg_.addr38, align 4, !tbaa !5 - store i32 %23, i32* %arrayinit.element56, align 4, !tbaa !5 - %24 = addrspacecast %"class._ZTSZ4mainE3$_0.anon"* %0 to %"class._ZTSZ4mainE3$_0.anon" addrspace(4)* - call spir_func void @"_ZZ4mainEN3$_0clEv"(%"class._ZTSZ4mainE3$_0.anon" addrspace(4)* %24) #4 - %25 = bitcast %"class._ZTSZ4mainE3$_0.anon"* %0 to i8* - call void @llvm.lifetime.end.p0i8(i64 80, i8* %25) #3 + br label %arrayinit.body + +arrayinit.body: ; preds = %arrayinit.body, %entry + %arrayinit.index = phi i64 [ 0, %entry ], [ %arrayinit.next, %arrayinit.body ] + %4 = getelementptr inbounds i32, i32* %arrayinit.begin, i64 %arrayinit.index + %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* %3, i64 0, i64 %arrayinit.index + %5 = load i32, i32* %arrayidx, align 4, !tbaa !5 + store i32 %5, i32* %4, align 4, !tbaa !5 + %arrayinit.next = add nuw i64 %arrayinit.index, 1 + %arrayinit.done = icmp eq i64 %arrayinit.next, 10 + br i1 %arrayinit.done, label %arrayinit.end, label %arrayinit.body + +arrayinit.end: ; preds = %arrayinit.body + %6 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon", %"class._ZTSZ4mainE3$_0.anon"* %0, i32 0, i32 1 + %7 = getelementptr inbounds %struct._ZTS15__wrapper_class.__wrapper_class.0, %struct._ZTS15__wrapper_class.__wrapper_class.0* %_arg_1, i32 0, i32 0 + %arrayinit.begin2 = getelementptr inbounds [10 x i32], [10 x i32]* %6, i64 0, i64 0 + br label %arrayinit.body3 + +arrayinit.body3: ; preds = %arrayinit.body3, %arrayinit.end + %arrayinit.index4 = phi i64 [ 0, %arrayinit.end ], [ %arrayinit.next6, %arrayinit.body3 ] + %8 = getelementptr inbounds i32, i32* %arrayinit.begin2, i64 %arrayinit.index4 + %arrayidx5 = getelementptr inbounds [10 x i32], [10 x i32]* %7, i64 0, i64 %arrayinit.index4 + %9 = load i32, i32* %arrayidx5, align 4, !tbaa !5 + store i32 %9, i32* %8, align 4, !tbaa !5 + %arrayinit.next6 = add nuw i64 %arrayinit.index4, 1 + %arrayinit.done7 = icmp eq i64 %arrayinit.next6, 10 + br i1 %arrayinit.done7, label %arrayinit.end8, label %arrayinit.body3 + +arrayinit.end8: ; preds = %arrayinit.body3 + %10 = addrspacecast %"class._ZTSZ4mainE3$_0.anon"* %0 to %"class._ZTSZ4mainE3$_0.anon" addrspace(4)* + call spir_func void @"_ZZ4mainEN3$_0clEv"(%"class._ZTSZ4mainE3$_0.anon" addrspace(4)* %10) #4 + %11 = bitcast %"class._ZTSZ4mainE3$_0.anon"* %0 to i8* + call void @llvm.lifetime.end.p0i8(i64 80, i8* %11) #3 ret void } @@ -202,7 +138,7 @@ declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1 ; CHECK-SPIRV: Function {{.*}} [[TYPE_EMB_FUNC]] ; CHECK-LLVM: define internal spir_func void {{.*}}(%[[CLOSURE_NAME_EMB]] addrspace(4)* %this) -; Function Attrs: convergent inlinehint norecurse nounwind +; Function Attrs: convergent inlinehint norecurse nounwind uwtable define internal spir_func void @"_ZZ4mainEN3$_0clEv"(%"class._ZTSZ4mainE3$_0.anon" addrspace(4)* %this) #2 align 2 { entry: ; CHECK-SPIRV: Variable [[TYPE_EMB_CLOSURE_PARAM_PTR]] [[THIS_EMB_ID:[0-9]+]] @@ -330,118 +266,28 @@ for.end20: ; preds = %for.cond.cleanup ; Function Attrs: argmemonly nounwind willreturn declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1 -; Function Attrs: convergent norecurse -define dso_local spir_kernel void @_ZTSZ4mainE18VaryingSafelenTest(i32 %_arg_, i32 %_arg_1, i32 %_arg_3, i32 %_arg_5, i32 %_arg_7, i32 %_arg_9, i32 %_arg_11, i32 %_arg_13, i32 %_arg_15, i32 %_arg_17, i32 %_arg_19, i32 %_arg_21, i32 %_arg_23, i32 %_arg_25, i32 %_arg_27, i32 %_arg_29, i32 %_arg_31, i32 %_arg_33, i32 %_arg_35, i32 %_arg_37) #0 !kernel_arg_buffer_location !4 { +; Function Attrs: convergent norecurse uwtable +define dso_local spir_kernel void @_ZTSZ4mainE18VaryingSafelenOnPointersTest(i32 addrspace(1)* %_arg_, i32 addrspace(1)* %_arg_1) #0 !kernel_arg_buffer_location !4 { entry: - %_arg_.addr = alloca i32, align 4 - %_arg_.addr2 = alloca i32, align 4 - %_arg_.addr4 = alloca i32, align 4 - %_arg_.addr6 = alloca i32, align 4 - %_arg_.addr8 = alloca i32, align 4 - %_arg_.addr10 = alloca i32, align 4 - %_arg_.addr12 = alloca i32, align 4 - %_arg_.addr14 = alloca i32, align 4 - %_arg_.addr16 = alloca i32, align 4 - %_arg_.addr18 = alloca i32, align 4 - %_arg_.addr20 = alloca i32, align 4 - %_arg_.addr22 = alloca i32, align 4 - %_arg_.addr24 = alloca i32, align 4 - %_arg_.addr26 = alloca i32, align 4 - %_arg_.addr28 = alloca i32, align 4 - %_arg_.addr30 = alloca i32, align 4 - %_arg_.addr32 = alloca i32, align 4 - %_arg_.addr34 = alloca i32, align 4 - %_arg_.addr36 = alloca i32, align 4 - %_arg_.addr38 = alloca i32, align 4 - %0 = alloca %"class._ZTSZ4mainE3$_0.anon.0", align 4 - store i32 %_arg_, i32* %_arg_.addr, align 4, !tbaa !5 - store i32 %_arg_1, i32* %_arg_.addr2, align 4, !tbaa !5 - store i32 %_arg_3, i32* %_arg_.addr4, align 4, !tbaa !5 - store i32 %_arg_5, i32* %_arg_.addr6, align 4, !tbaa !5 - store i32 %_arg_7, i32* %_arg_.addr8, align 4, !tbaa !5 - store i32 %_arg_9, i32* %_arg_.addr10, align 4, !tbaa !5 - store i32 %_arg_11, i32* %_arg_.addr12, align 4, !tbaa !5 - store i32 %_arg_13, i32* %_arg_.addr14, align 4, !tbaa !5 - store i32 %_arg_15, i32* %_arg_.addr16, align 4, !tbaa !5 - store i32 %_arg_17, i32* %_arg_.addr18, align 4, !tbaa !5 - store i32 %_arg_19, i32* %_arg_.addr20, align 4, !tbaa !5 - store i32 %_arg_21, i32* %_arg_.addr22, align 4, !tbaa !5 - store i32 %_arg_23, i32* %_arg_.addr24, align 4, !tbaa !5 - store i32 %_arg_25, i32* %_arg_.addr26, align 4, !tbaa !5 - store i32 %_arg_27, i32* %_arg_.addr28, align 4, !tbaa !5 - store i32 %_arg_29, i32* %_arg_.addr30, align 4, !tbaa !5 - store i32 %_arg_31, i32* %_arg_.addr32, align 4, !tbaa !5 - store i32 %_arg_33, i32* %_arg_.addr34, align 4, !tbaa !5 - store i32 %_arg_35, i32* %_arg_.addr36, align 4, !tbaa !5 - store i32 %_arg_37, i32* %_arg_.addr38, align 4, !tbaa !5 + %_arg_.addr = alloca i32 addrspace(1)*, align 8 + %_arg_.addr2 = alloca i32 addrspace(1)*, align 8 + %0 = alloca %"class._ZTSZ4mainE3$_0.anon.0", align 8 + store i32 addrspace(1)* %_arg_, i32 addrspace(1)** %_arg_.addr, align 8, !tbaa !9 + store i32 addrspace(1)* %_arg_1, i32 addrspace(1)** %_arg_.addr2, align 8, !tbaa !9 %1 = bitcast %"class._ZTSZ4mainE3$_0.anon.0"* %0 to i8* - call void @llvm.lifetime.start.p0i8(i64 80, i8* %1) #3 + call void @llvm.lifetime.start.p0i8(i64 16, i8* %1) #3 %2 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon.0", %"class._ZTSZ4mainE3$_0.anon.0"* %0, i32 0, i32 0 - %arrayinit.begin = getelementptr inbounds [10 x i32], [10 x i32]* %2, i64 0, i64 0 - %3 = load i32, i32* %_arg_.addr, align 4, !tbaa !5 - store i32 %3, i32* %arrayinit.begin, align 4, !tbaa !5 - %arrayinit.element = getelementptr inbounds i32, i32* %arrayinit.begin, i64 1 - %4 = load i32, i32* %_arg_.addr2, align 4, !tbaa !5 - store i32 %4, i32* %arrayinit.element, align 4, !tbaa !5 - %arrayinit.element39 = getelementptr inbounds i32, i32* %arrayinit.element, i64 1 - %5 = load i32, i32* %_arg_.addr4, align 4, !tbaa !5 - store i32 %5, i32* %arrayinit.element39, align 4, !tbaa !5 - %arrayinit.element40 = getelementptr inbounds i32, i32* %arrayinit.element39, i64 1 - %6 = load i32, i32* %_arg_.addr6, align 4, !tbaa !5 - store i32 %6, i32* %arrayinit.element40, align 4, !tbaa !5 - %arrayinit.element41 = getelementptr inbounds i32, i32* %arrayinit.element40, i64 1 - %7 = load i32, i32* %_arg_.addr8, align 4, !tbaa !5 - store i32 %7, i32* %arrayinit.element41, align 4, !tbaa !5 - %arrayinit.element42 = getelementptr inbounds i32, i32* %arrayinit.element41, i64 1 - %8 = load i32, i32* %_arg_.addr10, align 4, !tbaa !5 - store i32 %8, i32* %arrayinit.element42, align 4, !tbaa !5 - %arrayinit.element43 = getelementptr inbounds i32, i32* %arrayinit.element42, i64 1 - %9 = load i32, i32* %_arg_.addr12, align 4, !tbaa !5 - store i32 %9, i32* %arrayinit.element43, align 4, !tbaa !5 - %arrayinit.element44 = getelementptr inbounds i32, i32* %arrayinit.element43, i64 1 - %10 = load i32, i32* %_arg_.addr14, align 4, !tbaa !5 - store i32 %10, i32* %arrayinit.element44, align 4, !tbaa !5 - %arrayinit.element45 = getelementptr inbounds i32, i32* %arrayinit.element44, i64 1 - %11 = load i32, i32* %_arg_.addr16, align 4, !tbaa !5 - store i32 %11, i32* %arrayinit.element45, align 4, !tbaa !5 - %arrayinit.element46 = getelementptr inbounds i32, i32* %arrayinit.element45, i64 1 - %12 = load i32, i32* %_arg_.addr18, align 4, !tbaa !5 - store i32 %12, i32* %arrayinit.element46, align 4, !tbaa !5 - %13 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon.0", %"class._ZTSZ4mainE3$_0.anon.0"* %0, i32 0, i32 1 - %arrayinit.begin47 = getelementptr inbounds [10 x i32], [10 x i32]* %13, i64 0, i64 0 - %14 = load i32, i32* %_arg_.addr20, align 4, !tbaa !5 - store i32 %14, i32* %arrayinit.begin47, align 4, !tbaa !5 - %arrayinit.element48 = getelementptr inbounds i32, i32* %arrayinit.begin47, i64 1 - %15 = load i32, i32* %_arg_.addr22, align 4, !tbaa !5 - store i32 %15, i32* %arrayinit.element48, align 4, !tbaa !5 - %arrayinit.element49 = getelementptr inbounds i32, i32* %arrayinit.element48, i64 1 - %16 = load i32, i32* %_arg_.addr24, align 4, !tbaa !5 - store i32 %16, i32* %arrayinit.element49, align 4, !tbaa !5 - %arrayinit.element50 = getelementptr inbounds i32, i32* %arrayinit.element49, i64 1 - %17 = load i32, i32* %_arg_.addr26, align 4, !tbaa !5 - store i32 %17, i32* %arrayinit.element50, align 4, !tbaa !5 - %arrayinit.element51 = getelementptr inbounds i32, i32* %arrayinit.element50, i64 1 - %18 = load i32, i32* %_arg_.addr28, align 4, !tbaa !5 - store i32 %18, i32* %arrayinit.element51, align 4, !tbaa !5 - %arrayinit.element52 = getelementptr inbounds i32, i32* %arrayinit.element51, i64 1 - %19 = load i32, i32* %_arg_.addr30, align 4, !tbaa !5 - store i32 %19, i32* %arrayinit.element52, align 4, !tbaa !5 - %arrayinit.element53 = getelementptr inbounds i32, i32* %arrayinit.element52, i64 1 - %20 = load i32, i32* %_arg_.addr32, align 4, !tbaa !5 - store i32 %20, i32* %arrayinit.element53, align 4, !tbaa !5 - %arrayinit.element54 = getelementptr inbounds i32, i32* %arrayinit.element53, i64 1 - %21 = load i32, i32* %_arg_.addr34, align 4, !tbaa !5 - store i32 %21, i32* %arrayinit.element54, align 4, !tbaa !5 - %arrayinit.element55 = getelementptr inbounds i32, i32* %arrayinit.element54, i64 1 - %22 = load i32, i32* %_arg_.addr36, align 4, !tbaa !5 - store i32 %22, i32* %arrayinit.element55, align 4, !tbaa !5 - %arrayinit.element56 = getelementptr inbounds i32, i32* %arrayinit.element55, i64 1 - %23 = load i32, i32* %_arg_.addr38, align 4, !tbaa !5 - store i32 %23, i32* %arrayinit.element56, align 4, !tbaa !5 - %24 = addrspacecast %"class._ZTSZ4mainE3$_0.anon.0"* %0 to %"class._ZTSZ4mainE3$_0.anon.0" addrspace(4)* - call spir_func void @"_ZZ4mainEN3$_1clEv"(%"class._ZTSZ4mainE3$_0.anon.0" addrspace(4)* %24) #4 - %25 = bitcast %"class._ZTSZ4mainE3$_0.anon.0"* %0 to i8* - call void @llvm.lifetime.end.p0i8(i64 80, i8* %25) #3 + %3 = load i32 addrspace(1)*, i32 addrspace(1)** %_arg_.addr, align 8, !tbaa !9 + %4 = addrspacecast i32 addrspace(1)* %3 to i32 addrspace(4)* + store i32 addrspace(4)* %4, i32 addrspace(4)** %2, align 8, !tbaa !20 + %5 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon.0", %"class._ZTSZ4mainE3$_0.anon.0"* %0, i32 0, i32 1 + %6 = load i32 addrspace(1)*, i32 addrspace(1)** %_arg_.addr2, align 8, !tbaa !9 + %7 = addrspacecast i32 addrspace(1)* %6 to i32 addrspace(4)* + store i32 addrspace(4)* %7, i32 addrspace(4)** %5, align 8, !tbaa !22 + %8 = addrspacecast %"class._ZTSZ4mainE3$_0.anon.0"* %0 to %"class._ZTSZ4mainE3$_0.anon.0" addrspace(4)* + call spir_func void @"_ZZ4mainEN3$_1clEv"(%"class._ZTSZ4mainE3$_0.anon.0" addrspace(4)* %8) #4 + %9 = bitcast %"class._ZTSZ4mainE3$_0.anon.0"* %0 to i8* + call void @llvm.lifetime.end.p0i8(i64 16, i8* %9) #3 ret void } @@ -478,70 +324,80 @@ for.cond.cleanup: ; preds = %for.cond br label %for.end for.body: ; preds = %for.cond - ; CHECK-SPIRV: InBoundsPtrAccessChain [[TYPE_PTR]] [[BUF2_SFLN_PRE_ADD_1_ID]] [[THIS_SFLN_LOAD]] [[OFFSET_CONST_0]] [[OFFSET_CONST_1]] + ; CHECK-SPIRV: InBoundsPtrAccessChain [[TYPE_SFLN_INT_PTR]] [[BUF2_SFLN_PRE_ADD_1_ID]] [[THIS_SFLN_LOAD]] [[OFFSET_CONST_0]] [[OFFSET_CONST_1]] ; CHECK-LLVM: %[[BUF2_SFLN_CLOSURE_ACCESS:[0-9]+]] = getelementptr inbounds %[[CLOSURE_NAME_SFLN]], %[[CLOSURE_NAME_SFLN]] addrspace(4)* %this1, i32 0, i32 1 + ; CHECK-LLVM: %[[BUF2_SFLN_CLOSURE_ACCESS_LOAD:[0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* %[[BUF2_SFLN_CLOSURE_ACCESS]] %3 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon.0", %"class._ZTSZ4mainE3$_0.anon.0" addrspace(4)* %this1, i32 0, i32 1 - %4 = load i32, i32* %i, align 4, !tbaa !5 - %add = add nsw i32 %4, 4 + %4 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* %3, align 8, !tbaa !22 + %5 = load i32, i32* %i, align 4, !tbaa !5 + %add = add nsw i32 %5, 4 %idxprom = sext i32 %add to i64 - ; CHECK-LLVM: getelementptr inbounds [10 x i32], [10 x i32] addrspace(4)* %[[BUF2_SFLN_CLOSURE_ACCESS]]{{.*}}, !llvm.index.group ![[BUF2_SFLN_INDEX_GROUP:[0-9]+]] - %arrayidx = getelementptr inbounds [10 x i32], [10 x i32] addrspace(4)* %3, i64 0, i64 %idxprom, !llvm.index.group !20 - %5 = load i32, i32 addrspace(4)* %arrayidx, align 4, !tbaa !5 - %add2 = add nsw i32 %5, 42 - ; CHECK-SPIRV: InBoundsPtrAccessChain [[TYPE_PTR]] [[BUF1_SFLN_PRE_MUL_ID]] [[THIS_SFLN_LOAD]] [[OFFSET_CONST_0]] [[OFFSET_CONST_0]] + ; CHECK-LLVM: getelementptr inbounds i32, i32 addrspace(4)* %[[BUF2_SFLN_CLOSURE_ACCESS_LOAD]]{{.*}}, !llvm.index.group ![[BUF2_SFLN_INDEX_GROUP:[0-9]+]] + %ptridx = getelementptr inbounds i32, i32 addrspace(4)* %4, i64 %idxprom, !llvm.index.group !23 + %6 = load i32, i32 addrspace(4)* %ptridx, align 4, !tbaa !5 + %add2 = add nsw i32 %6, 42 + ; CHECK-SPIRV: InBoundsPtrAccessChain [[TYPE_SFLN_INT_PTR]] [[BUF1_SFLN_PRE_MUL_ID]] [[THIS_SFLN_LOAD]] [[OFFSET_CONST_0]] [[OFFSET_CONST_0]] ; CHECK-LLVM: %[[BUF1_SFLN_CLOSURE_ACCESS:[0-9]+]] = getelementptr inbounds %[[CLOSURE_NAME_SFLN]], %[[CLOSURE_NAME_SFLN]] addrspace(4)* %this1, i32 0, i32 0 - %6 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon.0", %"class._ZTSZ4mainE3$_0.anon.0" addrspace(4)* %this1, i32 0, i32 0 - %7 = load i32, i32* %i, align 4, !tbaa !5 - %idxprom3 = sext i32 %7 to i64 - ; CHECK-LLVM: getelementptr inbounds [10 x i32], [10 x i32] addrspace(4)* %[[BUF1_SFLN_CLOSURE_ACCESS]]{{.*}}, !llvm.index.group ![[BUF1_SFLN_INDEX_GROUP:[0-9]+]] - %arrayidx4 = getelementptr inbounds [10 x i32], [10 x i32] addrspace(4)* %6, i64 0, i64 %idxprom3, !llvm.index.group !21 - %8 = load i32, i32 addrspace(4)* %arrayidx4, align 4, !tbaa !5 - %mul = mul nsw i32 %8, %add2 - store i32 %mul, i32 addrspace(4)* %arrayidx4, align 4, !tbaa !5 - ; CHECK-SPIRV: InBoundsPtrAccessChain [[TYPE_PTR]] [[BUF1_SFLN_PRE_STORE_ID]] [[THIS_SFLN_LOAD]] [[OFFSET_CONST_0]] [[OFFSET_CONST_0]] + ; CHECK-LLVM: %[[BUF1_SFLN_CLOSURE_ACCESS_LOAD:[0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* %[[BUF1_SFLN_CLOSURE_ACCESS]] + %7 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon.0", %"class._ZTSZ4mainE3$_0.anon.0" addrspace(4)* %this1, i32 0, i32 0 + %8 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* %7, align 8, !tbaa !20 + %9 = load i32, i32* %i, align 4, !tbaa !5 + %idxprom3 = sext i32 %9 to i64 + ; CHECK-LLVM: getelementptr inbounds i32, i32 addrspace(4)* %[[BUF1_SFLN_CLOSURE_ACCESS_LOAD]]{{.*}}, !llvm.index.group ![[BUF1_SFLN_INDEX_GROUP:[0-9]+]] + %ptridx4 = getelementptr inbounds i32, i32 addrspace(4)* %8, i64 %idxprom3, !llvm.index.group !24 + %10 = load i32, i32 addrspace(4)* %ptridx4, align 4, !tbaa !5 + %mul = mul nsw i32 %10, %add2 + store i32 %mul, i32 addrspace(4)* %ptridx4, align 4, !tbaa !5 + ; CHECK-SPIRV: InBoundsPtrAccessChain [[TYPE_SFLN_INT_PTR]] [[BUF1_SFLN_PRE_STORE_ID]] [[THIS_SFLN_LOAD]] [[OFFSET_CONST_0]] [[OFFSET_CONST_0]] ; CHECK-LLVM: %[[BUF1_SFLN_CLOSURE_ACCESS:[0-9]+]] = getelementptr inbounds %[[CLOSURE_NAME_SFLN]], %[[CLOSURE_NAME_SFLN]] addrspace(4)* %this1, i32 0, i32 0 - %9 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon.0", %"class._ZTSZ4mainE3$_0.anon.0" addrspace(4)* %this1, i32 0, i32 0 - %10 = load i32, i32* %i, align 4, !tbaa !5 - %idxprom5 = sext i32 %10 to i64 - ; CHECK-LLVM: getelementptr inbounds [10 x i32], [10 x i32] addrspace(4)* %[[BUF1_SFLN_CLOSURE_ACCESS]]{{.*}}, !llvm.index.group ![[BUF1_SFLN_INDEX_GROUP]] - %arrayidx6 = getelementptr inbounds [10 x i32], [10 x i32] addrspace(4)* %9, i64 0, i64 %idxprom5, !llvm.index.group !21 - %11 = load i32, i32 addrspace(4)* %arrayidx6, align 4, !tbaa !5 - ; CHECK-SPIRV: InBoundsPtrAccessChain [[TYPE_PTR]] [[BUF2_SFLN_PRE_ADD_2_ID]] [[THIS_SFLN_LOAD]] [[OFFSET_CONST_0]] [[OFFSET_CONST_1]] - ; CHECK-LLVM: %[[BUF2_SFLN_CLOSURE_ACCESS:[0-9]+]] = getelementptr inbounds %[[CLOSURE_NAME_SFLN]], %[[CLOSURE_NAME_SFLN]] addrspace(4)* %this1, i32 0, i32 1 - %12 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon.0", %"class._ZTSZ4mainE3$_0.anon.0" addrspace(4)* %this1, i32 0, i32 1 + ; CHECK-LLVM: %[[BUF1_SFLN_CLOSURE_ACCESS_LOAD:[0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* %[[BUF1_SFLN_CLOSURE_ACCESS]] + %11 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon.0", %"class._ZTSZ4mainE3$_0.anon.0" addrspace(4)* %this1, i32 0, i32 0 + %12 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* %11, align 8, !tbaa !20 %13 = load i32, i32* %i, align 4, !tbaa !5 - %add7 = add nsw i32 %13, 3 - %idxprom8 = sext i32 %add7 to i64 - ; CHECK-LLVM: getelementptr inbounds [10 x i32], [10 x i32] addrspace(4)* %[[BUF2_SFLN_CLOSURE_ACCESS]]{{.*}}, !llvm.index.group ![[BUF2_SFLN_INDEX_GROUP]] - %arrayidx9 = getelementptr inbounds [10 x i32], [10 x i32] addrspace(4)* %12, i64 0, i64 %idxprom8, !llvm.index.group !20 - %14 = load i32, i32 addrspace(4)* %arrayidx9, align 4, !tbaa !5 - %add10 = add nsw i32 %11, %14 - ; CHECK-SPIRV: InBoundsPtrAccessChain [[TYPE_PTR]] [[BUF2_SFLN_PRE_STORE_ID]] [[THIS_SFLN_LOAD]] [[OFFSET_CONST_0]] [[OFFSET_CONST_1]] + %idxprom5 = sext i32 %13 to i64 + ; CHECK-LLVM: getelementptr inbounds i32, i32 addrspace(4)* %[[BUF1_SFLN_CLOSURE_ACCESS_LOAD]]{{.*}}, !llvm.index.group ![[BUF1_SFLN_INDEX_GROUP]] + %ptridx6 = getelementptr inbounds i32, i32 addrspace(4)* %12, i64 %idxprom5, !llvm.index.group !24 + %14 = load i32, i32 addrspace(4)* %ptridx6, align 4, !tbaa !5 + ; CHECK-SPIRV: InBoundsPtrAccessChain [[TYPE_SFLN_INT_PTR]] [[BUF2_SFLN_PRE_ADD_2_ID]] [[THIS_SFLN_LOAD]] [[OFFSET_CONST_0]] [[OFFSET_CONST_1]] ; CHECK-LLVM: %[[BUF2_SFLN_CLOSURE_ACCESS:[0-9]+]] = getelementptr inbounds %[[CLOSURE_NAME_SFLN]], %[[CLOSURE_NAME_SFLN]] addrspace(4)* %this1, i32 0, i32 1 + ; CHECK-LLVM: %[[BUF2_SFLN_CLOSURE_ACCESS_LOAD:[0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* %[[BUF2_SFLN_CLOSURE_ACCESS]] %15 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon.0", %"class._ZTSZ4mainE3$_0.anon.0" addrspace(4)* %this1, i32 0, i32 1 - %16 = load i32, i32* %i, align 4, !tbaa !5 - %idxprom11 = sext i32 %16 to i64 - ; CHECK-LLVM: getelementptr inbounds [10 x i32], [10 x i32] addrspace(4)* %[[BUF2_SFLN_CLOSURE_ACCESS]]{{.*}}, !llvm.index.group ![[BUF2_SFLN_INDEX_GROUP]] - %arrayidx12 = getelementptr inbounds [10 x i32], [10 x i32] addrspace(4)* %15, i64 0, i64 %idxprom11, !llvm.index.group !20 - %17 = load i32, i32 addrspace(4)* %arrayidx12, align 4, !tbaa !5 - %mul13 = mul nsw i32 %17, %add10 - store i32 %mul13, i32 addrspace(4)* %arrayidx12, align 4, !tbaa !5 + %16 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* %15, align 8, !tbaa !22 + %17 = load i32, i32* %i, align 4, !tbaa !5 + %add7 = add nsw i32 %17, 3 + %idxprom8 = sext i32 %add7 to i64 + ; CHECK-LLVM: getelementptr inbounds i32, i32 addrspace(4)* %[[BUF2_SFLN_CLOSURE_ACCESS_LOAD]]{{.*}}, !llvm.index.group ![[BUF2_SFLN_INDEX_GROUP]] + %ptridx9 = getelementptr inbounds i32, i32 addrspace(4)* %16, i64 %idxprom8, !llvm.index.group !23 + %18 = load i32, i32 addrspace(4)* %ptridx9, align 4, !tbaa !5 + %add10 = add nsw i32 %14, %18 + ; CHECK-SPIRV: InBoundsPtrAccessChain [[TYPE_SFLN_INT_PTR]] [[BUF2_SFLN_PRE_STORE_ID]] [[THIS_SFLN_LOAD]] [[OFFSET_CONST_0]] [[OFFSET_CONST_1]] + ; CHECK-LLVM: %[[BUF2_SFLN_CLOSURE_ACCESS:[0-9]+]] = getelementptr inbounds %[[CLOSURE_NAME_SFLN]], %[[CLOSURE_NAME_SFLN]] addrspace(4)* %this1, i32 0, i32 1 + ; CHECK-LLVM: %[[BUF2_SFLN_CLOSURE_ACCESS_LOAD:[0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* %[[BUF2_SFLN_CLOSURE_ACCESS]] + %19 = getelementptr inbounds %"class._ZTSZ4mainE3$_0.anon.0", %"class._ZTSZ4mainE3$_0.anon.0" addrspace(4)* %this1, i32 0, i32 1 + %20 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* %19, align 8, !tbaa !22 + %21 = load i32, i32* %i, align 4, !tbaa !5 + %idxprom11 = sext i32 %21 to i64 + ; CHECK-LLVM: getelementptr inbounds i32, i32 addrspace(4)* %[[BUF2_SFLN_CLOSURE_ACCESS_LOAD]]{{.*}}, !llvm.index.group ![[BUF2_SFLN_INDEX_GROUP]] + %ptridx12 = getelementptr inbounds i32, i32 addrspace(4)* %20, i64 %idxprom11, !llvm.index.group !23 + %22 = load i32, i32 addrspace(4)* %ptridx12, align 4, !tbaa !5 + %mul13 = mul nsw i32 %22, %add10 + store i32 %mul13, i32 addrspace(4)* %ptridx12, align 4, !tbaa !5 br label %for.inc for.inc: ; preds = %for.body - %18 = load i32, i32* %i, align 4, !tbaa !5 - %inc = add nsw i32 %18, 1 + %23 = load i32, i32* %i, align 4, !tbaa !5 + %inc = add nsw i32 %23, 1 store i32 %inc, i32* %i, align 4, !tbaa !5 ; CHECK-LLVM: br label %{{.*}}, !llvm.loop ![[SFLN_MD_LOOP:[0-9]+]] - br label %for.cond, !llvm.loop !22 + br label %for.cond, !llvm.loop !25 for.end: ; preds = %for.cond.cleanup ret void } -attributes #0 = { convergent norecurse "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "sycl-module-id"="../../../tests/ivdep.cpp" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { convergent norecurse uwtable "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind willreturn } -attributes #2 = { convergent inlinehint norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { convergent inlinehint norecurse nounwind uwtable "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #3 = { nounwind } attributes #4 = { convergent } @@ -554,7 +410,7 @@ attributes #4 = { convergent } !1 = !{i32 1, i32 2} !2 = !{i32 4, i32 100000} !3 = !{!"clang version 12.0.0"} -!4 = !{i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1} +!4 = !{i32 -1, i32 -1} !5 = !{!6, !6, i64 0} !6 = !{!"int", !7, i64 0} !7 = !{!"omnipotent char", !8, i64 0} @@ -587,6 +443,9 @@ attributes #4 = { convergent } !17 = !{!"llvm.loop.ivdep.safelen", i32 2} !18 = distinct !{!18, !19} !19 = !{!"llvm.loop.parallel_access_indices", !11, i32 3} +!20 = !{!21, !10, i64 0} +!21 = !{!"_ZTSZ4mainE3$_1", !10, i64 0, !10, i64 8} +!22 = !{!21, !10, i64 8} ; One-dimensional loop with varying ivdep parameters example ; ; CHECK-LLVM-DAG: ![[BUF1_SFLN_INDEX_GROUP]] = distinct !{} @@ -594,8 +453,8 @@ attributes #4 = { convergent } ; CHECK-LLVM-DAG: ![[SFLN_MD_LOOP]] = distinct !{![[SFLN_MD_LOOP]], ![[IVDEP_BUF2_SFLN:[0-9]+]], ![[IVDEP_BUF1_SFLN:[0-9]+]]} ; CHECK-LLVM-DAG: ![[IVDEP_BUF1_SFLN]] = !{!"llvm.loop.parallel_access_indices", ![[BUF1_SFLN_INDEX_GROUP]], i32 3} ; CHECK-LLVM-DAG: ![[IVDEP_BUF2_SFLN]] = !{!"llvm.loop.parallel_access_indices", ![[BUF2_SFLN_INDEX_GROUP]], i32 2} -!20 = distinct !{} -!21 = distinct !{} -!22 = distinct !{!22, !23, !24} -!23 = !{!"llvm.loop.parallel_access_indices", !21, i32 3} -!24 = !{!"llvm.loop.parallel_access_indices", !20, i32 2} +!23 = distinct !{} +!24 = distinct !{} +!25 = distinct !{!25, !26, !27} +!26 = !{!"llvm.loop.parallel_access_indices", !24, i32 3} +!27 = !{!"llvm.loop.parallel_access_indices", !23, i32 2} diff --git a/llvm-spirv/test/transcoding/SPV_INTEL_fpga_loop_controls/FPGALoopMergeInst.ll b/llvm-spirv/test/transcoding/SPV_INTEL_fpga_loop_controls/FPGALoopMergeInst.ll index a763ccddb889d..470f640444e35 100644 --- a/llvm-spirv/test/transcoding/SPV_INTEL_fpga_loop_controls/FPGALoopMergeInst.ll +++ b/llvm-spirv/test/transcoding/SPV_INTEL_fpga_loop_controls/FPGALoopMergeInst.ll @@ -6,7 +6,7 @@ ; int i = 0; ; int m = 42; -; [[intelfpga::ivdep]] +; [[intel::ivdep]] ; while (i < m) { ; if (i % 2) { ; ++i; @@ -15,7 +15,7 @@ ; } ; i = 0; -; [[intelfpga::ii(2)]] +; [[intel::ii(2)]] ; while (i < m) { ; if (i % 3) { ; ++i; @@ -24,7 +24,7 @@ ; } ; i = 0; -; [[intelfpga::max_concurrency(4)]] +; [[intel::max_concurrency(4)]] ; while (i < m) { ; if (i % 5) { ; ++i; @@ -33,7 +33,7 @@ ; } ; i = 0; -; [[intelfpga::ivdep(2)]] +; [[intel::ivdep(2)]] ; while (true) { ; if (i % 2) { ; ++i; @@ -46,14 +46,14 @@ ; void loop_pipelining() { ; int a[10]; -; [[intelfpga::disable_loop_pipelining]] +; [[intel::disable_loop_pipelining]] ; for (int i = 0; i != 10; ++i) ; a[i] = 0; ; } ; void loop_coalesce() { ; int i = 0, m = 42; -; [[intelfpga::loop_coalesce(4)]] +; [[intel::loop_coalesce(4)]] ; while (i < m) { ; if (i % 2) { ; ++i; @@ -61,7 +61,7 @@ ; } ; } ; i = 0; -; [[intelfpga::loop_coalesce]] +; [[intel::loop_coalesce]] ; while (i < m) { ; if (i % 3) { ; ++i; @@ -72,21 +72,28 @@ ; void max_interleaving() { ; int a[10]; -; [[intelfpga::max_interleaving(3)]] +; [[intel::max_interleaving(3)]] ; for (int i = 0; i != 10; ++i) ; a[i] = 0; ; } ; void speculated_iterations() { ; int a[10]; -; [[intelfpga::speculated_iterations(4)]] +; [[intel::speculated_iterations(4)]] +; for (int i = 0; i != 10; ++i) +; a[i] = 0; +; } +; +; void nofusion() { +; int a[10]; +; [[intel::nofusion]] ; for (int i = 0; i != 10; ++i) ; a[i] = 0; ; } ; TODO: This source code will result in different LLVM IR after ; rev [a47242e4b2c1c9] of https://github.com/intel/llvm (the -; [[intelfpga::ivdep]] attribute will be represented otherwise). +; [[intel::ivdep]] attribute will be represented otherwise). ; It's worth factoring out the old representation's translation: ; (!"llvm.loop.ivdep.*" <-> LoopControlDependency*Mask) ; into a separate test file @@ -341,9 +348,9 @@ while.end: ; preds = %while.cond br label %while.cond1 ; Per SPIR-V spec, LoopControlLoopCoalesceINTELMask = 0x100000 (1048576) -; CHECK-SPIRV: 4 LoopMerge {{[0-9]+}} {{[0-9]+}} 1048576 +; CHECK-SPIRV: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 1048576 0 ; CHECK-SPIRV-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} -; CHECK-SPIRV-NEGATIVE-NOT: 4 LoopMerge {{[0-9]+}} {{[0-9]+}} 1048576 +; CHECK-SPIRV-NEGATIVE-NOT: 5 LoopMerge {{[0-9]+}} {{[0-9]+}} 1048576 0 while.cond1: ; preds = %if.end8, %if.then6, %while.end %4 = load i32, i32* %i, align 4 %5 = load i32, i32* %m, align 4 @@ -437,6 +444,40 @@ for.end: ; preds = %for.cond ret void } +; Function Attrs: noinline nounwind optnone +define spir_func void @nofusion() #3 { +entry: + %a = alloca [10 x i32], align 4 + %i = alloca i32, align 4 + store i32 0, i32* %i, align 4 + br label %for.cond + +; Per SPIR-V spec, LoopControlNoFusionINTELMask = 0x800000 (8388608) +; CHECK-SPIRV: 4 LoopMerge {{[0-9]+}} {{[0-9]+}} 8388608 +; CHECK-SPIRV-NEXT: 4 BranchConditional {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} +; CHECK-SPIRV-NEGATIVE-NOT: 4 LoopMerge {{[0-9]+}} {{[0-9]+}} 8388608 +for.cond: ; preds = %for.inc, %entry + %0 = load i32, i32* %i, align 4 + %cmp = icmp ne i32 %0, 10 + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + %1 = load i32, i32* %i, align 4 + %idxprom = sext i32 %1 to i64 + %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* %a, i64 0, i64 %idxprom + store i32 0, i32* %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body + %2 = load i32, i32* %i, align 4 + %inc = add nsw i32 %2, 1 + store i32 %inc, i32* %i, align 4 + br label %for.cond, !llvm.loop !29 + +for.end: ; preds = %for.cond + ret void +} + attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "sycl-module-id"="FPGALoopMergeInst.cpp" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind willreturn } attributes #2 = { inlinehint nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } @@ -477,6 +518,8 @@ attributes #4 = { nounwind } !26 = !{!"llvm.loop.max_interleaving.count", i32 3} !27 = distinct !{!27, !28} !28 = !{!"llvm.loop.intel.speculated.iterations.count", i32 4} +!29 = distinct !{!29, !30} +!30 = !{!"llvm.loop.fusion.disable"} ; CHECK-LLVM: br label %while.cond, !llvm.loop ![[MD_A:[0-9]+]] ; CHECK-LLVM: br label %while.cond{{[0-9]+}}, !llvm.loop ![[MD_B:[0-9]+]] @@ -487,6 +530,7 @@ attributes #4 = { nounwind } ; CHECK-LLVM: br label %while.cond{{[0-9]+}}, !llvm.loop ![[MD_G:[0-9]+]] ; CHECK-LLVM: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_H:[0-9]+]] ; CHECK-LLVM: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_I:[0-9]+]] +; CHECK-LLVM: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_NF:[0-9]+]] ; CHECK-LLVM: ![[MD_A]] = distinct !{![[MD_A]], ![[MD_ivdep_enable:[0-9]+]]} ; CHECK-LLVM: ![[MD_ivdep_enable]] = !{!"llvm.loop.ivdep.enable"} @@ -507,3 +551,5 @@ attributes #4 = { nounwind } ; CHECK-LLVM: ![[MD_max_interleaving]] = !{!"llvm.loop.max_interleaving.count", i32 3} ; CHECK-LLVM: ![[MD_I]] = distinct !{![[MD_I]], ![[MD_spec_iterations:[0-9]+]]} ; CHECK-LLVM: ![[MD_spec_iterations]] = !{!"llvm.loop.intel.speculated.iterations.count", i32 4} +; CHECK-LLVM: ![[MD_NF]] = distinct !{![[MD_NF]], ![[MD_nofusion:[0-9]+]]} +; CHECK-LLVM: ![[MD_nofusion]] = !{!"llvm.loop.fusion.disable"} diff --git a/llvm-spirv/test/transcoding/SpecConstantComposite.ll b/llvm-spirv/test/transcoding/SpecConstantComposite.ll new file mode 100644 index 0000000000000..eb2ccd5d31667 --- /dev/null +++ b/llvm-spirv/test/transcoding/SpecConstantComposite.ll @@ -0,0 +1,136 @@ +; RUN: llvm-as < %s -o %t.bc +; RUN: llvm-spirv %t.bc -spirv-text -o %t.spt +; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV +; RUN: llvm-spirv %t.bc -o %t.spv +; RUN: spirv-val %t.spv +; RUN: llvm-spirv %t.spv -r -o - | llvm-dis -o %t.ll +; RUN: FileCheck < %t.ll %s --check-prefix=CHECK-LLVM + +; CHECK-SPIRV: Decorate [[#SC3:]] SpecId 3 +; CHECK-SPIRV: Decorate [[#SC4:]] SpecId 4 +; CHECK-SPIRV: Decorate [[#SC6:]] SpecId 6 +; CHECK-SPIRV: Decorate [[#SC7:]] SpecId 7 +; CHECK-SPIRV: Decorate [[#SC10:]] SpecId 10 +; CHECK-SPIRV: Decorate [[#SC11:]] SpecId 11 + +; CHECK-SPIRV-DAG: TypeInt [[#Int:]] 32 +; CHECK-SPIRV-DAG: TypeFloat [[#Float:]] 32 +; CHECK-SPIRV-DAG: TypeStruct [[#StructA:]] [[#Int]] [[#Float]] +; CHECK-SPIRV-DAG: TypeArray [[#Array:]] [[#StructA]] [[#]] +; CHECK-SPIRV-DAG: TypeVector [[#Vector:]] [[#Int]] 2 +; CHECK-SPIRV-DAG: TypeStruct [[#Struct:]] [[#Vector]] +; CHECK-SPIRV-DAG: TypeStruct [[#POD_TYPE:]] [[#Array]] [[#Struct]] + +source_filename = "./SpecConstantComposite.ll" +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64" +target triple = "spir64-unknown-unknown-sycldevice" + +%struct._ZTS3POD.POD = type { [2 x %struct._ZTS1A.A], %"class._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec" } +%struct._ZTS1A.A = type { i32, float } +%"class._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec" = type { <2 x i32> } +%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range" = type { %"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" } +%"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" = type { [1 x i64] } +%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id" = type { %"class._ZTSN2cl4sycl6detail5arrayILi1EEE.cl::sycl::detail::array" } + +$_ZTS4Test = comdat any + +; Function Attrs: convergent norecurse uwtable +define weak_odr dso_local spir_kernel void @_ZTS4Test(%struct._ZTS3POD.POD addrspace(1)* %_arg_, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_1, %"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range"* byval(%"class._ZTSN2cl4sycl5rangeILi1EEE.cl::sycl::range") align 8 %_arg_2, %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* byval(%"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id") align 8 %_arg_3) local_unnamed_addr #0 comdat !kernel_arg_buffer_location !4 { +entry: + %ref.tmp.i = alloca %struct._ZTS3POD.POD, align 8 + %0 = getelementptr inbounds %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id", %"class._ZTSN2cl4sycl2idILi1EEE.cl::sycl::id"* %_arg_3, i64 0, i32 0, i32 0, i64 0 + %1 = load i64, i64* %0, align 8 + %add.ptr.i = getelementptr inbounds %struct._ZTS3POD.POD, %struct._ZTS3POD.POD addrspace(1)* %_arg_, i64 %1 + %2 = bitcast %struct._ZTS3POD.POD* %ref.tmp.i to i8* + call void @llvm.lifetime.start.p0i8(i64 24, i8* nonnull %2) #2 + %3 = addrspacecast %struct._ZTS3POD.POD* %ref.tmp.i to %struct._ZTS3POD.POD addrspace(4)* + + %4 = call i32 @_Z20__spirv_SpecConstantii(i32 3, i32 1) +; CHECK-SPIRV-DAG: SpecConstant [[#Int]] [[#SC3]] 1 + + %5 = call float @_Z20__spirv_SpecConstantif(i32 4, float 0.000000e+00) +; CHECK-SPIRV-DAG: SpecConstant [[#Float]] [[#SC4]] 0 + + %6 = call %struct._ZTS1A.A @_Z29__spirv_SpecConstantCompositeif(i32 %4, float %5) +; CHECK-SPIRV-DAG: SpecConstantComposite [[#StructA]] [[#SC_StructA0:]] [[#SC3]] [[#SC4]] + + %7 = call i32 @_Z20__spirv_SpecConstantii(i32 6, i32 35) +; CHECK-SPIRV-DAG: SpecConstant [[#Int]] [[#SC6]] 35 + + %8 = call float @_Z20__spirv_SpecConstantif(i32 7, float 0.000000e+00) +; CHECK-SPIRV-DAG: SpecConstant [[#Float]] [[#SC7]] 0 + + %9 = call %struct._ZTS1A.A @_Z29__spirv_SpecConstantCompositeif(i32 %7, float %8) +; CHECK-SPIRV-DAG: SpecConstantComposite [[#StructA]] [[#SC_StructA1:]] [[#SC6]] [[#SC7]] + + %10 = call [2 x %struct._ZTS1A.A] @_Z29__spirv_SpecConstantCompositestruct._ZTS1A.Astruct._ZTS1A.A(%struct._ZTS1A.A %6, %struct._ZTS1A.A %9) +; CHECK-SPIRV-DAG: SpecConstantComposite [[#Array]] [[#SC_Array:]] [[#SC_StructA0]] [[#SC_StructA1]] + + %11 = call i32 @_Z20__spirv_SpecConstantii(i32 10, i32 45) +; CHECK-SPIRV-DAG: SpecConstant [[#Int]] [[#SC10]] 45 + + %12 = call i32 @_Z20__spirv_SpecConstantii(i32 11, i32 55) +; CHECK-SPIRV-DAG: SpecConstant [[#Int]] [[#SC11]] 55 + + %13 = call <2 x i32> @_Z29__spirv_SpecConstantCompositeii(i32 %11, i32 %12) +; CHECK-SPIRV-DAG: SpecConstantComposite [[#Vector]] [[#SC_Vector:]] [[#SC10]] [[#SC11]] + + %14 = call %"class._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec" @_Z29__spirv_SpecConstantCompositeDv2_i(<2 x i32> %13) +; CHECK-SPIRV-DAG: SpecConstantComposite [[#Struct]] [[#SC_Struct:]] [[#SC_Vector]] + + %15 = call %struct._ZTS3POD.POD @"_Z29__spirv_SpecConstantCompositeAstruct._ZTS1A.Aclass._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec"([2 x %struct._ZTS1A.A] %10, %"class._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec" %14), !SYCL_SPEC_CONST_SYM_ID !5 +; CHECK-SPIRV-DAG: SpecConstantComposite [[#POD_TYPE]] [[#SC_POD:]] [[#SC_Array]] [[#SC_Struct]] + + store %struct._ZTS3POD.POD %15, %struct._ZTS3POD.POD addrspace(4)* %3, align 8 +; CHECK-SPIRV-DAG: Store [[#]] [[#SC_POD]] +; CHECK-LLVM: store %struct._ZTS3POD.POD { [2 x %struct._ZTS1A.A] [%struct._ZTS1A.A { i32 1, float 0.000000e+00 }, %struct._ZTS1A.A { i32 35, float 0.000000e+00 }], %"class._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec" { <2 x i32> } } + + %16 = bitcast %struct._ZTS3POD.POD addrspace(1)* %add.ptr.i to i8 addrspace(1)* + %17 = addrspacecast i8 addrspace(1)* %16 to i8 addrspace(4)* + call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 8 dereferenceable(24) %17, i8* nonnull align 8 dereferenceable(24) %2, i64 24, i1 false), !tbaa.struct !6 + call void @llvm.lifetime.end.p0i8(i64 24, i8* nonnull %2) #2 + ret void +} + +; Function Attrs: argmemonly nounwind willreturn +declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1 + +; Function Attrs: argmemonly nounwind willreturn +declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1 + +; Function Attrs: argmemonly nounwind willreturn +declare void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg) #1 + +declare i32 @_Z20__spirv_SpecConstantii(i32, i32) + +declare float @_Z20__spirv_SpecConstantif(i32, float) + +declare %struct._ZTS1A.A @_Z29__spirv_SpecConstantCompositeif(i32, float) + +declare [2 x %struct._ZTS1A.A] @_Z29__spirv_SpecConstantCompositestruct._ZTS1A.Astruct._ZTS1A.A(%struct._ZTS1A.A, %struct._ZTS1A.A) + +declare <2 x i32> @_Z29__spirv_SpecConstantCompositeii(i32, i32) + +declare %"class._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec" @_Z29__spirv_SpecConstantCompositeDv2_i(<2 x i32>) + +declare %struct._ZTS3POD.POD @"_Z29__spirv_SpecConstantCompositeAstruct._ZTS1A.Aclass._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec"([2 x %struct._ZTS1A.A], %"class._ZTSN2cl4sycl3vecIiLi2EEE.cl::sycl::vec") + +attributes #0 = { convergent norecurse uwtable "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "sycl-module-id"="../sycl/test/spec_const/composite.cpp" "tune-cpu"="generic" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { argmemonly nounwind willreturn } +attributes #2 = { nounwind } + +!llvm.module.flags = !{!0} +!opencl.spir.version = !{!1} +!spirv.Source = !{!2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, i32 2} +!2 = !{i32 4, i32 100000} +!3 = !{!"clang version 12.0.0 (/data/github.com/intel/llvm/clang 56ee5b054b5a1f2f703722fc414fcb05af18b40a)"} +!4 = !{i32 -1, i32 -1, i32 -1, i32 -1} +!5 = !{!"_ZTS3POD", i32 3, i32 4, i32 6, i32 7, i32 10, i32 11} +!6 = !{i64 0, i64 16, !7, i64 16, i64 8, !7} +!7 = !{!8, !8, i64 0} +!8 = !{!"omnipotent char", !9, i64 0} +!9 = !{!"Simple C++ TBAA"} diff --git a/llvm-spirv/test/transcoding/atomics.spt b/llvm-spirv/test/transcoding/atomics.spt index f23e69f03f817..eabae2ca13010 100644 --- a/llvm-spirv/test/transcoding/atomics.spt +++ b/llvm-spirv/test/transcoding/atomics.spt @@ -94,3 +94,25 @@ ; CHECK-LLVM-20: call spir_func void @_Z21atomic_store_explicitPU3AS4VU7_Atomicii12memory_order12memory_scope(i32 addrspace(4)* %object.as14, i32 %desired, i32 5, i32 2) [[attr]] ; CHECK-LLVM-20: call spir_func i1 @_Z33atomic_flag_test_and_set_explicitPU3AS4VU7_Atomici12memory_order12memory_scope(i32 addrspace(4)* %object.as15, i32 5, i32 2) [[attr]] ; CHECK-LLVM-20: call spir_func void @_Z26atomic_flag_clear_explicitPU3AS4VU7_Atomici12memory_order12memory_scope(i32 addrspace(4)* %object.as16, i32 5, i32 2) [[attr]] + +; RUN: llvm-spirv -r %t1.spv -o %t2.bc --spirv-target-env="SPV-IR" +; RUN: llvm-dis < %t2.bc | FileCheck %s --check-prefix=CHECK-LLVM-SPV-IR + +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z24__spirv_AtomicIIncrementPU3AS1iii(i32 addrspace(1)* %dst, i32 1, i32 16) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z24__spirv_AtomicIDecrementPU3AS1iii(i32 addrspace(1)* %dst, i32 1, i32 16) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z18__spirv_AtomicSMaxPU3AS1iiii(i32 addrspace(1)* %dst, i32 1, i32 16, i32 0) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z18__spirv_AtomicUMaxPU3AS1iiii(i32 addrspace(1)* %dst, i32 1, i32 16, i32 0) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z18__spirv_AtomicSMinPU3AS1iiii(i32 addrspace(1)* %dst, i32 1, i32 16, i32 0) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z18__spirv_AtomicUMinPU3AS1iiii(i32 addrspace(1)* %dst, i32 1, i32 16, i32 0) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z18__spirv_AtomicIAddPU3AS1iiii(i32 addrspace(1)* %dst, i32 1, i32 16, i32 1) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z18__spirv_AtomicISubPU3AS1iiii(i32 addrspace(1)* %dst, i32 1, i32 16, i32 1) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z16__spirv_AtomicOrPU3AS1iiii(i32 addrspace(1)* %dst, i32 1, i32 16, i32 1) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z17__spirv_AtomicXorPU3AS1iiii(i32 addrspace(1)* %dst, i32 1, i32 16, i32 1) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z17__spirv_AtomicAndPU3AS1iiii(i32 addrspace(1)* %dst, i32 1, i32 16, i32 1) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z29__spirv_AtomicCompareExchangePU3AS1iiiiii(i32 addrspace(1)* %dst, i32 1, i32 16, i32 16, i32 1, i32 0) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z22__spirv_AtomicExchangePU3AS1iiii(i32 addrspace(1)* %dst, i32 1, i32 16, i32 1) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i32 @_Z18__spirv_AtomicLoadPU3AS1iii(i32 addrspace(1)* %object, i32 1, i32 16) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func void @_Z19__spirv_AtomicStorePU3AS1iiii(i32 addrspace(1)* %object, i32 1, i32 16, i32 %desired) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func i1 @_Z28__spirv_AtomicFlagTestAndSetPU3AS1iii(i32 addrspace(1)* %object, i32 1, i32 16) #[[#attr:]] +; CHECK-LLVM-SPV-IR: call spir_func void @_Z23__spirv_AtomicFlagClearPU3AS1iii(i32 addrspace(1)* %object, i32 1, i32 16) #[[#attr:]] + diff --git a/llvm-spirv/test/transcoding/fp_contract_reassoc_fast_mode.ll b/llvm-spirv/test/transcoding/fp_contract_reassoc_fast_mode.ll new file mode 100644 index 0000000000000..351654c639151 --- /dev/null +++ b/llvm-spirv/test/transcoding/fp_contract_reassoc_fast_mode.ll @@ -0,0 +1,56 @@ +; RUN: llvm-as %s -o %t.bc +; RUN: llvm-spirv -spirv-text %t.bc -o - | FileCheck %s --check-prefix=CHECK-SPIRV-OFF +; RUN: llvm-spirv --spirv-ext=+SPV_INTEL_fp_fast_math_mode -spirv-text %t.bc -o - | FileCheck %s --check-prefix=CHECK-SPIRV-ON +; RUN: llvm-spirv --spirv-ext=+SPV_INTEL_fp_fast_math_mode %t.bc -o %t.spv +; RUN: llvm-spirv -r %t.spv -o - | llvm-dis -o - | FileCheck %s --check-prefix=CHECK-LLVM + +; CHECK-SPIRV-ON: 2 Capability FPFastMathModeINTEL +; CHECK-SPIRV-ON: 3 Name [[mu:[0-9]+]] "mul" +; CHECK-SPIRV-ON: 3 Name [[su:[0-9]+]] "sub" +; CHECK-SPIRV-ON: 4 Decorate [[mu]] FPFastMathMode 65536 +; CHECK-SPIRV-ON: 4 Decorate [[su]] FPFastMathMode 131072 + +; CHECK-SPIRV-OFF-NOT: 2 Capability FPFastMathModeINTEL +; CHECK-SPIRV-OFF: 3 Name [[mu:[0-9]+]] "mul" +; CHECK-SPIRV-OFF: 3 Name [[su:[0-9]+]] "sub" +; CHECK-SPIRV-OFF-NOT: 4 Decorate [[mu]] FPFastMathMode 65536 +; CHECK-SPIRV-OFF-NOT: 4 Decorate [[su]] FPFastMathMode 131072 + +; CHECK-LLVM: %mul = fmul contract float %0, %1 +; CHECK-LLVM: %sub = fsub reassoc float %2, %3 + +target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64" +target triple = "spir" + +; Function Attrs: convergent noinline norecurse nounwind optnone +define spir_kernel void @test(float %a, float %b) #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 { +entry: + %a.addr = alloca float, align 4 + %b.addr = alloca float, align 4 + store float %a, float* %a.addr, align 4 + store float %b, float* %b.addr, align 4 + %0 = load float, float* %a.addr, align 4 + %1 = load float, float* %a.addr, align 4 + %mul = fmul contract float %0, %1 + store float %mul, float* %b.addr, align 4 + %2 = load float, float* %b.addr, align 4 + %3 = load float, float* %b.addr, align 4 + %sub = fsub reassoc float %2, %3 + store float %sub, float* %b.addr, align 4 + ret void +} + +attributes #0 = { convergent noinline norecurse nounwind optnone "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.module.flags = !{!0} +!opencl.ocl.version = !{!1} +!opencl.spir.version = !{!1} +!llvm.ident = !{!2} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 2, i32 0} +!2 = !{!"clang version 12.0.0 (https://github.com/intel/llvm.git 5cf8088c994778561c8584d5433d7d32618725b2)"} +!3 = !{i32 0, i32 0} +!4 = !{!"none", !"none"} +!5 = !{!"float", !"float"} +!6 = !{!"", !""} diff --git a/llvm/bindings/ocaml/llvm/llvm.ml b/llvm/bindings/ocaml/llvm/llvm.ml index fdef6eb176d6b..723ac66ffd05c 100644 --- a/llvm/bindings/ocaml/llvm/llvm.ml +++ b/llvm/bindings/ocaml/llvm/llvm.ml @@ -314,6 +314,7 @@ module ValueKind = struct | GlobalIFunc | GlobalVariable | UndefValue + | PoisonValue | Instruction of Opcode.t end @@ -547,8 +548,10 @@ external const_null : lltype -> llvalue = "LLVMConstNull" external const_all_ones : (*int|vec*)lltype -> llvalue = "LLVMConstAllOnes" external const_pointer_null : lltype -> llvalue = "LLVMConstPointerNull" external undef : lltype -> llvalue = "LLVMGetUndef" +external poison : lltype -> llvalue = "LLVMGetPoison" external is_null : llvalue -> bool = "llvm_is_null" external is_undef : llvalue -> bool = "llvm_is_undef" +external is_poison : llvalue -> bool = "llvm_is_poison" external constexpr_opcode : llvalue -> Opcode.t = "llvm_constexpr_get_opcode" (*--... Operations on instructions .........................................--*) diff --git a/llvm/bindings/ocaml/llvm/llvm.mli b/llvm/bindings/ocaml/llvm/llvm.mli index 04e27438a479b..ba9e6c1f21202 100644 --- a/llvm/bindings/ocaml/llvm/llvm.mli +++ b/llvm/bindings/ocaml/llvm/llvm.mli @@ -347,6 +347,7 @@ module ValueKind : sig | GlobalIFunc | GlobalVariable | UndefValue + | PoisonValue | Instruction of Opcode.t end @@ -842,6 +843,10 @@ val const_pointer_null : lltype -> llvalue See the method [llvm::UndefValue::get]. *) val undef : lltype -> llvalue +(** [poison ty] returns the poison value of the type [ty]. + See the method [llvm::PoisonValue::get]. *) +val poison : lltype -> llvalue + (** [is_null v] returns [true] if the value [v] is the null (zero) value. See the method [llvm::Constant::isNullValue]. *) val is_null : llvalue -> bool @@ -850,6 +855,10 @@ val is_null : llvalue -> bool otherwise. Similar to [llvm::isa]. *) val is_undef : llvalue -> bool +(** [is_poison v] returns [true] if the value [v] is a poison value, [false] + otherwise. Similar to [llvm::isa]. *) +val is_poison : llvalue -> bool + (** [constexpr_opcode v] returns an [Opcode.t] corresponding to constexpr value [v], or [Opcode.Invalid] if [v] is not a constexpr. *) val constexpr_opcode : llvalue -> Opcode.t diff --git a/llvm/bindings/ocaml/llvm/llvm_ocaml.c b/llvm/bindings/ocaml/llvm/llvm_ocaml.c index 1552abf29c039..5845783278d95 100644 --- a/llvm/bindings/ocaml/llvm/llvm_ocaml.c +++ b/llvm/bindings/ocaml/llvm/llvm_ocaml.c @@ -627,6 +627,7 @@ enum ValueKind { GlobalIFunc, GlobalVariable, UndefValue, + PoisonValue, Instruction }; @@ -669,6 +670,7 @@ CAMLprim value llvm_classify_value(LLVMValueRef Val) { DEFINE_CASE(Val, MDNode); DEFINE_CASE(Val, MDString); DEFINE_CASE(Val, UndefValue); + DEFINE_CASE(Val, PoisonValue); failwith("Unknown Value class"); } @@ -762,6 +764,11 @@ CAMLprim value llvm_is_undef(LLVMValueRef Val) { return Val_bool(LLVMIsUndef(Val)); } +/* llvalue -> bool */ +CAMLprim value llvm_is_poison(LLVMValueRef Val) { + return Val_bool(LLVMIsPoison(Val)); +} + /* llvalue -> Opcode.t */ CAMLprim value llvm_constexpr_get_opcode(LLVMValueRef Val) { return LLVMIsAConstantExpr(Val) ? diff --git a/llvm/cmake/modules/AddLLVM.cmake b/llvm/cmake/modules/AddLLVM.cmake index e3a20a054975f..a3e9eaeeb2622 100644 --- a/llvm/cmake/modules/AddLLVM.cmake +++ b/llvm/cmake/modules/AddLLVM.cmake @@ -228,14 +228,6 @@ function(add_link_opts target_name) LINK_FLAGS " -Wl,-O3") endif() - if(LLVM_LINKER_IS_GOLD) - # With gold gc-sections is always safe. - set_property(TARGET ${target_name} APPEND_STRING PROPERTY - LINK_FLAGS " -Wl,--gc-sections") - # Note that there is a bug with -Wl,--icf=safe so it is not safe - # to enable. See https://sourceware.org/bugzilla/show_bug.cgi?id=17704. - endif() - if(NOT LLVM_NO_DEAD_STRIP) if(${CMAKE_SYSTEM_NAME} MATCHES "Darwin") # ld64's implementation of -dead_strip breaks tools that use plugins. @@ -250,12 +242,7 @@ function(add_link_opts target_name) set_property(TARGET ${target_name} APPEND_STRING PROPERTY LINK_FLAGS " -Wl,-z,discard-unused=sections") endif() - elseif(NOT WIN32 AND NOT LLVM_LINKER_IS_GOLD AND - NOT CMAKE_SYSTEM_NAME MATCHES "OpenBSD|AIX|OS390") - # Object files are compiled with -ffunction-data-sections. - # Versions of bfd ld < 2.23.1 have a bug in --gc-sections that breaks - # tools that use plugins. Always pass --gc-sections once we require - # a newer linker. + elseif(NOT WIN32 AND NOT CMAKE_SYSTEM_NAME MATCHES "OpenBSD|AIX|OS390") # TODO Revisit this later on z/OS. set_property(TARGET ${target_name} APPEND_STRING PROPERTY LINK_FLAGS " -Wl,--gc-sections") diff --git a/llvm/cmake/modules/FindGRPC.cmake b/llvm/cmake/modules/FindGRPC.cmake index f2c9bee38c93b..8fdb3506dff17 100644 --- a/llvm/cmake/modules/FindGRPC.cmake +++ b/llvm/cmake/modules/FindGRPC.cmake @@ -40,6 +40,8 @@ else() endif() # On macOS the libraries are typically installed via Homebrew and are not on # the system path. + set(GRPC_OPTS "") + set(PROTOBUF_OPTS "") if (${APPLE}) find_program(HOMEBREW brew) # If Homebrew is not found, the user might have installed libraries @@ -57,28 +59,22 @@ else() # system path. if (GRPC_HOMEBREW_RETURN_CODE EQUAL "0") include_directories(${GRPC_HOMEBREW_PATH}/include) - find_library(GRPC_LIBRARY - grpc++ - PATHS ${GRPC_HOMEBREW_PATH}/lib - NO_DEFAULT_PATH - REQUIRED) - add_library(grpc++ UNKNOWN IMPORTED GLOBAL) - set_target_properties(grpc++ PROPERTIES - IMPORTED_LOCATION ${GRPC_LIBRARY}) + list(APPEND GRPC_OPTS PATHS ${GRPC_HOMEBREW_PATH}/lib NO_DEFAULT_PATH) endif() if (PROTOBUF_HOMEBREW_RETURN_CODE EQUAL "0") include_directories(${PROTOBUF_HOMEBREW_PATH}/include) - find_library(PROTOBUF_LIBRARY - protobuf - PATHS ${PROTOBUF_HOMEBREW_PATH}/lib - NO_DEFAULT_PATH - REQUIRED) - add_library(protobuf UNKNOWN IMPORTED GLOBAL) - set_target_properties(protobuf PROPERTIES - IMPORTED_LOCATION ${PROTOBUF_LIBRARY}) + list(APPEND PROTOBUF_OPTS PATHS ${PROTOBUF_HOMEBREW_PATH}/lib NO_DEFAULT_PATH) endif() endif() endif() + find_library(GRPC_LIBRARY grpc++ $GRPC_OPTS REQUIRED) + add_library(grpc++ UNKNOWN IMPORTED GLOBAL) + message(STATUS "Using grpc++: " ${GRPC_LIBRARY}) + set_target_properties(grpc++ PROPERTIES IMPORTED_LOCATION ${GRPC_LIBRARY}) + find_library(PROTOBUF_LIBRARY protobuf $PROTOBUF_OPTS REQUIRED) + message(STATUS "Using protobuf: " ${PROTOBUF_LIBRARY}) + add_library(protobuf UNKNOWN IMPORTED GLOBAL) + set_target_properties(protobuf PROPERTIES IMPORTED_LOCATION ${PROTOBUF_LIBRARY}) endif() # Proto headers are generated in ${CMAKE_CURRENT_BINARY_DIR}. @@ -112,7 +108,7 @@ function(generate_protos LibraryName ProtoFile) add_clang_library(${LibraryName} ${GeneratedProtoSource} PARTIAL_SOURCES_INTENDED - LINK_LIBS grpc++ protobuf) + LINK_LIBS PUBLIC grpc++ protobuf) # Ensure dependency headers are generated before dependent protos are built. # DEPENDS arg is a list of "Foo.proto". While they're logically relative to diff --git a/llvm/cmake/modules/LLVM-Build.cmake b/llvm/cmake/modules/LLVM-Build.cmake index ce56273c5a1da..525186cbbb19b 100644 --- a/llvm/cmake/modules/LLVM-Build.cmake +++ b/llvm/cmake/modules/LLVM-Build.cmake @@ -11,12 +11,9 @@ function(LLVMBuildGenerateCFragment) list(APPEND all_component_libdeps ${component_name}) endforeach() list(APPEND llvmbuild_components all) - list(APPEND llvmbuild_components all-targets) - list(APPEND llvmbuild_components Engine) - list(APPEND llvmbuild_components Native) - list(APPEND llvmbuild_components NativeCodeGen) - foreach(llvm_target_to_build ${LLVM_TARGETS_TO_BUILD}) - list(APPEND llvmbuild_components ${llvm_target_to_build}) + foreach(llvm_component all-targets Engine Native NativeCodeGen ${LLVM_TARGETS_TO_BUILD}) + list(APPEND llvmbuild_components ${llvm_component}) + list(APPEND all_component_libdeps ${llvm_component}) endforeach() list(LENGTH llvmbuild_components llvmbuild_components_size) diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 750779342466b..85cd045c598fd 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -3144,14 +3144,17 @@ A kernel descriptor consists of the information needed by CP to initiate the execution of a kernel, including the entry point address of the machine code that implements the kernel. -Kernel Descriptor for GFX6-GFX10 -++++++++++++++++++++++++++++++++ +Code Object V3 Kernel Descriptor for GFX6-GFX10 (--amdhsa-code-object-version=3) +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=+++++++++ CP microcode requires the Kernel descriptor to be allocated on 64-byte alignment. - .. table:: Kernel Descriptor for GFX6-GFX10 - :name: amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table +The fields used by CP for code objects before V3 also match those specified in +:ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`. + + .. table:: Code Object V3 Kernel Descriptor for GFX6-GFX10 + :name: amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3 ======= ======= =============================== ============================ Bits Size Field Name Description @@ -3235,8 +3238,12 @@ alignment. - If 1 execute in native wavefront size 32 mode. - 463:459 5 bits Reserved, must be 0. - 511:464 6 bytes Reserved, must be 0. + 463:459 1 bit Reserved, must be 0. + 464 1 bit RESERVED_464 Deprecated, must be 0. + 467:465 3 bits Reserved, must be 0. + 468 1 bit RESERVED_468 Deprecated, must be 0. + 469:471 3 bits Reserved, must be 0. + 511:472 5 bytes Reserved, must be 0. 512 **Total size 64 bytes.** ======= ==================================================================== @@ -8746,25 +8753,25 @@ terminated by an ``.end_amdhsa_kernel`` directive. Directive Default Supported On Description ======================================================== =================== ============ =================== ``.amdhsa_group_segment_fixed_size`` 0 GFX6-GFX10 Controls GROUP_SEGMENT_FIXED_SIZE in - :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`. ``.amdhsa_private_segment_fixed_size`` 0 GFX6-GFX10 Controls PRIVATE_SEGMENT_FIXED_SIZE in - :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`. ``.amdhsa_user_sgpr_private_segment_buffer`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in - :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`. ``.amdhsa_user_sgpr_dispatch_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_DISPATCH_PTR in - :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`. ``.amdhsa_user_sgpr_queue_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_QUEUE_PTR in - :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`. ``.amdhsa_user_sgpr_kernarg_segment_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in - :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`. ``.amdhsa_user_sgpr_dispatch_id`` 0 GFX6-GFX10 Controls ENABLE_SGPR_DISPATCH_ID in - :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`. ``.amdhsa_user_sgpr_flat_scratch_init`` 0 GFX6-GFX10 Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in - :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`. ``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in - :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. + :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`. ``.amdhsa_wavefront_size32`` Target GFX10 Controls ENABLE_WAVEFRONT_SIZE32 in - Feature :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. + Feature :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`. Specific (-wavefrontsize64) ``.amdhsa_system_sgpr_private_segment_wavefront_offset`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET in @@ -8821,7 +8828,7 @@ terminated by an ``.end_amdhsa_kernel`` directive. ``.amdhsa_fp16_overflow`` 0 GFX9-GFX10 Controls FP16_OVFL in :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. ``.amdhsa_workgroup_processor_mode`` Target GFX10 Controls ENABLE_WGP_MODE in - Feature :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. + Feature :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`. Specific (-cumode) ``.amdhsa_memory_ordered`` 1 GFX10 Controls MEM_ORDERED in diff --git a/llvm/docs/CommandGuide/index.rst b/llvm/docs/CommandGuide/index.rst index f822be96ceb06..f6a1fa970642b 100644 --- a/llvm/docs/CommandGuide/index.rst +++ b/llvm/docs/CommandGuide/index.rst @@ -74,5 +74,6 @@ Developer Tools tblgen lit llvm-exegesis - llvm-pdbutil llvm-locstats + llvm-pdbutil + llvm-profgen diff --git a/llvm/docs/CommandGuide/llvm-profgen.rst b/llvm/docs/CommandGuide/llvm-profgen.rst new file mode 100644 index 0000000000000..d9f9692f60117 --- /dev/null +++ b/llvm/docs/CommandGuide/llvm-profgen.rst @@ -0,0 +1,50 @@ +llvm-profgen - LLVM SPGO profile generation tool +================================================ + +.. program:: llvm-profgen + +SYNOPSIS +-------- + +:program:`llvm-profgen` [*commands*] [*options*] + +DESCRIPTION +----------- + +The :program:`llvm-profgen` utility generates a profile data file +from given perf script data files for sample-based profile guided +optimization(SPGO). + +COMMANDS +-------- +At least one of the following commands are required: + +.. option:: --perfscript= + + Path of perf-script trace created by Linux perf tool with `script` + command(the raw perf.data should be profiled with -b). + +.. option:: --binary= + + Path of the input profiled binary files. + +.. option:: --output= + + Path of the output profile file. + +OPTIONS +------- +:program:`llvm-profgen` supports the following options: + +.. option:: --show-mmap-events + + Print mmap events. + +.. option:: --show-disassembly + + Print disassembled code. + +.. option:: --x86-asm-syntax=[att|intel] + + Specify whether to print assembly code in AT&T syntax (the default) or Intel + syntax. diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 47f24e9aa9f7f..2cd3f93cffef8 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -3657,13 +3657,13 @@ input IR as well. Poison Values ------------- +A poison value is a result of an erroneous operation. In order to facilitate speculative execution, many instructions do not invoke immediate undefined behavior when provided with illegal operands, and return a poison value instead. - -There is currently no way of representing a poison value in the IR; they -only exist when produced by operations such as :ref:`add ` with -the ``nsw`` flag. +The string '``poison``' can be used anywhere a constant is expected, and +operations such as :ref:`add ` with the ``nsw`` flag can produce +a poison value. Poison value behavior is defined in terms of value *dependence*: @@ -3732,13 +3732,14 @@ Here are some examples: entry: %poison = sub nuw i32 0, 1 ; Results in a poison value. + %poison2 = sub i32 poison, 1 ; Also results in a poison value. %still_poison = and i32 %poison, 0 ; 0, but also poison. %poison_yet_again = getelementptr i32, i32* @h, i32 %still_poison store i32 0, i32* %poison_yet_again ; Undefined behavior due to ; store to poison. store i32 %poison, i32* @g ; Poison value stored to memory. - %poison2 = load i32, i32* @g ; Poison value loaded back from memory. + %poison3 = load i32, i32* @g ; Poison value loaded back from memory. %narrowaddr = bitcast i32* @g to i16* %wideaddr = bitcast i32* @g to i64* diff --git a/llvm/docs/TableGen/BackGuide.rst b/llvm/docs/TableGen/BackGuide.rst index 59a1ed1450f16..515eeab2403a8 100644 --- a/llvm/docs/TableGen/BackGuide.rst +++ b/llvm/docs/TableGen/BackGuide.rst @@ -336,14 +336,11 @@ The class provides the following additional functions. The ``CodeInit`` class is a subclass of ``TypedInit``. Its instances represent arbitrary-length strings produced from ``code`` literals in the TableGen files. It includes a data member that contains a ``StringRef`` of -the value. It also includes a data member specifying the source code -location of the code string. +the value. The class provides the usual ``get()`` and ``getValue()`` functions. The latter function returns the ``StringRef``. -The ``getLoc()`` function returns the source code location. - ``DagInit`` ~~~~~~~~~~~ diff --git a/llvm/include/llvm-c/Core.h b/llvm/include/llvm-c/Core.h index e950387242768..1803c38b445dd 100644 --- a/llvm/include/llvm-c/Core.h +++ b/llvm/include/llvm-c/Core.h @@ -269,6 +269,7 @@ typedef enum { LLVMConstantVectorValueKind, LLVMUndefValueValueKind, + LLVMPoisonValueValueKind, LLVMConstantAggregateZeroValueKind, LLVMConstantDataArrayValueKind, LLVMConstantDataVectorValueKind, @@ -1562,6 +1563,7 @@ LLVMTypeRef LLVMX86MMXType(void); macro(Function) \ macro(GlobalVariable) \ macro(UndefValue) \ + macro(PoisonValue) \ macro(Instruction) \ macro(UnaryOperator) \ macro(BinaryOperator) \ @@ -1695,6 +1697,11 @@ LLVMBool LLVMIsConstant(LLVMValueRef Val); */ LLVMBool LLVMIsUndef(LLVMValueRef Val); +/** + * Determine whether a value instance is poisonous. + */ +LLVMBool LLVMIsPoison(LLVMValueRef Val); + /** * Convert value instances between types. * @@ -1853,6 +1860,13 @@ LLVMValueRef LLVMConstAllOnes(LLVMTypeRef Ty); */ LLVMValueRef LLVMGetUndef(LLVMTypeRef Ty); +/** + * Obtain a constant value referring to a poison value of a type. + * + * @see llvm::PoisonValue::get() + */ +LLVMValueRef LLVMGetPoison(LLVMTypeRef Ty); + /** * Determine whether a value instance is null. * diff --git a/llvm/include/llvm/ADT/APInt.h b/llvm/include/llvm/ADT/APInt.h index f5860f6c75178..b97ea2cd9aeef 100644 --- a/llvm/include/llvm/ADT/APInt.h +++ b/llvm/include/llvm/ADT/APInt.h @@ -1403,6 +1403,12 @@ class LLVM_NODISCARD APInt { /// extended, truncated, or left alone to make it that width. APInt zextOrTrunc(unsigned width) const; + /// Truncate to width + /// + /// Make this APInt have the bit width given by \p width. The value is + /// truncated or left alone to make it that width. + APInt truncOrSelf(unsigned width) const; + /// Sign extend or truncate to width /// /// Make this APInt have the bit width given by \p width. The value is sign diff --git a/llvm/include/llvm/ADT/DenseMap.h b/llvm/include/llvm/ADT/DenseMap.h index 34d397cc9793d..42e4fc84175cf 100644 --- a/llvm/include/llvm/ADT/DenseMap.h +++ b/llvm/include/llvm/ADT/DenseMap.h @@ -954,7 +954,7 @@ class SmallDenseMap std::swap(*LHSB, *RHSB); continue; } - // Swap separately and handle any assymetry. + // Swap separately and handle any asymmetry. std::swap(LHSB->getFirst(), RHSB->getFirst()); if (hasLHSValue) { ::new (&RHSB->getSecond()) ValueT(std::move(LHSB->getSecond())); diff --git a/llvm/include/llvm/ADT/Statistic.h b/llvm/include/llvm/ADT/Statistic.h index d7aff6c5939a0..aa338ccff19a6 100644 --- a/llvm/include/llvm/ADT/Statistic.h +++ b/llvm/include/llvm/ADT/Statistic.h @@ -36,6 +36,8 @@ // configure time. #if !defined(NDEBUG) || LLVM_FORCE_ENABLE_STATS #define LLVM_ENABLE_STATS 1 +#else +#define LLVM_ENABLE_STATS 0 #endif namespace llvm { diff --git a/llvm/include/llvm/Analysis/AliasAnalysis.h b/llvm/include/llvm/Analysis/AliasAnalysis.h index 6e642d4e6f4c3..736917cf327a1 100644 --- a/llvm/include/llvm/Analysis/AliasAnalysis.h +++ b/llvm/include/llvm/Analysis/AliasAnalysis.h @@ -407,7 +407,8 @@ class AAResults { /// A convenience wrapper around the primary \c alias interface. AliasResult alias(const Value *V1, const Value *V2) { - return alias(V1, LocationSize::unknown(), V2, LocationSize::unknown()); + return alias(MemoryLocation::getBeforeOrAfter(V1), + MemoryLocation::getBeforeOrAfter(V2)); } /// A trivial helper function to check to see if the specified pointers are @@ -424,8 +425,8 @@ class AAResults { /// A convenience wrapper around the \c isNoAlias helper interface. bool isNoAlias(const Value *V1, const Value *V2) { - return isNoAlias(MemoryLocation(V1, LocationSize::unknown()), - MemoryLocation(V2, LocationSize::unknown())); + return isNoAlias(MemoryLocation::getBeforeOrAfter(V1), + MemoryLocation::getBeforeOrAfter(V2)); } /// A trivial helper function to check to see if the specified pointers are @@ -447,8 +448,7 @@ class AAResults { /// A convenience wrapper around the primary \c pointsToConstantMemory /// interface. bool pointsToConstantMemory(const Value *P, bool OrLocal = false) { - return pointsToConstantMemory(MemoryLocation(P, LocationSize::unknown()), - OrLocal); + return pointsToConstantMemory(MemoryLocation::getBeforeOrAfter(P), OrLocal); } /// @} diff --git a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h index 9e7950e4102ee..6f5a31d6a4b58 100644 --- a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h +++ b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h @@ -162,14 +162,19 @@ class BasicAAResult : public AAResultBase { /// Tracks instructions visited by pointsToConstantMemory. SmallPtrSet Visited; + /// Whether to disable persistent caching in AAQI. This is used to prevent + /// caching of results based on temporary assumptions. + bool DisableCache = false; + static const Value * GetLinearExpression(const Value *V, APInt &Scale, APInt &Offset, unsigned &ZExtBits, unsigned &SExtBits, const DataLayout &DL, unsigned Depth, AssumptionCache *AC, DominatorTree *DT, bool &NSW, bool &NUW); - static bool DecomposeGEPExpression(const Value *V, DecomposedGEP &Decomposed, - const DataLayout &DL, AssumptionCache *AC, DominatorTree *DT); + static DecomposedGEP + DecomposeGEPExpression(const Value *V, const DataLayout &DL, + AssumptionCache *AC, DominatorTree *DT); static bool isGEPBaseAtNegativeOffset(const GEPOperator *GEPOp, const DecomposedGEP &DecompGEP, const DecomposedGEP &DecompObject, @@ -215,6 +220,12 @@ class BasicAAResult : public AAResultBase { LocationSize V2Size, const AAMDNodes &V2AATag, AAQueryInfo &AAQI, const Value *O1 = nullptr, const Value *O2 = nullptr); + + AliasResult aliasCheckRecursive(const Value *V1, LocationSize V1Size, + const AAMDNodes &V1AATag, const Value *V2, + LocationSize V2Size, const AAMDNodes &V2AATag, + AAQueryInfo &AAQI, const Value *O1, + const Value *O2); }; /// Analysis pass providing a never-invalidated alias analysis result. diff --git a/llvm/include/llvm/Analysis/CGSCCPassManager.h b/llvm/include/llvm/Analysis/CGSCCPassManager.h index 755bc92ddccf6..05875c5c06287 100644 --- a/llvm/include/llvm/Analysis/CGSCCPassManager.h +++ b/llvm/include/llvm/Analysis/CGSCCPassManager.h @@ -90,6 +90,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/MapVector.h" #include "llvm/ADT/PriorityWorklist.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallPtrSet.h" @@ -314,6 +315,16 @@ struct CGSCCUpdateResult { /// for a better technique. SmallDenseSet, 4> &InlinedInternalEdges; + + /// Weak VHs to keep track of indirect calls for the purposes of detecting + /// devirtualization. + /// + /// This is a map to avoid having duplicate entries. If a Value is + /// deallocated, its corresponding WeakTrackingVH will be nulled out. When + /// checking if a Value is in the map or not, also check if the corresponding + /// WeakTrackingVH is null to avoid issues with a new Value sharing the same + /// address as a deallocated one. + SmallMapVector IndirectVHs; }; /// The core module pass which does a post-order walk of the SCCs and @@ -596,9 +607,6 @@ class DevirtSCCRepeatedPass // a pointer that we can update. LazyCallGraph::SCC *C = &InitialC; - // Collect value handles for all of the indirect call sites. - SmallVector CallHandles; - // Struct to track the counts of direct and indirect calls in each function // of the SCC. struct CallCount { @@ -608,35 +616,37 @@ class DevirtSCCRepeatedPass // Put value handles on all of the indirect calls and return the number of // direct calls for each function in the SCC. - auto ScanSCC = [](LazyCallGraph::SCC &C, - SmallVectorImpl &CallHandles) { - assert(CallHandles.empty() && "Must start with a clear set of handles."); - - SmallDenseMap CallCounts; - CallCount CountLocal = {0, 0}; - for (LazyCallGraph::Node &N : C) { - CallCount &Count = - CallCounts.insert(std::make_pair(&N.getFunction(), CountLocal)) - .first->second; - for (Instruction &I : instructions(N.getFunction())) - if (auto *CB = dyn_cast(&I)) { - if (CB->getCalledFunction()) { - ++Count.Direct; - } else { - ++Count.Indirect; - CallHandles.push_back(WeakTrackingVH(&I)); - } + auto ScanSCC = + [](LazyCallGraph::SCC &C, + SmallMapVector &CallHandles) { + assert(CallHandles.empty() && + "Must start with a clear set of handles."); + + SmallDenseMap CallCounts; + CallCount CountLocal = {0, 0}; + for (LazyCallGraph::Node &N : C) { + CallCount &Count = + CallCounts.insert(std::make_pair(&N.getFunction(), CountLocal)) + .first->second; + for (Instruction &I : instructions(N.getFunction())) + if (auto *CB = dyn_cast(&I)) { + if (CB->getCalledFunction()) { + ++Count.Direct; + } else { + ++Count.Indirect; + CallHandles.insert({CB, WeakTrackingVH(CB)}); + } + } } - } - return CallCounts; - }; + return CallCounts; + }; + UR.IndirectVHs.clear(); // Populate the initial call handles and get the initial call counts. - auto CallCounts = ScanSCC(*C, CallHandles); + auto CallCounts = ScanSCC(*C, UR.IndirectVHs); for (int Iteration = 0;; ++Iteration) { - if (!PI.runBeforePass(Pass, *C)) continue; @@ -659,33 +669,23 @@ class DevirtSCCRepeatedPass assert(C->begin() != C->end() && "Cannot have an empty SCC!"); // Check whether any of the handles were devirtualized. - auto IsDevirtualizedHandle = [&](WeakTrackingVH &CallH) { - if (!CallH) - return false; - auto *CB = dyn_cast(CallH); - if (!CB) - return false; - - // If the call is still indirect, leave it alone. - Function *F = CB->getCalledFunction(); - if (!F) - return false; - - LLVM_DEBUG(dbgs() << "Found devirtualized call from " - << CB->getParent()->getParent()->getName() << " to " - << F->getName() << "\n"); - - // We now have a direct call where previously we had an indirect call, - // so iterate to process this devirtualization site. - return true; - }; - bool Devirt = llvm::any_of(CallHandles, IsDevirtualizedHandle); + bool Devirt = llvm::any_of(UR.IndirectVHs, [](auto &P) -> bool { + if (P.second) { + if (CallBase *CB = dyn_cast(P.second)) { + if (CB->getCalledFunction()) { + LLVM_DEBUG(dbgs() << "Found devirtualized call: " << *CB << "\n"); + return true; + } + } + } + return false; + }); // Rescan to build up a new set of handles and count how many direct // calls remain. If we decide to iterate, this also sets up the input to // the next iteration. - CallHandles.clear(); - auto NewCallCounts = ScanSCC(*C, CallHandles); + UR.IndirectVHs.clear(); + auto NewCallCounts = ScanSCC(*C, UR.IndirectVHs); // If we haven't found an explicit devirtualization already see if we // have decreased the number of indirect calls and increased the number @@ -790,7 +790,8 @@ ModuleToPostOrderCGSCCPassAdaptor::run(Module &M, CGSCCUpdateResult UR = { RCWorklist, CWorklist, InvalidRefSCCSet, InvalidSCCSet, - nullptr, nullptr, PreservedAnalyses::all(), InlinedInternalEdges}; + nullptr, nullptr, PreservedAnalyses::all(), InlinedInternalEdges, + {}}; // Request PassInstrumentation from analysis manager, will use it to run // instrumenting callbacks for the passes later. diff --git a/llvm/include/llvm/Analysis/DominanceFrontier.h b/llvm/include/llvm/Analysis/DominanceFrontier.h index f67929c997f93..cef5e03b3b7a7 100644 --- a/llvm/include/llvm/Analysis/DominanceFrontier.h +++ b/llvm/include/llvm/Analysis/DominanceFrontier.h @@ -26,7 +26,6 @@ #include #include #include -#include namespace llvm { diff --git a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h index 663b9c9935db7..5ee98f3088780 100644 --- a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h +++ b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h @@ -171,7 +171,8 @@ class MemoryDepChecker { MemoryDepChecker(PredicatedScalarEvolution &PSE, const Loop *L) : PSE(PSE), InnermostLoop(L), AccessIdx(0), MaxSafeDepDistBytes(0), - MaxSafeRegisterWidth(-1U), FoundNonConstantDistanceDependence(false), + MaxSafeVectorWidthInBits(-1U), + FoundNonConstantDistanceDependence(false), Status(VectorizationSafetyStatus::Safe), RecordDependences(true) {} /// Register the location (instructions are given increasing numbers) @@ -210,7 +211,9 @@ class MemoryDepChecker { /// Return the number of elements that are safe to operate on /// simultaneously, multiplied by the size of the element in bits. - uint64_t getMaxSafeRegisterWidth() const { return MaxSafeRegisterWidth; } + uint64_t getMaxSafeVectorWidthInBits() const { + return MaxSafeVectorWidthInBits; + } /// In same cases when the dependency check fails we can still /// vectorize the loop with a dynamic array access check. @@ -275,7 +278,7 @@ class MemoryDepChecker { /// operate on simultaneously, multiplied by the size of the element in bits. /// The size of the element is taken from the memory access that is most /// restrictive. - uint64_t MaxSafeRegisterWidth; + uint64_t MaxSafeVectorWidthInBits; /// If we see a non-constant dependence distance we can still try to /// vectorize this loop with runtime checks. diff --git a/llvm/include/llvm/Analysis/MemDerefPrinter.h b/llvm/include/llvm/Analysis/MemDerefPrinter.h new file mode 100644 index 0000000000000..bafdc543eeaf4 --- /dev/null +++ b/llvm/include/llvm/Analysis/MemDerefPrinter.h @@ -0,0 +1,24 @@ +//===- MemDerefPrinter.h - Printer for isDereferenceablePointer -----------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ANALYSIS_MEMDEREFPRINTER_H +#define LLVM_ANALYSIS_MEMDEREFPRINTER_H + +#include "llvm/IR/PassManager.h" + +namespace llvm { +class MemDerefPrinterPass : public PassInfoMixin { + raw_ostream &OS; + +public: + MemDerefPrinterPass(raw_ostream &OS) : OS(OS) {} + PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); +}; +} // namespace llvm + +#endif // LLVM_ANALYSIS_MEMDEREFPRINTER_H diff --git a/llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h b/llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h index 0777dc7d7862b..efde00f82d570 100644 --- a/llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h +++ b/llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h @@ -302,7 +302,7 @@ class MemoryDependenceResults { /// The maximum size of the dereferences of the pointer. /// /// May be UnknownSize if the sizes are unknown. - LocationSize Size = LocationSize::unknown(); + LocationSize Size = LocationSize::afterPointer(); /// The AA tags associated with dereferences of the pointer. /// /// The members may be null if there are no tags or conflicting tags. diff --git a/llvm/include/llvm/Analysis/MemoryLocation.h b/llvm/include/llvm/Analysis/MemoryLocation.h index d838f690d894f..3b188d763ef28 100644 --- a/llvm/include/llvm/Analysis/MemoryLocation.h +++ b/llvm/include/llvm/Analysis/MemoryLocation.h @@ -64,10 +64,11 @@ class VAArgInst; // None. class LocationSize { enum : uint64_t { - Unknown = ~uint64_t(0), + BeforeOrAfterPointer = ~uint64_t(0), + AfterPointer = BeforeOrAfterPointer - 1, + MapEmpty = BeforeOrAfterPointer - 2, + MapTombstone = BeforeOrAfterPointer - 3, ImpreciseBit = uint64_t(1) << 63, - MapEmpty = Unknown - 1, - MapTombstone = Unknown - 2, // The maximum value we can represent without falling back to 'unknown'. MaxValue = (MapTombstone - 1) & ~ImpreciseBit, @@ -81,7 +82,11 @@ class LocationSize { constexpr LocationSize(uint64_t Raw, DirectConstruction): Value(Raw) {} - static_assert(Unknown & ImpreciseBit, "Unknown is imprecise by definition."); + static_assert(AfterPointer & ImpreciseBit, + "AfterPointer is imprecise by definition."); + static_assert(BeforeOrAfterPointer & ImpreciseBit, + "BeforeOrAfterPointer is imprecise by definition."); + public: // FIXME: Migrate all users to construct via either `precise` or `upperBound`, // to make it more obvious at the callsite the kind of size that they're @@ -90,12 +95,12 @@ class LocationSize { // Since the overwhelming majority of users of this provide precise values, // this assumes the provided value is precise. constexpr LocationSize(uint64_t Raw) - : Value(Raw > MaxValue ? Unknown : Raw) {} + : Value(Raw > MaxValue ? AfterPointer : Raw) {} static LocationSize precise(uint64_t Value) { return LocationSize(Value); } static LocationSize precise(TypeSize Value) { if (Value.isScalable()) - return unknown(); + return afterPointer(); return precise(Value.getFixedSize()); } @@ -104,17 +109,25 @@ class LocationSize { if (LLVM_UNLIKELY(Value == 0)) return precise(0); if (LLVM_UNLIKELY(Value > MaxValue)) - return unknown(); + return afterPointer(); return LocationSize(Value | ImpreciseBit, Direct); } static LocationSize upperBound(TypeSize Value) { if (Value.isScalable()) - return unknown(); + return afterPointer(); return upperBound(Value.getFixedSize()); } - constexpr static LocationSize unknown() { - return LocationSize(Unknown, Direct); + /// Any location after the base pointer (but still within the underlying + /// object). + constexpr static LocationSize afterPointer() { + return LocationSize(AfterPointer, Direct); + } + + /// Any location before or after the base pointer (but still within the + /// underlying object). + constexpr static LocationSize beforeOrAfterPointer() { + return LocationSize(BeforeOrAfterPointer, Direct); } // Sentinel values, generally used for maps. @@ -131,20 +144,24 @@ class LocationSize { if (Other == *this) return *this; - if (!hasValue() || !Other.hasValue()) - return unknown(); + if (Value == BeforeOrAfterPointer || Other.Value == BeforeOrAfterPointer) + return beforeOrAfterPointer(); + if (Value == AfterPointer || Other.Value == AfterPointer) + return afterPointer(); return upperBound(std::max(getValue(), Other.getValue())); } - bool hasValue() const { return Value != Unknown; } + bool hasValue() const { + return Value != AfterPointer && Value != BeforeOrAfterPointer; + } uint64_t getValue() const { assert(hasValue() && "Getting value from an unknown LocationSize!"); return Value & ~ImpreciseBit; } // Returns whether or not this value is precise. Note that if a value is - // precise, it's guaranteed to not be `unknown()`. + // precise, it's guaranteed to not be unknown. bool isPrecise() const { return (Value & ImpreciseBit) == 0; } @@ -152,6 +169,9 @@ class LocationSize { // Convenience method to check if this LocationSize's value is 0. bool isZero() const { return hasValue() && getValue() == 0; } + /// Whether accesses before the base pointer are possible. + bool mayBeBeforePointer() const { return Value == BeforeOrAfterPointer; } + bool operator==(const LocationSize &Other) const { return Value == Other.Value; } @@ -242,13 +262,28 @@ class MemoryLocation { return getForArgument(Call, ArgIdx, &TLI); } + /// Return a location that may access any location after Ptr, while remaining + /// within the underlying object. + static MemoryLocation getAfter(const Value *Ptr, + const AAMDNodes &AATags = AAMDNodes()) { + return MemoryLocation(Ptr, LocationSize::afterPointer(), AATags); + } + + /// Return a location that may access any location before or after Ptr, while + /// remaining within the underlying object. + static MemoryLocation + getBeforeOrAfter(const Value *Ptr, const AAMDNodes &AATags = AAMDNodes()) { + return MemoryLocation(Ptr, LocationSize::beforeOrAfterPointer(), AATags); + } + // Return the exact size if the exact size is known at compiletime, // otherwise return MemoryLocation::UnknownSize. static uint64_t getSizeOrUnknown(const TypeSize &T) { return T.isScalable() ? UnknownSize : T.getFixedSize(); } - MemoryLocation() : Ptr(nullptr), Size(LocationSize::unknown()), AATags() {} + MemoryLocation() + : Ptr(nullptr), Size(LocationSize::beforeOrAfterPointer()), AATags() {} explicit MemoryLocation(const Value *Ptr, LocationSize Size, const AAMDNodes &AATags = AAMDNodes()) diff --git a/llvm/include/llvm/Analysis/MemorySSA.h b/llvm/include/llvm/Analysis/MemorySSA.h index d91b676d2e5a8..e73af5f89ed60 100644 --- a/llvm/include/llvm/Analysis/MemorySSA.h +++ b/llvm/include/llvm/Analysis/MemorySSA.h @@ -1248,7 +1248,8 @@ class upward_defs_iterator // catch loop carried dependences. if (Location.Ptr && !IsGuaranteedLoopInvariant(const_cast(Location.Ptr))) - CurrentPair.second = Location.getWithNewSize(LocationSize::unknown()); + CurrentPair.second = + Location.getWithNewSize(LocationSize::beforeOrAfterPointer()); PHITransAddr Translator( const_cast(Location.Ptr), OriginalAccess->getBlock()->getModule()->getDataLayout(), nullptr); @@ -1262,8 +1263,8 @@ class upward_defs_iterator if (TransAddr && !IsGuaranteedLoopInvariant(const_cast(TransAddr))) - CurrentPair.second = - CurrentPair.second.getWithNewSize(LocationSize::unknown()); + CurrentPair.second = CurrentPair.second.getWithNewSize( + LocationSize::beforeOrAfterPointer()); if (PerformedPhiTranslation) *PerformedPhiTranslation = true; diff --git a/llvm/include/llvm/Analysis/ScalarEvolution.h b/llvm/include/llvm/Analysis/ScalarEvolution.h index a45034fb5494e..35e569710cabd 100644 --- a/llvm/include/llvm/Analysis/ScalarEvolution.h +++ b/llvm/include/llvm/Analysis/ScalarEvolution.h @@ -600,9 +600,17 @@ class ScalarEvolution { return getConstant(Ty, -1, /*isSigned=*/true); } - /// Return an expression for sizeof AllocTy that is type IntTy + /// Return an expression for sizeof ScalableTy that is type IntTy, where + /// ScalableTy is a scalable vector type. + const SCEV *getSizeOfScalableVectorExpr(Type *IntTy, + ScalableVectorType *ScalableTy); + + /// Return an expression for the alloc size of AllocTy that is type IntTy const SCEV *getSizeOfExpr(Type *IntTy, Type *AllocTy); + /// Return an expression for the store size of StoreTy that is type IntTy + const SCEV *getStoreSizeOfExpr(Type *IntTy, Type *StoreTy); + /// Return an expression for offsetof on the given field with type IntTy const SCEV *getOffsetOfExpr(Type *IntTy, StructType *STy, unsigned FieldNo); @@ -954,14 +962,9 @@ class ScalarEvolution { /// monotonically increasing or decreasing, returns /// Some(MonotonicallyIncreasing) and Some(MonotonicallyDecreasing) /// respectively. If we could not prove either of these facts, returns None. - /// - /// If NumIter was provided, then we are proving monotonicity during at least - /// NumIter first iterations. If it was not provided, then we are proving - /// monotonicity on all iteration space. Optional - getMonotonicPredicateType(const SCEVAddRecExpr *LHS, ICmpInst::Predicate Pred, - Optional NumIter = None, - const Instruction *Context = nullptr); + getMonotonicPredicateType(const SCEVAddRecExpr *LHS, + ICmpInst::Predicate Pred); struct LoopInvariantPredicate { ICmpInst::Predicate Pred; @@ -1160,15 +1163,6 @@ class ScalarEvolution { const SCEV *S, const Loop *L, SmallPtrSetImpl &Preds); - /// Compute \p LHS - \p RHS and returns the result as an APInt if it is a - /// constant, and None if it isn't. - /// - /// This is intended to be a cheaper version of getMinusSCEV. We can be - /// frugal here since we just bail out of actually constructing and - /// canonicalizing an expression in the cases where the result isn't going - /// to be a constant. - Optional computeConstantDifference(const SCEV *LHS, const SCEV *RHS); - /// Update no-wrap flags of an AddRec. This may drop the cached info about /// this AddRec (such as range info) in case if new flags may potentially /// sharpen it. @@ -1669,7 +1663,14 @@ class ScalarEvolution { Value *ExitCond, bool ExitIfTrue, bool ControlsExit, bool AllowPredicates); - + Optional + computeExitLimitFromCondFromBinOp(ExitLimitCacheTy &Cache, const Loop *L, + Value *ExitCond, bool ExitIfTrue, + bool ControlsExit, bool AllowPredicates); + ExitLimit computeExitLimitFromCondFromBinOpHelper( + ExitLimitCacheTy &Cache, const Loop *L, BinaryOperator *BO, + bool EitherMayExit, bool ExitIfTrue, bool ControlsExit, + bool AllowPredicates, const Constant *NeutralElement); /// Compute the number of times the backedge of the specified loop will /// execute if its exit condition were a conditional branch of the ICmpInst /// ExitCond and ExitIfTrue. If AllowPredicates is set, this call will try @@ -1883,6 +1884,15 @@ class ScalarEvolution { bool splitBinaryAdd(const SCEV *Expr, const SCEV *&L, const SCEV *&R, SCEV::NoWrapFlags &Flags); + /// Compute \p LHS - \p RHS and returns the result as an APInt if it is a + /// constant, and None if it isn't. + /// + /// This is intended to be a cheaper version of getMinusSCEV. We can be + /// frugal here since we just bail out of actually constructing and + /// canonicalizing an expression in the cases where the result isn't going + /// to be a constant. + Optional computeConstantDifference(const SCEV *LHS, const SCEV *RHS); + /// Drop memoized information computed for S. void forgetMemoizedResults(const SCEV *S); @@ -1913,9 +1923,9 @@ class ScalarEvolution { /// entry and backedge. SCEV::NoWrapFlags proveNoUnsignedWrapViaInduction(const SCEVAddRecExpr *AR); - Optional getMonotonicPredicateTypeImpl( - const SCEVAddRecExpr *LHS, ICmpInst::Predicate Pred, - Optional NumIter, const Instruction *Context); + Optional + getMonotonicPredicateTypeImpl(const SCEVAddRecExpr *LHS, + ICmpInst::Predicate Pred); /// Return SCEV no-wrap flags that can be proven based on reasoning about /// how poison produced from no-wrap flags on this value (e.g. a nuw add) diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index 77952247fe3c9..9cb5fe78f4182 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -93,7 +93,7 @@ struct HardwareLoopInfo { Loop *L = nullptr; BasicBlock *ExitBlock = nullptr; BranchInst *ExitBranch = nullptr; - const SCEV *ExitCount = nullptr; + const SCEV *TripCount = nullptr; IntegerType *CountType = nullptr; Value *LoopDecrement = nullptr; // Decrement the loop counter by this // value in every iteration. diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index ed997406f8a24..b4847844cd0ee 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -526,6 +526,7 @@ class TargetTransformInfoImplBase { case Intrinsic::annotation: case Intrinsic::assume: case Intrinsic::sideeffect: + case Intrinsic::pseudoprobe: case Intrinsic::dbg_declare: case Intrinsic::dbg_value: case Intrinsic::dbg_label: diff --git a/llvm/include/llvm/BinaryFormat/Wasm.h b/llvm/include/llvm/BinaryFormat/Wasm.h index f1441c7e07947..adcd9d3644316 100644 --- a/llvm/include/llvm/BinaryFormat/Wasm.h +++ b/llvm/include/llvm/BinaryFormat/Wasm.h @@ -67,12 +67,17 @@ struct WasmLimits { uint64_t Maximum; }; -struct WasmTable { - uint32_t Index; +struct WasmTableType { uint8_t ElemType; WasmLimits Limits; }; +struct WasmTable { + uint32_t Index; + WasmTableType Type; + StringRef SymbolName; // from the "linking" section +}; + struct WasmInitExpr { uint8_t Opcode; union { @@ -115,7 +120,7 @@ struct WasmImport { union { uint32_t SigIndex; WasmGlobalType Global; - WasmTable Table; + WasmTableType Table; WasmLimits Memory; WasmEventType Event; }; diff --git a/llvm/include/llvm/Bitcode/LLVMBitCodes.h b/llvm/include/llvm/Bitcode/LLVMBitCodes.h index 8abb20ced0c38..80fa4ac97d0d8 100644 --- a/llvm/include/llvm/Bitcode/LLVMBitCodes.h +++ b/llvm/include/llvm/Bitcode/LLVMBitCodes.h @@ -375,6 +375,7 @@ enum ConstantsCodes { // asmdialect,asmstr,conststr] CST_CODE_CE_GEP_WITH_INRANGE_INDEX = 24, // [opty, flags, n x operands] CST_CODE_CE_UNOP = 25, // CE_UNOP: [opcode, opval] + CST_CODE_POISON = 26, // POISON }; /// CastOpcodes - These are values used in the bitcode files to encode which diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index 8ba68ffdad676..0b6b2655e0d5b 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -991,6 +991,51 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { return Cost; } + unsigned getGatherScatterOpCost(unsigned Opcode, Type *DataTy, + const Value *Ptr, bool VariableMask, + Align Alignment, TTI::TargetCostKind CostKind, + const Instruction *I = nullptr) { + auto *VT = cast(DataTy); + // Assume the target does not have support for gather/scatter operations + // and provide a rough estimate. + // + // First, compute the cost of extracting the individual addresses and the + // individual memory operations. + int LoadCost = + VT->getNumElements() * + (getVectorInstrCost( + Instruction::ExtractElement, + FixedVectorType::get(PointerType::get(VT->getElementType(), 0), + VT->getNumElements()), + -1) + + getMemoryOpCost(Opcode, VT->getElementType(), Alignment, 0, CostKind)); + + // Next, compute the cost of packing the result in a vector. + int PackingCost = getScalarizationOverhead(VT, Opcode != Instruction::Store, + Opcode == Instruction::Store); + + int ConditionalCost = 0; + if (VariableMask) { + // Compute the cost of conditionally executing the memory operations with + // variable masks. This includes extracting the individual conditions, a + // branches and PHIs to combine the results. + // NOTE: Estimating the cost of conditionally executing the memory + // operations accurately is quite difficult and the current solution + // provides a very rough estimate only. + ConditionalCost = + VT->getNumElements() * + (getVectorInstrCost( + Instruction::ExtractElement, + FixedVectorType::get(Type::getInt1Ty(DataTy->getContext()), + VT->getNumElements()), + -1) + + getCFInstrCost(Instruction::Br, CostKind) + + getCFInstrCost(Instruction::PHI, CostKind)); + } + + return LoadCost + PackingCost + ConditionalCost; + } + unsigned getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, @@ -1172,9 +1217,6 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { FastMathFlags FMF = ICA.getFlags(); switch (IID) { default: - // FIXME: all cost kinds should default to the same thing? - if (CostKind != TTI::TCK_RecipThroughput) - return BaseT::getIntrinsicInstrCost(ICA, CostKind); break; case Intrinsic::cttz: @@ -1324,8 +1366,9 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { VecOpTy = dyn_cast(Tys[VecTyIndex]); } + // Library call cost - other than size, make it expensive. + unsigned SingleCallCost = CostKind == TTI::TCK_CodeSize ? 1 : 10; SmallVector ISDs; - unsigned SingleCallCost = 10; // Library call cost. Make it expensive. switch (IID) { default: { // Assume that we need to scalarize this intrinsic. @@ -1398,6 +1441,12 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { case Intrinsic::maxnum: ISDs.push_back(ISD::FMAXNUM); break; + case Intrinsic::minimum: + ISDs.push_back(ISD::FMINIMUM); + break; + case Intrinsic::maximum: + ISDs.push_back(ISD::FMAXIMUM); + break; case Intrinsic::copysign: ISDs.push_back(ISD::FCOPYSIGN); break; @@ -1438,6 +1487,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { case Intrinsic::lifetime_start: case Intrinsic::lifetime_end: case Intrinsic::sideeffect: + case Intrinsic::pseudoprobe: return 0; case Intrinsic::masked_store: { Type *Ty = Tys[0]; diff --git a/llvm/include/llvm/CodeGen/CommandFlags.h b/llvm/include/llvm/CodeGen/CommandFlags.h index dd9a74cad8d70..e18d16b4b3969 100644 --- a/llvm/include/llvm/CodeGen/CommandFlags.h +++ b/llvm/include/llvm/CodeGen/CommandFlags.h @@ -75,6 +75,8 @@ bool getDontPlaceZerosInBSS(); bool getEnableGuaranteedTailCallOpt(); +bool getEnableAIXExtendedAltivecABI(); + bool getDisableTailCalls(); bool getStackSymbolOrdering(); diff --git a/llvm/include/llvm/CodeGen/FastISel.h b/llvm/include/llvm/CodeGen/FastISel.h index 5c1ebc7af177e..96f809e11b376 100644 --- a/llvm/include/llvm/CodeGen/FastISel.h +++ b/llvm/include/llvm/CodeGen/FastISel.h @@ -246,7 +246,7 @@ class FastISel { /// be appended. void startNewBlock(); - /// Flush the local value map and sink local values if possible. + /// Flush the local value map. void finishBasicBlock(); /// Return current debug location information. @@ -313,10 +313,7 @@ class FastISel { void removeDeadCode(MachineBasicBlock::iterator I, MachineBasicBlock::iterator E); - struct SavePoint { - MachineBasicBlock::iterator InsertPt; - DebugLoc DL; - }; + using SavePoint = MachineBasicBlock::iterator; /// Prepare InsertPt to begin inserting instructions into the local /// value area and return the old insert position. @@ -560,20 +557,6 @@ class FastISel { /// Removes dead local value instructions after SavedLastLocalvalue. void removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue); - struct InstOrderMap { - DenseMap Orders; - MachineInstr *FirstTerminator = nullptr; - unsigned FirstTerminatorOrder = std::numeric_limits::max(); - - void initialize(MachineBasicBlock *MBB, - MachineBasicBlock::iterator LastFlushPoint); - }; - - /// Sinks the local value materialization instruction LocalMI to its first use - /// in the basic block, or deletes it if it is not used. - void sinkLocalValueMaterialization(MachineInstr &LocalMI, Register DefReg, - InstOrderMap &OrderMap); - /// Insertion point before trying to select the current instruction. MachineBasicBlock::iterator SavedInsertPt; diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h index 269bb14508b87..2cacb572a0e18 100644 --- a/llvm/include/llvm/CodeGen/ISDOpcodes.h +++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h @@ -1106,6 +1106,10 @@ enum NodeType { /// known nonzero constant. The only operand here is the chain. GET_DYNAMIC_AREA_OFFSET, + /// Pseudo probe for AutoFDO, as a place holder in a basic block to improve + /// the sample counts quality. + PSEUDO_PROBE, + /// VSCALE(IMM) - Returns the runtime scaling factor used to calculate the /// number of elements within a scalable vector. IMM is a constant integer /// multiplier that is applied to the runtime value. diff --git a/llvm/include/llvm/CodeGen/MachineDominanceFrontier.h b/llvm/include/llvm/CodeGen/MachineDominanceFrontier.h index f7bbd07a63ab5..e3e679608784a 100644 --- a/llvm/include/llvm/CodeGen/MachineDominanceFrontier.h +++ b/llvm/include/llvm/CodeGen/MachineDominanceFrontier.h @@ -14,7 +14,6 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/Support/GenericDomTree.h" -#include namespace llvm { diff --git a/llvm/include/llvm/CodeGen/MachineDominators.h b/llvm/include/llvm/CodeGen/MachineDominators.h index cf3af4d38223b..46bf73cdd7b63 100644 --- a/llvm/include/llvm/CodeGen/MachineDominators.h +++ b/llvm/include/llvm/CodeGen/MachineDominators.h @@ -23,7 +23,6 @@ #include "llvm/Support/GenericDomTreeConstruction.h" #include #include -#include namespace llvm { diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h index 6247f2a2c9b2e..6bbe2d03f9e58 100644 --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -1261,6 +1261,7 @@ class MachineInstr case TargetOpcode::DBG_LABEL: case TargetOpcode::LIFETIME_START: case TargetOpcode::LIFETIME_END: + case TargetOpcode::PSEUDO_PROBE: return true; } } diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index 42fc296a682c3..cbd2e8b043a04 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -1205,6 +1205,12 @@ class SelectionDAG { SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex, int64_t Size, int64_t Offset = -1); + /// Creates a PseudoProbeSDNode with function GUID `Guid` and + /// the index of the block `Index` it is probing, as well as the attributes + /// `attr` of the probe. + SDValue getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, uint64_t Guid, + uint64_t Index, uint32_t Attr); + /// Create a MERGE_VALUES node from the given operands. SDValue getMergeValues(ArrayRef Ops, const SDLoc &dl); @@ -1514,6 +1520,9 @@ class SelectionDAG { SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList, ArrayRef Ops); + /// Check if a node exists without modifying its flags. + bool doesNodeExist(unsigned Opcode, SDVTList VTList, ArrayRef Ops); + /// Creates a SDDbgValue node. SDDbgValue *getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index eaad25c508abc..7da81935904de 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -1749,6 +1749,32 @@ class LifetimeSDNode : public SDNode { } }; +/// This SDNode is used for PSEUDO_PROBE values, which are the function guid and +/// the index of the basic block being probed. A pseudo probe serves as a place +/// holder and will be removed at the end of compilation. It does not have any +/// operand because we do not want the instruction selection to deal with any. +class PseudoProbeSDNode : public SDNode { + friend class SelectionDAG; + uint64_t Guid; + uint64_t Index; + uint32_t Attributes; + + PseudoProbeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &Dl, + SDVTList VTs, uint64_t Guid, uint64_t Index, uint32_t Attr) + : SDNode(Opcode, Order, Dl, VTs), Guid(Guid), Index(Index), + Attributes(Attr) {} + +public: + uint64_t getGuid() const { return Guid; } + uint64_t getIndex() const { return Index; } + uint32_t getAttributes() const { return Attributes; } + + // Methods to support isa and dyn_cast + static bool classof(const SDNode *N) { + return N->getOpcode() == ISD::PSEUDO_PROBE; + } +}; + class JumpTableSDNode : public SDNode { friend class SelectionDAG; @@ -2604,7 +2630,8 @@ template <> struct GraphTraits { /// with 4 and 8 byte pointer alignment, respectively. using LargestSDNode = AlignedCharArrayUnion; + GlobalAddressSDNode, + PseudoProbeSDNode>; /// The SDNode class with the greatest alignment requirement. using MostAlignedSDNode = GlobalAddressSDNode; diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 30d1623d80c28..4aeefd980d7ad 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -4277,6 +4277,22 @@ class TargetLowering : public TargetLoweringBase { return SDValue(); } + /// Return a target-dependent comparison result if the input operand is + /// suitable for use with a square root estimate calculation. For example, the + /// comparison may check if the operand is NAN, INF, zero, normal, etc. The + /// result should be used as the condition operand for a select or branch. + virtual SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, + const DenormalMode &Mode) const { + return SDValue(); + } + + /// Return a target-dependent result if the input operand is not suitable for + /// use with a square root estimate calculation. + virtual SDValue getSqrtResultForDenormInput(SDValue Operand, + SelectionDAG &DAG) const { + return DAG.getConstantFP(0.0, SDLoc(Operand), Operand.getValueType()); + } + //===--------------------------------------------------------------------===// // Legalization utility functions // @@ -4418,6 +4434,10 @@ class TargetLowering : public TargetLoweringBase { SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) const; + /// Method for building the DAG expansion of ISD::[US][MIN|MAX]. This + /// method accepts integers as its arguments. + SDValue expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const; + /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This /// method accepts integers as its arguments. SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const; diff --git a/llvm/include/llvm/Config/abi-breaking.h.cmake b/llvm/include/llvm/Config/abi-breaking.h.cmake index a1ffad660770f..2d27e02b1d545 100644 --- a/llvm/include/llvm/Config/abi-breaking.h.cmake +++ b/llvm/include/llvm/Config/abi-breaking.h.cmake @@ -20,7 +20,7 @@ /* Allow selectively disabling link-time mismatch checking so that header-only ADT content from LLVM can be used without linking libSupport. */ -#if !LLVM_DISABLE_ABI_BREAKING_CHECKS_ENFORCING +#if !defined(LLVM_DISABLE_ABI_BREAKING_CHECKS_ENFORCING) || !LLVM_DISABLE_ABI_BREAKING_CHECKS_ENFORCING // ABI_BREAKING_CHECKS protection: provides link-time failure when clients build // mismatch with LLVM diff --git a/llvm/include/llvm/Demangle/ItaniumDemangle.h b/llvm/include/llvm/Demangle/ItaniumDemangle.h index bfece9684daa1..1cffb45d6b60f 100644 --- a/llvm/include/llvm/Demangle/ItaniumDemangle.h +++ b/llvm/include/llvm/Demangle/ItaniumDemangle.h @@ -82,6 +82,7 @@ X(PostfixExpr) \ X(ConditionalExpr) \ X(MemberExpr) \ + X(SubobjectExpr) \ X(EnclosingExpr) \ X(CastExpr) \ X(SizeofParamPackExpr) \ @@ -91,6 +92,7 @@ X(PrefixExpr) \ X(FunctionParam) \ X(ConversionExpr) \ + X(PointerToMemberConversionExpr) \ X(InitListExpr) \ X(FoldExpr) \ X(ThrowExpr) \ @@ -1664,6 +1666,40 @@ class MemberExpr : public Node { } }; +class SubobjectExpr : public Node { + const Node *Type; + const Node *SubExpr; + StringView Offset; + NodeArray UnionSelectors; + bool OnePastTheEnd; + +public: + SubobjectExpr(const Node *Type_, const Node *SubExpr_, StringView Offset_, + NodeArray UnionSelectors_, bool OnePastTheEnd_) + : Node(KSubobjectExpr), Type(Type_), SubExpr(SubExpr_), Offset(Offset_), + UnionSelectors(UnionSelectors_), OnePastTheEnd(OnePastTheEnd_) {} + + template void match(Fn F) const { + F(Type, SubExpr, Offset, UnionSelectors, OnePastTheEnd); + } + + void printLeft(OutputStream &S) const override { + SubExpr->print(S); + S += ".<"; + Type->print(S); + S += " at offset "; + if (Offset.empty()) { + S += "0"; + } else if (Offset[0] == 'n') { + S += "-"; + S += Offset.dropFront(); + } else { + S += Offset; + } + S += ">"; + } +}; + class EnclosingExpr : public Node { const StringView Prefix; const Node *Infix; @@ -1851,6 +1887,28 @@ class ConversionExpr : public Node { } }; +class PointerToMemberConversionExpr : public Node { + const Node *Type; + const Node *SubExpr; + StringView Offset; + +public: + PointerToMemberConversionExpr(const Node *Type_, const Node *SubExpr_, + StringView Offset_) + : Node(KPointerToMemberConversionExpr), Type(Type_), SubExpr(SubExpr_), + Offset(Offset_) {} + + template void match(Fn F) const { F(Type, SubExpr, Offset); } + + void printLeft(OutputStream &S) const override { + S += "("; + Type->print(S); + S += ")("; + SubExpr->print(S); + S += ")"; + } +}; + class InitListExpr : public Node { const Node *Ty; NodeArray Inits; @@ -2455,6 +2513,8 @@ template struct AbstractManglingParser { Node *parseConversionExpr(); Node *parseBracedExpr(); Node *parseFoldExpr(); + Node *parsePointerToMemberConversionExpr(); + Node *parseSubobjectExpr(); /// Parse the production. Node *parseType(); @@ -4422,6 +4482,50 @@ Node *AbstractManglingParser::parseFoldExpr() { return make(IsLeftFold, OperatorName, Pack, Init); } +// ::= mc [] E +// +// Not yet in the spec: https://github.com/itanium-cxx-abi/cxx-abi/issues/47 +template +Node *AbstractManglingParser::parsePointerToMemberConversionExpr() { + Node *Ty = getDerived().parseType(); + if (!Ty) + return nullptr; + Node *Expr = getDerived().parseExpr(); + if (!Expr) + return nullptr; + StringView Offset = getDerived().parseNumber(true); + if (!consumeIf('E')) + return nullptr; + return make(Ty, Expr, Offset); +} + +// ::= so [] * [p] E +// ::= _ [] +// +// Not yet in the spec: https://github.com/itanium-cxx-abi/cxx-abi/issues/47 +template +Node *AbstractManglingParser::parseSubobjectExpr() { + Node *Ty = getDerived().parseType(); + if (!Ty) + return nullptr; + Node *Expr = getDerived().parseExpr(); + if (!Expr) + return nullptr; + StringView Offset = getDerived().parseNumber(true); + size_t SelectorsBegin = Names.size(); + while (consumeIf('_')) { + Node *Selector = make(parseNumber()); + if (!Selector) + return nullptr; + Names.push_back(Selector); + } + bool OnePastTheEnd = consumeIf('p'); + if (!consumeIf('E')) + return nullptr; + return make( + Ty, Expr, Offset, popTrailingNodeArray(SelectorsBegin), OnePastTheEnd); +} + // ::= // ::= // ::= @@ -4679,6 +4783,9 @@ Node *AbstractManglingParser::parseExpr() { return nullptr; case 'm': switch (First[1]) { + case 'c': + First += 2; + return parsePointerToMemberConversionExpr(); case 'i': First += 2; return getDerived().parseBinaryExpr("-"); @@ -4826,6 +4933,9 @@ Node *AbstractManglingParser::parseExpr() { return Ex; return make("static_cast", T, Ex); } + case 'o': + First += 2; + return parseSubobjectExpr(); case 'p': { First += 2; Node *Child = getDerived().parseExpr(); @@ -4993,6 +5103,16 @@ Node *AbstractManglingParser::parseSpecialName() { switch (look()) { case 'T': switch (look(1)) { + // TA # template parameter object + // + // Not yet in the spec: https://github.com/itanium-cxx-abi/cxx-abi/issues/63 + case 'A': { + First += 2; + Node *Arg = getDerived().parseTemplateArg(); + if (Arg == nullptr) + return nullptr; + return make("template parameter object for ", Arg); + } // TV # virtual table case 'V': { First += 2; diff --git a/llvm/include/llvm/ExecutionEngine/Orc/OrcRPCTargetProcessControl.h b/llvm/include/llvm/ExecutionEngine/Orc/OrcRPCTargetProcessControl.h index b498661021ae3..0bc209120ce79 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/OrcRPCTargetProcessControl.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/OrcRPCTargetProcessControl.h @@ -94,7 +94,7 @@ class OrcRPCTPCJITLinkMemoryManager : public jitlink::JITLinkMemoryManager { << " bytes to " << ((Prot & orcrpctpc::WPF_Read) ? 'R' : '-') << ((Prot & orcrpctpc::WPF_Write) ? 'W' : '-') << ((Prot & orcrpctpc::WPF_Exec) ? 'X' : '-') - << " segment: local " << (void *)B.Buffer.data() + << " segment: local " << (const void *)B.Buffer.data() << " -> target " << formatv("{0:x16}", B.Address) << "\n"; } }); diff --git a/llvm/include/llvm/Frontend/OpenMP/OMP.td b/llvm/include/llvm/Frontend/OpenMP/OMP.td index 1ecf075c38a9e..3a93dd73edeb0 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMP.td +++ b/llvm/include/llvm/Frontend/OpenMP/OMP.td @@ -200,7 +200,7 @@ def OMPC_NumTasks : Clause<"num_tasks"> { } def OMPC_Hint : Clause<"hint"> { let clangClass = "OMPHintClause"; - let flangClass = "ConstantExpr"; + let flangClassValue = "ConstantExpr"; } def OMPC_DistSchedule : Clause<"dist_schedule"> { let clangClass = "OMPDistScheduleClause"; @@ -895,7 +895,12 @@ def OMP_Distribute : Directive<"distribute"> { VersionedClause ]; } -def OMP_DeclareTarget : Directive<"declare target"> {} +def OMP_DeclareTarget : Directive<"declare target"> { + let allowedClauses = [ + VersionedClause, + VersionedClause + ]; +} def OMP_EndDeclareTarget : Directive<"end declare target"> {} def OMP_DistributeParallelFor : Directive<"distribute parallel for"> { let allowedClauses = [ @@ -1606,9 +1611,24 @@ def OMP_ParallelWorkshare : Directive<"parallel workshare"> { def OMP_Workshare : Directive<"workshare"> {} def OMP_EndDo : Directive<"end do"> {} def OMP_EndDoSimd : Directive<"end do simd"> {} -def OMP_EndSections : Directive<"end sections"> {} -def OMP_EndSingle : Directive<"end single"> {} -def OMP_EndWorkshare : Directive<"end workshare"> {} +def OMP_EndSections : Directive<"end sections"> { + let allowedOnceClauses = [ + VersionedClause + ]; +} +def OMP_EndSingle : Directive<"end single"> { + let allowedClauses = [ + VersionedClause + ]; + let allowedOnceClauses = [ + VersionedClause + ]; +} +def OMP_EndWorkshare : Directive<"end workshare"> { + let allowedClauses = [ + VersionedClause + ]; +} def OMP_Unknown : Directive<"unknown"> { let isDefault = true; } diff --git a/llvm/include/llvm/IR/BasicBlock.h b/llvm/include/llvm/IR/BasicBlock.h index 24d568a728c6a..26cfdd9e51d69 100644 --- a/llvm/include/llvm/IR/BasicBlock.h +++ b/llvm/include/llvm/IR/BasicBlock.h @@ -165,19 +165,24 @@ class BasicBlock final : public Value, // Basic blocks are data objects also } /// Returns a pointer to the first instruction in this block that is not a - /// PHINode or a debug intrinsic. - const Instruction* getFirstNonPHIOrDbg() const; - Instruction* getFirstNonPHIOrDbg() { + /// PHINode or a debug intrinsic, or any pseudo operation if \c SkipPseudoOp + /// is true. + const Instruction *getFirstNonPHIOrDbg(bool SkipPseudoOp = false) const; + Instruction *getFirstNonPHIOrDbg(bool SkipPseudoOp = false) { return const_cast( - static_cast(this)->getFirstNonPHIOrDbg()); + static_cast(this)->getFirstNonPHIOrDbg( + SkipPseudoOp)); } /// Returns a pointer to the first instruction in this block that is not a - /// PHINode, a debug intrinsic, or a lifetime intrinsic. - const Instruction* getFirstNonPHIOrDbgOrLifetime() const; - Instruction* getFirstNonPHIOrDbgOrLifetime() { + /// PHINode, a debug intrinsic, or a lifetime intrinsic, or any pseudo + /// operation if \c SkipPseudoOp is true. + const Instruction * + getFirstNonPHIOrDbgOrLifetime(bool SkipPseudoOp = false) const; + Instruction *getFirstNonPHIOrDbgOrLifetime(bool SkipPseudoOp = false) { return const_cast( - static_cast(this)->getFirstNonPHIOrDbgOrLifetime()); + static_cast(this)->getFirstNonPHIOrDbgOrLifetime( + SkipPseudoOp)); } /// Returns an iterator to the first instruction in this block that is @@ -191,16 +196,18 @@ class BasicBlock final : public Value, // Basic blocks are data objects also } /// Return a const iterator range over the instructions in the block, skipping - /// any debug instructions. + /// any debug instructions. Skip any pseudo operations as well if \c + /// SkipPseudoOp is true. iterator_range>> - instructionsWithoutDebug() const; + instructionsWithoutDebug(bool SkipPseudoOp = false) const; /// Return an iterator range over the instructions in the block, skipping any - /// debug instructions. - iterator_range>> - instructionsWithoutDebug(); + /// debug instructions. Skip and any pseudo operations as well if \c + /// SkipPseudoOp is true. + iterator_range< + filter_iterator>> + instructionsWithoutDebug(bool SkipPseudoOp = false); /// Return the size of the basic block ignoring debug instructions filter_iteratorgetValueID() == UndefValueVal; + return V->getValueID() == UndefValueVal || + V->getValueID() == PoisonValueVal; + } +}; + +//===----------------------------------------------------------------------===// +/// In order to facilitate speculative execution, many instructions do not +/// invoke immediate undefined behavior when provided with illegal operands, +/// and return a poison value instead. +/// +/// see LangRef.html#poisonvalues for details. +/// +class PoisonValue final : public UndefValue { + friend class Constant; + + explicit PoisonValue(Type *T) : UndefValue(T, PoisonValueVal) {} + + void destroyConstantImpl(); + +public: + PoisonValue(const PoisonValue &) = delete; + + /// Static factory methods - Return an 'poison' object of the specified type. + static PoisonValue *get(Type *T); + + /// If this poison has array or vector type, return a poison with the right + /// element type. + PoisonValue *getSequentialElement() const; + + /// If this poison has struct type, return a poison with the right element + /// type for the specified element. + PoisonValue *getStructElement(unsigned Elt) const; + + /// Return an poison of the right value for the specified GEP index if we can, + /// otherwise return null (e.g. if C is a ConstantExpr). + PoisonValue *getElementValue(Constant *C) const; + + /// Return an poison of the right value for the specified GEP index. + PoisonValue *getElementValue(unsigned Idx) const; + + /// Methods for support type inquiry through isa, cast, and dyn_cast: + static bool classof(const Value *V) { + return V->getValueID() == PoisonValueVal; } }; diff --git a/llvm/include/llvm/IR/Function.h b/llvm/include/llvm/IR/Function.h index 061223d3bd780..1736b3ed0363b 100644 --- a/llvm/include/llvm/IR/Function.h +++ b/llvm/include/llvm/IR/Function.h @@ -472,14 +472,12 @@ class Function : public GlobalObject, public ilist_node { /// Extract the byval type for a parameter. Type *getParamByValType(unsigned ArgNo) const { - Type *Ty = AttributeSets.getParamByValType(ArgNo); - return Ty ? Ty : (arg_begin() + ArgNo)->getType()->getPointerElementType(); + return AttributeSets.getParamByValType(ArgNo); } /// Extract the sret type for a parameter. Type *getParamStructRetType(unsigned ArgNo) const { - Type *Ty = AttributeSets.getParamStructRetType(ArgNo); - return Ty ? Ty : (arg_begin() + ArgNo)->getType()->getPointerElementType(); + return AttributeSets.getParamStructRetType(ArgNo); } /// Extract the byref type for a parameter. diff --git a/llvm/include/llvm/IR/InstrTypes.h b/llvm/include/llvm/IR/InstrTypes.h index 5d3b603ad01b1..1091c4b0dc0fe 100644 --- a/llvm/include/llvm/IR/InstrTypes.h +++ b/llvm/include/llvm/IR/InstrTypes.h @@ -1338,7 +1338,7 @@ class CallBase : public Instruction { /// Returns true if this CallSite passes the given Value* as an argument to /// the called function. bool hasArgument(const Value *V) const { - return llvm::any_of(args(), [V](const Value *Arg) { return Arg == V; }); + return llvm::is_contained(args(), V); } Value *getCalledOperand() const { return Op(); } diff --git a/llvm/include/llvm/IR/Instruction.h b/llvm/include/llvm/IR/Instruction.h index ef83a250a5803..d2a55f89fac98 100644 --- a/llvm/include/llvm/IR/Instruction.h +++ b/llvm/include/llvm/IR/Instruction.h @@ -651,19 +651,25 @@ class Instruction : public User, bool isLifetimeStartOrEnd() const; /// Return a pointer to the next non-debug instruction in the same basic - /// block as 'this', or nullptr if no such instruction exists. - const Instruction *getNextNonDebugInstruction() const; - Instruction *getNextNonDebugInstruction() { + /// block as 'this', or nullptr if no such instruction exists. Skip any pseudo + /// operations if \c SkipPseudoOp is true. + const Instruction * + getNextNonDebugInstruction(bool SkipPseudoOp = false) const; + Instruction *getNextNonDebugInstruction(bool SkipPseudoOp = false) { return const_cast( - static_cast(this)->getNextNonDebugInstruction()); + static_cast(this)->getNextNonDebugInstruction( + SkipPseudoOp)); } /// Return a pointer to the previous non-debug instruction in the same basic - /// block as 'this', or nullptr if no such instruction exists. - const Instruction *getPrevNonDebugInstruction() const; - Instruction *getPrevNonDebugInstruction() { + /// block as 'this', or nullptr if no such instruction exists. Skip any pseudo + /// operations if \c SkipPseudoOp is true. + const Instruction * + getPrevNonDebugInstruction(bool SkipPseudoOp = false) const; + Instruction *getPrevNonDebugInstruction(bool SkipPseudoOp = false) { return const_cast( - static_cast(this)->getPrevNonDebugInstruction()); + static_cast(this)->getPrevNonDebugInstruction( + SkipPseudoOp)); } /// Create a copy of 'this' instruction that is identical in all ways except diff --git a/llvm/include/llvm/IR/Instructions.h b/llvm/include/llvm/IR/Instructions.h index ea1a60d52c877..eb855972256b1 100644 --- a/llvm/include/llvm/IR/Instructions.h +++ b/llvm/include/llvm/IR/Instructions.h @@ -106,7 +106,7 @@ class AllocaInst : public UnaryInstruction { /// Get allocation size in bits. Returns None if size can't be determined, /// e.g. in case of a VLA. - Optional getAllocationSizeInBits(const DataLayout &DL) const; + Optional getAllocationSizeInBits(const DataLayout &DL) const; /// Return the type that is being allocated by the instruction. Type *getAllocatedType() const { return AllocatedType; } diff --git a/llvm/include/llvm/IR/IntrinsicInst.h b/llvm/include/llvm/IR/IntrinsicInst.h index 9ba9ea68f9898..52504582dd1d3 100644 --- a/llvm/include/llvm/IR/IntrinsicInst.h +++ b/llvm/include/llvm/IR/IntrinsicInst.h @@ -967,6 +967,28 @@ class InstrProfValueProfileInst : public IntrinsicInst { } }; +class PseudoProbeInst : public IntrinsicInst { +public: + static bool classof(const IntrinsicInst *I) { + return I->getIntrinsicID() == Intrinsic::pseudoprobe; + } + + static bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } + + ConstantInt *getFuncGuid() const { + return cast(const_cast(getArgOperand(0))); + } + + ConstantInt *getAttributes() const { + return cast(const_cast(getArgOperand(2))); + } + + ConstantInt *getIndex() const { + return cast(const_cast(getArgOperand(1))); + } +}; } // end namespace llvm #endif // LLVM_IR_INTRINSICINST_H diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index 0ea46c51544f5..6f7317827ef87 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -1277,6 +1277,13 @@ def int_donothing : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrWillReturn]>; // which specify that infinite loops must be preserved. def int_sideeffect : DefaultAttrsIntrinsic<[], [], [IntrInaccessibleMemOnly, IntrWillReturn]>; +// The pseudoprobe intrinsic works as a place holder to the block it probes. +// Like the sideeffect intrinsic defined above, this intrinsic is treated by the +// optimizer as having opaque side effects so that it won't be get rid of or moved +// out of the block it probes. +def int_pseudoprobe : Intrinsic<[], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty], + [IntrInaccessibleMemOnly, IntrWillReturn]>; + // Intrinsics to support half precision floating point format let IntrProperties = [IntrNoMem, IntrWillReturn] in { def int_convert_to_fp16 : DefaultAttrsIntrinsic<[llvm_i16_ty], [llvm_anyfloat_ty]>; diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h index c78ea48b43786..c25573b9f8a65 100644 --- a/llvm/include/llvm/IR/PatternMatch.h +++ b/llvm/include/llvm/IR/PatternMatch.h @@ -96,6 +96,9 @@ inline class_match m_ConstantInt() { /// Match an arbitrary undef constant. inline class_match m_Undef() { return class_match(); } +/// Match an arbitrary poison constant. +inline class_match m_Poison() { return class_match(); } + /// Match an arbitrary Constant and ignore it. inline class_match m_Constant() { return class_match(); } diff --git a/llvm/include/llvm/IR/PredIteratorCache.h b/llvm/include/llvm/IR/PredIteratorCache.h index cc835277910bf..4d8efcfa9eab8 100644 --- a/llvm/include/llvm/IR/PredIteratorCache.h +++ b/llvm/include/llvm/IR/PredIteratorCache.h @@ -58,7 +58,7 @@ class PredIteratorCache { auto Result = BlockToPredCountMap.find(BB); if (Result != BlockToPredCountMap.end()) return Result->second; - return BlockToPredCountMap[BB] = std::distance(pred_begin(BB), pred_end(BB)); + return BlockToPredCountMap[BB] = pred_size(BB); } public: diff --git a/llvm/include/llvm/IR/Value.def b/llvm/include/llvm/IR/Value.def index 0a14b94a501dc..0a0125d319c3d 100644 --- a/llvm/include/llvm/IR/Value.def +++ b/llvm/include/llvm/IR/Value.def @@ -88,6 +88,7 @@ HANDLE_CONSTANT(ConstantVector) // ConstantData. HANDLE_CONSTANT(UndefValue) +HANDLE_CONSTANT(PoisonValue) HANDLE_CONSTANT(ConstantAggregateZero) HANDLE_CONSTANT(ConstantDataArray) HANDLE_CONSTANT(ConstantDataVector) diff --git a/llvm/include/llvm/InterfaceStub/ELFObjHandler.h b/llvm/include/llvm/InterfaceStub/ELFObjHandler.h index 1ffd9a614eecd..cbb9420cb666f 100644 --- a/llvm/include/llvm/InterfaceStub/ELFObjHandler.h +++ b/llvm/include/llvm/InterfaceStub/ELFObjHandler.h @@ -23,9 +23,21 @@ class MemoryBuffer; namespace elfabi { +enum class ELFTarget { ELF32LE, ELF32BE, ELF64LE, ELF64BE }; + /// Attempt to read a binary ELF file from a MemoryBuffer. Expected> readELFFile(MemoryBufferRef Buf); +/// Attempt to write a binary ELF stub. +/// This function determines appropriate ELFType using the passed ELFTarget and +/// then writes a binary ELF stub to a specified file path. +/// +/// @param FilePath File path for writing the ELF binary. +/// @param Stub Source ELFStub to generate a binary ELF stub from. +/// @param OutputFormat Target ELFType to write binary as. +Error writeBinaryStub(StringRef FilePath, const ELFStub &Stub, + ELFTarget OutputFormat); + } // end namespace elfabi } // end namespace llvm diff --git a/llvm/include/llvm/LinkAllPasses.h b/llvm/include/llvm/LinkAllPasses.h index e9135a46e5f7c..233a8bc4a17a1 100644 --- a/llvm/include/llvm/LinkAllPasses.h +++ b/llvm/include/llvm/LinkAllPasses.h @@ -246,7 +246,7 @@ namespace { llvm::TargetLibraryInfo TLI(TLII); llvm::AliasAnalysis AA(TLI); llvm::AliasSetTracker X(AA); - X.add(nullptr, llvm::LocationSize::unknown(), + X.add(nullptr, llvm::LocationSize::beforeOrAfterPointer(), llvm::AAMDNodes()); // for -print-alias-sets (void) llvm::AreStatisticsEnabled(); (void) llvm::sys::RunningOnValgrind(); diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h index 6a0ef5360cd4b..9581a08fc5cfb 100644 --- a/llvm/include/llvm/MC/MCStreamer.h +++ b/llvm/include/llvm/MC/MCStreamer.h @@ -206,6 +206,7 @@ class MCStreamer { std::vector> WinFrameInfos; WinEH::FrameInfo *CurrentWinFrameInfo; + size_t CurrentProcWinFrameInfoStartIndex; /// Tracks an index to represent the order a symbol was emitted in. /// Zero means we did not emit that symbol. @@ -244,6 +245,8 @@ class MCStreamer { return CurrentWinFrameInfo; } + virtual void EmitWindowsUnwindTables(WinEH::FrameInfo *Frame); + virtual void EmitWindowsUnwindTables(); virtual void emitRawTextImpl(StringRef String); diff --git a/llvm/include/llvm/MC/MCSymbolWasm.h b/llvm/include/llvm/MC/MCSymbolWasm.h index 52ff9f933f928..ae512fd27be2d 100644 --- a/llvm/include/llvm/MC/MCSymbolWasm.h +++ b/llvm/include/llvm/MC/MCSymbolWasm.h @@ -96,6 +96,15 @@ class MCSymbolWasm : public MCSymbol { StringRef getExportName() const { return ExportName.getValue(); } void setExportName(StringRef Name) { ExportName = Name; } + bool isFunctionTable() const { + return isTable() && hasTableType() && + getTableType() == wasm::ValType::FUNCREF; + } + void setFunctionTable() { + setType(wasm::WASM_SYMBOL_TYPE_TABLE); + setTableType(wasm::ValType::FUNCREF); + } + void setUsedInGOT() const { IsUsedInGOT = true; } bool isUsedInGOT() const { return IsUsedInGOT; } @@ -111,8 +120,9 @@ class MCSymbolWasm : public MCSymbol { } void setGlobalType(wasm::WasmGlobalType GT) { GlobalType = GT; } - const wasm::ValType &getTableType() const { - assert(TableType.hasValue()); + bool hasTableType() const { return TableType.hasValue(); } + wasm::ValType getTableType() const { + assert(hasTableType()); return TableType.getValue(); } void setTableType(wasm::ValType TT) { TableType = TT; } diff --git a/llvm/include/llvm/MC/MCWin64EH.h b/llvm/include/llvm/MC/MCWin64EH.h index 60ec06e61b7c8..065161d1759e6 100644 --- a/llvm/include/llvm/MC/MCWin64EH.h +++ b/llvm/include/llvm/MC/MCWin64EH.h @@ -53,14 +53,15 @@ struct Instruction { class UnwindEmitter : public WinEH::UnwindEmitter { public: void Emit(MCStreamer &Streamer) const override; - void EmitUnwindInfo(MCStreamer &Streamer, WinEH::FrameInfo *FI) const override; + void EmitUnwindInfo(MCStreamer &Streamer, WinEH::FrameInfo *FI, + bool HandlerData) const override; }; class ARM64UnwindEmitter : public WinEH::UnwindEmitter { public: void Emit(MCStreamer &Streamer) const override; - void EmitUnwindInfo(MCStreamer &Streamer, - WinEH::FrameInfo *FI) const override; + void EmitUnwindInfo(MCStreamer &Streamer, WinEH::FrameInfo *FI, + bool HandlerData) const override; }; } diff --git a/llvm/include/llvm/MC/MCWinEH.h b/llvm/include/llvm/MC/MCWinEH.h index a46f56d708ce7..5688255810d02 100644 --- a/llvm/include/llvm/MC/MCWinEH.h +++ b/llvm/include/llvm/MC/MCWinEH.h @@ -80,7 +80,8 @@ class UnwindEmitter { /// This emits the unwind info sections (.pdata and .xdata in PE/COFF). virtual void Emit(MCStreamer &Streamer) const = 0; - virtual void EmitUnwindInfo(MCStreamer &Streamer, FrameInfo *FI) const = 0; + virtual void EmitUnwindInfo(MCStreamer &Streamer, FrameInfo *FI, + bool HandlerData) const = 0; }; } } diff --git a/llvm/include/llvm/Object/ELF.h b/llvm/include/llvm/Object/ELF.h index 7ebe6869c7b5e..d47c8f7809fe2 100644 --- a/llvm/include/llvm/Object/ELF.h +++ b/llvm/include/llvm/Object/ELF.h @@ -238,9 +238,9 @@ class ELFFile { assert(Phdr.p_type == ELF::PT_NOTE && "Phdr is not of type PT_NOTE"); ErrorAsOutParameter ErrAsOutParam(&Err); if (Phdr.p_offset + Phdr.p_filesz > getBufSize()) { - Err = createError("PT_NOTE header has invalid offset (0x" + - Twine::utohexstr(Phdr.p_offset) + ") or size (0x" + - Twine::utohexstr(Phdr.p_filesz) + ")"); + Err = + createError("invalid offset (0x" + Twine::utohexstr(Phdr.p_offset) + + ") or size (0x" + Twine::utohexstr(Phdr.p_filesz) + ")"); return Elf_Note_Iterator(Err); } return Elf_Note_Iterator(base() + Phdr.p_offset, Phdr.p_filesz, Err); @@ -257,10 +257,9 @@ class ELFFile { assert(Shdr.sh_type == ELF::SHT_NOTE && "Shdr is not of type SHT_NOTE"); ErrorAsOutParameter ErrAsOutParam(&Err); if (Shdr.sh_offset + Shdr.sh_size > getBufSize()) { - Err = createError("SHT_NOTE section " + getSecIndexForError(*this, Shdr) + - " has invalid offset (0x" + - Twine::utohexstr(Shdr.sh_offset) + ") or size (0x" + - Twine::utohexstr(Shdr.sh_size) + ")"); + Err = + createError("invalid offset (0x" + Twine::utohexstr(Shdr.sh_offset) + + ") or size (0x" + Twine::utohexstr(Shdr.sh_size) + ")"); return Elf_Note_Iterator(Err); } return Elf_Note_Iterator(base() + Shdr.sh_offset, Shdr.sh_size, Err); diff --git a/llvm/include/llvm/Object/Wasm.h b/llvm/include/llvm/Object/Wasm.h index 72e4403a45cbe..e5091f5a85523 100644 --- a/llvm/include/llvm/Object/Wasm.h +++ b/llvm/include/llvm/Object/Wasm.h @@ -299,6 +299,7 @@ class WasmObjectFile : public ObjectFile { uint32_t DataSection = 0; uint32_t EventSection = 0; uint32_t GlobalSection = 0; + uint32_t TableSection = 0; }; class WasmSectionOrderChecker { diff --git a/llvm/include/llvm/Object/XCOFFObjectFile.h b/llvm/include/llvm/Object/XCOFFObjectFile.h index b649c12717f16..ba1df5e8dc0a9 100644 --- a/llvm/include/llvm/Object/XCOFFObjectFile.h +++ b/llvm/include/llvm/Object/XCOFFObjectFile.h @@ -469,7 +469,7 @@ class XCOFFTracebackTable { bool hasVectorInfo() const; bool hasExtensionTable() const; - uint8_t getNumofGPRsSaved() const; + uint8_t getNumOfGPRsSaved() const; uint8_t getNumberOfFixedParms() const; diff --git a/llvm/include/llvm/ObjectYAML/ELFYAML.h b/llvm/include/llvm/ObjectYAML/ELFYAML.h index 058d78d4f4fdf..9015fb680b605 100644 --- a/llvm/include/llvm/ObjectYAML/ELFYAML.h +++ b/llvm/include/llvm/ObjectYAML/ELFYAML.h @@ -658,6 +658,9 @@ struct Object { unsigned getMachine() const; }; +bool shouldAllocateFileSpace(ArrayRef Phdrs, + const NoBitsSection &S); + } // end namespace ELFYAML } // end namespace llvm diff --git a/llvm/include/llvm/PassAnalysisSupport.h b/llvm/include/llvm/PassAnalysisSupport.h index 84df171d38d85..4e28466c4968f 100644 --- a/llvm/include/llvm/PassAnalysisSupport.h +++ b/llvm/include/llvm/PassAnalysisSupport.h @@ -183,7 +183,7 @@ class AnalysisResolver { } /// Return analysis result or null if it doesn't exist. - Pass *getAnalysisIfAvailable(AnalysisID ID, bool Direction) const; + Pass *getAnalysisIfAvailable(AnalysisID ID) const; private: /// This keeps track of which passes implements the interfaces that are @@ -207,7 +207,7 @@ AnalysisType *Pass::getAnalysisIfAvailable() const { const void *PI = &AnalysisType::ID; - Pass *ResultPass = Resolver->getAnalysisIfAvailable(PI, true); + Pass *ResultPass = Resolver->getAnalysisIfAvailable(PI); if (!ResultPass) return nullptr; // Because the AnalysisType may not be a subclass of pass (for diff --git a/llvm/include/llvm/Passes/PassBuilder.h b/llvm/include/llvm/Passes/PassBuilder.h index 97e0b19ed07f0..fb1a83306f556 100644 --- a/llvm/include/llvm/Passes/PassBuilder.h +++ b/llvm/include/llvm/Passes/PassBuilder.h @@ -597,6 +597,15 @@ class PassBuilder { PipelineStartEPCallbacks.push_back(C); } + /// Register a callback for a default optimizer pipeline extension point. + /// + /// This extension point allows adding optimization right after passes that do + /// basic simplification of the input IR. + void registerPipelineEarlySimplificationEPCallback( + const std::function &C) { + PipelineEarlySimplificationEPCallbacks.push_back(C); + } + /// Register a callback for a default optimizer pipeline extension point /// /// This extension point allows adding optimizations at the very end of the @@ -729,6 +738,9 @@ class PassBuilder { // Module callbacks SmallVector, 2> PipelineStartEPCallbacks; + SmallVector, 2> + PipelineEarlySimplificationEPCallbacks; + SmallVector, 2> ModuleAnalysisRegistrationCallbacks; SmallVectorgetIDom())) return false; - auto RIt = llvm::find(DT.Roots, To->getBlock()); - if (RIt == DT.Roots.end()) + if (!llvm::is_contained(DT.Roots, To->getBlock())) return false; // To is not a root, nothing to update. LLVM_DEBUG(dbgs() << "\t\tAfter the insertion, " << BlockNamePrinter(To) @@ -925,7 +924,7 @@ struct SemiNCAInfo { // The check is O(N), so run it only in debug configuration. auto IsSuccessor = [BUI](const NodePtr SuccCandidate, const NodePtr Of) { auto Successors = getChildren(Of, BUI); - return llvm::find(Successors, SuccCandidate) != Successors.end(); + return llvm::is_contained(Successors, SuccCandidate); }; (void)IsSuccessor; assert(!IsSuccessor(To, From) && "Deleted edge still exists in the CFG!"); @@ -1059,7 +1058,7 @@ struct SemiNCAInfo { const TreeNodePtr TN = DT.getNode(To); assert(TN); if (TN->getLevel() > Level) return true; - if (llvm::find(AffectedQueue, To) == AffectedQueue.end()) + if (!llvm::is_contained(AffectedQueue, To)) AffectedQueue.push_back(To); return false; diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def index 38eb51b84ba7e..a63d40484089f 100644 --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -110,6 +110,9 @@ HANDLE_TARGET_OPCODE(BUNDLE) HANDLE_TARGET_OPCODE(LIFETIME_START) HANDLE_TARGET_OPCODE(LIFETIME_END) +/// Pseudo probe +HANDLE_TARGET_OPCODE(PSEUDO_PROBE) + /// A Stackmap instruction captures the location of live variables at its /// position in the instruction stream. It is followed by a shadow of bytes /// that must lie within the function and not contain another stackmap. diff --git a/llvm/include/llvm/TableGen/Record.h b/llvm/include/llvm/TableGen/Record.h index 2ff4df462b040..567908f93e55a 100644 --- a/llvm/include/llvm/TableGen/Record.h +++ b/llvm/include/llvm/TableGen/Record.h @@ -597,7 +597,13 @@ class IntInit : public TypedInit { /// "foo" - Represent an initialization by a string value. class StringInit : public TypedInit { +//// enum StringFormat { +//// SF_String, // Format as "text" +//// SF_Code, // Format as [{text}] +//// }; + StringRef Value; +//// StringFormat Format; explicit StringInit(StringRef V) : TypedInit(IK_StringInit, StringRecTy::get()), Value(V) {} @@ -630,11 +636,10 @@ class StringInit : public TypedInit { class CodeInit : public TypedInit { StringRef Value; - SMLoc Loc; - explicit CodeInit(StringRef V, const SMLoc &Loc) + explicit CodeInit(StringRef V) : TypedInit(IK_CodeInit, static_cast(CodeRecTy::get())), - Value(V), Loc(Loc) {} + Value(V) {} public: CodeInit(const StringInit &) = delete; @@ -644,10 +649,9 @@ class CodeInit : public TypedInit { return I->getKind() == IK_CodeInit; } - static CodeInit *get(StringRef, const SMLoc &Loc); + static CodeInit *get(StringRef); StringRef getValue() const { return Value; } - const SMLoc &getLoc() const { return Loc; } Init *convertInitializerTo(RecTy *Ty) const override; @@ -1649,6 +1653,9 @@ class Record { // High-level methods useful to tablegen back-ends // + ///Return the source location for the named field. + SMLoc getFieldLoc(StringRef FieldName) const; + /// Return the initializer for a value with the specified name, /// or throw an exception if the field does not exist. Init *getValueInit(StringRef FieldName) const; diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td index 96fbfcc1f3812..9664f70c7a02f 100644 --- a/llvm/include/llvm/Target/Target.td +++ b/llvm/include/llvm/Target/Target.td @@ -1145,6 +1145,13 @@ def LIFETIME_END : StandardPseudoInstruction { let AsmString = "LIFETIME_END"; let hasSideEffects = false; } +def PSEUDO_PROBE : StandardPseudoInstruction { + let OutOperandList = (outs); + let InOperandList = (ins i64imm:$guid, i64imm:$index, i8imm:$type, i32imm:$attr); + let AsmString = "PSEUDO_PROBE"; + let hasSideEffects = 1; +} + def STACKMAP : StandardPseudoInstruction { let OutOperandList = (outs); let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops); diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h index 3b41b97e0c892..14ec0a37b3fef 100644 --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -243,6 +243,10 @@ class TargetMachine { Options.SupportsDebugEntryValues = Enable; } + bool getAIXExtendedAltivecABI() const { + return Options.EnableAIXExtendedAltivecABI; + } + bool getUniqueSectionNames() const { return Options.UniqueSectionNames; } /// Return true if unique basic block section names must be generated. diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h index 4c27ce0e09b8b..8cc0b95b26dae 100644 --- a/llvm/include/llvm/Target/TargetOptions.h +++ b/llvm/include/llvm/Target/TargetOptions.h @@ -124,6 +124,7 @@ namespace llvm { TargetOptions() : UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false), NoTrappingFPMath(true), NoSignedZerosFPMath(false), + EnableAIXExtendedAltivecABI(false), HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false), GuaranteedTailCallOpt(false), StackSymbolOrdering(true), EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false), @@ -175,6 +176,12 @@ namespace llvm { /// argument or result as insignificant. unsigned NoSignedZerosFPMath : 1; + /// EnableAIXExtendedAltivecABI - This flag returns true when -vec-extabi is + /// specified. The code generator is then able to use both volatile and + /// nonvolitle vector regisers. When false, the code generator only uses + /// volatile vector registers which is the default setting on AIX. + unsigned EnableAIXExtendedAltivecABI : 1; + /// HonorSignDependentRoundingFPMath - This returns true when the /// -enable-sign-dependent-rounding-fp-math is specified. If this returns /// false (the default), the code generator is allowed to assume that the diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td index 20a51cea35ecb..e37cdc8d301e3 100644 --- a/llvm/include/llvm/Target/TargetSelectionDAG.td +++ b/llvm/include/llvm/Target/TargetSelectionDAG.td @@ -440,8 +440,8 @@ def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; -def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; -def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>; +def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp, [SDNPCommutative]>; +def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp, [SDNPCommutative]>; def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp, [SDNPCommutative, SDNPAssociative]>; @@ -498,7 +498,7 @@ def strict_fdiv : SDNode<"ISD::STRICT_FDIV", def strict_frem : SDNode<"ISD::STRICT_FREM", SDTFPBinOp, [SDNPHasChain]>; def strict_fma : SDNode<"ISD::STRICT_FMA", - SDTFPTernaryOp, [SDNPHasChain]>; + SDTFPTernaryOp, [SDNPHasChain, SDNPCommutative]>; def strict_fsqrt : SDNode<"ISD::STRICT_FSQRT", SDTFPUnaryOp, [SDNPHasChain]>; def strict_fsin : SDNode<"ISD::STRICT_FSIN", diff --git a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h index ae8d545d6112b..2be9ef10ac4fb 100644 --- a/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h +++ b/llvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h @@ -311,8 +311,8 @@ class LoopVectorizationLegality { unsigned getMaxSafeDepDistBytes() { return LAI->getMaxSafeDepDistBytes(); } - uint64_t getMaxSafeRegisterWidth() const { - return LAI->getDepChecker().getMaxSafeRegisterWidth(); + uint64_t getMaxSafeVectorWidthInBits() const { + return LAI->getDepChecker().getMaxSafeVectorWidthInBits(); } bool hasStride(Value *V) { return LAI->hasStride(V); } diff --git a/llvm/lib/Analysis/AliasAnalysisEvaluator.cpp b/llvm/lib/Analysis/AliasAnalysisEvaluator.cpp index b1433c579af81..bbfa82bcca6ad 100644 --- a/llvm/lib/Analysis/AliasAnalysisEvaluator.cpp +++ b/llvm/lib/Analysis/AliasAnalysisEvaluator.cpp @@ -140,13 +140,13 @@ void AAEvaluator::runInternal(Function &F, AAResults &AA) { // iterate over the worklist, and run the full (n^2)/2 disambiguations for (SetVector::iterator I1 = Pointers.begin(), E = Pointers.end(); I1 != E; ++I1) { - auto I1Size = LocationSize::unknown(); + auto I1Size = LocationSize::afterPointer(); Type *I1ElTy = cast((*I1)->getType())->getElementType(); if (I1ElTy->isSized()) I1Size = LocationSize::precise(DL.getTypeStoreSize(I1ElTy)); for (SetVector::iterator I2 = Pointers.begin(); I2 != I1; ++I2) { - auto I2Size = LocationSize::unknown(); + auto I2Size = LocationSize::afterPointer(); Type *I2ElTy = cast((*I2)->getType())->getElementType(); if (I2ElTy->isSized()) I2Size = LocationSize::precise(DL.getTypeStoreSize(I2ElTy)); @@ -231,7 +231,7 @@ void AAEvaluator::runInternal(Function &F, AAResults &AA) { // Mod/ref alias analysis: compare all pairs of calls and values for (CallBase *Call : Calls) { for (auto Pointer : Pointers) { - auto Size = LocationSize::unknown(); + auto Size = LocationSize::afterPointer(); Type *ElTy = cast(Pointer->getType())->getElementType(); if (ElTy->isSized()) Size = LocationSize::precise(DL.getTypeStoreSize(ElTy)); diff --git a/llvm/lib/Analysis/AliasSetTracker.cpp b/llvm/lib/Analysis/AliasSetTracker.cpp index 6f8f192d0d968..77dba3444e3da 100644 --- a/llvm/lib/Analysis/AliasSetTracker.cpp +++ b/llvm/lib/Analysis/AliasSetTracker.cpp @@ -439,6 +439,7 @@ void AliasSetTracker::addUnknown(Instruction *Inst) { // FIXME: Add lifetime/invariant intrinsics (See: PR30807). case Intrinsic::assume: case Intrinsic::sideeffect: + case Intrinsic::pseudoprobe: return; } } @@ -670,8 +671,10 @@ void AliasSet::print(raw_ostream &OS) const { for (iterator I = begin(), E = end(); I != E; ++I) { if (I != begin()) OS << ", "; I.getPointer()->printAsOperand(OS << "("); - if (I.getSize() == LocationSize::unknown()) - OS << ", unknown)"; + if (I.getSize() == LocationSize::afterPointer()) + OS << ", unknown after)"; + else if (I.getSize() == LocationSize::beforeOrAfterPointer()) + OS << ", unknown before-or-after)"; else OS << ", " << I.getSize() << ")"; } diff --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp b/llvm/lib/Analysis/BasicAliasAnalysis.cpp index 944ff8e9917b5..0f13f98868cf2 100644 --- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp +++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp @@ -416,15 +416,17 @@ static unsigned getMaxPointerSize(const DataLayout &DL) { /// can look through. To be able to do that getUnderlyingObject and /// DecomposeGEPExpression must use the same search depth /// (MaxLookupSearchDepth). -bool BasicAAResult::DecomposeGEPExpression(const Value *V, - DecomposedGEP &Decomposed, const DataLayout &DL, AssumptionCache *AC, - DominatorTree *DT) { +BasicAAResult::DecomposedGEP +BasicAAResult::DecomposeGEPExpression(const Value *V, const DataLayout &DL, + AssumptionCache *AC, DominatorTree *DT) { // Limit recursion depth to limit compile time in crazy cases. unsigned MaxLookup = MaxLookupSearchDepth; SearchTimes++; unsigned MaxPointerSize = getMaxPointerSize(DL); - Decomposed.VarIndices.clear(); + DecomposedGEP Decomposed; + Decomposed.Offset = APInt(MaxPointerSize, 0); + Decomposed.HasCompileTimeConstantScale = true; do { // See if this is a bitcast or GEP. const Operator *Op = dyn_cast(V); @@ -437,7 +439,7 @@ bool BasicAAResult::DecomposeGEPExpression(const Value *V, } } Decomposed.Base = V; - return false; + return Decomposed; } if (Op->getOpcode() == Instruction::BitCast || @@ -471,13 +473,13 @@ bool BasicAAResult::DecomposeGEPExpression(const Value *V, } Decomposed.Base = V; - return false; + return Decomposed; } // Don't attempt to analyze GEPs over unsized objects. if (!GEPOp->getSourceElementType()->isSized()) { Decomposed.Base = V; - return false; + return Decomposed; } // Don't attempt to analyze GEPs if index scale is not a compile-time @@ -485,7 +487,7 @@ bool BasicAAResult::DecomposeGEPExpression(const Value *V, if (isa(GEPOp->getSourceElementType())) { Decomposed.Base = V; Decomposed.HasCompileTimeConstantScale = false; - return false; + return Decomposed; } unsigned AS = GEPOp->getPointerAddressSpace(); @@ -513,9 +515,8 @@ bool BasicAAResult::DecomposeGEPExpression(const Value *V, if (CIdx->isZero()) continue; Decomposed.Offset += - (DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize() * - CIdx->getValue().sextOrSelf(MaxPointerSize)) - .sextOrTrunc(MaxPointerSize); + DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize() * + CIdx->getValue().sextOrTrunc(MaxPointerSize); continue; } @@ -599,7 +600,7 @@ bool BasicAAResult::DecomposeGEPExpression(const Value *V, // If the chain of expressions is too deep, just return early. Decomposed.Base = V; SearchLimitReached++; - return true; + return Decomposed; } /// Returns whether the given pointer value points to memory that is local to @@ -876,8 +877,8 @@ ModRefInfo BasicAAResult::getModRefInfo(const CallBase *Call, // If this is a no-capture pointer argument, see if we can tell that it // is impossible to alias the pointer we're checking. AliasResult AR = getBestAAResults().alias( - MemoryLocation(*CI, LocationSize::unknown()), - MemoryLocation(Object, LocationSize::unknown()), AAQI); + MemoryLocation::getBeforeOrAfter(*CI), + MemoryLocation::getBeforeOrAfter(Object), AAQI); if (AR != MustAlias) IsMustAlias = false; // Operand doesn't alias 'Object', continue looking for other aliases @@ -923,7 +924,7 @@ ModRefInfo BasicAAResult::getModRefInfo(const CallBase *Call, if (isMallocOrCallocLikeFn(Call, &TLI)) { // Be conservative if the accessed pointer may alias the allocation - // fallback to the generic handling below. - if (getBestAAResults().alias(MemoryLocation(Call, LocationSize::unknown()), + if (getBestAAResults().alias(MemoryLocation::getBeforeOrAfter(Call), Loc, AAQI) == NoAlias) return ModRefInfo::NoModRef; } @@ -1217,15 +1218,8 @@ AliasResult BasicAAResult::aliasGEP( const GEPOperator *GEP1, LocationSize V1Size, const AAMDNodes &V1AAInfo, const Value *V2, LocationSize V2Size, const AAMDNodes &V2AAInfo, const Value *UnderlyingV1, const Value *UnderlyingV2, AAQueryInfo &AAQI) { - DecomposedGEP DecompGEP1, DecompGEP2; - unsigned MaxPointerSize = getMaxPointerSize(DL); - DecompGEP1.Offset = APInt(MaxPointerSize, 0); - DecompGEP2.Offset = APInt(MaxPointerSize, 0); - DecompGEP1.HasCompileTimeConstantScale = - DecompGEP2.HasCompileTimeConstantScale = true; - - DecomposeGEPExpression(GEP1, DecompGEP1, DL, &AC, DT); - DecomposeGEPExpression(V2, DecompGEP2, DL, &AC, DT); + DecomposedGEP DecompGEP1 = DecomposeGEPExpression(GEP1, DL, &AC, DT); + DecomposedGEP DecompGEP2 = DecomposeGEPExpression(V2, DL, &AC, DT); // Don't attempt to analyze the decomposed GEP if index scale is not a // compile-time constant. @@ -1233,9 +1227,6 @@ AliasResult BasicAAResult::aliasGEP( !DecompGEP2.HasCompileTimeConstantScale) return MayAlias; - APInt GEP1BaseOffset = DecompGEP1.Offset; - APInt GEP2BaseOffset = DecompGEP2.Offset; - assert(DecompGEP1.Base == UnderlyingV1 && DecompGEP2.Base == UnderlyingV2 && "DecomposeGEPExpression returned a result different from " "getUnderlyingObject"); @@ -1254,13 +1245,13 @@ AliasResult BasicAAResult::aliasGEP( if (isGEPBaseAtNegativeOffset(GEP2, DecompGEP2, DecompGEP1, V1Size)) return NoAlias; // Do the base pointers alias? - AliasResult BaseAlias = - aliasCheck(UnderlyingV1, LocationSize::unknown(), AAMDNodes(), - UnderlyingV2, LocationSize::unknown(), AAMDNodes(), AAQI); + AliasResult BaseAlias = aliasCheck( + UnderlyingV1, LocationSize::beforeOrAfterPointer(), AAMDNodes(), + UnderlyingV2, LocationSize::beforeOrAfterPointer(), AAMDNodes(), AAQI); // For GEPs with identical offsets, we can preserve the size and AAInfo // when performing the alias check on the underlying objects. - if (BaseAlias == MayAlias && GEP1BaseOffset == GEP2BaseOffset && + if (BaseAlias == MayAlias && DecompGEP1.Offset == DecompGEP2.Offset && DecompGEP1.VarIndices == DecompGEP2.VarIndices) { AliasResult PreciseBaseAlias = aliasCheck( UnderlyingV1, V1Size, V1AAInfo, UnderlyingV2, V2Size, V2AAInfo, AAQI); @@ -1292,7 +1283,7 @@ AliasResult BasicAAResult::aliasGEP( // Subtract the GEP2 pointer from the GEP1 pointer to find out their // symbolic difference. - GEP1BaseOffset -= GEP2BaseOffset; + DecompGEP1.Offset -= DecompGEP2.Offset; GetIndexDifference(DecompGEP1.VarIndices, DecompGEP2.VarIndices); } else { @@ -1304,9 +1295,9 @@ AliasResult BasicAAResult::aliasGEP( if (!V1Size.hasValue() && !V2Size.hasValue()) return MayAlias; - AliasResult R = aliasCheck(UnderlyingV1, LocationSize::unknown(), - AAMDNodes(), V2, LocationSize::unknown(), - V2AAInfo, AAQI, nullptr, UnderlyingV2); + AliasResult R = aliasCheck( + UnderlyingV1, LocationSize::beforeOrAfterPointer(), AAMDNodes(), + V2, V2Size, V2AAInfo, AAQI, nullptr, UnderlyingV2); if (R != MustAlias) { // If V2 may alias GEP base pointer, conservatively returns MayAlias. // If V2 is known not to alias GEP base pointer, then the two values @@ -1324,17 +1315,17 @@ AliasResult BasicAAResult::aliasGEP( // // In the other case, if we have getelementptr , 0, 0, 0, 0, ... and V2 // must aliases the GEP, the end result is a must alias also. - if (GEP1BaseOffset == 0 && DecompGEP1.VarIndices.empty()) + if (DecompGEP1.Offset == 0 && DecompGEP1.VarIndices.empty()) return MustAlias; // If there is a constant difference between the pointers, but the difference // is less than the size of the associated memory object, then we know // that the objects are partially overlapping. If the difference is // greater, we know they do not overlap. - if (GEP1BaseOffset != 0 && DecompGEP1.VarIndices.empty()) { - if (GEP1BaseOffset.sge(0)) { + if (DecompGEP1.Offset != 0 && DecompGEP1.VarIndices.empty()) { + if (DecompGEP1.Offset.sge(0)) { if (V2Size.hasValue()) { - if (GEP1BaseOffset.ult(V2Size.getValue())) + if (DecompGEP1.Offset.ult(V2Size.getValue())) return PartialAlias; return NoAlias; } @@ -1348,7 +1339,7 @@ AliasResult BasicAAResult::aliasGEP( // We need to know that V2Size is not unknown, otherwise we might have // stripped a gep with negative index ('gep , -1, ...). if (V1Size.hasValue() && V2Size.hasValue()) { - if ((-GEP1BaseOffset).ult(V1Size.getValue())) + if ((-DecompGEP1.Offset).ult(V1Size.getValue())) return PartialAlias; return NoAlias; } @@ -1357,8 +1348,8 @@ AliasResult BasicAAResult::aliasGEP( if (!DecompGEP1.VarIndices.empty()) { APInt GCD; - bool AllNonNegative = GEP1BaseOffset.isNonNegative(); - bool AllNonPositive = GEP1BaseOffset.isNonPositive(); + bool AllNonNegative = DecompGEP1.Offset.isNonNegative(); + bool AllNonPositive = DecompGEP1.Offset.isNonPositive(); for (unsigned i = 0, e = DecompGEP1.VarIndices.size(); i != e; ++i) { const APInt &Scale = DecompGEP1.VarIndices[i].Scale; if (i == 0) @@ -1391,12 +1382,12 @@ AliasResult BasicAAResult::aliasGEP( } // We now have accesses at two offsets from the same base: - // 1. (...)*GCD + GEP1BaseOffset with size V1Size + // 1. (...)*GCD + DecompGEP1.Offset with size V1Size // 2. 0 with size V2Size // Using arithmetic modulo GCD, the accesses are at // [ModOffset..ModOffset+V1Size) and [0..V2Size). If the first access fits // into the range [V2Size..GCD), then we know they cannot overlap. - APInt ModOffset = GEP1BaseOffset.srem(GCD); + APInt ModOffset = DecompGEP1.Offset.srem(GCD); if (ModOffset.isNegative()) ModOffset += GCD; // We want mod, not rem. if (V1Size.hasValue() && V2Size.hasValue() && @@ -1405,22 +1396,22 @@ AliasResult BasicAAResult::aliasGEP( return NoAlias; // If we know all the variables are non-negative, then the total offset is - // also non-negative and >= GEP1BaseOffset. We have the following layout: + // also non-negative and >= DecompGEP1.Offset. We have the following layout: // [0, V2Size) ... [TotalOffset, TotalOffer+V1Size] - // If GEP1BaseOffset >= V2Size, the accesses don't alias. + // If DecompGEP1.Offset >= V2Size, the accesses don't alias. if (AllNonNegative && V2Size.hasValue() && - GEP1BaseOffset.uge(V2Size.getValue())) + DecompGEP1.Offset.uge(V2Size.getValue())) return NoAlias; // Similarly, if the variables are non-positive, then the total offset is - // also non-positive and <= GEP1BaseOffset. We have the following layout: + // also non-positive and <= DecompGEP1.Offset. We have the following layout: // [TotalOffset, TotalOffset+V1Size) ... [0, V2Size) - // If -GEP1BaseOffset >= V1Size, the accesses don't alias. + // If -DecompGEP1.Offset >= V1Size, the accesses don't alias. if (AllNonPositive && V1Size.hasValue() && - (-GEP1BaseOffset).uge(V1Size.getValue())) + (-DecompGEP1.Offset).uge(V1Size.getValue())) return NoAlias; if (constantOffsetHeuristic(DecompGEP1.VarIndices, V1Size, V2Size, - GEP1BaseOffset, &AC, DT)) + DecompGEP1.Offset, &AC, DT)) return NoAlias; } @@ -1498,8 +1489,10 @@ AliasResult BasicAAResult::aliasPHI(const PHINode *PN, LocationSize PNSize, // operand from outside the PHIs' cycle that is MayAlias/MustAlias or // there must be an operation on the PHIs within the PHIs' value cycle // that causes a MayAlias. - // Pretend the phis do not alias. - AliasResult Alias = NoAlias; + // Disable persistent caching, so intermediate results based on a + // possibly incorrect assumption do not get cached. + bool OrigDisableCache = DisableCache; + DisableCache = true; AliasResult OrigAliasResult; { // Limited lifetime iterator invalidated by the aliasCheck call below. @@ -1510,6 +1503,7 @@ AliasResult BasicAAResult::aliasPHI(const PHINode *PN, LocationSize PNSize, CacheIt->second = NoAlias; } + AliasResult Alias = NoAlias; for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { AliasResult ThisAlias = aliasCheck(PN->getIncomingValue(i), PNSize, PNAAInfo, @@ -1523,6 +1517,7 @@ AliasResult BasicAAResult::aliasPHI(const PHINode *PN, LocationSize PNSize, // Reset if speculation failed. if (Alias != NoAlias) AAQI.updateResult(Locs, OrigAliasResult); + DisableCache = OrigDisableCache; return Alias; } @@ -1597,7 +1592,11 @@ AliasResult BasicAAResult::aliasPHI(const PHINode *PN, LocationSize PNSize, // unknown to represent all the possible values the GEP could advance the // pointer to. if (isRecursive) - PNSize = LocationSize::unknown(); + // TODO: We are checking above that the addrec GEP has a positive offset + // and can thus assume that all accesses happen after the base pointer. + // It might be better to drop the offset requirement and use + // beforeOrAfterPointer(). + PNSize = LocationSize::afterPointer(); // In the recursive alias queries below, we may compare values from two // different loop iterations. Keep track of visited phi blocks, which will @@ -1735,6 +1734,18 @@ AliasResult BasicAAResult::aliasCheck(const Value *V1, LocationSize V1Size, TLI, NullIsValidLocation))) return NoAlias; + // If one the accesses may be before the accessed pointer, canonicalize this + // by using unknown after-pointer sizes for both accesses. This is + // equivalent, because regardless of which pointer is lower, one of them + // will always came after the other, as long as the underlying objects aren't + // disjoint. We do this so that the rest of BasicAA does not have to deal + // with accesses before the base pointer, and to improve cache utilization by + // merging equivalent states. + if (V1Size.mayBeBeforePointer() || V2Size.mayBeBeforePointer()) { + V1Size = LocationSize::afterPointer(); + V2Size = LocationSize::afterPointer(); + } + // Check the cache before climbing up use-def chains. This also terminates // otherwise infinitely recursive queries. AAQueryInfo::LocPair Locs(MemoryLocation(V1, V1Size, V1AAInfo), @@ -1746,57 +1757,73 @@ AliasResult BasicAAResult::aliasCheck(const Value *V1, LocationSize V1Size, if (!Pair.second) return Pair.first->second; - // FIXME: This isn't aggressively handling alias(GEP, PHI) for example: if the - // GEP can't simplify, we don't even look at the PHI cases. + AliasResult Result = aliasCheckRecursive(V1, V1Size, V1AAInfo, V2, V2Size, + V2AAInfo, AAQI, O1, O2); + + // If caching is disabled, remove the entry once the recursive checks are + // done. We only needed it to prevent infinite recursion. + if (DisableCache) + AAQI.AliasCache.erase(AAQI.AliasCache.find(Locs)); + else if (Result != MayAlias) + AAQI.updateResult(Locs, Result); + return Result; +} + +AliasResult BasicAAResult::aliasCheckRecursive( + const Value *V1, LocationSize V1Size, const AAMDNodes &V1AAInfo, + const Value *V2, LocationSize V2Size, const AAMDNodes &V2AAInfo, + AAQueryInfo &AAQI, const Value *O1, const Value *O2) { if (const GEPOperator *GV1 = dyn_cast(V1)) { AliasResult Result = aliasGEP(GV1, V1Size, V1AAInfo, V2, V2Size, V2AAInfo, O1, O2, AAQI); if (Result != MayAlias) - return AAQI.updateResult(Locs, Result); + return Result; } else if (const GEPOperator *GV2 = dyn_cast(V2)) { AliasResult Result = aliasGEP(GV2, V2Size, V2AAInfo, V1, V1Size, V1AAInfo, O2, O1, AAQI); if (Result != MayAlias) - return AAQI.updateResult(Locs, Result); + return Result; } if (const PHINode *PN = dyn_cast(V1)) { AliasResult Result = aliasPHI(PN, V1Size, V1AAInfo, V2, V2Size, V2AAInfo, O2, AAQI); if (Result != MayAlias) - return AAQI.updateResult(Locs, Result); + return Result; } else if (const PHINode *PN = dyn_cast(V2)) { AliasResult Result = aliasPHI(PN, V2Size, V2AAInfo, V1, V1Size, V1AAInfo, O1, AAQI); if (Result != MayAlias) - return AAQI.updateResult(Locs, Result); + return Result; } if (const SelectInst *S1 = dyn_cast(V1)) { AliasResult Result = aliasSelect(S1, V1Size, V1AAInfo, V2, V2Size, V2AAInfo, O2, AAQI); if (Result != MayAlias) - return AAQI.updateResult(Locs, Result); + return Result; } else if (const SelectInst *S2 = dyn_cast(V2)) { AliasResult Result = aliasSelect(S2, V2Size, V2AAInfo, V1, V1Size, V1AAInfo, O1, AAQI); if (Result != MayAlias) - return AAQI.updateResult(Locs, Result); + return Result; } // If both pointers are pointing into the same object and one of them // accesses the entire object, then the accesses must overlap in some way. - if (O1 == O2) + if (O1 == O2) { + bool NullIsValidLocation = NullPointerIsDefined(&F); if (V1Size.isPrecise() && V2Size.isPrecise() && (isObjectSize(O1, V1Size.getValue(), DL, TLI, NullIsValidLocation) || isObjectSize(O2, V2Size.getValue(), DL, TLI, NullIsValidLocation))) - return AAQI.updateResult(Locs, PartialAlias); + return PartialAlias; + } // Recurse back into the best AA results we have, potentially with refined // memory locations. We have already ensured that BasicAA has a MayAlias // cache result for these, so any recursion back into BasicAA won't loop. - AliasResult Result = getBestAAResults().alias(Locs.first, Locs.second, AAQI); - return AAQI.updateResult(Locs, Result); + return getBestAAResults().alias(MemoryLocation(V1, V1Size, V1AAInfo), + MemoryLocation(V2, V2Size, V2AAInfo), AAQI); } /// Check whether two Values can be considered equivalent. diff --git a/llvm/lib/Analysis/CGSCCPassManager.cpp b/llvm/lib/Analysis/CGSCCPassManager.cpp index 627ad03cd045c..95d2ebf5f9fbe 100644 --- a/llvm/lib/Analysis/CGSCCPassManager.cpp +++ b/llvm/lib/Analysis/CGSCCPassManager.cpp @@ -20,6 +20,7 @@ #include "llvm/IR/Instruction.h" #include "llvm/IR/PassManager.h" #include "llvm/IR/PassManagerImpl.h" +#include "llvm/IR/ValueHandle.h" #include "llvm/Support/Casting.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" @@ -476,9 +477,9 @@ static LazyCallGraph::SCC &updateCGAndAnalysisManagerForPass( // First walk the function and handle all called functions. We do this first // because if there is a single call edge, whether there are ref edges is // irrelevant. - for (Instruction &I : instructions(F)) - if (auto *CB = dyn_cast(&I)) - if (Function *Callee = CB->getCalledFunction()) + for (Instruction &I : instructions(F)) { + if (auto *CB = dyn_cast(&I)) { + if (Function *Callee = CB->getCalledFunction()) { if (Visited.insert(Callee).second && !Callee->isDeclaration()) { Node *CalleeN = G.lookup(*Callee); if (!CalleeN) { @@ -498,6 +499,17 @@ static LazyCallGraph::SCC &updateCGAndAnalysisManagerForPass( else if (!E->isCall()) PromotedRefTargets.insert(CalleeN); } + } else { + // We can miss devirtualization if an indirect call is created then + // promoted before updateCGAndAnalysisManagerForPass runs. + auto *Entry = UR.IndirectVHs.find(CB); + if (Entry == UR.IndirectVHs.end()) + UR.IndirectVHs.insert({CB, WeakTrackingVH(CB)}); + else if (!Entry->second) + Entry->second = WeakTrackingVH(CB); + } + } + } // Now walk all references. for (Instruction &I : instructions(F)) diff --git a/llvm/lib/Analysis/CallGraphSCCPass.cpp b/llvm/lib/Analysis/CallGraphSCCPass.cpp index 2de18fe3863d6..de5cada85fe2b 100644 --- a/llvm/lib/Analysis/CallGraphSCCPass.cpp +++ b/llvm/lib/Analysis/CallGraphSCCPass.cpp @@ -43,8 +43,8 @@ using namespace llvm; #define DEBUG_TYPE "cgscc-passmgr" -static cl::opt -MaxIterations("max-cg-scc-iterations", cl::ReallyHidden, cl::init(4)); +cl::opt MaxDevirtIterations("max-devirt-iterations", cl::ReallyHidden, + cl::init(4)); STATISTIC(MaxSCCIterations, "Maximum CGSCCPassMgr iterations on one SCC"); @@ -539,12 +539,12 @@ bool CGPassManager::runOnModule(Module &M) { << '\n'); DevirtualizedCall = false; Changed |= RunAllPassesOnSCC(CurSCC, CG, DevirtualizedCall); - } while (Iteration++ < MaxIterations && DevirtualizedCall); + } while (Iteration++ < MaxDevirtIterations && DevirtualizedCall); if (DevirtualizedCall) LLVM_DEBUG(dbgs() << " CGSCCPASSMGR: Stopped iteration after " << Iteration - << " times, due to -max-cg-scc-iterations\n"); + << " times, due to -max-devirt-iterations\n"); MaxSCCIterations.updateMax(Iteration); } diff --git a/llvm/lib/Analysis/DependenceAnalysis.cpp b/llvm/lib/Analysis/DependenceAnalysis.cpp index b5e28e731ade4..c2c61131e40e5 100644 --- a/llvm/lib/Analysis/DependenceAnalysis.cpp +++ b/llvm/lib/Analysis/DependenceAnalysis.cpp @@ -653,8 +653,10 @@ static AliasResult underlyingObjectsAlias(AAResults *AA, const MemoryLocation &LocB) { // Check the original locations (minus size) for noalias, which can happen for // tbaa, incompatible underlying object locations, etc. - MemoryLocation LocAS(LocA.Ptr, LocationSize::unknown(), LocA.AATags); - MemoryLocation LocBS(LocB.Ptr, LocationSize::unknown(), LocB.AATags); + MemoryLocation LocAS = + MemoryLocation::getBeforeOrAfter(LocA.Ptr, LocA.AATags); + MemoryLocation LocBS = + MemoryLocation::getBeforeOrAfter(LocB.Ptr, LocB.AATags); if (AA->alias(LocAS, LocBS) == NoAlias) return NoAlias; diff --git a/llvm/lib/Analysis/DivergenceAnalysis.cpp b/llvm/lib/Analysis/DivergenceAnalysis.cpp index d01a0b95612cc..c10971dab95cc 100644 --- a/llvm/lib/Analysis/DivergenceAnalysis.cpp +++ b/llvm/lib/Analysis/DivergenceAnalysis.cpp @@ -84,7 +84,6 @@ #include "llvm/IR/Value.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" -#include using namespace llvm; diff --git a/llvm/lib/Analysis/DomTreeUpdater.cpp b/llvm/lib/Analysis/DomTreeUpdater.cpp index 9594da0a4f91d..e690d64913564 100644 --- a/llvm/lib/Analysis/DomTreeUpdater.cpp +++ b/llvm/lib/Analysis/DomTreeUpdater.cpp @@ -32,8 +32,7 @@ bool DomTreeUpdater::isUpdateValid( // Since isUpdateValid() must be called *after* the Terminator of From is // altered we can determine if the update is unnecessary for batch updates // or invalid for a single update. - const bool HasEdge = llvm::any_of( - successors(From), [To](const BasicBlock *B) { return B == To; }); + const bool HasEdge = llvm::is_contained(successors(From), To); // If the IR does not match the update, // 1. In batch updates, this update is unnecessary. diff --git a/llvm/lib/Analysis/GlobalsModRef.cpp b/llvm/lib/Analysis/GlobalsModRef.cpp index e17aefc28a273..89bbd9b08afce 100644 --- a/llvm/lib/Analysis/GlobalsModRef.cpp +++ b/llvm/lib/Analysis/GlobalsModRef.cpp @@ -44,7 +44,7 @@ STATISTIC(NumIndirectGlobalVars, "Number of indirect global objects"); // An option to enable unsafe alias results from the GlobalsModRef analysis. // When enabled, GlobalsModRef will provide no-alias results which in extremely // rare cases may not be conservatively correct. In particular, in the face of -// transforms which cause assymetry between how effective getUnderlyingObject +// transforms which cause asymmetry between how effective getUnderlyingObject // is for two pointers, it may produce incorrect results. // // These unsafe results have been returned by GMR for many years without @@ -932,8 +932,8 @@ ModRefInfo GlobalsAAResult::getModRefInfoForArgument(const CallBase *Call, if (!all_of(Objects, isIdentifiedObject) && // Try ::alias to see if all objects are known not to alias GV. !all_of(Objects, [&](const Value *V) { - return this->alias(MemoryLocation(V, LocationSize::unknown()), - MemoryLocation(GV, LocationSize::unknown()), + return this->alias(MemoryLocation::getBeforeOrAfter(V), + MemoryLocation::getBeforeOrAfter(GV), AAQI) == NoAlias; })) return ConservativeResult; diff --git a/llvm/lib/Analysis/IVDescriptors.cpp b/llvm/lib/Analysis/IVDescriptors.cpp index 86cbcb015f0f6..a5cc622279c4e 100644 --- a/llvm/lib/Analysis/IVDescriptors.cpp +++ b/llvm/lib/Analysis/IVDescriptors.cpp @@ -578,6 +578,7 @@ RecurrenceDescriptor::isRecurrenceInstr(Instruction *I, RecurrenceKind Kind, return InstDesc(Kind == RK_IntegerOr, I); case Instruction::Xor: return InstDesc(Kind == RK_IntegerXor, I); + case Instruction::FDiv: case Instruction::FMul: return InstDesc(Kind == RK_FloatMult, I, UAI); case Instruction::FSub: diff --git a/llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp b/llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp index c32aa0340cebe..b112ed2e4439f 100644 --- a/llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp +++ b/llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp @@ -22,9 +22,7 @@ #include "llvm/ProfileData/InstrProf.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" -#include -#include -#include +#include using namespace llvm; diff --git a/llvm/lib/Analysis/InlineCost.cpp b/llvm/lib/Analysis/InlineCost.cpp index 0a2de5d4ba9b7..f6a1f2dc38797 100644 --- a/llvm/lib/Analysis/InlineCost.cpp +++ b/llvm/lib/Analysis/InlineCost.cpp @@ -1101,7 +1101,7 @@ bool CallAnalyzer::visitPtrToInt(PtrToIntInst &I) { // integer is large enough to represent the pointer. unsigned IntegerSize = I.getType()->getScalarSizeInBits(); unsigned AS = I.getOperand(0)->getType()->getPointerAddressSpace(); - if (IntegerSize >= DL.getPointerSizeInBits(AS)) { + if (IntegerSize == DL.getPointerSizeInBits(AS)) { std::pair BaseAndOffset = ConstantOffsetPtrs.lookup(I.getOperand(0)); if (BaseAndOffset.first) @@ -1911,6 +1911,10 @@ CallAnalyzer::analyzeBlock(BasicBlock *BB, if (isa(I)) continue; + // Skip pseudo-probes. + if (isa(I)) + continue; + // Skip ephemeral values. if (EphValues.count(&*I)) continue; @@ -2574,7 +2578,7 @@ InlineCostAnnotationPrinterPass::run(Function &F, // We can add a flag which determines InlineParams for this run. Right now, // the default InlineParams are used. const InlineParams Params = llvm::getInlineParams(); - for (BasicBlock &BB : F) { + for (BasicBlock &BB : F) { for (Instruction &I : BB) { if (CallInst *CI = dyn_cast(&I)) { Function *CalledFunction = CI->getCalledFunction(); diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index 813fb6c89863b..6b116eb0ed000 100644 --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -4136,7 +4136,8 @@ static Value *SimplifySelectInst(Value *Cond, Value *TrueVal, Value *FalseVal, // Deal with partial undef vector constants: select ?, VecC, VecC' --> VecC'' Constant *TrueC, *FalseC; - if (TrueVal->getType()->isVectorTy() && match(TrueVal, m_Constant(TrueC)) && + if (isa(TrueVal->getType()) && + match(TrueVal, m_Constant(TrueC)) && match(FalseVal, m_Constant(FalseC))) { unsigned NumElts = cast(TrueC->getType())->getNumElements(); diff --git a/llvm/lib/Analysis/Lint.cpp b/llvm/lib/Analysis/Lint.cpp index 002ac16529913..e188c23cf32b2 100644 --- a/llvm/lib/Analysis/Lint.cpp +++ b/llvm/lib/Analysis/Lint.cpp @@ -190,8 +190,8 @@ void Lint::visitFunction(Function &F) { void Lint::visitCallBase(CallBase &I) { Value *Callee = I.getCalledOperand(); - visitMemoryReference(I, MemoryLocation(Callee, LocationSize::unknown()), - None, nullptr, MemRef::Callee); + visitMemoryReference(I, MemoryLocation::getAfter(Callee), None, nullptr, + MemRef::Callee); if (Function *F = dyn_cast(findValue(Callee, /*OffsetOk=*/false))) { @@ -295,7 +295,7 @@ void Lint::visitCallBase(CallBase &I) { // Check that the memcpy arguments don't overlap. The AliasAnalysis API // isn't expressive enough for what we really want to do. Known partial // overlap is not distinguished from the case where nothing is known. - auto Size = LocationSize::unknown(); + auto Size = LocationSize::afterPointer(); if (const ConstantInt *Len = dyn_cast(findValue(MCI->getLength(), /*OffsetOk=*/false))) @@ -586,9 +586,8 @@ void Lint::visitVAArgInst(VAArgInst &I) { } void Lint::visitIndirectBrInst(IndirectBrInst &I) { - visitMemoryReference( - I, MemoryLocation(I.getAddress(), LocationSize::unknown()), - None, nullptr, MemRef::Branchee); + visitMemoryReference(I, MemoryLocation::getAfter(I.getAddress()), None, + nullptr, MemRef::Branchee); Assert(I.getNumDestinations() != 0, "Undefined behavior: indirectbr with no destinations", &I); diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp index 34de1a052ddfd..65d39161c1be4 100644 --- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp +++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp @@ -149,27 +149,23 @@ const SCEV *llvm::replaceSymbolicStrideSCEV(PredicatedScalarEvolution &PSE, // symbolic stride replaced by one. ValueToValueMap::const_iterator SI = PtrToStride.find(OrigPtr ? OrigPtr : Ptr); - if (SI != PtrToStride.end()) { - Value *StrideVal = SI->second; + if (SI == PtrToStride.end()) + // For a non-symbolic stride, just return the original expression. + return OrigSCEV; - // Strip casts. - StrideVal = stripIntegerCast(StrideVal); + Value *StrideVal = stripIntegerCast(SI->second); - ScalarEvolution *SE = PSE.getSE(); - const auto *U = cast(SE->getSCEV(StrideVal)); - const auto *CT = - static_cast(SE->getOne(StrideVal->getType())); + ScalarEvolution *SE = PSE.getSE(); + const auto *U = cast(SE->getSCEV(StrideVal)); + const auto *CT = + static_cast(SE->getOne(StrideVal->getType())); - PSE.addPredicate(*SE->getEqualPredicate(U, CT)); - auto *Expr = PSE.getSCEV(Ptr); + PSE.addPredicate(*SE->getEqualPredicate(U, CT)); + auto *Expr = PSE.getSCEV(Ptr); - LLVM_DEBUG(dbgs() << "LAA: Replacing SCEV: " << *OrigSCEV - << " by: " << *Expr << "\n"); - return Expr; - } - - // Otherwise, just return the SCEV of the original pointer. - return OrigSCEV; + LLVM_DEBUG(dbgs() << "LAA: Replacing SCEV: " << *OrigSCEV + << " by: " << *Expr << "\n"); + return Expr; } RuntimeCheckingPtrGroup::RuntimeCheckingPtrGroup( @@ -228,9 +224,9 @@ void RuntimePointerChecking::insert(Loop *Lp, Value *Ptr, bool WritePtr, } // Add the size of the pointed element to ScEnd. auto &DL = Lp->getHeader()->getModule()->getDataLayout(); - unsigned EltSize = - DL.getTypeStoreSizeInBits(Ptr->getType()->getPointerElementType()) / 8; - const SCEV *EltSizeSCEV = SE->getConstant(ScEnd->getType(), EltSize); + Type *IdxTy = DL.getIndexType(Ptr->getType()); + const SCEV *EltSizeSCEV = + SE->getStoreSizeOfExpr(IdxTy, Ptr->getType()->getPointerElementType()); ScEnd = SE->getAddExpr(ScEnd, EltSizeSCEV); } @@ -518,7 +514,7 @@ class AccessAnalysis { /// Register a load and whether it is only read from. void addLoad(MemoryLocation &Loc, bool IsReadOnly) { Value *Ptr = const_cast(Loc.Ptr); - AST.add(Ptr, LocationSize::unknown(), Loc.AATags); + AST.add(Ptr, LocationSize::beforeOrAfterPointer(), Loc.AATags); Accesses.insert(MemAccessInfo(Ptr, false)); if (IsReadOnly) ReadOnlyPtr.insert(Ptr); @@ -527,7 +523,7 @@ class AccessAnalysis { /// Register a store. void addStore(MemoryLocation &Loc) { Value *Ptr = const_cast(Loc.Ptr); - AST.add(Ptr, LocationSize::unknown(), Loc.AATags); + AST.add(Ptr, LocationSize::beforeOrAfterPointer(), Loc.AATags); Accesses.insert(MemAccessInfo(Ptr, true)); } @@ -1658,7 +1654,7 @@ MemoryDepChecker::isDependent(const MemAccessInfo &A, unsigned AIdx, LLVM_DEBUG(dbgs() << "LAA: Positive distance " << Val.getSExtValue() << " with max VF = " << MaxVF << '\n'); uint64_t MaxVFInBits = MaxVF * TypeByteSize * 8; - MaxSafeRegisterWidth = std::min(MaxSafeRegisterWidth, MaxVFInBits); + MaxSafeVectorWidthInBits = std::min(MaxSafeVectorWidthInBits, MaxVFInBits); return Dependence::BackwardVectorizable; } @@ -1807,7 +1803,7 @@ bool LoopAccessInfo::canAnalyzeLoop() { // ScalarEvolution needs to be able to find the exit count. const SCEV *ExitCount = PSE->getBackedgeTakenCount(); - if (ExitCount == PSE->getSE()->getCouldNotCompute()) { + if (isa(ExitCount)) { recordAnalysis("CantComputeNumberOfIterations") << "could not determine number of loop iterations"; LLVM_DEBUG(dbgs() << "LAA: SCEV could not compute the loop exit count.\n"); @@ -2150,12 +2146,8 @@ bool LoopAccessInfo::isUniform(Value *V) const { } void LoopAccessInfo::collectStridedAccess(Value *MemAccess) { - Value *Ptr = nullptr; - if (LoadInst *LI = dyn_cast(MemAccess)) - Ptr = LI->getPointerOperand(); - else if (StoreInst *SI = dyn_cast(MemAccess)) - Ptr = SI->getPointerOperand(); - else + Value *Ptr = getLoadStorePointerOperand(MemAccess); + if (!Ptr) return; Value *Stride = getStrideFromPointer(Ptr, PSE->getSE(), TheLoop); diff --git a/llvm/lib/Analysis/MemDerefPrinter.cpp b/llvm/lib/Analysis/MemDerefPrinter.cpp index 564410b8af083..0078ceacbad24 100644 --- a/llvm/lib/Analysis/MemDerefPrinter.cpp +++ b/llvm/lib/Analysis/MemDerefPrinter.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/Analysis/MemDerefPrinter.h" #include "llvm/Analysis/Loads.h" #include "llvm/Analysis/Passes.h" #include "llvm/IR/DataLayout.h" @@ -17,6 +18,7 @@ #include "llvm/Pass.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" + using namespace llvm; namespace { @@ -76,3 +78,35 @@ void MemDerefPrinter::print(raw_ostream &OS, const Module *M) const { OS << "\n\n"; } } + +PreservedAnalyses MemDerefPrinterPass::run(Function &F, + FunctionAnalysisManager &AM) { + OS << "Memory Dereferencibility of pointers in function '" << F.getName() + << "'\n"; + + SmallVector Deref; + SmallPtrSet DerefAndAligned; + + const DataLayout &DL = F.getParent()->getDataLayout(); + for (auto &I : instructions(F)) { + if (LoadInst *LI = dyn_cast(&I)) { + Value *PO = LI->getPointerOperand(); + if (isDereferenceablePointer(PO, LI->getType(), DL)) + Deref.push_back(PO); + if (isDereferenceableAndAlignedPointer( + PO, LI->getType(), MaybeAlign(LI->getAlignment()), DL)) + DerefAndAligned.insert(PO); + } + } + + OS << "The following are dereferenceable:\n"; + for (Value *V : Deref) { + V->print(OS); + if (DerefAndAligned.count(V)) + OS << "\t(aligned)"; + else + OS << "\t(unaligned)"; + OS << "\n\n"; + } + return PreservedAnalyses::all(); +} diff --git a/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp b/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp index ab01059066826..9f2629c00a7d9 100644 --- a/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp +++ b/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp @@ -148,7 +148,7 @@ static ModRefInfo GetLocation(const Instruction *Inst, MemoryLocation &Loc, if (const CallInst *CI = isFreeCall(Inst, &TLI)) { // calls to free() deallocate the entire structure - Loc = MemoryLocation(CI->getArgOperand(0), LocationSize::unknown()); + Loc = MemoryLocation::getAfter(CI->getArgOperand(0)); return ModRefInfo::Mod; } @@ -455,7 +455,7 @@ MemDepResult MemoryDependenceResults::getSimplePointerDependencyFrom( // pointer, not on query pointers that are indexed off of them. It'd // be nice to handle that at some point (the right approach is to use // GetPointerBaseWithConstantOffset). - MemoryLocation ArgLoc(II->getArgOperand(1), LocationSize::unknown()); + MemoryLocation ArgLoc = MemoryLocation::getAfter(II->getArgOperand(1)); if (BatchAA.isMustAlias(ArgLoc, MemLoc)) return MemDepResult::getDef(II); continue; diff --git a/llvm/lib/Analysis/MemoryLocation.cpp b/llvm/lib/Analysis/MemoryLocation.cpp index 8d58679dd42b3..39c9070027334 100644 --- a/llvm/lib/Analysis/MemoryLocation.cpp +++ b/llvm/lib/Analysis/MemoryLocation.cpp @@ -20,8 +20,10 @@ using namespace llvm; void LocationSize::print(raw_ostream &OS) const { OS << "LocationSize::"; - if (*this == unknown()) - OS << "unknown"; + if (*this == beforeOrAfterPointer()) + OS << "beforeOrAfterPointer"; + if (*this == afterPointer()) + OS << "afterPointer"; else if (*this == mapEmpty()) OS << "mapEmpty"; else if (*this == mapTombstone()) @@ -57,8 +59,8 @@ MemoryLocation MemoryLocation::get(const VAArgInst *VI) { AAMDNodes AATags; VI->getAAMetadata(AATags); - return MemoryLocation(VI->getPointerOperand(), LocationSize::unknown(), - AATags); + return MemoryLocation(VI->getPointerOperand(), + LocationSize::afterPointer(), AATags); } MemoryLocation MemoryLocation::get(const AtomicCmpXchgInst *CXI) { @@ -109,7 +111,7 @@ MemoryLocation MemoryLocation::getForSource(const AtomicMemTransferInst *MTI) { } MemoryLocation MemoryLocation::getForSource(const AnyMemTransferInst *MTI) { - auto Size = LocationSize::unknown(); + auto Size = LocationSize::afterPointer(); if (ConstantInt *C = dyn_cast(MTI->getLength())) Size = LocationSize::precise(C->getValue().getZExtValue()); @@ -130,7 +132,7 @@ MemoryLocation MemoryLocation::getForDest(const AtomicMemIntrinsic *MI) { } MemoryLocation MemoryLocation::getForDest(const AnyMemIntrinsic *MI) { - auto Size = LocationSize::unknown(); + auto Size = LocationSize::afterPointer(); if (ConstantInt *C = dyn_cast(MI->getLength())) Size = LocationSize::precise(C->getValue().getZExtValue()); @@ -165,7 +167,7 @@ MemoryLocation MemoryLocation::getForArgument(const CallBase *Call, if (ConstantInt *LenCI = dyn_cast(II->getArgOperand(2))) return MemoryLocation(Arg, LocationSize::precise(LenCI->getZExtValue()), AATags); - break; + return MemoryLocation::getAfter(Arg, AATags); case Intrinsic::lifetime_start: case Intrinsic::lifetime_end: @@ -237,7 +239,7 @@ MemoryLocation MemoryLocation::getForArgument(const CallBase *Call, dyn_cast(Call->getArgOperand(2))) return MemoryLocation(Arg, LocationSize::precise(LenCI->getZExtValue()), AATags); - break; + return MemoryLocation::getAfter(Arg, AATags); case LibFunc_bcmp: case LibFunc_memcmp: assert((ArgIdx == 0 || ArgIdx == 1) && @@ -246,14 +248,14 @@ MemoryLocation MemoryLocation::getForArgument(const CallBase *Call, dyn_cast(Call->getArgOperand(2))) return MemoryLocation(Arg, LocationSize::precise(LenCI->getZExtValue()), AATags); - break; + return MemoryLocation::getAfter(Arg, AATags); case LibFunc_memchr: assert((ArgIdx == 0) && "Invalid argument index for memchr"); if (const ConstantInt *LenCI = dyn_cast(Call->getArgOperand(2))) return MemoryLocation(Arg, LocationSize::precise(LenCI->getZExtValue()), AATags); - break; + return MemoryLocation::getAfter(Arg, AATags); case LibFunc_memccpy: assert((ArgIdx == 0 || ArgIdx == 1) && "Invalid argument index for memccpy"); @@ -262,13 +264,12 @@ MemoryLocation MemoryLocation::getForArgument(const CallBase *Call, dyn_cast(Call->getArgOperand(3))) return MemoryLocation( Arg, LocationSize::upperBound(LenCI->getZExtValue()), AATags); - break; + return MemoryLocation::getAfter(Arg, AATags); default: break; }; } // FIXME: Handle memset_pattern4 and memset_pattern8 also. - return MemoryLocation(Call->getArgOperand(ArgIdx), LocationSize::unknown(), - AATags); + return MemoryLocation::getBeforeOrAfter(Call->getArgOperand(ArgIdx), AATags); } diff --git a/llvm/lib/Analysis/MemorySSA.cpp b/llvm/lib/Analysis/MemorySSA.cpp index 0d0d990df4e7a..3973ef7f49aee 100644 --- a/llvm/lib/Analysis/MemorySSA.cpp +++ b/llvm/lib/Analysis/MemorySSA.cpp @@ -363,7 +363,7 @@ static bool lifetimeEndsAt(MemoryDef *MD, const MemoryLocation &Loc, if (IntrinsicInst *II = dyn_cast(Inst)) { switch (II->getIntrinsicID()) { case Intrinsic::lifetime_end: { - MemoryLocation ArgLoc(II->getArgOperand(1), LocationSize::unknown()); + MemoryLocation ArgLoc = MemoryLocation::getAfter(II->getArgOperand(1)); return AA.alias(ArgLoc, Loc) == MustAlias; } default: diff --git a/llvm/lib/Analysis/ObjCARCAliasAnalysis.cpp b/llvm/lib/Analysis/ObjCARCAliasAnalysis.cpp index 7c28b876597df..786d03f694b2e 100644 --- a/llvm/lib/Analysis/ObjCARCAliasAnalysis.cpp +++ b/llvm/lib/Analysis/ObjCARCAliasAnalysis.cpp @@ -57,9 +57,8 @@ AliasResult ObjCARCAAResult::alias(const MemoryLocation &LocA, const Value *UA = GetUnderlyingObjCPtr(SA); const Value *UB = GetUnderlyingObjCPtr(SB); if (UA != SA || UB != SB) { - Result = AAResultBase::alias( - MemoryLocation(UA, LocationSize::unknown()), - MemoryLocation(UB, LocationSize::unknown()), AAQI); + Result = AAResultBase::alias(MemoryLocation::getBeforeOrAfter(UA), + MemoryLocation::getBeforeOrAfter(UB), AAQI); // We can't use MustAlias or PartialAlias results here because // GetUnderlyingObjCPtr may return an offsetted pointer value. if (Result == NoAlias) @@ -88,7 +87,7 @@ bool ObjCARCAAResult::pointsToConstantMemory(const MemoryLocation &Loc, const Value *U = GetUnderlyingObjCPtr(S); if (U != S) return AAResultBase::pointsToConstantMemory( - MemoryLocation(U, LocationSize::unknown()), AAQI, OrLocal); + MemoryLocation::getBeforeOrAfter(U), AAQI, OrLocal); // If that failed, fail. We don't need to chain here, since that's covered // by the earlier precise query. diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp index 3176f8fc12f51..53fd668be05cd 100644 --- a/llvm/lib/Analysis/ScalarEvolution.cpp +++ b/llvm/lib/Analysis/ScalarEvolution.cpp @@ -3660,28 +3660,42 @@ const SCEV *ScalarEvolution::getUMinExpr(SmallVectorImpl &Ops) { return getMinMaxExpr(scUMinExpr, Ops); } +const SCEV * +ScalarEvolution::getSizeOfScalableVectorExpr(Type *IntTy, + ScalableVectorType *ScalableTy) { + Constant *NullPtr = Constant::getNullValue(ScalableTy->getPointerTo()); + Constant *One = ConstantInt::get(IntTy, 1); + Constant *GEP = ConstantExpr::getGetElementPtr(ScalableTy, NullPtr, One); + // Note that the expression we created is the final expression, we don't + // want to simplify it any further Also, if we call a normal getSCEV(), + // we'll end up in an endless recursion. So just create an SCEVUnknown. + return getUnknown(ConstantExpr::getPtrToInt(GEP, IntTy)); +} + const SCEV *ScalarEvolution::getSizeOfExpr(Type *IntTy, Type *AllocTy) { - if (isa(AllocTy)) { - Constant *NullPtr = Constant::getNullValue(AllocTy->getPointerTo()); - Constant *One = ConstantInt::get(IntTy, 1); - Constant *GEP = ConstantExpr::getGetElementPtr(AllocTy, NullPtr, One); - // Note that the expression we created is the final expression, we don't - // want to simplify it any further Also, if we call a normal getSCEV(), - // we'll end up in an endless recursion. So just create an SCEVUnknown. - return getUnknown(ConstantExpr::getPtrToInt(GEP, IntTy)); - } - // We can bypass creating a target-independent - // constant expression and then folding it back into a ConstantInt. - // This is just a compile-time optimization. + if (auto *ScalableAllocTy = dyn_cast(AllocTy)) + return getSizeOfScalableVectorExpr(IntTy, ScalableAllocTy); + // We can bypass creating a target-independent constant expression and then + // folding it back into a ConstantInt. This is just a compile-time + // optimization. return getConstant(IntTy, getDataLayout().getTypeAllocSize(AllocTy)); } +const SCEV *ScalarEvolution::getStoreSizeOfExpr(Type *IntTy, Type *StoreTy) { + if (auto *ScalableStoreTy = dyn_cast(StoreTy)) + return getSizeOfScalableVectorExpr(IntTy, ScalableStoreTy); + // We can bypass creating a target-independent constant expression and then + // folding it back into a ConstantInt. This is just a compile-time + // optimization. + return getConstant(IntTy, getDataLayout().getTypeStoreSize(StoreTy)); +} + const SCEV *ScalarEvolution::getOffsetOfExpr(Type *IntTy, StructType *STy, unsigned FieldNo) { - // We can bypass creating a target-independent - // constant expression and then folding it back into a ConstantInt. - // This is just a compile-time optimization. + // We can bypass creating a target-independent constant expression and then + // folding it back into a ConstantInt. This is just a compile-time + // optimization. return getConstant( IntTy, getDataLayout().getStructLayout(STy)->getElementOffset(FieldNo)); } @@ -7521,114 +7535,10 @@ ScalarEvolution::ExitLimit ScalarEvolution::computeExitLimitFromCondCached( ScalarEvolution::ExitLimit ScalarEvolution::computeExitLimitFromCondImpl( ExitLimitCacheTy &Cache, const Loop *L, Value *ExitCond, bool ExitIfTrue, bool ControlsExit, bool AllowPredicates) { - // Check if the controlling expression for this loop is an And or Or. - if (BinaryOperator *BO = dyn_cast(ExitCond)) { - if (BO->getOpcode() == Instruction::And) { - // Recurse on the operands of the and. - bool EitherMayExit = !ExitIfTrue; - ExitLimit EL0 = computeExitLimitFromCondCached( - Cache, L, BO->getOperand(0), ExitIfTrue, - ControlsExit && !EitherMayExit, AllowPredicates); - ExitLimit EL1 = computeExitLimitFromCondCached( - Cache, L, BO->getOperand(1), ExitIfTrue, - ControlsExit && !EitherMayExit, AllowPredicates); - // Be robust against unsimplified IR for the form "and i1 X, true" - if (ConstantInt *CI = dyn_cast(BO->getOperand(1))) - return CI->isOne() ? EL0 : EL1; - if (ConstantInt *CI = dyn_cast(BO->getOperand(0))) - return CI->isOne() ? EL1 : EL0; - const SCEV *BECount = getCouldNotCompute(); - const SCEV *MaxBECount = getCouldNotCompute(); - if (EitherMayExit) { - // Both conditions must be true for the loop to continue executing. - // Choose the less conservative count. - if (EL0.ExactNotTaken == getCouldNotCompute() || - EL1.ExactNotTaken == getCouldNotCompute()) - BECount = getCouldNotCompute(); - else - BECount = - getUMinFromMismatchedTypes(EL0.ExactNotTaken, EL1.ExactNotTaken); - if (EL0.MaxNotTaken == getCouldNotCompute()) - MaxBECount = EL1.MaxNotTaken; - else if (EL1.MaxNotTaken == getCouldNotCompute()) - MaxBECount = EL0.MaxNotTaken; - else - MaxBECount = - getUMinFromMismatchedTypes(EL0.MaxNotTaken, EL1.MaxNotTaken); - } else { - // Both conditions must be true at the same time for the loop to exit. - // For now, be conservative. - if (EL0.MaxNotTaken == EL1.MaxNotTaken) - MaxBECount = EL0.MaxNotTaken; - if (EL0.ExactNotTaken == EL1.ExactNotTaken) - BECount = EL0.ExactNotTaken; - } - - // There are cases (e.g. PR26207) where computeExitLimitFromCond is able - // to be more aggressive when computing BECount than when computing - // MaxBECount. In these cases it is possible for EL0.ExactNotTaken and - // EL1.ExactNotTaken to match, but for EL0.MaxNotTaken and EL1.MaxNotTaken - // to not. - if (isa(MaxBECount) && - !isa(BECount)) - MaxBECount = getConstant(getUnsignedRangeMax(BECount)); - - return ExitLimit(BECount, MaxBECount, false, - {&EL0.Predicates, &EL1.Predicates}); - } - if (BO->getOpcode() == Instruction::Or) { - // Recurse on the operands of the or. - bool EitherMayExit = ExitIfTrue; - ExitLimit EL0 = computeExitLimitFromCondCached( - Cache, L, BO->getOperand(0), ExitIfTrue, - ControlsExit && !EitherMayExit, AllowPredicates); - ExitLimit EL1 = computeExitLimitFromCondCached( - Cache, L, BO->getOperand(1), ExitIfTrue, - ControlsExit && !EitherMayExit, AllowPredicates); - // Be robust against unsimplified IR for the form "or i1 X, true" - if (ConstantInt *CI = dyn_cast(BO->getOperand(1))) - return CI->isZero() ? EL0 : EL1; - if (ConstantInt *CI = dyn_cast(BO->getOperand(0))) - return CI->isZero() ? EL1 : EL0; - const SCEV *BECount = getCouldNotCompute(); - const SCEV *MaxBECount = getCouldNotCompute(); - if (EitherMayExit) { - // Both conditions must be false for the loop to continue executing. - // Choose the less conservative count. - if (EL0.ExactNotTaken == getCouldNotCompute() || - EL1.ExactNotTaken == getCouldNotCompute()) - BECount = getCouldNotCompute(); - else - BECount = - getUMinFromMismatchedTypes(EL0.ExactNotTaken, EL1.ExactNotTaken); - if (EL0.MaxNotTaken == getCouldNotCompute()) - MaxBECount = EL1.MaxNotTaken; - else if (EL1.MaxNotTaken == getCouldNotCompute()) - MaxBECount = EL0.MaxNotTaken; - else - MaxBECount = - getUMinFromMismatchedTypes(EL0.MaxNotTaken, EL1.MaxNotTaken); - } else { - // Both conditions must be false at the same time for the loop to exit. - // For now, be conservative. - if (EL0.MaxNotTaken == EL1.MaxNotTaken) - MaxBECount = EL0.MaxNotTaken; - if (EL0.ExactNotTaken == EL1.ExactNotTaken) - BECount = EL0.ExactNotTaken; - } - // There are cases (e.g. PR26207) where computeExitLimitFromCond is able - // to be more aggressive when computing BECount than when computing - // MaxBECount. In these cases it is possible for EL0.ExactNotTaken and - // EL1.ExactNotTaken to match, but for EL0.MaxNotTaken and EL1.MaxNotTaken - // to not. - if (isa(MaxBECount) && - !isa(BECount)) - MaxBECount = getConstant(getUnsignedRangeMax(BECount)); - - return ExitLimit(BECount, MaxBECount, false, - {&EL0.Predicates, &EL1.Predicates}); - } - } + // Handle BinOp conditions (And, Or). + if (auto LimitFromBinOp = computeExitLimitFromCondFromBinOp( + Cache, L, ExitCond, ExitIfTrue, ControlsExit, AllowPredicates)) + return *LimitFromBinOp; // With an icmp, it may be feasible to compute an exact backedge-taken count. // Proceed to the next level to examine the icmp. @@ -7660,6 +7570,78 @@ ScalarEvolution::ExitLimit ScalarEvolution::computeExitLimitFromCondImpl( return computeExitCountExhaustively(L, ExitCond, ExitIfTrue); } +Optional +ScalarEvolution::computeExitLimitFromCondFromBinOp( + ExitLimitCacheTy &Cache, const Loop *L, Value *ExitCond, bool ExitIfTrue, + bool ControlsExit, bool AllowPredicates) { + // Check if the controlling expression for this loop is an And or Or. + if (auto *BO = dyn_cast(ExitCond)) { + if (BO->getOpcode() == Instruction::And) + return computeExitLimitFromCondFromBinOpHelper( + Cache, L, BO, !ExitIfTrue, ExitIfTrue, ControlsExit, AllowPredicates, + ConstantInt::get(BO->getType(), 1)); + if (BO->getOpcode() == Instruction::Or) + return computeExitLimitFromCondFromBinOpHelper( + Cache, L, BO, ExitIfTrue, ExitIfTrue, ControlsExit, AllowPredicates, + ConstantInt::get(BO->getType(), 0)); + } + return None; +} + +ScalarEvolution::ExitLimit +ScalarEvolution::computeExitLimitFromCondFromBinOpHelper( + ExitLimitCacheTy &Cache, const Loop *L, BinaryOperator *BO, + bool EitherMayExit, bool ExitIfTrue, bool ControlsExit, + bool AllowPredicates, const Constant *NeutralElement) { + ExitLimit EL0 = computeExitLimitFromCondCached( + Cache, L, BO->getOperand(0), ExitIfTrue, ControlsExit && !EitherMayExit, + AllowPredicates); + ExitLimit EL1 = computeExitLimitFromCondCached( + Cache, L, BO->getOperand(1), ExitIfTrue, ControlsExit && !EitherMayExit, + AllowPredicates); + // Be robust against unsimplified IR for the form "op i1 X, + // NeutralElement" + if (ConstantInt *CI = dyn_cast(BO->getOperand(1))) + return CI == NeutralElement ? EL0 : EL1; + if (ConstantInt *CI = dyn_cast(BO->getOperand(0))) + return CI == NeutralElement ? EL1 : EL0; + const SCEV *BECount = getCouldNotCompute(); + const SCEV *MaxBECount = getCouldNotCompute(); + if (EitherMayExit) { + // Both conditions must be same for the loop to continue executing. + // Choose the less conservative count. + if (EL0.ExactNotTaken == getCouldNotCompute() || + EL1.ExactNotTaken == getCouldNotCompute()) + BECount = getCouldNotCompute(); + else + BECount = + getUMinFromMismatchedTypes(EL0.ExactNotTaken, EL1.ExactNotTaken); + if (EL0.MaxNotTaken == getCouldNotCompute()) + MaxBECount = EL1.MaxNotTaken; + else if (EL1.MaxNotTaken == getCouldNotCompute()) + MaxBECount = EL0.MaxNotTaken; + else + MaxBECount = getUMinFromMismatchedTypes(EL0.MaxNotTaken, EL1.MaxNotTaken); + } else { + // Both conditions must be same at the same time for the loop to exit. + // For now, be conservative. + if (EL0.ExactNotTaken == EL1.ExactNotTaken) + BECount = EL0.ExactNotTaken; + } + + // There are cases (e.g. PR26207) where computeExitLimitFromCond is able + // to be more aggressive when computing BECount than when computing + // MaxBECount. In these cases it is possible for EL0.ExactNotTaken and + // EL1.ExactNotTaken to match, but for EL0.MaxNotTaken and EL1.MaxNotTaken + // to not. + if (isa(MaxBECount) && + !isa(BECount)) + MaxBECount = getConstant(getUnsignedRangeMax(BECount)); + + return ExitLimit(BECount, MaxBECount, false, + { &EL0.Predicates, &EL1.Predicates }); +} + ScalarEvolution::ExitLimit ScalarEvolution::computeExitLimitFromICmp(const Loop *L, ICmpInst *ExitCond, @@ -9536,19 +9518,15 @@ bool ScalarEvolution::isKnownOnEveryIteration(ICmpInst::Predicate Pred, Optional ScalarEvolution::getMonotonicPredicateType(const SCEVAddRecExpr *LHS, - ICmpInst::Predicate Pred, - Optional NumIter, - const Instruction *Context) { - assert((!NumIter || !isa(*NumIter)) && - "provided number of iterations must be computable!"); - auto Result = getMonotonicPredicateTypeImpl(LHS, Pred, NumIter, Context); + ICmpInst::Predicate Pred) { + auto Result = getMonotonicPredicateTypeImpl(LHS, Pred); #ifndef NDEBUG // Verify an invariant: inverting the predicate should turn a monotonically // increasing change to a monotonically decreasing one, and vice versa. if (Result) { - auto ResultSwapped = getMonotonicPredicateTypeImpl( - LHS, ICmpInst::getSwappedPredicate(Pred), NumIter, Context); + auto ResultSwapped = + getMonotonicPredicateTypeImpl(LHS, ICmpInst::getSwappedPredicate(Pred)); assert(ResultSwapped.hasValue() && "should be able to analyze both!"); assert(ResultSwapped.getValue() != Result.getValue() && @@ -9561,9 +9539,7 @@ ScalarEvolution::getMonotonicPredicateType(const SCEVAddRecExpr *LHS, Optional ScalarEvolution::getMonotonicPredicateTypeImpl(const SCEVAddRecExpr *LHS, - ICmpInst::Predicate Pred, - Optional NumIter, - const Instruction *Context) { + ICmpInst::Predicate Pred) { // A zero step value for LHS means the induction variable is essentially a // loop invariant value. We don't really depend on the predicate actually // flipping from false to true (for increasing predicates, and the other way @@ -9582,60 +9558,23 @@ ScalarEvolution::getMonotonicPredicateTypeImpl(const SCEVAddRecExpr *LHS, assert((IsGreater || ICmpInst::isLE(Pred) || ICmpInst::isLT(Pred)) && "Should be greater or less!"); - bool IsUnsigned = ICmpInst::isUnsigned(Pred); - assert((IsUnsigned || ICmpInst::isSigned(Pred)) && - "Should be either signed or unsigned!"); - // Check if we can prove no-wrap in the relevant range. - - const SCEV *Step = LHS->getStepRecurrence(*this); - bool IsStepNonNegative = isKnownNonNegative(Step); - bool IsStepNonPositive = isKnownNonPositive(Step); - // We need to know which direction the iteration is going. - if (!IsStepNonNegative && !IsStepNonPositive) - return None; - - auto ProvedNoWrap = [&]() { - // If the AddRec already has the flag, we are done. - if (IsUnsigned ? LHS->hasNoUnsignedWrap() : LHS->hasNoSignedWrap()) - return true; - - if (!NumIter) - return false; - // We could not prove no-wrap on all iteration space. Can we prove it for - // first iterations? In order to achieve it, check that: - // 1. The addrec does not self-wrap; - // 2. start <= end for non-negative step and start >= end for non-positive - // step. - bool HasNoSelfWrap = LHS->hasNoSelfWrap(); - if (!HasNoSelfWrap) - // If num iter has same type as the AddRec, and step is +/- 1, even max - // possible number of iterations is not enough to self-wrap. - if (NumIter.getValue()->getType() == LHS->getType()) - if (Step == getOne(LHS->getType()) || - Step == getMinusOne(LHS->getType())) - HasNoSelfWrap = true; - if (!HasNoSelfWrap) - return false; - const SCEV *Start = LHS->getStart(); - const SCEV *End = LHS->evaluateAtIteration(*NumIter, *this); - ICmpInst::Predicate NoOverflowPred = - IsStepNonNegative ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_SGE; - if (IsUnsigned) - NoOverflowPred = ICmpInst::getUnsignedPredicate(NoOverflowPred); - return isKnownPredicateAt(NoOverflowPred, Start, End, Context); - }; + // Check that AR does not wrap. + if (ICmpInst::isUnsigned(Pred)) { + if (!LHS->hasNoUnsignedWrap()) + return None; + return IsGreater ? MonotonicallyIncreasing : MonotonicallyDecreasing; + } else { + assert(ICmpInst::isSigned(Pred) && + "Relational predicate is either signed or unsigned!"); + if (!LHS->hasNoSignedWrap()) + return None; - // If nothing worked, bail. - if (!ProvedNoWrap()) - return None; + const SCEV *Step = LHS->getStepRecurrence(*this); - if (IsUnsigned) - return IsGreater ? MonotonicallyIncreasing : MonotonicallyDecreasing; - else { - if (IsStepNonNegative) + if (isKnownNonNegative(Step)) return IsGreater ? MonotonicallyIncreasing : MonotonicallyDecreasing; - if (IsStepNonPositive) + if (isKnownNonPositive(Step)) return !IsGreater ? MonotonicallyIncreasing : MonotonicallyDecreasing; return None; @@ -9696,6 +9635,7 @@ ScalarEvolution::getLoopInvariantExitCondDuringFirstIterations( // Try to prove the following set of facts: // - The predicate is monotonic in the iteration space. // - If the check does not fail on the 1st iteration: + // - No overflow will happen during first MaxIter iterations; // - It will not fail on the MaxIter'th iteration. // If the check does fail on the 1st iteration, we leave the loop and no // other checks matter. @@ -9713,17 +9653,43 @@ ScalarEvolution::getLoopInvariantExitCondDuringFirstIterations( if (!AR || AR->getLoop() != L) return None; - if (!getMonotonicPredicateType(AR, Pred, MaxIter, Context)) + // The predicate must be relational (i.e. <, <=, >=, >). + if (!ICmpInst::isRelational(Pred)) + return None; + + // TODO: Support steps other than +/- 1. + const SCEV *Step = AR->getStepRecurrence(*this); + auto *One = getOne(Step->getType()); + auto *MinusOne = getNegativeSCEV(One); + if (Step != One && Step != MinusOne) + return None; + + // Type mismatch here means that MaxIter is potentially larger than max + // unsigned value in start type, which mean we cannot prove no wrap for the + // indvar. + if (AR->getType() != MaxIter->getType()) return None; // Value of IV on suggested last iteration. const SCEV *Last = AR->evaluateAtIteration(MaxIter, *this); // Does it still meet the requirement? - if (!isKnownPredicateAt(Pred, Last, RHS, Context)) + if (!isLoopBackedgeGuardedByCond(L, Pred, Last, RHS)) + return None; + // Because step is +/- 1 and MaxIter has same type as Start (i.e. it does + // not exceed max unsigned value of this type), this effectively proves + // that there is no wrap during the iteration. To prove that there is no + // signed/unsigned wrap, we need to check that + // Start <= Last for step = 1 or Start >= Last for step = -1. + ICmpInst::Predicate NoOverflowPred = + CmpInst::isSigned(Pred) ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; + if (Step == MinusOne) + NoOverflowPred = CmpInst::getSwappedPredicate(NoOverflowPred); + const SCEV *Start = AR->getStart(); + if (!isKnownPredicateAt(NoOverflowPred, Start, Last, Context)) return None; // Everything is fine. - return ScalarEvolution::LoopInvariantPredicate(Pred, AR->getStart(), RHS); + return ScalarEvolution::LoopInvariantPredicate(Pred, Start, RHS); } bool ScalarEvolution::isKnownPredicateViaConstantRanges( diff --git a/llvm/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp b/llvm/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp index 79640256f6955..8f289feb3dcf4 100644 --- a/llvm/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp +++ b/llvm/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp @@ -82,10 +82,12 @@ AliasResult SCEVAAResult::alias(const MemoryLocation &LocA, Value *BO = GetBaseValue(BS); if ((AO && AO != LocA.Ptr) || (BO && BO != LocB.Ptr)) if (alias(MemoryLocation(AO ? AO : LocA.Ptr, - AO ? LocationSize::unknown() : LocA.Size, + AO ? LocationSize::beforeOrAfterPointer() + : LocA.Size, AO ? AAMDNodes() : LocA.AATags), MemoryLocation(BO ? BO : LocB.Ptr, - BO ? LocationSize::unknown() : LocB.Size, + BO ? LocationSize::beforeOrAfterPointer() + : LocB.Size, BO ? AAMDNodes() : LocB.AATags), AAQI) == NoAlias) return NoAlias; diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index b59a1a403e65d..2a79aa455fbc7 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -216,7 +216,11 @@ bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE, // Note that this block may not be the loop latch block, even if the loop // has a latch block. ExitBlock = BB; - ExitCount = EC; + TripCount = SE.getAddExpr(EC, SE.getOne(EC->getType())); + + if (!EC->getType()->isPointerTy() && EC->getType() != CountType) + TripCount = SE.getZeroExtendExpr(TripCount, CountType); + break; } diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index cdd07a63cf237..90f8dff874727 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -527,6 +527,7 @@ bool llvm::isAssumeLikeIntrinsic(const Instruction *I) { // FIXME: This list is repeated from NoTTI::getIntrinsicCost. case Intrinsic::assume: case Intrinsic::sideeffect: + case Intrinsic::pseudoprobe: case Intrinsic::dbg_declare: case Intrinsic::dbg_value: case Intrinsic::dbg_label: @@ -3609,12 +3610,13 @@ Value *llvm::isBytewiseValue(Value *V, const DataLayout &DL) { if (auto *CE = dyn_cast(C)) { if (CE->getOpcode() == Instruction::IntToPtr) { - auto PS = DL.getPointerSizeInBits( - cast(CE->getType())->getAddressSpace()); - return isBytewiseValue( - ConstantExpr::getIntegerCast(CE->getOperand(0), - Type::getIntNTy(Ctx, PS), false), - DL); + if (auto *PtrTy = dyn_cast(CE->getType())) { + unsigned BitWidth = DL.getPointerSizeInBits(PtrTy->getAddressSpace()); + return isBytewiseValue( + ConstantExpr::getIntegerCast(CE->getOperand(0), + Type::getIntNTy(Ctx, BitWidth), false), + DL); + } } } @@ -4722,7 +4724,7 @@ static bool canCreateUndefOrPoison(const Operator *Op, bool PoisonOnly) { ArrayRef Mask = isa(Op) ? cast(Op)->getShuffleMask() : cast(Op)->getShuffleMask(); - return any_of(Mask, [](int Elt) { return Elt == UndefMaskElem; }); + return is_contained(Mask, UndefMaskElem); } case Instruction::FNeg: case Instruction::PHI: @@ -4876,8 +4878,7 @@ static bool isGuaranteedNotToBeUndefOrPoison(const Value *V, else if (PoisonOnly && isa(Cond)) { // For poison, we can analyze further auto *Opr = cast(Cond); - if (propagatesPoison(Opr) && - any_of(Opr->operand_values(), [&](Value *Op) { return Op == V; })) + if (propagatesPoison(Opr) && is_contained(Opr->operand_values(), V)) return true; } } diff --git a/llvm/lib/Analysis/VectorUtils.cpp b/llvm/lib/Analysis/VectorUtils.cpp index e86508758be67..bd69055ac246d 100644 --- a/llvm/lib/Analysis/VectorUtils.cpp +++ b/llvm/lib/Analysis/VectorUtils.cpp @@ -125,7 +125,7 @@ Intrinsic::ID llvm::getVectorIntrinsicIDForCall(const CallInst *CI, if (isTriviallyVectorizable(ID) || ID == Intrinsic::lifetime_start || ID == Intrinsic::lifetime_end || ID == Intrinsic::assume || - ID == Intrinsic::sideeffect) + ID == Intrinsic::sideeffect || ID == Intrinsic::pseudoprobe) return ID; return Intrinsic::not_intrinsic; } diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp index b7e3a12cebf69..baabd553fbdfa 100644 --- a/llvm/lib/AsmParser/LLLexer.cpp +++ b/llvm/lib/AsmParser/LLLexer.cpp @@ -531,6 +531,7 @@ lltok::Kind LLLexer::LexIdentifier() { KEYWORD(undef); KEYWORD(null); KEYWORD(none); + KEYWORD(poison); KEYWORD(to); KEYWORD(caller); KEYWORD(within); diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp index 4f343dc9595d5..675151e6e1471 100644 --- a/llvm/lib/AsmParser/LLParser.cpp +++ b/llvm/lib/AsmParser/LLParser.cpp @@ -1699,14 +1699,14 @@ bool LLParser::parseOptionalParamAttrs(AttrBuilder &B) { } case lltok::kw_byval: { Type *Ty; - if (parseOptionalTypeAttr(Ty, lltok::kw_byval)) + if (parseRequiredTypeAttr(Ty, lltok::kw_byval)) return true; B.addByValAttr(Ty); continue; } case lltok::kw_sret: { Type *Ty; - if (parseOptionalTypeAttr(Ty, lltok::kw_sret)) + if (parseRequiredTypeAttr(Ty, lltok::kw_sret)) return true; B.addStructRetAttr(Ty); continue; @@ -2628,22 +2628,6 @@ bool LLParser::parseParameterList(SmallVectorImpl &ArgList, return false; } -/// parseByValWithOptionalType -/// ::= byval -/// ::= byval() -bool LLParser::parseOptionalTypeAttr(Type *&Result, lltok::Kind AttrName) { - Result = nullptr; - if (!EatIfPresent(AttrName)) - return true; - if (!EatIfPresent(lltok::lparen)) - return false; - if (parseType(Result)) - return true; - if (!EatIfPresent(lltok::rparen)) - return error(Lex.getLoc(), "expected ')'"); - return false; -} - /// parseRequiredTypeAttr /// ::= attrname() bool LLParser::parseRequiredTypeAttr(Type *&Result, lltok::Kind AttrName) { @@ -3289,6 +3273,7 @@ bool LLParser::parseValID(ValID &ID, PerFunctionState *PFS) { break; case lltok::kw_null: ID.Kind = ValID::t_Null; break; case lltok::kw_undef: ID.Kind = ValID::t_Undef; break; + case lltok::kw_poison: ID.Kind = ValID::t_Poison; break; case lltok::kw_zeroinitializer: ID.Kind = ValID::t_Zero; break; case lltok::kw_none: ID.Kind = ValID::t_None; break; @@ -5552,10 +5537,15 @@ bool LLParser::convertValIDToValue(Type *Ty, ValID &ID, Value *&V, return error(ID.Loc, "invalid type for none constant"); V = Constant::getNullValue(Ty); return false; + case ValID::t_Poison: + // FIXME: LabelTy should not be a first-class type. + if (!Ty->isFirstClassType() || Ty->isLabelTy()) + return error(ID.Loc, "invalid type for poison constant"); + V = PoisonValue::get(Ty); + return false; case ValID::t_Constant: if (ID.ConstantVal->getType() != Ty) return error(ID.Loc, "constant expression type mismatch"); - V = ID.ConstantVal; return false; case ValID::t_ConstantStruct: diff --git a/llvm/lib/AsmParser/LLParser.h b/llvm/lib/AsmParser/LLParser.h index f891f73443988..aa79823ce9868 100644 --- a/llvm/lib/AsmParser/LLParser.h +++ b/llvm/lib/AsmParser/LLParser.h @@ -46,7 +46,7 @@ namespace llvm { t_LocalID, t_GlobalID, // ID in UIntVal. t_LocalName, t_GlobalName, // Name in StrVal. t_APSInt, t_APFloat, // Value in APSIntVal/APFloatVal. - t_Null, t_Undef, t_Zero, t_None, // No value. + t_Null, t_Undef, t_Zero, t_None, t_Poison, // No value. t_EmptyArray, // No value: [] t_Constant, // Value in ConstantVal. t_InlineAsm, // Value in FTy/StrVal/StrVal2/UIntVal. @@ -328,7 +328,6 @@ namespace llvm { bool parseFnAttributeValuePairs(AttrBuilder &B, std::vector &FwdRefAttrGrps, bool inAttrGrp, LocTy &BuiltinLoc); - bool parseOptionalTypeAttr(Type *&Result, lltok::Kind AttrName); bool parseRequiredTypeAttr(Type *&Result, lltok::Kind AttrName); bool parsePreallocated(Type *&Result); bool parseByRef(Type *&Result); diff --git a/llvm/lib/AsmParser/LLToken.h b/llvm/lib/AsmParser/LLToken.h index c2b33355024de..7dd0fdab2cbf0 100644 --- a/llvm/lib/AsmParser/LLToken.h +++ b/llvm/lib/AsmParser/LLToken.h @@ -74,6 +74,7 @@ enum Kind { kw_localexec, kw_zeroinitializer, kw_undef, + kw_poison, kw_null, kw_none, kw_to, diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp index a39d7a2365aef..57c20d9502a9a 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -2410,6 +2410,9 @@ Error BitcodeReader::parseConstants() { case bitc::CST_CODE_UNDEF: // UNDEF V = UndefValue::get(CurTy); break; + case bitc::CST_CODE_POISON: // POISON + V = PoisonValue::get(CurTy); + break; case bitc::CST_CODE_SETTYPE: // SETTYPE: [typeid] if (Record.empty()) return error("Invalid record"); diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp index 2a921a7e29281..5c13738fad61c 100644 --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -2425,6 +2425,8 @@ void ModuleBitcodeWriter::writeConstants(unsigned FirstVal, unsigned LastVal, unsigned AbbrevToUse = 0; if (C->isNullValue()) { Code = bitc::CST_CODE_NULL; + } else if (isa(C)) { + Code = bitc::CST_CODE_POISON; } else if (isa(C)) { Code = bitc::CST_CODE_UNDEF; } else if (const ConstantInt *IV = dyn_cast(C)) { diff --git a/llvm/lib/CodeGen/Analysis.cpp b/llvm/lib/CodeGen/Analysis.cpp index 7da28ffec85cb..45099cdaf46fd 100644 --- a/llvm/lib/CodeGen/Analysis.cpp +++ b/llvm/lib/CodeGen/Analysis.cpp @@ -537,6 +537,9 @@ bool llvm::isInTailCallPosition(const CallBase &Call, const TargetMachine &TM) { // Debug info intrinsics do not get in the way of tail call optimization. if (isa(BBI)) continue; + // Pseudo probe intrinsics do not block tail call optimization either. + if (isa(BBI)) + continue; // A lifetime end or assume intrinsic should not stop tail call // optimization. if (const IntrinsicInst *II = dyn_cast(BBI)) diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 8287a45e6722a..4d7f17aa65bb8 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -307,6 +307,7 @@ bool AsmPrinter::doInitialization(Module &M) { std::unique_ptr STI(TM.getTarget().createMCSubtargetInfo( TM.getTargetTriple().str(), TM.getTargetCPU(), TM.getTargetFeatureString())); + assert(STI && "Unable to create subtarget info"); OutStreamer->AddComment("Start of file scope inline assembly"); OutStreamer->AddBlankLine(); emitInlineAsm(M.getModuleInlineAsm() + "\n", diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp index 57bf500ba8923..3a51134b494ea 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp @@ -147,6 +147,7 @@ void AsmPrinter::emitInlineAsm(StringRef Str, const MCSubtargetInfo &STI, // we only need MCInstrInfo for asm parsing. We create one unconditionally // because it's not subtarget dependent. std::unique_ptr MII(TM.getTarget().createMCInstrInfo()); + assert(MII && "Failed to create instruction info"); std::unique_ptr TAP(TM.getTarget().createMCAsmParser( STI, *Parser, *MII, MCOptions)); if (!TAP) diff --git a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp index 4d618cf3d6876..b15e750aaf85c 100644 --- a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp @@ -2150,10 +2150,13 @@ void CodeViewDebug::collectMemberInfo(ClassInfo &Info, if (!DDTy->getName().empty()) { Info.Members.push_back({DDTy, 0}); - // Collect static const data members. + // Collect static const data members with values. if ((DDTy->getFlags() & DINode::FlagStaticMember) == - DINode::FlagStaticMember) - StaticConstMembers.push_back(DDTy); + DINode::FlagStaticMember) { + if (DDTy->getConstant() && (isa(DDTy->getConstant()) || + isa(DDTy->getConstant()))) + StaticConstMembers.push_back(DDTy); + } return; } @@ -3134,7 +3137,7 @@ void CodeViewDebug::emitStaticConstMemberList() { dyn_cast_or_null(DTy->getConstant())) Value = APSInt(CFP->getValueAPF().bitcastToAPInt(), true); else - continue; + llvm_unreachable("cannot emit a constant without a value"); std::string QualifiedName = getFullyQualifiedName(Scope, DTy->getName()); diff --git a/llvm/lib/CodeGen/AsmPrinter/WinException.cpp b/llvm/lib/CodeGen/AsmPrinter/WinException.cpp index 26b6a322da383..3a9c9df797834 100644 --- a/llvm/lib/CodeGen/AsmPrinter/WinException.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/WinException.cpp @@ -258,11 +258,11 @@ void WinException::endFuncletImpl() { if (F.hasPersonalityFn()) Per = classifyEHPersonality(F.getPersonalityFn()->stripPointerCasts()); - // Emit an UNWIND_INFO struct describing the prologue. - Asm->OutStreamer->EmitWinEHHandlerData(); - if (Per == EHPersonality::MSVC_CXX && shouldEmitPersonality && !CurrentFuncletEntry->isCleanupFuncletEntry()) { + // Emit an UNWIND_INFO struct describing the prologue. + Asm->OutStreamer->EmitWinEHHandlerData(); + // If this is a C++ catch funclet (or the parent function), // emit a reference to the LSDA for the parent function. StringRef FuncLinkageName = GlobalValue::dropLLVMManglingEscape(F.getName()); @@ -271,9 +271,22 @@ void WinException::endFuncletImpl() { Asm->OutStreamer->emitValue(create32bitRef(FuncInfoXData), 4); } else if (Per == EHPersonality::MSVC_TableSEH && MF->hasEHFunclets() && !CurrentFuncletEntry->isEHFuncletEntry()) { + // Emit an UNWIND_INFO struct describing the prologue. + Asm->OutStreamer->EmitWinEHHandlerData(); + // If this is the parent function in Win64 SEH, emit the LSDA immediately // following .seh_handlerdata. emitCSpecificHandlerTable(MF); + } else if (shouldEmitPersonality || shouldEmitLSDA) { + // Emit an UNWIND_INFO struct describing the prologue. + Asm->OutStreamer->EmitWinEHHandlerData(); + // In these cases, no further info is written to the .xdata section + // right here, but is written by e.g. emitExceptionTable in endFunction() + // above. + } else { + // No need to emit the EH handler data right here if nothing needs + // writing to the .xdata section; it will be emitted for all + // functions that need it in the end anyway. } // Switch back to the funclet start .text section now that we are done diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index 06ed37cd6aea9..40e92b9e0a4ad 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -544,6 +544,7 @@ bool CodeGenPrepare::runOnFunction(Function &F) { LargeOffsetGEPID.clear(); } + NewGEPBases.clear(); SunkAddrs.clear(); if (!DisableBranchOpts) { @@ -559,7 +560,7 @@ bool CodeGenPrepare::runOnFunction(Function &F) { for (SmallVectorImpl::iterator II = Successors.begin(), IE = Successors.end(); II != IE; ++II) - if (pred_begin(*II) == pred_end(*II)) + if (pred_empty(*II)) WorkList.insert(*II); } @@ -573,7 +574,7 @@ bool CodeGenPrepare::runOnFunction(Function &F) { for (SmallVectorImpl::iterator II = Successors.begin(), IE = Successors.end(); II != IE; ++II) - if (pred_begin(*II) == pred_end(*II)) + if (pred_empty(*II)) WorkList.insert(*II); } @@ -2241,13 +2242,12 @@ bool CodeGenPrepare::dupRetToEnableTailCallOpts(BasicBlock *BB, bool &ModifiedDT // Skip over debug and the bitcast. do { ++BI; - } while (isa(BI) || &*BI == BCI || &*BI == EVI); + } while (isa(BI) || &*BI == BCI || &*BI == EVI || + isa(BI)); if (&*BI != RetI) return false; } else { - BasicBlock::iterator BI = BB->begin(); - while (isa(BI)) ++BI; - if (&*BI != RetI) + if (BB->getFirstNonPHIOrDbg(true) != RetI) return false; } @@ -2272,18 +2272,12 @@ bool CodeGenPrepare::dupRetToEnableTailCallOpts(BasicBlock *BB, bool &ModifiedDT for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE; ++PI) { if (!VisitedBBs.insert(*PI).second) continue; - - BasicBlock::InstListType &InstList = (*PI)->getInstList(); - BasicBlock::InstListType::reverse_iterator RI = InstList.rbegin(); - BasicBlock::InstListType::reverse_iterator RE = InstList.rend(); - do { ++RI; } while (RI != RE && isa(&*RI)); - if (RI == RE) - continue; - - CallInst *CI = dyn_cast(&*RI); - if (CI && CI->use_empty() && TLI->mayBeEmittedAsTailCall(CI) && - attributesPermitTailCall(F, CI, RetI, *TLI)) - TailCallBBs.push_back(*PI); + if (Instruction *I = (*PI)->rbegin()->getPrevNonDebugInstruction(true)) { + CallInst *CI = dyn_cast(I); + if (CI && CI->use_empty() && TLI->mayBeEmittedAsTailCall(CI) && + attributesPermitTailCall(F, CI, RetI, *TLI)) + TailCallBBs.push_back(*PI); + } } } @@ -2307,7 +2301,7 @@ bool CodeGenPrepare::dupRetToEnableTailCallOpts(BasicBlock *BB, bool &ModifiedDT } // If we eliminated all predecessors of the block, delete the block now. - if (Changed && !BB->hasAddressTaken() && pred_begin(BB) == pred_end(BB)) + if (Changed && !BB->hasAddressTaken() && pred_empty(BB)) BB->eraseFromParent(); return Changed; diff --git a/llvm/lib/CodeGen/CommandFlags.cpp b/llvm/lib/CodeGen/CommandFlags.cpp index bb15ff286d7c9..080592baa03a5 100644 --- a/llvm/lib/CodeGen/CommandFlags.cpp +++ b/llvm/lib/CodeGen/CommandFlags.cpp @@ -58,6 +58,7 @@ CGOPT(bool, EnableNoInfsFPMath) CGOPT(bool, EnableNoNaNsFPMath) CGOPT(bool, EnableNoSignedZerosFPMath) CGOPT(bool, EnableNoTrappingFPMath) +CGOPT(bool, EnableAIXExtendedAltivecABI) CGOPT(DenormalMode::DenormalModeKind, DenormalFPMath) CGOPT(DenormalMode::DenormalModeKind, DenormalFP32Math) CGOPT(bool, EnableHonorSignDependentRoundingFPMath) @@ -282,6 +283,11 @@ codegen::RegisterCodeGenFlags::RegisterCodeGenFlags() { cl::init(false)); CGBINDOPT(DontPlaceZerosInBSS); + static cl::opt EnableAIXExtendedAltivecABI( + "vec-extabi", cl::desc("Enable the AIX Extended Altivec ABI."), + cl::init(false)); + CGBINDOPT(EnableAIXExtendedAltivecABI); + static cl::opt EnableGuaranteedTailCallOpt( "tailcallopt", cl::desc( @@ -516,6 +522,7 @@ codegen::InitTargetOptionsFromCodeGenFlags(const Triple &TheTriple) { getEnableHonorSignDependentRoundingFPMath(); if (getFloatABIForCalls() != FloatABI::Default) Options.FloatABIType = getFloatABIForCalls(); + Options.EnableAIXExtendedAltivecABI = getEnableAIXExtendedAltivecABI(); Options.NoZerosInBSS = getDontPlaceZerosInBSS(); Options.GuaranteedTailCallOpt = getEnableGuaranteedTailCallOpt(); Options.StackAlignmentOverride = getOverrideStackAlignment(); diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp index d1529b08f7086..93467e9d09b87 100644 --- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp +++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp @@ -10,6 +10,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/ADT/PostOrderIterator.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -48,6 +49,8 @@ namespace { private: bool isDead(const MachineInstr *MI) const; + + bool eliminateDeadMI(MachineFunction &MF); }; } char DeadMachineInstructionElim::ID = 0; @@ -107,7 +110,13 @@ bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const { bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; + bool AnyChanges = eliminateDeadMI(MF); + while (AnyChanges && eliminateDeadMI(MF)) + ; + return AnyChanges; +} +bool DeadMachineInstructionElim::eliminateDeadMI(MachineFunction &MF) { bool AnyChanges = false; MRI = &MF.getRegInfo(); TRI = MF.getSubtarget().getRegisterInfo(); @@ -116,22 +125,24 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { // Loop over all instructions in all blocks, from bottom to top, so that it's // more likely that chains of dependent but ultimately dead instructions will // be cleaned up. - for (MachineBasicBlock &MBB : make_range(MF.rbegin(), MF.rend())) { + for (MachineBasicBlock *MBB : post_order(&MF)) { // Start out assuming that reserved registers are live out of this block. LivePhysRegs = MRI->getReservedRegs(); // Add live-ins from successors to LivePhysRegs. Normally, physregs are not // live across blocks, but some targets (x86) can have flags live out of a // block. - for (MachineBasicBlock::succ_iterator S = MBB.succ_begin(), - E = MBB.succ_end(); S != E; S++) + for (MachineBasicBlock::succ_iterator S = MBB->succ_begin(), + E = MBB->succ_end(); + S != E; S++) for (const auto &LI : (*S)->liveins()) LivePhysRegs.set(LI.PhysReg); // Now scan the instructions and delete dead ones, tracking physreg // liveness as we go. - for (MachineBasicBlock::reverse_iterator MII = MBB.rbegin(), - MIE = MBB.rend(); MII != MIE; ) { + for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(), + MIE = MBB->rend(); + MII != MIE;) { MachineInstr *MI = &*MII++; // If the instruction is dead, delete it! diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp index 6d5306c1dc0c7..03fe5f155291a 100644 --- a/llvm/lib/CodeGen/DetectDeadLanes.cpp +++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp @@ -25,11 +25,7 @@ // //===----------------------------------------------------------------------===// -#include -#include - #include "llvm/ADT/BitVector.h" -#include "llvm/ADT/SetVector.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" @@ -40,6 +36,7 @@ #include "llvm/PassRegistry.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" +#include using namespace llvm; diff --git a/llvm/lib/CodeGen/HardwareLoops.cpp b/llvm/lib/CodeGen/HardwareLoops.cpp index 76c9c1470868c..810b10c9c82a2 100644 --- a/llvm/lib/CodeGen/HardwareLoops.cpp +++ b/llvm/lib/CodeGen/HardwareLoops.cpp @@ -187,7 +187,7 @@ namespace { const DataLayout &DL, OptimizationRemarkEmitter *ORE) : SE(SE), DL(DL), ORE(ORE), L(Info.L), M(L->getHeader()->getModule()), - ExitCount(Info.ExitCount), + TripCount(Info.TripCount), CountType(Info.CountType), ExitBranch(Info.ExitBranch), LoopDecrement(Info.LoopDecrement), @@ -202,7 +202,7 @@ namespace { OptimizationRemarkEmitter *ORE = nullptr; Loop *L = nullptr; Module *M = nullptr; - const SCEV *ExitCount = nullptr; + const SCEV *TripCount = nullptr; Type *CountType = nullptr; BranchInst *ExitBranch = nullptr; Value *LoopDecrement = nullptr; @@ -298,7 +298,7 @@ bool HardwareLoops::TryConvertLoop(HardwareLoopInfo &HWLoopInfo) { } assert( - (HWLoopInfo.ExitBlock && HWLoopInfo.ExitBranch && HWLoopInfo.ExitCount) && + (HWLoopInfo.ExitBlock && HWLoopInfo.ExitBranch && HWLoopInfo.TripCount) && "Hardware Loop must have set exit info."); BasicBlock *Preheader = L->getLoopPreheader(); @@ -383,18 +383,13 @@ Value *HardwareLoop::InitLoopCount() { // loop counter and tests that is not zero? SCEVExpander SCEVE(SE, DL, "loopcnt"); - if (!ExitCount->getType()->isPointerTy() && - ExitCount->getType() != CountType) - ExitCount = SE.getZeroExtendExpr(ExitCount, CountType); - - ExitCount = SE.getAddExpr(ExitCount, SE.getOne(CountType)); // If we're trying to use the 'test and set' form of the intrinsic, we need // to replace a conditional branch that is controlling entry to the loop. It // is likely (guaranteed?) that the preheader has an unconditional branch to // the loop header, so also check if it has a single predecessor. - if (SE.isLoopEntryGuardedByCond(L, ICmpInst::ICMP_NE, ExitCount, - SE.getZero(ExitCount->getType()))) { + if (SE.isLoopEntryGuardedByCond(L, ICmpInst::ICMP_NE, TripCount, + SE.getZero(TripCount->getType()))) { LLVM_DEBUG(dbgs() << " - Attempting to use test.set counter.\n"); UseLoopGuard |= ForceGuardLoopEntry; } else @@ -406,19 +401,19 @@ Value *HardwareLoop::InitLoopCount() { BasicBlock *Predecessor = BB->getSinglePredecessor(); // If it's not safe to create a while loop then don't force it and create a // do-while loop instead - if (!isSafeToExpandAt(ExitCount, Predecessor->getTerminator(), SE)) + if (!isSafeToExpandAt(TripCount, Predecessor->getTerminator(), SE)) UseLoopGuard = false; else BB = Predecessor; } - if (!isSafeToExpandAt(ExitCount, BB->getTerminator(), SE)) { - LLVM_DEBUG(dbgs() << "- Bailing, unsafe to expand ExitCount " - << *ExitCount << "\n"); + if (!isSafeToExpandAt(TripCount, BB->getTerminator(), SE)) { + LLVM_DEBUG(dbgs() << "- Bailing, unsafe to expand TripCount " + << *TripCount << "\n"); return nullptr; } - Value *Count = SCEVE.expandCodeFor(ExitCount, CountType, + Value *Count = SCEVE.expandCodeFor(TripCount, CountType, BB->getTerminator()); // FIXME: We've expanded Count where we hope to insert the counter setting diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp index d0a4511e90e72..5cdaa9b74e802 100644 --- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp +++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp @@ -353,11 +353,9 @@ ImplicitNullChecks::areMemoryOpsAliased(const MachineInstr &MI, return AR_MayAlias; continue; } - llvm::AliasResult AAResult = - AA->alias(MemoryLocation(MMO1->getValue(), LocationSize::unknown(), - MMO1->getAAInfo()), - MemoryLocation(MMO2->getValue(), LocationSize::unknown(), - MMO2->getAAInfo())); + llvm::AliasResult AAResult = AA->alias( + MemoryLocation::getAfter(MMO1->getValue(), MMO1->getAAInfo()), + MemoryLocation::getAfter(MMO2->getValue(), MMO2->getAAInfo())); if (AAResult != NoAlias) return AR_MayAlias; } diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp index 6f3deff8cb3bc..650ad83e2e397 100644 --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -40,13 +40,16 @@ static cl::opt EnableTrapUnreachable("trap-unreachable", void LLVMTargetMachine::initAsmInfo() { MRI.reset(TheTarget.createMCRegInfo(getTargetTriple().str())); + assert(MRI && "Unable to create reg info"); MII.reset(TheTarget.createMCInstrInfo()); + assert(MII && "Unable to create instruction info"); // FIXME: Having an MCSubtargetInfo on the target machine is a hack due // to some backends having subtarget feature dependent module level // code generation. This is similar to the hack in the AsmPrinter for // module level assembly etc. STI.reset(TheTarget.createMCSubtargetInfo( getTargetTriple().str(), getTargetCPU(), getTargetFeatureString())); + assert(STI && "Unable to create subtarget info"); MCAsmInfo *TmpAsmInfo = TheTarget.createMCAsmInfo( *MRI, getTargetTriple().str(), Options.MCOptions); diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp index f4238bd381261..2325341070a38 100644 --- a/llvm/lib/CodeGen/LiveDebugVariables.cpp +++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp @@ -1022,10 +1022,10 @@ bool LDVImpl::runOnMachineFunction(MachineFunction &mf) { return Changed; } -static void removeDebugValues(MachineFunction &mf) { +static void removeDebugInstrs(MachineFunction &mf) { for (MachineBasicBlock &MBB : mf) { for (auto MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ) { - if (!MBBI->isDebugValue()) { + if (!MBBI->isDebugInstr()) { ++MBBI; continue; } @@ -1038,7 +1038,7 @@ bool LiveDebugVariables::runOnMachineFunction(MachineFunction &mf) { if (!EnableLDV) return false; if (!mf.getFunction().getSubprogram()) { - removeDebugValues(mf); + removeDebugInstrs(mf); return false; } if (!pImpl) diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp index 8a86696380311..461a737416484 100644 --- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp +++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp @@ -449,10 +449,6 @@ class MachineBlockPlacement : public MachineFunctionPass { const MachineBasicBlock *BB, const BlockChain &Chain, const BlockFilterSet *BlockFilter, SmallVector &Successors); - bool shouldPredBlockBeOutlined( - const MachineBasicBlock *BB, const MachineBasicBlock *Succ, - const BlockChain &Chain, const BlockFilterSet *BlockFilter, - BranchProbability SuccProb, BranchProbability HotProb); bool isBestSuccessor(MachineBasicBlock *BB, MachineBasicBlock *Pred, BlockFilterSet *BlockFilter); void findDuplicateCandidates(SmallVectorImpl &Candidates, diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp index 19e36669a2541..be18581d866df 100644 --- a/llvm/lib/CodeGen/MachineLICM.cpp +++ b/llvm/lib/CodeGen/MachineLICM.cpp @@ -246,8 +246,6 @@ namespace { void HoistOutOfLoop(MachineDomTreeNode *HeaderN); - void HoistRegion(MachineDomTreeNode *N, bool IsHeader); - void SinkIntoLoop(); void InitRegPressure(MachineBasicBlock *BB); diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index e11f8280407f5..a83c0154bd9f1 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -803,10 +803,8 @@ void SwingSchedulerDAG::addLoopCarriedDependences(AliasAnalysis *AA) { continue; } AliasResult AAResult = AA->alias( - MemoryLocation(MMO1->getValue(), LocationSize::unknown(), - MMO1->getAAInfo()), - MemoryLocation(MMO2->getValue(), LocationSize::unknown(), - MMO2->getAAInfo())); + MemoryLocation::getAfter(MMO1->getValue(), MMO1->getAAInfo()), + MemoryLocation::getAfter(MMO2->getValue(), MMO2->getAAInfo())); if (AAResult != NoAlias) { SDep Dep(Load, SDep::Barrier); diff --git a/llvm/lib/CodeGen/ParallelCG.cpp b/llvm/lib/CodeGen/ParallelCG.cpp index c19ed1f8f71da..849b667254bd0 100644 --- a/llvm/lib/CodeGen/ParallelCG.cpp +++ b/llvm/lib/CodeGen/ParallelCG.cpp @@ -28,6 +28,8 @@ static void codegen(Module *M, llvm::raw_pwrite_stream &OS, function_ref()> TMFactory, CodeGenFileType FileType) { std::unique_ptr TM = TMFactory(); + assert(TM && "Failed to create target machine!"); + legacy::PassManager CodeGenPasses; if (TM->addPassesToEmitFile(CodeGenPasses, OS, nullptr, FileType)) report_fatal_error("Failed to setup codegen"); diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index d18d37eea41aa..1b5debfe602e4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3209,6 +3209,19 @@ SDValue DAGCombiner::visitSUB(SDNode *N) { // 0 - X --> X if X is 0 or the minimum signed value. return N1; } + + // Convert 0 - abs(x) -> Y = sra (X, size(X)-1); sub (Y, xor (X, Y)). + if (N1->getOpcode() == ISD::ABS && + !TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { + SDValue X = N1->getOperand(0); + SDValue Shift = + DAG.getNode(ISD::SRA, DL, VT, X, + DAG.getConstant(BitWidth - 1, DL, getShiftAmountTy(VT))); + SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, X, Shift); + AddToWorklist(Shift.getNode()); + AddToWorklist(Xor.getNode()); + return DAG.getNode(ISD::SUB, DL, VT, Shift, Xor); + } } // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) @@ -22039,30 +22052,36 @@ SDValue DAGCombiner::buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, : buildSqrtNRTwoConst(Op, Est, Iterations, Flags, Reciprocal); if (!Reciprocal) { - // The estimate is now completely wrong if the input was exactly 0.0 or - // possibly a denormal. Force the answer to 0.0 for those cases. SDLoc DL(Op); EVT CCVT = getSetCCResultType(VT); - ISD::NodeType SelOpcode = VT.isVector() ? ISD::VSELECT : ISD::SELECT; + SDValue FPZero = DAG.getConstantFP(0.0, DL, VT); DenormalMode DenormMode = DAG.getDenormalMode(VT); - if (DenormMode.Input == DenormalMode::IEEE) { - // This is specifically a check for the handling of denormal inputs, - // not the result. - - // fabs(X) < SmallestNormal ? 0.0 : Est - const fltSemantics &FltSem = DAG.EVTToAPFloatSemantics(VT); - APFloat SmallestNorm = APFloat::getSmallestNormalized(FltSem); - SDValue NormC = DAG.getConstantFP(SmallestNorm, DL, VT); - SDValue FPZero = DAG.getConstantFP(0.0, DL, VT); - SDValue Fabs = DAG.getNode(ISD::FABS, DL, VT, Op); - SDValue IsDenorm = DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT); - Est = DAG.getNode(SelOpcode, DL, VT, IsDenorm, FPZero, Est); - } else { - // X == 0.0 ? 0.0 : Est - SDValue FPZero = DAG.getConstantFP(0.0, DL, VT); - SDValue IsZero = DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ); - Est = DAG.getNode(SelOpcode, DL, VT, IsZero, FPZero, Est); + // Try the target specific test first. + SDValue Test = TLI.getSqrtInputTest(Op, DAG, DenormMode); + if (!Test) { + // If no test provided by target, testing it with denormal inputs to + // avoid wrong estimate. + if (DenormMode.Input == DenormalMode::IEEE) { + // This is specifically a check for the handling of denormal inputs, + // not the result. + + // Test = fabs(X) < SmallestNormal + const fltSemantics &FltSem = DAG.EVTToAPFloatSemantics(VT); + APFloat SmallestNorm = APFloat::getSmallestNormalized(FltSem); + SDValue NormC = DAG.getConstantFP(SmallestNorm, DL, VT); + SDValue Fabs = DAG.getNode(ISD::FABS, DL, VT, Op); + Test = DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT); + } else + // Test = X == 0.0 + Test = DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ); } + + // The estimate is now completely wrong if the input was exactly 0.0 or + // possibly a denormal. Force the answer to 0.0 or value provided by + // target for those cases. + Est = DAG.getNode( + Test.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT, + Test, TLI.getSqrtResultForDenormInput(Op, DAG), Est); } } return Est; diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index 6cf0be5c65330..2d3ec0a0367f3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -139,7 +139,6 @@ void FastISel::startNewBlock() { LastLocalValue = EmitStartPt; } -/// Flush the local CSE map and sink anything we can. void FastISel::finishBasicBlock() { flushLocalValueMap(); } bool FastISel::lowerArguments() { @@ -164,48 +163,56 @@ bool FastISel::lowerArguments() { /// Return the defined register if this instruction defines exactly one /// virtual register and uses no other virtual registers. Otherwise return 0. -static Register findSinkableLocalRegDef(MachineInstr &MI) { +static Register findLocalRegDef(MachineInstr &MI) { Register RegDef; for (const MachineOperand &MO : MI.operands()) { if (!MO.isReg()) continue; if (MO.isDef()) { if (RegDef) - return 0; + return Register(); RegDef = MO.getReg(); } else if (MO.getReg().isVirtual()) { - // This is another use of a vreg. Don't try to sink it. + // This is another use of a vreg. Don't delete it. return Register(); } } return RegDef; } +static bool isRegUsedByPhiNodes(Register DefReg, + FunctionLoweringInfo &FuncInfo) { + for (auto &P : FuncInfo.PHINodesToUpdate) + if (P.second == DefReg) + return true; + return false; +} + void FastISel::flushLocalValueMap() { - // Try to sink local values down to their first use so that we can give them a - // better debug location. This has the side effect of shrinking local value - // live ranges, which helps out fast regalloc. - if (SinkLocalValues && LastLocalValue != EmitStartPt) { - // Sink local value materialization instructions between EmitStartPt and - // LastLocalValue. Visit them bottom-up, starting from LastLocalValue, to - // avoid inserting into the range that we're iterating over. + // If FastISel bails out, it could leave local value instructions behind + // that aren't used for anything. Detect and erase those. + if (LastLocalValue != EmitStartPt) { MachineBasicBlock::reverse_iterator RE = EmitStartPt ? MachineBasicBlock::reverse_iterator(EmitStartPt) : FuncInfo.MBB->rend(); MachineBasicBlock::reverse_iterator RI(LastLocalValue); - - InstOrderMap OrderMap; for (; RI != RE;) { MachineInstr &LocalMI = *RI; + // Increment before erasing what it points to. ++RI; - bool Store = true; - if (!LocalMI.isSafeToMove(nullptr, Store)) + Register DefReg = findLocalRegDef(LocalMI); + if (!DefReg) continue; - Register DefReg = findSinkableLocalRegDef(LocalMI); - if (DefReg == 0) + if (FuncInfo.RegsWithFixups.count(DefReg)) continue; - - sinkLocalValueMaterialization(LocalMI, DefReg, OrderMap); + bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo); + if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) { + if (EmitStartPt == &LocalMI) + EmitStartPt = EmitStartPt->getPrevNode(); + LLVM_DEBUG(dbgs() << "removing dead local value materialization" + << LocalMI); + LocalMI.eraseFromParent(); + } } } @@ -216,131 +223,6 @@ void FastISel::flushLocalValueMap() { LastFlushPoint = FuncInfo.InsertPt; } -static bool isRegUsedByPhiNodes(Register DefReg, - FunctionLoweringInfo &FuncInfo) { - for (auto &P : FuncInfo.PHINodesToUpdate) - if (P.second == DefReg) - return true; - return false; -} - -static bool isTerminatingEHLabel(MachineBasicBlock *MBB, MachineInstr &MI) { - // Ignore non-EH labels. - if (!MI.isEHLabel()) - return false; - - // Any EH label outside a landing pad must be for an invoke. Consider it a - // terminator. - if (!MBB->isEHPad()) - return true; - - // If this is a landingpad, the first non-phi instruction will be an EH_LABEL. - // Don't consider that label to be a terminator. - return MI.getIterator() != MBB->getFirstNonPHI(); -} - -/// Build a map of instruction orders. Return the first terminator and its -/// order. Consider EH_LABEL instructions to be terminators as well, since local -/// values for phis after invokes must be materialized before the call. -void FastISel::InstOrderMap::initialize( - MachineBasicBlock *MBB, MachineBasicBlock::iterator LastFlushPoint) { - unsigned Order = 0; - for (MachineInstr &I : *MBB) { - if (!FirstTerminator && - (I.isTerminator() || isTerminatingEHLabel(MBB, I))) { - FirstTerminator = &I; - FirstTerminatorOrder = Order; - } - Orders[&I] = Order++; - - // We don't need to order instructions past the last flush point. - if (I.getIterator() == LastFlushPoint) - break; - } -} - -void FastISel::sinkLocalValueMaterialization(MachineInstr &LocalMI, - Register DefReg, - InstOrderMap &OrderMap) { - // If this register is used by a register fixup, MRI will not contain all - // the uses until after register fixups, so don't attempt to sink or DCE - // this instruction. Register fixups typically come from no-op cast - // instructions, which replace the cast instruction vreg with the local - // value vreg. - if (FuncInfo.RegsWithFixups.count(DefReg)) - return; - - // We can DCE this instruction if there are no uses and it wasn't a - // materialized for a successor PHI node. - bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo); - if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) { - if (EmitStartPt == &LocalMI) - EmitStartPt = EmitStartPt->getPrevNode(); - LLVM_DEBUG(dbgs() << "removing dead local value materialization " - << LocalMI); - OrderMap.Orders.erase(&LocalMI); - LocalMI.eraseFromParent(); - return; - } - - // Number the instructions if we haven't yet so we can efficiently find the - // earliest use. - if (OrderMap.Orders.empty()) - OrderMap.initialize(FuncInfo.MBB, LastFlushPoint); - - // Find the first user in the BB. - MachineInstr *FirstUser = nullptr; - unsigned FirstOrder = std::numeric_limits::max(); - for (MachineInstr &UseInst : MRI.use_nodbg_instructions(DefReg)) { - auto I = OrderMap.Orders.find(&UseInst); - assert(I != OrderMap.Orders.end() && - "local value used by instruction outside local region"); - unsigned UseOrder = I->second; - if (UseOrder < FirstOrder) { - FirstOrder = UseOrder; - FirstUser = &UseInst; - } - } - - // The insertion point will be the first terminator or the first user, - // whichever came first. If there was no terminator, this must be a - // fallthrough block and the insertion point is the end of the block. - MachineBasicBlock::instr_iterator SinkPos; - if (UsedByPHI && OrderMap.FirstTerminatorOrder < FirstOrder) { - FirstOrder = OrderMap.FirstTerminatorOrder; - SinkPos = OrderMap.FirstTerminator->getIterator(); - } else if (FirstUser) { - SinkPos = FirstUser->getIterator(); - } else { - assert(UsedByPHI && "must be users if not used by a phi"); - SinkPos = FuncInfo.MBB->instr_end(); - } - - // Collect all DBG_VALUEs before the new insertion position so that we can - // sink them. - SmallVector DbgValues; - for (MachineInstr &DbgVal : MRI.use_instructions(DefReg)) { - if (!DbgVal.isDebugValue()) - continue; - unsigned UseOrder = OrderMap.Orders[&DbgVal]; - if (UseOrder < FirstOrder) - DbgValues.push_back(&DbgVal); - } - - // Sink LocalMI before SinkPos and assign it the same DebugLoc. - LLVM_DEBUG(dbgs() << "sinking local value to first use " << LocalMI); - FuncInfo.MBB->remove(&LocalMI); - FuncInfo.MBB->insert(SinkPos, &LocalMI); - if (SinkPos != FuncInfo.MBB->end()) - LocalMI.setDebugLoc(SinkPos->getDebugLoc()); - - // Sink any debug values that we've collected. - for (MachineInstr *DI : DbgValues) { - FuncInfo.MBB->remove(DI); - FuncInfo.MBB->insert(SinkPos, DI); - } -} - bool FastISel::hasTrivialKill(const Value *V) { // Don't consider constants or arguments to have trivial kills. const Instruction *I = dyn_cast(V); @@ -578,12 +460,9 @@ void FastISel::removeDeadCode(MachineBasicBlock::iterator I, } FastISel::SavePoint FastISel::enterLocalValueArea() { - MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt; - DebugLoc OldDL = DbgLoc; + SavePoint OldInsertPt = FuncInfo.InsertPt; recomputeInsertPt(); - DbgLoc = DebugLoc(); - SavePoint SP = {OldInsertPt, OldDL}; - return SP; + return OldInsertPt; } void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) { @@ -591,8 +470,7 @@ void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) { LastLocalValue = &*std::prev(FuncInfo.InsertPt); // Restore the previous insert position. - FuncInfo.InsertPt = OldInsertPt.InsertPt; - DbgLoc = OldInsertPt.DL; + FuncInfo.InsertPt = OldInsertPt; } bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) { @@ -1657,6 +1535,11 @@ void FastISel::removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue) } bool FastISel::selectInstruction(const Instruction *I) { + // Flush the local value map before starting each instruction. + // This improves locality and debugging, and can reduce spills. + // Reuse of values across IR instructions is relatively uncommon. + flushLocalValueMap(); + MachineInstr *SavedLastLocalValue = getLastLocalValue(); // Just before the terminator instruction, insert instructions to // feed PHI nodes in successor blocks. diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 95272d56f6970..2b208cee17163 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -1124,6 +1124,20 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, break; } + case ISD::PSEUDO_PROBE: { + unsigned TarOp = TargetOpcode::PSEUDO_PROBE; + auto Guid = cast(Node)->getGuid(); + auto Index = cast(Node)->getIndex(); + auto Attr = cast(Node)->getAttributes(); + + BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp)) + .addImm(Guid) + .addImm(Index) + .addImm(0) // 0 for block probes + .addImm(Attr); + break; + } + case ISD::INLINEASM: case ISD::INLINEASM_BR: { unsigned NumOps = Node->getNumOperands(); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 31a992810ebcc..5386754c3176e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -4417,7 +4417,9 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) { OVT = Node->getOperand(0).getSimpleValueType(); } if (Node->getOpcode() == ISD::STRICT_UINT_TO_FP || - Node->getOpcode() == ISD::STRICT_SINT_TO_FP) + Node->getOpcode() == ISD::STRICT_SINT_TO_FP || + Node->getOpcode() == ISD::STRICT_FSETCC || + Node->getOpcode() == ISD::STRICT_FSETCCS) OVT = Node->getOperand(1).getSimpleValueType(); if (Node->getOpcode() == ISD::BR_CC) OVT = Node->getOperand(2).getSimpleValueType(); @@ -4611,13 +4613,29 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) { Results.push_back(Tmp1); break; } - case ISD::SETCC: { + case ISD::SETCC: + case ISD::STRICT_FSETCC: + case ISD::STRICT_FSETCCS: { unsigned ExtOp = ISD::FP_EXTEND; if (NVT.isInteger()) { - ISD::CondCode CCCode = - cast(Node->getOperand(2))->get(); + ISD::CondCode CCCode = cast(Node->getOperand(2))->get(); ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; } + if (Node->isStrictFPOpcode()) { + SDValue InChain = Node->getOperand(0); + std::tie(Tmp1, std::ignore) = + DAG.getStrictFPExtendOrRound(Node->getOperand(1), InChain, dl, NVT); + std::tie(Tmp2, std::ignore) = + DAG.getStrictFPExtendOrRound(Node->getOperand(2), InChain, dl, NVT); + SmallVector TmpChains = {Tmp1.getValue(1), Tmp2.getValue(1)}; + SDValue OutChain = DAG.getTokenFactor(dl, TmpChains); + SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other); + Results.push_back(DAG.getNode(Node->getOpcode(), dl, VTs, + {OutChain, Tmp1, Tmp2, Node->getOperand(3)}, + Node->getFlags())); + Results.push_back(Results.back().getValue(1)); + break; + } Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), Tmp1, diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h index 6ed480f5c17c8..fdc829b61b650 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -776,6 +776,8 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer { SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo); SDValue ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo); SDValue ScalarizeVecOp_STRICT_FP_ROUND(SDNode *N, unsigned OpNo); + SDValue ScalarizeVecOp_FP_EXTEND(SDNode *N); + SDValue ScalarizeVecOp_STRICT_FP_EXTEND(SDNode *N); SDValue ScalarizeVecOp_VECREDUCE(SDNode *N); SDValue ScalarizeVecOp_VECREDUCE_SEQ(SDNode *N); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index c356895c61a7d..db44ea2553ced 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -143,7 +143,6 @@ class VectorLegalizer { void ExpandSADDSUBO(SDNode *Node, SmallVectorImpl &Results); void ExpandMULO(SDNode *Node, SmallVectorImpl &Results); void ExpandFixedPointDiv(SDNode *Node, SmallVectorImpl &Results); - SDValue ExpandStrictFPOp(SDNode *Node); void ExpandStrictFPOp(SDNode *Node, SmallVectorImpl &Results); void ExpandREM(SDNode *Node, SmallVectorImpl &Results); @@ -813,6 +812,15 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl &Results) { return; } break; + case ISD::SMIN: + case ISD::SMAX: + case ISD::UMIN: + case ISD::UMAX: + if (SDValue Expanded = TLI.expandIntMINMAX(Node, DAG)) { + Results.push_back(Expanded); + return; + } + break; case ISD::UADDO: case ISD::USUBO: ExpandUADDSUBO(Node, Results); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 634a37b4c7065..552545b854d87 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -607,6 +607,12 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { case ISD::FP_ROUND: Res = ScalarizeVecOp_FP_ROUND(N, OpNo); break; + case ISD::STRICT_FP_EXTEND: + Res = ScalarizeVecOp_STRICT_FP_EXTEND(N); + break; + case ISD::FP_EXTEND: + Res = ScalarizeVecOp_FP_EXTEND(N); + break; case ISD::VECREDUCE_FADD: case ISD::VECREDUCE_FMUL: case ISD::VECREDUCE_ADD: @@ -770,6 +776,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ /// If the value to round is a vector that needs to be scalarized, it must be /// <1 x ty>. Convert the element instead. SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) { + assert(OpNo == 0 && "Wrong operand for scalarization!"); SDValue Elt = GetScalarizedVector(N->getOperand(0)); SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N), N->getValueType(0).getVectorElementType(), Elt, @@ -795,7 +802,36 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_STRICT_FP_ROUND(SDNode *N, // handled all replacements since caller can only handle a single result. ReplaceValueWith(SDValue(N, 0), Res); return SDValue(); -} +} + +/// If the value to extend is a vector that needs to be scalarized, it must be +/// <1 x ty>. Convert the element instead. +SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_EXTEND(SDNode *N) { + SDValue Elt = GetScalarizedVector(N->getOperand(0)); + SDValue Res = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), + N->getValueType(0).getVectorElementType(), Elt); + return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); +} + +/// If the value to extend is a vector that needs to be scalarized, it must be +/// <1 x ty>. Convert the element instead. +SDValue DAGTypeLegalizer::ScalarizeVecOp_STRICT_FP_EXTEND(SDNode *N) { + SDValue Elt = GetScalarizedVector(N->getOperand(1)); + SDValue Res = + DAG.getNode(ISD::STRICT_FP_EXTEND, SDLoc(N), + {N->getValueType(0).getVectorElementType(), MVT::Other}, + {N->getOperand(0), Elt}); + // Legalize the chain result - switch anything that used the old chain to + // use the new one. + ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); + + Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res); + + // Do our own replacement and return SDValue() to tell the caller that we + // handled all replacements since caller can only handle a single result. + ReplaceValueWith(SDValue(N, 0), Res); + return SDValue(); +} SDValue DAGTypeLegalizer::ScalarizeVecOp_VECREDUCE(SDNode *N) { SDValue Res = GetScalarizedVector(N->getOperand(0)); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 2ae6f1cbec177..20e4ac590136e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -139,6 +139,15 @@ bool ConstantFPSDNode::isValueValidForType(EVT VT, //===----------------------------------------------------------------------===// bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) { + if (N->getOpcode() == ISD::SPLAT_VECTOR) { + unsigned EltSize = + N->getValueType(0).getVectorElementType().getSizeInBits(); + if (auto *Op0 = dyn_cast(N->getOperand(0))) { + SplatVal = Op0->getAPIntValue().truncOrSelf(EltSize); + return true; + } + } + auto *BV = dyn_cast(N); if (!BV) return false; @@ -572,6 +581,11 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { ID.AddInteger(cast(N)->getOffset()); } break; + case ISD::PSEUDO_PROBE: + ID.AddInteger(cast(N)->getGuid()); + ID.AddInteger(cast(N)->getIndex()); + ID.AddInteger(cast(N)->getAttributes()); + break; case ISD::JumpTable: case ISD::TargetJumpTable: ID.AddInteger(cast(N)->getIndex()); @@ -6883,6 +6897,30 @@ SDValue SelectionDAG::getLifetimeNode(bool IsStart, const SDLoc &dl, return V; } +SDValue SelectionDAG::getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, + uint64_t Guid, uint64_t Index, + uint32_t Attr) { + const unsigned Opcode = ISD::PSEUDO_PROBE; + const auto VTs = getVTList(MVT::Other); + SDValue Ops[] = {Chain}; + FoldingSetNodeID ID; + AddNodeIDNode(ID, Opcode, VTs, Ops); + ID.AddInteger(Guid); + ID.AddInteger(Index); + void *IP = nullptr; + if (SDNode *E = FindNodeOrInsertPos(ID, Dl, IP)) + return SDValue(E, 0); + + auto *N = newSDNode( + Opcode, Dl.getIROrder(), Dl.getDebugLoc(), VTs, Guid, Index, Attr); + createOperands(N, Ops); + CSEMap.InsertNode(N, IP); + InsertNode(N); + SDValue V(N, 0); + NewSDValueDbgMsg(V, "Creating new node: ", this); + return V; +} + /// InferPointerInfo - If the specified ptr/offset is a frame index, infer a /// MachinePointerInfo record from it. This is particularly useful because the /// code generator has many cases where it doesn't bother passing in a @@ -8297,6 +8335,19 @@ SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, return nullptr; } +/// doesNodeExist - Check if a node exists without modifying its flags. +bool SelectionDAG::doesNodeExist(unsigned Opcode, SDVTList VTList, + ArrayRef Ops) { + if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) { + FoldingSetNodeID ID; + AddNodeIDNode(ID, Opcode, VTList, Ops); + void *IP = nullptr; + if (FindNodeOrInsertPos(ID, SDLoc(), IP)) + return true; + } + return false; +} + /// getDbgValue - Creates a SDDbgValue node. /// /// SDNode diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp index 3a53ab9717a45..20c7d771bfb61 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/SelectionDAGAddressAnalysis.h" +#include "llvm/Analysis/MemoryLocation.h" #include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -96,18 +97,28 @@ bool BaseIndexOffset::computeAliasing(const SDNode *Op0, int64_t PtrDiff; if (NumBytes0.hasValue() && NumBytes1.hasValue() && BasePtr0.equalBaseIndex(BasePtr1, DAG, PtrDiff)) { + // If the size of memory access is unknown, do not use it to analysis. + // One example of unknown size memory access is to load/store scalable + // vector objects on the stack. // BasePtr1 is PtrDiff away from BasePtr0. They alias if none of the // following situations arise: - IsAlias = !( - // [----BasePtr0----] - // [---BasePtr1--] - // ========PtrDiff========> - (*NumBytes0 <= PtrDiff) || - // [----BasePtr0----] - // [---BasePtr1--] - // =====(-PtrDiff)====> - (PtrDiff + *NumBytes1 <= 0)); // i.e. *NumBytes1 < -PtrDiff. - return true; + if (PtrDiff >= 0 && + *NumBytes0 != static_cast(MemoryLocation::UnknownSize)) { + // [----BasePtr0----] + // [---BasePtr1--] + // ========PtrDiff========> + IsAlias = !(*NumBytes0 <= PtrDiff); + return true; + } + if (PtrDiff < 0 && + *NumBytes1 != static_cast(MemoryLocation::UnknownSize)) { + // [----BasePtr0----] + // [---BasePtr1--] + // =====(-PtrDiff)====> + IsAlias = !((PtrDiff + *NumBytes1) <= 0); + return true; + } + return false; } // If both BasePtr0 and BasePtr1 are FrameIndexes, we will not be // able to calculate their relative offset if at least one arises diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index f815da1cbfe42..dd5beb33eccec 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -3131,6 +3131,7 @@ void SelectionDAGBuilder::visitSelect(const User &I) { Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT; bool IsUnaryAbs = false; + bool Negate = false; SDNodeFlags Flags; if (auto *FPOp = dyn_cast(&I)) @@ -3195,12 +3196,13 @@ void SelectionDAGBuilder::visitSelect(const User &I) { break; } break; + case SPF_NABS: + Negate = true; + LLVM_FALLTHROUGH; case SPF_ABS: IsUnaryAbs = true; Opc = ISD::ABS; break; - case SPF_NABS: - // TODO: we need to produce sub(0, abs(X)). default: break; } @@ -3227,10 +3229,13 @@ void SelectionDAGBuilder::visitSelect(const User &I) { if (IsUnaryAbs) { for (unsigned i = 0; i != NumValues; ++i) { + SDLoc dl = getCurSDLoc(); + EVT VT = LHSVal.getNode()->getValueType(LHSVal.getResNo() + i); Values[i] = - DAG.getNode(OpCode, getCurSDLoc(), - LHSVal.getNode()->getValueType(LHSVal.getResNo() + i), - SDValue(LHSVal.getNode(), LHSVal.getResNo() + i)); + DAG.getNode(OpCode, dl, VT, LHSVal.getValue(LHSVal.getResNo() + i)); + if (Negate) + Values[i] = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), + Values[i]); } } else { for (unsigned i = 0; i != NumValues; ++i) { @@ -4353,7 +4358,7 @@ void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) { // Do not serialize masked loads of constant memory with anything. MemoryLocation ML; if (VT.isScalableVector()) - ML = MemoryLocation(PtrOperand, LocationSize::unknown()); + ML = MemoryLocation::getAfter(PtrOperand); else ML = MemoryLocation(PtrOperand, LocationSize::precise( DAG.getDataLayout().getTypeStoreSize(I.getType())), @@ -6590,6 +6595,14 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, } return; } + case Intrinsic::pseudoprobe: { + auto Guid = cast(I.getArgOperand(0))->getZExtValue(); + auto Index = cast(I.getArgOperand(1))->getZExtValue(); + auto Attr = cast(I.getArgOperand(2))->getZExtValue(); + Res = DAG.getPseudoProbeNode(sdl, getRoot(), Guid, Index, Attr); + DAG.setRoot(Res); + return; + } case Intrinsic::invariant_start: // Discard region information. setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout()))); @@ -9401,11 +9414,33 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { return std::make_pair(Res, CLI.Chain); } +/// Places new result values for the node in Results (their number +/// and types must exactly match those of the original return values of +/// the node), or leaves Results empty, which indicates that the node is not +/// to be custom lowered after all. void TargetLowering::LowerOperationWrapper(SDNode *N, SmallVectorImpl &Results, SelectionDAG &DAG) const { - if (SDValue Res = LowerOperation(SDValue(N, 0), DAG)) + SDValue Res = LowerOperation(SDValue(N, 0), DAG); + + if (!Res.getNode()) + return; + + // If the original node has one result, take the return value from + // LowerOperation as is. It might not be result number 0. + if (N->getNumValues() == 1) { Results.push_back(Res); + return; + } + + // If the original node has multiple results, then the return node should + // have the same number of results. + assert((N->getNumValues() == Res->getNumValues()) && + "Lowering returned the wrong number of results!"); + + // Places new result values base on N result number. + for (unsigned I = 0, E = N->getNumValues(); I != E; ++I) + Results.push_back(Res.getValue(I)); } SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp index df35f057072e7..17a4a5cbf02ad 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -396,6 +396,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::DEBUGTRAP: return "debugtrap"; case ISD::LIFETIME_START: return "lifetime.start"; case ISD::LIFETIME_END: return "lifetime.end"; + case ISD::PSEUDO_PROBE: + return "pseudoprobe"; case ISD::GC_TRANSITION_START: return "gc_transition.start"; case ISD::GC_TRANSITION_END: return "gc_transition.end"; case ISD::GET_DYNAMIC_AREA_OFFSET: return "get.dynamic.area.offset"; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 3f3eb354bee31..6c73842414cb5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2808,6 +2808,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, case ISD::ANNOTATION_LABEL: case ISD::LIFETIME_START: case ISD::LIFETIME_END: + case ISD::PSEUDO_PROBE: NodeToMatch->setNodeId(-1); // Mark selected. return; case ISD::AssertSext: diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 875a429253ca6..e45a311f84a48 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -3476,8 +3476,8 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) && (DCI.isBeforeLegalizeOps() || isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) && - DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N1, N0 } ) && - !DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N0, N1 } )) + DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N1, N0}) && + !DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N0, N1})) return DAG.getSetCC(dl, VT, N1, N0, SwappedCC); if (auto *N1C = isConstOrConstSplat(N1)) { @@ -6822,6 +6822,22 @@ bool TargetLowering::expandABS(SDNode *N, SDValue &Result, EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout()); SDValue Op = N->getOperand(0); + // abs(x) -> smax(x,sub(0,x)) + if (isOperationLegal(ISD::SUB, VT) && isOperationLegal(ISD::SMAX, VT)) { + SDValue Zero = DAG.getConstant(0, dl, VT); + Result = DAG.getNode(ISD::SMAX, dl, VT, Op, + DAG.getNode(ISD::SUB, dl, VT, Zero, Op)); + return true; + } + + // abs(x) -> umin(x,sub(0,x)) + if (isOperationLegal(ISD::SUB, VT) && isOperationLegal(ISD::UMIN, VT)) { + SDValue Zero = DAG.getConstant(0, dl, VT); + Result = DAG.getNode(ISD::UMIN, dl, VT, Op, + DAG.getNode(ISD::SUB, dl, VT, Zero, Op)); + return true; + } + // Only expand vector types if we have the appropriate vector operations. if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SRA, VT) || !isOperationLegalOrCustom(ISD::ADD, VT) || @@ -7458,6 +7474,46 @@ TargetLowering::getCanonicalIndexType(ISD::MemIndexType IndexType, EVT MemVT, return IndexType; } +SDValue TargetLowering::expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const { + SDValue Op0 = Node->getOperand(0); + SDValue Op1 = Node->getOperand(1); + EVT VT = Op0.getValueType(); + unsigned Opcode = Node->getOpcode(); + SDLoc DL(Node); + + // umin(x,y) -> sub(x,usubsat(x,y)) + if (Opcode == ISD::UMIN && isOperationLegal(ISD::SUB, VT) && + isOperationLegal(ISD::USUBSAT, VT)) { + return DAG.getNode(ISD::SUB, DL, VT, Op0, + DAG.getNode(ISD::USUBSAT, DL, VT, Op0, Op1)); + } + + // umax(x,y) -> add(x,usubsat(y,x)) + if (Opcode == ISD::UMAX && isOperationLegal(ISD::ADD, VT) && + isOperationLegal(ISD::USUBSAT, VT)) { + return DAG.getNode(ISD::ADD, DL, VT, Op0, + DAG.getNode(ISD::USUBSAT, DL, VT, Op1, Op0)); + } + + // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B + ISD::CondCode CC; + switch (Opcode) { + default: llvm_unreachable("How did we get here?"); + case ISD::SMAX: CC = ISD::SETGT; break; + case ISD::SMIN: CC = ISD::SETLT; break; + case ISD::UMAX: CC = ISD::SETUGT; break; + case ISD::UMIN: CC = ISD::SETULT; break; + } + + // FIXME: Should really try to split the vector in case it's legal on a + // subvector. + if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) + return DAG.UnrollVectorOp(Node); + + SDValue Cond = DAG.getSetCC(DL, VT, Op0, Op1, CC); + return DAG.getSelect(DL, VT, Cond, Op0, Op1); +} + SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const { unsigned Opcode = Node->getOpcode(); SDValue LHS = Node->getOperand(0); diff --git a/llvm/lib/CodeGen/WasmEHPrepare.cpp b/llvm/lib/CodeGen/WasmEHPrepare.cpp index 44f4fe2ff9b1f..171ba78203ec5 100644 --- a/llvm/lib/CodeGen/WasmEHPrepare.cpp +++ b/llvm/lib/CodeGen/WasmEHPrepare.cpp @@ -169,7 +169,7 @@ static void eraseDeadBBsAndChildren(const Container &BBs, DomTreeUpdater *DTU) { SmallVector WL(BBs.begin(), BBs.end()); while (!WL.empty()) { auto *BB = WL.pop_back_val(); - if (pred_begin(BB) != pred_end(BB)) + if (!pred_empty(BB)) continue; WL.append(succ_begin(BB), succ_end(BB)); DeleteDeadBlock(BB, DTU); diff --git a/llvm/lib/DebugInfo/PDB/Native/NativeFunctionSymbol.cpp b/llvm/lib/DebugInfo/PDB/Native/NativeFunctionSymbol.cpp index dc4d256b614a0..708ed36eb50be 100644 --- a/llvm/lib/DebugInfo/PDB/Native/NativeFunctionSymbol.cpp +++ b/llvm/lib/DebugInfo/PDB/Native/NativeFunctionSymbol.cpp @@ -121,7 +121,6 @@ NativeFunctionSymbol::findInlineFramesByVA(uint64_t VA) const { InlineSiteSym IS = cantFail(SymbolDeserializer::deserializeAs(*Start)); if (inlineSiteContainsAddress(IS, CodeOffset)) { - fprintf(stderr, "inline: %d\n", Start.offset()); // Insert frames in reverse order. SymIndexId Id = Session.getSymbolCache().getOrCreateInlineSymbol( IS, getVirtualAddress(), Modi, Start.offset()); diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index 75c25cde623c4..88331bf2ba161 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -1568,6 +1568,11 @@ static void WriteConstantInternal(raw_ostream &Out, const Constant *CV, return; } + if (isa(CV)) { + Out << "poison"; + return; + } + if (isa(CV)) { Out << "undef"; return; diff --git a/llvm/lib/IR/BasicBlock.cpp b/llvm/lib/IR/BasicBlock.cpp index b1d7960190d6e..23a1184e12462 100644 --- a/llvm/lib/IR/BasicBlock.cpp +++ b/llvm/lib/IR/BasicBlock.cpp @@ -97,18 +97,20 @@ void BasicBlock::setParent(Function *parent) { iterator_range>> -BasicBlock::instructionsWithoutDebug() const { - std::function Fn = [](const Instruction &I) { - return !isa(I); +BasicBlock::instructionsWithoutDebug(bool SkipPseudoOp) const { + std::function Fn = [=](const Instruction &I) { + return !isa(I) && + !(SkipPseudoOp && isa(I)); }; return make_filter_range(*this, Fn); } -iterator_range>> -BasicBlock::instructionsWithoutDebug() { - std::function Fn = [](Instruction &I) { - return !isa(I); +iterator_range< + filter_iterator>> +BasicBlock::instructionsWithoutDebug(bool SkipPseudoOp) { + std::function Fn = [=](Instruction &I) { + return !isa(I) && + !(SkipPseudoOp && isa(I)); }; return make_filter_range(*this, Fn); } @@ -218,14 +220,21 @@ const Instruction* BasicBlock::getFirstNonPHI() const { return nullptr; } -const Instruction* BasicBlock::getFirstNonPHIOrDbg() const { - for (const Instruction &I : *this) - if (!isa(I) && !isa(I)) - return &I; +const Instruction *BasicBlock::getFirstNonPHIOrDbg(bool SkipPseudoOp) const { + for (const Instruction &I : *this) { + if (isa(I) || isa(I)) + continue; + + if (SkipPseudoOp && isa(I)) + continue; + + return &I; + } return nullptr; } -const Instruction* BasicBlock::getFirstNonPHIOrDbgOrLifetime() const { +const Instruction * +BasicBlock::getFirstNonPHIOrDbgOrLifetime(bool SkipPseudoOp) const { for (const Instruction &I : *this) { if (isa(I) || isa(I)) continue; @@ -233,6 +242,9 @@ const Instruction* BasicBlock::getFirstNonPHIOrDbgOrLifetime() const { if (I.isLifetimeStartOrEnd()) continue; + if (SkipPseudoOp && isa(I)) + continue; + return &I; } return nullptr; diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp index 732d6e69ba921..764d32e39b05c 100644 --- a/llvm/lib/IR/Constants.cpp +++ b/llvm/lib/IR/Constants.cpp @@ -408,16 +408,20 @@ Constant *Constant::getAllOnesValue(Type *Ty) { } Constant *Constant::getAggregateElement(unsigned Elt) const { - if (const ConstantAggregate *CC = dyn_cast(this)) + if (const auto *CC = dyn_cast(this)) return Elt < CC->getNumOperands() ? CC->getOperand(Elt) : nullptr; - if (const ConstantAggregateZero *CAZ = dyn_cast(this)) + // FIXME: getNumElements() will fail for non-fixed vector types. + if (isa(getType())) + return nullptr; + + if (const auto *CAZ = dyn_cast(this)) return Elt < CAZ->getNumElements() ? CAZ->getElementValue(Elt) : nullptr; - if (const UndefValue *UV = dyn_cast(this)) + if (const auto *UV = dyn_cast(this)) return Elt < UV->getNumElements() ? UV->getElementValue(Elt) : nullptr; - if (const ConstantDataSequential *CDS =dyn_cast(this)) + if (const auto *CDS = dyn_cast(this)) return Elt < CDS->getNumElements() ? CDS->getElementAsConstant(Elt) : nullptr; return nullptr; @@ -515,6 +519,9 @@ void llvm::deleteConstant(Constant *C) { case Constant::UndefValueVal: delete static_cast(C); break; + case Constant::PoisonValueVal: + delete static_cast(C); + break; case Constant::ConstantExprVal: if (isa(C)) delete static_cast(C); @@ -1085,6 +1092,32 @@ unsigned UndefValue::getNumElements() const { return Ty->getStructNumElements(); } +//===----------------------------------------------------------------------===// +// PoisonValue Implementation +//===----------------------------------------------------------------------===// + +PoisonValue *PoisonValue::getSequentialElement() const { + if (ArrayType *ATy = dyn_cast(getType())) + return PoisonValue::get(ATy->getElementType()); + return PoisonValue::get(cast(getType())->getElementType()); +} + +PoisonValue *PoisonValue::getStructElement(unsigned Elt) const { + return PoisonValue::get(getType()->getStructElementType(Elt)); +} + +PoisonValue *PoisonValue::getElementValue(Constant *C) const { + if (isa(getType()) || isa(getType())) + return getSequentialElement(); + return getStructElement(cast(C)->getZExtValue()); +} + +PoisonValue *PoisonValue::getElementValue(unsigned Idx) const { + if (isa(getType()) || isa(getType())) + return getSequentialElement(); + return getStructElement(Idx); +} + //===----------------------------------------------------------------------===// // ConstantXXX Classes //===----------------------------------------------------------------------===// @@ -1692,7 +1725,26 @@ UndefValue *UndefValue::get(Type *Ty) { /// Remove the constant from the constant table. void UndefValue::destroyConstantImpl() { // Free the constant and any dangling references to it. - getContext().pImpl->UVConstants.erase(getType()); + if (getValueID() == UndefValueVal) { + getContext().pImpl->UVConstants.erase(getType()); + } else if (getValueID() == PoisonValueVal) { + getContext().pImpl->PVConstants.erase(getType()); + } + llvm_unreachable("Not a undef or a poison!"); +} + +PoisonValue *PoisonValue::get(Type *Ty) { + std::unique_ptr &Entry = Ty->getContext().pImpl->PVConstants[Ty]; + if (!Entry) + Entry.reset(new PoisonValue(Ty)); + + return Entry.get(); +} + +/// Remove the constant from the constant table. +void PoisonValue::destroyConstantImpl() { + // Free the constant and any dangling references to it. + getContext().pImpl->PVConstants.erase(getType()); } BlockAddress *BlockAddress::get(BasicBlock *BB) { diff --git a/llvm/lib/IR/Core.cpp b/llvm/lib/IR/Core.cpp index 28ada52ab9119..ea90a33f16292 100644 --- a/llvm/lib/IR/Core.cpp +++ b/llvm/lib/IR/Core.cpp @@ -1046,6 +1046,10 @@ LLVMValueRef LLVMGetUndef(LLVMTypeRef Ty) { return wrap(UndefValue::get(unwrap(Ty))); } +LLVMValueRef LLVMGetPoison(LLVMTypeRef Ty) { + return wrap(PoisonValue::get(unwrap(Ty))); +} + LLVMBool LLVMIsConstant(LLVMValueRef Ty) { return isa(unwrap(Ty)); } @@ -1060,6 +1064,10 @@ LLVMBool LLVMIsUndef(LLVMValueRef Val) { return isa(unwrap(Val)); } +LLVMBool LLVMIsPoison(LLVMValueRef Val) { + return isa(unwrap(Val)); +} + LLVMValueRef LLVMConstPointerNull(LLVMTypeRef Ty) { return wrap(ConstantPointerNull::get(unwrap(Ty))); } diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp index 04bd045d9fd11..1e3fcd672a43e 100644 --- a/llvm/lib/IR/Instruction.cpp +++ b/llvm/lib/IR/Instruction.cpp @@ -641,16 +641,18 @@ bool Instruction::isLifetimeStartOrEnd() const { return ID == Intrinsic::lifetime_start || ID == Intrinsic::lifetime_end; } -const Instruction *Instruction::getNextNonDebugInstruction() const { +const Instruction * +Instruction::getNextNonDebugInstruction(bool SkipPseudoOp) const { for (const Instruction *I = getNextNode(); I; I = I->getNextNode()) - if (!isa(I)) + if (!isa(I) && !(SkipPseudoOp && isa(I))) return I; return nullptr; } -const Instruction *Instruction::getPrevNonDebugInstruction() const { +const Instruction * +Instruction::getPrevNonDebugInstruction(bool SkipPseudoOp) const { for (const Instruction *I = getPrevNode(); I; I = I->getPrevNode()) - if (!isa(I)) + if (!isa(I) && !(SkipPseudoOp && isa(I))) return I; return nullptr; } diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp index 91340e2333adc..10427b22d5d71 100644 --- a/llvm/lib/IR/Instructions.cpp +++ b/llvm/lib/IR/Instructions.cpp @@ -49,13 +49,14 @@ using namespace llvm; // AllocaInst Class //===----------------------------------------------------------------------===// -Optional +Optional AllocaInst::getAllocationSizeInBits(const DataLayout &DL) const { - uint64_t Size = DL.getTypeAllocSizeInBits(getAllocatedType()); + TypeSize Size = DL.getTypeAllocSizeInBits(getAllocatedType()); if (isArrayAllocation()) { auto *C = dyn_cast(getArraySize()); if (!C) return None; + assert(!Size.isScalable() && "Array elements cannot have a scalable size"); Size *= C->getZExtValue(); } return Size; @@ -560,8 +561,9 @@ void CallInst::updateProfWeight(uint64_t S, uint64_t T) { ->getValue() .getZExtValue()); Val *= APS; - Vals.push_back(MDB.createConstant(ConstantInt::get( - Type::getInt64Ty(getContext()), Val.udiv(APT).getLimitedValue()))); + Vals.push_back(MDB.createConstant( + ConstantInt::get(Type::getInt32Ty(getContext()), + Val.udiv(APT).getLimitedValue(UINT32_MAX)))); } else if (ProfDataName->getString().equals("VP")) for (unsigned i = 1; i < ProfileData->getNumOperands(); i += 2) { // The first value is the key of the value profile, which will not change. diff --git a/llvm/lib/IR/LLVMContextImpl.cpp b/llvm/lib/IR/LLVMContextImpl.cpp index c4f0a0ac85491..875c61cda4230 100644 --- a/llvm/lib/IR/LLVMContextImpl.cpp +++ b/llvm/lib/IR/LLVMContextImpl.cpp @@ -97,6 +97,7 @@ LLVMContextImpl::~LLVMContextImpl() { CAZConstants.clear(); CPNConstants.clear(); UVConstants.clear(); + PVConstants.clear(); IntConstants.clear(); FPConstants.clear(); CDSConstants.clear(); diff --git a/llvm/lib/IR/LLVMContextImpl.h b/llvm/lib/IR/LLVMContextImpl.h index 8f1b2de1e61b3..1f7f04589404e 100644 --- a/llvm/lib/IR/LLVMContextImpl.h +++ b/llvm/lib/IR/LLVMContextImpl.h @@ -1376,6 +1376,8 @@ class LLVMContextImpl { DenseMap> UVConstants; + DenseMap> PVConstants; + StringMap> CDSConstants; DenseMap, BlockAddress *> diff --git a/llvm/lib/IR/LegacyPassManager.cpp b/llvm/lib/IR/LegacyPassManager.cpp index 7f94d42d6ecde..8fd35ef975e2c 100644 --- a/llvm/lib/IR/LegacyPassManager.cpp +++ b/llvm/lib/IR/LegacyPassManager.cpp @@ -675,11 +675,9 @@ PMTopLevelManager::setLastUser(ArrayRef AnalysisPasses, Pass *P) { // If AP is the last user of other passes then make P last user of // such passes. - for (auto LU : LastUser) { + for (auto &LU : LastUser) { if (LU.second == AP) - // DenseMap iterator is not invalidated here because - // this is just updating existing entries. - LastUser[LU.first] = P; + LU.second = P; } } } @@ -1392,8 +1390,8 @@ PMDataManager::~PMDataManager() { //===----------------------------------------------------------------------===// // NOTE: Is this the right place to define this method ? // getAnalysisIfAvailable - Return analysis result or null if it doesn't exist. -Pass *AnalysisResolver::getAnalysisIfAvailable(AnalysisID ID, bool dir) const { - return PM.findAnalysisPass(ID, dir); +Pass *AnalysisResolver::getAnalysisIfAvailable(AnalysisID ID) const { + return PM.findAnalysisPass(ID, true); } std::tuple diff --git a/llvm/lib/IR/Pass.cpp b/llvm/lib/IR/Pass.cpp index a815da2bdc513..0750501a92c4b 100644 --- a/llvm/lib/IR/Pass.cpp +++ b/llvm/lib/IR/Pass.cpp @@ -62,7 +62,7 @@ bool ModulePass::skipModule(Module &M) const { } bool Pass::mustPreserveAnalysisID(char &AID) const { - return Resolver->getAnalysisIfAvailable(&AID, true) != nullptr; + return Resolver->getAnalysisIfAvailable(&AID) != nullptr; } // dumpPassStructure - Implement the -debug-pass=Structure option diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index 737cbb910f104..eda923da8df8a 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -1754,17 +1754,6 @@ void Verifier::verifyParameterAttrs(AttributeSet Attrs, Type *Ty, "'noinline and alwaysinline' are incompatible!", V); - if (Attrs.hasAttribute(Attribute::ByVal) && Attrs.getByValType()) { - Assert(Attrs.getByValType() == cast(Ty)->getElementType(), - "Attribute 'byval' type does not match parameter!", V); - } - - if (Attrs.hasAttribute(Attribute::Preallocated)) { - Assert(Attrs.getPreallocatedType() == - cast(Ty)->getElementType(), - "Attribute 'preallocated' type does not match parameter!", V); - } - AttrBuilder IncompatibleAttrs = AttributeFuncs::typeIncompatible(Ty); Assert(!AttrBuilder(Attrs).overlaps(IncompatibleAttrs), "Wrong types for attribute: " + @@ -1792,6 +1781,16 @@ void Verifier::verifyParameterAttrs(AttributeSet Attrs, Type *Ty, Assert(Attrs.getByRefType() == PTy->getElementType(), "Attribute 'byref' type does not match parameter!", V); } + + if (Attrs.hasAttribute(Attribute::ByVal) && Attrs.getByValType()) { + Assert(Attrs.getByValType() == PTy->getElementType(), + "Attribute 'byval' type does not match parameter!", V); + } + + if (Attrs.hasAttribute(Attribute::Preallocated)) { + Assert(Attrs.getPreallocatedType() == PTy->getElementType(), + "Attribute 'preallocated' type does not match parameter!", V); + } } else { Assert(!Attrs.hasAttribute(Attribute::ByVal), "Attribute 'byval' only applies to parameters with pointer type!", diff --git a/llvm/lib/InterfaceStub/CMakeLists.txt b/llvm/lib/InterfaceStub/CMakeLists.txt index 4aacebf16cf94..17801999c485a 100644 --- a/llvm/lib/InterfaceStub/CMakeLists.txt +++ b/llvm/lib/InterfaceStub/CMakeLists.txt @@ -4,6 +4,7 @@ add_llvm_component_library(LLVMInterfaceStub TBEHandler.cpp LINK_COMPONENTS + MC Object Support ) diff --git a/llvm/lib/InterfaceStub/ELFObjHandler.cpp b/llvm/lib/InterfaceStub/ELFObjHandler.cpp index cc9a8743cd084..ba583b79571e4 100644 --- a/llvm/lib/InterfaceStub/ELFObjHandler.cpp +++ b/llvm/lib/InterfaceStub/ELFObjHandler.cpp @@ -8,11 +8,14 @@ #include "llvm/InterfaceStub/ELFObjHandler.h" #include "llvm/InterfaceStub/ELFStub.h" +#include "llvm/MC/StringTableBuilder.h" #include "llvm/Object/Binary.h" #include "llvm/Object/ELFObjectFile.h" #include "llvm/Object/ELFTypes.h" #include "llvm/Support/Errc.h" #include "llvm/Support/Error.h" +#include "llvm/Support/FileOutputBuffer.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/MemoryBuffer.h" using llvm::MemoryBufferRef; @@ -38,6 +41,297 @@ struct DynamicEntries { Optional GnuHash; }; +/// This initializes an ELF file header with information specific to a binary +/// dynamic shared object. +/// Offsets, indexes, links, etc. for section and program headers are just +/// zero-initialized as they will be updated elsewhere. +/// +/// @param ElfHeader Target ELFT::Ehdr to populate. +/// @param Machine Target architecture (e_machine from ELF specifications). +template +static void initELFHeader(typename ELFT::Ehdr &ElfHeader, uint16_t Machine) { + memset(&ElfHeader, 0, sizeof(ElfHeader)); + // ELF identification. + ElfHeader.e_ident[EI_MAG0] = ElfMagic[EI_MAG0]; + ElfHeader.e_ident[EI_MAG1] = ElfMagic[EI_MAG1]; + ElfHeader.e_ident[EI_MAG2] = ElfMagic[EI_MAG2]; + ElfHeader.e_ident[EI_MAG3] = ElfMagic[EI_MAG3]; + ElfHeader.e_ident[EI_CLASS] = ELFT::Is64Bits ? ELFCLASS64 : ELFCLASS32; + bool IsLittleEndian = ELFT::TargetEndianness == support::little; + ElfHeader.e_ident[EI_DATA] = IsLittleEndian ? ELFDATA2LSB : ELFDATA2MSB; + ElfHeader.e_ident[EI_VERSION] = EV_CURRENT; + ElfHeader.e_ident[EI_OSABI] = ELFOSABI_NONE; + + // Remainder of ELF header. + ElfHeader.e_type = ET_DYN; + ElfHeader.e_machine = Machine; + ElfHeader.e_version = EV_CURRENT; + ElfHeader.e_ehsize = sizeof(typename ELFT::Ehdr); + ElfHeader.e_phentsize = sizeof(typename ELFT::Phdr); + ElfHeader.e_shentsize = sizeof(typename ELFT::Shdr); +} + +namespace { +template struct OutputSection { + using Elf_Shdr = typename ELFT::Shdr; + std::string Name; + Elf_Shdr Shdr; + uint64_t Addr; + uint64_t Offset; + uint64_t Size; + uint64_t Align; + uint32_t Index; + bool NoBits = true; +}; + +template +struct ContentSection : public OutputSection { + T Content; + ContentSection() { this->NoBits = false; } +}; + +// This class just wraps StringTableBuilder for the purpose of adding a +// default constructor. +class ELFStringTableBuilder : public StringTableBuilder { +public: + ELFStringTableBuilder() : StringTableBuilder(StringTableBuilder::ELF) {} +}; + +template class ELFSymbolTableBuilder { +public: + using Elf_Sym = typename ELFT::Sym; + + ELFSymbolTableBuilder() { Symbols.push_back({}); } + + void add(size_t StNameOffset, uint64_t StSize, uint8_t StBind, uint8_t StType, + uint8_t StOther, uint16_t StShndx) { + Elf_Sym S{}; + S.st_name = StNameOffset; + S.st_size = StSize; + S.st_info = (StBind << 4) | (StType & 0xf); + S.st_other = StOther; + S.st_shndx = StShndx; + Symbols.push_back(S); + } + + size_t getSize() const { return Symbols.size() * sizeof(Elf_Sym); } + + void write(uint8_t *Buf) const { + memcpy(Buf, Symbols.data(), sizeof(Elf_Sym) * Symbols.size()); + } + +private: + llvm::SmallVector Symbols; +}; + +template class ELFDynamicTableBuilder { +public: + using Elf_Dyn = typename ELFT::Dyn; + + size_t addAddr(uint64_t Tag, uint64_t Addr) { + Elf_Dyn Entry; + Entry.d_tag = Tag; + Entry.d_un.d_ptr = Addr; + Entries.push_back(Entry); + return Entries.size() - 1; + } + + void modifyAddr(size_t Index, uint64_t Addr) { + Entries[Index].d_un.d_ptr = Addr; + } + + size_t addValue(uint64_t Tag, uint64_t Value) { + Elf_Dyn Entry; + Entry.d_tag = Tag; + Entry.d_un.d_val = Value; + Entries.push_back(Entry); + return Entries.size() - 1; + } + + void modifyValue(size_t Index, uint64_t Value) { + Entries[Index].d_un.d_val = Value; + } + + size_t getSize() const { + // Add DT_NULL entry at the end. + return (Entries.size() + 1) * sizeof(Elf_Dyn); + } + + void write(uint8_t *Buf) const { + memcpy(Buf, Entries.data(), sizeof(Elf_Dyn) * Entries.size()); + // Add DT_NULL entry at the end. + memset(Buf + sizeof(Elf_Dyn) * Entries.size(), 0, sizeof(Elf_Dyn)); + } + +private: + llvm::SmallVector Entries; +}; + +template class ELFStubBuilder { +public: + using Elf_Ehdr = typename ELFT::Ehdr; + using Elf_Shdr = typename ELFT::Shdr; + using Elf_Phdr = typename ELFT::Phdr; + using Elf_Sym = typename ELFT::Sym; + using Elf_Addr = typename ELFT::Addr; + using Elf_Dyn = typename ELFT::Dyn; + + ELFStubBuilder(const ELFStubBuilder &) = delete; + ELFStubBuilder(ELFStubBuilder &&) = default; + + explicit ELFStubBuilder(const ELFStub &Stub) { + DynSym.Name = ".dynsym"; + DynSym.Align = sizeof(Elf_Addr); + DynStr.Name = ".dynstr"; + DynStr.Align = 1; + DynTab.Name = ".dynamic"; + DynTab.Align = sizeof(Elf_Addr); + ShStrTab.Name = ".shstrtab"; + ShStrTab.Align = 1; + + // Populate string tables. + for (const ELFSymbol &Sym : Stub.Symbols) + DynStr.Content.add(Sym.Name); + for (const std::string &Lib : Stub.NeededLibs) + DynStr.Content.add(Lib); + if (Stub.SoName) + DynStr.Content.add(Stub.SoName.getValue()); + + std::vector *> Sections = {&DynSym, &DynStr, &DynTab, + &ShStrTab}; + const OutputSection *LastSection = Sections.back(); + // Now set the Index and put sections names into ".shstrtab". + uint64_t Index = 1; + for (OutputSection *Sec : Sections) { + Sec->Index = Index++; + ShStrTab.Content.add(Sec->Name); + } + ShStrTab.Content.finalize(); + ShStrTab.Size = ShStrTab.Content.getSize(); + DynStr.Content.finalize(); + DynStr.Size = DynStr.Content.getSize(); + + // Populate dynamic symbol table. + for (const ELFSymbol &Sym : Stub.Symbols) { + uint8_t Bind = Sym.Weak ? STB_WEAK : STB_GLOBAL; + // For non-undefined symbols, value of the shndx is not relevant at link + // time as long as it is not SHN_UNDEF. Set shndx to 1, which + // points to ".dynsym". + uint16_t Shndx = Sym.Undefined ? SHN_UNDEF : 1; + DynSym.Content.add(DynStr.Content.getOffset(Sym.Name), Sym.Size, Bind, + (uint8_t)Sym.Type, 0, Shndx); + } + DynSym.Size = DynSym.Content.getSize(); + + // Poplulate dynamic table. + size_t DynSymIndex = DynTab.Content.addAddr(DT_SYMTAB, 0); + size_t DynStrIndex = DynTab.Content.addAddr(DT_STRTAB, 0); + for (const std::string &Lib : Stub.NeededLibs) + DynTab.Content.addValue(DT_NEEDED, DynStr.Content.getOffset(Lib)); + if (Stub.SoName) + DynTab.Content.addValue(DT_SONAME, + DynStr.Content.getOffset(Stub.SoName.getValue())); + DynTab.Size = DynTab.Content.getSize(); + // Calculate sections' addresses and offsets. + uint64_t CurrentOffset = sizeof(Elf_Ehdr); + for (OutputSection *Sec : Sections) { + Sec->Offset = alignTo(CurrentOffset, Sec->Align); + Sec->Addr = Sec->Offset; + CurrentOffset = Sec->Offset + Sec->Size; + } + // Fill Addr back to dynamic table. + DynTab.Content.modifyAddr(DynSymIndex, DynSym.Addr); + DynTab.Content.modifyAddr(DynStrIndex, DynStr.Addr); + // Write section headers of string tables. + fillSymTabShdr(DynSym, SHT_DYNSYM); + fillStrTabShdr(DynStr, SHF_ALLOC); + fillDynTabShdr(DynTab); + fillStrTabShdr(ShStrTab); + + // Finish initializing the ELF header. + initELFHeader(ElfHeader, Stub.Arch); + ElfHeader.e_shstrndx = ShStrTab.Index; + ElfHeader.e_shnum = LastSection->Index + 1; + ElfHeader.e_shoff = + alignTo(LastSection->Offset + LastSection->Size, sizeof(Elf_Addr)); + } + + size_t getSize() const { + return ElfHeader.e_shoff + ElfHeader.e_shnum * sizeof(Elf_Shdr); + } + + void write(uint8_t *Data) const { + write(Data, ElfHeader); + DynSym.Content.write(Data + DynSym.Shdr.sh_offset); + DynStr.Content.write(Data + DynStr.Shdr.sh_offset); + DynTab.Content.write(Data + DynTab.Shdr.sh_offset); + ShStrTab.Content.write(Data + ShStrTab.Shdr.sh_offset); + writeShdr(Data, DynSym); + writeShdr(Data, DynStr); + writeShdr(Data, DynTab); + writeShdr(Data, ShStrTab); + } + +private: + Elf_Ehdr ElfHeader; + ContentSection DynStr; + ContentSection ShStrTab; + ContentSection, ELFT> DynSym; + ContentSection, ELFT> DynTab; + + template static void write(uint8_t *Data, const T &Value) { + *reinterpret_cast(Data) = Value; + } + + void fillStrTabShdr(ContentSection &StrTab, + uint32_t ShFlags = 0) const { + StrTab.Shdr.sh_type = SHT_STRTAB; + StrTab.Shdr.sh_flags = ShFlags; + StrTab.Shdr.sh_addr = StrTab.Addr; + StrTab.Shdr.sh_offset = StrTab.Offset; + StrTab.Shdr.sh_info = 0; + StrTab.Shdr.sh_size = StrTab.Size; + StrTab.Shdr.sh_name = ShStrTab.Content.getOffset(StrTab.Name); + StrTab.Shdr.sh_addralign = StrTab.Align; + StrTab.Shdr.sh_entsize = 0; + StrTab.Shdr.sh_link = 0; + } + void fillSymTabShdr(ContentSection, ELFT> &SymTab, + uint32_t ShType) const { + SymTab.Shdr.sh_type = ShType; + SymTab.Shdr.sh_flags = SHF_ALLOC; + SymTab.Shdr.sh_addr = SymTab.Addr; + SymTab.Shdr.sh_offset = SymTab.Offset; + SymTab.Shdr.sh_info = SymTab.Size / sizeof(Elf_Sym) > 1 ? 1 : 0; + SymTab.Shdr.sh_size = SymTab.Size; + SymTab.Shdr.sh_name = this->ShStrTab.Content.getOffset(SymTab.Name); + SymTab.Shdr.sh_addralign = SymTab.Align; + SymTab.Shdr.sh_entsize = sizeof(Elf_Sym); + SymTab.Shdr.sh_link = this->DynStr.Index; + } + void fillDynTabShdr( + ContentSection, ELFT> &DynTab) const { + DynTab.Shdr.sh_type = SHT_DYNAMIC; + DynTab.Shdr.sh_flags = SHF_ALLOC; + DynTab.Shdr.sh_addr = DynTab.Addr; + DynTab.Shdr.sh_offset = DynTab.Offset; + DynTab.Shdr.sh_info = 0; + DynTab.Shdr.sh_size = DynTab.Size; + DynTab.Shdr.sh_name = this->ShStrTab.Content.getOffset(DynTab.Name); + DynTab.Shdr.sh_addralign = DynTab.Align; + DynTab.Shdr.sh_entsize = sizeof(Elf_Dyn); + DynTab.Shdr.sh_link = this->DynStr.Index; + } + uint64_t shdrOffset(const OutputSection &Sec) const { + return ElfHeader.e_shoff + Sec.Index * sizeof(Elf_Shdr); + } + + void writeShdr(uint8_t *Data, const OutputSection &Sec) const { + write(Data + shdrOffset(Sec), Sec.Shdr); + } +}; +} // end anonymous namespace + /// This function behaves similarly to StringRef::substr(), but attempts to /// terminate the returned StringRef at the first null terminator. If no null /// terminator is found, an error is returned. @@ -364,6 +658,32 @@ buildStub(const ELFObjectFile &ElfObj) { return std::move(DestStub); } +/// This function opens a file for writing and then writes a binary ELF stub to +/// the file. +/// +/// @param FilePath File path for writing the ELF binary. +/// @param Stub Source ELFStub to generate a binary ELF stub from. +template +static Error writeELFBinaryToFile(StringRef FilePath, const ELFStub &Stub) { + ELFStubBuilder Builder{Stub}; + Expected> BufOrError = + FileOutputBuffer::create(FilePath, Builder.getSize()); + if (!BufOrError) + return createStringError(errc::invalid_argument, + toString(BufOrError.takeError()) + + " when trying to open `" + FilePath + + "` for writing"); + + // Write binary to file. + std::unique_ptr Buf = std::move(*BufOrError); + Builder.write(Buf->getBufferStart()); + + if (Error E = Buf->commit()) + return E; + + return Error::success(); +} + Expected> readELFFile(MemoryBufferRef Buf) { Expected> BinOrErr = createBinary(Buf); if (!BinOrErr) { @@ -380,8 +700,22 @@ Expected> readELFFile(MemoryBufferRef Buf) { } else if (auto Obj = dyn_cast>(Bin)) { return buildStub(*Obj); } + return createStringError(errc::not_supported, "unsupported binary format"); +} - return createStringError(errc::not_supported, "Unsupported binary format"); +// This function wraps the ELFT writeELFBinaryToFile() so writeBinaryStub() +// can be called without having to use ELFType templates directly. +Error writeBinaryStub(StringRef FilePath, const ELFStub &Stub, + ELFTarget OutputFormat) { + if (OutputFormat == ELFTarget::ELF32LE) + return writeELFBinaryToFile(FilePath, Stub); + if (OutputFormat == ELFTarget::ELF32BE) + return writeELFBinaryToFile(FilePath, Stub); + if (OutputFormat == ELFTarget::ELF64LE) + return writeELFBinaryToFile(FilePath, Stub); + if (OutputFormat == ELFTarget::ELF64BE) + return writeELFBinaryToFile(FilePath, Stub); + llvm_unreachable("invalid binary output target"); } } // end namespace elfabi diff --git a/llvm/lib/LTO/LTOBackend.cpp b/llvm/lib/LTO/LTOBackend.cpp index 635584a29e6e4..3365880d2ec10 100644 --- a/llvm/lib/LTO/LTOBackend.cpp +++ b/llvm/lib/LTO/LTOBackend.cpp @@ -199,9 +199,11 @@ createTargetMachine(const Config &Conf, const Target *TheTarget, Module &M) { else CodeModel = M.getCodeModel(); - return std::unique_ptr(TheTarget->createTargetMachine( + std::unique_ptr TM(TheTarget->createTargetMachine( TheTriple, Conf.CPU, Features.getString(), Conf.Options, RelocModel, CodeModel, Conf.CGOptLevel)); + assert(TM && "Failed to create target machine"); + return TM; } static void runNewPMPasses(const Config &Conf, Module &Mod, TargetMachine *TM, diff --git a/llvm/lib/LTO/LTOCodeGenerator.cpp b/llvm/lib/LTO/LTOCodeGenerator.cpp index aff1977850b88..6b85eea3bc717 100644 --- a/llvm/lib/LTO/LTOCodeGenerator.cpp +++ b/llvm/lib/LTO/LTOCodeGenerator.cpp @@ -374,10 +374,13 @@ bool LTOCodeGenerator::determineTarget() { } TargetMach = createTargetMachine(); + assert(TargetMach && "Unable to create target machine"); + return true; } std::unique_ptr LTOCodeGenerator::createTargetMachine() { + assert(MArch && "MArch is not set!"); return std::unique_ptr(MArch->createTargetMachine( TripleStr, MCpu, FeatureStr, Options, RelocModel, None, CGOptLevel)); } diff --git a/llvm/lib/LTO/LTOModule.cpp b/llvm/lib/LTO/LTOModule.cpp index ebe779aea62ea..9c14d4ad5adb4 100644 --- a/llvm/lib/LTO/LTOModule.cpp +++ b/llvm/lib/LTO/LTOModule.cpp @@ -46,6 +46,7 @@ using namespace llvm::object; LTOModule::LTOModule(std::unique_ptr M, MemoryBufferRef MBRef, llvm::TargetMachine *TM) : Mod(std::move(M)), MBRef(MBRef), _target(TM) { + assert(_target && "target machine is null"); SymTab.addModule(Mod.get()); } diff --git a/llvm/lib/LTO/ThinLTOCodeGenerator.cpp b/llvm/lib/LTO/ThinLTOCodeGenerator.cpp index 3f71487951c8d..092d555cacfae 100644 --- a/llvm/lib/LTO/ThinLTOCodeGenerator.cpp +++ b/llvm/lib/LTO/ThinLTOCodeGenerator.cpp @@ -575,9 +575,12 @@ std::unique_ptr TargetMachineBuilder::create() const { Features.getDefaultSubtargetFeatures(TheTriple); std::string FeatureStr = Features.getString(); - return std::unique_ptr( + std::unique_ptr TM( TheTarget->createTargetMachine(TheTriple.str(), MCpu, FeatureStr, Options, RelocModel, None, CGOptLevel)); + assert(TM && "Cannot create target machine"); + + return TM; } /** diff --git a/llvm/lib/MC/MCObjectFileInfo.cpp b/llvm/lib/MC/MCObjectFileInfo.cpp index b8c66c68f71c1..75e65e3f10f47 100644 --- a/llvm/lib/MC/MCObjectFileInfo.cpp +++ b/llvm/lib/MC/MCObjectFileInfo.cpp @@ -997,7 +997,7 @@ MCObjectFileInfo::getStackSizesSection(const MCSection &TextSec) const { } return Ctx->getELFSection(".stack_sizes", ELF::SHT_PROGBITS, Flags, 0, - GroupName, MCSection::NonUniqueID, + GroupName, ElfSec.getUniqueID(), cast(TextSec.getBeginSymbol())); } diff --git a/llvm/lib/MC/MCParser/COFFMasmParser.cpp b/llvm/lib/MC/MCParser/COFFMasmParser.cpp index 61d69ee4e7e8c..aacce928c1419 100644 --- a/llvm/lib/MC/MCParser/COFFMasmParser.cpp +++ b/llvm/lib/MC/MCParser/COFFMasmParser.cpp @@ -118,9 +118,7 @@ class COFFMasmParser : public MCAsmParserExtension { addDirectiveHandler<&COFFMasmParser::IgnoreDirective>("title"); // Macro directives - // exitm // goto - // purge // Miscellaneous directives addDirectiveHandler<&COFFMasmParser::ParseDirectiveAlias>("alias"); @@ -153,9 +151,6 @@ class COFFMasmParser : public MCAsmParserExtension { addDirectiveHandler<&COFFMasmParser::IgnoreDirective>(".mmx"); addDirectiveHandler<&COFFMasmParser::IgnoreDirective>(".xmm"); - // Repeat blocks directives - // goto - // Scope directives // comm // externdef diff --git a/llvm/lib/MC/MCParser/MasmParser.cpp b/llvm/lib/MC/MCParser/MasmParser.cpp index 9cdd2eb2cc935..8b5d4b85a58b0 100644 --- a/llvm/lib/MC/MCParser/MasmParser.cpp +++ b/llvm/lib/MC/MCParser/MasmParser.cpp @@ -108,6 +108,9 @@ struct ParseStatementInfo { /// Was there an error parsing the inline assembly? bool ParseError = false; + /// The value associated with a macro exit. + Optional ExitValue; + SmallVectorImpl *AsmRewrites = nullptr; ParseStatementInfo() = delete; @@ -368,6 +371,7 @@ class MasmParser : public MCAsmParser { /// This is the current buffer index we're lexing from as managed by the /// SourceMgr object. unsigned CurBuffer; + std::vector EndStatementAtEOFStack; AsmCond TheCondState; std::vector TheCondStack; @@ -539,8 +543,6 @@ class MasmParser : public MCAsmParser { bool parseCurlyBlockScope(SmallVectorImpl& AsmStrRewrites); bool parseCppHashLineFilenameComment(SMLoc L); - void checkForBadMacro(SMLoc DirectiveLoc, StringRef Name, StringRef Body, - ArrayRef Parameters); bool expandMacro(raw_svector_ostream &OS, StringRef Body, ArrayRef Parameters, ArrayRef A, @@ -553,7 +555,15 @@ class MasmParser : public MCAsmParser { /// /// \param M The macro. /// \param NameLoc Instantiation location. - bool handleMacroEntry(const MCAsmMacro *M, SMLoc NameLoc); + bool handleMacroEntry( + const MCAsmMacro *M, SMLoc NameLoc, + AsmToken::TokenKind ArgumentEndTok = AsmToken::EndOfStatement); + + /// Handle invocation of macro function. + /// + /// \param M The macro. + /// \param NameLoc Invocation location. + bool handleMacroInvocation(const MCAsmMacro *M, SMLoc NameLoc); /// Handle exit from macro instantiation. void handleMacroExit(); @@ -593,7 +603,8 @@ class MasmParser : public MCAsmParser { /// /// \param InBuffer If not 0, should be the known buffer id that contains the /// location. - void jumpToLoc(SMLoc Loc, unsigned InBuffer = 0); + void jumpToLoc(SMLoc Loc, unsigned InBuffer = 0, + bool EndStatementAtEOF = true); /// Parse up to a token of kind \p EndTok and return the contents from the /// current token up to (but not including) this token; the current token on @@ -723,7 +734,7 @@ class MasmParser : public MCAsmParser { DK_MACRO, DK_EXITM, DK_ENDM, - DK_PURGEM, + DK_PURGE, DK_ERR, DK_ERRB, DK_ERRNB, @@ -901,7 +912,8 @@ class MasmParser : public MCAsmParser { // macro directives bool parseDirectivePurgeMacro(SMLoc DirectiveLoc); - bool parseDirectiveExitMacro(StringRef Directive); + bool parseDirectiveExitMacro(SMLoc DirectiveLoc, StringRef Directive, + std::string &Value); bool parseDirectiveEndMacro(StringRef Directive); bool parseDirectiveMacro(StringRef Name, SMLoc NameLoc); @@ -1011,6 +1023,7 @@ MasmParser::MasmParser(SourceMgr &SM, MCContext &Ctx, MCStreamer &Out, // Set our own handler which calls the saved handler. SrcMgr.setDiagHandler(DiagHandler, this); Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)->getBuffer()); + EndStatementAtEOFStack.push_back(true); // Initialize the platform / file format parser. switch (Ctx.getObjectFileInfo()->getObjectFileType()) { @@ -1080,13 +1093,15 @@ bool MasmParser::enterIncludeFile(const std::string &Filename) { CurBuffer = NewBuf; Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)->getBuffer()); + EndStatementAtEOFStack.push_back(true); return false; } -void MasmParser::jumpToLoc(SMLoc Loc, unsigned InBuffer) { +void MasmParser::jumpToLoc(SMLoc Loc, unsigned InBuffer, + bool EndStatementAtEOF) { CurBuffer = InBuffer ? InBuffer : SrcMgr.FindBufferContainingLoc(Loc); Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)->getBuffer(), - Loc.getPointer()); + Loc.getPointer(), EndStatementAtEOF); } const AsmToken &MasmParser::Lex() { @@ -1115,6 +1130,7 @@ const AsmToken &MasmParser::Lex() { getTok().getEndLoc()); Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)->getBuffer(), nullptr, /*EndStatementAtEOF=*/false); + EndStatementAtEOFStack.push_back(false); tok = &Lexer.Lex(); } else { break; @@ -1141,9 +1157,12 @@ const AsmToken &MasmParser::Lex() { // include stack. SMLoc ParentIncludeLoc = SrcMgr.getParentIncludeLoc(CurBuffer); if (ParentIncludeLoc != SMLoc()) { - jumpToLoc(ParentIncludeLoc); + EndStatementAtEOFStack.pop_back(); + jumpToLoc(ParentIncludeLoc, 0, EndStatementAtEOFStack.back()); return Lex(); } + EndStatementAtEOFStack.pop_back(); + assert(EndStatementAtEOFStack.empty()); } return *tok; @@ -1345,6 +1364,7 @@ bool MasmParser::parseBracketExpr(const MCExpr *&Res, SMLoc &EndLoc) { /// Parse a primary expression and return it. /// primaryexpr ::= (parenexpr +/// primaryexpr ::= macro_function "(" macro_arguments ")" /// primaryexpr ::= symbol /// primaryexpr ::= number /// primaryexpr ::= '.' @@ -1395,6 +1415,12 @@ bool MasmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc, Res = MCUnaryExpr::createNot(Res, getContext(), FirstTokenLoc); return false; } + // Parse macro function invocation. + if (const MCAsmMacro *M = getContext().lookupMacro(Identifier)) { + if (handleMacroInvocation(M, FirstTokenLoc)) + return true; + return parsePrimaryExpr(Res, EndLoc, nullptr); + } // Parse symbol variant. std::pair Split; if (!MAI.useParensForSymbolVariant()) { @@ -2281,10 +2307,12 @@ bool MasmParser::parseStatement(ParseStatementInfo &Info, case DK_CFI_WINDOW_SAVE: return parseDirectiveCFIWindowSave(); case DK_EXITM: - return parseDirectiveExitMacro(IDVal); + Info.ExitValue = ""; + return parseDirectiveExitMacro(IDLoc, IDVal, *Info.ExitValue); case DK_ENDM: + Info.ExitValue = ""; return parseDirectiveEndMacro(IDVal); - case DK_PURGEM: + case DK_PURGE: return parseDirectivePurgeMacro(IDLoc); case DK_END: return parseDirectiveEnd(IDLoc); @@ -2615,13 +2643,10 @@ void MasmParser::DiagHandler(const SMDiagnostic &Diag, void *Context) { NewDiag.print(nullptr, OS); } -// FIXME: This is mostly duplicated from the function in AsmLexer.cpp. The -// difference being that that function accepts '@' as part of identifiers and -// we can't do that. AsmLexer.cpp should probably be changed to handle -// '@' as a special case when needed. -static bool isIdentifierChar(char c) { - return isalnum(static_cast(c)) || c == '_' || c == '$' || - c == '.'; +// This is similar to the IsIdentifierChar function in AsmLexer.cpp, but does +// not accept '.'. +static bool isMacroParameterChar(char C) { + return isAlnum(C) || C == '_' || C == '$' || C == '@' || C == '?'; } bool MasmParser::expandMacro(raw_svector_ostream &OS, StringRef Body, @@ -2648,11 +2673,11 @@ bool MasmParser::expandMacro(raw_svector_ostream &OS, StringRef Body, std::size_t End = Body.size(), Pos = 0; std::size_t IdentifierPos = End; for (; Pos != End; ++Pos) { - // Find the next possible identifier, including identifiers preceding a - // '&' inside quotes. + // Find the next possible macro parameter, including preceding a '&' + // inside quotes. if (Body[Pos] == '&') break; - if (isIdentifierChar(Body[Pos])) { + if (isMacroParameterChar(Body[Pos])) { if (!CurrentQuote.hasValue()) break; if (IdentifierPos == End) @@ -2695,7 +2720,7 @@ bool MasmParser::expandMacro(raw_svector_ostream &OS, StringRef Body, ++I; ++Pos; } - while (isIdentifierChar(Body[I]) && I + 1 != End) + while (isMacroParameterChar(Body[I]) && I + 1 != End) ++I; const char *Begin = Body.data() + Pos; @@ -2805,7 +2830,7 @@ bool MasmParser::parseMacroArgument(const MCAsmMacroParameter *MP, if (Lexer.is(AsmToken::Less) && isAngleBracketString(StrLoc, EndLoc)) { const char *StrChar = StrLoc.getPointer() + 1; const char *EndChar = EndLoc.getPointer() - 1; - jumpToLoc(EndLoc, CurBuffer); + jumpToLoc(EndLoc, CurBuffer, EndStatementAtEOFStack.back()); /// Eat from '<' to '>'. Lex(); MA.emplace_back(AsmToken::String, StringRef(StrChar, EndChar - StrChar)); @@ -2854,7 +2879,7 @@ bool MasmParser::parseMacroArgument(const MCAsmMacroParameter *MP, // handleMacroEntry relies on not advancing the lexer here // to be able to fill in the remaining default parameter values - if (Lexer.is(EndTok)) + if (Lexer.is(EndTok) && (EndTok != AsmToken::RParen || ParenLevel == 0)) break; // Adjust the current parentheses level. @@ -2998,7 +3023,8 @@ bool MasmParser::parseMacroArguments(const MCAsmMacro *M, return TokError("too many positional arguments"); } -bool MasmParser::handleMacroEntry(const MCAsmMacro *M, SMLoc NameLoc) { +bool MasmParser::handleMacroEntry(const MCAsmMacro *M, SMLoc NameLoc, + AsmToken::TokenKind ArgumentEndTok) { // Arbitrarily limit macro nesting depth (default matches 'as'). We can // eliminate this, although we should protect against infinite loops. unsigned MaxNestingDepth = AsmMacroMaxNestingDepth; @@ -3012,7 +3038,7 @@ bool MasmParser::handleMacroEntry(const MCAsmMacro *M, SMLoc NameLoc) { } MCAsmMacroArguments A; - if (parseMacroArguments(M, A)) + if (parseMacroArguments(M, A, ArgumentEndTok)) return true; // Macro instantiation is lexical, unfortunately. We construct a new buffer @@ -3042,14 +3068,17 @@ bool MasmParser::handleMacroEntry(const MCAsmMacro *M, SMLoc NameLoc) { // Jump to the macro instantiation and prime the lexer. CurBuffer = SrcMgr.AddNewSourceBuffer(std::move(Instantiation), SMLoc()); Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)->getBuffer()); + EndStatementAtEOFStack.push_back(true); Lex(); return false; } void MasmParser::handleMacroExit() { - // Jump to the EndOfStatement we should return to, and consume it. - jumpToLoc(ActiveMacros.back()->ExitLoc, ActiveMacros.back()->ExitBuffer); + // Jump to the token we should return to, and consume it. + EndStatementAtEOFStack.pop_back(); + jumpToLoc(ActiveMacros.back()->ExitLoc, ActiveMacros.back()->ExitBuffer, + EndStatementAtEOFStack.back()); Lex(); // Pop the instantiation entry. @@ -3057,6 +3086,60 @@ void MasmParser::handleMacroExit() { ActiveMacros.pop_back(); } +bool MasmParser::handleMacroInvocation(const MCAsmMacro *M, SMLoc NameLoc) { + if (parseToken(AsmToken::LParen, "invoking macro function '" + M->Name + + "' requires arguments in parentheses") || + handleMacroEntry(M, NameLoc, AsmToken::RParen)) + return true; + + // Parse all statements in the macro, retrieving the exit value when it ends. + std::string ExitValue; + SmallVector AsmStrRewrites; + while (Lexer.isNot(AsmToken::Eof)) { + ParseStatementInfo Info(&AsmStrRewrites); + bool Parsed = parseStatement(Info, nullptr); + + if (!Parsed && Info.ExitValue.hasValue()) { + ExitValue = std::move(*Info.ExitValue); + break; + } + + // If we have a Lexer Error we are on an Error Token. Load in Lexer Error + // for printing ErrMsg via Lex() only if no (presumably better) parser error + // exists. + if (Parsed && !hasPendingError() && Lexer.getTok().is(AsmToken::Error)) { + Lex(); + } + + // parseStatement returned true so may need to emit an error. + printPendingErrors(); + + // Skipping to the next line if needed. + if (Parsed && !getLexer().isAtStartOfStatement()) + eatToEndOfStatement(); + } + + // Consume the right-parenthesis on the other side of the arguments. + if (parseToken(AsmToken::RParen, "invoking macro function '" + M->Name + + "' requires arguments in parentheses")) + return true; + + // Exit values may require lexing, unfortunately. We construct a new buffer to + // hold the exit value. + std::unique_ptr MacroValue = + MemoryBuffer::getMemBufferCopy(ExitValue, ""); + + // Jump from this location to the instantiated exit value, and prime the + // lexer. + CurBuffer = SrcMgr.AddNewSourceBuffer(std::move(MacroValue), Lexer.getLoc()); + Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)->getBuffer(), nullptr, + /*EndStatementAtEOF=*/false); + EndStatementAtEOFStack.push_back(false); + Lex(); + + return false; +} + /// parseIdentifier: /// ::= identifier /// ::= string @@ -3125,7 +3208,7 @@ bool MasmParser::parseDirectiveEquate(StringRef IDVal, StringRef Name, // Accept a text-list, not just one text-item. auto parseItem = [&]() -> bool { if (parseTextItem(Value)) - return true; + return TokError("expected text item"); Var.TextValue += Value; return false; }; @@ -3189,7 +3272,7 @@ bool MasmParser::parseAngleBracketString(std::string &Data) { if (isAngleBracketString(StartLoc, EndLoc)) { const char *StartChar = StartLoc.getPointer() + 1; const char *EndChar = EndLoc.getPointer() - 1; - jumpToLoc(EndLoc, CurBuffer); + jumpToLoc(EndLoc, CurBuffer, EndStatementAtEOFStack.back()); // Eat from '<' to '>'. Lex(); @@ -3201,8 +3284,38 @@ bool MasmParser::parseAngleBracketString(std::string &Data) { /// textItem ::= textLiteral | textMacroID | % constExpr bool MasmParser::parseTextItem(std::string &Data) { - // TODO(epastor): Support textMacroID and % expansion of expressions. - return parseAngleBracketString(Data); + switch (getTok().getKind()) { + default: + return true; + case AsmToken::Percent: { + int64_t Res; + if (parseToken(AsmToken::Percent) || parseAbsoluteExpression(Res)) + return true; + Data = std::to_string(Res); + return false; + } + case AsmToken::Less: + case AsmToken::LessEqual: + case AsmToken::LessLess: + case AsmToken::LessGreater: + return parseAngleBracketString(Data); + case AsmToken::Identifier: { + StringRef ID; + if (parseIdentifier(ID)) + return true; + + auto it = Variables.find(ID); + if (it == Variables.end()) + return true; + + const Variable &Var = it->second; + if (!Var.IsText) + return true; + Data = Var.TextValue; + return false; + } + } + llvm_unreachable("unhandled token kind"); } /// parseDirectiveAscii: @@ -5412,7 +5525,6 @@ bool MasmParser::parseDirectiveMacro(StringRef Name, SMLoc NameLoc) { const char *BodyStart = StartToken.getLoc().getPointer(); const char *BodyEnd = EndToken.getLoc().getPointer(); StringRef Body = StringRef(BodyStart, BodyEnd - BodyStart); - checkForBadMacro(NameLoc, Name, Body, Parameters); MCAsmMacro Macro(Name, Body, std::move(Parameters), std::move(Locals)); DEBUG_WITH_TYPE("asm-macros", dbgs() << "Defining new macro:\n"; Macro.dump()); @@ -5420,114 +5532,16 @@ bool MasmParser::parseDirectiveMacro(StringRef Name, SMLoc NameLoc) { return false; } -/// checkForBadMacro -/// -/// With the support added for named parameters there may be code out there that -/// is transitioning from positional parameters. In versions of gas that did -/// not support named parameters they would be ignored on the macro definition. -/// But to support both styles of parameters this is not possible so if a macro -/// definition has named parameters but does not use them and has what appears -/// to be positional parameters, strings like $1, $2, ... and $n, then issue a -/// warning that the positional parameter found in body which have no effect. -/// Hoping the developer will either remove the named parameters from the macro -/// definition so the positional parameters get used if that was what was -/// intended or change the macro to use the named parameters. It is possible -/// this warning will trigger when the none of the named parameters are used -/// and the strings like $1 are infact to simply to be passed trough unchanged. -void MasmParser::checkForBadMacro(SMLoc DirectiveLoc, StringRef Name, - StringRef Body, - ArrayRef Parameters) { - // If this macro is not defined with named parameters the warning we are - // checking for here doesn't apply. - unsigned NParameters = Parameters.size(); - if (NParameters == 0) - return; - - bool NamedParametersFound = false; - bool PositionalParametersFound = false; - - // Look at the body of the macro for use of both the named parameters and what - // are likely to be positional parameters. This is what expandMacro() is - // doing when it finds the parameters in the body. - while (!Body.empty()) { - // Scan for the next possible parameter. - std::size_t End = Body.size(), Pos = 0; - for (; Pos != End; ++Pos) { - // Check for a substitution or escape. - // This macro is defined with parameters, look for \foo, \bar, etc. - if (Body[Pos] == '\\' && Pos + 1 != End) - break; - - // This macro should have parameters, but look for $0, $1, ..., $n too. - if (Body[Pos] != '$' || Pos + 1 == End) - continue; - char Next = Body[Pos + 1]; - if (Next == '$' || Next == 'n' || - isdigit(static_cast(Next))) - break; - } - - // Check if we reached the end. - if (Pos == End) - break; - - if (Body[Pos] == '$') { - switch (Body[Pos + 1]) { - // $$ => $ - case '$': - break; - - // $n => number of arguments - case 'n': - PositionalParametersFound = true; - break; - - // $[0-9] => argument - default: { - PositionalParametersFound = true; - break; - } - } - Pos += 2; - } else { - unsigned I = Pos + 1; - while (isIdentifierChar(Body[I]) && I + 1 != End) - ++I; - - const char *Begin = Body.data() + Pos + 1; - StringRef Argument(Begin, I - (Pos + 1)); - unsigned Index = 0; - for (; Index < NParameters; ++Index) - if (Parameters[Index].Name == Argument) - break; - - if (Index == NParameters) { - if (Body[Pos + 1] == '(' && Body[Pos + 2] == ')') - Pos += 3; - else { - Pos = I; - } - } else { - NamedParametersFound = true; - Pos += 1 + Argument.size(); - } - } - // Update the scan point. - Body = Body.substr(Pos); - } - - if (!NamedParametersFound && PositionalParametersFound) - Warning(DirectiveLoc, "macro defined with named parameters which are not " - "used in macro body, possible positional parameter " - "found in body which will have no effect"); -} - /// parseDirectiveExitMacro -/// ::= exitm -bool MasmParser::parseDirectiveExitMacro(StringRef Directive) { - if (parseToken(AsmToken::EndOfStatement, - "unexpected token in '" + Directive + "' directive")) - return true; +/// ::= "exitm" [textitem] +bool MasmParser::parseDirectiveExitMacro(SMLoc DirectiveLoc, + StringRef Directive, + std::string &Value) { + SMLoc EndLoc = getTok().getLoc(); + if (getTok().isNot(AsmToken::EndOfStatement) && parseTextItem(Value)) + return Error(EndLoc, + "unable to parse text item in '" + Directive + "' directive"); + eatToEndOfStatement(); if (!isInsideMacroInstantiation()) return TokError("unexpected '" + Directive + "' in file, " @@ -5563,23 +5577,27 @@ bool MasmParser::parseDirectiveEndMacro(StringRef Directive) { } /// parseDirectivePurgeMacro -/// ::= .purgem +/// ::= purge identifier ( , identifier )* bool MasmParser::parseDirectivePurgeMacro(SMLoc DirectiveLoc) { StringRef Name; - SMLoc Loc; - if (parseTokenLoc(Loc) || - check(parseIdentifier(Name), Loc, - "expected identifier in '.purgem' directive") || - parseToken(AsmToken::EndOfStatement, - "unexpected token in '.purgem' directive")) - return true; + while (true) { + SMLoc NameLoc; + if (parseTokenLoc(NameLoc) || + check(parseIdentifier(Name), NameLoc, + "expected identifier in 'purge' directive")) + return true; + + DEBUG_WITH_TYPE("asm-macros", dbgs() + << "Un-defining macro: " << Name << "\n"); + if (!getContext().lookupMacro(Name)) + return Error(NameLoc, "macro '" + Name + "' is not defined"); + getContext().undefineMacro(Name); - if (!getContext().lookupMacro(Name)) - return Error(DirectiveLoc, "macro '" + Name + "' is not defined"); + if (!parseOptionalToken(AsmToken::Comma)) + break; + parseOptionalToken(AsmToken::EndOfStatement); + } - getContext().undefineMacro(Name); - DEBUG_WITH_TYPE("asm-macros", dbgs() - << "Un-defining macro: " << Name << "\n"); return false; } @@ -5755,7 +5773,7 @@ bool MasmParser::parseDirectiveIf(SMLoc DirectiveLoc, DirectiveKind DirKind) { } /// parseDirectiveIfb -/// ::= .ifb string +/// ::= .ifb textitem bool MasmParser::parseDirectiveIfb(SMLoc DirectiveLoc, bool ExpectBlank) { TheCondStack.push_back(TheCondState); TheCondState.TheCond = AsmCond::IfCond; @@ -5765,7 +5783,7 @@ bool MasmParser::parseDirectiveIfb(SMLoc DirectiveLoc, bool ExpectBlank) { } else { std::string Str; if (parseTextItem(Str)) - return TokError("expected string parameter for 'ifb' directive"); + return TokError("expected text item parameter for 'ifb' directive"); if (parseToken(AsmToken::EndOfStatement, "unexpected token in 'ifb' directive")) @@ -5779,14 +5797,15 @@ bool MasmParser::parseDirectiveIfb(SMLoc DirectiveLoc, bool ExpectBlank) { } /// parseDirectiveIfidn -/// ::= ifidn string1, string2 -bool MasmParser::parseDirectiveIfidn(SMLoc DirectiveLoc, bool ExpectEqual, bool CaseInsensitive) { +/// ::= ifidn textitem, textitem +bool MasmParser::parseDirectiveIfidn(SMLoc DirectiveLoc, bool ExpectEqual, + bool CaseInsensitive) { std::string String1, String2; if (parseTextItem(String1)) { if (ExpectEqual) - return TokError("expected string parameter for 'ifidn' directive"); - return TokError("expected string parameter for 'ifdif' directive"); + return TokError("expected text item parameter for 'ifidn' directive"); + return TokError("expected text item parameter for 'ifdif' directive"); } if (Lexer.isNot(AsmToken::Comma)) { @@ -5799,8 +5818,8 @@ bool MasmParser::parseDirectiveIfidn(SMLoc DirectiveLoc, bool ExpectEqual, bool if (parseTextItem(String2)) { if (ExpectEqual) - return TokError("expected string parameter for 'ifidn' directive"); - return TokError("expected string parameter for 'ifdif' directive"); + return TokError("expected text item parameter for 'ifidn' directive"); + return TokError("expected text item parameter for 'ifdif' directive"); } TheCondStack.push_back(TheCondState); @@ -5894,7 +5913,7 @@ bool MasmParser::parseDirectiveElseIf(SMLoc DirectiveLoc, } /// parseDirectiveElseIfb -/// ::= elseifb expression +/// ::= elseifb textitem bool MasmParser::parseDirectiveElseIfb(SMLoc DirectiveLoc, bool ExpectBlank) { if (TheCondState.TheCond != AsmCond::IfCond && TheCondState.TheCond != AsmCond::ElseIfCond) @@ -5910,8 +5929,11 @@ bool MasmParser::parseDirectiveElseIfb(SMLoc DirectiveLoc, bool ExpectBlank) { eatToEndOfStatement(); } else { std::string Str; - if (parseTextItem(Str)) - return TokError("expected string parameter for 'elseifb' directive"); + if (parseTextItem(Str)) { + if (ExpectBlank) + return TokError("expected text item parameter for 'elseifb' directive"); + return TokError("expected text item parameter for 'elseifnb' directive"); + } if (parseToken(AsmToken::EndOfStatement, "unexpected token in 'elseifb' directive")) @@ -5971,7 +5993,7 @@ bool MasmParser::parseDirectiveElseIfdef(SMLoc DirectiveLoc, } /// parseDirectiveElseIfidn -/// ::= elseifidn string1, string2 +/// ::= elseifidn textitem, textitem bool MasmParser::parseDirectiveElseIfidn(SMLoc DirectiveLoc, bool ExpectEqual, bool CaseInsensitive) { if (TheCondState.TheCond != AsmCond::IfCond && @@ -5991,8 +6013,9 @@ bool MasmParser::parseDirectiveElseIfidn(SMLoc DirectiveLoc, bool ExpectEqual, if (parseTextItem(String1)) { if (ExpectEqual) - return TokError("expected string parameter for 'elseifidn' directive"); - return TokError("expected string parameter for 'elseifdif' directive"); + return TokError( + "expected text item parameter for 'elseifidn' directive"); + return TokError("expected text item parameter for 'elseifdif' directive"); } if (Lexer.isNot(AsmToken::Comma)) { @@ -6006,8 +6029,9 @@ bool MasmParser::parseDirectiveElseIfidn(SMLoc DirectiveLoc, bool ExpectEqual, if (parseTextItem(String2)) { if (ExpectEqual) - return TokError("expected string parameter for 'elseifidn' directive"); - return TokError("expected string parameter for 'elseifdif' directive"); + return TokError( + "expected text item parameter for 'elseifidn' directive"); + return TokError("expected text item parameter for 'elseifdif' directive"); } if (CaseInsensitive) @@ -6145,7 +6169,7 @@ bool MasmParser::parseDirectiveErrorIfdef(SMLoc DirectiveLoc, } /// parseDirectiveErrorIfidn -/// ::= .erridn textitem1, textitem2[, message] +/// ::= .erridn textitem, textitem[, message] bool MasmParser::parseDirectiveErrorIfidn(SMLoc DirectiveLoc, bool ExpectEqual, bool CaseInsensitive) { if (!TheCondStack.empty()) { @@ -6341,7 +6365,7 @@ void MasmParser::initializeDirectiveKindMap() { DirectiveKindMap["macro"] = DK_MACRO; DirectiveKindMap["exitm"] = DK_EXITM; DirectiveKindMap["endm"] = DK_ENDM; - // DirectiveKindMap[".purgem"] = DK_PURGEM; + DirectiveKindMap["purge"] = DK_PURGE; DirectiveKindMap[".err"] = DK_ERR; DirectiveKindMap[".errb"] = DK_ERRB; DirectiveKindMap[".errnb"] = DK_ERRNB; @@ -6452,6 +6476,7 @@ void MasmParser::instantiateMacroLikeBody(MCAsmMacro *M, SMLoc DirectiveLoc, // Jump to the macro instantiation and prime the lexer. CurBuffer = SrcMgr.AddNewSourceBuffer(std::move(Instantiation), SMLoc()); Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)->getBuffer()); + EndStatementAtEOFStack.push_back(true); Lex(); } diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp index e4216c429d8a9..0f1133898178b 100644 --- a/llvm/lib/MC/MCStreamer.cpp +++ b/llvm/lib/MC/MCStreamer.cpp @@ -90,7 +90,7 @@ void MCTargetStreamer::emitAssignment(MCSymbol *Symbol, const MCExpr *Value) {} MCStreamer::MCStreamer(MCContext &Ctx) : Context(Ctx), CurrentWinFrameInfo(nullptr), - UseAssemblerInfoForParsing(false) { + CurrentProcWinFrameInfoStartIndex(0), UseAssemblerInfoForParsing(false) { SectionStack.push_back(std::pair()); } @@ -692,6 +692,7 @@ void MCStreamer::EmitWinCFIStartProc(const MCSymbol *Symbol, SMLoc Loc) { MCSymbol *StartProc = emitCFILabel(); + CurrentProcWinFrameInfoStartIndex = WinFrameInfos.size(); WinFrameInfos.emplace_back( std::make_unique(Symbol, StartProc)); CurrentWinFrameInfo = WinFrameInfos.back().get(); @@ -709,6 +710,11 @@ void MCStreamer::EmitWinCFIEndProc(SMLoc Loc) { CurFrame->End = Label; if (!CurFrame->FuncletOrFuncEnd) CurFrame->FuncletOrFuncEnd = CurFrame->End; + + for (size_t I = CurrentProcWinFrameInfoStartIndex, E = WinFrameInfos.size(); + I != E; ++I) + EmitWindowsUnwindTables(WinFrameInfos[I].get()); + SwitchSection(CurFrame->TextSection); } void MCStreamer::EmitWinCFIFuncletOrFuncEnd(SMLoc Loc) { @@ -967,6 +973,9 @@ void MCStreamer::emitRawText(const Twine &T) { void MCStreamer::EmitWindowsUnwindTables() { } +void MCStreamer::EmitWindowsUnwindTables(WinEH::FrameInfo *Frame) { +} + void MCStreamer::Finish(SMLoc EndLoc) { if ((!DwarfFrameInfos.empty() && !DwarfFrameInfos.back().End) || (!WinFrameInfos.empty() && !WinFrameInfos.back()->End)) { diff --git a/llvm/lib/MC/MCWin64EH.cpp b/llvm/lib/MC/MCWin64EH.cpp index ffc2ed9a3fb6f..de1b0fd3c7424 100644 --- a/llvm/lib/MC/MCWin64EH.cpp +++ b/llvm/lib/MC/MCWin64EH.cpp @@ -238,8 +238,9 @@ void llvm::Win64EH::UnwindEmitter::Emit(MCStreamer &Streamer) const { } } -void llvm::Win64EH::UnwindEmitter::EmitUnwindInfo( - MCStreamer &Streamer, WinEH::FrameInfo *info) const { +void llvm::Win64EH::UnwindEmitter::EmitUnwindInfo(MCStreamer &Streamer, + WinEH::FrameInfo *info, + bool HandlerData) const { // Switch sections (the static function above is meant to be called from // here and from Emit(). MCSection *XData = Streamer.getAssociatedXDataSection(info->TextSection); @@ -1107,8 +1108,9 @@ void llvm::Win64EH::ARM64UnwindEmitter::Emit(MCStreamer &Streamer) const { } } -void llvm::Win64EH::ARM64UnwindEmitter::EmitUnwindInfo( - MCStreamer &Streamer, WinEH::FrameInfo *info) const { +void llvm::Win64EH::ARM64UnwindEmitter::EmitUnwindInfo(MCStreamer &Streamer, + WinEH::FrameInfo *info, + bool HandlerData) const { // Called if there's an .seh_handlerdata directive before the end of the // function. This forces writing the xdata record already here - and // in this case, the function isn't actually ended already, but the xdata @@ -1123,5 +1125,5 @@ void llvm::Win64EH::ARM64UnwindEmitter::EmitUnwindInfo( // here and from Emit(). MCSection *XData = Streamer.getAssociatedXDataSection(info->TextSection); Streamer.SwitchSection(XData); - ARM64EmitUnwindInfo(Streamer, info, false); + ARM64EmitUnwindInfo(Streamer, info, /* TryPacked = */ !HandlerData); } diff --git a/llvm/lib/MC/WasmObjectWriter.cpp b/llvm/lib/MC/WasmObjectWriter.cpp index 0cf6e310ae322..a05d4c9930894 100644 --- a/llvm/lib/MC/WasmObjectWriter.cpp +++ b/llvm/lib/MC/WasmObjectWriter.cpp @@ -40,8 +40,8 @@ using namespace llvm; namespace { -// Went we ceate the indirect function table we start at 1, so that there is -// and emtpy slot at 0 and therefore calling a null function pointer will trap. +// When we create the indirect function table we start at 1, so that there is +// and empty slot at 0 and therefore calling a null function pointer will trap. static const uint32_t InitialTableOffset = 1; // For patching purposes, we need to remember where each section starts, both @@ -218,9 +218,7 @@ class WasmObjectWriter : public MCObjectWriter { SmallVector DataSegments; unsigned NumFunctionImports = 0; unsigned NumGlobalImports = 0; - // NumTableImports is initialized to 1 to account for the hardcoded import of - // __indirect_function_table - unsigned NumTableImports = 1; + unsigned NumTableImports = 0; unsigned NumEventImports = 0; uint32_t SectionCount = 0; @@ -270,7 +268,7 @@ class WasmObjectWriter : public MCObjectWriter { SectionFunctions.clear(); NumFunctionImports = 0; NumGlobalImports = 0; - NumTableImports = 1; + NumTableImports = 0; MCObjectWriter::reset(); } @@ -497,6 +495,29 @@ void WasmObjectWriter::recordRelocation(MCAssembler &Asm, SymA = cast(SectionSymbol); } + if (Type == wasm::R_WASM_TABLE_INDEX_REL_SLEB || + Type == wasm::R_WASM_TABLE_INDEX_SLEB || + Type == wasm::R_WASM_TABLE_INDEX_SLEB64 || + Type == wasm::R_WASM_TABLE_INDEX_I32 || + Type == wasm::R_WASM_TABLE_INDEX_I64) { + // TABLE_INDEX relocs implicitly use the default indirect function table. + auto TableName = "__indirect_function_table"; + MCSymbolWasm *Sym = cast_or_null(Ctx.lookupSymbol(TableName)); + if (Sym) { + if (!Sym->isFunctionTable()) + Ctx.reportError( + Fixup.getLoc(), + "symbol '__indirect_function_table' is not a function table"); + } else { + Sym = cast(Ctx.getOrCreateSymbol(TableName)); + Sym->setFunctionTable(); + // The default function table is synthesized by the linker. + Sym->setUndefined(); + } + Sym->setUsedInReloc(); + Asm.registerSymbol(*Sym); + } + // Relocation other than R_WASM_TYPE_INDEX_LEB are required to be // against a named symbol. if (Type != wasm::R_WASM_TYPE_INDEX_LEB) { @@ -848,11 +869,11 @@ void WasmObjectWriter::writeTableSection(ArrayRef Tables) { encodeULEB128(Tables.size(), W->OS); for (const wasm::WasmTable &Table : Tables) { - encodeULEB128(Table.ElemType, W->OS); - encodeULEB128(Table.Limits.Flags, W->OS); - encodeULEB128(Table.Limits.Initial, W->OS); - if (Table.Limits.Flags & wasm::WASM_LIMITS_FLAG_HAS_MAX) - encodeULEB128(Table.Limits.Maximum, W->OS); + encodeULEB128(Table.Type.ElemType, W->OS); + encodeULEB128(Table.Type.Limits.Flags, W->OS); + encodeULEB128(Table.Type.Limits.Initial, W->OS); + if (Table.Type.Limits.Flags & wasm::WASM_LIMITS_FLAG_HAS_MAX) + encodeULEB128(Table.Type.Limits.Maximum, W->OS); } endSection(Section); } @@ -1201,16 +1222,6 @@ void WasmObjectWriter::prepareImports( : wasm::WASM_LIMITS_FLAG_NONE; Imports.push_back(MemImport); - // For now, always emit the table section, since indirect calls are not - // valid without it. In the future, we could perhaps be more clever and omit - // it if there are no indirect calls. - wasm::WasmImport TableImport; - TableImport.Module = "env"; - TableImport.Field = "__indirect_function_table"; - TableImport.Kind = wasm::WASM_EXTERNAL_TABLE; - TableImport.Table.ElemType = wasm::WASM_TYPE_FUNCREF; - Imports.push_back(TableImport); - // Populate SignatureIndices, and Imports and WasmIndices for undefined // symbols. This must be done before populating WasmIndices for defined // symbols. @@ -1269,6 +1280,23 @@ void WasmObjectWriter::prepareImports( Imports.push_back(Import); assert(WasmIndices.count(&WS) == 0); WasmIndices[&WS] = NumEventImports++; + } else if (WS.isTable()) { + if (WS.isWeak()) + report_fatal_error("undefined table symbol cannot be weak"); + + wasm::WasmImport Import; + Import.Module = WS.getImportModule(); + Import.Field = WS.getImportName(); + Import.Kind = wasm::WASM_EXTERNAL_TABLE; + wasm::ValType ElemType = WS.getTableType(); + Import.Table.ElemType = uint8_t(ElemType); + // FIXME: Extend table type to include limits? For now we don't specify + // a min or max which does not place any restrictions on the size of the + // imported table. + Import.Table.Limits = {wasm::WASM_LIMITS_FLAG_NONE, 0, 0}; + Imports.push_back(Import); + assert(WasmIndices.count(&WS) == 0); + WasmIndices[&WS] = NumTableImports++; } } } @@ -1527,10 +1555,10 @@ uint64_t WasmObjectWriter::writeOneObject(MCAssembler &Asm, if (WS.isDefined()) { assert(WasmIndices.count(&WS) == 0); wasm::WasmTable Table; - Table.ElemType = static_cast(WS.getTableType()); Table.Index = NumTableImports + Tables.size(); + Table.Type.ElemType = static_cast(WS.getTableType()); // FIXME: Work on custom limits is ongoing - Table.Limits = {wasm::WASM_LIMITS_FLAG_NONE, 0, 0}; + Table.Type.Limits = {wasm::WASM_LIMITS_FLAG_NONE, 0, 0}; WasmIndices[&WS] = Table.Index; Tables.push_back(Table); @@ -1618,6 +1646,10 @@ uint64_t WasmObjectWriter::writeOneObject(MCAssembler &Asm, WS.setIndex(InvalidIndex); continue; } + if (WS.isTable() && WS.getName() == "__indirect_function_table") { + // For the moment, don't emit table symbols -- wasm-ld can't handle them. + continue; + } LLVM_DEBUG(dbgs() << "adding to symtab: " << WS << "\n"); uint32_t Flags = 0; diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp index dd3ce5d2c49e7..2bad136017186 100644 --- a/llvm/lib/MCA/InstrBuilder.cpp +++ b/llvm/lib/MCA/InstrBuilder.cpp @@ -259,8 +259,9 @@ void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI, // the opcode descriptor (MCInstrDesc). // 2. Uses start at index #(MCDesc.getNumDefs()). // 3. There can only be a single optional register definition, an it is - // always the last operand of the sequence (excluding extra operands - // contributed by variadic opcodes). + // either the last operand of the sequence (excluding extra operands + // contributed by variadic opcodes) or one of the explicit register + // definitions. The latter occurs for some Thumb1 instructions. // // These assumptions work quite well for most out-of-order in-tree targets // like x86. This is mainly because the vast majority of instructions is @@ -308,12 +309,18 @@ void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI, // The first NumExplicitDefs register operands are expected to be register // definitions. unsigned CurrentDef = 0; + unsigned OptionalDefIdx = MCDesc.getNumOperands() - 1; unsigned i = 0; for (; i < MCI.getNumOperands() && CurrentDef < NumExplicitDefs; ++i) { const MCOperand &Op = MCI.getOperand(i); if (!Op.isReg()) continue; + if (MCDesc.OpInfo[CurrentDef].isOptionalDef()) { + OptionalDefIdx = CurrentDef++; + continue; + } + WriteDescriptor &Write = ID.Writes[CurrentDef]; Write.OpIndex = i; if (CurrentDef < NumWriteLatencyEntries) { @@ -369,7 +376,7 @@ void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI, if (MCDesc.hasOptionalDef()) { WriteDescriptor &Write = ID.Writes[NumExplicitDefs + NumImplicitDefs]; - Write.OpIndex = MCDesc.getNumOperands() - 1; + Write.OpIndex = OptionalDefIdx; // Assign a default latency for this write. Write.Latency = ID.MaxLatency; Write.SClassOrWriteResourceID = 0; diff --git a/llvm/lib/Object/WasmObjectFile.cpp b/llvm/lib/Object/WasmObjectFile.cpp index 2504fda1a8cb3..eb1f3983b578c 100644 --- a/llvm/lib/Object/WasmObjectFile.cpp +++ b/llvm/lib/Object/WasmObjectFile.cpp @@ -214,12 +214,11 @@ static wasm::WasmLimits readLimits(WasmObjectFile::ReadContext &Ctx) { return Result; } -static wasm::WasmTable readTable(WasmObjectFile::ReadContext &Ctx) { - wasm::WasmTable Table; - Table.ElemType = readUint8(Ctx); - Table.Limits = readLimits(Ctx); - // The caller needs to set Table.Index field for Table - return Table; +static wasm::WasmTableType readTableType(WasmObjectFile::ReadContext &Ctx) { + wasm::WasmTableType TableType; + TableType.ElemType = readUint8(Ctx); + TableType.Limits = readLimits(Ctx); + return TableType; } static Error readSection(WasmSection &Section, WasmObjectFile::ReadContext &Ctx, @@ -499,9 +498,11 @@ Error WasmObjectFile::parseLinkingSectionSymtab(ReadContext &Ctx) { std::vector ImportedGlobals; std::vector ImportedFunctions; std::vector ImportedEvents; + std::vector ImportedTables; ImportedGlobals.reserve(Imports.size()); ImportedFunctions.reserve(Imports.size()); ImportedEvents.reserve(Imports.size()); + ImportedTables.reserve(Imports.size()); for (auto &I : Imports) { if (I.Kind == wasm::WASM_EXTERNAL_FUNCTION) ImportedFunctions.emplace_back(&I); @@ -509,6 +510,8 @@ Error WasmObjectFile::parseLinkingSectionSymtab(ReadContext &Ctx) { ImportedGlobals.emplace_back(&I); else if (I.Kind == wasm::WASM_EXTERNAL_EVENT) ImportedEvents.emplace_back(&I); + else if (I.Kind == wasm::WASM_EXTERNAL_TABLE) + ImportedTables.emplace_back(&I); } while (Count--) { @@ -597,10 +600,22 @@ Error WasmObjectFile::parseLinkingSectionSymtab(ReadContext &Ctx) { Info.Name = readString(Ctx); unsigned TableIndex = Info.ElementIndex - NumImportedTables; wasm::WasmTable &Table = Tables[TableIndex]; - TableType = Table.ElemType; + TableType = Table.Type.ElemType; + if (Table.SymbolName.empty()) + Table.SymbolName = Info.Name; } else { - return make_error("undefined table symbol", - object_error::parse_failed); + wasm::WasmImport &Import = *ImportedTables[Info.ElementIndex]; + if ((Info.Flags & wasm::WASM_SYMBOL_EXPLICIT_NAME) != 0) { + Info.Name = readString(Ctx); + Info.ImportName = Import.Field; + } else { + Info.Name = Import.Field; + } + TableType = Import.Table.ElemType; + // FIXME: Parse limits here too. + if (!Import.Module.empty()) { + Info.ImportModule = Import.Module; + } } break; @@ -1014,8 +1029,7 @@ Error WasmObjectFile::parseImportSection(ReadContext &Ctx) { HasMemory64 = true; break; case wasm::WASM_EXTERNAL_TABLE: { - Im.Table = readTable(Ctx); - Im.Table.Index = NumImportedTables + Tables.size(); + Im.Table = readTableType(Ctx); NumImportedTables++; auto ElemType = Im.Table.ElemType; if (ElemType != wasm::WASM_TYPE_FUNCREF && @@ -1060,13 +1074,15 @@ Error WasmObjectFile::parseFunctionSection(ReadContext &Ctx) { } Error WasmObjectFile::parseTableSection(ReadContext &Ctx) { + TableSection = Sections.size(); uint32_t Count = readVaruint32(Ctx); Tables.reserve(Count); while (Count--) { - wasm::WasmTable T = readTable(Ctx); + wasm::WasmTable T; + T.Type = readTableType(Ctx); T.Index = NumImportedTables + Tables.size(); Tables.push_back(T); - auto ElemType = Tables.back().ElemType; + auto ElemType = Tables.back().Type.ElemType; if (ElemType != wasm::WASM_TYPE_FUNCREF && ElemType != wasm::WASM_TYPE_EXTERNREF) { return make_error("Invalid table element type", @@ -1431,6 +1447,7 @@ uint64_t WasmObjectFile::getWasmSymbolValue(const WasmSymbol &Sym) const { case wasm::WASM_SYMBOL_TYPE_FUNCTION: case wasm::WASM_SYMBOL_TYPE_GLOBAL: case wasm::WASM_SYMBOL_TYPE_EVENT: + case wasm::WASM_SYMBOL_TYPE_TABLE: return Sym.Info.ElementIndex; case wasm::WASM_SYMBOL_TYPE_DATA: { // The value of a data symbol is the segment offset, plus the symbol @@ -1480,6 +1497,8 @@ WasmObjectFile::getSymbolType(DataRefImpl Symb) const { return SymbolRef::ST_Debug; case wasm::WASM_SYMBOL_TYPE_EVENT: return SymbolRef::ST_Other; + case wasm::WASM_SYMBOL_TYPE_TABLE: + return SymbolRef::ST_Other; } llvm_unreachable("Unknown WasmSymbol::SymbolType"); @@ -1514,6 +1533,8 @@ uint32_t WasmObjectFile::getSymbolSectionIdImpl(const WasmSymbol &Sym) const { return Sym.Info.ElementIndex; case wasm::WASM_SYMBOL_TYPE_EVENT: return EventSection; + case wasm::WASM_SYMBOL_TYPE_TABLE: + return TableSection; default: llvm_unreachable("Unknown WasmSymbol::SymbolType"); } diff --git a/llvm/lib/Object/XCOFFObjectFile.cpp b/llvm/lib/Object/XCOFFObjectFile.cpp index 9c4f97d0a5e95..1a8afe4c95a4b 100644 --- a/llvm/lib/Object/XCOFFObjectFile.cpp +++ b/llvm/lib/Object/XCOFFObjectFile.cpp @@ -1133,7 +1133,7 @@ bool XCOFFTracebackTable::hasVectorInfo() const { return GETBITWITHMASK(4, HasVectorInfoMask); } -uint8_t XCOFFTracebackTable::getNumofGPRsSaved() const { +uint8_t XCOFFTracebackTable::getNumOfGPRsSaved() const { return GETBITWITHMASKSHIFT(4, GPRSavedMask, GPRSavedShift); } diff --git a/llvm/lib/ObjectYAML/ELFEmitter.cpp b/llvm/lib/ObjectYAML/ELFEmitter.cpp index b31b7681adad1..b8386bd46be26 100644 --- a/llvm/lib/ObjectYAML/ELFEmitter.cpp +++ b/llvm/lib/ObjectYAML/ELFEmitter.cpp @@ -1135,8 +1135,8 @@ void ELFState::setProgramHeaderLayout(std::vector &PHeaders, } } -static bool shouldAllocateFileSpace(ArrayRef Phdrs, - const ELFYAML::NoBitsSection &S) { +bool llvm::ELFYAML::shouldAllocateFileSpace( + ArrayRef Phdrs, const ELFYAML::NoBitsSection &S) { for (const ELFYAML::ProgramHeader &PH : Phdrs) { auto It = llvm::find_if( PH.Chunks, [&](ELFYAML::Chunk *C) { return C->Name == S.Name; }); diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index de8108f7d65b6..2a9b0c1e4f6ba 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -47,6 +47,7 @@ #include "llvm/Analysis/LoopCacheAnalysis.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/LoopNestAnalysis.h" +#include "llvm/Analysis/MemDerefPrinter.h" #include "llvm/Analysis/MemoryDependenceAnalysis.h" #include "llvm/Analysis/MemorySSA.h" #include "llvm/Analysis/ModuleDebugInfoPrinter.h" @@ -232,26 +233,7 @@ using namespace llvm; -static cl::opt MaxDevirtIterations("pm-max-devirt-iterations", - cl::ReallyHidden, cl::init(4)); -static cl::opt - RunPartialInlining("enable-npm-partial-inlining", cl::init(false), - cl::Hidden, cl::ZeroOrMore, - cl::desc("Run Partial inlinining pass")); - -static cl::opt PreInlineThreshold( - "npm-preinline-threshold", cl::Hidden, cl::init(75), cl::ZeroOrMore, - cl::desc("Control the amount of inlining in pre-instrumentation inliner " - "(default = 75)")); - -static cl::opt - RunNewGVN("enable-npm-newgvn", cl::init(false), - cl::Hidden, cl::ZeroOrMore, - cl::desc("Run NewGVN instead of GVN")); - -static cl::opt EnableGVNHoist( - "enable-npm-gvn-hoist", cl::init(false), cl::Hidden, - cl::desc("Enable the GVN hoisting pass for the new PM (default = off)")); +extern cl::opt MaxDevirtIterations; static cl::opt UseInlineAdvisor( "enable-ml-inliner", cl::init(InliningAdvisorMode::Default), cl::Hidden, @@ -263,18 +245,6 @@ static cl::opt UseInlineAdvisor( clEnumValN(InliningAdvisorMode::Release, "release", "Use release mode (AOT-compiled model)."))); -static cl::opt EnableGVNSink( - "enable-npm-gvn-sink", cl::init(false), cl::Hidden, - cl::desc("Enable the GVN hoisting pass for the new PM (default = off)")); - -static cl::opt EnableUnrollAndJam( - "enable-npm-unroll-and-jam", cl::init(false), cl::Hidden, - cl::desc("Enable the Unroll and Jam pass for the new PM (default = off)")); - -static cl::opt EnableLoopFlatten( - "enable-npm-loop-flatten", cl::init(false), cl::Hidden, - cl::desc("Enable the Loop flattening pass for the new PM (default = off)")); - static cl::opt EnableSyntheticCounts( "enable-npm-synthetic-counts", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Run synthetic function entry count generation " @@ -283,12 +253,6 @@ static cl::opt EnableSyntheticCounts( static const Regex DefaultAliasRegex( "^(default|thinlto-pre-link|thinlto|lto-pre-link|lto)<(O[0123sz])>$"); -// This option is used in simplifying testing SampleFDO optimizations for -// profile loading. -static cl::opt - EnableCHR("enable-chr-npm", cl::init(true), cl::Hidden, - cl::desc("Enable control height reduction optimization (CHR)")); - /// Flag to enable inline deferral during PGO. static cl::opt EnablePGOInlineDeferral("enable-npm-pgo-inline-deferral", cl::init(true), @@ -312,8 +276,15 @@ PipelineTuningOptions::PipelineTuningOptions() { } extern cl::opt EnableConstraintElimination; +extern cl::opt EnableGVNHoist; +extern cl::opt EnableGVNSink; extern cl::opt EnableHotColdSplit; extern cl::opt EnableOrderFileInstrumentation; +extern cl::opt EnableCHR; +extern cl::opt EnableUnrollAndJam; +extern cl::opt EnableLoopFlatten; +extern cl::opt RunNewGVN; +extern cl::opt RunPartialInlining; extern cl::opt FlattenedProfileUsed; @@ -323,6 +294,7 @@ extern cl::opt EnableKnowledgeRetention; extern cl::opt EnableMatrix; extern cl::opt DisablePreInliner; +extern cl::opt PreInlineThreshold; const PassBuilder::OptimizationLevel PassBuilder::OptimizationLevel::O0 = { /*SpeedLevel*/ 0, @@ -549,8 +521,8 @@ PassBuilder::buildO1FunctionSimplificationPipeline(OptimizationLevel Level, if (EnableLoopFlatten) FPM.addPass(LoopFlattenPass()); - LPM2.addPass(IndVarSimplifyPass()); LPM2.addPass(LoopIdiomRecognizePass()); + LPM2.addPass(IndVarSimplifyPass()); for (auto &C : LateLoopOptimizationsEPCallbacks) C(LPM2, Level); @@ -710,8 +682,8 @@ PassBuilder::buildFunctionSimplificationPipeline(OptimizationLevel Level, // TODO: Investigate promotion cap for O1. LPM1.addPass(LICMPass(PTO.LicmMssaOptCap, PTO.LicmMssaNoAccForPromotionCap)); LPM1.addPass(SimpleLoopUnswitchPass()); - LPM2.addPass(IndVarSimplifyPass()); LPM2.addPass(LoopIdiomRecognizePass()); + LPM2.addPass(IndVarSimplifyPass()); for (auto &C : LateLoopOptimizationsEPCallbacks) C(LPM2, Level); @@ -740,7 +712,7 @@ PassBuilder::buildFunctionSimplificationPipeline(OptimizationLevel Level, DebugLogging)); FPM.addPass(SimplifyCFGPass()); FPM.addPass(InstCombinePass()); - // The loop passes in LPM2 (IndVarSimplifyPass, LoopIdiomRecognizePass, + // The loop passes in LPM2 (LoopIdiomRecognizePass, IndVarSimplifyPass, // LoopDeletionPass and LoopFullUnrollPass) do not preserve MemorySSA. // *All* loop passes must preserve it, in order to be able to use it. FPM.addPass(createFunctionToLoopPassAdaptor( @@ -1060,6 +1032,9 @@ PassBuilder::buildModuleSimplificationPipeline(OptimizationLevel Level, if (Phase == ThinLTOPhase::PostLink) MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, true)); + for (auto &C : PipelineEarlySimplificationEPCallbacks) + C(MPM, Level); + // Interprocedural constant propagation now that basic cleanup has occurred // and prior to optimizing globals. // FIXME: This position in the pipeline hasn't been carefully considered in @@ -1731,6 +1706,8 @@ ModulePassManager PassBuilder::buildO0DefaultPipeline(OptimizationLevel Level, for (auto &C : PipelineStartEPCallbacks) C(MPM, Level); + for (auto &C : PipelineEarlySimplificationEPCallbacks) + C(MPM, Level); // Build a minimal pipeline based on the semantics required by LLVM, // which is just that always inlining occurs. Further, disable generating @@ -1843,7 +1820,7 @@ static Optional parseDevirtPassName(StringRef Name) { if (!Name.consume_front("devirt<") || !Name.consume_back(">")) return None; int Count; - if (Name.getAsInteger(0, Count) || Count <= 0) + if (Name.getAsInteger(0, Count) || Count < 0) return None; return Count; } diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index c761945e6768e..7f0f51ad09773 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -286,6 +286,7 @@ FUNCTION_PASS("print", StackSafetyPrinterPass(dbgs())) FUNCTION_PASS("print-alias-sets", AliasSetsPrinterPass(dbgs())) FUNCTION_PASS("print-predicateinfo", PredicateInfoPrinterPass(dbgs())) FUNCTION_PASS("print-mustexecute", MustExecutePrinterPass(dbgs())) +FUNCTION_PASS("print-memderefs", MemDerefPrinterPass(dbgs())) FUNCTION_PASS("reassociate", ReassociatePass()) FUNCTION_PASS("redundant-dbg-inst-elim", RedundantDbgInstEliminationPass()) FUNCTION_PASS("reg2mem", RegToMemPass()) diff --git a/llvm/lib/Support/APInt.cpp b/llvm/lib/Support/APInt.cpp index fc339de45af43..12ceb2df112ee 100644 --- a/llvm/lib/Support/APInt.cpp +++ b/llvm/lib/Support/APInt.cpp @@ -961,6 +961,12 @@ APInt APInt::sextOrTrunc(unsigned width) const { return *this; } +APInt APInt::truncOrSelf(unsigned width) const { + if (BitWidth > width) + return trunc(width); + return *this; +} + APInt APInt::zextOrSelf(unsigned width) const { if (BitWidth < width) return zext(width); diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp index f8413d703358a..4fb93928ff156 100644 --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp @@ -208,6 +208,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { .Case("0xd41", "cortex-a78") .Case("0xd44", "cortex-x1") .Case("0xd0c", "neoverse-n1") + .Case("0xd49", "neoverse-n2") .Default("generic"); } diff --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp index 43b906ea22481..a8f0e19a2bbd7 100644 --- a/llvm/lib/TableGen/Record.cpp +++ b/llvm/lib/TableGen/Record.cpp @@ -514,20 +514,13 @@ IntInit::convertInitializerBitRange(ArrayRef Bits) const { return BitsInit::get(NewBits); } -CodeInit *CodeInit::get(StringRef V, const SMLoc &Loc) { - static StringSet ThePool(Allocator); +CodeInit *CodeInit::get(StringRef V) { + static StringMap ThePool(Allocator); - CodeInitsConstructed++; - - // Unlike StringMap, StringSet doesn't accept empty keys. - if (V.empty()) - return new (Allocator) CodeInit("", Loc); - - // Location tracking prevents us from de-duping CodeInits as we're never - // called with the same string and same location twice. However, we can at - // least de-dupe the strings for a modest saving. - auto &Entry = *ThePool.insert(V).first; - return new(Allocator) CodeInit(Entry.getKey(), Loc); + auto &Entry = *ThePool.insert(std::make_pair(V, nullptr)).first; + if (!Entry.second) + Entry.second = new(Allocator) CodeInit(Entry.getKey()); + return Entry.second; } StringInit *StringInit::get(StringRef V) { @@ -543,7 +536,7 @@ Init *StringInit::convertInitializerTo(RecTy *Ty) const { if (isa(Ty)) return const_cast(this); if (isa(Ty)) - return CodeInit::get(getValue(), SMLoc()); + return CodeInit::get(getValue()); return nullptr; } @@ -1046,8 +1039,6 @@ Init *BinOpInit::Fold(Record *CurRec) const { default: llvm_unreachable("unhandled comparison"); } return BitInit::get(Result); -//// bool Equal = LHSs->getValue() == RHSs->getValue(); -//// return BitInit::get(getOpcode() == EQ ? Equal : !Equal); } // Finally, !eq and !ne can be used with records. @@ -2170,7 +2161,7 @@ bool RecordVal::setValue(Init *V) { return false; } -// This version of setValue takes an source location and resets the +// This version of setValue takes a source location and resets the // location in the RecordVal. bool RecordVal::setValue(Init *V, SMLoc NewLoc) { Loc = NewLoc; @@ -2351,6 +2342,14 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, const Record &R) { return OS << "}\n"; } +SMLoc Record::getFieldLoc(StringRef FieldName) const { + const RecordVal *R = getValue(FieldName); + if (!R) + PrintFatalError(getLoc(), "Record `" + getName() + + "' does not have a field named `" + FieldName + "'!\n"); + return R->getLoc(); +} + Init *Record::getValueInit(StringRef FieldName) const { const RecordVal *R = getValue(FieldName); if (!R || !R->getValue()) diff --git a/llvm/lib/TableGen/TGParser.cpp b/llvm/lib/TableGen/TGParser.cpp index 90b5afa0e82ef..5c9cba5bc9263 100644 --- a/llvm/lib/TableGen/TGParser.cpp +++ b/llvm/lib/TableGen/TGParser.cpp @@ -1920,7 +1920,7 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType, break; } case tgtok::CodeFragment: - R = CodeInit::get(Lex.getCurStrVal(), Lex.getLoc()); + R = CodeInit::get(Lex.getCurStrVal()); Lex.Lex(); break; case tgtok::question: diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 2e33801ddc4a9..aa10ec54cf2b2 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -903,6 +903,18 @@ def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", FeatureSSBS, ]>; +def ProcNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", + "NeoverseN2", + "Neoverse N2 ARM processors", [ + HasV8_5aOps, + FeatureBF16, + FeatureETE, + FeatureMatMulInt8, + FeatureMTE, + FeatureSVE2, + FeatureSVE2BitPerm, + FeatureTRBE]>; + def ProcNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1", "Neoverse V1 ARM processors", [ @@ -1064,6 +1076,7 @@ def : ProcessorModel<"cortex-r82", CortexA55Model, [ProcR82]>; def : ProcessorModel<"cortex-x1", CortexA57Model, [ProcX1]>; def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>; def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>; +def : ProcessorModel<"neoverse-n2", CortexA57Model, [ProcNeoverseN2]>; def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>; def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>; def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>; diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp index d9504072f8c2b..c18e9a4e6db14 100644 --- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -320,6 +320,7 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) { assert(TT.isOSBinFormatELF()); std::unique_ptr STI( TM.getTarget().createMCSubtargetInfo(TT.str(), "", "")); + assert(STI && "Unable to create subtarget info"); MCSymbol *HwasanTagMismatchV1Sym = OutContext.getOrCreateSymbol("__hwasan_tag_mismatch"); diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index 351f532ad4a37..cbbb0755b1240 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1649,7 +1649,7 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF, // If the prologue didn't contain any SEH opcodes and didn't set the // MF.hasWinCFI() flag, assume the epilogue won't either, and skip the // EpilogStart - to avoid generating CFI for functions that don't need it. - // (And as we didn't generate any prologue at all, it would be assymetrical + // (And as we didn't generate any prologue at all, it would be asymmetrical // to the epilogue.) By the end of the function, we assert that // HasWinCFI is equal to MF.hasWinCFI(), to verify this assumption. HasWinCFI = true; diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index b92eb1d0e4f6e..e4c20cc4e6e3e 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -835,6 +835,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, if (Subtarget->supportsAddressTopByteIgnored()) setTargetDAGCombine(ISD::LOAD); + setTargetDAGCombine(ISD::MSCATTER); + setTargetDAGCombine(ISD::MUL); setTargetDAGCombine(ISD::SELECT); @@ -13944,6 +13946,44 @@ static SDValue performSTORECombine(SDNode *N, return SDValue(); } +static SDValue performMSCATTERCombine(SDNode *N, + TargetLowering::DAGCombinerInfo &DCI, + SelectionDAG &DAG) { + MaskedScatterSDNode *MSC = cast(N); + assert(MSC && "Can only combine scatter store nodes"); + + SDLoc DL(MSC); + SDValue Chain = MSC->getChain(); + SDValue Scale = MSC->getScale(); + SDValue Index = MSC->getIndex(); + SDValue Data = MSC->getValue(); + SDValue Mask = MSC->getMask(); + SDValue BasePtr = MSC->getBasePtr(); + ISD::MemIndexType IndexType = MSC->getIndexType(); + + EVT IdxVT = Index.getValueType(); + + if (DCI.isBeforeLegalize()) { + // SVE gather/scatter requires indices of i32/i64. Promote anything smaller + // prior to legalisation so the result can be split if required. + if ((IdxVT.getVectorElementType() == MVT::i8) || + (IdxVT.getVectorElementType() == MVT::i16)) { + EVT NewIdxVT = IdxVT.changeVectorElementType(MVT::i32); + if (MSC->isIndexSigned()) + Index = DAG.getNode(ISD::SIGN_EXTEND, DL, NewIdxVT, Index); + else + Index = DAG.getNode(ISD::ZERO_EXTEND, DL, NewIdxVT, Index); + + SDValue Ops[] = { Chain, Data, Mask, BasePtr, Index, Scale }; + return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), + MSC->getMemoryVT(), DL, Ops, + MSC->getMemOperand(), IndexType, + MSC->isTruncatingStore()); + } + } + + return SDValue(); +} /// Target-specific DAG combine function for NEON load/store intrinsics /// to merge base address updates. @@ -15136,6 +15176,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N, break; case ISD::STORE: return performSTORECombine(N, DCI, DAG, Subtarget); + case ISD::MSCATTER: + return performMSCATTERCombine(N, DCI, DAG); case AArch64ISD::BRCOND: return performBRCONDCombine(N, DCI, DAG); case AArch64ISD::TBNZ: diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 8798890b2fe4f..88392b258d949 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -3738,18 +3738,6 @@ def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))), def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))), (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; -// And here "(-a) + b*(-c)" - -let Predicates = [HasNEON, HasFullFP16] in -def : Pat<(f16 (fma FPR16:$Rn, (fneg FPR16:$Rm), (fneg FPR16:$Ra))), - (FNMADDHrrr FPR16:$Rn, FPR16:$Rm, FPR16:$Ra)>; - -def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))), - (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; - -def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))), - (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; - //===----------------------------------------------------------------------===// // Floating point comparison instructions. //===----------------------------------------------------------------------===// @@ -4067,17 +4055,6 @@ defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b001, "fmla", defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b001, "fmls", TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >; -// The following def pats catch the case where the LHS of an FMA is negated. -// The TriOpFrag above catches the case where the middle operand is negated. -def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)), - (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>; - -def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)), - (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>; - -def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)), - (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>; - defm FMULX : SIMDThreeSameVectorFP<0,0,0b011,"fmulx", int_aarch64_neon_fmulx>; defm FMUL : SIMDThreeSameVectorFP<1,0,0b011,"fmul", fmul>; defm FRECPS : SIMDThreeSameVectorFP<0,0,0b111,"frecps", int_aarch64_neon_frecps>; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index b4d71acadf671..f3f9d662b6004 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -151,6 +151,7 @@ void AArch64Subtarget::initializeProperties() { PrefFunctionLogAlignment = 3; break; case NeoverseN1: + case NeoverseN2: case NeoverseV1: PrefFunctionLogAlignment = 4; break; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 631d18a8198d3..7795cfce6c542 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -64,6 +64,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { Kryo, NeoverseE1, NeoverseN1, + NeoverseN2, NeoverseV1, Saphira, ThunderX2T99, diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index 54bb3d0c7781b..37a34023b8d01 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -217,10 +217,17 @@ AArch64TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) { auto *RetTy = ICA.getReturnType(); switch (ICA.getID()) { - case Intrinsic::smin: case Intrinsic::umin: - case Intrinsic::smax: case Intrinsic::umax: { + auto LT = TLI->getTypeLegalizationCost(DL, RetTy); + // umin(x,y) -> sub(x,usubsat(x,y)) + // umax(x,y) -> add(x,usubsat(y,x)) + if (LT.second == MVT::v2i64) + return LT.first * 2; + LLVM_FALLTHROUGH; + } + case Intrinsic::smin: + case Intrinsic::smax: { static const auto ValidMinMaxTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16, MVT::v2i32, MVT::v4i32}; auto LT = TLI->getTypeLegalizationCost(DL, RetTy); diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index c3bf8737504fd..6691bf068042b 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -1815,6 +1815,19 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) { MRI.setType(DstReg, LLT::scalar(64)); return true; } + case AArch64::G_DUP: { + // Convert the type from p0 to s64 to help selection. + LLT DstTy = MRI.getType(I.getOperand(0).getReg()); + if (!DstTy.getElementType().isPointer()) + return false; + MachineIRBuilder MIB(I); + auto NewSrc = MIB.buildCopy(LLT::scalar(64), I.getOperand(1).getReg()); + MRI.setType(I.getOperand(0).getReg(), + DstTy.changeElementType(LLT::scalar(64))); + MRI.setRegBank(NewSrc.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID)); + I.getOperand(1).setReg(NewSrc.getReg(0)); + return true; + } default: return false; } @@ -3651,7 +3664,7 @@ bool AArch64InstructionSelector::selectExtractElt( (void)WideTy; assert(WideTy.getSizeInBits() >= NarrowTy.getSizeInBits() && "source register size too small!"); - assert(NarrowTy.isScalar() && "cannot extract vector into vector!"); + assert(!NarrowTy.isVector() && "cannot extract vector into vector!"); // Need the lane index to determine the correct copy opcode. MachineOperand &LaneIdxOp = I.getOperand(2); diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index efc82ffc1ab9c..d66862bd09978 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -589,7 +589,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) const LLT &VecTy = Query.Types[1]; return VecTy == v2s16 || VecTy == v4s16 || VecTy == v8s16 || VecTy == v4s32 || VecTy == v2s64 || VecTy == v2s32 || - VecTy == v16s8 || VecTy == v2s32; + VecTy == v16s8 || VecTy == v2s32 || VecTy == v2p0; }) .minScalarOrEltIf( [=](const LegalityQuery &Query) { @@ -650,7 +650,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) // to be the same size as the dest. if (DstTy != SrcTy) return false; - for (auto &Ty : {v2s32, v4s32, v2s64, v16s8, v8s16}) { + for (auto &Ty : {v2s32, v4s32, v2s64, v2p0, v16s8, v8s16}) { if (DstTy == Ty) return true; } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp index a07416420fe9e..1c50706a26f9b 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp @@ -28,6 +28,7 @@ class AArch64WinCOFFStreamer : public MCWinCOFFStreamer { void EmitWinEHHandlerData(SMLoc Loc) override; void EmitWindowsUnwindTables() override; + void EmitWindowsUnwindTables(WinEH::FrameInfo *Frame) override; void finishImpl() override; }; @@ -36,7 +37,12 @@ void AArch64WinCOFFStreamer::EmitWinEHHandlerData(SMLoc Loc) { // We have to emit the unwind info now, because this directive // actually switches to the .xdata section! - EHStreamer.EmitUnwindInfo(*this, getCurrentWinFrameInfo()); + EHStreamer.EmitUnwindInfo(*this, getCurrentWinFrameInfo(), + /* HandlerData = */ true); +} + +void AArch64WinCOFFStreamer::EmitWindowsUnwindTables(WinEH::FrameInfo *Frame) { + EHStreamer.EmitUnwindInfo(*this, Frame, /* HandlerData = */ false); } void AArch64WinCOFFStreamer::EmitWindowsUnwindTables() { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp index cf262c2a53580..6fc58816cf99a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp @@ -109,7 +109,7 @@ bool AMDGPUAnnotateUniformValues::isClobberedInFunction(LoadInst * Load) { BasicBlock::iterator StartIt = (!L && (BB == Load->getParent())) ? BasicBlock::iterator(Load) : BB->end(); auto Q = MDR->getPointerDependencyFrom( - MemoryLocation(Ptr, LocationSize::unknown()), true, StartIt, BB, Load); + MemoryLocation::getBeforeOrAfter(Ptr), true, StartIt, BB, Load); if (Q.isClobber() || Q.isUnknown()) return true; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 17c31a4bb0d8c..137f6896c87bf 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -338,7 +338,7 @@ bool AMDGPUAsmPrinter::doFinalization(Module &M) { // causing stale data in caches. Arguably this should be done by the linker, // which is why this isn't done for Mesa. const MCSubtargetInfo &STI = *getGlobalSTI(); - if (AMDGPU::isGFX10(STI) && + if (AMDGPU::isGFX10Plus(STI) && (STI.getTargetTriple().getOS() == Triple::AMDHSA || STI.getTargetTriple().getOS() == Triple::AMDPAL)) { OutStreamer->SwitchSection(getObjFileLowering().getTextSection()); @@ -456,9 +456,12 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { Info = analyzeResourceUsage(MF); } - if (STM.isAmdPalOS() && MFI->isEntryFunction()) - EmitPALMetadata(MF, CurrentProgramInfo); - else if (!STM.isAmdHsaOS()) { + if (STM.isAmdPalOS()) { + if (MFI->isEntryFunction()) + EmitPALMetadata(MF, CurrentProgramInfo); + else + emitPALFunctionMetadata(MF); + } else if (!STM.isAmdHsaOS()) { EmitProgramInfoSI(MF, CurrentProgramInfo); } @@ -1029,18 +1032,26 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, // Account for extra SGPRs and VGPRs reserved for debugger use. ProgInfo.NumSGPR += ExtraSGPRs; + const Function &F = MF.getFunction(); + // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave // dispatch registers are function args. unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0; - for (auto &Arg : MF.getFunction().args()) { - unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32; - if (Arg.hasAttribute(Attribute::InReg)) - WaveDispatchNumSGPR += NumRegs; - else - WaveDispatchNumVGPR += NumRegs; + + if (isShader(F.getCallingConv())) { + // FIXME: We should be using the number of registers determined during + // calling convention lowering to legalize the types. + const DataLayout &DL = F.getParent()->getDataLayout(); + for (auto &Arg : F.args()) { + unsigned NumRegs = (DL.getTypeSizeInBits(Arg.getType()) + 31) / 32; + if (Arg.hasAttribute(Attribute::InReg)) + WaveDispatchNumSGPR += NumRegs; + else + WaveDispatchNumVGPR += NumRegs; + } + ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR); + ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR); } - ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR); - ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR); // Adjust number of registers used to meet default/requested minimum/maximum // number of waves per execution unit request. @@ -1252,6 +1263,12 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF, MD->setWave32(MF.getFunction().getCallingConv()); } +void AMDGPUAsmPrinter::emitPALFunctionMetadata(const MachineFunction &MF) { + auto *MD = getTargetStreamer()->getPALMetadata(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); + MD->setStackFrameSize(MF, MFI.getStackSize()); +} + // This is supposed to be log2(Size) static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) { switch (Size) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h index 54e8338ab4b04..907ff2bfc1623 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h @@ -78,6 +78,7 @@ class AMDGPUAsmPrinter final : public AsmPrinter { const SIProgramInfo &KernelInfo); void EmitPALMetadata(const MachineFunction &MF, const SIProgramInfo &KernelInfo); + void emitPALFunctionMetadata(const MachineFunction &MF); void emitCommonFunctionComments(uint32_t NumVGPR, Optional NumAGPR, uint32_t TotalNumVGPR, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 37a79ce4fa37a..20b7c7849397b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -1485,7 +1485,7 @@ bool AMDGPUInstructionSelector::selectImageIntrinsic( const AMDGPU::MIMGMIPMappingInfo *MIPMappingInfo = AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode); unsigned IntrOpcode = Intr->BaseOpcode; - const bool IsGFX10 = STI.getGeneration() >= AMDGPUSubtarget::GFX10; + const bool IsGFX10Plus = AMDGPU::isGFX10Plus(STI); const unsigned ArgOffset = MI.getNumExplicitDefs() + 1; @@ -1603,12 +1603,12 @@ bool AMDGPUInstructionSelector::selectImageIntrinsic( GLC = true; // TODO no-return optimization if (!parseCachePolicy( MI.getOperand(ArgOffset + Intr->CachePolicyIndex).getImm(), nullptr, - &SLC, IsGFX10 ? &DLC : nullptr)) + &SLC, IsGFX10Plus ? &DLC : nullptr)) return false; } else { if (!parseCachePolicy( MI.getOperand(ArgOffset + Intr->CachePolicyIndex).getImm(), &GLC, - &SLC, IsGFX10 ? &DLC : nullptr)) + &SLC, IsGFX10Plus ? &DLC : nullptr)) return false; } @@ -1641,7 +1641,7 @@ bool AMDGPUInstructionSelector::selectImageIntrinsic( ++NumVDataDwords; int Opcode = -1; - if (IsGFX10) { + if (IsGFX10Plus) { Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, UseNSA ? AMDGPU::MIMGEncGfx10NSA : AMDGPU::MIMGEncGfx10Default, @@ -1693,22 +1693,22 @@ bool AMDGPUInstructionSelector::selectImageIntrinsic( MIB.addImm(DMask); // dmask - if (IsGFX10) + if (IsGFX10Plus) MIB.addImm(DimInfo->Encoding); MIB.addImm(Unorm); - if (IsGFX10) + if (IsGFX10Plus) MIB.addImm(DLC); MIB.addImm(GLC); MIB.addImm(SLC); MIB.addImm(IsA16 && // a16 or r128 STI.hasFeature(AMDGPU::FeatureR128A16) ? -1 : 0); - if (IsGFX10) + if (IsGFX10Plus) MIB.addImm(IsA16 ? -1 : 0); MIB.addImm(TFE); // tfe MIB.addImm(LWE); // lwe - if (!IsGFX10) + if (!IsGFX10Plus) MIB.addImm(DimInfo->DA ? -1 : 0); if (BaseOpcode->HasD16) MIB.addImm(IsD16 ? -1 : 0); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp b/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp index 17e2ac864a7bd..edc5fe2871678 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp @@ -304,8 +304,7 @@ bool AMDGPURewriteOutArguments::runOnFunction(Function &F) { BasicBlock *BB = RI->getParent(); MemDepResult Q = MDA->getPointerDependencyFrom( - MemoryLocation(OutArg, LocationSize::unknown()), true, BB->end(), - BB, RI); + MemoryLocation::getBeforeOrAfter(OutArg), true, BB->end(), BB, RI); StoreInst *SI = nullptr; if (Q.isDef()) SI = dyn_cast(Q.getInst()); diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 650c155c3536b..b8b747ea8f999 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -188,6 +188,12 @@ class AMDGPUOperand : public MCParsedAsmOperand { ImmTyEndpgm, }; + enum ImmKindTy { + ImmKindTyNone, + ImmKindTyLiteral, + ImmKindTyConst, + }; + private: struct TokOp { const char *Data; @@ -198,6 +204,7 @@ class AMDGPUOperand : public MCParsedAsmOperand { int64_t Val; ImmTy Type; bool IsFPImm; + mutable ImmKindTy Kind; Modifiers Mods; }; @@ -233,6 +240,29 @@ class AMDGPUOperand : public MCParsedAsmOperand { return Kind == Immediate; } + void setImmKindNone() const { + assert(isImm()); + Imm.Kind = ImmKindTyNone; + } + + void setImmKindLiteral() const { + assert(isImm()); + Imm.Kind = ImmKindTyLiteral; + } + + void setImmKindConst() const { + assert(isImm()); + Imm.Kind = ImmKindTyConst; + } + + bool IsImmKindLiteral() const { + return isImm() && Imm.Kind == ImmKindTyLiteral; + } + + bool isImmKindConst() const { + return isImm() && Imm.Kind == ImmKindTyConst; + } + bool isInlinableImm(MVT type) const; bool isLiteralImm(MVT type) const; @@ -911,6 +941,7 @@ class AMDGPUOperand : public MCParsedAsmOperand { auto Op = std::make_unique(Immediate, AsmParser); Op->Imm.Val = Val; Op->Imm.IsFPImm = IsFPImm; + Op->Imm.Kind = ImmKindTyNone; Op->Imm.Type = Type; Op->Imm.Mods = Modifiers(); Op->StartLoc = Loc; @@ -1201,6 +1232,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser { return AMDGPU::isGFX10(getSTI()); } + bool isGFX10Plus() const { return AMDGPU::isGFX10Plus(getSTI()); } + bool isGFX10_BEncoding() const { return AMDGPU::isGFX10_BEncoding(getSTI()); } @@ -1217,9 +1250,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser { return !isVI() && !isGFX9(); } - bool hasSGPR104_SGPR105() const { - return isGFX10(); - } + bool hasSGPR104_SGPR105() const { return isGFX10Plus(); } bool hasIntClamp() const { return getFeatureBits()[AMDGPU::FeatureIntClamp]; @@ -1358,13 +1389,15 @@ class AMDGPUAsmParser : public MCTargetAsmParser { const OperandVector &Operands) const; SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const; SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const; + SMLoc getLitLoc(const OperandVector &Operands) const; + SMLoc getConstLoc(const OperandVector &Operands) const; bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands); bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands); bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands); bool validateSOPLiteral(const MCInst &Inst) const; - bool validateConstantBusLimitations(const MCInst &Inst); - bool validateEarlyClobberLimitations(const MCInst &Inst); + bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands); + bool validateEarlyClobberLimitations(const MCInst &Inst, const OperandVector &Operands); bool validateIntClampSupported(const MCInst &Inst); bool validateMIMGAtomicDMask(const MCInst &Inst); bool validateMIMGGatherDMask(const MCInst &Inst); @@ -1376,8 +1409,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser { bool validateLdsDirect(const MCInst &Inst); bool validateOpSel(const MCInst &Inst); bool validateVccOperand(unsigned Reg) const; - bool validateVOP3Literal(const MCInst &Inst) const; - bool validateMAIAccWrite(const MCInst &Inst); + bool validateVOP3Literal(const MCInst &Inst, const OperandVector &Operands); + bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands); bool validateDivScale(const MCInst &Inst); bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands, const SMLoc &IDLoc); @@ -1719,7 +1752,7 @@ bool AMDGPUOperand::isRegClass(unsigned RCID) const { bool AMDGPUOperand::isSDWAOperand(MVT type) const { if (AsmParser->isVI()) return isVReg32(); - else if (AsmParser->isGFX9() || AsmParser->isGFX10()) + else if (AsmParser->isGFX9Plus()) return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(type); else return false; @@ -1772,6 +1805,7 @@ void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers } else { assert(!isImmTy(ImmTyNone) || !hasModifiers()); Inst.addOperand(MCOperand::createImm(Imm.Val)); + setImmKindNone(); } } @@ -1799,6 +1833,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(), AsmParser->hasInv2PiInlineImm())) { Inst.addOperand(MCOperand::createImm(Literal.getZExtValue())); + setImmKindConst(); return; } @@ -1812,6 +1847,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo } Inst.addOperand(MCOperand::createImm(Literal.lshr(32).getZExtValue())); + setImmKindLiteral(); return; } @@ -1848,6 +1884,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue(); Inst.addOperand(MCOperand::createImm(ImmVal)); + setImmKindLiteral(); return; } default: @@ -1872,10 +1909,12 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo AMDGPU::isInlinableLiteral32(static_cast(Val), AsmParser->hasInv2PiInlineImm())) { Inst.addOperand(MCOperand::createImm(Val)); + setImmKindConst(); return; } Inst.addOperand(MCOperand::createImm(Val & 0xffffffff)); + setImmKindLiteral(); return; case AMDGPU::OPERAND_REG_IMM_INT64: @@ -1884,10 +1923,12 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo case AMDGPU::OPERAND_REG_INLINE_C_FP64: if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) { Inst.addOperand(MCOperand::createImm(Val)); + setImmKindConst(); return; } Inst.addOperand(MCOperand::createImm(Lo_32(Val))); + setImmKindLiteral(); return; case AMDGPU::OPERAND_REG_IMM_INT16: @@ -1900,10 +1941,12 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo AMDGPU::isInlinableLiteral16(static_cast(Val), AsmParser->hasInv2PiInlineImm())) { Inst.addOperand(MCOperand::createImm(Val)); + setImmKindConst(); return; } Inst.addOperand(MCOperand::createImm(Val & 0xffff)); + setImmKindLiteral(); return; case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: @@ -1925,6 +1968,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo template void AMDGPUOperand::addKImmFPOperands(MCInst &Inst, unsigned N) const { APInt Literal(64, Imm.Val); + setImmKindNone(); if (!Imm.IsFPImm) { // We got int literal token. @@ -2984,7 +3028,7 @@ bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst, } unsigned AMDGPUAsmParser::getConstantBusLimit(unsigned Opcode) const { - if (!isGFX10()) + if (!isGFX10Plus()) return 1; switch (Opcode) { @@ -3018,9 +3062,12 @@ bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) { } } -bool AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst) { +bool +AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst, + const OperandVector &Operands) { const unsigned Opcode = Inst.getOpcode(); const MCInstrDesc &Desc = MII.get(Opcode); + unsigned LastSGPR = AMDGPU::NoRegister; unsigned ConstantBusUseCount = 0; unsigned NumLiterals = 0; unsigned LiteralSize; @@ -3054,15 +3101,15 @@ bool AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst) { const MCOperand &MO = Inst.getOperand(OpIdx); if (usesConstantBus(Inst, OpIdx)) { if (MO.isReg()) { - const unsigned Reg = mc2PseudoReg(MO.getReg()); + LastSGPR = mc2PseudoReg(MO.getReg()); // Pairs of registers with a partial intersections like these // s0, s[0:1] // flat_scratch_lo, flat_scratch // flat_scratch_lo, flat_scratch_hi // are theoretically valid but they are disabled anyway. // Note that this code mimics SIInstrInfo::verifyInstruction - if (!SGPRsUsed.count(Reg)) { - SGPRsUsed.insert(Reg); + if (!SGPRsUsed.count(LastSGPR)) { + SGPRsUsed.insert(LastSGPR); ++ConstantBusUseCount; } } else { // Expression or a literal @@ -3094,10 +3141,19 @@ bool AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst) { } ConstantBusUseCount += NumLiterals; - return ConstantBusUseCount <= getConstantBusLimit(Opcode); + if (ConstantBusUseCount <= getConstantBusLimit(Opcode)) + return true; + + SMLoc LitLoc = getLitLoc(Operands); + SMLoc RegLoc = getRegLoc(LastSGPR, Operands); + SMLoc Loc = (LitLoc.getPointer() < RegLoc.getPointer()) ? RegLoc : LitLoc; + Error(Loc, "invalid operand (violates constant bus restrictions)"); + return false; } -bool AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst) { +bool +AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst, + const OperandVector &Operands) { const unsigned Opcode = Inst.getOpcode(); const MCInstrDesc &Desc = MII.get(Opcode); @@ -3126,6 +3182,8 @@ bool AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst) { if (Src.isReg()) { const unsigned SrcReg = mc2PseudoReg(Src.getReg()); if (isRegIntersect(DstReg, SrcReg, TRI)) { + Error(getRegLoc(SrcReg, Operands), + "destination must be different than all sources"); return false; } } @@ -3186,7 +3244,7 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst) { const unsigned Opc = Inst.getOpcode(); const MCInstrDesc &Desc = MII.get(Opc); - if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0 || !isGFX10()) + if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0 || !isGFX10Plus()) return true; const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); @@ -3299,7 +3357,8 @@ bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst) { return !isSGPR(mc2PseudoReg(Reg), TRI); } -bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst) { +bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst, + const OperandVector &Operands) { const unsigned Opc = Inst.getOpcode(); @@ -3313,10 +3372,11 @@ bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst) { if (!Src0.isReg()) return true; - auto Reg = Src0.getReg(); + auto Reg = mc2PseudoReg(Src0.getReg()); const MCRegisterInfo *TRI = getContext().getRegisterInfo(); - if (isSGPR(mc2PseudoReg(Reg), TRI)) { - Error(getLoc(), "source operand must be either a VGPR or an inline constant"); + if (isSGPR(Reg, TRI)) { + Error(getRegLoc(Reg, Operands), + "source operand must be either a VGPR or an inline constant"); return false; } @@ -3699,7 +3759,8 @@ bool AMDGPUAsmParser::validateVccOperand(unsigned Reg) const { } // VOP3 literal is only allowed in GFX10+ and only one can be used -bool AMDGPUAsmParser::validateVOP3Literal(const MCInst &Inst) const { +bool AMDGPUAsmParser::validateVOP3Literal(const MCInst &Inst, + const OperandVector &Operands) { unsigned Opcode = Inst.getOpcode(); const MCInstrDesc &Desc = MII.get(Opcode); if (!(Desc.TSFlags & (SIInstrFlags::VOP3 | SIInstrFlags::VOP3P))) @@ -3725,8 +3786,11 @@ bool AMDGPUAsmParser::validateVOP3Literal(const MCInst &Inst) const { continue; if (OpIdx == Src2Idx && (Desc.TSFlags & SIInstrFlags::IsMAI) && - getFeatureBits()[AMDGPU::FeatureMFMAInlineLiteralBug]) + getFeatureBits()[AMDGPU::FeatureMFMAInlineLiteralBug]) { + Error(getConstLoc(Operands), + "inline constants are not allowed for this operand"); return false; + } if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) { uint32_t Value = static_cast(MO.getImm()); @@ -3740,8 +3804,20 @@ bool AMDGPUAsmParser::validateVOP3Literal(const MCInst &Inst) const { } NumLiterals += NumExprs; - return !NumLiterals || - (NumLiterals == 1 && getFeatureBits()[AMDGPU::FeatureVOP3Literal]); + if (!NumLiterals) + return true; + + if (!getFeatureBits()[AMDGPU::FeatureVOP3Literal]) { + Error(getLitLoc(Operands), "literal operands are not supported"); + return false; + } + + if (NumLiterals > 1) { + Error(getLitLoc(Operands), "only one literal operand is allowed"); + return false; + } + + return true; } bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst, @@ -3770,23 +3846,17 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst, return false; } if (!validateSOPLiteral(Inst)) { - Error(IDLoc, + Error(getLitLoc(Operands), "only one literal operand is allowed"); return false; } - if (!validateVOP3Literal(Inst)) { - Error(IDLoc, - "invalid literal operand"); + if (!validateVOP3Literal(Inst, Operands)) { return false; } - if (!validateConstantBusLimitations(Inst)) { - Error(IDLoc, - "invalid operand (violates constant bus restrictions)"); + if (!validateConstantBusLimitations(Inst, Operands)) { return false; } - if (!validateEarlyClobberLimitations(Inst)) { - Error(IDLoc, - "destination must be different than all sources"); + if (!validateEarlyClobberLimitations(Inst, Operands)) { return false; } if (!validateIntClampSupported(Inst)) { @@ -3839,7 +3909,7 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst, if (!validateSMEMOffset(Inst, Operands)) { return false; } - if (!validateMAIAccWrite(Inst)) { + if (!validateMAIAccWrite(Inst, Operands)) { return false; } if (!validateDivScale(Inst)) { @@ -4444,7 +4514,7 @@ bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID, if (ID == "enable_wavefront_size32") { if (Header.code_properties & AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32) { - if (!isGFX10()) + if (!isGFX10Plus()) return TokError("enable_wavefront_size32=1 is only allowed on GFX10+"); if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) return TokError("enable_wavefront_size32=1 requires +WavefrontSize32"); @@ -4456,7 +4526,7 @@ bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID, if (ID == "wavefront_size") { if (Header.wavefront_size == 5) { - if (!isGFX10()) + if (!isGFX10Plus()) return TokError("wavefront_size=5 is only allowed on GFX10+"); if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) return TokError("wavefront_size=5 requires +WavefrontSize32"); @@ -4467,17 +4537,20 @@ bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID, } if (ID == "enable_wgp_mode") { - if (G_00B848_WGP_MODE(Header.compute_pgm_resource_registers) && !isGFX10()) + if (G_00B848_WGP_MODE(Header.compute_pgm_resource_registers) && + !isGFX10Plus()) return TokError("enable_wgp_mode=1 is only allowed on GFX10+"); } if (ID == "enable_mem_ordered") { - if (G_00B848_MEM_ORDERED(Header.compute_pgm_resource_registers) && !isGFX10()) + if (G_00B848_MEM_ORDERED(Header.compute_pgm_resource_registers) && + !isGFX10Plus()) return TokError("enable_mem_ordered=1 is only allowed on GFX10+"); } if (ID == "enable_fwd_progress") { - if (G_00B848_FWD_PROGRESS(Header.compute_pgm_resource_registers) && !isGFX10()) + if (G_00B848_FWD_PROGRESS(Header.compute_pgm_resource_registers) && + !isGFX10Plus()) return TokError("enable_fwd_progress=1 is only allowed on GFX10+"); } @@ -4800,13 +4873,13 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI, case AMDGPU::TMA: case AMDGPU::TMA_LO: case AMDGPU::TMA_HI: - return !isGFX9() && !isGFX10(); + return !isGFX9Plus(); case AMDGPU::XNACK_MASK: case AMDGPU::XNACK_MASK_LO: case AMDGPU::XNACK_MASK_HI: - return !isCI() && !isSI() && !isGFX10() && hasXNACK(); + return !isCI() && !isSI() && !isGFX10Plus() && hasXNACK(); case AMDGPU::SGPR_NULL: - return isGFX10(); + return isGFX10Plus(); default: break; } @@ -4814,7 +4887,7 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI, if (isCI()) return true; - if (isSI() || isGFX10()) { + if (isSI() || isGFX10Plus()) { // No flat_scr on SI. // On GFX10 flat scratch is not a valid register operand and can only be // accessed with s_setreg/s_getreg. @@ -4920,7 +4993,7 @@ bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info, while (!getLexer().is(AsmToken::EndOfStatement)) { OperandMode Mode = OperandMode_Default; - if (IsMIMG && isGFX10() && Operands.size() == 2) + if (IsMIMG && isGFX10Plus() && Operands.size() == 2) Mode = OperandMode_NSA; OperandMatchResultTy Res = parseOperand(Operands, Name, Mode); @@ -5057,7 +5130,7 @@ AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands, } } - if (!isGFX10() && ImmTy == AMDGPUOperand::ImmTyDLC) + if (!isGFX10Plus() && ImmTy == AMDGPUOperand::ImmTyDLC) return MatchOperand_ParseFail; if (isGFX9() && ImmTy == AMDGPUOperand::ImmTyA16) @@ -5234,7 +5307,7 @@ AMDGPUAsmParser::parseSymbolicSplitFormat(StringRef FormatStr, Dfmt = (Dfmt == DFMT_UNDEF) ? DFMT_DEFAULT : Dfmt; Nfmt = (Nfmt == NFMT_UNDEF) ? NFMT_DEFAULT : Nfmt; - if (isGFX10()) { + if (isGFX10Plus()) { auto Ufmt = convertDfmtNfmt2Ufmt(Dfmt, Nfmt); if (Ufmt == UFMT_UNDEF) { Error(FormatLoc, "unsupported format"); @@ -5258,7 +5331,7 @@ AMDGPUAsmParser::parseSymbolicUnifiedFormat(StringRef FormatStr, if (Id == UFMT_UNDEF) return MatchOperand_NoMatch; - if (!isGFX10()) { + if (!isGFX10Plus()) { Error(Loc, "unified format is not supported on this GPU"); return MatchOperand_ParseFail; } @@ -5319,7 +5392,7 @@ AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) { SMLoc Loc = getLoc(); // Parse legacy format syntax. - Res = isGFX10() ? parseUfmt(Format) : parseDfmtNfmt(Format); + Res = isGFX10Plus() ? parseUfmt(Format) : parseDfmtNfmt(Format); if (Res == MatchOperand_ParseFail) return Res; @@ -5898,14 +5971,14 @@ OperandMatchResultTy AMDGPUAsmParser::parseExpTgtImpl(StringRef Str, if (Str.getAsInteger(10, Val)) return MatchOperand_ParseFail; - if (Val > (isGFX10() ? 4 : 3)) + if (Val > (isGFX10Plus() ? 4 : 3)) return MatchOperand_ParseFail; Val += Exp::ET_POS0; return MatchOperand_Success; } - if (isGFX10() && Str == "prim") { + if (isGFX10Plus() && Str == "prim") { Val = Exp::ET_PRIM; return MatchOperand_Success; } @@ -6112,6 +6185,22 @@ AMDGPUAsmParser::getRegLoc(unsigned Reg, return getOperandLoc(Test, Operands); } +SMLoc +AMDGPUAsmParser::getLitLoc(const OperandVector &Operands) const { + auto Test = [](const AMDGPUOperand& Op) { + return Op.IsImmKindLiteral() || Op.isExpr(); + }; + return getOperandLoc(Test, Operands); +} + +SMLoc +AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const { + auto Test = [](const AMDGPUOperand& Op) { + return Op.isImmKindConst(); + }; + return getOperandLoc(Test, Operands); +} + //===----------------------------------------------------------------------===// // swizzle //===----------------------------------------------------------------------===// @@ -6588,7 +6677,7 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst, addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE); } - if (isGFX10()) + if (isGFX10Plus()) addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDLC); } @@ -6628,7 +6717,7 @@ void AMDGPUAsmParser::cvtMtbuf(MCInst &Inst, const OperandVector &Operands) { addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE); - if (isGFX10()) + if (isGFX10Plus()) addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDLC); } @@ -6665,22 +6754,22 @@ void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands, } } - bool IsGFX10 = isGFX10(); + bool IsGFX10Plus = isGFX10Plus(); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask); - if (IsGFX10) + if (IsGFX10Plus) addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDim, -1); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm); - if (IsGFX10) + if (IsGFX10Plus) addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDLC); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128A16); - if (IsGFX10) + if (IsGFX10Plus) addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyA16); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE); - if (!IsGFX10) + if (!IsGFX10Plus) addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA); addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyD16); } @@ -7181,7 +7270,7 @@ bool AMDGPUOperand::isU16Imm() const { } OperandMatchResultTy AMDGPUAsmParser::parseDim(OperandVector &Operands) { - if (!isGFX10()) + if (!isGFX10Plus()) return MatchOperand_NoMatch; SMLoc S = Parser.getTok().getLoc(); @@ -7238,7 +7327,7 @@ OperandMatchResultTy AMDGPUAsmParser::parseDPP8(OperandVector &Operands) { if (Prefix != "dpp8") return parseDPPCtrl(Operands); - if (!isGFX10()) + if (!isGFX10Plus()) return MatchOperand_NoMatch; // dpp8:[%d,%d,%d,%d,%d,%d,%d,%d] @@ -7318,7 +7407,7 @@ AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) { return MatchOperand_NoMatch; } - if (!isGFX10() && (Prefix == "row_share" || Prefix == "row_xmask")) + if (!isGFX10Plus() && (Prefix == "row_share" || Prefix == "row_xmask")) return MatchOperand_NoMatch; if (!isVI() && !isGFX9() && diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 4907f325932d6..adc635d2cf4a6 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -52,8 +52,9 @@ using namespace llvm; #define DEBUG_TYPE "amdgpu-disassembler" -#define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ - : AMDGPU::EncValues::SGPR_MAX_SI) +#define SGPR_MAX \ + (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ + : AMDGPU::EncValues::SGPR_MAX_SI) using DecodeStatus = llvm::MCDisassembler::DecodeStatus; @@ -64,7 +65,7 @@ AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { // ToDo: AMDGPUDisassembler supports only VI ISA. - if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10()) + if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) report_fatal_error("Disassembly not yet supported for subtarget"); } @@ -1016,10 +1017,8 @@ unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { using namespace AMDGPU::EncValues; - unsigned TTmpMin = - (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN; - unsigned TTmpMax = - (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX; + unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN; + unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX; return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; } @@ -1157,8 +1156,8 @@ MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, Val - SDWA9EncValues::SRC_VGPR_MIN); } if (SDWA9EncValues::SRC_SGPR_MIN <= Val && - Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 - : SDWA9EncValues::SRC_SGPR_MAX_SI)) { + Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 + : SDWA9EncValues::SRC_SGPR_MAX_SI)) { return createSRegOperand(getSgprClassId(Width), Val - SDWA9EncValues::SRC_SGPR_MIN); } @@ -1227,12 +1226,14 @@ bool AMDGPUDisassembler::isVI() const { return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; } -bool AMDGPUDisassembler::isGFX9() const { - return STI.getFeatureBits()[AMDGPU::FeatureGFX9]; -} +bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } + +bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } + +bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } -bool AMDGPUDisassembler::isGFX10() const { - return STI.getFeatureBits()[AMDGPU::FeatureGFX10]; +bool AMDGPUDisassembler::isGFX10Plus() const { + return AMDGPU::isGFX10Plus(STI); } //===----------------------------------------------------------------------===// @@ -1287,7 +1288,7 @@ MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; - if (isGFX10() && GranulatedWavefrontSGPRCount) + if (isGFX10Plus() && GranulatedWavefrontSGPRCount) return MCDisassembler::Fail; uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * @@ -1331,7 +1332,7 @@ MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) return MCDisassembler::Fail; - if (isGFX10()) { + if (isGFX10Plus()) { PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", COMPUTE_PGM_RSRC1_WGP_MODE); PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); @@ -1456,7 +1457,7 @@ AMDGPUDisassembler::decodeKernelDescriptorDirective( // - Only set for GFX10, GFX6-9 have this to be 0. // - Currently no directives directly control this. FourByteBuffer = DE.getU32(Cursor); - if (!isGFX10() && FourByteBuffer) { + if (!isGFX10Plus() && FourByteBuffer) { return MCDisassembler::Fail; } return MCDisassembler::Success; @@ -1503,7 +1504,7 @@ AMDGPUDisassembler::decodeKernelDescriptorDirective( if (isGFX9() && (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { return MCDisassembler::Fail; - } else if (isGFX10()) { + } else if (isGFX10Plus()) { PRINT_DIRECTIVE(".amdhsa_wavefront_size32", KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); } diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h index 315602c35288c..34a1eb019c613 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h @@ -168,7 +168,9 @@ class AMDGPUDisassembler : public MCDisassembler { bool isVI() const; bool isGFX9() const; + bool isGFX9Plus() const; bool isGFX10() const; + bool isGFX10Plus() const; }; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index dc9c54e4aaac3..73cd9b9a8174c 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -155,7 +155,7 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo, if (IsFlatSeg) { // Unsigned offset printU16ImmDecOperand(MI, OpNo, O); } else { // Signed offset - if (AMDGPU::isGFX10(STI)) { + if (AMDGPU::isGFX10Plus(STI)) { O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm())); } else { O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm())); @@ -207,7 +207,7 @@ void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo, void AMDGPUInstPrinter::printDLC(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { - if (AMDGPU::isGFX10(STI)) + if (AMDGPU::isGFX10Plus(STI)) printNamedBit(MI, OpNo, O, "dlc"); } @@ -310,7 +310,7 @@ void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI, assert(OpNo != -1); unsigned Val = MI->getOperand(OpNo).getImm(); - if (AMDGPU::isGFX10(STI)) { + if (AMDGPU::isGFX10Plus(STI)) { if (Val == UFMT_DEFAULT) return; if (isValidUnifiedFormat(Val)) { @@ -780,7 +780,7 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI, void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { - if (!AMDGPU::isGFX10(STI)) + if (!AMDGPU::isGFX10Plus(STI)) llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10"); unsigned Imm = MI->getOperand(OpNo).getImm(); @@ -816,25 +816,25 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo, O << "row_ror:"; printU4ImmDecOperand(MI, OpNo, O); } else if (Imm == DppCtrl::WAVE_SHL1) { - if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) { + if (AMDGPU::isGFX10Plus(STI)) { O << "/* wave_shl is not supported starting from GFX10 */"; return; } O << "wave_shl:1"; } else if (Imm == DppCtrl::WAVE_ROL1) { - if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) { + if (AMDGPU::isGFX10Plus(STI)) { O << "/* wave_rol is not supported starting from GFX10 */"; return; } O << "wave_rol:1"; } else if (Imm == DppCtrl::WAVE_SHR1) { - if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) { + if (AMDGPU::isGFX10Plus(STI)) { O << "/* wave_shr is not supported starting from GFX10 */"; return; } O << "wave_shr:1"; } else if (Imm == DppCtrl::WAVE_ROR1) { - if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) { + if (AMDGPU::isGFX10Plus(STI)) { O << "/* wave_ror is not supported starting from GFX10 */"; return; } @@ -844,20 +844,20 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo, } else if (Imm == DppCtrl::ROW_HALF_MIRROR) { O << "row_half_mirror"; } else if (Imm == DppCtrl::BCAST15) { - if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) { + if (AMDGPU::isGFX10Plus(STI)) { O << "/* row_bcast is not supported starting from GFX10 */"; return; } O << "row_bcast:15"; } else if (Imm == DppCtrl::BCAST31) { - if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) { + if (AMDGPU::isGFX10Plus(STI)) { O << "/* row_bcast is not supported starting from GFX10 */"; return; } O << "row_bcast:31"; } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) && (Imm <= DppCtrl::ROW_SHARE_LAST)) { - if (!AMDGPU::isGFX10(STI)) { + if (!AMDGPU::isGFX10Plus(STI)) { O << "/* row_share is not supported on ASICs earlier than GFX10 */"; return; } @@ -865,7 +865,7 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo, printU4ImmDecOperand(MI, OpNo, O); } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) && (Imm <= DppCtrl::ROW_XMASK_LAST)) { - if (!AMDGPU::isGFX10(STI)) { + if (!AMDGPU::isGFX10Plus(STI)) { O << "/* row_xmask is not supported on ASICs earlier than GFX10 */"; return; } @@ -1023,9 +1023,9 @@ void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo, else if (Tgt == Exp::ET_NULL) O << " null"; else if (Tgt >= Exp::ET_POS0 && - Tgt <= uint32_t(isGFX10(STI) ? Exp::ET_POS4 : Exp::ET_POS3)) + Tgt <= uint32_t(isGFX10Plus(STI) ? Exp::ET_POS4 : Exp::ET_POS3)) O << " pos" << Tgt - Exp::ET_POS0; - else if (isGFX10(STI) && Tgt == Exp::ET_PRIM) + else if (isGFX10Plus(STI) && Tgt == Exp::ET_PRIM) O << " prim"; else if (Tgt >= Exp::ET_PARAM0 && Tgt <= Exp::ET_PARAM31) O << " param" << Tgt - Exp::ET_PARAM0; diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp index 2cd6c3a81d2bf..6226e6026740c 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -303,7 +303,7 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, } // NSA encoding. - if (AMDGPU::isGFX10(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { + if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(), diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h index 0abd96dc46074..b9a2bcf819038 100644 --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -33,26 +33,27 @@ enum : uint64_t { VOP2 = 1 << 8, VOPC = 1 << 9, - // TODO: Should this be spilt into VOP3 a and b? + // TODO: Should this be spilt into VOP3 a and b? VOP3 = 1 << 10, VOP3P = 1 << 12, VINTRP = 1 << 13, SDWA = 1 << 14, DPP = 1 << 15, + TRANS = 1 << 16, // Memory instruction formats. - MUBUF = 1 << 16, - MTBUF = 1 << 17, - SMRD = 1 << 18, - MIMG = 1 << 19, - EXP = 1 << 20, - FLAT = 1 << 21, - DS = 1 << 22, + MUBUF = 1 << 17, + MTBUF = 1 << 18, + SMRD = 1 << 19, + MIMG = 1 << 20, + EXP = 1 << 21, + FLAT = 1 << 22, + DS = 1 << 23, // Pseudo instruction formats. - VGPRSpill = 1 << 23, - SGPRSpill = 1 << 24, + VGPRSpill = 1 << 24, + SGPRSpill = 1 << 25, // High bits - other information. VM_CNT = UINT64_C(1) << 32, diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 26b2150703e36..8f74a2ee14bf7 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5987,7 +5987,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op, const AMDGPU::MIMGMIPMappingInfo *MIPMappingInfo = AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode); unsigned IntrOpcode = Intr->BaseOpcode; - bool IsGFX10 = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10; + bool IsGFX10Plus = AMDGPU::isGFX10Plus(*Subtarget); SmallVector ResultTypes(Op->value_begin(), Op->value_end()); SmallVector OrigResultTypes(Op->value_begin(), Op->value_end()); @@ -6235,11 +6235,11 @@ SDValue SITargetLowering::lowerImage(SDValue Op, if (BaseOpcode->Atomic) { GLC = True; // TODO no-return optimization if (!parseCachePolicy(Op.getOperand(ArgOffset + Intr->CachePolicyIndex), - DAG, nullptr, &SLC, IsGFX10 ? &DLC : nullptr)) + DAG, nullptr, &SLC, IsGFX10Plus ? &DLC : nullptr)) return Op; } else { if (!parseCachePolicy(Op.getOperand(ArgOffset + Intr->CachePolicyIndex), - DAG, &GLC, &SLC, IsGFX10 ? &DLC : nullptr)) + DAG, &GLC, &SLC, IsGFX10Plus ? &DLC : nullptr)) return Op; } @@ -6256,20 +6256,20 @@ SDValue SITargetLowering::lowerImage(SDValue Op, if (BaseOpcode->Sampler) Ops.push_back(Op.getOperand(ArgOffset + Intr->SampIndex)); Ops.push_back(DAG.getTargetConstant(DMask, DL, MVT::i32)); - if (IsGFX10) + if (IsGFX10Plus) Ops.push_back(DAG.getTargetConstant(DimInfo->Encoding, DL, MVT::i32)); Ops.push_back(Unorm); - if (IsGFX10) + if (IsGFX10Plus) Ops.push_back(DLC); Ops.push_back(GLC); Ops.push_back(SLC); Ops.push_back(IsA16 && // r128, a16 for gfx9 ST->hasFeature(AMDGPU::FeatureR128A16) ? True : False); - if (IsGFX10) + if (IsGFX10Plus) Ops.push_back(IsA16 ? True : False); Ops.push_back(TFE); Ops.push_back(LWE); - if (!IsGFX10) + if (!IsGFX10Plus) Ops.push_back(DimInfo->DA ? True : False); if (BaseOpcode->HasD16) Ops.push_back(IsD16 ? True : False); @@ -6280,7 +6280,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op, UseNSA ? VAddrs.size() : VAddr.getValueType().getSizeInBits() / 32; int Opcode = -1; - if (IsGFX10) { + if (IsGFX10Plus) { Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, UseNSA ? AMDGPU::MIMGEncGfx10NSA : AMDGPU::MIMGEncGfx10Default, @@ -6559,11 +6559,11 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return DAG.getConstant(MF.getSubtarget().getWavefrontSize(), SDLoc(Op), MVT::i32); case Intrinsic::amdgcn_s_buffer_load: { - bool IsGFX10 = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10; + bool IsGFX10Plus = AMDGPU::isGFX10Plus(*Subtarget); SDValue GLC; SDValue DLC = DAG.getTargetConstant(0, DL, MVT::i1); if (!parseCachePolicy(Op.getOperand(3), DAG, &GLC, nullptr, - IsGFX10 ? &DLC : nullptr)) + IsGFX10Plus ? &DLC : nullptr)) return Op; return lowerSBuffer(VT, DL, Op.getOperand(1), Op.getOperand(2), Op.getOperand(3), DAG); diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td index 79cd6a5bb8445..7ce042b67aba2 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td +++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td @@ -33,6 +33,7 @@ class InstSI getFeatureBits().test(FeatureCuMode)) + if (isGFX10Plus(*STI) && STI->getFeatureBits().test(FeatureCuMode)) return 2; // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP contains // two CUs, so a total of four SIMDs. @@ -335,7 +335,7 @@ unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) { unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI) { // FIXME: Need to take scratch memory into account. - if (!isGFX10(*STI)) + if (!isGFX10Plus(*STI)) return 10; return hasGFX10_3Insts(*STI) ? 16 : 20; } @@ -485,7 +485,7 @@ unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, } unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) { - if (!isGFX10(*STI)) + if (!isGFX10Plus(*STI)) return 256; return STI->getFeatureBits().test(FeatureWavefrontSize32) ? 1024 : 512; } @@ -896,11 +896,11 @@ int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt) { } bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI) { - return isGFX10(STI) ? (Val <= UFMT_MAX) : (Val <= DFMT_NFMT_MAX); + return isGFX10Plus(STI) ? (Val <= UFMT_MAX) : (Val <= DFMT_NFMT_MAX); } unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI) { - if (isGFX10(STI)) + if (isGFX10Plus(STI)) return UFMT_DEFAULT; return DFMT_NFMT_DEFAULT; } @@ -928,7 +928,7 @@ static bool isValidMsgId(int64_t MsgId) { bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict) { if (Strict) { if (MsgId == ID_GS_ALLOC_REQ || MsgId == ID_GET_DOORBELL) - return isGFX9(STI) || isGFX10(STI); + return isGFX9Plus(STI); else return isValidMsgId(MsgId); } else { @@ -1109,13 +1109,15 @@ bool isGFX9(const MCSubtargetInfo &STI) { } bool isGFX9Plus(const MCSubtargetInfo &STI) { - return isGFX9(STI) || isGFX10(STI); + return isGFX9(STI) || isGFX10Plus(STI); } bool isGFX10(const MCSubtargetInfo &STI) { return STI.getFeatureBits()[AMDGPU::FeatureGFX10]; } +bool isGFX10Plus(const MCSubtargetInfo &STI) { return isGFX10(STI); } + bool isGCN3Encoding(const MCSubtargetInfo &STI) { return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding]; } @@ -1455,11 +1457,11 @@ bool isArgPassedInSGPR(const Argument *A) { } static bool hasSMEMByteOffset(const MCSubtargetInfo &ST) { - return isGCN3Encoding(ST) || isGFX10(ST); + return isGCN3Encoding(ST) || isGFX10Plus(ST); } static bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST) { - return isGFX9(ST) || isGFX10(ST); + return isGFX9Plus(ST); } bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, @@ -1616,7 +1618,7 @@ const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI) { - return isGFX10(STI) + return isGFX10Plus(STI) ? getGfx10PlusBufferFormatInfo(BitsPerComp, NumComponents, NumFormat) : getGfx9BufferFormatInfo(BitsPerComp, NumComponents, NumFormat); @@ -1624,8 +1626,8 @@ const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp, const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format, const MCSubtargetInfo &STI) { - return isGFX10(STI) ? getGfx10PlusBufferFormatInfo(Format) - : getGfx9BufferFormatInfo(Format); + return isGFX10Plus(STI) ? getGfx10PlusBufferFormatInfo(Format) + : getGfx9BufferFormatInfo(Format); } } // namespace AMDGPU diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index e3cb4aa9641e0..7afc1bca670c8 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -601,6 +601,7 @@ bool isVI(const MCSubtargetInfo &STI); bool isGFX9(const MCSubtargetInfo &STI); bool isGFX9Plus(const MCSubtargetInfo &STI); bool isGFX10(const MCSubtargetInfo &STI); +bool isGFX10Plus(const MCSubtargetInfo &STI); bool isGCN3Encoding(const MCSubtargetInfo &STI); bool isGFX10_BEncoding(const MCSubtargetInfo &STI); bool hasGFX10_3Insts(const MCSubtargetInfo &STI); diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp index 85cba165770f2..efabab90422f0 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp @@ -238,6 +238,14 @@ void AMDGPUPALMetadata::setScratchSize(CallingConv::ID CC, unsigned Val) { getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val); } +// Set the scratch size in the metadata. +void AMDGPUPALMetadata::setStackFrameSize(const MachineFunction &MF, + unsigned Val) { + auto Node = MsgPackDoc.getMapNode(); + Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(Val); + getShaderFunctions()[MF.getFunction().getName()] = Node; +} + // Set the hardware register bit in PAL metadata to enable wave32 on the // shader of the given calling convention. void AMDGPUPALMetadata::setWave32(unsigned CC) { @@ -721,6 +729,24 @@ msgpack::MapDocNode AMDGPUPALMetadata::getRegisters() { return Registers.getMap(); } +// Reference (create if necessary) the node for the shader functions map. +msgpack::DocNode &AMDGPUPALMetadata::refShaderFunctions() { + auto &N = + MsgPackDoc.getRoot() + .getMap(/*Convert=*/true)[MsgPackDoc.getNode("amdpal.pipelines")] + .getArray(/*Convert=*/true)[0] + .getMap(/*Convert=*/true)[MsgPackDoc.getNode(".shader_functions")]; + N.getMap(/*Convert=*/true); + return N; +} + +// Get (create if necessary) the shader functions map. +msgpack::MapDocNode AMDGPUPALMetadata::getShaderFunctions() { + if (ShaderFunctions.isEmpty()) + ShaderFunctions = refShaderFunctions(); + return ShaderFunctions.getMap(); +} + // Return the PAL metadata hardware shader stage name. static const char *getStageName(CallingConv::ID CC) { switch (CC) { diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h index b089f295364ca..3b1767bb1f644 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h @@ -15,6 +15,7 @@ #define LLVM_LIB_TARGET_AMDGPU_AMDGPUPALMETADATA_H #include "llvm/BinaryFormat/MsgPackDocument.h" +#include "llvm/CodeGen/MachineFunction.h" namespace llvm { @@ -26,6 +27,7 @@ class AMDGPUPALMetadata { msgpack::Document MsgPackDoc; msgpack::DocNode Registers; msgpack::DocNode HwStages; + msgpack::DocNode ShaderFunctions; public: // Read the amdgpu.pal.metadata supplied by the frontend, ready for @@ -76,6 +78,9 @@ class AMDGPUPALMetadata { // Set the scratch size in the metadata. void setScratchSize(unsigned CC, unsigned Val); + // Set the stack frame size of a function in the metadata. + void setStackFrameSize(const MachineFunction &MF, unsigned Val); + // Set the hardware register bit in PAL metadata to enable wave32 on the // shader of the given calling convention. void setWave32(unsigned CC); @@ -119,6 +124,12 @@ class AMDGPUPALMetadata { // Get (create if necessary) the registers map. msgpack::MapDocNode getRegisters(); + // Reference (create if necessary) the node for the shader functions map. + msgpack::DocNode &refShaderFunctions(); + + // Get (create if necessary) the shader functions map. + msgpack::MapDocNode getShaderFunctions(); + // Get (create if necessary) the .hardware_stages entry for the given calling // convention. msgpack::MapDocNode getHwStage(unsigned CC); diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td index 11ec2953e1e84..37a2ad011929b 100644 --- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -242,25 +242,25 @@ defm V_CEIL_F32 : VOP1Inst <"v_ceil_f32", VOP_F32_F32, fceil>; defm V_RNDNE_F32 : VOP1Inst <"v_rndne_f32", VOP_F32_F32, frint>; defm V_FLOOR_F32 : VOP1Inst <"v_floor_f32", VOP_F32_F32, ffloor>; -let SchedRW = [WriteTrans32] in { +let TRANS = 1, SchedRW = [WriteTrans32] in { defm V_EXP_F32 : VOP1Inst <"v_exp_f32", VOP_F32_F32, fexp2>; defm V_LOG_F32 : VOP1Inst <"v_log_f32", VOP_F32_F32, flog2>; defm V_RCP_F32 : VOP1Inst <"v_rcp_f32", VOP_F32_F32, AMDGPUrcp>; defm V_RCP_IFLAG_F32 : VOP1Inst <"v_rcp_iflag_f32", VOP_F32_F32, AMDGPUrcp_iflag>; defm V_RSQ_F32 : VOP1Inst <"v_rsq_f32", VOP_F32_F32, AMDGPUrsq>; defm V_SQRT_F32 : VOP1Inst <"v_sqrt_f32", VOP_F32_F32, any_amdgcn_sqrt>; -} // End SchedRW = [WriteTrans32] +} // End TRANS = 1, SchedRW = [WriteTrans32] -let SchedRW = [WriteTrans64] in { +let TRANS = 1, SchedRW = [WriteTrans64] in { defm V_RCP_F64 : VOP1Inst <"v_rcp_f64", VOP_F64_F64, AMDGPUrcp>; defm V_RSQ_F64 : VOP1Inst <"v_rsq_f64", VOP_F64_F64, AMDGPUrsq>; defm V_SQRT_F64 : VOP1Inst <"v_sqrt_f64", VOP_F64_F64, any_amdgcn_sqrt>; -} // End SchedRW = [WriteTrans64] +} // End TRANS = 1, SchedRW = [WriteTrans64] -let SchedRW = [WriteTrans32] in { +let TRANS = 1, SchedRW = [WriteTrans32] in { defm V_SIN_F32 : VOP1Inst <"v_sin_f32", VOP_F32_F32, AMDGPUsin>; defm V_COS_F32 : VOP1Inst <"v_cos_f32", VOP_F32_F32, AMDGPUcos>; -} // End SchedRW = [WriteTrans32] +} // End TRANS = 1, SchedRW = [WriteTrans32] defm V_NOT_B32 : VOP1Inst <"v_not_b32", VOP_I32_I32>; defm V_BFREV_B32 : VOP1Inst <"v_bfrev_b32", VOP_I32_I32, bitreverse>; @@ -339,7 +339,7 @@ defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_MOVRELSD>; } // End Uses = [M0, EXEC] let SubtargetPredicate = isGFX6GFX7 in { - let SchedRW = [WriteTrans32] in { + let TRANS = 1, SchedRW = [WriteTrans32] in { defm V_LOG_CLAMP_F32 : VOP1Inst<"v_log_clamp_f32", VOP_F32_F32, int_amdgcn_log_clamp>; defm V_RCP_CLAMP_F32 : @@ -350,7 +350,7 @@ let SubtargetPredicate = isGFX6GFX7 in { VOP1Inst<"v_rsq_clamp_f32", VOP_F32_F32, AMDGPUrsq_clamp>; defm V_RSQ_LEGACY_F32 : VOP1Inst<"v_rsq_legacy_f32", VOP_F32_F32, int_amdgcn_rsq_legacy>; - } // End SchedRW = [WriteTrans32] + } // End TRANS = 1, SchedRW = [WriteTrans32] let SchedRW = [WriteDouble] in { defm V_RCP_CLAMP_F64 : @@ -361,10 +361,10 @@ let SubtargetPredicate = isGFX6GFX7 in { } // End SubtargetPredicate = isGFX6GFX7 let SubtargetPredicate = isGFX7GFX8GFX9 in { - let SchedRW = [WriteTrans32] in { + let TRANS = 1, SchedRW = [WriteTrans32] in { defm V_LOG_LEGACY_F32 : VOP1Inst<"v_log_legacy_f32", VOP_F32_F32>; defm V_EXP_LEGACY_F32 : VOP1Inst<"v_exp_legacy_f32", VOP_F32_F32>; - } // End SchedRW = [WriteTrans32] + } // End TRANS = 1, SchedRW = [WriteTrans32] } // End SubtargetPredicate = isGFX7GFX8GFX9 let SubtargetPredicate = isGFX7Plus in { @@ -384,7 +384,7 @@ defm V_CVT_F16_I16 : VOP1Inst <"v_cvt_f16_i16", VOP1_F16_I16, sint_to_fp>; } // End FPDPRounding = 1 defm V_CVT_U16_F16 : VOP1Inst <"v_cvt_u16_f16", VOP_I16_F16, fp_to_uint>; defm V_CVT_I16_F16 : VOP1Inst <"v_cvt_i16_f16", VOP_I16_F16, fp_to_sint>; -let SchedRW = [WriteTrans32] in { +let TRANS = 1, SchedRW = [WriteTrans32] in { defm V_RCP_F16 : VOP1Inst <"v_rcp_f16", VOP_F16_F16, AMDGPUrcp>; defm V_SQRT_F16 : VOP1Inst <"v_sqrt_f16", VOP_F16_F16, any_amdgcn_sqrt>; defm V_RSQ_F16 : VOP1Inst <"v_rsq_f16", VOP_F16_F16, AMDGPUrsq>; @@ -392,7 +392,7 @@ defm V_LOG_F16 : VOP1Inst <"v_log_f16", VOP_F16_F16, flog2>; defm V_EXP_F16 : VOP1Inst <"v_exp_f16", VOP_F16_F16, fexp2>; defm V_SIN_F16 : VOP1Inst <"v_sin_f16", VOP_F16_F16, AMDGPUsin>; defm V_COS_F16 : VOP1Inst <"v_cos_f16", VOP_F16_F16, AMDGPUcos>; -} // End SchedRW = [WriteTrans32] +} // End TRANS = 1, SchedRW = [WriteTrans32] defm V_FREXP_MANT_F16 : VOP1Inst <"v_frexp_mant_f16", VOP_F16_F16, int_amdgcn_frexp_mant>; defm V_FREXP_EXP_I16_F16 : VOP1Inst <"v_frexp_exp_i16_f16", VOP_I16_F16, int_amdgcn_frexp_exp>; defm V_FLOOR_F16 : VOP1Inst <"v_floor_f16", VOP_F16_F16, ffloor>; diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td index 8df1886022182..282c1002d3c92 100644 --- a/llvm/lib/Target/AMDGPU/VOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td @@ -8,6 +8,7 @@ // dummies for outer let class LetDummies { + bit TRANS; bit ReadsModeReg; bit mayRaiseFPException; bit isCommutable; diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 94e147b299206..3080152be55f5 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -885,14 +885,6 @@ def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; - -//===----------------------------------------------------------------------===// -// ARM schedules. -//===----------------------------------------------------------------------===// -// -include "ARMPredicates.td" -include "ARMSchedule.td" - //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// @@ -901,6 +893,13 @@ include "ARMRegisterInfo.td" include "ARMRegisterBanks.td" include "ARMCallingConv.td" +//===----------------------------------------------------------------------===// +// ARM schedules. +//===----------------------------------------------------------------------===// +// +include "ARMPredicates.td" +include "ARMSchedule.td" + //===----------------------------------------------------------------------===// // Instruction Descriptions //===----------------------------------------------------------------------===// @@ -1300,6 +1299,11 @@ def : ProcNoItin<"neoverse-n1", [ARMv82a, FeatureCRC, FeatureDotProd]>; +def : ProcNoItin<"neoverse-n2", [ARMv85a, + FeatureBF16, + FeatureMatMulInt8, + FeaturePerfMon]>; + def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, FeatureHasRetAddrStack, FeatureNEONForFP, diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td index 66a6d4bd6de0e..42498be05eea4 100644 --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -1962,9 +1962,10 @@ multiclass MVE_VQxDMULH_m { def "" : MVE_VQxDMULH_Base; defvar Inst = !cast(NAME); - defm : MVE_TwoOpPattern; let Predicates = [HasMVEInt] in { + defm : MVE_TwoOpPattern; + // Extra unpredicated multiply intrinsic patterns def : Pat<(VTI.Vec (unpred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn))), (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>; @@ -3683,16 +3684,10 @@ multiclass MVE_VFMA_fp_multi { if fms then { def : Pat<(VTI.Vec (fma (fneg m1), m2, add)), (Inst $add, $m1, $m2)>; - def : Pat<(VTI.Vec (fma m1, (fneg m2), add)), - (Inst $add, $m1, $m2)>; def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred), (VTI.Vec (fma (fneg m1), m2, add)), add)), (Inst $add, $m1, $m2, ARMVCCThen, $pred)>; - def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred), - (VTI.Vec (fma m1, (fneg m2), add)), - add)), - (Inst $add, $m1, $m2, ARMVCCThen, $pred)>; def : Pat<(VTI.Vec (pred_int (fneg m1), m2, add, pred)), (Inst $add, $m1, $m2, ARMVCCThen, $pred)>; def : Pat<(VTI.Vec (pred_int m1, (fneg m2), add, pred)), @@ -5492,7 +5487,10 @@ class MVE_VxxMUL_qr { def "" : MVE_VxxMUL_qr; - defm : MVE_TwoOpPatternDup(NAME)>; + + let Predicates = [HasMVEInt] in { + defm : MVE_TwoOpPatternDup(NAME)>; + } defm : MVE_vec_scalar_int_pat_m(NAME), VTI, int_unpred, int_pred>; } diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index 82bb137f82629..2be58d7a0e621 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -2264,16 +2264,6 @@ def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)), def : Pat<(f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin))), (VFMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, Requires<[HasFullFP16]>; -// (fma x, (fneg y), z) -> (vfms z, x, y) -def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)), - (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, - Requires<[HasVFP4,HasDPVFP]>; -def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)), - (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, - Requires<[HasVFP4]>; -def : Pat<(f16 (fma (f16 HPR:$Sn), (fneg (f16 HPR:$Sm)), (f16 HPR:$Sdin))), - (VFMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, - Requires<[HasFullFP16]>; def VFNMAD : ADbI<0b11101, 0b01, 1, 0, (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), @@ -2391,16 +2381,6 @@ def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))), def : Pat<(fneg (f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin)))), (VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, Requires<[HasFullFP16]>; -// (fneg (fma x, (fneg y), z) -> (vfnms z, x, y) -def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))), - (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, - Requires<[HasVFP4,HasDPVFP]>; -def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))), - (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, - Requires<[HasVFP4]>; -def : Pat<(fneg (f16 (fma (f16 HPR:$Sn), (fneg (f16 HPR:$Sm)), (f16 HPR:$Sdin)))), - (VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, - Requires<[HasFullFP16]>; //===----------------------------------------------------------------------===// // FP Conditional moves. diff --git a/llvm/lib/Target/ARM/ARMParallelDSP.cpp b/llvm/lib/Target/ARM/ARMParallelDSP.cpp index e750649ce86c2..730d6032dc551 100644 --- a/llvm/lib/Target/ARM/ARMParallelDSP.cpp +++ b/llvm/lib/Target/ARM/ARMParallelDSP.cpp @@ -374,7 +374,7 @@ bool ARMParallelDSP::RecordMemoryOps(BasicBlock *BB) { DepMap RAWDeps; // Record any writes that may alias a load. - const auto Size = LocationSize::unknown(); + const auto Size = LocationSize::beforeOrAfterPointer(); for (auto Write : Writes) { for (auto Read : Loads) { MemoryLocation ReadLoc = diff --git a/llvm/lib/Target/ARM/ARMSchedule.td b/llvm/lib/Target/ARM/ARMSchedule.td index 5838e7278c01b..53a2a6fec51e9 100644 --- a/llvm/lib/Target/ARM/ARMSchedule.td +++ b/llvm/lib/Target/ARM/ARMSchedule.td @@ -189,6 +189,23 @@ let FunctionMapper = "ARM_AM::getAM3Op" in { // LDM, base reg in list def IsLDMBaseRegInListPred : MCSchedPredicate; +class IsRegPCPred : MCSchedPredicate>; + +class BranchWriteRes resl, + list rcl, SchedWriteRes wr> : + SchedWriteRes { + let Latency = !add(wr.Latency, lat); + let ResourceCycles = !listconcat(wr.ResourceCycles, rcl); + let NumMicroOps = !add(wr.NumMicroOps, uops); + SchedWriteRes BaseWr = wr; +} + +class CheckBranchForm : + SchedWriteVariant<[ + SchedVar, [br]>, + SchedVar + ]>; + //===----------------------------------------------------------------------===// // Instruction Itinerary classes used for ARM // diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td index b5e745129c0ff..be85919358108 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA57.td +++ b/llvm/lib/Target/ARM/ARMScheduleA57.td @@ -173,22 +173,28 @@ def : InstRW<[A57Write_6cyc_1B_1L], (instregex "BR_JTm")>; def : InstRW<[A57Write_1cyc_1I], (instregex "tADDframe")>; +// Check branch forms of ALU ops: +// check reg 0 for ARM_AM::PC +// if so adds 2 cyc to latency, 1 uop, 1 res cycle for A57UnitB +class A57BranchForm : + BranchWriteRes<2, 1, [A57UnitB], [1], non_br>; + // shift by register, conditional or unconditional // TODO: according to the doc, conditional uses I0/I1, unconditional uses M // Why more complex instruction uses more simple pipeline? // May be an error in doc. def A57WriteALUsi : SchedWriteVariant<[ // lsl #2, lsl #1, or lsr #1. - SchedVar, - SchedVar + SchedVar>]>, + SchedVar>]> ]>; def A57WriteALUsr : SchedWriteVariant<[ - SchedVar, - SchedVar + SchedVar>]>, + SchedVar>]> ]>; def A57WriteALUSsr : SchedWriteVariant<[ - SchedVar, - SchedVar + SchedVar>]>, + SchedVar>]> ]>; def A57ReadALUsr : SchedReadVariant<[ SchedVar, @@ -830,7 +836,6 @@ def A57WriteVLDMuncond : SchedWriteVariant<[ SchedVar, SchedVar, SchedVar, - SchedVar, SchedVar ]> { let Variadic=1; } @@ -851,7 +856,6 @@ def A57WriteVLDMcond : SchedWriteVariant<[ SchedVar, SchedVar, SchedVar, - SchedVar, SchedVar ]> { let Variadic=1; } @@ -879,7 +883,6 @@ def A57WriteVLDMuncond_UPD : SchedWriteVariant<[ SchedVar, SchedVar, SchedVar, - SchedVar, SchedVar ]> { let Variadic=1; } @@ -900,7 +903,6 @@ def A57WriteVLDMcond_UPD : SchedWriteVariant<[ SchedVar, SchedVar, SchedVar, - SchedVar, SchedVar ]> { let Variadic=1; } @@ -1486,7 +1488,7 @@ def : InstRW<[A57Write_3cyc_1W], (instregex "^(t2)?CRC32")>; // ----------------------------------------------------------------------------- // Common definitions def : WriteRes { let Latency = 0; let NumMicroOps = 0; } -def : SchedAlias; +def : SchedAlias>>; def : SchedAlias; def : SchedAlias; diff --git a/llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td b/llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td index ffbf89a39d2c4..531b10bc5cfd4 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td +++ b/llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td @@ -36,13 +36,16 @@ def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19; def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20; let ResourceCycles = [20]; } def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; } -def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; } -def A57Write_2cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 2; } +def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; + let ResourceCycles = [1]; } +def A57Write_2cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 2; + let ResourceCycles = [1]; } def A57Write_3cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 3; } def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; } def A57Write_2cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 2; } def A57Write_3cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 3; } -def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; } +def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; + let ResourceCycles = [1]; } def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32; let ResourceCycles = [32]; } def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32; diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 0026901d54b3c..d90346df67da1 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -314,6 +314,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { PreISelOperandLatencyAdjustment = 1; break; case NeoverseN1: + case NeoverseN2: case NeoverseV1: break; case Swift: diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index 4c29b2bff6a9d..91002b429f7af 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -76,6 +76,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo { Krait, Kryo, NeoverseN1, + NeoverseN2, NeoverseV1, Swift }; diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 090ee8c443336..05f0499837649 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -10309,11 +10309,14 @@ bool ARMAsmParser::processInstruction(MCInst &Inst, !HasWideQualifier) { // The operands aren't the same for tMOV[S]r... (no cc_out) MCInst TmpInst; - TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); + unsigned Op = Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr; + TmpInst.setOpcode(Op); TmpInst.addOperand(Inst.getOperand(0)); TmpInst.addOperand(Inst.getOperand(1)); - TmpInst.addOperand(Inst.getOperand(2)); - TmpInst.addOperand(Inst.getOperand(3)); + if (Op == ARM::tMOVr) { + TmpInst.addOperand(Inst.getOperand(2)); + TmpInst.addOperand(Inst.getOperand(3)); + } Inst = TmpInst; return true; } diff --git a/llvm/lib/Target/ARM/MVETailPredication.cpp b/llvm/lib/Target/ARM/MVETailPredication.cpp index 25d5fd7e69c6e..8055b5cf500dc 100644 --- a/llvm/lib/Target/ARM/MVETailPredication.cpp +++ b/llvm/lib/Target/ARM/MVETailPredication.cpp @@ -22,23 +22,13 @@ /// The HardwareLoops pass inserts intrinsics identifying loops that the /// backend will attempt to convert into a low-overhead loop. The vectorizer is /// responsible for generating a vectorized loop in which the lanes are -/// predicated upon the iteration counter. This pass looks at these predicated -/// vector loops, that are targets for low-overhead loops, and prepares it for -/// code generation. Once the vectorizer has produced a masked loop, there's a -/// couple of final forms: -/// - A tail-predicated loop, with implicit predication. -/// - A loop containing multiple VCPT instructions, predicating multiple VPT -/// blocks of instructions operating on different vector types. -/// -/// This pass: -/// 1) Checks if the predicates of the masked load/store instructions are -/// generated by intrinsic @llvm.get.active.lanes(). This intrinsic consumes -/// the the scalar loop tripcount as its second argument, which we extract -/// to set up the number of elements processed by the loop. -/// 2) Intrinsic @llvm.get.active.lanes() is then replaced by the MVE target -/// specific VCTP intrinsic to represent the effect of tail predication. -/// This will be picked up by the ARM Low-overhead loop pass, which performs -/// the final transformation to a DLSTP or WLSTP tail-predicated loop. +/// predicated upon an get.active.lane.mask intrinsic. This pass looks at these +/// get.active.lane.mask intrinsic and attempts to convert them to VCTP +/// instructions. This will be picked up by the ARM Low-overhead loop pass later +/// in the backend, which performs the final transformation to a DLSTP or WLSTP +/// tail-predicated loop. +// +//===----------------------------------------------------------------------===// #include "ARM.h" #include "ARMSubtarget.h" @@ -57,6 +47,7 @@ #include "llvm/InitializePasses.h" #include "llvm/Support/Debug.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" +#include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/LoopUtils.h" #include "llvm/Transforms/Utils/ScalarEvolutionExpander.h" @@ -112,23 +103,18 @@ class MVETailPredication : public LoopPass { bool runOnLoop(Loop *L, LPPassManager&) override; private: - /// Perform the relevant checks on the loop and convert if possible. - bool TryConvert(Value *TripCount); - - /// Return whether this is a vectorized loop, that contains masked - /// load/stores. - bool IsPredicatedVectorLoop(); + /// Perform the relevant checks on the loop and convert active lane masks if + /// possible. + bool TryConvertActiveLaneMask(Value *TripCount); /// Perform several checks on the arguments of @llvm.get.active.lane.mask /// intrinsic. E.g., check that the loop induction variable and the element /// count are of the form we expect, and also perform overflow checks for /// the new expressions that are created. - bool IsSafeActiveMask(IntrinsicInst *ActiveLaneMask, Value *TripCount, - FixedVectorType *VecTy); + bool IsSafeActiveMask(IntrinsicInst *ActiveLaneMask, Value *TripCount); /// Insert the intrinsic to represent the effect of tail predication. - void InsertVCTPIntrinsic(IntrinsicInst *ActiveLaneMask, Value *TripCount, - FixedVectorType *VecTy); + void InsertVCTPIntrinsic(IntrinsicInst *ActiveLaneMask, Value *TripCount); /// Rematerialize the iteration count in exit blocks, which enables /// ARMLowOverheadLoops to better optimise away loop update statements inside @@ -138,25 +124,6 @@ class MVETailPredication : public LoopPass { } // end namespace -static bool IsDecrement(Instruction &I) { - auto *Call = dyn_cast(&I); - if (!Call) - return false; - - Intrinsic::ID ID = Call->getIntrinsicID(); - return ID == Intrinsic::loop_decrement_reg; -} - -static bool IsMasked(Instruction *I) { - auto *Call = dyn_cast(I); - if (!Call) - return false; - - Intrinsic::ID ID = Call->getIntrinsicID(); - return ID == Intrinsic::masked_store || ID == Intrinsic::masked_load || - isGatherScatter(Call); -} - bool MVETailPredication::runOnLoop(Loop *L, LPPassManager&) { if (skipLoop(L) || !EnableTailPredication) return false; @@ -207,147 +174,11 @@ bool MVETailPredication::runOnLoop(Loop *L, LPPassManager&) { return false; } - // Search for the hardware loop intrinic that decrements the loop counter. - IntrinsicInst *Decrement = nullptr; - for (auto *BB : L->getBlocks()) { - for (auto &I : *BB) { - if (IsDecrement(I)) { - Decrement = cast(&I); - break; - } - } - } - - if (!Decrement) - return false; - - LLVM_DEBUG(dbgs() << "ARM TP: Running on Loop: " << *L << *Setup << "\n" - << *Decrement << "\n"); - - if (!TryConvert(Setup->getArgOperand(0))) { - LLVM_DEBUG(dbgs() << "ARM TP: Can't tail-predicate this loop.\n"); - return false; - } - - return true; -} - -static FixedVectorType *getVectorType(IntrinsicInst *I) { - unsigned ID = I->getIntrinsicID(); - FixedVectorType *VecTy; - if (ID == Intrinsic::masked_load || isGather(I)) { - if (ID == Intrinsic::arm_mve_vldr_gather_base_wb || - ID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated) - // then the type is a StructType - VecTy = dyn_cast(I->getType()->getContainedType(0)); - else - VecTy = dyn_cast(I->getType()); - } else if (ID == Intrinsic::masked_store) { - VecTy = dyn_cast(I->getOperand(0)->getType()); - } else { - VecTy = dyn_cast(I->getOperand(2)->getType()); - } - assert(VecTy && "No scalable vectors expected here"); - return VecTy; -} - -bool MVETailPredication::IsPredicatedVectorLoop() { - // Check that the loop contains at least one masked load/store intrinsic. - // We only support 'normal' vector instructions - other than masked - // load/stores. - bool ActiveLaneMask = false; - for (auto *BB : L->getBlocks()) { - for (auto &I : *BB) { - auto *Int = dyn_cast(&I); - if (!Int) - continue; - - switch (Int->getIntrinsicID()) { - case Intrinsic::get_active_lane_mask: - ActiveLaneMask = true; - continue; - case Intrinsic::sadd_sat: - case Intrinsic::uadd_sat: - case Intrinsic::ssub_sat: - case Intrinsic::usub_sat: - case Intrinsic::vector_reduce_add: - continue; - case Intrinsic::fma: - case Intrinsic::trunc: - case Intrinsic::rint: - case Intrinsic::round: - case Intrinsic::floor: - case Intrinsic::ceil: - case Intrinsic::fabs: - if (ST->hasMVEFloatOps()) - continue; - break; - default: - break; - } - if (IsMasked(&I)) { - auto *VecTy = getVectorType(Int); - unsigned Lanes = VecTy->getNumElements(); - unsigned ElementWidth = VecTy->getScalarSizeInBits(); - // MVE vectors are 128-bit, but don't support 128 x i1. - // TODO: Can we support vectors larger than 128-bits? - unsigned MaxWidth = TTI->getRegisterBitWidth(true); - if (Lanes * ElementWidth > MaxWidth || Lanes == MaxWidth) - return false; - MaskedInsts.push_back(cast(&I)); - continue; - } - - for (const Use &U : Int->args()) { - if (isa(U->getType())) - return false; - } - } - } - - if (!ActiveLaneMask) { - LLVM_DEBUG(dbgs() << "ARM TP: No get.active.lane.mask intrinsic found.\n"); - return false; - } - return !MaskedInsts.empty(); -} - -// Look through the exit block to see whether there's a duplicate predicate -// instruction. This can happen when we need to perform a select on values -// from the last and previous iteration. Instead of doing a straight -// replacement of that predicate with the vctp, clone the vctp and place it -// in the block. This means that the VPR doesn't have to be live into the -// exit block which should make it easier to convert this loop into a proper -// tail predicated loop. -static void Cleanup(SetVector &MaybeDead, Loop *L) { - BasicBlock *Exit = L->getUniqueExitBlock(); - if (!Exit) { - LLVM_DEBUG(dbgs() << "ARM TP: can't find loop exit block\n"); - return; - } - - // Drop references and add operands to check for dead. - SmallPtrSet Dead; - while (!MaybeDead.empty()) { - auto *I = MaybeDead.front(); - MaybeDead.remove(I); - if (I->hasNUsesOrMore(1)) - continue; + LLVM_DEBUG(dbgs() << "ARM TP: Running on Loop: " << *L << *Setup << "\n"); - for (auto &U : I->operands()) - if (auto *OpI = dyn_cast(U)) - MaybeDead.insert(OpI); + bool Changed = TryConvertActiveLaneMask(Setup->getArgOperand(0)); - Dead.insert(I); - } - - for (auto *I : Dead) { - LLVM_DEBUG(dbgs() << "ARM TP: removing dead insn: "; I->dump()); - I->eraseFromParent(); - } - - for (auto I : L->blocks()) - DeleteDeadPHIs(I); + return Changed; } // The active lane intrinsic has this form: @@ -368,7 +199,7 @@ static void Cleanup(SetVector &MaybeDead, Loop *L) { // 3) The IV must be an induction phi with an increment equal to the // vector width. bool MVETailPredication::IsSafeActiveMask(IntrinsicInst *ActiveLaneMask, - Value *TripCount, FixedVectorType *VecTy) { + Value *TripCount) { bool ForceTailPredication = EnableTailPredication == TailPredication::ForceEnabledNoReductions || EnableTailPredication == TailPredication::ForceEnabled; @@ -376,7 +207,10 @@ bool MVETailPredication::IsSafeActiveMask(IntrinsicInst *ActiveLaneMask, Value *ElemCount = ActiveLaneMask->getOperand(1); auto *EC= SE->getSCEV(ElemCount); auto *TC = SE->getSCEV(TripCount); - int VectorWidth = VecTy->getNumElements(); + int VectorWidth = + cast(ActiveLaneMask->getType())->getNumElements(); + if (VectorWidth != 4 && VectorWidth != 8 && VectorWidth != 16) + return false; ConstantInt *ConstElemCount = nullptr; // 1) Smoke tests that the original scalar loop TripCount (TC) belongs to @@ -503,21 +337,22 @@ bool MVETailPredication::IsSafeActiveMask(IntrinsicInst *ActiveLaneMask, if (VectorWidth == StepValue) return true; - LLVM_DEBUG(dbgs() << "ARM TP: Step value " << StepValue << " doesn't match " - "vector width " << VectorWidth << "\n"); + LLVM_DEBUG(dbgs() << "ARM TP: Step value " << StepValue + << " doesn't match vector width " << VectorWidth << "\n"); return false; } void MVETailPredication::InsertVCTPIntrinsic(IntrinsicInst *ActiveLaneMask, - Value *TripCount, FixedVectorType *VecTy) { + Value *TripCount) { IRBuilder<> Builder(L->getLoopPreheader()->getTerminator()); Module *M = L->getHeader()->getModule(); Type *Ty = IntegerType::get(M->getContext(), 32); - unsigned VectorWidth = VecTy->getNumElements(); + unsigned VectorWidth = + cast(ActiveLaneMask->getType())->getNumElements(); // Insert a phi to count the number of elements processed by the loop. - Builder.SetInsertPoint(L->getHeader()->getFirstNonPHI() ); + Builder.SetInsertPoint(L->getHeader()->getFirstNonPHI()); PHINode *Processed = Builder.CreatePHI(Ty, 2); Processed->addIncoming(ActiveLaneMask->getOperand(1), L->getLoopPreheader()); @@ -553,50 +388,36 @@ void MVETailPredication::InsertVCTPIntrinsic(IntrinsicInst *ActiveLaneMask, << "ARM TP: Inserted VCTP: " << *VCTPCall << "\n"); } -bool MVETailPredication::TryConvert(Value *TripCount) { - if (!IsPredicatedVectorLoop()) { - LLVM_DEBUG(dbgs() << "ARM TP: no masked instructions in loop.\n"); +bool MVETailPredication::TryConvertActiveLaneMask(Value *TripCount) { + SmallVector ActiveLaneMasks; + for (auto *BB : L->getBlocks()) + for (auto &I : *BB) + if (auto *Int = dyn_cast(&I)) + if (Int->getIntrinsicID() == Intrinsic::get_active_lane_mask) + ActiveLaneMasks.push_back(Int); + + if (ActiveLaneMasks.empty()) return false; - } LLVM_DEBUG(dbgs() << "ARM TP: Found predicated vector loop.\n"); - SetVector Predicates; - - auto getPredicateOp = [](IntrinsicInst *I) { - unsigned IntrinsicID = I->getIntrinsicID(); - if (IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated || - IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated) - return 5; - return (IntrinsicID == Intrinsic::masked_load || isGather(I)) ? 2 : 3; - }; - - // Walk through the masked intrinsics and try to find whether the predicate - // operand is generated by intrinsic @llvm.get.active.lane.mask(). - for (auto *I : MaskedInsts) { - Value *PredOp = I->getArgOperand(getPredicateOp(I)); - auto *Predicate = dyn_cast(PredOp); - if (!Predicate || Predicates.count(Predicate)) - continue; - auto *ActiveLaneMask = dyn_cast(Predicate); - if (!ActiveLaneMask || - ActiveLaneMask->getIntrinsicID() != Intrinsic::get_active_lane_mask) - continue; - - Predicates.insert(Predicate); + for (auto *ActiveLaneMask : ActiveLaneMasks) { LLVM_DEBUG(dbgs() << "ARM TP: Found active lane mask: " << *ActiveLaneMask << "\n"); - auto *VecTy = getVectorType(I); - if (!IsSafeActiveMask(ActiveLaneMask, TripCount, VecTy)) { + if (!IsSafeActiveMask(ActiveLaneMask, TripCount)) { LLVM_DEBUG(dbgs() << "ARM TP: Not safe to insert VCTP.\n"); return false; } LLVM_DEBUG(dbgs() << "ARM TP: Safe to insert VCTP.\n"); - InsertVCTPIntrinsic(ActiveLaneMask, TripCount, VecTy); + InsertVCTPIntrinsic(ActiveLaneMask, TripCount); } - Cleanup(Predicates, L); + // Remove dead instructions and now dead phis. + for (auto *II : ActiveLaneMasks) + RecursivelyDeleteTriviallyDeadInstructions(II); + for (auto I : L->blocks()) + DeleteDeadPHIs(I); return true; } diff --git a/llvm/lib/Target/BPF/BPF.h b/llvm/lib/Target/BPF/BPF.h index 8629c1503b4e9..a98a3e08d5de7 100644 --- a/llvm/lib/Target/BPF/BPF.h +++ b/llvm/lib/Target/BPF/BPF.h @@ -56,6 +56,11 @@ class BPFPreserveDITypePass : public PassInfoMixin { static bool isRequired() { return true; } }; + +class BPFAdjustOptPass : public PassInfoMixin { +public: + PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); +}; } // namespace llvm #endif diff --git a/llvm/lib/Target/BPF/BPFAdjustOpt.cpp b/llvm/lib/Target/BPF/BPFAdjustOpt.cpp index 8efaa9d72b576..6afd2d77485dd 100644 --- a/llvm/lib/Target/BPF/BPFAdjustOpt.cpp +++ b/llvm/lib/Target/BPF/BPFAdjustOpt.cpp @@ -39,6 +39,14 @@ static cl::opt DisableBPFavoidSpeculation( namespace { class BPFAdjustOpt final : public ModulePass { +public: + static char ID; + + BPFAdjustOpt() : ModulePass(ID) {} + bool runOnModule(Module &M) override; +}; + +class BPFAdjustOptImpl { struct PassThroughInfo { Instruction *Input; Instruction *UsedInst; @@ -48,13 +56,12 @@ class BPFAdjustOpt final : public ModulePass { }; public: - static char ID; - Module *Mod; + BPFAdjustOptImpl(Module *M) : M(M) {} - BPFAdjustOpt() : ModulePass(ID) {} - bool runOnModule(Module &M) override; + bool run(); private: + Module *M; SmallVector PassThroughs; void adjustBasicBlock(BasicBlock &BB); @@ -73,9 +80,10 @@ INITIALIZE_PASS(BPFAdjustOpt, "bpf-adjust-opt", "BPF Adjust Optimization", ModulePass *llvm::createBPFAdjustOpt() { return new BPFAdjustOpt(); } -bool BPFAdjustOpt::runOnModule(Module &M) { - Mod = &M; - for (Function &F : M) +bool BPFAdjustOpt::runOnModule(Module &M) { return BPFAdjustOptImpl(&M).run(); } + +bool BPFAdjustOptImpl::run() { + for (Function &F : *M) for (auto &BB : F) { adjustBasicBlock(BB); for (auto &I : BB) @@ -85,10 +93,10 @@ bool BPFAdjustOpt::runOnModule(Module &M) { return insertPassThrough(); } -bool BPFAdjustOpt::insertPassThrough() { +bool BPFAdjustOptImpl::insertPassThrough() { for (auto &Info : PassThroughs) { auto *CI = BPFCoreSharedInfo::insertPassThrough( - Mod, Info.UsedInst->getParent(), Info.Input, Info.UsedInst); + M, Info.UsedInst->getParent(), Info.Input, Info.UsedInst); Info.UsedInst->setOperand(Info.OpIdx, CI); } @@ -97,7 +105,7 @@ bool BPFAdjustOpt::insertPassThrough() { // To avoid combining conditionals in the same basic block by // instrcombine optimization. -bool BPFAdjustOpt::serializeICMPInBB(Instruction &I) { +bool BPFAdjustOptImpl::serializeICMPInBB(Instruction &I) { // For: // comp1 = icmp ...; // comp2 = icmp ...; @@ -130,7 +138,7 @@ bool BPFAdjustOpt::serializeICMPInBB(Instruction &I) { // To avoid combining conditionals in the same basic block by // instrcombine optimization. -bool BPFAdjustOpt::serializeICMPCrossBB(BasicBlock &BB) { +bool BPFAdjustOptImpl::serializeICMPCrossBB(BasicBlock &BB) { // For: // B1: // comp1 = icmp ...; @@ -204,7 +212,7 @@ bool BPFAdjustOpt::serializeICMPCrossBB(BasicBlock &BB) { // To avoid speculative hoisting certain computations out of // a basic block. -bool BPFAdjustOpt::avoidSpeculation(Instruction &I) { +bool BPFAdjustOptImpl::avoidSpeculation(Instruction &I) { if (auto *LdInst = dyn_cast(&I)) { if (auto *GV = dyn_cast(LdInst->getOperand(0))) { if (GV->hasAttribute(BPFCoreSharedInfo::AmaAttr) || @@ -297,14 +305,19 @@ bool BPFAdjustOpt::avoidSpeculation(Instruction &I) { return true; } -void BPFAdjustOpt::adjustBasicBlock(BasicBlock &BB) { +void BPFAdjustOptImpl::adjustBasicBlock(BasicBlock &BB) { if (!DisableBPFserializeICMP && serializeICMPCrossBB(BB)) return; } -void BPFAdjustOpt::adjustInst(Instruction &I) { +void BPFAdjustOptImpl::adjustInst(Instruction &I) { if (!DisableBPFserializeICMP && serializeICMPInBB(I)) return; if (!DisableBPFavoidSpeculation && avoidSpeculation(I)) return; } + +PreservedAnalyses BPFAdjustOptPass::run(Module &M, ModuleAnalysisManager &AM) { + return BPFAdjustOptImpl(&M).run() ? PreservedAnalyses::none() + : PreservedAnalyses::all(); +} diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp index 25fccea256f12..c35a3192282f2 100644 --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -136,6 +136,10 @@ void BPFTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB, PassBuilder::OptimizationLevel Level) { FPM.addPass(SimplifyCFGPass(SimplifyCFGOptions().hoistCommonInsts(true))); }); + PB.registerPipelineEarlySimplificationEPCallback( + [=](ModulePassManager &MPM, PassBuilder::OptimizationLevel) { + MPM.addPass(BPFAdjustOptPass()); + }); } void BPFPassConfig::addIRPasses() { diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index b2fc79215c1e9..b60758a8be8a4 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -1517,8 +1517,11 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setMinimumJumpTableEntries(std::numeric_limits::max()); setOperationAction(ISD::BR_JT, MVT::Other, Expand); - setOperationAction(ISD::ABS, MVT::i32, Legal); - setOperationAction(ISD::ABS, MVT::i64, Legal); + for (unsigned LegalIntOp : + {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) { + setOperationAction(LegalIntOp, MVT::i32, Legal); + setOperationAction(LegalIntOp, MVT::i64, Legal); + } // Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit, // but they only operate on i64. @@ -1683,6 +1686,13 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::SPLAT_VECTOR, NativeVT, Legal); } + for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) { + setOperationAction(ISD::SMIN, VT, Legal); + setOperationAction(ISD::SMAX, VT, Legal); + setOperationAction(ISD::UMIN, VT, Legal); + setOperationAction(ISD::UMAX, VT, Legal); + } + // Custom lower unaligned loads. // Also, for both loads and stores, verify the alignment of the address // in case it is a compile-time constant. This is a usability feature to diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index 0b06e6ec9a3a5..f39c8e8890435 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -102,6 +102,13 @@ HexagonTargetLowering::initializeHVXLowering() { setOperationAction(ISD::BSWAP, T, Legal); } + setOperationAction(ISD::SMIN, T, Legal); + setOperationAction(ISD::SMAX, T, Legal); + if (T.getScalarType() != MVT::i32) { + setOperationAction(ISD::UMIN, T, Legal); + setOperationAction(ISD::UMAX, T, Legal); + } + setOperationAction(ISD::CTTZ, T, Custom); setOperationAction(ISD::LOAD, T, Custom); setOperationAction(ISD::MLOAD, T, Custom); @@ -183,6 +190,13 @@ HexagonTargetLowering::initializeHVXLowering() { // Promote all shuffles to operate on vectors of bytes. setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW); } + + setOperationAction(ISD::SMIN, T, Custom); + setOperationAction(ISD::SMAX, T, Custom); + if (T.getScalarType() != MVT::i32) { + setOperationAction(ISD::UMIN, T, Custom); + setOperationAction(ISD::UMAX, T, Custom); + } } // Boolean vectors. @@ -2029,6 +2043,10 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::SRA: case ISD::SHL: case ISD::SRL: + case ISD::SMIN: + case ISD::SMAX: + case ISD::UMIN: + case ISD::UMAX: case ISD::SETCC: case ISD::VSELECT: case ISD::SIGN_EXTEND: diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp index 2c1e0cadd9ee4..68c79d2a113f9 100644 --- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp +++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "HexagonLoopIdiomRecognition.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SetVector.h" @@ -16,6 +17,7 @@ #include "llvm/ADT/Triple.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/InstructionSimplify.h" +#include "llvm/Analysis/LoopAnalysisManager.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/LoopPass.h" #include "llvm/Analysis/MemoryLocation.h" @@ -40,6 +42,7 @@ #include "llvm/IR/Intrinsics.h" #include "llvm/IR/IntrinsicsHexagon.h" #include "llvm/IR/Module.h" +#include "llvm/IR/PassManager.h" #include "llvm/IR/PatternMatch.h" #include "llvm/IR/Type.h" #include "llvm/IR/User.h" @@ -108,136 +111,152 @@ static const char *HexagonVolatileMemcpyName namespace llvm { - void initializeHexagonLoopIdiomRecognizePass(PassRegistry&); - Pass *createHexagonLoopIdiomPass(); +void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &); +Pass *createHexagonLoopIdiomPass(); } // end namespace llvm namespace { - class HexagonLoopIdiomRecognize : public LoopPass { - public: - static char ID; - - explicit HexagonLoopIdiomRecognize() : LoopPass(ID) { - initializeHexagonLoopIdiomRecognizePass(*PassRegistry::getPassRegistry()); - } +class HexagonLoopIdiomRecognize { +public: + explicit HexagonLoopIdiomRecognize(AliasAnalysis *AA, DominatorTree *DT, + LoopInfo *LF, const TargetLibraryInfo *TLI, + ScalarEvolution *SE) + : AA(AA), DT(DT), LF(LF), TLI(TLI), SE(SE) {} + + bool run(Loop *L); + +private: + int getSCEVStride(const SCEVAddRecExpr *StoreEv); + bool isLegalStore(Loop *CurLoop, StoreInst *SI); + void collectStores(Loop *CurLoop, BasicBlock *BB, + SmallVectorImpl &Stores); + bool processCopyingStore(Loop *CurLoop, StoreInst *SI, const SCEV *BECount); + bool coverLoop(Loop *L, SmallVectorImpl &Insts) const; + bool runOnLoopBlock(Loop *CurLoop, BasicBlock *BB, const SCEV *BECount, + SmallVectorImpl &ExitBlocks); + bool runOnCountableLoop(Loop *L); + + AliasAnalysis *AA; + const DataLayout *DL; + DominatorTree *DT; + LoopInfo *LF; + const TargetLibraryInfo *TLI; + ScalarEvolution *SE; + bool HasMemcpy, HasMemmove; +}; + +class HexagonLoopIdiomRecognizeLegacyPass : public LoopPass { +public: + static char ID; + + explicit HexagonLoopIdiomRecognizeLegacyPass() : LoopPass(ID) { + initializeHexagonLoopIdiomRecognizeLegacyPassPass( + *PassRegistry::getPassRegistry()); + } - StringRef getPassName() const override { - return "Recognize Hexagon-specific loop idioms"; - } + StringRef getPassName() const override { + return "Recognize Hexagon-specific loop idioms"; + } - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); - AU.addRequiredID(LoopSimplifyID); - AU.addRequiredID(LCSSAID); - AU.addRequired(); - AU.addPreserved(); - AU.addRequired(); - AU.addRequired(); - AU.addRequired(); - AU.addPreserved(); - } + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + AU.addRequiredID(LoopSimplifyID); + AU.addRequiredID(LCSSAID); + AU.addRequired(); + AU.addPreserved(); + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + AU.addPreserved(); + } - bool runOnLoop(Loop *L, LPPassManager &LPM) override; + bool runOnLoop(Loop *L, LPPassManager &LPM) override; +}; - private: - int getSCEVStride(const SCEVAddRecExpr *StoreEv); - bool isLegalStore(Loop *CurLoop, StoreInst *SI); - void collectStores(Loop *CurLoop, BasicBlock *BB, - SmallVectorImpl &Stores); - bool processCopyingStore(Loop *CurLoop, StoreInst *SI, const SCEV *BECount); - bool coverLoop(Loop *L, SmallVectorImpl &Insts) const; - bool runOnLoopBlock(Loop *CurLoop, BasicBlock *BB, const SCEV *BECount, - SmallVectorImpl &ExitBlocks); - bool runOnCountableLoop(Loop *L); - - AliasAnalysis *AA; - const DataLayout *DL; - DominatorTree *DT; - LoopInfo *LF; - const TargetLibraryInfo *TLI; - ScalarEvolution *SE; - bool HasMemcpy, HasMemmove; +struct Simplifier { + struct Rule { + using FuncType = std::function; + Rule(StringRef N, FuncType F) : Name(N), Fn(F) {} + StringRef Name; // For debugging. + FuncType Fn; }; - struct Simplifier { - struct Rule { - using FuncType = std::function; - Rule(StringRef N, FuncType F) : Name(N), Fn(F) {} - StringRef Name; // For debugging. - FuncType Fn; - }; - - void addRule(StringRef N, const Rule::FuncType &F) { - Rules.push_back(Rule(N, F)); - } + void addRule(StringRef N, const Rule::FuncType &F) { + Rules.push_back(Rule(N, F)); + } - private: - struct WorkListType { - WorkListType() = default; +private: + struct WorkListType { + WorkListType() = default; - void push_back(Value* V) { - // Do not push back duplicates. - if (!S.count(V)) { Q.push_back(V); S.insert(V); } + void push_back(Value *V) { + // Do not push back duplicates. + if (!S.count(V)) { + Q.push_back(V); + S.insert(V); } + } - Value *pop_front_val() { - Value *V = Q.front(); Q.pop_front(); S.erase(V); - return V; - } + Value *pop_front_val() { + Value *V = Q.front(); + Q.pop_front(); + S.erase(V); + return V; + } - bool empty() const { return Q.empty(); } + bool empty() const { return Q.empty(); } - private: - std::deque Q; - std::set S; - }; + private: + std::deque Q; + std::set S; + }; - using ValueSetType = std::set; + using ValueSetType = std::set; - std::vector Rules; + std::vector Rules; - public: - struct Context { - using ValueMapType = DenseMap; +public: + struct Context { + using ValueMapType = DenseMap; - Value *Root; - ValueSetType Used; // The set of all cloned values used by Root. - ValueSetType Clones; // The set of all cloned values. - LLVMContext &Ctx; + Value *Root; + ValueSetType Used; // The set of all cloned values used by Root. + ValueSetType Clones; // The set of all cloned values. + LLVMContext &Ctx; - Context(Instruction *Exp) + Context(Instruction *Exp) : Ctx(Exp->getParent()->getParent()->getContext()) { - initialize(Exp); - } - - ~Context() { cleanup(); } + initialize(Exp); + } - void print(raw_ostream &OS, const Value *V) const; - Value *materialize(BasicBlock *B, BasicBlock::iterator At); + ~Context() { cleanup(); } - private: - friend struct Simplifier; + void print(raw_ostream &OS, const Value *V) const; + Value *materialize(BasicBlock *B, BasicBlock::iterator At); - void initialize(Instruction *Exp); - void cleanup(); + private: + friend struct Simplifier; - template void traverse(Value *V, FuncT F); - void record(Value *V); - void use(Value *V); - void unuse(Value *V); + void initialize(Instruction *Exp); + void cleanup(); - bool equal(const Instruction *I, const Instruction *J) const; - Value *find(Value *Tree, Value *Sub) const; - Value *subst(Value *Tree, Value *OldV, Value *NewV); - void replace(Value *OldV, Value *NewV); - void link(Instruction *I, BasicBlock *B, BasicBlock::iterator At); - }; + template void traverse(Value *V, FuncT F); + void record(Value *V); + void use(Value *V); + void unuse(Value *V); - Value *simplify(Context &C); + bool equal(const Instruction *I, const Instruction *J) const; + Value *find(Value *Tree, Value *Sub) const; + Value *subst(Value *Tree, Value *OldV, Value *NewV); + void replace(Value *OldV, Value *NewV); + void link(Instruction *I, BasicBlock *B, BasicBlock::iterator At); }; + Value *simplify(Context &C); +}; + struct PE { PE(const Simplifier::Context &c, Value *v = nullptr) : C(c), V(v) {} @@ -253,10 +272,10 @@ namespace { } // end anonymous namespace -char HexagonLoopIdiomRecognize::ID = 0; +char HexagonLoopIdiomRecognizeLegacyPass::ID = 0; -INITIALIZE_PASS_BEGIN(HexagonLoopIdiomRecognize, "hexagon-loop-idiom", - "Recognize Hexagon-specific loop idioms", false, false) +INITIALIZE_PASS_BEGIN(HexagonLoopIdiomRecognizeLegacyPass, "hexagon-loop-idiom", + "Recognize Hexagon-specific loop idioms", false, false) INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(LoopSimplify) INITIALIZE_PASS_DEPENDENCY(LCSSAWrapperPass) @@ -264,8 +283,8 @@ INITIALIZE_PASS_DEPENDENCY(ScalarEvolutionWrapperPass) INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) -INITIALIZE_PASS_END(HexagonLoopIdiomRecognize, "hexagon-loop-idiom", - "Recognize Hexagon-specific loop idioms", false, false) +INITIALIZE_PASS_END(HexagonLoopIdiomRecognizeLegacyPass, "hexagon-loop-idiom", + "Recognize Hexagon-specific loop idioms", false, false) template void Simplifier::Context::traverse(Value *V, FuncT F) { @@ -1973,7 +1992,7 @@ mayLoopAccessLocation(Value *Ptr, ModRefInfo Access, Loop *L, // Get the location that may be stored across the loop. Since the access // is strided positively through memory, we say that the modified location // starts at the pointer and has infinite size. - LocationSize AccessSize = LocationSize::unknown(); + LocationSize AccessSize = LocationSize::afterPointer(); // If the loop iterates a fixed number of times, we can refine the access // size to be exactly the size of the memset, which is (BECount+1)*StoreSize @@ -2404,14 +2423,11 @@ bool HexagonLoopIdiomRecognize::runOnCountableLoop(Loop *L) { return Changed; } -bool HexagonLoopIdiomRecognize::runOnLoop(Loop *L, LPPassManager &LPM) { +bool HexagonLoopIdiomRecognize::run(Loop *L) { const Module &M = *L->getHeader()->getParent()->getParent(); if (Triple(M.getTargetTriple()).getArch() != Triple::hexagon) return false; - if (skipLoop(L)) - return false; - // If the loop could not be converted to canonical form, it must have an // indirectbr in it, just give up. if (!L->getLoopPreheader()) @@ -2422,13 +2438,7 @@ bool HexagonLoopIdiomRecognize::runOnLoop(Loop *L, LPPassManager &LPM) { if (Name == "memset" || Name == "memcpy" || Name == "memmove") return false; - AA = &getAnalysis().getAAResults(); DL = &L->getHeader()->getModule()->getDataLayout(); - DT = &getAnalysis().getDomTree(); - LF = &getAnalysis().getLoopInfo(); - TLI = &getAnalysis().getTLI( - *L->getHeader()->getParent()); - SE = &getAnalysis().getSE(); HasMemcpy = TLI->has(LibFunc_memcpy); HasMemmove = TLI->has(LibFunc_memmove); @@ -2438,6 +2448,30 @@ bool HexagonLoopIdiomRecognize::runOnLoop(Loop *L, LPPassManager &LPM) { return false; } +bool HexagonLoopIdiomRecognizeLegacyPass::runOnLoop(Loop *L, + LPPassManager &LPM) { + if (skipLoop(L)) + return false; + + auto *AA = &getAnalysis().getAAResults(); + auto *DT = &getAnalysis().getDomTree(); + auto *LF = &getAnalysis().getLoopInfo(); + auto *TLI = &getAnalysis().getTLI( + *L->getHeader()->getParent()); + auto *SE = &getAnalysis().getSE(); + return HexagonLoopIdiomRecognize(AA, DT, LF, TLI, SE).run(L); +} + Pass *llvm::createHexagonLoopIdiomPass() { - return new HexagonLoopIdiomRecognize(); + return new HexagonLoopIdiomRecognizeLegacyPass(); +} + +PreservedAnalyses +HexagonLoopIdiomRecognitionPass::run(Loop &L, LoopAnalysisManager &AM, + LoopStandardAnalysisResults &AR, + LPMUpdater &U) { + return HexagonLoopIdiomRecognize(&AR.AA, &AR.DT, &AR.LI, &AR.TLI, &AR.SE) + .run(&L) + ? getLoopPassPreservedAnalyses() + : PreservedAnalyses::all(); } diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.h b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.h new file mode 100644 index 0000000000000..28ec83b05dac2 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.h @@ -0,0 +1,24 @@ +//===- HexagonLoopIdiomRecognition.h --------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONLOOPIDIOMRECOGNITION_H +#define LLVM_LIB_TARGET_HEXAGON_HEXAGONLOOPIDIOMRECOGNITION_H + +#include "llvm/IR/PassManager.h" +#include "llvm/Transforms/Scalar/LoopPassManager.h" + +namespace llvm { + +struct HexagonLoopIdiomRecognitionPass + : PassInfoMixin { + PreservedAnalyses run(Loop &L, LoopAnalysisManager &AM, + LoopStandardAnalysisResults &AR, LPMUpdater &U); +}; +} // namespace llvm + +#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONLOOPIDIOMRECOGNITION_H diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td index d1efb848ef998..fa91f7a31b140 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -366,12 +366,14 @@ multiclass NopCast_pat { def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>; } - // Frags for commonly used SDNodes. def Add: pf2; def And: pf2; def Sra: pf2; def Sub: pf2; def Or: pf2; def Srl: pf2; def Mul: pf2; def Xor: pf2; def Shl: pf2; +def Smin: pf2; def Smax: pf2; +def Umin: pf2; def Umax: pf2; + def Rol: pf2; // --(1) Immediate ------------------------------------------------------- @@ -924,25 +926,14 @@ let AddedComplexity = 200 in { defm: SelMinMax16_pats; } -let AddedComplexity = 200 in { - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; -} +def: OpR_RR_pat; +def: OpR_RR_pat; +def: OpR_RR_pat; +def: OpR_RR_pat; +def: OpR_RR_pat; +def: OpR_RR_pat; +def: OpR_RR_pat; +def: OpR_RR_pat; let AddedComplexity = 100 in { defm: MinMax_pats; @@ -958,18 +949,20 @@ let AddedComplexity = 100, Predicates = [HasV67] in { defm: MinMax_pats; } -defm: MinMax_pats; -defm: MinMax_pats; -defm: MinMax_pats; -defm: MinMax_pats; -defm: MinMax_pats; -defm: MinMax_pats; -defm: MinMax_pats; -defm: MinMax_pats; -defm: MinMax_pats; -defm: MinMax_pats; -defm: MinMax_pats; -defm: MinMax_pats; +def: OpR_RR_pat; +def: OpR_RR_pat; +def: OpR_RR_pat; +def: OpR_RR_pat; + +def: OpR_RR_pat; +def: OpR_RR_pat; +def: OpR_RR_pat; +def: OpR_RR_pat; + +def: OpR_RR_pat; +def: OpR_RR_pat; +def: OpR_RR_pat; +def: OpR_RR_pat; // --(7) Insert/extract -------------------------------------------------- // @@ -1708,8 +1701,6 @@ def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; -def: Pat<(fma F32:$Rs, (fneg F32:$Rt), F32:$Rx), - (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; def: Pat<(mul V2I32:$Rs, V2I32:$Rt), (PS_vmulw V2I32:$Rs, V2I32:$Rt)>; diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td index e37cfe34fa0eb..cd894c555adcd 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td +++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td @@ -274,21 +274,6 @@ class Vneg1 class Vnot : PatFrag<(ops node:$Vs), (xor $Vs, Vneg1)>; -let Predicates = [UseHVX] in { - let AddedComplexity = 220 in { - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - defm: MinMax_pats; - } -} - let Predicates = [UseHVX] in { let AddedComplexity = 200 in { def: Pat<(Vnot HVI8:$Vs), (V6_vnot HvxVR:$Vs)>; @@ -318,6 +303,17 @@ let Predicates = [UseHVX] in { def: OpR_RR_pat; def: OpR_RR_pat; + def: OpR_RR_pat; + def: OpR_RR_pat; + def: OpR_RR_pat; + def: OpR_RR_pat; + def: OpR_RR_pat; + def: OpR_RR_pat; + def: OpR_RR_pat; + def: OpR_RR_pat; + def: OpR_RR_pat; + def: OpR_RR_pat; + def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt), (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>; def: Pat<(vselect HQ16:$Qu, HVI16:$Vs, HVI16:$Vt), diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 0f15c46bc8bb6..1e034ce515c16 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -13,6 +13,7 @@ #include "HexagonTargetMachine.h" #include "Hexagon.h" #include "HexagonISelLowering.h" +#include "HexagonLoopIdiomRecognition.h" #include "HexagonMachineScheduler.h" #include "HexagonTargetObjectFile.h" #include "HexagonTargetTransformInfo.h" @@ -138,7 +139,7 @@ namespace llvm { void initializeHexagonExpandCondsetsPass(PassRegistry&); void initializeHexagonGenMuxPass(PassRegistry&); void initializeHexagonHardwareLoopsPass(PassRegistry&); - void initializeHexagonLoopIdiomRecognizePass(PassRegistry&); + void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &); void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &); void initializeHexagonNewValueJumpPass(PassRegistry&); void initializeHexagonOptAddrModePass(PassRegistry&); @@ -197,7 +198,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() { initializeHexagonEarlyIfConversionPass(PR); initializeHexagonGenMuxPass(PR); initializeHexagonHardwareLoopsPass(PR); - initializeHexagonLoopIdiomRecognizePass(PR); + initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR); initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PR); initializeHexagonNewValueJumpPass(PR); initializeHexagonOptAddrModePass(PR); @@ -276,6 +277,10 @@ void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) { void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB, bool DebugPassManager) { + PB.registerLateLoopOptimizationsEPCallback( + [=](LoopPassManager &LPM, PassBuilder::OptimizationLevel Level) { + LPM.addPass(HexagonLoopIdiomRecognitionPass()); + }); PB.registerOptimizerLastEPCallback( [=](ModulePassManager &MPM, PassBuilder::OptimizationLevel Level) { LoopPassManager LPM(DebugPassManager); diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 777d8d4d00be8..8b599bca3915a 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -1197,17 +1197,6 @@ bool MipsTargetLowering::shouldFoldConstantShiftPairToMask( return true; } -void -MipsTargetLowering::LowerOperationWrapper(SDNode *N, - SmallVectorImpl &Results, - SelectionDAG &DAG) const { - SDValue Res = LowerOperation(SDValue(N, 0), DAG); - - if (Res) - for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) - Results.push_back(Res.getValue(I)); -} - void MipsTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl &Results, diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h index 03933d8205766..3820c42ba8aa7 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.h +++ b/llvm/lib/Target/Mips/MipsISelLowering.h @@ -314,10 +314,6 @@ class TargetRegisterClass; return ISD::SIGN_EXTEND; } - void LowerOperationWrapper(SDNode *N, - SmallVectorImpl &Results, - SelectionDAG &DAG) const override; - /// LowerOperation - Provide custom lowering hooks for some operations. SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index 22aa9a5e1e45d..e2d90a846e3df 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -1076,6 +1076,7 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) { case PPC::GETtlsADDR: // Transform: %x3 = GETtlsADDR %x3, @sym // Into: BL8_NOP_TLS __tls_get_addr(sym at tlsgd) + case PPC::GETtlsADDRPCREL: case PPC::GETtlsADDR32: { // Transform: %r3 = GETtlsADDR32 %r3, @sym // Into: BL_TLS __tls_get_addr(sym at tlsgd)@PLT @@ -1121,6 +1122,7 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) { case PPC::GETtlsldADDR: // Transform: %x3 = GETtlsldADDR %x3, @sym // Into: BL8_NOP_TLS __tls_get_addr(sym at tlsld) + case PPC::GETtlsldADDRPCREL: case PPC::GETtlsldADDR32: { // Transform: %r3 = GETtlsldADDR32 %r3, @sym // Into: BL_TLS __tls_get_addr(sym at tlsld)@PLT @@ -1996,6 +1998,48 @@ bool PPCAIXAsmPrinter::doFinalization(Module &M) { return PPCAsmPrinter::doFinalization(M); } +static unsigned mapToSinitPriority(int P) { + if (P < 0 || P > 65535) + report_fatal_error("invalid init priority"); + + if (P <= 20) + return P; + + if (P < 81) + return 20 + (P - 20) * 16; + + if (P <= 1124) + return 1004 + (P - 81); + + if (P < 64512) + return 2047 + (P - 1124) * 33878; + + return 2147482625u + (P - 64512); +} + +static std::string convertToSinitPriority(int Priority) { + // This helper function converts clang init priority to values used in sinit + // and sterm functions. + // + // The conversion strategies are: + // We map the reserved clang/gnu priority range [0, 100] into the sinit/sterm + // reserved priority range [0, 1023] by + // - directly mapping the first 21 and the last 20 elements of the ranges + // - linear interpolating the intermediate values with a step size of 16. + // + // We map the non reserved clang/gnu priority range of [101, 65535] into the + // sinit/sterm priority range [1024, 2147483648] by: + // - directly mapping the first and the last 1024 elements of the ranges + // - linear interpolating the intermediate values with a step size of 33878. + unsigned int P = mapToSinitPriority(Priority); + + std::string PrioritySuffix; + llvm::raw_string_ostream os(PrioritySuffix); + os << llvm::format_hex_no_prefix(P, 8); + os.flush(); + return PrioritySuffix; +} + void PPCAIXAsmPrinter::emitXXStructorList(const DataLayout &DL, const Constant *List, bool IsCtor) { SmallVector Structors; @@ -2005,14 +2049,14 @@ void PPCAIXAsmPrinter::emitXXStructorList(const DataLayout &DL, unsigned Index = 0; for (Structor &S : Structors) { - if (S.Priority != 65535) - report_fatal_error( - "prioritized sinit and sterm functions are not yet supported on AIX"); + if (const ConstantExpr *CE = dyn_cast(S.Func)) + S.Func = CE->getOperand(0); llvm::GlobalAlias::create( GlobalValue::ExternalLinkage, (IsCtor ? llvm::Twine("__sinit") : llvm::Twine("__sterm")) + - llvm::Twine("80000000_", FormatIndicatorAndUniqueModId) + + llvm::Twine(convertToSinitPriority(S.Priority)) + + llvm::Twine("_", FormatIndicatorAndUniqueModId) + llvm::Twine("_", llvm::utostr(Index++)), cast(S.Func)); } diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td index 9a15490f1fb0d..cc34867181791 100644 --- a/llvm/lib/Target/PowerPC/PPCCallingConv.td +++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td @@ -59,7 +59,7 @@ def RetCC_PPC_Cold : CallingConv<[ CCIfType<[f32], CCAssignToReg<[F1]>>, CCIfType<[f64], CCAssignToReg<[F1]>>, - CCIfType<[f128], CCIfSubtarget<"hasP9Vector()", CCAssignToReg<[V2]>>>, + CCIfType<[f128], CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2]>>>, CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64], CCIfSubtarget<"hasAltivec()", @@ -92,7 +92,7 @@ def RetCC_PPC : CallingConv<[ // For P9, f128 are passed in vector registers. CCIfType<[f128], - CCIfSubtarget<"hasP9Vector()", + CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>, // Vector types returned as "direct" go into V2 .. V9; note that only the @@ -149,7 +149,7 @@ def RetCC_PPC64_ELF_FIS : CallingConv<[ CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, CCIfType<[f128], - CCIfSubtarget<"hasP9Vector()", + CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>, CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64], CCIfSubtarget<"hasAltivec()", @@ -216,7 +216,7 @@ def CC_PPC32_SVR4_Common : CallingConv<[ // Vectors and float128 get 16-byte stack slots that are 16-byte aligned. CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>, - CCIfType<[f128], CCIfSubtarget<"hasP9Vector()", CCAssignToStack<16, 16>>> + CCIfType<[f128], CCIfSubtarget<"hasAltivec()", CCAssignToStack<16, 16>>> ]>; // This calling convention puts vector arguments always on the stack. It is used @@ -238,7 +238,7 @@ def CC_PPC32_SVR4 : CallingConv<[ // Float128 types treated as vector arguments. CCIfType<[f128], - CCIfSubtarget<"hasP9Vector()", CCAssignToReg<[V2, V3, V4, V5, V6, V7, + CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>>, CCDelegateTo @@ -291,6 +291,8 @@ def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20, F27, F28, F29, F30, F31, CR2, CR3, CR4 )>; +def CSR_AIX32_Altivec : CalleeSavedRegs<(add CSR_AIX32, CSR_Altivec)>; + // Common CalleeSavedRegs for SVR4 and AIX. def CSR_PPC64 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index 6f1fe4e113bda..7df2f6dc92529 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -218,19 +218,14 @@ const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots( CALLEE_SAVED_VRS }; - static const SpillSlot AIXOffsets32[] = { - CALLEE_SAVED_FPRS, - CALLEE_SAVED_GPRS32, - // Add AIX's extra CSR. - {PPC::R13, -76}, - // TODO: Update when we add vector support for AIX. - }; + static const SpillSlot AIXOffsets32[] = {CALLEE_SAVED_FPRS, + CALLEE_SAVED_GPRS32, + // Add AIX's extra CSR. + {PPC::R13, -76}, + CALLEE_SAVED_VRS}; static const SpillSlot AIXOffsets64[] = { - CALLEE_SAVED_FPRS, - CALLEE_SAVED_GPRS64, - // TODO: Update when we add vector support for AIX. - }; + CALLEE_SAVED_FPRS, CALLEE_SAVED_GPRS64, CALLEE_SAVED_VRS}; if (Subtarget.is64BitELFABI()) { NumEntries = array_lengthof(ELFOffsets64); @@ -530,6 +525,8 @@ PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB, // register is available, we can adjust for that by not overlapping the spill // code. However, if we need to realign the stack (i.e. have a base pointer) // and the stack frame is large, we need two scratch registers. +// Also, stack probe requires two scratch registers, one for old sp, one for +// large frame and large probe size. bool PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const { const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); @@ -541,8 +538,10 @@ PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const { MachineFrameInfo &MFI = MF.getFrameInfo(); Align MaxAlign = MFI.getMaxAlign(); bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI(); + const PPCTargetLowering &TLI = *Subtarget.getTargetLowering(); - return (IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1; + return ((IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1) || + TLI.hasInlineStackProbe(MF); } bool PPCFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { @@ -681,12 +680,8 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF, "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."); // Using the same bool variable as below to suppress compiler warnings. - // Stack probe requires two scratch registers, one for old sp, one for large - // frame and large probe size. bool SingleScratchReg = findScratchRegister( - &MBB, false, - twoUniqueScratchRegsRequired(&MBB) || TLI.hasInlineStackProbe(MF), - &ScratchReg, &TempReg); + &MBB, false, twoUniqueScratchRegsRequired(&MBB), &ScratchReg, &TempReg); assert(SingleScratchReg && "Required number of registers not available in this block"); @@ -1207,10 +1202,12 @@ void PPCFrameLowering::inlineStackProbe(MachineFunction &MF, if (StackAllocMIPos == PrologMBB.end()) return; const BasicBlock *ProbedBB = PrologMBB.getBasicBlock(); + MachineBasicBlock *CurrentMBB = &PrologMBB; DebugLoc DL = PrologMBB.findDebugLoc(StackAllocMIPos); MachineInstr &MI = *StackAllocMIPos; int64_t NegFrameSize = MI.getOperand(2).getImm(); - int64_t NegProbeSize = -(int64_t)TLI.getStackProbeSize(MF); + unsigned ProbeSize = TLI.getStackProbeSize(MF); + int64_t NegProbeSize = -(int64_t)ProbeSize; assert(isInt<32>(NegProbeSize) && "Unhandled probe size"); int64_t NumBlocks = NegFrameSize / NegProbeSize; int64_t NegResidualSize = NegFrameSize % NegProbeSize; @@ -1219,10 +1216,9 @@ void PPCFrameLowering::inlineStackProbe(MachineFunction &MF, Register FPReg = MI.getOperand(1).getReg(); const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); bool HasBP = RegInfo->hasBasePointer(MF); + Register BPReg = RegInfo->getBaseRegister(MF); Align MaxAlign = MFI.getMaxAlign(); - // Initialize current frame pointer. const MCInstrDesc &CopyInst = TII.get(isPPC64 ? PPC::OR8 : PPC::OR); - BuildMI(PrologMBB, {MI}, DL, CopyInst, FPReg).addReg(SPReg).addReg(SPReg); // Subroutines to generate .cfi_* directives. auto buildDefCFAReg = [&](MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register Reg) { @@ -1262,89 +1258,218 @@ void PPCFrameLowering::inlineStackProbe(MachineFunction &MF, // Subroutine to store frame pointer and decrease stack pointer by probe size. auto allocateAndProbe = [&](MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int64_t NegSize, - Register NegSizeReg, bool UseDForm) { + Register NegSizeReg, bool UseDForm, + Register StoreReg) { if (UseDForm) BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::STDU : PPC::STWU), SPReg) - .addReg(FPReg) + .addReg(StoreReg) .addImm(NegSize) .addReg(SPReg); else BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg) - .addReg(FPReg) + .addReg(StoreReg) .addReg(SPReg) .addReg(NegSizeReg); }; - // Use FPReg to calculate CFA. - if (needsCFI) - buildDefCFA(PrologMBB, {MI}, FPReg, 0); - // For case HasBP && MaxAlign > 1, we have to align the SP by performing + // Used to probe realignment gap [stackptr - (stackptr % align), stackptr) + // when HasBP && isPPC64. In such scenario, normally we have r0, r1, r12, r30 + // available and r1 is already copied to r30 which is BPReg. So BPReg stores + // the value of stackptr. + // First we have to probe tail interval whose size is less than probesize, + // i.e., [stackptr - (stackptr % align) % probesize, stackptr). At this stage, + // ScratchReg stores the value of ((stackptr % align) % probesize). Then we + // probe each block sized probesize until stackptr meets + // (stackptr - (stackptr % align)). At this stage, ScratchReg is materialized + // as negprobesize. At both stages, TempReg stores the value of + // (stackptr - (stackptr % align)). + auto dynamicProbe = [&](MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, Register ScratchReg, + Register TempReg) { + assert(HasBP && isPPC64 && "Probe alignment part not available"); + assert(isPowerOf2_64(ProbeSize) && "Probe size should be power of 2"); + // ScratchReg = stackptr % align + BuildMI(MBB, MBBI, DL, TII.get(PPC::RLDICL), ScratchReg) + .addReg(BPReg) + .addImm(0) + .addImm(64 - Log2(MaxAlign)); + // TempReg = stackptr - (stackptr % align) + BuildMI(MBB, MBBI, DL, TII.get(PPC::SUBFC8), TempReg) + .addReg(ScratchReg) + .addReg(BPReg); + // ScratchReg = (stackptr % align) % probesize + BuildMI(MBB, MBBI, DL, TII.get(PPC::RLDICL), ScratchReg) + .addReg(ScratchReg) + .addImm(0) + .addImm(64 - Log2(ProbeSize)); + Register CRReg = PPC::CR0; + // If (stackptr % align) % probesize == 0, we should not generate probe + // code. Layout of output assembly kinda like: + // bb.0: + // ... + // cmpldi $scratchreg, 0 + // beq bb.2 + // bb.1: # Probe tail interval + // neg $scratchreg, $scratchreg + // stdux $bpreg, r1, $scratchreg + // bb.2: + // + // cmpd r1, $tempreg + // beq bb.4 + // bb.3: # Loop to probe each block + // stdux $bpreg, r1, $scratchreg + // cmpd r1, $tempreg + // bne bb.3 + // bb.4: + // ... + MachineFunction::iterator MBBInsertPoint = std::next(MBB.getIterator()); + MachineBasicBlock *ProbeResidualMBB = MF.CreateMachineBasicBlock(ProbedBB); + MF.insert(MBBInsertPoint, ProbeResidualMBB); + MachineBasicBlock *ProbeLoopPreHeaderMBB = + MF.CreateMachineBasicBlock(ProbedBB); + MF.insert(MBBInsertPoint, ProbeLoopPreHeaderMBB); + MachineBasicBlock *ProbeLoopBodyMBB = MF.CreateMachineBasicBlock(ProbedBB); + MF.insert(MBBInsertPoint, ProbeLoopBodyMBB); + MachineBasicBlock *ProbeExitMBB = MF.CreateMachineBasicBlock(ProbedBB); + MF.insert(MBBInsertPoint, ProbeExitMBB); + // bb.4 + ProbeExitMBB->splice(ProbeExitMBB->end(), &MBB, MBBI, MBB.end()); + ProbeExitMBB->transferSuccessorsAndUpdatePHIs(&MBB); + // bb.0 + BuildMI(&MBB, DL, TII.get(PPC::CMPDI), CRReg).addReg(ScratchReg).addImm(0); + BuildMI(&MBB, DL, TII.get(PPC::BCC)) + .addImm(PPC::PRED_EQ) + .addReg(CRReg) + .addMBB(ProbeLoopPreHeaderMBB); + MBB.addSuccessor(ProbeResidualMBB); + MBB.addSuccessor(ProbeLoopPreHeaderMBB); + // bb.1 + BuildMI(ProbeResidualMBB, DL, TII.get(PPC::NEG8), ScratchReg) + .addReg(ScratchReg); + allocateAndProbe(*ProbeResidualMBB, ProbeResidualMBB->end(), 0, ScratchReg, + false, BPReg); + ProbeResidualMBB->addSuccessor(ProbeLoopPreHeaderMBB); + // bb.2 + MaterializeImm(*ProbeLoopPreHeaderMBB, ProbeLoopPreHeaderMBB->end(), + NegProbeSize, ScratchReg); + BuildMI(ProbeLoopPreHeaderMBB, DL, TII.get(PPC::CMPD), CRReg) + .addReg(SPReg) + .addReg(TempReg); + BuildMI(ProbeLoopPreHeaderMBB, DL, TII.get(PPC::BCC)) + .addImm(PPC::PRED_EQ) + .addReg(CRReg) + .addMBB(ProbeExitMBB); + ProbeLoopPreHeaderMBB->addSuccessor(ProbeLoopBodyMBB); + ProbeLoopPreHeaderMBB->addSuccessor(ProbeExitMBB); + // bb.3 + allocateAndProbe(*ProbeLoopBodyMBB, ProbeLoopBodyMBB->end(), 0, ScratchReg, + false, BPReg); + BuildMI(ProbeLoopBodyMBB, DL, TII.get(PPC::CMPD), CRReg) + .addReg(SPReg) + .addReg(TempReg); + BuildMI(ProbeLoopBodyMBB, DL, TII.get(PPC::BCC)) + .addImm(PPC::PRED_NE) + .addReg(CRReg) + .addMBB(ProbeLoopBodyMBB); + ProbeLoopBodyMBB->addSuccessor(ProbeExitMBB); + ProbeLoopBodyMBB->addSuccessor(ProbeLoopBodyMBB); + // Update liveins. + recomputeLiveIns(*ProbeResidualMBB); + recomputeLiveIns(*ProbeLoopPreHeaderMBB); + recomputeLiveIns(*ProbeLoopBodyMBB); + recomputeLiveIns(*ProbeExitMBB); + return ProbeExitMBB; + }; + // For case HasBP && MaxAlign > 1, we have to realign the SP by performing // SP = SP - SP % MaxAlign. if (HasBP && MaxAlign > 1) { - if (isPPC64) - BuildMI(PrologMBB, {MI}, DL, TII.get(PPC::RLDICL), ScratchReg) - .addReg(FPReg) - .addImm(0) - .addImm(64 - Log2(MaxAlign)); - else - BuildMI(PrologMBB, {MI}, DL, TII.get(PPC::RLWINM), ScratchReg) + // FIXME: Currently only probe the gap [stackptr & alignmask, stackptr) in + // 64-bit mode. + if (isPPC64) { + // Use BPReg to calculate CFA. + if (needsCFI) + buildDefCFA(*CurrentMBB, {MI}, BPReg, 0); + // Since we have SPReg copied to BPReg at the moment, FPReg can be used as + // TempReg. + Register TempReg = FPReg; + CurrentMBB = dynamicProbe(*CurrentMBB, {MI}, ScratchReg, TempReg); + // Copy BPReg to FPReg to meet the definition of PROBED_STACKALLOC_64. + BuildMI(*CurrentMBB, {MI}, DL, CopyInst, FPReg) + .addReg(BPReg) + .addReg(BPReg); + } else { + // Initialize current frame pointer. + BuildMI(*CurrentMBB, {MI}, DL, CopyInst, FPReg) + .addReg(SPReg) + .addReg(SPReg); + // Use FPReg to calculate CFA. + if (needsCFI) + buildDefCFA(*CurrentMBB, {MI}, FPReg, 0); + BuildMI(*CurrentMBB, {MI}, DL, TII.get(PPC::RLWINM), ScratchReg) .addReg(FPReg) .addImm(0) .addImm(32 - Log2(MaxAlign)) .addImm(31); - BuildMI(PrologMBB, {MI}, DL, TII.get(isPPC64 ? PPC::SUBFC8 : PPC::SUBFC), - SPReg) - .addReg(ScratchReg) - .addReg(SPReg); + BuildMI(*CurrentMBB, {MI}, DL, TII.get(PPC::SUBFC), SPReg) + .addReg(ScratchReg) + .addReg(SPReg); + } + } else { + // Initialize current frame pointer. + BuildMI(*CurrentMBB, {MI}, DL, CopyInst, FPReg).addReg(SPReg).addReg(SPReg); + // Use FPReg to calculate CFA. + if (needsCFI) + buildDefCFA(*CurrentMBB, {MI}, FPReg, 0); } // Probe residual part. if (NegResidualSize) { bool ResidualUseDForm = CanUseDForm(NegResidualSize); if (!ResidualUseDForm) - MaterializeImm(PrologMBB, {MI}, NegResidualSize, ScratchReg); - allocateAndProbe(PrologMBB, {MI}, NegResidualSize, ScratchReg, - ResidualUseDForm); + MaterializeImm(*CurrentMBB, {MI}, NegResidualSize, ScratchReg); + allocateAndProbe(*CurrentMBB, {MI}, NegResidualSize, ScratchReg, + ResidualUseDForm, FPReg); } bool UseDForm = CanUseDForm(NegProbeSize); // If number of blocks is small, just probe them directly. if (NumBlocks < 3) { if (!UseDForm) - MaterializeImm(PrologMBB, {MI}, NegProbeSize, ScratchReg); + MaterializeImm(*CurrentMBB, {MI}, NegProbeSize, ScratchReg); for (int i = 0; i < NumBlocks; ++i) - allocateAndProbe(PrologMBB, {MI}, NegProbeSize, ScratchReg, UseDForm); + allocateAndProbe(*CurrentMBB, {MI}, NegProbeSize, ScratchReg, UseDForm, + FPReg); if (needsCFI) { // Restore using SPReg to calculate CFA. - buildDefCFAReg(PrologMBB, {MI}, SPReg); + buildDefCFAReg(*CurrentMBB, {MI}, SPReg); } } else { // Since CTR is a volatile register and current shrinkwrap implementation // won't choose an MBB in a loop as the PrologMBB, it's safe to synthesize a // CTR loop to probe. // Calculate trip count and stores it in CTRReg. - MaterializeImm(PrologMBB, {MI}, NumBlocks, ScratchReg); - BuildMI(PrologMBB, {MI}, DL, TII.get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR)) + MaterializeImm(*CurrentMBB, {MI}, NumBlocks, ScratchReg); + BuildMI(*CurrentMBB, {MI}, DL, TII.get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR)) .addReg(ScratchReg, RegState::Kill); if (!UseDForm) - MaterializeImm(PrologMBB, {MI}, NegProbeSize, ScratchReg); + MaterializeImm(*CurrentMBB, {MI}, NegProbeSize, ScratchReg); // Create MBBs of the loop. MachineFunction::iterator MBBInsertPoint = - std::next(PrologMBB.getIterator()); + std::next(CurrentMBB->getIterator()); MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(ProbedBB); MF.insert(MBBInsertPoint, LoopMBB); MachineBasicBlock *ExitMBB = MF.CreateMachineBasicBlock(ProbedBB); MF.insert(MBBInsertPoint, ExitMBB); // Synthesize the loop body. allocateAndProbe(*LoopMBB, LoopMBB->end(), NegProbeSize, ScratchReg, - UseDForm); + UseDForm, FPReg); BuildMI(LoopMBB, DL, TII.get(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)) .addMBB(LoopMBB); LoopMBB->addSuccessor(ExitMBB); LoopMBB->addSuccessor(LoopMBB); // Synthesize the exit MBB. - ExitMBB->splice(ExitMBB->end(), &PrologMBB, + ExitMBB->splice(ExitMBB->end(), CurrentMBB, std::next(MachineBasicBlock::iterator(MI)), - PrologMBB.end()); - ExitMBB->transferSuccessorsAndUpdatePHIs(&PrologMBB); - PrologMBB.addSuccessor(LoopMBB); + CurrentMBB->end()); + ExitMBB->transferSuccessorsAndUpdatePHIs(CurrentMBB); + CurrentMBB->addSuccessor(LoopMBB); if (needsCFI) { // Restore using SPReg to calculate CFA. buildDefCFAReg(*ExitMBB, ExitMBB->begin(), SPReg); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index d6841fbe8f77d..2d8dfb63f19c2 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -121,6 +121,11 @@ cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden); static cl::opt UseAbsoluteJumpTables("ppc-use-absolute-jumptables", cl::desc("use absolute jump tables on ppc"), cl::Hidden); +// TODO - Remove this option if soft fp128 has been fully supported . +static cl::opt + EnableSoftFP128("enable-soft-fp128", + cl::desc("temp option to enable soft fp128"), cl::Hidden); + STATISTIC(NumTailCalls, "Number of tail calls"); STATISTIC(NumSiblingCalls, "Number of sibling calls"); STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM"); @@ -801,9 +806,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::UMIN, MVT::v2i64, Expand); } - for (auto VT : {MVT::v2i64, MVT::v4i32, MVT::v8i16, MVT::v16i8}) - setOperationAction(ISD::ABS, VT, Custom); - // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle // with merges, splats, etc. setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); @@ -836,11 +838,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); - // Without hasP8Altivec set, v2i64 SMAX isn't available. - // But ABS custom lowering requires SMAX support. - if (!Subtarget.hasP8Altivec()) - setOperationAction(ISD::ABS, MVT::v2i64, Expand); - // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8. setOperationAction(ISD::ROTL, MVT::v1i128, Custom); // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w). @@ -1161,6 +1158,32 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::BSWAP, MVT::v4i32, Legal); setOperationAction(ISD::BSWAP, MVT::v2i64, Legal); setOperationAction(ISD::BSWAP, MVT::v1i128, Legal); + } else if (Subtarget.hasAltivec() && EnableSoftFP128) { + addRegisterClass(MVT::f128, &PPC::VRRCRegClass); + + for (MVT FPT : MVT::fp_valuetypes()) + setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand); + + setOperationAction(ISD::LOAD, MVT::f128, Promote); + setOperationAction(ISD::STORE, MVT::f128, Promote); + + AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32); + AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32); + + setOperationAction(ISD::FADD, MVT::f128, Expand); + setOperationAction(ISD::FSUB, MVT::f128, Expand); + setOperationAction(ISD::FMUL, MVT::f128, Expand); + setOperationAction(ISD::FDIV, MVT::f128, Expand); + setOperationAction(ISD::FNEG, MVT::f128, Expand); + setOperationAction(ISD::FABS, MVT::f128, Expand); + setOperationAction(ISD::FSIN, MVT::f128, Expand); + setOperationAction(ISD::FCOS, MVT::f128, Expand); + setOperationAction(ISD::FPOW, MVT::f128, Expand); + setOperationAction(ISD::FPOWI, MVT::f128, Expand); + setOperationAction(ISD::FREM, MVT::f128, Expand); + setOperationAction(ISD::FSQRT, MVT::f128, Expand); + setOperationAction(ISD::FMA, MVT::f128, Expand); + setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); } if (Subtarget.hasP9Altivec()) { @@ -1416,6 +1439,10 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { return "PPCISD::FP_TO_SINT_IN_VSR"; case PPCISD::FRE: return "PPCISD::FRE"; case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE"; + case PPCISD::FTSQRT: + return "PPCISD::FTSQRT"; + case PPCISD::FSQRT: + return "PPCISD::FSQRT"; case PPCISD::STFIWX: return "PPCISD::STFIWX"; case PPCISD::VPERM: return "PPCISD::VPERM"; case PPCISD::XXSPLT: return "PPCISD::XXSPLT"; @@ -6968,9 +6995,10 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT, const Align PtrAlign = IsPPC64 ? Align(8) : Align(4); const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; - assert((!ValVT.isInteger() || - (ValVT.getFixedSizeInBits() <= RegVT.getFixedSizeInBits())) && - "Integer argument exceeds register size: should have been legalized"); + if (ValVT.isVector() && !State.getMachineFunction() + .getTarget() + .Options.EnableAIXExtendedAltivecABI) + report_fatal_error("the default Altivec AIX ABI is not yet supported"); if (ValVT == MVT::f128) report_fatal_error("f128 is unimplemented on AIX."); @@ -6978,9 +7006,6 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT, if (ArgFlags.isNest()) report_fatal_error("Nest arguments are unimplemented."); - if (ValVT.isVector() || LocVT.isVector()) - report_fatal_error("Vector arguments are unimplemented on AIX."); - static const MCPhysReg GPR_32[] = {// 32-bit registers. PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10}; @@ -6988,6 +7013,11 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10}; + static const MCPhysReg VR[] = {// Vector registers. + PPC::V2, PPC::V3, PPC::V4, PPC::V5, + PPC::V6, PPC::V7, PPC::V8, PPC::V9, + PPC::V10, PPC::V11, PPC::V12, PPC::V13}; + if (ArgFlags.isByVal()) { if (ArgFlags.getNonZeroByValAlign() > PtrAlign) report_fatal_error("Pass-by-value arguments with alignment greater than " @@ -7083,6 +7113,25 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT, return false; } + case MVT::v4f32: + case MVT::v4i32: + case MVT::v8i16: + case MVT::v16i8: + case MVT::v2i64: + case MVT::v2f64: + case MVT::v1i128: { + if (State.isVarArg()) + report_fatal_error( + "variadic arguments for vector types are unimplemented for AIX"); + + if (unsigned VReg = State.AllocateReg(VR)) + State.addLoc(CCValAssign::getReg(ValNo, ValVT, VReg, LocVT, LocInfo)); + else { + report_fatal_error( + "passing vector parameters to the stack is unimplemented for AIX"); + } + return false; + } } return true; } @@ -7103,6 +7152,14 @@ static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT, return &PPC::F4RCRegClass; case MVT::f64: return &PPC::F8RCRegClass; + case MVT::v4f32: + case MVT::v4i32: + case MVT::v8i16: + case MVT::v16i8: + case MVT::v2i64: + case MVT::v2f64: + case MVT::v1i128: + return &PPC::VRRCRegClass; } } @@ -7219,6 +7276,9 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX( CCValAssign &VA = ArgLocs[I++]; MVT LocVT = VA.getLocVT(); ISD::ArgFlagsTy Flags = Ins[VA.getValNo()].Flags; + if (VA.isMemLoc() && VA.getValVT().isVector()) + report_fatal_error( + "passing vector parameters to the stack is unimplemented for AIX"); // For compatibility with the AIX XL compiler, the float args in the // parameter save area are initialized even if the argument is available @@ -7416,8 +7476,6 @@ SDValue PPCTargetLowering::LowerCall_AIX( const PPCSubtarget& Subtarget = static_cast(DAG.getSubtarget()); - if (Subtarget.hasAltivec()) - report_fatal_error("Altivec support is unimplemented on AIX."); MachineFunction &MF = DAG.getMachineFunction(); SmallVector ArgLocs; @@ -7563,6 +7621,10 @@ SDValue PPCTargetLowering::LowerCall_AIX( const MVT LocVT = VA.getLocVT(); const MVT ValVT = VA.getValVT(); + if (VA.isMemLoc() && VA.getValVT().isVector()) + report_fatal_error( + "passing vector parameters to the stack is unimplemented for AIX"); + switch (VA.getLocInfo()) { default: report_fatal_error("Unexpected argument extension type."); @@ -7707,10 +7769,6 @@ PPCTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, SDValue Arg = OutVals[RealResIdx]; - if (Subtarget.isAIXABI() && - (VA.getLocVT().isVector() || VA.getValVT().isVector())) - report_fatal_error("Returning vector types not yet supported on AIX."); - switch (VA.getLocInfo()) { default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; @@ -8413,6 +8471,13 @@ bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT, if (LD->getMemoryVT() != MemVT) return false; + // If the result of the load is an illegal type, then we can't build a + // valid chain for reuse since the legalised loads and token factor node that + // ties the legalised loads together uses a different output chain then the + // illegal load. + if (!isTypeLegal(LD->getValueType(0))) + return false; + RLI.Ptr = LD->getBasePtr(); if (LD->isIndexed() && !LD->getOffset().isUndef()) { assert(LD->getAddressingMode() == ISD::PRE_INC && @@ -10836,44 +10901,6 @@ SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { } } -SDValue PPCTargetLowering::LowerABS(SDValue Op, SelectionDAG &DAG) const { - - assert(Op.getOpcode() == ISD::ABS && "Should only be called for ISD::ABS"); - - EVT VT = Op.getValueType(); - assert(VT.isVector() && - "Only set vector abs as custom, scalar abs shouldn't reach here!"); - assert((VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || - VT == MVT::v16i8) && - "Unexpected vector element type!"); - assert((VT != MVT::v2i64 || Subtarget.hasP8Altivec()) && - "Current subtarget doesn't support smax v2i64!"); - - // For vector abs, it can be lowered to: - // abs x - // ==> - // y = -x - // smax(x, y) - - SDLoc dl(Op); - SDValue X = Op.getOperand(0); - SDValue Zero = DAG.getConstant(0, dl, VT); - SDValue Y = DAG.getNode(ISD::SUB, dl, VT, Zero, X); - - // SMAX patch https://reviews.llvm.org/D47332 - // hasn't landed yet, so use intrinsic first here. - // TODO: Should use SMAX directly once SMAX patch landed - Intrinsic::ID BifID = Intrinsic::ppc_altivec_vmaxsw; - if (VT == MVT::v2i64) - BifID = Intrinsic::ppc_altivec_vmaxsd; - else if (VT == MVT::v8i16) - BifID = Intrinsic::ppc_altivec_vmaxsh; - else if (VT == MVT::v16i8) - BifID = Intrinsic::ppc_altivec_vmaxsb; - - return BuildIntrinsicOp(BifID, X, Y, DAG, dl, VT); -} - // Custom lowering for fpext vf32 to v2f64 SDValue PPCTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const { @@ -11009,7 +11036,6 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); case ISD::MUL: return LowerMUL(Op, DAG); - case ISD::ABS: return LowerABS(Op, DAG); case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); case ISD::ROTL: return LowerROTL(Op, DAG); @@ -11031,28 +11057,6 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { } } -void PPCTargetLowering::LowerOperationWrapper(SDNode *N, - SmallVectorImpl &Results, - SelectionDAG &DAG) const { - SDValue Res = LowerOperation(SDValue(N, 0), DAG); - - if (!Res.getNode()) - return; - - // Take the return value as-is if original node has only one result. - if (N->getNumValues() == 1) { - Results.push_back(Res); - return; - } - - // New node should have the same number of results. - assert((N->getNumValues() == Res->getNumValues()) && - "Lowering returned the wrong number of results!"); - - for (unsigned i = 0; i < N->getNumValues(); ++i) - Results.push_back(Res.getValue(i)); -} - void PPCTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results, SelectionDAG &DAG) const { @@ -12732,6 +12736,44 @@ static int getEstimateRefinementSteps(EVT VT, const PPCSubtarget &Subtarget) { return RefinementSteps; } +SDValue PPCTargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG, + const DenormalMode &Mode) const { + // TODO - add support for v2f64/v4f32 + EVT VT = Op.getValueType(); + if (VT != MVT::f64) + return SDValue(); + + SDLoc DL(Op); + // The output register of FTSQRT is CR field. + SDValue FTSQRT = DAG.getNode(PPCISD::FTSQRT, DL, MVT::i32, Op); + // ftsqrt BF,FRB + // Let e_b be the unbiased exponent of the double-precision + // floating-point operand in register FRB. + // fe_flag is set to 1 if either of the following conditions occurs. + // - The double-precision floating-point operand in register FRB is a zero, + // a NaN, or an infinity, or a negative value. + // - e_b is less than or equal to -970. + // Otherwise fe_flag is set to 0. + // Both VSX and non-VSX versions would set EQ bit in the CR if the number is + // not eligible for iteration. (zero/negative/infinity/nan or unbiased + // exponent is less than -970) + SDValue SRIdxVal = DAG.getTargetConstant(PPC::sub_eq, DL, MVT::i32); + return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::i1, + FTSQRT, SRIdxVal), + 0); +} + +SDValue +PPCTargetLowering::getSqrtResultForDenormInput(SDValue Op, + SelectionDAG &DAG) const { + // TODO - add support for v2f64/v4f32 + EVT VT = Op.getValueType(); + if (VT != MVT::f64) + return TargetLowering::getSqrtResultForDenormInput(Op, DAG); + + return DAG.getNode(PPCISD::FSQRT, SDLoc(Op), VT, Op); +} + SDValue PPCTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index ca7c68624c68a..63b59dd916044 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -89,6 +89,12 @@ namespace llvm { FRE, FRSQRTE, + /// Test instruction for software square root. + FTSQRT, + + /// Square root instruction. + FSQRT, + /// VPERM - The PPC VPERM Instruction. /// VPERM, @@ -788,12 +794,6 @@ namespace llvm { /// SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; - /// LowerOperationWrapper - Place custom new result values for node in - /// Results. - void LowerOperationWrapper(SDNode *N, - SmallVectorImpl &Results, - SelectionDAG &DAG) const override; - /// ReplaceNodeResults - Replace the results of node with an illegal result /// type with new values built out of custom code. /// @@ -1160,7 +1160,6 @@ namespace llvm { SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; @@ -1289,6 +1288,10 @@ namespace llvm { bool Reciprocal) const override; SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override; + SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, + const DenormalMode &Mode) const override; + SDValue getSqrtResultForDenormInput(SDValue Operand, + SelectionDAG &DAG) const override; unsigned combineRepeatedFPDivisors() const override; SDValue diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index 1edc801205b7a..eaf20fdc0173d 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -1265,17 +1265,36 @@ def ADDItlsgdL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm6 [(set i64:$rD, (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, isPPC64; -// LR8 is a true define, while the rest of the Defs are clobbers. X3 is + +class GETtlsADDRPseudo : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), + asmstr, + [(set i64:$rD, + (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, + isPPC64; +class GETtlsldADDRPseudo : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), + asmstr, + [(set i64:$rD, + (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, + isPPC64; + +let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1 in { +// LR8 is a true define, while the rest of the Defs are clobbers. X3 is // explicitly defined when this op is created, so not mentioned here. // This is lowered to BL8_NOP_TLS by the assembly printer, so the size must be // correct because the branch select pass is relying on it. -let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8, - Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in -def GETtlsADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), - "#GETtlsADDR", - [(set i64:$rD, - (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, - isPPC64; +let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in +def GETtlsADDR : GETtlsADDRPseudo <"#GETtlsADDR">; +let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7], Size = 8 in +def GETtlsADDRPCREL : GETtlsADDRPseudo <"#GETtlsADDRPCREL">; + +// LR8 is a true define, while the rest of the Defs are clobbers. X3 is +// explicitly defined when this op is created, so not mentioned here. +let Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in +def GETtlsldADDR : GETtlsldADDRPseudo <"#GETtlsldADDR">; +let Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in +def GETtlsldADDRPCREL : GETtlsldADDRPseudo <"#GETtlsldADDRPCREL">; +} + // Combined op for ADDItlsgdL and GETtlsADDR, late expanded. X3 and LR8 // are true defines while the rest of the Defs are clobbers. let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, @@ -1299,15 +1318,6 @@ def ADDItlsldL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm6 [(set i64:$rD, (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, isPPC64; -// LR8 is a true define, while the rest of the Defs are clobbers. X3 is -// explicitly defined when this op is created, so not mentioned here. -let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, - Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in -def GETtlsldADDR : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), - "#GETtlsldADDR", - [(set i64:$rD, - (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, - isPPC64; // Combined op for ADDItlsldL and GETtlsADDR, late expanded. X3 and LR8 // are true defines, while the rest of the Defs are clobbers. let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index bda00b89892f2..599f0add2700b 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -933,6 +933,18 @@ def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>; def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>; def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>; +def : Pat<(f128 (bitconvert (v16i8 VRRC:$src))), (f128 VRRC:$src)>; +def : Pat<(f128 (bitconvert (v8i16 VRRC:$src))), (f128 VRRC:$src)>; +def : Pat<(f128 (bitconvert (v4i32 VRRC:$src))), (f128 VRRC:$src)>; +def : Pat<(f128 (bitconvert (v4f32 VRRC:$src))), (f128 VRRC:$src)>; +def : Pat<(f128 (bitconvert (v2f64 VRRC:$src))), (f128 VRRC:$src)>; + +def : Pat<(v16i8 (bitconvert (f128 VRRC:$src))), (v16i8 VRRC:$src)>; +def : Pat<(v8i16 (bitconvert (f128 VRRC:$src))), (v8i16 VRRC:$src)>; +def : Pat<(v4i32 (bitconvert (f128 VRRC:$src))), (v4i32 VRRC:$src)>; +def : Pat<(v4f32 (bitconvert (f128 VRRC:$src))), (v4f32 VRRC:$src)>; +def : Pat<(v2f64 (bitconvert (f128 VRRC:$src))), (v2f64 VRRC:$src)>; + // Max/Min def : Pat<(v16i8 (umax v16i8:$src1, v16i8:$src2)), (v16i8 (VMAXUB $src1, $src2))>; diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td index 5ff5fc78326ba..646efe64a22c7 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td @@ -637,9 +637,10 @@ class XForm_17 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, } class XForm_17a opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, - InstrItinClass itin> + InstrItinClass itin, list pattern> : XForm_17 { let FRA = 0; + let Pattern = pattern; } class XForm_18 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 2de6a77540153..45587504df569 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -3231,18 +3231,64 @@ bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI, return false; } -bool PPCInstrInfo::combineRLWINM(MachineInstr &MI, - MachineInstr **ToErase) const { +// This function tries to combine two RLWINMs. We not only perform such +// optimization in SSA, but also after RA, since some RLWINM is generated after +// RA. +bool PPCInstrInfo::simplifyRotateAndMaskInstr(MachineInstr &MI, + MachineInstr *&ToErase) const { + bool Is64Bit = false; + switch (MI.getOpcode()) { + case PPC::RLWINM: + case PPC::RLWINM_rec: + break; + case PPC::RLWINM8: + case PPC::RLWINM8_rec: + Is64Bit = true; + break; + default: + return false; + } MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo(); - unsigned FoldingReg = MI.getOperand(1).getReg(); - if (!Register::isVirtualRegister(FoldingReg)) + Register FoldingReg = MI.getOperand(1).getReg(); + MachineInstr *SrcMI = nullptr; + bool CanErase = false; + bool OtherIntermediateUse = true; + if (MRI->isSSA()) { + if (!Register::isVirtualRegister(FoldingReg)) + return false; + SrcMI = MRI->getVRegDef(FoldingReg); + } else { + SrcMI = getDefMIPostRA(FoldingReg, MI, OtherIntermediateUse); + } + if (!SrcMI) return false; - MachineInstr *SrcMI = MRI->getVRegDef(FoldingReg); - if (SrcMI->getOpcode() != PPC::RLWINM && - SrcMI->getOpcode() != PPC::RLWINM_rec && - SrcMI->getOpcode() != PPC::RLWINM8 && - SrcMI->getOpcode() != PPC::RLWINM8_rec) + // TODO: The pairs of RLWINM8(RLWINM) or RLWINM(RLWINM8) never occur before + // RA, but after RA. And We can fold RLWINM8(RLWINM) -> RLWINM8, or + // RLWINM(RLWINM8) -> RLWINM. + switch (SrcMI->getOpcode()) { + case PPC::RLWINM: + case PPC::RLWINM_rec: + if (Is64Bit) + return false; + break; + case PPC::RLWINM8: + case PPC::RLWINM8_rec: + if (!Is64Bit) + return false; + break; + default: return false; + } + if (MRI->isSSA()) { + CanErase = !SrcMI->hasImplicitDef() && MRI->hasOneNonDBGUse(FoldingReg); + } else { + CanErase = !OtherIntermediateUse && MI.getOperand(1).isKill() && + !SrcMI->hasImplicitDef(); + // In post-RA, if SrcMI also defines the register to be forwarded, we can + // only do the folding if SrcMI is going to be erased. + if (!CanErase && SrcMI->definesRegister(SrcMI->getOperand(1).getReg())) + return false; + } assert((MI.getOperand(2).isImm() && MI.getOperand(3).isImm() && MI.getOperand(4).isImm() && SrcMI->getOperand(2).isImm() && SrcMI->getOperand(3).isImm() && SrcMI->getOperand(4).isImm()) && @@ -3253,7 +3299,6 @@ bool PPCInstrInfo::combineRLWINM(MachineInstr &MI, uint64_t MBMI = MI.getOperand(3).getImm(); uint64_t MESrc = SrcMI->getOperand(4).getImm(); uint64_t MEMI = MI.getOperand(4).getImm(); - assert((MEMI < 32 && MESrc < 32 && MBMI < 32 && MBSrc < 32) && "Invalid PPC::RLWINM Instruction!"); // If MBMI is bigger than MEMI, we always can not get run of ones. @@ -3297,8 +3342,6 @@ bool PPCInstrInfo::combineRLWINM(MachineInstr &MI, // If final mask is 0, MI result should be 0 too. if (FinalMask.isNullValue()) { - bool Is64Bit = - (MI.getOpcode() == PPC::RLWINM8 || MI.getOpcode() == PPC::RLWINM8_rec); Simplified = true; LLVM_DEBUG(dbgs() << "Replace Instr: "); LLVM_DEBUG(MI.dump()); @@ -3356,12 +3399,10 @@ bool PPCInstrInfo::combineRLWINM(MachineInstr &MI, LLVM_DEBUG(dbgs() << "To: "); LLVM_DEBUG(MI.dump()); } - if (Simplified & MRI->use_nodbg_empty(FoldingReg) && - !SrcMI->hasImplicitDef()) { - // If FoldingReg has no non-debug use and it has no implicit def (it - // is not RLWINMO or RLWINM8o), it's safe to delete its def SrcMI. - // Otherwise keep it. - *ToErase = SrcMI; + if (Simplified && CanErase) { + // If SrcMI has no implicit def, and FoldingReg has no non-debug use or + // its flag is "killed", it's safe to delete SrcMI. Otherwise keep it. + ToErase = SrcMI; LLVM_DEBUG(dbgs() << "Delete dead instruction: "); LLVM_DEBUG(SrcMI->dump()); } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h index c633916e79744..68bd3df6168ac 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -585,7 +585,8 @@ class PPCInstrInfo : public PPCGenInstrInfo { bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef = nullptr) const; bool foldFrameOffset(MachineInstr &MI) const; - bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const; + bool simplifyRotateAndMaskInstr(MachineInstr &MI, + MachineInstr *&ToErase) const; bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const; bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const; bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 2e77d04d4a79e..1496accf83d81 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -74,6 +74,9 @@ def SDT_PPCcondbr : SDTypeProfile<0, 3, [ SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> ]>; +def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [ + SDTCisVT<0, i32>]>; + def SDT_PPClbrx : SDTypeProfile<1, 2, [ SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> ]>; @@ -124,6 +127,8 @@ def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; +def PPCfsqrt : SDNode<"PPCISD::FSQRT", SDTFPUnaryOp, []>; +def PPCftsqrt : SDNode<"PPCISD::FTSQRT", SDT_PPCFtsqrt,[]>; def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; @@ -2643,7 +2648,8 @@ let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in { def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), "ftdiv $crD, $fA, $fB", IIC_FPCompare>; def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB), - "ftsqrt $crD, $fB", IIC_FPCompare>; + "ftsqrt $crD, $fB", IIC_FPCompare, + [(set i32:$crD, (PPCftsqrt f64:$fB))]>; let mayRaiseFPException = 1, hasSideEffects = 0 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in @@ -2701,6 +2707,8 @@ let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in { } } +def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>; + /// Note that FMR is defined as pseudo-ops on the PPC970 because they are /// often coalesced away and we don't want the dispatch group builder to think /// that they will fill slots (which could cause the load of a LSU reject to diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 1ffbd405d87aa..e778ca4be6b5b 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -629,7 +629,8 @@ let hasSideEffects = 0 in { "xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>; def XSTSQRTDP : XX2Form_1<60, 106, (outs crrc:$crD), (ins vsfrc:$XB), - "xstsqrtdp $crD, $XB", IIC_FPCompare, []>; + "xstsqrtdp $crD, $XB", IIC_FPCompare, + [(set i32:$crD, (PPCftsqrt f64:$XB))]>; def XVTDIVDP : XX3Form_1<60, 125, (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB), "xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>; @@ -2462,6 +2463,8 @@ def : Pat<(fneg (PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C)), def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, (fneg v4f32:$C)), (XVNMADDASP $C, $A, $B)>; +def : Pat<(PPCfsqrt f64:$frA), (XSSQRTDP $frA)>; + def : Pat<(v2f64 (bitconvert v4f32:$A)), (COPY_TO_REGCLASS $A, VSRC)>; def : Pat<(v2f64 (bitconvert v4i32:$A)), diff --git a/llvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp b/llvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp index a61e1f83705e6..27b2c9a628d09 100644 --- a/llvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp +++ b/llvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp @@ -105,7 +105,7 @@ bool PPCLowerMASSVEntries::handlePowSpecialCases(CallInst *CI, Function &Func, return false; if (Constant *Exp = dyn_cast(CI->getArgOperand(1))) - if (ConstantFP *CFP = dyn_cast(Exp->getSplatValue())) { + if (ConstantFP *CFP = dyn_cast_or_null(Exp->getSplatValue())) { // If the argument is 0.75 or 0.25 it is cheaper to turn it into pow // intrinsic so that it could be optimzed as sequence of sqrt's. if (!CI->hasNoInfs() || !CI->hasApproxFunc()) diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp index 3fd02bc185c98..827d3c4693b95 100644 --- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp @@ -848,7 +848,7 @@ bool PPCMIPeephole::simplifyCode(void) { case PPC::RLWINM_rec: case PPC::RLWINM8: case PPC::RLWINM8_rec: { - Simplified = TII->combineRLWINM(MI, &ToErase); + Simplified = TII->simplifyRotateAndMaskInstr(MI, ToErase); if (Simplified) ++NumRotatesCollapsed; break; diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp index 04749cdd61c41..f3def378a93c5 100644 --- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp @@ -37,6 +37,8 @@ STATISTIC(NumberOfSelfCopies, "Number of self copy instructions eliminated"); STATISTIC(NumFrameOffFoldInPreEmit, "Number of folding frame offset by using r+r in pre-emit peephole"); +STATISTIC(NumRotateInstrFoldInPreEmit, + "Number of folding Rotate instructions in pre-emit peephole"); static cl::opt EnablePCRelLinkerOpt("ppc-pcrel-linker-opt", cl::Hidden, cl::init(true), @@ -472,6 +474,13 @@ static bool hasPCRelativeForm(MachineInstr &Use) { LLVM_DEBUG(dbgs() << "Frame offset folding by using index form: "); LLVM_DEBUG(MI.dump()); } + MachineInstr *ToErase = nullptr; + if (TII->simplifyRotateAndMaskInstr(MI, ToErase)) { + Changed = true; + NumRotateInstrFoldInPreEmit++; + if (ToErase) + InstrsToErase.push_back(ToErase); + } } // Eliminate conditional branch based on a constant CR bit by diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index 7dd495c1f0f88..03672f40b2af6 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -156,6 +156,10 @@ PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) const MCPhysReg* PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { const PPCSubtarget &Subtarget = MF->getSubtarget(); + if (Subtarget.isAIXABI() && + (Subtarget.hasAltivec() && !TM.getAIXExtendedAltivecABI())) + report_fatal_error("the default AIX Altivec ABI is not yet " + "supported."); if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) { if (!TM.isPPC64() && Subtarget.isAIXABI()) report_fatal_error("AnyReg unimplemented on 32-bit AIX."); @@ -202,8 +206,11 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList; } // 32-bit targets. - if (Subtarget.isAIXABI()) + if (Subtarget.isAIXABI()) { + if (Subtarget.hasAltivec()) + return CSR_AIX32_Altivec_SaveList; return CSR_AIX32_SaveList; + } if (Subtarget.hasAltivec()) return CSR_SVR432_Altivec_SaveList; else if (Subtarget.hasSPE()) @@ -224,8 +231,10 @@ PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, } if (Subtarget.isAIXABI()) { - assert(!Subtarget.hasAltivec() && "Altivec is not implemented on AIX yet."); - return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask; + return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask + : CSR_PPC64_RegMask) + : (Subtarget.hasAltivec() ? CSR_AIX32_Altivec_RegMask + : CSR_AIX32_RegMask); } if (CC == CallingConv::Cold) { diff --git a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp index 3c1262bab1569..43dcc5844c4e6 100644 --- a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp +++ b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp @@ -111,8 +111,8 @@ namespace { Opc1 = PPC::PADDI8pc; Opc2 = MI.getOperand(2).getTargetFlags() == PPCII::MO_GOT_TLSGD_PCREL_FLAG - ? PPC::GETtlsADDR - : PPC::GETtlsldADDR; + ? PPC::GETtlsADDRPCREL + : PPC::GETtlsldADDRPCREL; } // We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 2ab8ba8fe704e..f8093ff6a4406 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -181,8 +181,8 @@ def IsRV32 : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate<(all_of (not Feature64Bit)), "RV32I Base Instruction Set">; +defvar RV32 = DefaultMode; def RV64 : HwMode<"+64bit">; -def RV32 : HwMode<"-64bit">; def FeatureRV32E : SubtargetFeature<"e", "IsRV32E", "true", diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index 439f138defcdc..9222146c5909d 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -325,6 +325,11 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, // to determine the end of the prologue. DebugLoc DL; + // All calls are tail calls in GHC calling conv, and functions have no + // prologue/epilogue. + if (MF.getFunction().getCallingConv() == CallingConv::GHC) + return; + // Emit prologue for shadow call stack. emitSCSPrologue(MF, MBB, MBBI, DL); @@ -500,6 +505,11 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, Register FPReg = getFPReg(STI); Register SPReg = getSPReg(STI); + // All calls are tail calls in GHC calling conv, and functions have no + // prologue/epilogue. + if (MF.getFunction().getCallingConv() == CallingConv::GHC) + return; + // Get the insert location for the epilogue. If there were no terminators in // the block, get the last instruction. MachineBasicBlock::iterator MBBI = MBB.end(); diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 765775c035876..0f455a58f35cc 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -376,62 +376,6 @@ bool RISCVDAGToDAGISel::SelectSROIW(SDValue N, SDValue &RS1, SDValue &Shamt) { return true; } -// Check that it is a RORIW (i32 Right Rotate Immediate on RV64). -// We first check that it is the right node tree: -// -// (SIGN_EXTEND_INREG (OR (SHL RS1, VC2), -// (SRL (AND RS1, VC3), VC1))) -// -// Then we check that the constant operands respect these constraints: -// -// VC2 == 32 - VC1 -// VC3 | maskTrailingOnes(VC1) == 0xffffffff -// -// being VC1 the Shamt we need, VC2 the complementary of Shamt over 32 -// and VC3 being 0xffffffff after accounting for SimplifyDemandedBits removing -// some bits due to the right shift. - -bool RISCVDAGToDAGISel::SelectRORIW(SDValue N, SDValue &RS1, SDValue &Shamt) { - if (N.getOpcode() == ISD::SIGN_EXTEND_INREG && - Subtarget->getXLenVT() == MVT::i64 && - cast(N.getOperand(1))->getVT() == MVT::i32) { - if (N.getOperand(0).getOpcode() == ISD::OR) { - SDValue Or = N.getOperand(0); - SDValue Shl = Or.getOperand(0); - SDValue Srl = Or.getOperand(1); - - // OR is commutable so canonicalize SHL to LHS. - if (Srl.getOpcode() == ISD::SHL) - std::swap(Shl, Srl); - - if (Shl.getOpcode() == ISD::SHL && Srl.getOpcode() == ISD::SRL) { - if (Srl.getOperand(0).getOpcode() == ISD::AND) { - SDValue And = Srl.getOperand(0); - if (And.getOperand(0) == Shl.getOperand(0) && - isa(Srl.getOperand(1)) && - isa(Shl.getOperand(1)) && - isa(And.getOperand(1))) { - uint64_t VC1 = Srl.getConstantOperandVal(1); - uint64_t VC2 = Shl.getConstantOperandVal(1); - uint64_t VC3 = And.getConstantOperandVal(1); - // The mask needs to be 0xffffffff, but SimplifyDemandedBits may - // have removed lower bits that aren't necessary due to the right - // shift. - if (VC2 == (32 - VC1) && - (VC3 | maskTrailingOnes(VC1)) == 0xffffffff) { - RS1 = Shl.getOperand(0); - Shamt = CurDAG->getTargetConstant(VC1, SDLoc(N), - Srl.getOperand(1).getValueType()); - return true; - } - } - } - } - } - } - return false; -} - // Merge an ADDI into the offset of a load/store instruction where possible. // (load (addi base, off1), off2) -> (load base, off1+off2) // (store val, (addi base, off1), off2) -> (store val, base, off1+off2) diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h index 10096c39cdbe3..4e382ee585002 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -50,7 +50,6 @@ class RISCVDAGToDAGISel : public SelectionDAGISel { bool SelectSLLIUW(SDValue N, SDValue &RS1, SDValue &Shamt); bool SelectSLOIW(SDValue N, SDValue &RS1, SDValue &Shamt); bool SelectSROIW(SDValue N, SDValue &RS1, SDValue &Shamt); - bool SelectRORIW(SDValue N, SDValue &RS1, SDValue &Shamt); // Include the pieces autogenerated from the target description. #include "RISCVGenDAGISel.inc" diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index b0f62f3d45f3d..e855b77bfa645 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -151,26 +151,46 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::SRL_PARTS, XLenVT, Custom); setOperationAction(ISD::SRA_PARTS, XLenVT, Custom); - if (!(Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp())) { + if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) { + if (Subtarget.is64Bit()) { + setOperationAction(ISD::ROTL, MVT::i32, Custom); + setOperationAction(ISD::ROTR, MVT::i32, Custom); + } + } else { setOperationAction(ISD::ROTL, XLenVT, Expand); setOperationAction(ISD::ROTR, XLenVT, Expand); } - if (!Subtarget.hasStdExtZbp()) + if (Subtarget.hasStdExtZbp()) { + setOperationAction(ISD::BITREVERSE, XLenVT, Legal); + + if (Subtarget.is64Bit()) { + setOperationAction(ISD::BITREVERSE, MVT::i32, Custom); + setOperationAction(ISD::BSWAP, MVT::i32, Custom); + } + } else { setOperationAction(ISD::BSWAP, XLenVT, Expand); + } - if (!Subtarget.hasStdExtZbb()) { + if (Subtarget.hasStdExtZbb()) { + setOperationAction(ISD::SMIN, XLenVT, Legal); + setOperationAction(ISD::SMAX, XLenVT, Legal); + setOperationAction(ISD::UMIN, XLenVT, Legal); + setOperationAction(ISD::UMAX, XLenVT, Legal); + } else { setOperationAction(ISD::CTTZ, XLenVT, Expand); setOperationAction(ISD::CTLZ, XLenVT, Expand); setOperationAction(ISD::CTPOP, XLenVT, Expand); } - if (Subtarget.hasStdExtZbp()) - setOperationAction(ISD::BITREVERSE, XLenVT, Legal); - if (Subtarget.hasStdExtZbt()) { setOperationAction(ISD::FSHL, XLenVT, Legal); setOperationAction(ISD::FSHR, XLenVT, Legal); + + if (Subtarget.is64Bit()) { + setOperationAction(ISD::FSHL, MVT::i32, Custom); + setOperationAction(ISD::FSHR, MVT::i32, Custom); + } } ISD::CondCode FPCCToExtend[] = { @@ -655,6 +675,10 @@ SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op, TLSModel::Model Model = getTargetMachine().getTLSModel(N->getGlobal()); + if (DAG.getMachineFunction().getFunction().getCallingConv() == + CallingConv::GHC) + report_fatal_error("In GHC calling convention TLS is not supported"); + SDValue Addr; switch (Model) { case TLSModel::LocalExec: @@ -908,6 +932,10 @@ static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) { return RISCVISD::DIVUW; case ISD::UREM: return RISCVISD::REMUW; + case ISD::ROTL: + return RISCVISD::ROLW; + case ISD::ROTR: + return RISCVISD::RORW; case RISCVISD::GREVI: return RISCVISD::GREVIW; case RISCVISD::GORCI: @@ -1013,6 +1041,12 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, return; Results.push_back(customLegalizeToWOp(N, DAG)); break; + case ISD::ROTL: + case ISD::ROTR: + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && + "Unexpected custom legalisation"); + Results.push_back(customLegalizeToWOp(N, DAG)); + break; case ISD::SDIV: case ISD::UDIV: case ISD::UREM: @@ -1052,6 +1086,41 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes)); break; } + case ISD::BSWAP: + case ISD::BITREVERSE: { + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && + Subtarget.hasStdExtZbp() && "Unexpected custom legalisation"); + SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, + N->getOperand(0)); + unsigned Imm = N->getOpcode() == ISD::BITREVERSE ? 31 : 24; + SDValue GREVIW = DAG.getNode(RISCVISD::GREVIW, DL, MVT::i64, NewOp0, + DAG.getTargetConstant(Imm, DL, + Subtarget.getXLenVT())); + // ReplaceNodeResults requires we maintain the same type for the return + // value. + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, GREVIW)); + break; + } + case ISD::FSHL: + case ISD::FSHR: { + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && + Subtarget.hasStdExtZbt() && "Unexpected custom legalisation"); + SDValue NewOp0 = + DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); + SDValue NewOp1 = + DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); + SDValue NewOp2 = + DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2)); + // FSLW/FSRW take a 6 bit shift amount but i32 FSHL/FSHR only use 5 bits. + // Mask the shift amount to 5 bits. + NewOp2 = DAG.getNode(ISD::AND, DL, MVT::i64, NewOp2, + DAG.getConstant(0x1f, DL, MVT::i64)); + unsigned Opc = + N->getOpcode() == ISD::FSHL ? RISCVISD::FSLW : RISCVISD::FSRW; + SDValue NewOp = DAG.getNode(Opc, DL, MVT::i64, NewOp0, NewOp1, NewOp2); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewOp)); + break; + } } } @@ -1267,7 +1336,9 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, } case RISCVISD::SLLW: case RISCVISD::SRAW: - case RISCVISD::SRLW: { + case RISCVISD::SRLW: + case RISCVISD::ROLW: + case RISCVISD::RORW: { // Only the lower 32 bits of LHS and lower 5 bits of RHS are read. SDValue LHS = N->getOperand(0); SDValue RHS = N->getOperand(1); @@ -1281,6 +1352,24 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, } break; } + case RISCVISD::FSLW: + case RISCVISD::FSRW: { + // Only the lower 32 bits of Values and lower 6 bits of shift amount are + // read. + SDValue Op0 = N->getOperand(0); + SDValue Op1 = N->getOperand(1); + SDValue ShAmt = N->getOperand(2); + APInt OpMask = APInt::getLowBitsSet(Op0.getValueSizeInBits(), 32); + APInt ShAmtMask = APInt::getLowBitsSet(ShAmt.getValueSizeInBits(), 6); + if (SimplifyDemandedBits(Op0, OpMask, DCI) || + SimplifyDemandedBits(Op1, OpMask, DCI) || + SimplifyDemandedBits(ShAmt, ShAmtMask, DCI)) { + if (N->getOpcode() != ISD::DELETED_NODE) + DCI.AddToWorklist(N); + return SDValue(N, 0); + } + break; + } case RISCVISD::GREVIW: case RISCVISD::GORCIW: { // Only the lower 32 bits of the first operand are read @@ -1323,6 +1412,23 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, return DAG.getNode(ISD::AND, DL, MVT::i64, NewFMV, DAG.getConstant(~SignBit, DL, MVT::i64)); } + case RISCVISD::GREVI: { + // Combine (GREVI (GREVI x, C2), C1) -> (GREVI x, C1^C2) when C1^C2 is + // non-zero, and to x when it is. Any repeated GREVI stage undoes itself. + SDLoc DL(N); + auto GREVSrc = N->getOperand(0); + uint64_t ShAmt1 = N->getConstantOperandVal(1); + if (GREVSrc->getOpcode() != RISCVISD::GREVI) + break; + uint64_t ShAmt2 = GREVSrc.getConstantOperandVal(1); + GREVSrc = GREVSrc->getOperand(0); + uint64_t CombinedShAmt = ShAmt1 ^ ShAmt2; + if (CombinedShAmt == 0) + return GREVSrc; + return DAG.getNode( + RISCVISD::GREVI, DL, N->getValueType(0), GREVSrc, + DAG.getTargetConstant(CombinedShAmt, DL, Subtarget.getXLenVT())); + } case ISD::OR: if (auto GREV = combineORToGREV(SDValue(N, 0), DCI.DAG, Subtarget)) return GREV; @@ -1392,8 +1498,12 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode( case RISCVISD::DIVW: case RISCVISD::DIVUW: case RISCVISD::REMUW: + case RISCVISD::ROLW: + case RISCVISD::RORW: case RISCVISD::GREVIW: case RISCVISD::GORCIW: + case RISCVISD::FSLW: + case RISCVISD::FSRW: // TODO: As the result is sign-extended, this is conservatively correct. A // more precise answer could be calculated for SRAW depending on known // bits in the shift amount. @@ -1481,17 +1591,19 @@ static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI, TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC, RI); - MachineMemOperand *MMO = - MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI), - MachineMemOperand::MOLoad, 8, Align(8)); + MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI); + MachineMemOperand *MMOLo = + MF.getMachineMemOperand(MPI, MachineMemOperand::MOLoad, 4, Align(8)); + MachineMemOperand *MMOHi = MF.getMachineMemOperand( + MPI.getWithOffset(4), MachineMemOperand::MOLoad, 4, Align(8)); BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg) .addFrameIndex(FI) .addImm(0) - .addMemOperand(MMO); + .addMemOperand(MMOLo); BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) .addFrameIndex(FI) .addImm(4) - .addMemOperand(MMO); + .addMemOperand(MMOHi); MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -1511,19 +1623,21 @@ static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI, const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass; int FI = MF.getInfo()->getMoveF64FrameIndex(MF); - MachineMemOperand *MMO = - MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI), - MachineMemOperand::MOStore, 8, Align(8)); + MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI); + MachineMemOperand *MMOLo = + MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, Align(8)); + MachineMemOperand *MMOHi = MF.getMachineMemOperand( + MPI.getWithOffset(4), MachineMemOperand::MOStore, 4, Align(8)); BuildMI(*BB, MI, DL, TII.get(RISCV::SW)) .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill())) .addFrameIndex(FI) .addImm(0) - .addMemOperand(MMO); + .addMemOperand(MMOLo); BuildMI(*BB, MI, DL, TII.get(RISCV::SW)) .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())) .addFrameIndex(FI) .addImm(4) - .addMemOperand(MMO); + .addMemOperand(MMOHi); TII.loadRegFromStackSlot(*BB, MI, DstReg, FI, DstRC, RI); MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; @@ -2180,22 +2294,71 @@ static bool CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT, return true; // CC didn't match. } +static bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State) { + + if (LocVT == MVT::i32 || LocVT == MVT::i64) { + // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, SpLim + // s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 + static const MCPhysReg GPRList[] = { + RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, + RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27}; + if (unsigned Reg = State.AllocateReg(GPRList)) { + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + } + + if (LocVT == MVT::f32) { + // Pass in STG registers: F1, ..., F6 + // fs0 ... fs5 + static const MCPhysReg FPR32List[] = {RISCV::F8_F, RISCV::F9_F, + RISCV::F18_F, RISCV::F19_F, + RISCV::F20_F, RISCV::F21_F}; + if (unsigned Reg = State.AllocateReg(FPR32List)) { + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + } + + if (LocVT == MVT::f64) { + // Pass in STG registers: D1, ..., D6 + // fs6 ... fs11 + static const MCPhysReg FPR64List[] = {RISCV::F22_D, RISCV::F23_D, + RISCV::F24_D, RISCV::F25_D, + RISCV::F26_D, RISCV::F27_D}; + if (unsigned Reg = State.AllocateReg(FPR64List)) { + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + return false; + } + } + + report_fatal_error("No registers left in GHC calling convention"); + return true; +} + // Transform physical registers into virtual registers. SDValue RISCVTargetLowering::LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl &InVals) const { + MachineFunction &MF = DAG.getMachineFunction(); + switch (CallConv) { default: report_fatal_error("Unsupported calling convention"); case CallingConv::C: case CallingConv::Fast: break; + case CallingConv::GHC: + if (!MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtF] || + !MF.getSubtarget().getFeatureBits()[RISCV::FeatureStdExtD]) + report_fatal_error( + "GHC calling convention requires the F and D instruction set extensions"); } - MachineFunction &MF = DAG.getMachineFunction(); - const Function &Func = MF.getFunction(); if (Func.hasFnAttribute("interrupt")) { if (!Func.arg_empty()) @@ -2222,6 +2385,8 @@ SDValue RISCVTargetLowering::LowerFormalArguments( if (CallConv == CallingConv::Fast) CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_FastCC); + else if (CallConv == CallingConv::GHC) + CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_GHC); else analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false); @@ -2422,6 +2587,8 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, if (CallConv == CallingConv::Fast) ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_FastCC); + else if (CallConv == CallingConv::GHC) + ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_GHC); else analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI); @@ -2709,6 +2876,9 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true, nullptr); + if (CallConv == CallingConv::GHC && !RVLocs.empty()) + report_fatal_error("GHC functions return void only"); + SDValue Glue; SmallVector RetOps(1, Chain); @@ -2829,6 +2999,10 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(DIVW) NODE_NAME_CASE(DIVUW) NODE_NAME_CASE(REMUW) + NODE_NAME_CASE(ROLW) + NODE_NAME_CASE(RORW) + NODE_NAME_CASE(FSLW) + NODE_NAME_CASE(FSRW) NODE_NAME_CASE(FMV_W_X_RV64) NODE_NAME_CASE(FMV_X_ANYEXTW_RV64) NODE_NAME_CASE(READ_CYCLE_WIDE) @@ -3191,6 +3365,25 @@ Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic( return Result; } +bool RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, + EVT VT) const { + VT = VT.getScalarType(); + + if (!VT.isSimple()) + return false; + + switch (VT.getSimpleVT().SimpleTy) { + case MVT::f32: + return Subtarget.hasStdExtF(); + case MVT::f64: + return Subtarget.hasStdExtD(); + default: + break; + } + + return false; +} + Register RISCVTargetLowering::getExceptionPointerRegister( const Constant *PersonalityFn) const { return RISCV::X10; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index e62d3ff857ff4..065b35874e84c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -42,6 +42,14 @@ enum NodeType : unsigned { DIVW, DIVUW, REMUW, + // RV64IB rotates, directly matching the semantics of the named RISC-V + // instructions. + ROLW, + RORW, + // RV64IB funnel shifts, with the semantics of the named RISC-V instructions, + // but the same operand order as fshl/fshr intrinsics. + FSRW, + FSLW, // FPR32<->GPR transfer operations for RV64. Needed as an i32<->f32 bitcast // is not legal on RV64. FMV_W_X_RV64 matches the semantics of the FMV.W.X. // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result. @@ -138,6 +146,9 @@ class RISCVTargetLowering : public TargetLowering { Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override; + bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, + EVT VT) const override; + ISD::NodeType getExtendForAtomicOps() const override { return ISD::SIGN_EXTEND; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 6a3bd3fa11091..8c34094878066 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1144,6 +1144,8 @@ def : Pat<(srl (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt), (SRLIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>; def : Pat<(sra (sext_inreg GPR:$rs1, i32), uimm5:$shamt), (SRAIW GPR:$rs1, uimm5:$shamt)>; +def : Pat<(sra (shl GPR:$rs1, (i64 32)), uimm6gt32:$shamt), + (SRAIW GPR:$rs1, (ImmSub32 uimm6gt32:$shamt))>; def : PatGprGpr; def : PatGprGpr; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td index abd0adb25bf48..7a8a1bc364e11 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -17,6 +17,11 @@ // Operand and SDNode transformation definitions. //===----------------------------------------------------------------------===// +def riscv_rolw : SDNode<"RISCVISD::ROLW", SDTIntShiftOp>; +def riscv_rorw : SDNode<"RISCVISD::RORW", SDTIntShiftOp>; +def riscv_fslw : SDNode<"RISCVISD::FSLW", SDTIntShiftDOp>; +def riscv_fsrw : SDNode<"RISCVISD::FSRW", SDTIntShiftDOp>; + def UImmLog2XLenHalfAsmOperand : AsmOperandClass { let Name = "UImmLog2XLenHalf"; let RenderMethod = "addImmOperands"; @@ -655,7 +660,6 @@ def SROIPat : ComplexPattern; def SLLIUWPat : ComplexPattern; def SLOIWPat : ComplexPattern; def SROIWPat : ComplexPattern; -def RORIWPat : ComplexPattern; let Predicates = [HasStdExtZbbOrZbp] in { def : Pat<(and GPR:$rs1, (not GPR:$rs2)), (ANDN GPR:$rs1, GPR:$rs2)>; @@ -685,6 +689,9 @@ def : Pat<(xor (shiftop 1, GPR:$rs2), GPR:$rs1), (SBINV GPR:$rs1, GPR:$rs2)>; def : Pat<(and (shiftop GPR:$rs1, GPR:$rs2), 1), (SBEXT GPR:$rs1, GPR:$rs2)>; + +def : Pat<(shiftop 1, GPR:$rs2), + (SBSET X0, GPR:$rs2)>; } let Predicates = [HasStdExtZbb] in { @@ -724,17 +731,11 @@ def : Pat<(riscv_gorci GPR:$rs1, timm:$shamt), (GORCI GPR:$rs1, timm:$shamt)>; let Predicates = [HasStdExtZbp, IsRV32] in { def : Pat<(rotr (bswap GPR:$rs1), (i32 16)), (GREVI GPR:$rs1, (i32 8))>; -// FIXME: Is grev better than rori? -def : Pat<(rotl GPR:$rs1, (i32 16)), (GREVI GPR:$rs1, (i32 16))>; -def : Pat<(rotr GPR:$rs1, (i32 16)), (GREVI GPR:$rs1, (i32 16))>; def : Pat<(bswap GPR:$rs1), (GREVI GPR:$rs1, (i32 24))>; def : Pat<(bitreverse GPR:$rs1), (GREVI GPR:$rs1, (i32 31))>; } // Predicates = [HasStdExtZbp, IsRV32] let Predicates = [HasStdExtZbp, IsRV64] in { -// FIXME: Is grev better than rori? -def : Pat<(rotl GPR:$rs1, (i64 32)), (GREVI GPR:$rs1, (i64 32))>; -def : Pat<(rotr GPR:$rs1, (i64 32)), (GREVI GPR:$rs1, (i64 32))>; def : Pat<(bswap GPR:$rs1), (GREVI GPR:$rs1, (i64 56))>; def : Pat<(bitreverse GPR:$rs1), (GREVI GPR:$rs1, (i64 63))>; } // Predicates = [HasStdExtZbp, IsRV64] @@ -791,17 +792,9 @@ def : Pat<(sext_inreg GPR:$rs1, i16), (SEXTH GPR:$rs1)>; let Predicates = [HasStdExtZbb] in { def : Pat<(smin GPR:$rs1, GPR:$rs2), (MIN GPR:$rs1, GPR:$rs2)>; -def : Pat<(riscv_selectcc GPR:$rs1, GPR:$rs2, (XLenVT 20), GPR:$rs1, GPR:$rs2), - (MIN GPR:$rs1, GPR:$rs2)>; def : Pat<(smax GPR:$rs1, GPR:$rs2), (MAX GPR:$rs1, GPR:$rs2)>; -def : Pat<(riscv_selectcc GPR:$rs2, GPR:$rs1, (XLenVT 20), GPR:$rs1, GPR:$rs2), - (MAX GPR:$rs1, GPR:$rs2)>; def : Pat<(umin GPR:$rs1, GPR:$rs2), (MINU GPR:$rs1, GPR:$rs2)>; -def : Pat<(riscv_selectcc GPR:$rs1, GPR:$rs2, (XLenVT 12), GPR:$rs1, GPR:$rs2), - (MINU GPR:$rs1, GPR:$rs2)>; def : Pat<(umax GPR:$rs1, GPR:$rs2), (MAXU GPR:$rs1, GPR:$rs2)>; -def : Pat<(riscv_selectcc GPR:$rs2, GPR:$rs1, (XLenVT 12), GPR:$rs1, GPR:$rs2), - (MAXU GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtZbb] let Predicates = [HasStdExtZbbOrZbp, IsRV32] in @@ -890,23 +883,34 @@ def : Pat<(not (riscv_srlw (not GPR:$rs1), GPR:$rs2)), } // Predicates = [HasStdExtZbb, IsRV64] let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { -def : Pat<(or (riscv_sllw GPR:$rs1, GPR:$rs2), - (riscv_srlw GPR:$rs1, (ineg GPR:$rs2))), +def : Pat<(riscv_rolw GPR:$rs1, GPR:$rs2), (ROLW GPR:$rs1, GPR:$rs2)>; -def : Pat<(or (riscv_sllw GPR:$rs1, (ineg GPR:$rs2)), - (riscv_srlw GPR:$rs1, GPR:$rs2)), +def : Pat<(riscv_rorw GPR:$rs1, GPR:$rs2), (RORW GPR:$rs1, GPR:$rs2)>; +def : Pat<(riscv_rorw GPR:$rs1, uimm5:$rs2), + (RORIW GPR:$rs1, uimm5:$rs2)>; +def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2), + (RORIW GPR:$rs1, (ImmROTL2RW uimm5:$rs2))>; } // Predicates = [HasStdExtZbbOrZbp, IsRV64] let Predicates = [HasStdExtZbs, IsRV64] in { def : Pat<(and (not (riscv_sllw 1, GPR:$rs2)), (assertsexti32 GPR:$rs1)), (SBCLRW GPR:$rs1, GPR:$rs2)>; +def : Pat<(sext_inreg (and (not (riscv_sllw 1, GPR:$rs2)), GPR:$rs1), i32), + (SBCLRW GPR:$rs1, GPR:$rs2)>; def : Pat<(or (riscv_sllw 1, GPR:$rs2), (assertsexti32 GPR:$rs1)), (SBSETW GPR:$rs1, GPR:$rs2)>; +def : Pat<(sext_inreg (or (riscv_sllw 1, GPR:$rs2), GPR:$rs1), i32), + (SBSETW GPR:$rs1, GPR:$rs2)>; def : Pat<(xor (riscv_sllw 1, GPR:$rs2), (assertsexti32 GPR:$rs1)), (SBINVW GPR:$rs1, GPR:$rs2)>; +def : Pat<(sext_inreg (xor (riscv_sllw 1, GPR:$rs2), GPR:$rs1), i32), + (SBINVW GPR:$rs1, GPR:$rs2)>; def : Pat<(and (riscv_srlw GPR:$rs1, GPR:$rs2), 1), (SBEXTW GPR:$rs1, GPR:$rs2)>; + +def : Pat<(riscv_sllw 1, GPR:$rs2), + (SBSETW X0, GPR:$rs2)>; } // Predicates = [HasStdExtZbs, IsRV64] let Predicates = [HasStdExtZbb, IsRV64] in { @@ -916,34 +920,19 @@ def : Pat<(SROIWPat GPR:$rs1, uimmlog2xlen:$shamt), (SROIW GPR:$rs1, uimmlog2xlen:$shamt)>; } // Predicates = [HasStdExtZbb, IsRV64] -let Predicates = [HasStdExtZbbOrZbp, IsRV64] in -def : Pat<(RORIWPat GPR:$rs1, uimmlog2xlen:$shamt), - (RORIW GPR:$rs1, uimmlog2xlen:$shamt)>; - let Predicates = [HasStdExtZbp, IsRV64] in { def : Pat<(riscv_greviw GPR:$rs1, timm:$shamt), (GREVIW GPR:$rs1, timm:$shamt)>; def : Pat<(riscv_gorciw GPR:$rs1, timm:$shamt), (GORCIW GPR:$rs1, timm:$shamt)>; - -def : Pat<(sra (bswap GPR:$rs1), (i64 32)), (GREVIW GPR:$rs1, (i64 24))>; -def : Pat<(sra (bitreverse GPR:$rs1), (i64 32)), (GREVIW GPR:$rs1, (i64 31))>; } // Predicates = [HasStdExtZbp, IsRV64] let Predicates = [HasStdExtZbt, IsRV64] in { -def : Pat<(sext_inreg (fshl GPR:$rs1, (shl GPR:$rs3, (i64 32)), - (and GPR:$rs2, (i64 31))), - i32), - (FSLW GPR:$rs1, (ANDI GPR:$rs2, 31), GPR:$rs3)>; -def : Pat<(sext_inreg (fshr GPR:$rs3, (shl GPR:$rs1, (i64 32)), - (or GPR:$rs2, (i64 32))), - i32), - (FSRW GPR:$rs1, (ANDI GPR:$rs2, 31), GPR:$rs3)>; -def : Pat<(sext_inreg (fshr GPR:$rs3, (shl GPR:$rs1, (i64 32)), - uimm6gt32:$shamt), - i32), - (FSRIW GPR:$rs1, GPR:$rs3, (ImmSub32 uimm6gt32:$shamt))>; -def : Pat<(sext_inreg (fshl GPR:$rs3, (shl GPR:$rs1, (i64 32)), - uimm5:$shamt), - i32), +def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2), + (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; +def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, GPR:$rs2), + (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>; +def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, uimm5:$shamt), + (FSRIW GPR:$rs1, GPR:$rs3, uimm5:$shamt)>; +def : Pat<(riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt), (FSRIW GPR:$rs1, GPR:$rs3, (ImmROTL2RW uimm5:$shamt))>; } // Predicates = [HasStdExtZbt, IsRV64] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td index a9960ea546ada..fbddde2b4bdcb 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -239,7 +239,7 @@ class CStore_rri funct3, string OpcodeStr, OpcodeStr, "$rs2, ${imm}(${rs1})">; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in -class Bcz funct3, string OpcodeStr, PatFrag CondOp, +class Bcz funct3, string OpcodeStr, RegisterClass cls> : RVInst16CB { @@ -469,8 +469,8 @@ def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins simm12_lsb0:$offset), let isBarrier=1; } -def C_BEQZ : Bcz<0b110, "c.beqz", seteq, GPRC>, Sched<[WriteJmp]>; -def C_BNEZ : Bcz<0b111, "c.bnez", setne, GPRC>, Sched<[WriteJmp]>; +def C_BEQZ : Bcz<0b110, "c.beqz", GPRC>, Sched<[WriteJmp]>; +def C_BNEZ : Bcz<0b111, "c.bnez", GPRC>, Sched<[WriteJmp]>; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td index ddd86d9a7a9a0..6c36f53cd563d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -276,14 +276,10 @@ def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)), // fnmsub: -rs1 * rs2 + rs3 def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3), (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; -def : Pat<(fma FPR64:$rs1, (fneg FPR64:$rs2), FPR64:$rs3), - (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; // fnmadd: -rs1 * rs2 - rs3 def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)), (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; -def : Pat<(fma FPR64:$rs1, (fneg FPR64:$rs2), (fneg FPR64:$rs3)), - (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; // The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the // canonical NaN when giving a signaling NaN. This doesn't match the LLVM diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td index d466069ab2a14..79281e7d8a5b4 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -332,14 +332,10 @@ def : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)), // fnmsub: -rs1 * rs2 + rs3 def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3), (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; -def : Pat<(fma FPR32:$rs1, (fneg FPR32:$rs2), FPR32:$rs3), - (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; // fnmadd: -rs1 * rs2 - rs3 def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)), (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; -def : Pat<(fma FPR32:$rs1, (fneg FPR32:$rs2), (fneg FPR32:$rs3)), - (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; // The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the // canonical NaN when given a signaling NaN. This doesn't match the LLVM diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td index 987534aadd79f..8cfb903a173ce 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td @@ -81,9 +81,11 @@ def : PatGprGpr; // Handle the specific cases where using DIVU/REMU would be correct and result // in fewer instructions than emitting DIVUW/REMUW then zero-extending the // result. -def : Pat<(zexti32 (riscv_divuw (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))), +def : Pat<(and (riscv_divuw (assertzexti32 GPR:$rs1), + (assertzexti32 GPR:$rs2)), 0xffffffff), (DIVU GPR:$rs1, GPR:$rs2)>; -def : Pat<(zexti32 (riscv_remuw (zexti32 GPR:$rs1), (zexti32 GPR:$rs2))), +def : Pat<(and (riscv_remuw (assertzexti32 GPR:$rs1), + (assertzexti32 GPR:$rs2)), 0xffffffff), (REMU GPR:$rs1, GPR:$rs2)>; // Although the sexti32 operands may not have originated from an i32 srem, diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 97475e807526f..05a2bd3f1febd 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -45,6 +45,8 @@ RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) const MCPhysReg * RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { auto &Subtarget = MF->getSubtarget(); + if (MF->getFunction().getCallingConv() == CallingConv::GHC) + return CSR_NoRegs_SaveList; if (MF->getFunction().hasFnAttribute("interrupt")) { if (Subtarget.hasStdExtD()) return CSR_XLEN_F64_Interrupt_SaveList; @@ -191,9 +193,11 @@ Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const { const uint32_t * RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF, - CallingConv::ID /*CC*/) const { + CallingConv::ID CC) const { auto &Subtarget = MF.getSubtarget(); + if (CC == CallingConv::GHC) + return CSR_NoRegs_RegMask; switch (Subtarget.getTargetABI()) { default: llvm_unreachable("Unrecognized ABI"); diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 2b44847104a02..6d6babce98ca8 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -97,8 +97,8 @@ let RegAltNameIndices = [ABIRegAltName] in { } } -def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode], - [i32, i64, i32]>; +def XLenVT : ValueTypeByHwMode<[RV32, RV64], + [i32, i64]>; // The order of registers represents the preferred allocation sequence. // Registers are listed in the order caller-save, callee-save, specials. @@ -111,14 +111,14 @@ def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add (sequence "X%u", 0, 4) )> { let RegInfos = RegInfoByHwMode< - [RV32, RV64, DefaultMode], - [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } def GPRX0 : RegisterClass<"RISCV", [XLenVT], 32, (add X0)> { let RegInfos = RegInfoByHwMode< - [RV32, RV64, DefaultMode], - [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } // The order of registers represents the preferred allocation sequence. @@ -132,8 +132,8 @@ def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (add (sequence "X%u", 1, 4) )> { let RegInfos = RegInfoByHwMode< - [RV32, RV64, DefaultMode], - [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (add @@ -145,8 +145,8 @@ def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X3, X4 )> { let RegInfos = RegInfoByHwMode< - [RV32, RV64, DefaultMode], - [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add @@ -154,8 +154,8 @@ def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add (sequence "X%u", 8, 9) )> { let RegInfos = RegInfoByHwMode< - [RV32, RV64, DefaultMode], - [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } // For indirect tail calls, we can't use callee-saved registers, as they are @@ -167,14 +167,14 @@ def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add (sequence "X%u", 28, 31) )> { let RegInfos = RegInfoByHwMode< - [RV32, RV64, DefaultMode], - [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> { let RegInfos = RegInfoByHwMode< - [RV32, RV64, DefaultMode], - [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>; + [RV32, RV64], + [RegInfo<32,32,32>, RegInfo<64,64,64>]>; } // Floating point registers @@ -331,13 +331,6 @@ def VRM8 : RegisterClass<"RISCV", [nxv32i16, nxv16i32, nxv8i64], 64, def VMaskVT : RegisterTypes<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, nxv32i1]>; -def VM : RegisterClass<"RISCV", VMaskVT.types, 64, (add - (sequence "V%u", 25, 31), - (sequence "V%u", 8, 24), - (sequence "V%u", 0, 7))> { - let Size = 64; -} - def VMV0 : RegisterClass<"RISCV", VMaskVT.types, 64, (add V0)> { let Size = 64; } diff --git a/llvm/lib/Target/VE/VEFrameLowering.cpp b/llvm/lib/Target/VE/VEFrameLowering.cpp index ec18bee743290..e15e4130f74bc 100644 --- a/llvm/lib/Target/VE/VEFrameLowering.cpp +++ b/llvm/lib/Target/VE/VEFrameLowering.cpp @@ -8,6 +8,105 @@ // // This file contains the VE implementation of TargetFrameLowering class. // +// On VE, stack frames are structured as follows: +// +// The stack grows downward. +// +// All of the individual frame areas on the frame below are optional, i.e. it's +// possible to create a function so that the particular area isn't present +// in the frame. +// +// At function entry, the "frame" looks as follows: +// +// | | Higher address +// |----------------------------------------------| +// | Parameter area for this function | +// |----------------------------------------------| +// | Register save area (RSA) for this function | +// |----------------------------------------------| +// | Return address for this function | +// |----------------------------------------------| +// | Frame pointer for this function | +// |----------------------------------------------| <- sp +// | | Lower address +// +// VE doesn't use on demand stack allocation, so user code generated by LLVM +// needs to call VEOS to allocate stack frame. VE's ABI want to reduce the +// number of VEOS calls, so ABI requires to allocate not only RSA (in general +// CSR, callee saved register) area but also call frame at the prologue of +// caller function. +// +// After the prologue has run, the frame has the following general structure. +// Note that technically the last frame area (VLAs) doesn't get created until +// in the main function body, after the prologue is run. However, it's depicted +// here for completeness. +// +// | | Higher address +// |----------------------------------------------| +// | Parameter area for this function | +// |----------------------------------------------| +// | Register save area (RSA) for this function | +// |----------------------------------------------| +// | Return address for this function | +// |----------------------------------------------| +// | Frame pointer for this function | +// |----------------------------------------------| <- fp(=old sp) +// |.empty.space.to.make.part.below.aligned.in....| +// |.case.it.needs.more.than.the.standard.16-byte.| (size of this area is +// |.alignment....................................| unknown at compile time) +// |----------------------------------------------| +// | Local variables of fixed size including spill| +// | slots | +// |----------------------------------------------| <- bp(not defined by ABI, +// |.variable-sized.local.variables.(VLAs)........| LLVM chooses SX17) +// |..............................................| (size of this area is +// |..............................................| unknown at compile time) +// |----------------------------------------------| <- stack top (returned by +// | Parameter area for callee | alloca) +// |----------------------------------------------| +// | Register save area (RSA) for callee | +// |----------------------------------------------| +// | Return address for callee | +// |----------------------------------------------| +// | Frame pointer for callee | +// |----------------------------------------------| <- sp +// | | Lower address +// +// To access the data in a frame, at-compile time, a constant offset must be +// computable from one of the pointers (fp, bp, sp) to access it. The size +// of the areas with a dotted background cannot be computed at compile-time +// if they are present, making it required to have all three of fp, bp and +// sp to be set up to be able to access all contents in the frame areas, +// assuming all of the frame areas are non-empty. +// +// For most functions, some of the frame areas are empty. For those functions, +// it may not be necessary to set up fp or bp: +// * A base pointer is definitely needed when there are both VLAs and local +// variables with more-than-default alignment requirements. +// * A frame pointer is definitely needed when there are local variables with +// more-than-default alignment requirements. +// +// In addition, VE ABI defines RSA frame, return address, and frame pointer +// as follows: +// +// |----------------------------------------------| <- sp+176 +// | %s18...%s33 | +// |----------------------------------------------| <- sp+48 +// | Linkage area register (%s17) | +// |----------------------------------------------| <- sp+40 +// | Procedure linkage table register (%plt=%s16) | +// |----------------------------------------------| <- sp+32 +// | Global offset table register (%got=%s15) | +// |----------------------------------------------| <- sp+24 +// | Thread pointer register (%tp=%s14) | +// |----------------------------------------------| <- sp+16 +// | Return address | +// |----------------------------------------------| <- sp+8 +// | Frame pointer | +// |----------------------------------------------| <- sp+0 +// +// NOTE: This description is based on VE ABI and description in +// AArch64FrameLowering.cpp. Thanks a lot. //===----------------------------------------------------------------------===// #include "VEFrameLowering.h" @@ -224,8 +323,8 @@ void VEFrameLowering::emitPrologue(MachineFunction &MF, // Get the number of bytes to allocate from the FrameInfo uint64_t NumBytes = MFI.getStackSize(); - // The VE ABI requires a reserved 176 bytes area at the top - // of stack as described in VESubtarget.cpp. So, we adjust it here. + // The VE ABI requires a reserved area at the top of stack as described + // in VESubtarget.cpp. So, we adjust it here. NumBytes = STI.getAdjustedFrameSize(NumBytes); // Finally, ensure that the size is sufficiently aligned for the diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp index c41d0a416eaae..cc7f5f6800ecd 100644 --- a/llvm/lib/Target/VE/VEISelLowering.cpp +++ b/llvm/lib/Target/VE/VEISelLowering.cpp @@ -254,8 +254,17 @@ void VETargetLowering::initSPUActions() { } void VETargetLowering::initVPUActions() { - for (MVT LegalVecVT : AllVectorVTs) + for (MVT LegalVecVT : AllVectorVTs) { setOperationAction(ISD::BUILD_VECTOR, LegalVecVT, Custom); + // Translate all vector instructions with legal element types to VVP_* + // nodes. + // TODO We will custom-widen into VVP_* nodes in the future. While we are + // buildling the infrastructure for this, we only do this for legal vector + // VTs. +#define ADD_VVP_OP(VVP_NAME, ISD_NAME) \ + setOperationAction(ISD::ISD_NAME, LegalVecVT, Custom); +#include "VVPNodes.def" + } } SDValue @@ -341,7 +350,7 @@ SDValue VETargetLowering::LowerFormalArguments( MachineFunction &MF = DAG.getMachineFunction(); // Get the base offset of the incoming arguments stack space. - unsigned ArgsBaseOffset = 176; + unsigned ArgsBaseOffset = Subtarget->getRsaSize(); // Get the size of the preserved arguments area unsigned ArgsPreserved = 64; @@ -411,7 +420,7 @@ SDValue VETargetLowering::LowerFormalArguments( // The registers are exhausted. This argument was passed on the stack. assert(VA.isMemLoc()); // The CC_VE_Full/Half functions compute stack offsets relative to the - // beginning of the arguments area at %fp+176. + // beginning of the arguments area at %fp + the size of reserved area. unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset; unsigned ValSize = VA.getValVT().getSizeInBits() / 8; @@ -446,7 +455,7 @@ SDValue VETargetLowering::LowerFormalArguments( // TODO: need to calculate offset correctly once we support f128. unsigned ArgOffset = ArgLocs.size() * 8; VEMachineFunctionInfo *FuncInfo = MF.getInfo(); - // Skip the 176 bytes of register save area. + // Skip the reserved area at the top of stack. FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgsBaseOffset); return Chain; @@ -489,7 +498,7 @@ SDValue VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, CLI.IsTailCall = false; // Get the base offset of the outgoing arguments stack space. - unsigned ArgsBaseOffset = 176; + unsigned ArgsBaseOffset = Subtarget->getRsaSize(); // Get the size of the preserved arguments area unsigned ArgsPreserved = 8 * 8u; @@ -631,8 +640,7 @@ SDValue VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Create a store off the stack pointer for this argument. SDValue StackPtr = DAG.getRegister(VE::SX11, PtrVT); - // The argument area starts at %fp+176 in the callee frame, - // %sp+176 in ours. + // The argument area starts at %fp/%sp + the size of reserved area. SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + ArgsBaseOffset, DL); PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff); @@ -801,30 +809,6 @@ bool VETargetLowering::allowsMisalignedMemoryAccesses(EVT VT, return true; } -bool VETargetLowering::hasAndNot(SDValue Y) const { - EVT VT = Y.getValueType(); - - // VE doesn't have vector and not instruction. - if (VT.isVector()) - return false; - - // VE allows different immediate values for X and Y where ~X & Y. - // Only simm7 works for X, and only mimm works for Y on VE. However, this - // function is used to check whether an immediate value is OK for and-not - // instruction as both X and Y. Generating additional instruction to - // retrieve an immediate value is no good since the purpose of this - // function is to convert a series of 3 instructions to another series of - // 3 instructions with better parallelism. Therefore, we return false - // for all immediate values now. - // FIXME: Change hasAndNot function to have two operands to make it work - // correctly with Aurora VE. - if (isa(Y)) - return false; - - // It's ok for generic registers. - return true; -} - VETargetLowering::VETargetLowering(const TargetMachine &TM, const VESubtarget &STI) : TargetLowering(TM), Subtarget(&STI) { @@ -871,6 +855,10 @@ const char *VETargetLowering::getTargetNodeName(unsigned Opcode) const { TARGET_NODE_CASE(VEC_BROADCAST) TARGET_NODE_CASE(RET_FLAG) TARGET_NODE_CASE(GLOBAL_BASE_REG) + + // Register the VVP_* SDNodes. +#define ADD_VVP_OP(VVP_NAME, ...) TARGET_NODE_CASE(VVP_NAME) +#include "VVPNodes.def" } #undef TARGET_NODE_CASE return nullptr; @@ -1428,6 +1416,10 @@ SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { return lowerVASTART(Op, DAG); case ISD::VAARG: return lowerVAARG(Op, DAG); + +#define ADD_BINARY_VVP_OP(VVP_NAME, ISD_NAME) case ISD::ISD_NAME: +#include "VVPNodes.def" + return lowerToVVP(Op, DAG); } } /// } Custom Lower @@ -1617,7 +1609,7 @@ SDValue VETargetLowering::PerformDAGCombine(SDNode *N, } //===----------------------------------------------------------------------===// -// VE Inline Assembly Support +// VE Inline Assembly Support //===----------------------------------------------------------------------===// VETargetLowering::ConstraintType @@ -1666,3 +1658,77 @@ unsigned VETargetLowering::getMinimumJumpTableEntries() const { return TargetLowering::getMinimumJumpTableEntries(); } + +bool VETargetLowering::hasAndNot(SDValue Y) const { + EVT VT = Y.getValueType(); + + // VE doesn't have vector and not instruction. + if (VT.isVector()) + return false; + + // VE allows different immediate values for X and Y where ~X & Y. + // Only simm7 works for X, and only mimm works for Y on VE. However, this + // function is used to check whether an immediate value is OK for and-not + // instruction as both X and Y. Generating additional instruction to + // retrieve an immediate value is no good since the purpose of this + // function is to convert a series of 3 instructions to another series of + // 3 instructions with better parallelism. Therefore, we return false + // for all immediate values now. + // FIXME: Change hasAndNot function to have two operands to make it work + // correctly with Aurora VE. + if (isa(Y)) + return false; + + // It's ok for generic registers. + return true; +} + +/// \returns the VVP_* SDNode opcode corresponsing to \p OC. +static Optional getVVPOpcode(unsigned OC) { + switch (OC) { +#define ADD_VVP_OP(VVPNAME, SDNAME) \ + case VEISD::VVPNAME: \ + case ISD::SDNAME: \ + return VEISD::VVPNAME; +#include "VVPNodes.def" + } + return None; +} + +SDValue VETargetLowering::lowerToVVP(SDValue Op, SelectionDAG &DAG) const { + // Can we represent this as a VVP node. + auto OCOpt = getVVPOpcode(Op->getOpcode()); + if (!OCOpt.hasValue()) + return SDValue(); + unsigned VVPOC = OCOpt.getValue(); + + // The representative and legalized vector type of this operation. + EVT OpVecVT = Op.getValueType(); + EVT LegalVecVT = getTypeToTransformTo(*DAG.getContext(), OpVecVT); + + // Materialize the VL parameter. + SDLoc DL(Op); + SDValue AVL = DAG.getConstant(OpVecVT.getVectorNumElements(), DL, MVT::i32); + MVT MaskVT = MVT::v256i1; + SDValue ConstTrue = DAG.getConstant(1, DL, MVT::i32); + SDValue Mask = DAG.getNode(VEISD::VEC_BROADCAST, DL, MaskVT, + ConstTrue); // emit a VEISD::VEC_BROADCAST here. + + // Categories we are interested in. + bool IsBinaryOp = false; + + switch (VVPOC) { +#define ADD_BINARY_VVP_OP(VVPNAME, ...) \ + case VEISD::VVPNAME: \ + IsBinaryOp = true; \ + break; +#include "VVPNodes.def" + } + + if (IsBinaryOp) { + assert(LegalVecVT.isSimple()); + return DAG.getNode(VVPOC, DL, LegalVecVT, Op->getOperand(0), + Op->getOperand(1), Mask, AVL); + } + llvm_unreachable("lowerToVVP called for unexpected SDNode."); +} diff --git a/llvm/lib/Target/VE/VEISelLowering.h b/llvm/lib/Target/VE/VEISelLowering.h index e12bef882d8ad..9924db647f461 100644 --- a/llvm/lib/Target/VE/VEISelLowering.h +++ b/llvm/lib/Target/VE/VEISelLowering.h @@ -39,6 +39,10 @@ enum NodeType : unsigned { CALL, // A call instruction. RET_FLAG, // Return with a flag operand. GLOBAL_BASE_REG, // Global base reg for PIC. + + // VVP_* nodes. +#define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME, +#include "VVPNodes.def" }; } @@ -120,6 +124,10 @@ class VETargetLowering : public TargetLowering { SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; /// } Custom Lower + /// VVP Lowering { + SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const; + /// } VVPLowering + /// Custom DAGCombine { SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp index c6c77aface52a..eb375ccca3714 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.cpp +++ b/llvm/lib/Target/VE/VEInstrInfo.cpp @@ -915,8 +915,8 @@ bool VEInstrInfo::expandGetStackTopPseudo(MachineInstr &MI) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); const VEFrameLowering &TFL = *STI.getFrameLowering(); - // The VE ABI requires a reserved 176 bytes area at the top - // of stack as described in VESubtarget.cpp. So, we adjust it here. + // The VE ABI requires a reserved area at the top of stack as described + // in VEFrameLowering.cpp. So, we adjust it here. unsigned NumBytes = STI.getAdjustedFrameSize(0); // Also adds the size of parameter area. diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td index 863213f179ce7..86635adf9ef29 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.td +++ b/llvm/lib/Target/VE/VEInstrInfo.td @@ -245,6 +245,7 @@ def fplomsbzero : PatLeaf<(fpimm), [{ return (getFpImmVal(N) & 0x80000000) == 0; }]>; def fplozero : PatLeaf<(fpimm), [{ return (getFpImmVal(N) & 0xffffffff) == 0; }]>; +def nonzero : PatLeaf<(imm), [{ return N->getSExtValue() !=0 ; }]>; def CCSIOp : PatLeaf<(cond), [{ switch (N->get()) { @@ -2219,6 +2220,22 @@ def : Pat<(i32 (and i32:$val, 0xffff)), def : Pat<(i64 (and i64:$val, 0xffffffff)), (ANDrm $val, !add(32, 64))>; +//===----------------------------------------------------------------------===// +// Vector Instruction Pattern Stuff +//===----------------------------------------------------------------------===// + +// Custom intermediate ISDs. +class IsVLVT : SDTCisVT; +def vec_broadcast : SDNode<"VEISD::VEC_BROADCAST", SDTypeProfile<1, 2, + [SDTCisVec<0>, IsVLVT<2>]>>; + +// Whether this is an all-true mask (assuming undef-bits above VL are all-true). +def true_mask : PatLeaf< + (vec_broadcast (i32 nonzero), (i32 srcvalue))>; +// Match any broadcast (ignoring VL). +def any_broadcast : PatFrag<(ops node:$sx), + (vec_broadcast node:$sx, (i32 srcvalue))>; + // Vector instructions. include "VEInstrVec.td" @@ -2227,3 +2244,6 @@ include "VEInstrIntrinsicVL.td" // Patterns and intermediate SD nodes (VEC_*). include "VEInstrPatternsVec.td" + +// Patterns and intermediate SD nodes (VVP_*). +include "VVPInstrPatternsVec.td" diff --git a/llvm/lib/Target/VE/VEInstrPatternsVec.td b/llvm/lib/Target/VE/VEInstrPatternsVec.td index 947b1ac8fb548..c08e7ba7bbe70 100644 --- a/llvm/lib/Target/VE/VEInstrPatternsVec.td +++ b/llvm/lib/Target/VE/VEInstrPatternsVec.td @@ -15,10 +15,6 @@ // Instruction format superclass //===----------------------------------------------------------------------===// -// Custom intermediate ISDs. -class IsVLVT : SDTCisVT; -def vec_broadcast : SDNode<"VEISD::VEC_BROADCAST", SDTypeProfile<1, 2, [SDTCisVec<0>, IsVLVT<2>]>>; - multiclass vbrd_elem32 { // VBRDil def : Pat<(v32 (vec_broadcast (s32 ImmOp:$sy), i32:$vl)), diff --git a/llvm/lib/Target/VE/VERegisterInfo.cpp b/llvm/lib/Target/VE/VERegisterInfo.cpp index 0559c330368fb..07249616c2496 100644 --- a/llvm/lib/Target/VE/VERegisterInfo.cpp +++ b/llvm/lib/Target/VE/VERegisterInfo.cpp @@ -174,26 +174,3 @@ void VERegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, Register VERegisterInfo::getFrameRegister(const MachineFunction &MF) const { return VE::SX9; } - -// VE has no architectural need for stack realignment support, -// except that LLVM unfortunately currently implements overaligned -// stack objects by depending upon stack realignment support. -// If that ever changes, this can probably be deleted. -bool VERegisterInfo::canRealignStack(const MachineFunction &MF) const { - if (!TargetRegisterInfo::canRealignStack(MF)) - return false; - - // VE always has a fixed frame pointer register, so don't need to - // worry about needing to reserve it. [even if we don't have a frame - // pointer for our frame, it still cannot be used for other things, - // or register window traps will be SADNESS.] - - // If there's a reserved call frame, we can use VE to access locals. - if (getFrameLowering(MF)->hasReservedCallFrame(MF)) - return true; - - // Otherwise, we'd need a base pointer, but those aren't implemented - // for VE at the moment. - - return false; -} diff --git a/llvm/lib/Target/VE/VERegisterInfo.h b/llvm/lib/Target/VE/VERegisterInfo.h index 9a32da16bea60..334fb965a986f 100644 --- a/llvm/lib/Target/VE/VERegisterInfo.h +++ b/llvm/lib/Target/VE/VERegisterInfo.h @@ -40,8 +40,6 @@ struct VERegisterInfo : public VEGenRegisterInfo { RegScavenger *RS = nullptr) const override; Register getFrameRegister(const MachineFunction &MF) const override; - - bool canRealignStack(const MachineFunction &MF) const override; }; } // namespace llvm diff --git a/llvm/lib/Target/VE/VESubtarget.cpp b/llvm/lib/Target/VE/VESubtarget.cpp index f9c179e185282..3406a613e89d1 100644 --- a/llvm/lib/Target/VE/VESubtarget.cpp +++ b/llvm/lib/Target/VE/VESubtarget.cpp @@ -47,56 +47,15 @@ VESubtarget::VESubtarget(const Triple &TT, const std::string &CPU, InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), FrameLowering(*this) {} -int VESubtarget::getAdjustedFrameSize(int frameSize) const { +uint64_t VESubtarget::getAdjustedFrameSize(uint64_t FrameSize) const { + // Calculate adjusted frame size by adding the size of RSA frame, + // return address, and frame poitner as described in VEFrameLowering.cpp. + const VEFrameLowering *TFL = getFrameLowering(); - // VE stack frame: - // - // +----------------------------------------+ - // | Locals and temporaries | - // +----------------------------------------+ - // | Parameter area for callee | - // 176(fp) | | - // +----------------------------------------+ - // | Register save area (RSA) for callee | - // | | - // 16(fp) | 20 * 8 bytes | - // +----------------------------------------+ - // 8(fp) | Return address | - // +----------------------------------------+ - // 0(fp) | Frame pointer of caller | - // --------+----------------------------------------+-------- - // | Locals and temporaries for callee | - // +----------------------------------------+ - // | Parameter area for callee of callee | - // +----------------------------------------+ - // 16(sp) | RSA for callee of callee | - // +----------------------------------------+ - // 8(sp) | Return address | - // +----------------------------------------+ - // 0(sp) | Frame pointer of callee | - // +----------------------------------------+ + FrameSize += getRsaSize(); + FrameSize = alignTo(FrameSize, TFL->getStackAlign()); - // RSA frame: - // +----------------------------------------------+ - // 168(fp) | %s33 | - // +----------------------------------------------+ - // | %s19...%s32 | - // +----------------------------------------------+ - // 48(fp) | %s18 | - // +----------------------------------------------+ - // 40(fp) | Linkage area register (%s17) | - // +----------------------------------------------+ - // 32(fp) | Procedure linkage table register (%plt=%s16) | - // +----------------------------------------------+ - // 24(fp) | Global offset table register (%got=%s15) | - // +----------------------------------------------+ - // 16(fp) | Thread pointer register (%tp=%s14) | - // +----------------------------------------------+ - - frameSize += 176; // for RSA, RA, and FP - frameSize = alignTo(frameSize, 16); // requires 16 bytes alignment - - return frameSize; + return FrameSize; } bool VESubtarget::enableMachineScheduler() const { return true; } diff --git a/llvm/lib/Target/VE/VESubtarget.h b/llvm/lib/Target/VE/VESubtarget.h index 04c133342f2a3..213aca2ea3f96 100644 --- a/llvm/lib/Target/VE/VESubtarget.h +++ b/llvm/lib/Target/VE/VESubtarget.h @@ -70,9 +70,13 @@ class VESubtarget : public VEGenSubtargetInfo { VESubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); /// Given a actual stack size as determined by FrameInfo, this function - /// returns adjusted framesize which includes space for register window - /// spills and arguments. - int getAdjustedFrameSize(int stackSize) const; + /// returns adjusted framesize which includes space for RSA, return + /// address, and frame poitner. + uint64_t getAdjustedFrameSize(uint64_t FrameSize) const; + + /// Get the size of RSA, return address, and frame pointer as described + /// in VEFrameLowering.cpp. + unsigned getRsaSize(void) const { return 176; }; bool isTargetLinux() const { return TargetTriple.isOSLinux(); } }; diff --git a/llvm/lib/Target/VE/VVPInstrInfo.td b/llvm/lib/Target/VE/VVPInstrInfo.td new file mode 100644 index 0000000000000..81fbfe03b48f3 --- /dev/null +++ b/llvm/lib/Target/VE/VVPInstrInfo.td @@ -0,0 +1,43 @@ +//===-------------- VVPInstrInfo.td - VVP_* SDNode patterns ---------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the VE Vector Predicated SDNodes (VVP SDNodes). VVP +// SDNodes are an intermediate isel layer between the vector SDNodes emitted by +// LLVM and the actual VE vector instructions. For example: +// +// ADD(x,y) --> VVP_ADD(x,y,mask,evl) --> VADDSWSXrvml(x,y,mask,evl) +// ^ ^ ^ +// The standard The VVP layer SDNode. The VE vector instruction. +// SDNode. +// +// TODO explain how VVP nodes relate to VP SDNodes once VP ISel is uptream. +//===----------------------------------------------------------------------===// + +// Binary Operators { + +// BinaryOp(x,y,mask,vl) +def SDTIntBinOpVVP : SDTypeProfile<1, 4, [ // vp_add, vp_and, etc. + SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>, + SDTCisInt<0>, + SDTCisSameNumEltsAs<0, 3>, + IsVLVT<4> +]>; + +// Binary operator commutative pattern. +class vvp_commutative : + PatFrags< + (ops node:$lhs, node:$rhs, node:$mask, node:$vlen), + [(RootOp node:$lhs, node:$rhs, node:$mask, node:$vlen), + (RootOp node:$rhs, node:$lhs, node:$mask, node:$vlen)]>; + +// VVP node definitions. +def vvp_add : SDNode<"VEISD::VVP_ADD", SDTIntBinOpVVP>; +def c_vvp_add : vvp_commutative; + +// } Binary Operators diff --git a/llvm/lib/Target/VE/VVPInstrPatternsVec.td b/llvm/lib/Target/VE/VVPInstrPatternsVec.td new file mode 100644 index 0000000000000..2345173314a4a --- /dev/null +++ b/llvm/lib/Target/VE/VVPInstrPatternsVec.td @@ -0,0 +1,68 @@ +//===----------- VVPInstrPatternsVec.td - VVP_* SDNode patterns -----------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes how VVP_* SDNodes are lowered to machine instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// +// VVP SDNode definitions. +// +//===----------------------------------------------------------------------===// +include "VVPInstrInfo.td" + +multiclass VectorBinaryArith< + SDPatternOperator OpNode, + ValueType ScalarVT, ValueType DataVT, ValueType MaskVT, + string OpBaseName, + SDPatternOperator ImmOp, SDNodeXForm ImmCast> { + // No mask. + def : Pat<(OpNode + (any_broadcast ScalarVT:$sx), + DataVT:$vy, (MaskVT true_mask), i32:$avl), + (!cast(OpBaseName#"rvl") + ScalarVT:$sx, $vy, $avl)>; + def : Pat<(OpNode DataVT:$vx, DataVT:$vy, (MaskVT true_mask), i32:$avl), + (!cast(OpBaseName#"vvl") + $vx, $vy, $avl)>; + + // Mask. + def : Pat<(OpNode + (any_broadcast ScalarVT:$sx), + DataVT:$vy, MaskVT:$mask, i32:$avl), + (!cast(OpBaseName#"rvml") + ScalarVT:$sx, $vy, $mask, $avl)>; + def : Pat<(OpNode DataVT:$vx, DataVT:$vy, MaskVT:$mask, i32:$avl), + (!cast(OpBaseName#"vvml") + $vx, $vy, $mask, $avl)>; + + // TODO We do not specify patterns for the immediate variants here. There + // will be an immediate folding pass that takes care of switching to the + // immediate variant where applicable. + + // TODO Fold vvp_select into passthru. +} + +// Expand both 64bit and 32 bit variant (256 elements) +multiclass VectorBinaryArith_ShortLong< + SDPatternOperator OpNode, + ValueType LongScalarVT, ValueType LongDataVT, string LongOpBaseName, + ValueType ShortScalarVT, ValueType ShortDataVT, string ShortOpBaseName> { + defm : VectorBinaryArith; + defm : VectorBinaryArith; +} + + +defm : VectorBinaryArith_ShortLong; diff --git a/llvm/lib/Target/VE/VVPNodes.def b/llvm/lib/Target/VE/VVPNodes.def new file mode 100644 index 0000000000000..4319b332388e1 --- /dev/null +++ b/llvm/lib/Target/VE/VVPNodes.def @@ -0,0 +1,32 @@ +//===-- VVPNodes.def - Lists & properties of VE Vector Predication Nodes --===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines all VVP_* SDNodes and their properties +// +//===----------------------------------------------------------------------===// + +/// ADD_VVP_OP(VVPNAME,SDNAME) +/// \p VVPName is a VVP SDNode operator. +/// \p SDNAME is the generic SD opcode corresponding to \p VVPName. +#ifndef ADD_VVP_OP +#define ADD_VVP_OP(X, Y) +#endif + +/// ADD_BINARY_VVP_OP(VVPNAME,SDNAME) +/// \p VVPName is a VVP Binary operator. +/// \p SDNAME is the generic SD opcode corresponding to \p VVPName. +#ifndef ADD_BINARY_VVP_OP +#define ADD_BINARY_VVP_OP(X,Y) ADD_VVP_OP(X,Y) +#endif + +// Integer arithmetic. +ADD_BINARY_VVP_OP(VVP_ADD,ADD) + + +#undef ADD_BINARY_VVP_OP +#undef ADD_VVP_OP diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp index f207de68025f6..c29211246123e 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFStreamer.cpp @@ -26,6 +26,7 @@ class X86WinCOFFStreamer : public MCWinCOFFStreamer { : MCWinCOFFStreamer(C, std::move(AB), std::move(CE), std::move(OW)) {} void EmitWinEHHandlerData(SMLoc Loc) override; + void EmitWindowsUnwindTables(WinEH::FrameInfo *Frame) override; void EmitWindowsUnwindTables() override; void EmitCVFPOData(const MCSymbol *ProcSym, SMLoc Loc) override; void finishImpl() override; @@ -37,7 +38,11 @@ void X86WinCOFFStreamer::EmitWinEHHandlerData(SMLoc Loc) { // We have to emit the unwind info now, because this directive // actually switches to the .xdata section. if (WinEH::FrameInfo *CurFrame = getCurrentWinFrameInfo()) - EHStreamer.EmitUnwindInfo(*this, CurFrame); + EHStreamer.EmitUnwindInfo(*this, CurFrame, /* HandlerData = */ true); +} + +void X86WinCOFFStreamer::EmitWindowsUnwindTables(WinEH::FrameInfo *Frame) { + EHStreamer.EmitUnwindInfo(*this, Frame, /* HandlerData = */ false); } void X86WinCOFFStreamer::EmitWindowsUnwindTables() { diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index e59ebd701528b..15b04c0c7357e 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -779,14 +779,14 @@ bool X86FastISel::handleConstantAddresses(const Value *V, X86AddressMode &AM) { if (TLI.getPointerTy(DL) == MVT::i64) { Opc = X86::MOV64rm; RC = &X86::GR64RegClass; - - if (Subtarget->isPICStyleRIPRel()) - StubAM.Base.Reg = X86::RIP; } else { Opc = X86::MOV32rm; RC = &X86::GR32RegClass; } + if (Subtarget->isPICStyleRIPRel()) + StubAM.Base.Reg = X86::RIP; + LoadReg = createResultReg(RC); MachineInstrBuilder LoadMI = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), LoadReg); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index ae4cc6424ae64..5cbca95f45f52 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1313,6 +1313,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom); setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom); setOperationAction(ISD::SSUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom); + setOperationAction(ISD::UADDSAT, MVT::v8i32, Custom); + setOperationAction(ISD::USUBSAT, MVT::v8i32, Custom); + setOperationAction(ISD::UADDSAT, MVT::v4i64, Custom); + setOperationAction(ISD::USUBSAT, MVT::v4i64, Custom); for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) { setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom); @@ -26854,50 +26858,58 @@ static SDValue LowerADDSAT_SUBSAT(SDValue Op, SelectionDAG &DAG, MVT VT = Op.getSimpleValueType(); SDValue X = Op.getOperand(0), Y = Op.getOperand(1); unsigned Opcode = Op.getOpcode(); + SDLoc DL(Op); + if (VT.getScalarType() == MVT::i1) { - SDLoc dl(Op); switch (Opcode) { default: llvm_unreachable("Expected saturated arithmetic opcode"); case ISD::UADDSAT: case ISD::SADDSAT: // *addsat i1 X, Y --> X | Y - return DAG.getNode(ISD::OR, dl, VT, X, Y); + return DAG.getNode(ISD::OR, DL, VT, X, Y); case ISD::USUBSAT: case ISD::SSUBSAT: // *subsat i1 X, Y --> X & ~Y - return DAG.getNode(ISD::AND, dl, VT, X, DAG.getNOT(dl, Y, VT)); + return DAG.getNode(ISD::AND, DL, VT, X, DAG.getNOT(DL, Y, VT)); } } - if (VT.is128BitVector()) { - // Avoid the generic expansion with min/max if we don't have pminu*/pmaxu*. - const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - EVT SetCCResultType = TLI.getSetCCResultType(DAG.getDataLayout(), - *DAG.getContext(), VT); - SDLoc DL(Op); - if (Opcode == ISD::UADDSAT && !TLI.isOperationLegal(ISD::UMIN, VT)) { - // uaddsat X, Y --> (X >u (X + Y)) ? -1 : X + Y - SDValue Add = DAG.getNode(ISD::ADD, DL, VT, X, Y); - SDValue Cmp = DAG.getSetCC(DL, SetCCResultType, X, Add, ISD::SETUGT); - return DAG.getSelect(DL, VT, Cmp, DAG.getAllOnesConstant(DL, VT), Add); - } - if (Opcode == ISD::USUBSAT && !TLI.isOperationLegal(ISD::UMAX, VT)) { - // usubsat X, Y --> (X >u Y) ? X - Y : 0 - SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, X, Y); - SDValue Cmp = DAG.getSetCC(DL, SetCCResultType, X, Y, ISD::SETUGT); - return DAG.getSelect(DL, VT, Cmp, Sub, DAG.getConstant(0, DL, VT)); - } - // Use default expansion. - return SDValue(); - } - - if (VT == MVT::v32i16 || VT == MVT::v64i8) + if (VT == MVT::v32i16 || VT == MVT::v64i8 || + (VT.is256BitVector() && !Subtarget.hasInt256())) { + assert(Op.getSimpleValueType().isInteger() && + "Only handle AVX vector integer operation"); return splitVectorIntBinary(Op, DAG); + } - assert(Op.getSimpleValueType().is256BitVector() && - Op.getSimpleValueType().isInteger() && - "Only handle AVX 256-bit vector integer operation"); - return splitVectorIntBinary(Op, DAG); + // Avoid the generic expansion with min/max if we don't have pminu*/pmaxu*. + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + EVT SetCCResultType = + TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); + + if (Opcode == ISD::UADDSAT && !TLI.isOperationLegal(ISD::UMIN, VT)) { + // uaddsat X, Y --> (X >u (X + Y)) ? -1 : X + Y + SDValue Add = DAG.getNode(ISD::ADD, DL, VT, X, Y); + SDValue Cmp = DAG.getSetCC(DL, SetCCResultType, X, Add, ISD::SETUGT); + // TODO: Move this to DAGCombiner? + if (SetCCResultType == VT && + DAG.ComputeNumSignBits(Cmp) == VT.getScalarSizeInBits()) + return DAG.getNode(ISD::OR, DL, VT, Cmp, Add); + return DAG.getSelect(DL, VT, Cmp, DAG.getAllOnesConstant(DL, VT), Add); + } + + if (Opcode == ISD::USUBSAT && !TLI.isOperationLegal(ISD::UMAX, VT)) { + // usubsat X, Y --> (X >u Y) ? X - Y : 0 + SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, X, Y); + SDValue Cmp = DAG.getSetCC(DL, SetCCResultType, X, Y, ISD::SETUGT); + // TODO: Move this to DAGCombiner? + if (SetCCResultType == VT && + DAG.ComputeNumSignBits(Cmp) == VT.getScalarSizeInBits()) + return DAG.getNode(ISD::AND, DL, VT, Cmp, Sub); + return DAG.getSelect(DL, VT, Cmp, Sub, DAG.getConstant(0, DL, VT)); + } + + // Use default expansion. + return SDValue(); } static SDValue LowerABS(SDValue Op, const X86Subtarget &Subtarget, @@ -26947,34 +26959,8 @@ static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) { if (VT == MVT::v32i16 || VT == MVT::v64i8) return splitVectorIntBinary(Op, DAG); - SDLoc DL(Op); - unsigned Opcode = Op.getOpcode(); - SDValue N0 = Op.getOperand(0); - SDValue N1 = Op.getOperand(1); - - // For pre-SSE41, we can perform UMIN/UMAX v8i16 by using psubusw. - if (VT == MVT::v8i16) { - assert((Opcode == ISD::UMIN || Opcode == ISD::UMAX) && - "Unexpected MIN/MAX opcode"); - if (Opcode == ISD::UMIN) - return DAG.getNode(ISD::SUB, DL, VT, N0, - DAG.getNode(ISD::USUBSAT, DL, VT, N0, N1)); - return DAG.getNode(ISD::ADD, DL, VT, - DAG.getNode(ISD::USUBSAT, DL, VT, N1, N0), N0); - } - - // Else, expand to a compare/select. - ISD::CondCode CC; - switch (Opcode) { - case ISD::SMIN: CC = ISD::CondCode::SETLT; break; - case ISD::SMAX: CC = ISD::CondCode::SETGT; break; - case ISD::UMIN: CC = ISD::CondCode::SETULT; break; - case ISD::UMAX: CC = ISD::CondCode::SETUGT; break; - default: llvm_unreachable("Unknown MINMAX opcode"); - } - - SDValue Cond = DAG.getSetCC(DL, VT, N0, N1, CC); - return DAG.getSelect(DL, VT, Cond, N0, N1); + // Default to expand. + return SDValue(); } static SDValue LowerMUL(SDValue Op, const X86Subtarget &Subtarget, @@ -29832,35 +29818,6 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { } } -/// Places new result values for the node in Results (their number -/// and types must exactly match those of the original return values of -/// the node), or leaves Results empty, which indicates that the node is not -/// to be custom lowered after all. -void X86TargetLowering::LowerOperationWrapper(SDNode *N, - SmallVectorImpl &Results, - SelectionDAG &DAG) const { - SDValue Res = LowerOperation(SDValue(N, 0), DAG); - - if (!Res.getNode()) - return; - - // If the original node has one result, take the return value from - // LowerOperation as is. It might not be result number 0. - if (N->getNumValues() == 1) { - Results.push_back(Res); - return; - } - - // If the original node has multiple results, then the return node should - // have the same number of results. - assert((N->getNumValues() == Res->getNumValues()) && - "Lowering returned the wrong number of results!"); - - // Places new result values base on N result number. - for (unsigned I = 0, E = N->getNumValues(); I != E; ++I) - Results.push_back(Res.getValue(I)); -} - /// Replace a node with an illegal result type with a new node built out of /// custom code. void X86TargetLowering::ReplaceNodeResults(SDNode *N, diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 118b3add461d6..b7de117292a2c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -925,14 +925,6 @@ namespace llvm { /// SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; - /// Places new result values for the node in Results (their number - /// and types must exactly match those of the original return values of - /// the node), or leaves Results empty, which indicates that the node is not - /// to be custom lowered after all. - void LowerOperationWrapper(SDNode *N, - SmallVectorImpl &Results, - SelectionDAG &DAG) const override; - /// Replace the results of node with an illegal result /// type with new values built out of custom code. /// diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 339fd00164359..f223a152fff61 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -6533,7 +6533,7 @@ multiclass avx512_fma3p_213_f opc, string OpcodeStr, SDNode OpNode, avx512vl_f64_info, "PD">, VEX_W; } -defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86any_Fmadd, +defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", any_fma, X86Fmadd, X86FmaddRnd>; defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86any_Fmsub, X86Fmsub, X86FmsubRnd>; @@ -6624,7 +6624,7 @@ multiclass avx512_fma3p_231_f opc, string OpcodeStr, SDNode OpNode, avx512vl_f64_info, "PD">, VEX_W; } -defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86any_Fmadd, +defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", any_fma, X86Fmadd, X86FmaddRnd>; defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86any_Fmsub, X86Fmsub, X86FmsubRnd>; @@ -6716,7 +6716,7 @@ multiclass avx512_fma3p_132_f opc, string OpcodeStr, SDNode OpNode, avx512vl_f64_info, "PD">, VEX_W; } -defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86any_Fmadd, +defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", any_fma, X86Fmadd, X86FmaddRnd>; defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86any_Fmsub, X86Fmsub, X86FmsubRnd>; @@ -6819,7 +6819,7 @@ multiclass avx512_fma3s opc213, bits<8> opc231, bits<8> opc132, } } -defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86any_Fmadd, X86FmaddRnd>; +defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", any_fma, X86FmaddRnd>; defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86any_Fmsub, X86FmsubRnd>; defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86any_Fnmadd, X86FnmaddRnd>; defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86any_Fnmsub, X86FnmsubRnd>; @@ -7027,7 +7027,7 @@ multiclass avx512_scalar_fma_patterns; defm : avx512_scalar_fma_patterns; @@ -7036,7 +7036,7 @@ defm : avx512_scalar_fma_patterns; -defm : avx512_scalar_fma_patterns; defm : avx512_scalar_fma_patterns; diff --git a/llvm/lib/Target/X86/X86InstrFMA.td b/llvm/lib/Target/X86/X86InstrFMA.td index 4dbd6bb8cd7e0..f9be3a783279e 100644 --- a/llvm/lib/Target/X86/X86InstrFMA.td +++ b/llvm/lib/Target/X86/X86InstrFMA.td @@ -123,7 +123,7 @@ multiclass fma3p_forms opc132, bits<8> opc213, bits<8> opc231, // Fused Multiply-Add let ExeDomain = SSEPackedSingle in { defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", "PS", - loadv4f32, loadv8f32, X86any_Fmadd, v4f32, v8f32, + loadv4f32, loadv8f32, any_fma, v4f32, v8f32, SchedWriteFMA>; defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", "PS", loadv4f32, loadv8f32, X86any_Fmsub, v4f32, v8f32, @@ -138,7 +138,7 @@ let ExeDomain = SSEPackedSingle in { let ExeDomain = SSEPackedDouble in { defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", "PD", - loadv2f64, loadv4f64, X86any_Fmadd, v2f64, + loadv2f64, loadv4f64, any_fma, v2f64, v4f64, SchedWriteFMA>, VEX_W; defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", "PD", loadv2f64, loadv4f64, X86any_Fmsub, v2f64, @@ -319,7 +319,7 @@ multiclass fma3s opc132, bits<8> opc213, bits<8> opc231, VR128, sdmem, sched>, VEX_W; } -defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", X86any_Fmadd, +defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", any_fma, SchedWriteFMA.Scl>, VEX_LIG; defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", X86any_Fmsub, SchedWriteFMA.Scl>, VEX_LIG; @@ -372,12 +372,12 @@ multiclass scalar_fma_patterns; +defm : scalar_fma_patterns; defm : scalar_fma_patterns; defm : scalar_fma_patterns; defm : scalar_fma_patterns; -defm : scalar_fma_patterns; +defm : scalar_fma_patterns; defm : scalar_fma_patterns; defm : scalar_fma_patterns; defm : scalar_fma_patterns; @@ -538,7 +538,7 @@ let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { let ExeDomain = SSEPackedSingle in { // Scalar Instructions - defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86any_Fmadd, loadf32, + defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, any_fma, loadf32, SchedWriteFMA.Scl>, fma4s_int<0x6A, "vfmaddss", ssmem, v4f32, SchedWriteFMA.Scl>; @@ -555,7 +555,7 @@ let ExeDomain = SSEPackedSingle in { fma4s_int<0x7E, "vfnmsubss", ssmem, v4f32, SchedWriteFMA.Scl>; // Packed Instructions - defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86any_Fmadd, v4f32, v8f32, + defm VFMADDPS4 : fma4p<0x68, "vfmaddps", any_fma, v4f32, v8f32, loadv4f32, loadv8f32, SchedWriteFMA>; defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86any_Fmsub, v4f32, v8f32, loadv4f32, loadv8f32, SchedWriteFMA>; @@ -571,7 +571,7 @@ let ExeDomain = SSEPackedSingle in { let ExeDomain = SSEPackedDouble in { // Scalar Instructions - defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86any_Fmadd, loadf64, + defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, any_fma, loadf64, SchedWriteFMA.Scl>, fma4s_int<0x6B, "vfmaddsd", sdmem, v2f64, SchedWriteFMA.Scl>; @@ -588,7 +588,7 @@ let ExeDomain = SSEPackedDouble in { fma4s_int<0x7F, "vfnmsubsd", sdmem, v2f64, SchedWriteFMA.Scl>; // Packed Instructions - defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86any_Fmadd, v2f64, v4f64, + defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", any_fma, v2f64, v4f64, loadv2f64, loadv4f64, SchedWriteFMA>; defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86any_Fmsub, v2f64, v4f64, loadv2f64, loadv4f64, SchedWriteFMA>; @@ -629,12 +629,12 @@ multiclass scalar_fma4_patterns; +defm : scalar_fma4_patterns; defm : scalar_fma4_patterns; defm : scalar_fma4_patterns; defm : scalar_fma4_patterns; -defm : scalar_fma4_patterns; +defm : scalar_fma4_patterns; defm : scalar_fma4_patterns; defm : scalar_fma4_patterns; defm : scalar_fma4_patterns; diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td index fde3bc3f0be8b..9cea4cbc7b8ac 100644 --- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -540,9 +540,6 @@ def X86fgetexpSAEs : SDNode<"X86ISD::FGETEXPS_SAE", SDTFPBinOp>; def X86Fmadd : SDNode<"ISD::FMA", SDTFPTernaryOp, [SDNPCommutative]>; def X86strict_Fmadd : SDNode<"ISD::STRICT_FMA", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>; -def X86any_Fmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3), - [(X86strict_Fmadd node:$src1, node:$src2, node:$src3), - (X86Fmadd node:$src1, node:$src2, node:$src3)]>; def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFPTernaryOp, [SDNPCommutative]>; def X86strict_Fnmadd : SDNode<"X86ISD::STRICT_FNMADD", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>; def X86any_Fnmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3), diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 2c35f74ab95ef..770317a9a8b5c 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -2483,7 +2483,7 @@ int X86TTIImpl::getTypeBasedIntrinsicInstrCost( { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ }; static const CostTblEntry AVX1CostTbl[] = { - { ISD::ABS, MVT::v4i64, 6 }, // VBLENDVPD(X,VPSUBQ(0,X),X) + { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) { ISD::ABS, MVT::v8i32, 3 }, { ISD::ABS, MVT::v16i16, 3 }, { ISD::ABS, MVT::v32i8, 3 }, @@ -2554,13 +2554,13 @@ int X86TTIImpl::getTypeBasedIntrinsicInstrCost( { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd }; static const CostTblEntry SSE42CostTbl[] = { - { ISD::ABS, MVT::v2i64, 3 }, // BLENDVPD(X,PSUBQ(0,X),X) { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ }; static const CostTblEntry SSE41CostTbl[] = { + { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) { ISD::SMAX, MVT::v4i32, 1 }, { ISD::SMAX, MVT::v16i8, 1 }, { ISD::SMIN, MVT::v4i32, 1 }, @@ -2597,8 +2597,8 @@ int X86TTIImpl::getTypeBasedIntrinsicInstrCost( static const CostTblEntry SSE2CostTbl[] = { { ISD::ABS, MVT::v2i64, 4 }, { ISD::ABS, MVT::v4i32, 3 }, - { ISD::ABS, MVT::v8i16, 3 }, - { ISD::ABS, MVT::v16i8, 3 }, + { ISD::ABS, MVT::v8i16, 2 }, + { ISD::ABS, MVT::v16i8, 2 }, { ISD::BITREVERSE, MVT::v2i64, 29 }, { ISD::BITREVERSE, MVT::v4i32, 27 }, { ISD::BITREVERSE, MVT::v8i16, 27 }, @@ -2668,6 +2668,7 @@ int X86TTIImpl::getTypeBasedIntrinsicInstrCost( { ISD::CTPOP, MVT::i8, 1 }, }; static const CostTblEntry X64CostTbl[] = { // 64-bit targets + { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV { ISD::BITREVERSE, MVT::i64, 14 }, { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH @@ -2677,6 +2678,8 @@ int X86TTIImpl::getTypeBasedIntrinsicInstrCost( { ISD::UMULO, MVT::i64, 2 }, // mulq + seto }; static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets + { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV + { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV { ISD::BITREVERSE, MVT::i32, 14 }, { ISD::BITREVERSE, MVT::i16, 14 }, { ISD::BITREVERSE, MVT::i8, 11 }, diff --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp index 204fb5d8f4c70..1a000c1913c60 100644 --- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp @@ -576,9 +576,10 @@ void FrameTypeBuilder::addFieldForAllocas(const Function &F, StackLifetimeAnalyzer.getLiveRange(AI2)); }; auto GetAllocaSize = [&](const AllocaInfo &A) { - Optional RetSize = A.Alloca->getAllocationSizeInBits(DL); - assert(RetSize && "We can't handle scalable type now.\n"); - return RetSize.getValue(); + Optional RetSize = A.Alloca->getAllocationSizeInBits(DL); + assert(RetSize && "Variable Length Arrays (VLA) are not supported.\n"); + assert(!RetSize->isScalable() && "Scalable vectors are not yet supported"); + return RetSize->getFixedSize(); }; // Put larger allocas in the front. So the larger allocas have higher // priority to merge, which can save more space potentially. Also each diff --git a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp index 2e5d9095989ea..171d42788d76f 100644 --- a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp +++ b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Transforms/IPO/FunctionAttrs.h" +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SCCIterator.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SetVector.h" @@ -166,7 +167,7 @@ static MemoryAccessKind checkFunctionMemoryAccess(Function &F, bool ThisBody, AAMDNodes AAInfo; I->getAAMetadata(AAInfo); - MemoryLocation Loc(Arg, LocationSize::unknown(), AAInfo); + MemoryLocation Loc = MemoryLocation::getBeforeOrAfter(Arg, AAInfo); // Skip accesses to local or constant memory as they don't impact the // externally visible mod/ref behavior. @@ -1218,6 +1219,11 @@ bool AttributeInferer::run(const SCCNodeSet &SCCNodes) { return Changed; } +struct SCCNodesResult { + SCCNodeSet SCCNodes; + bool HasUnknownCall; +}; + } // end anonymous namespace /// Helper for non-Convergent inference predicate InstrBreaksAttribute. @@ -1265,15 +1271,10 @@ static bool InstrBreaksNoFree(Instruction &I, const SCCNodeSet &SCCNodes) { return true; } -/// Infer attributes from all functions in the SCC by scanning every -/// instruction for compliance to the attribute assumptions. Currently it -/// does: -/// - removal of Convergent attribute -/// - addition of NoUnwind attribute +/// Attempt to remove convergent function attribute when possible. /// /// Returns true if any changes to function attributes were made. -static bool inferAttrsFromFunctionBodies(const SCCNodeSet &SCCNodes) { - +static bool inferConvergent(const SCCNodeSet &SCCNodes) { AttributeInferer AI; // Request to remove the convergent attribute from all functions in the SCC @@ -1295,6 +1296,18 @@ static bool inferAttrsFromFunctionBodies(const SCCNodeSet &SCCNodes) { F.setNotConvergent(); }, /* RequiresExactDefinition= */ false}); + // Perform all the requested attribute inference actions. + return AI.run(SCCNodes); +} + +/// Infer attributes from all functions in the SCC by scanning every +/// instruction for compliance to the attribute assumptions. Currently it +/// does: +/// - addition of NoUnwind attribute +/// +/// Returns true if any changes to function attributes were made. +static bool inferAttrsFromFunctionBodies(const SCCNodeSet &SCCNodes) { + AttributeInferer AI; if (!DisableNoUnwindInference) // Request to infer nounwind attribute for all the functions in the SCC if @@ -1376,27 +1389,57 @@ static bool addNoRecurseAttrs(const SCCNodeSet &SCCNodes) { return true; } +static SCCNodesResult createSCCNodeSet(ArrayRef Functions) { + SCCNodesResult Res; + Res.HasUnknownCall = false; + for (Function *F : Functions) { + if (!F || F->hasOptNone() || F->hasFnAttribute(Attribute::Naked)) { + // Treat any function we're trying not to optimize as if it were an + // indirect call and omit it from the node set used below. + Res.HasUnknownCall = true; + continue; + } + // Track whether any functions in this SCC have an unknown call edge. + // Note: if this is ever a performance hit, we can common it with + // subsequent routines which also do scans over the instructions of the + // function. + if (!Res.HasUnknownCall) { + for (Instruction &I : instructions(*F)) { + if (auto *CB = dyn_cast(&I)) { + if (!CB->getCalledFunction()) { + Res.HasUnknownCall = true; + break; + } + } + } + } + Res.SCCNodes.insert(F); + } + return Res; +} + template -static bool deriveAttrsInPostOrder(SCCNodeSet &SCCNodes, - AARGetterT &&AARGetter, - bool HasUnknownCall) { +static bool deriveAttrsInPostOrder(ArrayRef Functions, + AARGetterT &&AARGetter) { + SCCNodesResult Nodes = createSCCNodeSet(Functions); bool Changed = false; // Bail if the SCC only contains optnone functions. - if (SCCNodes.empty()) + if (Nodes.SCCNodes.empty()) return Changed; - Changed |= addArgumentReturnedAttrs(SCCNodes); - Changed |= addReadAttrs(SCCNodes, AARGetter); - Changed |= addArgumentAttrs(SCCNodes); + Changed |= addArgumentReturnedAttrs(Nodes.SCCNodes); + Changed |= addReadAttrs(Nodes.SCCNodes, AARGetter); + Changed |= addArgumentAttrs(Nodes.SCCNodes); + Changed |= inferConvergent(Nodes.SCCNodes); // If we have no external nodes participating in the SCC, we can deduce some // more precise attributes as well. - if (!HasUnknownCall) { - Changed |= addNoAliasAttrs(SCCNodes); - Changed |= addNonNullAttrs(SCCNodes); - Changed |= inferAttrsFromFunctionBodies(SCCNodes); - Changed |= addNoRecurseAttrs(SCCNodes); + if (!Nodes.HasUnknownCall) { + Changed |= addNoAliasAttrs(Nodes.SCCNodes); + Changed |= addNonNullAttrs(Nodes.SCCNodes); + Changed |= inferAttrsFromFunctionBodies(Nodes.SCCNodes); + Changed |= addNoRecurseAttrs(Nodes.SCCNodes); } return Changed; @@ -1415,35 +1458,12 @@ PreservedAnalyses PostOrderFunctionAttrsPass::run(LazyCallGraph::SCC &C, return FAM.getResult(F); }; - // Fill SCCNodes with the elements of the SCC. Also track whether there are - // any external or opt-none nodes that will prevent us from optimizing any - // part of the SCC. - SCCNodeSet SCCNodes; - bool HasUnknownCall = false; + SmallVector Functions; for (LazyCallGraph::Node &N : C) { - Function &F = N.getFunction(); - if (F.hasOptNone() || F.hasFnAttribute(Attribute::Naked)) { - // Treat any function we're trying not to optimize as if it were an - // indirect call and omit it from the node set used below. - HasUnknownCall = true; - continue; - } - // Track whether any functions in this SCC have an unknown call edge. - // Note: if this is ever a performance hit, we can common it with - // subsequent routines which also do scans over the instructions of the - // function. - if (!HasUnknownCall) - for (Instruction &I : instructions(F)) - if (auto *CB = dyn_cast(&I)) - if (!CB->getCalledFunction()) { - HasUnknownCall = true; - break; - } - - SCCNodes.insert(&F); + Functions.push_back(&N.getFunction()); } - if (deriveAttrsInPostOrder(SCCNodes, AARGetter, HasUnknownCall)) + if (deriveAttrsInPostOrder(Functions, AARGetter)) return PreservedAnalyses::none(); return PreservedAnalyses::all(); @@ -1486,26 +1506,12 @@ Pass *llvm::createPostOrderFunctionAttrsLegacyPass() { template static bool runImpl(CallGraphSCC &SCC, AARGetterT AARGetter) { - - // Fill SCCNodes with the elements of the SCC. Used for quickly looking up - // whether a given CallGraphNode is in this SCC. Also track whether there are - // any external or opt-none nodes that will prevent us from optimizing any - // part of the SCC. - SCCNodeSet SCCNodes; - bool ExternalNode = false; + SmallVector Functions; for (CallGraphNode *I : SCC) { - Function *F = I->getFunction(); - if (!F || F->hasOptNone() || F->hasFnAttribute(Attribute::Naked)) { - // External node or function we're trying not to optimize - we both avoid - // transform them and avoid leveraging information they provide. - ExternalNode = true; - continue; - } - - SCCNodes.insert(F); + Functions.push_back(I->getFunction()); } - return deriveAttrsInPostOrder(SCCNodes, AARGetter, ExternalNode); + return deriveAttrsInPostOrder(Functions, AARGetter); } bool PostOrderFunctionAttrsLegacyPass::runOnSCC(CallGraphSCC &SCC) { diff --git a/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp b/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp index 4a1eaa85276b7..dbc1159b8a32d 100644 --- a/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp +++ b/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp @@ -51,9 +51,9 @@ using namespace llvm; -static cl::opt - RunPartialInlining("enable-partial-inlining", cl::init(false), cl::Hidden, - cl::ZeroOrMore, cl::desc("Run Partial inlinining pass")); +cl::opt RunPartialInlining("enable-partial-inlining", cl::init(false), + cl::Hidden, cl::ZeroOrMore, + cl::desc("Run Partial inlinining pass")); static cl::opt UseGVNAfterVectorization("use-gvn-after-vectorization", @@ -72,8 +72,8 @@ static cl::opt SYCLOptimizationMode("sycl-opt", cl::init(false), cl::Hidden, cl::desc("Enable SYCL optimization mode.")); -static cl::opt RunNewGVN("enable-newgvn", cl::init(false), cl::Hidden, - cl::desc("Run the NewGVN pass")); +cl::opt RunNewGVN("enable-newgvn", cl::init(false), cl::Hidden, + cl::desc("Run the NewGVN pass")); // Experimental option to use CFL-AA enum class CFLAAType { None, Steensgaard, Andersen, Both }; @@ -92,13 +92,13 @@ static cl::opt EnableLoopInterchange( "enable-loopinterchange", cl::init(false), cl::Hidden, cl::desc("Enable the new, experimental LoopInterchange Pass")); -static cl::opt EnableUnrollAndJam("enable-unroll-and-jam", - cl::init(false), cl::Hidden, - cl::desc("Enable Unroll And Jam Pass")); +cl::opt EnableUnrollAndJam("enable-unroll-and-jam", cl::init(false), + cl::Hidden, + cl::desc("Enable Unroll And Jam Pass")); -static cl::opt EnableLoopFlatten("enable-loop-flatten", cl::init(false), - cl::Hidden, - cl::desc("Enable the LoopFlatten Pass")); +cl::opt EnableLoopFlatten("enable-loop-flatten", cl::init(false), + cl::Hidden, + cl::desc("Enable the LoopFlatten Pass")); static cl::opt EnablePrepareForThinLTO("prepare-for-thinlto", cl::init(false), cl::Hidden, @@ -119,14 +119,14 @@ cl::opt DisablePreInliner("disable-preinline", cl::init(false), cl::Hidden, cl::desc("Disable pre-instrumentation inliner")); -static cl::opt PreInlineThreshold( +cl::opt PreInlineThreshold( "preinline-threshold", cl::Hidden, cl::init(75), cl::ZeroOrMore, cl::desc("Control the amount of inlining in pre-instrumentation inliner " "(default = 75)")); -static cl::opt EnableGVNHoist( - "enable-gvn-hoist", cl::init(false), cl::ZeroOrMore, - cl::desc("Enable the GVN hoisting pass (default = off)")); +cl::opt + EnableGVNHoist("enable-gvn-hoist", cl::init(false), cl::ZeroOrMore, + cl::desc("Enable the GVN hoisting pass (default = off)")); static cl::opt DisableLibCallsShrinkWrap("disable-libcalls-shrinkwrap", cl::init(false), @@ -138,13 +138,13 @@ static cl::opt EnableSimpleLoopUnswitch( cl::desc("Enable the simple loop unswitch pass. Also enables independent " "cleanup passes integrated into the loop pass manager pipeline.")); -static cl::opt EnableGVNSink( - "enable-gvn-sink", cl::init(false), cl::ZeroOrMore, - cl::desc("Enable the GVN sinking pass (default = off)")); +cl::opt + EnableGVNSink("enable-gvn-sink", cl::init(false), cl::ZeroOrMore, + cl::desc("Enable the GVN sinking pass (default = off)")); // This option is used in simplifying testing SampleFDO optimizations for // profile loading. -static cl::opt +cl::opt EnableCHR("enable-chr", cl::init(true), cl::Hidden, cl::desc("Enable control height reduction optimization (CHR)")); @@ -449,13 +449,13 @@ void PassManagerBuilder::addFunctionSimplificationPasses( MPM.add(createLoopFlattenPass()); // Flatten loops MPM.add(createLoopSimplifyCFGPass()); } + MPM.add(createLoopIdiomPass()); // Recognize idioms like memset. // TODO: this pass hurts performance due to promotions of induction variables // from 32-bit value to 64-bit values. I assume it's because SPIR is a virtual // target with unlimited # of registers and pass doesn't take into account // that on real HW this promotion is not beneficial. if (!SYCLOptimizationMode) MPM.add(createIndVarSimplifyPass()); // Canonicalize indvars - MPM.add(createLoopIdiomPass()); // Recognize idioms like memset. addExtensionsToPM(EP_LateLoopOptimizations, MPM); MPM.add(createLoopDeletionPass()); // Delete dead loops diff --git a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp index e97f1acbb3962..5350d85e11f32 100644 --- a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp +++ b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp @@ -1030,6 +1030,10 @@ bool DevirtIndex::tryFindVirtualCallTargets( void DevirtModule::applySingleImplDevirt(VTableSlotInfo &SlotInfo, Constant *TheFn, bool &IsExported) { + // Don't devirtualize function if we're told to skip it + // in -wholeprogramdevirt-skip. + if (FunctionsToSkip.match(TheFn->stripPointerCasts()->getName())) + return; auto Apply = [&](CallSiteInfo &CSInfo) { for (auto &&VCallSite : CSInfo.CallSites) { if (RemarksEnabled) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index b8431a5a45321..bf356d0de94b7 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -1678,11 +1678,12 @@ Value *InstCombinerImpl::OptimizePointerDifference(Value *LHS, Value *RHS, I->getOpcode() == Instruction::Mul) I->setHasNoUnsignedWrap(); - // If we had a constant expression GEP on the other side offsetting the - // pointer, subtract it from the offset we have. + // If we have a 2nd GEP of the same base pointer, subtract the offsets. + // If both GEPs are inbounds, then the subtract does not have signed overflow. if (GEP2) { Value *Offset = EmitGEPOffset(GEP2); - Result = Builder.CreateSub(Result, Offset, "gepdiff"); + Result = Builder.CreateSub(Result, Offset, "gepdiff", /* NUW */ false, + GEP1->isInBounds() && GEP2->isInBounds()); } // If we have p - gep(p, ...) then we have to negate the result. @@ -1721,6 +1722,10 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) { return Res; } + // Try this before Negator to preserve NSW flag. + if (Instruction *R = factorizeMathWithShlOps(I, Builder)) + return R; + if (Constant *C = dyn_cast(Op0)) { Value *X; Constant *C2; @@ -1769,9 +1774,6 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) { if (Value *V = SimplifyUsingDistributiveLaws(I)) return replaceInstUsesWith(I, V); - if (Instruction *R = factorizeMathWithShlOps(I, Builder)) - return R; - if (I.getType()->isIntOrIntVectorTy(1)) return BinaryOperator::CreateXor(Op0, Op1); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp index 29c4aced75e73..06f22cdfb63de 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp @@ -2144,7 +2144,7 @@ static Instruction *foldShuffleWithInsert(ShuffleVectorInst &Shuf, uint64_t IdxC; if (match(V0, m_InsertElt(m_Value(X), m_Value(), m_ConstantInt(IdxC)))) { // shuf (inselt X, ?, IdxC), ?, Mask --> shuf X, ?, Mask - if (none_of(Mask, [IdxC](int MaskElt) { return MaskElt == (int)IdxC; })) + if (!is_contained(Mask, (int)IdxC)) return IC.replaceOperand(Shuf, 0, X); } if (match(V1, m_InsertElt(m_Value(X), m_Value(), m_ConstantInt(IdxC)))) { @@ -2152,7 +2152,7 @@ static Instruction *foldShuffleWithInsert(ShuffleVectorInst &Shuf, // accesses to the 2nd vector input of the shuffle. IdxC += NumElts; // shuf ?, (inselt X, ?, IdxC), Mask --> shuf ?, X, Mask - if (none_of(Mask, [IdxC](int MaskElt) { return MaskElt == (int)IdxC; })) + if (!is_contained(Mask, (int)IdxC)) return IC.replaceOperand(Shuf, 1, X); } diff --git a/llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp b/llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp index a99c58b74fb1c..9bfb176dcd7f3 100644 --- a/llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp +++ b/llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp @@ -1609,9 +1609,7 @@ static void insertTrivialPHIs(CHRScope *Scope, // Insert a trivial phi for I (phi [&I, P0], [&I, P1], ...) at // ExitBlock. Replace I with the new phi in UI unless UI is another // phi at ExitBlock. - unsigned PredCount = std::distance(pred_begin(ExitBlock), - pred_end(ExitBlock)); - PHINode *PN = PHINode::Create(I.getType(), PredCount, "", + PHINode *PN = PHINode::Create(I.getType(), pred_size(ExitBlock), "", &ExitBlock->front()); for (BasicBlock *Pred : predecessors(ExitBlock)) { PN->addIncoming(&I, Pred); diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp index 385795812df48..25b70f7ea68cd 100644 --- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp @@ -213,7 +213,6 @@ class HWAddressSanitizer { Value *getShadowNonTls(IRBuilder<> &IRB); void untagPointerOperand(Instruction *I, Value *Addr); - Value *shadowBase(); Value *memToShadow(Value *Shadow, IRBuilder<> &IRB); void instrumentMemAccessInline(Value *Ptr, bool IsWrite, unsigned AccessSizeIndex, diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index d4f481f7c3271..1d4f279aeff4c 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -2734,14 +2734,16 @@ struct MemorySanitizerVisitor : public InstVisitor { // We copy the shadow of \p CopyOp[NumUsedElements:] to \p // Out[NumUsedElements:]. This means that intrinsics without \p CopyOp always // return a fully initialized value. - void handleVectorConvertIntrinsic(IntrinsicInst &I, int NumUsedElements) { + void handleVectorConvertIntrinsic(IntrinsicInst &I, int NumUsedElements, + bool HasRoundingMode = false) { IRBuilder<> IRB(&I); Value *CopyOp, *ConvertOp; - switch (I.getNumArgOperands()) { - case 3: - assert(isa(I.getArgOperand(2)) && "Invalid rounding mode"); - LLVM_FALLTHROUGH; + assert((!HasRoundingMode || + isa(I.getArgOperand(I.getNumArgOperands() - 1))) && + "Invalid rounding mode"); + + switch (I.getNumArgOperands() - HasRoundingMode) { case 2: CopyOp = I.getArgOperand(0); ConvertOp = I.getArgOperand(1); @@ -3294,6 +3296,8 @@ struct MemorySanitizerVisitor : public InstVisitor { case Intrinsic::x86_avx512_cvtusi2ss: case Intrinsic::x86_avx512_cvtusi642sd: case Intrinsic::x86_avx512_cvtusi642ss: + handleVectorConvertIntrinsic(I, 1, true); + break; case Intrinsic::x86_sse2_cvtsd2si64: case Intrinsic::x86_sse2_cvtsd2si: case Intrinsic::x86_sse2_cvtsd2ss: diff --git a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp index a1050ee634512..330d25c4dbc8d 100644 --- a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp +++ b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp @@ -275,7 +275,7 @@ static MemoryLocation getLocForWrite(Instruction *Inst, default: return MemoryLocation(); // Unhandled intrinsic. case Intrinsic::init_trampoline: - return MemoryLocation(II->getArgOperand(0), LocationSize::unknown()); + return MemoryLocation::getAfter(II->getArgOperand(0)); case Intrinsic::masked_store: return MemoryLocation::getForArgument(II, 1, TLI); case Intrinsic::lifetime_end: { @@ -287,7 +287,7 @@ static MemoryLocation getLocForWrite(Instruction *Inst, if (auto *CB = dyn_cast(Inst)) // All the supported TLI functions so far happen to have dest as their // first argument. - return MemoryLocation(CB->getArgOperand(0), LocationSize::unknown()); + return MemoryLocation::getAfter(CB->getArgOperand(0)); return MemoryLocation(); } @@ -828,8 +828,7 @@ static bool handleFree(CallInst *F, AliasAnalysis *AA, MapVector &ThrowableInst) { bool MadeChange = false; - MemoryLocation Loc = MemoryLocation(F->getOperand(0), - LocationSize::unknown()); + MemoryLocation Loc = MemoryLocation::getAfter(F->getOperand(0)); SmallVector Blocks; Blocks.push_back(F->getParent()); @@ -1726,15 +1725,14 @@ struct DSEState { case LibFunc_strncpy: case LibFunc_strcat: case LibFunc_strncat: - return {MemoryLocation(CB->getArgOperand(0), - LocationSize::unknown())}; + return {MemoryLocation::getAfter(CB->getArgOperand(0))}; default: break; } } switch (CB->getIntrinsicID()) { case Intrinsic::init_trampoline: - return {MemoryLocation(CB->getArgOperand(0), LocationSize::unknown())}; + return {MemoryLocation::getAfter(CB->getArgOperand(0))}; case Intrinsic::masked_store: return {MemoryLocation::getForArgument(CB, 1, TLI)}; default: @@ -1829,8 +1827,7 @@ struct DSEState { if (auto *CB = dyn_cast(I)) { if (isFreeCall(I, &TLI)) - return {std::make_pair(MemoryLocation(CB->getArgOperand(0), - LocationSize::unknown()), + return {std::make_pair(MemoryLocation::getAfter(CB->getArgOperand(0)), true)}; } diff --git a/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp b/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp index 5ff4c9ad18f46..ab40a9e533de2 100644 --- a/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp +++ b/llvm/lib/Transforms/Scalar/IndVarSimplify.cpp @@ -1869,11 +1869,15 @@ bool IndVarSimplify::run(Loop *L) { // Now that we're done iterating through lists, clean up any instructions // which are now dead. - while (!DeadInsts.empty()) - if (Instruction *Inst = - dyn_cast_or_null(DeadInsts.pop_back_val())) + while (!DeadInsts.empty()) { + Value *V = DeadInsts.pop_back_val(); + + if (PHINode *PHI = dyn_cast_or_null(V)) + Changed |= RecursivelyDeleteDeadPHINode(PHI, TLI, MSSAU.get()); + else if (Instruction *Inst = dyn_cast_or_null(V)) Changed |= RecursivelyDeleteTriviallyDeadInstructions(Inst, TLI, MSSAU.get()); + } // The Rewriter may not be used from this point on. diff --git a/llvm/lib/Transforms/Scalar/JumpThreading.cpp b/llvm/lib/Transforms/Scalar/JumpThreading.cpp index 0c3ee85d10a88..b287a804600ae 100644 --- a/llvm/lib/Transforms/Scalar/JumpThreading.cpp +++ b/llvm/lib/Transforms/Scalar/JumpThreading.cpp @@ -543,6 +543,10 @@ static unsigned getJumpThreadDuplicationCost(BasicBlock *BB, // Debugger intrinsics don't incur code size. if (isa(I)) continue; + // Pseudo-probes don't incur code size. + if (isa(I)) + continue; + // If this is a pointer->pointer bitcast, it is free. if (isa(I) && I->getType()->isPointerTy()) continue; diff --git a/llvm/lib/Transforms/Scalar/LICM.cpp b/llvm/lib/Transforms/Scalar/LICM.cpp index 1885d1d9f5577..9d90986c54ad4 100644 --- a/llvm/lib/Transforms/Scalar/LICM.cpp +++ b/llvm/lib/Transforms/Scalar/LICM.cpp @@ -1209,8 +1209,7 @@ bool llvm::canSinkOrHoistInst(Instruction &I, AAResults *AA, DominatorTree *DT, bool Invalidated; if (CurAST) Invalidated = pointerInvalidatedByLoop( - MemoryLocation(Op, LocationSize::unknown(), AAMDNodes()), - CurAST, CurLoop, AA); + MemoryLocation::getBeforeOrAfter(Op), CurAST, CurLoop, AA); else Invalidated = pointerInvalidatedByLoopWithMSSA( MSSA, cast(MSSA->getMemoryAccess(CI)), CurLoop, I, diff --git a/llvm/lib/Transforms/Scalar/LoopFlatten.cpp b/llvm/lib/Transforms/Scalar/LoopFlatten.cpp index 3d9617d43aea7..aaff68436c135 100644 --- a/llvm/lib/Transforms/Scalar/LoopFlatten.cpp +++ b/llvm/lib/Transforms/Scalar/LoopFlatten.cpp @@ -35,6 +35,7 @@ #include "llvm/Analysis/ValueTracking.h" #include "llvm/IR/Dominators.h" #include "llvm/IR/Function.h" +#include "llvm/IR/IRBuilder.h" #include "llvm/IR/Module.h" #include "llvm/IR/PatternMatch.h" #include "llvm/IR/Verifier.h" @@ -66,7 +67,7 @@ static cl::opt static cl::opt WidenIV("loop-flatten-widen-iv", cl::Hidden, - cl::init(false), + cl::init(true), cl::desc("Widen the loop induction variables, if possible, so " "overflow checks won't reject flattening")); @@ -84,6 +85,9 @@ struct FlattenInfo { SmallPtrSet LinearIVUses; SmallPtrSet InnerPHIsToTransform; + // Whether this holds the flatten info before or after widening. + bool Widened = false; + FlattenInfo(Loop *OL, Loop *IL) : OuterLoop(OL), InnerLoop(IL) {}; }; @@ -335,8 +339,9 @@ static bool checkIVUsers(struct FlattenInfo &FI) { // transformation wouldn't be profitable. Value *InnerLimit = FI.InnerLimit; - if (auto *I = dyn_cast(InnerLimit)) - InnerLimit = I->getOperand(0); + if (FI.Widened && + (isa(InnerLimit) || isa(InnerLimit))) + InnerLimit = cast(InnerLimit)->getOperand(0); // Check that all uses of the inner loop's induction variable match the // expected pattern, recording the uses of the outer IV. @@ -347,7 +352,7 @@ static bool checkIVUsers(struct FlattenInfo &FI) { // After widening the IVs, a trunc instruction might have been introduced, so // look through truncs. - if (dyn_cast(U) ) { + if (isa(U)) { if (!U->hasOneUse()) return false; U = *U->user_begin(); @@ -544,20 +549,18 @@ static bool DoFlattenLoopPair(struct FlattenInfo &FI, DominatorTree *DT, BranchInst::Create(InnerExitBlock, InnerExitingBlock); DT->deleteEdge(InnerExitingBlock, FI.InnerLoop->getHeader()); - auto HasSExtUser = [] (Value *V) -> Value * { - for (User *U : V->users() ) - if (dyn_cast(U)) - return U; - return nullptr; - }; - // Replace all uses of the polynomial calculated from the two induction // variables with the one new one. + IRBuilder<> Builder(FI.OuterInductionPHI->getParent()->getTerminator()); for (Value *V : FI.LinearIVUses) { - // If the induction variable has been widened, look through the SExt. - if (Value *U = HasSExtUser(V)) - V = U; - V->replaceAllUsesWith(FI.OuterInductionPHI); + Value *OuterValue = FI.OuterInductionPHI; + if (FI.Widened) + OuterValue = Builder.CreateTrunc(FI.OuterInductionPHI, V->getType(), + "flatten.trunciv"); + + LLVM_DEBUG(dbgs() << "Replacing: "; V->dump(); + dbgs() << "with: "; OuterValue->dump()); + V->replaceAllUsesWith(OuterValue); } // Tell LoopInfo, SCEV and the pass manager that the inner loop has been @@ -613,6 +616,8 @@ static bool CanWidenIV(struct FlattenInfo &FI, DominatorTree *DT, RecursivelyDeleteDeadPHINode(WideIVs[i].NarrowIV); } // After widening, rediscover all the loop components. + assert(Widened && "Widenend IV expected"); + FI.Widened = true; return CanFlattenLoopPair(FI, DT, LI, SE, AC, TTI); } diff --git a/llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp b/llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp index ef872a586965a..526f1fe2388f9 100644 --- a/llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp +++ b/llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp @@ -844,7 +844,7 @@ mayLoopAccessLocation(Value *Ptr, ModRefInfo Access, Loop *L, // Get the location that may be stored across the loop. Since the access is // strided positively through memory, we say that the modified location starts // at the pointer and has infinite size. - LocationSize AccessSize = LocationSize::unknown(); + LocationSize AccessSize = LocationSize::afterPointer(); // If the loop iterates a fixed number of times, we can refine the access size // to be exactly the size of the memset, which is (BECount+1)*StoreSize diff --git a/llvm/lib/Transforms/Scalar/LoopInterchange.cpp b/llvm/lib/Transforms/Scalar/LoopInterchange.cpp index 81b7c3a8338a4..f676ffc18e2dd 100644 --- a/llvm/lib/Transforms/Scalar/LoopInterchange.cpp +++ b/llvm/lib/Transforms/Scalar/LoopInterchange.cpp @@ -452,7 +452,7 @@ struct LoopInterchange { bool isComputableLoopNest(LoopVector LoopList) { for (Loop *L : LoopList) { const SCEV *ExitCountOuter = SE->getBackedgeTakenCount(L); - if (ExitCountOuter == SE->getCouldNotCompute()) { + if (isa(ExitCountOuter)) { LLVM_DEBUG(dbgs() << "Couldn't compute backedge count\n"); return false; } diff --git a/llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp b/llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp index 74e32fb870b56..475448740ae47 100644 --- a/llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp +++ b/llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp @@ -56,6 +56,7 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils.h" +#include "llvm/Transforms/Utils/LoopSimplify.h" #include "llvm/Transforms/Utils/LoopVersioning.h" #include "llvm/Transforms/Utils/ScalarEvolutionExpander.h" #include "llvm/Transforms/Utils/SizeOpts.h" @@ -610,6 +611,7 @@ class LoadEliminationForLoop { static bool eliminateLoadsAcrossLoops(Function &F, LoopInfo &LI, DominatorTree &DT, BlockFrequencyInfo *BFI, ProfileSummaryInfo *PSI, + ScalarEvolution *SE, AssumptionCache *AC, function_ref GetLAI) { // Build up a worklist of inner-loops to transform to avoid iterator // invalidation. @@ -618,14 +620,17 @@ eliminateLoadsAcrossLoops(Function &F, LoopInfo &LI, DominatorTree &DT, // which merely optimizes the use of loads in a loop. SmallVector Worklist; + bool Changed = false; + for (Loop *TopLevelLoop : LI) - for (Loop *L : depth_first(TopLevelLoop)) + for (Loop *L : depth_first(TopLevelLoop)) { + Changed |= simplifyLoop(L, &DT, &LI, SE, AC, /*MSSAU*/ nullptr, false); // We only handle inner-most loops. if (L->isInnermost()) Worklist.push_back(L); + } // Now walk the identified inner loops. - bool Changed = false; for (Loop *L : Worklist) { // The actual work is performed by LoadEliminationForLoop. LoadEliminationForLoop LEL(L, &LI, GetLAI(*L), &DT, BFI, PSI); @@ -660,7 +665,7 @@ class LoopLoadElimination : public FunctionPass { // Process each loop nest in the function. return eliminateLoadsAcrossLoops( - F, LI, DT, BFI, PSI, + F, LI, DT, BFI, PSI, /*SE*/ nullptr, /*AC*/ nullptr, [&LAA](Loop &L) -> const LoopAccessInfo & { return LAA.getInfo(&L); }); } @@ -717,7 +722,7 @@ PreservedAnalyses LoopLoadEliminationPass::run(Function &F, auto &LAM = AM.getResult(F).getManager(); bool Changed = eliminateLoadsAcrossLoops( - F, LI, DT, BFI, PSI, [&](Loop &L) -> const LoopAccessInfo & { + F, LI, DT, BFI, PSI, &SE, &AC, [&](Loop &L) -> const LoopAccessInfo & { LoopStandardAnalysisResults AR = {AA, AC, DT, LI, SE, TLI, TTI, nullptr, MSSA}; return LAM.getResult(L, AR); diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp index 2713fa61ba31e..a1d182931d0f6 100644 --- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp +++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp @@ -59,7 +59,6 @@ #include "llvm/ADT/Hashing.h" #include "llvm/ADT/PointerIntPair.h" #include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/SetOperations.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallBitVector.h" #include "llvm/ADT/SmallPtrSet.h" @@ -81,7 +80,6 @@ #include "llvm/IR/BasicBlock.h" #include "llvm/IR/Constant.h" #include "llvm/IR/Constants.h" -#include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Dominators.h" #include "llvm/IR/GlobalValue.h" @@ -5788,27 +5786,6 @@ static bool ReduceLoopStrength(Loop *L, IVUsers &IU, ScalarEvolution &SE, if (MSSA) MSSAU = std::make_unique(MSSA); - // Debug preservation - record all llvm.dbg.value from the loop as well as - // the SCEV of their variable location. Since salvageDebugInfo may change the - // DIExpression we need to store the original here as well (i.e. it needs to - // be in sync with the SCEV). - SmallVector< - std::tuple, - 32> - DbgValues; - for (auto &B : L->getBlocks()) { - for (auto &I : *B) { - if (DbgValueInst *D = dyn_cast(&I)) { - auto V = D->getVariableLocation(); - if (!V || !SE.isSCEVable(V->getType())) - continue; - auto DS = SE.getSCEV(V); - DbgValues.push_back( - std::make_tuple(D, V->getType(), DS, D->getExpression())); - } - } - } - // Run the main LSR transformation. Changed |= LSRInstance(L, IU, SE, DT, LI, TTI, AC, TLI, MSSAU.get()).getChanged(); @@ -5830,40 +5807,6 @@ static bool ReduceLoopStrength(Loop *L, IVUsers &IU, ScalarEvolution &SE, DeleteDeadPHIs(L->getHeader(), &TLI, MSSAU.get()); } } - // Debug preservation - go through all recorded llvm.dbg.value and for those - // that now have an undef variable location use the recorded SCEV to try and - // update it. Compare with SCEV of Phi-nodes of loop header to find a - // suitable update candidate. SCEV match with constant offset is allowed and - // will be compensated for in the DIExpression. - if (Changed) { - for (auto &D : DbgValues) { - auto DbgValue = std::get(D); - auto DbgValueType = std::get(D); - auto DbgValueSCEV = std::get(D); - auto DbgDIExpr = std::get(D); - if (!isa(DbgValue->getVariableLocation())) - continue; - for (PHINode &Phi : L->getHeader()->phis()) { - if (DbgValueType != Phi.getType()) - continue; - if (!SE.isSCEVable(Phi.getType())) - continue; - auto PhiSCEV = SE.getSCEV(&Phi); - if (Optional Offset = - SE.computeConstantDifference(DbgValueSCEV, PhiSCEV)) { - auto &Ctx = DbgValue->getContext(); - DbgValue->setOperand( - 0, MetadataAsValue::get(Ctx, ValueAsMetadata::get(&Phi))); - if (Offset.getValue().getSExtValue()) { - SmallVector Ops; - DIExpression::appendOffset(Ops, Offset.getValue().getSExtValue()); - DbgDIExpr = DIExpression::prependOpcodes(DbgDIExpr, Ops, true); - } - DbgValue->setOperand(2, MetadataAsValue::get(Ctx, DbgDIExpr)); - } - } - } - } return Changed; } diff --git a/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp b/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp index 3d0ce87047add..2ff1e84807494 100644 --- a/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp +++ b/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp @@ -267,7 +267,7 @@ bool LoopVersioningLICM::legalLoopStructure() { // We need to be able to compute the loop trip count in order // to generate the bound checks. const SCEV *ExitCount = SE->getBackedgeTakenCount(CurLoop); - if (ExitCount == SE->getCouldNotCompute()) { + if (isa(ExitCount)) { LLVM_DEBUG(dbgs() << " loop does not has trip count\n"); return false; } diff --git a/llvm/lib/Transforms/Scalar/PlaceSafepoints.cpp b/llvm/lib/Transforms/Scalar/PlaceSafepoints.cpp index 4553b23532f21..ca114581a5156 100644 --- a/llvm/lib/Transforms/Scalar/PlaceSafepoints.cpp +++ b/llvm/lib/Transforms/Scalar/PlaceSafepoints.cpp @@ -243,7 +243,7 @@ static bool mustBeFiniteCountedLoop(Loop *L, ScalarEvolution *SE, BasicBlock *Pred) { // A conservative bound on the loop as a whole. const SCEV *MaxTrips = SE->getConstantMaxBackedgeTakenCount(L); - if (MaxTrips != SE->getCouldNotCompute() && + if (!isa(MaxTrips) && SE->getUnsignedRange(MaxTrips).getUnsignedMax().isIntN( CountedLoopTripWidth)) return true; @@ -255,7 +255,7 @@ static bool mustBeFiniteCountedLoop(Loop *L, ScalarEvolution *SE, // This returns an exact expression only. TODO: We really only need an // upper bound here, but SE doesn't expose that. const SCEV *MaxExec = SE->getExitCount(L, Pred); - if (MaxExec != SE->getCouldNotCompute() && + if (!isa(MaxExec) && SE->getUnsignedRange(MaxExec).getUnsignedMax().isIntN( CountedLoopTripWidth)) return true; diff --git a/llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp b/llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp index c5dc443300720..9e7cccc884127 100644 --- a/llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp +++ b/llvm/lib/Transforms/Scalar/TailRecursionElimination.cpp @@ -240,7 +240,11 @@ static bool markTails(Function &F, bool &AllCallsAreTailCalls, Escaped = ESCAPED; CallInst *CI = dyn_cast(&I); - if (!CI || CI->isTailCall() || isa(&I)) + // A PseudoProbeInst has the IntrInaccessibleMemOnly tag hence it is + // considered accessing memory and will be marked as a tail call if we + // don't bail out here. + if (!CI || CI->isTailCall() || isa(&I) || + isa(&I)) continue; bool IsNoTail = CI->isNoTailCall() || CI->hasOperandBundles(); @@ -752,7 +756,7 @@ bool TailRecursionEliminator::processBlock( return false; BasicBlock *Succ = BI->getSuccessor(0); - ReturnInst *Ret = dyn_cast(Succ->getFirstNonPHIOrDbg()); + ReturnInst *Ret = dyn_cast(Succ->getFirstNonPHIOrDbg(true)); if (!Ret) return false; diff --git a/llvm/lib/Transforms/Utils/Evaluator.cpp b/llvm/lib/Transforms/Utils/Evaluator.cpp index c5dfbf9d92d13..6fe29381c71ac 100644 --- a/llvm/lib/Transforms/Utils/Evaluator.cpp +++ b/llvm/lib/Transforms/Utils/Evaluator.cpp @@ -551,6 +551,10 @@ bool Evaluator::EvaluateBlock(BasicBlock::iterator CurInst, LLVM_DEBUG(dbgs() << "Skipping sideeffect intrinsic.\n"); ++CurInst; continue; + } else if (II->getIntrinsicID() == Intrinsic::pseudoprobe) { + LLVM_DEBUG(dbgs() << "Skipping pseudoprobe intrinsic.\n"); + ++CurInst; + continue; } LLVM_DEBUG(dbgs() << "Unknown intrinsic. Can not evaluate.\n"); diff --git a/llvm/lib/Transforms/Utils/FunctionComparator.cpp b/llvm/lib/Transforms/Utils/FunctionComparator.cpp index f25c4e5d6e99b..2696557a719fa 100644 --- a/llvm/lib/Transforms/Utils/FunctionComparator.cpp +++ b/llvm/lib/Transforms/Utils/FunctionComparator.cpp @@ -291,6 +291,7 @@ int FunctionComparator::cmpConstants(const Constant *L, switch (L->getValueID()) { case Value::UndefValueVal: + case Value::PoisonValueVal: case Value::ConstantTokenNoneVal: return TypesRes; case Value::ConstantIntVal: { diff --git a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp index 877495be2dcd8..c7e37fe0d1b33 100644 --- a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp +++ b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp @@ -2468,7 +2468,7 @@ Value *SCEVExpander::generateOverflowCheck(const SCEVAddRecExpr *AR, const SCEV *ExitCount = SE.getPredicatedBackedgeTakenCount(AR->getLoop(), Pred); - assert(ExitCount != SE.getCouldNotCompute() && "Invalid loop count"); + assert(!isa(ExitCount) && "Invalid loop count"); const SCEV *Step = AR->getStepRecurrence(SE); const SCEV *Start = AR->getStart(); diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index a48a335eda577..55ce05987bfd7 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -159,6 +159,8 @@ STATISTIC( NumLookupTablesHoles, "Number of switch instructions turned into lookup tables (holes checked)"); STATISTIC(NumTableCmpReuses, "Number of reused switch table lookup compares"); +STATISTIC(NumFoldBranchToCommonDest, + "Number of branches folded into predecessor basic block"); STATISTIC( NumHoistCommonCode, "Number of common instruction 'blocks' hoisted up to the begin block"); @@ -1981,7 +1983,9 @@ static Value *isSafeToSpeculateStore(Instruction *I, BasicBlock *BrBB, // Look for a store to the same pointer in BrBB. unsigned MaxNumInstToLookAt = 9; - for (Instruction &CurI : reverse(BrBB->instructionsWithoutDebug())) { + // Skip pseudo probe intrinsic calls which are not really killing any memory + // accesses. + for (Instruction &CurI : reverse(BrBB->instructionsWithoutDebug(true))) { if (!MaxNumInstToLookAt) break; --MaxNumInstToLookAt; @@ -2141,6 +2145,14 @@ bool SimplifyCFGOpt::SpeculativelyExecuteBB(BranchInst *BI, BasicBlock *ThenBB, continue; } + // Skip pseudo probes. The consequence is we lose track of the branch + // probability for ThenBB, which is fine since the optimization here takes + // place regardless of the branch probability. + if (isa(I)) { + SpeculatedDbgIntrinsics.push_back(I); + continue; + } + // Only speculatively execute a single instruction (not counting the // terminator) for now. ++SpeculatedInstructions; @@ -2495,7 +2507,8 @@ static bool FoldTwoEntryPHINode(PHINode *PN, const TargetTransformInfo &TTI, } else { DomBlock = *pred_begin(IfBlock1); for (BasicBlock::iterator I = IfBlock1->begin(); !I->isTerminator(); ++I) - if (!AggressiveInsts.count(&*I) && !isa(I)) { + if (!AggressiveInsts.count(&*I) && !isa(I) && + !isa(I)) { // This is not an aggressive instruction that we can promote. // Because of this, we won't be able to get rid of the control flow, so // the xform is not worth it. @@ -2508,7 +2521,8 @@ static bool FoldTwoEntryPHINode(PHINode *PN, const TargetTransformInfo &TTI, } else { DomBlock = *pred_begin(IfBlock2); for (BasicBlock::iterator I = IfBlock2->begin(); !I->isTerminator(); ++I) - if (!AggressiveInsts.count(&*I) && !isa(I)) { + if (!AggressiveInsts.count(&*I) && !isa(I) && + !isa(I)) { // This is not an aggressive instruction that we can promote. // Because of this, we won't be able to get rid of the control flow, so // the xform is not worth it. @@ -2698,6 +2712,12 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI, MemorySSAUpdater *MSSAU, const unsigned PredCount = pred_size(BB); bool Changed = false; + + auto _ = make_scope_exit([&]() { + if (Changed) + ++NumFoldBranchToCommonDest; + }); + TargetTransformInfo::TargetCostKind CostKind = BB->getParent()->hasMinSize() ? TargetTransformInfo::TCK_CodeSize : TargetTransformInfo::TCK_SizeAndLatency; @@ -2759,15 +2779,9 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI, MemorySSAUpdater *MSSAU, // Ignore dbg intrinsics. if (isa(I)) continue; - if (!I->hasOneUse() || !isSafeToSpeculativelyExecute(&*I)) - return Changed; - // I has only one use and can be executed unconditionally. - Instruction *User = dyn_cast(I->user_back()); - if (User == nullptr || User->getParent() != BB) + // I must be safe to execute unconditionally. + if (!isSafeToSpeculativelyExecute(&*I)) return Changed; - // I is used in the same BB. Since BI uses Cond and doesn't have more slots - // to use any other instruction, User must be an instruction between next(I) - // and Cond. // Account for the cost of duplicating this instruction into each // predecessor. @@ -2863,6 +2877,13 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI, MemorySSAUpdater *MSSAU, PBI->swapSuccessors(); } + // Before cloning instructions, notify the successor basic block that it + // is about to have a new predecessor. This will update PHI nodes, + // which will allow us to update live-out uses of bonus instructions. + if (BI->isConditional()) + AddPredecessorToBlock(PBI->getSuccessor(0) == BB ? TrueDest : FalseDest, + PredBlock, BB, MSSAU); + // If we have bonus instructions, clone them into the predecessor block. // Note that there may be multiple predecessor blocks, so we cannot move // bonus instructions to a predecessor block. @@ -2894,6 +2915,18 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI, MemorySSAUpdater *MSSAU, PredBlock->getInstList().insert(PBI->getIterator(), NewBonusInst); NewBonusInst->takeName(&*BonusInst); BonusInst->setName(BonusInst->getName() + ".old"); + BonusInst->replaceUsesWithIf(NewBonusInst, [BB](Use &U) { + auto *User = cast(U.getUser()); + // Ignore uses in the same block as the bonus instruction itself. + if (User->getParent() == BB) + return false; + // We can safely update external non-PHI uses. + if (!isa(User)) + return true; + // For PHI nodes, don't touch incoming values for same block + // as the bonus instruction itself. + return cast(User)->getIncomingBlock(U) != BB; + }); } // Clone Cond into the predecessor basic block, and or/and the @@ -2935,7 +2968,6 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI, MemorySSAUpdater *MSSAU, (SuccFalseWeight + SuccTrueWeight) + PredTrueWeight * SuccFalseWeight); } - AddPredecessorToBlock(TrueDest, PredBlock, BB, MSSAU); PBI->setSuccessor(0, TrueDest); } if (PBI->getSuccessor(1) == BB) { @@ -2950,7 +2982,6 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI, MemorySSAUpdater *MSSAU, // FalseWeight is FalseWeight for PBI * FalseWeight for BI. NewWeights.push_back(PredFalseWeight * SuccFalseWeight); } - AddPredecessorToBlock(FalseDest, PredBlock, BB, MSSAU); PBI->setSuccessor(1, FalseDest); } if (NewWeights.size() == 2) { diff --git a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp index 2693f451ebde1..d37fe74a0039d 100644 --- a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp @@ -1542,16 +1542,26 @@ bool WidenIV::widenWithVariantUse(WidenIV::NarrowIVDefUse DU) { auto AnotherOpExtKind = ExtKind; // Check that all uses are either s/zext, or narrow def (in case of we are - // widening the IV increment). + // widening the IV increment), or single-input LCSSA Phis. SmallVector ExtUsers; + SmallVector LCSSAPhiUsers; for (Use &U : NarrowUse->uses()) { - if (U.getUser() == NarrowDef) + Instruction *User = cast(U.getUser()); + if (User == NarrowDef) continue; - Instruction *User = nullptr; + if (!L->contains(User)) { + auto *LCSSAPhi = cast(User); + // Make sure there is only 1 input, so that we don't have to split + // critical edges. + if (LCSSAPhi->getNumOperands() != 1) + return false; + LCSSAPhiUsers.push_back(LCSSAPhi); + continue; + } if (ExtKind == SignExtended) - User = dyn_cast(U.getUser()); + User = dyn_cast(User); else - User = dyn_cast(U.getUser()); + User = dyn_cast(User); if (!User || User->getType() != WideType) return false; ExtUsers.push_back(User); @@ -1561,6 +1571,21 @@ bool WidenIV::widenWithVariantUse(WidenIV::NarrowIVDefUse DU) { return true; } + // We'll prove some facts that should be true in the context of ext users. If + // there is no users, we are done now. If there are some, pick their common + // dominator as context. + Instruction *Context = nullptr; + for (auto *Ext : ExtUsers) { + if (!Context || DT->dominates(Ext, Context)) + Context = Ext; + else if (!DT->dominates(Context, Ext)) + // For users that don't have dominance relation, use common dominator. + Context = + DT->findNearestCommonDominator(Context->getParent(), Ext->getParent()) + ->getTerminator(); + } + assert(Context && "Context not found?"); + if (!CanSignExtend && !CanZeroExtend) { // Because InstCombine turns 'sub nuw' to 'add' losing the no-wrap flag, we // will most likely not see it. Let's try to prove it. @@ -1573,7 +1598,7 @@ bool WidenIV::widenWithVariantUse(WidenIV::NarrowIVDefUse DU) { if (!SE->isKnownNegative(RHS)) return false; bool ProvedSubNUW = SE->isKnownPredicateAt( - ICmpInst::ICMP_UGE, LHS, SE->getNegativeSCEV(RHS), NarrowUse); + ICmpInst::ICMP_UGE, LHS, SE->getNegativeSCEV(RHS), Context); if (!ProvedSubNUW) return false; // In fact, our 'add' is 'sub nuw'. We will need to widen the 2nd operand as @@ -1615,6 +1640,21 @@ bool WidenIV::widenWithVariantUse(WidenIV::NarrowIVDefUse DU) { User->replaceAllUsesWith(WideBO); DeadInsts.emplace_back(User); } + + for (PHINode *User : LCSSAPhiUsers) { + assert(User->getNumOperands() == 1 && "Checked before!"); + Builder.SetInsertPoint(User); + auto *WidePN = + Builder.CreatePHI(WideBO->getType(), 1, User->getName() + ".wide"); + BasicBlock *LoopExitingBlock = User->getParent()->getSinglePredecessor(); + assert(LoopExitingBlock && L->contains(LoopExitingBlock) && + "Not a LCSSA Phi?"); + WidePN->addIncoming(WideBO, LoopExitingBlock); + Builder.SetInsertPoint(User->getParent()->getFirstNonPHI()); + auto *TruncPN = Builder.CreateTrunc(WidePN, User->getType()); + User->replaceAllUsesWith(TruncPN); + DeadInsts.emplace_back(User); + } return true; } diff --git a/llvm/lib/Transforms/Utils/ValueMapper.cpp b/llvm/lib/Transforms/Utils/ValueMapper.cpp index ec5769309f86f..fac7b555e9757 100644 --- a/llvm/lib/Transforms/Utils/ValueMapper.cpp +++ b/llvm/lib/Transforms/Utils/ValueMapper.cpp @@ -172,7 +172,6 @@ class Mapper { bool IsOldCtorDtor, ArrayRef NewMembers); void mapGlobalIndirectSymbol(GlobalIndirectSymbol &GIS, Constant &Target); - void remapFunction(Function &F, ValueToValueMapTy &VM); ValueToValueMapTy &getVM() { return *MCs[CurrentMCID].VM; } ValueMaterializer *getMaterializer() { return MCs[CurrentMCID].Materializer; } diff --git a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp index 770e6e3037cfa..6ec5590d76baa 100644 --- a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp @@ -666,6 +666,10 @@ Vectorizer::getVectorizablePrefix(ArrayRef Chain) { cast(&I)->getIntrinsicID() == Intrinsic::sideeffect) { // Ignore llvm.sideeffect calls. + } else if (isa(&I) && + cast(&I)->getIntrinsicID() == + Intrinsic::pseudoprobe) { + // Ignore llvm.pseudoprobe calls. } else if (IsLoadChain && (I.mayWriteToMemory() || I.mayThrow())) { LLVM_DEBUG(dbgs() << "LSV: Found may-write/throw operation: " << I << '\n'); diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h index b3b744947c1f1..ec88bebe684d7 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h +++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h @@ -292,8 +292,7 @@ class LoopVectorizationPlanner { /// Build a VPlan using VPRecipes according to the information gather by /// Legal. This method is only used for the legacy inner loop vectorizer. VPlanPtr buildVPlanWithVPRecipes( - VFRange &Range, SmallPtrSetImpl &NeedDef, - SmallPtrSetImpl &DeadInstructions, + VFRange &Range, SmallPtrSetImpl &DeadInstructions, const DenseMap &SinkAfter); /// Build VPlans for power-of-2 VF's between \p MinVF and \p MaxVF inclusive, diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 7404c92cdb2f8..0f519d136b31d 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -461,7 +461,7 @@ class InnerLoopVectorizer { BasicBlock *createVectorizedLoopSkeleton(); /// Widen a single instruction within the innermost loop. - void widenInstruction(Instruction &I, VPUser &Operands, + void widenInstruction(Instruction &I, VPValue *Def, VPUser &Operands, VPTransformState &State); /// Widen a single call instruction within the innermost loop. @@ -2661,7 +2661,12 @@ void InnerLoopVectorizer::scalarizeInstruction(Instruction *Instr, VPUser &User, // Replace the operands of the cloned instructions with their scalar // equivalents in the new loop. for (unsigned op = 0, e = User.getNumOperands(); op != e; ++op) { - auto *NewOp = State.get(User.getOperand(op), Instance); + auto *Operand = dyn_cast(Instr->getOperand(op)); + auto InputInstance = Instance; + if (!Operand || !OrigLoop->contains(Operand) || + (Cost->isUniformAfterVectorization(Operand, State.VF))) + InputInstance.Lane = 0; + auto *NewOp = State.get(User.getOperand(op), InputInstance); Cloned->setOperand(op, NewOp); } addNewMetadata(Cloned, Instr); @@ -2669,7 +2674,9 @@ void InnerLoopVectorizer::scalarizeInstruction(Instruction *Instr, VPUser &User, // Place the cloned scalar in the new loop. Builder.Insert(Cloned); - // Add the cloned scalar to the scalar map entry. + // TODO: Set result for VPValue of VPReciplicateRecipe. This requires + // representing scalar values in VPTransformState. Add the cloned scalar to + // the scalar map entry. VectorLoopValueMap.setScalarValue(Instr, Instance, Cloned); // If we just cloned a new assumption, add it the assumption cache. @@ -2723,7 +2730,7 @@ Value *InnerLoopVectorizer::getOrCreateTripCount(Loop *L) { // Find the loop boundaries. ScalarEvolution *SE = PSE.getSE(); const SCEV *BackedgeTakenCount = PSE.getBackedgeTakenCount(); - assert(BackedgeTakenCount != SE->getCouldNotCompute() && + assert(!isa(BackedgeTakenCount) && "Invalid loop count"); Type *IdxTy = Legal->getWidestInductionType(); @@ -4315,7 +4322,7 @@ void InnerLoopVectorizer::widenGEP(GetElementPtrInst *GEP, VPValue *VPDef, auto *Clone = Builder.Insert(GEP->clone()); for (unsigned Part = 0; Part < UF; ++Part) { Value *EntryPart = Builder.CreateVectorSplat(VF, Clone); - VectorLoopValueMap.setVectorValue(GEP, Part, EntryPart); + State.set(VPDef, GEP, EntryPart, Part); addMetadata(EntryPart, GEP); } } else { @@ -4352,7 +4359,7 @@ void InnerLoopVectorizer::widenGEP(GetElementPtrInst *GEP, VPValue *VPDef, : Builder.CreateGEP(GEP->getSourceElementType(), Ptr, Indices); assert((VF.isScalar() || NewGEP->getType()->isVectorTy()) && "NewGEP is not a pointer vector"); - VectorLoopValueMap.setVectorValue(GEP, Part, NewGEP); + State.set(VPDef, GEP, NewGEP, Part); addMetadata(NewGEP, GEP); } } @@ -4507,7 +4514,8 @@ static bool mayDivideByZero(Instruction &I) { return !CInt || CInt->isZero(); } -void InnerLoopVectorizer::widenInstruction(Instruction &I, VPUser &User, +void InnerLoopVectorizer::widenInstruction(Instruction &I, VPValue *Def, + VPUser &User, VPTransformState &State) { assert(!VF.isScalable() && "scalable vectors not yet supported."); switch (I.getOpcode()) { @@ -4550,7 +4558,7 @@ void InnerLoopVectorizer::widenInstruction(Instruction &I, VPUser &User, VecOp->copyIRFlags(&I); // Use this vector value for all users of the original instruction. - VectorLoopValueMap.setVectorValue(&I, Part, V); + State.set(Def, &I, V, Part); addMetadata(V, &I); } @@ -4574,7 +4582,7 @@ void InnerLoopVectorizer::widenInstruction(Instruction &I, VPUser &User, } else { C = Builder.CreateICmp(Cmp->getPredicate(), A, B); } - VectorLoopValueMap.setVectorValue(&I, Part, C); + State.set(Def, &I, C, Part); addMetadata(C, &I); } @@ -4604,7 +4612,7 @@ void InnerLoopVectorizer::widenInstruction(Instruction &I, VPUser &User, for (unsigned Part = 0; Part < UF; ++Part) { Value *A = State.get(User.getOperand(0), Part); Value *Cast = Builder.CreateCast(CI->getOpcode(), A, DestTy); - VectorLoopValueMap.setVectorValue(&I, Part, Cast); + State.set(Def, &I, Cast, Part); addMetadata(Cast, &I); } break; @@ -5031,6 +5039,11 @@ void LoopVectorizationCostModel::collectLoopUniforms(ElementCount VF) { // replicating region where only a single instance out of VF should be formed. // TODO: optimize such seldom cases if found important, see PR40816. auto addToWorklistIfAllowed = [&](Instruction *I) -> void { + if (isOutOfScope(I)) { + LLVM_DEBUG(dbgs() << "LV: Found not uniform due to scope: " + << *I << "\n"); + return; + } if (isScalarWithPredication(I, VF)) { LLVM_DEBUG(dbgs() << "LV: Found not uniform being ScalarWithPredication: " << *I << "\n"); @@ -5051,20 +5064,37 @@ void LoopVectorizationCostModel::collectLoopUniforms(ElementCount VF) { // are pointers that are treated like consecutive pointers during // vectorization. The pointer operands of interleaved accesses are an // example. - SmallSetVector ConsecutiveLikePtrs; + SmallSetVector ConsecutiveLikePtrs; // Holds pointer operands of instructions that are possibly non-uniform. - SmallPtrSet PossibleNonUniformPtrs; + SmallPtrSet PossibleNonUniformPtrs; auto isUniformDecision = [&](Instruction *I, ElementCount VF) { InstWidening WideningDecision = getWideningDecision(I, VF); assert(WideningDecision != CM_Unknown && "Widening decision should be ready at this moment"); + // The address of a uniform mem op is itself uniform. We exclude stores + // here as there's an assumption in the current code that all uses of + // uniform instructions are uniform and, as noted below, uniform stores are + // still handled via replication (i.e. aren't uniform after vectorization). + if (isa(I) && Legal->isUniformMemOp(*I)) { + assert(WideningDecision == CM_Scalarize); + return true; + } + return (WideningDecision == CM_Widen || WideningDecision == CM_Widen_Reverse || WideningDecision == CM_Interleave); }; + + + // Returns true if Ptr is the pointer operand of a memory access instruction + // I, and I is known to not require scalarization. + auto isVectorizedMemAccessUse = [&](Instruction *I, Value *Ptr) -> bool { + return getLoadStorePointerOperand(I) == Ptr && isUniformDecision(I, VF); + }; + // Iterate over the instructions in the loop, and collect all // consecutive-like pointer operands in ConsecutiveLikePtrs. If it's possible // that a consecutive-like pointer operand will be scalarized, we collect it @@ -5076,12 +5106,24 @@ void LoopVectorizationCostModel::collectLoopUniforms(ElementCount VF) { for (auto *BB : TheLoop->blocks()) for (auto &I : *BB) { // If there's no pointer operand, there's nothing to do. - auto *Ptr = dyn_cast_or_null(getLoadStorePointerOperand(&I)); + auto *Ptr = getLoadStorePointerOperand(&I); if (!Ptr) continue; + // For now, avoid walking use lists in other functions. + // TODO: Rewrite this algorithm from uses up. + if (!isa(Ptr) && !isa(Ptr)) + continue; + + // A uniform memory op is itself uniform. We exclude stores here as we + // haven't yet added dedicated logic in the CLONE path and rely on + // REPLICATE + DSE for correctness. + if (isa(I) && Legal->isUniformMemOp(I)) + addToWorklistIfAllowed(&I); + // True if all users of Ptr are memory accesses that have Ptr as their - // pointer operand. + // pointer operand. Since loops are assumed to be in LCSSA form, this + // disallows uses outside the loop as well. auto UsersAreMemAccesses = llvm::all_of(Ptr->users(), [&](User *U) -> bool { return getLoadStorePointerOperand(U) == Ptr; @@ -5105,7 +5147,8 @@ void LoopVectorizationCostModel::collectLoopUniforms(ElementCount VF) { // aren't also identified as possibly non-uniform. for (auto *V : ConsecutiveLikePtrs) if (!PossibleNonUniformPtrs.count(V)) - addToWorklistIfAllowed(V); + if (auto *I = dyn_cast(V)) + addToWorklistIfAllowed(I); // Expand Worklist in topological order: whenever a new instruction // is added , its users should be already inside Worklist. It ensures @@ -5128,20 +5171,12 @@ void LoopVectorizationCostModel::collectLoopUniforms(ElementCount VF) { auto *OI = cast(OV); if (llvm::all_of(OI->users(), [&](User *U) -> bool { auto *J = cast(U); - return Worklist.count(J) || - (OI == getLoadStorePointerOperand(J) && - isUniformDecision(J, VF)); + return Worklist.count(J) || isVectorizedMemAccessUse(J, OI); })) addToWorklistIfAllowed(OI); } } - // Returns true if Ptr is the pointer operand of a memory access instruction - // I, and I is known to not require scalarization. - auto isVectorizedMemAccessUse = [&](Instruction *I, Value *Ptr) -> bool { - return getLoadStorePointerOperand(I) == Ptr && isUniformDecision(I, VF); - }; - // For an instruction to be added into Worklist above, all its users inside // the loop should also be in Worklist. However, this condition cannot be // true for phi nodes that form a cyclic dependence. We must process phi @@ -5336,9 +5371,9 @@ LoopVectorizationCostModel::computeFeasibleMaxVF(unsigned ConstTripCount) { // It is computed by MaxVF * sizeOf(type) * 8, where type is taken from // the memory accesses that is most restrictive (involved in the smallest // dependence distance). - unsigned MaxSafeRegisterWidth = Legal->getMaxSafeRegisterWidth(); + unsigned MaxSafeVectorWidthInBits = Legal->getMaxSafeVectorWidthInBits(); - WidestRegister = std::min(WidestRegister, MaxSafeRegisterWidth); + WidestRegister = std::min(WidestRegister, MaxSafeVectorWidthInBits); // Ensure MaxVF is a power of 2; the dependence distance bound may not be. // Note that both WidestRegister and WidestType may not be a powers of 2. @@ -6228,6 +6263,8 @@ unsigned LoopVectorizationCostModel::getConsecutiveMemOpCost(Instruction *I, unsigned LoopVectorizationCostModel::getUniformMemOpCost(Instruction *I, ElementCount VF) { + assert(Legal->isUniformMemOp(*I)); + Type *ValTy = getMemInstValueType(I); auto *VectorTy = cast(ToVectorTy(ValTy, VF)); const Align Alignment = getLoadStoreAlignment(I); @@ -7099,6 +7136,12 @@ void LoopVectorizationPlanner::collectTriviallyDeadInstructions( for (auto &Induction : Legal->getInductionVars()) { PHINode *Ind = Induction.first; auto *IndUpdate = cast(Ind->getIncomingValueForBlock(Latch)); + + // If the tail is to be folded by masking, the primary induction variable, + // if exists, isn't dead: it will be used for masking. Don't kill it. + if (CM.foldTailByMasking() && IndUpdate == Legal->getPrimaryInduction()) + continue; + if (llvm::all_of(IndUpdate->users(), [&](User *U) -> bool { return U == Ind || DeadInstructions.count(cast(U)); })) @@ -7222,7 +7265,7 @@ VPValue *VPRecipeBuilder::createEdgeMask(BasicBlock *Src, BasicBlock *Dst, if (!BI->isConditional() || BI->getSuccessor(0) == BI->getSuccessor(1)) return EdgeMaskCache[Edge] = SrcMask; - VPValue *EdgeMask = Plan->getVPValue(BI->getCondition()); + VPValue *EdgeMask = Plan->getOrAddVPValue(BI->getCondition()); assert(EdgeMask && "No Edge Mask found for condition"); if (BI->getSuccessor(0) != Dst) @@ -7260,7 +7303,7 @@ VPValue *VPRecipeBuilder::createBlockInMask(BasicBlock *BB, VPlanPtr &Plan) { // Start by constructing the desired canonical IV. VPValue *IV = nullptr; if (Legal->getPrimaryInduction()) - IV = Plan->getVPValue(Legal->getPrimaryInduction()); + IV = Plan->getOrAddVPValue(Legal->getPrimaryInduction()); else { auto IVRecipe = new VPWidenCanonicalIVRecipe(); Builder.getInsertBlock()->insert(IVRecipe, NewInsertionPoint); @@ -7407,7 +7450,8 @@ VPWidenCallRecipe *VPRecipeBuilder::tryToWidenCall(CallInst *CI, VFRange &Range, Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI); if (ID && (ID == Intrinsic::assume || ID == Intrinsic::lifetime_end || - ID == Intrinsic::lifetime_start || ID == Intrinsic::sideeffect)) + ID == Intrinsic::lifetime_start || ID == Intrinsic::sideeffect || + ID == Intrinsic::pseudoprobe)) return nullptr; auto willWiden = [&](ElementCount VF) -> bool { @@ -7507,6 +7551,7 @@ VPBasicBlock *VPRecipeBuilder::handleReplication( auto *Recipe = new VPReplicateRecipe(I, Plan->mapToVPValues(I->operands()), IsUniform, IsPredicated); setRecipe(I, Recipe); + Plan->addVPValue(I, Recipe); // Find if I uses a predicated instruction. If so, it will use its scalar // value. Avoid hoisting the insert-element which packs the scalar value into @@ -7607,24 +7652,6 @@ void LoopVectorizationPlanner::buildVPlansWithVPRecipes(ElementCount MinVF, ElementCount MaxVF) { assert(OrigLoop->isInnermost() && "Inner loop expected."); - // Collect conditions feeding internal conditional branches; they need to be - // represented in VPlan for it to model masking. - SmallPtrSet NeedDef; - - auto *Latch = OrigLoop->getLoopLatch(); - for (BasicBlock *BB : OrigLoop->blocks()) { - if (BB == Latch) - continue; - BranchInst *Branch = dyn_cast(BB->getTerminator()); - if (Branch && Branch->isConditional()) - NeedDef.insert(Branch->getCondition()); - } - - // If the tail is to be folded by masking, the primary induction variable, if - // exists needs to be represented in VPlan for it to model early-exit masking. - if (CM.foldTailByMasking() && Legal->getPrimaryInduction()) - NeedDef.insert(Legal->getPrimaryInduction()); - // Collect instructions from the original loop that will become trivially dead // in the vectorized loop. We don't need to vectorize these instructions. For // example, original induction update instructions can become dead because we @@ -7649,15 +7676,14 @@ void LoopVectorizationPlanner::buildVPlansWithVPRecipes(ElementCount MinVF, auto MaxVFPlusOne = MaxVF.getWithIncrement(1); for (ElementCount VF = MinVF; ElementCount::isKnownLT(VF, MaxVFPlusOne);) { VFRange SubRange = {VF, MaxVFPlusOne}; - VPlans.push_back(buildVPlanWithVPRecipes(SubRange, NeedDef, - DeadInstructions, SinkAfter)); + VPlans.push_back( + buildVPlanWithVPRecipes(SubRange, DeadInstructions, SinkAfter)); VF = SubRange.End; } } VPlanPtr LoopVectorizationPlanner::buildVPlanWithVPRecipes( - VFRange &Range, SmallPtrSetImpl &NeedDef, - SmallPtrSetImpl &DeadInstructions, + VFRange &Range, SmallPtrSetImpl &DeadInstructions, const DenseMap &SinkAfter) { // Hold a mapping from predicated instructions to their recipes, in order to @@ -7726,10 +7752,6 @@ VPlanPtr LoopVectorizationPlanner::buildVPlanWithVPRecipes( VPBasicBlock *VPBB = new VPBasicBlock("Pre-Entry"); Plan->setEntry(VPBB); - // Represent values that will have defs inside VPlan. - for (Value *V : NeedDef) - Plan->addVPValue(V); - // Scan the body of the loop in a topological order to visit each basic block // after having visited its predecessor basic blocks. LoopBlocksDFS DFS(OrigLoop); @@ -7759,12 +7781,8 @@ VPlanPtr LoopVectorizationPlanner::buildVPlanWithVPRecipes( // Check if the recipe can be converted to a VPValue. We need the extra // down-casting step until VPRecipeBase inherits from VPValue. VPValue *MaybeVPValue = Recipe->toVPValue(); - if (!Instr->getType()->isVoidTy() && MaybeVPValue) { - if (NeedDef.contains(Instr)) - Plan->addOrReplaceVPValue(Instr, MaybeVPValue); - else - Plan->addVPValue(Instr, MaybeVPValue); - } + if (!Instr->getType()->isVoidTy() && MaybeVPValue) + Plan->addVPValue(Instr, MaybeVPValue); RecipeBuilder.setRecipe(Instr, Recipe); VPBB->appendRecipe(Recipe); @@ -7933,6 +7951,9 @@ void LoopVectorizationPlanner::adjustRecipesForInLoopReductions( : nullptr; VPReductionRecipe *RedRecipe = new VPReductionRecipe( &RdxDesc, R, ChainOp, VecOp, CondOp, Legal->hasFunNoNaNAttr(), TTI); + WidenRecipe->toVPValue()->replaceAllUsesWith(RedRecipe); + Plan->removeVPValueFor(R); + Plan->addVPValue(R, RedRecipe); WidenRecipe->getParent()->insert(RedRecipe, WidenRecipe->getIterator()); WidenRecipe->eraseFromParent(); @@ -7942,6 +7963,8 @@ void LoopVectorizationPlanner::adjustRecipesForInLoopReductions( RecipeBuilder.getRecipe(cast(R->getOperand(0))); assert(isa(CompareRecipe) && "Expected to replace a VPWidenSC"); + assert(CompareRecipe->toVPValue()->getNumUsers() == 0 && + "Expected no remaining users"); CompareRecipe->eraseFromParent(); } Chain = R; @@ -7986,7 +8009,7 @@ void VPWidenSelectRecipe::execute(VPTransformState &State) { } void VPWidenRecipe::execute(VPTransformState &State) { - State.ILV->widenInstruction(Ingredient, *this, State); + State.ILV->widenInstruction(*getUnderlyingInstr(), this, *this, State); } void VPWidenGEPRecipe::execute(VPTransformState &State) { @@ -8052,9 +8075,9 @@ void VPReductionRecipe::execute(VPTransformState &State) { assert(!State.Instance && "Reduction being replicated."); for (unsigned Part = 0; Part < State.UF; ++Part) { RecurrenceDescriptor::RecurrenceKind Kind = RdxDesc->getRecurrenceKind(); - Value *NewVecOp = State.get(VecOp, Part); - if (CondOp) { - Value *NewCond = State.get(CondOp, Part); + Value *NewVecOp = State.get(getVecOp(), Part); + if (VPValue *Cond = getCondOp()) { + Value *NewCond = State.get(Cond, Part); VectorType *VecTy = cast(NewVecOp->getType()); Constant *Iden = RecurrenceDescriptor::getRecurrenceIdentity( Kind, RdxDesc->getMinMaxRecurrenceKind(), VecTy->getElementType()); @@ -8065,7 +8088,7 @@ void VPReductionRecipe::execute(VPTransformState &State) { } Value *NewRed = createTargetReduction(State.Builder, TTI, *RdxDesc, NewVecOp, NoNaN); - Value *PrevInChain = State.get(ChainOp, Part); + Value *PrevInChain = State.get(getChainOp(), Part); Value *NextInChain; if (Kind == RecurrenceDescriptor::RK_IntegerMinMax || Kind == RecurrenceDescriptor::RK_FloatMinMax) { @@ -8074,26 +8097,29 @@ void VPReductionRecipe::execute(VPTransformState &State) { NewRed, PrevInChain); } else { NextInChain = State.Builder.CreateBinOp( - (Instruction::BinaryOps)I->getOpcode(), NewRed, PrevInChain); + (Instruction::BinaryOps)getUnderlyingInstr()->getOpcode(), NewRed, + PrevInChain); } - State.ValueMap.setVectorValue(I, Part, NextInChain); + State.set(this, getUnderlyingInstr(), NextInChain, Part); } } void VPReplicateRecipe::execute(VPTransformState &State) { if (State.Instance) { // Generate a single instance. - State.ILV->scalarizeInstruction(Ingredient, *this, *State.Instance, - IsPredicated, State); + State.ILV->scalarizeInstruction(getUnderlyingInstr(), *this, + *State.Instance, IsPredicated, State); // Insert scalar instance packing it into a vector. if (AlsoPack && State.VF.isVector()) { // If we're constructing lane 0, initialize to start from undef. if (State.Instance->Lane == 0) { assert(!State.VF.isScalable() && "VF is assumed to be non scalable."); - Value *Undef = - UndefValue::get(VectorType::get(Ingredient->getType(), State.VF)); - State.ValueMap.setVectorValue(Ingredient, State.Instance->Part, Undef); + Value *Undef = UndefValue::get( + VectorType::get(getUnderlyingValue()->getType(), State.VF)); + State.ValueMap.setVectorValue(getUnderlyingInstr(), + State.Instance->Part, Undef); } - State.ILV->packScalarIntoVectorValue(Ingredient, *State.Instance); + State.ILV->packScalarIntoVectorValue(getUnderlyingInstr(), + *State.Instance); } return; } @@ -8104,7 +8130,7 @@ void VPReplicateRecipe::execute(VPTransformState &State) { unsigned EndLane = IsUniform ? 1 : State.VF.getKnownMinValue(); for (unsigned Part = 0; Part < State.UF; ++Part) for (unsigned Lane = 0; Lane < EndLane; ++Lane) - State.ILV->scalarizeInstruction(Ingredient, *this, {Part, Lane}, + State.ILV->scalarizeInstruction(getUnderlyingInstr(), *this, {Part, Lane}, IsPredicated, State); } @@ -8233,7 +8259,7 @@ static bool processLoopInVPlanNativePath( OptimizationRemarkEmitter *ORE, BlockFrequencyInfo *BFI, ProfileSummaryInfo *PSI, LoopVectorizeHints &Hints) { - if (PSE.getBackedgeTakenCount() == PSE.getSE()->getCouldNotCompute()) { + if (isa(PSE.getBackedgeTakenCount())) { LLVM_DEBUG(dbgs() << "LV: cannot compute the outer-loop trip count\n"); return false; } diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 2da3de2eb00a9..a68c8c10e8f34 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -1744,6 +1744,19 @@ class BoUpSLP { #endif }; +#ifndef NDEBUG + void dumpTreeCosts(TreeEntry *E, int ReuseShuffleCost, int VecCost, + int ScalarCost) const { + dbgs() << "SLP: Calculated costs for Tree:\n"; E->dump(); + dbgs() << "SLP: Costs:\n"; + dbgs() << "SLP: ReuseShuffleCost = " << ReuseShuffleCost << "\n"; + dbgs() << "SLP: VectorCost = " << VecCost << "\n"; + dbgs() << "SLP: ScalarCost = " << ScalarCost << "\n"; + dbgs() << "SLP: ReuseShuffleCost + VecCost - ScalarCost = " << + ReuseShuffleCost + VecCost - ScalarCost << "\n"; + } +#endif + /// Create a new VectorizableTree entry. TreeEntry *newTreeEntry(ArrayRef VL, Optional Bundle, const InstructionsState &S, @@ -1763,9 +1776,8 @@ class BoUpSLP { const EdgeInfo &UserTreeIdx, ArrayRef ReuseShuffleIndices = None, ArrayRef ReorderIndices = None) { - assert(!(Bundle && EntryState == TreeEntry::NeedToGather) && - "Need to gather vectorized entry?"); - assert((Bundle || EntryState == TreeEntry::NeedToGather) && + assert(((!Bundle && EntryState == TreeEntry::NeedToGather) || + (Bundle && EntryState != TreeEntry::NeedToGather)) && "Need to vectorize gather entry?"); VectorizableTree.push_back(std::make_unique(VectorizableTree)); TreeEntry *Last = VectorizableTree.back().get(); @@ -3563,6 +3575,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) { TTI->getCastInstrCost(E->getOpcode(), VecTy, SrcVecTy, TTI::getCastContextHint(VL0), CostKind, VL0); } + LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecCost, ScalarCost)); return VecCost - ScalarCost; } case Instruction::FCmp: @@ -3613,6 +3626,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) { CmpInst::BAD_ICMP_PREDICATE, CostKind); VecCost = std::min(VecCost, IntrinsicCost); } + LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecCost, ScalarCost)); return ReuseShuffleCost + VecCost - ScalarCost; } case Instruction::FNeg: @@ -3682,6 +3696,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) { int VecCost = TTI->getArithmeticInstrCost( E->getOpcode(), VecTy, CostKind, Op1VK, Op2VK, Op1VP, Op2VP, Operands, VL0); + LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecCost, ScalarCost)); return ReuseShuffleCost + VecCost - ScalarCost; } case Instruction::GetElementPtr: { @@ -3700,6 +3715,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) { int VecCost = TTI->getArithmeticInstrCost(Instruction::Add, VecTy, CostKind, Op1VK, Op2VK); + LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecCost, ScalarCost)); return ReuseShuffleCost + VecCost - ScalarCost; } case Instruction::Load: { @@ -3727,6 +3743,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) { VecLdCost += TTI->getShuffleCost( TargetTransformInfo::SK_PermuteSingleSrc, VecTy); } + LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecLdCost, ScalarLdCost)); return ReuseShuffleCost + VecLdCost - ScalarLdCost; } case Instruction::Store: { @@ -3748,6 +3765,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) { VecStCost += TTI->getShuffleCost( TargetTransformInfo::SK_PermuteSingleSrc, VecTy); } + LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecStCost, ScalarStCost)); return ReuseShuffleCost + VecStCost - ScalarStCost; } case Instruction::Call: { @@ -3812,6 +3830,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) { TTI::CastContextHint::None, CostKind); } VecCost += TTI->getShuffleCost(TargetTransformInfo::SK_Select, VecTy, 0); + LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecCost, ScalarCost)); return ReuseShuffleCost + VecCost - ScalarCost; } default: @@ -4035,10 +4054,11 @@ int BoUpSLP::getTreeCost() { continue; int C = getEntryCost(&TE); + Cost += C; LLVM_DEBUG(dbgs() << "SLP: Adding cost " << C << " for bundle that starts with " << *TE.Scalars[0] - << ".\n"); - Cost += C; + << ".\n" + << "SLP: Current total cost = " << Cost << "\n"); } SmallPtrSet ExtractCostCalculated; @@ -5261,7 +5281,9 @@ void BoUpSLP::BlockScheduling::initScheduleData(Instruction *FromI, if (I->mayReadOrWriteMemory() && (!isa(I) || - cast(I)->getIntrinsicID() != Intrinsic::sideeffect)) { + (cast(I)->getIntrinsicID() != Intrinsic::sideeffect && + cast(I)->getIntrinsicID() != + Intrinsic::pseudoprobe))) { // Update the linked list of memory accessing instructions. if (CurrentLoadStore) { CurrentLoadStore->NextLoadStore = SD; @@ -5940,9 +5962,9 @@ bool SLPVectorizerPass::vectorizeStoreChain(ArrayRef Chain, BoUpSLP &R, int Cost = R.getTreeCost(); - LLVM_DEBUG(dbgs() << "SLP: Found cost=" << Cost << " for VF=" << VF << "\n"); + LLVM_DEBUG(dbgs() << "SLP: Found cost = " << Cost << " for VF =" << VF << "\n"); if (Cost < -SLPCostThreshold) { - LLVM_DEBUG(dbgs() << "SLP: Decided to vectorize cost=" << Cost << "\n"); + LLVM_DEBUG(dbgs() << "SLP: Decided to vectorize cost = " << Cost << "\n"); using namespace ore; diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp index f7df8a4fb0e61..3b26d6b52efd3 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp @@ -22,6 +22,7 @@ #include "llvm/ADT/PostOrderIterator.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Twine.h" +#include "llvm/Analysis/IVDescriptors.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/IR/BasicBlock.h" #include "llvm/IR/CFG.h" @@ -110,12 +111,16 @@ VPUser *VPRecipeBase::toVPUser() { return U; if (auto *U = dyn_cast(this)) return U; + if (auto *U = dyn_cast(this)) + return U; return nullptr; } VPValue *VPRecipeBase::toVPValue() { if (auto *V = dyn_cast(this)) return V; + if (auto *V = dyn_cast(this)) + return V; if (auto *V = dyn_cast(this)) return V; if (auto *V = dyn_cast(this)) @@ -124,12 +129,18 @@ VPValue *VPRecipeBase::toVPValue() { return V; if (auto *V = dyn_cast(this)) return V; + if (auto *V = dyn_cast(this)) + return V; + if (auto *V = dyn_cast(this)) + return V; return nullptr; } const VPValue *VPRecipeBase::toVPValue() const { if (auto *V = dyn_cast(this)) return V; + if (auto *V = dyn_cast(this)) + return V; if (auto *V = dyn_cast(this)) return V; if (auto *V = dyn_cast(this)) @@ -138,6 +149,10 @@ const VPValue *VPRecipeBase::toVPValue() const { return V; if (auto *V = dyn_cast(this)) return V; + if (auto *V = dyn_cast(this)) + return V; + if (auto *V = dyn_cast(this)) + return V; return nullptr; } @@ -222,14 +237,8 @@ VPBlockBase *VPBlockBase::getEnclosingBlockWithPredecessors() { void VPBlockBase::deleteCFG(VPBlockBase *Entry) { SmallVector Blocks; - VPValue DummyValue; - for (VPBlockBase *Block : depth_first(Entry)) { - // Drop all references in VPBasicBlocks and replace all uses with - // DummyValue. - if (auto *VPBB = dyn_cast(Block)) - VPBB->dropAllReferences(&DummyValue); + for (VPBlockBase *Block : depth_first(Entry)) Blocks.push_back(Block); - } for (VPBlockBase *Block : Blocks) delete Block; @@ -373,6 +382,13 @@ void VPBasicBlock::dropAllReferences(VPValue *NewValue) { } } +void VPRegionBlock::dropAllReferences(VPValue *NewValue) { + for (VPBlockBase *Block : depth_first(Entry)) + // Drop all references in VPBasicBlocks and replace all uses with + // DummyValue. + Block->dropAllReferences(NewValue); +} + void VPRegionBlock::execute(VPTransformState *State) { ReversePostOrderTraversal RPOT(Entry); @@ -876,8 +892,10 @@ void VPWidenSelectRecipe::print(raw_ostream &O, const Twine &Indent, void VPWidenRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "\"WIDEN\\l\""; - O << "\" " << VPlanIngredient(&Ingredient); + O << "\"WIDEN "; + printAsOperand(O, SlotTracker); + O << " = " << getUnderlyingInstr()->getOpcodeName() << " "; + printOperands(O, SlotTracker); } void VPWidenIntOrFpInductionRecipe::print(raw_ostream &O, const Twine &Indent, @@ -932,13 +950,16 @@ void VPBlendRecipe::print(raw_ostream &O, const Twine &Indent, void VPReductionRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { - O << "\"REDUCE of" << *I << " as "; - ChainOp->printAsOperand(O, SlotTracker); - O << " + reduce("; - VecOp->printAsOperand(O, SlotTracker); - if (CondOp) { + O << "\"REDUCE "; + printAsOperand(O, SlotTracker); + O << " = "; + getChainOp()->printAsOperand(O, SlotTracker); + O << " + reduce." << Instruction::getOpcodeName(RdxDesc->getRecurrenceBinOp()) + << " ("; + getVecOp()->printAsOperand(O, SlotTracker); + if (getCondOp()) { O << ", "; - CondOp->printAsOperand(O, SlotTracker); + getCondOp()->printAsOperand(O, SlotTracker); } O << ")"; } @@ -946,7 +967,7 @@ void VPReductionRecipe::print(raw_ostream &O, const Twine &Indent, void VPReplicateRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { O << "\"" << (IsUniform ? "CLONE " : "REPLICATE ") - << VPlanIngredient(Ingredient); + << VPlanIngredient(getUnderlyingInstr()); if (AlsoPack) O << " (S->V)"; } diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index fe18004b2458a..b4d84ed57773d 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -614,6 +614,10 @@ class VPBlockBase { // hoisted into a VPBlockBase. return true; } + + /// Replace all operands of VPUsers in the block with \p NewValue and also + /// replaces all uses of VPValues defined in the block with NewValue. + virtual void dropAllReferences(VPValue *NewValue) = 0; }; /// VPRecipeBase is a base class modeling a sequence of one or more output IR @@ -726,6 +730,7 @@ inline bool VPUser::classof(const VPRecipeBase *Recipe) { Recipe->getVPRecipeID() == VPRecipeBase::VPBlendSC || Recipe->getVPRecipeID() == VPRecipeBase::VPInterleaveSC || Recipe->getVPRecipeID() == VPRecipeBase::VPReplicateSC || + Recipe->getVPRecipeID() == VPRecipeBase::VPReductionSC || Recipe->getVPRecipeID() == VPRecipeBase::VPBranchOnMaskSC || Recipe->getVPRecipeID() == VPRecipeBase::VPWidenMemoryInstructionSC; } @@ -760,7 +765,7 @@ class VPInstruction : public VPUser, public VPValue, public VPRecipeBase { public: VPInstruction(unsigned Opcode, ArrayRef Operands) - : VPUser(Operands), VPValue(VPValue::VPInstructionSC), + : VPUser(Operands), VPValue(VPValue::VPVInstructionSC), VPRecipeBase(VPRecipeBase::VPInstructionSC), Opcode(Opcode) {} VPInstruction(unsigned Opcode, std::initializer_list Operands) @@ -768,7 +773,7 @@ class VPInstruction : public VPUser, public VPValue, public VPRecipeBase { /// Method to support type inquiry through isa, cast, and dyn_cast. static inline bool classof(const VPValue *V) { - return V->getVPValueID() == VPValue::VPInstructionSC; + return V->getVPValueID() == VPValue::VPVInstructionSC; } VPInstruction *clone() const { @@ -828,14 +833,12 @@ class VPInstruction : public VPUser, public VPValue, public VPRecipeBase { /// VPWidenRecipe is a recipe for producing a copy of vector type its /// ingredient. This recipe covers most of the traditional vectorization cases /// where each ingredient transforms into a vectorized version of itself. -class VPWidenRecipe : public VPRecipeBase, public VPUser { - /// Hold the instruction to be widened. - Instruction &Ingredient; - +class VPWidenRecipe : public VPRecipeBase, public VPValue, public VPUser { public: template VPWidenRecipe(Instruction &I, iterator_range Operands) - : VPRecipeBase(VPWidenSC), VPUser(Operands), Ingredient(I) {} + : VPRecipeBase(VPRecipeBase::VPWidenSC), VPValue(VPValue::VPVWidenSC, &I), + VPUser(Operands) {} ~VPWidenRecipe() override = default; @@ -843,6 +846,9 @@ class VPWidenRecipe : public VPRecipeBase, public VPUser { static inline bool classof(const VPRecipeBase *V) { return V->getVPRecipeID() == VPRecipeBase::VPWidenSC; } + static inline bool classof(const VPValue *V) { + return V->getVPValueID() == VPValue::VPVWidenSC; + } /// Produce widened copies of all Ingredients. void execute(VPTransformState &State) override; @@ -1071,17 +1077,10 @@ class VPInterleaveRecipe : public VPRecipeBase, public VPUser { /// A recipe to represent inloop reduction operations, performing a reduction on /// a vector operand into a scalar value, and adding the result to a chain. -class VPReductionRecipe : public VPRecipeBase { +/// The Operands are {ChainOp, VecOp, [Condition]}. +class VPReductionRecipe : public VPRecipeBase, public VPValue, public VPUser { /// The recurrence decriptor for the reduction in question. RecurrenceDescriptor *RdxDesc; - /// The original instruction being converted to a reduction. - Instruction *I; - /// The VPValue of the vector value to be reduced. - VPValue *VecOp; - /// The VPValue of the scalar Chain being accumulated. - VPValue *ChainOp; - /// The VPValue of the condition for the block. - VPValue *CondOp; /// Fast math flags to use for the resulting reduction operation. bool NoNaN; /// Pointer to the TTI, needed to create the target reduction @@ -1091,12 +1090,19 @@ class VPReductionRecipe : public VPRecipeBase { VPReductionRecipe(RecurrenceDescriptor *R, Instruction *I, VPValue *ChainOp, VPValue *VecOp, VPValue *CondOp, bool NoNaN, const TargetTransformInfo *TTI) - : VPRecipeBase(VPReductionSC), RdxDesc(R), I(I), VecOp(VecOp), - ChainOp(ChainOp), CondOp(CondOp), NoNaN(NoNaN), TTI(TTI) {} + : VPRecipeBase(VPRecipeBase::VPReductionSC), + VPValue(VPValue::VPVReductionSC, I), VPUser({ChainOp, VecOp}), + RdxDesc(R), NoNaN(NoNaN), TTI(TTI) { + if (CondOp) + addOperand(CondOp); + } ~VPReductionRecipe() override = default; /// Method to support type inquiry through isa, cast, and dyn_cast. + static inline bool classof(const VPValue *V) { + return V->getVPValueID() == VPValue::VPVReductionSC; + } static inline bool classof(const VPRecipeBase *V) { return V->getVPRecipeID() == VPRecipeBase::VPReductionSC; } @@ -1107,16 +1113,22 @@ class VPReductionRecipe : public VPRecipeBase { /// Print the recipe. void print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const override; + + /// The VPValue of the scalar Chain being accumulated. + VPValue *getChainOp() const { return getOperand(0); } + /// The VPValue of the vector value to be reduced. + VPValue *getVecOp() const { return getOperand(1); } + /// The VPValue of the condition for the block. + VPValue *getCondOp() const { + return getNumOperands() > 2 ? getOperand(2) : nullptr; + } }; /// VPReplicateRecipe replicates a given instruction producing multiple scalar /// copies of the original scalar type, one per lane, instead of producing a /// single copy of widened type for all lanes. If the instruction is known to be /// uniform only one copy, per lane zero, will be generated. -class VPReplicateRecipe : public VPRecipeBase, public VPUser { - /// The instruction being replicated. - Instruction *Ingredient; - +class VPReplicateRecipe : public VPRecipeBase, public VPUser, public VPValue { /// Indicator if only a single replica per lane is needed. bool IsUniform; @@ -1130,8 +1142,9 @@ class VPReplicateRecipe : public VPRecipeBase, public VPUser { template VPReplicateRecipe(Instruction *I, iterator_range Operands, bool IsUniform, bool IsPredicated = false) - : VPRecipeBase(VPReplicateSC), VPUser(Operands), Ingredient(I), - IsUniform(IsUniform), IsPredicated(IsPredicated) { + : VPRecipeBase(VPReplicateSC), VPUser(Operands), + VPValue(VPVReplicateSC, I), IsUniform(IsUniform), + IsPredicated(IsPredicated) { // Retain the previous behavior of predicateInstructions(), where an // insert-element of a predicated instruction got hoisted into the // predicated basic block iff it was its only user. This is achieved by @@ -1147,6 +1160,10 @@ class VPReplicateRecipe : public VPRecipeBase, public VPUser { return V->getVPRecipeID() == VPRecipeBase::VPReplicateSC; } + static inline bool classof(const VPValue *V) { + return V->getVPValueID() == VPValue::VPVReplicateSC; + } + /// Generate replicas of the desired Ingredient. Replicas will be generated /// for all parts and lanes unless a specific part and lane are specified in /// the \p State. @@ -1157,6 +1174,8 @@ class VPReplicateRecipe : public VPRecipeBase, public VPUser { /// Print the recipe. void print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const override; + + bool isUniform() const { return IsUniform; } }; /// A recipe for generating conditional branches on the bits of a mask. @@ -1247,14 +1266,14 @@ class VPWidenMemoryInstructionRecipe : public VPRecipeBase, public: VPWidenMemoryInstructionRecipe(LoadInst &Load, VPValue *Addr, VPValue *Mask) : VPRecipeBase(VPWidenMemoryInstructionSC), - VPValue(VPValue::VPMemoryInstructionSC, &Load), VPUser({Addr}) { + VPValue(VPValue::VPVMemoryInstructionSC, &Load), VPUser({Addr}) { setMask(Mask); } VPWidenMemoryInstructionRecipe(StoreInst &Store, VPValue *Addr, VPValue *StoredValue, VPValue *Mask) : VPRecipeBase(VPWidenMemoryInstructionSC), - VPValue(VPValue::VPMemoryInstructionSC, &Store), + VPValue(VPValue::VPVMemoryInstructionSC, &Store), VPUser({Addr, StoredValue}) { setMask(Mask); } @@ -1396,13 +1415,11 @@ class VPBasicBlock : public VPBlockBase { /// this VPBasicBlock, thereby "executing" the VPlan. void execute(struct VPTransformState *State) override; - /// Replace all operands of VPUsers in the block with \p NewValue and also - /// replaces all uses of VPValues defined in the block with NewValue. - void dropAllReferences(VPValue *NewValue); - /// Return the position of the first non-phi node recipe in the block. iterator getFirstNonPhi(); + void dropAllReferences(VPValue *NewValue) override; + private: /// Create an IR BasicBlock to hold the output instructions generated by this /// VPBasicBlock, and return it. Update the CFGState accordingly. @@ -1443,8 +1460,11 @@ class VPRegionBlock : public VPBlockBase { IsReplicator(IsReplicator) {} ~VPRegionBlock() override { - if (Entry) + if (Entry) { + VPValue DummyValue; + Entry->dropAllReferences(&DummyValue); deleteCFG(Entry); + } } /// Method to support type inquiry through isa, cast, and dyn_cast. @@ -1489,6 +1509,8 @@ class VPRegionBlock : public VPBlockBase { /// The method which generates the output IR instructions that correspond to /// this VPRegionBlock, thereby "executing" the VPlan. void execute(struct VPTransformState *State) override; + + void dropAllReferences(VPValue *NewValue) override; }; //===----------------------------------------------------------------------===// @@ -1663,8 +1685,13 @@ class VPlan { } ~VPlan() { - if (Entry) + if (Entry) { + VPValue DummyValue; + for (VPBlockBase *Block : depth_first(Entry)) + Block->dropAllReferences(&DummyValue); + VPBlockBase::deleteCFG(Entry); + } for (VPValue *VPV : VPValuesToFree) delete VPV; if (BackedgeTakenCount) @@ -1727,15 +1754,6 @@ class VPlan { Value2VPValue[V] = VPV; } - void addOrReplaceVPValue(Value *V, VPValue *VPV) { - assert(V && "Trying to add a null Value to VPlan"); - auto I = Value2VPValue.find(V); - if (I == Value2VPValue.end()) - Value2VPValue[V] = VPV; - else - I->second = VPV; - } - VPValue *getVPValue(Value *V) { assert(V && "Trying to get the VPValue of a null Value"); assert(Value2VPValue.count(V) && "Value does not exist in VPlan"); diff --git a/llvm/lib/Transforms/Vectorize/VPlanValue.h b/llvm/lib/Transforms/Vectorize/VPlanValue.h index 29c455e6924fd..5cb818e13d072 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanValue.h +++ b/llvm/lib/Transforms/Vectorize/VPlanValue.h @@ -87,11 +87,14 @@ class VPValue { /// type identification. enum { VPValueSC, - VPInstructionSC, - VPMemoryInstructionSC, + VPVInstructionSC, + VPVMemoryInstructionSC, + VPVReductionSC, + VPVReplicateSC, + VPVWidenSC, VPVWidenCallSC, + VPVWidenGEPSC, VPVWidenSelectSC, - VPVWidenGEPSC }; VPValue(Value *UV = nullptr, VPDef *Def = nullptr) diff --git a/llvm/test/Analysis/AliasSet/argmemonly.ll b/llvm/test/Analysis/AliasSet/argmemonly.ll index 0149a6651e20e..b29937453f8db 100644 --- a/llvm/test/Analysis/AliasSet/argmemonly.ll +++ b/llvm/test/Analysis/AliasSet/argmemonly.ll @@ -6,7 +6,7 @@ ; CHECK: Alias sets for function 'test_alloca_argmemonly': ; CHECK-NEXT: Alias Set Tracker: 2 alias sets for 3 pointer values. ; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %a, LocationSize::precise(1)) -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 2] may alias, Mod/Ref Pointers: (i8* %d, unknown), (i8* %s, unknown) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 2] may alias, Mod/Ref Pointers: (i8* %d, unknown before-or-after), (i8* %s, unknown before-or-after) define void @test_alloca_argmemonly(i8* %s, i8* %d) { entry: %a = alloca i8, align 1 @@ -17,8 +17,8 @@ entry: ; CHECK: Alias sets for function 'test_readonly_arg' ; CHECK-NEXT: Alias Set Tracker: 2 alias sets for 2 pointer values. -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %d, unknown) -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Ref Pointers: (i8* %s, unknown) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %d, unknown before-or-after) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Ref Pointers: (i8* %s, unknown before-or-after) define i8 @test_readonly_arg(i8* noalias %s, i8* noalias %d) { entry: call void @my_memcpy(i8* %d, i8* %s, i64 1) @@ -29,7 +29,7 @@ entry: ; CHECK: Alias sets for function 'test_noalias_argmemonly': ; CHECK-NEXT: Alias Set Tracker: 2 alias sets for 3 pointer values. ; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %a, LocationSize::precise(1)) -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 2] may alias, Mod/Ref Pointers: (i8* %d, unknown), (i8* %s, unknown) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 2] may alias, Mod/Ref Pointers: (i8* %d, unknown before-or-after), (i8* %s, unknown before-or-after) define void @test_noalias_argmemonly(i8* noalias %a, i8* %s, i8* %d) { entry: store i8 1, i8* %a, align 1 @@ -39,8 +39,8 @@ entry: ; CHECK: Alias sets for function 'test5': ; CHECK-NEXT: Alias Set Tracker: 2 alias sets for 2 pointer values. -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod/Ref Pointers: (i8* %a, unknown) -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %b, unknown) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod/Ref Pointers: (i8* %a, unknown before-or-after) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %b, unknown before-or-after) define void @test5(i8* noalias %a, i8* noalias %b) { entry: store i8 1, i8* %a, align 1 @@ -51,8 +51,8 @@ entry: ; CHECK: Alias sets for function 'test_argcollapse': ; CHECK-NEXT: Alias Set Tracker: 2 alias sets for 2 pointer values. -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod/Ref Pointers: (i8* %a, unknown) -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod/Ref Pointers: (i8* %b, unknown) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod/Ref Pointers: (i8* %a, unknown before-or-after) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod/Ref Pointers: (i8* %b, unknown before-or-after) define void @test_argcollapse(i8* noalias %a, i8* noalias %b) { entry: store i8 1, i8* %a, align 1 @@ -63,8 +63,8 @@ entry: ; CHECK: Alias sets for function 'test_memcpy1': ; CHECK-NEXT: Alias Set Tracker: 2 alias sets for 2 pointer values. -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod/Ref Pointers: (i8* %b, unknown) -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod/Ref Pointers: (i8* %a, unknown) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod/Ref Pointers: (i8* %b, unknown before-or-after) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod/Ref Pointers: (i8* %a, unknown before-or-after) define void @test_memcpy1(i8* noalias %a, i8* noalias %b) { entry: call void @my_memcpy(i8* %b, i8* %a, i64 1) @@ -74,7 +74,7 @@ entry: ; CHECK: Alias sets for function 'test_memset1': ; CHECK-NEXT: Alias Set Tracker: 1 alias sets for 1 pointer values. -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %a, unknown) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %a, unknown before-or-after) define void @test_memset1() { entry: %a = alloca i8, align 1 @@ -84,7 +84,7 @@ entry: ; CHECK: Alias sets for function 'test_memset2': ; CHECK-NEXT: Alias Set Tracker: 1 alias sets for 1 pointer values. -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %a, unknown) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %a, unknown before-or-after) define void @test_memset2(i8* %a) { entry: call void @my_memset(i8* %a, i8 0, i64 1) @@ -93,7 +93,7 @@ entry: ; CHECK: Alias sets for function 'test_memset3': ; CHECK-NEXT: Alias Set Tracker: 1 alias sets for 2 pointer values. -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 2] may alias, Mod Pointers: (i8* %a, unknown), (i8* %b, unknown) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 2] may alias, Mod Pointers: (i8* %a, unknown before-or-after), (i8* %b, unknown before-or-after) define void @test_memset3(i8* %a, i8* %b) { entry: call void @my_memset(i8* %a, i8 0, i64 1) @@ -105,8 +105,8 @@ entry: ; CHECK: Alias sets for function 'test_memset4': ; CHECK-NEXT: Alias Set Tracker: 2 alias sets for 2 pointer values. -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %a, unknown) -; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %b, unknown) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %a, unknown before-or-after) +; CHECK-NEXT: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %b, unknown before-or-after) define void @test_memset4(i8* noalias %a, i8* noalias %b) { entry: call void @my_memset(i8* %a, i8 0, i64 1) diff --git a/llvm/test/Analysis/AliasSet/memset.ll b/llvm/test/Analysis/AliasSet/memset.ll index bfa5e1b2fc6c7..ccec88c60ebbc 100644 --- a/llvm/test/Analysis/AliasSet/memset.ll +++ b/llvm/test/Analysis/AliasSet/memset.ll @@ -14,7 +14,7 @@ entry: ; CHECK: Alias sets for function 'test_unknown_size': ; CHECK: Alias Set Tracker: 1 alias sets for 1 pointer values. -; CHECK: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %d, unknown) +; CHECK: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %d, unknown after) define void @test_unknown_size(i8* noalias %d, i64 %len) { entry: call void @llvm.memset.p0i8.i64(i8* align 1 %d, i8 0, i64 %len, i1 false) @@ -33,7 +33,7 @@ entry: ; CHECK: Alias sets for function 'test_atomic_unknown_size': ; CHECK: Alias Set Tracker: 1 alias sets for 1 pointer values. -; CHECK: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %d, unknown) +; CHECK: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %d, unknown after) define void @test_atomic_unknown_size(i8* noalias %d, i64 %len) { entry: call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 1 %d, i8 0, i64 %len, i32 1) diff --git a/llvm/test/Analysis/AliasSet/memtransfer.ll b/llvm/test/Analysis/AliasSet/memtransfer.ll index 0883db024f223..d30bbce140dc2 100644 --- a/llvm/test/Analysis/AliasSet/memtransfer.ll +++ b/llvm/test/Analysis/AliasSet/memtransfer.ll @@ -16,8 +16,8 @@ entry: ; CHECK: Alias sets for function 'test_unknown_size': ; CHECK: Alias Set Tracker: 2 alias sets for 2 pointer values. -; CHECK: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %d, unknown) -; CHECK: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Ref Pointers: (i8* %s, unknown) +; CHECK: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Mod Pointers: (i8* %d, unknown after) +; CHECK: AliasSet[0x{{[0-9a-f]+}}, 1] must alias, Ref Pointers: (i8* %s, unknown after) define void @test_unknown_size(i8* noalias %s, i8* noalias %d, i64 %len) { entry: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %d, i8* %s, i64 %len, i1 false) diff --git a/llvm/test/Analysis/BasicAA/2008-04-15-Byval.ll b/llvm/test/Analysis/BasicAA/2008-04-15-Byval.ll index 9d4fd14831859..e5d260c54f291 100644 --- a/llvm/test/Analysis/BasicAA/2008-04-15-Byval.ll +++ b/llvm/test/Analysis/BasicAA/2008-04-15-Byval.ll @@ -4,13 +4,13 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3 target triple = "i386-apple-darwin8" %struct.x = type { [4 x i32] } -define void @foo(%struct.x* byval align 4 %X) nounwind { +define void @foo(%struct.x* byval(%struct.x) align 4 %X) nounwind { ; CHECK: store i32 2, i32* %tmp1 entry: %tmp = getelementptr %struct.x, %struct.x* %X, i32 0, i32 0 ; <[4 x i32]*> [#uses=1] %tmp1 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 3 ; [#uses=1] store i32 2, i32* %tmp1, align 4 - %tmp2 = call i32 (...) @bar( %struct.x* byval align 4 %X ) nounwind ; [#uses=0] + %tmp2 = call i32 (...) @bar(%struct.x* byval(%struct.x) align 4 %X ) nounwind ; [#uses=0] br label %return return: ; preds = %entry ret void diff --git a/llvm/test/Analysis/BasicAA/byval.ll b/llvm/test/Analysis/BasicAA/byval.ll index 0699436a8a0be..91d7ad9ee28d1 100644 --- a/llvm/test/Analysis/BasicAA/byval.ll +++ b/llvm/test/Analysis/BasicAA/byval.ll @@ -4,7 +4,7 @@ target triple = "i686-apple-darwin8" %struct.x = type { i32, i32, i32, i32 } @g = weak global i32 0 ; [#uses=1] -define i32 @foo(%struct.x* byval %a) nounwind { +define i32 @foo(%struct.x* byval(%struct.x) %a) nounwind { ; CHECK: ret i32 1 %tmp1 = tail call i32 (...) @bar( %struct.x* %a ) nounwind ; [#uses=0] %tmp2 = getelementptr %struct.x, %struct.x* %a, i32 0, i32 0 ; [#uses=2] diff --git a/llvm/test/Analysis/BasicAA/cs-cs.ll b/llvm/test/Analysis/BasicAA/cs-cs.ll index bbca235923579..4eb348a02bbfb 100644 --- a/llvm/test/Analysis/BasicAA/cs-cs.ll +++ b/llvm/test/Analysis/BasicAA/cs-cs.ll @@ -273,9 +273,9 @@ entry: ; CHECK-LABEL: Function: test8 ; CHECK: NoModRef: Ptr: i8* %p <-> call void @an_inaccessiblememonly_func() ; CHECK: NoModRef: Ptr: i8* %q <-> call void @an_inaccessiblememonly_func() -; CHECK: NoModRef: Ptr: i8* %p <-> call void @an_inaccessibleorargmemonly_func(i8* %q) +; CHECK: Both ModRef: Ptr: i8* %p <-> call void @an_inaccessibleorargmemonly_func(i8* %q) ; CHECK: Both ModRef (MustAlias): Ptr: i8* %q <-> call void @an_inaccessibleorargmemonly_func(i8* %q) -; CHECK: NoModRef: Ptr: i8* %p <-> call void @an_argmemonly_func(i8* %q) +; CHECK: Both ModRef: Ptr: i8* %p <-> call void @an_argmemonly_func(i8* %q) ; CHECK: Both ModRef (MustAlias): Ptr: i8* %q <-> call void @an_argmemonly_func(i8* %q) ; CHECK: Just Ref: call void @a_readonly_func(i8* %p) <-> call void @an_inaccessiblememonly_func() ; CHECK: Just Ref: call void @a_readonly_func(i8* %p) <-> call void @an_inaccessibleorargmemonly_func(i8* %q) @@ -368,9 +368,9 @@ entry: ; CHECK: Just Ref: Ptr: i8* %q <-> call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] ; CHECK: NoModRef: Ptr: i8* %p <-> call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] ; CHECK: NoModRef: Ptr: i8* %q <-> call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] -; CHECK: NoModRef: Ptr: i8* %p <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] +; CHECK: Both ModRef: Ptr: i8* %p <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] ; CHECK: Both ModRef (MustAlias): Ptr: i8* %q <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] -; CHECK: NoModRef: Ptr: i8* %p <-> call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] +; CHECK: Both ModRef: Ptr: i8* %p <-> call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] ; CHECK: Both ModRef (MustAlias): Ptr: i8* %q <-> call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] ; CHECK: Just Ref: call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] <-> call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] ; CHECK: Just Ref: call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] diff --git a/llvm/test/Analysis/BasicAA/dereferenceable.ll b/llvm/test/Analysis/BasicAA/dereferenceable.ll index fcceb50b2c588..438114d8ac4f5 100644 --- a/llvm/test/Analysis/BasicAA/dereferenceable.ll +++ b/llvm/test/Analysis/BasicAA/dereferenceable.ll @@ -24,7 +24,7 @@ bb: ret i32 %tmp } -define i32 @byval_and_deref_arg_1(i32* byval %obj, i64* dereferenceable(8) %arg) { +define i32 @byval_and_deref_arg_1(i32* byval(i32) %obj, i64* dereferenceable(8) %arg) { ; CHECK: Function: byval_and_deref_arg_1: 2 pointers, 0 call sites ; CHECK-NEXT: NoAlias: i32* %obj, i64* %arg bb: @@ -34,7 +34,7 @@ bb: ret i32 %tmp } -define i32 @byval_and_deref_arg_2(i32* byval %obj, i32* dereferenceable(8) %arg) { +define i32 @byval_and_deref_arg_2(i32* byval(i32) %obj, i32* dereferenceable(8) %arg) { ; CHECK: Function: byval_and_deref_arg_2: 2 pointers, 0 call sites ; CHECK-NEXT: NoAlias: i32* %arg, i32* %obj bb: @@ -98,7 +98,7 @@ bb: ret i32 %tmp } -define i32 @byval_and_deref_arg_non_deref_1(i32* byval %obj, i64* dereferenceable(2) %arg) { +define i32 @byval_and_deref_arg_non_deref_1(i32* byval(i32) %obj, i64* dereferenceable(2) %arg) { ; CHECK: Function: byval_and_deref_arg_non_deref_1: 2 pointers, 0 call sites ; CHECK-NEXT: NoAlias: i32* %obj, i64* %arg bb: @@ -108,7 +108,7 @@ bb: ret i32 %tmp } -define i32 @byval_and_deref_arg_non_deref_2(i32* byval %obj, i32* dereferenceable(2) %arg) { +define i32 @byval_and_deref_arg_non_deref_2(i32* byval(i32) %obj, i32* dereferenceable(2) %arg) { ; CHECK: Function: byval_and_deref_arg_non_deref_2: 2 pointers, 0 call sites ; CHECK-NEXT: NoAlias: i32* %arg, i32* %obj bb: diff --git a/llvm/test/Analysis/BasicAA/phi-speculation.ll b/llvm/test/Analysis/BasicAA/phi-speculation.ll index 198c5340488ec..12b2310f4c455 100644 --- a/llvm/test/Analysis/BasicAA/phi-speculation.ll +++ b/llvm/test/Analysis/BasicAA/phi-speculation.ll @@ -92,3 +92,85 @@ while.body: the_exit: ret i32 1 } + +; CHECK-LABEL: test_different_stride_noalias +; CHECK: NoAlias: i16* %y.base, i8* %x.base +; CHECK: NoAlias: i16* %y, i8* %x +; CHECK: NoAlias: i16* %y.next, i8* %x.next +define void @test_different_stride_noalias(i1 %c, i8* noalias %x.base, i16* noalias %y.base) { +entry: + br label %loop + +loop: + %x = phi i8* [ %x.base, %entry ], [ %x.next, %loop ] + %y = phi i16* [ %y.base, %entry ], [ %y.next, %loop ] + %x.next = getelementptr i8, i8* %x, i64 1 + %y.next = getelementptr i16, i16* %y, i64 1 + br i1 %c, label %loop, label %exit + +exit: + ret void +} + +; CHECK-LABEL: test_no_loop_mustalias +; CHECK: MayAlias: i16* %z16, i8* %z8 +; TODO: (z8, z16) could be MustAlias +define void @test_no_loop_mustalias(i1 %c, i8* noalias %x8, i8* noalias %y8) { + br i1 %c, label %if, label %else + +if: + %x16 = bitcast i8* %x8 to i16* + br label %end + +else: + %y16 = bitcast i8* %y8 to i16* + br label %end + +end: + %z8 = phi i8* [ %x8, %if ], [ %y8, %else ] + %z16 = phi i16* [ %x16, %if ], [ %y16, %else ] + ret void +} + +; CHECK-LABEL: test_same_stride_mustalias +; CHECK: MustAlias: i4* %y.base, i8* %x.base +; CHECK: MayAlias: i4* %y, i8* %x +; CHECK: MayAlias: i4* %y.next, i8* %x.next +; TODO: (x, y) could be MustAlias +define void @test_same_stride_mustalias(i1 %c, i8* noalias %x.base) { +entry: + %y.base = bitcast i8* %x.base to i4* + br label %loop + +loop: + %x = phi i8* [ %x.base, %entry ], [ %x.next, %loop ] + %y = phi i4* [ %y.base, %entry ], [ %y.next, %loop ] + %x.next = getelementptr i8, i8* %x, i64 1 + %y.next = getelementptr i4, i4* %y, i64 1 + br i1 %c, label %loop, label %exit + +exit: + ret void +} + +; CHECK-LABEL: test_different_stride_mustalias +; CHECK: MustAlias: i16* %y.base, i8* %x.base +; CHECK: MayAlias: i16* %y, i8* %x +; CHECK: MayAlias: i16* %y.next, i8* %x.next +; Even though the base pointers MustAlias, the different strides don't preserve +; this property across iterations. +define void @test_different_stride_mustalias(i1 %c, i8* noalias %x.base) { +entry: + %y.base = bitcast i8* %x.base to i16* + br label %loop + +loop: + %x = phi i8* [ %x.base, %entry ], [ %x.next, %loop ] + %y = phi i16* [ %y.base, %entry ], [ %y.next, %loop ] + %x.next = getelementptr i8, i8* %x, i64 1 + %y.next = getelementptr i16, i16* %y, i64 1 + br i1 %c, label %loop, label %exit + +exit: + ret void +} diff --git a/llvm/test/Analysis/BasicAA/recphi.ll b/llvm/test/Analysis/BasicAA/recphi.ll index f0ddb8c94751b..26114fc60e1ca 100644 --- a/llvm/test/Analysis/BasicAA/recphi.ll +++ b/llvm/test/Analysis/BasicAA/recphi.ll @@ -188,6 +188,28 @@ bb5: ; preds = %bb3, %bb4 ret i16 0 } +; CHECK-LABEL: Function: dynamic_offset +; CHECK: NoAlias: i8* %a, i8* %p.base +; CHECK: MayAlias: i8* %p, i8* %p.base +; CHECK: MayAlias: i8* %a, i8* %p +; CHECK: MayAlias: i8* %p.base, i8* %p.next +; CHECK: MayAlias: i8* %a, i8* %p.next +; CHECK: MayAlias: i8* %p, i8* %p.next +define void @dynamic_offset(i1 %c, i8* noalias %p.base) { +entry: + %a = alloca i8 + br label %loop + +loop: + %p = phi i8* [ %p.base, %entry ], [ %p.next, %loop ] + %offset = call i16 @call(i32 0) + %p.next = getelementptr inbounds i8, i8* %p, i16 %offset + br i1 %c, label %loop, label %exit + +exit: + ret void +} + ; TODO: Currently yields an asymmetric result. ; CHECK-LABEL: Function: symmetry ; CHECK: MayAlias: i32* %p, i32* %p.base diff --git a/llvm/test/Analysis/BasicAA/tail-byval.ll b/llvm/test/Analysis/BasicAA/tail-byval.ll index 2fdedb2ae60b0..58c211c20b9d8 100644 --- a/llvm/test/Analysis/BasicAA/tail-byval.ll +++ b/llvm/test/Analysis/BasicAA/tail-byval.ll @@ -1,15 +1,15 @@ ; RUN: opt -basic-aa -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s -declare void @takebyval(i32* byval %p) +declare void @takebyval(i32* byval(i32) %p) define i32 @tailbyval() { entry: %p = alloca i32 store i32 42, i32* %p - tail call void @takebyval(i32* byval %p) + tail call void @takebyval(i32* byval(i32) %p) %rv = load i32, i32* %p ret i32 %rv } ; FIXME: This should be Just Ref. ; CHECK-LABEL: Function: tailbyval: 1 pointers, 1 call sites -; CHECK-NEXT: Both ModRef: Ptr: i32* %p <-> tail call void @takebyval(i32* byval %p) +; CHECK-NEXT: Both ModRef: Ptr: i32* %p <-> tail call void @takebyval(i32* byval(i32) %p) diff --git a/llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll b/llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll index 3a4e0f080a49a..78f6b8d1a03d2 100644 --- a/llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll +++ b/llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll @@ -86,3 +86,95 @@ define <8 x i64> @load_512(<8 x i64>* %ptr) { %out = load <8 x i64>, <8 x i64>* %ptr ret <8 x i64> %out } + +declare <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*>, i32 immarg, <4 x i1>, <4 x i8>) +define <4 x i8> @gather_load_4xi8_constant_mask(<4 x i8*> %ptrs) { +; CHECK: gather_load_4xi8_constant_mask +; CHECK-NEON: Cost Model: Found an estimated cost of 17 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8 +; CHECK-SVE-128: Cost Model: Found an estimated cost of 17 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8 +; CHECK-SVE-256: Cost Model: Found an estimated cost of 17 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8 +; CHECK-SVE-512: Cost Model: Found an estimated cost of 17 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8 +; + %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> , <4 x i8> undef) + ret <4 x i8> %lv +} + +define <4 x i8> @gather_load_4xi8_variable_mask(<4 x i8*> %ptrs, <4 x i1> %cond) { +; CHECK: gather_load_4xi8_variable_mask +; CHECK-NEON: Cost Model: Found an estimated cost of 29 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8 +; CHECK-SVE-128: Cost Model: Found an estimated cost of 29 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8 +; CHECK-SVE-256: Cost Model: Found an estimated cost of 29 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8 +; CHECK-SVE-512: Cost Model: Found an estimated cost of 29 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8 +; + %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> %cond, <4 x i8> undef) + ret <4 x i8> %lv +} + +declare void @llvm.masked.scatter.v4i8.v4p0i8(<4 x i8>, <4 x i8*>, i32 immarg, <4 x i1>) +define void @scatter_store_4xi8_constant_mask(<4 x i8> %val, <4 x i8*> %ptrs) { +; CHECK: scatter_store_4xi8_constant_mask +; CHECK-NEON: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i8.v4p0i8( +; CHECK-SVE-128: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i8.v4p0i8( +; CHECK-SVE-256: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i8.v4p0i8( +; CHECK-SVE-512: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i8.v4p0i8( +; + call void @llvm.masked.scatter.v4i8.v4p0i8(<4 x i8> %val, <4 x i8*> %ptrs, i32 1, <4 x i1> ) + ret void +} + +define void @scatter_store_4xi8_variable_mask(<4 x i8> %val, <4 x i8*> %ptrs, <4 x i1> %cond) { +; CHECK: scatter_store_4xi8_variable_mask +; CHECK-NEON: Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.scatter.v4i8.v4p0i8( +; CHECK-SVE-128: Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.scatter.v4i8.v4p0i8( +; CHECK-SVE-256: Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.scatter.v4i8.v4p0i8( +; CHECK-SVE-512: Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.scatter.v4i8.v4p0i8( +; + call void @llvm.masked.scatter.v4i8.v4p0i8(<4 x i8> %val, <4 x i8*> %ptrs, i32 1, <4 x i1> %cond) + ret void +} + +declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32 immarg, <4 x i1>, <4 x i32>) +define <4 x i32> @gather_load_4xi32_constant_mask(<4 x i32*> %ptrs) { +; CHECK: gather_load_4xi32_constant_mask +; CHECK-NEON: Cost Model: Found an estimated cost of 17 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32 +; CHECK-SVE-128: Cost Model: Found an estimated cost of 17 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32 +; CHECK-SVE-256: Cost Model: Found an estimated cost of 17 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32 +; CHECK-SVE-512: Cost Model: Found an estimated cost of 17 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32 +; + %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 1, <4 x i1> , <4 x i32> undef) + ret <4 x i32> %lv +} + +define <4 x i32> @gather_load_4xi32_variable_mask(<4 x i32*> %ptrs, <4 x i1> %cond) { +; CHECK: gather_load_4xi32_variable_mask +; CHECK-NEON: Cost Model: Found an estimated cost of 29 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32 +; CHECK-SVE-128: Cost Model: Found an estimated cost of 29 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32 +; CHECK-SVE-256: Cost Model: Found an estimated cost of 29 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32 +; CHECK-SVE-512: Cost Model: Found an estimated cost of 29 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32 +; + %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 1, <4 x i1> %cond, <4 x i32> undef) + ret <4 x i32> %lv +} + +declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32 immarg, <4 x i1>) +define void @scatter_store_4xi32_constant_mask(<4 x i32> %val, <4 x i32*> %ptrs) { +; CHECK: scatter_store_4xi32_constant_mask +; CHECK-NEON: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32( +; CHECK-SVE-128: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32( +; CHECK-SVE-256: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32( +; CHECK-SVE-512: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32( +; + call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %val, <4 x i32*> %ptrs, i32 1, <4 x i1> ) + ret void +} + +define void @scatter_store_4xi32_variable_mask(<4 x i32> %val, <4 x i32*> %ptrs, <4 x i1> %cond) { +; CHECK: scatter_store_4xi32_variable_mask +; CHECK-NEON: Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32( +; CHECK-SVE-128: Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32( +; CHECK-SVE-256: Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32( +; CHECK-SVE-512: Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32( +; + call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %val, <4 x i32*> %ptrs, i32 1, <4 x i1> %cond) + ret void +} diff --git a/llvm/test/Analysis/CostModel/AArch64/min-max.ll b/llvm/test/Analysis/CostModel/AArch64/min-max.ll index f47fc1c49ef55..18bac082a66ac 100644 --- a/llvm/test/Analysis/CostModel/AArch64/min-max.ll +++ b/llvm/test/Analysis/CostModel/AArch64/min-max.ll @@ -115,12 +115,13 @@ define <8 x i32> @umin.v8i32(<8 x i32> %v0, <8 x i32> %v1) { } ; COST-LABEL: umin.v2i64 -; COST-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %v0, <2 x i64> %v1) +; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %v0, <2 x i64> %v1) ; CODE-LABEL: umin.v2i64 ; CODE: bb.0 -; CODE: csel -; CODE: csel +; CODE-NEXT: uqsub v{{.*}}.2d, v{{.*}}.2d, v{{.*}}.2d +; CODE-NEXT: sub v{{.*}}.2d, v{{.*}}.2d, v{{.*}}.2d +; CODE-NEXT: ret declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>) define <2 x i64> @umin.v2i64(<2 x i64> %v0, <2 x i64> %v1) { @@ -369,12 +370,13 @@ define <8 x i32> @umax.v8i32(<8 x i32> %v0, <8 x i32> %v1) { } ; COST-LABEL: umax.v2i64 -; COST-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %v0, <2 x i64> %v1) +; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %v0, <2 x i64> %v1) ; CODE-LABEL: umax.v2i64 ; CODE: bb.0 -; CODE: csel -; CODE: csel +; CODE-NEXT: uqsub v{{.*}}.2d, v{{.*}}.2d, v{{.*}}.2d +; CODE-NEXT: add v{{.*}}.2d, v{{.*}}.2d, v{{.*}}.2d +; CODE-NEXT: ret declare <2 x i64> @llvm.umax.v2i64(<2 x i64>, <2 x i64>) define <2 x i64> @umax.v2i64(<2 x i64> %v0, <2 x i64> %v1) { diff --git a/llvm/test/Analysis/CostModel/AArch64/mul.ll b/llvm/test/Analysis/CostModel/AArch64/mul.ll new file mode 100644 index 0000000000000..6a29c6d772d4a --- /dev/null +++ b/llvm/test/Analysis/CostModel/AArch64/mul.ll @@ -0,0 +1,211 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py +; RUN: opt < %s -mtriple=aarch64-unknown-linux-gnu -cost-model -cost-kind=throughput -analyze | FileCheck %s --check-prefix=THROUGHPUT + +; Verify the cost of (vector) multiply instructions. + +define <2 x i8> @t1(<2 x i8> %a, <2 x i8> %b) { +; THROUGHPUT-LABEL: 't1' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = mul <2 x i8> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i8> %1 +; + %1 = mul <2 x i8> %a, %b + ret <2 x i8> %1 +} + +define <4 x i8> @t2(<4 x i8> %a, <4 x i8> %b) { +; THROUGHPUT-LABEL: 't2' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = mul <4 x i8> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i8> %1 +; + %1 = mul <4 x i8> %a, %b + ret <4 x i8> %1 +} + +define <8 x i8> @t3(<8 x i8> %a, <8 x i8> %b) { +; THROUGHPUT-LABEL: 't3' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = mul <8 x i8> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %1 +; + %1 = mul <8 x i8> %a, %b + ret <8 x i8> %1 +} + +define <16 x i8> @t4(<16 x i8> %a, <16 x i8> %b) { +; THROUGHPUT-LABEL: 't4' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = mul <16 x i8> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %1 +; + %1 = mul <16 x i8> %a, %b + ret <16 x i8> %1 +} + +define <32 x i8> @t5(<32 x i8> %a, <32 x i8> %b) { +; THROUGHPUT-LABEL: 't5' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = mul <32 x i8> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %1 +; + %1 = mul <32 x i8> %a, %b + ret <32 x i8> %1 +} + +define <2 x i16> @t6(<2 x i16> %a, <2 x i16> %b) { +; THROUGHPUT-LABEL: 't6' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = mul <2 x i16> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i16> %1 +; + %1 = mul <2 x i16> %a, %b + ret <2 x i16> %1 +} + +define <4 x i16> @t7(<4 x i16> %a, <4 x i16> %b) { +; THROUGHPUT-LABEL: 't7' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = mul <4 x i16> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i16> %1 +; + %1 = mul <4 x i16> %a, %b + ret <4 x i16> %1 +} + +define <8 x i16> @t8(<8 x i16> %a, <8 x i16> %b) { +; THROUGHPUT-LABEL: 't8' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = mul <8 x i16> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %1 +; + %1 = mul <8 x i16> %a, %b + ret <8 x i16> %1 +} + +define <16 x i16> @t9(<16 x i16> %a, <16 x i16> %b) { +; THROUGHPUT-LABEL: 't9' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = mul <16 x i16> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %1 +; + %1 = mul <16 x i16> %a, %b + ret <16 x i16> %1 +} + +define <2 x i32> @t10(<2 x i32> %a, <2 x i32> %b) { +; THROUGHPUT-LABEL: 't10' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = mul <2 x i32> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i32> %1 +; + %1 = mul <2 x i32> %a, %b + ret <2 x i32> %1 +} + +define <4 x i32> @t11(<4 x i32> %a, <4 x i32> %b) { +; THROUGHPUT-LABEL: 't11' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = mul <4 x i32> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %1 +; + %1 = mul <4 x i32> %a, %b + ret <4 x i32> %1 +} + +define <8 x i32> @t12(<8 x i32> %a, <8 x i32> %b) { +; THROUGHPUT-LABEL: 't12' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = mul <8 x i32> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %1 +; + %1 = mul <8 x i32> %a, %b + ret <8 x i32> %1 +} + +define <2 x i64> @t13(<2 x i64> %a, <2 x i64> %b) { +; THROUGHPUT-LABEL: 't13' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = mul nsw <2 x i64> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %1 +; + %1 = mul nsw <2 x i64> %a, %b + ret <2 x i64> %1 +} + +define <4 x i64> @t14(<4 x i64> %a, <4 x i64> %b) { +; THROUGHPUT-LABEL: 't14' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = mul nsw <4 x i64> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %1 +; + %1 = mul nsw <4 x i64> %a, %b + ret <4 x i64> %1 +} + +define <2 x float> @t15(<2 x float> %a, <2 x float> %b) { +; THROUGHPUT-LABEL: 't15' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fmul <2 x float> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x float> %1 +; + %1 = fmul <2 x float> %a, %b + ret <2 x float> %1 +} + +define <4 x float> @t16(<4 x float> %a, <4 x float> %b) { +; THROUGHPUT-LABEL: 't16' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fmul <4 x float> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %1 +; + %1 = fmul <4 x float> %a, %b + ret <4 x float> %1 +} + +define <8 x float> @t17(<8 x float> %a, <8 x float> %b) { +; THROUGHPUT-LABEL: 't17' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = fmul <8 x float> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x float> %1 +; + %1 = fmul <8 x float> %a, %b + ret <8 x float> %1 +} + +define <2 x half> @t18(<2 x half> %a, <2 x half> %b) { +; THROUGHPUT-LABEL: 't18' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fmul <2 x half> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x half> %1 +; + %1 = fmul <2 x half> %a, %b + ret <2 x half> %1 +} + +define <4 x half> @t19(<4 x half> %a, <4 x half> %b) { +; THROUGHPUT-LABEL: 't19' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fmul <4 x half> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x half> %1 +; + %1 = fmul <4 x half> %a, %b + ret <4 x half> %1 +} + +define <8 x half> @t20(<8 x half> %a, <8 x half> %b) { +; THROUGHPUT-LABEL: 't20' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 58 for instruction: %1 = fmul <8 x half> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x half> %1 +; + %1 = fmul <8 x half> %a, %b + ret <8 x half> %1 +} + +define <16 x half> @t21(<16 x half> %a, <16 x half> %b) { +; THROUGHPUT-LABEL: 't21' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 116 for instruction: %1 = fmul <16 x half> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <16 x half> %1 +; + %1 = fmul <16 x half> %a, %b + ret <16 x half> %1 +} + +define <2 x double> @t22(<2 x double> %a, <2 x double> %b) { +; THROUGHPUT-LABEL: 't22' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = fmul <2 x double> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %1 +; + %1 = fmul <2 x double> %a, %b + ret <2 x double> %1 +} + +define <4 x double> @t23(<4 x double> %a, <4 x double> %b) { +; THROUGHPUT-LABEL: 't23' +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = fmul <4 x double> %a, %b +; THROUGHPUT-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x double> %1 +; + %1 = fmul <4 x double> %a, %b + ret <4 x double> %1 +} diff --git a/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll b/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll index 050f2a790533c..25b268b9b2446 100644 --- a/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll +++ b/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll @@ -85,60 +85,60 @@ define i32 @sadd(i32 %arg) { ; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; V8M-SIZE-LABEL: 'sadd' -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 undef, i64 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.sadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.sadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 undef, i32 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.sadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.sadd.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 undef, i16 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.sadd.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.sadd.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.sadd.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 undef, i8 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.sadd.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.sadd.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.sadd.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %I64 = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 undef, i64 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.sadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.sadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %I32 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 undef, i32 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.sadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.sadd.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %I16 = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 undef, i16 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.sadd.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.sadd.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.sadd.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %I8 = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 undef, i8 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.sadd.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.sadd.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.sadd.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; NEON-SIZE-LABEL: 'sadd' -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 undef, i64 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.sadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.sadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 undef, i32 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.sadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.sadd.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 undef, i16 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.sadd.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.sadd.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.sadd.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 undef, i8 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.sadd.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.sadd.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.sadd.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I64 = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 undef, i64 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.sadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.sadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I32 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 undef, i32 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.sadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.sadd.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I16 = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 undef, i16 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.sadd.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.sadd.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.sadd.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I8 = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 undef, i8 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.sadd.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.sadd.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.sadd.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; MVE-SIZE-LABEL: 'sadd' -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 undef, i64 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.sadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.sadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 undef, i32 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.sadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.sadd.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 undef, i16 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.sadd.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.sadd.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.sadd.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 undef, i8 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.sadd.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.sadd.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.sadd.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %I64 = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 undef, i64 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.sadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.sadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 150 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.sadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %I32 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 undef, i32 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.sadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.sadd.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %I16 = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 undef, i16 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.sadd.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.sadd.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.sadd.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %I8 = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 undef, i8 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.sadd.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.sadd.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.sadd.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %I64 = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 undef, i64 undef) @@ -243,60 +243,60 @@ define i32 @uadd(i32 %arg) { ; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; V8M-SIZE-LABEL: 'uadd' -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 undef, i64 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.uadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.uadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.uadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 undef, i32 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.uadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.uadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.uadd.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 undef, i16 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.uadd.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.uadd.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.uadd.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 undef, i8 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.uadd.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.uadd.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.uadd.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 undef, i64 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.uadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.uadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.uadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 undef, i32 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.uadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.uadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.uadd.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 undef, i16 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.uadd.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.uadd.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.uadd.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I8 = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 undef, i8 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.uadd.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.uadd.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.uadd.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; NEON-SIZE-LABEL: 'uadd' -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 undef, i64 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.uadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.uadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.uadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 undef, i32 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.uadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.uadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.uadd.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 undef, i16 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.uadd.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.uadd.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.uadd.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 undef, i8 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.uadd.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.uadd.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.uadd.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 undef, i64 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.uadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.uadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.uadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 undef, i32 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.uadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.uadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.uadd.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 undef, i16 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.uadd.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.uadd.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.uadd.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I8 = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 undef, i8 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.uadd.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.uadd.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.uadd.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; MVE-SIZE-LABEL: 'uadd' -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 undef, i64 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.uadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.uadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.uadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 undef, i32 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.uadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.uadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.uadd.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 undef, i16 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.uadd.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.uadd.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.uadd.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 undef, i8 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.uadd.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.uadd.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.uadd.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 undef, i64 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.uadd.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.uadd.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 145 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.uadd.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 undef, i32 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.uadd.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.uadd.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.uadd.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 undef, i16 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.uadd.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.uadd.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.uadd.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I8 = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 undef, i8 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.uadd.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.uadd.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.uadd.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %I64 = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 undef, i64 undef) @@ -401,60 +401,60 @@ define i32 @ssub(i32 %arg) { ; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; V8M-SIZE-LABEL: 'ssub' -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 undef, i64 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.ssub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.ssub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.ssub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 undef, i32 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.ssub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.ssub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.ssub.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 undef, i16 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.ssub.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.ssub.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.ssub.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 undef, i8 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.ssub.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.ssub.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.ssub.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %I64 = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 undef, i64 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.ssub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.ssub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.ssub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %I32 = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 undef, i32 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.ssub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.ssub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.ssub.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %I16 = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 undef, i16 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.ssub.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.ssub.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.ssub.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %I8 = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 undef, i8 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.ssub.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.ssub.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 133 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.ssub.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; NEON-SIZE-LABEL: 'ssub' -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 undef, i64 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.ssub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.ssub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.ssub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 undef, i32 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.ssub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.ssub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.ssub.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 undef, i16 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.ssub.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.ssub.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.ssub.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 undef, i8 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.ssub.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.ssub.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.ssub.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I64 = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 undef, i64 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.ssub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.ssub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.ssub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I32 = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 undef, i32 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.ssub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.ssub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.ssub.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I16 = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 undef, i16 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.ssub.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.ssub.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.ssub.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I8 = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 undef, i8 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.ssub.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.ssub.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.ssub.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; MVE-SIZE-LABEL: 'ssub' -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 undef, i64 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.ssub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.ssub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.ssub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 undef, i32 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.ssub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.ssub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.ssub.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 undef, i16 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.ssub.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.ssub.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.ssub.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 undef, i8 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.ssub.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.ssub.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.ssub.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %I64 = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 undef, i64 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.ssub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.ssub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 150 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.ssub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %I32 = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 undef, i32 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.ssub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.ssub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.ssub.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %I16 = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 undef, i16 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.ssub.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.ssub.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.ssub.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %I8 = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 undef, i8 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.ssub.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.ssub.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.ssub.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %I64 = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 undef, i64 undef) @@ -559,60 +559,60 @@ define i32 @usub(i32 %arg) { ; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; V8M-SIZE-LABEL: 'usub' -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 undef, i64 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.usub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.usub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.usub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 undef, i32 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.usub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.usub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.usub.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 undef, i16 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.usub.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.usub.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.usub.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 undef, i8 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.usub.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.usub.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.usub.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 undef, i64 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.usub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.usub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.usub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 undef, i32 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.usub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.usub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.usub.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 undef, i16 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.usub.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.usub.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.usub.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I8 = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 undef, i8 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.usub.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.usub.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.usub.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; NEON-SIZE-LABEL: 'usub' -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 undef, i64 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.usub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.usub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.usub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 undef, i32 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.usub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.usub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.usub.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 undef, i16 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.usub.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.usub.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.usub.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 undef, i8 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.usub.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.usub.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.usub.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 undef, i64 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.usub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.usub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.usub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 undef, i32 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.usub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.usub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.usub.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 undef, i16 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.usub.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.usub.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.usub.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I8 = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 undef, i8 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.usub.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.usub.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.usub.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; MVE-SIZE-LABEL: 'usub' -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 undef, i64 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.usub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.usub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.usub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 undef, i32 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.usub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.usub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.usub.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 undef, i16 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.usub.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.usub.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.usub.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 undef, i8 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.usub.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.usub.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.usub.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 undef, i64 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.usub.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.usub.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 145 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.usub.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 undef, i32 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.usub.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.usub.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.usub.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 undef, i16 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.usub.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.usub.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.usub.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I8 = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 undef, i8 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.usub.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.usub.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.usub.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %I64 = call {i64, i1} @llvm.usub.with.overflow.i64(i64 undef, i64 undef) @@ -717,60 +717,60 @@ define i32 @smul(i32 %arg) { ; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; V8M-SIZE-LABEL: 'smul' -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.smul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.smul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.smul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.smul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.smul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.smul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.smul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.smul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.smul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.smul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.smul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.smul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.smul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 51 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.smul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 99 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 51 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.smul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 99 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 195 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.smul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; NEON-SIZE-LABEL: 'smul' -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.smul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.smul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.smul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.smul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.smul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.smul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.smul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.smul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.smul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.smul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.smul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.smul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.smul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.smul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.smul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.smul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; MVE-SIZE-LABEL: 'smul' -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.smul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.smul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.smul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.smul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.smul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.smul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.smul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.smul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 101 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.smul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 325 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.smul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.smul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 557 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.smul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.smul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.smul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.smul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.smul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %I64 = call {i64, i1} @llvm.smul.with.overflow.i64(i64 undef, i64 undef) @@ -875,60 +875,60 @@ define i32 @umul(i32 %arg) { ; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; V8M-SIZE-LABEL: 'umul' -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.umul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.umul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.umul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.umul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.umul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.umul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.umul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.umul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.umul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 53 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.umul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 53 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %I16 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.umul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.umul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.umul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.umul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.umul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 131 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.umul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; NEON-SIZE-LABEL: 'umul' -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.umul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.umul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.umul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.umul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.umul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.umul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.umul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.umul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.umul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.umul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %I16 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.umul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.umul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.umul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.umul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.umul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.umul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; MVE-SIZE-LABEL: 'umul' -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.umul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.umul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.umul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.umul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.umul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.umul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.umul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.umul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 61 for instruction: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.umul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 181 for instruction: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.umul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 151 for instruction: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 553 for instruction: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %I16 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.umul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.umul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.umul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.umul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.umul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.umul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %I64 = call {i64, i1} @llvm.umul.with.overflow.i64(i64 undef, i64 undef) diff --git a/llvm/test/Analysis/CostModel/ARM/arith-ssat.ll b/llvm/test/Analysis/CostModel/ARM/arith-ssat.ll index d5afce84b1360..66c99d804b267 100644 --- a/llvm/test/Analysis/CostModel/ARM/arith-ssat.ll +++ b/llvm/test/Analysis/CostModel/ARM/arith-ssat.ll @@ -85,60 +85,60 @@ define i32 @add(i32 %arg) { ; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; V8M-SIZE-LABEL: 'add' -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.sadd.sat.i32(i32 undef, i32 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.sadd.sat.i16(i16 undef, i16 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.sadd.sat.i8(i8 undef, i8 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V2I64 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I64 = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %I32 = call i32 @llvm.sadd.sat.i32(i32 undef, i32 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V4I32 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8I32 = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V16I32 = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %I16 = call i16 @llvm.sadd.sat.i16(i16 undef, i16 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8I16 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %V32I16 = call <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %I8 = call i8 @llvm.sadd.sat.i8(i8 undef, i8 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V16I8 = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %V32I8 = call <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 136 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef) ; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; NEON-SIZE-LABEL: 'add' -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.sadd.sat.i32(i32 undef, i32 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.sadd.sat.i16(i16 undef, i16 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.sadd.sat.i8(i8 undef, i8 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V4I64 = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 108 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %I32 = call i32 @llvm.sadd.sat.i32(i32 undef, i32 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4I32 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8I32 = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V16I32 = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %I16 = call i16 @llvm.sadd.sat.i16(i16 undef, i16 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I16 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V32I16 = call <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %I8 = call i8 @llvm.sadd.sat.i8(i8 undef, i8 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16I8 = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V32I8 = call <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef) ; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; MVE-SIZE-LABEL: 'add' -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.sadd.sat.i32(i32 undef, i32 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.sadd.sat.i16(i16 undef, i16 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.sadd.sat.i8(i8 undef, i8 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V2I64 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V4I64 = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8I64 = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %I32 = call i32 @llvm.sadd.sat.i32(i32 undef, i32 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4I32 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V8I32 = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16I32 = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %I16 = call i16 @llvm.sadd.sat.i16(i16 undef, i16 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I16 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V32I16 = call <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %I8 = call i8 @llvm.sadd.sat.i8(i8 undef, i8 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16I8 = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32I8 = call <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef) ; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %I64 = call i64 @llvm.sadd.sat.i64(i64 undef, i64 undef) @@ -243,60 +243,60 @@ define i32 @sub(i32 %arg) { ; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; V8M-SIZE-LABEL: 'sub' -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.ssub.sat.i32(i32 undef, i32 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.ssub.sat.i16(i16 undef, i16 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.ssub.sat.i8(i8 undef, i8 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V2I64 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I64 = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V8I64 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %I32 = call i32 @llvm.ssub.sat.i32(i32 undef, i32 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V4I32 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8I32 = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V16I32 = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %I16 = call i16 @llvm.ssub.sat.i16(i16 undef, i16 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8I16 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V16I16 = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %V32I16 = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %I8 = call i8 @llvm.ssub.sat.i8(i8 undef, i8 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V16I8 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 72 for instruction: %V32I8 = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 136 for instruction: %V64I8 = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) ; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; NEON-SIZE-LABEL: 'sub' -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.ssub.sat.i32(i32 undef, i32 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.ssub.sat.i16(i16 undef, i16 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.ssub.sat.i8(i8 undef, i8 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V4I64 = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 108 for instruction: %V8I64 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %I32 = call i32 @llvm.ssub.sat.i32(i32 undef, i32 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4I32 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8I32 = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V16I32 = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %I16 = call i16 @llvm.ssub.sat.i16(i16 undef, i16 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I16 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16I16 = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V32I16 = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %I8 = call i8 @llvm.ssub.sat.i8(i8 undef, i8 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16I8 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V32I8 = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V64I8 = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) ; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; MVE-SIZE-LABEL: 'sub' -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.ssub.sat.i32(i32 undef, i32 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.ssub.sat.i16(i16 undef, i16 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.ssub.sat.i8(i8 undef, i8 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V2I64 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %V4I64 = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 153 for instruction: %V8I64 = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %I32 = call i32 @llvm.ssub.sat.i32(i32 undef, i32 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4I32 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V8I32 = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V16I32 = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %I16 = call i16 @llvm.ssub.sat.i16(i16 undef, i16 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I16 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V16I16 = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V32I16 = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %I8 = call i8 @llvm.ssub.sat.i8(i8 undef, i8 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16I8 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32I8 = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V64I8 = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) ; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %I64 = call i64 @llvm.ssub.sat.i64(i64 undef, i64 undef) diff --git a/llvm/test/Analysis/CostModel/ARM/arith-usat.ll b/llvm/test/Analysis/CostModel/ARM/arith-usat.ll index 1059c2ee551cc..036cb607753d5 100644 --- a/llvm/test/Analysis/CostModel/ARM/arith-usat.ll +++ b/llvm/test/Analysis/CostModel/ARM/arith-usat.ll @@ -85,60 +85,60 @@ define i32 @add(i32 %arg) { ; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; V8M-SIZE-LABEL: 'add' -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.uadd.sat.i32(i32 undef, i32 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.uadd.sat.i16(i16 undef, i16 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.uadd.sat.i8(i8 undef, i8 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2I64 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = call i32 @llvm.uadd.sat.i32(i32 undef, i32 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I32 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I32 = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16I32 = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = call i16 @llvm.uadd.sat.i16(i16 undef, i16 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I16 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V32I16 = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I8 = call i8 @llvm.uadd.sat.i8(i8 undef, i8 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16I8 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V32I8 = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef) ; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; NEON-SIZE-LABEL: 'add' -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.uadd.sat.i32(i32 undef, i32 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.uadd.sat.i16(i16 undef, i16 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.uadd.sat.i8(i8 undef, i8 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2I64 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 52 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.uadd.sat.i32(i32 undef, i32 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4I32 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16I32 = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.uadd.sat.i16(i16 undef, i16 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8I16 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32I16 = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I8 = call i8 @llvm.uadd.sat.i8(i8 undef, i8 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16I8 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I8 = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef) ; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; MVE-SIZE-LABEL: 'add' -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.uadd.sat.i32(i32 undef, i32 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.uadd.sat.i16(i16 undef, i16 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.uadd.sat.i8(i8 undef, i8 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V2I64 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V4I64 = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 146 for instruction: %V8I64 = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = call i32 @llvm.uadd.sat.i32(i32 undef, i32 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4I32 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16I32 = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = call i16 @llvm.uadd.sat.i16(i16 undef, i16 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8I16 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32I16 = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I8 = call i8 @llvm.uadd.sat.i8(i8 undef, i8 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16I8 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I8 = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef) ; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %I64 = call i64 @llvm.uadd.sat.i64(i64 undef, i64 undef) @@ -243,60 +243,60 @@ define i32 @sub(i32 %arg) { ; MVE-RECIP-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; V8M-SIZE-LABEL: 'sub' -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.usub.sat.i8(i8 undef, i8 undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V32I16 = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I8 = call i8 @llvm.usub.sat.i8(i8 undef, i8 undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V16I8 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V32I8 = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64I8 = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) ; V8M-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; NEON-SIZE-LABEL: 'sub' -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.usub.sat.i8(i8 undef, i8 undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 52 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32I16 = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I8 = call i8 @llvm.usub.sat.i8(i8 undef, i8 undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16I8 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I8 = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64I8 = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) ; NEON-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; ; MVE-SIZE-LABEL: 'sub' -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.usub.sat.i8(i8 undef, i8 undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 146 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32I16 = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %I8 = call i8 @llvm.usub.sat.i8(i8 undef, i8 undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16I8 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I8 = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64I8 = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) ; MVE-SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) diff --git a/llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll b/llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll index 8b84afc9b9a65..2ed26243733b8 100644 --- a/llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll +++ b/llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll @@ -22,6 +22,9 @@ declare <16 x float> @llvm.log2.v16f32(<16 x float>) declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) declare <16 x float> @llvm.experimental.constrained.fadd.v16f32(<16 x float>, <16 x float>, metadata, metadata) +declare float @llvm.maximum.f32(float, float) +declare <16 x float> @llvm.maximum.v16f32(<16 x float>, <16 x float>) + declare i32 @llvm.cttz.i32(i32, i1) declare <16 x i32> @llvm.cttz.v16i32(<16 x i32>, i1) @@ -49,13 +52,13 @@ define void @smax(i32 %a, i32 %b, <16 x i32> %va, <16 x i32> %vb) { ; LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE-LABEL: 'smax' -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call i32 @llvm.smax.i32(i32 %a, i32 %b) -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <16 x i32> %vb) +; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %s = call i32 @llvm.smax.i32(i32 %a, i32 %b) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <16 x i32> %vb) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE_LATE-LABEL: 'smax' -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call i32 @llvm.smax.i32(i32 %a, i32 %b) -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <16 x i32> %vb) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s = call i32 @llvm.smax.i32(i32 %a, i32 %b) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <16 x i32> %vb) ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %s = call i32 @llvm.smax.i32(i32 %a, i32 %b) @@ -76,12 +79,12 @@ define void @fmuladd(float %a, float %b, float %c, <16 x float> %va, <16 x float ; ; SIZE-LABEL: 'fmuladd' ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.fmuladd.f32(float %a, float %b, float %c) -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE_LATE-LABEL: 'fmuladd' ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.fmuladd.f32(float %a, float %b, float %c) -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %s = call float @llvm.fmuladd.f32(float %a, float %b, float %c) @@ -102,12 +105,12 @@ define void @log2(float %a, <16 x float> %va) { ; ; SIZE-LABEL: 'log2' ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.log2.f32(float %a) -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call <16 x float> @llvm.log2.v16f32(<16 x float> %va) +; SIZE-NEXT: Cost Model: Found an estimated cost of 528 for instruction: %v = call <16 x float> @llvm.log2.v16f32(<16 x float> %va) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE_LATE-LABEL: 'log2' -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.log2.f32(float %a) -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call <16 x float> @llvm.log2.v16f32(<16 x float> %va) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %s = call float @llvm.log2.f32(float %a) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 672 for instruction: %v = call <16 x float> @llvm.log2.v16f32(<16 x float> %va) ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %s = call float @llvm.log2.f32(float %a) @@ -128,12 +131,12 @@ define void @constrained_fadd(float %a, <16 x float> %va) { ; ; SIZE-LABEL: 'constrained_fadd' ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.experimental.constrained.fadd.f32(float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.ignore") -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %t = call <16 x float> @llvm.experimental.constrained.fadd.v16f32(<16 x float> %va, <16 x float> %va, metadata !"round.dynamic", metadata !"fpexcept.ignore") +; SIZE-NEXT: Cost Model: Found an estimated cost of 528 for instruction: %t = call <16 x float> @llvm.experimental.constrained.fadd.v16f32(<16 x float> %va, <16 x float> %va, metadata !"round.dynamic", metadata !"fpexcept.ignore") ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE_LATE-LABEL: 'constrained_fadd' ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.experimental.constrained.fadd.f32(float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.ignore") -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %t = call <16 x float> @llvm.experimental.constrained.fadd.v16f32(<16 x float> %va, <16 x float> %va, metadata !"round.dynamic", metadata !"fpexcept.ignore") +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 528 for instruction: %t = call <16 x float> @llvm.experimental.constrained.fadd.v16f32(<16 x float> %va, <16 x float> %va, metadata !"round.dynamic", metadata !"fpexcept.ignore") ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %s = call float @llvm.experimental.constrained.fadd.f32(float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.ignore") @@ -141,6 +144,32 @@ define void @constrained_fadd(float %a, <16 x float> %va) { ret void } +define void @fmaximum(float %a, float %b, <16 x float> %va, <16 x float> %vb) { +; THRU-LABEL: 'fmaximum' +; THRU-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %s = call float @llvm.maximum.f32(float %a, float %b) +; THRU-NEXT: Cost Model: Found an estimated cost of 928 for instruction: %v = call <16 x float> @llvm.maximum.v16f32(<16 x float> %va, <16 x float> %vb) +; THRU-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; LATE-LABEL: 'fmaximum' +; LATE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %s = call float @llvm.maximum.f32(float %a, float %b) +; LATE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v = call <16 x float> @llvm.maximum.v16f32(<16 x float> %va, <16 x float> %vb) +; LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; +; SIZE-LABEL: 'fmaximum' +; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.maximum.f32(float %a, float %b) +; SIZE-NEXT: Cost Model: Found an estimated cost of 784 for instruction: %v = call <16 x float> @llvm.maximum.v16f32(<16 x float> %va, <16 x float> %vb) +; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; +; SIZE_LATE-LABEL: 'fmaximum' +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %s = call float @llvm.maximum.f32(float %a, float %b) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 928 for instruction: %v = call <16 x float> @llvm.maximum.v16f32(<16 x float> %va, <16 x float> %vb) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; + %s = call float @llvm.maximum.f32(float %a, float %b) + %v = call <16 x float> @llvm.maximum.v16f32(<16 x float> %va, <16 x float> %vb) + ret void +} + define void @cttz(i32 %a, <16 x i32> %va) { ; THRU-LABEL: 'cttz' ; THRU-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call i32 @llvm.cttz.i32(i32 %a, i1 false) diff --git a/llvm/test/Analysis/CostModel/X86/abs.ll b/llvm/test/Analysis/CostModel/X86/abs.ll index 6361602013424..dbfcb20779dc5 100644 --- a/llvm/test/Analysis/CostModel/X86/abs.ll +++ b/llvm/test/Analysis/CostModel/X86/abs.ll @@ -14,42 +14,42 @@ define void @cost_abs_i64(i64 %a64, <2 x i64> %a128, <4 x i64> %a256, <8 x i64> %a512) { ; SSE2-LABEL: 'cost_abs_i64' -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 false) +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 false) ; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 false) ; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 false) ; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 false) ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSSE3-LABEL: 'cost_abs_i64' -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 false) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 false) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 false) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 false) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 false) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSE42-LABEL: 'cost_abs_i64' -; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 false) -; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 false) -; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 false) -; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 false) +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 false) +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 false) +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 false) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 false) ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX1-LABEL: 'cost_abs_i64' -; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 false) -; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 false) -; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 false) -; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 false) +; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 false) +; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 false) +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 false) +; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 false) ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX2-LABEL: 'cost_abs_i64' -; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 false) -; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 false) +; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 false) +; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 false) ; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 false) ; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 false) ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512-LABEL: 'cost_abs_i64' -; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 false) +; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 false) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 false) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 false) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 false) @@ -64,42 +64,42 @@ define void @cost_abs_i64(i64 %a64, <2 x i64> %a128, <4 x i64> %a256, <8 x i64> define void @cost_abs_i32(i32 %a32, <4 x i32> %a128, <8 x i32> %a256, <16 x i32> %a512) { ; SSE2-LABEL: 'cost_abs_i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 false) +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 false) ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a128, i1 false) ; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a256, i1 false) ; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %a512, i1 false) ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSSE3-LABEL: 'cost_abs_i32' -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 false) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 false) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a128, i1 false) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a256, i1 false) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %a512, i1 false) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSE42-LABEL: 'cost_abs_i32' -; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 false) +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 false) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a128, i1 false) ; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a256, i1 false) ; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %a512, i1 false) ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX1-LABEL: 'cost_abs_i32' -; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 false) +; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 false) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a128, i1 false) ; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a256, i1 false) ; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %a512, i1 false) ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX2-LABEL: 'cost_abs_i32' -; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 false) +; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 false) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a128, i1 false) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a256, i1 false) ; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %a512, i1 false) ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512-LABEL: 'cost_abs_i32' -; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 false) +; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 false) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a128, i1 false) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a256, i1 false) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %a512, i1 false) @@ -114,56 +114,56 @@ define void @cost_abs_i32(i32 %a32, <4 x i32> %a128, <8 x i32> %a256, <16 x i32> define void @cost_abs_i16(i16 %a16, <8 x i16> %a128, <16 x i16> %a256, <32 x i16> %a512) { ; SSE2-LABEL: 'cost_abs_i16' -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 false) -; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 false) -; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 false) +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 false) +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 false) +; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 false) ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSSE3-LABEL: 'cost_abs_i16' -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 false) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 false) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 false) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSE42-LABEL: 'cost_abs_i16' -; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 false) ; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 false) ; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 false) ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX1-LABEL: 'cost_abs_i16' -; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) +; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 false) ; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 false) ; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 false) ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX2-LABEL: 'cost_abs_i16' -; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) +; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 false) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 false) ; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 false) ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512F-LABEL: 'cost_abs_i16' -; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) +; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) ; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 false) ; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 false) ; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 false) ; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512DQ-LABEL: 'cost_abs_i16' -; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) +; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 false) ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 false) ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 false) ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512BW-LABEL: 'cost_abs_i16' -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 false) ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 false) ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 false) ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 false) @@ -179,9 +179,9 @@ define void @cost_abs_i16(i16 %a16, <8 x i16> %a128, <16 x i16> %a256, <32 x i16 define void @cost_abs_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <64 x i8> %a512) { ; SSE2-LABEL: 'cost_abs_i8' ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I8 = call i8 @llvm.abs.i8(i8 %a8, i1 false) -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16I8 = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a128, i1 false) -; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32I8 = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a256, i1 false) -; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i1 false) +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I8 = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a128, i1 false) +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I8 = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a256, i1 false) +; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i1 false) ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSSE3-LABEL: 'cost_abs_i8' @@ -246,42 +246,42 @@ define void @cost_abs_i8(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <64 x i8> %a5 define void @cost_abs_i64_poison(i64 %a64, <2 x i64> %a128, <4 x i64> %a256, <8 x i64> %a512) { ; SSE2-LABEL: 'cost_abs_i64_poison' -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 true) +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 true) ; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 true) ; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 true) ; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 true) ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSSE3-LABEL: 'cost_abs_i64_poison' -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 true) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 true) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 true) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 true) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 true) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSE42-LABEL: 'cost_abs_i64_poison' -; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 true) -; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 true) -; SSE42-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 true) -; SSE42-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 true) +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 true) +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 true) +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 true) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 true) ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX1-LABEL: 'cost_abs_i64_poison' -; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 true) -; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 true) -; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 true) -; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 true) +; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 true) +; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 true) +; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 true) +; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 true) ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX2-LABEL: 'cost_abs_i64_poison' -; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 true) -; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 true) +; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 true) +; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 true) ; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 true) ; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 true) ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512-LABEL: 'cost_abs_i64_poison' -; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 true) +; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I64 = call i64 @llvm.abs.i64(i64 %a64, i1 true) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a128, i1 true) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a256, i1 true) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %a512, i1 true) @@ -296,42 +296,42 @@ define void @cost_abs_i64_poison(i64 %a64, <2 x i64> %a128, <4 x i64> %a256, <8 define void @cost_abs_i32_poison(i32 %a32, <4 x i32> %a128, <8 x i32> %a256, <16 x i32> %a512) { ; SSE2-LABEL: 'cost_abs_i32_poison' -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 true) +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 true) ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a128, i1 true) ; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a256, i1 true) ; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V8I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %a512, i1 true) ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSSE3-LABEL: 'cost_abs_i32_poison' -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 true) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 true) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a128, i1 true) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a256, i1 true) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %a512, i1 true) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSE42-LABEL: 'cost_abs_i32_poison' -; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 true) +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 true) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a128, i1 true) ; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a256, i1 true) ; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %a512, i1 true) ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX1-LABEL: 'cost_abs_i32_poison' -; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 true) +; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 true) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a128, i1 true) ; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a256, i1 true) ; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %a512, i1 true) ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX2-LABEL: 'cost_abs_i32_poison' -; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 true) +; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 true) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a128, i1 true) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a256, i1 true) ; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %a512, i1 true) ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512-LABEL: 'cost_abs_i32_poison' -; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 true) +; AVX512-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I32 = call i32 @llvm.abs.i32(i32 %a32, i1 true) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a128, i1 true) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a256, i1 true) ; AVX512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %a512, i1 true) @@ -346,56 +346,56 @@ define void @cost_abs_i32_poison(i32 %a32, <4 x i32> %a128, <8 x i32> %a256, <16 define void @cost_abs_i16_poison(i16 %a16, <8 x i16> %a128, <16 x i16> %a256, <32 x i16> %a512) { ; SSE2-LABEL: 'cost_abs_i16_poison' -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 true) -; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 true) -; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 true) +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 true) +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 true) +; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 true) ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSSE3-LABEL: 'cost_abs_i16_poison' -; SSSE3-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 true) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 true) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 true) ; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSE42-LABEL: 'cost_abs_i16_poison' -; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 true) ; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 true) ; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 true) ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX1-LABEL: 'cost_abs_i16_poison' -; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) +; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 true) ; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 true) ; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 true) ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX2-LABEL: 'cost_abs_i16_poison' -; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) +; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 true) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 true) ; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 true) ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512F-LABEL: 'cost_abs_i16_poison' -; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) +; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) ; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 true) ; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 true) ; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 true) ; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512DQ-LABEL: 'cost_abs_i16_poison' -; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) +; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 true) ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 true) ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 true) ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; AVX512BW-LABEL: 'cost_abs_i16_poison' -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %I16 = call i16 @llvm.abs.i16(i16 %a16, i1 true) ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a128, i1 true) ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 true) ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> %a512, i1 true) @@ -411,9 +411,9 @@ define void @cost_abs_i16_poison(i16 %a16, <8 x i16> %a128, <16 x i16> %a256, <3 define void @cost_abs_i8_poison(i8 %a8, <16 x i8> %a128, <32 x i8> %a256, <64 x i8> %a512) { ; SSE2-LABEL: 'cost_abs_i8_poison' ; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %I8 = call i8 @llvm.abs.i8(i8 %a8, i1 true) -; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16I8 = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a128, i1 true) -; SSE2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V32I8 = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a256, i1 true) -; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i1 true) +; SSE2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I8 = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a128, i1 true) +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I8 = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a256, i1 true) +; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i1 true) ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SSSE3-LABEL: 'cost_abs_i8_poison' diff --git a/llvm/test/Analysis/CostModel/X86/fmaxnum-size-latency.ll b/llvm/test/Analysis/CostModel/X86/fmaxnum-size-latency.ll index 25aafc0bdfcfb..4b22b74f7a563 100644 --- a/llvm/test/Analysis/CostModel/X86/fmaxnum-size-latency.ll +++ b/llvm/test/Analysis/CostModel/X86/fmaxnum-size-latency.ll @@ -1,15 +1,23 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt < %s -cost-model -analyze -cost-kind=size-latency -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s -; RUN: opt < %s -cost-model -analyze -cost-kind=size-latency -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s +; RUN: opt < %s -cost-model -analyze -cost-kind=size-latency -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE2 +; RUN: opt < %s -cost-model -analyze -cost-kind=size-latency -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX2 define i32 @f32(i32 %arg) { -; CHECK-LABEL: 'f32' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.maxnum.f32(float undef, float undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F32 = call <2 x float> @llvm.maxnum.v2f32(<2 x float> undef, <2 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> undef, <4 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.maxnum.v8f32(<8 x float> undef, <8 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.maxnum.v16f32(<16 x float> undef, <16 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; SSE2-LABEL: 'f32' +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = call float @llvm.maxnum.f32(float undef, float undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F32 = call <2 x float> @llvm.maxnum.v2f32(<2 x float> undef, <2 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> undef, <4 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = call <8 x float> @llvm.maxnum.v8f32(<8 x float> undef, <8 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V16F32 = call <16 x float> @llvm.maxnum.v16f32(<16 x float> undef, <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX2-LABEL: 'f32' +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = call float @llvm.maxnum.f32(float undef, float undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.maxnum.v2f32(<2 x float> undef, <2 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = call <4 x float> @llvm.maxnum.v4f32(<4 x float> undef, <4 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8F32 = call <8 x float> @llvm.maxnum.v8f32(<8 x float> undef, <8 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16F32 = call <16 x float> @llvm.maxnum.v16f32(<16 x float> undef, <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %F32 = call float @llvm.maxnum.f32(float undef, float undef) %V2F32 = call <2 x float> @llvm.maxnum.v2f32(<2 x float> undef, <2 x float> undef) @@ -20,13 +28,21 @@ define i32 @f32(i32 %arg) { } define i32 @f64(i32 %arg) { -; CHECK-LABEL: 'f64' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f64 = call double @llvm.maxnum.f64(double undef, double undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2f64 = call <2 x double> @llvm.maxnum.v2f64(<2 x double> undef, <2 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4f64 = call <4 x double> @llvm.maxnum.v4f64(<4 x double> undef, <4 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8f64 = call <8 x double> @llvm.maxnum.v8f64(<8 x double> undef, <8 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16f64 = call <16 x double> @llvm.maxnum.v16f64(<16 x double> undef, <16 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; SSE2-LABEL: 'f64' +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f64 = call double @llvm.maxnum.f64(double undef, double undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2f64 = call <2 x double> @llvm.maxnum.v2f64(<2 x double> undef, <2 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4f64 = call <4 x double> @llvm.maxnum.v4f64(<4 x double> undef, <4 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8f64 = call <8 x double> @llvm.maxnum.v8f64(<8 x double> undef, <8 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16f64 = call <16 x double> @llvm.maxnum.v16f64(<16 x double> undef, <16 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX2-LABEL: 'f64' +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %f64 = call double @llvm.maxnum.f64(double undef, double undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2f64 = call <2 x double> @llvm.maxnum.v2f64(<2 x double> undef, <2 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4f64 = call <4 x double> @llvm.maxnum.v4f64(<4 x double> undef, <4 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8f64 = call <8 x double> @llvm.maxnum.v8f64(<8 x double> undef, <8 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16f64 = call <16 x double> @llvm.maxnum.v16f64(<16 x double> undef, <16 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %f64 = call double @llvm.maxnum.f64(double undef, double undef) %V2f64 = call <2 x double> @llvm.maxnum.v2f64(<2 x double> undef, <2 x double> undef) diff --git a/llvm/test/Analysis/CostModel/X86/fminnum-size-latency.ll b/llvm/test/Analysis/CostModel/X86/fminnum-size-latency.ll index b81b4d8177582..666e7d33f34e3 100644 --- a/llvm/test/Analysis/CostModel/X86/fminnum-size-latency.ll +++ b/llvm/test/Analysis/CostModel/X86/fminnum-size-latency.ll @@ -1,15 +1,23 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt < %s -cost-model -analyze -cost-kind=size-latency -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s -; RUN: opt < %s -cost-model -analyze -cost-kind=size-latency -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s +; RUN: opt < %s -cost-model -analyze -cost-kind=size-latency -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE2 +; RUN: opt < %s -cost-model -analyze -cost-kind=size-latency -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX2 define i32 @f32(i32 %arg) { -; CHECK-LABEL: 'f32' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = call float @llvm.minnum.f32(float undef, float undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F32 = call <2 x float> @llvm.minnum.v2f32(<2 x float> undef, <2 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.minnum.v4f32(<4 x float> undef, <4 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.minnum.v8f32(<8 x float> undef, <8 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.minnum.v16f32(<16 x float> undef, <16 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; SSE2-LABEL: 'f32' +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F32 = call float @llvm.minnum.f32(float undef, float undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F32 = call <2 x float> @llvm.minnum.v2f32(<2 x float> undef, <2 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = call <4 x float> @llvm.minnum.v4f32(<4 x float> undef, <4 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = call <8 x float> @llvm.minnum.v8f32(<8 x float> undef, <8 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V16F32 = call <16 x float> @llvm.minnum.v16f32(<16 x float> undef, <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX2-LABEL: 'f32' +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F32 = call float @llvm.minnum.f32(float undef, float undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.minnum.v2f32(<2 x float> undef, <2 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4F32 = call <4 x float> @llvm.minnum.v4f32(<4 x float> undef, <4 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8F32 = call <8 x float> @llvm.minnum.v8f32(<8 x float> undef, <8 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16F32 = call <16 x float> @llvm.minnum.v16f32(<16 x float> undef, <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %F32 = call float @llvm.minnum.f32(float undef, float undef) %V2F32 = call <2 x float> @llvm.minnum.v2f32(<2 x float> undef, <2 x float> undef) @@ -20,13 +28,21 @@ define i32 @f32(i32 %arg) { } define i32 @f64(i32 %arg) { -; CHECK-LABEL: 'f64' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %f64 = call double @llvm.minnum.f64(double undef, double undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2f64 = call <2 x double> @llvm.minnum.v2f64(<2 x double> undef, <2 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4f64 = call <4 x double> @llvm.minnum.v4f64(<4 x double> undef, <4 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8f64 = call <8 x double> @llvm.minnum.v8f64(<8 x double> undef, <8 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16f64 = call <16 x double> @llvm.minnum.v16f64(<16 x double> undef, <16 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; SSE2-LABEL: 'f64' +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %f64 = call double @llvm.minnum.f64(double undef, double undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2f64 = call <2 x double> @llvm.minnum.v2f64(<2 x double> undef, <2 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4f64 = call <4 x double> @llvm.minnum.v4f64(<4 x double> undef, <4 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8f64 = call <8 x double> @llvm.minnum.v8f64(<8 x double> undef, <8 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16f64 = call <16 x double> @llvm.minnum.v16f64(<16 x double> undef, <16 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef +; +; AVX2-LABEL: 'f64' +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %f64 = call double @llvm.minnum.f64(double undef, double undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2f64 = call <2 x double> @llvm.minnum.v2f64(<2 x double> undef, <2 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4f64 = call <4 x double> @llvm.minnum.v4f64(<4 x double> undef, <4 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8f64 = call <8 x double> @llvm.minnum.v8f64(<8 x double> undef, <8 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16f64 = call <16 x double> @llvm.minnum.v16f64(<16 x double> undef, <16 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef ; %f64 = call double @llvm.minnum.f64(double undef, double undef) %V2f64 = call <2 x double> @llvm.minnum.v2f64(<2 x double> undef, <2 x double> undef) diff --git a/llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll b/llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll index 4601fbd0ae9d6..4d0dbe544fb59 100644 --- a/llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll +++ b/llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll @@ -25,6 +25,9 @@ declare <16 x float> @llvm.log2.v16f32(<16 x float>) declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) declare <16 x float> @llvm.experimental.constrained.fadd.v16f32(<16 x float>, <16 x float>, metadata, metadata) +declare float @llvm.maximum.f32(float, float) +declare <16 x float> @llvm.maximum.v16f32(<16 x float>, <16 x float>) + declare i32 @llvm.cttz.i32(i32, i1) declare <16 x i32> @llvm.cttz.v16i32(<16 x i32>, i1) @@ -54,13 +57,13 @@ define void @umul(i32 %a, i32 %b, <16 x i32> %va, <16 x i32> %vb) { ; LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE-LABEL: 'umul' -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a, i32 %b) -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> %va, <16 x i32> %vb) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a, i32 %b) +; SIZE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> %va, <16 x i32> %vb) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE_LATE-LABEL: 'umul' -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a, i32 %b) -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> %va, <16 x i32> %vb) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a, i32 %b) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> %va, <16 x i32> %vb) ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %s = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b) @@ -80,13 +83,13 @@ define void @smax(i32 %a, i32 %b, <16 x i32> %va, <16 x i32> %vb) { ; LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE-LABEL: 'smax' -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call i32 @llvm.smax.i32(i32 %a, i32 %b) -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <16 x i32> %vb) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s = call i32 @llvm.smax.i32(i32 %a, i32 %b) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <16 x i32> %vb) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE_LATE-LABEL: 'smax' -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call i32 @llvm.smax.i32(i32 %a, i32 %b) -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <16 x i32> %vb) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s = call i32 @llvm.smax.i32(i32 %a, i32 %b) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <16 x i32> %vb) ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %s = call i32 @llvm.smax.i32(i32 %a, i32 %b) @@ -106,13 +109,13 @@ define void @fmuladd(float %a, float %b, float %c, <16 x float> %va, <16 x float ; LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE-LABEL: 'fmuladd' -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.fmuladd.f32(float %a, float %b, float %c) -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s = call float @llvm.fmuladd.f32(float %a, float %b, float %c) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE_LATE-LABEL: 'fmuladd' -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.fmuladd.f32(float %a, float %b, float %c) -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s = call float @llvm.fmuladd.f32(float %a, float %b, float %c) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc) ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %s = call float @llvm.fmuladd.f32(float %a, float %b, float %c) @@ -133,12 +136,12 @@ define void @log2(float %a, <16 x float> %va) { ; ; SIZE-LABEL: 'log2' ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.log2.f32(float %a) -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call <16 x float> @llvm.log2.v16f32(<16 x float> %va) +; SIZE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %v = call <16 x float> @llvm.log2.v16f32(<16 x float> %va) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE_LATE-LABEL: 'log2' -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.log2.f32(float %a) -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v = call <16 x float> @llvm.log2.v16f32(<16 x float> %va) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %s = call float @llvm.log2.f32(float %a) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 184 for instruction: %v = call <16 x float> @llvm.log2.v16f32(<16 x float> %va) ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %s = call float @llvm.log2.f32(float %a) @@ -159,12 +162,12 @@ define void @constrained_fadd(float %a, <16 x float> %va) { ; ; SIZE-LABEL: 'constrained_fadd' ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.experimental.constrained.fadd.f32(float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.ignore") -; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %t = call <16 x float> @llvm.experimental.constrained.fadd.v16f32(<16 x float> %va, <16 x float> %va, metadata !"round.dynamic", metadata !"fpexcept.ignore") +; SIZE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t = call <16 x float> @llvm.experimental.constrained.fadd.v16f32(<16 x float> %va, <16 x float> %va, metadata !"round.dynamic", metadata !"fpexcept.ignore") ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE_LATE-LABEL: 'constrained_fadd' ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.experimental.constrained.fadd.f32(float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.ignore") -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %t = call <16 x float> @llvm.experimental.constrained.fadd.v16f32(<16 x float> %va, <16 x float> %va, metadata !"round.dynamic", metadata !"fpexcept.ignore") +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %t = call <16 x float> @llvm.experimental.constrained.fadd.v16f32(<16 x float> %va, <16 x float> %va, metadata !"round.dynamic", metadata !"fpexcept.ignore") ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %s = call float @llvm.experimental.constrained.fadd.f32(float %a, float %a, metadata !"round.dynamic", metadata !"fpexcept.ignore") @@ -172,6 +175,32 @@ define void @constrained_fadd(float %a, <16 x float> %va) { ret void } +define void @fmaximum(float %a, float %b, <16 x float> %va, <16 x float> %vb) { +; THRU-LABEL: 'fmaximum' +; THRU-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %s = call float @llvm.maximum.f32(float %a, float %b) +; THRU-NEXT: Cost Model: Found an estimated cost of 196 for instruction: %v = call <16 x float> @llvm.maximum.v16f32(<16 x float> %va, <16 x float> %vb) +; THRU-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; LATE-LABEL: 'fmaximum' +; LATE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %s = call float @llvm.maximum.f32(float %a, float %b) +; LATE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v = call <16 x float> @llvm.maximum.v16f32(<16 x float> %va, <16 x float> %vb) +; LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; +; SIZE-LABEL: 'fmaximum' +; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %s = call float @llvm.maximum.f32(float %a, float %b) +; SIZE-NEXT: Cost Model: Found an estimated cost of 52 for instruction: %v = call <16 x float> @llvm.maximum.v16f32(<16 x float> %va, <16 x float> %vb) +; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; +; SIZE_LATE-LABEL: 'fmaximum' +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %s = call float @llvm.maximum.f32(float %a, float %b) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 196 for instruction: %v = call <16 x float> @llvm.maximum.v16f32(<16 x float> %va, <16 x float> %vb) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; + %s = call float @llvm.maximum.f32(float %a, float %b) + %v = call <16 x float> @llvm.maximum.v16f32(<16 x float> %va, <16 x float> %vb) + ret void +} + define void @cttz(i32 %a, <16 x i32> %va) { ; THRU-LABEL: 'cttz' ; THRU-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %s = call i32 @llvm.cttz.i32(i32 %a, i1 false) diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll index 85712e63d5f36..bc9ed6fb879b2 100644 --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll @@ -32,7 +32,7 @@ define amdgpu_kernel void @test_amdgpu_kernel([4 x <16 x i8>] addrspace(4)* byre ; CHECK: DIVERGENT: ; CHECK: DIVERGENT: ; CHECK: DIVERGENT: -define void @test_c([4 x <16 x i8>] addrspace(5)* byval %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { +define void @test_c([4 x <16 x i8>] addrspace(5)* byval([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { ret void } diff --git a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll index 7276634f225f1..f06c9e2a315b0 100644 --- a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll +++ b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll @@ -32,7 +32,7 @@ define amdgpu_kernel void @test_amdgpu_kernel([4 x <16 x i8>] addrspace(4)* byre ; CHECK: DIVERGENT: ; CHECK: DIVERGENT: ; CHECK: DIVERGENT: -define void @test_c([4 x <16 x i8>] addrspace(4)* byval %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { +define void @test_c([4 x <16 x i8>] addrspace(4)* byval([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { ret void } diff --git a/llvm/test/Analysis/Lint/noalias-byval.ll b/llvm/test/Analysis/Lint/noalias-byval.ll index 76e2d03d29fae..be33238ddc7cc 100644 --- a/llvm/test/Analysis/Lint/noalias-byval.ll +++ b/llvm/test/Analysis/Lint/noalias-byval.ll @@ -8,7 +8,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture r ; Function Attrs: argmemonly nounwind declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1) #0 -declare void @f1(%s* noalias nocapture sret, %s* nocapture readnone) +declare void @f1(%s* noalias nocapture sret(%s), %s* nocapture readnone) define void @f2() { entry: @@ -17,16 +17,16 @@ entry: %0 = bitcast %s* %c to i8* %1 = bitcast %s* %tmp to i8* call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 1, i1 false) - call void @f1(%s* sret %c, %s* %c) + call void @f1(%s* sret(%s) %c, %s* %c) ret void } ; Lint should complain about us passing %c to both arguments since one of them ; is noalias. ; CHECK: Unusual: noalias argument aliases another argument -; CHECK-NEXT: call void @f1(%s* sret %c, %s* %c) +; CHECK-NEXT: call void @f1(%s* sret(%s) %c, %s* %c) -declare void @f3(%s* noalias nocapture sret, %s* byval nocapture readnone) +declare void @f3(%s* noalias nocapture sret(%s), %s* byval(%s) nocapture readnone) define void @f4() { entry: @@ -35,7 +35,7 @@ entry: %0 = bitcast %s* %c to i8* %1 = bitcast %s* %tmp to i8* call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 1, i1 false) - call void @f3(%s* sret %c, %s* byval %c) + call void @f3(%s* sret(%s) %c, %s* byval(%s) %c) ret void } @@ -43,6 +43,6 @@ entry: ; noalias, since the other one is byval, effectively copying the data to the ; stack instead of passing the pointer itself. ; CHECK-NOT: Unusual: noalias argument aliases another argument -; CHECK-NOT: call void @f3(%s* sret %c, %s* %c) +; CHECK-NOT: call void @f3(%s* sret(%s) %c, %s* byval(%s) %c) attributes #0 = { argmemonly nounwind } diff --git a/llvm/test/Analysis/Lint/tail-call-byval.ll b/llvm/test/Analysis/Lint/tail-call-byval.ll index 9f27498189802..14d1474b0bff5 100644 --- a/llvm/test/Analysis/Lint/tail-call-byval.ll +++ b/llvm/test/Analysis/Lint/tail-call-byval.ll @@ -15,12 +15,12 @@ entry: ; CHECK: Undefined behavior: Call with "tail" keyword references alloca ; CHECK-NEXT: tail call void @f1(%s* %c) -declare void @f3(%s* byval) +declare void @f3(%s* byval(%s)) define void @f4() { entry: %c = alloca %s - tail call void @f3(%s* byval %c) + tail call void @f3(%s* byval(%s) %c) ret void } @@ -28,6 +28,6 @@ entry: ; byval, effectively copying the data to the stack instead of leaking the ; pointer itself. ; CHECK-NOT: Undefined behavior: Call with "tail" keyword references alloca -; CHECK-NOT: tail call void @f3(%s* byval %c) +; CHECK-NOT: tail call void @f3(%s* byval(%s) %c) diff --git a/llvm/test/Analysis/LoopAccessAnalysis/memcheck-store-vs-alloc-size.ll b/llvm/test/Analysis/LoopAccessAnalysis/memcheck-store-vs-alloc-size.ll new file mode 100644 index 0000000000000..6d1e19608082b --- /dev/null +++ b/llvm/test/Analysis/LoopAccessAnalysis/memcheck-store-vs-alloc-size.ll @@ -0,0 +1,39 @@ +; RUN: opt -analyze --loop-accesses %s -enable-new-pm=0 | FileCheck %s +; RUN: opt -passes=print-access-info %s -disable-output 2>&1 | FileCheck %s + +; This test defends against accidentally using alloc size instead of store size when performing run-time +; boundary check of memory accesses. The IR in this file is based on +; llvm/test/Analysis/LoopAccessAnalysis/memcheck-off-by-one-error.ll. +; Here, we use i19 instead of i64 because it has a different alloc size to its store size. + +;CHECK: function 'fastCopy': +;CHECK: (Low: %op High: (27 + %op)) +;CHECK: (Low: %src High: (27 + %src)) + +define void @fastCopy(i8* nocapture readonly %src, i8* nocapture %op) { +entry: + br label %while.body.preheader + +while.body.preheader: ; preds = %entry + br label %while.body + +while.body: ; preds = %while.body.preheader, %while.body + %len.addr.07 = phi i32 [ %sub, %while.body ], [ 32, %while.body.preheader ] + %op.addr.06 = phi i8* [ %add.ptr1, %while.body ], [ %op, %while.body.preheader ] + %src.addr.05 = phi i8* [ %add.ptr, %while.body ], [ %src, %while.body.preheader ] + %0 = bitcast i8* %src.addr.05 to i19* + %1 = load i19, i19* %0, align 8 + %2 = bitcast i8* %op.addr.06 to i19* + store i19 %1, i19* %2, align 8 + %add.ptr = getelementptr inbounds i8, i8* %src.addr.05, i19 8 + %add.ptr1 = getelementptr inbounds i8, i8* %op.addr.06, i19 8 + %sub = add nsw i32 %len.addr.07, -8 + %cmp = icmp sgt i32 %len.addr.07, 8 + br i1 %cmp, label %while.body, label %while.end.loopexit + +while.end.loopexit: ; preds = %while.body + br label %while.end + +while.end: ; preds = %while.end.loopexit, %entry + ret void +} diff --git a/llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll b/llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll new file mode 100644 index 0000000000000..d1a980f51c37b --- /dev/null +++ b/llvm/test/Analysis/LoopAccessAnalysis/runtime-pointer-checking-insert-typesize.ll @@ -0,0 +1,27 @@ +; RUN: opt -loop-accesses -analyze -enable-new-pm=0 %s | FileCheck %s +; RUN: opt -passes='print-access-info' -disable-output < %s 2>&1 | FileCheck %s + +; This regression test is defending against a TypeSize warning 'assumption that +; TypeSize is not scalable'. This warning cropped up in +; RuntimePointerChecking::insert when performing loop load elimination because +; this function was previously unaware of scalable types. + +; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. +; CHECK-NOT: warning: {{.*}}TypeSize is not scalable + +define void @runtime_pointer_checking_insert_typesize(* %a, + * %b) { +entry: + br label %loop.body +loop.body: + %0 = phi i64 [ 0, %entry ], [%1, %loop.body] + %idx_a = getelementptr , * %a, i64 %0 + %idx_b = getelementptr , * %b, i64 %0 + %tmp = load , * %idx_a + store %tmp, * %idx_b + %1 = add i64 %0, 2 + %2 = icmp eq i64 %1, 1024 + br i1 %2, label %loop.end, label %loop.body +loop.end: + ret void +} diff --git a/llvm/test/Analysis/MemoryDependenceAnalysis/invariant.group-bug.ll b/llvm/test/Analysis/MemoryDependenceAnalysis/invariant.group-bug.ll index 5ef98b888b3b6..39d6a9fdeac45 100644 --- a/llvm/test/Analysis/MemoryDependenceAnalysis/invariant.group-bug.ll +++ b/llvm/test/Analysis/MemoryDependenceAnalysis/invariant.group-bug.ll @@ -17,7 +17,7 @@ target triple = "x86_64-grtev4-linux-gnu" %4 = type { i8* } %5 = type { i64, [8 x i8] } -define void @fail(i1* noalias sret, %0*, %1*, i8*) local_unnamed_addr #0 { +define void @fail(i1* noalias sret(i1), %0*, %1*, i8*) local_unnamed_addr #0 { ; CHECK-LABEL: @fail( ; CHECK-NEXT: [[TMP5:%.*]] = bitcast %0* [[TMP1:%.*]] to i64 (%0*)*** ; CHECK-NEXT: [[TMP6:%.*]] = load i64 (%0*)**, i64 (%0*)*** [[TMP5]], align 8, !invariant.group !6 diff --git a/llvm/test/Analysis/ScalarEvolution/pr48225.ll b/llvm/test/Analysis/ScalarEvolution/pr48225.ll index bd7dac26ebd3d..eaf9b18d7c5a7 100644 --- a/llvm/test/Analysis/ScalarEvolution/pr48225.ll +++ b/llvm/test/Analysis/ScalarEvolution/pr48225.ll @@ -4,7 +4,6 @@ ; Tests demonstrate the bug reported as PR48225 by Congzhe Cao. -; FIXME: This test demonstrates a bug in max backedge taken count computation. ; When %boolcond = false and %cond = 0: ; - %cond.false.on.first.iter is false on 1st iteration; ; - %cond.false.on.second.iter is false on 2nd iteration; @@ -17,16 +16,16 @@ define void @test_and(i1 %boolcond) { ; CHECK-NEXT: %conv = zext i1 %boolcond to i32 ; CHECK-NEXT: --> (zext i1 %boolcond to i32) U: [0,2) S: [0,2) ; CHECK-NEXT: %iv = phi i32 [ 0, %entry ], [ %inc, %backedge ] -; CHECK-NEXT: --> {0,+,1}<%loop> U: [0,2) S: [0,2) Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: --> {0,+,1}<%loop> U: [0,3) S: [0,3) Exits: <> LoopDispositions: { %loop: Computable } ; CHECK-NEXT: %or.cond = and i1 %cond.false.on.first.iter, %cond.false.on.second.iter ; CHECK-NEXT: --> %or.cond U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: %inc = add nuw nsw i32 %iv, 1 -; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,3) S: [1,3) Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,4) S: [1,4) Exits: <> LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_and ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: 2 ; CHECK-NEXT: exit count for backedge: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %loop: max backedge-taken count is 1 +; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -52,7 +51,6 @@ for.end: ret void } -; FIXME: This test demonstrates a bug in max backedge taken count computation. ; When %boolcond = false and %cond = 0: ; - %cond.true.on.first.iter is true on 1st iteration; ; - %cond.true.on.second.iter is true on 2nd iteration; @@ -65,16 +63,16 @@ define void @test_or(i1 %boolcond) { ; CHECK-NEXT: %conv = zext i1 %boolcond to i32 ; CHECK-NEXT: --> (zext i1 %boolcond to i32) U: [0,2) S: [0,2) ; CHECK-NEXT: %iv = phi i32 [ 0, %entry ], [ %inc, %backedge ] -; CHECK-NEXT: --> {0,+,1}<%loop> U: [0,2) S: [0,2) Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: --> {0,+,1}<%loop> U: [0,3) S: [0,3) Exits: <> LoopDispositions: { %loop: Computable } ; CHECK-NEXT: %or.cond = or i1 %cond.true.on.first.iter, %cond.true.on.second.iter ; CHECK-NEXT: --> %or.cond U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: %inc = add nuw nsw i32 %iv, 1 -; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,3) S: [1,3) Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,4) S: [1,4) Exits: <> LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_or ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: 2 ; CHECK-NEXT: exit count for backedge: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %loop: max backedge-taken count is 1 +; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/StackSafetyAnalysis/local.ll b/llvm/test/Analysis/StackSafetyAnalysis/local.ll index 4d3ee0d210ae8..1a14a0c87a530 100644 --- a/llvm/test/Analysis/StackSafetyAnalysis/local.ll +++ b/llvm/test/Analysis/StackSafetyAnalysis/local.ll @@ -445,7 +445,7 @@ entry: ret void } -define void @ByVal(i16* byval %p) { +define void @ByVal(i16* byval(i16) %p) { ; CHECK-LABEL: @ByVal dso_preemptable{{$}} ; CHECK-NEXT: args uses: ; CHECK-NEXT: allocas uses: @@ -463,16 +463,16 @@ define void @TestByVal() { ; CHECK-EMPTY: entry: %x = alloca i16, align 4 - call void @ByVal(i16* byval %x) + call void @ByVal(i16* byval(i16) %x) %y = alloca i64, align 4 %y1 = bitcast i64* %y to i16* - call void @ByVal(i16* byval %y1) - + call void @ByVal(i16* byval(i16) %y1) + ret void } -declare void @ByValArray([100000 x i64]* byval %p) +declare void @ByValArray([100000 x i64]* byval([100000 x i64]) %p) define void @TestByValArray() { ; CHECK-LABEL: @TestByValArray dso_preemptable{{$}} @@ -485,7 +485,7 @@ entry: %z1 = bitcast [100000 x i64]* %z to i8* %z2 = getelementptr i8, i8* %z1, i64 500000 %z3 = bitcast i8* %z2 to [100000 x i64]* - call void @ByValArray([100000 x i64]* byval %z3) + call void @ByValArray([100000 x i64]* byval([100000 x i64]) %z3) ret void } diff --git a/llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll b/llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll index 340123abba9d3..95ba9f2a1ddf9 100644 --- a/llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll +++ b/llvm/test/Analysis/ValueTracking/memory-dereferenceable.ll @@ -1,4 +1,5 @@ -; RUN: opt -print-memderefs -analyze -S <%s | FileCheck %s +; RUN: opt -print-memderefs -analyze -S < %s -enable-new-pm=0 | FileCheck %s +; RUN: opt -passes=print-memderefs -S < %s -disable-output 2>&1 | FileCheck %s ; Uses the print-deref (+ analyze to print) pass to run ; isDereferenceablePointer() on many load instruction operands @@ -20,12 +21,12 @@ declare i32* @foo() @globalptr.align16 = external global i8, align 16 ; CHECK-LABEL: 'test' -define void @test(%struct.A* sret %result, +define void @test(%struct.A* sret(%struct.A) %result, i32 addrspace(1)* dereferenceable(8) %dparam, i8 addrspace(1)* dereferenceable(32) align 1 %dparam.align1, i8 addrspace(1)* dereferenceable(32) align 16 %dparam.align16, - i8* byval %i8_byval, - %struct.A* byval %A_byval) + i8* byval(i8) %i8_byval, + %struct.A* byval(%struct.A) %A_byval) gc "statepoint-example" { ; CHECK: The following are dereferenceable: entry: @@ -177,7 +178,7 @@ entry: define i32 @f_0(i32 %val) { %ptr = inttoptr i32 %val to i32*, !dereferenceable !0 %load29 = load i32, i32* %ptr, align 8 - ret i32 %load29 + ret i32 %load29 } ; Just check that we don't crash. diff --git a/llvm/test/Assembler/2008-01-11-VarargAttrs.ll b/llvm/test/Assembler/2008-01-11-VarargAttrs.ll index 3111f2d321657..72d02efa21259 100644 --- a/llvm/test/Assembler/2008-01-11-VarargAttrs.ll +++ b/llvm/test/Assembler/2008-01-11-VarargAttrs.ll @@ -6,6 +6,6 @@ declare void @foo(...) define void @bar() { - call void (...) @foo(%struct* byval null ) + call void (...) @foo(%struct* byval(%struct) null ) ret void } diff --git a/llvm/test/Assembler/byval-parse-error0.ll b/llvm/test/Assembler/byval-parse-error0.ll new file mode 100644 index 0000000000000..c451ceea0ba20 --- /dev/null +++ b/llvm/test/Assembler/byval-parse-error0.ll @@ -0,0 +1,6 @@ +; RUN: not llvm-as < %s 2>&1 | FileCheck %s + +; CHECK: :[[@LINE+1]]:34: error: expected '('{{$}} +define void @test_byval(i8* byval) { + ret void +} diff --git a/llvm/test/Assembler/byval-type-attr.ll b/llvm/test/Assembler/byval-type-attr.ll index dd195a39651c0..4b2e31bc3f9ce 100644 --- a/llvm/test/Assembler/byval-type-attr.ll +++ b/llvm/test/Assembler/byval-type-attr.ll @@ -13,8 +13,8 @@ define void @bar({i32*, i8}* byval({i32*, i8}) align 4 %0) { define void @caller({ i32*, i8 }* %ptr) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { ; CHECK: call void @bar({ i32*, i8 }* byval({ i32*, i8 }) %ptr) ; CHECK: invoke void @bar({ i32*, i8 }* byval({ i32*, i8 }) %ptr) - call void @bar({i32*, i8}* byval %ptr) - invoke void @bar({i32*, i8}* byval %ptr) to label %success unwind label %fail + call void @bar({i32*, i8}* byval({i32*, i8}) %ptr) + invoke void @bar({i32*, i8}* byval({i32*, i8}) %ptr) to label %success unwind label %fail success: ret void diff --git a/llvm/test/Assembler/invalid-immarg.ll b/llvm/test/Assembler/invalid-immarg.ll index 65f6ba6c5f467..f2203d2609fd3 100644 --- a/llvm/test/Assembler/invalid-immarg.ll +++ b/llvm/test/Assembler/invalid-immarg.ll @@ -1,7 +1,7 @@ ; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s ; CHECK: Attribute 'immarg' is incompatible with other attributes -declare void @llvm.immarg.byval(i32* byval immarg) +declare void @llvm.immarg.byval(i32* byval(i32) immarg) ; CHECK: Attribute 'immarg' is incompatible with other attributes declare void @llvm.immarg.inalloca(i32* inalloca immarg) @@ -13,7 +13,7 @@ declare void @llvm.immarg.inreg(i32 inreg immarg) declare void @llvm.immarg.nest(i32* nest immarg) ; CHECK: Attribute 'immarg' is incompatible with other attributes -declare void @llvm.immarg.sret(i32* sret immarg) +declare void @llvm.immarg.sret(i32* sret(i32) immarg) ; CHECK: Attribute 'immarg' is incompatible with other attributes declare void @llvm.immarg.zeroext(i32 zeroext immarg) diff --git a/llvm/test/Assembler/sret-parse-error0.ll b/llvm/test/Assembler/sret-parse-error0.ll new file mode 100644 index 0000000000000..47a4aac3fa4ab --- /dev/null +++ b/llvm/test/Assembler/sret-parse-error0.ll @@ -0,0 +1,6 @@ +; RUN: not llvm-as < %s 2>&1 | FileCheck %s + +; CHECK: :[[@LINE+1]]:32: error: expected '('{{$}} +define void @test_sret(i8* sret) { + ret void +} diff --git a/llvm/test/Assembler/sret-type-attr.ll b/llvm/test/Assembler/sret-type-attr.ll index b2efcf576e3e2..1b9dae9481ff8 100644 --- a/llvm/test/Assembler/sret-type-attr.ll +++ b/llvm/test/Assembler/sret-type-attr.ll @@ -13,8 +13,8 @@ define void @bar({i32*, i8}* sret({i32*, i8}) align 4 %0) { define void @caller({ i32*, i8 }* %ptr) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { ; CHECK: call void @bar({ i32*, i8 }* sret({ i32*, i8 }) %ptr) ; CHECK: invoke void @bar({ i32*, i8 }* sret({ i32*, i8 }) %ptr) - call void @bar({i32*, i8}* sret %ptr) - invoke void @bar({i32*, i8}* sret %ptr) to label %success unwind label %fail + call void @bar({i32*, i8}* sret({i32*, i8}) %ptr) + invoke void @bar({i32*, i8}* sret({i32*, i8}) %ptr) to label %success unwind label %fail success: ret void diff --git a/llvm/test/Bindings/OCaml/core.ml b/llvm/test/Bindings/OCaml/core.ml index 86f865267cfa0..c1bf8f908751a 100644 --- a/llvm/test/Bindings/OCaml/core.ml +++ b/llvm/test/Bindings/OCaml/core.ml @@ -262,6 +262,14 @@ let test_constants () = insist (i1_type = type_of c); insist (is_undef c); + (* CHECK: const_poison{{.*}}poison + *) + group "poison"; + let c = poison i1_type in + ignore (define_global "const_poison" c m); + insist (i1_type = type_of c); + insist (is_poison c); + group "constant arithmetic"; (* CHECK: @const_neg = global i64 sub * CHECK: @const_nsw_neg = global i64 sub nsw diff --git a/llvm/test/Bitcode/DIExpression-aggresult.ll b/llvm/test/Bitcode/DIExpression-aggresult.ll index 27298710adbcd..0b89454aa2f94 100644 --- a/llvm/test/Bitcode/DIExpression-aggresult.ll +++ b/llvm/test/Bitcode/DIExpression-aggresult.ll @@ -1,7 +1,7 @@ ; RUN: llvm-dis -o - %s.bc | FileCheck %s %class.A = type { i32, i32, i32, i32 } -define void @_Z3fooi(%class.A* sret %agg.result) #0 !dbg !3 { +define void @_Z3fooi(%class.A* sret(%class.A) %agg.result) #0 !dbg !3 { ; CHECK: call void @llvm.dbg.declare({{.*}}, metadata !DIExpression()), !dbg call void @llvm.dbg.declare(metadata %class.A* %agg.result, metadata !13, metadata !16), !dbg !17 ret void, !dbg !17 diff --git a/llvm/test/Bitcode/attributes-3.3.ll b/llvm/test/Bitcode/attributes-3.3.ll index 9149fc9e10e45..72a8982880163 100644 --- a/llvm/test/Bitcode/attributes-3.3.ll +++ b/llvm/test/Bitcode/attributes-3.3.ll @@ -29,7 +29,7 @@ define void @f4(i8 inreg %0) ret void; } -define void @f5(i8* sret %0) +define void @f5(i8* sret(i8) %0) ; CHECK: define void @f5(i8* sret(i8) %0) { ret void; @@ -47,7 +47,7 @@ define void @f7(i8* noalias %0) ret void; } -define void @f8(i8* byval %0) +define void @f8(i8* byval(i8) %0) ; CHECK: define void @f8(i8* byval(i8) %0) { ret void; diff --git a/llvm/test/Bitcode/attributes.ll b/llvm/test/Bitcode/attributes.ll index f87708e834717..baafc70cf40b0 100644 --- a/llvm/test/Bitcode/attributes.ll +++ b/llvm/test/Bitcode/attributes.ll @@ -26,7 +26,7 @@ define void @f4(i8 inreg %0) ret void; } -define void @f5(i8* sret %0) +define void @f5(i8* sret(i8) %0) ; CHECK: define void @f5(i8* sret(i8) %0) { ret void; @@ -44,7 +44,7 @@ define void @f7(i8* noalias %0) ret void; } -define void @f8(i8* byval %0) +define void @f8(i8* byval(i8) %0) ; CHECK: define void @f8(i8* byval(i8) %0) { ret void; diff --git a/llvm/test/Bitcode/compatibility-3.6.ll b/llvm/test/Bitcode/compatibility-3.6.ll index 4aa4d42aaae1b..05e6b71f14778 100644 --- a/llvm/test/Bitcode/compatibility-3.6.ll +++ b/llvm/test/Bitcode/compatibility-3.6.ll @@ -403,11 +403,11 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) -declare void @f.param.sret(i8* sret) +declare void @f.param.sret(i8* sret(i8)) ; CHECK: declare void @f.param.sret(i8* sret(i8)) declare void @f.param.noalias(i8* noalias) ; CHECK: declare void @f.param.noalias(i8* noalias) diff --git a/llvm/test/Bitcode/compatibility-3.7.ll b/llvm/test/Bitcode/compatibility-3.7.ll index c3658440a2674..b31509ec0a867 100644 --- a/llvm/test/Bitcode/compatibility-3.7.ll +++ b/llvm/test/Bitcode/compatibility-3.7.ll @@ -409,11 +409,11 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) -declare void @f.param.sret(i8* sret) +declare void @f.param.sret(i8* sret(i8)) ; CHECK: declare void @f.param.sret(i8* sret(i8)) declare void @f.param.noalias(i8* noalias) ; CHECK: declare void @f.param.noalias(i8* noalias) diff --git a/llvm/test/Bitcode/compatibility-3.8.ll b/llvm/test/Bitcode/compatibility-3.8.ll index a4e1426059e29..72b01f6a1d98b 100644 --- a/llvm/test/Bitcode/compatibility-3.8.ll +++ b/llvm/test/Bitcode/compatibility-3.8.ll @@ -434,11 +434,11 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) -declare void @f.param.sret(i8* sret) +declare void @f.param.sret(i8* sret(i8)) ; CHECK: declare void @f.param.sret(i8* sret(i8)) declare void @f.param.noalias(i8* noalias) ; CHECK: declare void @f.param.noalias(i8* noalias) diff --git a/llvm/test/Bitcode/compatibility-3.9.ll b/llvm/test/Bitcode/compatibility-3.9.ll index 448adfb33e838..f5b409ab25789 100644 --- a/llvm/test/Bitcode/compatibility-3.9.ll +++ b/llvm/test/Bitcode/compatibility-3.9.ll @@ -503,11 +503,11 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) -declare void @f.param.sret(i8* sret) +declare void @f.param.sret(i8* sret(i8)) ; CHECK: declare void @f.param.sret(i8* sret(i8)) declare void @f.param.noalias(i8* noalias) ; CHECK: declare void @f.param.noalias(i8* noalias) diff --git a/llvm/test/Bitcode/compatibility-4.0.ll b/llvm/test/Bitcode/compatibility-4.0.ll index e5e7194662feb..c7874106d2b99 100644 --- a/llvm/test/Bitcode/compatibility-4.0.ll +++ b/llvm/test/Bitcode/compatibility-4.0.ll @@ -503,11 +503,11 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) -declare void @f.param.sret(i8* sret) +declare void @f.param.sret(i8* sret(i8)) ; CHECK: declare void @f.param.sret(i8* sret(i8)) declare void @f.param.noalias(i8* noalias) ; CHECK: declare void @f.param.noalias(i8* noalias) diff --git a/llvm/test/Bitcode/compatibility-5.0.ll b/llvm/test/Bitcode/compatibility-5.0.ll index 45055486c1ed0..e63ff3a7cc066 100644 --- a/llvm/test/Bitcode/compatibility-5.0.ll +++ b/llvm/test/Bitcode/compatibility-5.0.ll @@ -507,11 +507,11 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) -declare void @f.param.sret(i8* sret) +declare void @f.param.sret(i8* sret(i8)) ; CHECK: declare void @f.param.sret(i8* sret(i8)) declare void @f.param.noalias(i8* noalias) ; CHECK: declare void @f.param.noalias(i8* noalias) diff --git a/llvm/test/Bitcode/compatibility-6.0.ll b/llvm/test/Bitcode/compatibility-6.0.ll index 75e9e8dbc3d95..6018e9b2a8ca9 100644 --- a/llvm/test/Bitcode/compatibility-6.0.ll +++ b/llvm/test/Bitcode/compatibility-6.0.ll @@ -514,11 +514,11 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) -declare void @f.param.sret(i8* sret) +declare void @f.param.sret(i8* sret(i8)) ; CHECK: declare void @f.param.sret(i8* sret(i8)) declare void @f.param.noalias(i8* noalias) ; CHECK: declare void @f.param.noalias(i8* noalias) diff --git a/llvm/test/Bitcode/compatibility.ll b/llvm/test/Bitcode/compatibility.ll index 41fb68455bd39..993d5715721e9 100644 --- a/llvm/test/Bitcode/compatibility.ll +++ b/llvm/test/Bitcode/compatibility.ll @@ -41,10 +41,10 @@ $comdat.samesize = comdat samesize ; CHECK: @const.float = constant double 0.0 @const.null = constant i8* null ; CHECK: @const.null = constant i8* null -%const.struct.type = type { i32, i8 } +%const.struct.type = type { i32, i8, i64 } %const.struct.type.packed = type <{ i32, i8 }> -@const.struct = constant %const.struct.type { i32 -1, i8 undef } -; CHECK: @const.struct = constant %const.struct.type { i32 -1, i8 undef } +@const.struct = constant %const.struct.type { i32 -1, i8 undef, i64 poison } +; CHECK: @const.struct = constant %const.struct.type { i32 -1, i8 undef, i64 poison } @const.struct.packed = constant %const.struct.type.packed <{ i32 -1, i8 1 }> ; CHECK: @const.struct.packed = constant %const.struct.type.packed <{ i32 -1, i8 1 }> @@ -530,11 +530,11 @@ declare void @f.param.signext(i8 signext) ; CHECK: declare void @f.param.signext(i8 signext) declare void @f.param.inreg(i8 inreg) ; CHECK: declare void @f.param.inreg(i8 inreg) -declare void @f.param.byval({ i8, i8 }* byval) +declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) ; CHECK: declare void @f.param.byval({ i8, i8 }* byval({ i8, i8 })) declare void @f.param.inalloca(i8* inalloca) ; CHECK: declare void @f.param.inalloca(i8* inalloca) -declare void @f.param.sret(i8* sret) +declare void @f.param.sret(i8* sret(i8)) ; CHECK: declare void @f.param.sret(i8* sret(i8)) declare void @f.param.noalias(i8* noalias) ; CHECK: declare void @f.param.noalias(i8* noalias) @@ -1075,6 +1075,8 @@ exc: resume i32 undef ; CHECK: resume i32 undef + resume i32 poison + ; CHECK: resume i32 poison unreachable ; CHECK: unreachable @@ -1354,6 +1356,14 @@ define void @instructions.conversions() { ; CHECK: fptoui float undef to i32 fptosi float undef to i32 ; CHECK: fptosi float undef to i32 + fptrunc float poison to half + ; CHECK: fptrunc float poison to half + fpext half poison to float + ; CHECK: fpext half poison to float + fptoui float poison to i32 + ; CHECK: fptoui float poison to i32 + fptosi float poison to i32 + ; CHECK: fptosi float poison to i32 uitofp i32 1 to float ; CHECK: uitofp i32 1 to float sitofp i32 -1 to float diff --git a/llvm/test/Bitcode/highLevelStructure.3.2.ll b/llvm/test/Bitcode/highLevelStructure.3.2.ll index 97f9a26c41431..84c5a8ecda6db 100644 --- a/llvm/test/Bitcode/highLevelStructure.3.2.ll +++ b/llvm/test/Bitcode/highLevelStructure.3.2.ll @@ -36,23 +36,23 @@ declare void @ParamAttr1(i8 zeroext) ; CHECK: declare void @ParamAttr2(i8* nest) declare void @ParamAttr2(i8* nest) ; CHECK: declare void @ParamAttr3(i8* sret(i8)) -declare void @ParamAttr3(i8* sret) +declare void @ParamAttr3(i8* sret(i8)) ; CHECK: declare void @ParamAttr4(i8 signext) declare void @ParamAttr4(i8 signext) ; CHECK: declare void @ParamAttr5(i8* inreg) declare void @ParamAttr5(i8* inreg) ; CHECK: declare void @ParamAttr6(i8* byval(i8)) -declare void @ParamAttr6(i8* byval) +declare void @ParamAttr6(i8* byval(i8)) ; CHECK: declare void @ParamAttr7(i8* noalias) declare void @ParamAttr7(i8* noalias) ; CHECK: declare void @ParamAttr8(i8* nocapture) declare void @ParamAttr8(i8* nocapture) ; CHECK: declare void @ParamAttr9{{[(i8* nest noalias nocapture) | (i8* noalias nocapture nest)]}} declare void @ParamAttr9(i8* nest noalias nocapture) -; CHECK: declare void @ParamAttr10{{[(i8* sret noalias nocapture) | (i8* noalias nocapture sret)]}} -declare void @ParamAttr10(i8* sret noalias nocapture) +; CHECK: declare void @ParamAttr10{{[(i8* sret(i8) noalias nocapture) | (i8* noalias nocapture sret(i8))]}} +declare void @ParamAttr10(i8* sret(i8) noalias nocapture) ;CHECK: declare void @ParamAttr11{{[(i8* byval(i8) noalias nocapture) | (i8* noalias nocapture byval(i8))]}} -declare void @ParamAttr11(i8* byval noalias nocapture) +declare void @ParamAttr11(i8* byval(i8) noalias nocapture) ;CHECK: declare void @ParamAttr12{{[(i8* inreg noalias nocapture) | (i8* noalias nocapture inreg)]}} declare void @ParamAttr12(i8* inreg noalias nocapture) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index 21ea67c5a1cc3..137e859d0b4d7 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -71,23 +71,6 @@ define fp128 @test_quad_dump() { ret fp128 0xL00000000000000004000000000000000 } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %2:_(p0) = G_EXTRACT_VECTOR_ELT %{{[0-9]+}}:_(<2 x p0>), %{{[0-9]+}}:_(s64) (in function: vector_of_pointers_extractelement) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_extractelement -; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_extractelement: -@var = global <2 x i16*> zeroinitializer -define void @vector_of_pointers_extractelement() { - br label %end - -block: - %dummy = extractelement <2 x i16*> %vec, i32 0 - store i16* %dummy, i16** undef - ret void - -end: - %vec = load <2 x i16*>, <2 x i16*>* undef - br label %block -} - ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %2:_(<2 x p0>) = G_INSERT_VECTOR_ELT %0:_, %{{[0-9]+}}:_(p0), %{{[0-9]+}}:_(s32) (in function: vector_of_pointers_insertelement) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll index a9a93d1b7f7a9..5a1ce24bf025a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll @@ -2,10 +2,10 @@ ; RUN: llc < %s -mtriple arm64-apple-darwin -global-isel -stop-after=irtranslator -verify-machineinstrs | FileCheck %s ; Check that we don't try to tail-call with a non-forwarded sret parameter. -declare void @test_explicit_sret(i64* sret) +declare void @test_explicit_sret(i64* sret(i64)) ; Forwarded explicit sret pointer => we can tail call. -define void @can_tail_call_forwarded_explicit_sret_ptr(i64* sret %arg) { +define void @can_tail_call_forwarded_explicit_sret_ptr(i64* sret(i64) %arg) { ; CHECK-LABEL: name: can_tail_call_forwarded_explicit_sret_ptr ; CHECK: bb.1 (%ir-block.0): ; CHECK: liveins: $x8 @@ -17,7 +17,7 @@ define void @can_tail_call_forwarded_explicit_sret_ptr(i64* sret %arg) { } ; Not marked as tail, so don't tail call. -define void @test_call_explicit_sret(i64* sret %arg) { +define void @test_call_explicit_sret(i64* sret(i64) %arg) { ; CHECK-LABEL: name: test_call_explicit_sret ; CHECK: bb.1 (%ir-block.0): ; CHECK: liveins: $x8 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll index 4c2bae9070632..8f43ed01d1b45 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll @@ -166,7 +166,7 @@ define void @test_bad_call_conv() { } ; Shouldn't tail call when the caller has byval arguments. -define void @test_byval(i8* byval %ptr) { +define void @test_byval(i8* byval(i8) %ptr) { ; COMMON-LABEL: name: test_byval ; COMMON: bb.1 (%ir-block.0): ; COMMON: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir index 0144df5197b14..bc3d049c7cdf4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir @@ -131,3 +131,20 @@ body: | $x0 = COPY %5(s64) RET_ReallyLR ... +--- +name: test_eve_v2p0 +body: | + bb.0: + liveins: $q0, $q1, $x0 + ; CHECK-LABEL: name: test_eve_v2p0 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0 + ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK: [[EVEC:%[0-9]+]]:_(p0) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x p0>), [[COPY1]](s64) + ; CHECK: $x0 = COPY [[EVEC]](p0) + ; CHECK: RET_ReallyLR + %0:_(<2 x p0>) = COPY $q0 + %2:_(s64) = COPY $x0 + %3:_(p0) = G_EXTRACT_VECTOR_ELT %0:_(<2 x p0>), %2:_(s64) + $x0 = COPY %3(p0) + RET_ReallyLR +... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir index 22d9406ac4f6f..264d85bad08d9 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir @@ -43,6 +43,28 @@ body: | $q0 = COPY %2(<2 x s64>) RET_ReallyLR implicit $q0 +... +--- +name: shuffle_v2p0 +alignment: 4 +tracksRegLiveness: true +body: | + bb.1: + liveins: $q0, $q1 + + ; CHECK-LABEL: name: shuffle_v2p0 + ; CHECK: liveins: $q0, $q1 + ; CHECK: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0 + ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $q1 + ; CHECK: [[SHUF:%[0-9]+]]:_(<2 x p0>) = G_SHUFFLE_VECTOR [[COPY]](<2 x p0>), [[COPY1]], shufflemask(0, 0) + ; CHECK: $q0 = COPY [[SHUF]](<2 x p0>) + ; CHECK: RET_ReallyLR implicit $q0 + %0:_(<2 x p0>) = COPY $q0 + %1:_(<2 x p0>) = COPY $q1 + %2:_(<2 x p0>) = G_SHUFFLE_VECTOR %0(<2 x p0>), %1, shufflemask(0, 0) + $q0 = COPY %2(<2 x p0>) + RET_ReallyLR implicit $q0 + ... --- name: shuffle_v16i8 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir index 182bba1ae3842..be01e0c347580 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-dup.mir @@ -310,3 +310,28 @@ body: | $q0 = COPY %dup(<16 x s8>) RET_ReallyLR implicit $q0 ... +--- +name: dup_v2p0 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +liveins: + - { reg: '$x0' } +body: | + bb.1: + liveins: $x0 + + ; CHECK-LABEL: name: dup_v2p0 + ; CHECK: liveins: $x0 + ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]] + ; CHECK: [[DUPv2i64gpr:%[0-9]+]]:fpr128 = DUPv2i64gpr [[COPY1]] + ; CHECK: $q0 = COPY [[DUPv2i64gpr]] + ; CHECK: RET_ReallyLR implicit $q0 + %0:gpr(p0) = COPY $x0 + %4:fpr(<2 x p0>) = G_DUP %0(p0) + $q0 = COPY %4(<2 x p0>) + RET_ReallyLR implicit $q0 + +... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir index 17cd2ee27fdb0..919fec7e1b1ff 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select %s -o - | FileCheck %s +# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s ... --- name: v2s32_fpr @@ -209,3 +209,27 @@ body: | %5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64) $h0 = COPY %5(s16) RET_ReallyLR implicit $h0 +... +--- +name: v2p0 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $q0 + + ; CHECK-LABEL: name: v2p0 + ; CHECK: liveins: $q0 + ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 + ; CHECK: [[CPYi64_:%[0-9]+]]:fpr64 = CPYi64 [[COPY]], 1 + ; CHECK: $d0 = COPY [[CPYi64_]] + ; CHECK: RET_ReallyLR implicit $d0 + %0:fpr(<2 x p0>) = COPY $q0 + %2:gpr(s64) = G_CONSTANT i64 1 + %1:fpr(p0) = G_EXTRACT_VECTOR_ELT %0(<2 x p0>), %2(s64) + $d0 = COPY %1(p0) + RET_ReallyLR implicit $d0 + +... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir index 01e6bd820efbc..0b8f1ed948e64 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir @@ -279,8 +279,8 @@ body: | ; CHECK: liveins: $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load 1) - ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[LDRBui]] - ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY2]], 0, 0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[LDRBui]] + ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 0 ; CHECK: $noreg = PATCHABLE_RET [[UBFMWri]] %2:gpr(p0) = COPY $x0 %0:fpr(s1) = G_LOAD %2(p0) :: (load 1) @@ -544,7 +544,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 - ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]] ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]] %5:fpr(s32) = COPY $s2 %4:fpr(s32) = COPY $s1 @@ -581,7 +581,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]] + ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]] ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]] %5:fpr(s64) = COPY $d2 %4:fpr(s64) = COPY $d1 @@ -1083,7 +1083,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY]], [[COPY2]] + ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]] ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]] %4:fpr(<2 x s32>) = COPY $d2 %3:fpr(<2 x s32>) = COPY $d1 @@ -1118,7 +1118,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 - ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY]], [[COPY2]] + ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]] ; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]] %4:fpr(<4 x s32>) = COPY $q2 %3:fpr(<4 x s32>) = COPY $q1 @@ -1153,7 +1153,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 - ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY]], [[COPY2]] + ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]] ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]] %4:fpr(<2 x s64>) = COPY $q2 %3:fpr(<2 x s64>) = COPY $q1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll b/llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll index cbfadbdb5d720..678a9ece6fea0 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll @@ -159,7 +159,7 @@ bb_end: ; "foo_sret" is a function that takes a swifterror parameter, it also has a sret ; parameter. -define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { +define void @foo_sret(%struct.S* sret(%struct.S) %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { ; CHECK-LABEL: foo_sret: ; CHECK: mov [[SRET:x[0-9]+]], x8 ; CHECK: mov w0, #16 @@ -198,7 +198,7 @@ entry: %s = alloca %struct.S, align 8 %error_ptr_ref = alloca swifterror %swift_error* store %swift_error* null, %swift_error** %error_ptr_ref - call void @foo_sret(%struct.S* sret %s, i32 1, %swift_error** swifterror %error_ptr_ref) + call void @foo_sret(%struct.S* sret(%struct.S) %s, i32 1, %swift_error** swifterror %error_ptr_ref) %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null %tmp = bitcast %swift_error* %error_from_foo to i8* diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/swiftself.ll b/llvm/test/CodeGen/AArch64/GlobalISel/swiftself.ll index 0f090d488cf10..2a6bf8734d4ea 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/swiftself.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/swiftself.ll @@ -53,7 +53,7 @@ declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself) ; CHECK: bl {{_?}}thisreturn_attribute ; CHECK: str x0, {{\[}}[[CSREG]] ; CHECK: ret -define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret, i8** noalias nocapture readonly swiftself) { +define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret(i8*), i8** noalias nocapture readonly swiftself) { entry: %2 = load i8*, i8** %1, align 8 %3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2) diff --git a/llvm/test/CodeGen/AArch64/arm64-abi_align.ll b/llvm/test/CodeGen/AArch64/arm64-abi_align.ll index ba2995affe802..fe0b31fb2db91 100644 --- a/llvm/test/CodeGen/AArch64/arm64-abi_align.ll +++ b/llvm/test/CodeGen/AArch64/arm64-abi_align.ll @@ -456,11 +456,11 @@ entry: ; FAST: str {{x[0-9]+}}, [sp, #40] ; FAST: str {{x[0-9]+}}, [sp, #48] ; FAST: str {{x[0-9]+}}, [sp, #56] -; FAST: str {{w[0-9]+}}, [sp] ; Address of s1 is passed on stack at sp+8 ; FAST: sub x[[A:[0-9]+]], x29, #32 -; FAST: str x[[A]], [sp, #8] ; FAST: add x[[B:[0-9]+]], sp, #32 +; FAST: str {{w[0-9]+}}, [sp] +; FAST: str x[[A]], [sp, #8] ; FAST: str x[[B]], [sp, #16] %tmp = alloca %struct.s43, align 16 %tmp1 = alloca %struct.s43, align 16 diff --git a/llvm/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll b/llvm/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll index 71bf2039eaa12..1ea61a8ac71bd 100644 --- a/llvm/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll +++ b/llvm/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll @@ -5,7 +5,7 @@ ; aligned. @T3_retval = common global <16 x float> zeroinitializer, align 16 -define void @test(<16 x float>* noalias sret %agg.result) nounwind ssp { +define void @test(<16 x float>* noalias sret(<16 x float>) %agg.result) nounwind ssp { entry: ; CHECK: test ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], [sp, #32] diff --git a/llvm/test/CodeGen/AArch64/arm64-elf-globals.ll b/llvm/test/CodeGen/AArch64/arm64-elf-globals.ll index 50064ddf5000b..92431ad93b814 100644 --- a/llvm/test/CodeGen/AArch64/arm64-elf-globals.ll +++ b/llvm/test/CodeGen/AArch64/arm64-elf-globals.ll @@ -26,6 +26,7 @@ define i8 @test_i8(i8 %new) { ; CHECK-PIC: ldr x[[VAR_ADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8] ; CHECK-PIC: ldrb {{w[0-9]+}}, [x[[VAR_ADDR]]] +; CHECK-FAST-LABEL: test_i8: ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8] @@ -43,6 +44,7 @@ define i16 @test_i16(i16 %new) { ; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16] ; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16] +; CHECK-FAST-LABEL: test_i16: ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var16 ; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16] } @@ -56,6 +58,7 @@ define i32 @test_i32(i32 %new) { ; CHECK: ldr {{w[0-9]+}}, [x[[HIREG]], :lo12:var32] ; CHECK: str {{w[0-9]+}}, [x[[HIREG]], :lo12:var32] +; CHECK-FAST-LABEL: test_i32: ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var32 ; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var32 } @@ -69,6 +72,7 @@ define i64 @test_i64(i64 %new) { ; CHECK: ldr {{x[0-9]+}}, [x[[HIREG]], :lo12:var64] ; CHECK: str {{x[0-9]+}}, [x[[HIREG]], :lo12:var64] +; CHECK-FAST-LABEL: test_i64: ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var64 ; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var64 } @@ -79,6 +83,7 @@ define i64* @test_addr() { ; CHECK: adrp [[HIREG:x[0-9]+]], var64 ; CHECK: add x0, [[HIREG]], :lo12:var64 +; CHECK-FAST-LABEL: test_addr: ; CHECK-FAST: adrp [[HIREG:x[0-9]+]], var64 ; CHECK-FAST: add x0, [[HIREG]], :lo12:var64 } diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll index 586b7d116f5c8..a677d4a143535 100644 --- a/llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll @@ -78,16 +78,16 @@ declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 ; Test materialization of integers. Target-independent selector handles this. define i32 @t2() { entry: -; CHECK-LABEL: t2 +; CHECK-LABEL: t2: ; CHECK: mov x0, xzr ; CHECK: mov w1, #-8 ; CHECK: mov [[REG2:w[0-9]+]], #1023 -; CHECK: uxth w2, [[REG2]] ; CHECK: mov [[REG3:w[0-9]+]], #2 -; CHECK: sxtb w3, [[REG3]] ; CHECK: mov [[REG4:w[0-9]+]], wzr -; CHECK: and w4, [[REG4]], #0x1 ; CHECK: mov [[REG5:w[0-9]+]], #1 +; CHECK: uxth w2, [[REG2]] +; CHECK: sxtb w3, [[REG3]] +; CHECK: and w4, [[REG4]], #0x1 ; CHECK: and w5, [[REG5]], #0x1 ; CHECK: bl _func2 %call = call i32 @func2(i64 zeroext 0, i32 signext -8, i16 zeroext 1023, i8 signext -254, i1 zeroext 0, i1 zeroext 1) @@ -99,6 +99,7 @@ declare i32 @func2(i64 zeroext, i32 signext, i16 zeroext, i8 signext, i1 zeroext declare void @callee_b0f(i8 %bp10, i8 %bp11, i8 %bp12, i8 %bp13, i8 %bp14, i8 %bp15, i8 %bp17, i8 %bp18, i8 %bp19) define void @caller_b1f() { entry: +; CHECK-LABEL: caller_b1f ; CHECK-BE-LABEL: caller_b1f ; CHECK-BE: strb w{{.*}}, [sp, #7] call void @callee_b0f(i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 42) diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll index 63854b97dea51..ef49962c380c3 100644 --- a/llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll @@ -24,7 +24,11 @@ entry: ; CHECK: mov [[REG3:x[0-9]+]], #13849 ; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]] ; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff +; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE +; CHECK: ldr [[REG1]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}} ; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}} +; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE +; CHECK: ldr [[REG1]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}} ; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]]{{\]}} %0 = load i64, i64* @seed, align 8 %mul = mul nsw i64 %0, 1309 diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll index c1b7d790878d6..e36f33c7f4b4d 100644 --- a/llvm/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll @@ -8,8 +8,8 @@ define void @t1() { ; ARM64: adrp x8, _message@PAGE ; ARM64: add x0, x8, _message@PAGEOFF ; ARM64: mov [[REG:w[0-9]+]], wzr -; ARM64: uxtb w1, [[REG]] ; ARM64: mov x2, #80 +; ARM64: uxtb w1, [[REG]] ; ARM64: bl _memset call void @llvm.memset.p0i8.i64(i8* align 16 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i1 false) ret void diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll index 7dc849b7d2c45..4370b4f979174 100644 --- a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll @@ -2,7 +2,7 @@ define void @t0(i32 %a) nounwind { entry: -; CHECK: t0 +; CHECK-LABEL: t0: ; CHECK: str {{w[0-9]+}}, [sp, #12] ; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12] ; CHECK-NEXT: str [[REGISTER]], [sp, #12] @@ -15,7 +15,7 @@ entry: } define void @t1(i64 %a) nounwind { -; CHECK: t1 +; CHECK-LABEL: t1: ; CHECK: str {{x[0-9]+}}, [sp, #8] ; CHECK-NEXT: ldr [[REGISTER:x[0-9]+]], [sp, #8] ; CHECK-NEXT: str [[REGISTER]], [sp, #8] @@ -29,7 +29,7 @@ define void @t1(i64 %a) nounwind { define zeroext i1 @i1(i1 %a) nounwind { entry: -; CHECK: @i1 +; CHECK-LABEL: i1: ; CHECK: and [[REG:w[0-9]+]], w0, #0x1 ; CHECK: strb [[REG]], [sp, #15] ; CHECK: ldrb [[REG1:w[0-9]+]], [sp, #15] @@ -84,7 +84,7 @@ entry: } define void @t6() nounwind { -; CHECK: t6 +; CHECK-LABEL: t6: ; CHECK: brk #0x1 tail call void @llvm.trap() ret void @@ -93,11 +93,12 @@ define void @t6() nounwind { declare void @llvm.trap() nounwind define void @ands(i32* %addr) { -; CHECK-LABEL: ands: -; CHECK: tst [[COND:w[0-9]+]], #0x1 -; CHECK-NEXT: mov w{{[0-9]+}}, #2 -; CHECK-NEXT: mov w{{[0-9]+}}, #1 -; CHECK-NEXT: csel [[COND]], +; FIXME: 'select i1 undef' makes this unreliable (ub?). +; CHECK-COM-LABEL: ands: +; CHECK-COM: tst [[COND:w[0-9]+]], #0x1 +; CHECK-COM-NEXT: mov w{{[0-9]+}}, #2 +; CHECK-COM-NEXT: mov w{{[0-9]+}}, #1 +; CHECK-COM-NEXT: csel [[COND]], entry: %cond91 = select i1 undef, i32 1, i32 2 store i32 %cond91, i32* %addr, align 4 diff --git a/llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll b/llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll index be52469ec55d9..fa07beb2fb96b 100644 --- a/llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll +++ b/llvm/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll @@ -51,10 +51,10 @@ entry: ; CHECK-NEXT: blr x16 ; FAST-LABEL: jscall_patchpoint_codegen2: ; FAST: mov [[REG1:x[0-9]+]], #2 -; FAST-NEXT: str [[REG1]], [sp] ; FAST-NEXT: mov [[REG2:w[0-9]+]], #4 -; FAST-NEXT: str [[REG2]], [sp, #16] ; FAST-NEXT: mov [[REG3:x[0-9]+]], #6 +; FAST-NEXT: str [[REG1]], [sp] +; FAST-NEXT: str [[REG2]], [sp, #16] ; FAST-NEXT: str [[REG3]], [sp, #24] ; FAST: Ltmp ; FAST-NEXT: mov x16, #281470681743360 @@ -87,14 +87,14 @@ entry: ; CHECK-NEXT: blr x16 ; FAST-LABEL: jscall_patchpoint_codegen3: ; FAST: mov [[REG1:x[0-9]+]], #2 -; FAST-NEXT: str [[REG1]], [sp] ; FAST-NEXT: mov [[REG2:w[0-9]+]], #4 -; FAST-NEXT: str [[REG2]], [sp, #16] ; FAST-NEXT: mov [[REG3:x[0-9]+]], #6 -; FAST-NEXT: str [[REG3]], [sp, #24] ; FAST-NEXT: mov [[REG4:w[0-9]+]], #8 -; FAST-NEXT: str [[REG4]], [sp, #36] ; FAST-NEXT: mov [[REG5:x[0-9]+]], #10 +; FAST-NEXT: str [[REG1]], [sp] +; FAST-NEXT: str [[REG2]], [sp, #16] +; FAST-NEXT: str [[REG3]], [sp, #24] +; FAST-NEXT: str [[REG4]], [sp, #36] ; FAST-NEXT: str [[REG5]], [sp, #48] ; FAST: Ltmp ; FAST-NEXT: mov x16, #281470681743360 diff --git a/llvm/test/CodeGen/AArch64/arm64-vmul.ll b/llvm/test/CodeGen/AArch64/arm64-vmul.ll index bfb4183f4dacd..736e1d8155181 100644 --- a/llvm/test/CodeGen/AArch64/arm64-vmul.ll +++ b/llvm/test/CodeGen/AArch64/arm64-vmul.ll @@ -725,7 +725,7 @@ define <2 x float> @fmls_commuted_neg_2s(<2 x float>* %A, <2 x float>* %B, <2 x ; CHECK-NEXT: ldr d1, [x0] ; CHECK-NEXT: ldr d2, [x1] ; CHECK-NEXT: ldr d0, [x2] -; CHECK-NEXT: fmls.2s v0, v2, v1 +; CHECK-NEXT: fmls.2s v0, v1, v2 ; CHECK-NEXT: ret %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = load <2 x float>, <2 x float>* %B @@ -741,7 +741,7 @@ define <4 x float> @fmls_commuted_neg_4s(<4 x float>* %A, <4 x float>* %B, <4 x ; CHECK-NEXT: ldr q1, [x0] ; CHECK-NEXT: ldr q2, [x1] ; CHECK-NEXT: ldr q0, [x2] -; CHECK-NEXT: fmls.4s v0, v2, v1 +; CHECK-NEXT: fmls.4s v0, v1, v2 ; CHECK-NEXT: ret %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = load <4 x float>, <4 x float>* %B @@ -757,7 +757,7 @@ define <2 x double> @fmls_commuted_neg_2d(<2 x double>* %A, <2 x double>* %B, <2 ; CHECK-NEXT: ldr q1, [x0] ; CHECK-NEXT: ldr q2, [x1] ; CHECK-NEXT: ldr q0, [x2] -; CHECK-NEXT: fmls.2d v0, v2, v1 +; CHECK-NEXT: fmls.2d v0, v1, v2 ; CHECK-NEXT: ret %tmp1 = load <2 x double>, <2 x double>* %A %tmp2 = load <2 x double>, <2 x double>* %B diff --git a/llvm/test/CodeGen/AArch64/arm64-windows-calls.ll b/llvm/test/CodeGen/AArch64/arm64-windows-calls.ll index bbdc594eca95b..1fee2246b7510 100644 --- a/llvm/test/CodeGen/AArch64/arm64-windows-calls.ll +++ b/llvm/test/CodeGen/AArch64/arm64-windows-calls.ll @@ -51,7 +51,7 @@ entry: ; Arguments > 16 bytes should be passed in X8. %struct.S3 = type { i32, i32, i32, i32, i32 } -define dso_local void @"?f3"(%struct.S3* noalias sret %agg.result) { +define dso_local void @"?f3"(%struct.S3* noalias sret(%struct.S3) %agg.result) { entry: ; CHECK-LABEL: f3 ; CHECK: stp xzr, xzr, [x8] @@ -73,7 +73,7 @@ entry: ; InReg arguments to non-instance methods must be passed in X0 and returns in ; X0. %class.B = type { i32 } -define dso_local void @"?f4"(%class.B* inreg noalias nocapture sret %agg.result) { +define dso_local void @"?f4"(%class.B* inreg noalias nocapture sret(%class.B) %agg.result) { entry: ; CHECK-LABEL: f4 ; CHECK: mov w8, #1 @@ -87,7 +87,7 @@ entry: %class.C = type { i8 } %class.A = type { i8 } -define dso_local void @"?inst@C"(%class.C* %this, %class.A* inreg noalias sret %agg.result) { +define dso_local void @"?inst@C"(%class.C* %this, %class.A* inreg noalias sret(%class.A) %agg.result) { entry: ; CHECK-LABEL: inst@C ; CHECK: str x0, [sp, #8] diff --git a/llvm/test/CodeGen/AArch64/arm64-windows-tailcall.ll b/llvm/test/CodeGen/AArch64/arm64-windows-tailcall.ll index 4198e10a9a13d..9694994386c7c 100644 --- a/llvm/test/CodeGen/AArch64/arm64-windows-tailcall.ll +++ b/llvm/test/CodeGen/AArch64/arm64-windows-tailcall.ll @@ -4,7 +4,7 @@ %class.C = type { [1 x i32] } -define dso_local void @"?bar"(%class.C* inreg noalias sret %agg.result) { +define dso_local void @"?bar"(%class.C* inreg noalias sret(%class.C) %agg.result) { entry: ; CHECK-LABEL: bar ; CHECK: mov x19, x0 diff --git a/llvm/test/CodeGen/AArch64/arm64_32.ll b/llvm/test/CodeGen/AArch64/arm64_32.ll index 4e764a7c37c09..5857156587b61 100644 --- a/llvm/test/CodeGen/AArch64/arm64_32.ll +++ b/llvm/test/CodeGen/AArch64/arm64_32.ll @@ -422,7 +422,7 @@ define void @test_bare_frameaddr(i8** %addr) { ret void } -define void @test_sret_use([8 x i64]* sret %out) { +define void @test_sret_use([8 x i64]* sret([8 x i64]) %out) { ; CHECK-LABEL: test_sret_use: ; CHECK: str xzr, [x8] %addr = getelementptr [8 x i64], [8 x i64]* %out, i32 0, i32 0 @@ -435,7 +435,7 @@ define i64 @test_sret_call() { ; CHECK: mov x8, sp ; CHECK: bl _test_sret_use %arr = alloca [8 x i64] - call void @test_sret_use([8 x i64]* sret %arr) + call void @test_sret_use([8 x i64]* sret([8 x i64]) %arr) %addr = getelementptr [8 x i64], [8 x i64]* %arr, i32 0, i32 0 %val = load i64, i64* %addr diff --git a/llvm/test/CodeGen/AArch64/big-callframe.ll b/llvm/test/CodeGen/AArch64/big-callframe.ll index d5ee233095cae..3ef57d5abc973 100644 --- a/llvm/test/CodeGen/AArch64/big-callframe.ll +++ b/llvm/test/CodeGen/AArch64/big-callframe.ll @@ -6,11 +6,11 @@ ; CHECK: stur {{.*}}, [x29, #{{.*}}] // 8-byte Folded Spill ; CHECK: ldur {{.*}}, [x29, #{{.*}}] // 8-byte Folded Reload target triple = "aarch64--" -declare void @extfunc([4096 x i64]* byval %p) +declare void @extfunc([4096 x i64]* byval([4096 x i64]) %p) define void @func([4096 x i64]* %z) { %lvar = alloca [31 x i8] %v = load volatile [31 x i8], [31 x i8]* %lvar store volatile [31 x i8] %v, [31 x i8]* %lvar - call void @extfunc([4096 x i64]* byval %z) + call void @extfunc([4096 x i64]* byval([4096 x i64]) %z) ret void } diff --git a/llvm/test/CodeGen/AArch64/byval-type.ll b/llvm/test/CodeGen/AArch64/byval-type.ll index 0c2e2dc471dd9..d49ac16f8e155 100644 --- a/llvm/test/CodeGen/AArch64/byval-type.ll +++ b/llvm/test/CodeGen/AArch64/byval-type.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s -define i8 @byval_match(i8* byval(i8) align 1, i8* byval %ptr) { +define i8 @byval_match(i8* byval(i8) align 1, i8* byval(i8) %ptr) { ; CHECK-LABEL: byval_match: ; CHECK: ldrb w0, [sp, #8] %res = load i8, i8* %ptr @@ -14,11 +14,11 @@ define void @caller_match(i8* %p0, i8* %p1) { ; CHECK: ldrb [[P0:w[0-9]+]], [x0] ; CHECK: strb [[P0]], [sp] ; CHECK: bl byval_match - call i8 @byval_match(i8* byval(i8) align 1 %p0, i8* byval %p1) + call i8 @byval_match(i8* byval(i8) align 1 %p0, i8* byval(i8) %p1) ret void } -define i8 @byval_large([3 x i64]* byval([3 x i64]) align 8, i8* byval %ptr) { +define i8 @byval_large([3 x i64]* byval([3 x i64]) align 8, i8* byval(i8) %ptr) { ; CHECK-LABEL: byval_large: ; CHECK: ldrb w0, [sp, #24] %res = load i8, i8* %ptr @@ -32,6 +32,6 @@ define void @caller_large([3 x i64]* %p0, i8* %p1) { ; CHECK: str [[P0HI]], [sp, #16] ; CHECK: str [[P0LO]], [sp] ; CHECK: bl byval_large - call i8 @byval_large([3 x i64]* byval([3 x i64]) align 8 %p0, i8* byval %p1) + call i8 @byval_large([3 x i64]* byval([3 x i64]) align 8 %p0, i8* byval(i8) %p1) ret void } diff --git a/llvm/test/CodeGen/AArch64/cfguard-checks.ll b/llvm/test/CodeGen/AArch64/cfguard-checks.ll index 5ebe1dd13659d..cb31decd57ba9 100644 --- a/llvm/test/CodeGen/AArch64/cfguard-checks.ll +++ b/llvm/test/CodeGen/AArch64/cfguard-checks.ll @@ -36,10 +36,10 @@ entry: ; The call to __guard_check_icall_fptr should come immediately before the call to the target function. ; CHECK-LABEL: func_optnone_cf - ; CHECK: adrp x8, __guard_check_icall_fptr - ; CHECK: add x9, x8, __guard_check_icall_fptr ; CHECK: adrp x8, target_func ; CHECK: add x8, x8, target_func + ; CHECK: adrp x9, __guard_check_icall_fptr + ; CHECK: add x9, x9, __guard_check_icall_fptr ; CHECK: ldr x9, [x9] ; CHECK: mov x15, x8 ; CHECK: blr x9 diff --git a/llvm/test/CodeGen/AArch64/cpus.ll b/llvm/test/CodeGen/AArch64/cpus.ll index 863e1e77e32dc..1c63186c0ee40 100644 --- a/llvm/test/CodeGen/AArch64/cpus.ll +++ b/llvm/test/CodeGen/AArch64/cpus.ll @@ -20,6 +20,7 @@ ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-x1 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-e1 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n1 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n2 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-v1 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m4 2>&1 | FileCheck %s diff --git a/llvm/test/CodeGen/AArch64/elim-dead-mi.mir b/llvm/test/CodeGen/AArch64/elim-dead-mi.mir new file mode 100644 index 0000000000000..1bfd5b44d9c5c --- /dev/null +++ b/llvm/test/CodeGen/AArch64/elim-dead-mi.mir @@ -0,0 +1,61 @@ +# RUN: llc -mtriple=aarch64-arm-none-eabi -o - %s \ +# RUN: -run-pass dead-mi-elimination | FileCheck %s +--- | + @c = internal unnamed_addr global [3 x i8] zeroinitializer, align 4 + @d = common dso_local local_unnamed_addr global i32 0, align 4 + + define dso_local i32 @main() local_unnamed_addr { + %scevgep = getelementptr i8, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @c, i64 0, i64 1), i64 0 + ret i32 0 + } +... +--- +name: main +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64common, preferred-register: '' } + - { id: 2, class: gpr64, preferred-register: '' } + - { id: 3, class: gpr64common, preferred-register: '' } + - { id: 4, class: gpr32, preferred-register: '' } + - { id: 5, class: gpr32all, preferred-register: '' } + - { id: 6, class: gpr64, preferred-register: '' } +body: | + bb.0: + successors: %bb.4(0x30000000), %bb.5(0x50000000) + + %0:gpr64 = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) @c + CBZX killed %0, %bb.4 + B %bb.5 + + bb.1: + successors: %bb.3(0x04000000), %bb.2(0x7c000000) + + %1:gpr64common = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) @c + %2:gpr64 = SUBSXri %1, 2, 0, implicit-def $nzcv + Bcc 0, %bb.3, implicit $nzcv + B %bb.2 + + bb.2: + successors: %bb.1(0x80000000) + %3:gpr64common = ADDXrr %6, %2 + %4:gpr32 = LDRBBui killed %3, 1 :: (load 1 from %ir.scevgep) + %5:gpr32all = COPY %4 + B %bb.1 + + bb.3: + ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp + $x0 = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) @c + ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp + RET_ReallyLR implicit $w0 + + bb.4: + successors: %bb.5(0x80000000) + + bb.5: + successors: %bb.1(0x80000000) + ; CHECK: bb.5 + ; CHECK-NOT: %6:gpr64 = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) @c + %6:gpr64 = MOVaddr target-flags(aarch64-page) @c, target-flags(aarch64-pageoff, aarch64-nc) @c + B %bb.1 +... diff --git a/llvm/test/CodeGen/AArch64/func-argpassing.ll b/llvm/test/CodeGen/AArch64/func-argpassing.ll index 3e6a8bb2c8ce7..000fc7d9ca351 100644 --- a/llvm/test/CodeGen/AArch64/func-argpassing.ll +++ b/llvm/test/CodeGen/AArch64/func-argpassing.ll @@ -32,7 +32,7 @@ define void @add_floats(float %val1, float %val2) { ; byval pointers should be allocated to the stack and copied as if ; with memcpy. -define void @take_struct(%myStruct* byval %structval) { +define void @take_struct(%myStruct* byval(%myStruct) %structval) { ; CHECK-LABEL: take_struct: %addr0 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 2 %addr1 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 0 @@ -52,7 +52,7 @@ define void @take_struct(%myStruct* byval %structval) { } ; %structval should be at sp + 16 -define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) { +define void @check_byval_align(i32* byval(i32) %ignore, %myStruct* byval(%myStruct) align 16 %structval) { ; CHECK-LABEL: check_byval_align: %addr0 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 2 @@ -106,7 +106,7 @@ define [2 x i64] @return_struct() { ; to preserve value semantics) in x8. Strictly this only applies to ; structs larger than 16 bytes, but C semantics can still be provided ; if LLVM does it to %myStruct too. So this is the simplest check -define void @return_large_struct(%myStruct* sret %retval) { +define void @return_large_struct(%myStruct* sret(%myStruct) %retval) { ; CHECK-LABEL: return_large_struct: %addr0 = getelementptr %myStruct, %myStruct* %retval, i64 0, i32 0 %addr1 = getelementptr %myStruct, %myStruct* %retval, i64 0, i32 1 @@ -126,7 +126,7 @@ define void @return_large_struct(%myStruct* sret %retval) { ; available, but it needs two). Also make sure that %stacked doesn't ; sneak into x7 behind. define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45, - i32* %var6, %myStruct* byval %struct, i32* byval %stacked, + i32* %var6, %myStruct* byval(%myStruct) %struct, i32* byval(i32) %stacked, double %notstacked) { ; CHECK-LABEL: struct_on_stack: %addr = getelementptr %myStruct, %myStruct* %struct, i64 0, i32 0 diff --git a/llvm/test/CodeGen/AArch64/func-calls.ll b/llvm/test/CodeGen/AArch64/func-calls.ll index fe48fd308265a..adc9996ef6d14 100644 --- a/llvm/test/CodeGen/AArch64/func-calls.ll +++ b/llvm/test/CodeGen/AArch64/func-calls.ll @@ -43,7 +43,7 @@ define void @simple_args() { declare i32 @return_int() declare double @return_double() declare [2 x i64] @return_smallstruct() -declare void @return_large_struct(%myStruct* sret %retval) +declare void @return_large_struct(%myStruct* sret(%myStruct) %retval) define void @simple_rets() { ; CHECK-LABEL: simple_rets: @@ -65,7 +65,7 @@ define void @simple_rets() { ; CHECK: add x[[VARSMALLSTRUCT:[0-9]+]], {{x[0-9]+}}, :lo12:varsmallstruct ; CHECK: stp x0, x1, [x[[VARSMALLSTRUCT]]] - call void @return_large_struct(%myStruct* sret @varstruct) + call void @return_large_struct(%myStruct* sret(%myStruct) @varstruct) ; CHECK: add x8, {{x[0-9]+}}, {{#?}}:lo12:varstruct ; CHECK: bl return_large_struct @@ -74,7 +74,7 @@ define void @simple_rets() { declare i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45, - i32* %var6, %myStruct* byval %struct, i32 %stacked, + i32* %var6, %myStruct* byval(%myStruct) %struct, i32 %stacked, double %notstacked) declare void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, float %var4, float %var5, float %var6, float %var7, @@ -83,7 +83,7 @@ declare void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, define void @check_stack_args() { ; CHECK-LABEL: check_stack_args: call i32 @struct_on_stack(i8 0, i16 12, i32 42, i64 99, i128 1, - i32* @var32, %myStruct* byval @varstruct, + i32* @var32, %myStruct* byval(%myStruct) @varstruct, i32 999, double 1.0) ; Want to check that the final double is passed in registers and ; that varstruct is passed on the stack. Rather dependent on how a diff --git a/llvm/test/CodeGen/AArch64/large-stack.ll b/llvm/test/CodeGen/AArch64/large-stack.ll index 11027652df92d..60cac6302fd7f 100644 --- a/llvm/test/CodeGen/AArch64/large-stack.ll +++ b/llvm/test/CodeGen/AArch64/large-stack.ll @@ -32,12 +32,13 @@ attributes #0 = { noinline optnone "frame-pointer"="all" } ; CHECK: sub x[[INDEX:[0-9]+]], x[[FRAME]], #8 ; CHECK-NEXT: str x0, [x[[INDEX]]] ; CHECK-NEXT: ldr x[[VAL1:[0-9]+]], [x[[INDEX]]] -; CHECK-NEXT: mov x[[VAL2:[0-9]+]], #8 ; CHECK-NEXT: add x[[VAL3:[0-9]+]], sp, #8 +; CHECK-NEXT: mov x[[VAL2:[0-9]+]], #8 ; CHECK-NEXT: madd x[[VAL1]], x[[VAL1]], x[[VAL2]], x[[VAL3]] ; CHECK-NEXT: mov x[[TMP1:[0-9]+]], #1 ; CHECK-NEXT: str x[[TMP1]], [x[[VAL1]]] ; CHECK-NEXT: ldr x[[INDEX]], [x[[INDEX]]] +; CHECK-NEXT: add x[[VAL3:[0-9]+]], sp, #8 ; CHECK-NEXT: mov x[[VAL4:[0-9]+]], #8 ; CHECK-NEXT: madd x[[INDEX]], x[[INDEX]], x[[VAL4]], x[[VAL3]] ; CHECK-NEXT: ldr x1, [x[[INDEX]] diff --git a/llvm/test/CodeGen/AArch64/minmax.ll b/llvm/test/CodeGen/AArch64/minmax.ll index df4912ca1f7ab..5e99121cac2a9 100644 --- a/llvm/test/CodeGen/AArch64/minmax.ll +++ b/llvm/test/CodeGen/AArch64/minmax.ll @@ -1,73 +1,92 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s -; CHECK-LABEL: t1 -; CHECK: smax define <4 x i32> @t1(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: t1: +; CHECK: // %bb.0: +; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s +; CHECK-NEXT: ret %t1 = icmp sgt <4 x i32> %a, %b %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b ret <4 x i32> %t2 } -; CHECK-LABEL: t2 -; CHECK: smin define <4 x i32> @t2(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: t2: +; CHECK: // %bb.0: +; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s +; CHECK-NEXT: ret %t1 = icmp slt <4 x i32> %a, %b %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b ret <4 x i32> %t2 } -; CHECK-LABEL: t3 -; CHECK: umax define <4 x i32> @t3(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: t3: +; CHECK: // %bb.0: +; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s +; CHECK-NEXT: ret %t1 = icmp ugt <4 x i32> %a, %b %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b ret <4 x i32> %t2 } -; CHECK-LABEL: t4 -; CHECK: umin define <8 x i8> @t4(<8 x i8> %a, <8 x i8> %b) { +; CHECK-LABEL: t4: +; CHECK: // %bb.0: +; CHECK-NEXT: umin v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %t1 = icmp ult <8 x i8> %a, %b %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b ret <8 x i8> %t2 } -; CHECK-LABEL: t5 -; CHECK: smin define <4 x i16> @t5(<4 x i16> %a, <4 x i16> %b) { +; CHECK-LABEL: t5: +; CHECK: // %bb.0: +; CHECK-NEXT: smin v0.4h, v1.4h, v0.4h +; CHECK-NEXT: ret %t1 = icmp sgt <4 x i16> %b, %a %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b ret <4 x i16> %t2 } -; CHECK-LABEL: t6 -; CHECK: smax define <2 x i32> @t6(<2 x i32> %a, <2 x i32> %b) { +; CHECK-LABEL: t6: +; CHECK: // %bb.0: +; CHECK-NEXT: smax v0.2s, v1.2s, v0.2s +; CHECK-NEXT: ret %t1 = icmp slt <2 x i32> %b, %a %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b ret <2 x i32> %t2 } -; CHECK-LABEL: t7 -; CHECK: umin define <16 x i8> @t7(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: t7: +; CHECK: // %bb.0: +; CHECK-NEXT: umin v0.16b, v1.16b, v0.16b +; CHECK-NEXT: ret %t1 = icmp ugt <16 x i8> %b, %a %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b ret <16 x i8> %t2 } -; CHECK-LABEL: t8 -; CHECK: umax define <8 x i16> @t8(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: t8: +; CHECK: // %bb.0: +; CHECK-NEXT: umax v0.8h, v1.8h, v0.8h +; CHECK-NEXT: ret %t1 = icmp ult <8 x i16> %b, %a %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b ret <8 x i16> %t2 } -; CHECK-LABEL: t9 -; CHECK: umin -; CHECK: smax define <4 x i32> @t9(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { +; CHECK-LABEL: t9: +; CHECK: // %bb.0: +; CHECK-NEXT: umin v0.4s, v1.4s, v0.4s +; CHECK-NEXT: smax v0.4s, v0.4s, v2.4s +; CHECK-NEXT: ret %t1 = icmp ugt <4 x i32> %b, %a %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b %t3 = icmp sge <4 x i32> %t2, %c @@ -75,33 +94,78 @@ define <4 x i32> @t9(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { ret <4 x i32> %t4 } -; CHECK-LABEL: t10 -; CHECK: smax -; CHECK: smax define <8 x i32> @t10(<8 x i32> %a, <8 x i32> %b) { +; CHECK-LABEL: t10: +; CHECK: // %bb.0: +; CHECK-NEXT: smax v0.4s, v0.4s, v2.4s +; CHECK-NEXT: smax v1.4s, v1.4s, v3.4s +; CHECK-NEXT: ret %t1 = icmp sgt <8 x i32> %a, %b %t2 = select <8 x i1> %t1, <8 x i32> %a, <8 x i32> %b ret <8 x i32> %t2 } -; CHECK-LABEL: t11 -; CHECK: smin -; CHECK: smin -; CHECK: smin -; CHECK: smin define <16 x i32> @t11(<16 x i32> %a, <16 x i32> %b) { +; CHECK-LABEL: t11: +; CHECK: // %bb.0: +; CHECK-NEXT: smin v0.4s, v0.4s, v4.4s +; CHECK-NEXT: smin v1.4s, v1.4s, v5.4s +; CHECK-NEXT: smin v2.4s, v2.4s, v6.4s +; CHECK-NEXT: smin v3.4s, v3.4s, v7.4s +; CHECK-NEXT: ret %t1 = icmp sle <16 x i32> %a, %b %t2 = select <16 x i1> %t1, <16 x i32> %a, <16 x i32> %b ret <16 x i32> %t2 } -; CHECK-LABEL: t12 -; CHECK-NOT: umin ; The icmp is used by two instructions, so don't produce a umin node. define <16 x i8> @t12(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: t12: +; CHECK: // %bb.0: +; CHECK-NEXT: cmhi v2.16b, v1.16b, v0.16b +; CHECK-NEXT: movi v3.16b, #1 +; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b +; CHECK-NEXT: and v1.16b, v2.16b, v3.16b +; CHECK-NEXT: add v0.16b, v1.16b, v0.16b +; CHECK-NEXT: ret %t1 = icmp ugt <16 x i8> %b, %a %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b %t3 = zext <16 x i1> %t1 to <16 x i8> %t4 = add <16 x i8> %t3, %t2 ret <16 x i8> %t4 } + +define <1 x i64> @t13(<1 x i64> %a, <1 x i64> %b) { +; CHECK-LABEL: t13: +; CHECK: // %bb.0: +; CHECK-NEXT: cmhi d2, d1, d0 +; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b +; CHECK-NEXT: ret + %t1 = icmp ult <1 x i64> %a, %b + %t2 = select <1 x i1> %t1, <1 x i64> %a, <1 x i64> %b + ret <1 x i64> %t2 +} + +define <2 x i64> @t14(<2 x i64> %a, <2 x i64> %b) { +; CHECK-LABEL: t14: +; CHECK: // %bb.0: +; CHECK-NEXT: cmhi v2.2d, v0.2d, v1.2d +; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b +; CHECK-NEXT: ret + %t1 = icmp ugt <2 x i64> %a, %b + %t2 = select <2 x i1> %t1, <2 x i64> %a, <2 x i64> %b + ret <2 x i64> %t2 +} + +define <4 x i64> @t15(<4 x i64> %a, <4 x i64> %b) { +; CHECK-LABEL: t15: +; CHECK: // %bb.0: +; CHECK-NEXT: cmhs v4.2d, v3.2d, v1.2d +; CHECK-NEXT: cmhs v5.2d, v2.2d, v0.2d +; CHECK-NEXT: bif v0.16b, v2.16b, v5.16b +; CHECK-NEXT: bif v1.16b, v3.16b, v4.16b +; CHECK-NEXT: ret + %t1 = icmp ule <4 x i64> %a, %b + %t2 = select <4 x i1> %t1, <4 x i64> %a, <4 x i64> %b + ret <4 x i64> %t2 +} diff --git a/llvm/test/CodeGen/AArch64/neg-abs.ll b/llvm/test/CodeGen/AArch64/neg-abs.ll index 3dcb04a8e35f6..0ee39f516f76b 100644 --- a/llvm/test/CodeGen/AArch64/neg-abs.ll +++ b/llvm/test/CodeGen/AArch64/neg-abs.ll @@ -7,9 +7,9 @@ declare i64 @llvm.abs.i64(i64, i1 immarg) define i64@neg_abs(i64 %x) { ; CHECK-LABEL: neg_abs: ; CHECK: // %bb.0: -; CHECK-NEXT: cmp x0, #0 // =0 -; CHECK-NEXT: cneg x8, x0, mi -; CHECK-NEXT: neg x0, x8 +; CHECK-NEXT: asr x8, x0, #63 +; CHECK-NEXT: eor x9, x0, x8 +; CHECK-NEXT: sub x0, x8, x9 ; CHECK-NEXT: ret %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) %neg = sub nsw i64 0, %abs diff --git a/llvm/test/CodeGen/AArch64/neon-dot-product.ll b/llvm/test/CodeGen/AArch64/neon-dot-product.ll index 67435546f9717..2f5ec6d48be6d 100644 --- a/llvm/test/CodeGen/AArch64/neon-dot-product.ll +++ b/llvm/test/CodeGen/AArch64/neon-dot-product.ll @@ -3,6 +3,7 @@ ; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=cortex-a65ae < %s | FileCheck %s ; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-e1 < %s | FileCheck %s ; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-n1 < %s | FileCheck %s +; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-n2 < %s | FileCheck %s declare <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>) declare <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/AArch64/neon-fpextend_f16.ll b/llvm/test/CodeGen/AArch64/neon-fpextend_f16.ll new file mode 100644 index 0000000000000..b78486770ddaf --- /dev/null +++ b/llvm/test/CodeGen/AArch64/neon-fpextend_f16.ll @@ -0,0 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s + +; This is testing that we can scalarize the v1f16 input to fp_extend even +; though the v1f64 result is legal. + +define <1 x double> @fpext_v1f16_v1f64(<1 x half>* %a) { +; CHECK-LABEL: fpext_v1f16_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr h0, [x0] +; CHECK-NEXT: fcvt d0, h0 +; CHECK-NEXT: ret + %b = load <1 x half>, <1 x half>* %a + %c = fpext <1 x half> %b to <1 x double> + ret <1 x double> %c +} + +define <1 x double> @strict_fpext_v1f32_v1f64(<1 x half> %x) #0 { +; CHECK-LABEL: strict_fpext_v1f32_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvt d0, h0 +; CHECK-NEXT: ret + %val = call <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f16(<1 x half> %x, metadata !"fpexcept.strict") strictfp + ret <1 x double> %val +} +declare <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f16(<1 x half>, metadata) diff --git a/llvm/test/CodeGen/AArch64/remat.ll b/llvm/test/CodeGen/AArch64/remat.ll index 90ad2508fe170..bd2786f66e413 100644 --- a/llvm/test/CodeGen/AArch64/remat.ll +++ b/llvm/test/CodeGen/AArch64/remat.ll @@ -13,6 +13,7 @@ ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-x1 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=neoverse-e1 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=neoverse-n1 -o - %s | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=neoverse-n2 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m3 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m4 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m5 -o - %s | FileCheck %s diff --git a/llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll b/llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll index 9819f64a9546a..da35684a09a6d 100644 --- a/llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll +++ b/llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll @@ -171,9 +171,9 @@ right: %struct2 = type { i64, i64, i64 } -declare void @consume_attributes(i32, i8* nest, i32, %struct2* byval) +declare void @consume_attributes(i32, i8* nest, i32, %struct2* byval(%struct2)) -define void @test_attributes(%struct2* byval %s) gc "statepoint-example" { +define void @test_attributes(%struct2* byval(%struct2) %s) gc "statepoint-example" { ; CHECK-LABEL: test_attributes: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: sub sp, sp, #32 // =32 @@ -192,7 +192,7 @@ define void @test_attributes(%struct2* byval %s) gc "statepoint-example" { entry: ; Check that arguments with attributes are lowered correctly. ; We call a function that has a nest argument and a byval argument. - %statepoint_token = call token (i64, i32, void (i32, i8*, i32, %struct2*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32p0i8i32p0s_struct2sf(i64 0, i32 0, void (i32, i8*, i32, %struct2*)* @consume_attributes, i32 4, i32 0, i32 42, i8* nest null, i32 17, %struct2* byval %s, i32 0, i32 0) + %statepoint_token = call token (i64, i32, void (i32, i8*, i32, %struct2*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32p0i8i32p0s_struct2sf(i64 0, i32 0, void (i32, i8*, i32, %struct2*)* @consume_attributes, i32 4, i32 0, i32 42, i8* nest null, i32 17, %struct2* byval(%struct2) %s, i32 0, i32 0) ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-gep.ll b/llvm/test/CodeGen/AArch64/sve-gep.ll index 8f68a38e2cd20..ffde9289a55df 100644 --- a/llvm/test/CodeGen/AArch64/sve-gep.ll +++ b/llvm/test/CodeGen/AArch64/sve-gep.ll @@ -105,11 +105,9 @@ define *> @scalable_of_scalable_1( insertelement ( undef, i64 1, i32 0), zeroinitializer, zeroinitializer %d = getelementptr , * %base, %idx @@ -120,10 +118,8 @@ define *> @scalable_of_scalable_2( insertelement ( undef, i64 1, i32 0), zeroinitializer, zeroinitializer %d = getelementptr , *> %base, %idx diff --git a/llvm/test/CodeGen/AArch64/sve-masked-scatter-legalise.ll b/llvm/test/CodeGen/AArch64/sve-masked-scatter-legalise.ll new file mode 100644 index 0000000000000..c3746a61d8754 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-masked-scatter-legalise.ll @@ -0,0 +1,59 @@ +; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s + +; Tests that exercise various type legalisation scenarios for ISD::MSCATTER. + +; Code generate the scenario where the offset vector type is illegal. +define void @masked_scatter_nxv16i8( %data, i8* %base, %offsets, %mask) { +; CHECK-LABEL: masked_scatter_nxv16i8: +; CHECK-DAG: st1b { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw] +; CHECK-DAG: st1b { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw] +; CHECK-DAG: st1b { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw] +; CHECK-DAG: st1b { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw] +; CHECK: ret + %ptrs = getelementptr i8, i8* %base, %offsets + call void @llvm.masked.scatter.nxv16i8( %data, %ptrs, i32 1, %mask) + ret void +} + +define void @masked_scatter_nxv8i16( %data, i16* %base, %offsets, %mask) { +; CHECK-LABEL: masked_scatter_nxv8i16 +; CHECK-DAG: st1h { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #1] +; CHECK-DAG: st1h { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #1] +; CHECK: ret + %ptrs = getelementptr i16, i16* %base, %offsets + call void @llvm.masked.scatter.nxv8i16( %data, %ptrs, i32 1, %mask) + ret void +} + +define void @masked_scatter_nxv8f32( %data, float* %base, %indexes, %masks) { +; CHECK-LABEL: masked_scatter_nxv8f32 +; CHECK-DAG: st1w { z0.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, uxtw #2] +; CHECK-DAG: st1w { z1.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, uxtw #2] + %ext = zext %indexes to + %ptrs = getelementptr float, float* %base, %ext + call void @llvm.masked.scatter.nxv8f32( %data, %ptrs, i32 0, %masks) + ret void +} + +; Code generate the worst case scenario when all vector types are illegal. +define void @masked_scatter_nxv32i32( %data, i32* %base, %offsets, %mask) { +; CHECK-LABEL: masked_scatter_nxv32i32: +; CHECK-NOT: unpkhi +; CHECK-DAG: st1w { z0.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2] +; CHECK-DAG: st1w { z1.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2] +; CHECK-DAG: st1w { z2.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2] +; CHECK-DAG: st1w { z3.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2] +; CHECK-DAG: st1w { z4.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2] +; CHECK-DAG: st1w { z5.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2] +; CHECK-DAG: st1w { z6.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2] +; CHECK-DAG: st1w { z7.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2] +; CHECK: ret + %ptrs = getelementptr i32, i32* %base, %offsets + call void @llvm.masked.scatter.nxv32i32( %data, %ptrs, i32 4, %mask) + ret void +} + +declare void @llvm.masked.scatter.nxv16i8(, , i32, ) +declare void @llvm.masked.scatter.nxv8i16(, , i32, ) +declare void @llvm.masked.scatter.nxv8f32(, , i32, ) +declare void @llvm.masked.scatter.nxv32i32(, , i32, ) diff --git a/llvm/test/CodeGen/AArch64/swifterror.ll b/llvm/test/CodeGen/AArch64/swifterror.ll index e219ef770f934..d6f4e9518c917 100644 --- a/llvm/test/CodeGen/AArch64/swifterror.ll +++ b/llvm/test/CodeGen/AArch64/swifterror.ll @@ -243,7 +243,7 @@ bb_end: ; "foo_sret" is a function that takes a swifterror parameter, it also has a sret ; parameter. -define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { +define void @foo_sret(%struct.S* sret(%struct.S) %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { ; CHECK-APPLE-LABEL: foo_sret: ; CHECK-APPLE: mov [[SRET:x[0-9]+]], x8 ; CHECK-APPLE: mov w0, #16 @@ -309,7 +309,7 @@ entry: %s = alloca %struct.S, align 8 %error_ptr_ref = alloca swifterror %swift_error* store %swift_error* null, %swift_error** %error_ptr_ref - call void @foo_sret(%struct.S* sret %s, i32 1, %swift_error** swifterror %error_ptr_ref) + call void @foo_sret(%struct.S* sret(%struct.S) %s, i32 1, %swift_error** swifterror %error_ptr_ref) %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null %tmp = bitcast %swift_error* %error_from_foo to i8* diff --git a/llvm/test/CodeGen/AArch64/swiftself.ll b/llvm/test/CodeGen/AArch64/swiftself.ll index a13fbb8d5a60f..b9c8ab2172dcb 100644 --- a/llvm/test/CodeGen/AArch64/swiftself.ll +++ b/llvm/test/CodeGen/AArch64/swiftself.ll @@ -86,7 +86,7 @@ declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself) ; OPTARM64_32: bl {{_?}}thisreturn_attribute ; OPTARM64_32: str w0, {{\[}}[[CSREG]] ; OPTARM64_32: ret -define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret, i8** noalias nocapture readonly swiftself) { +define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret(i8*), i8** noalias nocapture readonly swiftself) { entry: %2 = load i8*, i8** %1, align 8 %3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2) diff --git a/llvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll b/llvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll index b60958b5a25df..f1eb8d82b54f6 100644 --- a/llvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll +++ b/llvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll @@ -4,13 +4,13 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" ; Check that we don't try to tail-call with a non-forwarded sret parameter. -declare void @test_explicit_sret(i1024* sret) #0 +declare void @test_explicit_sret(i1024* sret(i1024)) #0 ; This is the only OK case, where we forward the explicit sret pointer. ; CHECK-LABEL: _test_tailcall_explicit_sret: ; CHECK-NEXT: b _test_explicit_sret -define void @test_tailcall_explicit_sret(i1024* sret %arg) #0 { +define void @test_tailcall_explicit_sret(i1024* sret(i1024) %arg) #0 { tail call void @test_explicit_sret(i1024* %arg) ret void } @@ -19,7 +19,7 @@ define void @test_tailcall_explicit_sret(i1024* sret %arg) #0 { ; CHECK-NOT: mov x8 ; CHECK: bl _test_explicit_sret ; CHECK: ret -define void @test_call_explicit_sret(i1024* sret %arg) #0 { +define void @test_call_explicit_sret(i1024* sret(i1024) %arg) #0 { call void @test_explicit_sret(i1024* %arg) ret void } @@ -82,7 +82,7 @@ define i1024 @test_tailcall_explicit_sret_alloca_returned() #0 { ; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] ; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret -define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret %arg, void (i1024*)* %f) #0 { +define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret(i1024) %arg, void (i1024*)* %f) #0 { %l = alloca i1024, align 8 tail call void %f(i1024* %l) %r = load i1024, i1024* %l, align 8 @@ -97,7 +97,7 @@ define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret %arg, v ; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] ; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret -define void @test_indirect_tailcall_explicit_sret_(i1024* sret %arg, i1024 ()* %f) #0 { +define void @test_indirect_tailcall_explicit_sret_(i1024* sret(i1024) %arg, i1024 ()* %f) #0 { %ret = tail call i1024 %f() store i1024 %ret, i1024* %arg, align 8 ret void diff --git a/llvm/test/CodeGen/AArch64/tailcall-string-rvo.ll b/llvm/test/CodeGen/AArch64/tailcall-string-rvo.ll index ac9ce4d10df94..49ac1681e67ae 100644 --- a/llvm/test/CodeGen/AArch64/tailcall-string-rvo.ll +++ b/llvm/test/CodeGen/AArch64/tailcall-string-rvo.ll @@ -17,15 +17,15 @@ target triple = "aarch64-linux-gnu" %"struct.__gnu_cxx::__vstring_utility, std::allocator >::_Alloc_hider.7.38.69" = type { i8* } %union.anon.8.39.70 = type { i64, [8 x i8] } -declare void @TestBaz(%class.basic_string.11.42.73* noalias sret %arg) +declare void @TestBaz(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) -define void @TestBar(%class.basic_string.11.42.73* noalias sret %arg) { +define void @TestBar(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) { bb: - call void @TestBaz(%class.basic_string.11.42.73* noalias sret %arg) + call void @TestBaz(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) ret void } -define void @TestFoo(%class.basic_string.11.42.73* noalias sret %arg) { +define void @TestFoo(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) { ; CHECK-LABEL: TestFoo: ; CHECK: b TestBar bb: @@ -38,7 +38,7 @@ bb: store i64 13, i64* %tmp3, align 8 %tmp4 = getelementptr inbounds %class.basic_string.11.42.73, %class.basic_string.11.42.73* %arg, i64 0, i32 0, i32 0, i32 2, i32 1, i64 5 store i8 0, i8* %tmp4, align 1 - tail call void @TestBar(%class.basic_string.11.42.73* noalias sret %arg) + tail call void @TestBar(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) ret void } diff --git a/llvm/test/CodeGen/AArch64/win64-jumptable.ll b/llvm/test/CodeGen/AArch64/win64-jumptable.ll index 1071a736cffd7..7c4efa22f609f 100644 --- a/llvm/test/CodeGen/AArch64/win64-jumptable.ll +++ b/llvm/test/CodeGen/AArch64/win64-jumptable.ll @@ -44,8 +44,6 @@ declare void @g(i32, i32) ; CHECK: .word .LBB0_3-.Ltmp0 ; CHECK: .word .LBB0_4-.Ltmp0 ; CHECK: .word .LBB0_5-.Ltmp0 -; CHECK: .seh_handlerdata -; CHECK: .text ; CHECK: .seh_endproc ; Check that we can emit an object file with correct unwind info. diff --git a/llvm/test/CodeGen/AArch64/wineh1.mir b/llvm/test/CodeGen/AArch64/wineh1.mir index 2f73a5291ddd0..d82e4bce7d194 100644 --- a/llvm/test/CodeGen/AArch64/wineh1.mir +++ b/llvm/test/CodeGen/AArch64/wineh1.mir @@ -73,8 +73,6 @@ # ASM: .seh_endepilogue # ASM: .seh_endfunclet -# ASM: .seh_handlerdata -# ASM: .text # ASM: .seh_endproc ... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll index fa569b941c935..b340be5ac2c89 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll @@ -1141,7 +1141,7 @@ define {i8, i32} @struct_i8_i32_func_void() #0 { ret { i8, i32 } %val } -define void @void_func_sret_struct_i8_i32({ i8, i32 } addrspace(5)* sret %arg0) #0 { +define void @void_func_sret_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }) %arg0) #0 { ; CHECK-LABEL: name: void_func_sret_struct_i8_i32 ; CHECK: bb.1 (%ir-block.0): ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 @@ -1302,7 +1302,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 { ret { <3 x float>, i32 } %insert.4 } -define void @void_func_sret_max_known_zero_bits(i8 addrspace(5)* sret %arg0) #0 { +define void @void_func_sret_max_known_zero_bits(i8 addrspace(5)* sret(i8) %arg0) #0 { ; CHECK-LABEL: name: void_func_sret_max_known_zero_bits ; CHECK: bb.1 (%ir-block.0): ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll index f244a840476da..d215dc05c959b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -amdgpu-fixed-function-abi -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0 +declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }), { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(i32) #0 { ; GCN-LABEL: name: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll index 3cd6235cf5d61..76048be98a874 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll @@ -67,8 +67,8 @@ declare hidden void @external_void_func_v32i32_i8_i8_i16(<32 x i32>, i8, i8, i16 ; Structs declare hidden void @external_void_func_struct_i8_i32({ i8, i32 }) #0 -declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval) #0 -declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0 +declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 +declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }), { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 declare hidden void @external_void_func_v2i8(<2 x i8>) #0 declare hidden void @external_void_func_v3i8(<3 x i8>) #0 @@ -76,7 +76,7 @@ declare hidden void @external_void_func_v4i8(<4 x i8>) #0 declare hidden void @external_void_func_v8i8(<8 x i8>) #0 declare hidden void @external_void_func_v16i8(<16 x i8>) #0 -declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval align 16) #0 +declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval(double) align 16) #0 declare hidden void @stack_passed_f64_arg(<32 x i32>, double) #0 declare hidden void @external_void_func_12xv3i32(<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>) #0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll index 96d0c9d1d4a80..3bf46196fd586 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll @@ -1683,7 +1683,7 @@ define void @void_func_struct_i8_i32({ i8, i32 } %arg0) #0 { ret void } -define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0) #0 { +define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 { ; CHECK-LABEL: name: void_func_byval_struct_i8_i32 ; CHECK: bb.1 (%ir-block.0): ; CHECK: liveins: $sgpr30_sgpr31 @@ -1706,7 +1706,7 @@ define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0 ret void } -define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %arg0, { i8, i32 } addrspace(5)* byval %arg1, i32 %arg2) #0 { +define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg1, i32 %arg2) #0 { ; CHECK-LABEL: name: void_func_byval_struct_i8_i32_x2 ; CHECK: bb.1 (%ir-block.0): ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 @@ -1743,7 +1743,7 @@ define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %a ret void } -define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval %arg0, i64 addrspace(5)* byval %arg1) #0 { +define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval(i32) %arg0, i64 addrspace(5)* byval(i64) %arg1) #0 { ; CHECK-LABEL: name: void_func_byval_i32_byval_i64 ; CHECK: bb.1 (%ir-block.0): ; CHECK: liveins: $sgpr30_sgpr31 diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll b/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll index f50a07d9afeff..c6a065e1e65fd 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll @@ -1,16 +1,161 @@ -; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s -; RUN: llc -global-isel -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s - -; GCN-LABEL: {{^}}gfx_callable_amdpal: -; GCN: .amdgpu_pal_metadata -; GCN-NEXT: --- -; GCN-NEXT: amdpal.pipelines: +; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SDAG -enable-var-scope %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SDAG -enable-var-scope %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SDAG -enable-var-scope %s +; RUN: llc -global-isel -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GISEL -enable-var-scope %s + +declare float @extern_func(float) #0 +declare float @extern_func_many_args(<64 x float>) #0 + +@funcptr = external hidden unnamed_addr addrspace(4) constant void()*, align 4 + +define amdgpu_gfx float @no_stack(float %arg0) #0 { + %add = fadd float %arg0, 1.0 + ret float %add +} + +define amdgpu_gfx float @simple_stack(float %arg0) #0 { + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, float addrspace(5)* %stack + %val = load volatile float, float addrspace(5)* %stack + %add = fadd float %arg0, %val + ret float %add +} + +define amdgpu_gfx float @multiple_stack(float %arg0) #0 { + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, float addrspace(5)* %stack + %val = load volatile float, float addrspace(5)* %stack + %add = fadd float %arg0, %val + %stack2 = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, float addrspace(5)* %stack2 + %val2 = load volatile float, float addrspace(5)* %stack2 + %add2 = fadd float %add, %val2 + ret float %add2 +} + +define amdgpu_gfx float @dynamic_stack(float %arg0) #0 { +bb0: + %cmp = fcmp ogt float %arg0, 0.0 + br i1 %cmp, label %bb1, label %bb2 + +bb1: + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, float addrspace(5)* %stack + %val = load volatile float, float addrspace(5)* %stack + %add = fadd float %arg0, %val + br label %bb2 + +bb2: + %res = phi float [ 0.0, %bb0 ], [ %add, %bb1 ] + ret float %res +} + +define amdgpu_gfx float @dynamic_stack_loop(float %arg0) #0 { +bb0: + br label %bb1 + +bb1: + %ctr = phi i32 [ 0, %bb0 ], [ %newctr, %bb1 ] + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, float addrspace(5)* %stack + %val = load volatile float, float addrspace(5)* %stack + %add = fadd float %arg0, %val + %cmp = icmp sgt i32 %ctr, 0 + %newctr = sub i32 %ctr, 1 + br i1 %cmp, label %bb1, label %bb2 + +bb2: + ret float %add +} + +define amdgpu_gfx float @no_stack_call(float %arg0) #0 { + %res = call amdgpu_gfx float @simple_stack(float %arg0) + ret float %res +} + +define amdgpu_gfx float @simple_stack_call(float %arg0) #0 { + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, float addrspace(5)* %stack + %val = load volatile float, float addrspace(5)* %stack + %res = call amdgpu_gfx float @simple_stack(float %arg0) + %add = fadd float %res, %val + ret float %add +} + +define amdgpu_gfx float @no_stack_extern_call(float %arg0) #0 { + %res = call amdgpu_gfx float @extern_func(float %arg0) + ret float %res +} + +define amdgpu_gfx float @simple_stack_extern_call(float %arg0) #0 { + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, float addrspace(5)* %stack + %val = load volatile float, float addrspace(5)* %stack + %res = call amdgpu_gfx float @extern_func(float %arg0) + %add = fadd float %res, %val + ret float %add +} + +define amdgpu_gfx float @no_stack_extern_call_many_args(<64 x float> %arg0) #0 { + %res = call amdgpu_gfx float @extern_func_many_args(<64 x float> %arg0) + ret float %res +} + +define amdgpu_gfx float @no_stack_indirect_call(float %arg0) #0 { + %fptr = load void()*, void()* addrspace(4)* @funcptr + call amdgpu_gfx void %fptr() + ret float %arg0 +} + +define amdgpu_gfx float @simple_stack_indirect_call(float %arg0) #0 { + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, float addrspace(5)* %stack + %val = load volatile float, float addrspace(5)* %stack + %fptr = load void()*, void()* addrspace(4)* @funcptr + call amdgpu_gfx void %fptr() + %add = fadd float %arg0, %val + ret float %add +} + +define amdgpu_gfx float @simple_stack_recurse(float %arg0) #0 { + %stack = alloca float, i32 4, align 4, addrspace(5) + store volatile float 2.0, float addrspace(5)* %stack + %val = load volatile float, float addrspace(5)* %stack + %res = call amdgpu_gfx float @simple_stack_recurse(float %arg0) + %add = fadd float %res, %val + ret float %add +} + +attributes #0 = { nounwind } + +; GCN: amdpal.pipelines: ; GCN-NEXT: - .registers: {} +; GCN-NEXT: .shader_functions: +; GCN-NEXT: dynamic_stack: +; GCN-NEXT: .stack_frame_size_in_bytes: 0x10{{$}} +; GCN-NEXT: dynamic_stack_loop: +; GCN-NEXT: .stack_frame_size_in_bytes: 0x10{{$}} +; GCN-NEXT: multiple_stack: +; GCN-NEXT: .stack_frame_size_in_bytes: 0x24{{$}} +; GCN-NEXT: no_stack: +; GCN-NEXT: .stack_frame_size_in_bytes: 0{{$}} +; GCN-NEXT: no_stack_call: +; GCN-NEXT: .stack_frame_size_in_bytes: 0{{$}} +; GCN-NEXT: no_stack_extern_call: +; GCN-NEXT: .stack_frame_size_in_bytes: 0x10{{$}} +; GCN-NEXT: no_stack_extern_call_many_args: +; SDAG-NEXT: .stack_frame_size_in_bytes: 0x90{{$}} +; GISEL-NEXT: .stack_frame_size_in_bytes: 0xd0{{$}} +; GCN-NEXT: no_stack_indirect_call: +; GCN-NEXT: .stack_frame_size_in_bytes: 0x10{{$}} +; GCN-NEXT: simple_stack: +; GCN-NEXT: .stack_frame_size_in_bytes: 0x14{{$}} +; GCN-NEXT: simple_stack_call: +; GCN-NEXT: .stack_frame_size_in_bytes: 0x20{{$}} +; GCN-NEXT: simple_stack_extern_call: +; GCN-NEXT: .stack_frame_size_in_bytes: 0x20{{$}} +; GCN-NEXT: simple_stack_indirect_call: +; GCN-NEXT: .stack_frame_size_in_bytes: 0x20{{$}} +; GCN-NEXT: simple_stack_recurse: +; GCN-NEXT: .stack_frame_size_in_bytes: 0x20{{$}} ; GCN-NEXT: ... -; GCN-NEXT: .end_amdgpu_pal_metadata -define amdgpu_gfx half @gfx_callable_amdpal(half %arg0) { - %add = fadd half %arg0, 1.0 - ret half %add -} diff --git a/llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll b/llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll index 91eb7d0add483..cf6fb6f1adeac 100644 --- a/llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll +++ b/llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll @@ -23,7 +23,7 @@ ; GCN: [[BB1]] ; GCN: s_or_b64 exec, exec -define hidden void @void_func_byval_struct_use_outside_entry_block(%struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg1, i1 %cond) #1 { +define hidden void @void_func_byval_struct_use_outside_entry_block(%struct.ByValStruct addrspace(5)* byval(%struct.ByValStruct) noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval(%struct.ByValStruct) noalias nocapture align 4 %arg1, i1 %cond) #1 { entry: br i1 %cond, label %bb0, label %bb1 diff --git a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll index 20d398c772a31..153e15dd65321 100644 --- a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll +++ b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll @@ -52,8 +52,8 @@ declare hidden i32 @external_i32_func_i32(i32) #0 ; Structs declare hidden void @external_void_func_struct_i8_i32({ i8, i32 }) #0 -declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval) #0 -declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0 +declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 +declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }), { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 declare hidden void @external_void_func_v16i8(<16 x i8>) #0 @@ -681,7 +681,7 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0 %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %val, i32 0, i32 1 store i8 3, i8 addrspace(5)* %gep0 store i32 8, i32 addrspace(5)* %gep1 - call void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %val) + call void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %val) ret void } @@ -713,7 +713,7 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval %in.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 1 store i8 3, i8 addrspace(5)* %in.gep0 store i32 8, i32 addrspace(5)* %in.gep1 - call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %out.val, { i8, i32 } addrspace(5)* %in.val) + call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %out.val, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %in.val) %out.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 0 %out.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 1 %out.val0 = load i8, i8 addrspace(5)* %out.gep0 @@ -756,7 +756,7 @@ entry: define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 { entry: %alloca = alloca double, align 8, addrspace(5) - tail call void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval align 16 %alloca) + tail call void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval(double) align 16 %alloca) ret void } @@ -902,7 +902,7 @@ entry: ret void } -declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval align 16) #0 +declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval(double) align 16) #0 declare hidden void @stack_passed_f64_arg(<32 x i32>, double) #0 declare hidden void @external_void_func_12xv3i32(<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>) #0 diff --git a/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll b/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll index 20d50200e3a2f..ed6140228fc66 100644 --- a/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll +++ b/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll @@ -479,7 +479,7 @@ define void @no_unused_non_csr_sgpr_for_fp_no_scratch_vgpr() #1 { ; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC1]] ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_setpc_b64 -define void @scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval align 4 %arg) #1 { +define void @scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval([4096 x i8]) align 4 %arg) #1 { %alloca = alloca i32, addrspace(5) store volatile i32 0, i32 addrspace(5)* %alloca @@ -608,7 +608,7 @@ define void @callee_need_to_spill_fp_to_memory_full_reserved_vgpr() #3 { ; FLATSCR: s_add_u32 [[SOFF:s[0-9]+]], s33, 0x1004 ; FLATSCR: v_mov_b32_e32 v0, 0 ; FLATSCR: scratch_store_dword off, v0, [[SOFF]] -define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval align 4 %arg) #3 { +define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval([4096 x i8]) align 4 %arg) #3 { %alloca = alloca i32, addrspace(5) store volatile i32 0, i32 addrspace(5)* %alloca diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll index 18fe484f4e3a6..44cc53e2ce4ce 100644 --- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll +++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll @@ -560,7 +560,7 @@ define void @too_many_args_use_workitem_id_x_byval( i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, - i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval %arg32) #1 { + i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval(i32) %arg32) #1 { %val = call i32 @llvm.amdgcn.workitem.id.x() store volatile i32 %val, i32 addrspace(1)* undef diff --git a/llvm/test/CodeGen/AMDGPU/code-object-v3.ll b/llvm/test/CodeGen/AMDGPU/code-object-v3.ll index 20f96fdaeefd7..b51b30b1cd235 100644 --- a/llvm/test/CodeGen/AMDGPU/code-object-v3.ll +++ b/llvm/test/CodeGen/AMDGPU/code-object-v3.ll @@ -50,8 +50,9 @@ ; OSABI-AMDHSA-ELF: .rodata PROGBITS {{[0-9]+}} {{[0-9]+}} {{[0-9a-f]+}} {{[0-9]+}} A {{[0-9]+}} {{[0-9]+}} 64 ; OSABI-AMDHSA-ELF: Relocation section '.rela.rodata' at offset -; OSABI-AMDHSA-ELF: 0000000000000010 0000000100000005 R_AMDGPU_REL64 0000000000000000 fadd + 10 -; OSABI-AMDHSA-ELF: 0000000000000050 0000000300000005 R_AMDGPU_REL64 0000000000000100 fsub + 10 +; OSABI-AMDHSA-ELF: 0000000000000010 0000000300000005 R_AMDGPU_REL64 0000000000000000 fadd + 10 +; OSABI-AMDHSA-ELF: 0000000000000050 0000000500000005 R_AMDGPU_REL64 0000000000000100 fsub + 10 +; OSABI-AMDHSA-ELF: 0000000000000090 0000000100000005 R_AMDGPU_REL64 0000000000000200 empty + 10 ; OSABI-AMDHSA-ELF: Symbol table '.symtab' contains {{[0-9]+}} entries ; OSABI-AMDHSA-ELF: {{[0-9]+}}: 0000000000000000 {{[0-9]+}} FUNC GLOBAL PROTECTED {{[0-9]+}} fadd @@ -85,3 +86,18 @@ entry: store float %r.val, float addrspace(1)* %r ret void } + +; Make sure kernel arguments do not count towards the number of +; registers used. +; +; ALL-ASM-LABEL: {{^}}empty: +; ALL-ASM: .amdhsa_next_free_vgpr 1 +; ALL-ASM: .amdhsa_next_free_sgpr 1 +define amdgpu_kernel void @empty( + i32 %i, + float addrspace(1)* %r, + float addrspace(1)* %a, + float addrspace(1)* %b) { +entry: + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/enqueue-kernel.ll b/llvm/test/CodeGen/AMDGPU/enqueue-kernel.ll index 7358d9b0dc82c..3a5d7bb9be0a5 100644 --- a/llvm/test/CodeGen/AMDGPU/enqueue-kernel.ll +++ b/llvm/test/CodeGen/AMDGPU/enqueue-kernel.ll @@ -53,13 +53,13 @@ entry: store i8 %b, i8 addrspace(5)* %block.captured1, align 8 %tmp1 = bitcast <{ i32, i32, i8 addrspace(1)*, i8 }> addrspace(5)* %block to void () addrspace(5)* %tmp4 = addrspacecast void () addrspace(5)* %tmp1 to i8* - %tmp5 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp, + %tmp5 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp, i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i8 }>)* @__test_block_invoke_kernel to i8*), i8* nonnull %tmp4) #2 - %tmp10 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp, + %tmp10 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp, i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i8 }>)* @__test_block_invoke_kernel to i8*), i8* nonnull %tmp4) #2 - %tmp11 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp, + %tmp11 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp, i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i8 }>)* @0 to i8*), i8* nonnull %tmp4) #2 - %tmp12 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp, + %tmp12 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp, i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i8 }>)* @1 to i8*), i8* nonnull %tmp4) #2 %block.size4 = getelementptr inbounds <{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }>, <{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }> addrspace(5)* %block2, i32 0, i32 0 store i32 41, i32 addrspace(5)* %block.size4, align 8 @@ -75,7 +75,7 @@ entry: store i64 %d, i64 addrspace(5)* %block.captured10, align 8 %tmp6 = bitcast <{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }> addrspace(5)* %block2 to void () addrspace(5)* %tmp8 = addrspacecast void () addrspace(5)* %tmp6 to i8* - %tmp9 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval nonnull %tmp3, + %tmp9 = call i32 @__enqueue_kernel_basic(%opencl.queue_t addrspace(1)* undef, i32 0, %struct.ndrange_t addrspace(5)* byval(%struct.ndrange_t) nonnull %tmp3, i8* bitcast (void (<{ i32, i32, i8 addrspace(1)*, i64 addrspace(1)*, i64, i8 }>)* @__test_block_invoke_2_kernel to i8*), i8* nonnull %tmp8) #2 ret void } diff --git a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll index 4ef1c41b4326c..2c18e724278fd 100644 --- a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll +++ b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll @@ -128,7 +128,7 @@ define void @func_load_private_arg_i32_ptr(i32 addrspace(5)* %ptr) #0 { ; GCN-NOT: v_mov ; GCN: ds_write_b32 v0, v0 -define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 } addrspace(5)* byval %arg0) #0 { +define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 { %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0 %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 1 %load1 = load i32, i32 addrspace(5)* %gep1 @@ -142,7 +142,7 @@ define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 } addrspace(5)* byval % ; MUBUF-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 ; GFX9-FLATSCR-NEXT: scratch_load_ubyte v0, off, s32 ; GFX9-FLATSCR-NEXT: scratch_load_dword v1, off, s32 offset:4 -define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 } addrspace(5)* byval %arg0) #0 { +define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 { %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0 %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 1 %load0 = load i8, i8 addrspace(5)* %gep0 @@ -169,7 +169,7 @@ define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 } addrspace(5)* b ; GFX9-FLATSCR: scratch_load_dword v{{[0-9]+}}, [[SP]], off offset:4{{$}} ; GCN: ds_write_b32 v{{[0-9]+}}, [[GEP]] -define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 } addrspace(5)* byval %arg0, i32 %arg2) #0 { +define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, i32 %arg2) #0 { %cmp = icmp eq i32 %arg2, 0 br i1 %cmp, label %bb, label %ret diff --git a/llvm/test/CodeGen/AMDGPU/function-args.ll b/llvm/test/CodeGen/AMDGPU/function-args.ll index 1f2657fe94d29..8923c8a701b44 100644 --- a/llvm/test/CodeGen/AMDGPU/function-args.ll +++ b/llvm/test/CodeGen/AMDGPU/function-args.ll @@ -530,7 +530,7 @@ define void @void_func_struct_i8_i32({ i8, i32 } %arg0) #0 { ; GCN-DAG: buffer_load_dword v[[ELT1:[0-9]+]], off, s[0:3], s32 offset:4{{$}} ; GCN-DAG: buffer_store_dword v[[ELT1]] ; GCN-DAG: buffer_store_byte v[[ELT0]] -define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0) #0 { +define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 { %arg0.load = load { i8, i32 }, { i8, i32 } addrspace(5)* %arg0 store { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef ret void @@ -544,7 +544,7 @@ define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0 ; GCN: ds_write_b32 v0, v0 ; GCN: s_setpc_b64 -define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %arg0, { i8, i32 } addrspace(5)* byval %arg1, i32 %arg2) #0 { +define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg1, i32 %arg2) #0 { %arg0.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg0 %arg1.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg1 store volatile { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef @@ -559,7 +559,7 @@ define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %a ; GCN-DAG: buffer_load_dword v[[ARG1_LOAD1:[0-9]+]], off, s[0:3], s32 offset:12{{$}} ; GCN-DAG: buffer_store_dword v[[ARG0_LOAD]], off ; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ARG1_LOAD0]]:[[ARG1_LOAD1]]{{\]}}, off -define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval %arg0, i64 addrspace(5)* byval %arg1) #0 { +define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval(i32) %arg0, i64 addrspace(5)* byval(i64) %arg1) #0 { %arg0.load = load i32, i32 addrspace(5)* %arg0 %arg1.load = load i64, i64 addrspace(5)* %arg1 store i32 %arg0.load, i32 addrspace(1)* undef diff --git a/llvm/test/CodeGen/AMDGPU/function-returns.ll b/llvm/test/CodeGen/AMDGPU/function-returns.ll index 9c84996379481..04dc4a2ba628e 100644 --- a/llvm/test/CodeGen/AMDGPU/function-returns.ll +++ b/llvm/test/CodeGen/AMDGPU/function-returns.ll @@ -459,7 +459,7 @@ define {i8, i32} @struct_i8_i32_func_void() #0 { ; GCN: buffer_load_dword [[VAL1:v[0-9]+]] ; GCN: buffer_store_byte [[VAL0]], v0, s[0:3], 0 offen{{$}} ; GCN: buffer_store_dword [[VAL1]], v0, s[0:3], 0 offen offset:4{{$}} -define void @void_func_sret_struct_i8_i32({ i8, i32 } addrspace(5)* sret %arg0) #0 { +define void @void_func_sret_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }) %arg0) #0 { %val0 = load volatile i8, i8 addrspace(1)* undef %val1 = load volatile i32, i32 addrspace(1)* undef %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0 @@ -645,7 +645,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 { ; GCN: v_mov_b32_e32 [[HIGH_BITS:v[0-9]+]], 0 ; GCN: ds_write_b32 {{v[0-9]+}}, [[HIGH_BITS]] ; GCN-NEXT: ds_write_b32 {{v[0-9]+}}, [[HIGH_BITS]] -define void @void_func_sret_max_known_zero_bits(i8 addrspace(5)* sret %arg0) #0 { +define void @void_func_sret_max_known_zero_bits(i8 addrspace(5)* sret(i8) %arg0) #0 { %arg0.int = ptrtoint i8 addrspace(5)* %arg0 to i32 %lshr0 = lshr i32 %arg0.int, 16 diff --git a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll index 122b10d1e4e61..ec5227d03d2b7 100644 --- a/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll +++ b/llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll @@ -86,8 +86,8 @@ declare hidden amdgpu_gfx i32 @external_i32_func_i32(i32) #0 ; Structs declare hidden amdgpu_gfx void @external_void_func_struct_i8_i32({ i8, i32 }) #0 -declare hidden amdgpu_gfx void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval) #0 -declare hidden amdgpu_gfx void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0 +declare hidden amdgpu_gfx void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 +declare hidden amdgpu_gfx void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }), { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0 declare hidden amdgpu_gfx void @external_void_func_v16i8(<16 x i8>) #0 @@ -3392,7 +3392,7 @@ define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 { ; GFX10-NEXT: s_setpc_b64 s[4:5] entry: %alloca = alloca double, align 8, addrspace(5) - tail call amdgpu_gfx void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval align 16 %alloca) + tail call amdgpu_gfx void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval(double) align 16 %alloca) ret void } @@ -6542,7 +6542,7 @@ entry: ret void } -declare hidden amdgpu_gfx void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval align 16) #0 +declare hidden amdgpu_gfx void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval(double) align 16) #0 declare hidden amdgpu_gfx void @stack_passed_f64_arg(<32 x i32>, double) #0 declare hidden amdgpu_gfx void @external_void_func_12xv3i32(<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>) #0 diff --git a/llvm/test/CodeGen/AMDGPU/global_smrd_cfg.ll b/llvm/test/CodeGen/AMDGPU/global_smrd_cfg.ll index 1a675ce57bc25..fd51f47bce892 100644 --- a/llvm/test/CodeGen/AMDGPU/global_smrd_cfg.ll +++ b/llvm/test/CodeGen/AMDGPU/global_smrd_cfg.ll @@ -9,8 +9,9 @@ ; ##################################################################### ; Load from %arg1 has no-alias store in Loop - arg1[i+1] never alias arg1[i] +; However, our analysis cannot detect this. -; CHECK: s_load_dword +; CHECK: flat_load_dword ; ##################################################################### diff --git a/llvm/test/CodeGen/AMDGPU/load-hi16.ll b/llvm/test/CodeGen/AMDGPU/load-hi16.ll index cda335d73f0c0..ec757689f6c52 100644 --- a/llvm/test/CodeGen/AMDGPU/load-hi16.ll +++ b/llvm/test/CodeGen/AMDGPU/load-hi16.ll @@ -502,7 +502,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s32 offset:4094{{$}} -define void @load_private_hi_v2i16_reglo_vreg(i16 addrspace(5)* byval %in, i16 %reg) #0 { +define void @load_private_hi_v2i16_reglo_vreg(i16 addrspace(5)* byval(i16) %in, i16 %reg) #0 { entry: %gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i64 2047 %load = load i16, i16 addrspace(5)* %gep @@ -522,7 +522,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s32 offset:4094{{$}} -define void @load_private_hi_v2f16_reglo_vreg(half addrspace(5)* byval %in, half %reg) #0 { +define void @load_private_hi_v2f16_reglo_vreg(half addrspace(5)* byval(half) %in, half %reg) #0 { entry: %gep = getelementptr inbounds half, half addrspace(5)* %in, i64 2047 %load = load half, half addrspace(5)* %gep @@ -543,7 +543,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], 0 offset:4094{{$}} -define void @load_private_hi_v2i16_reglo_vreg_nooff(i16 addrspace(5)* byval %in, i16 %reg) #0 { +define void @load_private_hi_v2i16_reglo_vreg_nooff(i16 addrspace(5)* byval(i16) %in, i16 %reg) #0 { entry: %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*) %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 @@ -582,7 +582,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}} -define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, i16 %reg) #0 { +define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval(i8) %in, i16 %reg) #0 { entry: %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095 %load = load i8, i8 addrspace(5)* %gep @@ -603,7 +603,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}} -define void @load_private_hi_v2f16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, half %reg) #0 { +define void @load_private_hi_v2f16_reglo_vreg_zexti8(i8 addrspace(5)* byval(i8) %in, half %reg) #0 { entry: %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095 %load = load i8, i8 addrspace(5)* %gep @@ -625,7 +625,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}} -define void @load_private_hi_v2f16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, half %reg) #0 { +define void @load_private_hi_v2f16_reglo_vreg_sexti8(i8 addrspace(5)* byval(i8) %in, half %reg) #0 { entry: %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095 %load = load i8, i8 addrspace(5)* %gep @@ -647,7 +647,7 @@ entry: ; GFX900-NEXT: s_setpc_b64 ; NO-D16-HI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}} -define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, i16 %reg) #0 { +define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval(i8) %in, i16 %reg) #0 { entry: %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095 %load = load i8, i8 addrspace(5)* %gep @@ -1004,7 +1004,7 @@ entry: ; GFX900-FLATSCR-NEXT: scratch_load_short_d16_hi v0, off, s32 offset:2 ; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_setpc_b64 -define <2 x i16> @load_private_v2i16_split(i16 addrspace(5)* byval %in) #0 { +define <2 x i16> @load_private_v2i16_split(i16 addrspace(5)* byval(i16) %in) #0 { entry: %gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i32 1 %load0 = load volatile i16, i16 addrspace(5)* %in diff --git a/llvm/test/CodeGen/AMDGPU/load-lo16.ll b/llvm/test/CodeGen/AMDGPU/load-lo16.ll index 44fe6cdf915b2..e0866ca5195f4 100644 --- a/llvm/test/CodeGen/AMDGPU/load-lo16.ll +++ b/llvm/test/CodeGen/AMDGPU/load-lo16.ll @@ -1177,7 +1177,7 @@ entry: ret void } -define void @load_private_lo_v2i16_reglo_vreg(i16 addrspace(5)* byval %in, i32 %reg) #0 { +define void @load_private_lo_v2i16_reglo_vreg(i16 addrspace(5)* byval(i16) %in, i32 %reg) #0 { ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg: ; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1226,7 +1226,7 @@ entry: ret void } -define void @load_private_lo_v2i16_reghi_vreg(i16 addrspace(5)* byval %in, i16 %reg) #0 { +define void @load_private_lo_v2i16_reghi_vreg(i16 addrspace(5)* byval(i16) %in, i16 %reg) #0 { ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reghi_vreg: ; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1279,7 +1279,7 @@ entry: ret void } -define void @load_private_lo_v2f16_reglo_vreg(half addrspace(5)* byval %in, i32 %reg) #0 { +define void @load_private_lo_v2f16_reglo_vreg(half addrspace(5)* byval(half) %in, i32 %reg) #0 { ; GFX900-MUBUF-LABEL: load_private_lo_v2f16_reglo_vreg: ; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1477,7 +1477,7 @@ entry: ret void } -define void @load_private_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, i32 %reg) #0 { +define void @load_private_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval(i8) %in, i32 %reg) #0 { ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8: ; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1528,7 +1528,7 @@ entry: ret void } -define void @load_private_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, i32 %reg) #0 { +define void @load_private_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval(i8) %in, i32 %reg) #0 { ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8: ; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/opt-pipeline.ll b/llvm/test/CodeGen/AMDGPU/opt-pipeline.ll index 55461ea5b66e3..8a8ce1e0c1852 100644 --- a/llvm/test/CodeGen/AMDGPU/opt-pipeline.ll +++ b/llvm/test/CodeGen/AMDGPU/opt-pipeline.ll @@ -163,8 +163,8 @@ ; GCN-O1-NEXT: Loop-Closed SSA Form Pass ; GCN-O1-NEXT: Scalar Evolution Analysis ; GCN-O1-NEXT: Loop Pass Manager -; GCN-O1-NEXT: Induction Variable Simplification ; GCN-O1-NEXT: Recognize loop idioms +; GCN-O1-NEXT: Induction Variable Simplification ; GCN-O1-NEXT: Delete dead loops ; GCN-O1-NEXT: Unroll loops ; GCN-O1-NEXT: SROA @@ -487,8 +487,8 @@ ; GCN-O2-NEXT: Loop-Closed SSA Form Pass ; GCN-O2-NEXT: Scalar Evolution Analysis ; GCN-O2-NEXT: Loop Pass Manager -; GCN-O2-NEXT: Induction Variable Simplification ; GCN-O2-NEXT: Recognize loop idioms +; GCN-O2-NEXT: Induction Variable Simplification ; GCN-O2-NEXT: Delete dead loops ; GCN-O2-NEXT: Unroll loops ; GCN-O2-NEXT: SROA @@ -851,8 +851,8 @@ ; GCN-O3-NEXT: Loop-Closed SSA Form Pass ; GCN-O3-NEXT: Scalar Evolution Analysis ; GCN-O3-NEXT: Loop Pass Manager -; GCN-O3-NEXT: Induction Variable Simplification ; GCN-O3-NEXT: Recognize loop idioms +; GCN-O3-NEXT: Induction Variable Simplification ; GCN-O3-NEXT: Delete dead loops ; GCN-O3-NEXT: Unroll loops ; GCN-O3-NEXT: SROA diff --git a/llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll b/llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll index 35797c42b9ac0..673fbb991ad12 100644 --- a/llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll +++ b/llvm/test/CodeGen/AMDGPU/rewrite-out-arguments.ll @@ -56,7 +56,7 @@ define void @void_one_out_arg_i32_no_use(i32* %val) #0 { ; CHECK-LABEL: define void @skip_byval_arg( ; CHECK-NEXT: store i32 0, i32* %val ; CHECK-NEXT: ret void -define void @skip_byval_arg(i32* byval %val) #0 { +define void @skip_byval_arg(i32* byval(i32) %val) #0 { store i32 0, i32* %val ret void } @@ -65,7 +65,7 @@ define void @skip_byval_arg(i32* byval %val) #0 { ; CHECK-LABEL: define void @skip_optnone( ; CHECK-NEXT: store i32 0, i32* %val ; CHECK-NEXT: ret void -define void @skip_optnone(i32* byval %val) #1 { +define void @skip_optnone(i32* byval(i32) %val) #1 { store i32 0, i32* %val ret void } @@ -74,7 +74,7 @@ define void @skip_optnone(i32* byval %val) #1 { ; CHECK-LABEL: define void @skip_volatile( ; CHECK-NEXT: store volatile i32 0, i32* %val ; CHECK-NEXT: ret void -define void @skip_volatile(i32* byval %val) #0 { +define void @skip_volatile(i32* byval(i32) %val) #0 { store volatile i32 0, i32* %val ret void } @@ -83,7 +83,7 @@ define void @skip_volatile(i32* byval %val) #0 { ; CHECK-LABEL: define void @skip_atomic( ; CHECK-NEXT: store atomic i32 0, i32* %val ; CHECK-NEXT: ret void -define void @skip_atomic(i32* byval %val) #0 { +define void @skip_atomic(i32* byval(i32) %val) #0 { store atomic i32 0, i32* %val seq_cst, align 4 ret void } @@ -108,11 +108,11 @@ define void @skip_store_gep(i32* %val) #0 { ret void } -; CHECK-LABEL: define void @skip_sret(i32* sret %sret, i32* %out) #0 { +; CHECK-LABEL: define void @skip_sret(i32* sret(i32) %sret, i32* %out) #0 { ; CHECK-NEXT: store ; CHECK-NEXT: store ; CHECK-NEXT: ret void -define void @skip_sret(i32* sret %sret, i32* %out) #0 { +define void @skip_sret(i32* sret(i32) %sret, i32* %out) #0 { store i32 1, i32* %sret store i32 0, i32* %out ret void diff --git a/llvm/test/CodeGen/AMDGPU/sibling-call.ll b/llvm/test/CodeGen/AMDGPU/sibling-call.ll index bfab65bbab041..3f711e4989f0a 100644 --- a/llvm/test/CodeGen/AMDGPU/sibling-call.ll +++ b/llvm/test/CodeGen/AMDGPU/sibling-call.ll @@ -91,7 +91,7 @@ entry: ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 ; GCN-NEXT: s_setpc_b64 s[30:31] -define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)* byval align 4 %arg1) #1 { +define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)* byval(i32) align 4 %arg1) #1 { %arg1.load = load i32, i32 addrspace(5)* %arg1, align 4 %add0 = add i32 %arg0, %arg1.load ret i32 %add0 @@ -104,9 +104,9 @@ define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)* ; GCN: s_swappc_b64 ; GCN-NOT: v_readlane_b32 s32 ; GCN: s_setpc_b64 -define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, i32 addrspace(5)* byval %b.byval, i32 %c) #1 { +define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, i32 addrspace(5)* byval(i32) %b.byval, i32 %c) #1 { entry: - %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* %b.byval) + %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* byval(i32) %b.byval) ret i32 %ret } @@ -122,7 +122,7 @@ entry: ; GCN-NEXT: s_setpc_b64 define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32(i32 %a, [32 x i32] %large) #1 { entry: - %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* inttoptr (i32 16 to i32 addrspace(5)*)) + %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* byval(i32) inttoptr (i32 16 to i32 addrspace(5)*)) ret i32 %ret } diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign.ll b/llvm/test/CodeGen/AMDGPU/stack-realign.ll index c9203e8a8c248..438031226aefe 100644 --- a/llvm/test/CodeGen/AMDGPU/stack-realign.ll +++ b/llvm/test/CodeGen/AMDGPU/stack-realign.ll @@ -284,7 +284,7 @@ define void @no_free_regs_spill_bp_to_memory(<32 x i32> %a, i32 %b) #5 { ret void } -define void @spill_bp_to_memory_scratch_reg_needed_mubuf_offset(<32 x i32> %a, i32 %b, [4096 x i8] addrspace(5)* byval align 4 %arg) #5 { +define void @spill_bp_to_memory_scratch_reg_needed_mubuf_offset(<32 x i32> %a, i32 %b, [4096 x i8] addrspace(5)* byval([4096 x i8]) align 4 %arg) #5 { ; If the size of the offset exceeds the MUBUF offset field we need another ; scratch VGPR to hold the offset. diff --git a/llvm/test/CodeGen/AMDGPU/store-hi16.ll b/llvm/test/CodeGen/AMDGPU/store-hi16.ll index 85ea81ff17219..702c28a33a92b 100644 --- a/llvm/test/CodeGen/AMDGPU/store-hi16.ll +++ b/llvm/test/CodeGen/AMDGPU/store-hi16.ll @@ -495,7 +495,7 @@ entry: ; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_setpc_b64 -define void @store_private_hi_v2i16_max_offset(i16 addrspace(5)* byval %out, i32 %arg) #0 { +define void @store_private_hi_v2i16_max_offset(i16 addrspace(5)* byval(i16) %out, i32 %arg) #0 { entry: %value = bitcast i32 %arg to <2 x i16> %hi = extractelement <2 x i16> %value, i32 1 diff --git a/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll b/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll index a48e41f55e5fb..c50aa4a018be4 100644 --- a/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll +++ b/llvm/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll @@ -6,6 +6,6 @@ define fastcc void @t() { entry: - %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null) ; [#uses=0] + %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval(%tango.time.Time.Time) null) ; [#uses=0] ret void } diff --git a/llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll b/llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll index 9eae0d75e8724..5fc3f6e80c362 100644 --- a/llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll +++ b/llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll @@ -8,7 +8,7 @@ @_2E_str7 = internal constant [21 x i8] c"ERROR: Only 1 point!\00", section "__TEXT,__cstring,cstring_literals", align 1 @llvm.used = appending global [1 x i8*] [i8* bitcast (void (%struct.EDGE_PAIR*, %struct.VERTEX*, %struct.VERTEX*)* @build_delaunay to i8*)], section "llvm.metadata" -define void @build_delaunay(%struct.EDGE_PAIR* noalias nocapture sret %agg.result, %struct.VERTEX* %tree, %struct.VERTEX* %extra) nounwind { +define void @build_delaunay(%struct.EDGE_PAIR* noalias nocapture sret(%struct.EDGE_PAIR) %agg.result, %struct.VERTEX* %tree, %struct.VERTEX* %extra) nounwind { entry: %delright = alloca %struct.EDGE_PAIR, align 8 %delleft = alloca %struct.EDGE_PAIR, align 8 @@ -29,10 +29,10 @@ bb1.i: br i1 %6, label %get_low.exit, label %bb1.i get_low.exit: - call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind + call void @build_delaunay(%struct.EDGE_PAIR* noalias sret(%struct.EDGE_PAIR) %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind %7 = getelementptr %struct.VERTEX, %struct.VERTEX* %tree, i32 0, i32 1 %8 = load %struct.VERTEX*, %struct.VERTEX** %7, align 4 - call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind + call void @build_delaunay(%struct.EDGE_PAIR* noalias sret(%struct.EDGE_PAIR) %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind %9 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delleft, i32 0, i32 0 %10 = load %struct.edge_rec*, %struct.edge_rec** %9, align 8 %11 = getelementptr %struct.EDGE_PAIR, %struct.EDGE_PAIR* %delleft, i32 0, i32 1 diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll index d5570df717f59..4aa46d0000ced 100644 --- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll +++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll @@ -11,7 +11,7 @@ target triple = "armv7-apple-darwin9" declare double @floor(double) nounwind readnone -define void @intcoord(%struct.icstruct* noalias nocapture sret %agg.result, i1 %a, double %b) { +define void @intcoord(%struct.icstruct* noalias nocapture sret(%struct.icstruct) %agg.result, i1 %a, double %b) { entry: br i1 %a, label %bb3, label %bb1 diff --git a/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll b/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll index aace4751915d1..eec0afcb89401 100644 --- a/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll +++ b/llvm/test/CodeGen/ARM/2009-09-21-LiveVariablesBug.ll @@ -7,7 +7,7 @@ declare arm_aapcs_vfpcc <4 x float> @bbb(%bar*) nounwind -define arm_aapcs_vfpcc void @aaa(%foo* noalias sret %agg.result, %foo* %tfrm) nounwind { +define arm_aapcs_vfpcc void @aaa(%foo* noalias sret(%foo) %agg.result, %foo* %tfrm) nounwind { entry: %0 = call arm_aapcs_vfpcc <4 x float> @bbb(%bar* undef) nounwind ; <<4 x float>> [#uses=0] ret void diff --git a/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll index 287384fbc214c..8bf73e924b7ca 100644 --- a/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll +++ b/llvm/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll @@ -3,7 +3,7 @@ %0 = type { double, double } -define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { +define void @foo(%0* noalias nocapture sret(%0) %agg.result, double %x.0, double %y.0) nounwind { ; CHECK-LABEL: foo: ; CHECK: bl __aeabi_dadd ; CHECK-NOT: strd diff --git a/llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll b/llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll index 1fc10564a460f..abc815bb8a8b8 100644 --- a/llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll +++ b/llvm/test/CodeGen/ARM/2009-11-01-NeonMoves.ll @@ -5,7 +5,7 @@ target triple = "armv7-eabi" %foo = type { <4 x float> } -define arm_aapcs_vfpcc void @bar(%foo* noalias sret %agg.result, <4 x float> %quat.0) nounwind { +define arm_aapcs_vfpcc void @bar(%foo* noalias sret(%foo) %agg.result, <4 x float> %quat.0) nounwind { entry: %quat_addr = alloca %foo, align 16 ; <%foo*> [#uses=2] %0 = getelementptr inbounds %foo, %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1] diff --git a/llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll b/llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll index 8cba9116481e7..be9dcffedcd44 100644 --- a/llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll +++ b/llvm/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll @@ -6,7 +6,7 @@ target triple = "armv7-apple-darwin10" %struct.int16x8_t = type { <8 x i16> } %struct.int16x8x2_t = type { [2 x %struct.int16x8_t] } -define void @t(%struct.int16x8x2_t* noalias nocapture sret %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind { +define void @t(%struct.int16x8x2_t* noalias nocapture sret(%struct.int16x8x2_t) %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind { entry: ;CHECK: vtrn.16 %0 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> diff --git a/llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll b/llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll index f4b93ca74fc0f..b2557b7165db8 100644 --- a/llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll +++ b/llvm/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll @@ -33,8 +33,8 @@ target triple = "thumbv7-apple-darwin10" define i32 @"\01_fnmatch"(i8* %pattern, i8* %string, i32 %flags) nounwind optsize { entry: - %call4 = tail call i32 @fnmatch1(i8* %pattern, i8* %string, i8* %string, i32 %flags, %union.__mbstate_t* byval @"\01_fnmatch.initial", %union.__mbstate_t* byval @"\01_fnmatch.initial", %struct._xlocale* undef, i32 64) optsize + %call4 = tail call i32 @fnmatch1(i8* %pattern, i8* %string, i8* %string, i32 %flags, %union.__mbstate_t* byval(%union.__mbstate_t) @"\01_fnmatch.initial", %union.__mbstate_t* byval(%union.__mbstate_t) @"\01_fnmatch.initial", %struct._xlocale* undef, i32 64) optsize ret i32 %call4 } -declare i32 @fnmatch1(i8*, i8*, i8*, i32, %union.__mbstate_t* byval, %union.__mbstate_t* byval, %struct._xlocale*, i32) nounwind optsize +declare i32 @fnmatch1(i8*, i8*, i8*, i32, %union.__mbstate_t* byval(%union.__mbstate_t), %union.__mbstate_t* byval(%union.__mbstate_t), %struct._xlocale*, i32) nounwind optsize diff --git a/llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll b/llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll index d93cc57574b42..aa83b7e2fa820 100644 --- a/llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll +++ b/llvm/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll @@ -16,7 +16,7 @@ target triple = "thumbv7-apple-ios5.0" ; CHECK: add sp, #12 ; CHECK: b.w _puts -define void @f(i8* %s, %struct.A* nocapture byval %a) nounwind optsize { +define void @f(i8* %s, %struct.A* nocapture byval(%struct.A) %a) nounwind optsize { entry: %puts = tail call i32 @puts(i8* %s) ret void diff --git a/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll b/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll index 2484f0d42ed37..0ee79086e9fff 100644 --- a/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll +++ b/llvm/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll @@ -77,7 +77,7 @@ bb3: ; preds = %bb2 %tmp60 = fadd <4 x float> %tmp59, undef %tmp61 = fadd <4 x float> %tmp60, zeroinitializer %tmp62 = load void (i8*, i8*)*, void (i8*, i8*)** undef, align 4 - call arm_aapcs_vfpcc void %tmp62(i8* sret undef, i8* undef) nounwind + call arm_aapcs_vfpcc void %tmp62(i8* sret(i8) undef, i8* undef) nounwind %tmp63 = bitcast <4 x float> %tmp46 to i128 %tmp64 = bitcast <4 x float> %tmp54 to i128 %tmp65 = bitcast <4 x float> %tmp61 to i128 @@ -93,7 +93,7 @@ bb3: ; preds = %bb2 %tmp75 = insertvalue [8 x i64] %tmp74, i64 undef, 5 %tmp76 = insertvalue [8 x i64] %tmp75, i64 undef, 6 %tmp77 = insertvalue [8 x i64] %tmp76, i64 undef, 7 - call arm_aapcs_vfpcc void @bar(i8* sret null, [8 x i64] %tmp77) nounwind + call arm_aapcs_vfpcc void @bar(i8* sret(i8) null, [8 x i64] %tmp77) nounwind %tmp78 = call arm_aapcs_vfpcc i8* null(i8* null) nounwind %tmp79 = bitcast i8* %tmp78 to i512* %tmp80 = load i512, i512* %tmp79, align 16 @@ -115,4 +115,4 @@ bb92: ; preds = %bb2 ret void } -declare arm_aapcs_vfpcc void @bar(i8* noalias nocapture sret, [8 x i64]) nounwind uwtable inlinehint +declare arm_aapcs_vfpcc void @bar(i8* noalias nocapture sret(i8), [8 x i64]) nounwind uwtable inlinehint diff --git a/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll index 1b0dbe9f47fd9..f50fa8c77c7af 100644 --- a/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll +++ b/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll @@ -34,7 +34,7 @@ entry: ; CHECK: movw r0, #555 define i32 @main() { entry: - call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val) + call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval(%struct_t) @static_val) ret i32 0 } @@ -45,7 +45,7 @@ declare void @f(double); ; CHECK-DAG: str r3, [sp, #12] ; CHECK-DAG: str r2, [sp, #8] ; CHECK-NOT: str r1 -define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval %val) nounwind { +define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval(%struct_t) %val) nounwind { entry: %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0 %0 = load double, double* %a @@ -61,6 +61,6 @@ entry: ; CHECK: movw r0, #555 define i32 @main_fixed_arg() { entry: - call void (i32, %struct_t*) @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val) + call void (i32, %struct_t*) @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval(%struct_t) @static_val) ret i32 0 } diff --git a/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll b/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll index 1530d645620a3..3ac6f6879a4f4 100644 --- a/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll +++ b/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll @@ -10,7 +10,7 @@ declare i32 @printf(i8*, ...) ; CHECK-DAG: str r3, [sp, #12] ; CHECK-DAG: str r2, [sp, #8] ; CHECK: vldr d16, [sp, #8] -define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval %val) nounwind { +define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval(%struct_t) %val) nounwind { entry: %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0 %0 = load double, double* %a diff --git a/llvm/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll b/llvm/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll index a59533c4a85db..b06da52973d35 100644 --- a/llvm/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll +++ b/llvm/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll @@ -4,13 +4,13 @@ %my_struct_t = type { i8, i8, i8, i8, i8 } @main.val = private unnamed_addr constant %my_struct_t { i8 1, i8 2, i8 3, i8 4, i8 5 } -declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval %val); +declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval(%my_struct_t) %val); ; CHECK-LABEL: main: define i32 @main() nounwind { entry: ; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1 - call void @f(i32 555, i32 555, i32 555, %my_struct_t* byval @main.val) + call void @f(i32 555, i32 555, i32 555, %my_struct_t* byval(%my_struct_t) @main.val) ret i32 0 } diff --git a/llvm/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll b/llvm/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll index fefe16747f106..a1c2bede04ae7 100644 --- a/llvm/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll +++ b/llvm/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll @@ -1,12 +1,12 @@ ; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s %struct.s = type { [4 x i32] } -@v = constant %struct.s zeroinitializer; +@v = constant %struct.s zeroinitializer; declare void @f(%struct.s* %p); ; CHECK-LABEL: t: -define void @t(i32 %a, %struct.s* byval %s) nounwind { +define void @t(i32 %a, %struct.s* byval(%struct.s) %s) nounwind { entry: ; Here we need to only check proper start address of restored %s argument. @@ -25,6 +25,6 @@ entry: define void @caller() { ; CHECK: ldm r{{[0-9]+}}, {r1, r2, r3} - call void @t(i32 0, %struct.s* @v); + call void @t(i32 0, %struct.s* byval(%struct.s) @v); ret void } diff --git a/llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll b/llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll index c38dd16f0d27d..6d26c04445f26 100644 --- a/llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll +++ b/llvm/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll @@ -49,12 +49,12 @@ declare void @fooUseParam(%artz* ) -define void @foo(%artz* byval %s) { +define void @foo(%artz* byval(%artz) %s) { call void @fooUseParam(%artz* %s) ret void } -define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2) { +define void @foo2(%artz* byval(%artz) %s, i32 %p, %artz* byval(%artz) %s2) { call void @fooUseParam(%artz* %s) call void @fooUseParam(%artz* %s2) ret void @@ -62,12 +62,12 @@ define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2) { define void @doFoo() { - call void @foo(%artz* byval @static_val) + call void @foo(%artz* byval(%artz) @static_val) ret void } define void @doFoo2() { - call void @foo2(%artz* byval @static_val, i32 0, %artz* byval @static_val) + call void @foo2(%artz* byval(%artz) @static_val, i32 0, %artz* byval(%artz) @static_val) ret void } diff --git a/llvm/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll b/llvm/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll index 5e82b0925b24a..91e0114773020 100644 --- a/llvm/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll +++ b/llvm/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll @@ -30,7 +30,7 @@ define void @foo2(double %p0, ; --> D0 double %p7, ; --> D7 double %p8, ; --> Stack i32 %p9, ; --> R0 - %struct_t* byval %p10) ; --> Stack+8 + %struct_t* byval(%struct_t) %p10) ; --> Stack+8 { entry: ;CHECK: push {r7, lr} @@ -55,7 +55,7 @@ entry: double 23.7, ; --> D7 double 23.8, ; --> Stack i32 43, ; --> R0, not Stack+8 - %struct_t* byval @static_val) ; --> Stack+8, not R1 + %struct_t* byval(%struct_t) @static_val) ; --> Stack+8, not R1 ret void } diff --git a/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll b/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll index ac5b6f9c97089..d6de8c9587c1d 100644 --- a/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll +++ b/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll @@ -16,9 +16,9 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP double %vfp6, ; --> D6, NSAA=SP double %vfp7, ; --> D7, NSAA=SP double %vfp8, ; --> SP, NSAA=SP+8 (!) - i32 %p0, ; --> R0, NSAA=SP+8 - %st_t* byval %p1, ; --> R1, R2, NSAA=SP+8 - i32 %p2, ; --> R3, NSAA=SP+8 + i32 %p0, ; --> R0, NSAA=SP+8 + %st_t* byval(%st_t) %p1, ; --> R1, R2, NSAA=SP+8 + i32 %p2, ; --> R3, NSAA=SP+8 i32 %p3) #0 { ; --> SP+4, NSAA=SP+12 entry: ;CHECK: sub sp, #12 @@ -42,7 +42,7 @@ entry: double 23.6, double 23.7, double 23.8, - i32 0, %st_t* byval @static_val, i32 1, i32 2) + i32 0, %st_t* byval(%st_t) @static_val, i32 1, i32 2) ret void } diff --git a/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll b/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll index 944a60c06107b..d2e3fef51c32f 100644 --- a/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll +++ b/llvm/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll @@ -14,10 +14,10 @@ define void @foo(double %vfp0, ; --> D0, NSAA=SP double %vfp6, ; --> D6, NSAA=SP double %vfp7, ; --> D7, NSAA=SP double %vfp8, ; --> SP, NSAA=SP+8 (!) - i32 %p0, ; --> R0, NSAA=SP+8 - %st_t* byval %p1, ; --> SP+8, 4 words NSAA=SP+24 - i32 %p2) #0 { ; --> SP+24, NSAA=SP+24 - + i32 %p0, ; --> R0, NSAA=SP+8 + %st_t* byval(%st_t) %p1, ; --> SP+8, 4 words NSAA=SP+24 + i32 %p2) #0 { ; --> SP+24, NSAA=SP+24 + entry: ;CHECK: push {r7, lr} ;CHECK: ldr r0, [sp, #32] @@ -39,7 +39,7 @@ entry: double 23.6, double 23.7, double 23.8, - i32 0, %st_t* byval @static_val, i32 1) + i32 0, %st_t* byval(%st_t) @static_val, i32 1) ret void } diff --git a/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll b/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll index 3c20c6b536332..353fade4992d6 100644 --- a/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll +++ b/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding.ll @@ -5,7 +5,7 @@ define void @check227( i32 %b, - %struct.S227* byval nocapture %arg0, + %struct.S227* byval(%struct.S227) nocapture %arg0, %struct.S227* %arg1) { ; b --> R0 ; arg0 --> [R1, R2, R3, SP+0 .. SP+188) diff --git a/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll b/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll index d3aa2331d45fa..0f9273ded6bf0 100644 --- a/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll +++ b/llvm/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll @@ -4,8 +4,8 @@ %struct4bytes = type { i32 } %struct20bytes = type { i32, i32, i32, i32, i32 } -define void @foo(%struct4bytes* byval %p0, ; --> R0 - %struct20bytes* byval %p1 ; --> R1,R2,R3, [SP+0 .. SP+8) +define void @foo(%struct4bytes* byval(%struct4bytes) %p0, ; --> R0 + %struct20bytes* byval(%struct20bytes) %p1 ; --> R1,R2,R3, [SP+0 .. SP+8) ) { ;CHECK: sub sp, sp, #16 ;CHECK: push {r11, lr} diff --git a/llvm/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll b/llvm/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll index 1c13800702198..e5059edf0c4dd 100644 --- a/llvm/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll +++ b/llvm/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll @@ -12,19 +12,19 @@ define void @f(%big_struct0* %p0, %big_struct1* %p1) { ;CHECK: sub sp, sp, #8 ;CHECK: sub sp, sp, #2048 ;CHECK: bl callme0 - call void @callme0(%big_struct0* byval %p0) + call void @callme0(%big_struct0* byval(%big_struct0) %p0) ;CHECK: add sp, sp, #8 ;CHECK: add sp, sp, #2048 ;CHECK: sub sp, sp, #2048 ;CHECK: bl callme1 - call void @callme1(%big_struct1* byval %p1) + call void @callme1(%big_struct1* byval(%big_struct1) %p1) ;CHECK: add sp, sp, #2048 ret void } -declare void @callme0(%big_struct0* byval) -declare void @callme1(%big_struct1* byval) +declare void @callme0(%big_struct0* byval(%big_struct0)) +declare void @callme1(%big_struct1* byval(%big_struct1)) diff --git a/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll b/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll index f8c4d5d8db8cc..f9d24ad1ad444 100644 --- a/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll +++ b/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll @@ -11,7 +11,7 @@ declare void @usePtr(%struct8bytes8align*) ; a -> r0 ; b -> r1..r3 ; c -> sp+0..sp+7 -define void @foo1(i32 %a, %struct12bytes* byval %b, i64 %c) { +define void @foo1(i32 %a, %struct12bytes* byval(%struct12bytes) %b, i64 %c) { ; CHECK-LABEL: foo1 ; CHECK: sub sp, sp, #12 ; CHECK: push {r11, lr} @@ -30,7 +30,7 @@ define void @foo1(i32 %a, %struct12bytes* byval %b, i64 %c) { ; a -> r0 ; b -> r2..r3 -define void @foo2(i32 %a, %struct8bytes8align* byval %b) { +define void @foo2(i32 %a, %struct8bytes8align* byval(%struct8bytes8align) %b) { ; CHECK-LABEL: foo2 ; CHECK: sub sp, sp, #8 ; CHECK: push {r11, lr} @@ -47,7 +47,7 @@ define void @foo2(i32 %a, %struct8bytes8align* byval %b) { ; a -> r0..r1 ; b -> r2 -define void @foo3(%struct8bytes8align* byval %a, %struct4bytes* byval %b) { +define void @foo3(%struct8bytes8align* byval(%struct8bytes8align) %a, %struct4bytes* byval(%struct4bytes) %b) { ; CHECK-LABEL: foo3 ; CHECK: sub sp, sp, #16 ; CHECK: push {r11, lr} @@ -64,7 +64,7 @@ define void @foo3(%struct8bytes8align* byval %a, %struct4bytes* byval %b) { ; a -> r0 ; b -> r2..r3 -define void @foo4(%struct4bytes* byval %a, %struct8bytes8align* byval %b) { +define void @foo4(%struct4bytes* byval(%struct4bytes) %a, %struct8bytes8align* byval(%struct8bytes8align) %b) { ; CHECK-LABEL: foo4 ; CHECK: sub sp, sp, #16 ; CHECK: push {r11, lr} @@ -84,7 +84,7 @@ define void @foo4(%struct4bytes* byval %a, %struct8bytes8align* byval %b) { ; a -> r0..r1 ; b -> r2 ; c -> r3 -define void @foo5(%struct8bytes8align* byval %a, %struct4bytes* byval %b, %struct4bytes* byval %c) { +define void @foo5(%struct8bytes8align* byval(%struct8bytes8align) %a, %struct4bytes* byval(%struct4bytes) %b, %struct4bytes* byval(%struct4bytes) %c) { ; CHECK-LABEL: foo5 ; CHECK: sub sp, sp, #16 ; CHECK: push {r11, lr} @@ -102,7 +102,7 @@ define void @foo5(%struct8bytes8align* byval %a, %struct4bytes* byval %b, %struc ; a..c -> r0..r2 ; d -> sp+0..sp+7 -define void @foo6(i32 %a, i32 %b, i32 %c, %struct8bytes8align* byval %d) { +define void @foo6(i32 %a, i32 %b, i32 %c, %struct8bytes8align* byval(%struct8bytes8align) %d) { ; CHECK-LABEL: foo6 ; CHECK: push {r11, lr} ; CHECK: add r0, sp, #8 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir index b2c6f7d4cbb66..77eeb34ef18cf 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir @@ -640,7 +640,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 - ; CHECK: [[VFMSD:%[0-9]+]]:dpr = VFMSD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VFMSD:%[0-9]+]]:dpr = VFMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg ; CHECK: $d0 = COPY [[VFMSD]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll index 78cdd59894f2e..1c0072ef5e331 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll @@ -122,7 +122,7 @@ define i32 @test_thread_local_global() { %byval.class = type { i32 } -define void @test_byval_arg(%byval.class* byval %x) { +define void @test_byval_arg(%byval.class* byval(%byval.class) %x) { ; CHECK: remark: {{.*}} unable to lower arguments: void (%byval.class*)* ; CHECK-LABEL: warning: Instruction selection used fallback path for test_byval ret void @@ -131,7 +131,7 @@ define void @test_byval_arg(%byval.class* byval %x) { define void @test_byval_param(%byval.class* %x) { ; CHECK: remark: {{.*}} unable to translate instruction: call ; CHECK-LABEL: warning: Instruction selection used fallback path for test_byval_param - call void @test_byval_arg(%byval.class* byval %x) + call void @test_byval_arg(%byval.class* byval(%byval.class) %x) ret void } diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir index e8b9d37055bba..6bd35b05851e4 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir @@ -31,7 +31,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 - ; CHECK: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg ; CHECK: $d0 = COPY [[VFNMSD]] ; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $d0 %0:fprb(s64) = COPY $d0 diff --git a/llvm/test/CodeGen/ARM/align-sp-adjustment.ll b/llvm/test/CodeGen/ARM/align-sp-adjustment.ll index cce7b03e2362a..7840d95c151be 100644 --- a/llvm/test/CodeGen/ARM/align-sp-adjustment.ll +++ b/llvm/test/CodeGen/ARM/align-sp-adjustment.ll @@ -11,7 +11,7 @@ @.str.3 = private unnamed_addr constant [2 x i8] c"d\00", align 1 declare i32* @_Z4bar3iiPKcS0_i(i32, i32, i8*, i8*, i32) -declare void @_Z4bar1i8struct_2(i32, %struct.struct_2* byval align 4) +declare void @_Z4bar1i8struct_2(i32, %struct.struct_2* byval(%struct.struct_2) align 4) declare i32 @_Z4bar2PiPKc(i32*, i8*) define void @_Z3fooiiiii(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) #0 { @@ -38,7 +38,7 @@ for.inc: br i1 %cmp, label %for.body, label %for.end for.end: - call void @_Z4bar1i8struct_2(i32 %p4, %struct.struct_2* byval nonnull align 4 %params) #4 + call void @_Z4bar1i8struct_2(i32 %p4, %struct.struct_2* byval(%struct.struct_2) nonnull align 4 %params) #4 br label %cleanup.8 cleanup.8: diff --git a/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll b/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll index b6f3e07475683..ad19d8d1ce8f7 100644 --- a/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll +++ b/llvm/test/CodeGen/ARM/alloc-no-stack-realign.ll @@ -5,7 +5,7 @@ ; objects that are assumed to be 64-byte aligned. @T3_retval = common global <16 x float> zeroinitializer, align 16 -define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" { +define void @test1(<16 x float>* noalias sret(<16 x float>) %agg.result) nounwind ssp "no-realign-stack" { entry: ; CHECK-LABEL: test1: ; CHECK: ldr r[[R1:[0-9]+]], [pc, r[[R1]]] @@ -42,7 +42,7 @@ entry: ret void } -define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp { +define void @test2(<16 x float>* noalias sret(<16 x float>) %agg.result) nounwind ssp { entry: ; CHECK-LABEL: test2: ; CHECK: ldr r[[R1:[0-9]+]], [pc, r[[R1]]] diff --git a/llvm/test/CodeGen/ARM/alloca-align.ll b/llvm/test/CodeGen/ARM/alloca-align.ll index 3326d361c07f0..76c265abbd1a3 100644 --- a/llvm/test/CodeGen/ARM/alloca-align.ll +++ b/llvm/test/CodeGen/ARM/alloca-align.ll @@ -3,7 +3,7 @@ target triple="arm--" @glob = external global i32* -declare void @bar(i32*, [20000 x i8]* byval) +declare void @bar(i32*, [20000 x i8]* byval([20000 x i8])) ; CHECK-LABEL: foo: ; We should see the stack getting additional alignment @@ -17,7 +17,7 @@ declare void @bar(i32*, [20000 x i8]* byval) define void @foo([20000 x i8]* %addr) { %tmp = alloca [4 x i32], align 32 %tmp0 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 0 - call void @bar(i32* %tmp0, [20000 x i8]* byval %addr) + call void @bar(i32* %tmp0, [20000 x i8]* byval([20000 x i8]) %addr) ret void } diff --git a/llvm/test/CodeGen/ARM/byval-align.ll b/llvm/test/CodeGen/ARM/byval-align.ll index 8a506280dd57d..e3fe15c701066 100644 --- a/llvm/test/CodeGen/ARM/byval-align.ll +++ b/llvm/test/CodeGen/ARM/byval-align.ll @@ -6,7 +6,7 @@ ; users of byval alignments > 4, so no real calls for ABI stability. ; "byval align 16" can't fit in any regs with an i8* taking up r0. -define i32 @test_align16(i8*, [4 x i32]* byval align 16 %b) { +define i32 @test_align16(i8*, [4 x i32]* byval([4 x i32]) align 16 %b) { ; CHECK-LABEL: test_align16: ; CHECK-NOT: sub sp ; CHECK: push {r4, r7, lr} @@ -22,7 +22,7 @@ define i32 @test_align16(i8*, [4 x i32]* byval align 16 %b) { ; byval align 8 can, but we used to incorrectly set r7 here (miscalculating the ; space taken up by arg regs). -define i32 @test_align8(i8*, [4 x i32]* byval align 8 %b) { +define i32 @test_align8(i8*, [4 x i32]* byval([4 x i32]) align 8 %b) { ; CHECK-LABEL: test_align8: ; CHECK: sub sp, #8 ; CHECK: push {r4, r7, lr} @@ -40,7 +40,7 @@ define i32 @test_align8(i8*, [4 x i32]* byval align 8 %b) { ; "byval align 32" can't fit in regs no matter what: it would be misaligned ; unless the incoming stack was deliberately misaligned. -define i32 @test_align32(i8*, [4 x i32]* byval align 32 %b) { +define i32 @test_align32(i8*, [4 x i32]* byval([4 x i32]) align 32 %b) { ; CHECK-LABEL: test_align32: ; CHECK-NOT: sub sp ; CHECK: push {r4, r7, lr} @@ -67,7 +67,7 @@ define void @test_call_align16() { ; While we're here, make sure the caller also puts it at sp ; CHECK: mov r[[BASE:[0-9]+]], sp ; CHECK: vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]] - call i32 @test_align16(i8* null, [4 x i32]* byval align 16 @var) + call i32 @test_align16(i8* null, [4 x i32]* byval([4 x i32]) align 16 @var) ret void } diff --git a/llvm/test/CodeGen/ARM/byval_load_align.ll b/llvm/test/CodeGen/ARM/byval_load_align.ll index 141ead6c0ad64..eb34badc8d566 100644 --- a/llvm/test/CodeGen/ARM/byval_load_align.ll +++ b/llvm/test/CodeGen/ARM/byval_load_align.ll @@ -16,11 +16,11 @@ ; Function Attrs: nounwind ssp define void @Client() #0 { entry: - tail call void @Logger(i8 signext 97, %struct.ModuleID* byval @sID) #2 + tail call void @Logger(i8 signext 97, %struct.ModuleID* byval(%struct.ModuleID) @sID) #2 ret void } -declare void @Logger(i8 signext, %struct.ModuleID* byval) #1 +declare void @Logger(i8 signext, %struct.ModuleID* byval(%struct.ModuleID)) #1 attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/ARM/cmse-errors.ll b/llvm/test/CodeGen/ARM/cmse-errors.ll index ea7976b0fe490..80a9caa04e714 100644 --- a/llvm/test/CodeGen/ARM/cmse-errors.ll +++ b/llvm/test/CodeGen/ARM/cmse-errors.ll @@ -3,7 +3,7 @@ %struct.two_ints = type { i32, i32 } %struct.__va_list = type { i8* } -define void @test1(%struct.two_ints* noalias nocapture sret align 4 %agg.result) "cmse_nonsecure_entry" { +define void @test1(%struct.two_ints* noalias nocapture sret(%struct.two_ints) align 4 %agg.result) "cmse_nonsecure_entry" { entry: %0 = bitcast %struct.two_ints* %agg.result to i64* store i64 8589934593, i64* %0, align 4 @@ -29,7 +29,7 @@ define void @test4(void (%struct.two_ints*)* nocapture %p) { entry: %r = alloca %struct.two_ints, align 4 %0 = bitcast %struct.two_ints* %r to i8* - call void %p(%struct.two_ints* nonnull sret align 4 %r) "cmse_nonsecure_call" + call void %p(%struct.two_ints* nonnull sret(%struct.two_ints) align 4 %r) "cmse_nonsecure_call" ret void } ; CHECK: error: {{.*}}test4{{.*}}: call to non-secure function would return value through pointer diff --git a/llvm/test/CodeGen/ARM/coalesce-subregs.ll b/llvm/test/CodeGen/ARM/coalesce-subregs.ll index a11976e274486..c13af8a69cb1c 100644 --- a/llvm/test/CodeGen/ARM/coalesce-subregs.ll +++ b/llvm/test/CodeGen/ARM/coalesce-subregs.ll @@ -294,7 +294,7 @@ bb: ; The shuffle in if.else3 must be preserved even though adjustCopiesBackFrom ; is tempted to remove it. ; CHECK: vorr d -define internal void @adjustCopiesBackFrom(<2 x i64>* noalias nocapture sret %agg.result, <2 x i64> %in) { +define internal void @adjustCopiesBackFrom(<2 x i64>* noalias nocapture sret(<2 x i64>) %agg.result, <2 x i64> %in) { entry: %0 = extractelement <2 x i64> %in, i32 0 %cmp = icmp slt i64 %0, 1 diff --git a/llvm/test/CodeGen/ARM/copy-by-struct-i32.ll b/llvm/test/CodeGen/ARM/copy-by-struct-i32.ll index d6b72a2f0aff6..d3bc2d61fcb89 100644 --- a/llvm/test/CodeGen/ARM/copy-by-struct-i32.ll +++ b/llvm/test/CodeGen/ARM/copy-by-struct-i32.ll @@ -54,7 +54,7 @@ define arm_aapcscc void @s(i64* %q, %struct.anon* %p) { entry: %0 = load i64, i64* %q, align 8 %sub = add nsw i64 %0, -1 - tail call arm_aapcscc void bitcast (void (...)* @r to void (%struct.anon*, %struct.anon*, i64)*)(%struct.anon* byval nonnull align 8 %p, %struct.anon* byval nonnull align 8 %p, i64 %sub) + tail call arm_aapcscc void bitcast (void (...)* @r to void (%struct.anon*, %struct.anon*, i64)*)(%struct.anon* byval(%struct.anon) nonnull align 8 %p, %struct.anon* byval(%struct.anon) nonnull align 8 %p, i64 %sub) ret void } diff --git a/llvm/test/CodeGen/ARM/fast-isel-call.ll b/llvm/test/CodeGen/ARM/fast-isel-call.ll index 293c268c5359b..26b7f09e13fde 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-call.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-call.ll @@ -38,8 +38,8 @@ define i32 @t4(i16 zeroext %a) nounwind { } define void @foo(i8 %a, i16 %b) nounwind { -; ARM: foo -; THUMB: foo +; ARM-LABEL: foo: +; THUMB-LABEL: foo: ;; Materialize i1 1 ; ARM: movw [[REG0:r[0-9]+]], #1 ; THUMB: movs [[REG0:r[0-9]+]], #1 @@ -87,7 +87,7 @@ declare zeroext i1 @t9(); define i32 @t10() { entry: -; ARM: @t10 +; ARM-LABEL: @t10 ; ARM-DAG: movw [[R0:l?r[0-9]*]], #0 ; ARM-DAG: movw [[R1:l?r[0-9]*]], #248 ; ARM-DAG: movw [[R2:l?r[0-9]*]], #187 @@ -100,8 +100,8 @@ entry: ; ARM-DAG: and [[R3]], [[R3]], #255 ; ARM-DAG: and [[R4]], [[R4]], #255 ; ARM-DAG: str [[R4]], [sp] -; ARM-DAG: and [[R4]], [[R5]], #255 -; ARM-DAG: str [[R4]], [sp, #4] +; ARM-DAG: and [[R5]], [[R5]], #255 +; ARM-DAG: str [[R5]], [sp, #4] ; ARM: bl {{_?}}bar ; ARM-LONG-LABEL: @t10 @@ -113,7 +113,7 @@ entry: ; ARM-LONG-ELF: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}} ; ARM-LONG: blx [[R]] -; THUMB: @t10 +; THUMB-LABEL: @t10 ; THUMB-DAG: movs [[R0:l?r[0-9]*]], #0 ; THUMB-DAG: movs [[R1:l?r[0-9]*]], #248 ; THUMB-DAG: movs [[R2:l?r[0-9]*]], #187 @@ -126,8 +126,8 @@ entry: ; THUMB-DAG: and [[R3]], [[R3]], #255 ; THUMB-DAG: and [[R4]], [[R4]], #255 ; THUMB-DAG: str.w [[R4]], [sp] -; THUMB-DAG: and [[R4]], [[R5]], #255 -; THUMB-DAG: str.w [[R4]], [sp, #4] +; THUMB-DAG: and [[R5]], [[R5]], #255 +; THUMB-DAG: str.w [[R5]], [sp, #4] ; THUMB: bl {{_?}}bar ; THUMB-LONG-LABEL: @t10 ; THUMB-LONG: {{(movw)|(ldr.n)}} [[R1:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}} @@ -145,7 +145,7 @@ define i32 @bar0(i32 %i) nounwind { } define void @foo3() uwtable { -; ARM: @foo3 +; ARM-LABEL: @foo3 ; ARM: {{(movw r[0-9]+, :lower16:_?bar0)|(ldr r[0-9]+, .LCPI)}} ; ARM: {{(movt r[0-9]+, :upper16:_?bar0)|(ldr r[0-9]+, \[r[0-9]+\])}} ; ARM: movw {{r[0-9]+}}, #0 @@ -163,9 +163,9 @@ define void @foo3() uwtable { define i32 @LibCall(i32 %a, i32 %b) { entry: -; ARM: LibCall +; ARM-LABEL: LibCall: ; ARM: bl {{___udivsi3|__aeabi_uidiv}} -; ARM-LONG-LABEL: LibCall +; ARM-LONG-LABEL: LibCall: ; ARM-LONG-MACHO: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr r2, .LCPI)}} ; ARM-LONG-MACHO: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}} @@ -175,7 +175,7 @@ entry: ; ARM-LONG-ELF: movt r2, :upper16:__aeabi_uidiv ; ARM-LONG: blx r2 -; THUMB: LibCall +; THUMB-LABEL: LibCall: ; THUMB: bl {{___udivsi3|__aeabi_uidiv}} ; THUMB-LONG-LABEL: LibCall ; THUMB-LONG: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr.n r2, .LCPI)}} @@ -190,9 +190,9 @@ entry: define fastcc void @fast_callee(float %i) ssp { entry: -; ARM: fast_callee +; ARM-LABEL: fast_callee: ; ARM: vmov r0, s0 -; THUMB: fast_callee +; THUMB-LABEL: fast_callee: ; THUMB: vmov r0, s0 ; ARM-NOVFP: fast_callee ; ARM-NOVFP-NOT: s0 @@ -204,14 +204,14 @@ entry: define void @fast_caller() ssp { entry: -; ARM: fast_caller +; ARM-LABEL: fast_caller: ; ARM: vldr s0, -; THUMB: fast_caller +; THUMB-LABEL: fast_caller: ; THUMB: vldr s0, -; ARM-NOVFP: fast_caller +; ARM-NOVFP-LABEL: fast_caller: ; ARM-NOVFP: movw r0, #13107 ; ARM-NOVFP: movt r0, #16611 -; THUMB-NOVFP: fast_caller +; THUMB-NOVFP-LABEL: fast_caller: ; THUMB-NOVFP: movw r0, #13107 ; THUMB-NOVFP: movt r0, #16611 call fastcc void @fast_callee(float 0x401C666660000000) @@ -220,13 +220,13 @@ entry: define void @no_fast_callee(float %i) ssp { entry: -; ARM: no_fast_callee +; ARM-LABEL: no_fast_callee: ; ARM: vmov s0, r0 -; THUMB: no_fast_callee +; THUMB-LABEL: no_fast_callee: ; THUMB: vmov s0, r0 -; ARM-NOVFP: no_fast_callee +; ARM-NOVFP-LABEL: no_fast_callee: ; ARM-NOVFP-NOT: s0 -; THUMB-NOVFP: no_fast_callee +; THUMB-NOVFP-LABEL: no_fast_callee: ; THUMB-NOVFP-NOT: s0 call void @print(float %i) ret void @@ -234,14 +234,14 @@ entry: define void @no_fast_caller() ssp { entry: -; ARM: no_fast_caller +; ARM-LABEL: no_fast_caller: ; ARM: vmov r0, s0 -; THUMB: no_fast_caller +; THUMB-LABEL: no_fast_caller: ; THUMB: vmov r0, s0 -; ARM-NOVFP: no_fast_caller +; ARM-NOVFP-LABEL: no_fast_caller: ; ARM-NOVFP: movw r0, #13107 ; ARM-NOVFP: movt r0, #16611 -; THUMB-NOVFP: no_fast_caller +; THUMB-NOVFP-LABEL: no_fast_caller: ; THUMB-NOVFP: movw r0, #13107 ; THUMB-NOVFP: movt r0, #16611 call void @no_fast_callee(float 0x401C666660000000) @@ -251,7 +251,7 @@ entry: declare void @bar2(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) define void @call_undef_args() { -; ARM-LABEL: call_undef_args +; ARM-LABEL: call_undef_args: ; ARM: movw r0, #1 ; ARM-NEXT: movw r1, #2 ; ARM-NEXT: movw r2, #3 diff --git a/llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll b/llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll index bda4c6d47237c..13e6d12468acb 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll @@ -36,8 +36,8 @@ define void @t1() nounwind ssp { ; THUMB: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}} ; THUMB: adds r0, #5 ; THUMB: movs r1, #64 -; THUMB: and r1, r1, #255 ; THUMB: movs r2, #10 +; THUMB: and r1, r1, #255 ; THUMB: bl {{_?}}memset ; THUMB-LONG-LABEL: t1: ; THUMB-LONG: movw r3, :lower16:L_memset$non_lazy_ptr diff --git a/llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll b/llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll index 95942c271c9ca..b692b4bd6ffc2 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll @@ -106,10 +106,12 @@ entry: ; THUMB-LABEL: t12: %add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64 store i32 0, i32* %add.ptr, align 4 +; THUMB: mov [[PTR:r[0-9]+]], r0 +; THUMB: movs [[VAL:r[0-9]+]], #0 ; THUMB: movw [[REG:r[0-9]+]], #65280 ; THUMB: movt [[REG]], #65535 -; THUMB: add [[REG]], r0 -; THUMB: str r{{[0-9]}}, {{\[}}[[REG]]] +; THUMB: add [[PTR]], [[REG]] +; THUMB: str [[VAL]], {{\[}}[[PTR]]] ret void } @@ -138,10 +140,12 @@ entry: ; THUMB-LABEL: t15: %add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128 store i16 0, i16* %add.ptr, align 2 +; THUMB: mov [[PTR:r[0-9]+]], r0 +; THUMB: movs [[VAL:r[0-9]+]], #0 ; THUMB: movw [[REG:r[0-9]+]], #65280 ; THUMB: movt [[REG]], #65535 -; THUMB: add [[REG]], r0 -; THUMB: strh r{{[0-9]}}, {{\[}}[[REG]]] +; THUMB: add [[PTR]], [[REG]] +; THUMB: strh [[VAL]], {{\[}}[[PTR]]] ret void } @@ -170,9 +174,11 @@ entry: ; THUMB-LABEL: t18: %add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256 store i8 0, i8* %add.ptr, align 1 +; THUMB: mov [[PTR:r[0-9]+]], r0 +; THUMB: movs [[VAL]], #0 ; THUMB: movw [[REG:r[0-9]+]], #65280 ; THUMB: movt [[REG]], #65535 -; THUMB: add [[REG]], r0 -; THUMB: strb r{{[0-9]}}, {{\[}}[[REG]]] +; THUMB: add [[PTR]], [[REG]] +; THUMB: strb [[VAL]], {{\[}}[[PTR]]] ret void } diff --git a/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll b/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll index f49c907c4145a..f2d728c8b361b 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll @@ -4,7 +4,7 @@ define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp { entry: -; ARM: t1 +; ARM-LABEL: t1: %add.ptr = getelementptr inbounds i16, i16* %a, i64 -8 %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #-16] @@ -13,7 +13,7 @@ entry: define zeroext i16 @t2(i16* nocapture %a) nounwind uwtable readonly ssp { entry: -; ARM: t2 +; ARM-LABEL: t2: %add.ptr = getelementptr inbounds i16, i16* %a, i64 -16 %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #-32] @@ -22,7 +22,7 @@ entry: define zeroext i16 @t3(i16* nocapture %a) nounwind uwtable readonly ssp { entry: -; ARM: t3 +; ARM-LABEL: t3: %add.ptr = getelementptr inbounds i16, i16* %a, i64 -127 %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #-254] @@ -31,7 +31,7 @@ entry: define zeroext i16 @t4(i16* nocapture %a) nounwind uwtable readonly ssp { entry: -; ARM: t4 +; ARM-LABEL: t4: %add.ptr = getelementptr inbounds i16, i16* %a, i64 -128 %0 = load i16, i16* %add.ptr, align 2 ; ARM: mvn r{{[1-9]}}, #255 @@ -42,7 +42,7 @@ entry: define zeroext i16 @t5(i16* nocapture %a) nounwind uwtable readonly ssp { entry: -; ARM: t5 +; ARM-LABEL: t5: %add.ptr = getelementptr inbounds i16, i16* %a, i64 8 %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #16] @@ -51,7 +51,7 @@ entry: define zeroext i16 @t6(i16* nocapture %a) nounwind uwtable readonly ssp { entry: -; ARM: t6 +; ARM-LABEL: t6: %add.ptr = getelementptr inbounds i16, i16* %a, i64 16 %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #32] @@ -60,7 +60,7 @@ entry: define zeroext i16 @t7(i16* nocapture %a) nounwind uwtable readonly ssp { entry: -; ARM: t7 +; ARM-LABEL: t7: %add.ptr = getelementptr inbounds i16, i16* %a, i64 127 %0 = load i16, i16* %add.ptr, align 2 ; ARM: ldrh r0, [r0, #254] @@ -69,7 +69,7 @@ entry: define zeroext i16 @t8(i16* nocapture %a) nounwind uwtable readonly ssp { entry: -; ARM: t8 +; ARM-LABEL: t8: %add.ptr = getelementptr inbounds i16, i16* %a, i64 128 %0 = load i16, i16* %add.ptr, align 2 ; ARM: add r0, r0, #256 @@ -79,7 +79,7 @@ entry: define void @t9(i16* nocapture %a) nounwind uwtable ssp { entry: -; ARM: t9 +; ARM-LABEL: t9: %add.ptr = getelementptr inbounds i16, i16* %a, i64 -8 store i16 0, i16* %add.ptr, align 2 ; ARM: movw [[REG0:r[0-9]+]], #0 @@ -91,19 +91,20 @@ entry: ; strh r2, [r0, r1] define void @t10(i16* nocapture %a) nounwind uwtable ssp { entry: -; ARM: t10 +; ARM-LABEL: t10: %add.ptr = getelementptr inbounds i16, i16* %a, i64 -128 store i16 0, i16* %add.ptr, align 2 -; ARM: mvn r1, #255 -; ARM: add [[REG0:r[0-9]+]], r0, r1 +; ARM: mov r1, r0 ; ARM: movw [[REG1:r[0-9]+]], #0 +; ARM: mvn [[REG2:r[0-9]+]], #255 +; ARM: add [[REG0:r[0-9]+]], r1, [[REG2]] ; ARM: strh [[REG1]], {{\[}}[[REG0]]] ret void } define void @t11(i16* nocapture %a) nounwind uwtable ssp { entry: -; ARM: t11 +; ARM-LABEL: t11: %add.ptr = getelementptr inbounds i16, i16* %a, i64 8 store i16 0, i16* %add.ptr, align 2 ; ARM: movw [[REG1:r[0-9]+]], #0 @@ -115,18 +116,19 @@ entry: ; strh r2, [r0, r1] define void @t12(i16* nocapture %a) nounwind uwtable ssp { entry: -; ARM: t12 +; ARM-LABEL: t12: %add.ptr = getelementptr inbounds i16, i16* %a, i64 128 store i16 0, i16* %add.ptr, align 2 -; ARM: add [[REG0:r[0-9]+]], r0, #256 +; ARM: mov r1, r0 ; ARM: movw [[REG1:r[0-9]+]], #0 +; ARM: add [[REG0:r[0-9]+]], r1, #256 ; ARM: strh [[REG1]], {{\[}}[[REG0]]] ret void } define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp { entry: -; ARM: t13 +; ARM-LABEL: t13: %add.ptr = getelementptr inbounds i8, i8* %a, i64 -8 %0 = load i8, i8* %add.ptr, align 2 ; ARM: ldrsb r0, [r0, #-8] @@ -135,7 +137,7 @@ entry: define signext i8 @t14(i8* nocapture %a) nounwind uwtable readonly ssp { entry: -; ARM: t14 +; ARM-LABEL: t14: %add.ptr = getelementptr inbounds i8, i8* %a, i64 -255 %0 = load i8, i8* %add.ptr, align 2 ; ARM: ldrsb r0, [r0, #-255] @@ -144,7 +146,7 @@ entry: define signext i8 @t15(i8* nocapture %a) nounwind uwtable readonly ssp { entry: -; ARM: t15 +; ARM-LABEL: t15: %add.ptr = getelementptr inbounds i8, i8* %a, i64 -256 %0 = load i8, i8* %add.ptr, align 2 ; ARM: mvn r{{[1-9]}}, #255 diff --git a/llvm/test/CodeGen/ARM/fast-isel-select.ll b/llvm/test/CodeGen/ARM/fast-isel-select.ll index 70987422dfde7..1b6973ddb4116 100644 --- a/llvm/test/CodeGen/ARM/fast-isel-select.ll +++ b/llvm/test/CodeGen/ARM/fast-isel-select.ll @@ -5,13 +5,15 @@ define i32 @t1(i1 %c) nounwind readnone { entry: -; ARM: t1 -; ARM: tst r0, #1 +; ARM-LABEL: t1: +; ARM: mov r1, r0 ; ARM: movw r0, #10 +; ARM: tst r1, #1 ; ARM: moveq r0, #20 -; THUMB: t1 -; THUMB: tst.w r0, #1 -; THUMB: movw r0, #10 +; THUMB-LABEL: t1: +; THUMB: mov r1, r0 +; THUMB: movs r0, #10 +; THUMB: tst.w r1, #1 ; THUMB: it eq ; THUMB: moveq r0, #20 %0 = select i1 %c, i32 10, i32 20 @@ -20,10 +22,10 @@ entry: define i32 @t2(i1 %c, i32 %a) nounwind readnone { entry: -; ARM: t2 +; ARM-LABEL: t2: ; ARM: tst {{r[0-9]+}}, #1 ; ARM: moveq {{r[0-9]+}}, #20 -; THUMB-LABEL: t2 +; THUMB-LABEL: t2: ; THUMB: tst.w {{r[0-9]+}}, #1 ; THUMB: it eq ; THUMB: moveq {{r[0-9]+}}, #20 @@ -33,11 +35,11 @@ entry: define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone { entry: -; ARM: t3 +; ARM-LABEL: t3: ; ARM: tst r0, #1 ; ARM: movne r2, r1 ; ARM: add r0, r2, r1 -; THUMB: t3 +; THUMB-LABEL: t3: ; THUMB: tst.w r0, #1 ; THUMB: it ne ; THUMB: movne r2, r1 @@ -49,13 +51,15 @@ entry: define i32 @t4(i1 %c) nounwind readnone { entry: -; ARM: t4 -; ARM: tst r0, #1 +; ARM-LABEL: t4: +; ARM: mov r1, r0 ; ARM: mvn r0, #9 +; ARM: tst r1, #1 ; ARM: mvneq r0, #0 -; THUMB-LABEL: t4 -; THUMB: tst.w r0, #1 +; THUMB-LABEL: t4: +; THUMB: mov r1, r0 ; THUMB: mvn r0, #9 +; THUMB: tst.w r1, #1 ; THUMB: it eq ; THUMB: mvneq r0, #0 %0 = select i1 %c, i32 -10, i32 -1 @@ -64,10 +68,10 @@ entry: define i32 @t5(i1 %c, i32 %a) nounwind readnone { entry: -; ARM: t5 +; ARM-LABEL: t5: ; ARM: tst {{r[0-9]+}}, #1 ; ARM: mvneq {{r[0-9]+}}, #1 -; THUMB: t5 +; THUMB-LABEL: t5: ; THUMB: tst.w {{r[0-9]+}}, #1 ; THUMB: it eq ; THUMB: mvneq {{r[0-9]+}}, #1 @@ -78,10 +82,10 @@ entry: ; Check one large negative immediates. define i32 @t6(i1 %c, i32 %a) nounwind readnone { entry: -; ARM: t6 +; ARM-LABEL: t6: ; ARM: tst {{r[0-9]+}}, #1 ; ARM: mvneq {{r[0-9]+}}, #978944 -; THUMB: t6 +; THUMB-LABEL: t6: ; THUMB: tst.w {{r[0-9]+}}, #1 ; THUMB: it eq ; THUMB: mvneq {{r[0-9]+}}, #978944 diff --git a/llvm/test/CodeGen/ARM/fast-isel.ll b/llvm/test/CodeGen/ARM/fast-isel.ll index 3661beab5c028..2437bda498bad 100644 --- a/llvm/test/CodeGen/ARM/fast-isel.ll +++ b/llvm/test/CodeGen/ARM/fast-isel.ll @@ -152,7 +152,10 @@ define void @test4() { ; THUMB: ldr [[REG:r[0-9]+]], [r0] ; THUMB: ldr [[REG1:r[0-9]+]], {{\[}}[[REG]]] ; THUMB: adds [[REG1]], #1 -; THUMB: str [[REG1]], {{\[}}[[REG]]] +; THUMB: {{(movw r1, :lower16:L_test4g\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} +; THUMB: {{(movt r1, :upper16:L_test4g\$non_lazy_ptr)?}} +; THUMB: ldr [[REG2:r[0-9]+]], [r1] +; THUMB: str [[REG1]], {{\[}}[[REG2]]] ; ARM-MACHO: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}} ; ARM-MACHO: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}} @@ -163,7 +166,15 @@ define void @test4() { ; ARM: ldr [[REG1:r[0-9]+]], {{\[}}[[REG]]] ; ARM: add [[REG2:r[0-9]+]], [[REG1]], #1 -; ARM: str [[REG2]], {{\[}}[[REG]]] + +; ARM-MACHO: {{(movw r1, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM-MACHO: {{(movt r1, :upper16:L_test4g\$non_lazy_ptr)?}} +; ARM-MACHO: ldr [[REG3:r[0-9]+]], [r1] + +; ARM-ELF: movw [[REG3:r[0-9]+]], :lower16:test4g +; ARM-ELF: movt [[REG3]], :upper16:test4g + +; ARM: str [[REG2]], {{\[}}[[REG3]]] } ; ARM: @urem_fold diff --git a/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll b/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll index 03909b8005983..fe9f7b13506c1 100644 --- a/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll +++ b/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll @@ -257,8 +257,8 @@ define arm_aapcs_vfpcc void @fms1(half *%a1, half *%a2, half *%a3) { define arm_aapcs_vfpcc void @fms2(half *%a1, half *%a2, half *%a3) { ; CHECK-LABEL: fms2: ; CHECK: @ %bb.0: -; CHECK-NEXT: vldr.16 s0, [r0] -; CHECK-NEXT: vldr.16 s2, [r1] +; CHECK-NEXT: vldr.16 s0, [r1] +; CHECK-NEXT: vldr.16 s2, [r0] ; CHECK-NEXT: vldr.16 s4, [r2] ; CHECK-NEXT: vfms.f16 s4, s2, s0 ; CHECK-NEXT: vstr.16 s4, [r0] @@ -266,8 +266,8 @@ define arm_aapcs_vfpcc void @fms2(half *%a1, half *%a2, half *%a3) { ; ; DONT-FUSE-LABEL: fms2: ; DONT-FUSE: @ %bb.0: -; DONT-FUSE-NEXT: vldr.16 s0, [r0] -; DONT-FUSE-NEXT: vldr.16 s2, [r1] +; DONT-FUSE-NEXT: vldr.16 s0, [r1] +; DONT-FUSE-NEXT: vldr.16 s2, [r0] ; DONT-FUSE-NEXT: vldr.16 s4, [r2] ; DONT-FUSE-NEXT: vfms.f16 s4, s2, s0 ; DONT-FUSE-NEXT: vstr.16 s4, [r0] @@ -399,8 +399,8 @@ define arm_aapcs_vfpcc void @fnms2(half *%a1, half *%a2, half *%a3) { define arm_aapcs_vfpcc void @fnms3(half *%a1, half *%a2, half *%a3) { ; CHECK-LABEL: fnms3: ; CHECK: @ %bb.0: -; CHECK-NEXT: vldr.16 s0, [r1] -; CHECK-NEXT: vldr.16 s2, [r0] +; CHECK-NEXT: vldr.16 s0, [r0] +; CHECK-NEXT: vldr.16 s2, [r1] ; CHECK-NEXT: vldr.16 s4, [r2] ; CHECK-NEXT: vfnms.f16 s4, s2, s0 ; CHECK-NEXT: vstr.16 s4, [r0] @@ -408,8 +408,8 @@ define arm_aapcs_vfpcc void @fnms3(half *%a1, half *%a2, half *%a3) { ; ; DONT-FUSE-LABEL: fnms3: ; DONT-FUSE: @ %bb.0: -; DONT-FUSE-NEXT: vldr.16 s0, [r1] -; DONT-FUSE-NEXT: vldr.16 s2, [r0] +; DONT-FUSE-NEXT: vldr.16 s0, [r0] +; DONT-FUSE-NEXT: vldr.16 s2, [r1] ; DONT-FUSE-NEXT: vldr.16 s4, [r2] ; DONT-FUSE-NEXT: vfnms.f16 s4, s2, s0 ; DONT-FUSE-NEXT: vstr.16 s4, [r0] diff --git a/llvm/test/CodeGen/ARM/interval-update-remat.ll b/llvm/test/CodeGen/ARM/interval-update-remat.ll index 216f7e915a804..9d343321d1fe3 100644 --- a/llvm/test/CodeGen/ARM/interval-update-remat.ll +++ b/llvm/test/CodeGen/ARM/interval-update-remat.ll @@ -52,7 +52,7 @@ entry: %call5 = call %class.TestCompletionCallback.9.234.284.1309.2334* @_ZN22TestCompletionCallbackC1Ev(%class.TestCompletionCallback.9.234.284.1309.2334* nonnull %callback) %transport_socket_pool_ = getelementptr inbounds %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326, %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326* %this, i32 0, i32 0 %call6 = call i32 @_ZN29MockTransportClientSocketPool5m_fn9Ev(%class.MockTransportClientSocketPool.0.225.275.1300.2325* %transport_socket_pool_) - call void @_Z11CmpHelperEQPcS_xx(%class.AssertionResult.24.249.299.1324.2349* nonnull sret %gtest_ar, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i64 0, i64 undef) + call void @_Z11CmpHelperEQPcS_xx(%class.AssertionResult.24.249.299.1324.2349* nonnull sret(%class.AssertionResult.24.249.299.1324.2349) %gtest_ar, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i64 0, i64 undef) %tmp = load i8, i8* undef, align 4 %tobool.i = icmp eq i8 %tmp, 0 br i1 %tobool.i, label %if.else, label %if.end @@ -87,14 +87,14 @@ if.end: ; preds = %_ZN7MessageD1Ev.exi %call.i.i.i = call %class.scoped_ptr.23.248.298.1323.2348* @_ZN10scoped_ptrI25Trans_NS___1_basic_stringIciiEED2Ev(%class.scoped_ptr.23.248.298.1323.2348* %message_.i.i) call void @llvm.memset.p0i8.i32(i8* align 4 null, i8 0, i32 12, i1 false) call void @_ZN25Trans_NS___1_basic_stringIciiE5m_fn2Ev(%class.Trans_NS___1_basic_string.18.243.293.1318.2343* nonnull %ref.tmp) - call void @_Z19CreateSOCKSv5Paramsv(%class.scoped_refptr.19.244.294.1319.2344* nonnull sret %agg.tmp16) + call void @_Z19CreateSOCKSv5Paramsv(%class.scoped_refptr.19.244.294.1319.2344* nonnull sret(%class.scoped_refptr.19.244.294.1319.2344) %agg.tmp16) %callback_.i = getelementptr inbounds %class.TestCompletionCallback.9.234.284.1309.2334, %class.TestCompletionCallback.9.234.284.1309.2334* %callback, i32 0, i32 1 %pool_ = getelementptr inbounds %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326, %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326* %this, i32 0, i32 1 %tmp1 = getelementptr inbounds %class.BoundNetLog.20.245.295.1320.2345, %class.BoundNetLog.20.245.295.1320.2345* %agg.tmp18, i32 0, i32 0 store i32 0, i32* %tmp1, align 4 call void @_ZN18ClientSocketHandle5m_fn3IPiEEvRK25Trans_NS___1_basic_stringIciiE13scoped_refptr15RequestPriorityN16ClientSocketPool13RespectLimitsERiT_11BoundNetLog(%class.ClientSocketHandle.14.239.289.1314.2339* nonnull undef, %class.Trans_NS___1_basic_string.18.243.293.1318.2343* nonnull dereferenceable(12) %ref.tmp, %class.scoped_refptr.19.244.294.1319.2344* nonnull %agg.tmp16, i32 0, i32 1, i32* nonnull dereferenceable(4) %callback_.i, i32* %pool_, %class.BoundNetLog.20.245.295.1320.2345* nonnull %agg.tmp18) %call19 = call %class.BoundNetLog.20.245.295.1320.2345* @_ZN11BoundNetLogD1Ev(%class.BoundNetLog.20.245.295.1320.2345* nonnull %agg.tmp18) - call void @_Z11CmpHelperEQPcS_xx(%class.AssertionResult.24.249.299.1324.2349* nonnull sret undef, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i64 -1, i64 0) + call void @_Z11CmpHelperEQPcS_xx(%class.AssertionResult.24.249.299.1324.2349* nonnull sret(%class.AssertionResult.24.249.299.1324.2349) undef, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i64 -1, i64 0) br i1 undef, label %if.then.i.i.i.i, label %_ZN7MessageD1Ev.exit if.then.i.i.i.i: ; preds = %if.end @@ -134,7 +134,7 @@ declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #0 declare void @_ZN18ClientSocketHandle5m_fn3IPiEEvRK25Trans_NS___1_basic_stringIciiE13scoped_refptr15RequestPriorityN16ClientSocketPool13RespectLimitsERiT_11BoundNetLog(%class.ClientSocketHandle.14.239.289.1314.2339*, %class.Trans_NS___1_basic_string.18.243.293.1318.2343* dereferenceable(12), %class.scoped_refptr.19.244.294.1319.2344*, i32, i32, i32* dereferenceable(4), i32*, %class.BoundNetLog.20.245.295.1320.2345*) -declare void @_Z19CreateSOCKSv5Paramsv(%class.scoped_refptr.19.244.294.1319.2344* sret) +declare void @_Z19CreateSOCKSv5Paramsv(%class.scoped_refptr.19.244.294.1319.2344* sret(%class.scoped_refptr.19.244.294.1319.2344)) ; Function Attrs: argmemonly nounwind declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) #0 @@ -155,7 +155,7 @@ declare %"class.(anonymous namespace)::basic_iostream.22.247.297.1322.2347"* @_Z declare %class.scoped_ptr.23.248.298.1323.2348* @_ZN10scoped_ptrI25Trans_NS___1_basic_stringIciiEED2Ev(%class.scoped_ptr.23.248.298.1323.2348* readonly returned) unnamed_addr align 2 -declare void @_Z11CmpHelperEQPcS_xx(%class.AssertionResult.24.249.299.1324.2349* sret, i8*, i8*, i64, i64) +declare void @_Z11CmpHelperEQPcS_xx(%class.AssertionResult.24.249.299.1324.2349* sret(%class.AssertionResult.24.249.299.1324.2349), i8*, i8*, i64, i64) declare void @_ZN25Trans_NS___1_basic_stringIciiE5m_fn2Ev(%class.Trans_NS___1_basic_string.18.243.293.1318.2343*) diff --git a/llvm/test/CodeGen/ARM/ssp-data-layout.ll b/llvm/test/CodeGen/ARM/ssp-data-layout.ll index feb0189be9ed2..8a850c48db80b 100644 --- a/llvm/test/CodeGen/ARM/ssp-data-layout.ll +++ b/llvm/test/CodeGen/ARM/ssp-data-layout.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -frame-pointer=all -mcpu=cortex-a8 -mtriple arm-linux-gnu -target-abi=apcs -o - | FileCheck %s ; This test is fairly fragile. The goal is to ensure that "large" stack -; objects are allocated closest to the stack protector (i.e., farthest away +; objects are allocated closest to the stack protector (i.e., farthest away ; from the Stack Pointer.) In standard SSP mode this means that large (>= ; ssp-buffer-size) arrays and structures containing such arrays are ; closet to the protector. With sspstrong and sspreq this means large @@ -159,7 +159,7 @@ entry: %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* %8 = load i32, i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } @@ -170,7 +170,7 @@ entry: ; 136 large_char . arrays >= ssp-buffer-size ; 128 struct_large_char . ; 96 struct_large_nonchar . -; 84+8 small_non_char | Group 2, nested arrays, +; 84+8 small_non_char | Group 2, nested arrays, ; 90 small_char | arrays < ssp-buffer-size ; 88 struct_small_char | ; 84 struct_small_nonchar | @@ -178,7 +178,7 @@ entry: ; 76 scalar1 + Group 4, everything else ; 72 scalar2 + ; 68 scalar3 + -; +; ; CHECK: layout_sspstrong: ; CHECK: bl get_scalar1 @@ -304,14 +304,14 @@ entry: %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* %8 = load i32, i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } define void @layout_sspreq() sspreq { entry: ; Expected stack layout for sspreq is the same as sspstrong -; +; ; CHECK: layout_sspreq: ; CHECK: bl get_scalar1 @@ -437,7 +437,7 @@ entry: %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* %8 = load i32, i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } @@ -476,7 +476,7 @@ entry: %coerce.dive5 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d2, i32 0, i32 0 %5 = bitcast [2 x i16]* %coerce.dive5 to i32* %6 = load i32, i32* %5, align 1 - call void @takes_all(i64 %2, i16 %4, %struct.struct_large_nonchar* byval align 4 %d1, i32 %6, i8* null, i8* null, i32* null, i16* null, i32* null, i32 0, i32 0, i32 0) + call void @takes_all(i64 %2, i16 %4, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 4 %d1, i32 %6, i8* null, i8* null, i32* null, i16* null, i32* null, i32 0, i32 0, i32 0) ret void } @@ -519,4 +519,4 @@ declare void @end_struct_large_nonchar() declare signext i16 @get_struct_small_nonchar() declare void @end_struct_small_nonchar() -declare void @takes_all(i64, i16, %struct.struct_large_nonchar* byval align 8, i32, i8*, i8*, i32*, i16*, i32*, i32, i32, i32) +declare void @takes_all(i64, i16, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 8, i32, i8*, i8*, i32*, i16*, i32*, i32, i32, i32) diff --git a/llvm/test/CodeGen/ARM/struct-byval-frame-index.ll b/llvm/test/CodeGen/ARM/struct-byval-frame-index.ll index 0e33a9efbc9db..c398e362b1c31 100644 --- a/llvm/test/CodeGen/ARM/struct-byval-frame-index.ll +++ b/llvm/test/CodeGen/ARM/struct-byval-frame-index.ll @@ -33,6 +33,6 @@ entry: } ; Function Attrs: nounwind -declare void @RestoreMVBlock8x8(i32, i32, %structN* byval nocapture, i32) #1 +declare void @RestoreMVBlock8x8(i32, i32, %structN* byval(%structN) nocapture, i32) #1 attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/ARM/struct_byval.ll b/llvm/test/CodeGen/ARM/struct_byval.ll index 6c8f6fa0b39c3..69fdd2435594b 100644 --- a/llvm/test/CodeGen/ARM/struct_byval.ll +++ b/llvm/test/CodeGen/ARM/struct_byval.ll @@ -16,7 +16,7 @@ entry: ; CHECK: str ; CHECK-NOT:bne %st = alloca %struct.SmallStruct, align 4 - %call = call i32 @e1(%struct.SmallStruct* byval %st) + %call = call i32 @e1(%struct.SmallStruct* byval(%struct.SmallStruct) %st) ret i32 0 } @@ -37,7 +37,7 @@ entry: ; NACL: str ; NACL: bne %st = alloca %struct.LargeStruct, align 4 - %call = call i32 @e2(%struct.LargeStruct* byval %st) + %call = call i32 @e2(%struct.LargeStruct* byval(%struct.LargeStruct) %st) ret i32 0 } @@ -55,18 +55,18 @@ entry: ; NACL: vst1 ; NACL: bne %st = alloca %struct.LargeStruct, align 16 - %call = call i32 @e3(%struct.LargeStruct* byval align 16 %st) + %call = call i32 @e3(%struct.LargeStruct* byval(%struct.LargeStruct) align 16 %st) ret i32 0 } -declare i32 @e1(%struct.SmallStruct* nocapture byval %in) nounwind -declare i32 @e2(%struct.LargeStruct* nocapture byval %in) nounwind -declare i32 @e3(%struct.LargeStruct* nocapture byval align 16 %in) nounwind +declare i32 @e1(%struct.SmallStruct* nocapture byval(%struct.SmallStruct) %in) nounwind +declare i32 @e2(%struct.LargeStruct* nocapture byval(%struct.LargeStruct) %in) nounwind +declare i32 @e3(%struct.LargeStruct* nocapture byval(%struct.LargeStruct) align 16 %in) nounwind ; rdar://12442472 ; We can't do tail call since address of s is passed to the callee and part of ; s is in caller's local frame. -define void @f3(%struct.SmallStruct* nocapture byval %s) nounwind optsize { +define void @f3(%struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize { ; CHECK-LABEL: f3 ; CHECK: bl _consumestruct entry: @@ -75,7 +75,7 @@ entry: ret void } -define void @f4(%struct.SmallStruct* nocapture byval %s) nounwind optsize { +define void @f4(%struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize { ; CHECK-LABEL: f4 ; CHECK: bl _consumestruct entry: @@ -86,7 +86,7 @@ entry: } ; We can do tail call here since s is in the incoming argument area. -define void @f5(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize { +define void @f5(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize { ; CHECK-LABEL: f5 ; CHECK: b{{(\.w)?}} _consumestruct entry: @@ -95,7 +95,7 @@ entry: ret void } -define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize { +define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval(%struct.SmallStruct) %s) nounwind optsize { ; CHECK-LABEL: f6 ; CHECK: b{{(\.w)?}} _consumestruct entry: @@ -110,12 +110,12 @@ declare void @consumestruct(i8* nocapture %structp, i32 %structsize) nounwind ; PR17309 %struct.I.8 = type { [10 x i32], [3 x i8] } -declare void @use_I(%struct.I.8* byval) +declare void @use_I(%struct.I.8* byval(%struct.I.8)) define void @test_I_16() { ; CHECK-LABEL: test_I_16 ; CHECK: ldrb ; CHECK: strb entry: - call void @use_I(%struct.I.8* byval align 16 undef) + call void @use_I(%struct.I.8* byval(%struct.I.8) align 16 undef) ret void } diff --git a/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll b/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll index 1ff8a39fbb8e2..eb1e710ae6c11 100644 --- a/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll +++ b/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll @@ -25,33 +25,33 @@ ;cleanup if the number of bytes does not divide evenly by the store size %struct.A = type <{ [ 10 x i32 ] }> ; 40 bytes -declare void @use_A(%struct.A* byval) +declare void @use_A(%struct.A* byval(%struct.A)) %struct.B = type <{ [ 10 x i32 ], i8 }> ; 41 bytes -declare void @use_B(%struct.B* byval) +declare void @use_B(%struct.B* byval(%struct.B)) %struct.C = type <{ [ 10 x i32 ], [ 3 x i8 ] }> ; 43 bytes -declare void @use_C(%struct.C* byval) +declare void @use_C(%struct.C* byval(%struct.C)) %struct.D = type <{ [ 100 x i32 ] }> ; 400 bytes -declare void @use_D(%struct.D* byval) +declare void @use_D(%struct.D* byval(%struct.D)) %struct.E = type <{ [ 100 x i32 ], i8 }> ; 401 bytes -declare void @use_E(%struct.E* byval) +declare void @use_E(%struct.E* byval(%struct.E)) %struct.F = type <{ [ 100 x i32 ], [ 3 x i8 ] }> ; 403 bytes -declare void @use_F(%struct.F* byval) +declare void @use_F(%struct.F* byval(%struct.F)) %struct.G = type { [ 10 x i32 ] } ; 40 bytes -declare void @use_G(%struct.G* byval) +declare void @use_G(%struct.G* byval(%struct.G)) %struct.H = type { [ 10 x i32 ], i8 } ; 41 bytes -declare void @use_H(%struct.H* byval) +declare void @use_H(%struct.H* byval(%struct.H)) %struct.I = type { [ 10 x i32 ], [ 3 x i8 ] } ; 43 bytes -declare void @use_I(%struct.I* byval) +declare void @use_I(%struct.I* byval(%struct.I)) %struct.J = type { [ 100 x i32 ] } ; 400 bytes -declare void @use_J(%struct.J* byval) +declare void @use_J(%struct.J* byval(%struct.J)) %struct.K = type { [ 100 x i32 ], i8 } ; 401 bytes -declare void @use_K(%struct.K* byval) +declare void @use_K(%struct.K* byval(%struct.K)) %struct.L = type { [ 100 x i32 ], [ 3 x i8 ] } ; 403 bytes -declare void @use_L(%struct.L* byval) +declare void @use_L(%struct.L* byval(%struct.L)) %struct.M = type { [ 64 x i8 ] } ; 64 bytes -declare void @use_M(%struct.M* byval) +declare void @use_M(%struct.M* byval(%struct.M)) %struct.N = type { [ 128 x i8 ] } ; 128 bytes -declare void @use_N(%struct.N* byval) +declare void @use_N(%struct.N* byval(%struct.N)) ;ARM-LABEL: : ;THUMB2-LABEL: : @@ -71,7 +71,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.A, align 1 - call void @use_A(%struct.A* byval align 1 %a) + call void @use_A(%struct.A* byval(%struct.A) align 1 %a) ret void } ;ARM-LABEL: : @@ -92,7 +92,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.A, align 2 - call void @use_A(%struct.A* byval align 2 %a) + call void @use_A(%struct.A* byval(%struct.A) align 2 %a) ret void } ;ARM-LABEL: : @@ -113,7 +113,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.A, align 4 - call void @use_A(%struct.A* byval align 4 %a) + call void @use_A(%struct.A* byval(%struct.A) align 4 %a) ret void } ;ARM-LABEL: : @@ -135,7 +135,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.A, align 8 - call void @use_A(%struct.A* byval align 8 %a) + call void @use_A(%struct.A* byval(%struct.A) align 8 %a) ret void } ;ARM-LABEL: : @@ -159,7 +159,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.A, align 16 - call void @use_A(%struct.A* byval align 16 %a) + call void @use_A(%struct.A* byval(%struct.A) align 16 %a) ret void } ;ARM-LABEL: : @@ -180,7 +180,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.B, align 1 - call void @use_B(%struct.B* byval align 1 %a) + call void @use_B(%struct.B* byval(%struct.B) align 1 %a) ret void } ;ARM-LABEL: : @@ -205,7 +205,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.B, align 2 - call void @use_B(%struct.B* byval align 2 %a) + call void @use_B(%struct.B* byval(%struct.B) align 2 %a) ret void } ;ARM-LABEL: : @@ -230,7 +230,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.B, align 4 - call void @use_B(%struct.B* byval align 4 %a) + call void @use_B(%struct.B* byval(%struct.B) align 4 %a) ret void } ;ARM-LABEL: : @@ -256,7 +256,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.B, align 8 - call void @use_B(%struct.B* byval align 8 %a) + call void @use_B(%struct.B* byval(%struct.B) align 8 %a) ret void } ;ARM-LABEL: : @@ -282,7 +282,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.B, align 16 - call void @use_B(%struct.B* byval align 16 %a) + call void @use_B(%struct.B* byval(%struct.B) align 16 %a) ret void } ;ARM-LABEL: : @@ -303,7 +303,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.C, align 1 - call void @use_C(%struct.C* byval align 1 %a) + call void @use_C(%struct.C* byval(%struct.C) align 1 %a) ret void } ;ARM-LABEL: : @@ -328,7 +328,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.C, align 2 - call void @use_C(%struct.C* byval align 2 %a) + call void @use_C(%struct.C* byval(%struct.C) align 2 %a) ret void } ;ARM-LABEL: : @@ -354,7 +354,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.C, align 4 - call void @use_C(%struct.C* byval align 4 %a) + call void @use_C(%struct.C* byval(%struct.C) align 4 %a) ret void } ;ARM-LABEL: : @@ -381,7 +381,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.C, align 8 - call void @use_C(%struct.C* byval align 8 %a) + call void @use_C(%struct.C* byval(%struct.C) align 8 %a) ret void } ;ARM-LABEL: : @@ -408,7 +408,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.C, align 16 - call void @use_C(%struct.C* byval align 16 %a) + call void @use_C(%struct.C* byval(%struct.C) align 16 %a) ret void } ;ARM-LABEL: : @@ -433,7 +433,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.D, align 1 - call void @use_D(%struct.D* byval align 1 %a) + call void @use_D(%struct.D* byval(%struct.D) align 1 %a) ret void } ;ARM-LABEL: : @@ -458,7 +458,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.D, align 2 - call void @use_D(%struct.D* byval align 2 %a) + call void @use_D(%struct.D* byval(%struct.D) align 2 %a) ret void } ;ARM-LABEL: : @@ -483,7 +483,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.D, align 4 - call void @use_D(%struct.D* byval align 4 %a) + call void @use_D(%struct.D* byval(%struct.D) align 4 %a) ret void } ;ARM-LABEL: : @@ -509,7 +509,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.D, align 8 - call void @use_D(%struct.D* byval align 8 %a) + call void @use_D(%struct.D* byval(%struct.D) align 8 %a) ret void } ;ARM-LABEL: : @@ -535,7 +535,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.D, align 16 - call void @use_D(%struct.D* byval align 16 %a) + call void @use_D(%struct.D* byval(%struct.D) align 16 %a) ret void } ;ARM-LABEL: : @@ -560,7 +560,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.E, align 1 - call void @use_E(%struct.E* byval align 1 %a) + call void @use_E(%struct.E* byval(%struct.E) align 1 %a) ret void } ;ARM-LABEL: : @@ -589,7 +589,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.E, align 2 - call void @use_E(%struct.E* byval align 2 %a) + call void @use_E(%struct.E* byval(%struct.E) align 2 %a) ret void } ;ARM-LABEL: : @@ -618,7 +618,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.E, align 4 - call void @use_E(%struct.E* byval align 4 %a) + call void @use_E(%struct.E* byval(%struct.E) align 4 %a) ret void } ;ARM-LABEL: : @@ -648,7 +648,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.E, align 8 - call void @use_E(%struct.E* byval align 8 %a) + call void @use_E(%struct.E* byval(%struct.E) align 8 %a) ret void } ;ARM-LABEL: : @@ -678,7 +678,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.E, align 16 - call void @use_E(%struct.E* byval align 16 %a) + call void @use_E(%struct.E* byval(%struct.E) align 16 %a) ret void } ;ARM-LABEL: : @@ -703,7 +703,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.F, align 1 - call void @use_F(%struct.F* byval align 1 %a) + call void @use_F(%struct.F* byval(%struct.F) align 1 %a) ret void } ;ARM-LABEL: : @@ -732,7 +732,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.F, align 2 - call void @use_F(%struct.F* byval align 2 %a) + call void @use_F(%struct.F* byval(%struct.F) align 2 %a) ret void } ;ARM-LABEL: : @@ -762,7 +762,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.F, align 4 - call void @use_F(%struct.F* byval align 4 %a) + call void @use_F(%struct.F* byval(%struct.F) align 4 %a) ret void } ;ARM-LABEL: : @@ -793,7 +793,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.F, align 8 - call void @use_F(%struct.F* byval align 8 %a) + call void @use_F(%struct.F* byval(%struct.F) align 8 %a) ret void } ;ARM-LABEL: : @@ -824,7 +824,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.F, align 16 - call void @use_F(%struct.F* byval align 16 %a) + call void @use_F(%struct.F* byval(%struct.F) align 16 %a) ret void } ;ARM-LABEL: : @@ -845,7 +845,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.G, align 1 - call void @use_G(%struct.G* byval align 1 %a) + call void @use_G(%struct.G* byval(%struct.G) align 1 %a) ret void } ;ARM-LABEL: : @@ -866,7 +866,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.G, align 2 - call void @use_G(%struct.G* byval align 2 %a) + call void @use_G(%struct.G* byval(%struct.G) align 2 %a) ret void } ;ARM-LABEL: : @@ -887,7 +887,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.G, align 4 - call void @use_G(%struct.G* byval align 4 %a) + call void @use_G(%struct.G* byval(%struct.G) align 4 %a) ret void } ;ARM-LABEL: : @@ -909,7 +909,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.G, align 8 - call void @use_G(%struct.G* byval align 8 %a) + call void @use_G(%struct.G* byval(%struct.G) align 8 %a) ret void } ;ARM-LABEL: : @@ -931,7 +931,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.G, align 16 - call void @use_G(%struct.G* byval align 16 %a) + call void @use_G(%struct.G* byval(%struct.G) align 16 %a) ret void } ;ARM-LABEL: : @@ -952,7 +952,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.H, align 1 - call void @use_H(%struct.H* byval align 1 %a) + call void @use_H(%struct.H* byval(%struct.H) align 1 %a) ret void } ;ARM-LABEL: : @@ -973,7 +973,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.H, align 2 - call void @use_H(%struct.H* byval align 2 %a) + call void @use_H(%struct.H* byval(%struct.H) align 2 %a) ret void } ;ARM-LABEL: : @@ -994,7 +994,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.H, align 4 - call void @use_H(%struct.H* byval align 4 %a) + call void @use_H(%struct.H* byval(%struct.H) align 4 %a) ret void } ;ARM-LABEL: : @@ -1016,7 +1016,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.H, align 8 - call void @use_H(%struct.H* byval align 8 %a) + call void @use_H(%struct.H* byval(%struct.H) align 8 %a) ret void } ;ARM-LABEL: : @@ -1038,7 +1038,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.H, align 16 - call void @use_H(%struct.H* byval align 16 %a) + call void @use_H(%struct.H* byval(%struct.H) align 16 %a) ret void } ;ARM-LABEL: : @@ -1059,7 +1059,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.I, align 1 - call void @use_I(%struct.I* byval align 1 %a) + call void @use_I(%struct.I* byval(%struct.I) align 1 %a) ret void } ;ARM-LABEL: : @@ -1080,7 +1080,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.I, align 2 - call void @use_I(%struct.I* byval align 2 %a) + call void @use_I(%struct.I* byval(%struct.I) align 2 %a) ret void } ;ARM-LABEL: : @@ -1101,7 +1101,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.I, align 4 - call void @use_I(%struct.I* byval align 4 %a) + call void @use_I(%struct.I* byval(%struct.I) align 4 %a) ret void } ;ARM-LABEL: : @@ -1123,7 +1123,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.I, align 8 - call void @use_I(%struct.I* byval align 8 %a) + call void @use_I(%struct.I* byval(%struct.I) align 8 %a) ret void } ;ARM-LABEL: : @@ -1145,7 +1145,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.I, align 16 - call void @use_I(%struct.I* byval align 16 %a) + call void @use_I(%struct.I* byval(%struct.I) align 16 %a) ret void } ;ARM-LABEL: : @@ -1170,7 +1170,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.J, align 1 - call void @use_J(%struct.J* byval align 1 %a) + call void @use_J(%struct.J* byval(%struct.J) align 1 %a) ret void } ;ARM-LABEL: : @@ -1195,7 +1195,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.J, align 2 - call void @use_J(%struct.J* byval align 2 %a) + call void @use_J(%struct.J* byval(%struct.J) align 2 %a) ret void } ;ARM-LABEL: : @@ -1220,7 +1220,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.J, align 4 - call void @use_J(%struct.J* byval align 4 %a) + call void @use_J(%struct.J* byval(%struct.J) align 4 %a) ret void } ;ARM-LABEL: : @@ -1246,7 +1246,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.J, align 8 - call void @use_J(%struct.J* byval align 8 %a) + call void @use_J(%struct.J* byval(%struct.J) align 8 %a) ret void } ;ARM-LABEL: : @@ -1272,7 +1272,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.J, align 16 - call void @use_J(%struct.J* byval align 16 %a) + call void @use_J(%struct.J* byval(%struct.J) align 16 %a) ret void } ;ARM-LABEL: : @@ -1297,7 +1297,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.K, align 1 - call void @use_K(%struct.K* byval align 1 %a) + call void @use_K(%struct.K* byval(%struct.K) align 1 %a) ret void } ;ARM-LABEL: : @@ -1322,7 +1322,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.K, align 2 - call void @use_K(%struct.K* byval align 2 %a) + call void @use_K(%struct.K* byval(%struct.K) align 2 %a) ret void } ;ARM-LABEL: : @@ -1347,7 +1347,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.K, align 4 - call void @use_K(%struct.K* byval align 4 %a) + call void @use_K(%struct.K* byval(%struct.K) align 4 %a) ret void } ;ARM-LABEL: : @@ -1373,7 +1373,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.K, align 8 - call void @use_K(%struct.K* byval align 8 %a) + call void @use_K(%struct.K* byval(%struct.K) align 8 %a) ret void } ;ARM-LABEL: : @@ -1399,7 +1399,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.K, align 16 - call void @use_K(%struct.K* byval align 16 %a) + call void @use_K(%struct.K* byval(%struct.K) align 16 %a) ret void } ;ARM-LABEL: : @@ -1424,7 +1424,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 entry: %a = alloca %struct.L, align 1 - call void @use_L(%struct.L* byval align 1 %a) + call void @use_L(%struct.L* byval(%struct.L) align 1 %a) ret void } ;ARM-LABEL: : @@ -1449,7 +1449,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 entry: %a = alloca %struct.L, align 2 - call void @use_L(%struct.L* byval align 2 %a) + call void @use_L(%struct.L* byval(%struct.L) align 2 %a) ret void } ;ARM-LABEL: : @@ -1474,7 +1474,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 entry: %a = alloca %struct.L, align 4 - call void @use_L(%struct.L* byval align 4 %a) + call void @use_L(%struct.L* byval(%struct.L) align 4 %a) ret void } ;ARM-LABEL: : @@ -1500,7 +1500,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.L, align 8 - call void @use_L(%struct.L* byval align 8 %a) + call void @use_L(%struct.L* byval(%struct.L) align 8 %a) ret void } ;ARM-LABEL: : @@ -1526,7 +1526,7 @@ declare void @use_N(%struct.N* byval) ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [{{.*}}]! entry: %a = alloca %struct.L, align 16 - call void @use_L(%struct.L* byval align 16 %a) + call void @use_L(%struct.L* byval(%struct.L) align 16 %a) ret void } ;V8MBASE-LABEL: : @@ -1537,7 +1537,7 @@ declare void @use_N(%struct.N* byval) ;V8MBASE-NOT: movw entry: %a = alloca %struct.M, align 1 - call void @use_M(%struct.M* byval align 1 %a) + call void @use_M(%struct.M* byval(%struct.M) align 1 %a) ret void } ;V8MBASE-LABEL: : @@ -1547,6 +1547,6 @@ declare void @use_N(%struct.N* byval) ;V8MBASE-NOT: b #{{[0-9]+}} entry: %a = alloca %struct.N, align 1 - call void @use_N(%struct.N* byval align 1 %a) + call void @use_N(%struct.N* byval(%struct.N) align 1 %a) ret void } diff --git a/llvm/test/CodeGen/ARM/swifterror.ll b/llvm/test/CodeGen/ARM/swifterror.ll index 7968230ccab2e..bdd1bc70006ed 100644 --- a/llvm/test/CodeGen/ARM/swifterror.ll +++ b/llvm/test/CodeGen/ARM/swifterror.ll @@ -221,7 +221,7 @@ bb_end: ; "foo_sret" is a function that takes a swifterror parameter, it also has a sret ; parameter. -define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { +define void @foo_sret(%struct.S* sret(%struct.S) %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { ; CHECK-APPLE-LABEL: foo_sret: ; CHECK-APPLE: mov [[SRET:r[0-9]+]], r0 ; CHECK-APPLE: mov r0, #16 @@ -286,7 +286,7 @@ entry: %s = alloca %struct.S, align 8 %error_ptr_ref = alloca swifterror %swift_error* store %swift_error* null, %swift_error** %error_ptr_ref - call void @foo_sret(%struct.S* sret %s, i32 1, %swift_error** swifterror %error_ptr_ref) + call void @foo_sret(%struct.S* sret(%struct.S) %s, i32 1, %swift_error** swifterror %error_ptr_ref) %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null %tmp = bitcast %swift_error* %error_from_foo to i8* diff --git a/llvm/test/CodeGen/ARM/swiftself.ll b/llvm/test/CodeGen/ARM/swiftself.ll index 6db0ae8114ff1..3878b85a8aded 100644 --- a/llvm/test/CodeGen/ARM/swiftself.ll +++ b/llvm/test/CodeGen/ARM/swiftself.ll @@ -73,7 +73,7 @@ declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself) ; OPT-DAG: ldr r10, [r10] ; OPT: bl {{_?}}thisreturn_attribute ; OPT: str r0, {{\[}}[[CSREG]] -define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret, i8** noalias nocapture readonly swiftself) { +define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret(i8**), i8** noalias nocapture readonly swiftself) { entry: %2 = load i8*, i8** %1, align 8 %3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2) diff --git a/llvm/test/CodeGen/ARM/vlddup.ll b/llvm/test/CodeGen/ARM/vlddup.ll index 25637540befe0..53f996d24ce4c 100644 --- a/llvm/test/CodeGen/ARM/vlddup.ll +++ b/llvm/test/CodeGen/ARM/vlddup.ll @@ -222,7 +222,7 @@ define <8 x i8> @vld2dupi8(i8* %A) nounwind { ret <8 x i8> %tmp5 } -define void @vld2dupi8_preinc(%struct.__neon_int8x8x2_t* noalias nocapture sret %agg.result, i8** noalias nocapture %a, i32 %b) nounwind { +define void @vld2dupi8_preinc(%struct.__neon_int8x8x2_t* noalias nocapture sret(%struct.__neon_int8x8x2_t) %agg.result, i8** noalias nocapture %a, i32 %b) nounwind { ;CHECK-LABEL: vld2dupi8_preinc: ;CHECK: vld2.8 {d16[], d17[]}, [r2] entry: @@ -241,7 +241,7 @@ entry: ret void } -define void @vld2dupi8_postinc_fixed(%struct.__neon_int8x8x2_t* noalias nocapture sret %agg.result, i8** noalias nocapture %a) nounwind { +define void @vld2dupi8_postinc_fixed(%struct.__neon_int8x8x2_t* noalias nocapture sret(%struct.__neon_int8x8x2_t) %agg.result, i8** noalias nocapture %a) nounwind { entry: ;CHECK-LABEL: vld2dupi8_postinc_fixed: ;CHECK: vld2.8 {d16[], d17[]}, [r2]! @@ -260,7 +260,7 @@ entry: ret void } -define void @vld2dupi8_postinc_variable(%struct.__neon_int8x8x2_t* noalias nocapture sret %agg.result, i8** noalias nocapture %a, i32 %n) nounwind { +define void @vld2dupi8_postinc_variable(%struct.__neon_int8x8x2_t* noalias nocapture sret(%struct.__neon_int8x8x2_t) %agg.result, i8** noalias nocapture %a, i32 %n) nounwind { entry: ;CHECK-LABEL: vld2dupi8_postinc_variable: ;CHECK: vld2.8 {d16[], d17[]}, [r3], r2 diff --git a/llvm/test/CodeGen/ARM/vmov.ll b/llvm/test/CodeGen/ARM/vmov.ll index 995e015b4b819..694ffb1d0ecd1 100644 --- a/llvm/test/CodeGen/ARM/vmov.ll +++ b/llvm/test/CodeGen/ARM/vmov.ll @@ -228,7 +228,7 @@ define arm_aapcs_vfpcc <2 x i64> @v_movQi64() nounwind { ; Check for correct assembler printing for immediate values. %struct.int8x8_t = type { <8 x i8> } -define arm_aapcs_vfpcc void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { +define arm_aapcs_vfpcc void @vdupn128(%struct.int8x8_t* noalias nocapture sret(%struct.int8x8_t) %agg.result) nounwind { ; CHECK-LABEL: vdupn128: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmov.i8 d16, #0x80 @@ -240,7 +240,7 @@ entry: ret void } -define arm_aapcs_vfpcc void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { +define arm_aapcs_vfpcc void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret(%struct.int8x8_t) %agg.result) nounwind { ; CHECK-LABEL: vdupnneg75: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmov.i8 d16, #0xb5 diff --git a/llvm/test/CodeGen/BPF/adjust-opt-icmp1.ll b/llvm/test/CodeGen/BPF/adjust-opt-icmp1.ll index bb651f4ea57ad..6eea4d2f4618c 100644 --- a/llvm/test/CodeGen/BPF/adjust-opt-icmp1.ll +++ b/llvm/test/CodeGen/BPF/adjust-opt-icmp1.ll @@ -1,7 +1,11 @@ ; RUN: opt -O2 -mtriple=bpf-pc-linux %s | llvm-dis > %t1 ; RUN: llc %t1 -o - | FileCheck -check-prefixes=CHECK %s +; RUN: opt -passes='default' -mtriple=bpf-pc-linux %s | llvm-dis > %t1 +; RUN: llc %t1 -o - | FileCheck -check-prefixes=CHECK %s ; RUN: opt -O2 -mtriple=bpf-pc-linux -bpf-disable-serialize-icmp %s | llvm-dis > %t1 ; RUN: llc %t1 -o - | FileCheck -check-prefixes=CHECK-DISABLE %s +; RUN: opt -passes='default' -mtriple=bpf-pc-linux -bpf-disable-serialize-icmp %s | llvm-dis > %t1 +; RUN: llc %t1 -o - | FileCheck -check-prefixes=CHECK-DISABLE %s ; ; Source: ; int foo(); diff --git a/llvm/test/CodeGen/BPF/byval.ll b/llvm/test/CodeGen/BPF/byval.ll index 2d2e8d289d6f4..b8ae806c092ff 100644 --- a/llvm/test/CodeGen/BPF/byval.ll +++ b/llvm/test/CodeGen/BPF/byval.ll @@ -17,11 +17,11 @@ entry: %arrayinit.start = getelementptr inbounds %struct.S, %struct.S* %.compoundliteral, i64 0, i32 0, i64 3 %scevgep4 = bitcast i32* %arrayinit.start to i8* call void @llvm.memset.p0i8.i64(i8* align 4 %scevgep4, i8 0, i64 28, i1 false) - call void @foo(i32 %a, %struct.S* byval align 8 %.compoundliteral) #3 + call void @foo(i32 %a, %struct.S* byval(%struct.S) align 8 %.compoundliteral) #3 ret void } -declare void @foo(i32, %struct.S* byval align 8) #1 +declare void @foo(i32, %struct.S* byval(%struct.S) align 8) #1 ; Function Attrs: nounwind declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) #3 diff --git a/llvm/test/CodeGen/Generic/2010-11-04-BigByval.ll b/llvm/test/CodeGen/Generic/2010-11-04-BigByval.ll index df2ca4c18a059..39b98a77552a4 100644 --- a/llvm/test/CodeGen/Generic/2010-11-04-BigByval.ll +++ b/llvm/test/CodeGen/Generic/2010-11-04-BigByval.ll @@ -3,9 +3,9 @@ %big = type [131072 x i8] -declare void @foo(%big* byval align 1) +declare void @foo(%big* byval(%big) align 1) -define void @bar(%big* byval align 1 %x) { - call void @foo(%big* byval align 1 %x) +define void @bar(%big* byval(%big) align 1 %x) { + call void @foo(%big* byval(%big) align 1 %x) ret void } diff --git a/llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll index bd5ca331e750e..e3f14966be33e 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll @@ -3,7 +3,7 @@ ; minb ; CHECK: test_00: -; CHECK: v0.b = vmin(v1.b,v0.b) +; CHECK: v0.b = vmin(v0.b,v1.b) define <128 x i8> @test_00(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp slt <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1 @@ -27,7 +27,7 @@ define <128 x i8> @test_02(<128 x i8> %v0, <128 x i8> %v1) #0 { } ; CHECK: test_03: -; CHECK: v0.b = vmin(v1.b,v0.b) +; CHECK: v0.b = vmin(v0.b,v1.b) define <128 x i8> @test_03(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp sge <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0 @@ -37,7 +37,7 @@ define <128 x i8> @test_03(<128 x i8> %v0, <128 x i8> %v1) #0 { ; maxb ; CHECK: test_04: -; CHECK: v0.b = vmax(v1.b,v0.b) +; CHECK: v0.b = vmax(v0.b,v1.b) define <128 x i8> @test_04(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp slt <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0 @@ -61,7 +61,7 @@ define <128 x i8> @test_06(<128 x i8> %v0, <128 x i8> %v1) #0 { } ; CHECK: test_07: -; CHECK: v0.b = vmax(v1.b,v0.b) +; CHECK: v0.b = vmax(v0.b,v1.b) define <128 x i8> @test_07(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp sge <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1 @@ -71,7 +71,7 @@ define <128 x i8> @test_07(<128 x i8> %v0, <128 x i8> %v1) #0 { ; minub ; CHECK: test_08: -; CHECK: v0.ub = vmin(v1.ub,v0.ub) +; CHECK: v0.ub = vmin(v0.ub,v1.ub) define <128 x i8> @test_08(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp ult <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1 @@ -95,7 +95,7 @@ define <128 x i8> @test_0a(<128 x i8> %v0, <128 x i8> %v1) #0 { } ; CHECK: test_0b: -; CHECK: v0.ub = vmin(v1.ub,v0.ub) +; CHECK: v0.ub = vmin(v0.ub,v1.ub) define <128 x i8> @test_0b(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp uge <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0 @@ -105,7 +105,7 @@ define <128 x i8> @test_0b(<128 x i8> %v0, <128 x i8> %v1) #0 { ; maxub ; CHECK: test_0c: -; CHECK: v0.ub = vmax(v1.ub,v0.ub) +; CHECK: v0.ub = vmax(v0.ub,v1.ub) define <128 x i8> @test_0c(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp ult <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0 @@ -129,7 +129,7 @@ define <128 x i8> @test_0e(<128 x i8> %v0, <128 x i8> %v1) #0 { } ; CHECK: test_0f: -; CHECK: v0.ub = vmax(v1.ub,v0.ub) +; CHECK: v0.ub = vmax(v0.ub,v1.ub) define <128 x i8> @test_0f(<128 x i8> %v0, <128 x i8> %v1) #0 { %t0 = icmp uge <128 x i8> %v0, %v1 %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1 @@ -139,7 +139,7 @@ define <128 x i8> @test_0f(<128 x i8> %v0, <128 x i8> %v1) #0 { ; minh ; CHECK: test_10: -; CHECK: v0.h = vmin(v1.h,v0.h) +; CHECK: v0.h = vmin(v0.h,v1.h) define <64 x i16> @test_10(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp slt <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1 @@ -163,7 +163,7 @@ define <64 x i16> @test_12(<64 x i16> %v0, <64 x i16> %v1) #0 { } ; CHECK: test_13: -; CHECK: v0.h = vmin(v1.h,v0.h) +; CHECK: v0.h = vmin(v0.h,v1.h) define <64 x i16> @test_13(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp sge <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v1, <64 x i16> %v0 @@ -173,7 +173,7 @@ define <64 x i16> @test_13(<64 x i16> %v0, <64 x i16> %v1) #0 { ; maxh ; CHECK: test_14: -; CHECK: v0.h = vmax(v1.h,v0.h) +; CHECK: v0.h = vmax(v0.h,v1.h) define <64 x i16> @test_14(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp slt <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v1, <64 x i16> %v0 @@ -197,7 +197,7 @@ define <64 x i16> @test_16(<64 x i16> %v0, <64 x i16> %v1) #0 { } ; CHECK: test_17: -; CHECK: v0.h = vmax(v1.h,v0.h) +; CHECK: v0.h = vmax(v0.h,v1.h) define <64 x i16> @test_17(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp sge <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1 @@ -207,7 +207,7 @@ define <64 x i16> @test_17(<64 x i16> %v0, <64 x i16> %v1) #0 { ; minuh ; CHECK: test_18: -; CHECK: v0.uh = vmin(v1.uh,v0.uh) +; CHECK: v0.uh = vmin(v0.uh,v1.uh) define <64 x i16> @test_18(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp ult <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1 @@ -231,7 +231,7 @@ define <64 x i16> @test_1a(<64 x i16> %v0, <64 x i16> %v1) #0 { } ; CHECK: test_1b: -; CHECK: v0.uh = vmin(v1.uh,v0.uh) +; CHECK: v0.uh = vmin(v0.uh,v1.uh) define <64 x i16> @test_1b(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp uge <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v1, <64 x i16> %v0 @@ -241,7 +241,7 @@ define <64 x i16> @test_1b(<64 x i16> %v0, <64 x i16> %v1) #0 { ; maxuh ; CHECK: test_1c: -; CHECK: v0.uh = vmax(v1.uh,v0.uh) +; CHECK: v0.uh = vmax(v0.uh,v1.uh) define <64 x i16> @test_1c(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp ult <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v1, <64 x i16> %v0 @@ -265,7 +265,7 @@ define <64 x i16> @test_1e(<64 x i16> %v0, <64 x i16> %v1) #0 { } ; CHECK: test_1f: -; CHECK: v0.uh = vmax(v1.uh,v0.uh) +; CHECK: v0.uh = vmax(v0.uh,v1.uh) define <64 x i16> @test_1f(<64 x i16> %v0, <64 x i16> %v1) #0 { %t0 = icmp uge <64 x i16> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i16> %v0, <64 x i16> %v1 @@ -275,7 +275,7 @@ define <64 x i16> @test_1f(<64 x i16> %v0, <64 x i16> %v1) #0 { ; minw ; CHECK: test_20: -; CHECK: v0.w = vmin(v1.w,v0.w) +; CHECK: v0.w = vmin(v0.w,v1.w) define <32 x i32> @test_20(<32 x i32> %v0, <32 x i32> %v1) #0 { %t0 = icmp slt <32 x i32> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1 @@ -299,7 +299,7 @@ define <32 x i32> @test_22(<32 x i32> %v0, <32 x i32> %v1) #0 { } ; CHECK: test_23: -; CHECK: v0.w = vmin(v1.w,v0.w) +; CHECK: v0.w = vmin(v0.w,v1.w) define <32 x i32> @test_23(<32 x i32> %v0, <32 x i32> %v1) #0 { %t0 = icmp sge <32 x i32> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i32> %v1, <32 x i32> %v0 @@ -309,7 +309,7 @@ define <32 x i32> @test_23(<32 x i32> %v0, <32 x i32> %v1) #0 { ; maxw ; CHECK: test_24: -; CHECK: v0.w = vmax(v1.w,v0.w) +; CHECK: v0.w = vmax(v0.w,v1.w) define <32 x i32> @test_24(<32 x i32> %v0, <32 x i32> %v1) #0 { %t0 = icmp slt <32 x i32> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i32> %v1, <32 x i32> %v0 @@ -333,7 +333,7 @@ define <32 x i32> @test_26(<32 x i32> %v0, <32 x i32> %v1) #0 { } ; CHECK: test_27: -; CHECK: v0.w = vmax(v1.w,v0.w) +; CHECK: v0.w = vmax(v0.w,v1.w) define <32 x i32> @test_27(<32 x i32> %v0, <32 x i32> %v1) #0 { %t0 = icmp sge <32 x i32> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i32> %v0, <32 x i32> %v1 diff --git a/llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll index 15e33e32296fd..4ec758e613873 100644 --- a/llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll @@ -3,7 +3,7 @@ ; minb ; CHECK: test_00: -; CHECK: v0.b = vmin(v1.b,v0.b) +; CHECK: v0.b = vmin(v0.b,v1.b) define <64 x i8> @test_00(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp slt <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1 @@ -27,7 +27,7 @@ define <64 x i8> @test_02(<64 x i8> %v0, <64 x i8> %v1) #0 { } ; CHECK: test_03: -; CHECK: v0.b = vmin(v1.b,v0.b) +; CHECK: v0.b = vmin(v0.b,v1.b) define <64 x i8> @test_03(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp sge <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v1, <64 x i8> %v0 @@ -37,7 +37,7 @@ define <64 x i8> @test_03(<64 x i8> %v0, <64 x i8> %v1) #0 { ; maxb ; CHECK: test_04: -; CHECK: v0.b = vmax(v1.b,v0.b) +; CHECK: v0.b = vmax(v0.b,v1.b) define <64 x i8> @test_04(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp slt <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v1, <64 x i8> %v0 @@ -61,7 +61,7 @@ define <64 x i8> @test_06(<64 x i8> %v0, <64 x i8> %v1) #0 { } ; CHECK: test_07: -; CHECK: v0.b = vmax(v1.b,v0.b) +; CHECK: v0.b = vmax(v0.b,v1.b) define <64 x i8> @test_07(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp sge <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1 @@ -71,7 +71,7 @@ define <64 x i8> @test_07(<64 x i8> %v0, <64 x i8> %v1) #0 { ; minub ; CHECK: test_08: -; CHECK: v0.ub = vmin(v1.ub,v0.ub) +; CHECK: v0.ub = vmin(v0.ub,v1.ub) define <64 x i8> @test_08(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp ult <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1 @@ -95,7 +95,7 @@ define <64 x i8> @test_0a(<64 x i8> %v0, <64 x i8> %v1) #0 { } ; CHECK: test_0b: -; CHECK: v0.ub = vmin(v1.ub,v0.ub) +; CHECK: v0.ub = vmin(v0.ub,v1.ub) define <64 x i8> @test_0b(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp uge <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v1, <64 x i8> %v0 @@ -105,7 +105,7 @@ define <64 x i8> @test_0b(<64 x i8> %v0, <64 x i8> %v1) #0 { ; maxub ; CHECK: test_0c: -; CHECK: v0.ub = vmax(v1.ub,v0.ub) +; CHECK: v0.ub = vmax(v0.ub,v1.ub) define <64 x i8> @test_0c(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp ult <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v1, <64 x i8> %v0 @@ -129,7 +129,7 @@ define <64 x i8> @test_0e(<64 x i8> %v0, <64 x i8> %v1) #0 { } ; CHECK: test_0f: -; CHECK: v0.ub = vmax(v1.ub,v0.ub) +; CHECK: v0.ub = vmax(v0.ub,v1.ub) define <64 x i8> @test_0f(<64 x i8> %v0, <64 x i8> %v1) #0 { %t0 = icmp uge <64 x i8> %v0, %v1 %t1 = select <64 x i1> %t0, <64 x i8> %v0, <64 x i8> %v1 @@ -139,7 +139,7 @@ define <64 x i8> @test_0f(<64 x i8> %v0, <64 x i8> %v1) #0 { ; minh ; CHECK: test_10: -; CHECK: v0.h = vmin(v1.h,v0.h) +; CHECK: v0.h = vmin(v0.h,v1.h) define <32 x i16> @test_10(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp slt <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1 @@ -163,7 +163,7 @@ define <32 x i16> @test_12(<32 x i16> %v0, <32 x i16> %v1) #0 { } ; CHECK: test_13: -; CHECK: v0.h = vmin(v1.h,v0.h) +; CHECK: v0.h = vmin(v0.h,v1.h) define <32 x i16> @test_13(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp sge <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v1, <32 x i16> %v0 @@ -173,7 +173,7 @@ define <32 x i16> @test_13(<32 x i16> %v0, <32 x i16> %v1) #0 { ; maxh ; CHECK: test_14: -; CHECK: v0.h = vmax(v1.h,v0.h) +; CHECK: v0.h = vmax(v0.h,v1.h) define <32 x i16> @test_14(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp slt <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v1, <32 x i16> %v0 @@ -197,7 +197,7 @@ define <32 x i16> @test_16(<32 x i16> %v0, <32 x i16> %v1) #0 { } ; CHECK: test_17: -; CHECK: v0.h = vmax(v1.h,v0.h) +; CHECK: v0.h = vmax(v0.h,v1.h) define <32 x i16> @test_17(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp sge <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1 @@ -207,7 +207,7 @@ define <32 x i16> @test_17(<32 x i16> %v0, <32 x i16> %v1) #0 { ; minuh ; CHECK: test_18: -; CHECK: v0.uh = vmin(v1.uh,v0.uh) +; CHECK: v0.uh = vmin(v0.uh,v1.uh) define <32 x i16> @test_18(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp ult <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1 @@ -231,7 +231,7 @@ define <32 x i16> @test_1a(<32 x i16> %v0, <32 x i16> %v1) #0 { } ; CHECK: test_1b: -; CHECK: v0.uh = vmin(v1.uh,v0.uh) +; CHECK: v0.uh = vmin(v0.uh,v1.uh) define <32 x i16> @test_1b(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp uge <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v1, <32 x i16> %v0 @@ -241,7 +241,7 @@ define <32 x i16> @test_1b(<32 x i16> %v0, <32 x i16> %v1) #0 { ; maxuh ; CHECK: test_1c: -; CHECK: v0.uh = vmax(v1.uh,v0.uh) +; CHECK: v0.uh = vmax(v0.uh,v1.uh) define <32 x i16> @test_1c(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp ult <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v1, <32 x i16> %v0 @@ -265,7 +265,7 @@ define <32 x i16> @test_1e(<32 x i16> %v0, <32 x i16> %v1) #0 { } ; CHECK: test_1f: -; CHECK: v0.uh = vmax(v1.uh,v0.uh) +; CHECK: v0.uh = vmax(v0.uh,v1.uh) define <32 x i16> @test_1f(<32 x i16> %v0, <32 x i16> %v1) #0 { %t0 = icmp uge <32 x i16> %v0, %v1 %t1 = select <32 x i1> %t0, <32 x i16> %v0, <32 x i16> %v1 @@ -275,7 +275,7 @@ define <32 x i16> @test_1f(<32 x i16> %v0, <32 x i16> %v1) #0 { ; minw ; CHECK: test_20: -; CHECK: v0.w = vmin(v1.w,v0.w) +; CHECK: v0.w = vmin(v0.w,v1.w) define <16 x i32> @test_20(<16 x i32> %v0, <16 x i32> %v1) #0 { %t0 = icmp slt <16 x i32> %v0, %v1 %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1 @@ -299,7 +299,7 @@ define <16 x i32> @test_22(<16 x i32> %v0, <16 x i32> %v1) #0 { } ; CHECK: test_23: -; CHECK: v0.w = vmin(v1.w,v0.w) +; CHECK: v0.w = vmin(v0.w,v1.w) define <16 x i32> @test_23(<16 x i32> %v0, <16 x i32> %v1) #0 { %t0 = icmp sge <16 x i32> %v0, %v1 %t1 = select <16 x i1> %t0, <16 x i32> %v1, <16 x i32> %v0 @@ -309,7 +309,7 @@ define <16 x i32> @test_23(<16 x i32> %v0, <16 x i32> %v1) #0 { ; maxw ; CHECK: test_24: -; CHECK: v0.w = vmax(v1.w,v0.w) +; CHECK: v0.w = vmax(v0.w,v1.w) define <16 x i32> @test_24(<16 x i32> %v0, <16 x i32> %v1) #0 { %t0 = icmp slt <16 x i32> %v0, %v1 %t1 = select <16 x i1> %t0, <16 x i32> %v1, <16 x i32> %v0 @@ -333,7 +333,7 @@ define <16 x i32> @test_26(<16 x i32> %v0, <16 x i32> %v1) #0 { } ; CHECK: test_27: -; CHECK: v0.w = vmax(v1.w,v0.w) +; CHECK: v0.w = vmax(v0.w,v1.w) define <16 x i32> @test_27(<16 x i32> %v0, <16 x i32> %v1) #0 { %t0 = icmp sge <16 x i32> %v0, %v1 %t1 = select <16 x i1> %t0, <16 x i32> %v0, <16 x i32> %v1 diff --git a/llvm/test/CodeGen/Hexagon/bit-skip-byval.ll b/llvm/test/CodeGen/Hexagon/bit-skip-byval.ll index 9ee4014ae346a..139726626c3d8 100644 --- a/llvm/test/CodeGen/Hexagon/bit-skip-byval.ll +++ b/llvm/test/CodeGen/Hexagon/bit-skip-byval.ll @@ -5,7 +5,7 @@ %struct.t0 = type { i32 } -define i32 @foo(%struct.t0* byval align 8 %s, i8 zeroext %t, i8 %u) #0 { +define i32 @foo(%struct.t0* byval(%struct.t0) align 8 %s, i8 zeroext %t, i8 %u) #0 { %a = zext i8 %u to i32 ret i32 %a } diff --git a/llvm/test/CodeGen/Hexagon/calling-conv-2.ll b/llvm/test/CodeGen/Hexagon/calling-conv-2.ll index f2526b36e3369..bca6ac71927e3 100644 --- a/llvm/test/CodeGen/Hexagon/calling-conv-2.ll +++ b/llvm/test/CodeGen/Hexagon/calling-conv-2.ll @@ -3,12 +3,12 @@ %struct.test_struct = type { i32, i8, i64 } ; CHECK: r1 = #45 -define void @foo(%struct.test_struct* noalias nocapture sret %agg.result, i32 %a) #0 { +define void @foo(%struct.test_struct* noalias nocapture sret(%struct.test_struct) %agg.result, i32 %a) #0 { entry: - call void @bar(%struct.test_struct* sret %agg.result, i32 45) #0 + call void @bar(%struct.test_struct* sret(%struct.test_struct) %agg.result, i32 45) #0 ret void } -declare void @bar(%struct.test_struct* sret, i32) #0 +declare void @bar(%struct.test_struct* sret(%struct.test_struct), i32) #0 attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/Hexagon/calling-conv.ll b/llvm/test/CodeGen/Hexagon/calling-conv.ll index bbe376b7f5162..881709f98c0d7 100644 --- a/llvm/test/CodeGen/Hexagon/calling-conv.ll +++ b/llvm/test/CodeGen/Hexagon/calling-conv.ll @@ -11,7 +11,7 @@ ; CHECK-TWO: memw(r29+#52) = r2 ; CHECK-THREE: memw(r29+#56) = r2 -define void @f0(%s.0* noalias nocapture sret %a0, i32 %a1, i8 zeroext %a2, %s.0* byval nocapture readnone align 8 %a3, %s.1* byval nocapture readnone align 8 %a4) #0 { +define void @f0(%s.0* noalias nocapture sret(%s.0) %a0, i32 %a1, i8 zeroext %a2, %s.0* byval(%s.0) nocapture readnone align 8 %a3, %s.1* byval(%s.1) nocapture readnone align 8 %a4) #0 { b0: %v0 = alloca %s.0, align 8 %v1 = load %s.0*, %s.0** @g0, align 4 @@ -19,7 +19,7 @@ b0: %v3 = add nsw i64 %v2, 1 %v4 = add nsw i32 %a1, 2 %v5 = add nsw i64 %v2, 3 - call void @f1(%s.0* sret %v0, i32 45, %s.0* byval align 8 %v1, %s.0* byval align 8 %v1, i8 zeroext %a2, i64 %v3, i32 %v4, i64 %v5, i8 zeroext %a2, i8 zeroext %a2, i8 zeroext %a2, i32 45) + call void @f1(%s.0* sret(%s.0) %v0, i32 45, %s.0* byval(%s.0) align 8 %v1, %s.0* byval(%s.0) align 8 %v1, i8 zeroext %a2, i64 %v3, i32 %v4, i64 %v5, i8 zeroext %a2, i8 zeroext %a2, i8 zeroext %a2, i32 45) %v6 = bitcast %s.0* %v0 to i32* store i32 20, i32* %v6, align 8 %v7 = bitcast %s.0* %a0 to i8* @@ -28,7 +28,7 @@ b0: ret void } -declare void @f1(%s.0* sret, i32, %s.0* byval align 8, %s.0* byval align 8, i8 zeroext, i64, i32, i64, i8 zeroext, i8 zeroext, i8 zeroext, i32) +declare void @f1(%s.0* sret(%s.0), i32, %s.0* byval(%s.0) align 8, %s.0* byval(%s.0) align 8, i8 zeroext, i64, i32, i64, i8 zeroext, i8 zeroext, i8 zeroext, i32) ; Function Attrs: argmemonly nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) #1 diff --git a/llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir b/llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir index 0390ac292b761..63277e05cd1e7 100644 --- a/llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir +++ b/llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir @@ -22,7 +22,7 @@ %s.9 = type { i8, i8 } ; Function Attrs: nounwind optsize - define dso_local void @f0(%s.0* byval nocapture readonly align 8 %a0) local_unnamed_addr #0 { + define dso_local void @f0(%s.0* byval(%s.0) nocapture readonly align 8 %a0) local_unnamed_addr #0 { b0: %v0 = getelementptr inbounds %s.0, %s.0* %a0, i32 0, i32 10 %v1 = load i8, i8* %v0, align 8 diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll index 284170b5edb43..8fef933dd12e9 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll @@ -5,7 +5,7 @@ target triple = "hexagon" %struct.0 = type { i64, i16 } -declare void @foo(%struct.0* noalias nocapture sret, i8 zeroext, i32, i64) #0 +declare void @foo(%struct.0* noalias nocapture sret(%struct.0), i8 zeroext, i32, i64) #0 define hidden fastcc void @fred(%struct.0* noalias nocapture %p, i8 zeroext %t, i32 %r) unnamed_addr #0 { entry: @@ -14,7 +14,7 @@ entry: %inc = zext i1 %cmp104 to i32 %inc.r = add nsw i32 %inc, %r %.inc.r = select i1 undef, i32 0, i32 %inc.r - tail call void @foo(%struct.0* sret %p, i8 zeroext %t, i32 %.inc.r, i64 undef) + tail call void @foo(%struct.0* sret(%struct.0) %p, i8 zeroext %t, i32 %.inc.r, i64 undef) ret void } diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-error.ll b/llvm/test/CodeGen/Hexagon/inline-asm-error.ll index a8901a9d22688..0a1e70830f586 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-error.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-error.ll @@ -6,7 +6,7 @@ %s.1 = type { %s.2 } %s.2 = type { i32, i8* } -define void @f0(%s.0* byval align 8 %a0) { +define void @f0(%s.0* byval(%s.0) align 8 %a0) { b0: call void asm sideeffect ".weak OFFSET_0;jump ##(OFFSET_0 + 0x14c15f0)", "*r"(%s.0* nonnull %a0), !srcloc !0 ret void diff --git a/llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll b/llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll index 53dec510a865f..d175d8dd295cb 100644 --- a/llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll +++ b/llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll @@ -3,7 +3,7 @@ ; min ; CHECK-LABEL: test_00: -; CHECK: r1:0 = vminb(r3:2,r1:0) +; CHECK: r1:0 = vminb(r1:0,r3:2) define <8 x i8> @test_00(<8 x i8> %a0, <8 x i8> %a1) #0 { %v0 = icmp slt <8 x i8> %a0, %a1 %v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1 @@ -19,7 +19,7 @@ define <8 x i8> @test_01(<8 x i8> %a0, <8 x i8> %a1) #0 { } ; CHECK-LABEL: test_02: -; CHECK: r1:0 = vminh(r3:2,r1:0) +; CHECK: r1:0 = vminh(r1:0,r3:2) define <4 x i16> @test_02(<4 x i16> %a0, <4 x i16> %a1) #0 { %v0 = icmp slt <4 x i16> %a0, %a1 %v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1 @@ -35,7 +35,7 @@ define <4 x i16> @test_03(<4 x i16> %a0, <4 x i16> %a1) #0 { } ; CHECK-LABEL: test_04: -; CHECK: r1:0 = vminw(r3:2,r1:0) +; CHECK: r1:0 = vminw(r1:0,r3:2) define <2 x i32> @test_04(<2 x i32> %a0, <2 x i32> %a1) #0 { %v0 = icmp slt <2 x i32> %a0, %a1 %v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1 @@ -53,7 +53,7 @@ define <2 x i32> @test_05(<2 x i32> %a0, <2 x i32> %a1) #0 { ; minu ; CHECK-LABEL: test_06: -; CHECK: r1:0 = vminub(r3:2,r1:0) +; CHECK: r1:0 = vminub(r1:0,r3:2) define <8 x i8> @test_06(<8 x i8> %a0, <8 x i8> %a1) #0 { %v0 = icmp ult <8 x i8> %a0, %a1 %v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1 @@ -69,7 +69,7 @@ define <8 x i8> @test_07(<8 x i8> %a0, <8 x i8> %a1) #0 { } ; CHECK-LABEL: test_08: -; CHECK: r1:0 = vminuh(r3:2,r1:0) +; CHECK: r1:0 = vminuh(r1:0,r3:2) define <4 x i16> @test_08(<4 x i16> %a0, <4 x i16> %a1) #0 { %v0 = icmp ult <4 x i16> %a0, %a1 %v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1 @@ -85,7 +85,7 @@ define <4 x i16> @test_09(<4 x i16> %a0, <4 x i16> %a1) #0 { } ; CHECK-LABEL: test_0a: -; CHECK: r1:0 = vminuw(r3:2,r1:0) +; CHECK: r1:0 = vminuw(r1:0,r3:2) define <2 x i32> @test_0a(<2 x i32> %a0, <2 x i32> %a1) #0 { %v0 = icmp ult <2 x i32> %a0, %a1 %v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1 @@ -111,7 +111,7 @@ define <8 x i8> @test_0c(<8 x i8> %a0, <8 x i8> %a1) #0 { } ; CHECK-LABEL: test_0d: -; CHECK: r1:0 = vmaxb(r3:2,r1:0) +; CHECK: r1:0 = vmaxb(r1:0,r3:2) define <8 x i8> @test_0d(<8 x i8> %a0, <8 x i8> %a1) #0 { %v0 = icmp sge <8 x i8> %a0, %a1 %v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1 @@ -127,7 +127,7 @@ define <4 x i16> @test_0e(<4 x i16> %a0, <4 x i16> %a1) #0 { } ; CHECK-LABEL: test_0f: -; CHECK: r1:0 = vmaxh(r3:2,r1:0) +; CHECK: r1:0 = vmaxh(r1:0,r3:2) define <4 x i16> @test_0f(<4 x i16> %a0, <4 x i16> %a1) #0 { %v0 = icmp sge <4 x i16> %a0, %a1 %v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1 @@ -143,7 +143,7 @@ define <2 x i32> @test_10(<2 x i32> %a0, <2 x i32> %a1) #0 { } ; CHECK-LABEL: test_11: -; CHECK: r1:0 = vmaxw(r3:2,r1:0) +; CHECK: r1:0 = vmaxw(r1:0,r3:2) define <2 x i32> @test_11(<2 x i32> %a0, <2 x i32> %a1) #0 { %v0 = icmp sge <2 x i32> %a0, %a1 %v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1 @@ -161,7 +161,7 @@ define <8 x i8> @test_12(<8 x i8> %a0, <8 x i8> %a1) #0 { } ; CHECK-LABEL: test_13: -; CHECK: r1:0 = vmaxub(r3:2,r1:0) +; CHECK: r1:0 = vmaxub(r1:0,r3:2) define <8 x i8> @test_13(<8 x i8> %a0, <8 x i8> %a1) #0 { %v0 = icmp uge <8 x i8> %a0, %a1 %v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1 @@ -177,7 +177,7 @@ define <4 x i16> @test_14(<4 x i16> %a0, <4 x i16> %a1) #0 { } ; CHECK-LABEL: test_15: -; CHECK: r1:0 = vmaxuh(r3:2,r1:0) +; CHECK: r1:0 = vmaxuh(r1:0,r3:2) define <4 x i16> @test_15(<4 x i16> %a0, <4 x i16> %a1) #0 { %v0 = icmp uge <4 x i16> %a0, %a1 %v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1 @@ -193,7 +193,7 @@ define <2 x i32> @test_16(<2 x i32> %a0, <2 x i32> %a1) #0 { } ; CHECK-LABEL: test_17: -; CHECK: r1:0 = vmaxuw(r3:2,r1:0) +; CHECK: r1:0 = vmaxuw(r1:0,r3:2) define <2 x i32> @test_17(<2 x i32> %a0, <2 x i32> %a1) #0 { %v0 = icmp uge <2 x i32> %a0, %a1 %v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1 diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll index 3e1e39b9d0944..06d4544be5cf8 100644 --- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll +++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll @@ -3,6 +3,7 @@ ; get this opportunity regardless of what happens before. ; RUN: opt -O2 -march=hexagon -S < %s | FileCheck %s +; RUN: opt -aa-pipeline=default -passes='default' -march=hexagon -S < %s | FileCheck %s target triple = "hexagon" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" diff --git a/llvm/test/CodeGen/Hexagon/opt-addr-mode-subreg-use.ll b/llvm/test/CodeGen/Hexagon/opt-addr-mode-subreg-use.ll index 54ae8c7637103..667b284ca0955 100644 --- a/llvm/test/CodeGen/Hexagon/opt-addr-mode-subreg-use.ll +++ b/llvm/test/CodeGen/Hexagon/opt-addr-mode-subreg-use.ll @@ -17,22 +17,22 @@ declare zeroext i1 @f0(i32*) #0 align 2 declare zeroext i1 @f1(i32*) #0 align 2 ; Function Attrs: optsize -declare hidden void @f2(i32* noalias nocapture sret, i32) #1 align 2 +declare hidden void @f2(i32* noalias nocapture sret(i32), i32) #1 align 2 ; Function Attrs: optsize -declare hidden void @f3(i32* noalias nocapture sret, i32) #1 align 2 +declare hidden void @f3(i32* noalias nocapture sret(i32), i32) #1 align 2 ; Function Attrs: optsize -declare hidden void @f4(i32* noalias nocapture sret, i32) #1 align 2 +declare hidden void @f4(i32* noalias nocapture sret(i32), i32) #1 align 2 ; Function Attrs: optsize -declare hidden void @f5(i32* noalias nocapture sret, i32) #1 align 2 +declare hidden void @f5(i32* noalias nocapture sret(i32), i32) #1 align 2 ; Function Attrs: optsize -declare hidden void @f6(i32* noalias nocapture sret, i32) #1 align 2 +declare hidden void @f6(i32* noalias nocapture sret(i32), i32) #1 align 2 ; Function Attrs: optsize -declare hidden void @f7(i32* noalias nocapture sret, i32) #1 align 2 +declare hidden void @f7(i32* noalias nocapture sret(i32), i32) #1 align 2 ; Function Attrs: optsize declare zeroext i1 @f8(i32*, i32*, i64) #1 align 2 diff --git a/llvm/test/CodeGen/Hexagon/regscavengerbug.ll b/llvm/test/CodeGen/Hexagon/regscavengerbug.ll index cf03f1d2e498f..ab9318e52ba66 100644 --- a/llvm/test/CodeGen/Hexagon/regscavengerbug.ll +++ b/llvm/test/CodeGen/Hexagon/regscavengerbug.ll @@ -13,7 +13,7 @@ target triple = "hexagon-unknown-linux-gnu" %5 = type { i32 (...)** } %6 = type { %3, %3 } -declare void @f0(%3* sret, %0*, %3*) +declare void @f0(%3* sret(%3), %0*, %3*) ; Function Attrs: nounwind define void @f1(%4* %a0, %0* nocapture %a1, %0* nocapture %a2) #0 align 2 { @@ -98,7 +98,7 @@ b3: ; preds = %b0 %v50 = load double, double* %v41, align 8, !tbaa !6 %v51 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2 store double %v50, double* %v51, align 8, !tbaa !6 - call void @f0(%3* sret %v2, %0* %v3, %3* %v24) + call void @f0(%3* sret(%3) %v2, %0* %v3, %3* %v24) call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %v25, i8* align 8 %v42, i32 24, i1 false) %v52 = load double, double* %v39, align 8, !tbaa !6 %v53 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0 @@ -110,7 +110,7 @@ b3: ; preds = %b0 %v57 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 0, i32 0, i32 1, i32 0, i32 2 store double %v56, double* %v57, align 8, !tbaa !6 %v58 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 0, i32 0, i32 1 - call void @f0(%3* sret %v2, %0* %v3, %3* %v58) + call void @f0(%3* sret(%3) %v2, %0* %v3, %3* %v58) %v59 = bitcast %3* %v58 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %v59, i8* align 8 %v42, i32 24, i1 false) %v60 = load double, double* %v39, align 8, !tbaa !6 @@ -123,7 +123,7 @@ b3: ; preds = %b0 %v65 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 2 store double %v64, double* %v65, align 8, !tbaa !6 %v66 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 0, i32 1, i32 0 - call void @f0(%3* sret %v2, %0* %v3, %3* %v66) + call void @f0(%3* sret(%3) %v2, %0* %v3, %3* %v66) %v67 = bitcast %3* %v66 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %v67, i8* align 8 %v42, i32 24, i1 false) %v68 = load double, double* %v39, align 8, !tbaa !6 @@ -136,7 +136,7 @@ b3: ; preds = %b0 %v73 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 0, i32 1, i32 1, i32 0, i32 2 store double %v72, double* %v73, align 8, !tbaa !6 %v74 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 0, i32 1, i32 1 - call void @f0(%3* sret %v2, %0* %v3, %3* %v74) + call void @f0(%3* sret(%3) %v2, %0* %v3, %3* %v74) %v75 = bitcast %3* %v74 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %v75, i8* align 8 %v42, i32 24, i1 false) %v76 = load double, double* %v45, align 8, !tbaa !6 @@ -149,7 +149,7 @@ b3: ; preds = %b0 %v81 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 1, i32 0, i32 0, i32 0, i32 2 store double %v80, double* %v81, align 8, !tbaa !6 %v82 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 1, i32 0, i32 0 - call void @f0(%3* sret %v2, %0* %v3, %3* %v82) + call void @f0(%3* sret(%3) %v2, %0* %v3, %3* %v82) %v83 = bitcast %3* %v82 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %v83, i8* align 8 %v42, i32 24, i1 false) %v84 = load double, double* %v45, align 8, !tbaa !6 @@ -162,7 +162,7 @@ b3: ; preds = %b0 %v89 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 2 store double %v88, double* %v89, align 8, !tbaa !6 %v90 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 1, i32 0, i32 1 - call void @f0(%3* sret %v2, %0* %v3, %3* %v90) + call void @f0(%3* sret(%3) %v2, %0* %v3, %3* %v90) %v91 = bitcast %3* %v90 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %v91, i8* align 8 %v42, i32 24, i1 false) %v92 = load double, double* %v45, align 8, !tbaa !6 @@ -175,7 +175,7 @@ b3: ; preds = %b0 %v97 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 1, i32 1, i32 0, i32 0, i32 2 store double %v96, double* %v97, align 8, !tbaa !6 %v98 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 1, i32 1, i32 0 - call void @f0(%3* sret %v2, %0* %v3, %3* %v98) + call void @f0(%3* sret(%3) %v2, %0* %v3, %3* %v98) %v99 = bitcast %3* %v98 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %v99, i8* align 8 %v42, i32 24, i1 false) %v100 = load double, double* %v45, align 8, !tbaa !6 @@ -188,7 +188,7 @@ b3: ; preds = %b0 %v105 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 1, i32 1, i32 1, i32 0, i32 2 store double %v104, double* %v105, align 8, !tbaa !6 %v106 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 1, i32 1, i32 1 - call void @f0(%3* sret %v2, %0* %v3, %3* %v106) + call void @f0(%3* sret(%3) %v2, %0* %v3, %3* %v106) %v107 = bitcast %3* %v106 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %v107, i8* align 8 %v42, i32 24, i1 false) %v108 = getelementptr inbounds [2 x [2 x [2 x %3]]], [2 x [2 x [2 x %3]]]* %v1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0 diff --git a/llvm/test/CodeGen/Hexagon/struct_args_large.ll b/llvm/test/CodeGen/Hexagon/struct_args_large.ll index fb4780b0e5a92..86550cce0cbee 100644 --- a/llvm/test/CodeGen/Hexagon/struct_args_large.ll +++ b/llvm/test/CodeGen/Hexagon/struct_args_large.ll @@ -10,8 +10,8 @@ define void @foo() nounwind { entry: - call void @bar(%struct.large* byval @s2) + call void @bar(%struct.large* byval(%struct.large) @s2) ret void } -declare void @bar(%struct.large* byval) +declare void @bar(%struct.large* byval(%struct.large)) diff --git a/llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll b/llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll index f61103080113c..bd87e2a2b213d 100644 --- a/llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll +++ b/llvm/test/CodeGen/Hexagon/tail-dup-subreg-map.ll @@ -14,7 +14,7 @@ target triple = "hexagon" declare hidden fastcc void @foo(%struct.0* noalias nocapture, i8 signext, i8 zeroext, i32, i64, i64) unnamed_addr #0 -define void @fred(%struct.0* noalias nocapture sret %agg.result, %struct.1* byval nocapture readonly align 8 %a, i32 %a0) #1 { +define void @fred(%struct.0* noalias nocapture sret(%struct.0) %agg.result, %struct.1* byval(%struct.1) nocapture readonly align 8 %a, i32 %a0) #1 { entry: %0 = load i64, i64* undef, align 8 switch i32 %a0, label %if.else [ diff --git a/llvm/test/CodeGen/Hexagon/v6vect-locals1.ll b/llvm/test/CodeGen/Hexagon/v6vect-locals1.ll index c1ab52f50f728..8ae0c7b66ee40 100644 --- a/llvm/test/CodeGen/Hexagon/v6vect-locals1.ll +++ b/llvm/test/CodeGen/Hexagon/v6vect-locals1.ll @@ -16,7 +16,7 @@ target triple = "hexagon" declare i32 @f0(i8* nocapture, ...) #0 ; Function Attrs: nounwind -define void @f1(%s.0* byval %a0, <16 x i32> %a1) #0 { +define void @f1(%s.0* byval(%s.0) %a0, <16 x i32> %a1) #0 { b0: %v0 = alloca <16 x i32>, align 64 store <16 x i32> %a1, <16 x i32>* %v0, align 64, !tbaa !0 @@ -30,7 +30,7 @@ b0: define i32 @f2() #0 { b0: %v0 = load <16 x i32>, <16 x i32>* @g2, align 64, !tbaa !0 - tail call void @f1(%s.0* byval @g1, <16 x i32> %v0) + tail call void @f1(%s.0* byval(%s.0) @g1, <16 x i32> %v0) ret i32 0 } diff --git a/llvm/test/CodeGen/Hexagon/vararg.ll b/llvm/test/CodeGen/Hexagon/vararg.ll index ed9029016af5c..c22da1a1163eb 100644 --- a/llvm/test/CodeGen/Hexagon/vararg.ll +++ b/llvm/test/CodeGen/Hexagon/vararg.ll @@ -82,7 +82,7 @@ declare void @llvm.va_end(i8*) #1 ; Function Attrs: nounwind define i32 @main() #0 { entry: - %call = tail call i32 (i32, ...) @foo(i32 undef, i32 2, %struct.AAA* byval align 4 @aaa, i32 4) + %call = tail call i32 (i32, ...) @foo(i32 undef, i32 2, %struct.AAA* byval(%struct.AAA) align 4 @aaa, i32 4) %call1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %call) #1 ret i32 %call } diff --git a/llvm/test/CodeGen/Hexagon/vararg_align_check.ll b/llvm/test/CodeGen/Hexagon/vararg_align_check.ll index 0152eec7020de..647625f4ed1f7 100644 --- a/llvm/test/CodeGen/Hexagon/vararg_align_check.ll +++ b/llvm/test/CodeGen/Hexagon/vararg_align_check.ll @@ -29,7 +29,7 @@ @.str = private unnamed_addr constant [13 x i8] c"result = %d\0A\00", align 1 ; Function Attrs: nounwind -define i32 @foo(i32 %xx, %struct.BBB* byval align 8 %eee, ...) #0 { +define i32 @foo(i32 %xx, %struct.BBB* byval(%struct.BBB) align 8 %eee, ...) #0 { entry: %xx.addr = alloca i32, align 4 %ap = alloca [1 x %struct.__va_list_tag], align 8 @@ -169,7 +169,7 @@ entry: store i32 0, i32* %retval store i64 1000000, i64* %m, align 8 %0 = load i64, i64* %m, align 8 - %call = call i32 (i32, %struct.BBB*, ...) @foo(i32 1, %struct.BBB* byval align 8 bitcast ({ i8, i64, i32, [4 x i8] }* @ddd to %struct.BBB*), i64 %0, %struct.AAA* byval align 4 @aaa, i32 4) + %call = call i32 (i32, %struct.BBB*, ...) @foo(i32 1, %struct.BBB* byval(%struct.BBB) align 8 bitcast ({ i8, i64, i32, [4 x i8] }* @ddd to %struct.BBB*), i64 %0, %struct.AAA* byval(%struct.AAA) align 4 @aaa, i32 4) store i32 %call, i32* %x, align 4 %1 = load i32, i32* %x, align 4 %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %1) diff --git a/llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll b/llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll index 0a755e57fe0c0..613fce8bb0ef3 100644 --- a/llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll +++ b/llvm/test/CodeGen/Hexagon/vararg_double_onstack.ll @@ -197,7 +197,7 @@ entry: store i64 1000000, i64* %y, align 8 %0 = load i64, i64* %y, align 8 %1 = load i64, i64* %y, align 8 - %call = call i32 (i32, i32, i32, i32, i32, ...) @foo(i32 1, i32 2, i32 3, i32 4, i32 5, i64 %0, %struct.AAA* byval align 4 @aaa, i32 4, i64 %1) + %call = call i32 (i32, i32, i32, i32, i32, ...) @foo(i32 1, i32 2, i32 3, i32 4, i32 5, i64 %0, %struct.AAA* byval(%struct.AAA) align 4 @aaa, i32 4, i64 %1) store i32 %call, i32* %x, align 4 %2 = load i32, i32* %x, align 4 %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %2) diff --git a/llvm/test/CodeGen/Hexagon/vararg_named.ll b/llvm/test/CodeGen/Hexagon/vararg_named.ll index 5a357284caf8f..413dc2e1d5da7 100644 --- a/llvm/test/CodeGen/Hexagon/vararg_named.ll +++ b/llvm/test/CodeGen/Hexagon/vararg_named.ll @@ -31,7 +31,7 @@ @.str = private unnamed_addr constant [13 x i8] c"result = %d\0A\00", align 1 ; Function Attrs: nounwind -define i32 @foo(i32 %xx, i32 %z, i32 %m, %struct.AAA* byval align 4 %bbb, %struct.AAA* byval align 4 %GGG, ...) #0 { +define i32 @foo(i32 %xx, i32 %z, i32 %m, %struct.AAA* byval(%struct.AAA) align 4 %bbb, %struct.AAA* byval(%struct.AAA) align 4 %GGG, ...) #0 { entry: %xx.addr = alloca i32, align 4 %z.addr = alloca i32, align 4 @@ -194,7 +194,7 @@ entry: %retval = alloca i32, align 4 %x = alloca i32, align 4 store i32 0, i32* %retval - %call = call i32 (i32, i32, i32, %struct.AAA*, %struct.AAA*, ...) @foo(i32 1, i32 3, i32 5, %struct.AAA* byval align 4 @aaa, %struct.AAA* byval align 4 @fff, i32 2, %struct.AAA* byval align 4 @xxx, %struct.AAA* byval align 4 @yyy, %struct.AAA* byval align 4 @ccc, i32 4) + %call = call i32 (i32, i32, i32, %struct.AAA*, %struct.AAA*, ...) @foo(i32 1, i32 3, i32 5, %struct.AAA* byval(%struct.AAA) align 4 @aaa, %struct.AAA* byval(%struct.AAA) align 4 @fff, i32 2, %struct.AAA* byval(%struct.AAA) align 4 @xxx, %struct.AAA* byval(%struct.AAA) align 4 @yyy, %struct.AAA* byval(%struct.AAA) align 4 @ccc, i32 4) store i32 %call, i32* %x, align 4 %0 = load i32, i32* %x, align 4 %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %0) diff --git a/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir b/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir index 8f88926376f71..c1fe8cbd7e9b3 100644 --- a/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir +++ b/llvm/test/CodeGen/MIR/X86/diexpr-win32.mir @@ -67,7 +67,7 @@ %struct.string = type { i32, i32, i8* } - define void @fun(%struct.string* noalias sret %agg.result, %struct.string* noalias %str) !dbg !12 { + define void @fun(%struct.string* noalias sret(%struct.string) %agg.result, %struct.string* noalias %str) !dbg !12 { entry: call void @llvm.dbg.value(metadata %struct.string* %agg.result, metadata !23, metadata !24), !dbg !25 call void @llvm.dbg.value(metadata %struct.string* %str, metadata !26, metadata !28), !dbg !25 diff --git a/llvm/test/CodeGen/MIR/X86/fixed-stack-di.mir b/llvm/test/CodeGen/MIR/X86/fixed-stack-di.mir index 0add9f1c79332..5bdece87aa83f 100644 --- a/llvm/test/CodeGen/MIR/X86/fixed-stack-di.mir +++ b/llvm/test/CodeGen/MIR/X86/fixed-stack-di.mir @@ -8,7 +8,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 - define hidden void @foo(i32* byval %dstRect) { + define hidden void @foo(i32* byval(i32) %dstRect) { entry: call void @llvm.dbg.declare(metadata i32* %dstRect, metadata !3, metadata !DIExpression()), !dbg !5 unreachable diff --git a/llvm/test/CodeGen/MSP430/byval.ll b/llvm/test/CodeGen/MSP430/byval.ll index 838e883d4bec3..5faeba5f7c6e0 100644 --- a/llvm/test/CodeGen/MSP430/byval.ll +++ b/llvm/test/CodeGen/MSP430/byval.ll @@ -6,7 +6,7 @@ target triple = "msp430---elf" %struct.Foo = type { i16, i16, i16 } @foo = global %struct.Foo { i16 1, i16 2, i16 3 }, align 2 -define i16 @callee(%struct.Foo* byval %f) nounwind { +define i16 @callee(%struct.Foo* byval(%struct.Foo) %f) nounwind { entry: ; CHECK-LABEL: callee: ; CHECK: mov 2(r1), r12 @@ -21,6 +21,6 @@ entry: ; CHECK: mov &foo+4, 4(r1) ; CHECK-NEXT: mov &foo+2, 2(r1) ; CHECK-NEXT: mov &foo, 0(r1) - %call = call i16 @callee(%struct.Foo* byval @foo) + %call = call i16 @callee(%struct.Foo* byval(%struct.Foo) @foo) ret void } diff --git a/llvm/test/CodeGen/MSP430/spill-to-stack.ll b/llvm/test/CodeGen/MSP430/spill-to-stack.ll index d925bc91b72d7..549e30c43a2c7 100644 --- a/llvm/test/CodeGen/MSP430/spill-to-stack.ll +++ b/llvm/test/CodeGen/MSP430/spill-to-stack.ll @@ -2,7 +2,7 @@ %VeryLarge = type { i8, i32, i32, i32, i32, i32, i32, i32, i32, i32 } ; intentionally cause a spill -define void @inc(%VeryLarge* byval align 1 %s) { +define void @inc(%VeryLarge* byval(%VeryLarge) align 1 %s) { entry: %p0 = getelementptr inbounds %VeryLarge, %VeryLarge* %s, i32 0, i32 0 %0 = load i8, i8* %p0 diff --git a/llvm/test/CodeGen/MSP430/struct-return.ll b/llvm/test/CodeGen/MSP430/struct-return.ll index 8f662897a2919..d0e5a7f8bb255 100644 --- a/llvm/test/CodeGen/MSP430/struct-return.ll +++ b/llvm/test/CodeGen/MSP430/struct-return.ll @@ -31,11 +31,11 @@ define void @test() #1 { %1 = alloca %struct.S, align 2 ; CHECK: mov r1, r12 ; CHECK-NEXT: call #sret - call void @sret(%struct.S* nonnull sret %1) #3 + call void @sret(%struct.S* nonnull sret(%struct.S) %1) #3 ret void } -define void @sret(%struct.S* noalias nocapture sret) #0 { +define void @sret(%struct.S* noalias nocapture sret(%struct.S)) #0 { ; CHECK-LABEL: sret: ; CHECK: mov &a, 0(r12) ; CHECK: mov &b, 2(r12) diff --git a/llvm/test/CodeGen/Mips/2008-07-03-SRet.ll b/llvm/test/CodeGen/Mips/2008-07-03-SRet.ll index 6313ec4af3562..f586b5823b9d6 100644 --- a/llvm/test/CodeGen/Mips/2008-07-03-SRet.ll +++ b/llvm/test/CodeGen/Mips/2008-07-03-SRet.ll @@ -2,7 +2,7 @@ %struct.sret0 = type { i32, i32, i32 } -define void @test0(%struct.sret0* noalias sret %agg.result, i32 %dummy) nounwind { +define void @test0(%struct.sret0* noalias sret(%struct.sret0) %agg.result, i32 %dummy) nounwind { entry: ; CHECK: sw ${{[0-9]+}}, {{[0-9]+}}($4) ; CHECK: sw ${{[0-9]+}}, {{[0-9]+}}($4) diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll b/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll index f22fbcc7b73ee..a0f5d1e75dfbb 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll @@ -163,22 +163,22 @@ declare void @xcccc(i8, i8, i8, i8) define void @cxcccc() { ; ALL-LABEL: cxcccc: - ; ALL: addiu $[[R:[0-9]+]], $zero, 88 - ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24 - ; 32R1: sra $4, $[[R]], 24 - ; 32R2: seb $4, $[[R]] - ; ALL: addiu $[[R:[0-9]+]], $zero, 44 - ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24 - ; 32R1: sra $5, $[[R]], 24 - ; 32R2: seb $5, $[[R]] - ; ALL: addiu $[[R:[0-9]+]], $zero, 11 - ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24 - ; 32R1: sra $6, $[[R]], 24 - ; 32R2: seb $6, $[[R]] - ; ALL: addiu $[[R:[0-9]+]], $zero, 33 - ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24 - ; 32R1: sra $7, $[[R]], 24 - ; 32R2: seb $7, $[[R]] + ; ALL: addiu $[[R1:[0-9]+]], $zero, 88 + ; ALL: addiu $[[R2:[0-9]+]], $zero, 44 + ; ALL: addiu $[[R3:[0-9]+]], $zero, 11 + ; ALL: addiu $[[R4:[0-9]+]], $zero, 33 + ; 32R1: sll $[[R1:[0-9]+]], $[[R1]], 24 + ; 32R1: sra $4, $[[R1]], 24 + ; 32R2: seb $4, $[[R1]] + ; 32R1: sll $[[R2]], $[[R2]], 24 + ; 32R1: sra $5, $[[R2]], 24 + ; 32R2: seb $5, $[[R2]] + ; 32R1: sll $[[R3]], $[[R3]], 24 + ; 32R1: sra $6, $[[R3]], 24 + ; 32R2: seb $6, $[[R3]] + ; 32R1: sll $[[R4]], $[[R4]], 24 + ; 32R1: sra $7, $[[R4]], 24 + ; 32R2: seb $7, $[[R4]] ; ALL: lw $25, %got(xcccc)(${{[0-9]+}}) ; ALL: jalr $25 @@ -192,22 +192,22 @@ declare void @xhhhh(i16, i16, i16, i16) define void @cxhhhh() { ; ALL-LABEL: cxhhhh: - ; ALL: addiu $[[R:[0-9]+]], $zero, 88 - ; 32R1: sll $[[R]], $[[R]], 16 - ; 32R1: sra $4, $[[R]], 16 - ; 32R2: seh $4, $[[R]] - ; ALL: addiu $[[R:[0-9]+]], $zero, 44 - ; 32R1: sll $[[R]], $[[R]], 16 - ; 32R1: sra $5, $[[R]], 16 - ; 32R2: seh $5, $[[R]] - ; ALL: addiu $[[R:[0-9]+]], $zero, 11 - ; 32R1: sll $[[R]], $[[R]], 16 - ; 32R1: sra $6, $[[R]], 16 - ; 32R2: seh $6, $[[R]] - ; ALL: addiu $[[R:[0-9]+]], $zero, 33 - ; 32R1: sll $[[R]], $[[R]], 16 - ; 32R1: sra $7, $[[R]], 16 - ; 32R2: seh $7, $[[R]] + ; ALL: addiu $[[R1:[0-9]+]], $zero, 88 + ; ALL: addiu $[[R2:[0-9]+]], $zero, 44 + ; ALL: addiu $[[R3:[0-9]+]], $zero, 11 + ; ALL: addiu $[[R4:[0-9]+]], $zero, 33 + ; 32R1: sll $[[R1]], $[[R1]], 16 + ; 32R1: sra $4, $[[R1]], 16 + ; 32R2: seh $4, $[[R1]] + ; 32R1: sll $[[R2]], $[[R2]], 16 + ; 32R1: sra $5, $[[R2]], 16 + ; 32R2: seh $5, $[[R2]] + ; 32R1: sll $[[R3]], $[[R3]], 16 + ; 32R1: sra $6, $[[R3]], 16 + ; 32R2: seh $6, $[[R3]] + ; 32R1: sll $[[R4]], $[[R4]], 16 + ; 32R1: sra $7, $[[R4]], 16 + ; 32R2: seh $7, $[[R4]] ; ALL: lw $25, %got(xhhhh)(${{[0-9]+}}) ; ALL: jalr $25 @@ -426,13 +426,13 @@ define void @cxiff() { ; ALL-LABEL: cxiff: ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} + ; ALL-DAG: addiu $4, $zero, 12239 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17526 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 55706 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]] ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 16543 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 65326 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]] - ; ALL-DAG: addiu $4, $zero, 12239 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]] ; ALL-DAG: mfc1 $6, $f[[REGF1_3]] ; ALL-DAG: lw $25, %got(xiff)($[[REG_GP]]) @@ -470,11 +470,11 @@ define void @cxifif() { ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17527 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 2015 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]] + ; ALL-DAG: addiu $6, $zero, 9991 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17802 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 58470 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]] ; ALL-DAG: mfc1 $5, $f[[REGF0_3]] - ; ALL-DAG: addiu $6, $zero, 9991 ; ALL-DAG: mfc1 $7, $f[[REGF1_3]] ; ALL-DAG: lw $25, %got(xifif)($[[REG_GP]]) ; ALL: jalr $25 @@ -489,13 +489,13 @@ define void @cxiffi() { ; ALL-LABEL: cxiffi: ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} + ; ALL-DAG: addiu $4, $zero, 45 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 16307 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 13107 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]] ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17529 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 39322 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]] - ; ALL-DAG: addiu $4, $zero, 45 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]] ; ALL-DAG: mfc1 $6, $f[[REGF1_3]] ; ALL-DAG: addiu $7, $zero, 234 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll index ad2a0f8f2a841..a7a537e68a7eb 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll @@ -22,8 +22,8 @@ entry: %2 = load i32, i32* %x2, align 4 store i32 %2, i32* @i, align 4 %3 = load i32, i32* %retval -; CHECK: lw $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]]) ; CHECK: addiu $[[A_ADDR:[0-9]+]], $sp, 8 +; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]]) ; CHECK-DAG: sw $[[A_ADDR]], [[A_ADDR_FI:[0-9]+]]($sp) ; CHECK-DAG: lw $[[A_ADDR2:[0-9]+]], [[A_ADDR_FI]]($sp) ; CHECK-DAG: lw $[[A_X:[0-9]+]], 0($[[A_ADDR2]]) diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll index b27b20c8f7191..67b49c6a8ea27 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll @@ -16,10 +16,10 @@ entry: %1 = load float, float* @f2, align 4 %cmp = fcmp oeq float %0, %1 ; CHECK-LABEL: feq1: -; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) -; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) -; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) +; CHECK: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) +; CHECK: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 ; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]] @@ -37,10 +37,10 @@ entry: %1 = load float, float* @f2, align 4 %cmp = fcmp une float %0, %1 ; CHECK-LABEL: fne1: -; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) -; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) -; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) +; CHECK: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) +; CHECK: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 ; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]] @@ -57,10 +57,10 @@ entry: %1 = load float, float* @f2, align 4 %cmp = fcmp olt float %0, %1 ; CHECK-LABEL: flt1: -; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) -; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) -; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) +; CHECK: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) +; CHECK: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 ; CHECK: c.olt.s $f[[REG_F1]], $f[[REG_F2]] @@ -78,10 +78,10 @@ entry: %1 = load float, float* @f2, align 4 %cmp = fcmp ogt float %0, %1 ; CHECK-LABEL: fgt1: -; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) -; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) -; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) +; CHECK: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) +; CHECK: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 ; CHECK: c.ule.s $f[[REG_F1]], $f[[REG_F2]] @@ -98,10 +98,10 @@ entry: %1 = load float, float* @f2, align 4 %cmp = fcmp ole float %0, %1 ; CHECK-LABEL: fle1: -; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) -; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) -; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) +; CHECK: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) +; CHECK: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 ; CHECK: c.ole.s $f[[REG_F1]], $f[[REG_F2]] @@ -118,10 +118,10 @@ entry: %1 = load float, float* @f2, align 4 %cmp = fcmp oge float %0, %1 ; CHECK-LABEL: fge1: -; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) -; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) -; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) +; CHECK: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) +; CHECK: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 ; CHECK: c.ult.s $f[[REG_F1]], $f[[REG_F2]] @@ -138,10 +138,10 @@ entry: %1 = load double, double* @d2, align 8 %cmp = fcmp oeq double %0, %1 ; CHECK-LABEL: deq1: -; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) -; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) -; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) +; CHECK: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) +; CHECK: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 ; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]] @@ -158,10 +158,10 @@ entry: %1 = load double, double* @d2, align 8 %cmp = fcmp une double %0, %1 ; CHECK-LABEL: dne1: -; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) -; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) -; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) +; CHECK: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) +; CHECK: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 ; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]] @@ -178,12 +178,12 @@ entry: %1 = load double, double* @d2, align 8 %cmp = fcmp olt double %0, %1 ; CHECK-LABEL: dlt1: -; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) -; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) -; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) +; CHECK: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) +; CHECK: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) +; CHECK: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK: addiu $[[REG_ONE:[0-9]+]], $zero, 1 ; CHECK: c.olt.d $f[[REG_D1]], $f[[REG_D2]] ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 %conv = zext i1 %cmp to i32 @@ -198,10 +198,10 @@ entry: %1 = load double, double* @d2, align 8 %cmp = fcmp ogt double %0, %1 ; CHECK-LABEL: dgt1: -; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) -; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) -; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) +; CHECK: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) +; CHECK: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 ; CHECK: c.ule.d $f[[REG_D1]], $f[[REG_D2]] @@ -218,10 +218,10 @@ entry: %1 = load double, double* @d2, align 8 %cmp = fcmp ole double %0, %1 ; CHECK-LABEL: dle1: -; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) -; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) -; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) +; CHECK: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) +; CHECK: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 ; CHECK: c.ole.d $f[[REG_D1]], $f[[REG_D2]] @@ -238,10 +238,10 @@ entry: %1 = load double, double* @d2, align 8 %cmp = fcmp oge double %0, %1 ; CHECK-LABEL: dge1: -; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) -; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) -; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) +; CHECK: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) +; CHECK: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 ; CHECK: c.ult.d $f[[REG_D1]], $f[[REG_D2]] diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll index cc19beafd38de..e9bf30ed7b1d8 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll @@ -60,10 +60,10 @@ entry: %1 = load i32, i32* @ud, align 4 %cmp = icmp ugt i32 %0, %1 %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) -; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) +; CHECK: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) +; CHECK: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) +; CHECK: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) +; CHECK: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]] ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 @@ -119,10 +119,10 @@ entry: %1 = load i32, i32* @ud, align 4 %cmp = icmp ule i32 %0, %1 %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) -; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) +; CHECK: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) +; CHECK: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) +; CHECK: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) +; CHECK: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) ; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]] ; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 ; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. @@ -139,10 +139,10 @@ entry: %1 = load i32, i32* @d, align 4 %cmp = icmp sgt i32 %0, %1 %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) -; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) +; CHECK: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) +; CHECK: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) +; CHECK: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) +; CHECK: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) ; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]] ; FIXME: This instruction is redundant. The slt can only produce 0 and 1. ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 @@ -197,10 +197,10 @@ entry: %1 = load i32, i32* @d, align 4 %cmp = icmp sle i32 %0, %1 %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) -; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) +; CHECK: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) +; CHECK: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) +; CHECK: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) +; CHECK: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) ; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]] ; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 ; FIXME: This instruction is redundant. The slt can only produce 0 and 1. diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll b/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll index bd35eeedaf9ae..65ca213235fe7 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll @@ -33,13 +33,13 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]]) ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) ; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]] ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 +; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) ret void } @@ -56,11 +56,11 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) ; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $zero ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 +; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) ; CHECK: .end andUb0 ret void @@ -79,12 +79,12 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1 ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) ; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]] ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 +; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) ; CHECK: .end andUb1 ret void @@ -104,13 +104,13 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]]) ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) ; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]] ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 +; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) ret void } @@ -127,10 +127,10 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) ; CHECK: andi $[[RES:[0-9]+]], $[[UB1]], 1 +; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) ; CHECK: .end orUb0 ret void @@ -148,12 +148,12 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1 ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) ; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]] ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 +; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) ; CHECK: .end orUb1 ret void @@ -173,13 +173,13 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]]) ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) ; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) ; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]] ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 +; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) ret void } @@ -196,11 +196,11 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) ; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB1]], $zero ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 +; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) ; CHECK: .end xorUb0 ret void @@ -218,12 +218,12 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1 ; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) ; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) ; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]] ; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 +; CHECK: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) ; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) ; CHECK: .end xorUb1 ret void diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll b/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll index ed1dc2157355b..6ee50fe3fe99a 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll @@ -15,10 +15,10 @@ entry: %0 = load float*, float** @y, align 4 %arrayidx = getelementptr inbounds float, float* %0, i32 64000 store float 5.500000e+00, float* %arrayidx, align 4 -; CHECK: lui $[[REG_FPCONST_INT:[0-9]+]], 16560 -; CHECK: mtc1 $[[REG_FPCONST_INT]], $f[[REG_FPCONST:[0-9]+]] ; CHECK: lw $[[REG_Y_GOT:[0-9]+]], %got(y)(${{[0-9]+}}) ; CHECK: lw $[[REG_Y:[0-9]+]], 0($[[REG_Y_GOT]]) +; CHECK: lui $[[REG_FPCONST_INT:[0-9]+]], 16560 +; CHECK: mtc1 $[[REG_FPCONST_INT]], $f[[REG_FPCONST:[0-9]+]] ; CHECK: lui $[[REG_IDX_UPPER:[0-9]+]], 3 ; CHECK: ori $[[REG_IDX:[0-9]+]], $[[REG_IDX_UPPER]], 59392 ; CHECK: addu $[[REG_Y_IDX:[0-9]+]], $[[REG_IDX]], $[[REG_Y]] diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll b/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll index 184db73ceab02..871accfff2fef 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll @@ -25,7 +25,7 @@ entry: ; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]]) ; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]]) -; CHECK: sllv $[[RES:[0-9]+]], $[[S1]], $[[S2]] +; CHECK-DAG: sllv $[[RES:[0-9]+]], $[[S1]], $[[S2]] ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) ret void } @@ -39,10 +39,10 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]]) ; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]]) ; CHECK: sll $[[RES:[0-9]+]], $[[S1]], 5 +; CHECK: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]]) ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) ret void } @@ -58,12 +58,12 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]]) ; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]]) ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]]) ; CHECK: srlv $[[RES:[0-9]+]], $[[US1]], $[[US2]] +; CHECK: lw $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]]) ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) } @@ -76,10 +76,10 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]]) ; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) ; CHECK: srl $[[RES:[0-9]+]], $[[US1]], 4 +; CHECK: lw $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]]) ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) ret void } @@ -94,12 +94,12 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]]) ; CHECK-DAG: lw $[[S2_ADDR:[0-9]+]], %got(s2)($[[REG_GP]]) ; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]]) ; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]]) ; CHECK: srav $[[RES:[0-9]+]], $[[S1]], $[[S2]] +; CHECK: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]]) ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) ret void } @@ -113,10 +113,10 @@ entry: ; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) ; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]]) ; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]]) ; CHECK: sra $[[RES:[0-9]+]], $[[S1]], 2 +; CHECK: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]]) ; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) ret void } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll index 5cac57b798a84..49b9375f3fa79 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll @@ -9,8 +9,8 @@ define void @foo() { entry: store i32 12345, i32* @abcd, align 4 -; CHECK: lw $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}}) ; CHECK: addiu $[[REG1:[0-9]+]], $zero, 12345 +; CHECK: lw $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}}) ; CHECK: sw $[[REG1]], 0($[[REG2]]) ret void } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll index 7fc0841e3e706..798c40b161d29 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll @@ -10,8 +10,8 @@ define void @si2_1() #0 { entry: store i32 32767, i32* @ijk, align 4 ; CHECK: .ent si2_1 -; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}}) ; CHECK: addiu $[[REG1:[0-9]+]], $zero, 32767 +; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}}) ; CHECK: sw $[[REG1]], 0($[[REG2]]) ret void @@ -34,8 +34,8 @@ define void @ui2_1() #0 { entry: store i32 65535, i32* @ijk, align 4 ; CHECK: .ent ui2_1 -; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}}) ; CHECK: ori $[[REG1:[0-9]+]], $zero, 65535 +; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}}) ; CHECK: sw $[[REG1]], 0($[[REG2]]) ret void } @@ -45,8 +45,8 @@ define void @ui4_1() #0 { entry: store i32 983040, i32* @ijk, align 4 ; CHECK: .ent ui4_1 -; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}}) ; CHECK: lui $[[REG1:[0-9]+]], 15 +; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}}) ; CHECK: sw $[[REG1]], 0($[[REG2]]) ret void } diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll index 7d37239c4ba3b..f9487d325b029 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll @@ -3,7 +3,7 @@ %struct.S = type { i32, i32 } -define void @ZeroInit(%struct.S* noalias sret %agg.result) { +define void @ZeroInit(%struct.S* noalias sret(%struct.S) %agg.result) { ; MIPS32-LABEL: name: ZeroInit ; MIPS32: bb.1.entry: ; MIPS32: liveins: $a0 @@ -23,7 +23,7 @@ entry: ret void } -define void @CallZeroInit(%struct.S* noalias sret %agg.result) { +define void @CallZeroInit(%struct.S* noalias sret(%struct.S) %agg.result) { ; MIPS32-LABEL: name: CallZeroInit ; MIPS32: bb.1.entry: ; MIPS32: liveins: $a0 @@ -34,6 +34,6 @@ define void @CallZeroInit(%struct.S* noalias sret %agg.result) { ; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp ; MIPS32: RetRA entry: - call void @ZeroInit(%struct.S* sret %agg.result) + call void @ZeroInit(%struct.S* sret(%struct.S) %agg.result) ret void } diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sret_pointer.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sret_pointer.ll index 4e5cbb08fdecd..2f22950340583 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sret_pointer.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sret_pointer.ll @@ -3,7 +3,7 @@ %struct.S = type { i32, i32 } -define void @ZeroInit(%struct.S* noalias sret %agg.result) { +define void @ZeroInit(%struct.S* noalias sret(%struct.S) %agg.result) { ; MIPS32-LABEL: ZeroInit: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: ori $1, $zero, 0 @@ -19,7 +19,7 @@ entry: ret void } -define void @CallZeroInit(%struct.S* noalias sret %agg.result) { +define void @CallZeroInit(%struct.S* noalias sret(%struct.S) %agg.result) { ; MIPS32-LABEL: CallZeroInit: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: addiu $sp, $sp, -24 @@ -33,6 +33,6 @@ define void @CallZeroInit(%struct.S* noalias sret %agg.result) { ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: - call void @ZeroInit(%struct.S* sret %agg.result) + call void @ZeroInit(%struct.S* sret(%struct.S) %agg.result) ret void } diff --git a/llvm/test/CodeGen/Mips/cconv/byval.ll b/llvm/test/CodeGen/Mips/cconv/byval.ll index e3e7eccd26223..180563d1ec943 100644 --- a/llvm/test/CodeGen/Mips/cconv/byval.ll +++ b/llvm/test/CodeGen/Mips/cconv/byval.ll @@ -152,11 +152,11 @@ define dso_local void @g() #0 { ; N64-NEXT: daddu $sp, $sp, $1 entry: %a = alloca %struct.S1, align 4 - call void @f2(%struct.S1* byval align 4 %a) + call void @f2(%struct.S1* byval(%struct.S1) align 4 %a) ret void } -declare dso_local void @f2(%struct.S1* byval align 4) #1 +declare dso_local void @f2(%struct.S1* byval(%struct.S1) align 4) #1 ; O32-SDAG-LABEL: Initial selection DAG: %bb.0 'g2:entry' ; O32-SDAG: t{{.*}}: ch,glue = callseq_start t{{.*}}, TargetConstant:i32<{{.*}}> @@ -348,7 +348,7 @@ entry: %1 = bitcast %struct.S1* %byval-temp to i8* %2 = bitcast %struct.S1* %0 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %1, i8* align 1 %2, i32 65520, i1 false) - call void @f2(%struct.S1* byval align 4 %byval-temp) + call void @f2(%struct.S1* byval(%struct.S1) align 4 %byval-temp) ret void } diff --git a/llvm/test/CodeGen/Mips/cconv/return-struct.ll b/llvm/test/CodeGen/Mips/cconv/return-struct.ll index 83cf14feceed9..d89ad0569631a 100644 --- a/llvm/test/CodeGen/Mips/cconv/return-struct.ll +++ b/llvm/test/CodeGen/Mips/cconv/return-struct.ll @@ -149,7 +149,7 @@ entry: ; Ensure that large structures (>128-bit) are returned indirectly. ; We pick an extremely large structure so we don't have to match inlined memcpy's. -define void @ret_struct_128xi16({[128 x i16]}* sret %returnval) { +define void @ret_struct_128xi16({[128 x i16]}* sret({[128 x i16]}) %returnval) { entry: %0 = bitcast {[128 x i16]}* %returnval to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 %0, i8* align 2 bitcast ({[128 x i16]}* @struct_128xi16 to i8*), i64 256, i1 false) diff --git a/llvm/test/CodeGen/Mips/cprestore.ll b/llvm/test/CodeGen/Mips/cprestore.ll index a618b675c5594..b4489b6e2211a 100644 --- a/llvm/test/CodeGen/Mips/cprestore.ll +++ b/llvm/test/CodeGen/Mips/cprestore.ll @@ -13,8 +13,8 @@ define void @foo2() nounwind { entry: %s = alloca %struct.S, align 4 - call void @foo1(%struct.S* byval %s) + call void @foo1(%struct.S* byval(%struct.S) %s) ret void } -declare void @foo1(%struct.S* byval) +declare void @foo1(%struct.S* byval(%struct.S)) diff --git a/llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll b/llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll index 625abc1a7e04b..042d003a82245 100644 --- a/llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll +++ b/llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll @@ -2,6 +2,9 @@ ; Check that register scavenging spill slot is close to $fp. target triple="mipsel--" +; FIXME: After recent rework to FastISel, don't know how to trigger the +; emergency spill slot. Filed PR48301. +; XFAIL: * @var = external global i32 @ptrvar = external global i8* diff --git a/llvm/test/CodeGen/Mips/fastcc_byval.ll b/llvm/test/CodeGen/Mips/fastcc_byval.ll index 4a55ac7422ce2..135411021dc55 100644 --- a/llvm/test/CodeGen/Mips/fastcc_byval.ll +++ b/llvm/test/CodeGen/Mips/fastcc_byval.ll @@ -5,9 +5,9 @@ %struct.str = type { i32, i32, [3 x i32*] } -declare fastcc void @_Z1F3str(%struct.str* noalias nocapture sret %agg.result, %struct.str* byval nocapture readonly align 4 %s) +declare fastcc void @_Z1F3str(%struct.str* noalias nocapture sret(%struct.str) %agg.result, %struct.str* byval(%struct.str) nocapture readonly align 4 %s) -define i32 @_Z1g3str(%struct.str* byval nocapture readonly align 4 %s) { +define i32 @_Z1g3str(%struct.str* byval(%struct.str) nocapture readonly align 4 %s) { ; CHECK-LABEL: _Z1g3str: ; CHECK: sw $7, [[OFFSET:[0-9]+]]($sp) ; CHECK: lw ${{[0-9]+}}, [[OFFSET]]($sp) @@ -15,7 +15,7 @@ entry: %ref.tmp = alloca %struct.str, align 4 %0 = bitcast %struct.str* %ref.tmp to i8* call void @llvm.lifetime.start.p0i8(i64 20, i8* nonnull %0) - call fastcc void @_Z1F3str(%struct.str* nonnull sret %ref.tmp, %struct.str* byval nonnull align 4 %s) + call fastcc void @_Z1F3str(%struct.str* nonnull sret(%struct.str) %ref.tmp, %struct.str* byval(%struct.str) nonnull align 4 %s) %cl.sroa.3.0..sroa_idx2 = getelementptr inbounds %struct.str, %struct.str* %ref.tmp, i32 0, i32 1 %cl.sroa.3.0.copyload = load i32, i32* %cl.sroa.3.0..sroa_idx2, align 4 call void @llvm.lifetime.end.p0i8(i64 20, i8* nonnull %0) diff --git a/llvm/test/CodeGen/Mips/largeimmprinting.ll b/llvm/test/CodeGen/Mips/largeimmprinting.ll index 6460260f67be6..1d5b9c47b7df2 100644 --- a/llvm/test/CodeGen/Mips/largeimmprinting.ll +++ b/llvm/test/CodeGen/Mips/largeimmprinting.ll @@ -27,10 +27,10 @@ entry: %agg.tmp = alloca %struct.S1, align 1 %tmp = getelementptr inbounds %struct.S1, %struct.S1* %agg.tmp, i32 0, i32 0, i32 0 call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp, i8* align 1 getelementptr inbounds (%struct.S1, %struct.S1* @s1, i32 0, i32 0, i32 0), i32 65536, i1 false) - call void @f2(%struct.S1* byval %agg.tmp) nounwind + call void @f2(%struct.S1* byval(%struct.S1) %agg.tmp) nounwind ret void } -declare void @f2(%struct.S1* byval) +declare void @f2(%struct.S1* byval(%struct.S1)) declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind diff --git a/llvm/test/CodeGen/Mips/load-store-left-right.ll b/llvm/test/CodeGen/Mips/load-store-left-right.ll index 69ad307df7af7..8da37e7a02b41 100644 --- a/llvm/test/CodeGen/Mips/load-store-left-right.ll +++ b/llvm/test/CodeGen/Mips/load-store-left-right.ll @@ -535,8 +535,8 @@ entry: ; MIPS64R6: ld $[[SPTR:[0-9]+]], %got_disp(arr)( - tail call void @extern_func([7 x i8]* byval @arr) nounwind + tail call void @extern_func([7 x i8]* byval([7 x i8]) @arr) nounwind ret void } -declare void @extern_func([7 x i8]* byval) +declare void @extern_func([7 x i8]* byval([7 x i8])) diff --git a/llvm/test/CodeGen/Mips/mips64-sret.ll b/llvm/test/CodeGen/Mips/mips64-sret.ll index 0559747f62cce..8d3d6cbbb58dd 100644 --- a/llvm/test/CodeGen/Mips/mips64-sret.ll +++ b/llvm/test/CodeGen/Mips/mips64-sret.ll @@ -1,6 +1,6 @@ ; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s -define void @foo(i32* noalias sret %agg.result) nounwind { +define void @foo(i32* noalias sret(i32) %agg.result) nounwind { entry: ; CHECK-LABEL: foo: ; CHECK: sw {{.*}}, 0($4) @@ -11,7 +11,7 @@ entry: ret void } -define void @bar(i32 signext %v, i32* noalias sret %agg.result) nounwind { +define void @bar(i32 signext %v, i32* noalias sret(i32) %agg.result) nounwind { entry: ; CHECK-LABEL: bar: ; CHECK: sw $4, 0($5) diff --git a/llvm/test/CodeGen/Mips/o32_cc_byval.ll b/llvm/test/CodeGen/Mips/o32_cc_byval.ll index d9951ebeaf3a9..de17a1e502f43 100644 --- a/llvm/test/CodeGen/Mips/o32_cc_byval.ll +++ b/llvm/test/CodeGen/Mips/o32_cc_byval.ll @@ -81,21 +81,21 @@ define void @f1() nounwind { ; CHECK-NEXT: addiu $sp, $sp, 64 entry: %agg.tmp10 = alloca %struct.S3, align 4 - call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind - call void @callee2(%struct.S2* byval @f1.s2) nounwind + call void @callee1(float 2.000000e+01, %struct.S1* byval(%struct.S1) bitcast (%0* @f1.s1 to %struct.S1*)) nounwind + call void @callee2(%struct.S2* byval(%struct.S2) @f1.s2) nounwind %tmp11 = getelementptr inbounds %struct.S3, %struct.S3* %agg.tmp10, i32 0, i32 0 store i8 11, i8* %tmp11, align 4 - call void @callee3(float 2.100000e+01, %struct.S3* byval %agg.tmp10, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind + call void @callee3(float 2.100000e+01, %struct.S3* byval(%struct.S3) %agg.tmp10, %struct.S1* byval(%struct.S1) bitcast (%0* @f1.s1 to %struct.S1*)) nounwind ret void } -declare void @callee1(float, %struct.S1* byval) +declare void @callee1(float, %struct.S1* byval(%struct.S1)) -declare void @callee2(%struct.S2* byval) +declare void @callee2(%struct.S2* byval(%struct.S2)) -declare void @callee3(float, %struct.S3* byval, %struct.S1* byval) +declare void @callee3(float, %struct.S3* byval(%struct.S3), %struct.S1* byval(%struct.S1)) -define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind { +define void @f2(float %f, %struct.S1* nocapture byval(%struct.S1) %s1) nounwind { ; CHECK-LABEL: f2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lui $2, %hi(_gp_disp) @@ -144,7 +144,7 @@ entry: declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float) -define void @f3(%struct.S2* nocapture byval %s2) nounwind { +define void @f3(%struct.S2* nocapture byval(%struct.S2) %s2) nounwind { ; CHECK-LABEL: f3: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lui $2, %hi(_gp_disp) @@ -184,7 +184,7 @@ entry: ret void } -define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind { +define void @f4(float %f, %struct.S3* nocapture byval(%struct.S3) %s3, %struct.S1* nocapture byval(%struct.S1) %s1) nounwind { ; CHECK-LABEL: f4: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lui $2, %hi(_gp_disp) @@ -230,7 +230,7 @@ entry: %struct.S4 = type { [4 x i32] } -define void @f5(i64 %a0, %struct.S4* nocapture byval %a1) nounwind { +define void @f5(i64 %a0, %struct.S4* nocapture byval(%struct.S4) %a1) nounwind { ; CHECK-LABEL: f5: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lui $2, %hi(_gp_disp) @@ -252,8 +252,8 @@ define void @f5(i64 %a0, %struct.S4* nocapture byval %a1) nounwind { ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $sp, $sp, 32 entry: - tail call void @f6(%struct.S4* byval %a1, i64 %a0) nounwind + tail call void @f6(%struct.S4* byval(%struct.S4) %a1, i64 %a0) nounwind ret void } -declare void @f6(%struct.S4* nocapture byval, i64) +declare void @f6(%struct.S4* nocapture byval(%struct.S4), i64) diff --git a/llvm/test/CodeGen/Mips/tailcall/tailcall.ll b/llvm/test/CodeGen/Mips/tailcall/tailcall.ll index 50759b2104eab..aaa596c425850 100644 --- a/llvm/test/CodeGen/Mips/tailcall/tailcall.ll +++ b/llvm/test/CodeGen/Mips/tailcall/tailcall.ll @@ -192,7 +192,7 @@ entry: @gs1 = external global %struct.S -declare i32 @callee9(%struct.S* byval) +declare i32 @callee9(%struct.S* byval(%struct.S)) define i32 @caller9_0() nounwind { entry: @@ -223,7 +223,7 @@ entry: ; PIC64R6: jalrc $25 ; PIC16: jalrc - %call = tail call i32 @callee9(%struct.S* byval @gs1) nounwind + %call = tail call i32 @callee9(%struct.S* byval(%struct.S) @gs1) nounwind ret i32 %call } @@ -246,7 +246,7 @@ entry: ret i32 %call } -declare i32 @callee11(%struct.S* byval) +declare i32 @callee11(%struct.S* byval(%struct.S)) define i32 @caller11() nounwind noinline { entry: @@ -261,7 +261,7 @@ entry: ; PIC64R6: jalrc $25 ; PIC16: jalrc - %call = tail call i32 @callee11(%struct.S* byval @gs1) nounwind + %call = tail call i32 @callee11(%struct.S* byval(%struct.S) @gs1) nounwind ret i32 %call } @@ -269,7 +269,7 @@ declare i32 @callee12() declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind -define i32 @caller12(%struct.S* nocapture byval %a0) nounwind { +define i32 @caller12(%struct.S* nocapture byval(%struct.S) %a0) nounwind { entry: ; ALL-LABEL: caller12: ; PIC32: jalr $25 diff --git a/llvm/test/CodeGen/Mips/unalignedload.ll b/llvm/test/CodeGen/Mips/unalignedload.ll index 9a4a0456a7e59..14a94313c1cea 100644 --- a/llvm/test/CodeGen/Mips/unalignedload.ll +++ b/llvm/test/CodeGen/Mips/unalignedload.ll @@ -30,7 +30,7 @@ entry: ; MIPS32R6-DAG: lhu $[[PART1:[0-9]+]], 2($[[R0]]) - tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2, %struct.S2* @s2, i32 0, i32 1)) nounwind + tail call void @foo2(%struct.S1* byval(%struct.S1) getelementptr inbounds (%struct.S2, %struct.S2* @s2, i32 0, i32 1)) nounwind ret void } @@ -76,10 +76,10 @@ entry: ; MIPS32R6-EB-DAG: sll $[[T3:[0-9]+]], $[[T1]], 8 ; MIPS32R6-EB-DAG: or $5, $[[T2]], $[[T3]] - tail call void @foo4(%struct.S4* byval @s4) nounwind + tail call void @foo4(%struct.S4* byval(%struct.S4) @s4) nounwind ret void } -declare void @foo2(%struct.S1* byval) +declare void @foo2(%struct.S1* byval(%struct.S1)) -declare void @foo4(%struct.S4* byval) +declare void @foo4(%struct.S4* byval(%struct.S4)) diff --git a/llvm/test/CodeGen/NVPTX/bug21465.ll b/llvm/test/CodeGen/NVPTX/bug21465.ll index 9a221988d901c..03cde33f31c16 100644 --- a/llvm/test/CodeGen/NVPTX/bug21465.ll +++ b/llvm/test/CodeGen/NVPTX/bug21465.ll @@ -7,7 +7,7 @@ target triple = "nvptx64-unknown-unknown" %struct.S = type { i32, i32 } ; Function Attrs: nounwind -define void @_Z11TakesStruct1SPi(%struct.S* byval nocapture readonly %input, i32* nocapture %output) #0 { +define void @_Z11TakesStruct1SPi(%struct.S* byval(%struct.S) nocapture readonly %input, i32* nocapture %output) #0 { entry: ; CHECK-LABEL: @_Z11TakesStruct1SPi ; PTX-LABEL: .visible .entry _Z11TakesStruct1SPi( diff --git a/llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll b/llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll index bdb1d3c546c7a..3430f1eecadcb 100644 --- a/llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll +++ b/llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll @@ -28,7 +28,7 @@ define void @kernel2(float addrspace(1)* %input, float addrspace(1)* %output) { %struct.S = type { i32*, i32* } -define void @ptr_in_byval_kernel(%struct.S* byval %input, i32* %output) { +define void @ptr_in_byval_kernel(%struct.S* byval(%struct.S) %input, i32* %output) { ; CHECK-LABEL: .visible .entry ptr_in_byval_kernel( ; CHECK: ld.param.u64 %[[optr:rd.*]], [ptr_in_byval_kernel_param_1] ; CHECK: cvta.to.global.u64 %[[optr_g:.*]], %[[optr]]; @@ -46,7 +46,7 @@ define void @ptr_in_byval_kernel(%struct.S* byval %input, i32* %output) { ; Regular functions lower byval arguments differently. We need to make ; sure that we're loading byval argument data using [symbol+offset]. ; There's also no assumption that all pointers within are in global space. -define void @ptr_in_byval_func(%struct.S* byval %input, i32* %output) { +define void @ptr_in_byval_func(%struct.S* byval(%struct.S) %input, i32* %output) { ; CHECK-LABEL: .visible .func ptr_in_byval_func( ; CHECK: ld.param.u64 %[[optr:rd.*]], [ptr_in_byval_func_param_1] ; CHECK: ld.param.u64 %[[iptr:rd.*]], [ptr_in_byval_func_param_0+8] diff --git a/llvm/test/CodeGen/NVPTX/param-align.ll b/llvm/test/CodeGen/NVPTX/param-align.ll index 75b6917265e85..b5b27770c455c 100644 --- a/llvm/test/CodeGen/NVPTX/param-align.ll +++ b/llvm/test/CodeGen/NVPTX/param-align.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ;;; Need 4-byte alignment on float* passed byval -define ptx_device void @t1(float* byval %x) { +define ptx_device void @t1(float* byval(float) %x) { ; CHECK: .func t1 ; CHECK: .param .align 4 .b8 t1_param_0[4] ret void @@ -9,7 +9,7 @@ define ptx_device void @t1(float* byval %x) { ;;; Need 8-byte alignment on double* passed byval -define ptx_device void @t2(double* byval %x) { +define ptx_device void @t2(double* byval(double) %x) { ; CHECK: .func t2 ; CHECK: .param .align 8 .b8 t2_param_0[8] ret void @@ -18,7 +18,7 @@ define ptx_device void @t2(double* byval %x) { ;;; Need 4-byte alignment on float2* passed byval %struct.float2 = type { float, float } -define ptx_device void @t3(%struct.float2* byval %x) { +define ptx_device void @t3(%struct.float2* byval(%struct.float2) %x) { ; CHECK: .func t3 ; CHECK: .param .align 4 .b8 t3_param_0[8] ret void @@ -26,19 +26,19 @@ define ptx_device void @t3(%struct.float2* byval %x) { ;;; Need at least 4-byte alignment in order to avoid miscompilation by ;;; ptxas for sm_50+ -define ptx_device void @t4(i8* byval %x) { +define ptx_device void @t4(i8* byval(i8) %x) { ; CHECK: .func t4 ; CHECK: .param .align 4 .b8 t4_param_0[1] ret void } ;;; Make sure we adjust alignment at the call site as well. -define ptx_device void @t5(i8* align 2 byval %x) { +define ptx_device void @t5(i8* align 2 byval(i8) %x) { ; CHECK: .func t5 ; CHECK: .param .align 4 .b8 t5_param_0[1] ; CHECK: { ; CHECK: .param .align 4 .b8 param0[1]; ; CHECK: call.uni - call void @t4(i8* byval %x) + call void @t4(i8* byval(i8) %x) ret void } diff --git a/llvm/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll b/llvm/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll index 3174a7130f002..012450e184ec7 100644 --- a/llvm/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll +++ b/llvm/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll @@ -1,6 +1,6 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc64-- -define void @__divtc3({ ppc_fp128, ppc_fp128 }* noalias sret %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind { +define void @__divtc3({ ppc_fp128, ppc_fp128 }* noalias sret({ ppc_fp128, ppc_fp128 }) %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind { entry: %imag59 = load ppc_fp128, ppc_fp128* null, align 8 ; [#uses=1] %0 = fmul ppc_fp128 0xM00000000000000000000000000000000, %imag59 ; [#uses=1] diff --git a/llvm/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll b/llvm/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll index 6355795e79e70..69280af65458f 100644 --- a/llvm/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll +++ b/llvm/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll @@ -1,6 +1,6 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu.5 -define void @__multc3({ ppc_fp128, ppc_fp128 }* noalias sret %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind { +define void @__multc3({ ppc_fp128, ppc_fp128 }* noalias sret({ ppc_fp128, ppc_fp128 }) %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind { entry: %.pre139 = and i1 false, false ; [#uses=1] br i1 false, label %bb6, label %bb21 diff --git a/llvm/test/CodeGen/PowerPC/MMO-flags-assertion.ll b/llvm/test/CodeGen/PowerPC/MMO-flags-assertion.ll index 64fa85a8195cc..e0550b89d19c1 100644 --- a/llvm/test/CodeGen/PowerPC/MMO-flags-assertion.ll +++ b/llvm/test/CodeGen/PowerPC/MMO-flags-assertion.ll @@ -3,18 +3,18 @@ ; void llvm::MachineMemOperand::refineAlignment(const llvm::MachineMemOperand*): ; Assertion `MMO->getFlags() == getFlags() && "Flags mismatch !"' failed. -declare void @_Z3fn11F(%class.F* byval align 8) local_unnamed_addr +declare void @_Z3fn11F(%class.F* byval(%class.F) align 8) local_unnamed_addr declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) declare signext i32 @_ZN1F11isGlobalRegEv(%class.F*) local_unnamed_addr declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) -declare void @_Z10EmitLValuev(%class.F* sret) local_unnamed_addr +declare void @_Z10EmitLValuev(%class.F* sret(%class.F)) local_unnamed_addr declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) %class.F = type { i32, i64, i8, [64 x i8], i8, i32* } -define signext i32 @_Z29EmitOMPAtomicSimpleUpdateExpr1F(%class.F* byval align 8 %p1) local_unnamed_addr { +define signext i32 @_Z29EmitOMPAtomicSimpleUpdateExpr1F(%class.F* byval(%class.F) align 8 %p1) local_unnamed_addr { entry: - call void @_Z3fn11F(%class.F* byval nonnull align 8 %p1) + call void @_Z3fn11F(%class.F* byval(%class.F) nonnull align 8 %p1) %call = call signext i32 @_ZN1F11isGlobalRegEv(%class.F* nonnull %p1) ret i32 %call } @@ -25,11 +25,11 @@ entry: %XLValue = alloca %class.F, align 8 %0 = bitcast %class.F* %XLValue to i8* call void @llvm.lifetime.start.p0i8(i64 96, i8* nonnull %0) - call void @_Z10EmitLValuev(%class.F* nonnull sret %XLValue) + call void @_Z10EmitLValuev(%class.F* nonnull sret(%class.F) %XLValue) %1 = bitcast %class.F* %agg.tmp1 to i8* call void @llvm.lifetime.start.p0i8(i64 96, i8* nonnull %1) call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 nonnull %1, i8* align 8 nonnull %0, i64 96, i1 false) - call void @_Z3fn11F(%class.F* byval nonnull align 8 %XLValue) + call void @_Z3fn11F(%class.F* byval(%class.F) nonnull align 8 %XLValue) %call.i = call signext i32 @_ZN1F11isGlobalRegEv(%class.F* nonnull %agg.tmp1) call void @llvm.lifetime.end.p0i8(i64 96, i8* nonnull %1) call void @llvm.lifetime.end.p0i8(i64 96, i8* nonnull %0) diff --git a/llvm/test/CodeGen/PowerPC/a2-fp-basic.ll b/llvm/test/CodeGen/PowerPC/a2-fp-basic.ll index e4a7c537d7440..bfb6ba059712f 100644 --- a/llvm/test/CodeGen/PowerPC/a2-fp-basic.ll +++ b/llvm/test/CodeGen/PowerPC/a2-fp-basic.ll @@ -2,7 +2,7 @@ %0 = type { double, double } -define void @maybe_an_fma(%0* sret %agg.result, %0* byval %a, %0* byval %b, %0* byval %c) nounwind { +define void @maybe_an_fma(%0* sret(%0) %agg.result, %0* byval(%0) %a, %0* byval(%0) %b, %0* byval(%0) %c) nounwind { entry: %a.realp = getelementptr inbounds %0, %0* %a, i32 0, i32 0 %a.real = load double, double* %a.realp diff --git a/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll b/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll index 2809aab5a7116..5ed48e98f3e87 100644 --- a/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll +++ b/llvm/test/CodeGen/PowerPC/aix-AppendingLinkage.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < \ ; RUN: %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < \ ; RUN: %s | FileCheck %s @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }] diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll b/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll index 5be6213398dad..a801a65229e47 100644 --- a/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll +++ b/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll @@ -1,12 +1,7 @@ -; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s - -; This test expects a compiler diagnostic for an AIX limitation on Altivec -; support. When the Altivec limitation diagnostic is removed, this test -; should compile clean and fail in order to alert the author to validate the -; instructions emitted to initialize the GPR for the double vararg. -; The mfvsrwz and mfvsrd instructions should be used to initialize the GPR for -; the double vararg without going through memory. +; RUN: llc < %s -mtriple powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr8 2>&1 +; | FileCheck %s --check-prefix=ASM64 +; RUN: llc < %s -mtriple powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr8 2>&1 +; | FileCheck %s --check-prefix=ASM32 @f1 = global float 0.000000e+00, align 4 @@ -20,4 +15,15 @@ entry: declare void @test_vararg(i32, ...) -; CHECK: LLVM ERROR: Altivec support is unimplemented on AIX. + +; ASM64: xscvdpspn +; ASM64: mffprd +; ASM64: xxsldwi +; ASM64: mffprwz + + +; ASM32: lfsx +; ASM32: fmr +; ASM32: stfs +; ASM32: lwz +; ASM32: stfd diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll new file mode 100644 index 0000000000000..120083ed36bd6 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll @@ -0,0 +1,115 @@ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ +; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \ +; RUN: FileCheck --check-prefixes=ASM32,ASM %s + +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ +; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff < %s | \ +; RUN: FileCheck --check-prefixes=ASM64,ASM %s + +define dso_local <4 x i32> @vec_callee(<4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7, <4 x i32> %vec8, <4 x i32> %vec9, <4 x i32> %vec10, <4 x i32> %vec11, <4 x i32> %vec12) { +entry: + %add = add <4 x i32> %vec1, %vec2 + %add1 = add <4 x i32> %add, %vec3 + %add2 = add <4 x i32> %add1, %vec4 + %add3 = add <4 x i32> %add2, %vec5 + %add4 = add <4 x i32> %add3, %vec6 + %add5 = add <4 x i32> %add4, %vec7 + %add6 = add <4 x i32> %add5, %vec8 + %add7 = add <4 x i32> %add6, %vec9 + %add8 = add <4 x i32> %add7, %vec10 + %add9 = add <4 x i32> %add8, %vec11 + %add10 = add <4 x i32> %add9, %vec12 + ret <4 x i32> %add10 +} + +; ASM-LABEL: .vec_callee: + +; ASM: %entry +; ASM-DAG: vadduwm 2, 2, 3 +; ASM-DAG: vadduwm 2, 2, 4 +; ASM-DAG: vadduwm 2, 2, 5 +; ASM-DAG: vadduwm 2, 2, 6 +; ASM-DAG: vadduwm 2, 2, 7 +; ASM-DAG: vadduwm 2, 2, 8 +; ASM-DAG: vadduwm 2, 2, 9 +; ASM-DAG: vadduwm 2, 2, 10 +; ASM-DAG: vadduwm 2, 2, 11 +; ASM-DAG: vadduwm 2, 2, 12 +; ASM-DAG: vadduwm 2, 2, 13 +; ASM: blr + +define dso_local i32 @vec_caller() { +entry: + %call = call <4 x i32> @vec_callee(<4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> ) + ret i32 0 +} + +; ASM-LABEL: .vec_caller: +; ASM32: # %bb.0: # %entry +; ASM32-DAG: mflr 0 +; ASM32-DAG: stw 0, 8(1) +; ASM32-DAG: stwu 1, -64(1) +; ASM32-DAG: lwz [[REG1:[0-9]+]], L..C0(2) +; ASM32-DAG: lxvw4x 34, 0, [[REG1]] +; ASM32-DAG: lwz [[REG2:[0-9]+]], L..C1(2) +; ASM32-DAG: lxvw4x 35, 0, [[REG2]] +; ASM32-DAG: lwz [[REG3:[0-9]+]], L..C2(2) +; ASM32-DAG: lxvw4x 36, 0, [[REG3]] +; ASM32-DAG: lwz [[REG4:[0-9]+]], L..C3(2) +; ASM32-DAG: lxvw4x 37, 0, [[REG4]] +; ASM32-DAG: lwz [[REG5:[0-9]+]], L..C4(2) +; ASM32-DAG: lxvw4x 38, 0, [[REG5]] +; ASM32-DAG: lwz [[REG6:[0-9]+]], L..C5(2) +; ASM32-DAG: lxvw4x 39, 0, [[REG6]] +; ASM32-DAG: lwz [[REG7:[0-9]+]], L..C6(2) +; ASM32-DAG: lxvw4x 40, 0, [[REG7]] +; ASM32-DAG: lwz [[REG8:[0-9]+]], L..C7(2) +; ASM32-DAG: lxvw4x 41, 0, [[REG8]] +; ASM32-DAG: lwz [[REG9:[0-9]+]], L..C8(2) +; ASM32-DAG: lxvw4x 42, 0, [[REG9]] +; ASM32-DAG: lwz [[REG10:[0-9]+]], L..C9(2) +; ASM32-DAG: lxvw4x 43, 0, [[REG10]] +; ASM32-DAG: lwz [[REG11:[0-9]+]], L..C10(2) +; ASM32-DAG: lxvw4x 44, 0, [[REG11]] +; ASM32-DAG: lwz [[REG12:[0-9]+]], L..C11(2) +; ASM32-DAG: lxvw4x 45, 0, [[REG12]] +; ASM32-DAG: bl .vec_callee +; ASM32-DAG: li 3, 0 +; ASM32-DAG: addi 1, 1, 64 +; ASM32-DAG: lwz 0, 8(1) +; ASM32-DAG: mtlr 0 +; ASM32: blr + +; ASM64: # %entry +; ASM64-DAG: std 0, 16(1) +; ASM64-DAG: stdu 1, -112(1) +; ASM64-DAG: ld [[REG1:[0-9]+]], L..C0(2) +; ASM64-DAG: lxvw4x 34, 0, [[REG1]] +; ASM64-DAG: ld [[REG2:[0-9]+]], L..C1(2) +; ASM64-DAG: lxvw4x 35, 0, [[REG2]] +; ASM64-DAG: ld [[REG3:[0-9]+]], L..C2(2) +; ASM64-DAG: lxvw4x 36, 0, [[REG3]] +; ASM64-DAG: ld [[REG4:[0-9]+]], L..C3(2) +; ASM64-DAG: lxvw4x 37, 0, [[REG4]] +; ASM64-DAG: ld [[REG5:[0-9]+]], L..C4(2) +; ASM64-DAG: lxvw4x 38, 0, [[REG5]] +; ASM64-DAG: ld [[REG6:[0-9]+]], L..C5(2) +; ASM64-DAG: lxvw4x 39, 0, [[REG6]] +; ASM64-DAG: ld [[REG7:[0-9]+]], L..C6(2) +; ASM64-DAG: lxvw4x 40, 0, [[REG7]] +; ASM64-DAG: ld [[REG8:[0-9]+]], L..C7(2) +; ASM64-DAG: lxvw4x 41, 0, [[REG8]] +; ASM64-DAG: ld [[REG9:[0-9]+]], L..C8(2) +; ASM64-DAG: lxvw4x 42, 0, [[REG9]] +; ASM64-DAG: ld [[REG10:[0-9]+]], L..C9(2) +; ASM64-DAG: lxvw4x 43, 0, [[REG10]] +; ASM64-DAG: ld [[REG11:[0-9]+]], L..C10(2) +; ASM64-DAG: lxvw4x 44, 0, [[REG11]] +; ASM64-DAG: ld [[REG12:[0-9]+]], L..C11(2) +; ASM64-DAG: lxvw4x 45, 0, [[REG12]] +; ASM64-DAG: bl .vec_callee +; ASM64-DAG: li 3, 0 +; ASM64-DAG: addi 1, 1, 112 +; ASM64-DAG: ld 0, 16(1) +; ASM64-DAG: mtlr 0 +; ASM64: blr diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll new file mode 100644 index 0000000000000..744ec2f63acb7 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll @@ -0,0 +1,308 @@ +; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs -mcpu=pwr7 \ +; RUN: -mattr=+altivec -stop-after=prologepilog < %s | \ +; RUN: FileCheck --check-prefix=MIR32 %s + +; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \ +; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \ +; RUN: FileCheck --check-prefix=ASM32 %s + +; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \ +; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \ +; RUN: FileCheck --check-prefix=MIR64 %s + +; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -vec-extabi -verify-machineinstrs \ +; RUN: -mcpu=pwr7 -mattr=+altivec < %s | \ +; RUN: FileCheck --check-prefix=ASM64 %s + + +define dso_local void @vec_regs() { +entry: + call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"() + ret void +} + +; MIR32: name: vec_regs + +; MIR32-LABEL: fixedStack: +; MIR32-NEXT: - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: stack: + +; MIR32: liveins: $v20, $v26, $v31 + +; MIR32-DAG: STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2) +; MIR32-DAG: STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1) +; MIR32-DAG: STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0) + +; MIR32: INLINEASM + +; MIR32-DAG: $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.2) +; MIR32-DAG: $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1) +; MIR32-DAG: $v31 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0) +; MIR32: BLR implicit $lr, implicit $rm + +; MIR64: name: vec_regs + +; MIR64-LABEL: fixedStack: +; MIR64-NEXT: - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 1, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 2, type: spill-slot, offset: -192, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: stack: + +; MIR64: liveins: $v20, $v26, $v31 + +; MIR64-DAG: STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.2) +; MIR64-DAG: STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1) +; MIR64-DAG: STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0) + +; MIR64: INLINEASM + +; MIR64-DAG: $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.2) +; MIR64-DAG: $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.1) +; MIR64-DAG: $v31 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.0) +; MIR64: BLR8 implicit $lr8, implicit $rm + + +; ASM32-LABEL: .vec_regs: + +; ASM32: li {{[0-9]+}}, -192 +; ASM32-DAG: stxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: li {{[0-9]+}}, -96 +; ASM32-DAG: stxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: li {{[0-9]+}}, -16 +; ASM32-DAG: stxvd2x 63, 1, {{[0-9]+}} # 16-byte Folded Spill +; ASM32: #APP +; ASM32-DAG: #NO_APP +; ASM32-DAG: lxvd2x 63, 1, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: li {{[0-9]+}}, -96 +; ASM32-DAG: lxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: li {{[0-9]+}}, -192 +; ASM32-DAG: lxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Reload +; ASM32: blr + +; ASM64-LABEL: .vec_regs: + +; ASM64-DAG: li {{[0-9]+}}, -192 +; ASM64-DAG: stxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: li {{[0-9]+}}, -96 +; ASM64-DAG: stxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: li {{[0-9]+}}, -16 +; ASM64-DAG: stxvd2x {{[0-9]+}}, 1, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: #APP +; ASM64-DAG: #NO_APP +; ASM64-DAG: lxvd2x {{[0-9]+}}, 1, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: li {{[0-9]+}}, -96 +; ASM64-DAG: lxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: li {{[0-9]+}}, -192 +; ASM64-DAG: lxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: blr + +define dso_local void @fprs_gprs_vecregs() { + call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"() + ret void +} + +; MIR32: name: fprs_gprs_vecregs + +; MIR32-LABEL: fixedStack: +; MIR32-NEXT: - { id: 0, type: spill-slot, offset: -240, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 1, type: spill-slot, offset: -320, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 2, type: spill-slot, offset: -416, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 3, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 4, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 5, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 6, type: spill-slot, offset: -148, size: 4, alignment: 4, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$r31', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 7, type: spill-slot, offset: -172, size: 4, alignment: 4, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$r25', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 8, type: spill-slot, offset: -216, size: 4, alignment: 8, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$r14', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: stack: + +; MIR32: liveins: $r14, $r25, $r31, $f14, $f21, $f31, $v20, $v26, $v31 + +; MIR32-DAG: STW killed $r14, 232, $r1 :: (store 4 into %fixed-stack.8, align 8) +; MIR32-DAG: STW killed $r25, 276, $r1 :: (store 4 into %fixed-stack.7) +; MIR32-DAG: STW killed $r31, 300, $r1 :: (store 4 into %fixed-stack.6) +; MIR32-DAG: STFD killed $f14, 304, $r1 :: (store 8 into %fixed-stack.5, align 16) +; MIR32-DAG: STFD killed $f21, 360, $r1 :: (store 8 into %fixed-stack.4) +; MIR32-DAG: STFD killed $f31, 440, $r1 :: (store 8 into %fixed-stack.3) +; MIR32-DAG: $r{{[0-9]+}} = LI 32 +; MIR32-DAG: STXVD2X killed $v20, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2) +; MIR32-DAG: $r{{[0-9]+}} = LI 128 +; MIR32-DAG: STXVD2X killed $v26, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1) +; MIR32-DAG: $r{{[0-9]+}} = LI 208 +; MIR32-DAG: STXVD2X killed $v31, $r1, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0) +; MIR32-DAG: $r1 = STWU $r1, -448, $r1 + +; MIR32: INLINEASM + +; MIR32-DAG: $r14 = LWZ 232, $r1 :: (load 4 from %fixed-stack.8, align 8) +; MIR32-DAG: $r25 = LWZ 276, $r1 :: (load 4 from %fixed-stack.7) +; MIR32-DAG: $r31 = LWZ 300, $r1 :: (load 4 from %fixed-stack.6) +; MIR32-DAG: $f14 = LFD 304, $r1 :: (load 8 from %fixed-stack.5, align 16) +; MIR32-DAG: $f21 = LFD 360, $r1 :: (load 8 from %fixed-stack.4) +; MIR32-DAG: $f31 = LFD 440, $r1 :: (load 8 from %fixed-stack.3) +; MIR32-DAG: $v20 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.2) +; MIR32-DAG: $r{{[0-9]+}} = LI 32 +; MIR32-DAG: $v26 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1) +; MIR32-DAG: $r{{[0-9]+}} = LI 128 +; MIR32-DAG: $v31 = LXVD2X $r1, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0) +; MIR32-DAG: $r{{[0-9]+}} = LI 208 +; MIR32-DAG: $r1 = ADDI $r1, 448 +; MIR32-DAG: BLR implicit $lr, implicit $rm + +; MIR64: name: fprs_gprs_vecregs + +; MIR64-LABEL: fixedStack: +; MIR64-NEXT: - { id: 0, type: spill-slot, offset: -304, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 1, type: spill-slot, offset: -384, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 2, type: spill-slot, offset: -480, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v20', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 3, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 4, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 5, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 6, type: spill-slot, offset: -152, size: 8, alignment: 8, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$x31', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 7, type: spill-slot, offset: -200, size: 8, alignment: 8, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$x25', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 8, type: spill-slot, offset: -288, size: 8, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$x14', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: stack: + +; MIR64: liveins: $x14, $x25, $x31, $f14, $f21, $f31, $v20, $v26, $v31 + +; MIR64-DAG: $x1 = STDU $x1, -544, $x1 +; MIR64-DAG: STD killed $x14, 256, $x1 :: (store 8 into %fixed-stack.8, align 16) +; MIR64-DAG: STD killed $x25, 344, $x1 :: (store 8 into %fixed-stack.7) +; MIR64-DAG: STD killed $x31, 392, $x1 :: (store 8 into %fixed-stack.6) +; MIR64-DAG: STFD killed $f14, 400, $x1 :: (store 8 into %fixed-stack.5, align 16) +; MIR64-DAG: STFD killed $f21, 456, $x1 :: (store 8 into %fixed-stack.4) +; MIR64-DAG: STFD killed $f31, 536, $x1 :: (store 8 into %fixed-stack.3) +; MIR64-DAG: $x{{[0-9]+}} = LI8 64 +; MIR64-DAG: STXVD2X killed $v20, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.2) +; MIR64-DAG: $x{{[0-9]+}} = LI8 160 +; MIR64-DAG: STXVD2X killed $v26, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1) +; MIR64-DAG: $x{{[0-9]+}} = LI8 240 +; MIR64-DAG: STXVD2X killed $v31, $x1, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0) + +; MIR64: INLINEASM + +; MIR64-DAG: $x14 = LD 256, $x1 :: (load 8 from %fixed-stack.8, align 16) +; MIR64-DAG: $x25 = LD 344, $x1 :: (load 8 from %fixed-stack.7) +; MIR64-DAG: $x31 = LD 392, $x1 :: (load 8 from %fixed-stack.6) +; MIR64-DAG: $f14 = LFD 400, $x1 :: (load 8 from %fixed-stack.5, align 16) +; MIR64-DAG: $f21 = LFD 456, $x1 :: (load 8 from %fixed-stack.4) +; MIR64-DAG: $f31 = LFD 536, $x1 :: (load 8 from %fixed-stack.3) +; MIR64-DAG: $v20 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.2) +; MIR64-DAG: $x{{[0-9]+}} = LI8 64 +; MIR64-DAG: $v26 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.1) +; MIR64-DAG: $x{{[0-9]+}} = LI8 160 +; MIR64-DAG: $v31 = LXVD2X $x1, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.0) +; MIR64-DAG: $x{{[0-9]+}} = LI8 240 +; MIR64-DAG: $x1 = ADDI8 $x1, 544 +; MIR64-DAG: BLR8 implicit $lr8, implicit $rm + +; ASM32-LABEL: .fprs_gprs_vecregs: + +; ASM32: stwu 1, -448(1) +; ASM32-DAG: li {{[0-9]+}}, 32 +; ASM32-DAG: stw 14, 232(1) # 4-byte Folded Spill +; ASM32-DAG: stfd 14, 304(1) # 8-byte Folded Spill +; ASM32-DAG: stxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: li {{[0-9]+}}, 128 +; ASM32-DAG: stw 25, 276(1) # 4-byte Folded Spill +; ASM32-DAG: stxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: li {{[0-9]+}}, 208 +; ASM32-DAG: stw 31, 300(1) # 4-byte Folded Spill +; ASM32-DAG: stfd 21, 360(1) # 8-byte Folded Spill +; ASM32-DAG: stfd 31, 440(1) # 8-byte Folded Spill +; ASM32-DAG: stxvd2x 63, 1, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: #APP +; ASM32-DAG: #NO_APP +; ASM32-DAG: lxvd2x 63, 1, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: li {{[0-9]+}}, 128 +; ASM32-DAG: lfd 31, 440(1) # 8-byte Folded Reload +; ASM32-DAG: lxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: li {{[0-9]+}}, 32 +; ASM32-DAG: lfd 21, 360(1) # 8-byte Folded Reload +; ASM32-DAG: lxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: lfd 14, 304(1) # 8-byte Folded Reload +; ASM32-DAG: lwz 31, 300(1) # 4-byte Folded Reload +; ASM32-DAG: lwz 25, 276(1) # 4-byte Folded Reload +; ASM32-DAG: lwz 14, 232(1) # 4-byte Folded Reload +; ASM32-DAG: addi 1, 1, 448 +; ASM32: blr + +; ASM64-LABEL .fprs_gprs_vecregs: + +; ASM64: stdu 1, -544(1) +; ASM64-DAG: li {{[0-9]+}}, 64 +; ASM64-DAG: std 14, 256(1) # 8-byte Folded Spill +; ASM64-DAG: stfd 14, 400(1) # 8-byte Folded Spill +; ASM64-DAG: stxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: li {{[0-9]+}}, 160 +; ASM64-DAG: std 25, 344(1) # 8-byte Folded Spill +; ASM64-DAG: stxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: li {{[0-9]+}}, 240 +; ASM64-DAG: std 31, 392(1) # 8-byte Folded Spill +; ASM64-DAG: stfd 21, 456(1) # 8-byte Folded Spill +; ASM64-DAG: stfd 31, 536(1) # 8-byte Folded Spill +; ASM64-DAG: stxvd2x 63, 1, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: #APP +; ASM64-DAG: #NO_APP +; ASM64-DAG: lxvd2x 63, 1, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: li {{[0-9]+}}, 160 +; ASM64-DAG: lfd 31, 536(1) # 8-byte Folded Reload +; ASM64-DAG: lxvd2x 58, 1, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: li {{[0-9]+}}, 64 +; ASM64-DAG: lfd 21, 456(1) # 8-byte Folded Reload +; ASM64-DAG: lxvd2x 52, 1, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: lfd 14, 400(1) # 8-byte Folded Reload +; ASM64-DAG: ld 31, 392(1) # 8-byte Folded Reload +; ASM64-DAG: ld 25, 344(1) # 8-byte Folded Reload +; ASM64-DAG: ld 14, 256(1) # 8-byte Folded Reload +; ASM64-DAG: addi 1, 1, 544 +; ASM64: blr diff --git a/llvm/test/CodeGen/PowerPC/aix-func-align.ll b/llvm/test/CodeGen/PowerPC/aix-func-align.ll index 6d69a4f55a951..2e7ea176b14c5 100644 --- a/llvm/test/CodeGen/PowerPC/aix-func-align.ll +++ b/llvm/test/CodeGen/PowerPC/aix-func-align.ll @@ -1,9 +1,9 @@ ; This test tries to verify if a csect containing code would have the correct alignment. -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s ; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ diff --git a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll index 27cd5b5ba190e..e87f9e7e22551 100644 --- a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll +++ b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --symbols %t.o | FileCheck %s define void @foo() { diff --git a/llvm/test/CodeGen/PowerPC/aix-internal.ll b/llvm/test/CodeGen/PowerPC/aix-internal.ll index 1a1fb78dfaf76..6f3ce858f6e85 100644 --- a/llvm/test/CodeGen/PowerPC/aix-internal.ll +++ b/llvm/test/CodeGen/PowerPC/aix-internal.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple powerpc-ibm-aix -verify-machineinstrs -mcpu=pwr4 \ +; RUN: llc -mtriple powerpc-ibm-aix -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ ; RUN: -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --syms %t.o | FileCheck %s -; RUN: not --crash llc -mtriple powerpc64-ibm-aix -verify-machineinstrs -mcpu=pwr4 \ +; RUN: not --crash llc -mtriple powerpc64-ibm-aix -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ ; RUN: -filetype=obj -o %t.o < %s 2>&1 | FileCheck --check-prefix=64-CHECK %s define internal i32 @foo() { diff --git a/llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll b/llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll index 4db879aec0f13..73452d51d4ad9 100644 --- a/llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll +++ b/llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll @@ -1,29 +1,29 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \ ; RUN: --check-prefix=32SMALL-MIR %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \ ; RUN: --check-prefix=32LARGE-MIR %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \ ; RUN: --check-prefix=64SMALL-MIR %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \ ; RUN: --check-prefix=64LARGE-MIR %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,SMALL-ASM %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,LARGE-ASM %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,SMALL-ASM %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,LARGE-ASM %s define void @foo() { diff --git a/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll b/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll index d125b89889ed8..c774412e6b55f 100644 --- a/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll +++ b/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll @@ -1,29 +1,29 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \ ; RUN: --check-prefix=32SMALL-MIR %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \ ; RUN: --check-prefix=32LARGE-MIR %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \ ; RUN: --check-prefix=64SMALL-MIR %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \ ; RUN: --check-prefix=64LARGE-MIR %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,SMALL-ASM %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,LARGE-ASM %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,SMALL-ASM %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,LARGE-ASM %s define float @test_float() { diff --git a/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll b/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll index 78ef175e11480..ec3d9c3c03f18 100644 --- a/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll +++ b/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll @@ -1,16 +1,16 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \ ; RUN: --check-prefix=32SMALL-MIR %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \ ; RUN: --check-prefix=32LARGE-MIR %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \ ; RUN: --check-prefix=64SMALL-MIR %s -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \ ; RUN: --check-prefix=64LARGE-MIR %s diff --git a/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll b/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll index 72661bf5379f6..0bb393b7dd79c 100644 --- a/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll +++ b/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -data-sections=false < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -data-sections=false < %s | FileCheck --check-prefix=CHECK64 %s @foo_ptr = global void (...)* @foo diff --git a/llvm/test/CodeGen/PowerPC/aix-return55.ll b/llvm/test/CodeGen/PowerPC/aix-return55.ll index 344437c66f95e..83d95fce1528a 100644 --- a/llvm/test/CodeGen/PowerPC/aix-return55.ll +++ b/llvm/test/CodeGen/PowerPC/aix-return55.ll @@ -1,5 +1,5 @@ -; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s -; RUN: llc -mcpu=pwr4 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s +; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false < %s | FileCheck %s +; RUN: llc -mcpu=pwr4 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs -data-sections=false -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -sections %t.o | FileCheck --check-prefix=CHECKSECT %s diff --git a/llvm/test/CodeGen/PowerPC/aix-space.ll b/llvm/test/CodeGen/PowerPC/aix-space.ll index d681d636e66a8..27a87676fba2f 100644 --- a/llvm/test/CodeGen/PowerPC/aix-space.ll +++ b/llvm/test/CodeGen/PowerPC/aix-space.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s @a = common global double 0.000000e+00, align 8 diff --git a/llvm/test/CodeGen/PowerPC/aix-sret-param.ll b/llvm/test/CodeGen/PowerPC/aix-sret-param.ll index 98f3dccc6bb40..3547be0b69ad4 100644 --- a/llvm/test/CodeGen/PowerPC/aix-sret-param.ll +++ b/llvm/test/CodeGen/PowerPC/aix-sret-param.ll @@ -18,19 +18,19 @@ define void @test1() { entry: %s = alloca %struct.S, align 4 - call void @foo(%struct.S* sret %s) + call void @foo(%struct.S* sret(%struct.S) %s) ret void } define void @test2() { entry: %t = alloca %struct.T, align 8 - call void @bar(%struct.T* sret %t) + call void @bar(%struct.T* sret(%struct.T) %t) ret void } -declare void @foo(%struct.S* sret) -declare void @bar(%struct.T* sret) +declare void @foo(%struct.S* sret(%struct.S)) +declare void @bar(%struct.T* sret(%struct.T)) ; MIR: name: test1 ; MIR: stack: diff --git a/llvm/test/CodeGen/PowerPC/aix-static-init-non-default-priority.ll b/llvm/test/CodeGen/PowerPC/aix-static-init-non-default-priority.ll index 96566a912bb8e..81777c2dec140 100644 --- a/llvm/test/CodeGen/PowerPC/aix-static-init-non-default-priority.ll +++ b/llvm/test/CodeGen/PowerPC/aix-static-init-non-default-priority.ll @@ -1,10 +1,146 @@ -; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s -; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s -@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 655, void ()* @foo, i8* null }] +@llvm.global_ctors = appending global [5 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 0, void ()* bitcast (i32 (i32)* @cf1 to void ()*), i8* null }, { i32, void ()*, i8* } { i32 21, void ()* @cf2, i8* null }, { i32, void ()*, i8* } { i32 81, void ()* @cf3, i8* null }, { i32, void ()*, i8* } { i32 1125, void ()* @cf4, i8* null }, { i32, void ()*, i8* } { i32 64512, void ()* @cf5, i8* null }] +@llvm.global_dtors = appending global [5 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 20, void ()* bitcast (i32 (i32)* @df1 to void ()*), i8* null }, { i32, void ()*, i8* } { i32 80, void ()* @df2, i8* null }, { i32, void ()*, i8* } { i32 1124, void ()* @df3, i8* null }, { i32, void ()*, i8* } { i32 64511, void ()* @df4, i8* null }, { i32, void ()*, i8* } { i32 65535, void ()* @df5, i8* null }] -define void @foo() { +define i32 @cf1(i32 %a) { + ret i32 %a +} + +define void @cf2() { + ret void +} + +define void @cf3() { + ret void +} + +define void @cf4() { + ret void +} + +define void @cf5() { ret void } -; CHECK: LLVM ERROR: prioritized sinit and sterm functions are not yet supported +define i32 @df1(i32 %a) { + ret i32 %a +} + +define void @df2() { + ret void +} + +define void @df3() { + ret void +} + +define void @df4() { + ret void +} + +define void @df5() { + ret void +} + +; CHECK: .globl cf1[DS] +; CHECK: .globl .cf1 +; CHECK: .align 2 +; CHECK: .csect cf1[DS] +; CHECK: __sinit00000000_clang_f6a1bc9396775a64c6249effda300afe_0: # @cf1 +; CHECK: .cf1: +; CHECK: .__sinit00000000_clang_f6a1bc9396775a64c6249effda300afe_0: + +; CHECK: .globl cf2[DS] +; CHECK: .globl .cf2 +; CHECK: .align 2 +; CHECK: .csect cf2[DS] +; CHECK: __sinit00000024_clang_f6a1bc9396775a64c6249effda300afe_1: # @cf2 +; CHECK: .cf2: +; CHECK: .__sinit00000024_clang_f6a1bc9396775a64c6249effda300afe_1: + +; CHECK: .globl cf3[DS] +; CHECK: .globl .cf3 +; CHECK: .align 2 +; CHECK: .csect cf3[DS] +; CHECK: __sinit000003ec_clang_f6a1bc9396775a64c6249effda300afe_2: # @cf3 +; CHECK: .cf3: +; CHECK: .__sinit000003ec_clang_f6a1bc9396775a64c6249effda300afe_2: + +; CHECK: .globl cf4[DS] +; CHECK: .globl .cf4 +; CHECK: .align 2 +; CHECK: .csect cf4[DS] +; CHECK: __sinit00008c55_clang_f6a1bc9396775a64c6249effda300afe_3: # @cf4 +; CHECK: .cf4: +; CHECK: .__sinit00008c55_clang_f6a1bc9396775a64c6249effda300afe_3: + +; CHECK: .globl cf5[DS] +; CHECK: .globl .cf5 +; CHECK: .align 2 +; CHECK: .csect cf5[DS] +; CHECK: __sinit7ffffc01_clang_f6a1bc9396775a64c6249effda300afe_4: # @cf5 +; CHECK: .cf5: +; CHECK: .__sinit7ffffc01_clang_f6a1bc9396775a64c6249effda300afe_4: + +; CHECK: .globl df1[DS] +; CHECK: .globl .df1 +; CHECK: .align 2 +; CHECK: .csect df1[DS] +; CHECK: __sterm00000014_clang_f6a1bc9396775a64c6249effda300afe_0: # @df1 +; CHECK: .df1: +; CHECK: .__sterm00000014_clang_f6a1bc9396775a64c6249effda300afe_0: + +; CHECK: .globl df2[DS] +; CHECK: .globl .df2 +; CHECK: .align 2 +; CHECK: .csect df2[DS] +; CHECK: __sterm000003d4_clang_f6a1bc9396775a64c6249effda300afe_1: # @df2 +; CHECK: .df2: +; CHECK: .__sterm000003d4_clang_f6a1bc9396775a64c6249effda300afe_1: + +; CHECK: .globl df3[DS] +; CHECK: .globl .df3 +; CHECK: .align 2 +; CHECK: .csect df3[DS] +; CHECK: __sterm000007ff_clang_f6a1bc9396775a64c6249effda300afe_2: # @df3 +; CHECK: .df3: +; CHECK: .__sterm000007ff_clang_f6a1bc9396775a64c6249effda300afe_2: + +; CHECK: .globl df4[DS] +; CHECK: .globl .df4 +; CHECK: .align 2 +; CHECK: .csect df4[DS] +; CHECK: __sterm7fff2211_clang_f6a1bc9396775a64c6249effda300afe_3: # @df4 +; CHECK: .df4: +; CHECK: .__sterm7fff2211_clang_f6a1bc9396775a64c6249effda300afe_3: + +; CHECK: .globl df5[DS] +; CHECK: .globl .df5 +; CHECK: .align 2 +; CHECK: .csect df5[DS] +; CHECK: __sterm80000000_clang_f6a1bc9396775a64c6249effda300afe_4: # @df5 +; CHECK: .df5: +; CHECK: .__sterm80000000_clang_f6a1bc9396775a64c6249effda300afe_4: + +; CHECK: .globl __sinit00000000_clang_f6a1bc9396775a64c6249effda300afe_0 +; CHECK: .globl .__sinit00000000_clang_f6a1bc9396775a64c6249effda300afe_0 +; CHECK: .globl __sinit00000024_clang_f6a1bc9396775a64c6249effda300afe_1 +; CHECK: .globl .__sinit00000024_clang_f6a1bc9396775a64c6249effda300afe_1 +; CHECK: .globl __sinit000003ec_clang_f6a1bc9396775a64c6249effda300afe_2 +; CHECK: .globl .__sinit000003ec_clang_f6a1bc9396775a64c6249effda300afe_2 +; CHECK: .globl __sinit00008c55_clang_f6a1bc9396775a64c6249effda300afe_3 +; CHECK: .globl .__sinit00008c55_clang_f6a1bc9396775a64c6249effda300afe_3 +; CHECK: .globl __sinit7ffffc01_clang_f6a1bc9396775a64c6249effda300afe_4 +; CHECK: .globl .__sinit7ffffc01_clang_f6a1bc9396775a64c6249effda300afe_4 +; CHECK: .globl __sterm00000014_clang_f6a1bc9396775a64c6249effda300afe_0 +; CHECK: .globl .__sterm00000014_clang_f6a1bc9396775a64c6249effda300afe_0 +; CHECK: .globl __sterm000003d4_clang_f6a1bc9396775a64c6249effda300afe_1 +; CHECK: .globl .__sterm000003d4_clang_f6a1bc9396775a64c6249effda300afe_1 +; CHECK: .globl __sterm000007ff_clang_f6a1bc9396775a64c6249effda300afe_2 +; CHECK: .globl .__sterm000007ff_clang_f6a1bc9396775a64c6249effda300afe_2 +; CHECK: .globl __sterm7fff2211_clang_f6a1bc9396775a64c6249effda300afe_3 +; CHECK: .globl .__sterm7fff2211_clang_f6a1bc9396775a64c6249effda300afe_3 +; CHECK: .globl __sterm80000000_clang_f6a1bc9396775a64c6249effda300afe_4 +; CHECK: .globl .__sterm80000000_clang_f6a1bc9396775a64c6249effda300afe_4 diff --git a/llvm/test/CodeGen/PowerPC/aix-vec-abi.ll b/llvm/test/CodeGen/PowerPC/aix-vec-abi.ll new file mode 100644 index 0000000000000..9dac55c37b93b --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-vec-abi.ll @@ -0,0 +1,8 @@ +; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR +; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR + +define void @vec_callee(<4 x i32> %vec1) { + ret void +} + +; DFLTERROR: LLVM ERROR: the default Altivec AIX ABI is not yet supported diff --git a/llvm/test/CodeGen/PowerPC/aix-vector-return.ll b/llvm/test/CodeGen/PowerPC/aix-vector-return.ll deleted file mode 100644 index b4e39d6c05fe1..0000000000000 --- a/llvm/test/CodeGen/PowerPC/aix-vector-return.ll +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: not --crash llc --verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff \ -; RUN: -mattr=+altivec 2>&1 < %s | FileCheck %s - -; RUN: not --crash llc --verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \ -; RUN: -mattr=+altivec 2>&1 < %s | FileCheck %s - -; CHECK: LLVM ERROR: Returning vector types not yet supported on AIX. - -define dso_local <4 x i32> @test() local_unnamed_addr #0 { - entry: - ret <4 x i32> zeroinitializer -} diff --git a/llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll b/llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll new file mode 100644 index 0000000000000..63653f524c5d6 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll @@ -0,0 +1,17 @@ +; RUN: not --crash llc < %s -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ +; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff 2>&1 | \ +; RUN: FileCheck %s --check-prefix=AIX-ERROR + +; RUN: not --crash llc < %s -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ +; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff 2>&1 | \ +; RUN: FileCheck %s --check-prefix=AIX-ERROR + +define dso_local i32 @vec_caller() { +entry: + %call = call i32 bitcast (i32 (...)* @vec_callee_stack to i32 (<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>)*)(<4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> , <4 x i32> ) + ret i32 0 +} + +declare i32 @vec_callee_stack(...) + +; AIX-ERROR: LLVM ERROR: passing vector parameters to the stack is unimplemented for AIX diff --git a/llvm/test/CodeGen/PowerPC/aix-vector-stack.ll b/llvm/test/CodeGen/PowerPC/aix-vector-stack.ll new file mode 100644 index 0000000000000..8809de9c5019d --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-vector-stack.ll @@ -0,0 +1,27 @@ +; RUN: not --crash llc < %s -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ +; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff 2>&1 | \ +; RUN: FileCheck %s --check-prefix=AIX-ERROR + +; RUN: not --crash llc < %s -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \ +; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff 2>&1 | \ +; RUN: FileCheck %s --check-prefix=AIX-ERROR + +define dso_local <4 x i32> @vec_callee_stack(<4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7, <4 x i32> %vec8, <4 x i32> %vec9, <4 x i32> %vec10, <4 x i32> %vec11, <4 x i32> %vec12, <4 x i32> %vec13, <4 x i32> %vec14) { +entry: + %add = add <4 x i32> %vec1, %vec2 + %add1 = add <4 x i32> %add, %vec3 + %add2 = add <4 x i32> %add1, %vec4 + %add3 = add <4 x i32> %add2, %vec5 + %add4 = add <4 x i32> %add3, %vec6 + %add5 = add <4 x i32> %add4, %vec7 + %add6 = add <4 x i32> %add5, %vec8 + %add7 = add <4 x i32> %add6, %vec9 + %add8 = add <4 x i32> %add7, %vec10 + %add9 = add <4 x i32> %add8, %vec11 + %add10 = add <4 x i32> %add9, %vec12 + %add11 = add <4 x i32> %add10, %vec13 + %add12 = add <4 x i32> %add11, %vec14 + ret <4 x i32> %add12 +} + +; AIX-ERROR: LLVM ERROR: passing vector parameters to the stack is unimplemented for AIX diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll index 3d72a4bcfcbfd..708177f6c37da 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll @@ -1,26 +1,26 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -data-sections -o %t.o < %s ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s ;; Test to see if the default is correct for -data-sections on AIX. -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s ;; Test to see if the default is correct for -data-sections on AIX. -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll index 5e8c155a7b924..643e8810b1fbe 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll @@ -1,6 +1,6 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll index 0cf2022d2f2c5..dbb3349f36924 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll @@ -1,10 +1,10 @@ ; This file tests the codegen of mergeable const in AIX assembly. ; This file also tests mergeable const in XCOFF object file generation. -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | \ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll index f4fe2744c9ce5..3cb860d95cb12 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll @@ -3,12 +3,12 @@ ; the test in this file should be merged into aix-xcoff-data.ll with additional ; tests for XCOFF object files. -; RUN: llc -verify-machineinstrs -mcpu=pwr4 \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ ; RUN: -mtriple powerpc-ibm-aix-xcoff -data-sections=false < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ ; RUN: -mtriple powerpc64-ibm-aix-xcoff -data-sections=false < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s @magic16 = private unnamed_addr constant [4 x i16] [i16 264, i16 272, i16 213, i16 0], align 2 diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll index 18aea72f6681f..0f2c0ed2beec3 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -filetype=obj -code-model=large -o %t.o < %s ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefixes=RELOC %s ; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll index d68fe8bdf2b48..5410b03ab844b 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-textdisassembly.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECK %s define i32 @foo() #0 { diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll index 5fa60f4eda08d..730fdadafb396 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll @@ -1,12 +1,12 @@ ; This file tests TOC entry generation and undefined symbol generation. -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64 %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes CHECK,CHECK32 %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck --check-prefixes CHECK,CHECK64 %s -; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s +; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \ +; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \ ; RUN: < %s | FileCheck --check-prefix=XCOFF64 %s ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/aix32-crsave.mir b/llvm/test/CodeGen/PowerPC/aix32-crsave.mir index 8faf10233f7db..5622c963d933f 100644 --- a/llvm/test/CodeGen/PowerPC/aix32-crsave.mir +++ b/llvm/test/CodeGen/PowerPC/aix32-crsave.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 \ +# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \ # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \ # RUN: FileCheck %s --check-prefixes=CHECK diff --git a/llvm/test/CodeGen/PowerPC/anon_aggr.ll b/llvm/test/CodeGen/PowerPC/anon_aggr.ll index cc07c4843655a..ca29ad889e2b2 100644 --- a/llvm/test/CodeGen/PowerPC/anon_aggr.ll +++ b/llvm/test/CodeGen/PowerPC/anon_aggr.ll @@ -25,7 +25,7 @@ unequal: ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) -define i8* @func2({ i64, i8* } %array1, %tarray* byval %array2) { +define i8* @func2({ i64, i8* } %array1, %tarray* byval(%tarray) %array2) { entry: %array1_ptr = extractvalue {i64, i8* } %array1, 1 %tmp = getelementptr inbounds %tarray, %tarray* %array2, i32 0, i32 1 @@ -46,7 +46,7 @@ unequal: ; CHECK: ld 3, -[[OFFSET1]](1) ; CHECK: ld 3, -[[OFFSET2]](1) -define i8* @func3({ i64, i8* }* byval %array1, %tarray* byval %array2) { +define i8* @func3({ i64, i8* }* byval({ i64, i8* }) %array1, %tarray* byval(%tarray) %array2) { entry: %tmp1 = getelementptr inbounds { i64, i8* }, { i64, i8* }* %array1, i32 0, i32 1 %array1_ptr = load i8*, i8** %tmp1 @@ -69,7 +69,7 @@ unequal: define i8* @func4(i64 %p1, i64 %p2, i64 %p3, i64 %p4, i64 %p5, i64 %p6, i64 %p7, i64 %p8, - { i64, i8* } %array1, %tarray* byval %array2) { + { i64, i8* } %array1, %tarray* byval(%tarray) %array2) { entry: %array1_ptr = extractvalue {i64, i8* } %array1, 1 %tmp = getelementptr inbounds %tarray, %tarray* %array2, i32 0, i32 1 diff --git a/llvm/test/CodeGen/PowerPC/byval-agg-info.ll b/llvm/test/CodeGen/PowerPC/byval-agg-info.ll index 21aa5821c88d0..d78ea09d37e14 100644 --- a/llvm/test/CodeGen/PowerPC/byval-agg-info.ll +++ b/llvm/test/CodeGen/PowerPC/byval-agg-info.ll @@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.anon = type { i32, i32 } declare void @foo(%struct.anon* %v) -define void @test(i32 %a, i32 %b, %struct.anon* byval nocapture %v) { +define void @test(i32 %a, i32 %b, %struct.anon* byval(%struct.anon) nocapture %v) { entry: call void @foo(%struct.anon* %v) ret void diff --git a/llvm/test/CodeGen/PowerPC/byval-aliased.ll b/llvm/test/CodeGen/PowerPC/byval-aliased.ll index 8c8cbc0e71d9a..18d748defa14c 100644 --- a/llvm/test/CodeGen/PowerPC/byval-aliased.ll +++ b/llvm/test/CodeGen/PowerPC/byval-aliased.ll @@ -1,11 +1,11 @@ ; RUN: llc -verify-machineinstrs -mcpu=ppc64 -ppc-asm-full-reg-names < %s | FileCheck %s target datalayout = "E-m:o-p:32:32-f64:32:64-n32" target triple = "powerpc-unknown-linux-gnu" - + %struct.sm = type { i8, i8 } - + ; Function Attrs: nounwind ssp -define void @foo(%struct.sm* byval %s) #0 { +define void @foo(%struct.sm* byval(%struct.sm) %s) #0 { entry: %a = getelementptr inbounds %struct.sm, %struct.sm* %s, i32 0, i32 0 %0 = load i8, i8* %a, align 1 @@ -13,7 +13,7 @@ entry: %add = add nuw nsw i32 %conv2, 3 %conv1 = trunc i32 %add to i8 store i8 %conv1, i8* %a, align 1 - call void @bar(%struct.sm* byval %s, %struct.sm* byval %s) #1 + call void @bar(%struct.sm* byval(%struct.sm) %s, %struct.sm* byval(%struct.sm) %s) #1 ret void } @@ -22,9 +22,9 @@ entry: ; CHECK: lhz r4, [[OFF]]({{r[3?1]}}) ; CHECK: bl bar ; CHECK: blr - -declare void @bar(%struct.sm* byval, %struct.sm* byval) - + +declare void @bar(%struct.sm* byval(%struct.sm), %struct.sm* byval(%struct.sm)) + attributes #0 = { nounwind ssp } attributes #1 = { nounwind } - + diff --git a/llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll b/llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll new file mode 100644 index 0000000000000..0bf8b47dbc631 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll @@ -0,0 +1,28 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --verify-machineinstrs -mtriple powerpc-unknown-freebsd \ +; RUN: -mcpu=pwr4 < %s | FileCheck %s + +define double @postinctodbl(i64* nocapture %llp) #0 { +; CHECK-LABEL: postinctodbl: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: stwu 1, -16(1) +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: lwz 4, 4(3) +; CHECK-NEXT: stw 4, 12(1) +; CHECK-NEXT: addic 4, 4, 1 +; CHECK-NEXT: lwz 5, 0(3) +; CHECK-NEXT: stw 5, 8(1) +; CHECK-NEXT: addze 5, 5 +; CHECK-NEXT: lfd 0, 8(1) +; CHECK-NEXT: stw 5, 0(3) +; CHECK-NEXT: fcfid 1, 0 +; CHECK-NEXT: stw 4, 4(3) +; CHECK-NEXT: addi 1, 1, 16 +; CHECK-NEXT: blr +entry: + %0 = load i64, i64* %llp, align 8 + %inc = add nsw i64 %0, 1 + store i64 %inc, i64* %llp, align 8 + %conv = sitofp i64 %0 to double + ret double %conv +} diff --git a/llvm/test/CodeGen/PowerPC/dyn-alloca-aligned.ll b/llvm/test/CodeGen/PowerPC/dyn-alloca-aligned.ll index e0f28475d8fd4..bb6c47a7e19fd 100644 --- a/llvm/test/CodeGen/PowerPC/dyn-alloca-aligned.ll +++ b/llvm/test/CodeGen/PowerPC/dyn-alloca-aligned.ll @@ -6,7 +6,7 @@ target triple = "powerpc64-unknown-linux-gnu" declare void @bar(i32*, i32*) #0 -define void @goo(%struct.s* byval nocapture readonly %a, i32 signext %n) #0 { +define void @goo(%struct.s* byval(%struct.s) nocapture readonly %a, i32 signext %n) #0 { entry: %0 = zext i32 %n to i64 %vla = alloca i32, i64 %0, align 128 diff --git a/llvm/test/CodeGen/PowerPC/elf-common.ll b/llvm/test/CodeGen/PowerPC/elf-common.ll index 722b4803ca3a2..cf3e79bc21ad7 100644 --- a/llvm/test/CodeGen/PowerPC/elf-common.ll +++ b/llvm/test/CodeGen/PowerPC/elf-common.ll @@ -14,9 +14,11 @@ define signext i32 @test_comm() nounwind { ; NOOPT-LABEL: test_comm: ; NOOPT: # %bb.0: # %entry ; NOOPT-NEXT: addis 3, 2, comm_glob@toc@ha -; NOOPT-NEXT: addi 5, 3, comm_glob@toc@l -; NOOPT-NEXT: lwz 3, 0(5) +; NOOPT-NEXT: addi 3, 3, comm_glob@toc@l +; NOOPT-NEXT: lwz 3, 0(3) ; NOOPT-NEXT: addi 4, 3, 1 +; NOOPT-NEXT: addis 5, 2, comm_glob@toc@ha +; NOOPT-NEXT: addi 5, 5, comm_glob@toc@l ; NOOPT-NEXT: stw 4, 0(5) ; NOOPT-NEXT: extsw 3, 3 ; NOOPT-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/emptystruct.ll b/llvm/test/CodeGen/PowerPC/emptystruct.ll index b0e41ec29e4f8..b8222c0ba2f7e 100644 --- a/llvm/test/CodeGen/PowerPC/emptystruct.ll +++ b/llvm/test/CodeGen/PowerPC/emptystruct.ll @@ -3,8 +3,8 @@ ; This tests correct handling of empty aggregate parameters and return values. ; An empty parameter passed by value does not consume a protocol register or ; a parameter save area doubleword. An empty parameter passed by reference -; is treated as any other pointer parameter. An empty aggregate return value -; is treated as any other aggregate return value, passed via address as a +; is treated as any other pointer parameter. An empty aggregate return value +; is treated as any other aggregate return value, passed via address as a ; hidden parameter in GPR3. In this example, GPR3 contains the return value ; address, GPR4 contains the address of e2, and e1 and e3 are not passed or ; received. @@ -14,7 +14,7 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.empty = type {} -define void @callee(%struct.empty* noalias sret %agg.result, %struct.empty* byval %a1, %struct.empty* %a2, %struct.empty* byval %a3) nounwind { +define void @callee(%struct.empty* noalias sret(%struct.empty) %agg.result, %struct.empty* byval(%struct.empty) %a1, %struct.empty* %a2, %struct.empty* byval(%struct.empty) %a3) nounwind { entry: %a2.addr = alloca %struct.empty*, align 8 store %struct.empty* %a2, %struct.empty** %a2.addr, align 8 @@ -33,12 +33,12 @@ entry: declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind -define void @caller(%struct.empty* noalias sret %agg.result) nounwind { +define void @caller(%struct.empty* noalias sret(%struct.empty) %agg.result) nounwind { entry: %e1 = alloca %struct.empty, align 1 %e2 = alloca %struct.empty, align 1 %e3 = alloca %struct.empty, align 1 - call void @callee(%struct.empty* sret %agg.result, %struct.empty* byval %e1, %struct.empty* %e2, %struct.empty* byval %e3) + call void @callee(%struct.empty* sret(%struct.empty) %agg.result, %struct.empty* byval(%struct.empty) %e1, %struct.empty* %e2, %struct.empty* byval(%struct.empty) %e3) ret void } diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll index 2dacdabd2de92..0a23f7ad460d6 100644 --- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll +++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll @@ -115,7 +115,7 @@ entry: ; Since we can only pass a max of 8 float128 value in VSX registers, ensure we ; store to stack if passing more. ; Function Attrs: norecurse nounwind readonly -define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly align 16 %a) { +define fp128 @testStruct_03(%struct.With9fp128params* byval(%struct.With9fp128params) nocapture readonly align 16 %a) { ; CHECK-LABEL: testStruct_03: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lxv v2, 128(r1) @@ -409,7 +409,7 @@ entry: ; Function Attrs: norecurse nounwind readonly -define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) { +define fp128 @testNestedAggregate(%struct.MixedC* byval(%struct.MixedC) nocapture readonly align 16 %a) { ; CHECK-LABEL: testNestedAggregate: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: std r8, 72(r1) diff --git a/llvm/test/CodeGen/PowerPC/f128-arith.ll b/llvm/test/CodeGen/PowerPC/f128-arith.ll index 2be0b42ff454f..61bd03aa63683 100644 --- a/llvm/test/CodeGen/PowerPC/f128-arith.ll +++ b/llvm/test/CodeGen/PowerPC/f128-arith.ll @@ -2,7 +2,7 @@ ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \ ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \ -; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s \ +; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -enable-soft-fp128 | FileCheck %s \ ; RUN: -check-prefix=CHECK-P8 ; Function Attrs: norecurse nounwind @@ -23,15 +23,12 @@ define void @qpAdd(fp128* nocapture readonly %a, fp128* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 +; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: bl __addkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -62,15 +59,12 @@ define void @qpSub(fp128* nocapture readonly %a, fp128* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 +; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: bl __subkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -101,15 +95,12 @@ define void @qpMul(fp128* nocapture readonly %a, fp128* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 +; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: bl __mulkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -140,15 +131,12 @@ define void @qpDiv(fp128* nocapture readonly %a, fp128* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 +; CHECK-P8-NEXT: vmr v3, v2 ; CHECK-P8-NEXT: bl __divkf3 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -173,9 +161,9 @@ define void @testLdNSt(i8* nocapture readonly %PtrC, fp128* nocapture %PtrF) { ; CHECK-P8-LABEL: testLdNSt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addi r3, r3, 4 -; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: addi r3, r4, 8 -; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 +; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %PtrC, i64 4 @@ -205,15 +193,11 @@ define void @qpSqrt(fp128* nocapture readonly %a, fp128* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 ; CHECK-P8-NEXT: bl sqrtl ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -239,13 +223,18 @@ define void @qpCpsgn(fp128* nocapture readonly %a, fp128* nocapture readonly %b, ; ; CHECK-P8-LABEL: qpCpsgn: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: ld r4, 8(r4) -; CHECK-P8-NEXT: ld r6, 0(r3) -; CHECK-P8-NEXT: ld r3, 8(r3) -; CHECK-P8-NEXT: rotldi r4, r4, 1 -; CHECK-P8-NEXT: rldimi r3, r4, 63, 0 -; CHECK-P8-NEXT: std r6, 0(r5) -; CHECK-P8-NEXT: std r3, 8(r5) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 +; CHECK-P8-NEXT: addi r3, r1, -16 +; CHECK-P8-NEXT: addi r4, r1, -32 +; CHECK-P8-NEXT: stvx v3, 0, r3 +; CHECK-P8-NEXT: stvx v2, 0, r4 +; CHECK-P8-NEXT: lbz r3, -1(r1) +; CHECK-P8-NEXT: lbz r6, -17(r1) +; CHECK-P8-NEXT: rlwimi r6, r3, 0, 0, 24 +; CHECK-P8-NEXT: stb r6, -17(r1) +; CHECK-P8-NEXT: lvx v2, 0, r4 +; CHECK-P8-NEXT: stvx v2, 0, r5 ; CHECK-P8-NEXT: blr fp128* nocapture %res) { entry: @@ -268,11 +257,14 @@ define void @qpAbs(fp128* nocapture readonly %a, fp128* nocapture %res) { ; ; CHECK-P8-LABEL: qpAbs: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r3, 8(r3) -; CHECK-P8-NEXT: clrldi r3, r3, 1 -; CHECK-P8-NEXT: std r5, 0(r4) -; CHECK-P8-NEXT: std r3, 8(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: addi r3, r1, -16 +; CHECK-P8-NEXT: stvx v2, 0, r3 +; CHECK-P8-NEXT: lbz r5, -1(r1) +; CHECK-P8-NEXT: clrlwi r5, r5, 25 +; CHECK-P8-NEXT: stb r5, -1(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: stvx v2, 0, r4 ; CHECK-P8-NEXT: blr entry: %0 = load fp128, fp128* %a, align 16 @@ -293,12 +285,20 @@ define void @qpNAbs(fp128* nocapture readonly %a, fp128* nocapture %res) { ; ; CHECK-P8-LABEL: qpNAbs: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: ld r6, 0(r3) -; CHECK-P8-NEXT: ld r3, 8(r3) -; CHECK-P8-NEXT: li r5, -1 -; CHECK-P8-NEXT: rldimi r3, r5, 63, 0 -; CHECK-P8-NEXT: std r6, 0(r4) -; CHECK-P8-NEXT: std r3, 8(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: addi r3, r1, -32 +; CHECK-P8-NEXT: stvx v2, 0, r3 +; CHECK-P8-NEXT: lbz r5, -17(r1) +; CHECK-P8-NEXT: clrlwi r5, r5, 25 +; CHECK-P8-NEXT: stb r5, -17(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: addi r3, r1, -16 +; CHECK-P8-NEXT: stvx v2, 0, r3 +; CHECK-P8-NEXT: lbz r5, -1(r1) +; CHECK-P8-NEXT: xori r5, r5, 128 +; CHECK-P8-NEXT: stb r5, -1(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: stvx v2, 0, r4 ; CHECK-P8-NEXT: blr entry: %0 = load fp128, fp128* %a, align 16 @@ -319,13 +319,14 @@ define void @qpNeg(fp128* nocapture readonly %a, fp128* nocapture %res) { ; ; CHECK-P8-LABEL: qpNeg: ; CHECK-P8: # %bb.0: # %entry -; CHECK-P8-NEXT: li r5, 1 -; CHECK-P8-NEXT: ld r6, 0(r3) -; CHECK-P8-NEXT: ld r3, 8(r3) -; CHECK-P8-NEXT: sldi r5, r5, 63 -; CHECK-P8-NEXT: xor r3, r3, r5 -; CHECK-P8-NEXT: std r6, 0(r4) -; CHECK-P8-NEXT: std r3, 8(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: addi r3, r1, -16 +; CHECK-P8-NEXT: stvx v2, 0, r3 +; CHECK-P8-NEXT: lbz r5, -1(r1) +; CHECK-P8-NEXT: xori r5, r5, 128 +; CHECK-P8-NEXT: stb r5, -1(r1) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: stvx v2, 0, r4 ; CHECK-P8-NEXT: blr entry: %0 = load fp128, fp128* %a, align 16 @@ -358,9 +359,7 @@ define fp128 @qp_sin(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl sinf128 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -397,9 +396,7 @@ define fp128 @qp_cos(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl cosf128 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -436,9 +433,7 @@ define fp128 @qp_log(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl logf128 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -475,9 +470,7 @@ define fp128 @qp_log10(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl log10f128 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -514,9 +507,7 @@ define fp128 @qp_log2(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl log2f128 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -554,12 +545,8 @@ define fp128 @qp_minnum(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: ld r8, 8(r3) -; CHECK-P8-NEXT: ld r5, 0(r4) -; CHECK-P8-NEXT: ld r6, 8(r4) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: mr r4, r8 +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl fminf128 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -599,12 +586,8 @@ define fp128 @qp_maxnum(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: ld r8, 8(r3) -; CHECK-P8-NEXT: ld r5, 0(r4) -; CHECK-P8-NEXT: ld r6, 8(r4) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: mr r4, r8 +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl fmaxf128 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -644,12 +627,8 @@ define fp128 @qp_pow(fp128* nocapture readonly %a, ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r7, 0(r3) -; CHECK-P8-NEXT: ld r8, 8(r3) -; CHECK-P8-NEXT: ld r5, 0(r4) -; CHECK-P8-NEXT: ld r6, 8(r4) -; CHECK-P8-NEXT: mr r3, r7 -; CHECK-P8-NEXT: mr r4, r8 +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl powf128 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -688,9 +667,7 @@ define fp128 @qp_exp(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl expf128 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -727,9 +704,7 @@ define fp128 @qp_exp2(fp128* nocapture readonly %a) { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r4, 8(r3) -; CHECK-P8-NEXT: mr r3, r5 +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: bl exp2f128 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -774,17 +749,13 @@ define void @qp_powi(fp128* nocapture readonly %a, i32* nocapture readonly %b, ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r6, 0(r3) -; CHECK-P8-NEXT: ld r7, 8(r3) -; CHECK-P8-NEXT: lwz r8, 0(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lwz r3, 0(r4) ; CHECK-P8-NEXT: mr r30, r5 -; CHECK-P8-NEXT: mr r3, r6 -; CHECK-P8-NEXT: mr r4, r7 -; CHECK-P8-NEXT: mr r5, r8 +; CHECK-P8-NEXT: mr r5, r3 ; CHECK-P8-NEXT: bl __powikf2 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -831,14 +802,12 @@ define fp128 @qp_frem() #0 { ; CHECK-P8-NEXT: stdu r1, -32(r1) ; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 +; CHECK-P8-NEXT: addis r3, r2, a@toc@ha ; CHECK-P8-NEXT: addis r4, r2, b@toc@ha -; CHECK-P8-NEXT: addis r5, r2, a@toc@ha -; CHECK-P8-NEXT: addi r6, r5, a@toc@l -; CHECK-P8-NEXT: addi r7, r4, b@toc@l -; CHECK-P8-NEXT: ld r3, a@toc@l(r5) -; CHECK-P8-NEXT: ld r5, b@toc@l(r4) -; CHECK-P8-NEXT: ld r4, 8(r6) -; CHECK-P8-NEXT: ld r6, 8(r7) +; CHECK-P8-NEXT: addi r3, r3, a@toc@l +; CHECK-P8-NEXT: addi r4, r4, b@toc@l +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 ; CHECK-P8-NEXT: bl fmodf128 ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: addi r1, r1, 32 @@ -869,15 +838,11 @@ define void @qpCeil(fp128* nocapture readonly %a, fp128* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 ; CHECK-P8-NEXT: bl ceill ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -908,15 +873,11 @@ define void @qpFloor(fp128* nocapture readonly %a, fp128* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 ; CHECK-P8-NEXT: bl floorl ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -947,15 +908,11 @@ define void @qpTrunc(fp128* nocapture readonly %a, fp128* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 ; CHECK-P8-NEXT: bl truncl ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -986,15 +943,11 @@ define void @qpRound(fp128* nocapture readonly %a, fp128* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 ; CHECK-P8-NEXT: bl roundl ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -1038,11 +991,8 @@ define void @qpLRound(fp128* nocapture readonly %a, i32* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 ; CHECK-P8-NEXT: bl lroundl ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: stw r3, 0(r30) @@ -1089,11 +1039,8 @@ define void @qpLLRound(fp128* nocapture readonly %a, i64* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 ; CHECK-P8-NEXT: bl llroundl ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: std r3, 0(r30) @@ -1127,15 +1074,11 @@ define void @qpRint(fp128* nocapture readonly %a, fp128* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 ; CHECK-P8-NEXT: bl rintl ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -1179,11 +1122,8 @@ define void @qpLRint(fp128* nocapture readonly %a, i32* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 ; CHECK-P8-NEXT: bl lrintl ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: stw r3, 0(r30) @@ -1230,11 +1170,8 @@ define void @qpLLRint(fp128* nocapture readonly %a, i64* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 ; CHECK-P8-NEXT: bl llrintl ; CHECK-P8-NEXT: nop ; CHECK-P8-NEXT: std r3, 0(r30) @@ -1268,15 +1205,11 @@ define void @qpNearByInt(fp128* nocapture readonly %a, fp128* nocapture %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r5, 0(r3) -; CHECK-P8-NEXT: ld r6, 8(r3) +; CHECK-P8-NEXT: lvx v2, 0, r3 ; CHECK-P8-NEXT: mr r30, r4 -; CHECK-P8-NEXT: mr r3, r5 -; CHECK-P8-NEXT: mr r4, r6 ; CHECK-P8-NEXT: bl nearbyintl ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload @@ -1309,21 +1242,13 @@ define void @qpFMA(fp128* %a, fp128* %b, fp128* %c, fp128* %res) { ; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-P8-NEXT: std r0, 16(r1) ; CHECK-P8-NEXT: stdu r1, -48(r1) -; CHECK-P8-NEXT: ld r11, 0(r3) -; CHECK-P8-NEXT: ld r12, 8(r3) -; CHECK-P8-NEXT: ld r9, 0(r4) -; CHECK-P8-NEXT: ld r10, 8(r4) +; CHECK-P8-NEXT: lvx v2, 0, r3 +; CHECK-P8-NEXT: lvx v3, 0, r4 +; CHECK-P8-NEXT: lvx v4, 0, r5 ; CHECK-P8-NEXT: mr r30, r6 -; CHECK-P8-NEXT: ld r7, 0(r5) -; CHECK-P8-NEXT: ld r8, 8(r5) -; CHECK-P8-NEXT: mr r3, r11 -; CHECK-P8-NEXT: mr r4, r12 -; CHECK-P8-NEXT: mr r5, r9 -; CHECK-P8-NEXT: mr r6, r10 ; CHECK-P8-NEXT: bl fmal ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: std r3, 0(r30) -; CHECK-P8-NEXT: std r4, 8(r30) +; CHECK-P8-NEXT: stvx v2, 0, r30 ; CHECK-P8-NEXT: addi r1, r1, 48 ; CHECK-P8-NEXT: ld r0, 16(r1) ; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll b/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll index cb9e1c9256d54..1735c50a7d959 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll @@ -23,7 +23,7 @@ ; load define i8 @t1() nounwind { -; ELF64: t1 +; ELF64-LABEL: t1: %1 = load i8, i8* @a, align 1 ; ELF64: lbz %2 = add nsw i8 %1, 1 @@ -32,7 +32,7 @@ define i8 @t1() nounwind { } define i16 @t2() nounwind { -; ELF64: t2 +; ELF64-LABEL: t2: %1 = load i16, i16* @b, align 2 ; ELF64: lhz %2 = add nsw i16 %1, 1 @@ -41,7 +41,7 @@ define i16 @t2() nounwind { } define i32 @t3() nounwind { -; ELF64: t3 +; ELF64-LABEL: t3: %1 = load i32, i32* @c, align 4 ; ELF64: lwz %2 = add nsw i32 %1, 1 @@ -50,7 +50,7 @@ define i32 @t3() nounwind { } define i64 @t4() nounwind { -; ELF64: t4 +; ELF64-LABEL: t4: %1 = load i64, i64* @d, align 4 ; ELF64: ld %2 = add nsw i64 %1, 1 @@ -59,8 +59,8 @@ define i64 @t4() nounwind { } define float @t5() nounwind { -; ELF64: t5 -; SPE: t5 +; ELF64-LABEL: t5: +; SPE-LABEL: t5: %1 = load float, float* @e, align 4 ; ELF64: lfs ; SPE: lwz @@ -71,8 +71,8 @@ define float @t5() nounwind { } define double @t6() nounwind { -; ELF64: t6 -; SPE: t6 +; ELF64-LABEL: t6: +; SPE-LABEL: t6: %1 = load double, double* @f, align 8 ; ELF64: lfd ; VSX: lxsdx @@ -87,52 +87,52 @@ define double @t6() nounwind { ; store define void @t7(i8 %v) nounwind { -; ELF64: t7 +; ELF64-LABEL: t7: %1 = add nsw i8 %v, 1 store i8 %1, i8* @a, align 1 -; ELF64: addis ; ELF64: addi +; ELF64: addis ; ELF64: addi ; ELF64: stb ret void } define void @t8(i16 %v) nounwind { -; ELF64: t8 +; ELF64-LABEL: t8: %1 = add nsw i16 %v, 1 store i16 %1, i16* @b, align 2 -; ELF64: addis ; ELF64: addi +; ELF64: addis ; ELF64: addi ; ELF64: sth ret void } define void @t9(i32 %v) nounwind { -; ELF64: t9 +; ELF64-LABEL: t9: %1 = add nsw i32 %v, 1 store i32 %1, i32* @c, align 4 -; ELF64: addis ; ELF64: addi +; ELF64: addis ; ELF64: addi ; ELF64: stw ret void } define void @t10(i64 %v) nounwind { -; ELF64: t10 +; ELF64-LABEL: t10: %1 = add nsw i64 %v, 1 store i64 %1, i64* @d, align 4 -; ELF64: addis ; ELF64: addi +; ELF64: addis ; ELF64: addi ; ELF64: std ret void } define void @t11(float %v) nounwind { -; ELF64: t11 -; SPE: t11 +; ELF64-LABEL: t11: +; SPE: t11: %1 = fadd float %v, 1.0 store float %1, float* @e, align 4 ; ELF64: fadds @@ -143,8 +143,8 @@ define void @t11(float %v) nounwind { } define void @t12(double %v) nounwind { -; ELF64: t12 -; SPE: t12 +; ELF64-LABEL: t12: +; SPE-LABEL: t12: %1 = fadd double %v, 1.0 store double %1, double* @f, align 8 ; ELF64: fadd @@ -158,7 +158,7 @@ define void @t12(double %v) nounwind { ;; lwa requires an offset divisible by 4, so we need lwax here. define i64 @t13() nounwind { -; ELF64: t13 +; ELF64-LABEL: t13: %1 = load i32, i32* getelementptr inbounds (%struct.s, %struct.s* @g, i32 0, i32 1), align 1 %2 = sext i32 %1 to i64 ; ELF64: li @@ -170,7 +170,7 @@ define i64 @t13() nounwind { ;; ld requires an offset divisible by 4, so we need ldx here. define i64 @t14() nounwind { -; ELF64: t14 +; ELF64-LABEL: t14: %1 = load i64, i64* getelementptr inbounds (%struct.t, %struct.t* @h, i32 0, i32 1), align 1 ; ELF64: li ; ELF64: ldx @@ -181,11 +181,11 @@ define i64 @t14() nounwind { ;; std requires an offset divisible by 4, so we need stdx here. define void @t15(i64 %v) nounwind { -; ELF64: t15 +; ELF64-LABEL: t15: %1 = add nsw i64 %v, 1 store i64 %1, i64* getelementptr inbounds (%struct.t, %struct.t* @h, i32 0, i32 1), align 1 -; ELF64: addis ; ELF64: addi +; ELF64: addis ; ELF64: addi ; ELF64: li ; ELF64: stdx @@ -194,7 +194,7 @@ define void @t15(i64 %v) nounwind { ;; ld requires an offset that fits in 16 bits, so we need ldx here. define i64 @t16() nounwind { -; ELF64: t16 +; ELF64-LABEL: t16: %1 = load i64, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8 ; ELF64: lis ; ELF64: ori @@ -206,11 +206,11 @@ define i64 @t16() nounwind { ;; std requires an offset that fits in 16 bits, so we need stdx here. define void @t17(i64 %v) nounwind { -; ELF64: t17 +; ELF64-LABEL: t17: %1 = add nsw i64 %v, 1 store i64 %1, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8 -; ELF64: addis ; ELF64: addi +; ELF64: addis ; ELF64: addi ; ELF64: lis ; ELF64: ori diff --git a/llvm/test/CodeGen/PowerPC/fastcc_stacksize.ll b/llvm/test/CodeGen/PowerPC/fastcc_stacksize.ll index d3e357e89e917..bf3693ac0073d 100644 --- a/llvm/test/CodeGen/PowerPC/fastcc_stacksize.ll +++ b/llvm/test/CodeGen/PowerPC/fastcc_stacksize.ll @@ -60,7 +60,7 @@ declare fastcc void define internal fastcc void @CallPassByValue(%"myClass::Mem"* %E) align 2 { entry: - call fastcc void @PassByValue(%"myClass::Mem"* byval nonnull align 8 undef); + call fastcc void @PassByValue(%"myClass::Mem"* byval(%"myClass::Mem") nonnull align 8 undef); ret void ; CHECK-LABEL: PassByValue @@ -69,7 +69,7 @@ entry: } declare dso_local fastcc void - @PassByValue(%"myClass::Mem"* byval nocapture readonly align 8) align 2 + @PassByValue(%"myClass::Mem"* byval(%"myClass::Mem") nocapture readonly align 8) align 2 ; Verify Paramater Save Area is allocated if parameter exceed the number that ; can be passed via registers @@ -127,8 +127,8 @@ declare fastcc void define internal fastcc void @AggMemExprEmitter(%"myClass::MemK"* %E) align 2 { entry: - call fastcc void @MemExprEmitterInitialization(%"myClass::MemK" * - byval nonnull align 8 undef); + call fastcc void @MemExprEmitterInitialization(%"myClass::MemK"* + byval(%"myClass::MemK") nonnull align 8 undef); ret void ; CHECK-LABEL: AggMemExprEmitter @@ -137,5 +137,5 @@ entry: } declare dso_local fastcc void - @MemExprEmitterInitialization(%"myClass::MemK" * - byval nocapture readonly align 8) align 2 + @MemExprEmitterInitialization(%"myClass::MemK"* + byval(%"myClass::MemK") nocapture readonly align 8) align 2 diff --git a/llvm/test/CodeGen/PowerPC/fma-mutate.ll b/llvm/test/CodeGen/PowerPC/fma-mutate.ll index a1e3473edf222..0c85c2457ff5d 100644 --- a/llvm/test/CodeGen/PowerPC/fma-mutate.ll +++ b/llvm/test/CodeGen/PowerPC/fma-mutate.ll @@ -9,12 +9,8 @@ declare double @llvm.sqrt.f64(double) define double @foo3_fmf(double %a) nounwind { ; CHECK-LABEL: foo3_fmf: ; CHECK: # %bb.0: -; CHECK-NEXT: xsabsdp 0, 1 -; CHECK-NEXT: addis 3, 2, .LCPI0_2@toc@ha -; CHECK-NEXT: lfd 2, .LCPI0_2@toc@l(3) -; CHECK-NEXT: xscmpudp 0, 0, 2 -; CHECK-NEXT: xxlxor 0, 0, 0 -; CHECK-NEXT: blt 0, .LBB0_2 +; CHECK-NEXT: xstsqrtdp 0, 1 +; CHECK-NEXT: bc 12, 2, .LBB0_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: xsrsqrtedp 0, 1 ; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha @@ -28,9 +24,10 @@ define double @foo3_fmf(double %a) nounwind { ; CHECK-NEXT: xsmuldp 1, 1, 0 ; CHECK-NEXT: xsmaddadp 3, 1, 0 ; CHECK-NEXT: xsmuldp 0, 1, 4 -; CHECK-NEXT: xsmuldp 0, 0, 3 +; CHECK-NEXT: xsmuldp 1, 0, 3 +; CHECK-NEXT: blr ; CHECK-NEXT: .LBB0_2: -; CHECK-NEXT: fmr 1, 0 +; CHECK-NEXT: xssqrtdp 1, 1 ; CHECK-NEXT: blr %r = call reassoc afn ninf double @llvm.sqrt.f64(double %a) ret double %r diff --git a/llvm/test/CodeGen/PowerPC/fold-rlwinm-after-ra.mir b/llvm/test/CodeGen/PowerPC/fold-rlwinm-after-ra.mir new file mode 100644 index 0000000000000..182929053c63e --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fold-rlwinm-after-ra.mir @@ -0,0 +1,163 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -stop-after \ +# RUN: ppc-pre-emit-peephole %s -o - | FileCheck %s + +--- +name: testFoldRLWINM +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $r3 + ; CHECK-LABEL: name: testFoldRLWINM + ; CHECK: liveins: $r3 + ; CHECK: renamable $r3 = RLWINM killed renamable $r3, 14, 0, 12, implicit-def $x3 + ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3 + $r3 = RLWINM killed $r3, 27, 5, 31 + dead renamable $r3 = RLWINM killed renamable $r3, 19, 0, 12, implicit-def $x3 + BLR8 implicit $lr8, implicit $rm, implicit killed $x3 +... +--- +name: testFoldRLWINMSrcFullMask1 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $r3 + ; CHECK-LABEL: name: testFoldRLWINMSrcFullMask1 + ; CHECK: liveins: $r3 + ; CHECK: renamable $r3 = RLWINM killed renamable $r3, 14, 0, 12, implicit-def $x3 + ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3 + $r3 = RLWINM killed $r3, 27, 0, 31 + dead renamable $r3 = RLWINM killed renamable $r3, 19, 0, 12, implicit-def $x3 + BLR8 implicit $lr8, implicit $rm, implicit killed $x3 +... +--- +name: testFoldRLWINMSrcFullMask2 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $r2, $r3 + ; CHECK-LABEL: name: testFoldRLWINMSrcFullMask2 + ; CHECK: liveins: $r2, $r3 + ; CHECK: renamable $r3 = RLWINM $r2, 14, 10, 1, implicit-def $x3 + ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3 + $r3 = RLWINM killed $r2, 27, 10, 9 + dead renamable $r3 = RLWINM killed renamable $r3, 19, 10, 1, implicit-def $x3 + BLR8 implicit $lr8, implicit $rm, implicit killed $x3 +... +--- +name: testFoldRLWINMSrcWrapped +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $r3 + ; CHECK-LABEL: name: testFoldRLWINMSrcWrapped + ; CHECK: liveins: $r3 + ; CHECK: renamable $r3 = RLWINM killed renamable $r3, 14, 11, 12, implicit-def $x3 + ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3 + $r3 = RLWINM killed $r3, 27, 30, 10 + dead renamable $r3 = RLWINM killed renamable $r3, 19, 0, 12, implicit-def $x3 + BLR8 implicit $lr8, implicit $rm, implicit killed $x3 +... +--- +name: testFoldRLWINMUserWrapped +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $r3 + ; CHECK-LABEL: name: testFoldRLWINMUserWrapped + ; CHECK: liveins: $r3 + ; CHECK: $r3 = RLWINM killed $r3, 10, 5, 31 + ; CHECK: renamable $r3 = RLWINM killed renamable $r3, 10, 30, 5, implicit-def $x3 + ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3 + $r3 = RLWINM killed $r3, 10, 5, 31 + dead renamable $r3 = RLWINM killed renamable $r3, 10, 30, 5, implicit-def $x3 + BLR8 implicit $lr8, implicit $rm, implicit killed $x3 +... +--- +name: testFoldRLWINMResultWrapped +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $r3 + ; CHECK-LABEL: name: testFoldRLWINMResultWrapped + ; CHECK: liveins: $r3 + ; CHECK: $r3 = RLWINM killed $r3, 10, 20, 10 + ; CHECK: renamable $r3 = RLWINM killed renamable $r3, 10, 0, 31, implicit-def $x3 + ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3 + $r3 = RLWINM killed $r3, 10, 20, 10 + dead renamable $r3 = RLWINM killed renamable $r3, 10, 0, 31, implicit-def $x3 + BLR8 implicit $lr8, implicit $rm, implicit killed $x3 +... +--- +name: testFoldRLWINMToZero +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $r3 + ; CHECK-LABEL: name: testFoldRLWINMToZero + ; CHECK: liveins: $r3 + ; CHECK: renamable $r3 = LI 0, implicit-def $x3 + ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3 + $r3 = RLWINM killed $r3, 27, 5, 10 + dead renamable $r3 = RLWINM killed renamable $r3, 8, 5, 10, implicit-def $x3 + BLR8 implicit $lr8, implicit $rm, implicit killed $x3 +... +--- +name: testFoldRLWINM_recToZero +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $r3 + ; CHECK-LABEL: name: testFoldRLWINM_recToZero + ; CHECK: liveins: $r3 + ; CHECK: dead renamable $r3 = ANDI_rec killed renamable $r3, 0, implicit-def $cr0 + ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $cr0 + $r3 = RLWINM killed $r3, 27, 5, 10 + dead renamable $r3 = RLWINM_rec killed renamable $r3, 8, 5, 10, implicit-def $cr0 + BLR8 implicit $lr8, implicit $rm, implicit killed $cr0 +... +--- +name: testFoldRLWINMInvalidMask +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $r3 + ; CHECK-LABEL: name: testFoldRLWINMInvalidMask + ; CHECK: liveins: $r3 + ; CHECK: $r3 = RLWINM killed $r3, 20, 5, 31 + ; CHECK: renamable $r3 = RLWINM killed renamable $r3, 19, 10, 20, implicit-def $x3 + ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3 + $r3 = RLWINM killed $r3, 20, 5, 31 + dead renamable $r3 = RLWINM killed renamable $r3, 19, 10, 20, implicit-def $x3 + BLR8 implicit $lr8, implicit $rm, implicit killed $x3 +... +--- +name: testFoldRLWINCanNotBeDeleted +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $r2, $r3 + ; CHECK-LABEL: name: testFoldRLWINCanNotBeDeleted + ; CHECK: liveins: $r2, $r3 + ; CHECK: $r3 = RLWINM_rec $r2, 27, 5, 10, implicit-def dead $cr0 + ; CHECK: dead renamable $r3 = ANDI_rec $r2, 0, implicit-def $cr0 + ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $cr0 + $r3 = RLWINM_rec $r2, 27, 5, 10, implicit-def $cr0 + dead renamable $r3 = RLWINM_rec killed renamable $r3, 8, 5, 10, implicit-def $cr0 + BLR8 implicit $lr8, implicit $rm, implicit killed $cr0 +... +--- +name: testCanNotFoldRLWINM +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $r3 + ; CHECK-LABEL: name: testCanNotFoldRLWINM + ; CHECK: liveins: $r3 + ; CHECK: $r3 = RLWINM_rec killed $r3, 27, 5, 10, implicit-def dead $cr0 + ; CHECK: dead renamable $r3 = RLWINM_rec killed renamable $r3, 8, 5, 10, implicit-def $cr0 + ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $cr0 + $r3 = RLWINM_rec $r3, 27, 5, 10, implicit-def $cr0 + dead renamable $r3 = RLWINM_rec killed renamable $r3, 8, 5, 10, implicit-def $cr0 + BLR8 implicit $lr8, implicit $rm, implicit killed $cr0 +... diff --git a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll index ffc626be2dead..26832efb3f4c0 100644 --- a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll +++ b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll @@ -1,65 +1,197 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mcpu=a2 < %s | FileCheck %s -check-prefix=FPCVT ; RUN: llc -verify-machineinstrs -mcpu=ppc64 < %s | FileCheck %s -check-prefix=PPC64 +; RUN: llc -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck %s -check-prefix=PWR9 target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" ; Function Attrs: nounwind readnone define float @fool(float %X) #0 { +; FPCVT-LABEL: fool: +; FPCVT: # %bb.0: # %entry +; FPCVT-NEXT: friz 1, 1 +; FPCVT-NEXT: blr +; +; PPC64-LABEL: fool: +; PPC64: # %bb.0: # %entry +; PPC64-NEXT: fctidz 0, 1 +; PPC64-NEXT: fcfid 0, 0 +; PPC64-NEXT: frsp 1, 0 +; PPC64-NEXT: blr +; +; PWR9-LABEL: fool: +; PWR9: # %bb.0: # %entry +; PWR9-NEXT: xsrdpiz 1, 1 +; PWR9-NEXT: blr entry: %conv = fptosi float %X to i64 %conv1 = sitofp i64 %conv to float ret float %conv1 -; FPCVT-LABEL: @fool -; FPCVT: friz 1, 1 -; FPCVT: blr -; PPC64-LABEL: @fool -; PPC64: fctidz [[REG1:[0-9]+]], 1 -; PPC64: fcfid [[REG2:[0-9]+]], [[REG1]] -; PPC64: frsp 1, [[REG2]] -; PPC64: blr } ; Function Attrs: nounwind readnone define double @foodl(double %X) #0 { +; FPCVT-LABEL: foodl: +; FPCVT: # %bb.0: # %entry +; FPCVT-NEXT: friz 1, 1 +; FPCVT-NEXT: blr +; +; PPC64-LABEL: foodl: +; PPC64: # %bb.0: # %entry +; PPC64-NEXT: fctidz 0, 1 +; PPC64-NEXT: fcfid 1, 0 +; PPC64-NEXT: blr +; +; PWR9-LABEL: foodl: +; PWR9: # %bb.0: # %entry +; PWR9-NEXT: xsrdpiz 1, 1 +; PWR9-NEXT: blr entry: %conv = fptosi double %X to i64 %conv1 = sitofp i64 %conv to double ret double %conv1 -; FPCVT-LABEL: @foodl -; FPCVT: friz 1, 1 -; FPCVT: blr -; PPC64-LABEL: @foodl -; PPC64: fctidz [[REG1:[0-9]+]], 1 -; PPC64: fcfid 1, [[REG1]] -; PPC64: blr } ; Function Attrs: nounwind readnone define float @fooul(float %X) #0 { +; FPCVT-LABEL: fooul: +; FPCVT: # %bb.0: # %entry +; FPCVT-NEXT: friz 1, 1 +; FPCVT-NEXT: blr +; +; PPC64-LABEL: fooul: +; PPC64: # %bb.0: # %entry +; PPC64-NEXT: addis 3, 2, .LCPI2_0@toc@ha +; PPC64-NEXT: li 4, 1 +; PPC64-NEXT: lfs 0, .LCPI2_0@toc@l(3) +; PPC64-NEXT: sldi 4, 4, 63 +; PPC64-NEXT: fsubs 2, 1, 0 +; PPC64-NEXT: fcmpu 0, 1, 0 +; PPC64-NEXT: fctidz 2, 2 +; PPC64-NEXT: stfd 2, -8(1) +; PPC64-NEXT: fctidz 2, 1 +; PPC64-NEXT: stfd 2, -16(1) +; PPC64-NEXT: ld 3, -8(1) +; PPC64-NEXT: ld 5, -16(1) +; PPC64-NEXT: xor 3, 3, 4 +; PPC64-NEXT: bc 12, 0, .LBB2_1 +; PPC64-NEXT: b .LBB2_2 +; PPC64-NEXT: .LBB2_1: # %entry +; PPC64-NEXT: addi 3, 5, 0 +; PPC64-NEXT: .LBB2_2: # %entry +; PPC64-NEXT: sradi 4, 3, 53 +; PPC64-NEXT: clrldi 5, 3, 63 +; PPC64-NEXT: addi 4, 4, 1 +; PPC64-NEXT: cmpldi 4, 1 +; PPC64-NEXT: rldicl 4, 3, 63, 1 +; PPC64-NEXT: or 5, 5, 4 +; PPC64-NEXT: rldicl 6, 5, 11, 53 +; PPC64-NEXT: addi 6, 6, 1 +; PPC64-NEXT: clrldi 7, 5, 53 +; PPC64-NEXT: cmpldi 1, 6, 1 +; PPC64-NEXT: clrldi 6, 3, 53 +; PPC64-NEXT: addi 7, 7, 2047 +; PPC64-NEXT: addi 6, 6, 2047 +; PPC64-NEXT: or 4, 7, 4 +; PPC64-NEXT: or 6, 6, 3 +; PPC64-NEXT: rldicl 4, 4, 53, 11 +; PPC64-NEXT: rldicr 6, 6, 0, 52 +; PPC64-NEXT: bc 12, 1, .LBB2_4 +; PPC64-NEXT: # %bb.3: # %entry +; PPC64-NEXT: ori 6, 3, 0 +; PPC64-NEXT: b .LBB2_4 +; PPC64-NEXT: .LBB2_4: # %entry +; PPC64-NEXT: rldicl 4, 4, 11, 1 +; PPC64-NEXT: cmpdi 3, 0 +; PPC64-NEXT: std 6, -32(1) +; PPC64-NEXT: bc 12, 5, .LBB2_6 +; PPC64-NEXT: # %bb.5: # %entry +; PPC64-NEXT: ori 4, 5, 0 +; PPC64-NEXT: b .LBB2_6 +; PPC64-NEXT: .LBB2_6: # %entry +; PPC64-NEXT: std 4, -24(1) +; PPC64-NEXT: bc 12, 0, .LBB2_8 +; PPC64-NEXT: # %bb.7: # %entry +; PPC64-NEXT: lfd 0, -32(1) +; PPC64-NEXT: fcfid 0, 0 +; PPC64-NEXT: frsp 1, 0 +; PPC64-NEXT: blr +; PPC64-NEXT: .LBB2_8: +; PPC64-NEXT: lfd 0, -24(1) +; PPC64-NEXT: fcfid 0, 0 +; PPC64-NEXT: frsp 0, 0 +; PPC64-NEXT: fadds 1, 0, 0 +; PPC64-NEXT: blr +; +; PWR9-LABEL: fooul: +; PWR9: # %bb.0: # %entry +; PWR9-NEXT: xsrdpiz 1, 1 +; PWR9-NEXT: blr entry: %conv = fptoui float %X to i64 %conv1 = uitofp i64 %conv to float ret float %conv1 -; FPCVT-LABEL: @fooul -; FPCVT: friz 1, 1 -; FPCVT: blr } ; Function Attrs: nounwind readnone define double @fooudl(double %X) #0 { +; FPCVT-LABEL: fooudl: +; FPCVT: # %bb.0: # %entry +; FPCVT-NEXT: friz 1, 1 +; FPCVT-NEXT: blr +; +; PPC64-LABEL: fooudl: +; PPC64: # %bb.0: # %entry +; PPC64-NEXT: addis 3, 2, .LCPI3_0@toc@ha +; PPC64-NEXT: li 4, 1 +; PPC64-NEXT: lfs 0, .LCPI3_0@toc@l(3) +; PPC64-NEXT: sldi 4, 4, 63 +; PPC64-NEXT: fsub 2, 1, 0 +; PPC64-NEXT: fcmpu 0, 1, 0 +; PPC64-NEXT: fctidz 2, 2 +; PPC64-NEXT: stfd 2, -8(1) +; PPC64-NEXT: fctidz 2, 1 +; PPC64-NEXT: stfd 2, -16(1) +; PPC64-NEXT: ld 3, -8(1) +; PPC64-NEXT: ld 5, -16(1) +; PPC64-NEXT: xor 3, 3, 4 +; PPC64-NEXT: li 4, 1107 +; PPC64-NEXT: sldi 4, 4, 52 +; PPC64-NEXT: bc 12, 0, .LBB3_1 +; PPC64-NEXT: b .LBB3_2 +; PPC64-NEXT: .LBB3_1: # %entry +; PPC64-NEXT: addi 3, 5, 0 +; PPC64-NEXT: .LBB3_2: # %entry +; PPC64-NEXT: rldicl 5, 3, 32, 32 +; PPC64-NEXT: clrldi 3, 3, 32 +; PPC64-NEXT: or 4, 5, 4 +; PPC64-NEXT: addis 5, 2, .LCPI3_1@toc@ha +; PPC64-NEXT: std 4, -24(1) +; PPC64-NEXT: li 4, 1075 +; PPC64-NEXT: sldi 4, 4, 52 +; PPC64-NEXT: or 3, 3, 4 +; PPC64-NEXT: lfd 0, .LCPI3_1@toc@l(5) +; PPC64-NEXT: std 3, -32(1) +; PPC64-NEXT: lfd 1, -24(1) +; PPC64-NEXT: lfd 2, -32(1) +; PPC64-NEXT: fsub 0, 1, 0 +; PPC64-NEXT: fadd 1, 2, 0 +; PPC64-NEXT: blr +; +; PWR9-LABEL: fooudl: +; PWR9: # %bb.0: # %entry +; PWR9-NEXT: xsrdpiz 1, 1 +; PWR9-NEXT: blr entry: %conv = fptoui double %X to i64 %conv1 = uitofp i64 %conv to double ret double %conv1 -; FPCVT-LABEL: @fooudl -; FPCVT: friz 1, 1 -; FPCVT: blr } attributes #0 = { nounwind readnone "no-signed-zeros-fp-math"="true" } diff --git a/llvm/test/CodeGen/PowerPC/fsl-e500mc.ll b/llvm/test/CodeGen/PowerPC/fsl-e500mc.ll index b1bb09da3e14d..d0f8fa856fba8 100644 --- a/llvm/test/CodeGen/PowerPC/fsl-e500mc.ll +++ b/llvm/test/CodeGen/PowerPC/fsl-e500mc.ll @@ -9,7 +9,7 @@ target triple = "powerpc-fsl-linux" %struct.teststruct = type { [12 x i32], i32 } -define void @copy(%struct.teststruct* noalias nocapture sret %agg.result, %struct.teststruct* nocapture %in) nounwind { +define void @copy(%struct.teststruct* noalias nocapture sret(%struct.teststruct) %agg.result, %struct.teststruct* nocapture %in) nounwind { entry: ; CHECK: @copy ; CHECK-NOT: bl memcpy diff --git a/llvm/test/CodeGen/PowerPC/fsl-e5500.ll b/llvm/test/CodeGen/PowerPC/fsl-e5500.ll index 595d91ad6206e..93d05fe48a4a1 100644 --- a/llvm/test/CodeGen/PowerPC/fsl-e5500.ll +++ b/llvm/test/CodeGen/PowerPC/fsl-e5500.ll @@ -9,7 +9,7 @@ target triple = "powerpc64-fsl-linux" %struct.teststruct = type { [24 x i32], i32 } -define void @copy(%struct.teststruct* noalias nocapture sret %agg.result, %struct.teststruct* nocapture %in) nounwind { +define void @copy(%struct.teststruct* noalias nocapture sret(%struct.teststruct) %agg.result, %struct.teststruct* nocapture %in) nounwind { entry: ; CHECK: @copy ; CHECK-NOT: bl memcpy diff --git a/llvm/test/CodeGen/PowerPC/glob-comp-aa-crash.ll b/llvm/test/CodeGen/PowerPC/glob-comp-aa-crash.ll index 2aa5239f25eb8..8f56e68505f03 100644 --- a/llvm/test/CodeGen/PowerPC/glob-comp-aa-crash.ll +++ b/llvm/test/CodeGen/PowerPC/glob-comp-aa-crash.ll @@ -36,7 +36,7 @@ invoke.cont: ; preds = %entry %__exception_ = getelementptr inbounds %"class.std::__1::__assoc_sub_state", %"class.std::__1::__assoc_sub_state"* %this, i64 0, i32 1 %0 = bitcast { i64, i64 }* %tmp to i8* call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 16, i1 false) - call void @_ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE(%"class.std::__exception_ptr::exception_ptr"* %ref.tmp, { i64, i64 }* byval %tmp) #5 + call void @_ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE(%"class.std::__exception_ptr::exception_ptr"* %ref.tmp, { i64, i64 }* byval({ i64, i64 }) %tmp) #5 %call = call zeroext i1 @_ZNSt15__exception_ptrneERKNS_13exception_ptrES2_(%"class.std::__exception_ptr::exception_ptr"* %__exception_, %"class.std::__exception_ptr::exception_ptr"* %ref.tmp) #5 call void @_ZNSt15__exception_ptr13exception_ptrD1Ev(%"class.std::__exception_ptr::exception_ptr"* %ref.tmp) #5 br i1 %call, label %if.then, label %if.end @@ -102,7 +102,7 @@ declare void @_ZNSt3__117__assoc_sub_state10__sub_waitERNS_11unique_lockINS_5mut declare zeroext i1 @_ZNSt15__exception_ptrneERKNS_13exception_ptrES2_(%"class.std::__exception_ptr::exception_ptr"*, %"class.std::__exception_ptr::exception_ptr"*) #1 ; Function Attrs: nounwind optsize -declare void @_ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE(%"class.std::__exception_ptr::exception_ptr"*, { i64, i64 }* byval) #1 +declare void @_ZNSt15__exception_ptr13exception_ptrC1EMS0_FvvE(%"class.std::__exception_ptr::exception_ptr"*, { i64, i64 }* byval({ i64, i64 })) #1 ; Function Attrs: nounwind optsize declare void @_ZNSt15__exception_ptr13exception_ptrD1Ev(%"class.std::__exception_ptr::exception_ptr"*) #1 diff --git a/llvm/test/CodeGen/PowerPC/jaggedstructs.ll b/llvm/test/CodeGen/PowerPC/jaggedstructs.ll index 45e043a669d74..18ec0143f02ac 100644 --- a/llvm/test/CodeGen/PowerPC/jaggedstructs.ll +++ b/llvm/test/CodeGen/PowerPC/jaggedstructs.ll @@ -12,9 +12,9 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.S6 = type { [6 x i8] } %struct.S7 = type { [7 x i8] } -define void @test(%struct.S3* byval %s3, %struct.S5* byval %s5, %struct.S6* byval %s6, %struct.S7* byval %s7) nounwind { +define void @test(%struct.S3* byval(%struct.S3) %s3, %struct.S5* byval(%struct.S5) %s5, %struct.S6* byval(%struct.S6) %s6, %struct.S7* byval(%struct.S7) %s7) nounwind { entry: - call void @check(%struct.S3* byval %s3, %struct.S5* byval %s5, %struct.S6* byval %s6, %struct.S7* byval %s7) + call void @check(%struct.S3* byval(%struct.S3) %s3, %struct.S5* byval(%struct.S5) %s5, %struct.S6* byval(%struct.S6) %s6, %struct.S7* byval(%struct.S7) %s7) ret void } @@ -43,4 +43,4 @@ entry: ; CHECK-DAG: ld 4, 56(1) ; CHECK-DAG: ld 3, 48(1) -declare void @check(%struct.S3* byval, %struct.S5* byval, %struct.S6* byval, %struct.S7* byval) +declare void @check(%struct.S3* byval(%struct.S3), %struct.S5* byval(%struct.S5), %struct.S6* byval(%struct.S6), %struct.S7* byval(%struct.S7)) diff --git a/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll b/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll index 04aa0d58fa800..a068059589469 100644 --- a/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll +++ b/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE @a = common global i32 0 diff --git a/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll b/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll index 14c24f039ff0f..54b148057ffa5 100644 --- a/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll +++ b/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL -; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE @a = common global i32 0 diff --git a/llvm/test/CodeGen/PowerPC/mcm-1.ll b/llvm/test/CodeGen/PowerPC/mcm-1.ll index 08bae365f18bc..47266563edc56 100644 --- a/llvm/test/CodeGen/PowerPC/mcm-1.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-1.ll @@ -33,13 +33,15 @@ entry: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) -; CHECK: stw {{[0-9]+}}, 0([[REG2]]) +; CHECK: addis [[REG3:[0-9]+]], 2, .LC[[TOCNUM]]@toc@ha +; CHECK: ld [[REG4:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG3]]) +; CHECK: stw {{[0-9]+}}, 0([[REG4]]) ; CHECK: .section .toc,"aw",@progbits ; CHECK-NEXT: .LC0: ; CHECK-NEXT: .tc ei[TC],ei ; CHECK-NEXT: .LC1: -; CHECK-NEXT: .tc fi[TC],fi -; CHECK-NEXT: .LC2: ; CHECK-NEXT: .tc gi[TC],gi +; CHECK-NEXT: .LC2: +; CHECK-NEXT: .tc fi[TC],fi diff --git a/llvm/test/CodeGen/PowerPC/mcm-13.ll b/llvm/test/CodeGen/PowerPC/mcm-13.ll index d7c50efbbae59..86748e3f4119a 100644 --- a/llvm/test/CodeGen/PowerPC/mcm-13.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-13.ll @@ -21,7 +21,9 @@ entry: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) -; CHECK: stw {{[0-9]+}}, 0([[REG2]]) +; CHECK: addis [[REG3:[0-9]+]], 2, .LC[[TOCNUM]]@toc@ha +; CHECK: ld [[REG4:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG3]]) +; CHECK: stw {{[0-9]+}}, 0([[REG4]]) ; CHECK: .section .toc ; CHECK: .LC[[TOCNUM]]: ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} diff --git a/llvm/test/CodeGen/PowerPC/mcm-2.ll b/llvm/test/CodeGen/PowerPC/mcm-2.ll index 980fcb7caa10c..5fbc5ffa5b9c3 100644 --- a/llvm/test/CodeGen/PowerPC/mcm-2.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-2.ll @@ -21,7 +21,9 @@ entry: ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]]) -; MEDIUM: stw {{[0-9]+}}, 0([[REG2]]) +; MEDIUM: addis [[REG3:[0-9]+]], 2, [[VAR]]@toc@ha +; MEDIUM: addi [[REG4:[0-9]+]], [[REG3]], [[VAR]]@toc@l +; MEDIUM: stw {{[0-9]+}}, 0([[REG4]]) ; MEDIUM: .type [[VAR]],@object ; MEDIUM: .lcomm [[VAR]],4,4 @@ -29,7 +31,9 @@ entry: ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) ; LARGE: lwz {{[0-9]+}}, 0([[REG2]]) -; LARGE: stw {{[0-9]+}}, 0([[REG2]]) +; LARGE: addis [[REG3:[0-9]+]], 2, [[VAR]]@toc@ha +; LARGE: ld [[REG4:[0-9]+]], [[VAR]]@toc@l([[REG3]]) +; LARGE: stw {{[0-9]+}}, 0([[REG4]]) ; LARGE: .type test_fn_static.si,@object ; LARGE-NEXT: .lcomm test_fn_static.si,4,4 diff --git a/llvm/test/CodeGen/PowerPC/mcm-3.ll b/llvm/test/CodeGen/PowerPC/mcm-3.ll index 562cbff286c53..abf99cd028feb 100644 --- a/llvm/test/CodeGen/PowerPC/mcm-3.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-3.ll @@ -21,7 +21,9 @@ entry: ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]]) -; MEDIUM: stw {{[0-9]+}}, 0([[REG2]]) +; MEDIUM: addis [[REG3:[0-9]+]], 2, [[VAR]]@toc@ha +; MEDIUM: addi [[REG4:[0-9]+]], [[REG3]], [[VAR]]@toc@l +; MEDIUM: stw {{[0-9]+}}, 0([[REG4]]) ; MEDIUM: .type [[VAR]],@object ; MEDIUM: .data ; MEDIUM: .globl [[VAR]] @@ -32,7 +34,9 @@ entry: ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) ; LARGE: lwz {{[0-9]+}}, 0([[REG2]]) -; LARGE: stw {{[0-9]+}}, 0([[REG2]]) +; LARGE: addis [[REG3:[0-9]+]], 2, [[VAR]]@toc@ha +; LARGE: ld [[REG4:[0-9]+]], [[VAR]]@toc@l([[REG3]]) +; LARGE: stw {{[0-9]+}}, 0([[REG4]]) ; LARGE: .type gi,@object ; LARGE-NEXT: .data ; LARGE-NEXT: .globl gi diff --git a/llvm/test/CodeGen/PowerPC/mcm-6.ll b/llvm/test/CodeGen/PowerPC/mcm-6.ll index 0572f107dff47..5a8eb7bcb0abd 100644 --- a/llvm/test/CodeGen/PowerPC/mcm-6.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-6.ll @@ -21,7 +21,9 @@ entry: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) -; CHECK: stw {{[0-9]+}}, 0([[REG2]]) +; CHECK: addis [[REG3:[0-9]+]], 2, .LC[[TOCNUM]]@toc@ha +; CHECK: ld [[REG4:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG3]]) +; CHECK: stw {{[0-9]+}}, 0([[REG4]]) ; CHECK: .comm ti,4,4 ; CHECK: .section .toc,"aw",@progbits ; CHECK-NEXT: .LC[[TOCNUM]]: diff --git a/llvm/test/CodeGen/PowerPC/mcm-9.ll b/llvm/test/CodeGen/PowerPC/mcm-9.ll index c4950ad4a92eb..9afd15a98fd77 100644 --- a/llvm/test/CodeGen/PowerPC/mcm-9.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-9.ll @@ -21,7 +21,9 @@ entry: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) -; CHECK: stw {{[0-9]+}}, 0([[REG2]]) +; CHECK: addis [[REG3:[0-9]+]], 2, .LC[[TOCNUM]]@toc@ha +; CHECK: ld [[REG4:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG3]]) +; CHECK: stw {{[0-9]+}}, 0([[REG4]]) ; CHECK: .section .toc ; CHECK: .LC[[TOCNUM]]: ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} diff --git a/llvm/test/CodeGen/PowerPC/mcm-default.ll b/llvm/test/CodeGen/PowerPC/mcm-default.ll index a7ac560971b99..69f74eeeeac47 100644 --- a/llvm/test/CodeGen/PowerPC/mcm-default.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-default.ll @@ -20,7 +20,9 @@ entry: ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]]) ; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) -; CHECK: stw {{[0-9]+}}, 0([[REG2]]) +; CHECK: addis [[REG3:[0-9]+]], 2, .LC[[TOCNUM]]@toc@ha +; CHECK: ld [[REG4:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG3]]) +; CHECK: stw {{[0-9]+}}, 0([[REG4]]) ; CHECK: .section .toc ; CHECK: .LC[[TOCNUM]]: ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}} diff --git a/llvm/test/CodeGen/PowerPC/neg-abs.ll b/llvm/test/CodeGen/PowerPC/neg-abs.ll index b870bd3ce1955..bbe27fdd057c3 100644 --- a/llvm/test/CodeGen/PowerPC/neg-abs.ll +++ b/llvm/test/CodeGen/PowerPC/neg-abs.ll @@ -9,9 +9,8 @@ define i64@neg_abs(i64 %x) { ; CHECK-LE-LABEL: neg_abs: ; CHECK-LE: # %bb.0: ; CHECK-LE-NEXT: sradi r4, r3, 63 -; CHECK-LE-NEXT: add r3, r3, r4 ; CHECK-LE-NEXT: xor r3, r3, r4 -; CHECK-LE-NEXT: neg r3, r3 +; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: blr %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) %neg = sub nsw i64 0, %abs diff --git a/llvm/test/CodeGen/PowerPC/pcrel-tls_get_addr_clobbers.ll b/llvm/test/CodeGen/PowerPC/pcrel-tls_get_addr_clobbers.ll new file mode 100644 index 0000000000000..291fb92691778 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pcrel-tls_get_addr_clobbers.ll @@ -0,0 +1,25 @@ +; RUN: llc -verify-machineinstrs -mtriple="powerpc64le-unknown-linux-gnu" \ +; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 -relocation-model=pic < %s | FileCheck %s + +%0 = type { i32 (...)**, %0* } +@x = external dso_local thread_local unnamed_addr global %0*, align 8 +define void @test(i8* %arg) { +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mflr r0 +; CHECK: std r30, -16(r1) +; CHECK-NEXT: std r0, 16(r1) +; CHECK-NEXT: stdu r1, -48(r1) +; CHECK-NEXT: mr r30, r3 +; CHECK-NEXT: paddi r3, 0, x@got@tlsld@pcrel, 1 +; CHECK-NEXT: bl __tls_get_addr@notoc(x@tlsld) +; CHECK-NEXT: paddi r3, r3, x@DTPREL, 0 +; CHECK-NEXT: std r30, 0(r3) +; CHECK-NEXT: addi r1, r1, 48 +; CHECK-NEXT: ld r0, 16(r1) +; CHECK-NEXT: ld r30, -16(r1) +; CHECK-NEXT: mtlr r0 +entry: + store i8* %arg, i8** bitcast (%0** @x to i8**), align 8 + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/pow_massv_075_025exp.ll b/llvm/test/CodeGen/PowerPC/pow_massv_075_025exp.ll index 43b0477b9a740..f4c3a149bfcde 100644 --- a/llvm/test/CodeGen/PowerPC/pow_massv_075_025exp.ll +++ b/llvm/test/CodeGen/PowerPC/pow_massv_075_025exp.ll @@ -2,8 +2,8 @@ ; RUN: llc -vector-library=MASSV < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 | FileCheck -check-prefixes=CHECK-PWR8 %s ; Exponent is a variable -define void @my_vpow_var(double* nocapture %z, double* nocapture readonly %y, double* nocapture readonly %x) { -; CHECK-LABEL: @vspow_var +define void @vpow_var(double* nocapture %z, double* nocapture readonly %y, double* nocapture readonly %x) { +; CHECK-LABEL: @vpow_var ; CHECK-PWR9: bl __powd2_P9 ; CHECK-PWR8: bl __powd2_P8 ; CHECK: blr @@ -31,8 +31,8 @@ for.end: } ; Exponent is a constant != 0.75 and !=0.25 -define void @my_vpow_const(double* nocapture %y, double* nocapture readonly %x) { -; CHECK-LABEL: @vspow_const +define void @vpow_const(double* nocapture %y, double* nocapture readonly %x) { +; CHECK-LABEL: @vpow_const ; CHECK-PWR9: bl __powd2_P9 ; CHECK-PWR8: bl __powd2_P8 ; CHECK: blr @@ -56,9 +56,87 @@ for.end: ret void } +; Exponent is a constant != 0.75 and !=0.25 and they are different +define void @vpow_noeq_const(double* nocapture %y, double* nocapture readonly %x) { +; CHECK-LABEL: @vpow_noeq_const +; CHECK-PWR9: bl __powd2_P9 +; CHECK-PWR8: bl __powd2_P8 +; CHECK: blr +entry: + br label %vector.body + +vector.body: + %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ] + %next.gep = getelementptr double, double* %y, i64 %index + %next.gep19 = getelementptr double, double* %x, i64 %index + %0 = bitcast double* %next.gep19 to <2 x double>* + %wide.load = load <2 x double>, <2 x double>* %0, align 8 + %1 = call ninf afn nsz <2 x double> @__powd2_massv(<2 x double> %wide.load, <2 x double> ) + %2 = bitcast double* %next.gep to <2 x double>* + store <2 x double> %1, <2 x double>* %2, align 8 + %index.next = add i64 %index, 2 + %3 = icmp eq i64 %index.next, 1024 + br i1 %3, label %for.end, label %vector.body + +for.end: + ret void +} + +; Exponent is a constant != 0.75 and !=0.25 and they are different +define void @vpow_noeq075_const(double* nocapture %y, double* nocapture readonly %x) { +; CHECK-LABEL: @vpow_noeq075_const +; CHECK-PWR9: bl __powd2_P9 +; CHECK-PWR8: bl __powd2_P8 +; CHECK: blr +entry: + br label %vector.body + +vector.body: + %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ] + %next.gep = getelementptr double, double* %y, i64 %index + %next.gep19 = getelementptr double, double* %x, i64 %index + %0 = bitcast double* %next.gep19 to <2 x double>* + %wide.load = load <2 x double>, <2 x double>* %0, align 8 + %1 = call ninf afn nsz <2 x double> @__powd2_massv(<2 x double> %wide.load, <2 x double> ) + %2 = bitcast double* %next.gep to <2 x double>* + store <2 x double> %1, <2 x double>* %2, align 8 + %index.next = add i64 %index, 2 + %3 = icmp eq i64 %index.next, 1024 + br i1 %3, label %for.end, label %vector.body + +for.end: + ret void +} + +; Exponent is a constant != 0.75 and !=0.25 and they are different +define void @vpow_noeq025_const(double* nocapture %y, double* nocapture readonly %x) { +; CHECK-LABEL: @vpow_noeq025_const +; CHECK-PWR9: bl __powd2_P9 +; CHECK-PWR8: bl __powd2_P8 +; CHECK: blr +entry: + br label %vector.body + +vector.body: + %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ] + %next.gep = getelementptr double, double* %y, i64 %index + %next.gep19 = getelementptr double, double* %x, i64 %index + %0 = bitcast double* %next.gep19 to <2 x double>* + %wide.load = load <2 x double>, <2 x double>* %0, align 8 + %1 = call ninf afn nsz <2 x double> @__powd2_massv(<2 x double> %wide.load, <2 x double> ) + %2 = bitcast double* %next.gep to <2 x double>* + store <2 x double> %1, <2 x double>* %2, align 8 + %index.next = add i64 %index, 2 + %3 = icmp eq i64 %index.next, 1024 + br i1 %3, label %for.end, label %vector.body + +for.end: + ret void +} + ; Exponent is 0.75 -define void @my_vpow_075(double* nocapture %y, double* nocapture readonly %x) { -; CHECK-LABEL: @vspow_075 +define void @vpow_075(double* nocapture %y, double* nocapture readonly %x) { +; CHECK-LABEL: @vpow_075 ; CHECK-NOT: bl __powd2_P{{[8,9]}} ; CHECK: xvrsqrtesp ; CHECK: blr @@ -83,8 +161,8 @@ for.end: } ; Exponent is 0.25 -define void @my_vpow_025(double* nocapture %y, double* nocapture readonly %x) { -; CHECK-LABEL: @vspow_025 +define void @vpow_025(double* nocapture %y, double* nocapture readonly %x) { +; CHECK-LABEL: @vpow_025 ; CHECK-NOT: bl __powd2_P{{[8,9]}} ; CHECK: xvrsqrtesp ; CHECK: blr @@ -109,8 +187,8 @@ for.end: } ; Exponent is 0.75 but no proper fast-math flags -define void @my_vpow_075_nofast(double* nocapture %y, double* nocapture readonly %x) { -; CHECK-LABEL: @vspow_075_nofast +define void @vpow_075_nofast(double* nocapture %y, double* nocapture readonly %x) { +; CHECK-LABEL: @vpow_075_nofast ; CHECK-PWR9: bl __powd2_P9 ; CHECK-PWR8: bl __powd2_P8 ; CHECK-NOT: xvrsqrtesp @@ -136,8 +214,8 @@ for.end: } ; Exponent is 0.25 but no proper fast-math flags -define void @my_vpow_025_nofast(double* nocapture %y, double* nocapture readonly %x) { -; CHECK-LABEL: @vspow_025_nofast +define void @vpow_025_nofast(double* nocapture %y, double* nocapture readonly %x) { +; CHECK-LABEL: @vpow_025_nofast ; CHECK-PWR9: bl __powd2_P9 ; CHECK-PWR8: bl __powd2_P8 ; CHECK-NOT: xvrsqrtesp diff --git a/llvm/test/CodeGen/PowerPC/powf_massv_075_025exp.ll b/llvm/test/CodeGen/PowerPC/powf_massv_075_025exp.ll index f251225975d3b..caa247acc2b68 100644 --- a/llvm/test/CodeGen/PowerPC/powf_massv_075_025exp.ll +++ b/llvm/test/CodeGen/PowerPC/powf_massv_075_025exp.ll @@ -56,6 +56,84 @@ for.end: ret void } +; Exponent is a constant != 0.75 and !=0.25 and they are different +define void @vspow_neq_const(float* nocapture %y, float* nocapture readonly %x) { +; CHECK-LABEL: @vspow_neq_const +; CHECK-PWR9: bl __powf4_P9 +; CHECK-PWR8: bl __powf4_P8 +; CHECK: blr +entry: + br label %vector.body + +vector.body: + %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ] + %next.gep = getelementptr float, float* %y, i64 %index + %next.gep19 = getelementptr float, float* %x, i64 %index + %0 = bitcast float* %next.gep19 to <4 x float>* + %wide.load = load <4 x float>, <4 x float>* %0, align 4 + %1 = call ninf afn nsz <4 x float> @__powf4_massv(<4 x float> %wide.load, <4 x float> ) + %2 = bitcast float* %next.gep to <4 x float>* + store <4 x float> %1, <4 x float>* %2, align 4 + %index.next = add i64 %index, 4 + %3 = icmp eq i64 %index.next, 1024 + br i1 %3, label %for.end, label %vector.body + +for.end: + ret void +} + +; Exponent is a constant != 0.75 and !=0.25 +define void @vspow_neq075_const(float* nocapture %y, float* nocapture readonly %x) { +; CHECK-LABEL: @vspow_neq075_const +; CHECK-PWR9: bl __powf4_P9 +; CHECK-PWR8: bl __powf4_P8 +; CHECK: blr +entry: + br label %vector.body + +vector.body: + %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ] + %next.gep = getelementptr float, float* %y, i64 %index + %next.gep19 = getelementptr float, float* %x, i64 %index + %0 = bitcast float* %next.gep19 to <4 x float>* + %wide.load = load <4 x float>, <4 x float>* %0, align 4 + %1 = call ninf afn nsz <4 x float> @__powf4_massv(<4 x float> %wide.load, <4 x float> ) + %2 = bitcast float* %next.gep to <4 x float>* + store <4 x float> %1, <4 x float>* %2, align 4 + %index.next = add i64 %index, 4 + %3 = icmp eq i64 %index.next, 1024 + br i1 %3, label %for.end, label %vector.body + +for.end: + ret void +} + +; Exponent is a constant != 0.75 and !=0.25 +define void @vspow_neq025_const(float* nocapture %y, float* nocapture readonly %x) { +; CHECK-LABEL: @vspow_neq025_const +; CHECK-PWR9: bl __powf4_P9 +; CHECK-PWR8: bl __powf4_P8 +; CHECK: blr +entry: + br label %vector.body + +vector.body: + %index = phi i64 [ %index.next, %vector.body ], [ 0, %entry ] + %next.gep = getelementptr float, float* %y, i64 %index + %next.gep19 = getelementptr float, float* %x, i64 %index + %0 = bitcast float* %next.gep19 to <4 x float>* + %wide.load = load <4 x float>, <4 x float>* %0, align 4 + %1 = call ninf afn nsz <4 x float> @__powf4_massv(<4 x float> %wide.load, <4 x float> ) + %2 = bitcast float* %next.gep to <4 x float>* + store <4 x float> %1, <4 x float>* %2, align 4 + %index.next = add i64 %index, 4 + %3 = icmp eq i64 %index.next, 1024 + br i1 %3, label %for.end, label %vector.body + +for.end: + ret void +} + ; Exponent is 0.75 define void @vspow_075(float* nocapture %y, float* nocapture readonly %x) { ; CHECK-LABEL: @vspow_075 diff --git a/llvm/test/CodeGen/PowerPC/ppc-empty-fs.ll b/llvm/test/CodeGen/PowerPC/ppc-empty-fs.ll index 71fd1821360e6..dbeaa94a9a728 100644 --- a/llvm/test/CodeGen/PowerPC/ppc-empty-fs.ll +++ b/llvm/test/CodeGen/PowerPC/ppc-empty-fs.ll @@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.fab = type { float, float } ; Function Attrs: nounwind -define void @func_fab(%struct.fab* noalias sret %agg.result, i64 %x.coerce) #0 { +define void @func_fab(%struct.fab* noalias sret(%struct.fab) %agg.result, i64 %x.coerce) #0 { entry: %x = alloca %struct.fab, align 8 %0 = bitcast %struct.fab* %x to i64* diff --git a/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll b/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll index e2fead90522dd..5a7e4c2fd2b3c 100644 --- a/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll +++ b/llvm/test/CodeGen/PowerPC/ppc32-i64-to-float-conv.ll @@ -1,7 +1,7 @@ -; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \ +; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \ ; RUN: -mtriple=powerpc-ibm-aix-xcoff 2>&1 | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 \ +; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \ ; RUN: -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s ; When we convert an `i64` to `f32` on 32-bit PPC target, a `setcc` will be diff --git a/llvm/test/CodeGen/PowerPC/ppc440-fp-basic.ll b/llvm/test/CodeGen/PowerPC/ppc440-fp-basic.ll index 646722958f562..ed8553dde0ef8 100644 --- a/llvm/test/CodeGen/PowerPC/ppc440-fp-basic.ll +++ b/llvm/test/CodeGen/PowerPC/ppc440-fp-basic.ll @@ -2,7 +2,7 @@ %0 = type { double, double } -define void @maybe_an_fma(%0* sret %agg.result, %0* byval %a, %0* byval %b, %0* byval %c) nounwind { +define void @maybe_an_fma(%0* sret(%0) %agg.result, %0* byval(%0) %a, %0* byval(%0) %b, %0* byval(%0) %c) nounwind { entry: %a.realp = getelementptr inbounds %0, %0* %a, i32 0, i32 0 %a.real = load double, double* %a.realp diff --git a/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll b/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll index 883d892fce37b..72fb997c0594d 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll @@ -18,7 +18,7 @@ target triple = "powerpc64-unknown-linux-gnu" ; value. Since the target does bitcast through memory and we no longer ; remember the address we need to do the store in a fresh local ; address. -define ppc_fp128 @test(%struct.S* byval %x) nounwind { +define ppc_fp128 @test(%struct.S* byval(%struct.S) %x) nounwind { ; CHECK-LABEL: test: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: std 5, -16(1) diff --git a/llvm/test/CodeGen/PowerPC/ppc64-byval-align.ll b/llvm/test/CodeGen/PowerPC/ppc64-byval-align.ll index db0cd86995ad0..ebc8bdb839fc2 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-byval-align.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-byval-align.ll @@ -9,7 +9,7 @@ target triple = "powerpc64-unknown-linux-gnu" @gt = common global %struct.test zeroinitializer, align 16 @gp = common global %struct.pad zeroinitializer, align 8 -define signext i32 @callee1(i32 signext %x, %struct.test* byval align 16 nocapture readnone %y, i32 signext %z) { +define signext i32 @callee1(i32 signext %x, %struct.test* byval(%struct.test) align 16 nocapture readnone %y, i32 signext %z) { entry: ret i32 %z } @@ -17,17 +17,17 @@ entry: ; CHECK: mr 3, 7 ; CHECK: blr -declare signext i32 @test1(i32 signext, %struct.test* byval align 16, i32 signext) +declare signext i32 @test1(i32 signext, %struct.test* byval(%struct.test) align 16, i32 signext) define void @caller1(i32 signext %z) { entry: - %call = tail call signext i32 @test1(i32 signext 0, %struct.test* byval align 16 @gt, i32 signext %z) + %call = tail call signext i32 @test1(i32 signext 0, %struct.test* byval(%struct.test) align 16 @gt, i32 signext %z) ret void } ; CHECK-LABEL: @caller1 ; CHECK: mr 7, 3 ; CHECK: bl test1 -define i64 @callee2(%struct.pad* byval nocapture readnone %x, i32 signext %y, %struct.test* byval align 16 nocapture readonly %z) { +define i64 @callee2(%struct.pad* byval(%struct.pad) nocapture readnone %x, i32 signext %y, %struct.test* byval(%struct.test) align 16 nocapture readonly %z) { entry: %x1 = getelementptr inbounds %struct.test, %struct.test* %z, i64 0, i32 0 %0 = load i64, i64* %x1, align 16 @@ -37,13 +37,13 @@ entry: ; CHECK: ld {{[0-9]+}}, 128(1) ; CHECK: blr -declare i64 @test2(%struct.pad* byval, i32 signext, %struct.test* byval align 16) +declare i64 @test2(%struct.pad* byval(%struct.pad), i32 signext, %struct.test* byval(%struct.test) align 16) define void @caller2(i64 %z) { entry: %tmp = alloca %struct.test, align 16 %.compoundliteral.sroa.0.0..sroa_idx = getelementptr inbounds %struct.test, %struct.test* %tmp, i64 0, i32 0 store i64 %z, i64* %.compoundliteral.sroa.0.0..sroa_idx, align 16 - %call = call i64 @test2(%struct.pad* byval @gp, i32 signext 0, %struct.test* byval align 16 %tmp) + %call = call i64 @test2(%struct.pad* byval(%struct.pad) @gp, i32 signext 0, %struct.test* byval(%struct.test) align 16 %tmp) ret void } ; CHECK-LABEL: @caller2 diff --git a/llvm/test/CodeGen/PowerPC/ppc64-crash.ll b/llvm/test/CodeGen/PowerPC/ppc64-crash.ll index d335e1b8229cd..4431f0c15ece7 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-crash.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-crash.ll @@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-freebsd" %struct.pos_T = type { i64 } ; check that we're not copying stuff between R and X registers -define internal void @serialize_pos(%struct.pos_T* byval %pos, %struct.__sFILE* %fp) nounwind { +define internal void @serialize_pos(%struct.pos_T* byval(%struct.pos_T) %pos, %struct.__sFILE* %fp) nounwind { entry: ret void } diff --git a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir index b7c0b7ef8b66b..e6a29a79524b4 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir +++ b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir @@ -1,13 +1,13 @@ -# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 \ +# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 -mattr=-altivec \ # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \ # RUN: FileCheck %s --check-prefixes=CHECK,SAVEONE -# RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 \ +# RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 -mattr=-altivec \ # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \ # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL -# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \ +# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 -mattr=-altivec \ # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \ # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL diff --git a/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll b/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll index 357f28e88b184..61a588f9bb87f 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll @@ -87,15 +87,15 @@ entry: ; Struct return test ; Function Attrs: noinline nounwind -define void @callee_sret_56(%S_56* noalias sret %agg.result) #0 { ret void } -define void @callee_sret_32(%S_32* noalias sret %agg.result) #0 { ret void } +define void @callee_sret_56(%S_56* noalias sret(%S_56) %agg.result) #0 { ret void } +define void @callee_sret_32(%S_32* noalias sret(%S_32) %agg.result) #0 { ret void } ; Function Attrs: nounwind -define void @caller_do_something_sret_32(%S_32* noalias sret %agg.result) #1 { +define void @caller_do_something_sret_32(%S_32* noalias sret(%S_32) %agg.result) #1 { %1 = alloca %S_56, align 4 %2 = bitcast %S_56* %1 to i8* - call void @callee_sret_56(%S_56* nonnull sret %1) - tail call void @callee_sret_32(%S_32* sret %agg.result) + call void @callee_sret_56(%S_56* nonnull sret(%S_56) %1) + tail call void @callee_sret_32(%S_32* sret(%S_32) %agg.result) ret void ; CHECK-SCO-LABEL: caller_do_something_sret_32: @@ -107,7 +107,7 @@ define void @caller_do_something_sret_32(%S_32* noalias sret %agg.result) #1 { define void @caller_local_sret_32(%S_32* %a) #1 { %tmp = alloca %S_32, align 4 - tail call void @callee_sret_32(%S_32* nonnull sret %tmp) + tail call void @callee_sret_32(%S_32* nonnull sret(%S_32) %tmp) ret void ; CHECK-SCO-LABEL: caller_local_sret_32: @@ -204,9 +204,9 @@ define void @w_caller(i8* %ptr) { %struct.byvalTest = type { [8 x i8] } @byval = common global %struct.byvalTest zeroinitializer -define void @byval_callee(%struct.byvalTest* byval %ptr) { ret void } +define void @byval_callee(%struct.byvalTest* byval(%struct.byvalTest) %ptr) { ret void } define void @byval_caller() { - tail call void @byval_callee(%struct.byvalTest* byval @byval) + tail call void @byval_callee(%struct.byvalTest* byval(%struct.byvalTest) @byval) ret void ; CHECK-SCO-LABEL: bl byval_callee diff --git a/llvm/test/CodeGen/PowerPC/ppc64-smallarg.ll b/llvm/test/CodeGen/PowerPC/ppc64-smallarg.ll index a71ea80b6f9e1..cd6ccd8bb88da 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-smallarg.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-smallarg.ll @@ -13,7 +13,7 @@ target triple = "powerpc64-unknown-linux-gnu" @gs = common global %struct.small_arg zeroinitializer, align 2 @gf = common global float 0.000000e+00, align 4 -define void @callee1(%struct.small_arg* noalias nocapture sret %agg.result, %struct.large_arg* byval nocapture readnone %pad, %struct.small_arg* byval nocapture readonly %x) { +define void @callee1(%struct.small_arg* noalias nocapture sret(%struct.small_arg) %agg.result, %struct.large_arg* byval(%struct.large_arg) nocapture readnone %pad, %struct.small_arg* byval(%struct.small_arg) nocapture readonly %x) { entry: %0 = bitcast %struct.small_arg* %x to i32* %1 = bitcast %struct.small_arg* %agg.result to i32* @@ -28,14 +28,14 @@ entry: define void @caller1() { entry: %tmp = alloca %struct.small_arg, align 2 - call void @test1(%struct.small_arg* sret %tmp, %struct.large_arg* byval @gl, %struct.small_arg* byval @gs) + call void @test1(%struct.small_arg* sret(%struct.small_arg) %tmp, %struct.large_arg* byval(%struct.large_arg) @gl, %struct.small_arg* byval(%struct.small_arg) @gs) ret void } ; CHECK: @caller1 ; CHECK: stw {{[0-9]+}}, 124(1) ; CHECK: bl test1 -declare void @test1(%struct.small_arg* sret, %struct.large_arg* byval, %struct.small_arg* byval) +declare void @test1(%struct.small_arg* sret(%struct.small_arg), %struct.large_arg* byval(%struct.large_arg), %struct.small_arg* byval(%struct.small_arg)) define float @callee2(float %pad1, float %pad2, float %pad3, float %pad4, float %pad5, float %pad6, float %pad7, float %pad8, float %pad9, float %pad10, float %pad11, float %pad12, float %pad13, float %x) { entry: diff --git a/llvm/test/CodeGen/PowerPC/ppc64le-smallarg.ll b/llvm/test/CodeGen/PowerPC/ppc64le-smallarg.ll index 9eac7d0c4d7a4..4b2982401ba81 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64le-smallarg.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64le-smallarg.ll @@ -13,7 +13,7 @@ target triple = "powerpc64le-unknown-linux-gnu" @gs = common global %struct.small_arg zeroinitializer, align 2 @gf = common global float 0.000000e+00, align 4 -define void @callee1(%struct.small_arg* noalias nocapture sret %agg.result, %struct.large_arg* byval nocapture readnone %pad, %struct.small_arg* byval nocapture readonly %x) { +define void @callee1(%struct.small_arg* noalias nocapture sret(%struct.small_arg) %agg.result, %struct.large_arg* byval(%struct.large_arg) nocapture readnone %pad, %struct.small_arg* byval(%struct.small_arg) nocapture readonly %x) { entry: %0 = bitcast %struct.small_arg* %x to i32* %1 = bitcast %struct.small_arg* %agg.result to i32* @@ -28,21 +28,21 @@ entry: define void @caller1() { entry: %tmp = alloca %struct.small_arg, align 2 - call void @test1(%struct.small_arg* sret %tmp, %struct.large_arg* byval @gl, %struct.small_arg* byval @gs) + call void @test1(%struct.small_arg* sret(%struct.small_arg) %tmp, %struct.large_arg* byval(%struct.large_arg) @gl, %struct.small_arg* byval(%struct.small_arg) @gs) ret void } ; CHECK: @caller1 ; CHECK: stw {{[0-9]+}}, 104(1) ; CHECK: bl test1 -declare void @test1(%struct.small_arg* sret, %struct.large_arg* byval, %struct.small_arg* byval) +declare void @test1(%struct.small_arg* sret(%struct.small_arg), %struct.large_arg* byval(%struct.large_arg), %struct.small_arg* byval(%struct.small_arg)) define float @callee2(float %pad1, float %pad2, float %pad3, float %pad4, float %pad5, float %pad6, float %pad7, float %pad8, float %pad9, float %pad10, float %pad11, float %pad12, float %pad13, float %x) { entry: ret float %x } ; CHECK: @callee2 -; CHECK: lfs {{[0-9]+}}, 136(1) +; CHECK: lfs {{[0-9]+}}, 136(1) ; CHECK: blr define void @caller2() { diff --git a/llvm/test/CodeGen/PowerPC/pr13891.ll b/llvm/test/CodeGen/PowerPC/pr13891.ll index 10532a9b38eac..f35a0a724bfd4 100644 --- a/llvm/test/CodeGen/PowerPC/pr13891.ll +++ b/llvm/test/CodeGen/PowerPC/pr13891.ll @@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.foo = type { i8, i8 } -define void @_Z5check3foos(%struct.foo* nocapture byval %f, i16 signext %i) noinline { +define void @_Z5check3foos(%struct.foo* nocapture byval(%struct.foo) %f, i16 signext %i) noinline { ; CHECK-LABEL: _Z5check3foos: ; CHECK: sth 3, {{[0-9]+}}(1) ; CHECK: lha {{[0-9]+}}, {{[0-9]+}}(1) diff --git a/llvm/test/CodeGen/PowerPC/pr17354.ll b/llvm/test/CodeGen/PowerPC/pr17354.ll index 0f77e5936aa1d..83a9ac9818624 100644 --- a/llvm/test/CodeGen/PowerPC/pr17354.ll +++ b/llvm/test/CodeGen/PowerPC/pr17354.ll @@ -14,7 +14,7 @@ target triple = "powerpc64-unknown-linux-gnu" define internal void @__cxx_global_var_init() section ".text.startup" { entry: - call void @_Z4funcv(%struct.CS* sret getelementptr inbounds ([1 x %struct.CS], [1 x %struct.CS]* @_ZL3glb, i64 0, i64 0)) + call void @_Z4funcv(%struct.CS* sret(%struct.CS) getelementptr inbounds ([1 x %struct.CS], [1 x %struct.CS]* @_ZL3glb, i64 0, i64 0)) ret void } @@ -23,7 +23,7 @@ entry: ; CHECK-NEXT: nop ; Function Attrs: nounwind -define void @_Z4funcv(%struct.CS* noalias sret %agg.result) #0 { +define void @_Z4funcv(%struct.CS* noalias sret(%struct.CS) %agg.result) #0 { entry: %a_ = getelementptr inbounds %struct.CS, %struct.CS* %agg.result, i32 0, i32 0 store i32 0, i32* %a_, align 4 diff --git a/llvm/test/CodeGen/PowerPC/pr18663.ll b/llvm/test/CodeGen/PowerPC/pr18663.ll index 331870e456f33..8e66858b893a4 100644 --- a/llvm/test/CodeGen/PowerPC/pr18663.ll +++ b/llvm/test/CodeGen/PowerPC/pr18663.ll @@ -59,7 +59,7 @@ %struct.TriaNumberCache.52.52 = type { %struct.TriaNumberCache.53.51, i32, %"class.std::vector.12.15", i32, %"class.std::vector.12.15" } %struct.TriaNumberCache.53.51 = type { i32, %"class.std::vector.12.15", i32, %"class.std::vector.12.15" } -define void @_ZNK18TriaObjectAccessorILi3ELi3EE10barycenterEv(%class.Point.1* noalias nocapture sret %agg.result, %class.TriaObjectAccessor.57* %this) #0 align 2 { +define void @_ZNK18TriaObjectAccessorILi3ELi3EE10barycenterEv(%class.Point.1* noalias nocapture sret(%class.Point.1) %agg.result, %class.TriaObjectAccessor.57* %this) #0 align 2 { entry: %0 = load double, double* null, align 8 %1 = load double, double* undef, align 8 diff --git a/llvm/test/CodeGen/PowerPC/pr46759.ll b/llvm/test/CodeGen/PowerPC/pr46759.ll index d1d68a5db7e31..716e050cdbeef 100644 --- a/llvm/test/CodeGen/PowerPC/pr46759.ll +++ b/llvm/test/CodeGen/PowerPC/pr46759.ll @@ -9,10 +9,26 @@ define void @foo(i32 %vla_size) #0 { ; CHECK-LE-NEXT: std r31, -8(r1) ; CHECK-LE-NEXT: std r30, -16(r1) ; CHECK-LE-NEXT: mr r30, r1 -; CHECK-LE-NEXT: mr r12, r1 -; CHECK-LE-NEXT: .cfi_def_cfa r12, 0 -; CHECK-LE-NEXT: clrldi r0, r12, 53 -; CHECK-LE-NEXT: subc r1, r1, r0 +; CHECK-LE-NEXT: .cfi_def_cfa r30, 0 +; CHECK-LE-NEXT: clrldi r0, r30, 53 +; CHECK-LE-NEXT: subc r12, r30, r0 +; CHECK-LE-NEXT: clrldi r0, r0, 52 +; CHECK-LE-NEXT: cmpdi r0, 0 +; CHECK-LE-NEXT: beq cr0, .LBB0_2 +; CHECK-LE-NEXT: # %bb.1: # %entry +; CHECK-LE-NEXT: neg r0, r0 +; CHECK-LE-NEXT: stdux r30, r1, r0 +; CHECK-LE-NEXT: .LBB0_2: # %entry +; CHECK-LE-NEXT: li r0, -4096 +; CHECK-LE-NEXT: cmpd r1, r12 +; CHECK-LE-NEXT: beq cr0, .LBB0_4 +; CHECK-LE-NEXT: .LBB0_3: # %entry +; CHECK-LE-NEXT: # +; CHECK-LE-NEXT: stdux r30, r1, r0 +; CHECK-LE-NEXT: cmpd r1, r12 +; CHECK-LE-NEXT: bne cr0, .LBB0_3 +; CHECK-LE-NEXT: .LBB0_4: # %entry +; CHECK-LE-NEXT: mr r12, r30 ; CHECK-LE-NEXT: stdu r12, -2048(r1) ; CHECK-LE-NEXT: stdu r12, -4096(r1) ; CHECK-LE-NEXT: .cfi_def_cfa_register r1 @@ -36,13 +52,13 @@ define void @foo(i32 %vla_size) #0 { ; CHECK-LE-NEXT: add r4, r1, r4 ; CHECK-LE-NEXT: stdux r3, r1, r5 ; CHECK-LE-NEXT: cmpd r1, r4 -; CHECK-LE-NEXT: beq cr0, .LBB0_2 -; CHECK-LE-NEXT: .LBB0_1: # %entry +; CHECK-LE-NEXT: beq cr0, .LBB0_6 +; CHECK-LE-NEXT: .LBB0_5: # %entry ; CHECK-LE-NEXT: # ; CHECK-LE-NEXT: stdu r3, -4096(r1) ; CHECK-LE-NEXT: cmpd r1, r4 -; CHECK-LE-NEXT: bne cr0, .LBB0_1 -; CHECK-LE-NEXT: .LBB0_2: # %entry +; CHECK-LE-NEXT: bne cr0, .LBB0_5 +; CHECK-LE-NEXT: .LBB0_6: # %entry ; CHECK-LE-NEXT: addi r3, r1, 2048 ; CHECK-LE-NEXT: lbz r3, 0(r3) ; CHECK-LE-NEXT: ld r1, 0(r1) diff --git a/llvm/test/CodeGen/PowerPC/recipest.ll b/llvm/test/CodeGen/PowerPC/recipest.ll index e3894bcd23f5a..3d9f2efc32e04 100644 --- a/llvm/test/CodeGen/PowerPC/recipest.ll +++ b/llvm/test/CodeGen/PowerPC/recipest.ll @@ -749,11 +749,8 @@ define <4 x float> @hoo2_safe(<4 x float> %a, <4 x float> %b) nounwind { define double @foo3_fmf(double %a) nounwind { ; CHECK-P7-LABEL: foo3_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fabs 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI20_2@toc@ha -; CHECK-P7-NEXT: lfd 2, .LCPI20_2@toc@l(3) -; CHECK-P7-NEXT: fcmpu 0, 0, 2 -; CHECK-P7-NEXT: blt 0, .LBB20_2 +; CHECK-P7-NEXT: ftsqrt 0, 1 +; CHECK-P7-NEXT: bc 12, 2, .LBB20_2 ; CHECK-P7-NEXT: # %bb.1: ; CHECK-P7-NEXT: frsqrte 0, 1 ; CHECK-P7-NEXT: addis 3, 2, .LCPI20_0@toc@ha @@ -770,18 +767,13 @@ define double @foo3_fmf(double %a) nounwind { ; CHECK-P7-NEXT: fmul 1, 1, 0 ; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: .LBB20_2: -; CHECK-P7-NEXT: addis 3, 2, .LCPI20_3@toc@ha -; CHECK-P7-NEXT: lfs 1, .LCPI20_3@toc@l(3) +; CHECK-P7-NEXT: fsqrt 1, 1 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: foo3_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xsabsdp 0, 1 -; CHECK-P8-NEXT: addis 3, 2, .LCPI20_2@toc@ha -; CHECK-P8-NEXT: lfd 2, .LCPI20_2@toc@l(3) -; CHECK-P8-NEXT: xscmpudp 0, 0, 2 -; CHECK-P8-NEXT: xxlxor 0, 0, 0 -; CHECK-P8-NEXT: blt 0, .LBB20_2 +; CHECK-P8-NEXT: xstsqrtdp 0, 1 +; CHECK-P8-NEXT: bc 12, 2, .LBB20_2 ; CHECK-P8-NEXT: # %bb.1: ; CHECK-P8-NEXT: xsrsqrtedp 0, 1 ; CHECK-P8-NEXT: addis 3, 2, .LCPI20_0@toc@ha @@ -796,19 +788,16 @@ define double @foo3_fmf(double %a) nounwind { ; CHECK-P8-NEXT: xsmuldp 1, 1, 0 ; CHECK-P8-NEXT: xsmaddadp 3, 1, 0 ; CHECK-P8-NEXT: xsmuldp 0, 1, 4 -; CHECK-P8-NEXT: xsmuldp 0, 0, 3 +; CHECK-P8-NEXT: xsmuldp 1, 0, 3 +; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: .LBB20_2: -; CHECK-P8-NEXT: fmr 1, 0 +; CHECK-P8-NEXT: xssqrtdp 1, 1 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: foo3_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: addis 3, 2, .LCPI20_2@toc@ha -; CHECK-P9-NEXT: xsabsdp 0, 1 -; CHECK-P9-NEXT: lfd 2, .LCPI20_2@toc@l(3) -; CHECK-P9-NEXT: xscmpudp 0, 0, 2 -; CHECK-P9-NEXT: xxlxor 0, 0, 0 -; CHECK-P9-NEXT: blt 0, .LBB20_2 +; CHECK-P9-NEXT: xstsqrtdp 0, 1 +; CHECK-P9-NEXT: bc 12, 2, .LBB20_2 ; CHECK-P9-NEXT: # %bb.1: ; CHECK-P9-NEXT: xsrsqrtedp 0, 1 ; CHECK-P9-NEXT: addis 3, 2, .LCPI20_0@toc@ha @@ -823,9 +812,10 @@ define double @foo3_fmf(double %a) nounwind { ; CHECK-P9-NEXT: xsmuldp 1, 1, 0 ; CHECK-P9-NEXT: xsmaddadp 3, 1, 0 ; CHECK-P9-NEXT: xsmuldp 0, 1, 2 -; CHECK-P9-NEXT: xsmuldp 0, 0, 3 +; CHECK-P9-NEXT: xsmuldp 1, 0, 3 +; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: .LBB20_2: -; CHECK-P9-NEXT: fmr 1, 0 +; CHECK-P9-NEXT: xssqrtdp 1, 1 ; CHECK-P9-NEXT: blr %r = call reassoc ninf afn double @llvm.sqrt.f64(double %a) ret double %r @@ -1037,45 +1027,41 @@ define <4 x float> @hoo3_safe(<4 x float> %a) nounwind { define <2 x double> @hoo4_fmf(<2 x double> %a) #1 { ; CHECK-P7-LABEL: hoo4_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: addis 3, 2, .LCPI26_2@toc@ha -; CHECK-P7-NEXT: fmr 3, 1 -; CHECK-P7-NEXT: addis 4, 2, .LCPI26_1@toc@ha -; CHECK-P7-NEXT: lfs 0, .LCPI26_2@toc@l(3) +; CHECK-P7-NEXT: ftsqrt 0, 1 ; CHECK-P7-NEXT: addis 3, 2, .LCPI26_0@toc@ha -; CHECK-P7-NEXT: lfs 4, .LCPI26_1@toc@l(4) -; CHECK-P7-NEXT: lfs 5, .LCPI26_0@toc@l(3) -; CHECK-P7-NEXT: fcmpu 0, 1, 0 -; CHECK-P7-NEXT: fmr 1, 0 -; CHECK-P7-NEXT: bne 0, .LBB26_3 +; CHECK-P7-NEXT: addis 4, 2, .LCPI26_1@toc@ha +; CHECK-P7-NEXT: lfs 3, .LCPI26_0@toc@l(3) +; CHECK-P7-NEXT: lfs 0, .LCPI26_1@toc@l(4) +; CHECK-P7-NEXT: bc 12, 2, .LBB26_3 ; CHECK-P7-NEXT: # %bb.1: -; CHECK-P7-NEXT: fcmpu 0, 2, 0 -; CHECK-P7-NEXT: bne 0, .LBB26_4 +; CHECK-P7-NEXT: frsqrte 4, 1 +; CHECK-P7-NEXT: fmul 5, 1, 4 +; CHECK-P7-NEXT: fmadd 5, 5, 4, 3 +; CHECK-P7-NEXT: fmul 4, 4, 0 +; CHECK-P7-NEXT: fmul 4, 4, 5 +; CHECK-P7-NEXT: fmul 1, 1, 4 +; CHECK-P7-NEXT: fmadd 4, 1, 4, 3 +; CHECK-P7-NEXT: fmul 1, 1, 0 +; CHECK-P7-NEXT: fmul 1, 1, 4 +; CHECK-P7-NEXT: ftsqrt 0, 2 +; CHECK-P7-NEXT: bc 4, 2, .LBB26_4 ; CHECK-P7-NEXT: .LBB26_2: -; CHECK-P7-NEXT: fmr 2, 0 +; CHECK-P7-NEXT: fsqrt 2, 2 ; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: .LBB26_3: -; CHECK-P7-NEXT: frsqrte 1, 3 -; CHECK-P7-NEXT: fmul 6, 3, 1 -; CHECK-P7-NEXT: fmadd 6, 6, 1, 5 -; CHECK-P7-NEXT: fmul 1, 1, 4 -; CHECK-P7-NEXT: fmul 1, 1, 6 -; CHECK-P7-NEXT: fmul 3, 3, 1 -; CHECK-P7-NEXT: fmadd 1, 3, 1, 5 -; CHECK-P7-NEXT: fmul 3, 3, 4 -; CHECK-P7-NEXT: fmul 1, 3, 1 -; CHECK-P7-NEXT: fcmpu 0, 2, 0 -; CHECK-P7-NEXT: beq 0, .LBB26_2 +; CHECK-P7-NEXT: fsqrt 1, 1 +; CHECK-P7-NEXT: ftsqrt 0, 2 +; CHECK-P7-NEXT: bc 12, 2, .LBB26_2 ; CHECK-P7-NEXT: .LBB26_4: -; CHECK-P7-NEXT: frsqrte 0, 2 -; CHECK-P7-NEXT: fmul 3, 2, 0 -; CHECK-P7-NEXT: fmadd 3, 3, 0, 5 -; CHECK-P7-NEXT: fmul 0, 0, 4 -; CHECK-P7-NEXT: fmul 0, 0, 3 -; CHECK-P7-NEXT: fmul 2, 2, 0 -; CHECK-P7-NEXT: fmadd 0, 2, 0, 5 +; CHECK-P7-NEXT: frsqrte 4, 2 +; CHECK-P7-NEXT: fmul 5, 2, 4 +; CHECK-P7-NEXT: fmadd 5, 5, 4, 3 +; CHECK-P7-NEXT: fmul 4, 4, 0 +; CHECK-P7-NEXT: fmul 4, 4, 5 ; CHECK-P7-NEXT: fmul 2, 2, 4 +; CHECK-P7-NEXT: fmadd 3, 2, 4, 3 ; CHECK-P7-NEXT: fmul 0, 2, 0 -; CHECK-P7-NEXT: fmr 2, 0 +; CHECK-P7-NEXT: fmul 2, 0, 3 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: hoo4_fmf: diff --git a/llvm/test/CodeGen/PowerPC/reloc-align.ll b/llvm/test/CodeGen/PowerPC/reloc-align.ll index 59f7137fd648b..929d2bf86c809 100644 --- a/llvm/test/CodeGen/PowerPC/reloc-align.ll +++ b/llvm/test/CodeGen/PowerPC/reloc-align.ll @@ -15,13 +15,13 @@ target triple = "powerpc64-unknown-linux-gnu" ; Function Attrs: nounwind readonly define signext i32 @main() #0 { entry: - %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*)) + %call = tail call fastcc signext i32 @func_90(%struct.S1* byval(%struct.S1) bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*)) ; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l ret i32 %call } ; Function Attrs: nounwind readonly -define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 { +define internal fastcc signext i32 @func_90(%struct.S1* byval(%struct.S1) nocapture %p_91) #0 { entry: %0 = bitcast %struct.S1* %p_91 to i64* %bf.load = load i64, i64* %0, align 1 diff --git a/llvm/test/CodeGen/PowerPC/resolvefi-basereg.ll b/llvm/test/CodeGen/PowerPC/resolvefi-basereg.ll index 731f37d277024..b9029b205db91 100644 --- a/llvm/test/CodeGen/PowerPC/resolvefi-basereg.ll +++ b/llvm/test/CodeGen/PowerPC/resolvefi-basereg.ll @@ -332,15 +332,15 @@ if.end: ; preds = %if.then, %entry call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %62, i8* align 16 bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i1 false) %63 = bitcast %struct.S1998* %agg.tmp112 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %63, i8* align 16 bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i1 false) - call void @check1998(%struct.S1998* sret %agg.tmp, %struct.S1998* byval align 16 %agg.tmp111, %struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 1), %struct.S1998* byval align 16 %agg.tmp112) - call void @checkx1998(%struct.S1998* byval align 16 %agg.tmp) + call void @check1998(%struct.S1998* sret(%struct.S1998) %agg.tmp, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp111, %struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 1), %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp112) + call void @checkx1998(%struct.S1998* byval(%struct.S1998) align 16 %agg.tmp) %64 = bitcast %struct.S1998* %agg.tmp113 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %64, i8* align 16 bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i1 false) %65 = bitcast %struct.S1998* %agg.tmp114 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %65, i8* align 16 bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i1 false) %66 = bitcast %struct.S1998* %agg.tmp115 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %66, i8* align 16 bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i1 false) - call void (i32, ...) @check1998va(i32 signext 1, double 1.000000e+00, %struct.S1998* byval align 16 %agg.tmp113, i64 2, %struct.S1998* byval align 16 %agg.tmp114, %struct.S1998* byval align 16 %agg.tmp115) + call void (i32, ...) @check1998va(i32 signext 1, double 1.000000e+00, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp113, i64 2, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp114, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp115) %67 = bitcast %struct.S1998* %agg.tmp116 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %67, i8* align 16 bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i1 false) %68 = bitcast %struct.S1998* %agg.tmp117 to i8* @@ -349,14 +349,14 @@ if.end: ; preds = %if.then, %entry call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %69, i8* align 16 bitcast (%struct.S1998* getelementptr inbounds ([5 x %struct.S1998], [5 x %struct.S1998]* @a1998, i32 0, i64 2) to i8*), i64 5168, i1 false) %70 = bitcast %struct.S1998* %agg.tmp119 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %70, i8* align 16 bitcast (%struct.S1998* @s1998 to i8*), i64 5168, i1 false) - call void (i32, ...) @check1998va(i32 signext 2, %struct.S1998* byval align 16 %agg.tmp116, %struct.S1998* byval align 16 %agg.tmp117, ppc_fp128 0xM40000000000000000000000000000000, %struct.S1998* byval align 16 %agg.tmp118, %struct.S1998* byval align 16 %agg.tmp119) + call void (i32, ...) @check1998va(i32 signext 2, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp116, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp117, ppc_fp128 0xM40000000000000000000000000000000, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp118, %struct.S1998* byval(%struct.S1998) align 16 %agg.tmp119) ret void } declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) -declare void @check1998(%struct.S1998* sret, %struct.S1998* byval align 16, %struct.S1998*, %struct.S1998* byval align 16) +declare void @check1998(%struct.S1998* sret(%struct.S1998), %struct.S1998* byval(%struct.S1998) align 16, %struct.S1998*, %struct.S1998* byval(%struct.S1998) align 16) declare void @check1998va(i32 signext, ...) -declare void @checkx1998(%struct.S1998* byval align 16 %arg) +declare void @checkx1998(%struct.S1998* byval(%struct.S1998) align 16 %arg) diff --git a/llvm/test/CodeGen/PowerPC/resolvefi-disp.ll b/llvm/test/CodeGen/PowerPC/resolvefi-disp.ll index 68a31278e77d1..0bbb01d511700 100644 --- a/llvm/test/CodeGen/PowerPC/resolvefi-disp.ll +++ b/llvm/test/CodeGen/PowerPC/resolvefi-disp.ll @@ -20,7 +20,7 @@ target triple = "powerpc64le-unknown-linux-gnu" @s2760 = external global %struct.S2760 @fails = external global i32 -define void @check2760(%struct.S2760* noalias sret %agg.result, %struct.S2760* byval align 16, %struct.S2760* %arg1, %struct.S2760* byval align 16) { +define void @check2760(%struct.S2760* noalias sret(%struct.S2760) %agg.result, %struct.S2760* byval(%struct.S2760) align 16, %struct.S2760* %arg1, %struct.S2760* byval(%struct.S2760) align 16) { entry: %arg0 = alloca %struct.S2760, align 32 %arg2 = alloca %struct.S2760, align 32 diff --git a/llvm/test/CodeGen/PowerPC/select.ll b/llvm/test/CodeGen/PowerPC/select.ll index 7bfa03e32f112..bbbffe4d62cde 100644 --- a/llvm/test/CodeGen/PowerPC/select.ll +++ b/llvm/test/CodeGen/PowerPC/select.ll @@ -111,26 +111,18 @@ define i64 @f3(i64 %x, i64 %y) { define i64 @f4(i64 %x) { ; CHECK-LE-LABEL: f4: ; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: neg r4, r3 -; CHECK-LE-NEXT: cmpdi r3, 0 -; CHECK-LE-NEXT: iselgt r3, r4, r3 +; CHECK-LE-NEXT: sradi r4, r3, 63 +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: blr ; ; CHECK-32-LABEL: f4: ; CHECK-32: # %bb.0: -; CHECK-32-NEXT: cmplwi r3, 0 -; CHECK-32-NEXT: cmpwi cr1, r3, 0 -; CHECK-32-NEXT: crandc 4*cr5+lt, 4*cr1+gt, eq -; CHECK-32-NEXT: cmpwi cr1, r4, 0 -; CHECK-32-NEXT: subfic r5, r4, 0 -; CHECK-32-NEXT: crandc 4*cr5+gt, eq, 4*cr1+eq -; CHECK-32-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt -; CHECK-32-NEXT: subfze r6, r3 -; CHECK-32-NEXT: bc 12, 4*cr5+lt, .LBB4_1 -; CHECK-32-NEXT: blr -; CHECK-32-NEXT: .LBB4_1: -; CHECK-32-NEXT: addi r3, r6, 0 -; CHECK-32-NEXT: addi r4, r5, 0 +; CHECK-32-NEXT: srawi r5, r3, 31 +; CHECK-32-NEXT: xor r4, r4, r5 +; CHECK-32-NEXT: xor r3, r3, r5 +; CHECK-32-NEXT: subc r4, r5, r4 +; CHECK-32-NEXT: subfe r3, r3, r5 ; CHECK-32-NEXT: blr %c = icmp sgt i64 %x, 0 %x.neg = sub i64 0, %x @@ -166,20 +158,18 @@ define i64 @f4_sge_0(i64 %x) { define i64 @f4_slt_0(i64 %x) { ; CHECK-LE-LABEL: f4_slt_0: ; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: neg r4, r3 -; CHECK-LE-NEXT: cmpdi r3, 0 -; CHECK-LE-NEXT: isellt r3, r3, r4 +; CHECK-LE-NEXT: sradi r4, r3, 63 +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: blr ; ; CHECK-32-LABEL: f4_slt_0: ; CHECK-32: # %bb.0: -; CHECK-32-NEXT: subfic r5, r4, 0 -; CHECK-32-NEXT: subfze r6, r3 -; CHECK-32-NEXT: cmpwi r3, 0 -; CHECK-32-NEXT: bclr 12, lt, 0 -; CHECK-32-NEXT: # %bb.1: -; CHECK-32-NEXT: ori r3, r6, 0 -; CHECK-32-NEXT: ori r4, r5, 0 +; CHECK-32-NEXT: srawi r5, r3, 31 +; CHECK-32-NEXT: xor r4, r4, r5 +; CHECK-32-NEXT: xor r3, r3, r5 +; CHECK-32-NEXT: subc r4, r5, r4 +; CHECK-32-NEXT: subfe r3, r3, r5 ; CHECK-32-NEXT: blr %c = icmp slt i64 %x, 0 %x.neg = sub i64 0, %x @@ -219,24 +209,107 @@ define i64 @f4_sle_0(i64 %x) { define i64 @f4_sgt_m1(i64 %x) { ; CHECK-LE-LABEL: f4_sgt_m1: ; CHECK-LE: # %bb.0: -; CHECK-LE-NEXT: neg r4, r3 -; CHECK-LE-NEXT: cmpdi r3, -1 -; CHECK-LE-NEXT: iselgt r3, r4, r3 +; CHECK-LE-NEXT: sradi r4, r3, 63 +; CHECK-LE-NEXT: xor r3, r3, r4 +; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: blr ; ; CHECK-32-LABEL: f4_sgt_m1: ; CHECK-32: # %bb.0: -; CHECK-32-NEXT: subfic r5, r4, 0 -; CHECK-32-NEXT: subfze r6, r3 -; CHECK-32-NEXT: cmpwi r3, -1 -; CHECK-32-NEXT: bc 12, gt, .LBB8_1 -; CHECK-32-NEXT: blr -; CHECK-32-NEXT: .LBB8_1: -; CHECK-32-NEXT: addi r3, r6, 0 -; CHECK-32-NEXT: addi r4, r5, 0 +; CHECK-32-NEXT: srawi r5, r3, 31 +; CHECK-32-NEXT: xor r4, r4, r5 +; CHECK-32-NEXT: xor r3, r3, r5 +; CHECK-32-NEXT: subc r4, r5, r4 +; CHECK-32-NEXT: subfe r3, r3, r5 ; CHECK-32-NEXT: blr %c = icmp sgt i64 %x, -1 %x.neg = sub i64 0, %x %r = select i1 %c, i64 %x.neg, i64 %x ret i64 %r } + +define i64 @f5(i64 %x, i64 %y) { +; CHECK-LE-LABEL: f5: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: li r5, 0 +; CHECK-LE-NEXT: cmpldi r3, 0 +; CHECK-LE-NEXT: iseleq r3, r4, r5 +; CHECK-LE-NEXT: blr +; +; CHECK-32-LABEL: f5: +; CHECK-32: # %bb.0: +; CHECK-32-NEXT: li r7, 0 +; CHECK-32-NEXT: or. r3, r4, r3 +; CHECK-32-NEXT: bc 12, eq, .LBB9_2 +; CHECK-32-NEXT: # %bb.1: +; CHECK-32-NEXT: ori r3, r7, 0 +; CHECK-32-NEXT: ori r4, r7, 0 +; CHECK-32-NEXT: blr +; CHECK-32-NEXT: .LBB9_2: +; CHECK-32-NEXT: addi r3, r5, 0 +; CHECK-32-NEXT: addi r4, r6, 0 +; CHECK-32-NEXT: blr + %c = icmp eq i64 %x, 0 + %r = select i1 %c, i64 %y, i64 0 + ret i64 %r +} + +define i32 @f5_i32(i32 %x, i32 %y) { +; CHECK-LE-LABEL: f5_i32: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: li r5, 0 +; CHECK-LE-NEXT: cmplwi r3, 0 +; CHECK-LE-NEXT: iseleq r3, r4, r5 +; CHECK-LE-NEXT: blr +; +; CHECK-32-LABEL: f5_i32: +; CHECK-32: # %bb.0: +; CHECK-32-NEXT: li r5, 0 +; CHECK-32-NEXT: cmplwi r3, 0 +; CHECK-32-NEXT: bc 12, eq, .LBB10_2 +; CHECK-32-NEXT: # %bb.1: +; CHECK-32-NEXT: ori r3, r5, 0 +; CHECK-32-NEXT: blr +; CHECK-32-NEXT: .LBB10_2: +; CHECK-32-NEXT: addi r3, r4, 0 +; CHECK-32-NEXT: blr + %c = icmp eq i32 %x, 0 + %r = select i1 %c, i32 %y, i32 0 + ret i32 %r +} + +define i64 @f6(i64 %x) { +; CHECK-LE-LABEL: f6: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: cntlzd r3, r3 +; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 +; CHECK-LE-NEXT: blr +; +; CHECK-32-LABEL: f6: +; CHECK-32: # %bb.0: +; CHECK-32-NEXT: or r3, r4, r3 +; CHECK-32-NEXT: cntlzw r3, r3 +; CHECK-32-NEXT: rlwinm r4, r3, 27, 31, 31 +; CHECK-32-NEXT: li r3, 0 +; CHECK-32-NEXT: blr + %c = icmp ne i64 %x, 0 + %r = select i1 %c, i64 0, i64 1 + ret i64 %r +} + +define i32 @f6_i32(i32 %x) { +; CHECK-LE-LABEL: f6_i32: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: cntlzw r3, r3 +; CHECK-LE-NEXT: srwi r3, r3, 5 +; CHECK-LE-NEXT: blr +; +; CHECK-32-LABEL: f6_i32: +; CHECK-32: # %bb.0: +; CHECK-32-NEXT: cntlzw r3, r3 +; CHECK-32-NEXT: rlwinm r3, r3, 27, 31, 31 +; CHECK-32-NEXT: blr + %c = icmp ne i32 %x, 0 + %r = select i1 %c, i32 0, i32 1 + ret i32 %r +} diff --git a/llvm/test/CodeGen/PowerPC/setcc-sub-flag.ll b/llvm/test/CodeGen/PowerPC/setcc-sub-flag.ll index ee4697b874e25..3d89fea122160 100644 --- a/llvm/test/CodeGen/PowerPC/setcc-sub-flag.ll +++ b/llvm/test/CodeGen/PowerPC/setcc-sub-flag.ll @@ -10,7 +10,7 @@ define void @f(i64 %a, i64 %b) { ; CHECK: liveins: $x3, $x4 ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x4 ; CHECK: [[COPY1:%[0-9]+]]:g8rc = COPY $x3 - ; CHECK: [[SUBF8_:%[0-9]+]]:g8rc = SUBF8 [[COPY1]], [[COPY]] + ; CHECK: [[SUBF8_:%[0-9]+]]:g8rc = nsw SUBF8 [[COPY1]], [[COPY]] %c = sub nsw i64 %b, %a call void @foo(i64 %c) %d = icmp slt i64 %a, %b diff --git a/llvm/test/CodeGen/PowerPC/shrink-wrap.ll b/llvm/test/CodeGen/PowerPC/shrink-wrap.ll index 74a83fee14e82..8bdba1e3ea3e5 100644 --- a/llvm/test/CodeGen/PowerPC/shrink-wrap.ll +++ b/llvm/test/CodeGen/PowerPC/shrink-wrap.ll @@ -32,9 +32,7 @@ entry: ; CHECK: std ; CHECK: blt 0, .LBB0_3 ; CHECK: # %bb.1: -; CHECK-NEXT: addi ; CHECK-NEXT: clrldi -; CHECK-NEXT: addi ; CHECK-NEXT: mtctr ; CHECK-NEXT: li ; CHECK: .LBB0_2: diff --git a/llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll b/llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll index cb513be9128cc..e4d5fa216b453 100644 --- a/llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll +++ b/llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll @@ -528,4 +528,502 @@ entry: ret i8 %c } +; alloca + align < probe_size +define i32 @f8(i64 %i) local_unnamed_addr #0 { +; CHECK-LE-LABEL: f8: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: clrldi r0, r1, 58 +; CHECK-LE-NEXT: std r30, -16(r1) +; CHECK-LE-NEXT: mr r30, r1 +; CHECK-LE-NEXT: subfic r0, r0, -896 +; CHECK-LE-NEXT: stdux r1, r1, r0 +; CHECK-LE-NEXT: .cfi_def_cfa_register r30 +; CHECK-LE-NEXT: .cfi_offset r30, -16 +; CHECK-LE-NEXT: addi r4, r1, 64 +; CHECK-LE-NEXT: sldi r3, r3, 2 +; CHECK-LE-NEXT: li r5, 1 +; CHECK-LE-NEXT: stwx r5, r4, r3 +; CHECK-LE-NEXT: lwz r3, 64(r1) +; CHECK-LE-NEXT: ld r1, 0(r1) +; CHECK-LE-NEXT: ld r30, -16(r1) +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: f8: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: clrldi r0, r1, 58 +; CHECK-BE-NEXT: std r30, -16(r1) +; CHECK-BE-NEXT: mr r30, r1 +; CHECK-BE-NEXT: subfic r0, r0, -896 +; CHECK-BE-NEXT: stdux r1, r1, r0 +; CHECK-BE-NEXT: .cfi_def_cfa_register r30 +; CHECK-BE-NEXT: .cfi_offset r30, -16 +; CHECK-BE-NEXT: addi r4, r1, 64 +; CHECK-BE-NEXT: li r5, 1 +; CHECK-BE-NEXT: sldi r3, r3, 2 +; CHECK-BE-NEXT: stwx r5, r4, r3 +; CHECK-BE-NEXT: lwz r3, 64(r1) +; CHECK-BE-NEXT: ld r1, 0(r1) +; CHECK-BE-NEXT: ld r30, -16(r1) +; CHECK-BE-NEXT: blr +; +; CHECK-32-LABEL: f8: +; CHECK-32: # %bb.0: +; CHECK-32-NEXT: clrlwi r0, r1, 26 +; CHECK-32-NEXT: subfic r0, r0, -896 +; CHECK-32-NEXT: stwux r1, r1, r0 +; CHECK-32-NEXT: sub r0, r1, r0 +; CHECK-32-NEXT: addic r0, r0, -8 +; CHECK-32-NEXT: stwx r30, 0, r0 +; CHECK-32-NEXT: addic r30, r0, 8 +; CHECK-32-NEXT: .cfi_def_cfa_register r30 +; CHECK-32-NEXT: .cfi_offset r30, -8 +; CHECK-32-NEXT: addi r3, r1, 64 +; CHECK-32-NEXT: li r5, 1 +; CHECK-32-NEXT: slwi r4, r4, 2 +; CHECK-32-NEXT: stwx r5, r3, r4 +; CHECK-32-NEXT: mr r0, r31 +; CHECK-32-NEXT: lwz r3, 64(r1) +; CHECK-32-NEXT: lwz r31, 0(r1) +; CHECK-32-NEXT: lwz r30, -8(r31) +; CHECK-32-NEXT: mr r1, r31 +; CHECK-32-NEXT: mr r31, r0 +; CHECK-32-NEXT: blr + %a = alloca i32, i32 200, align 64 + %b = getelementptr inbounds i32, i32* %a, i64 %i + store volatile i32 1, i32* %b + %c = load volatile i32, i32* %a + ret i32 %c +} + +; alloca > probe_size, align > probe_size +define i32 @f9(i64 %i) local_unnamed_addr #0 { +; CHECK-LE-LABEL: f9: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: std r30, -16(r1) +; CHECK-LE-NEXT: mr r30, r1 +; CHECK-LE-NEXT: .cfi_def_cfa r30, 0 +; CHECK-LE-NEXT: clrldi r0, r30, 53 +; CHECK-LE-NEXT: subc r12, r30, r0 +; CHECK-LE-NEXT: clrldi r0, r0, 52 +; CHECK-LE-NEXT: cmpdi r0, 0 +; CHECK-LE-NEXT: beq cr0, .LBB9_2 +; CHECK-LE-NEXT: # %bb.1: +; CHECK-LE-NEXT: neg r0, r0 +; CHECK-LE-NEXT: stdux r30, r1, r0 +; CHECK-LE-NEXT: .LBB9_2: +; CHECK-LE-NEXT: li r0, -4096 +; CHECK-LE-NEXT: cmpd r1, r12 +; CHECK-LE-NEXT: beq cr0, .LBB9_4 +; CHECK-LE-NEXT: .LBB9_3: +; CHECK-LE-NEXT: stdux r30, r1, r0 +; CHECK-LE-NEXT: cmpd r1, r12 +; CHECK-LE-NEXT: bne cr0, .LBB9_3 +; CHECK-LE-NEXT: .LBB9_4: +; CHECK-LE-NEXT: mr r12, r30 +; CHECK-LE-NEXT: stdu r12, -2048(r1) +; CHECK-LE-NEXT: stdu r12, -4096(r1) +; CHECK-LE-NEXT: stdu r12, -4096(r1) +; CHECK-LE-NEXT: .cfi_def_cfa_register r1 +; CHECK-LE-NEXT: .cfi_def_cfa_register r30 +; CHECK-LE-NEXT: .cfi_offset r30, -16 +; CHECK-LE-NEXT: addi r4, r1, 2048 +; CHECK-LE-NEXT: sldi r3, r3, 2 +; CHECK-LE-NEXT: li r5, 1 +; CHECK-LE-NEXT: stwx r5, r4, r3 +; CHECK-LE-NEXT: lwz r3, 2048(r1) +; CHECK-LE-NEXT: ld r1, 0(r1) +; CHECK-LE-NEXT: ld r30, -16(r1) +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: f9: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: std r30, -16(r1) +; CHECK-BE-NEXT: mr r30, r1 +; CHECK-BE-NEXT: .cfi_def_cfa r30, 0 +; CHECK-BE-NEXT: clrldi r0, r30, 53 +; CHECK-BE-NEXT: subc r12, r30, r0 +; CHECK-BE-NEXT: clrldi r0, r0, 52 +; CHECK-BE-NEXT: cmpdi r0, 0 +; CHECK-BE-NEXT: beq cr0, .LBB9_2 +; CHECK-BE-NEXT: # %bb.1: +; CHECK-BE-NEXT: neg r0, r0 +; CHECK-BE-NEXT: stdux r30, r1, r0 +; CHECK-BE-NEXT: .LBB9_2: +; CHECK-BE-NEXT: li r0, -4096 +; CHECK-BE-NEXT: cmpd r1, r12 +; CHECK-BE-NEXT: beq cr0, .LBB9_4 +; CHECK-BE-NEXT: .LBB9_3: +; CHECK-BE-NEXT: stdux r30, r1, r0 +; CHECK-BE-NEXT: cmpd r1, r12 +; CHECK-BE-NEXT: bne cr0, .LBB9_3 +; CHECK-BE-NEXT: .LBB9_4: +; CHECK-BE-NEXT: mr r12, r30 +; CHECK-BE-NEXT: stdu r12, -2048(r1) +; CHECK-BE-NEXT: stdu r12, -4096(r1) +; CHECK-BE-NEXT: stdu r12, -4096(r1) +; CHECK-BE-NEXT: .cfi_def_cfa_register r1 +; CHECK-BE-NEXT: .cfi_def_cfa_register r30 +; CHECK-BE-NEXT: .cfi_offset r30, -16 +; CHECK-BE-NEXT: addi r4, r1, 2048 +; CHECK-BE-NEXT: li r5, 1 +; CHECK-BE-NEXT: sldi r3, r3, 2 +; CHECK-BE-NEXT: stwx r5, r4, r3 +; CHECK-BE-NEXT: lwz r3, 2048(r1) +; CHECK-BE-NEXT: ld r1, 0(r1) +; CHECK-BE-NEXT: ld r30, -16(r1) +; CHECK-BE-NEXT: blr +; +; CHECK-32-LABEL: f9: +; CHECK-32: # %bb.0: +; CHECK-32-NEXT: mr r12, r1 +; CHECK-32-NEXT: .cfi_def_cfa r12, 0 +; CHECK-32-NEXT: clrlwi r0, r12, 21 +; CHECK-32-NEXT: subc r1, r1, r0 +; CHECK-32-NEXT: stwu r12, -2048(r1) +; CHECK-32-NEXT: stwu r12, -4096(r1) +; CHECK-32-NEXT: stwu r12, -4096(r1) +; CHECK-32-NEXT: .cfi_def_cfa_register r1 +; CHECK-32-NEXT: sub r0, r1, r12 +; CHECK-32-NEXT: sub r0, r1, r0 +; CHECK-32-NEXT: addic r0, r0, -8 +; CHECK-32-NEXT: stwx r30, 0, r0 +; CHECK-32-NEXT: addic r30, r0, 8 +; CHECK-32-NEXT: .cfi_def_cfa_register r30 +; CHECK-32-NEXT: .cfi_offset r30, -8 +; CHECK-32-NEXT: addi r3, r1, 2048 +; CHECK-32-NEXT: li r5, 1 +; CHECK-32-NEXT: slwi r4, r4, 2 +; CHECK-32-NEXT: stwx r5, r3, r4 +; CHECK-32-NEXT: mr r0, r31 +; CHECK-32-NEXT: lwz r3, 2048(r1) +; CHECK-32-NEXT: lwz r31, 0(r1) +; CHECK-32-NEXT: lwz r30, -8(r31) +; CHECK-32-NEXT: mr r1, r31 +; CHECK-32-NEXT: mr r31, r0 +; CHECK-32-NEXT: blr + %a = alloca i32, i32 2000, align 2048 + %b = getelementptr inbounds i32, i32* %a, i64 %i + store volatile i32 1, i32* %b + %c = load volatile i32, i32* %a + ret i32 %c +} + +; alloca < probe_size, align < probe_size, alloca + align > probe_size +define i32 @f10(i64 %i) local_unnamed_addr #0 { +; CHECK-LE-LABEL: f10: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: std r30, -16(r1) +; CHECK-LE-NEXT: mr r30, r1 +; CHECK-LE-NEXT: .cfi_def_cfa r30, 0 +; CHECK-LE-NEXT: clrldi r0, r30, 54 +; CHECK-LE-NEXT: subc r12, r30, r0 +; CHECK-LE-NEXT: clrldi r0, r0, 52 +; CHECK-LE-NEXT: cmpdi r0, 0 +; CHECK-LE-NEXT: beq cr0, .LBB10_2 +; CHECK-LE-NEXT: # %bb.1: +; CHECK-LE-NEXT: neg r0, r0 +; CHECK-LE-NEXT: stdux r30, r1, r0 +; CHECK-LE-NEXT: .LBB10_2: +; CHECK-LE-NEXT: li r0, -4096 +; CHECK-LE-NEXT: cmpd r1, r12 +; CHECK-LE-NEXT: beq cr0, .LBB10_4 +; CHECK-LE-NEXT: .LBB10_3: +; CHECK-LE-NEXT: stdux r30, r1, r0 +; CHECK-LE-NEXT: cmpd r1, r12 +; CHECK-LE-NEXT: bne cr0, .LBB10_3 +; CHECK-LE-NEXT: .LBB10_4: +; CHECK-LE-NEXT: mr r12, r30 +; CHECK-LE-NEXT: stdu r12, -1024(r1) +; CHECK-LE-NEXT: stdu r12, -4096(r1) +; CHECK-LE-NEXT: .cfi_def_cfa_register r1 +; CHECK-LE-NEXT: .cfi_def_cfa_register r30 +; CHECK-LE-NEXT: .cfi_offset r30, -16 +; CHECK-LE-NEXT: addi r4, r1, 1024 +; CHECK-LE-NEXT: sldi r3, r3, 2 +; CHECK-LE-NEXT: li r5, 1 +; CHECK-LE-NEXT: stwx r5, r4, r3 +; CHECK-LE-NEXT: lwz r3, 1024(r1) +; CHECK-LE-NEXT: ld r1, 0(r1) +; CHECK-LE-NEXT: ld r30, -16(r1) +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: f10: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: std r30, -16(r1) +; CHECK-BE-NEXT: mr r30, r1 +; CHECK-BE-NEXT: .cfi_def_cfa r30, 0 +; CHECK-BE-NEXT: clrldi r0, r30, 54 +; CHECK-BE-NEXT: subc r12, r30, r0 +; CHECK-BE-NEXT: clrldi r0, r0, 52 +; CHECK-BE-NEXT: cmpdi r0, 0 +; CHECK-BE-NEXT: beq cr0, .LBB10_2 +; CHECK-BE-NEXT: # %bb.1: +; CHECK-BE-NEXT: neg r0, r0 +; CHECK-BE-NEXT: stdux r30, r1, r0 +; CHECK-BE-NEXT: .LBB10_2: +; CHECK-BE-NEXT: li r0, -4096 +; CHECK-BE-NEXT: cmpd r1, r12 +; CHECK-BE-NEXT: beq cr0, .LBB10_4 +; CHECK-BE-NEXT: .LBB10_3: +; CHECK-BE-NEXT: stdux r30, r1, r0 +; CHECK-BE-NEXT: cmpd r1, r12 +; CHECK-BE-NEXT: bne cr0, .LBB10_3 +; CHECK-BE-NEXT: .LBB10_4: +; CHECK-BE-NEXT: mr r12, r30 +; CHECK-BE-NEXT: stdu r12, -1024(r1) +; CHECK-BE-NEXT: stdu r12, -4096(r1) +; CHECK-BE-NEXT: .cfi_def_cfa_register r1 +; CHECK-BE-NEXT: .cfi_def_cfa_register r30 +; CHECK-BE-NEXT: .cfi_offset r30, -16 +; CHECK-BE-NEXT: addi r4, r1, 1024 +; CHECK-BE-NEXT: li r5, 1 +; CHECK-BE-NEXT: sldi r3, r3, 2 +; CHECK-BE-NEXT: stwx r5, r4, r3 +; CHECK-BE-NEXT: lwz r3, 1024(r1) +; CHECK-BE-NEXT: ld r1, 0(r1) +; CHECK-BE-NEXT: ld r30, -16(r1) +; CHECK-BE-NEXT: blr +; +; CHECK-32-LABEL: f10: +; CHECK-32: # %bb.0: +; CHECK-32-NEXT: mr r12, r1 +; CHECK-32-NEXT: .cfi_def_cfa r12, 0 +; CHECK-32-NEXT: clrlwi r0, r12, 22 +; CHECK-32-NEXT: subc r1, r1, r0 +; CHECK-32-NEXT: stwu r12, -1024(r1) +; CHECK-32-NEXT: stwu r12, -4096(r1) +; CHECK-32-NEXT: .cfi_def_cfa_register r1 +; CHECK-32-NEXT: sub r0, r1, r12 +; CHECK-32-NEXT: sub r0, r1, r0 +; CHECK-32-NEXT: addic r0, r0, -8 +; CHECK-32-NEXT: stwx r30, 0, r0 +; CHECK-32-NEXT: addic r30, r0, 8 +; CHECK-32-NEXT: .cfi_def_cfa_register r30 +; CHECK-32-NEXT: .cfi_offset r30, -8 +; CHECK-32-NEXT: addi r3, r1, 1024 +; CHECK-32-NEXT: li r5, 1 +; CHECK-32-NEXT: slwi r4, r4, 2 +; CHECK-32-NEXT: stwx r5, r3, r4 +; CHECK-32-NEXT: mr r0, r31 +; CHECK-32-NEXT: lwz r3, 1024(r1) +; CHECK-32-NEXT: lwz r31, 0(r1) +; CHECK-32-NEXT: lwz r30, -8(r31) +; CHECK-32-NEXT: mr r1, r31 +; CHECK-32-NEXT: mr r31, r0 +; CHECK-32-NEXT: blr + %a = alloca i32, i32 1000, align 1024 + %b = getelementptr inbounds i32, i32* %a, i64 %i + store volatile i32 1, i32* %b + %c = load volatile i32, i32* %a + ret i32 %c +} + +define void @f11(i32 %vla_size, i64 %i) #0 { +; CHECK-LE-LABEL: f11: +; CHECK-LE: # %bb.0: +; CHECK-LE-NEXT: std r31, -8(r1) +; CHECK-LE-NEXT: std r30, -16(r1) +; CHECK-LE-NEXT: mr r30, r1 +; CHECK-LE-NEXT: .cfi_def_cfa r30, 0 +; CHECK-LE-NEXT: clrldi r0, r30, 49 +; CHECK-LE-NEXT: subc r12, r30, r0 +; CHECK-LE-NEXT: clrldi r0, r0, 52 +; CHECK-LE-NEXT: cmpdi r0, 0 +; CHECK-LE-NEXT: beq cr0, .LBB11_2 +; CHECK-LE-NEXT: # %bb.1: +; CHECK-LE-NEXT: neg r0, r0 +; CHECK-LE-NEXT: stdux r30, r1, r0 +; CHECK-LE-NEXT: .LBB11_2: +; CHECK-LE-NEXT: li r0, -4096 +; CHECK-LE-NEXT: cmpd r1, r12 +; CHECK-LE-NEXT: beq cr0, .LBB11_4 +; CHECK-LE-NEXT: .LBB11_3: +; CHECK-LE-NEXT: stdux r30, r1, r0 +; CHECK-LE-NEXT: cmpd r1, r12 +; CHECK-LE-NEXT: bne cr0, .LBB11_3 +; CHECK-LE-NEXT: .LBB11_4: +; CHECK-LE-NEXT: mr r12, r30 +; CHECK-LE-NEXT: li r0, 24 +; CHECK-LE-NEXT: mtctr r0 +; CHECK-LE-NEXT: .LBB11_5: +; CHECK-LE-NEXT: stdu r12, -4096(r1) +; CHECK-LE-NEXT: bdnz .LBB11_5 +; CHECK-LE-NEXT: # %bb.6: +; CHECK-LE-NEXT: .cfi_def_cfa_register r1 +; CHECK-LE-NEXT: .cfi_def_cfa_register r30 +; CHECK-LE-NEXT: .cfi_offset r31, -8 +; CHECK-LE-NEXT: .cfi_offset r30, -16 +; CHECK-LE-NEXT: clrldi r3, r3, 32 +; CHECK-LE-NEXT: lis r5, 1 +; CHECK-LE-NEXT: mr r31, r1 +; CHECK-LE-NEXT: li r6, 1 +; CHECK-LE-NEXT: addi r3, r3, 15 +; CHECK-LE-NEXT: ori r5, r5, 0 +; CHECK-LE-NEXT: rldicl r3, r3, 60, 4 +; CHECK-LE-NEXT: sldi r4, r4, 2 +; CHECK-LE-NEXT: add r5, r31, r5 +; CHECK-LE-NEXT: rldicl r3, r3, 4, 31 +; CHECK-LE-NEXT: stwx r6, r5, r4 +; CHECK-LE-NEXT: li r4, -32768 +; CHECK-LE-NEXT: neg r7, r3 +; CHECK-LE-NEXT: ld r3, 0(r1) +; CHECK-LE-NEXT: and r4, r7, r4 +; CHECK-LE-NEXT: mr r7, r4 +; CHECK-LE-NEXT: li r4, -4096 +; CHECK-LE-NEXT: divd r5, r7, r4 +; CHECK-LE-NEXT: mulld r4, r5, r4 +; CHECK-LE-NEXT: sub r5, r7, r4 +; CHECK-LE-NEXT: add r4, r1, r7 +; CHECK-LE-NEXT: stdux r3, r1, r5 +; CHECK-LE-NEXT: cmpd r1, r4 +; CHECK-LE-NEXT: beq cr0, .LBB11_8 +; CHECK-LE-NEXT: .LBB11_7: +; CHECK-LE-NEXT: stdu r3, -4096(r1) +; CHECK-LE-NEXT: cmpd r1, r4 +; CHECK-LE-NEXT: bne cr0, .LBB11_7 +; CHECK-LE-NEXT: .LBB11_8: +; CHECK-LE-NEXT: addi r3, r1, -32768 +; CHECK-LE-NEXT: lbz r3, 0(r3) +; CHECK-LE-NEXT: ld r1, 0(r1) +; CHECK-LE-NEXT: ld r31, -8(r1) +; CHECK-LE-NEXT: ld r30, -16(r1) +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: f11: +; CHECK-BE: # %bb.0: +; CHECK-BE-NEXT: std r31, -8(r1) +; CHECK-BE-NEXT: std r30, -16(r1) +; CHECK-BE-NEXT: mr r30, r1 +; CHECK-BE-NEXT: .cfi_def_cfa r30, 0 +; CHECK-BE-NEXT: clrldi r0, r30, 49 +; CHECK-BE-NEXT: subc r12, r30, r0 +; CHECK-BE-NEXT: clrldi r0, r0, 52 +; CHECK-BE-NEXT: cmpdi r0, 0 +; CHECK-BE-NEXT: beq cr0, .LBB11_2 +; CHECK-BE-NEXT: # %bb.1: +; CHECK-BE-NEXT: neg r0, r0 +; CHECK-BE-NEXT: stdux r30, r1, r0 +; CHECK-BE-NEXT: .LBB11_2: +; CHECK-BE-NEXT: li r0, -4096 +; CHECK-BE-NEXT: cmpd r1, r12 +; CHECK-BE-NEXT: beq cr0, .LBB11_4 +; CHECK-BE-NEXT: .LBB11_3: +; CHECK-BE-NEXT: stdux r30, r1, r0 +; CHECK-BE-NEXT: cmpd r1, r12 +; CHECK-BE-NEXT: bne cr0, .LBB11_3 +; CHECK-BE-NEXT: .LBB11_4: +; CHECK-BE-NEXT: mr r12, r30 +; CHECK-BE-NEXT: li r0, 24 +; CHECK-BE-NEXT: mtctr r0 +; CHECK-BE-NEXT: .LBB11_5: +; CHECK-BE-NEXT: stdu r12, -4096(r1) +; CHECK-BE-NEXT: bdnz .LBB11_5 +; CHECK-BE-NEXT: # %bb.6: +; CHECK-BE-NEXT: .cfi_def_cfa_register r1 +; CHECK-BE-NEXT: .cfi_def_cfa_register r30 +; CHECK-BE-NEXT: .cfi_offset r31, -8 +; CHECK-BE-NEXT: .cfi_offset r30, -16 +; CHECK-BE-NEXT: clrldi r3, r3, 32 +; CHECK-BE-NEXT: lis r5, 1 +; CHECK-BE-NEXT: addi r3, r3, 15 +; CHECK-BE-NEXT: mr r31, r1 +; CHECK-BE-NEXT: ori r5, r5, 0 +; CHECK-BE-NEXT: rldicl r3, r3, 60, 4 +; CHECK-BE-NEXT: add r5, r31, r5 +; CHECK-BE-NEXT: sldi r4, r4, 2 +; CHECK-BE-NEXT: li r6, 1 +; CHECK-BE-NEXT: rldicl r3, r3, 4, 31 +; CHECK-BE-NEXT: stwx r6, r5, r4 +; CHECK-BE-NEXT: neg r7, r3 +; CHECK-BE-NEXT: li r4, -32768 +; CHECK-BE-NEXT: and r4, r7, r4 +; CHECK-BE-NEXT: ld r3, 0(r1) +; CHECK-BE-NEXT: mr r7, r4 +; CHECK-BE-NEXT: li r4, -4096 +; CHECK-BE-NEXT: divd r5, r7, r4 +; CHECK-BE-NEXT: mulld r4, r5, r4 +; CHECK-BE-NEXT: sub r5, r7, r4 +; CHECK-BE-NEXT: add r4, r1, r7 +; CHECK-BE-NEXT: stdux r3, r1, r5 +; CHECK-BE-NEXT: cmpd r1, r4 +; CHECK-BE-NEXT: beq cr0, .LBB11_8 +; CHECK-BE-NEXT: .LBB11_7: +; CHECK-BE-NEXT: stdu r3, -4096(r1) +; CHECK-BE-NEXT: cmpd r1, r4 +; CHECK-BE-NEXT: bne cr0, .LBB11_7 +; CHECK-BE-NEXT: .LBB11_8: +; CHECK-BE-NEXT: addi r3, r1, -32768 +; CHECK-BE-NEXT: lbz r3, 0(r3) +; CHECK-BE-NEXT: ld r1, 0(r1) +; CHECK-BE-NEXT: ld r31, -8(r1) +; CHECK-BE-NEXT: ld r30, -16(r1) +; CHECK-BE-NEXT: blr +; +; CHECK-32-LABEL: f11: +; CHECK-32: # %bb.0: +; CHECK-32-NEXT: mr r12, r1 +; CHECK-32-NEXT: .cfi_def_cfa r12, 0 +; CHECK-32-NEXT: clrlwi r0, r12, 17 +; CHECK-32-NEXT: subc r1, r1, r0 +; CHECK-32-NEXT: li r0, 24 +; CHECK-32-NEXT: mtctr r0 +; CHECK-32-NEXT: .LBB11_1: +; CHECK-32-NEXT: stwu r12, -4096(r1) +; CHECK-32-NEXT: bdnz .LBB11_1 +; CHECK-32-NEXT: # %bb.2: +; CHECK-32-NEXT: .cfi_def_cfa_register r1 +; CHECK-32-NEXT: sub r0, r1, r12 +; CHECK-32-NEXT: sub r0, r1, r0 +; CHECK-32-NEXT: addic r0, r0, -4 +; CHECK-32-NEXT: stwx r31, 0, r0 +; CHECK-32-NEXT: addic r0, r0, -4 +; CHECK-32-NEXT: stwx r30, 0, r0 +; CHECK-32-NEXT: addic r30, r0, 8 +; CHECK-32-NEXT: .cfi_def_cfa_register r30 +; CHECK-32-NEXT: .cfi_offset r31, -4 +; CHECK-32-NEXT: .cfi_offset r30, -8 +; CHECK-32-NEXT: lis r4, 1 +; CHECK-32-NEXT: mr r31, r1 +; CHECK-32-NEXT: ori r4, r4, 0 +; CHECK-32-NEXT: addi r3, r3, 15 +; CHECK-32-NEXT: add r4, r31, r4 +; CHECK-32-NEXT: li r5, 1 +; CHECK-32-NEXT: slwi r6, r6, 2 +; CHECK-32-NEXT: rlwinm r3, r3, 0, 0, 27 +; CHECK-32-NEXT: neg r7, r3 +; CHECK-32-NEXT: stwx r5, r4, r6 +; CHECK-32-NEXT: li r4, -32768 +; CHECK-32-NEXT: and r4, r7, r4 +; CHECK-32-NEXT: lwz r3, 0(r1) +; CHECK-32-NEXT: mr r7, r4 +; CHECK-32-NEXT: li r4, -4096 +; CHECK-32-NEXT: divw r5, r7, r4 +; CHECK-32-NEXT: mullw r4, r5, r4 +; CHECK-32-NEXT: sub r5, r7, r4 +; CHECK-32-NEXT: add r4, r1, r7 +; CHECK-32-NEXT: stwux r3, r1, r5 +; CHECK-32-NEXT: cmpw r1, r4 +; CHECK-32-NEXT: beq cr0, .LBB11_4 +; CHECK-32-NEXT: .LBB11_3: +; CHECK-32-NEXT: stwu r3, -4096(r1) +; CHECK-32-NEXT: cmpw r1, r4 +; CHECK-32-NEXT: bne cr0, .LBB11_3 +; CHECK-32-NEXT: .LBB11_4: +; CHECK-32-NEXT: addi r3, r1, -32768 +; CHECK-32-NEXT: lbz r3, 0(r3) +; CHECK-32-NEXT: lwz r31, 0(r1) +; CHECK-32-NEXT: lwz r0, -4(r31) +; CHECK-32-NEXT: lwz r30, -8(r31) +; CHECK-32-NEXT: mr r1, r31 +; CHECK-32-NEXT: mr r31, r0 +; CHECK-32-NEXT: blr + %a = alloca i32, i32 4096, align 32768 + %b = getelementptr inbounds i32, i32* %a, i64 %i + store volatile i32 1, i32* %b + %1 = zext i32 %vla_size to i64 + %vla = alloca i8, i64 %1, align 2048 + %2 = load volatile i8, i8* %vla, align 2048 + ret void +} + attributes #0 = { "probe-stack"="inline-asm" } diff --git a/llvm/test/CodeGen/PowerPC/stack-realign.ll b/llvm/test/CodeGen/PowerPC/stack-realign.ll index ea3603b9ce20c..abb608797f072 100644 --- a/llvm/test/CodeGen/PowerPC/stack-realign.ll +++ b/llvm/test/CodeGen/PowerPC/stack-realign.ll @@ -11,7 +11,7 @@ declare void @bar(i32*) @barbaz = external global i32 -define void @goo(%struct.s* byval nocapture readonly %a) { +define void @goo(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [2 x i32], align 32 %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 @@ -105,7 +105,7 @@ entry: ; CHECK-32-PIC: addic 29, 0, 12 ; The large-frame-size case. -define void @hoo(%struct.s* byval nocapture readonly %a) { +define void @hoo(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [200000 x i32], align 32 %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 @@ -174,7 +174,7 @@ entry: ; Make sure that the FP save area is still allocated correctly relative to ; where r30 is saved. -define void @loo(%struct.s* byval nocapture readonly %a) { +define void @loo(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [2 x i32], align 32 %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 diff --git a/llvm/test/CodeGen/PowerPC/store_fptoi.ll b/llvm/test/CodeGen/PowerPC/store_fptoi.ll index 1e5b8414243b1..737ead9946f12 100644 --- a/llvm/test/CodeGen/PowerPC/store_fptoi.ll +++ b/llvm/test/CodeGen/PowerPC/store_fptoi.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \ @@ -9,254 +10,377 @@ ; Function Attrs: norecurse nounwind define void @qpConv2sdw(fp128* nocapture readonly %a, i64* nocapture %b) { +; CHECK-LABEL: qpConv2sdw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lxv 2, 0(3) +; CHECK-NEXT: xscvqpsdz 2, 2 +; CHECK-NEXT: stxsd 2, 0(4) +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: qpConv2sdw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: mflr 0 +; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48 +; CHECK-PWR8-NEXT: .cfi_offset lr, 16 +; CHECK-PWR8-NEXT: .cfi_offset r30, -16 +; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill +; CHECK-PWR8-NEXT: std 0, 16(1) +; CHECK-PWR8-NEXT: stdu 1, -48(1) +; CHECK-PWR8-NEXT: ld 5, 0(3) +; CHECK-PWR8-NEXT: ld 6, 8(3) +; CHECK-PWR8-NEXT: mr 30, 4 +; CHECK-PWR8-NEXT: mr 3, 5 +; CHECK-PWR8-NEXT: mr 4, 6 +; CHECK-PWR8-NEXT: bl __fixkfdi +; CHECK-PWR8-NEXT: nop +; CHECK-PWR8-NEXT: std 3, 0(30) +; CHECK-PWR8-NEXT: addi 1, 1, 48 +; CHECK-PWR8-NEXT: ld 0, 16(1) +; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: mtlr 0 +; CHECK-PWR8-NEXT: blr entry: %0 = load fp128, fp128* %a, align 16 %conv = fptosi fp128 %0 to i64 store i64 %conv, i64* %b, align 8 ret void -; CHECK-LABEL: qpConv2sdw -; CHECK: lxv [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvqpsdz [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsd [[CONV]], 0(4) -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: qpConv2sdw -; CHECK-PWR8: bl __fixkfdi -; CHECK-PWR8: blr } ; Function Attrs: norecurse nounwind define void @qpConv2sw(fp128* nocapture readonly %a, i32* nocapture %b) { +; CHECK-LABEL: qpConv2sw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lxv 2, 0(3) +; CHECK-NEXT: xscvqpswz 2, 2 +; CHECK-NEXT: stxsiwx 2, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: qpConv2sw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: mflr 0 +; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48 +; CHECK-PWR8-NEXT: .cfi_offset lr, 16 +; CHECK-PWR8-NEXT: .cfi_offset r30, -16 +; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill +; CHECK-PWR8-NEXT: std 0, 16(1) +; CHECK-PWR8-NEXT: stdu 1, -48(1) +; CHECK-PWR8-NEXT: ld 5, 0(3) +; CHECK-PWR8-NEXT: ld 6, 8(3) +; CHECK-PWR8-NEXT: mr 30, 4 +; CHECK-PWR8-NEXT: mr 3, 5 +; CHECK-PWR8-NEXT: mr 4, 6 +; CHECK-PWR8-NEXT: bl __fixkfsi +; CHECK-PWR8-NEXT: nop +; CHECK-PWR8-NEXT: stw 3, 0(30) +; CHECK-PWR8-NEXT: addi 1, 1, 48 +; CHECK-PWR8-NEXT: ld 0, 16(1) +; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: mtlr 0 +; CHECK-PWR8-NEXT: blr entry: %0 = load fp128, fp128* %a, align 16 %conv = fptosi fp128 %0 to i32 store i32 %conv, i32* %b, align 4 ret void -; CHECK-LABEL: qpConv2sw -; CHECK: lxv [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsiwx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: qpConv2sw -; CHECK-PWR8: bl __fixkfsi -; CHECK-PWR8: blr } ; Function Attrs: norecurse nounwind define void @qpConv2udw(fp128* nocapture readonly %a, i64* nocapture %b) { +; CHECK-LABEL: qpConv2udw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lxv 2, 0(3) +; CHECK-NEXT: xscvqpudz 2, 2 +; CHECK-NEXT: stxsd 2, 0(4) +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: qpConv2udw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: mflr 0 +; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48 +; CHECK-PWR8-NEXT: .cfi_offset lr, 16 +; CHECK-PWR8-NEXT: .cfi_offset r30, -16 +; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill +; CHECK-PWR8-NEXT: std 0, 16(1) +; CHECK-PWR8-NEXT: stdu 1, -48(1) +; CHECK-PWR8-NEXT: ld 5, 0(3) +; CHECK-PWR8-NEXT: ld 6, 8(3) +; CHECK-PWR8-NEXT: mr 30, 4 +; CHECK-PWR8-NEXT: mr 3, 5 +; CHECK-PWR8-NEXT: mr 4, 6 +; CHECK-PWR8-NEXT: bl __fixunskfdi +; CHECK-PWR8-NEXT: nop +; CHECK-PWR8-NEXT: std 3, 0(30) +; CHECK-PWR8-NEXT: addi 1, 1, 48 +; CHECK-PWR8-NEXT: ld 0, 16(1) +; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: mtlr 0 +; CHECK-PWR8-NEXT: blr entry: %0 = load fp128, fp128* %a, align 16 %conv = fptoui fp128 %0 to i64 store i64 %conv, i64* %b, align 8 ret void -; CHECK-LABEL: qpConv2udw -; CHECK: lxv [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvqpudz [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsd [[CONV]], 0(4) -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: qpConv2udw -; CHECK-PWR8: bl __fixunskfdi -; CHECK-PWR8: blr } ; Function Attrs: norecurse nounwind define void @qpConv2uw(fp128* nocapture readonly %a, i32* nocapture %b) { +; CHECK-LABEL: qpConv2uw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lxv 2, 0(3) +; CHECK-NEXT: xscvqpuwz 2, 2 +; CHECK-NEXT: stxsiwx 2, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: qpConv2uw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: mflr 0 +; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 48 +; CHECK-PWR8-NEXT: .cfi_offset lr, 16 +; CHECK-PWR8-NEXT: .cfi_offset r30, -16 +; CHECK-PWR8-NEXT: std 30, -16(1) # 8-byte Folded Spill +; CHECK-PWR8-NEXT: std 0, 16(1) +; CHECK-PWR8-NEXT: stdu 1, -48(1) +; CHECK-PWR8-NEXT: ld 5, 0(3) +; CHECK-PWR8-NEXT: ld 6, 8(3) +; CHECK-PWR8-NEXT: mr 30, 4 +; CHECK-PWR8-NEXT: mr 3, 5 +; CHECK-PWR8-NEXT: mr 4, 6 +; CHECK-PWR8-NEXT: bl __fixunskfsi +; CHECK-PWR8-NEXT: nop +; CHECK-PWR8-NEXT: stw 3, 0(30) +; CHECK-PWR8-NEXT: addi 1, 1, 48 +; CHECK-PWR8-NEXT: ld 0, 16(1) +; CHECK-PWR8-NEXT: ld 30, -16(1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: mtlr 0 +; CHECK-PWR8-NEXT: blr entry: %0 = load fp128, fp128* %a, align 16 %conv = fptoui fp128 %0 to i32 store i32 %conv, i32* %b, align 4 ret void -; CHECK-LABEL: qpConv2uw -; CHECK: lxv [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsiwx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: qpConv2uw -; CHECK-PWR8: bl __fixunskfsi -; CHECK-PWR8: blr } ; Function Attrs: norecurse nounwind define void @dpConv2sdw(double* nocapture readonly %a, i64* nocapture %b) { +; CHECK-LABEL: dpConv2sdw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: xscvdpsxds 2, 0 +; CHECK-NEXT: stxsd 2, 0(4) +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2sdw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxds 0, 0 +; CHECK-PWR8-NEXT: stxsdx 0, 0, 4 +; CHECK-PWR8-NEXT: blr entry: %0 = load double, double* %a, align 8 %conv = fptosi double %0 to i64 store i64 %conv, i64* %b, align 8 ret void -; CHECK-LABEL: dpConv2sdw -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK: xscvdpsxds [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsd [[CONV]], 0(4) -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2sdw -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4 -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2sw(double* nocapture readonly %a, i32* nocapture %b) { +; CHECK-LABEL: dpConv2sw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: xscvdpsxws 0, 0 +; CHECK-NEXT: stfiwx 0, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2sw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: stfiwx 0, 0, 4 +; CHECK-PWR8-NEXT: blr entry: %0 = load double, double* %a, align 8 %conv = fptosi double %0 to i32 store i32 %conv, i32* %b, align 4 ret void -; CHECK-LABEL: dpConv2sw -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stfiwx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2sw -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4 -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2shw(double* nocapture readonly %a, i16* nocapture %b) { +; CHECK-LABEL: dpConv2shw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: xscvdpsxws 0, 0 +; CHECK-NEXT: stxsihx 0, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2shw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: sth 3, 0(4) +; CHECK-PWR8-NEXT: blr entry: %0 = load double, double* %a, align 8 %conv = fptosi double %0 to i16 store i16 %conv, i16* %b, align 2 ret void -; CHECK-LABEL: dpConv2shw -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsihx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2shw -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: sth [[REG]], 0(4) -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2sb(double* nocapture readonly %a, i8* nocapture %b) { +; CHECK-LABEL: dpConv2sb: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: xscvdpsxws 0, 0 +; CHECK-NEXT: stxsibx 0, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2sb: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: stb 3, 0(4) +; CHECK-PWR8-NEXT: blr entry: %0 = load double, double* %a, align 8 %conv = fptosi double %0 to i8 store i8 %conv, i8* %b, align 1 ret void -; CHECK-LABEL: dpConv2sb -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsibx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2sb -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: stb [[REG]], 0(4) -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2sdw(float* nocapture readonly %a, i64* nocapture %b) { +; CHECK-LABEL: spConv2sdw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpsxds 2, 0 +; CHECK-NEXT: stxsd 2, 0(4) +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2sdw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxds 0, 0 +; CHECK-PWR8-NEXT: stxsdx 0, 0, 4 +; CHECK-PWR8-NEXT: blr entry: %0 = load float, float* %a, align 4 %conv = fptosi float %0 to i64 store i64 %conv, i64* %b, align 8 ret void -; CHECK-LABEL: spConv2sdw -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsd [[CONV]], 0(4) -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2sdw -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4 -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2sw(float* nocapture readonly %a, i32* nocapture %b) { +; CHECK-LABEL: spConv2sw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpsxws 0, 0 +; CHECK-NEXT: stfiwx 0, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2sw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: stfiwx 0, 0, 4 +; CHECK-PWR8-NEXT: blr entry: %0 = load float, float* %a, align 4 %conv = fptosi float %0 to i32 store i32 %conv, i32* %b, align 4 ret void -; CHECK-LABEL: spConv2sw -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stfiwx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2sw -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4 -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2shw(float* nocapture readonly %a, i16* nocapture %b) { +; CHECK-LABEL: spConv2shw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpsxws 0, 0 +; CHECK-NEXT: stxsihx 0, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2shw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: sth 3, 0(4) +; CHECK-PWR8-NEXT: blr entry: %0 = load float, float* %a, align 4 %conv = fptosi float %0 to i16 store i16 %conv, i16* %b, align 2 ret void -; CHECK-LABEL: spConv2shw -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsihx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2shw -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: sth [[REG]], 0(4) -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2sb(float* nocapture readonly %a, i8* nocapture %b) { +; CHECK-LABEL: spConv2sb: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpsxws 0, 0 +; CHECK-NEXT: stxsibx 0, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2sb: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: stb 3, 0(4) +; CHECK-PWR8-NEXT: blr entry: %0 = load float, float* %a, align 4 %conv = fptosi float %0 to i8 store i8 %conv, i8* %b, align 1 ret void -; CHECK-LABEL: spConv2sb -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsibx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2sb -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: stb [[REG]], 0(4) -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2sdw_x(double* nocapture readonly %a, i64* nocapture %b, +; CHECK-LABEL: dpConv2sdw_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: sldi 3, 5, 3 +; CHECK-NEXT: xscvdpsxds 0, 0 +; CHECK-NEXT: stxsdx 0, 4, 3 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2sdw_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: sldi 3, 5, 3 +; CHECK-PWR8-NEXT: xscvdpsxds 0, 0 +; CHECK-PWR8-NEXT: stxsdx 0, 4, 3 +; CHECK-PWR8-NEXT: blr i32 signext %idx) { entry: %0 = load double, double* %a, align 8 @@ -266,23 +390,26 @@ entry: store i64 %conv, i64* %arrayidx, align 8 ret void -; CHECK-LABEL: dpConv2sdw_x -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 3 -; CHECK-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]] -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2sdw_x -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3 -; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]] -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2sw_x(double* nocapture readonly %a, i32* nocapture %b, +; CHECK-LABEL: dpConv2sw_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: sldi 3, 5, 2 +; CHECK-NEXT: xscvdpsxws 0, 0 +; CHECK-NEXT: stfiwx 0, 4, 3 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2sw_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: sldi 3, 5, 2 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: stfiwx 0, 4, 3 +; CHECK-PWR8-NEXT: blr i32 signext %idx) { entry: %0 = load double, double* %a, align 8 @@ -292,23 +419,27 @@ entry: store i32 %conv, i32* %arrayidx, align 4 ret void -; CHECK-LABEL: dpConv2sw_x -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 2 -; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]] -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2sw_x -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]] -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2shw_x(double* nocapture readonly %a, i16* nocapture %b, +; CHECK-LABEL: dpConv2shw_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: sldi 3, 5, 1 +; CHECK-NEXT: xscvdpsxws 0, 0 +; CHECK-NEXT: stxsihx 0, 4, 3 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2shw_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: sldi 5, 5, 1 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: sthx 3, 4, 5 +; CHECK-PWR8-NEXT: blr i32 signext %idx) { entry: %0 = load double, double* %a, align 8 @@ -318,24 +449,25 @@ entry: store i16 %conv, i16* %arrayidx, align 2 ret void -; CHECK-LABEL: dpConv2shw_x -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 1 -; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]] -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2shw_x -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5 -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2sb_x(double* nocapture readonly %a, i8* nocapture %b, +; CHECK-LABEL: dpConv2sb_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: xscvdpsxws 0, 0 +; CHECK-NEXT: stxsibx 0, 4, 5 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2sb_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: stbx 3, 4, 5 +; CHECK-PWR8-NEXT: blr i32 signext %idx) { entry: %0 = load double, double* %a, align 8 @@ -345,22 +477,26 @@ entry: store i8 %conv, i8* %arrayidx, align 1 ret void -; CHECK-LABEL: dpConv2sb_x -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsibx [[CONV]], 4, 5 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2sb_x -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5 -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2sdw_x(float* nocapture readonly %a, i64* nocapture %b, +; CHECK-LABEL: spConv2sdw_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpsxds 0, 0 +; CHECK-NEXT: sldi 5, 5, 3 +; CHECK-NEXT: stxsdx 0, 4, 5 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2sdw_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: sldi 3, 5, 3 +; CHECK-PWR8-NEXT: xscvdpsxds 0, 0 +; CHECK-PWR8-NEXT: stxsdx 0, 4, 3 +; CHECK-PWR8-NEXT: blr i32 signext %idx) { entry: %0 = load float, float* %a, align 4 @@ -370,23 +506,26 @@ entry: store i64 %conv, i64* %arrayidx, align 8 ret void -; CHECK-LABEL: spConv2sdw_x -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 3 -; CHECK-DAG: xscvdpsxds [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]] -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2sdw_x -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 3 -; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]] -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2sw_x(float* nocapture readonly %a, i32* nocapture %b, +; CHECK-LABEL: spConv2sw_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpsxws 0, 0 +; CHECK-NEXT: sldi 5, 5, 2 +; CHECK-NEXT: stfiwx 0, 4, 5 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2sw_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: sldi 3, 5, 2 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: stfiwx 0, 4, 3 +; CHECK-PWR8-NEXT: blr i32 signext %idx) { entry: %0 = load float, float* %a, align 4 @@ -396,23 +535,27 @@ entry: store i32 %conv, i32* %arrayidx, align 4 ret void -; CHECK-LABEL: spConv2sw_x -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 2 -; CHECK-DAG: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]] -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2sw_x -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]] -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2shw_x(float* nocapture readonly %a, i16* nocapture %b, +; CHECK-LABEL: spConv2shw_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpsxws 0, 0 +; CHECK-NEXT: sldi 5, 5, 1 +; CHECK-NEXT: stxsihx 0, 4, 5 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2shw_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: sldi 5, 5, 1 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: sthx 3, 4, 5 +; CHECK-PWR8-NEXT: blr i32 signext %idx) { entry: %0 = load float, float* %a, align 4 @@ -422,24 +565,25 @@ entry: store i16 %conv, i16* %arrayidx, align 2 ret void -; CHECK-LABEL: spConv2shw_x -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 1 -; CHECK-DAG: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]] -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2shw_x -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG2:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: sthx [[REG2]], 4, [[REG]] -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2sb_x(float* nocapture readonly %a, i8* nocapture %b, +; CHECK-LABEL: spConv2sb_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpsxws 0, 0 +; CHECK-NEXT: stxsibx 0, 4, 5 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2sb_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: stbx 3, 4, 5 +; CHECK-PWR8-NEXT: blr i32 signext %idx) { entry: %0 = load float, float* %a, align 4 @@ -449,18 +593,7 @@ entry: store i8 %conv, i8* %arrayidx, align 1 ret void -; CHECK-LABEL: spConv2sb_x -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsibx [[CONV]], 4, 5 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2sb_x -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5 -; CHECK-PWR8-NEXT: blr } ; ========================================== @@ -469,178 +602,217 @@ entry: ; Function Attrs: norecurse nounwind define void @dpConv2udw(double* nocapture readonly %a, i64* nocapture %b) { +; CHECK-LABEL: dpConv2udw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: xscvdpuxds 2, 0 +; CHECK-NEXT: stxsd 2, 0(4) +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2udw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpuxds 0, 0 +; CHECK-PWR8-NEXT: stxsdx 0, 0, 4 +; CHECK-PWR8-NEXT: blr entry: %0 = load double, double* %a, align 8 %conv = fptoui double %0 to i64 store i64 %conv, i64* %b, align 8 ret void -; CHECK-LABEL: dpConv2udw -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK: xscvdpuxds [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsd [[CONV]], 0(4) -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2udw -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4 -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2uw(double* nocapture readonly %a, i32* nocapture %b) { +; CHECK-LABEL: dpConv2uw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: xscvdpuxws 0, 0 +; CHECK-NEXT: stfiwx 0, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2uw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpuxws 0, 0 +; CHECK-PWR8-NEXT: stfiwx 0, 0, 4 +; CHECK-PWR8-NEXT: blr entry: %0 = load double, double* %a, align 8 %conv = fptoui double %0 to i32 store i32 %conv, i32* %b, align 4 ret void -; CHECK-LABEL: dpConv2uw -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stfiwx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2uw -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4 -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2uhw(double* nocapture readonly %a, i16* nocapture %b) { +; CHECK-LABEL: dpConv2uhw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: xscvdpuxws 0, 0 +; CHECK-NEXT: stxsihx 0, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2uhw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: sth 3, 0(4) +; CHECK-PWR8-NEXT: blr entry: %0 = load double, double* %a, align 8 %conv = fptoui double %0 to i16 store i16 %conv, i16* %b, align 2 ret void -; CHECK-LABEL: dpConv2uhw -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsihx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2uhw -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: sth [[REG]], 0(4) -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2ub(double* nocapture readonly %a, i8* nocapture %b) { +; CHECK-LABEL: dpConv2ub: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: xscvdpuxws 0, 0 +; CHECK-NEXT: stxsibx 0, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2ub: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: stb 3, 0(4) +; CHECK-PWR8-NEXT: blr entry: %0 = load double, double* %a, align 8 %conv = fptoui double %0 to i8 store i8 %conv, i8* %b, align 1 ret void -; CHECK-LABEL: dpConv2ub -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsibx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2ub -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: stb [[REG]], 0(4) -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2udw(float* nocapture readonly %a, i64* nocapture %b) { +; CHECK-LABEL: spConv2udw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpuxds 2, 0 +; CHECK-NEXT: stxsd 2, 0(4) +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2udw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpuxds 0, 0 +; CHECK-PWR8-NEXT: stxsdx 0, 0, 4 +; CHECK-PWR8-NEXT: blr entry: %0 = load float, float* %a, align 4 %conv = fptoui float %0 to i64 store i64 %conv, i64* %b, align 8 ret void -; CHECK-LABEL: spConv2udw -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsd [[CONV]], 0(4) -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2udw -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4 -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2uw(float* nocapture readonly %a, i32* nocapture %b) { +; CHECK-LABEL: spConv2uw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpuxws 0, 0 +; CHECK-NEXT: stfiwx 0, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2uw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpuxws 0, 0 +; CHECK-PWR8-NEXT: stfiwx 0, 0, 4 +; CHECK-PWR8-NEXT: blr entry: %0 = load float, float* %a, align 4 %conv = fptoui float %0 to i32 store i32 %conv, i32* %b, align 4 ret void -; CHECK-LABEL: spConv2uw -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stfiwx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2uw -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4 -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2uhw(float* nocapture readonly %a, i16* nocapture %b) { +; CHECK-LABEL: spConv2uhw: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpuxws 0, 0 +; CHECK-NEXT: stxsihx 0, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2uhw: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: sth 3, 0(4) +; CHECK-PWR8-NEXT: blr entry: %0 = load float, float* %a, align 4 %conv = fptoui float %0 to i16 store i16 %conv, i16* %b, align 2 ret void -; CHECK-LABEL: spConv2uhw -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsihx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2uhw -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: sth [[REG]], 0(4) -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2ub(float* nocapture readonly %a, i8* nocapture %b) { +; CHECK-LABEL: spConv2ub: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpuxws 0, 0 +; CHECK-NEXT: stxsibx 0, 0, 4 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2ub: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: stb 3, 0(4) +; CHECK-PWR8-NEXT: blr entry: %0 = load float, float* %a, align 4 %conv = fptoui float %0 to i8 store i8 %conv, i8* %b, align 1 ret void -; CHECK-LABEL: spConv2ub -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsibx [[CONV]], 0, 4 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2ub -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: stb [[REG]], 0(4) -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2udw_x(double* nocapture readonly %a, i64* nocapture %b, +; CHECK-LABEL: dpConv2udw_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: sldi 3, 5, 3 +; CHECK-NEXT: xscvdpuxds 0, 0 +; CHECK-NEXT: stxsdx 0, 4, 3 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2udw_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: sldi 3, 5, 3 +; CHECK-PWR8-NEXT: xscvdpuxds 0, 0 +; CHECK-PWR8-NEXT: stxsdx 0, 4, 3 +; CHECK-PWR8-NEXT: blr i32 zeroext %idx) { entry: %0 = load double, double* %a, align 8 @@ -650,23 +822,26 @@ entry: store i64 %conv, i64* %arrayidx, align 8 ret void -; CHECK-LABEL: dpConv2udw_x -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 3 -; CHECK-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]] -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2udw_x -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3 -; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]] -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2uw_x(double* nocapture readonly %a, i32* nocapture %b, +; CHECK-LABEL: dpConv2uw_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: sldi 3, 5, 2 +; CHECK-NEXT: xscvdpuxws 0, 0 +; CHECK-NEXT: stfiwx 0, 4, 3 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2uw_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: sldi 3, 5, 2 +; CHECK-PWR8-NEXT: xscvdpuxws 0, 0 +; CHECK-PWR8-NEXT: stfiwx 0, 4, 3 +; CHECK-PWR8-NEXT: blr i32 zeroext %idx) { entry: %0 = load double, double* %a, align 8 @@ -676,23 +851,27 @@ entry: store i32 %conv, i32* %arrayidx, align 4 ret void -; CHECK-LABEL: dpConv2uw_x -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 2 -; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]] -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2uw_x -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2 -; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]] -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2uhw_x(double* nocapture readonly %a, i16* nocapture %b, +; CHECK-LABEL: dpConv2uhw_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: sldi 3, 5, 1 +; CHECK-NEXT: xscvdpuxws 0, 0 +; CHECK-NEXT: stxsihx 0, 4, 3 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2uhw_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: sldi 5, 5, 1 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: sthx 3, 4, 5 +; CHECK-PWR8-NEXT: blr i32 zeroext %idx) { entry: %0 = load double, double* %a, align 8 @@ -702,24 +881,25 @@ entry: store i16 %conv, i16* %arrayidx, align 2 ret void -; CHECK-LABEL: dpConv2uhw_x -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: sldi [[REG:[0-9]+]], 5, 1 -; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]] -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2uhw_x -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5 -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @dpConv2ub_x(double* nocapture readonly %a, i8* nocapture %b, +; CHECK-LABEL: dpConv2ub_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfd 0, 0(3) +; CHECK-NEXT: xscvdpuxws 0, 0 +; CHECK-NEXT: stxsibx 0, 4, 5 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: dpConv2ub_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfdx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: stbx 3, 4, 5 +; CHECK-PWR8-NEXT: blr i32 zeroext %idx) { entry: %0 = load double, double* %a, align 8 @@ -729,22 +909,26 @@ entry: store i8 %conv, i8* %arrayidx, align 1 ret void -; CHECK-LABEL: dpConv2ub_x -; CHECK: lfd [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsibx [[CONV]], 4, 5 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: dpConv2ub_x -; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5 -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2udw_x(float* nocapture readonly %a, i64* nocapture %b, +; CHECK-LABEL: spConv2udw_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpuxds 0, 0 +; CHECK-NEXT: sldi 5, 5, 3 +; CHECK-NEXT: stxsdx 0, 4, 5 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2udw_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: sldi 3, 5, 3 +; CHECK-PWR8-NEXT: xscvdpuxds 0, 0 +; CHECK-PWR8-NEXT: stxsdx 0, 4, 3 +; CHECK-PWR8-NEXT: blr i32 zeroext %idx) { entry: %0 = load float, float* %a, align 4 @@ -754,23 +938,26 @@ entry: store i64 %conv, i64* %arrayidx, align 8 ret void -; CHECK-LABEL: spConv2udw_x -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 3 -; CHECK-DAG: xscvdpuxds [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsdx [[CONV]], 4, [[REG]] -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2udw_x -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 3 -; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]] -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2uw_x(float* nocapture readonly %a, i32* nocapture %b, +; CHECK-LABEL: spConv2uw_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpuxws 0, 0 +; CHECK-NEXT: sldi 5, 5, 2 +; CHECK-NEXT: stfiwx 0, 4, 5 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2uw_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: sldi 3, 5, 2 +; CHECK-PWR8-NEXT: xscvdpuxws 0, 0 +; CHECK-PWR8-NEXT: stfiwx 0, 4, 3 +; CHECK-PWR8-NEXT: blr i32 zeroext %idx) { entry: %0 = load float, float* %a, align 4 @@ -780,23 +967,27 @@ entry: store i32 %conv, i32* %arrayidx, align 4 ret void -; CHECK-LABEL: spConv2uw_x -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 2 -; CHECK-DAG: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stfiwx [[CONV]], 4, [[REG]] -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2uw_x -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2 -; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]] -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2uhw_x(float* nocapture readonly %a, i16* nocapture %b, +; CHECK-LABEL: spConv2uhw_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpuxws 0, 0 +; CHECK-NEXT: sldi 5, 5, 1 +; CHECK-NEXT: stxsihx 0, 4, 5 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2uhw_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: sldi 5, 5, 1 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: sthx 3, 4, 5 +; CHECK-PWR8-NEXT: blr i32 zeroext %idx) { entry: %0 = load float, float* %a, align 4 @@ -806,24 +997,25 @@ entry: store i16 %conv, i16* %arrayidx, align 2 ret void -; CHECK-LABEL: spConv2uhw_x -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-DAG: sldi [[REG:[0-9]+]], 5, 1 -; CHECK-DAG: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsihx [[CONV]], 4, [[REG]] -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2uhw_x -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG2:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: sthx [[REG2]], 4, [[REG]] -; CHECK-PWR8-NEXT: blr } ; Function Attrs: norecurse nounwind define void @spConv2ub_x(float* nocapture readonly %a, i8* nocapture %b, +; CHECK-LABEL: spConv2ub_x: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lfs 0, 0(3) +; CHECK-NEXT: xscvdpuxws 0, 0 +; CHECK-NEXT: stxsibx 0, 4, 5 +; CHECK-NEXT: blr +; +; CHECK-PWR8-LABEL: spConv2ub_x: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: lfsx 0, 0, 3 +; CHECK-PWR8-NEXT: xscvdpsxws 0, 0 +; CHECK-PWR8-NEXT: mffprwz 3, 0 +; CHECK-PWR8-NEXT: stbx 3, 4, 5 +; CHECK-PWR8-NEXT: blr i32 zeroext %idx) { entry: %0 = load float, float* %a, align 4 @@ -833,16 +1025,5 @@ entry: store i8 %conv, i8* %arrayidx, align 1 ret void -; CHECK-LABEL: spConv2ub_x -; CHECK: lfs [[LD:[0-9]+]], 0(3) -; CHECK-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]] -; CHECK-NEXT: stxsibx [[CONV]], 4, 5 -; CHECK-NEXT: blr -; CHECK-PWR8-LABEL: spConv2ub_x -; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3 -; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]] -; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]] -; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5 -; CHECK-PWR8-NEXT: blr } diff --git a/llvm/test/CodeGen/PowerPC/structsinmem.ll b/llvm/test/CodeGen/PowerPC/structsinmem.ll index b994aae6eea9a..bbbd95ccd5f50 100644 --- a/llvm/test/CodeGen/PowerPC/structsinmem.ll +++ b/llvm/test/CodeGen/PowerPC/structsinmem.ll @@ -56,7 +56,7 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %5, i8* align 4 bitcast ({ i32, i16, [2 x i8] }* @caller1.p6 to i8*), i64 8, i1 false) %6 = bitcast %struct.s7* %p7 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %6, i8* align 4 bitcast ({ i32, i16, i8, i8 }* @caller1.p7 to i8*), i64 8, i1 false) - %call = call i32 @callee1(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, %struct.s1* byval %p1, %struct.s2* byval %p2, %struct.s3* byval %p3, %struct.s4* byval %p4, %struct.s5* byval %p5, %struct.s6* byval %p6, %struct.s7* byval %p7) + %call = call i32 @callee1(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, %struct.s1* byval(%struct.s1) %p1, %struct.s2* byval(%struct.s2) %p2, %struct.s3* byval(%struct.s3) %p3, %struct.s4* byval(%struct.s4) %p4, %struct.s5* byval(%struct.s5) %p5, %struct.s6* byval(%struct.s6) %p6, %struct.s7* byval(%struct.s7) %p7) ret i32 %call ; CHECK: stb {{[0-9]+}}, 119(1) @@ -70,7 +70,7 @@ entry: declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind -define internal i32 @callee1(i32 %z1, i32 %z2, i32 %z3, i32 %z4, i32 %z5, i32 %z6, i32 %z7, i32 %z8, %struct.s1* byval %v1, %struct.s2* byval %v2, %struct.s3* byval %v3, %struct.s4* byval %v4, %struct.s5* byval %v5, %struct.s6* byval %v6, %struct.s7* byval %v7) nounwind { +define internal i32 @callee1(i32 %z1, i32 %z2, i32 %z3, i32 %z4, i32 %z5, i32 %z6, i32 %z7, i32 %z8, %struct.s1* byval(%struct.s1) %v1, %struct.s2* byval(%struct.s2) %v2, %struct.s3* byval(%struct.s3) %v3, %struct.s4* byval(%struct.s4) %v4, %struct.s5* byval(%struct.s5) %v5, %struct.s6* byval(%struct.s6) %v6, %struct.s7* byval(%struct.s7) %v7) nounwind { entry: %z1.addr = alloca i32, align 4 %z2.addr = alloca i32, align 4 @@ -145,7 +145,7 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %5, i8* bitcast (%struct.t6* @caller2.p6 to i8*), i64 6, i1 false) %6 = bitcast %struct.t7* %p7 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* %6, i8* bitcast (%struct.t7* @caller2.p7 to i8*), i64 7, i1 false) - %call = call i32 @callee2(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, %struct.t1* byval %p1, %struct.t2* byval %p2, %struct.t3* byval %p3, %struct.t4* byval %p4, %struct.t5* byval %p5, %struct.t6* byval %p6, %struct.t7* byval %p7) + %call = call i32 @callee2(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, %struct.t1* byval(%struct.t1) %p1, %struct.t2* byval(%struct.t2) %p2, %struct.t3* byval(%struct.t3) %p3, %struct.t4* byval(%struct.t4) %p4, %struct.t5* byval(%struct.t5) %p5, %struct.t6* byval(%struct.t6) %p6, %struct.t7* byval(%struct.t7) %p7) ret i32 %call ; CHECK: stb {{[0-9]+}}, 119(1) @@ -161,7 +161,7 @@ entry: ; CHECK: stw {{[0-9]+}}, 161(1) } -define internal i32 @callee2(i32 %z1, i32 %z2, i32 %z3, i32 %z4, i32 %z5, i32 %z6, i32 %z7, i32 %z8, %struct.t1* byval %v1, %struct.t2* byval %v2, %struct.t3* byval %v3, %struct.t4* byval %v4, %struct.t5* byval %v5, %struct.t6* byval %v6, %struct.t7* byval %v7) nounwind { +define internal i32 @callee2(i32 %z1, i32 %z2, i32 %z3, i32 %z4, i32 %z5, i32 %z6, i32 %z7, i32 %z8, %struct.t1* byval(%struct.t1) %v1, %struct.t2* byval(%struct.t2) %v2, %struct.t3* byval(%struct.t3) %v3, %struct.t4* byval(%struct.t4) %v4, %struct.t5* byval(%struct.t5) %v5, %struct.t6* byval(%struct.t6) %v6, %struct.t7* byval(%struct.t7) %v7) nounwind { entry: %z1.addr = alloca i32, align 4 %z2.addr = alloca i32, align 4 diff --git a/llvm/test/CodeGen/PowerPC/structsinregs.ll b/llvm/test/CodeGen/PowerPC/structsinregs.ll index 08f8ba90fd1e7..caa78246e054d 100644 --- a/llvm/test/CodeGen/PowerPC/structsinregs.ll +++ b/llvm/test/CodeGen/PowerPC/structsinregs.ll @@ -56,7 +56,7 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %5, i8* align 4 bitcast ({ i32, i16, [2 x i8] }* @caller1.p6 to i8*), i64 8, i1 false) %6 = bitcast %struct.s7* %p7 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %6, i8* align 4 bitcast ({ i32, i16, i8, i8 }* @caller1.p7 to i8*), i64 8, i1 false) - %call = call i32 @callee1(%struct.s1* byval %p1, %struct.s2* byval %p2, %struct.s3* byval %p3, %struct.s4* byval %p4, %struct.s5* byval %p5, %struct.s6* byval %p6, %struct.s7* byval %p7) + %call = call i32 @callee1(%struct.s1* byval(%struct.s1) %p1, %struct.s2* byval(%struct.s2) %p2, %struct.s3* byval(%struct.s3) %p3, %struct.s4* byval(%struct.s4) %p4, %struct.s5* byval(%struct.s5) %p5, %struct.s6* byval(%struct.s6) %p6, %struct.s7* byval(%struct.s7) %p7) ret i32 %call ; CHECK-LABEL: caller1 @@ -71,7 +71,7 @@ entry: declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind -define internal i32 @callee1(%struct.s1* byval %v1, %struct.s2* byval %v2, %struct.s3* byval %v3, %struct.s4* byval %v4, %struct.s5* byval %v5, %struct.s6* byval %v6, %struct.s7* byval %v7) nounwind { +define internal i32 @callee1(%struct.s1* byval(%struct.s1) %v1, %struct.s2* byval(%struct.s2) %v2, %struct.s3* byval(%struct.s3) %v3, %struct.s4* byval(%struct.s4) %v4, %struct.s5* byval(%struct.s5) %v5, %struct.s6* byval(%struct.s6) %v6, %struct.s7* byval(%struct.s7) %v7) nounwind { entry: %a = getelementptr inbounds %struct.s1, %struct.s1* %v1, i32 0, i32 0 %0 = load i8, i8* %a, align 1 @@ -138,7 +138,7 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %5, i8* bitcast (%struct.t6* @caller2.p6 to i8*), i64 6, i1 false) %6 = bitcast %struct.t7* %p7 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* %6, i8* bitcast (%struct.t7* @caller2.p7 to i8*), i64 7, i1 false) - %call = call i32 @callee2(%struct.t1* byval %p1, %struct.t2* byval %p2, %struct.t3* byval %p3, %struct.t4* byval %p4, %struct.t5* byval %p5, %struct.t6* byval %p6, %struct.t7* byval %p7) + %call = call i32 @callee2(%struct.t1* byval(%struct.t1) %p1, %struct.t2* byval(%struct.t2) %p2, %struct.t3* byval(%struct.t3) %p3, %struct.t4* byval(%struct.t4) %p4, %struct.t5* byval(%struct.t5) %p5, %struct.t6* byval(%struct.t6) %p6, %struct.t7* byval(%struct.t7) %p7) ret i32 %call ; CHECK-LABEL: caller2 @@ -159,7 +159,7 @@ entry: ; CHECK: lbz 3, 160(31) } -define internal i32 @callee2(%struct.t1* byval %v1, %struct.t2* byval %v2, %struct.t3* byval %v3, %struct.t4* byval %v4, %struct.t5* byval %v5, %struct.t6* byval %v6, %struct.t7* byval %v7) nounwind { +define internal i32 @callee2(%struct.t1* byval(%struct.t1) %v1, %struct.t2* byval(%struct.t2) %v2, %struct.t3* byval(%struct.t3) %v3, %struct.t4* byval(%struct.t4) %v4, %struct.t5* byval(%struct.t5) %v5, %struct.t6* byval(%struct.t6) %v6, %struct.t7* byval(%struct.t7) %v7) nounwind { entry: %a = getelementptr inbounds %struct.t1, %struct.t1* %v1, i32 0, i32 0 %0 = load i8, i8* %a, align 1 diff --git a/llvm/test/CodeGen/PowerPC/tailcall-string-rvo.ll b/llvm/test/CodeGen/PowerPC/tailcall-string-rvo.ll index c48ee467031ca..86e7021cd26c4 100644 --- a/llvm/test/CodeGen/PowerPC/tailcall-string-rvo.ll +++ b/llvm/test/CodeGen/PowerPC/tailcall-string-rvo.ll @@ -16,15 +16,15 @@ target triple = "powerpc64le-linux-gnu" %"struct.__gnu_cxx::__vstring_utility, std::allocator >::_Alloc_hider.7.38.69" = type { i8* } %union.anon.8.39.70 = type { i64, [8 x i8] } -declare void @TestBaz(%class.basic_string.11.42.73* noalias sret %arg) +declare void @TestBaz(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) -define void @TestBar(%class.basic_string.11.42.73* noalias sret %arg) { +define void @TestBar(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) { bb: - call void @TestBaz(%class.basic_string.11.42.73* noalias sret %arg) + call void @TestBaz(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) ret void } -define void @TestFoo(%class.basic_string.11.42.73* noalias sret %arg) { +define void @TestFoo(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) { ; CHECK-LABEL: TestFoo: ; CHECK: #TC_RETURNd8 TestBar 0 bb: @@ -37,7 +37,7 @@ bb: store i64 13, i64* %tmp3, align 8 %tmp4 = getelementptr inbounds %class.basic_string.11.42.73, %class.basic_string.11.42.73* %arg, i64 0, i32 0, i32 0, i32 2, i32 1, i64 5 store i8 0, i8* %tmp4, align 1 - tail call void @TestBar(%class.basic_string.11.42.73* noalias sret %arg) + tail call void @TestBar(%class.basic_string.11.42.73* noalias sret(%class.basic_string.11.42.73) %arg) ret void } diff --git a/llvm/test/CodeGen/PowerPC/toc-load-sched-bug.ll b/llvm/test/CodeGen/PowerPC/toc-load-sched-bug.ll index 1ebc8d5143d0d..f017d216d546c 100644 --- a/llvm/test/CodeGen/PowerPC/toc-load-sched-bug.ll +++ b/llvm/test/CodeGen/PowerPC/toc-load-sched-bug.ll @@ -154,7 +154,7 @@ target triple = "powerpc64le-unknown-linux-gnu" @__PRETTY_FUNCTION__._ZN4llvm7ErrorOrISt10unique_ptrINS_12MemoryBufferESt14default_deleteIS2_EEE10getStorageEv = private unnamed_addr constant [206 x i8] c"storage_type *llvm::ErrorOr > >::getStorage() [T = std::unique_ptr >]\00", align 1 @_ZNSs4_Rep20_S_empty_rep_storageE = external global [0 x i64] -declare void @_ZN4llvm12MemoryBuffer14getFileOrSTDINENS_9StringRefEl(%"class.llvm::ErrorOr"* sret, [2 x i64], i64) #1 +declare void @_ZN4llvm12MemoryBuffer14getFileOrSTDINENS_9StringRefEl(%"class.llvm::ErrorOr"* sret(%"class.llvm::ErrorOr"), [2 x i64], i64) #1 declare void @_ZN4llvm16NamedRegionTimerC1ENS_9StringRefES1_b(%"struct.llvm::NamedRegionTimer"*, [2 x i64], [2 x i64], i1 zeroext) #1 @@ -184,7 +184,7 @@ entry: %2 = load i64, i64* %_M_length.i.i, align 8, !tbaa !7 %.fca.0.insert18 = insertvalue [2 x i64] undef, i64 %1, 0 %.fca.1.insert21 = insertvalue [2 x i64] %.fca.0.insert18, i64 %2, 1 - call void @_ZN4llvm12MemoryBuffer14getFileOrSTDINENS_9StringRefEl(%"class.llvm::ErrorOr"* sret %FileOrErr, [2 x i64] %.fca.1.insert21, i64 -1) #3 + call void @_ZN4llvm12MemoryBuffer14getFileOrSTDINENS_9StringRefEl(%"class.llvm::ErrorOr"* sret(%"class.llvm::ErrorOr") %FileOrErr, [2 x i64] %.fca.1.insert21, i64 -1) #3 %HasError.i24 = getelementptr inbounds %"class.llvm::ErrorOr", %"class.llvm::ErrorOr"* %FileOrErr, i64 0, i32 1 %bf.load.i25 = load i8, i8* %HasError.i24, align 8 %3 = and i8 %bf.load.i25, 1 @@ -211,7 +211,7 @@ if.then: ; preds = %_ZNK4llvm7ErrorOrIS %vtable.i = load void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)**, void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)*** %6, align 8, !tbaa !11 %vfn.i = getelementptr inbounds void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)*, void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)** %vtable.i, i64 3 %7 = load void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)*, void (%"class.std::basic_string"*, %"class.std::error_category"*, i32)** %vfn.i, align 8 - call void %7(%"class.std::basic_string"* sret %ref.tmp5, %"class.std::error_category"* %.c, i32 signext %phitmp) #3 + call void %7(%"class.std::basic_string"* sret(%"class.std::basic_string") %ref.tmp5, %"class.std::error_category"* %.c, i32 signext %phitmp) #3 %call2.i.i = call dereferenceable(8) %"class.std::basic_string"* @_ZNSs6insertEmPKcm(%"class.std::basic_string"* %ref.tmp5, i64 0, i8* getelementptr inbounds ([28 x i8], [28 x i8]* @.str, i64 0, i64 0), i64 27) #3 %_M_p2.i.i.i.i = getelementptr inbounds %"class.std::basic_string", %"class.std::basic_string"* %call2.i.i, i64 0, i32 0, i32 0 %8 = load i8*, i8** %_M_p2.i.i.i.i, align 8, !tbaa !13 diff --git a/llvm/test/CodeGen/PowerPC/vec-abi-align.ll b/llvm/test/CodeGen/PowerPC/vec-abi-align.ll index ba687d3f0b879..c01b55a32a6b0 100644 --- a/llvm/test/CodeGen/PowerPC/vec-abi-align.ll +++ b/llvm/test/CodeGen/PowerPC/vec-abi-align.ll @@ -24,7 +24,7 @@ entry: } ; Function Attrs: nounwind -define void @test2(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, %struct.s2* byval nocapture readonly %vs) #0 { +define void @test2(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, %struct.s2* byval(%struct.s2) nocapture readonly %vs) #0 { entry: %m = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 0 %0 = load i64, i64* %m, align 8 @@ -50,7 +50,7 @@ entry: } ; Function Attrs: nounwind -define void @test3(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, %struct.s2* byval nocapture readonly %vs) #0 { +define void @test3(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, %struct.s2* byval(%struct.s2) nocapture readonly %vs) #0 { entry: %m = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 0 %0 = load i64, i64* %m, align 8 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll index ecf02feff826d..6a95771a589e0 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll @@ -331,7 +331,7 @@ entry: ret <8 x i16> %1 } -define void @test16elt(<16 x i16>* noalias nocapture sret %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 { +define void @test16elt(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: lvx v5, 0, r4 @@ -979,7 +979,7 @@ entry: ret <8 x i16> %1 } -define void @test16elt_signed(<16 x i16>* noalias nocapture sret %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 { +define void @test16elt_signed(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: lvx v5, 0, r4 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll index fe87bea1c1381..a94e1f2359145 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll @@ -41,7 +41,7 @@ entry: ret <2 x i64> %1 } -define void @test4elt(<4 x i64>* noalias nocapture sret %agg.result, <4 x float> %a) local_unnamed_addr #1 { +define void @test4elt(<4 x i64>* noalias nocapture sret(<4 x i64>) %agg.result, <4 x float> %a) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 @@ -86,7 +86,7 @@ entry: ret void } -define void @test8elt(<8 x i64>* noalias nocapture sret %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { +define void @test8elt(<8 x i64>* noalias nocapture sret(<8 x i64>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -166,7 +166,7 @@ entry: ret void } -define void @test16elt(<16 x i64>* noalias nocapture sret %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { +define void @test16elt(<16 x i64>* noalias nocapture sret(<16 x i64>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r7, 48 @@ -340,7 +340,7 @@ entry: ret <2 x i64> %1 } -define void @test4elt_signed(<4 x i64>* noalias nocapture sret %agg.result, <4 x float> %a) local_unnamed_addr #1 { +define void @test4elt_signed(<4 x i64>* noalias nocapture sret(<4 x i64>) %agg.result, <4 x float> %a) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 @@ -385,7 +385,7 @@ entry: ret void } -define void @test8elt_signed(<8 x i64>* noalias nocapture sret %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { +define void @test8elt_signed(<8 x i64>* noalias nocapture sret(<8 x i64>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -465,7 +465,7 @@ entry: ret void } -define void @test16elt_signed(<16 x i64>* noalias nocapture sret %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { +define void @test16elt_signed(<16 x i64>* noalias nocapture sret(<16 x i64>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r7, 48 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll index 0e0a3240f471f..26db909198d5e 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll @@ -290,7 +290,7 @@ entry: ret <8 x i16> %1 } -define void @test16elt(<16 x i16>* noalias nocapture sret %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #3 { +define void @test16elt(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -853,7 +853,7 @@ entry: ret <8 x i16> %1 } -define void @test16elt_signed(<16 x i16>* noalias nocapture sret %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #3 { +define void @test16elt_signed(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll index c0d2dd35aeb85..887cee610b8b1 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll @@ -97,7 +97,7 @@ entry: ret <4 x i32> %1 } -define void @test8elt(<8 x i32>* noalias nocapture sret %agg.result, <8 x double>* nocapture readonly) local_unnamed_addr #2 { +define void @test8elt(<8 x i32>* noalias nocapture sret(<8 x i32>) %agg.result, <8 x double>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 32 @@ -171,7 +171,7 @@ entry: ret void } -define void @test16elt(<16 x i32>* noalias nocapture sret %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #2 { +define void @test16elt(<16 x i32>* noalias nocapture sret(<16 x i32>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 32 @@ -389,7 +389,7 @@ entry: ret <4 x i32> %1 } -define void @test8elt_signed(<8 x i32>* noalias nocapture sret %agg.result, <8 x double>* nocapture readonly) local_unnamed_addr #2 { +define void @test8elt_signed(<8 x i32>* noalias nocapture sret(<8 x i32>) %agg.result, <8 x double>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 32 @@ -463,7 +463,7 @@ entry: ret void } -define void @test16elt_signed(<16 x i32>* noalias nocapture sret %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #2 { +define void @test16elt_signed(<16 x i32>* noalias nocapture sret(<16 x i32>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 32 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll index 4a4f332225af4..a09fbf2000b74 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll @@ -60,7 +60,7 @@ entry: ret <4 x i32> %0 } -define void @test8elt(<8 x i32>* noalias nocapture sret %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { +define void @test8elt(<8 x i32>* noalias nocapture sret(<8 x i32>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -98,7 +98,7 @@ entry: ret void } -define void @test16elt(<16 x i32>* noalias nocapture sret %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { +define void @test16elt(<16 x i32>* noalias nocapture sret(<16 x i32>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -207,7 +207,7 @@ entry: ret <4 x i32> %0 } -define void @test8elt_signed(<8 x i32>* noalias nocapture sret %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { +define void @test8elt_signed(<8 x i32>* noalias nocapture sret(<8 x i32>) %agg.result, <8 x float>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -245,7 +245,7 @@ entry: ret void } -define void @test16elt_signed(<16 x i32>* noalias nocapture sret %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { +define void @test16elt_signed(<16 x i32>* noalias nocapture sret(<16 x i32>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_8byte_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_8byte_elts.ll index dfca814cab23e..b8a55d7ef448d 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_8byte_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_8byte_elts.ll @@ -29,7 +29,7 @@ entry: ret <2 x i64> %0 } -define void @test4elt(<4 x i64>* noalias nocapture sret %agg.result, <4 x double>* nocapture readonly) local_unnamed_addr #1 { +define void @test4elt(<4 x i64>* noalias nocapture sret(<4 x i64>) %agg.result, <4 x double>* nocapture readonly) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -67,7 +67,7 @@ entry: ret void } -define void @test8elt(<8 x i64>* noalias nocapture sret %agg.result, <8 x double>* nocapture readonly) local_unnamed_addr #1 { +define void @test8elt(<8 x i64>* noalias nocapture sret(<8 x i64>) %agg.result, <8 x double>* nocapture readonly) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -125,7 +125,7 @@ entry: ret void } -define void @test16elt(<16 x i64>* noalias nocapture sret %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #1 { +define void @test16elt(<16 x i64>* noalias nocapture sret(<16 x i64>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -243,7 +243,7 @@ entry: ret <2 x i64> %0 } -define void @test4elt_signed(<4 x i64>* noalias nocapture sret %agg.result, <4 x double>* nocapture readonly) local_unnamed_addr #1 { +define void @test4elt_signed(<4 x i64>* noalias nocapture sret(<4 x i64>) %agg.result, <4 x double>* nocapture readonly) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -281,7 +281,7 @@ entry: ret void } -define void @test8elt_signed(<8 x i64>* noalias nocapture sret %agg.result, <8 x double>* nocapture readonly) local_unnamed_addr #1 { +define void @test8elt_signed(<8 x i64>* noalias nocapture sret(<8 x i64>) %agg.result, <8 x double>* nocapture readonly) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -339,7 +339,7 @@ entry: ret void } -define void @test16elt_signed(<16 x i64>* noalias nocapture sret %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #1 { +define void @test16elt_signed(<16 x i64>* noalias nocapture sret(<16 x i64>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll index 60fb0c29b5588..ee03a5edf13ee 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll @@ -110,7 +110,7 @@ entry: ret <4 x float> %1 } -define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, <8 x i16> %a) local_unnamed_addr #2 { +define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: xxlxor v3, v3, v3 @@ -156,7 +156,7 @@ entry: ret void } -define void @test16elt(<16 x float>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { +define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r5, r2, .LCPI3_0@toc@ha @@ -342,7 +342,7 @@ entry: ret <4 x float> %1 } -define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, <8 x i16> %a) local_unnamed_addr #2 { +define void @test8elt_signed(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: vmrglh v4, v2, v2 @@ -393,7 +393,7 @@ entry: ret void } -define void @test16elt_signed(<16 x float>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { +define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll index 903b492e33963..99a1031030968 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll @@ -48,7 +48,7 @@ entry: ret <2 x double> %1 } -define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 { +define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha @@ -112,7 +112,7 @@ entry: ret void } -define void @test8elt(<8 x double>* noalias nocapture sret %agg.result, <8 x i16> %a) local_unnamed_addr #2 { +define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_0@toc@ha @@ -212,7 +212,7 @@ entry: ret void } -define void @test16elt(<16 x double>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { +define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r6, r2, .LCPI3_2@toc@ha @@ -407,7 +407,7 @@ entry: ret <2 x double> %1 } -define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 { +define void @test4elt_signed(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha @@ -481,7 +481,7 @@ entry: ret void } -define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, <8 x i16> %a) local_unnamed_addr #2 { +define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_2@toc@ha @@ -599,7 +599,7 @@ entry: ret void } -define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { +define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r5, r2, .LCPI7_0@toc@ha diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll index 71a1718ab8776..a96a0e55b4e22 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll @@ -38,7 +38,7 @@ entry: ret <2 x double> %1 } -define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, <4 x i32> %a) local_unnamed_addr #1 { +define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, <4 x i32> %a) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: xxmrglw v3, v2, v2 @@ -77,7 +77,7 @@ entry: ret void } -define void @test8elt(<8 x double>* noalias nocapture sret %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 { +define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -145,7 +145,7 @@ entry: ret void } -define void @test16elt(<16 x double>* noalias nocapture sret %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 { +define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -292,7 +292,7 @@ entry: ret <2 x double> %1 } -define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, <4 x i32> %a) local_unnamed_addr #1 { +define void @test4elt_signed(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, <4 x i32> %a) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: xxmrglw v3, v2, v2 @@ -331,7 +331,7 @@ entry: ret void } -define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 { +define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -399,7 +399,7 @@ entry: ret void } -define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 { +define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll index 2e757152e4285..8dd041aa25dc6 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll @@ -98,7 +98,7 @@ entry: ret <4 x float> %1 } -define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #2 { +define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 32 @@ -172,7 +172,7 @@ entry: ret void } -define void @test16elt(<16 x float>* noalias nocapture sret %agg.result, <16 x i64>* nocapture readonly) local_unnamed_addr #2 { +define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i64>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 32 @@ -391,7 +391,7 @@ entry: ret <4 x float> %1 } -define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #2 { +define void @test8elt_signed(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 32 @@ -465,7 +465,7 @@ entry: ret void } -define void @test16elt_signed(<16 x float>* noalias nocapture sret %agg.result, <16 x i64>* nocapture readonly) local_unnamed_addr #2 { +define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i64>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 32 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll index 1962ffa653112..6f0f6fd26ed0f 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll @@ -116,7 +116,7 @@ entry: ret <4 x float> %1 } -define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #2 { +define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha @@ -178,7 +178,7 @@ entry: ret void } -define void @test16elt(<16 x float>* noalias nocapture sret %agg.result, <16 x i8> %a) local_unnamed_addr #3 { +define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i8> %a) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha @@ -384,7 +384,7 @@ entry: ret <4 x float> %1 } -define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #2 { +define void @test8elt_signed(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha @@ -454,7 +454,7 @@ entry: ret void } -define void @test16elt_signed(<16 x float>* noalias nocapture sret %agg.result, <16 x i8> %a) local_unnamed_addr #3 { +define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i8> %a) local_unnamed_addr #3 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll index c68fa812ffe54..9e4014c8a2dbe 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll @@ -48,7 +48,7 @@ entry: ret <2 x double> %1 } -define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, i32 %a.coerce) local_unnamed_addr #1 { +define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha @@ -112,7 +112,7 @@ entry: ret void } -define void @test8elt(<8 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 { +define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha @@ -216,7 +216,7 @@ entry: ret void } -define void @test16elt(<16 x double>* noalias nocapture sret %agg.result, <16 x i8> %a) local_unnamed_addr #2 { +define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r4, r2, .LCPI3_0@toc@ha @@ -440,7 +440,7 @@ entry: ret <2 x double> %1 } -define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, i32 %a.coerce) local_unnamed_addr #1 { +define void @test4elt_signed(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha @@ -514,7 +514,7 @@ entry: ret void } -define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 { +define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha @@ -636,7 +636,7 @@ entry: ret void } -define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result, <16 x i8> %a) local_unnamed_addr #2 { +define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i8> %a) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: addis r4, r2, .LCPI7_0@toc@ha diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll index 8e99e032805f7..7ec148a029067 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll @@ -60,7 +60,7 @@ entry: ret <4 x float> %0 } -define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 { +define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -98,7 +98,7 @@ entry: ret void } -define void @test16elt(<16 x float>* noalias nocapture sret %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 { +define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -207,7 +207,7 @@ entry: ret <4 x float> %0 } -define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 { +define void @test8elt_signed(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i32>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -245,7 +245,7 @@ entry: ret void } -define void @test16elt_signed(<16 x float>* noalias nocapture sret %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 { +define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i32>* nocapture readonly) local_unnamed_addr #2 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_8byte_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_8byte_elts.ll index a18eab406657d..00443f36c7d2b 100644 --- a/llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_8byte_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_8byte_elts.ll @@ -29,7 +29,7 @@ entry: ret <2 x double> %0 } -define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, <4 x i64>* nocapture readonly) local_unnamed_addr #1 { +define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, <4 x i64>* nocapture readonly) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -67,7 +67,7 @@ entry: ret void } -define void @test8elt(<8 x double>* noalias nocapture sret %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #1 { +define void @test8elt(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test8elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -125,7 +125,7 @@ entry: ret void } -define void @test16elt(<16 x double>* noalias nocapture sret %agg.result, <16 x i64>* nocapture readonly) local_unnamed_addr #1 { +define void @test16elt(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i64>* nocapture readonly) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test16elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -243,7 +243,7 @@ entry: ret <2 x double> %0 } -define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, <4 x i64>* nocapture readonly) local_unnamed_addr #1 { +define void @test4elt_signed(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, <4 x i64>* nocapture readonly) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -281,7 +281,7 @@ entry: ret void } -define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #1 { +define void @test8elt_signed(<8 x double>* noalias nocapture sret(<8 x double>) %agg.result, <8 x i64>* nocapture readonly) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 @@ -339,7 +339,7 @@ entry: ret void } -define void @test16elt_signed(<16 x double>* noalias nocapture sret %agg.result, <16 x i64>* nocapture readonly) local_unnamed_addr #1 { +define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i64>* nocapture readonly) local_unnamed_addr #1 { ; CHECK-P8-LABEL: test16elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: li r5, 16 diff --git a/llvm/test/CodeGen/PowerPC/vec_select.ll b/llvm/test/CodeGen/PowerPC/vec_select.ll index 3b4f390611d49..2a839675b2a87 100644 --- a/llvm/test/CodeGen/PowerPC/vec_select.ll +++ b/llvm/test/CodeGen/PowerPC/vec_select.ll @@ -1,100 +1,178 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX -; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX +; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefixes=CHECK-NOVSX,CHECK-NOVSX-BE ; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX -; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX +; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefixes=CHECK-NOVSX,CHECK-NOVSX-LE define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) { +; CHECK-VSX-LABEL: test1: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: xvcmpeqsp vs0, v4, v5 +; CHECK-VSX-NEXT: xxsel v2, v3, v2, vs0 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: test1: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vcmpeqfp v4, v4, v5 +; CHECK-NOVSX-NEXT: vsel v2, v3, v2, v4 +; CHECK-NOVSX-NEXT: blr entry: %m = fcmp oeq <4 x float> %c, %d %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b ret <4 x float> %v } -; CHECK-VSX-LABLE: test1 -; CHECK-VSX: xvcmpeqsp [[REG1:(vs|v)[0-9]+]], v4, v5 -; CHECK-VSX: xxsel v2, v3, v2, [[REG1]] -; CHECK-VSX: blr - -; CHECK-NOVSX-LABLE: test1 -; CHECK-NOVSX: vcmpeqfp v[[REG1:[0-9]+]], v4, v5 -; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]] -; CHECK-NOVSX: blr define <2 x double> @test2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) { +; CHECK-VSX-LABEL: test2: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: xvcmpeqdp v4, v4, v5 +; CHECK-VSX-NEXT: xxsel v2, v3, v2, v4 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: test2: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: fcmpu cr0, f5, f7 +; CHECK-NOVSX-NEXT: beq cr0, .LBB1_2 +; CHECK-NOVSX-NEXT: # %bb.1: # %entry +; CHECK-NOVSX-NEXT: fmr f1, f3 +; CHECK-NOVSX-NEXT: .LBB1_2: # %entry +; CHECK-NOVSX-NEXT: fcmpu cr0, f6, f8 +; CHECK-NOVSX-NEXT: beqlr cr0 +; CHECK-NOVSX-NEXT: # %bb.3: # %entry +; CHECK-NOVSX-NEXT: fmr f2, f4 +; CHECK-NOVSX-NEXT: blr entry: %m = fcmp oeq <2 x double> %c, %d %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b ret <2 x double> %v } -; CHECK-VSX-LABLE: test2 -; CHECK-VSX: xvcmpeqdp [[REG1:(vs|v)[0-9]+]], v4, v5 -; CHECK-VSX: xxsel v2, v3, v2, [[REG1]] -; CHECK-VSX: blr - -; CHECK-NOVSX-LABLE: test2 -; CHECK-NOVSX: fcmp -; CHECK-NOVSX: fcmp -; CHECK-NOVSX: blr define <16 x i8> @test3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) { +; CHECK-VSX-LABEL: test3: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: vcmpequb v4, v4, v5 +; CHECK-VSX-NEXT: xxsel v2, v3, v2, v4 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: test3: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vcmpequb v4, v4, v5 +; CHECK-NOVSX-NEXT: vsel v2, v3, v2, v4 +; CHECK-NOVSX-NEXT: blr entry: %m = icmp eq <16 x i8> %c, %d %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b ret <16 x i8> %v } -; CHECK-VSX-LABLE: test3 -; CHECK-VSX: vcmpequb v[[REG1:[0-9]+]], v4, v5 -; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]] -; CHECK-VSX: blr - -; CHECK-NOVSX-LABLE: test3 -; CHECK-NOVSX: vcmpequb v[[REG1:[0-9]+]], v4, v5 -; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]] -; CHECK-NOVSX: blr define <8 x i16> @test4(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) { +; CHECK-VSX-LABEL: test4: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: vcmpequh v4, v4, v5 +; CHECK-VSX-NEXT: xxsel v2, v3, v2, v4 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: test4: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vcmpequh v4, v4, v5 +; CHECK-NOVSX-NEXT: vsel v2, v3, v2, v4 +; CHECK-NOVSX-NEXT: blr entry: %m = icmp eq <8 x i16> %c, %d %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b ret <8 x i16> %v } -; CHECK-VSX-LABLE: test4 -; CHECK-VSX: vcmpequh v[[REG1:[0-9]+]], v4, v5 -; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]] -; CHECK-VSX: blr - -; CHECK-NOVSX-LABLE: test4 -; CHECK-NOVSX: vcmpequh v[[REG1:[0-9]+]], v4, v5 -; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]] -; CHECK-NOVSX: blr define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { +; CHECK-VSX-LABEL: test5: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: vcmpequw v4, v4, v5 +; CHECK-VSX-NEXT: xxsel v2, v3, v2, v4 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: test5: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vcmpequw v4, v4, v5 +; CHECK-NOVSX-NEXT: vsel v2, v3, v2, v4 +; CHECK-NOVSX-NEXT: blr entry: %m = icmp eq <4 x i32> %c, %d %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b ret <4 x i32> %v } -; CHECK-VSX-LABLE: test5 -; CHECK-VSX: vcmpequw v[[REG1:[0-9]+]], v4, v5 -; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]] -; CHECK-VSX: blr - -; CHECK-NOVSX-LABLE: test5 -; CHECK-NOVSX: vcmpequw v[[REG1:[0-9]+]], v4, v5 -; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]] -; CHECK-NOVSX: blr define <2 x i64> @test6(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) { +; CHECK-VSX-LABEL: test6: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: vcmpequd v4, v4, v5 +; CHECK-VSX-NEXT: xxsel v2, v3, v2, v4 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-LABEL: test6: +; CHECK-NOVSX: # %bb.0: # %entry +; CHECK-NOVSX-NEXT: vcmpequd v4, v4, v5 +; CHECK-NOVSX-NEXT: vsel v2, v3, v2, v4 +; CHECK-NOVSX-NEXT: blr entry: %m = icmp eq <2 x i64> %c, %d %v = select <2 x i1> %m, <2 x i64> %a, <2 x i64> %b ret <2 x i64> %v } -; CHECK-VSX-LABLE: test6 -; CHECK-VSX: vcmpequd v[[REG1:[0-9]+]], v4, v5 -; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]] -; CHECK-VSX: blr -; CHECK-NOVSX-LABLE: test6 -; CHECK-NOVSX: vcmpequd v[[REG1:[0-9]+]], v4, v5 -; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]] -; CHECK-NOVSX: blr +define <1 x i128> @test7(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c, <1 x i128> %d) { +; CHECK-VSX-LABEL: test7: +; CHECK-VSX: # %bb.0: # %entry +; CHECK-VSX-NEXT: xxswapd vs0, v5 +; CHECK-VSX-NEXT: xxswapd vs1, v4 +; CHECK-VSX-NEXT: mfvsrd r3, v5 +; CHECK-VSX-NEXT: mfvsrd r4, v4 +; CHECK-VSX-NEXT: mffprd r5, f0 +; CHECK-VSX-NEXT: mffprd r6, f1 +; CHECK-VSX-NEXT: xor r3, r4, r3 +; CHECK-VSX-NEXT: xor r4, r6, r5 +; CHECK-VSX-NEXT: or. r3, r4, r3 +; CHECK-VSX-NEXT: bclr 12, eq, 0 +; CHECK-VSX-NEXT: # %bb.1: # %entry +; CHECK-VSX-NEXT: vmr v2, v3 +; CHECK-VSX-NEXT: blr +; +; CHECK-NOVSX-BE-LABEL: test7: +; CHECK-NOVSX-BE: # %bb.0: # %entry +; CHECK-NOVSX-BE-NEXT: addi r3, r1, -16 +; CHECK-NOVSX-BE-NEXT: addi r4, r1, -32 +; CHECK-NOVSX-BE-NEXT: stvx v5, 0, r3 +; CHECK-NOVSX-BE-NEXT: stvx v4, 0, r4 +; CHECK-NOVSX-BE-NEXT: ld r3, -16(r1) +; CHECK-NOVSX-BE-NEXT: ld r4, -32(r1) +; CHECK-NOVSX-BE-NEXT: ld r5, -8(r1) +; CHECK-NOVSX-BE-NEXT: ld r6, -24(r1) +; CHECK-NOVSX-BE-NEXT: xor r3, r4, r3 +; CHECK-NOVSX-BE-NEXT: xor r4, r6, r5 +; CHECK-NOVSX-BE-NEXT: or. r3, r4, r3 +; CHECK-NOVSX-BE-NEXT: bclr 12, eq, 0 +; CHECK-NOVSX-BE-NEXT: # %bb.1: # %entry +; CHECK-NOVSX-BE-NEXT: vmr v2, v3 +; CHECK-NOVSX-BE-NEXT: blr +; +; CHECK-NOVSX-LE-LABEL: test7: +; CHECK-NOVSX-LE: # %bb.0: # %entry +; CHECK-NOVSX-LE-NEXT: addi r3, r1, -16 +; CHECK-NOVSX-LE-NEXT: addi r4, r1, -32 +; CHECK-NOVSX-LE-NEXT: stvx v5, 0, r3 +; CHECK-NOVSX-LE-NEXT: stvx v4, 0, r4 +; CHECK-NOVSX-LE-NEXT: ld r3, -8(r1) +; CHECK-NOVSX-LE-NEXT: ld r4, -24(r1) +; CHECK-NOVSX-LE-NEXT: ld r5, -16(r1) +; CHECK-NOVSX-LE-NEXT: ld r6, -32(r1) +; CHECK-NOVSX-LE-NEXT: xor r3, r4, r3 +; CHECK-NOVSX-LE-NEXT: xor r4, r6, r5 +; CHECK-NOVSX-LE-NEXT: or. r3, r4, r3 +; CHECK-NOVSX-LE-NEXT: bclr 12, eq, 0 +; CHECK-NOVSX-LE-NEXT: # %bb.1: # %entry +; CHECK-NOVSX-LE-NEXT: vmr v2, v3 +; CHECK-NOVSX-LE-NEXT: blr +entry: + %m = icmp eq <1 x i128> %c, %d + %v = select <1 x i1> %m, <1 x i128> %a, <1 x i128> %b + ret <1 x i128> %v +} diff --git a/llvm/test/CodeGen/PowerPC/vsx_builtins.ll b/llvm/test/CodeGen/PowerPC/vsx_builtins.ll index 0aae50af26490..b40a84a7e95c5 100644 --- a/llvm/test/CodeGen/PowerPC/vsx_builtins.ll +++ b/llvm/test/CodeGen/PowerPC/vsx_builtins.ll @@ -131,8 +131,7 @@ define i32 @xvtdivdp_shift(<2 x double> %a, <2 x double> %b) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xvtdivdp cr0, v2, v3 ; CHECK-NEXT: mfocrf r3, 128 -; CHECK-NEXT: srwi r3, r3, 28 -; CHECK-NEXT: rlwinm r3, r3, 28, 31, 31 +; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: blr entry: %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b) diff --git a/llvm/test/CodeGen/RISCV/alu64.ll b/llvm/test/CodeGen/RISCV/alu64.ll index 1160b4055674d..197420d581064 100644 --- a/llvm/test/CodeGen/RISCV/alu64.ll +++ b/llvm/test/CodeGen/RISCV/alu64.ll @@ -431,6 +431,23 @@ define signext i32 @sraiw(i32 %a) nounwind { ret i32 %1 } +define i64 @sraiw_i64(i64 %a) nounwind { +; RV64I-LABEL: sraiw_i64: +; RV64I: # %bb.0: +; RV64I-NEXT: sraiw a0, a0, 9 +; RV64I-NEXT: ret +; +; RV32I-LABEL: sraiw_i64: +; RV32I: # %bb.0: +; RV32I-NEXT: srai a2, a0, 9 +; RV32I-NEXT: srai a1, a0, 31 +; RV32I-NEXT: mv a0, a2 +; RV32I-NEXT: ret + %1 = shl i64 %a, 32 + %2 = ashr i64 %1, 41 + ret i64 %2 +} + define signext i32 @sextw(i32 zeroext %a) nounwind { ; RV64I-LABEL: sextw: ; RV64I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/byval.ll b/llvm/test/CodeGen/RISCV/byval.ll index 832dfb2e8a2f0..99e6abf23b882 100644 --- a/llvm/test/CodeGen/RISCV/byval.ll +++ b/llvm/test/CodeGen/RISCV/byval.ll @@ -5,7 +5,7 @@ %struct.Foo = type { i32, i32, i32, i16, i8 } @foo = global %struct.Foo { i32 1, i32 2, i32 3, i16 4, i8 5 }, align 4 -define i32 @callee(%struct.Foo* byval %f) nounwind { +define i32 @callee(%struct.Foo* byval(%struct.Foo) %f) nounwind { ; RV32I-LABEL: callee: ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: lw a0, 0(a0) @@ -38,6 +38,6 @@ define void @caller() nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret entry: - %call = call i32 @callee(%struct.Foo* byval @foo) + %call = call i32 @callee(%struct.Foo* byval(%struct.Foo) @foo) ret void } diff --git a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll index 3e7945887f4d1..150d786f4c3b6 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll @@ -521,7 +521,7 @@ define i32 @caller_small_coerced_struct() nounwind { %struct.large = type { i32, i32, i32, i32 } -define i32 @callee_large_struct(%struct.large* byval align 4 %a) nounwind { +define i32 @callee_large_struct(%struct.large* byval(%struct.large) align 4 %a) nounwind { ; RV32I-FPELIM-LABEL: callee_large_struct: ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: lw a1, 0(a0) @@ -607,7 +607,7 @@ define i32 @caller_large_struct() nounwind { store i32 3, i32* %c %d = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 3 store i32 4, i32* %d - %2 = call i32 @callee_large_struct(%struct.large* byval align 4 %ls) + %2 = call i32 @callee_large_struct(%struct.large* byval(%struct.large) align 4 %ls) ret i32 %2 } @@ -939,7 +939,7 @@ define void @caller_large_scalar_ret() nounwind { ; Check return of >2x xlen structs -define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind { +define void @callee_large_struct_ret(%struct.large* noalias sret(%struct.large) %agg.result) nounwind { ; RV32I-FPELIM-LABEL: callee_large_struct_ret: ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi a1, zero, 1 @@ -1011,7 +1011,7 @@ define i32 @caller_large_struct_ret() nounwind { ; RV32I-WITHFP-NEXT: addi sp, sp, 32 ; RV32I-WITHFP-NEXT: ret %1 = alloca %struct.large - call void @callee_large_struct_ret(%struct.large* sret %1) + call void @callee_large_struct_ret(%struct.large* sret(%struct.large) %1) %2 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 0 %3 = load i32, i32* %2 %4 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 3 diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll index fac227f4978c4..175abe20bdea5 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll @@ -274,7 +274,7 @@ define i64 @caller_small_coerced_struct() nounwind { %struct.large = type { i64, i64, i64, i64 } -define i64 @callee_large_struct(%struct.large* byval align 8 %a) nounwind { +define i64 @callee_large_struct(%struct.large* byval(%struct.large) align 8 %a) nounwind { ; RV64I-LABEL: callee_large_struct: ; RV64I: # %bb.0: ; RV64I-NEXT: ld a1, 0(a0) @@ -321,7 +321,7 @@ define i64 @caller_large_struct() nounwind { store i64 3, i64* %c %d = getelementptr inbounds %struct.large, %struct.large* %ls, i64 0, i32 3 store i64 4, i64* %d - %2 = call i64 @callee_large_struct(%struct.large* byval align 8 %ls) + %2 = call i64 @callee_large_struct(%struct.large* byval(%struct.large) align 8 %ls) ret i64 %2 } @@ -479,7 +479,7 @@ define void @caller_large_scalar_ret() nounwind { ; Check return of >2x xlen structs -define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind { +define void @callee_large_struct_ret(%struct.large* noalias sret(%struct.large) %agg.result) nounwind { ; RV64I-LABEL: callee_large_struct_ret: ; RV64I: # %bb.0: ; RV64I-NEXT: sw zero, 4(a0) @@ -520,7 +520,7 @@ define i64 @caller_large_struct_ret() nounwind { ; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: ret %1 = alloca %struct.large - call void @callee_large_struct_ret(%struct.large* sret %1) + call void @callee_large_struct_ret(%struct.large* sret(%struct.large) %1) %2 = getelementptr inbounds %struct.large, %struct.large* %1, i64 0, i32 0 %3 = load i64, i64* %2 %4 = getelementptr inbounds %struct.large, %struct.large* %1, i64 0, i32 3 diff --git a/llvm/test/CodeGen/RISCV/double-arith.ll b/llvm/test/CodeGen/RISCV/double-arith.ll index 7c5f4393ef34b..e33d2e4736587 100644 --- a/llvm/test/CodeGen/RISCV/double-arith.ll +++ b/llvm/test/CodeGen/RISCV/double-arith.ll @@ -543,7 +543,7 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind { ; RV32IFD-NEXT: fcvt.d.w ft3, zero ; RV32IFD-NEXT: fadd.d ft2, ft2, ft3 ; RV32IFD-NEXT: fadd.d ft1, ft1, ft3 -; RV32IFD-NEXT: fnmadd.d ft0, ft0, ft2, ft1 +; RV32IFD-NEXT: fnmadd.d ft0, ft2, ft0, ft1 ; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a1, 12(sp) @@ -558,7 +558,7 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind { ; RV64IFD-NEXT: fmv.d.x ft3, zero ; RV64IFD-NEXT: fadd.d ft2, ft2, ft3 ; RV64IFD-NEXT: fadd.d ft1, ft1, ft3 -; RV64IFD-NEXT: fnmadd.d ft0, ft0, ft2, ft1 +; RV64IFD-NEXT: fnmadd.d ft0, ft2, ft0, ft1 ; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: ret %b_ = fadd double 0.0, %b @@ -622,7 +622,7 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind { ; RV32IFD-NEXT: fld ft2, 8(sp) ; RV32IFD-NEXT: fcvt.d.w ft3, zero ; RV32IFD-NEXT: fadd.d ft2, ft2, ft3 -; RV32IFD-NEXT: fnmsub.d ft0, ft1, ft2, ft0 +; RV32IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0 ; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a1, 12(sp) @@ -636,7 +636,7 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind { ; RV64IFD-NEXT: fmv.d.x ft2, a1 ; RV64IFD-NEXT: fmv.d.x ft3, zero ; RV64IFD-NEXT: fadd.d ft2, ft2, ft3 -; RV64IFD-NEXT: fnmsub.d ft0, ft1, ft2, ft0 +; RV64IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: ret %b_ = fadd double 0.0, %b @@ -644,3 +644,160 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind { %1 = call double @llvm.fma.f64(double %a, double %negb, double %c) ret double %1 } + +define double @fmadd_d_contract(double %a, double %b, double %c) nounwind { +; RV32IFD-LABEL: fmadd_d_contract: +; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw a4, 8(sp) +; RV32IFD-NEXT: sw a5, 12(sp) +; RV32IFD-NEXT: fld ft0, 8(sp) +; RV32IFD-NEXT: sw a2, 8(sp) +; RV32IFD-NEXT: sw a3, 12(sp) +; RV32IFD-NEXT: fld ft1, 8(sp) +; RV32IFD-NEXT: sw a0, 8(sp) +; RV32IFD-NEXT: sw a1, 12(sp) +; RV32IFD-NEXT: fld ft2, 8(sp) +; RV32IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0 +; RV32IFD-NEXT: fsd ft0, 8(sp) +; RV32IFD-NEXT: lw a0, 8(sp) +; RV32IFD-NEXT: lw a1, 12(sp) +; RV32IFD-NEXT: addi sp, sp, 16 +; RV32IFD-NEXT: ret +; +; RV64IFD-LABEL: fmadd_d_contract: +; RV64IFD: # %bb.0: +; RV64IFD-NEXT: fmv.d.x ft0, a2 +; RV64IFD-NEXT: fmv.d.x ft1, a1 +; RV64IFD-NEXT: fmv.d.x ft2, a0 +; RV64IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0 +; RV64IFD-NEXT: fmv.x.d a0, ft0 +; RV64IFD-NEXT: ret + %1 = fmul contract double %a, %b + %2 = fadd contract double %1, %c + ret double %2 +} + +define double @fmsub_d_contract(double %a, double %b, double %c) nounwind { +; RV32IFD-LABEL: fmsub_d_contract: +; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw a2, 8(sp) +; RV32IFD-NEXT: sw a3, 12(sp) +; RV32IFD-NEXT: fld ft0, 8(sp) +; RV32IFD-NEXT: sw a0, 8(sp) +; RV32IFD-NEXT: sw a1, 12(sp) +; RV32IFD-NEXT: fld ft1, 8(sp) +; RV32IFD-NEXT: sw a4, 8(sp) +; RV32IFD-NEXT: sw a5, 12(sp) +; RV32IFD-NEXT: fld ft2, 8(sp) +; RV32IFD-NEXT: fcvt.d.w ft3, zero +; RV32IFD-NEXT: fadd.d ft2, ft2, ft3 +; RV32IFD-NEXT: fmsub.d ft0, ft1, ft0, ft2 +; RV32IFD-NEXT: fsd ft0, 8(sp) +; RV32IFD-NEXT: lw a0, 8(sp) +; RV32IFD-NEXT: lw a1, 12(sp) +; RV32IFD-NEXT: addi sp, sp, 16 +; RV32IFD-NEXT: ret +; +; RV64IFD-LABEL: fmsub_d_contract: +; RV64IFD: # %bb.0: +; RV64IFD-NEXT: fmv.d.x ft0, a1 +; RV64IFD-NEXT: fmv.d.x ft1, a0 +; RV64IFD-NEXT: fmv.d.x ft2, a2 +; RV64IFD-NEXT: fmv.d.x ft3, zero +; RV64IFD-NEXT: fadd.d ft2, ft2, ft3 +; RV64IFD-NEXT: fmsub.d ft0, ft1, ft0, ft2 +; RV64IFD-NEXT: fmv.x.d a0, ft0 +; RV64IFD-NEXT: ret + %c_ = fadd double 0.0, %c ; avoid negation using xor + %1 = fmul contract double %a, %b + %2 = fsub contract double %1, %c_ + ret double %2 +} + +define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind { +; RV32IFD-LABEL: fnmadd_d_contract: +; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw a4, 8(sp) +; RV32IFD-NEXT: sw a5, 12(sp) +; RV32IFD-NEXT: fld ft0, 8(sp) +; RV32IFD-NEXT: sw a2, 8(sp) +; RV32IFD-NEXT: sw a3, 12(sp) +; RV32IFD-NEXT: fld ft1, 8(sp) +; RV32IFD-NEXT: sw a0, 8(sp) +; RV32IFD-NEXT: sw a1, 12(sp) +; RV32IFD-NEXT: fld ft2, 8(sp) +; RV32IFD-NEXT: fcvt.d.w ft3, zero +; RV32IFD-NEXT: fadd.d ft2, ft2, ft3 +; RV32IFD-NEXT: fadd.d ft1, ft1, ft3 +; RV32IFD-NEXT: fadd.d ft0, ft0, ft3 +; RV32IFD-NEXT: fnmadd.d ft0, ft2, ft1, ft0 +; RV32IFD-NEXT: fsd ft0, 8(sp) +; RV32IFD-NEXT: lw a0, 8(sp) +; RV32IFD-NEXT: lw a1, 12(sp) +; RV32IFD-NEXT: addi sp, sp, 16 +; RV32IFD-NEXT: ret +; +; RV64IFD-LABEL: fnmadd_d_contract: +; RV64IFD: # %bb.0: +; RV64IFD-NEXT: fmv.d.x ft0, a2 +; RV64IFD-NEXT: fmv.d.x ft1, a1 +; RV64IFD-NEXT: fmv.d.x ft2, a0 +; RV64IFD-NEXT: fmv.d.x ft3, zero +; RV64IFD-NEXT: fadd.d ft2, ft2, ft3 +; RV64IFD-NEXT: fadd.d ft1, ft1, ft3 +; RV64IFD-NEXT: fadd.d ft0, ft0, ft3 +; RV64IFD-NEXT: fnmadd.d ft0, ft2, ft1, ft0 +; RV64IFD-NEXT: fmv.x.d a0, ft0 +; RV64IFD-NEXT: ret + %a_ = fadd double 0.0, %a ; avoid negation using xor + %b_ = fadd double 0.0, %b ; avoid negation using xor + %c_ = fadd double 0.0, %c ; avoid negation using xor + %1 = fmul contract double %a_, %b_ + %2 = fneg double %1 + %3 = fsub contract double %2, %c_ + ret double %3 +} + +define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind { +; RV32IFD-LABEL: fnmsub_d_contract: +; RV32IFD: # %bb.0: +; RV32IFD-NEXT: addi sp, sp, -16 +; RV32IFD-NEXT: sw a4, 8(sp) +; RV32IFD-NEXT: sw a5, 12(sp) +; RV32IFD-NEXT: fld ft0, 8(sp) +; RV32IFD-NEXT: sw a2, 8(sp) +; RV32IFD-NEXT: sw a3, 12(sp) +; RV32IFD-NEXT: fld ft1, 8(sp) +; RV32IFD-NEXT: sw a0, 8(sp) +; RV32IFD-NEXT: sw a1, 12(sp) +; RV32IFD-NEXT: fld ft2, 8(sp) +; RV32IFD-NEXT: fcvt.d.w ft3, zero +; RV32IFD-NEXT: fadd.d ft2, ft2, ft3 +; RV32IFD-NEXT: fadd.d ft1, ft1, ft3 +; RV32IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0 +; RV32IFD-NEXT: fsd ft0, 8(sp) +; RV32IFD-NEXT: lw a0, 8(sp) +; RV32IFD-NEXT: lw a1, 12(sp) +; RV32IFD-NEXT: addi sp, sp, 16 +; RV32IFD-NEXT: ret +; +; RV64IFD-LABEL: fnmsub_d_contract: +; RV64IFD: # %bb.0: +; RV64IFD-NEXT: fmv.d.x ft0, a2 +; RV64IFD-NEXT: fmv.d.x ft1, a1 +; RV64IFD-NEXT: fmv.d.x ft2, a0 +; RV64IFD-NEXT: fmv.d.x ft3, zero +; RV64IFD-NEXT: fadd.d ft2, ft2, ft3 +; RV64IFD-NEXT: fadd.d ft1, ft1, ft3 +; RV64IFD-NEXT: fnmsub.d ft0, ft2, ft1, ft0 +; RV64IFD-NEXT: fmv.x.d a0, ft0 +; RV64IFD-NEXT: ret + %a_ = fadd double 0.0, %a ; avoid negation using xor + %b_ = fadd double 0.0, %b ; avoid negation using xor + %1 = fmul contract double %a_, %b_ + %2 = fsub contract double %c, %1 + ret double %2 +} diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll index b8873883cd586..4126c01cb637e 100644 --- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll @@ -341,7 +341,6 @@ define double @fma_f64(double %a, double %b, double %c) nounwind { declare double @llvm.fmuladd.f64(double, double, double) define double @fmuladd_f64(double %a, double %b, double %c) nounwind { -; Use of fmadd depends on TargetLowering::isFMAFasterthanFMulAndFAdd ; RV32IFD-LABEL: fmuladd_f64: ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 @@ -354,8 +353,7 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind { ; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: fld ft2, 8(sp) -; RV32IFD-NEXT: fmul.d ft1, ft2, ft1 -; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 +; RV32IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0 ; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a1, 12(sp) @@ -367,8 +365,7 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind { ; RV64IFD-NEXT: fmv.d.x ft0, a2 ; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft2, a0 -; RV64IFD-NEXT: fmul.d ft1, ft2, ft1 -; RV64IFD-NEXT: fadd.d ft0, ft1, ft0 +; RV64IFD-NEXT: fmadd.d ft0, ft2, ft1, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: ret %1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c) diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll index f665975ab4f14..d302dd5ebc0ac 100644 --- a/llvm/test/CodeGen/RISCV/float-arith.ll +++ b/llvm/test/CodeGen/RISCV/float-arith.ll @@ -405,7 +405,7 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind { ; RV32IF-NEXT: fmv.w.x ft3, zero ; RV32IF-NEXT: fadd.s ft2, ft2, ft3 ; RV32IF-NEXT: fadd.s ft1, ft1, ft3 -; RV32IF-NEXT: fnmadd.s ft0, ft0, ft2, ft1 +; RV32IF-NEXT: fnmadd.s ft0, ft2, ft0, ft1 ; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: ret ; @@ -417,7 +417,7 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind { ; RV64IF-NEXT: fmv.w.x ft3, zero ; RV64IF-NEXT: fadd.s ft2, ft2, ft3 ; RV64IF-NEXT: fadd.s ft1, ft1, ft3 -; RV64IF-NEXT: fnmadd.s ft0, ft0, ft2, ft1 +; RV64IF-NEXT: fnmadd.s ft0, ft2, ft0, ft1 ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret %b_ = fadd float 0.0, %b @@ -464,7 +464,7 @@ define float @fnmsub_s_2(float %a, float %b, float %c) nounwind { ; RV32IF-NEXT: fmv.w.x ft2, a1 ; RV32IF-NEXT: fmv.w.x ft3, zero ; RV32IF-NEXT: fadd.s ft2, ft2, ft3 -; RV32IF-NEXT: fnmsub.s ft0, ft1, ft2, ft0 +; RV32IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: ret ; @@ -475,7 +475,7 @@ define float @fnmsub_s_2(float %a, float %b, float %c) nounwind { ; RV64IF-NEXT: fmv.w.x ft2, a1 ; RV64IF-NEXT: fmv.w.x ft3, zero ; RV64IF-NEXT: fadd.s ft2, ft2, ft3 -; RV64IF-NEXT: fnmsub.s ft0, ft1, ft2, ft0 +; RV64IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret %b_ = fadd float 0.0, %b @@ -483,3 +483,120 @@ define float @fnmsub_s_2(float %a, float %b, float %c) nounwind { %1 = call float @llvm.fma.f32(float %a, float %negb, float %c) ret float %1 } + +define float @fmadd_s_contract(float %a, float %b, float %c) nounwind { +; RV32IF-LABEL: fmadd_s_contract: +; RV32IF: # %bb.0: +; RV32IF-NEXT: fmv.w.x ft0, a2 +; RV32IF-NEXT: fmv.w.x ft1, a1 +; RV32IF-NEXT: fmv.w.x ft2, a0 +; RV32IF-NEXT: fmadd.s ft0, ft2, ft1, ft0 +; RV32IF-NEXT: fmv.x.w a0, ft0 +; RV32IF-NEXT: ret +; +; RV64IF-LABEL: fmadd_s_contract: +; RV64IF: # %bb.0: +; RV64IF-NEXT: fmv.w.x ft0, a2 +; RV64IF-NEXT: fmv.w.x ft1, a1 +; RV64IF-NEXT: fmv.w.x ft2, a0 +; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0 +; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: ret + %1 = fmul contract float %a, %b + %2 = fadd contract float %1, %c + ret float %2 +} + +define float @fmsub_s_contract(float %a, float %b, float %c) nounwind { +; RV32IF-LABEL: fmsub_s_contract: +; RV32IF: # %bb.0: +; RV32IF-NEXT: fmv.w.x ft0, a1 +; RV32IF-NEXT: fmv.w.x ft1, a0 +; RV32IF-NEXT: fmv.w.x ft2, a2 +; RV32IF-NEXT: fmv.w.x ft3, zero +; RV32IF-NEXT: fadd.s ft2, ft2, ft3 +; RV32IF-NEXT: fmsub.s ft0, ft1, ft0, ft2 +; RV32IF-NEXT: fmv.x.w a0, ft0 +; RV32IF-NEXT: ret +; +; RV64IF-LABEL: fmsub_s_contract: +; RV64IF: # %bb.0: +; RV64IF-NEXT: fmv.w.x ft0, a1 +; RV64IF-NEXT: fmv.w.x ft1, a0 +; RV64IF-NEXT: fmv.w.x ft2, a2 +; RV64IF-NEXT: fmv.w.x ft3, zero +; RV64IF-NEXT: fadd.s ft2, ft2, ft3 +; RV64IF-NEXT: fmsub.s ft0, ft1, ft0, ft2 +; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: ret + %c_ = fadd float 0.0, %c ; avoid negation using xor + %1 = fmul contract float %a, %b + %2 = fsub contract float %1, %c_ + ret float %2 +} + +define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind { +; RV32IF-LABEL: fnmadd_s_contract: +; RV32IF: # %bb.0: +; RV32IF-NEXT: fmv.w.x ft0, a2 +; RV32IF-NEXT: fmv.w.x ft1, a1 +; RV32IF-NEXT: fmv.w.x ft2, a0 +; RV32IF-NEXT: fmv.w.x ft3, zero +; RV32IF-NEXT: fadd.s ft2, ft2, ft3 +; RV32IF-NEXT: fadd.s ft1, ft1, ft3 +; RV32IF-NEXT: fadd.s ft0, ft0, ft3 +; RV32IF-NEXT: fnmadd.s ft0, ft2, ft1, ft0 +; RV32IF-NEXT: fmv.x.w a0, ft0 +; RV32IF-NEXT: ret +; +; RV64IF-LABEL: fnmadd_s_contract: +; RV64IF: # %bb.0: +; RV64IF-NEXT: fmv.w.x ft0, a2 +; RV64IF-NEXT: fmv.w.x ft1, a1 +; RV64IF-NEXT: fmv.w.x ft2, a0 +; RV64IF-NEXT: fmv.w.x ft3, zero +; RV64IF-NEXT: fadd.s ft2, ft2, ft3 +; RV64IF-NEXT: fadd.s ft1, ft1, ft3 +; RV64IF-NEXT: fadd.s ft0, ft0, ft3 +; RV64IF-NEXT: fnmadd.s ft0, ft2, ft1, ft0 +; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: ret + %a_ = fadd float 0.0, %a ; avoid negation using xor + %b_ = fadd float 0.0, %b ; avoid negation using xor + %c_ = fadd float 0.0, %c ; avoid negation using xor + %1 = fmul contract float %a_, %b_ + %2 = fneg float %1 + %3 = fsub contract float %2, %c_ + ret float %3 +} + +define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind { +; RV32IF-LABEL: fnmsub_s_contract: +; RV32IF: # %bb.0: +; RV32IF-NEXT: fmv.w.x ft0, a2 +; RV32IF-NEXT: fmv.w.x ft1, a1 +; RV32IF-NEXT: fmv.w.x ft2, a0 +; RV32IF-NEXT: fmv.w.x ft3, zero +; RV32IF-NEXT: fadd.s ft2, ft2, ft3 +; RV32IF-NEXT: fadd.s ft1, ft1, ft3 +; RV32IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0 +; RV32IF-NEXT: fmv.x.w a0, ft0 +; RV32IF-NEXT: ret +; +; RV64IF-LABEL: fnmsub_s_contract: +; RV64IF: # %bb.0: +; RV64IF-NEXT: fmv.w.x ft0, a2 +; RV64IF-NEXT: fmv.w.x ft1, a1 +; RV64IF-NEXT: fmv.w.x ft2, a0 +; RV64IF-NEXT: fmv.w.x ft3, zero +; RV64IF-NEXT: fadd.s ft2, ft2, ft3 +; RV64IF-NEXT: fadd.s ft1, ft1, ft3 +; RV64IF-NEXT: fnmsub.s ft0, ft2, ft1, ft0 +; RV64IF-NEXT: fmv.x.w a0, ft0 +; RV64IF-NEXT: ret + %a_ = fadd float 0.0, %a ; avoid negation using xor + %b_ = fadd float 0.0, %b ; avoid negation using xor + %1 = fmul contract float %a_, %b_ + %2 = fsub contract float %c, %1 + ret float %2 +} diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll index 68bb95b634877..85d1564d1a993 100644 --- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll @@ -319,14 +319,12 @@ define float @fma_f32(float %a, float %b, float %c) nounwind { declare float @llvm.fmuladd.f32(float, float, float) define float @fmuladd_f32(float %a, float %b, float %c) nounwind { -; Use of fmadd depends on TargetLowering::isFMAFasterthanFMulAndFAdd ; RV32IF-LABEL: fmuladd_f32: ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.w.x ft0, a2 ; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft2, a0 -; RV32IF-NEXT: fmul.s ft1, ft2, ft1 -; RV32IF-NEXT: fadd.s ft0, ft1, ft0 +; RV32IF-NEXT: fmadd.s ft0, ft2, ft1, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: ret ; @@ -335,8 +333,7 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind { ; RV64IF-NEXT: fmv.w.x ft0, a2 ; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft2, a0 -; RV64IF-NEXT: fmul.s ft1, ft2, ft1 -; RV64IF-NEXT: fadd.s ft0, ft1, ft0 +; RV64IF-NEXT: fmadd.s ft0, ft2, ft1, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret %1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c) diff --git a/llvm/test/CodeGen/RISCV/ghccc-rv32.ll b/llvm/test/CodeGen/RISCV/ghccc-rv32.ll new file mode 100644 index 0000000000000..1d7b05ba3b9a8 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/ghccc-rv32.ll @@ -0,0 +1,114 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+f,+d < %s | FileCheck %s + +; Check the GHC call convention works (rv32) + +@base = external global i32 ; assigned to register: s1 +@sp = external global i32 ; assigned to register: s2 +@hp = external global i32 ; assigned to register: s3 +@r1 = external global i32 ; assigned to register: s4 +@r2 = external global i32 ; assigned to register: s5 +@r3 = external global i32 ; assigned to register: s6 +@r4 = external global i32 ; assigned to register: s7 +@r5 = external global i32 ; assigned to register: s8 +@r6 = external global i32 ; assigned to register: s9 +@r7 = external global i32 ; assigned to register: s10 +@splim = external global i32 ; assigned to register: s11 + +@f1 = external global float ; assigned to register: fs0 +@f2 = external global float ; assigned to register: fs1 +@f3 = external global float ; assigned to register: fs2 +@f4 = external global float ; assigned to register: fs3 +@f5 = external global float ; assigned to register: fs4 +@f6 = external global float ; assigned to register: fs5 + +@d1 = external global double ; assigned to register: fs6 +@d2 = external global double ; assigned to register: fs7 +@d3 = external global double ; assigned to register: fs8 +@d4 = external global double ; assigned to register: fs9 +@d5 = external global double ; assigned to register: fs10 +@d6 = external global double ; assigned to register: fs11 + +define ghccc void @foo() nounwind { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lui a0, %hi(d6) +; CHECK-NEXT: fld fs11, %lo(d6)(a0) +; CHECK-NEXT: lui a0, %hi(d5) +; CHECK-NEXT: fld fs10, %lo(d5)(a0) +; CHECK-NEXT: lui a0, %hi(d4) +; CHECK-NEXT: fld fs9, %lo(d4)(a0) +; CHECK-NEXT: lui a0, %hi(d3) +; CHECK-NEXT: fld fs8, %lo(d3)(a0) +; CHECK-NEXT: lui a0, %hi(d2) +; CHECK-NEXT: fld fs7, %lo(d2)(a0) +; CHECK-NEXT: lui a0, %hi(d1) +; CHECK-NEXT: fld fs6, %lo(d1)(a0) +; CHECK-NEXT: lui a0, %hi(f6) +; CHECK-NEXT: flw fs5, %lo(f6)(a0) +; CHECK-NEXT: lui a0, %hi(f5) +; CHECK-NEXT: flw fs4, %lo(f5)(a0) +; CHECK-NEXT: lui a0, %hi(f4) +; CHECK-NEXT: flw fs3, %lo(f4)(a0) +; CHECK-NEXT: lui a0, %hi(f3) +; CHECK-NEXT: flw fs2, %lo(f3)(a0) +; CHECK-NEXT: lui a0, %hi(f2) +; CHECK-NEXT: flw fs1, %lo(f2)(a0) +; CHECK-NEXT: lui a0, %hi(f1) +; CHECK-NEXT: flw fs0, %lo(f1)(a0) +; CHECK-NEXT: lui a0, %hi(splim) +; CHECK-NEXT: lw s11, %lo(splim)(a0) +; CHECK-NEXT: lui a0, %hi(r7) +; CHECK-NEXT: lw s10, %lo(r7)(a0) +; CHECK-NEXT: lui a0, %hi(r6) +; CHECK-NEXT: lw s9, %lo(r6)(a0) +; CHECK-NEXT: lui a0, %hi(r5) +; CHECK-NEXT: lw s8, %lo(r5)(a0) +; CHECK-NEXT: lui a0, %hi(r4) +; CHECK-NEXT: lw s7, %lo(r4)(a0) +; CHECK-NEXT: lui a0, %hi(r3) +; CHECK-NEXT: lw s6, %lo(r3)(a0) +; CHECK-NEXT: lui a0, %hi(r2) +; CHECK-NEXT: lw s5, %lo(r2)(a0) +; CHECK-NEXT: lui a0, %hi(r1) +; CHECK-NEXT: lw s4, %lo(r1)(a0) +; CHECK-NEXT: lui a0, %hi(hp) +; CHECK-NEXT: lw s3, %lo(hp)(a0) +; CHECK-NEXT: lui a0, %hi(sp) +; CHECK-NEXT: lw s2, %lo(sp)(a0) +; CHECK-NEXT: lui a0, %hi(base) +; CHECK-NEXT: lw s1, %lo(base)(a0) +; CHECK-NEXT: tail bar +entry: + %0 = load double, double* @d6 + %1 = load double, double* @d5 + %2 = load double, double* @d4 + %3 = load double, double* @d3 + %4 = load double, double* @d2 + %5 = load double, double* @d1 + %6 = load float, float* @f6 + %7 = load float, float* @f5 + %8 = load float, float* @f4 + %9 = load float, float* @f3 + %10 = load float, float* @f2 + %11 = load float, float* @f1 + %12 = load i32, i32* @splim + %13 = load i32, i32* @r7 + %14 = load i32, i32* @r6 + %15 = load i32, i32* @r5 + %16 = load i32, i32* @r4 + %17 = load i32, i32* @r3 + %18 = load i32, i32* @r2 + %19 = load i32, i32* @r1 + %20 = load i32, i32* @hp + %21 = load i32, i32* @sp + %22 = load i32, i32* @base + tail call ghccc void @bar(i32 %22, i32 %21, i32 %20, i32 %19, i32 %18, i32 %17, i32 %16, i32 %15, i32 %14, i32 %13, i32 %12, + float %11, float %10, float %9, float %8, float %7, float %6, + double %5, double %4, double %3, double %2, double %1, double %0) nounwind + ret void +} + +declare ghccc void @bar(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, + float, float, float, float, float, float, + double, double, double, double, double, double) diff --git a/llvm/test/CodeGen/RISCV/ghccc-rv64.ll b/llvm/test/CodeGen/RISCV/ghccc-rv64.ll new file mode 100644 index 0000000000000..aaca2e102a796 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/ghccc-rv64.ll @@ -0,0 +1,114 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+f,+d < %s | FileCheck %s + +; Check the GHC call convention works (rv64) + +@base = external global i64 ; assigned to register: s1 +@sp = external global i64 ; assigned to register: s2 +@hp = external global i64 ; assigned to register: s3 +@r1 = external global i64 ; assigned to register: s4 +@r2 = external global i64 ; assigned to register: s5 +@r3 = external global i64 ; assigned to register: s6 +@r4 = external global i64 ; assigned to register: s7 +@r5 = external global i64 ; assigned to register: s8 +@r6 = external global i64 ; assigned to register: s9 +@r7 = external global i64 ; assigned to register: s10 +@splim = external global i64 ; assigned to register: s11 + +@f1 = external global float ; assigned to register: fs0 +@f2 = external global float ; assigned to register: fs1 +@f3 = external global float ; assigned to register: fs2 +@f4 = external global float ; assigned to register: fs3 +@f5 = external global float ; assigned to register: fs4 +@f6 = external global float ; assigned to register: fs5 + +@d1 = external global double ; assigned to register: fs6 +@d2 = external global double ; assigned to register: fs7 +@d3 = external global double ; assigned to register: fs8 +@d4 = external global double ; assigned to register: fs9 +@d5 = external global double ; assigned to register: fs10 +@d6 = external global double ; assigned to register: fs11 + +define ghccc void @foo() nounwind { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lui a0, %hi(d6) +; CHECK-NEXT: fld fs11, %lo(d6)(a0) +; CHECK-NEXT: lui a0, %hi(d5) +; CHECK-NEXT: fld fs10, %lo(d5)(a0) +; CHECK-NEXT: lui a0, %hi(d4) +; CHECK-NEXT: fld fs9, %lo(d4)(a0) +; CHECK-NEXT: lui a0, %hi(d3) +; CHECK-NEXT: fld fs8, %lo(d3)(a0) +; CHECK-NEXT: lui a0, %hi(d2) +; CHECK-NEXT: fld fs7, %lo(d2)(a0) +; CHECK-NEXT: lui a0, %hi(d1) +; CHECK-NEXT: fld fs6, %lo(d1)(a0) +; CHECK-NEXT: lui a0, %hi(f6) +; CHECK-NEXT: flw fs5, %lo(f6)(a0) +; CHECK-NEXT: lui a0, %hi(f5) +; CHECK-NEXT: flw fs4, %lo(f5)(a0) +; CHECK-NEXT: lui a0, %hi(f4) +; CHECK-NEXT: flw fs3, %lo(f4)(a0) +; CHECK-NEXT: lui a0, %hi(f3) +; CHECK-NEXT: flw fs2, %lo(f3)(a0) +; CHECK-NEXT: lui a0, %hi(f2) +; CHECK-NEXT: flw fs1, %lo(f2)(a0) +; CHECK-NEXT: lui a0, %hi(f1) +; CHECK-NEXT: flw fs0, %lo(f1)(a0) +; CHECK-NEXT: lui a0, %hi(splim) +; CHECK-NEXT: ld s11, %lo(splim)(a0) +; CHECK-NEXT: lui a0, %hi(r7) +; CHECK-NEXT: ld s10, %lo(r7)(a0) +; CHECK-NEXT: lui a0, %hi(r6) +; CHECK-NEXT: ld s9, %lo(r6)(a0) +; CHECK-NEXT: lui a0, %hi(r5) +; CHECK-NEXT: ld s8, %lo(r5)(a0) +; CHECK-NEXT: lui a0, %hi(r4) +; CHECK-NEXT: ld s7, %lo(r4)(a0) +; CHECK-NEXT: lui a0, %hi(r3) +; CHECK-NEXT: ld s6, %lo(r3)(a0) +; CHECK-NEXT: lui a0, %hi(r2) +; CHECK-NEXT: ld s5, %lo(r2)(a0) +; CHECK-NEXT: lui a0, %hi(r1) +; CHECK-NEXT: ld s4, %lo(r1)(a0) +; CHECK-NEXT: lui a0, %hi(hp) +; CHECK-NEXT: ld s3, %lo(hp)(a0) +; CHECK-NEXT: lui a0, %hi(sp) +; CHECK-NEXT: ld s2, %lo(sp)(a0) +; CHECK-NEXT: lui a0, %hi(base) +; CHECK-NEXT: ld s1, %lo(base)(a0) +; CHECK-NEXT: tail bar +entry: + %0 = load double, double* @d6 + %1 = load double, double* @d5 + %2 = load double, double* @d4 + %3 = load double, double* @d3 + %4 = load double, double* @d2 + %5 = load double, double* @d1 + %6 = load float, float* @f6 + %7 = load float, float* @f5 + %8 = load float, float* @f4 + %9 = load float, float* @f3 + %10 = load float, float* @f2 + %11 = load float, float* @f1 + %12 = load i64, i64* @splim + %13 = load i64, i64* @r7 + %14 = load i64, i64* @r6 + %15 = load i64, i64* @r5 + %16 = load i64, i64* @r4 + %17 = load i64, i64* @r3 + %18 = load i64, i64* @r2 + %19 = load i64, i64* @r1 + %20 = load i64, i64* @hp + %21 = load i64, i64* @sp + %22 = load i64, i64* @base + tail call ghccc void @bar(i64 %22, i64 %21, i64 %20, i64 %19, i64 %18, i64 %17, i64 %16, i64 %15, i64 %14, i64 %13, i64 %12, + float %11, float %10, float %9, float %8, float %7, float %6, + double %5, double %4, double %3, double %2, double %1, double %0) nounwind + ret void +} + +declare ghccc void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, + float, float, float, float, float, float, + double, double, double, double, double, double) diff --git a/llvm/test/CodeGen/RISCV/musttail-call.ll b/llvm/test/CodeGen/RISCV/musttail-call.ll index 37b0ab4569284..81d079c6c788a 100644 --- a/llvm/test/CodeGen/RISCV/musttail-call.ll +++ b/llvm/test/CodeGen/RISCV/musttail-call.ll @@ -11,10 +11,10 @@ %struct.A = type { i32 } -declare void @callee_musttail(%struct.A* sret %a) -define void @caller_musttail(%struct.A* sret %a) { +declare void @callee_musttail(%struct.A* sret(%struct.A) %a) +define void @caller_musttail(%struct.A* sret(%struct.A) %a) { ; CHECK: LLVM ERROR: failed to perform tail call elimination on a call site marked musttail entry: - musttail call void @callee_musttail(%struct.A* sret %a) + musttail call void @callee_musttail(%struct.A* sret(%struct.A) %a) ret void } diff --git a/llvm/test/CodeGen/RISCV/neg-abs.ll b/llvm/test/CodeGen/RISCV/neg-abs.ll index 9f56a2e777678..b5e5d2ae31490 100644 --- a/llvm/test/CodeGen/RISCV/neg-abs.ll +++ b/llvm/test/CodeGen/RISCV/neg-abs.ll @@ -9,48 +9,85 @@ define i32 @neg_abs32(i32 %x) { ; RV32-LABEL: neg_abs32: ; RV32: # %bb.0: ; RV32-NEXT: srai a1, a0, 31 -; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: xor a0, a0, a1 -; RV32-NEXT: neg a0, a0 +; RV32-NEXT: sub a0, a1, a0 ; RV32-NEXT: ret ; ; RV64-LABEL: neg_abs32: ; RV64: # %bb.0: -; RV64-NEXT: sext.w a1, a0 -; RV64-NEXT: srai a1, a1, 63 -; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: sraiw a1, a0, 31 ; RV64-NEXT: xor a0, a0, a1 -; RV64-NEXT: negw a0, a0 +; RV64-NEXT: subw a0, a1, a0 ; RV64-NEXT: ret %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) %neg = sub nsw i32 0, %abs ret i32 %neg } +define i32 @select_neg_abs32(i32 %x) { +; RV32-LABEL: select_neg_abs32: +; RV32: # %bb.0: +; RV32-NEXT: srai a1, a0, 31 +; RV32-NEXT: xor a0, a0, a1 +; RV32-NEXT: sub a0, a1, a0 +; RV32-NEXT: ret +; +; RV64-LABEL: select_neg_abs32: +; RV64: # %bb.0: +; RV64-NEXT: sraiw a1, a0, 31 +; RV64-NEXT: xor a0, a0, a1 +; RV64-NEXT: subw a0, a1, a0 +; RV64-NEXT: ret + %1 = icmp slt i32 %x, 0 + %2 = sub nsw i32 0, %x + %3 = select i1 %1, i32 %x, i32 %2 + ret i32 %3 +} + define i64 @neg_abs64(i64 %x) { ; RV32-LABEL: neg_abs64: ; RV32: # %bb.0: -; RV32-NEXT: bgez a1, .LBB1_2 -; RV32-NEXT: # %bb.1: -; RV32-NEXT: snez a2, a0 -; RV32-NEXT: add a1, a1, a2 -; RV32-NEXT: neg a1, a1 -; RV32-NEXT: neg a0, a0 -; RV32-NEXT: .LBB1_2: -; RV32-NEXT: snez a2, a0 -; RV32-NEXT: add a1, a1, a2 -; RV32-NEXT: neg a1, a1 -; RV32-NEXT: neg a0, a0 +; RV32-NEXT: srai a2, a1, 31 +; RV32-NEXT: xor a0, a0, a2 +; RV32-NEXT: sltu a3, a2, a0 +; RV32-NEXT: xor a1, a1, a2 +; RV32-NEXT: sub a1, a2, a1 +; RV32-NEXT: sub a1, a1, a3 +; RV32-NEXT: sub a0, a2, a0 ; RV32-NEXT: ret ; ; RV64-LABEL: neg_abs64: ; RV64: # %bb.0: ; RV64-NEXT: srai a1, a0, 63 -; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: xor a0, a0, a1 -; RV64-NEXT: neg a0, a0 +; RV64-NEXT: sub a0, a1, a0 ; RV64-NEXT: ret %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) %neg = sub nsw i64 0, %abs ret i64 %neg } + +define i64 @select_neg_abs64(i64 %x) { +; RV32-LABEL: select_neg_abs64: +; RV32: # %bb.0: +; RV32-NEXT: srai a2, a1, 31 +; RV32-NEXT: xor a0, a0, a2 +; RV32-NEXT: sltu a3, a2, a0 +; RV32-NEXT: xor a1, a1, a2 +; RV32-NEXT: sub a1, a2, a1 +; RV32-NEXT: sub a1, a1, a3 +; RV32-NEXT: sub a0, a2, a0 +; RV32-NEXT: ret +; +; RV64-LABEL: select_neg_abs64: +; RV64: # %bb.0: +; RV64-NEXT: srai a1, a0, 63 +; RV64-NEXT: xor a0, a0, a1 +; RV64-NEXT: sub a0, a1, a0 +; RV64-NEXT: ret + %1 = icmp slt i64 %x, 0 + %2 = sub nsw i64 0, %x + %3 = select i1 %1, i64 %x, i64 %2 + ret i64 %3 +} + diff --git a/llvm/test/CodeGen/RISCV/rv32Zbb.ll b/llvm/test/CodeGen/RISCV/rv32Zbb.ll index 8da1fe64c65fb..86ef499b18070 100644 --- a/llvm/test/CodeGen/RISCV/rv32Zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv32Zbb.ll @@ -910,34 +910,36 @@ define i64 @min_i64(i64 %a, i64 %b) nounwind { ; ; RV32IB-LABEL: min_i64: ; RV32IB: # %bb.0: -; RV32IB-NEXT: beq a1, a3, .LBB19_2 +; RV32IB-NEXT: mv a4, a0 +; RV32IB-NEXT: bge a1, a3, .LBB19_3 ; RV32IB-NEXT: # %bb.1: -; RV32IB-NEXT: slt a4, a1, a3 -; RV32IB-NEXT: beqz a4, .LBB19_3 -; RV32IB-NEXT: j .LBB19_4 +; RV32IB-NEXT: beq a1, a3, .LBB19_4 ; RV32IB-NEXT: .LBB19_2: -; RV32IB-NEXT: sltu a4, a0, a2 -; RV32IB-NEXT: bnez a4, .LBB19_4 +; RV32IB-NEXT: min a1, a1, a3 +; RV32IB-NEXT: ret ; RV32IB-NEXT: .LBB19_3: ; RV32IB-NEXT: mv a0, a2 -; RV32IB-NEXT: mv a1, a3 +; RV32IB-NEXT: bne a1, a3, .LBB19_2 ; RV32IB-NEXT: .LBB19_4: +; RV32IB-NEXT: minu a0, a4, a2 +; RV32IB-NEXT: min a1, a1, a3 ; RV32IB-NEXT: ret ; ; RV32IBB-LABEL: min_i64: ; RV32IBB: # %bb.0: -; RV32IBB-NEXT: beq a1, a3, .LBB19_2 +; RV32IBB-NEXT: mv a4, a0 +; RV32IBB-NEXT: bge a1, a3, .LBB19_3 ; RV32IBB-NEXT: # %bb.1: -; RV32IBB-NEXT: slt a4, a1, a3 -; RV32IBB-NEXT: beqz a4, .LBB19_3 -; RV32IBB-NEXT: j .LBB19_4 +; RV32IBB-NEXT: beq a1, a3, .LBB19_4 ; RV32IBB-NEXT: .LBB19_2: -; RV32IBB-NEXT: sltu a4, a0, a2 -; RV32IBB-NEXT: bnez a4, .LBB19_4 +; RV32IBB-NEXT: min a1, a1, a3 +; RV32IBB-NEXT: ret ; RV32IBB-NEXT: .LBB19_3: ; RV32IBB-NEXT: mv a0, a2 -; RV32IBB-NEXT: mv a1, a3 +; RV32IBB-NEXT: bne a1, a3, .LBB19_2 ; RV32IBB-NEXT: .LBB19_4: +; RV32IBB-NEXT: minu a0, a4, a2 +; RV32IBB-NEXT: min a1, a1, a3 ; RV32IBB-NEXT: ret %cmp = icmp slt i64 %a, %b %cond = select i1 %cmp, i64 %a, i64 %b @@ -991,34 +993,36 @@ define i64 @max_i64(i64 %a, i64 %b) nounwind { ; ; RV32IB-LABEL: max_i64: ; RV32IB: # %bb.0: -; RV32IB-NEXT: beq a1, a3, .LBB21_2 +; RV32IB-NEXT: mv a4, a0 +; RV32IB-NEXT: bge a3, a1, .LBB21_3 ; RV32IB-NEXT: # %bb.1: -; RV32IB-NEXT: slt a4, a3, a1 -; RV32IB-NEXT: beqz a4, .LBB21_3 -; RV32IB-NEXT: j .LBB21_4 +; RV32IB-NEXT: beq a1, a3, .LBB21_4 ; RV32IB-NEXT: .LBB21_2: -; RV32IB-NEXT: sltu a4, a2, a0 -; RV32IB-NEXT: bnez a4, .LBB21_4 +; RV32IB-NEXT: max a1, a1, a3 +; RV32IB-NEXT: ret ; RV32IB-NEXT: .LBB21_3: ; RV32IB-NEXT: mv a0, a2 -; RV32IB-NEXT: mv a1, a3 +; RV32IB-NEXT: bne a1, a3, .LBB21_2 ; RV32IB-NEXT: .LBB21_4: +; RV32IB-NEXT: maxu a0, a4, a2 +; RV32IB-NEXT: max a1, a1, a3 ; RV32IB-NEXT: ret ; ; RV32IBB-LABEL: max_i64: ; RV32IBB: # %bb.0: -; RV32IBB-NEXT: beq a1, a3, .LBB21_2 +; RV32IBB-NEXT: mv a4, a0 +; RV32IBB-NEXT: bge a3, a1, .LBB21_3 ; RV32IBB-NEXT: # %bb.1: -; RV32IBB-NEXT: slt a4, a3, a1 -; RV32IBB-NEXT: beqz a4, .LBB21_3 -; RV32IBB-NEXT: j .LBB21_4 +; RV32IBB-NEXT: beq a1, a3, .LBB21_4 ; RV32IBB-NEXT: .LBB21_2: -; RV32IBB-NEXT: sltu a4, a2, a0 -; RV32IBB-NEXT: bnez a4, .LBB21_4 +; RV32IBB-NEXT: max a1, a1, a3 +; RV32IBB-NEXT: ret ; RV32IBB-NEXT: .LBB21_3: ; RV32IBB-NEXT: mv a0, a2 -; RV32IBB-NEXT: mv a1, a3 +; RV32IBB-NEXT: bne a1, a3, .LBB21_2 ; RV32IBB-NEXT: .LBB21_4: +; RV32IBB-NEXT: maxu a0, a4, a2 +; RV32IBB-NEXT: max a1, a1, a3 ; RV32IBB-NEXT: ret %cmp = icmp sgt i64 %a, %b %cond = select i1 %cmp, i64 %a, i64 %b @@ -1072,34 +1076,36 @@ define i64 @minu_i64(i64 %a, i64 %b) nounwind { ; ; RV32IB-LABEL: minu_i64: ; RV32IB: # %bb.0: -; RV32IB-NEXT: beq a1, a3, .LBB23_2 +; RV32IB-NEXT: mv a4, a0 +; RV32IB-NEXT: bgeu a1, a3, .LBB23_3 ; RV32IB-NEXT: # %bb.1: -; RV32IB-NEXT: sltu a4, a1, a3 -; RV32IB-NEXT: beqz a4, .LBB23_3 -; RV32IB-NEXT: j .LBB23_4 +; RV32IB-NEXT: beq a1, a3, .LBB23_4 ; RV32IB-NEXT: .LBB23_2: -; RV32IB-NEXT: sltu a4, a0, a2 -; RV32IB-NEXT: bnez a4, .LBB23_4 +; RV32IB-NEXT: minu a1, a1, a3 +; RV32IB-NEXT: ret ; RV32IB-NEXT: .LBB23_3: ; RV32IB-NEXT: mv a0, a2 -; RV32IB-NEXT: mv a1, a3 +; RV32IB-NEXT: bne a1, a3, .LBB23_2 ; RV32IB-NEXT: .LBB23_4: +; RV32IB-NEXT: minu a0, a4, a2 +; RV32IB-NEXT: minu a1, a1, a3 ; RV32IB-NEXT: ret ; ; RV32IBB-LABEL: minu_i64: ; RV32IBB: # %bb.0: -; RV32IBB-NEXT: beq a1, a3, .LBB23_2 +; RV32IBB-NEXT: mv a4, a0 +; RV32IBB-NEXT: bgeu a1, a3, .LBB23_3 ; RV32IBB-NEXT: # %bb.1: -; RV32IBB-NEXT: sltu a4, a1, a3 -; RV32IBB-NEXT: beqz a4, .LBB23_3 -; RV32IBB-NEXT: j .LBB23_4 +; RV32IBB-NEXT: beq a1, a3, .LBB23_4 ; RV32IBB-NEXT: .LBB23_2: -; RV32IBB-NEXT: sltu a4, a0, a2 -; RV32IBB-NEXT: bnez a4, .LBB23_4 +; RV32IBB-NEXT: minu a1, a1, a3 +; RV32IBB-NEXT: ret ; RV32IBB-NEXT: .LBB23_3: ; RV32IBB-NEXT: mv a0, a2 -; RV32IBB-NEXT: mv a1, a3 +; RV32IBB-NEXT: bne a1, a3, .LBB23_2 ; RV32IBB-NEXT: .LBB23_4: +; RV32IBB-NEXT: minu a0, a4, a2 +; RV32IBB-NEXT: minu a1, a1, a3 ; RV32IBB-NEXT: ret %cmp = icmp ult i64 %a, %b %cond = select i1 %cmp, i64 %a, i64 %b @@ -1153,36 +1159,102 @@ define i64 @maxu_i64(i64 %a, i64 %b) nounwind { ; ; RV32IB-LABEL: maxu_i64: ; RV32IB: # %bb.0: -; RV32IB-NEXT: beq a1, a3, .LBB25_2 +; RV32IB-NEXT: mv a4, a0 +; RV32IB-NEXT: bgeu a3, a1, .LBB25_3 ; RV32IB-NEXT: # %bb.1: -; RV32IB-NEXT: sltu a4, a3, a1 -; RV32IB-NEXT: beqz a4, .LBB25_3 -; RV32IB-NEXT: j .LBB25_4 +; RV32IB-NEXT: beq a1, a3, .LBB25_4 ; RV32IB-NEXT: .LBB25_2: -; RV32IB-NEXT: sltu a4, a2, a0 -; RV32IB-NEXT: bnez a4, .LBB25_4 +; RV32IB-NEXT: maxu a1, a1, a3 +; RV32IB-NEXT: ret ; RV32IB-NEXT: .LBB25_3: ; RV32IB-NEXT: mv a0, a2 -; RV32IB-NEXT: mv a1, a3 +; RV32IB-NEXT: bne a1, a3, .LBB25_2 ; RV32IB-NEXT: .LBB25_4: +; RV32IB-NEXT: maxu a0, a4, a2 +; RV32IB-NEXT: maxu a1, a1, a3 ; RV32IB-NEXT: ret ; ; RV32IBB-LABEL: maxu_i64: ; RV32IBB: # %bb.0: -; RV32IBB-NEXT: beq a1, a3, .LBB25_2 +; RV32IBB-NEXT: mv a4, a0 +; RV32IBB-NEXT: bgeu a3, a1, .LBB25_3 ; RV32IBB-NEXT: # %bb.1: -; RV32IBB-NEXT: sltu a4, a3, a1 -; RV32IBB-NEXT: beqz a4, .LBB25_3 -; RV32IBB-NEXT: j .LBB25_4 +; RV32IBB-NEXT: beq a1, a3, .LBB25_4 ; RV32IBB-NEXT: .LBB25_2: -; RV32IBB-NEXT: sltu a4, a2, a0 -; RV32IBB-NEXT: bnez a4, .LBB25_4 +; RV32IBB-NEXT: maxu a1, a1, a3 +; RV32IBB-NEXT: ret ; RV32IBB-NEXT: .LBB25_3: ; RV32IBB-NEXT: mv a0, a2 -; RV32IBB-NEXT: mv a1, a3 +; RV32IBB-NEXT: bne a1, a3, .LBB25_2 ; RV32IBB-NEXT: .LBB25_4: +; RV32IBB-NEXT: maxu a0, a4, a2 +; RV32IBB-NEXT: maxu a1, a1, a3 ; RV32IBB-NEXT: ret %cmp = icmp ugt i64 %a, %b %cond = select i1 %cmp, i64 %a, i64 %b ret i64 %cond } + +declare i32 @llvm.abs.i32(i32, i1 immarg) + +define i32 @abs_i32(i32 %x) { +; RV32I-LABEL: abs_i32: +; RV32I: # %bb.0: +; RV32I-NEXT: srai a1, a0, 31 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: xor a0, a0, a1 +; RV32I-NEXT: ret +; +; RV32IB-LABEL: abs_i32: +; RV32IB: # %bb.0: +; RV32IB-NEXT: neg a1, a0 +; RV32IB-NEXT: max a0, a0, a1 +; RV32IB-NEXT: ret +; +; RV32IBB-LABEL: abs_i32: +; RV32IBB: # %bb.0: +; RV32IBB-NEXT: neg a1, a0 +; RV32IBB-NEXT: max a0, a0, a1 +; RV32IBB-NEXT: ret + %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) + ret i32 %abs +} + +declare i64 @llvm.abs.i64(i64, i1 immarg) + +define i64 @abs_i64(i64 %x) { +; RV32I-LABEL: abs_i64: +; RV32I: # %bb.0: +; RV32I-NEXT: bgez a1, .LBB27_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: snez a2, a0 +; RV32I-NEXT: neg a0, a0 +; RV32I-NEXT: add a1, a1, a2 +; RV32I-NEXT: neg a1, a1 +; RV32I-NEXT: .LBB27_2: +; RV32I-NEXT: ret +; +; RV32IB-LABEL: abs_i64: +; RV32IB: # %bb.0: +; RV32IB-NEXT: bgez a1, .LBB27_2 +; RV32IB-NEXT: # %bb.1: +; RV32IB-NEXT: snez a2, a0 +; RV32IB-NEXT: neg a0, a0 +; RV32IB-NEXT: add a1, a1, a2 +; RV32IB-NEXT: neg a1, a1 +; RV32IB-NEXT: .LBB27_2: +; RV32IB-NEXT: ret +; +; RV32IBB-LABEL: abs_i64: +; RV32IBB: # %bb.0: +; RV32IBB-NEXT: bgez a1, .LBB27_2 +; RV32IBB-NEXT: # %bb.1: +; RV32IBB-NEXT: snez a2, a0 +; RV32IBB-NEXT: neg a0, a0 +; RV32IBB-NEXT: add a1, a1, a2 +; RV32IBB-NEXT: neg a1, a1 +; RV32IBB-NEXT: .LBB27_2: +; RV32IBB-NEXT: ret + %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) + ret i64 %abs +} diff --git a/llvm/test/CodeGen/RISCV/rv32Zbp.ll b/llvm/test/CodeGen/RISCV/rv32Zbp.ll index 22aee569ff28a..1382e1b714594 100644 --- a/llvm/test/CodeGen/RISCV/rv32Zbp.ll +++ b/llvm/test/CodeGen/RISCV/rv32Zbp.ll @@ -498,7 +498,6 @@ define i64 @grev2_i64(i64 %a) nounwind { ret i64 %or } -; FIXME: we should generate grevi 3 here define i32 @grev3_i32(i32 %a) nounwind { ; RV32I-LABEL: grev3_i32: ; RV32I: # %bb.0: @@ -524,14 +523,12 @@ define i32 @grev3_i32(i32 %a) nounwind { ; ; RV32IB-LABEL: grev3_i32: ; RV32IB: # %bb.0: -; RV32IB-NEXT: rev.p a0, a0 -; RV32IB-NEXT: rev2.n a0, a0 +; RV32IB-NEXT: rev.n a0, a0 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: grev3_i32: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: rev.p a0, a0 -; RV32IBP-NEXT: rev2.n a0, a0 +; RV32IBP-NEXT: rev.n a0, a0 ; RV32IBP-NEXT: ret %and1 = shl i32 %a, 1 %shl1 = and i32 %and1, -1431655766 @@ -546,7 +543,6 @@ define i32 @grev3_i32(i32 %a) nounwind { ret i32 %or2 } -; FIXME: we should generate grevi 3 here define i64 @grev3_i64(i64 %a) nounwind { ; RV32I-LABEL: grev3_i64: ; RV32I: # %bb.0: @@ -582,18 +578,14 @@ define i64 @grev3_i64(i64 %a) nounwind { ; ; RV32IB-LABEL: grev3_i64: ; RV32IB: # %bb.0: -; RV32IB-NEXT: rev.p a1, a1 -; RV32IB-NEXT: rev.p a0, a0 -; RV32IB-NEXT: rev2.n a0, a0 -; RV32IB-NEXT: rev2.n a1, a1 +; RV32IB-NEXT: rev.n a0, a0 +; RV32IB-NEXT: rev.n a1, a1 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: grev3_i64: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: rev.p a1, a1 -; RV32IBP-NEXT: rev.p a0, a0 -; RV32IBP-NEXT: rev2.n a0, a0 -; RV32IBP-NEXT: rev2.n a1, a1 +; RV32IBP-NEXT: rev.n a0, a0 +; RV32IBP-NEXT: rev.n a1, a1 ; RV32IBP-NEXT: ret %and1 = shl i64 %a, 1 %shl1 = and i64 %and1, -6148914691236517206 @@ -677,7 +669,6 @@ define i64 @grev4_i64(i64 %a) nounwind { ret i64 %or } -; FIXME: we should generate grevi 5 here define i32 @grev5_i32(i32 %a) nounwind { ; RV32I-LABEL: grev5_i32: ; RV32I: # %bb.0: @@ -703,14 +694,12 @@ define i32 @grev5_i32(i32 %a) nounwind { ; ; RV32IB-LABEL: grev5_i32: ; RV32IB: # %bb.0: -; RV32IB-NEXT: rev.p a0, a0 -; RV32IB-NEXT: rev4.b a0, a0 +; RV32IB-NEXT: grevi a0, a0, 5 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: grev5_i32: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: rev.p a0, a0 -; RV32IBP-NEXT: rev4.b a0, a0 +; RV32IBP-NEXT: grevi a0, a0, 5 ; RV32IBP-NEXT: ret %and1 = shl i32 %a, 1 %shl1 = and i32 %and1, -1431655766 @@ -725,7 +714,6 @@ define i32 @grev5_i32(i32 %a) nounwind { ret i32 %or2 } -; FIXME: we should generate grevi 5 here define i64 @grev5_i64(i64 %a) nounwind { ; RV32I-LABEL: grev5_i64: ; RV32I: # %bb.0: @@ -761,18 +749,14 @@ define i64 @grev5_i64(i64 %a) nounwind { ; ; RV32IB-LABEL: grev5_i64: ; RV32IB: # %bb.0: -; RV32IB-NEXT: rev.p a1, a1 -; RV32IB-NEXT: rev.p a0, a0 -; RV32IB-NEXT: rev4.b a0, a0 -; RV32IB-NEXT: rev4.b a1, a1 +; RV32IB-NEXT: grevi a0, a0, 5 +; RV32IB-NEXT: grevi a1, a1, 5 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: grev5_i64: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: rev.p a1, a1 -; RV32IBP-NEXT: rev.p a0, a0 -; RV32IBP-NEXT: rev4.b a0, a0 -; RV32IBP-NEXT: rev4.b a1, a1 +; RV32IBP-NEXT: grevi a0, a0, 5 +; RV32IBP-NEXT: grevi a1, a1, 5 ; RV32IBP-NEXT: ret %and1 = shl i64 %a, 1 %shl1 = and i64 %and1, -6148914691236517206 @@ -788,7 +772,6 @@ define i64 @grev5_i64(i64 %a) nounwind { ret i64 %or2 } -; FIXME: we should generate grevi 6 here define i32 @grev6_i32(i32 %a) nounwind { ; RV32I-LABEL: grev6_i32: ; RV32I: # %bb.0: @@ -814,14 +797,12 @@ define i32 @grev6_i32(i32 %a) nounwind { ; ; RV32IB-LABEL: grev6_i32: ; RV32IB: # %bb.0: -; RV32IB-NEXT: rev2.n a0, a0 -; RV32IB-NEXT: rev4.b a0, a0 +; RV32IB-NEXT: rev2.b a0, a0 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: grev6_i32: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: rev2.n a0, a0 -; RV32IBP-NEXT: rev4.b a0, a0 +; RV32IBP-NEXT: rev2.b a0, a0 ; RV32IBP-NEXT: ret %and1 = shl i32 %a, 2 %shl1 = and i32 %and1, -858993460 @@ -836,7 +817,6 @@ define i32 @grev6_i32(i32 %a) nounwind { ret i32 %or2 } -; FIXME: we should generate grevi 6 here define i64 @grev6_i64(i64 %a) nounwind { ; RV32I-LABEL: grev6_i64: ; RV32I: # %bb.0: @@ -872,18 +852,14 @@ define i64 @grev6_i64(i64 %a) nounwind { ; ; RV32IB-LABEL: grev6_i64: ; RV32IB: # %bb.0: -; RV32IB-NEXT: rev2.n a1, a1 -; RV32IB-NEXT: rev2.n a0, a0 -; RV32IB-NEXT: rev4.b a0, a0 -; RV32IB-NEXT: rev4.b a1, a1 +; RV32IB-NEXT: rev2.b a0, a0 +; RV32IB-NEXT: rev2.b a1, a1 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: grev6_i64: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: rev2.n a1, a1 -; RV32IBP-NEXT: rev2.n a0, a0 -; RV32IBP-NEXT: rev4.b a0, a0 -; RV32IBP-NEXT: rev4.b a1, a1 +; RV32IBP-NEXT: rev2.b a0, a0 +; RV32IBP-NEXT: rev2.b a1, a1 ; RV32IBP-NEXT: ret %and1 = shl i64 %a, 2 %shl1 = and i64 %and1, -3689348814741910324 @@ -898,7 +874,6 @@ define i64 @grev6_i64(i64 %a) nounwind { ret i64 %or2 } -; FIXME: we should generate grevi 7 here define i32 @grev7_i32(i32 %a) nounwind { ; RV32I-LABEL: grev7_i32: ; RV32I: # %bb.0: @@ -933,16 +908,12 @@ define i32 @grev7_i32(i32 %a) nounwind { ; ; RV32IB-LABEL: grev7_i32: ; RV32IB: # %bb.0: -; RV32IB-NEXT: rev.p a0, a0 -; RV32IB-NEXT: rev2.n a0, a0 -; RV32IB-NEXT: rev4.b a0, a0 +; RV32IB-NEXT: rev.b a0, a0 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: grev7_i32: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: rev.p a0, a0 -; RV32IBP-NEXT: rev2.n a0, a0 -; RV32IBP-NEXT: rev4.b a0, a0 +; RV32IBP-NEXT: rev.b a0, a0 ; RV32IBP-NEXT: ret %and1 = shl i32 %a, 1 %shl1 = and i32 %and1, -1431655766 @@ -962,7 +933,6 @@ define i32 @grev7_i32(i32 %a) nounwind { ret i32 %or3 } -; FIXME: we should generate grevi 7 here define i64 @grev7_i64(i64 %a) nounwind { ; RV32I-LABEL: grev7_i64: ; RV32I: # %bb.0: @@ -1012,22 +982,14 @@ define i64 @grev7_i64(i64 %a) nounwind { ; ; RV32IB-LABEL: grev7_i64: ; RV32IB: # %bb.0: -; RV32IB-NEXT: rev.p a0, a0 -; RV32IB-NEXT: rev.p a1, a1 -; RV32IB-NEXT: rev2.n a1, a1 -; RV32IB-NEXT: rev2.n a0, a0 -; RV32IB-NEXT: rev4.b a0, a0 -; RV32IB-NEXT: rev4.b a1, a1 +; RV32IB-NEXT: rev.b a0, a0 +; RV32IB-NEXT: rev.b a1, a1 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: grev7_i64: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: rev.p a0, a0 -; RV32IBP-NEXT: rev.p a1, a1 -; RV32IBP-NEXT: rev2.n a1, a1 -; RV32IBP-NEXT: rev2.n a0, a0 -; RV32IBP-NEXT: rev4.b a0, a0 -; RV32IBP-NEXT: rev4.b a1, a1 +; RV32IBP-NEXT: rev.b a0, a0 +; RV32IBP-NEXT: rev.b a1, a1 ; RV32IBP-NEXT: ret %and1 = shl i64 %a, 1 %shl1 = and i64 %and1, -6148914691236517206 @@ -1126,12 +1088,12 @@ define i32 @grev16_i32(i32 %a) nounwind { ; ; RV32IB-LABEL: grev16_i32: ; RV32IB: # %bb.0: -; RV32IB-NEXT: rev16 a0, a0 +; RV32IB-NEXT: rori a0, a0, 16 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: grev16_i32: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: rev16 a0, a0 +; RV32IBP-NEXT: rori a0, a0, 16 ; RV32IBP-NEXT: ret %shl = shl i32 %a, 16 %shr = lshr i32 %a, 16 @@ -1139,6 +1101,386 @@ define i32 @grev16_i32(i32 %a) nounwind { ret i32 %or } + +define i32 @grev3b_i32(i32 %a) nounwind { +; RV32I-LABEL: grev3b_i32: +; RV32I: # %bb.0: +; RV32I-NEXT: slli a1, a0, 2 +; RV32I-NEXT: lui a2, 838861 +; RV32I-NEXT: addi a2, a2, -820 +; RV32I-NEXT: and a1, a1, a2 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: lui a2, 209715 +; RV32I-NEXT: addi a2, a2, 819 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: slli a1, a0, 1 +; RV32I-NEXT: lui a2, 699051 +; RV32I-NEXT: addi a2, a2, -1366 +; RV32I-NEXT: and a1, a1, a2 +; RV32I-NEXT: srli a0, a0, 1 +; RV32I-NEXT: lui a2, 349525 +; RV32I-NEXT: addi a2, a2, 1365 +; RV32I-NEXT: and a0, a0, a2 +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: ret +; +; RV32IB-LABEL: grev3b_i32: +; RV32IB: # %bb.0: +; RV32IB-NEXT: rev.n a0, a0 +; RV32IB-NEXT: ret +; +; RV32IBP-LABEL: grev3b_i32: +; RV32IBP: # %bb.0: +; RV32IBP-NEXT: rev.n a0, a0 +; RV32IBP-NEXT: ret + %and2 = shl i32 %a, 2 + %shl2 = and i32 %and2, -858993460 + %and2b = lshr i32 %a, 2 + %shr2 = and i32 %and2b, 858993459 + %or2 = or i32 %shl2, %shr2 + %and1 = shl i32 %or2, 1 + %shl1 = and i32 %and1, -1431655766 + %and1b = lshr i32 %or2, 1 + %shr1 = and i32 %and1b, 1431655765 + %or1 = or i32 %shl1, %shr1 + ret i32 %or1 +} + +define i64 @grev3b_i64(i64 %a) nounwind { +; RV32I-LABEL: grev3b_i64: +; RV32I: # %bb.0: +; RV32I-NEXT: slli a2, a1, 2 +; RV32I-NEXT: slli a3, a0, 2 +; RV32I-NEXT: lui a4, 838861 +; RV32I-NEXT: addi a4, a4, -820 +; RV32I-NEXT: and a3, a3, a4 +; RV32I-NEXT: and a2, a2, a4 +; RV32I-NEXT: srli a1, a1, 2 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: lui a4, 209715 +; RV32I-NEXT: addi a4, a4, 819 +; RV32I-NEXT: and a0, a0, a4 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: or a1, a2, a1 +; RV32I-NEXT: or a0, a3, a0 +; RV32I-NEXT: slli a2, a0, 1 +; RV32I-NEXT: slli a3, a1, 1 +; RV32I-NEXT: lui a4, 699051 +; RV32I-NEXT: addi a4, a4, -1366 +; RV32I-NEXT: and a3, a3, a4 +; RV32I-NEXT: and a2, a2, a4 +; RV32I-NEXT: srli a0, a0, 1 +; RV32I-NEXT: srli a1, a1, 1 +; RV32I-NEXT: lui a4, 349525 +; RV32I-NEXT: addi a4, a4, 1365 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: and a0, a0, a4 +; RV32I-NEXT: or a0, a2, a0 +; RV32I-NEXT: or a1, a3, a1 +; RV32I-NEXT: ret +; +; RV32IB-LABEL: grev3b_i64: +; RV32IB: # %bb.0: +; RV32IB-NEXT: rev.n a0, a0 +; RV32IB-NEXT: rev.n a1, a1 +; RV32IB-NEXT: ret +; +; RV32IBP-LABEL: grev3b_i64: +; RV32IBP: # %bb.0: +; RV32IBP-NEXT: rev.n a0, a0 +; RV32IBP-NEXT: rev.n a1, a1 +; RV32IBP-NEXT: ret + %and2 = shl i64 %a, 2 + %shl2 = and i64 %and2, -3689348814741910324 + %and2b = lshr i64 %a, 2 + %shr2 = and i64 %and2b, 3689348814741910323 + %or2 = or i64 %shl2, %shr2 + %and1 = shl i64 %or2, 1 + %shl1 = and i64 %and1, -6148914691236517206 + %and1b = lshr i64 %or2, 1 + %shr1 = and i64 %and1b, 6148914691236517205 + %or1 = or i64 %shl1, %shr1 + ret i64 %or1 +} + +; grev1, grev2, grev1 -> grev2 +define i32 @grev2b_i32(i32 %a) nounwind { +; RV32I-LABEL: grev2b_i32: +; RV32I: # %bb.0: +; RV32I-NEXT: slli a1, a0, 1 +; RV32I-NEXT: lui a2, 699051 +; RV32I-NEXT: addi a2, a2, -1366 +; RV32I-NEXT: and a1, a1, a2 +; RV32I-NEXT: srli a0, a0, 1 +; RV32I-NEXT: lui a3, 349525 +; RV32I-NEXT: addi a3, a3, 1365 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: slli a1, a0, 2 +; RV32I-NEXT: lui a4, 838861 +; RV32I-NEXT: addi a4, a4, -820 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: lui a4, 209715 +; RV32I-NEXT: addi a4, a4, 819 +; RV32I-NEXT: and a0, a0, a4 +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: slli a1, a0, 1 +; RV32I-NEXT: and a1, a1, a2 +; RV32I-NEXT: srli a0, a0, 1 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: ret +; +; RV32IB-LABEL: grev2b_i32: +; RV32IB: # %bb.0: +; RV32IB-NEXT: rev2.n a0, a0 +; RV32IB-NEXT: ret +; +; RV32IBP-LABEL: grev2b_i32: +; RV32IBP: # %bb.0: +; RV32IBP-NEXT: rev2.n a0, a0 +; RV32IBP-NEXT: ret + %and1 = shl i32 %a, 1 + %shl1 = and i32 %and1, -1431655766 + %and1b = lshr i32 %a, 1 + %shr1 = and i32 %and1b, 1431655765 + %or1 = or i32 %shl1, %shr1 + %and2 = shl i32 %or1, 2 + %shl2 = and i32 %and2, -858993460 + %and2b = lshr i32 %or1, 2 + %shr2 = and i32 %and2b, 858993459 + %or2 = or i32 %shl2, %shr2 + %and3 = shl i32 %or2, 1 + %shl3 = and i32 %and3, -1431655766 + %and3b = lshr i32 %or2, 1 + %shr3 = and i32 %and3b, 1431655765 + %or3 = or i32 %shl3, %shr3 + ret i32 %or3 +} + +; grev1, grev2, grev1 -> grev2 +define i64 @grev2b_i64(i64 %a) nounwind { +; RV32I-LABEL: grev2b_i64: +; RV32I: # %bb.0: +; RV32I-NEXT: slli a2, a0, 1 +; RV32I-NEXT: slli a3, a1, 1 +; RV32I-NEXT: lui a4, 699051 +; RV32I-NEXT: addi a4, a4, -1366 +; RV32I-NEXT: and a3, a3, a4 +; RV32I-NEXT: and a2, a2, a4 +; RV32I-NEXT: srli a0, a0, 1 +; RV32I-NEXT: srli a1, a1, 1 +; RV32I-NEXT: lui a5, 349525 +; RV32I-NEXT: addi a5, a5, 1365 +; RV32I-NEXT: and a1, a1, a5 +; RV32I-NEXT: and a0, a0, a5 +; RV32I-NEXT: or a0, a2, a0 +; RV32I-NEXT: or a1, a3, a1 +; RV32I-NEXT: slli a6, a1, 2 +; RV32I-NEXT: slli a3, a0, 2 +; RV32I-NEXT: lui a2, 838861 +; RV32I-NEXT: addi a2, a2, -820 +; RV32I-NEXT: and a7, a3, a2 +; RV32I-NEXT: and a2, a6, a2 +; RV32I-NEXT: srli a1, a1, 2 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: lui a3, 209715 +; RV32I-NEXT: addi a3, a3, 819 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: and a1, a1, a3 +; RV32I-NEXT: or a1, a2, a1 +; RV32I-NEXT: or a0, a7, a0 +; RV32I-NEXT: slli a2, a0, 1 +; RV32I-NEXT: slli a3, a1, 1 +; RV32I-NEXT: and a3, a3, a4 +; RV32I-NEXT: and a2, a2, a4 +; RV32I-NEXT: srli a0, a0, 1 +; RV32I-NEXT: srli a1, a1, 1 +; RV32I-NEXT: and a1, a1, a5 +; RV32I-NEXT: and a0, a0, a5 +; RV32I-NEXT: or a0, a2, a0 +; RV32I-NEXT: or a1, a3, a1 +; RV32I-NEXT: ret +; +; RV32IB-LABEL: grev2b_i64: +; RV32IB: # %bb.0: +; RV32IB-NEXT: rev2.n a0, a0 +; RV32IB-NEXT: rev2.n a1, a1 +; RV32IB-NEXT: ret +; +; RV32IBP-LABEL: grev2b_i64: +; RV32IBP: # %bb.0: +; RV32IBP-NEXT: rev2.n a0, a0 +; RV32IBP-NEXT: rev2.n a1, a1 +; RV32IBP-NEXT: ret + %and1 = shl i64 %a, 1 + %shl1 = and i64 %and1, -6148914691236517206 + %and1b = lshr i64 %a, 1 + %shr1 = and i64 %and1b, 6148914691236517205 + %or1 = or i64 %shl1, %shr1 + %and2 = shl i64 %or1, 2 + %shl2 = and i64 %and2, -3689348814741910324 + %and2b = lshr i64 %or1, 2 + %shr2 = and i64 %and2b, 3689348814741910323 + %or2 = or i64 %shl2, %shr2 + %and3 = shl i64 %or2, 1 + %shl3 = and i64 %and3, -6148914691236517206 + %and3b = lshr i64 %or2, 1 + %shr3 = and i64 %and3b, 6148914691236517205 + %or3 = or i64 %shl3, %shr3 + ret i64 %or3 +} + +; grev1, grev2, grev1, grev2 -> identity +define i32 @grev0_i32(i32 %a) nounwind { +; RV32I-LABEL: grev0_i32: +; RV32I: # %bb.0: +; RV32I-NEXT: slli a1, a0, 1 +; RV32I-NEXT: lui a2, 699051 +; RV32I-NEXT: addi a2, a2, -1366 +; RV32I-NEXT: and a1, a1, a2 +; RV32I-NEXT: srli a0, a0, 1 +; RV32I-NEXT: lui a3, 349525 +; RV32I-NEXT: addi a3, a3, 1365 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: slli a1, a0, 2 +; RV32I-NEXT: lui a4, 838861 +; RV32I-NEXT: addi a4, a4, -820 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: lui a5, 209715 +; RV32I-NEXT: addi a5, a5, 819 +; RV32I-NEXT: and a0, a0, a5 +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: slli a1, a0, 1 +; RV32I-NEXT: and a1, a1, a2 +; RV32I-NEXT: srli a0, a0, 1 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: slli a1, a0, 2 +; RV32I-NEXT: and a1, a1, a4 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: and a0, a0, a5 +; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: ret +; +; RV32IB-LABEL: grev0_i32: +; RV32IB: # %bb.0: +; RV32IB-NEXT: ret +; +; RV32IBP-LABEL: grev0_i32: +; RV32IBP: # %bb.0: +; RV32IBP-NEXT: ret + %and1 = shl i32 %a, 1 + %shl1 = and i32 %and1, -1431655766 + %and1b = lshr i32 %a, 1 + %shr1 = and i32 %and1b, 1431655765 + %or1 = or i32 %shl1, %shr1 + %and2 = shl i32 %or1, 2 + %shl2 = and i32 %and2, -858993460 + %and2b = lshr i32 %or1, 2 + %shr2 = and i32 %and2b, 858993459 + %or2 = or i32 %shl2, %shr2 + %and3 = shl i32 %or2, 1 + %shl3 = and i32 %and3, -1431655766 + %and3b = lshr i32 %or2, 1 + %shr3 = and i32 %and3b, 1431655765 + %or3 = or i32 %shl3, %shr3 + %and4 = shl i32 %or3, 2 + %shl4 = and i32 %and4, -858993460 + %and4b = lshr i32 %or3, 2 + %shr4 = and i32 %and4b, 858993459 + %or4 = or i32 %shl4, %shr4 + ret i32 %or4 +} + +; grev1, grev2, grev1, grev2 -> identity +define i64 @grev0_i64(i64 %a) nounwind { +; RV32I-LABEL: grev0_i64: +; RV32I: # %bb.0: +; RV32I-NEXT: slli a2, a1, 1 +; RV32I-NEXT: slli a3, a0, 1 +; RV32I-NEXT: lui a4, 699051 +; RV32I-NEXT: addi a4, a4, -1366 +; RV32I-NEXT: and a3, a3, a4 +; RV32I-NEXT: and a2, a2, a4 +; RV32I-NEXT: srli a1, a1, 1 +; RV32I-NEXT: srli a0, a0, 1 +; RV32I-NEXT: lui a5, 349525 +; RV32I-NEXT: addi a5, a5, 1365 +; RV32I-NEXT: and a0, a0, a5 +; RV32I-NEXT: and a1, a1, a5 +; RV32I-NEXT: or a1, a2, a1 +; RV32I-NEXT: or a0, a3, a0 +; RV32I-NEXT: slli a6, a0, 2 +; RV32I-NEXT: slli a3, a1, 2 +; RV32I-NEXT: lui a2, 838861 +; RV32I-NEXT: addi a2, a2, -820 +; RV32I-NEXT: and a7, a3, a2 +; RV32I-NEXT: and a6, a6, a2 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: srli a1, a1, 2 +; RV32I-NEXT: lui a3, 209715 +; RV32I-NEXT: addi a3, a3, 819 +; RV32I-NEXT: and a1, a1, a3 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: or t0, a6, a0 +; RV32I-NEXT: or a1, a7, a1 +; RV32I-NEXT: slli a6, a1, 1 +; RV32I-NEXT: slli a0, t0, 1 +; RV32I-NEXT: and a7, a0, a4 +; RV32I-NEXT: and a4, a6, a4 +; RV32I-NEXT: srli a1, a1, 1 +; RV32I-NEXT: srli a0, t0, 1 +; RV32I-NEXT: and a0, a0, a5 +; RV32I-NEXT: and a1, a1, a5 +; RV32I-NEXT: or a1, a4, a1 +; RV32I-NEXT: or a0, a7, a0 +; RV32I-NEXT: slli a4, a0, 2 +; RV32I-NEXT: slli a5, a1, 2 +; RV32I-NEXT: and a5, a5, a2 +; RV32I-NEXT: and a2, a4, a2 +; RV32I-NEXT: srli a0, a0, 2 +; RV32I-NEXT: srli a1, a1, 2 +; RV32I-NEXT: and a1, a1, a3 +; RV32I-NEXT: and a0, a0, a3 +; RV32I-NEXT: or a0, a2, a0 +; RV32I-NEXT: or a1, a5, a1 +; RV32I-NEXT: ret +; +; RV32IB-LABEL: grev0_i64: +; RV32IB: # %bb.0: +; RV32IB-NEXT: ret +; +; RV32IBP-LABEL: grev0_i64: +; RV32IBP: # %bb.0: +; RV32IBP-NEXT: ret + %and1 = shl i64 %a, 1 + %shl1 = and i64 %and1, -6148914691236517206 + %and1b = lshr i64 %a, 1 + %shr1 = and i64 %and1b, 6148914691236517205 + %or1 = or i64 %shl1, %shr1 + %and2 = shl i64 %or1, 2 + %shl2 = and i64 %and2, -3689348814741910324 + %and2b = lshr i64 %or1, 2 + %shr2 = and i64 %and2b, 3689348814741910323 + %or2 = or i64 %shl2, %shr2 + %and3 = shl i64 %or2, 1 + %shl3 = and i64 %and3, -6148914691236517206 + %and3b = lshr i64 %or2, 1 + %shr3 = and i64 %and3b, 6148914691236517205 + %or3 = or i64 %shl3, %shr3 + %and4 = shl i64 %or3, 2 + %shl4 = and i64 %and4, -3689348814741910324 + %and4b = lshr i64 %or3, 2 + %shr4 = and i64 %and4b, 3689348814741910323 + %or4 = or i64 %shl4, %shr4 + ret i64 %or4 +} + declare i32 @llvm.fshl.i32(i32, i32, i32) declare i32 @llvm.fshr.i32(i32, i32, i32) @@ -1152,12 +1494,12 @@ define signext i32 @grev16_i32_fshl(i32 signext %a) nounwind { ; ; RV32IB-LABEL: grev16_i32_fshl: ; RV32IB: # %bb.0: -; RV32IB-NEXT: rev16 a0, a0 +; RV32IB-NEXT: rori a0, a0, 16 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: grev16_i32_fshl: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: rev16 a0, a0 +; RV32IBP-NEXT: rori a0, a0, 16 ; RV32IBP-NEXT: ret %or = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 16) ret i32 %or @@ -1173,12 +1515,12 @@ define signext i32 @grev16_i32_fshr(i32 signext %a) nounwind { ; ; RV32IB-LABEL: grev16_i32_fshr: ; RV32IB: # %bb.0: -; RV32IB-NEXT: rev16 a0, a0 +; RV32IB-NEXT: rori a0, a0, 16 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: grev16_i32_fshr: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: rev16 a0, a0 +; RV32IBP-NEXT: rori a0, a0, 16 ; RV32IBP-NEXT: ret %or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 16) ret i32 %or @@ -1197,14 +1539,14 @@ define i64 @grev16_i64(i64 %a) nounwind { ; ; RV32IB-LABEL: grev16_i64: ; RV32IB: # %bb.0: -; RV32IB-NEXT: rev16 a0, a0 -; RV32IB-NEXT: rev16 a1, a1 +; RV32IB-NEXT: rori a0, a0, 16 +; RV32IB-NEXT: rori a1, a1, 16 ; RV32IB-NEXT: ret ; ; RV32IBP-LABEL: grev16_i64: ; RV32IBP: # %bb.0: -; RV32IBP-NEXT: rev16 a0, a0 -; RV32IBP-NEXT: rev16 a1, a1 +; RV32IBP-NEXT: rori a0, a0, 16 +; RV32IBP-NEXT: rori a1, a1, 16 ; RV32IBP-NEXT: ret %and = shl i64 %a, 16 %shl = and i64 %and, -281470681808896 diff --git a/llvm/test/CodeGen/RISCV/rv32Zbs.ll b/llvm/test/CodeGen/RISCV/rv32Zbs.ll index 56e8ac57bc7c8..355389340da59 100644 --- a/llvm/test/CodeGen/RISCV/rv32Zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv32Zbs.ll @@ -79,36 +79,34 @@ define i64 @sbclr_i64(i64 %a, i64 %b) nounwind { ; RV32IB-LABEL: sbclr_i64: ; RV32IB: # %bb.0: ; RV32IB-NEXT: andi a3, a2, 63 -; RV32IB-NEXT: addi a4, a3, -32 -; RV32IB-NEXT: addi a3, zero, 1 -; RV32IB-NEXT: bltz a4, .LBB2_2 +; RV32IB-NEXT: addi a3, a3, -32 +; RV32IB-NEXT: bltz a3, .LBB2_2 ; RV32IB-NEXT: # %bb.1: ; RV32IB-NEXT: mv a2, zero -; RV32IB-NEXT: sll a4, a3, a4 +; RV32IB-NEXT: sbset a3, zero, a3 ; RV32IB-NEXT: j .LBB2_3 ; RV32IB-NEXT: .LBB2_2: -; RV32IB-NEXT: mv a4, zero -; RV32IB-NEXT: sll a2, a3, a2 +; RV32IB-NEXT: mv a3, zero +; RV32IB-NEXT: sbset a2, zero, a2 ; RV32IB-NEXT: .LBB2_3: ; RV32IB-NEXT: andn a0, a0, a2 -; RV32IB-NEXT: andn a1, a1, a4 +; RV32IB-NEXT: andn a1, a1, a3 ; RV32IB-NEXT: ret ; ; RV32IBS-LABEL: sbclr_i64: ; RV32IBS: # %bb.0: ; RV32IBS-NEXT: andi a3, a2, 63 -; RV32IBS-NEXT: addi a4, a3, -32 -; RV32IBS-NEXT: addi a3, zero, 1 -; RV32IBS-NEXT: bltz a4, .LBB2_2 +; RV32IBS-NEXT: addi a3, a3, -32 +; RV32IBS-NEXT: bltz a3, .LBB2_2 ; RV32IBS-NEXT: # %bb.1: ; RV32IBS-NEXT: mv a2, zero -; RV32IBS-NEXT: sll a4, a3, a4 +; RV32IBS-NEXT: sbset a3, zero, a3 ; RV32IBS-NEXT: j .LBB2_3 ; RV32IBS-NEXT: .LBB2_2: -; RV32IBS-NEXT: mv a4, zero -; RV32IBS-NEXT: sll a2, a3, a2 +; RV32IBS-NEXT: mv a3, zero +; RV32IBS-NEXT: sbset a2, zero, a2 ; RV32IBS-NEXT: .LBB2_3: -; RV32IBS-NEXT: not a3, a4 +; RV32IBS-NEXT: not a3, a3 ; RV32IBS-NEXT: not a2, a2 ; RV32IBS-NEXT: and a0, a2, a0 ; RV32IBS-NEXT: and a1, a3, a1 @@ -165,6 +163,27 @@ define i32 @sbset_i32_no_mask(i32 %a, i32 %b) nounwind { ret i32 %or } +; We can use sbsetw for 1 << x by setting the first source to zero. +define signext i32 @sbset_i32_zero(i32 signext %a) nounwind { +; RV32I-LABEL: sbset_i32_zero: +; RV32I: # %bb.0: +; RV32I-NEXT: addi a1, zero, 1 +; RV32I-NEXT: sll a0, a1, a0 +; RV32I-NEXT: ret +; +; RV32IB-LABEL: sbset_i32_zero: +; RV32IB: # %bb.0: +; RV32IB-NEXT: sbset a0, zero, a0 +; RV32IB-NEXT: ret +; +; RV32IBS-LABEL: sbset_i32_zero: +; RV32IBS: # %bb.0: +; RV32IBS-NEXT: sbset a0, zero, a0 +; RV32IBS-NEXT: ret + %shl = shl i32 1, %a + ret i32 %shl +} + ; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; don't have yet any matching bit manipulation instructions on RV32. ; This test is presented here in case future expansions of the experimental-b @@ -182,8 +201,7 @@ define i64 @sbset_i64(i64 %a, i64 %b) nounwind { ; ; RV32IB-LABEL: sbset_i64: ; RV32IB: # %bb.0: -; RV32IB-NEXT: addi a3, zero, 1 -; RV32IB-NEXT: sll a3, a3, a2 +; RV32IB-NEXT: sbset a3, zero, a2 ; RV32IB-NEXT: srai a3, a3, 31 ; RV32IB-NEXT: sbset a0, a0, a2 ; RV32IB-NEXT: or a1, a3, a1 @@ -191,8 +209,7 @@ define i64 @sbset_i64(i64 %a, i64 %b) nounwind { ; ; RV32IBS-LABEL: sbset_i64: ; RV32IBS: # %bb.0: -; RV32IBS-NEXT: addi a3, zero, 1 -; RV32IBS-NEXT: sll a3, a3, a2 +; RV32IBS-NEXT: sbset a3, zero, a2 ; RV32IBS-NEXT: srai a3, a3, 31 ; RV32IBS-NEXT: sbset a0, a0, a2 ; RV32IBS-NEXT: or a1, a3, a1 @@ -205,6 +222,50 @@ define i64 @sbset_i64(i64 %a, i64 %b) nounwind { ret i64 %or } +define signext i64 @sbset_i64_zero(i64 signext %a) nounwind { +; RV32I-LABEL: sbset_i64_zero: +; RV32I: # %bb.0: +; RV32I-NEXT: addi a1, a0, -32 +; RV32I-NEXT: addi a2, zero, 1 +; RV32I-NEXT: bltz a1, .LBB7_2 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: mv a0, zero +; RV32I-NEXT: sll a1, a2, a1 +; RV32I-NEXT: ret +; RV32I-NEXT: .LBB7_2: +; RV32I-NEXT: mv a1, zero +; RV32I-NEXT: sll a0, a2, a0 +; RV32I-NEXT: ret +; +; RV32IB-LABEL: sbset_i64_zero: +; RV32IB: # %bb.0: +; RV32IB-NEXT: addi a1, a0, -32 +; RV32IB-NEXT: bltz a1, .LBB7_2 +; RV32IB-NEXT: # %bb.1: +; RV32IB-NEXT: mv a0, zero +; RV32IB-NEXT: sbset a1, zero, a1 +; RV32IB-NEXT: ret +; RV32IB-NEXT: .LBB7_2: +; RV32IB-NEXT: mv a1, zero +; RV32IB-NEXT: sbset a0, zero, a0 +; RV32IB-NEXT: ret +; +; RV32IBS-LABEL: sbset_i64_zero: +; RV32IBS: # %bb.0: +; RV32IBS-NEXT: addi a1, a0, -32 +; RV32IBS-NEXT: bltz a1, .LBB7_2 +; RV32IBS-NEXT: # %bb.1: +; RV32IBS-NEXT: mv a0, zero +; RV32IBS-NEXT: sbset a1, zero, a1 +; RV32IBS-NEXT: ret +; RV32IBS-NEXT: .LBB7_2: +; RV32IBS-NEXT: mv a1, zero +; RV32IBS-NEXT: sbset a0, zero, a0 +; RV32IBS-NEXT: ret + %shl = shl i64 1, %a + ret i64 %shl +} + define i32 @sbinv_i32(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: sbinv_i32: ; RV32I: # %bb.0: @@ -245,8 +306,7 @@ define i64 @sbinv_i64(i64 %a, i64 %b) nounwind { ; ; RV32IB-LABEL: sbinv_i64: ; RV32IB: # %bb.0: -; RV32IB-NEXT: addi a3, zero, 1 -; RV32IB-NEXT: sll a3, a3, a2 +; RV32IB-NEXT: sbset a3, zero, a2 ; RV32IB-NEXT: srai a3, a3, 31 ; RV32IB-NEXT: sbinv a0, a0, a2 ; RV32IB-NEXT: xor a1, a3, a1 @@ -254,8 +314,7 @@ define i64 @sbinv_i64(i64 %a, i64 %b) nounwind { ; ; RV32IBS-LABEL: sbinv_i64: ; RV32IBS: # %bb.0: -; RV32IBS-NEXT: addi a3, zero, 1 -; RV32IBS-NEXT: sll a3, a3, a2 +; RV32IBS-NEXT: sbset a3, zero, a2 ; RV32IBS-NEXT: srai a3, a3, 31 ; RV32IBS-NEXT: sbinv a0, a0, a2 ; RV32IBS-NEXT: xor a1, a3, a1 @@ -321,18 +380,18 @@ define i64 @sbext_i64(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: andi a3, a2, 63 ; RV32I-NEXT: addi a4, a3, -32 -; RV32I-NEXT: bltz a4, .LBB10_2 +; RV32I-NEXT: bltz a4, .LBB12_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srl a0, a1, a4 -; RV32I-NEXT: j .LBB10_3 -; RV32I-NEXT: .LBB10_2: +; RV32I-NEXT: j .LBB12_3 +; RV32I-NEXT: .LBB12_2: ; RV32I-NEXT: srl a0, a0, a2 ; RV32I-NEXT: addi a2, zero, 31 ; RV32I-NEXT: sub a2, a2, a3 ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: sll a1, a1, a2 ; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: .LBB10_3: +; RV32I-NEXT: .LBB12_3: ; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: ret @@ -341,18 +400,18 @@ define i64 @sbext_i64(i64 %a, i64 %b) nounwind { ; RV32IB: # %bb.0: ; RV32IB-NEXT: andi a3, a2, 63 ; RV32IB-NEXT: addi a4, a3, -32 -; RV32IB-NEXT: bltz a4, .LBB10_2 +; RV32IB-NEXT: bltz a4, .LBB12_2 ; RV32IB-NEXT: # %bb.1: ; RV32IB-NEXT: srl a0, a1, a4 -; RV32IB-NEXT: j .LBB10_3 -; RV32IB-NEXT: .LBB10_2: +; RV32IB-NEXT: j .LBB12_3 +; RV32IB-NEXT: .LBB12_2: ; RV32IB-NEXT: srl a0, a0, a2 ; RV32IB-NEXT: addi a2, zero, 31 ; RV32IB-NEXT: sub a2, a2, a3 ; RV32IB-NEXT: slli a1, a1, 1 ; RV32IB-NEXT: sll a1, a1, a2 ; RV32IB-NEXT: or a0, a0, a1 -; RV32IB-NEXT: .LBB10_3: +; RV32IB-NEXT: .LBB12_3: ; RV32IB-NEXT: andi a0, a0, 1 ; RV32IB-NEXT: mv a1, zero ; RV32IB-NEXT: ret @@ -361,18 +420,18 @@ define i64 @sbext_i64(i64 %a, i64 %b) nounwind { ; RV32IBS: # %bb.0: ; RV32IBS-NEXT: andi a3, a2, 63 ; RV32IBS-NEXT: addi a4, a3, -32 -; RV32IBS-NEXT: bltz a4, .LBB10_2 +; RV32IBS-NEXT: bltz a4, .LBB12_2 ; RV32IBS-NEXT: # %bb.1: ; RV32IBS-NEXT: srl a0, a1, a4 -; RV32IBS-NEXT: j .LBB10_3 -; RV32IBS-NEXT: .LBB10_2: +; RV32IBS-NEXT: j .LBB12_3 +; RV32IBS-NEXT: .LBB12_2: ; RV32IBS-NEXT: srl a0, a0, a2 ; RV32IBS-NEXT: addi a2, zero, 31 ; RV32IBS-NEXT: sub a2, a2, a3 ; RV32IBS-NEXT: slli a1, a1, 1 ; RV32IBS-NEXT: sll a1, a1, a2 ; RV32IBS-NEXT: or a0, a0, a1 -; RV32IBS-NEXT: .LBB10_3: +; RV32IBS-NEXT: .LBB12_3: ; RV32IBS-NEXT: andi a0, a0, 1 ; RV32IBS-NEXT: mv a1, zero ; RV32IBS-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rv64Zbb.ll b/llvm/test/CodeGen/RISCV/rv64Zbb.ll index 66985c565370f..3c96af27c057f 100644 --- a/llvm/test/CodeGen/RISCV/rv64Zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64Zbb.ll @@ -856,12 +856,18 @@ define signext i32 @minu_i32(i32 signext %a, i32 signext %b) nounwind { ; ; RV64IB-LABEL: minu_i32: ; RV64IB: # %bb.0: +; RV64IB-NEXT: zext.w a1, a1 +; RV64IB-NEXT: zext.w a0, a0 ; RV64IB-NEXT: minu a0, a0, a1 +; RV64IB-NEXT: sext.w a0, a0 ; RV64IB-NEXT: ret ; ; RV64IBB-LABEL: minu_i32: ; RV64IBB: # %bb.0: +; RV64IBB-NEXT: zext.w a1, a1 +; RV64IBB-NEXT: zext.w a0, a0 ; RV64IBB-NEXT: minu a0, a0, a1 +; RV64IBB-NEXT: sext.w a0, a0 ; RV64IBB-NEXT: ret %cmp = icmp ult i32 %a, %b %cond = select i1 %cmp, i32 %a, i32 %b @@ -902,12 +908,18 @@ define signext i32 @maxu_i32(i32 signext %a, i32 signext %b) nounwind { ; ; RV64IB-LABEL: maxu_i32: ; RV64IB: # %bb.0: +; RV64IB-NEXT: zext.w a1, a1 +; RV64IB-NEXT: zext.w a0, a0 ; RV64IB-NEXT: maxu a0, a0, a1 +; RV64IB-NEXT: sext.w a0, a0 ; RV64IB-NEXT: ret ; ; RV64IBB-LABEL: maxu_i32: ; RV64IBB: # %bb.0: +; RV64IBB-NEXT: zext.w a1, a1 +; RV64IBB-NEXT: zext.w a0, a0 ; RV64IBB-NEXT: maxu a0, a0, a1 +; RV64IBB-NEXT: sext.w a0, a0 ; RV64IBB-NEXT: ret %cmp = icmp ugt i32 %a, %b %cond = select i1 %cmp, i32 %a, i32 %b @@ -937,6 +949,59 @@ define i64 @maxu_i64(i64 %a, i64 %b) nounwind { ret i64 %cond } +declare i32 @llvm.abs.i32(i32, i1 immarg) + +define i32 @abs_i32(i32 %x) { +; RV64I-LABEL: abs_i32: +; RV64I: # %bb.0: +; RV64I-NEXT: sext.w a0, a0 +; RV64I-NEXT: srai a1, a0, 63 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: xor a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: abs_i32: +; RV64IB: # %bb.0: +; RV64IB-NEXT: sext.w a0, a0 +; RV64IB-NEXT: neg a1, a0 +; RV64IB-NEXT: max a0, a0, a1 +; RV64IB-NEXT: ret +; +; RV64IBB-LABEL: abs_i32: +; RV64IBB: # %bb.0: +; RV64IBB-NEXT: sext.w a0, a0 +; RV64IBB-NEXT: neg a1, a0 +; RV64IBB-NEXT: max a0, a0, a1 +; RV64IBB-NEXT: ret + %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) + ret i32 %abs +} + +declare i64 @llvm.abs.i64(i64, i1 immarg) + +define i64 @abs_i64(i64 %x) { +; RV64I-LABEL: abs_i64: +; RV64I: # %bb.0: +; RV64I-NEXT: srai a1, a0, 63 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: xor a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: abs_i64: +; RV64IB: # %bb.0: +; RV64IB-NEXT: neg a1, a0 +; RV64IB-NEXT: max a0, a0, a1 +; RV64IB-NEXT: ret +; +; RV64IBB-LABEL: abs_i64: +; RV64IBB: # %bb.0: +; RV64IBB-NEXT: neg a1, a0 +; RV64IBB-NEXT: max a0, a0, a1 +; RV64IBB-NEXT: ret + %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) + ret i64 %abs +} + ; We select a i32 addi that zero-extends the result on RV64 as addiwu define zeroext i32 @zext_add_to_addiwu(i32 signext %a) nounwind { diff --git a/llvm/test/CodeGen/RISCV/rv64Zbbp.ll b/llvm/test/CodeGen/RISCV/rv64Zbbp.ll index 771967d22e195..f6787b833132a 100644 --- a/llvm/test/CodeGen/RISCV/rv64Zbbp.ll +++ b/llvm/test/CodeGen/RISCV/rv64Zbbp.ll @@ -374,7 +374,6 @@ define signext i32 @rori_i32_fshl(i32 signext %a) nounwind { } ; Similar to rori_i32_fshl, but doesn't sign extend the result. -; FIXME: We should be using RORIW, but we need a sext_inreg. define void @rori_i32_fshl_nosext(i32 signext %a, i32* %x) nounwind { ; RV64I-LABEL: rori_i32_fshl_nosext: ; RV64I: # %bb.0: @@ -386,25 +385,19 @@ define void @rori_i32_fshl_nosext(i32 signext %a, i32* %x) nounwind { ; ; RV64IB-LABEL: rori_i32_fshl_nosext: ; RV64IB: # %bb.0: -; RV64IB-NEXT: srliw a2, a0, 1 -; RV64IB-NEXT: slli a0, a0, 31 -; RV64IB-NEXT: or a0, a0, a2 +; RV64IB-NEXT: roriw a0, a0, 1 ; RV64IB-NEXT: sw a0, 0(a1) ; RV64IB-NEXT: ret ; ; RV64IBB-LABEL: rori_i32_fshl_nosext: ; RV64IBB: # %bb.0: -; RV64IBB-NEXT: srliw a2, a0, 1 -; RV64IBB-NEXT: slli a0, a0, 31 -; RV64IBB-NEXT: or a0, a0, a2 +; RV64IBB-NEXT: roriw a0, a0, 1 ; RV64IBB-NEXT: sw a0, 0(a1) ; RV64IBB-NEXT: ret ; ; RV64IBP-LABEL: rori_i32_fshl_nosext: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: srliw a2, a0, 1 -; RV64IBP-NEXT: slli a0, a0, 31 -; RV64IBP-NEXT: or a0, a0, a2 +; RV64IBP-NEXT: roriw a0, a0, 1 ; RV64IBP-NEXT: sw a0, 0(a1) ; RV64IBP-NEXT: ret %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 31) @@ -440,7 +433,6 @@ define signext i32 @rori_i32_fshr(i32 signext %a) nounwind { } ; Similar to rori_i32_fshr, but doesn't sign extend the result. -; FIXME: We should be using RORIW, but we need a sext_inreg. define void @rori_i32_fshr_nosext(i32 signext %a, i32* %x) nounwind { ; RV64I-LABEL: rori_i32_fshr_nosext: ; RV64I: # %bb.0: @@ -452,25 +444,19 @@ define void @rori_i32_fshr_nosext(i32 signext %a, i32* %x) nounwind { ; ; RV64IB-LABEL: rori_i32_fshr_nosext: ; RV64IB: # %bb.0: -; RV64IB-NEXT: slli a2, a0, 1 -; RV64IB-NEXT: srliw a0, a0, 31 -; RV64IB-NEXT: or a0, a0, a2 +; RV64IB-NEXT: roriw a0, a0, 31 ; RV64IB-NEXT: sw a0, 0(a1) ; RV64IB-NEXT: ret ; ; RV64IBB-LABEL: rori_i32_fshr_nosext: ; RV64IBB: # %bb.0: -; RV64IBB-NEXT: slli a2, a0, 1 -; RV64IBB-NEXT: srliw a0, a0, 31 -; RV64IBB-NEXT: or a0, a0, a2 +; RV64IBB-NEXT: roriw a0, a0, 31 ; RV64IBB-NEXT: sw a0, 0(a1) ; RV64IBB-NEXT: ret ; ; RV64IBP-LABEL: rori_i32_fshr_nosext: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: slli a2, a0, 1 -; RV64IBP-NEXT: srliw a0, a0, 31 -; RV64IBP-NEXT: or a0, a0, a2 +; RV64IBP-NEXT: roriw a0, a0, 31 ; RV64IBP-NEXT: sw a0, 0(a1) ; RV64IBP-NEXT: ret %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 31) diff --git a/llvm/test/CodeGen/RISCV/rv64Zbp.ll b/llvm/test/CodeGen/RISCV/rv64Zbp.ll index 3a57967f51837..763e85dc92209 100644 --- a/llvm/test/CodeGen/RISCV/rv64Zbp.ll +++ b/llvm/test/CodeGen/RISCV/rv64Zbp.ll @@ -571,7 +571,6 @@ define i64 @grev2_i64(i64 %a) nounwind { ret i64 %or } -; FIXME: we should generate greviw 3 here define signext i32 @grev3_i32(i32 signext %a) nounwind { ; RV64I-LABEL: grev3_i32: ; RV64I: # %bb.0: @@ -600,14 +599,12 @@ define signext i32 @grev3_i32(i32 signext %a) nounwind { ; ; RV64IB-LABEL: grev3_i32: ; RV64IB: # %bb.0: -; RV64IB-NEXT: greviw a0, a0, 1 -; RV64IB-NEXT: greviw a0, a0, 2 +; RV64IB-NEXT: greviw a0, a0, 3 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: grev3_i32: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: greviw a0, a0, 1 -; RV64IBP-NEXT: greviw a0, a0, 2 +; RV64IBP-NEXT: greviw a0, a0, 3 ; RV64IBP-NEXT: ret %and1 = shl i32 %a, 1 %shl1 = and i32 %and1, -1431655766 @@ -622,7 +619,6 @@ define signext i32 @grev3_i32(i32 signext %a) nounwind { ret i32 %or2 } -; FIXME: we should generate grevi 3 here define i64 @grev3_i64(i64 %a) nounwind { ; RV64I-LABEL: grev3_i64: ; RV64I: # %bb.0: @@ -672,14 +668,12 @@ define i64 @grev3_i64(i64 %a) nounwind { ; ; RV64IB-LABEL: grev3_i64: ; RV64IB: # %bb.0: -; RV64IB-NEXT: rev.p a0, a0 -; RV64IB-NEXT: rev2.n a0, a0 +; RV64IB-NEXT: rev.n a0, a0 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: grev3_i64: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: rev.p a0, a0 -; RV64IBP-NEXT: rev2.n a0, a0 +; RV64IBP-NEXT: rev.n a0, a0 ; RV64IBP-NEXT: ret %and1 = shl i64 %a, 1 %shl1 = and i64 %and1, -6148914691236517206 @@ -771,7 +765,6 @@ define i64 @grev4_i64(i64 %a) nounwind { ret i64 %or } -; FIXME: we should generate greviw 5 here define signext i32 @grev5_i32(i32 signext %a) nounwind { ; RV64I-LABEL: grev5_i32: ; RV64I: # %bb.0: @@ -800,14 +793,12 @@ define signext i32 @grev5_i32(i32 signext %a) nounwind { ; ; RV64IB-LABEL: grev5_i32: ; RV64IB: # %bb.0: -; RV64IB-NEXT: greviw a0, a0, 1 -; RV64IB-NEXT: greviw a0, a0, 4 +; RV64IB-NEXT: greviw a0, a0, 5 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: grev5_i32: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: greviw a0, a0, 1 -; RV64IBP-NEXT: greviw a0, a0, 4 +; RV64IBP-NEXT: greviw a0, a0, 5 ; RV64IBP-NEXT: ret %and1 = shl i32 %a, 1 %shl1 = and i32 %and1, -1431655766 @@ -822,7 +813,6 @@ define signext i32 @grev5_i32(i32 signext %a) nounwind { ret i32 %or2 } -; FIXME: we should generate grevi 5 here define i64 @grev5_i64(i64 %a) nounwind { ; RV64I-LABEL: grev5_i64: ; RV64I: # %bb.0: @@ -872,14 +862,12 @@ define i64 @grev5_i64(i64 %a) nounwind { ; ; RV64IB-LABEL: grev5_i64: ; RV64IB: # %bb.0: -; RV64IB-NEXT: rev.p a0, a0 -; RV64IB-NEXT: rev4.b a0, a0 +; RV64IB-NEXT: grevi a0, a0, 5 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: grev5_i64: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: rev.p a0, a0 -; RV64IBP-NEXT: rev4.b a0, a0 +; RV64IBP-NEXT: grevi a0, a0, 5 ; RV64IBP-NEXT: ret %and1 = shl i64 %a, 1 %shl1 = and i64 %and1, -6148914691236517206 @@ -895,7 +883,6 @@ define i64 @grev5_i64(i64 %a) nounwind { ret i64 %or2 } -; FIXME: we should generate greviw 6 here define signext i32 @grev6_i32(i32 signext %a) nounwind { ; RV64I-LABEL: grev6_i32: ; RV64I: # %bb.0: @@ -924,14 +911,12 @@ define signext i32 @grev6_i32(i32 signext %a) nounwind { ; ; RV64IB-LABEL: grev6_i32: ; RV64IB: # %bb.0: -; RV64IB-NEXT: greviw a0, a0, 2 -; RV64IB-NEXT: greviw a0, a0, 4 +; RV64IB-NEXT: greviw a0, a0, 6 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: grev6_i32: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: greviw a0, a0, 2 -; RV64IBP-NEXT: greviw a0, a0, 4 +; RV64IBP-NEXT: greviw a0, a0, 6 ; RV64IBP-NEXT: ret %and1 = shl i32 %a, 2 %shl1 = and i32 %and1, -858993460 @@ -946,7 +931,6 @@ define signext i32 @grev6_i32(i32 signext %a) nounwind { ret i32 %or2 } -; FIXME: we should generate grevi 6 here define i64 @grev6_i64(i64 %a) nounwind { ; RV64I-LABEL: grev6_i64: ; RV64I: # %bb.0: @@ -996,14 +980,12 @@ define i64 @grev6_i64(i64 %a) nounwind { ; ; RV64IB-LABEL: grev6_i64: ; RV64IB: # %bb.0: -; RV64IB-NEXT: rev2.n a0, a0 -; RV64IB-NEXT: rev4.b a0, a0 +; RV64IB-NEXT: rev2.b a0, a0 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: grev6_i64: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: rev2.n a0, a0 -; RV64IBP-NEXT: rev4.b a0, a0 +; RV64IBP-NEXT: rev2.b a0, a0 ; RV64IBP-NEXT: ret %and1 = shl i64 %a, 2 %shl1 = and i64 %and1, -3689348814741910324 @@ -1018,7 +1000,6 @@ define i64 @grev6_i64(i64 %a) nounwind { ret i64 %or2 } -; FIXME: we should generate greviw 7 here define signext i32 @grev7_i32(i32 signext %a) nounwind { ; RV64I-LABEL: grev7_i32: ; RV64I: # %bb.0: @@ -1056,16 +1037,12 @@ define signext i32 @grev7_i32(i32 signext %a) nounwind { ; ; RV64IB-LABEL: grev7_i32: ; RV64IB: # %bb.0: -; RV64IB-NEXT: greviw a0, a0, 1 -; RV64IB-NEXT: greviw a0, a0, 2 -; RV64IB-NEXT: greviw a0, a0, 4 +; RV64IB-NEXT: greviw a0, a0, 7 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: grev7_i32: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: greviw a0, a0, 1 -; RV64IBP-NEXT: greviw a0, a0, 2 -; RV64IBP-NEXT: greviw a0, a0, 4 +; RV64IBP-NEXT: greviw a0, a0, 7 ; RV64IBP-NEXT: ret %and1 = shl i32 %a, 1 %shl1 = and i32 %and1, -1431655766 @@ -1085,7 +1062,6 @@ define signext i32 @grev7_i32(i32 signext %a) nounwind { ret i32 %or3 } -; FIXME: we should generate grevi 7 here define i64 @grev7_i64(i64 %a) nounwind { ; RV64I-LABEL: grev7_i64: ; RV64I: # %bb.0: @@ -1156,16 +1132,12 @@ define i64 @grev7_i64(i64 %a) nounwind { ; ; RV64IB-LABEL: grev7_i64: ; RV64IB: # %bb.0: -; RV64IB-NEXT: rev.p a0, a0 -; RV64IB-NEXT: rev2.n a0, a0 -; RV64IB-NEXT: rev4.b a0, a0 +; RV64IB-NEXT: rev.b a0, a0 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: grev7_i64: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: rev.p a0, a0 -; RV64IBP-NEXT: rev2.n a0, a0 -; RV64IBP-NEXT: rev4.b a0, a0 +; RV64IBP-NEXT: rev.b a0, a0 ; RV64IBP-NEXT: ret %and1 = shl i64 %a, 1 %shl1 = and i64 %and1, -6148914691236517206 @@ -1377,12 +1349,12 @@ define i64 @grev32(i64 %a) nounwind { ; ; RV64IB-LABEL: grev32: ; RV64IB: # %bb.0: -; RV64IB-NEXT: rev32 a0, a0 +; RV64IB-NEXT: rori a0, a0, 32 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: grev32: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: rev32 a0, a0 +; RV64IBP-NEXT: rori a0, a0, 32 ; RV64IBP-NEXT: ret %shl = shl i64 %a, 32 %shr = lshr i64 %a, 32 @@ -1390,6 +1362,421 @@ define i64 @grev32(i64 %a) nounwind { ret i64 %or } +define signext i32 @grev3b_i32(i32 signext %a) nounwind { +; RV64I-LABEL: grev3b_i32: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a0, 2 +; RV64I-NEXT: lui a2, 838861 +; RV64I-NEXT: addiw a2, a2, -820 +; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: lui a2, 209715 +; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: slli a1, a0, 1 +; RV64I-NEXT: lui a2, 171 +; RV64I-NEXT: addiw a2, a2, -1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -1366 +; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: srli a0, a0, 1 +; RV64I-NEXT: lui a2, 349525 +; RV64I-NEXT: addiw a2, a2, 1365 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: sext.w a0, a0 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: grev3b_i32: +; RV64IB: # %bb.0: +; RV64IB-NEXT: greviw a0, a0, 3 +; RV64IB-NEXT: ret +; +; RV64IBP-LABEL: grev3b_i32: +; RV64IBP: # %bb.0: +; RV64IBP-NEXT: greviw a0, a0, 3 +; RV64IBP-NEXT: ret + %and2 = shl i32 %a, 2 + %shl2 = and i32 %and2, -858993460 + %and2b = lshr i32 %a, 2 + %shr2 = and i32 %and2b, 858993459 + %or2 = or i32 %shl2, %shr2 + %and1 = shl i32 %or2, 1 + %shl1 = and i32 %and1, -1431655766 + %and1b = lshr i32 %or2, 1 + %shr1 = and i32 %and1b, 1431655765 + %or1 = or i32 %shl1, %shr1 + ret i32 %or1 +} + +define i64 @grev3b_i64(i64 %a) nounwind { +; RV64I-LABEL: grev3b_i64: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a0, 2 +; RV64I-NEXT: lui a2, 1035469 +; RV64I-NEXT: addiw a2, a2, -819 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -819 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -819 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -820 +; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: lui a2, 13107 +; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, 819 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, 819 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, 819 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: slli a1, a0, 1 +; RV64I-NEXT: lui a2, 1026731 +; RV64I-NEXT: addiw a2, a2, -1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -1366 +; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: srli a0, a0, 1 +; RV64I-NEXT: lui a2, 21845 +; RV64I-NEXT: addiw a2, a2, 1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, 1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, 1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, 1365 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: grev3b_i64: +; RV64IB: # %bb.0: +; RV64IB-NEXT: rev.n a0, a0 +; RV64IB-NEXT: ret +; +; RV64IBP-LABEL: grev3b_i64: +; RV64IBP: # %bb.0: +; RV64IBP-NEXT: rev.n a0, a0 +; RV64IBP-NEXT: ret + %and2 = shl i64 %a, 2 + %shl2 = and i64 %and2, -3689348814741910324 + %and2b = lshr i64 %a, 2 + %shr2 = and i64 %and2b, 3689348814741910323 + %or2 = or i64 %shl2, %shr2 + %and1 = shl i64 %or2, 1 + %shl1 = and i64 %and1, -6148914691236517206 + %and1b = lshr i64 %or2, 1 + %shr1 = and i64 %and1b, 6148914691236517205 + %or1 = or i64 %shl1, %shr1 + ret i64 %or1 +} + +; grev1, grev2, grev1 -> grev2 +define signext i32 @grev2b_i32(i32 signext %a) nounwind { +; RV64I-LABEL: grev2b_i32: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a0, 1 +; RV64I-NEXT: lui a2, 699051 +; RV64I-NEXT: addiw a2, a2, -1366 +; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: srli a0, a0, 1 +; RV64I-NEXT: lui a2, 349525 +; RV64I-NEXT: addiw a2, a2, 1365 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: slli a1, a0, 2 +; RV64I-NEXT: lui a3, 838861 +; RV64I-NEXT: addiw a3, a3, -820 +; RV64I-NEXT: and a1, a1, a3 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: lui a3, 209715 +; RV64I-NEXT: addiw a3, a3, 819 +; RV64I-NEXT: and a0, a0, a3 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: slli a1, a0, 1 +; RV64I-NEXT: lui a3, 171 +; RV64I-NEXT: addiw a3, a3, -1365 +; RV64I-NEXT: slli a3, a3, 12 +; RV64I-NEXT: addi a3, a3, -1366 +; RV64I-NEXT: and a1, a1, a3 +; RV64I-NEXT: srli a0, a0, 1 +; RV64I-NEXT: and a0, a0, a2 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: sext.w a0, a0 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: grev2b_i32: +; RV64IB: # %bb.0: +; RV64IB-NEXT: greviw a0, a0, 2 +; RV64IB-NEXT: ret +; +; RV64IBP-LABEL: grev2b_i32: +; RV64IBP: # %bb.0: +; RV64IBP-NEXT: greviw a0, a0, 2 +; RV64IBP-NEXT: ret + %and1 = shl i32 %a, 1 + %shl1 = and i32 %and1, -1431655766 + %and1b = lshr i32 %a, 1 + %shr1 = and i32 %and1b, 1431655765 + %or1 = or i32 %shl1, %shr1 + %and2 = shl i32 %or1, 2 + %shl2 = and i32 %and2, -858993460 + %and2b = lshr i32 %or1, 2 + %shr2 = and i32 %and2b, 858993459 + %or2 = or i32 %shl2, %shr2 + %and3 = shl i32 %or2, 1 + %shl3 = and i32 %and3, -1431655766 + %and3b = lshr i32 %or2, 1 + %shr3 = and i32 %and3b, 1431655765 + %or3 = or i32 %shl3, %shr3 + ret i32 %or3 +} + +; grev1, grev2, grev1 -> grev2 +define i64 @grev2b_i64(i64 %a) nounwind { +; RV64I-LABEL: grev2b_i64: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a0, 1 +; RV64I-NEXT: lui a2, 1026731 +; RV64I-NEXT: addiw a2, a2, -1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -1366 +; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: srli a0, a0, 1 +; RV64I-NEXT: lui a3, 21845 +; RV64I-NEXT: addiw a3, a3, 1365 +; RV64I-NEXT: slli a3, a3, 12 +; RV64I-NEXT: addi a3, a3, 1365 +; RV64I-NEXT: slli a3, a3, 12 +; RV64I-NEXT: addi a3, a3, 1365 +; RV64I-NEXT: slli a3, a3, 12 +; RV64I-NEXT: addi a3, a3, 1365 +; RV64I-NEXT: and a0, a0, a3 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: slli a1, a0, 2 +; RV64I-NEXT: lui a4, 1035469 +; RV64I-NEXT: addiw a4, a4, -819 +; RV64I-NEXT: slli a4, a4, 12 +; RV64I-NEXT: addi a4, a4, -819 +; RV64I-NEXT: slli a4, a4, 12 +; RV64I-NEXT: addi a4, a4, -819 +; RV64I-NEXT: slli a4, a4, 12 +; RV64I-NEXT: addi a4, a4, -820 +; RV64I-NEXT: and a1, a1, a4 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: lui a4, 13107 +; RV64I-NEXT: addiw a4, a4, 819 +; RV64I-NEXT: slli a4, a4, 12 +; RV64I-NEXT: addi a4, a4, 819 +; RV64I-NEXT: slli a4, a4, 12 +; RV64I-NEXT: addi a4, a4, 819 +; RV64I-NEXT: slli a4, a4, 12 +; RV64I-NEXT: addi a4, a4, 819 +; RV64I-NEXT: and a0, a0, a4 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: slli a1, a0, 1 +; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: srli a0, a0, 1 +; RV64I-NEXT: and a0, a0, a3 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: grev2b_i64: +; RV64IB: # %bb.0: +; RV64IB-NEXT: rev2.n a0, a0 +; RV64IB-NEXT: ret +; +; RV64IBP-LABEL: grev2b_i64: +; RV64IBP: # %bb.0: +; RV64IBP-NEXT: rev2.n a0, a0 +; RV64IBP-NEXT: ret + %and1 = shl i64 %a, 1 + %shl1 = and i64 %and1, -6148914691236517206 + %and1b = lshr i64 %a, 1 + %shr1 = and i64 %and1b, 6148914691236517205 + %or1 = or i64 %shl1, %shr1 + %and2 = shl i64 %or1, 2 + %shl2 = and i64 %and2, -3689348814741910324 + %and2b = lshr i64 %or1, 2 + %shr2 = and i64 %and2b, 3689348814741910323 + %or2 = or i64 %shl2, %shr2 + %and3 = shl i64 %or2, 1 + %shl3 = and i64 %and3, -6148914691236517206 + %and3b = lshr i64 %or2, 1 + %shr3 = and i64 %and3b, 6148914691236517205 + %or3 = or i64 %shl3, %shr3 + ret i64 %or3 +} + +; grev1, grev2, grev1, grev2 -> identity +define signext i32 @grev0_i32(i32 signext %a) nounwind { +; RV64I-LABEL: grev0_i32: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a0, 1 +; RV64I-NEXT: lui a2, 699051 +; RV64I-NEXT: addiw a2, a2, -1366 +; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: srli a0, a0, 1 +; RV64I-NEXT: lui a3, 349525 +; RV64I-NEXT: addiw a3, a3, 1365 +; RV64I-NEXT: and a0, a0, a3 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: slli a1, a0, 2 +; RV64I-NEXT: lui a4, 838861 +; RV64I-NEXT: addiw a4, a4, -820 +; RV64I-NEXT: and a1, a1, a4 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: lui a4, 209715 +; RV64I-NEXT: addiw a4, a4, 819 +; RV64I-NEXT: and a0, a0, a4 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: slli a1, a0, 1 +; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: srli a0, a0, 1 +; RV64I-NEXT: and a0, a0, a3 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: slli a1, a0, 2 +; RV64I-NEXT: lui a2, 205 +; RV64I-NEXT: addiw a2, a2, -819 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -820 +; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: and a0, a0, a4 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: sext.w a0, a0 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: grev0_i32: +; RV64IB: # %bb.0: +; RV64IB-NEXT: ret +; +; RV64IBP-LABEL: grev0_i32: +; RV64IBP: # %bb.0: +; RV64IBP-NEXT: ret + %and1 = shl i32 %a, 1 + %shl1 = and i32 %and1, -1431655766 + %and1b = lshr i32 %a, 1 + %shr1 = and i32 %and1b, 1431655765 + %or1 = or i32 %shl1, %shr1 + %and2 = shl i32 %or1, 2 + %shl2 = and i32 %and2, -858993460 + %and2b = lshr i32 %or1, 2 + %shr2 = and i32 %and2b, 858993459 + %or2 = or i32 %shl2, %shr2 + %and3 = shl i32 %or2, 1 + %shl3 = and i32 %and3, -1431655766 + %and3b = lshr i32 %or2, 1 + %shr3 = and i32 %and3b, 1431655765 + %or3 = or i32 %shl3, %shr3 + %and4 = shl i32 %or3, 2 + %shl4 = and i32 %and4, -858993460 + %and4b = lshr i32 %or3, 2 + %shr4 = and i32 %and4b, 858993459 + %or4 = or i32 %shl4, %shr4 + ret i32 %or4 +} + +; grev1, grev2, grev1, grev2 -> identity +define i64 @grev0_i64(i64 %a) nounwind { +; RV64I-LABEL: grev0_i64: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a0, 1 +; RV64I-NEXT: lui a2, 1026731 +; RV64I-NEXT: addiw a2, a2, -1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -1365 +; RV64I-NEXT: slli a2, a2, 12 +; RV64I-NEXT: addi a2, a2, -1366 +; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: srli a0, a0, 1 +; RV64I-NEXT: lui a3, 21845 +; RV64I-NEXT: addiw a3, a3, 1365 +; RV64I-NEXT: slli a3, a3, 12 +; RV64I-NEXT: addi a3, a3, 1365 +; RV64I-NEXT: slli a3, a3, 12 +; RV64I-NEXT: addi a3, a3, 1365 +; RV64I-NEXT: slli a3, a3, 12 +; RV64I-NEXT: addi a3, a3, 1365 +; RV64I-NEXT: and a0, a0, a3 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: slli a1, a0, 2 +; RV64I-NEXT: lui a4, 1035469 +; RV64I-NEXT: addiw a4, a4, -819 +; RV64I-NEXT: slli a4, a4, 12 +; RV64I-NEXT: addi a4, a4, -819 +; RV64I-NEXT: slli a4, a4, 12 +; RV64I-NEXT: addi a4, a4, -819 +; RV64I-NEXT: slli a4, a4, 12 +; RV64I-NEXT: addi a4, a4, -820 +; RV64I-NEXT: and a1, a1, a4 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: lui a5, 13107 +; RV64I-NEXT: addiw a5, a5, 819 +; RV64I-NEXT: slli a5, a5, 12 +; RV64I-NEXT: addi a5, a5, 819 +; RV64I-NEXT: slli a5, a5, 12 +; RV64I-NEXT: addi a5, a5, 819 +; RV64I-NEXT: slli a5, a5, 12 +; RV64I-NEXT: addi a5, a5, 819 +; RV64I-NEXT: and a0, a0, a5 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: slli a1, a0, 1 +; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: srli a0, a0, 1 +; RV64I-NEXT: and a0, a0, a3 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: slli a1, a0, 2 +; RV64I-NEXT: and a1, a1, a4 +; RV64I-NEXT: srli a0, a0, 2 +; RV64I-NEXT: and a0, a0, a5 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: grev0_i64: +; RV64IB: # %bb.0: +; RV64IB-NEXT: ret +; +; RV64IBP-LABEL: grev0_i64: +; RV64IBP: # %bb.0: +; RV64IBP-NEXT: ret + %and1 = shl i64 %a, 1 + %shl1 = and i64 %and1, -6148914691236517206 + %and1b = lshr i64 %a, 1 + %shr1 = and i64 %and1b, 6148914691236517205 + %or1 = or i64 %shl1, %shr1 + %and2 = shl i64 %or1, 2 + %shl2 = and i64 %and2, -3689348814741910324 + %and2b = lshr i64 %or1, 2 + %shr2 = and i64 %and2b, 3689348814741910323 + %or2 = or i64 %shl2, %shr2 + %and3 = shl i64 %or2, 1 + %shl3 = and i64 %and3, -6148914691236517206 + %and3b = lshr i64 %or2, 1 + %shr3 = and i64 %and3b, 6148914691236517205 + %or3 = or i64 %shl3, %shr3 + %and4 = shl i64 %or3, 2 + %shl4 = and i64 %and4, -3689348814741910324 + %and4b = lshr i64 %or3, 2 + %shr4 = and i64 %and4b, 3689348814741910323 + %or4 = or i64 %shl4, %shr4 + ret i64 %or4 +} + declare i64 @llvm.fshl.i64(i64, i64, i64) declare i64 @llvm.fshr.i64(i64, i64, i64) @@ -1403,12 +1790,12 @@ define i64 @grev32_fshl(i64 %a) nounwind { ; ; RV64IB-LABEL: grev32_fshl: ; RV64IB: # %bb.0: -; RV64IB-NEXT: rev32 a0, a0 +; RV64IB-NEXT: rori a0, a0, 32 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: grev32_fshl: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: rev32 a0, a0 +; RV64IBP-NEXT: rori a0, a0, 32 ; RV64IBP-NEXT: ret %or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 32) ret i64 %or @@ -1424,12 +1811,12 @@ define i64 @grev32_fshr(i64 %a) nounwind { ; ; RV64IB-LABEL: grev32_fshr: ; RV64IB: # %bb.0: -; RV64IB-NEXT: rev32 a0, a0 +; RV64IB-NEXT: rori a0, a0, 32 ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: grev32_fshr: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: rev32 a0, a0 +; RV64IBP-NEXT: rori a0, a0, 32 ; RV64IBP-NEXT: ret %or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 32) ret i64 %or @@ -1495,15 +1882,13 @@ define void @bswap_i32_nosext(i32 signext %a, i32* %x) nounwind { ; ; RV64IB-LABEL: bswap_i32_nosext: ; RV64IB: # %bb.0: -; RV64IB-NEXT: rev8 a0, a0 -; RV64IB-NEXT: srli a0, a0, 32 +; RV64IB-NEXT: greviw a0, a0, 24 ; RV64IB-NEXT: sw a0, 0(a1) ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: bswap_i32_nosext: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: rev8 a0, a0 -; RV64IBP-NEXT: srli a0, a0, 32 +; RV64IBP-NEXT: greviw a0, a0, 24 ; RV64IBP-NEXT: sw a0, 0(a1) ; RV64IBP-NEXT: ret %1 = tail call i32 @llvm.bswap.i32(i32 %a) @@ -1756,15 +2141,13 @@ define void @bitreverse_i32_nosext(i32 signext %a, i32* %x) nounwind { ; ; RV64IB-LABEL: bitreverse_i32_nosext: ; RV64IB: # %bb.0: -; RV64IB-NEXT: rev a0, a0 -; RV64IB-NEXT: srli a0, a0, 32 +; RV64IB-NEXT: greviw a0, a0, 31 ; RV64IB-NEXT: sw a0, 0(a1) ; RV64IB-NEXT: ret ; ; RV64IBP-LABEL: bitreverse_i32_nosext: ; RV64IBP: # %bb.0: -; RV64IBP-NEXT: rev a0, a0 -; RV64IBP-NEXT: srli a0, a0, 32 +; RV64IBP-NEXT: greviw a0, a0, 31 ; RV64IBP-NEXT: sw a0, 0(a1) ; RV64IBP-NEXT: ret %1 = tail call i32 @llvm.bitreverse.i32(i32 %a) diff --git a/llvm/test/CodeGen/RISCV/rv64Zbs.ll b/llvm/test/CodeGen/RISCV/rv64Zbs.ll index c81eb7176d621..e50b7a24c536e 100644 --- a/llvm/test/CodeGen/RISCV/rv64Zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv64Zbs.ll @@ -55,6 +55,35 @@ define signext i32 @sbclr_i32_no_mask(i32 signext %a, i32 signext %b) nounwind { ret i32 %and1 } +define signext i32 @sbclr_i32_load(i32* %p, i32 signext %b) nounwind { +; RV64I-LABEL: sbclr_i32_load: +; RV64I: # %bb.0: +; RV64I-NEXT: lw a0, 0(a0) +; RV64I-NEXT: addi a2, zero, 1 +; RV64I-NEXT: sllw a1, a2, a1 +; RV64I-NEXT: not a1, a1 +; RV64I-NEXT: and a0, a1, a0 +; RV64I-NEXT: sext.w a0, a0 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: sbclr_i32_load: +; RV64IB: # %bb.0: +; RV64IB-NEXT: lw a0, 0(a0) +; RV64IB-NEXT: sbclrw a0, a0, a1 +; RV64IB-NEXT: ret +; +; RV64IBS-LABEL: sbclr_i32_load: +; RV64IBS: # %bb.0: +; RV64IBS-NEXT: lw a0, 0(a0) +; RV64IBS-NEXT: sbclrw a0, a0, a1 +; RV64IBS-NEXT: ret + %a = load i32, i32* %p + %shl = shl i32 1, %b + %neg = xor i32 %shl, -1 + %and1 = and i32 %neg, %a + ret i32 %and1 +} + define i64 @sbclr_i64(i64 %a, i64 %b) nounwind { ; RV64I-LABEL: sbclr_i64: ; RV64I: # %bb.0: @@ -149,6 +178,54 @@ define signext i32 @sbset_i32_no_mask(i32 signext %a, i32 signext %b) nounwind { ret i32 %or } +define signext i32 @sbset_i32_load(i32* %p, i32 signext %b) nounwind { +; RV64I-LABEL: sbset_i32_load: +; RV64I: # %bb.0: +; RV64I-NEXT: lw a0, 0(a0) +; RV64I-NEXT: addi a2, zero, 1 +; RV64I-NEXT: sllw a1, a2, a1 +; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: sext.w a0, a0 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: sbset_i32_load: +; RV64IB: # %bb.0: +; RV64IB-NEXT: lw a0, 0(a0) +; RV64IB-NEXT: sbsetw a0, a0, a1 +; RV64IB-NEXT: ret +; +; RV64IBS-LABEL: sbset_i32_load: +; RV64IBS: # %bb.0: +; RV64IBS-NEXT: lw a0, 0(a0) +; RV64IBS-NEXT: sbsetw a0, a0, a1 +; RV64IBS-NEXT: ret + %a = load i32, i32* %p + %shl = shl i32 1, %b + %or = or i32 %shl, %a + ret i32 %or +} + +; We can use sbsetw for 1 << x by setting the first source to zero. +define signext i32 @sbset_i32_zero(i32 signext %a) nounwind { +; RV64I-LABEL: sbset_i32_zero: +; RV64I: # %bb.0: +; RV64I-NEXT: addi a1, zero, 1 +; RV64I-NEXT: sllw a0, a1, a0 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: sbset_i32_zero: +; RV64IB: # %bb.0: +; RV64IB-NEXT: sbsetw a0, zero, a0 +; RV64IB-NEXT: ret +; +; RV64IBS-LABEL: sbset_i32_zero: +; RV64IBS: # %bb.0: +; RV64IBS-NEXT: sbsetw a0, zero, a0 +; RV64IBS-NEXT: ret + %shl = shl i32 1, %a + ret i32 %shl +} + define i64 @sbset_i64(i64 %a, i64 %b) nounwind { ; RV64I-LABEL: sbset_i64: ; RV64I: # %bb.0: @@ -194,6 +271,27 @@ define i64 @sbset_i64_no_mask(i64 %a, i64 %b) nounwind { ret i64 %or } +; We can use sbsetw for 1 << x by setting the first source to zero. +define signext i64 @sbset_i64_zero(i64 signext %a) nounwind { +; RV64I-LABEL: sbset_i64_zero: +; RV64I: # %bb.0: +; RV64I-NEXT: addi a1, zero, 1 +; RV64I-NEXT: sll a0, a1, a0 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: sbset_i64_zero: +; RV64IB: # %bb.0: +; RV64IB-NEXT: sbset a0, zero, a0 +; RV64IB-NEXT: ret +; +; RV64IBS-LABEL: sbset_i64_zero: +; RV64IBS: # %bb.0: +; RV64IBS-NEXT: sbset a0, zero, a0 +; RV64IBS-NEXT: ret + %shl = shl i64 1, %a + ret i64 %shl +} + define signext i32 @sbinv_i32(i32 signext %a, i32 signext %b) nounwind { ; RV64I-LABEL: sbinv_i32: ; RV64I: # %bb.0: @@ -239,6 +337,33 @@ define signext i32 @sbinv_i32_no_mask(i32 signext %a, i32 signext %b) nounwind { ret i32 %xor } +define signext i32 @sbinv_i32_load(i32* %p, i32 signext %b) nounwind { +; RV64I-LABEL: sbinv_i32_load: +; RV64I: # %bb.0: +; RV64I-NEXT: lw a0, 0(a0) +; RV64I-NEXT: addi a2, zero, 1 +; RV64I-NEXT: sllw a1, a2, a1 +; RV64I-NEXT: xor a0, a1, a0 +; RV64I-NEXT: sext.w a0, a0 +; RV64I-NEXT: ret +; +; RV64IB-LABEL: sbinv_i32_load: +; RV64IB: # %bb.0: +; RV64IB-NEXT: lw a0, 0(a0) +; RV64IB-NEXT: sbinvw a0, a0, a1 +; RV64IB-NEXT: ret +; +; RV64IBS-LABEL: sbinv_i32_load: +; RV64IBS: # %bb.0: +; RV64IBS-NEXT: lw a0, 0(a0) +; RV64IBS-NEXT: sbinvw a0, a0, a1 +; RV64IBS-NEXT: ret + %a = load i32, i32* %p + %shl = shl i32 1, %b + %xor = xor i32 %shl, %a + ret i32 %xor +} + define i64 @sbinv_i64(i64 %a, i64 %b) nounwind { ; RV64I-LABEL: sbinv_i64: ; RV64I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/rv64Zbt.ll b/llvm/test/CodeGen/RISCV/rv64Zbt.ll index d88a2adffb113..cb8205b141dfd 100644 --- a/llvm/test/CodeGen/RISCV/rv64Zbt.ll +++ b/llvm/test/CodeGen/RISCV/rv64Zbt.ll @@ -134,7 +134,6 @@ define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nou } ; Similar to fshl_i32 but result is not sign extended. -; FIXME: This should use fslw define void @fshl_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32* %x) nounwind { ; RV64I-LABEL: fshl_i32_nosext: ; RV64I: # %bb.0: @@ -150,19 +149,15 @@ define void @fshl_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32 ; ; RV64IB-LABEL: fshl_i32_nosext: ; RV64IB: # %bb.0: -; RV64IB-NEXT: slli a1, a1, 32 ; RV64IB-NEXT: andi a2, a2, 31 -; RV64IB-NEXT: andi a2, a2, 63 -; RV64IB-NEXT: fsl a0, a0, a1, a2 +; RV64IB-NEXT: fslw a0, a0, a1, a2 ; RV64IB-NEXT: sw a0, 0(a3) ; RV64IB-NEXT: ret ; ; RV64IBT-LABEL: fshl_i32_nosext: ; RV64IBT: # %bb.0: -; RV64IBT-NEXT: slli a1, a1, 32 ; RV64IBT-NEXT: andi a2, a2, 31 -; RV64IBT-NEXT: andi a2, a2, 63 -; RV64IBT-NEXT: fsl a0, a0, a1, a2 +; RV64IBT-NEXT: fslw a0, a0, a1, a2 ; RV64IBT-NEXT: sw a0, 0(a3) ; RV64IBT-NEXT: ret %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c) @@ -227,7 +222,6 @@ define signext i32 @fshr_i32(i32 signext %a, i32 signext %b, i32 signext %c) nou } ; Similar to fshr_i32 but result is not sign extended. -; FIXME: This should use fsrw define void @fshr_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32* %x) nounwind { ; RV64I-LABEL: fshr_i32_nosext: ; RV64I: # %bb.0: @@ -242,19 +236,15 @@ define void @fshr_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32 ; ; RV64IB-LABEL: fshr_i32_nosext: ; RV64IB: # %bb.0: -; RV64IB-NEXT: slli a1, a1, 32 -; RV64IB-NEXT: ori a2, a2, 32 -; RV64IB-NEXT: andi a2, a2, 63 -; RV64IB-NEXT: fsr a0, a1, a0, a2 +; RV64IB-NEXT: andi a2, a2, 31 +; RV64IB-NEXT: fsrw a0, a1, a0, a2 ; RV64IB-NEXT: sw a0, 0(a3) ; RV64IB-NEXT: ret ; ; RV64IBT-LABEL: fshr_i32_nosext: ; RV64IBT: # %bb.0: -; RV64IBT-NEXT: slli a1, a1, 32 -; RV64IBT-NEXT: ori a2, a2, 32 -; RV64IBT-NEXT: andi a2, a2, 63 -; RV64IBT-NEXT: fsr a0, a1, a0, a2 +; RV64IBT-NEXT: andi a2, a2, 31 +; RV64IBT-NEXT: fsrw a0, a1, a0, a2 ; RV64IBT-NEXT: sw a0, 0(a3) ; RV64IBT-NEXT: ret %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c) @@ -312,7 +302,6 @@ define signext i32 @fshri_i32(i32 signext %a, i32 signext %b) nounwind { } ; Similar to fshr_i32 but result is not sign extended. -; FIXME: This should use fsriw define void @fshri_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind { ; RV64I-LABEL: fshri_i32_nosext: ; RV64I: # %bb.0: @@ -324,15 +313,13 @@ define void @fshri_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind ; ; RV64IB-LABEL: fshri_i32_nosext: ; RV64IB: # %bb.0: -; RV64IB-NEXT: slli a1, a1, 32 -; RV64IB-NEXT: fsri a0, a1, a0, 37 +; RV64IB-NEXT: fsriw a0, a1, a0, 5 ; RV64IB-NEXT: sw a0, 0(a2) ; RV64IB-NEXT: ret ; ; RV64IBT-LABEL: fshri_i32_nosext: ; RV64IBT: # %bb.0: -; RV64IBT-NEXT: slli a1, a1, 32 -; RV64IBT-NEXT: fsri a0, a1, a0, 37 +; RV64IBT-NEXT: fsriw a0, a1, a0, 5 ; RV64IBT-NEXT: sw a0, 0(a2) ; RV64IBT-NEXT: ret %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 5) @@ -384,7 +371,6 @@ define signext i32 @fshli_i32(i32 signext %a, i32 signext %b) nounwind { } ; Similar to fshl_i32 but result is not sign extended. -; FIXME: This should use fsriw define void @fshli_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind { ; RV64I-LABEL: fshli_i32_nosext: ; RV64I: # %bb.0: @@ -396,15 +382,13 @@ define void @fshli_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind ; ; RV64IB-LABEL: fshli_i32_nosext: ; RV64IB: # %bb.0: -; RV64IB-NEXT: slli a1, a1, 32 -; RV64IB-NEXT: fsri a0, a1, a0, 59 +; RV64IB-NEXT: fsriw a0, a1, a0, 27 ; RV64IB-NEXT: sw a0, 0(a2) ; RV64IB-NEXT: ret ; ; RV64IBT-LABEL: fshli_i32_nosext: ; RV64IBT: # %bb.0: -; RV64IBT-NEXT: slli a1, a1, 32 -; RV64IBT-NEXT: fsri a0, a1, a0, 59 +; RV64IBT-NEXT: fsriw a0, a1, a0, 27 ; RV64IBT-NEXT: sw a0, 0(a2) ; RV64IBT-NEXT: ret %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5) diff --git a/llvm/test/CodeGen/RISCV/tail-calls.ll b/llvm/test/CodeGen/RISCV/tail-calls.ll index c989df932a4be..7df14fc2ca10b 100644 --- a/llvm/test/CodeGen/RISCV/tail-calls.ll +++ b/llvm/test/CodeGen/RISCV/tail-calls.ll @@ -122,14 +122,14 @@ attributes #0 = { "interrupt"="machine" } ; Byval parameters hand the function a pointer directly into the stack area ; we want to reuse during a tail call. Do not tail call optimize functions with ; byval parameters. -declare i32 @callee_byval(i32** byval %a) +declare i32 @callee_byval(i32** byval(i32*) %a) define i32 @caller_byval() nounwind { ; CHECK-LABEL: caller_byval ; CHECK-NOT: tail callee_byval ; CHECK: call callee_byval entry: %a = alloca i32* - %r = tail call i32 @callee_byval(i32** byval %a) + %r = tail call i32 @callee_byval(i32** byval(i32*) %a) ret i32 %r } @@ -137,19 +137,19 @@ entry: %struct.A = type { i32 } @a = global %struct.A zeroinitializer -declare void @callee_struct(%struct.A* sret %a) +declare void @callee_struct(%struct.A* sret(%struct.A) %a) define void @caller_nostruct() nounwind { ; CHECK-LABEL: caller_nostruct ; CHECK-NOT: tail callee_struct ; CHECK: call callee_struct entry: - tail call void @callee_struct(%struct.A* sret @a) + tail call void @callee_struct(%struct.A* sret(%struct.A) @a) ret void } ; Do not tail call optimize if caller uses structret semantics. declare void @callee_nostruct() -define void @caller_struct(%struct.A* sret %a) nounwind { +define void @caller_struct(%struct.A* sret(%struct.A) %a) nounwind { ; CHECK-LABEL: caller_struct ; CHECK-NOT: tail callee_nostruct ; CHECK: call callee_nostruct diff --git a/llvm/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll b/llvm/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll index 408b13d70a38f..cd95fbcf052fc 100644 --- a/llvm/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll +++ b/llvm/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll @@ -11,8 +11,8 @@ entry: ;CHECK: st ;CHECK: st ;CHECK: bar - %0 = tail call i32 @bar(%struct.foo_t* byval @s) nounwind + %0 = tail call i32 @bar(%struct.foo_t* byval(%struct.foo_t) @s) nounwind ret i32 %0 } -declare i32 @bar(%struct.foo_t* byval) +declare i32 @bar(%struct.foo_t* byval(%struct.foo_t)) diff --git a/llvm/test/CodeGen/SPARC/2011-01-22-SRet.ll b/llvm/test/CodeGen/SPARC/2011-01-22-SRet.ll index 678544ebf2cb4..445edc9e89e8f 100644 --- a/llvm/test/CodeGen/SPARC/2011-01-22-SRet.ll +++ b/llvm/test/CodeGen/SPARC/2011-01-22-SRet.ll @@ -2,7 +2,7 @@ %struct.foo_t = type { i32, i32, i32 } -define weak void @make_foo(%struct.foo_t* noalias sret %agg.result, i32 %a, i32 %b, i32 %c) nounwind { +define weak void @make_foo(%struct.foo_t* noalias sret(%struct.foo_t) %agg.result, i32 %a, i32 %b, i32 %c) nounwind { entry: ;CHECK-LABEL: make_foo: ;CHECK: ld [%sp+64], {{.+}} @@ -23,7 +23,7 @@ entry: ;CHECK: st {{.+}}, [%sp+64] ;CHECK: unimp 12 %f = alloca %struct.foo_t, align 8 - call void @make_foo(%struct.foo_t* noalias sret %f, i32 10, i32 20, i32 30) nounwind + call void @make_foo(%struct.foo_t* noalias sret(%struct.foo_t) %f, i32 10, i32 20, i32 30) nounwind %0 = getelementptr inbounds %struct.foo_t, %struct.foo_t* %f, i32 0, i32 0 %1 = load i32, i32* %0, align 8 %2 = getelementptr inbounds %struct.foo_t, %struct.foo_t* %f, i32 0, i32 1 diff --git a/llvm/test/CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll b/llvm/test/CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll index c79414d279145..c4c022d9f72f2 100644 --- a/llvm/test/CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll +++ b/llvm/test/CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll @@ -19,7 +19,7 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop -define double @test_1(double* byval %a, double* byval %b) { +define double @test_1(double* byval(double) %a, double* byval(double) %b) { entry: %0 = load double, double* %a, align 8 %1 = load double, double* %b, align 8 @@ -50,7 +50,7 @@ declare double @llvm.sqrt.f64(double) nounwind readonly ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop -define double @test_2(double* byval %a) { +define double @test_2(double* byval(double) %a) { entry: %0 = load double, double* %a, align 8 %1 = call double @llvm.sqrt.f64(double %0) nounwind diff --git a/llvm/test/CodeGen/SPARC/LeonItinerariesUT.ll b/llvm/test/CodeGen/SPARC/LeonItinerariesUT.ll index 5a6be134686bb..796dcf2e145c8 100644 --- a/llvm/test/CodeGen/SPARC/LeonItinerariesUT.ll +++ b/llvm/test/CodeGen/SPARC/LeonItinerariesUT.ll @@ -4,39 +4,39 @@ ; RUN: llc < %s -O1 -march=sparc -mcpu=leon4 | FileCheck %s -check-prefix=LEON3_4_ITIN ; NO_ITIN-LABEL: f32_ops: -; NO_ITIN: ld -; NO_ITIN-NEXT: ld -; NO_ITIN-NEXT: ld -; NO_ITIN-NEXT: ld -; NO_ITIN-NEXT: fadds -; NO_ITIN-NEXT: fsubs -; NO_ITIN-NEXT: fmuls -; NO_ITIN-NEXT: retl -; NO_ITIN-NEXT: fdivs +; NO_ITIN: ld +; NO_ITIN-NEXT: ld +; NO_ITIN-NEXT: ld +; NO_ITIN-NEXT: ld +; NO_ITIN-NEXT: fadds +; NO_ITIN-NEXT: fsubs +; NO_ITIN-NEXT: fmuls +; NO_ITIN-NEXT: retl +; NO_ITIN-NEXT: fdivs ; LEON2_ITIN-LABEL: f32_ops: -; LEON2_ITIN: ld -; LEON2_ITIN-NEXT: ld -; LEON2_ITIN-NEXT: fadds -; LEON2_ITIN-NEXT: ld -; LEON2_ITIN-NEXT: fsubs -; LEON2_ITIN-NEXT: ld -; LEON2_ITIN-NEXT: fmuls -; LEON2_ITIN-NEXT: retl -; LEON2_ITIN-NEXT: fdivs +; LEON2_ITIN: ld +; LEON2_ITIN-NEXT: ld +; LEON2_ITIN-NEXT: fadds +; LEON2_ITIN-NEXT: ld +; LEON2_ITIN-NEXT: fsubs +; LEON2_ITIN-NEXT: ld +; LEON2_ITIN-NEXT: fmuls +; LEON2_ITIN-NEXT: retl +; LEON2_ITIN-NEXT: fdivs ; LEON3_4_ITIN-LABEL: f32_ops: -; LEON3_4_ITIN: ld -; LEON3_4_ITIN-NEXT: ld -; LEON3_4_ITIN-NEXT: ld -; LEON3_4_ITIN-NEXT: fadds -; LEON3_4_ITIN-NEXT: ld -; LEON3_4_ITIN-NEXT: fsubs -; LEON3_4_ITIN-NEXT: fmuls -; LEON3_4_ITIN-NEXT: retl -; LEON3_4_ITIN-NEXT: fdivs +; LEON3_4_ITIN: ld +; LEON3_4_ITIN-NEXT: ld +; LEON3_4_ITIN-NEXT: ld +; LEON3_4_ITIN-NEXT: fadds +; LEON3_4_ITIN-NEXT: ld +; LEON3_4_ITIN-NEXT: fsubs +; LEON3_4_ITIN-NEXT: fmuls +; LEON3_4_ITIN-NEXT: retl +; LEON3_4_ITIN-NEXT: fdivs -define float @f32_ops(float* byval %a, float* byval %b, float* byval %c, float* byval %d) { +define float @f32_ops(float* byval(float) %a, float* byval(float) %b, float* byval(float) %c, float* byval(float) %d) { entry: %0 = load float, float* %a, align 8 %1 = load float, float* %b, align 8 diff --git a/llvm/test/CodeGen/SPARC/cast-sret-func.ll b/llvm/test/CodeGen/SPARC/cast-sret-func.ll index 1503e278c7da4..192a5ef7567ec 100644 --- a/llvm/test/CodeGen/SPARC/cast-sret-func.ll +++ b/llvm/test/CodeGen/SPARC/cast-sret-func.ll @@ -10,7 +10,7 @@ define void @test() nounwind { entry: %tmp = alloca %struct, align 4 call void bitcast (void ()* @func to void (%struct*)*) - (%struct* nonnull sret %tmp) + (%struct* nonnull sret(%struct) %tmp) ret void } diff --git a/llvm/test/CodeGen/SPARC/fp128.ll b/llvm/test/CodeGen/SPARC/fp128.ll index 22fab41f479cd..773e0698ffd3e 100644 --- a/llvm/test/CodeGen/SPARC/fp128.ll +++ b/llvm/test/CodeGen/SPARC/fp128.ll @@ -23,7 +23,7 @@ ; CHECK: std ; CHECK: std -define void @f128_ops(fp128* noalias sret %scalar.result, fp128* byval %a, fp128* byval %b, fp128* byval %c, fp128* byval %d) { +define void @f128_ops(fp128* noalias sret(fp128) %scalar.result, fp128* byval(fp128) %a, fp128* byval(fp128) %b, fp128* byval(fp128) %c, fp128* byval(fp128) %d) { entry: %0 = load fp128, fp128* %a, align 8 %1 = load fp128, fp128* %b, align 8 @@ -44,7 +44,7 @@ entry: ; CHECK-DAG: ldd [%[[S1]]], %f{{.+}} ; CHECK: jmp {{%[oi]7}}+12 -define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval %a) { +define void @f128_spill(fp128* noalias sret(fp128) %scalar.result, fp128* byval(fp128) %a) { entry: %0 = load fp128, fp128* %a, align 8 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() @@ -67,7 +67,7 @@ entry: ; CHECK-NEXT: add %g1, %sp, %g1 ; CHECK-NEXT: ldd [%g1+8], %f{{.+}} -define void @f128_spill_large(<251 x fp128>* noalias sret %scalar.result, <251 x fp128>* byval %a) { +define void @f128_spill_large(<251 x fp128>* noalias sret(<251 x fp128>) %scalar.result, <251 x fp128>* byval(<251 x fp128>) %a) { entry: %0 = load <251 x fp128>, <251 x fp128>* %a, align 8 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() @@ -80,7 +80,7 @@ entry: ; HARD-NEXT: nop ; SOFT: _Q_cmp -define i32 @f128_compare(fp128* byval %f0, fp128* byval %f1, i32 %a, i32 %b) { +define i32 @f128_compare(fp128* byval(fp128) %f0, fp128* byval(fp128) %f1, i32 %a, i32 %b) { entry: %0 = load fp128, fp128* %f0, align 8 %1 = load fp128, fp128* %f1, align 8 @@ -95,7 +95,7 @@ entry: ; SOFT: _Q_cmp ; SOFT: cmp -define i32 @f128_compare2(fp128* byval %f0) { +define i32 @f128_compare2(fp128* byval(fp128) %f0) { entry: %0 = load fp128, fp128* %f0, align 8 %1 = fcmp ogt fp128 %0, 0xL00000000000000000000000000000000 @@ -115,7 +115,7 @@ entry: ; BE: fabss %f0, %f0 ; EL: fabss %f3, %f3 -define void @f128_abs(fp128* noalias sret %scalar.result, fp128* byval %a) { +define void @f128_abs(fp128* noalias sret(fp128) %scalar.result, fp128* byval(fp128) %a) { entry: %0 = load fp128, fp128* %a, align 8 %1 = tail call fp128 @llvm.fabs.f128(fp128 %0) @@ -130,7 +130,7 @@ declare fp128 @llvm.fabs.f128(fp128) nounwind readonly ; SOFT: _Q_itoq ; SOFT: unimp 16 -define void @int_to_f128(fp128* noalias sret %scalar.result, i32 %i) { +define void @int_to_f128(fp128* noalias sret(fp128) %scalar.result, i32 %i) { entry: %0 = sitofp i32 %i to fp128 store fp128 %0, fp128* %scalar.result, align 8 @@ -159,7 +159,7 @@ entry: ; SOFT: _Q_utoq ; SOFT: unimp 16 -define void @uint_to_f128(fp128* noalias sret %scalar.result, i32 %i) { +define void @uint_to_f128(fp128* noalias sret(fp128) %scalar.result, i32 %i) { entry: %0 = uitofp i32 %i to fp128 store fp128 %0, fp128* %scalar.result, align 8 @@ -242,7 +242,7 @@ entry: ; BE: fnegs %f0, %f0 ; EL: fnegs %f3, %f3 -define void @f128_neg(fp128* noalias sret %scalar.result, fp128* byval %a) { +define void @f128_neg(fp128* noalias sret(fp128) %scalar.result, fp128* byval(fp128) %a) { entry: %0 = load fp128, fp128* %a, align 8 %1 = fsub fp128 0xL00000000000000008000000000000000, %0 diff --git a/llvm/test/CodeGen/SPARC/missing-sret.ll b/llvm/test/CodeGen/SPARC/missing-sret.ll index 683d840bd2507..c7435766aebc7 100644 --- a/llvm/test/CodeGen/SPARC/missing-sret.ll +++ b/llvm/test/CodeGen/SPARC/missing-sret.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=sparc -filetype=obj < %s > /dev/null 2> %t2 -define void @mul_double_cc({ double, double }* noalias sret %agg.result, double %a, double %b, double %c, double %d) { +define void @mul_double_cc({ double, double }* noalias sret({ double, double }) %agg.result, double %a, double %b, double %c, double %d) { entry: - call void @__muldc3({ double, double }* sret %agg.result, double %a, double %b, double %c, double %d) + call void @__muldc3({ double, double }* sret({ double, double }) %agg.result, double %a, double %b, double %c, double %d) ret void } diff --git a/llvm/test/CodeGen/SPARC/setjmp.ll b/llvm/test/CodeGen/SPARC/setjmp.ll index 17519c5162736..3f81876b3f885 100644 --- a/llvm/test/CodeGen/SPARC/setjmp.ll +++ b/llvm/test/CodeGen/SPARC/setjmp.ll @@ -24,7 +24,7 @@ ; V9: st %o0, [%[[R]]+{{.+}}] ; Function Attrs: nounwind -define i32 @foo(%struct.jmpbuf_env* byval %inbuf) #0 { +define i32 @foo(%struct.jmpbuf_env* byval(%struct.jmpbuf_env) %inbuf) #0 { entry: %0 = getelementptr inbounds %struct.jmpbuf_env, %struct.jmpbuf_env* %inbuf, i32 0, i32 0 store i32 0, i32* %0, align 4, !tbaa !4 diff --git a/llvm/test/CodeGen/SPARC/sret-secondary.ll b/llvm/test/CodeGen/SPARC/sret-secondary.ll index 8f334e823834b..84ac0b943c931 100644 --- a/llvm/test/CodeGen/SPARC/sret-secondary.ll +++ b/llvm/test/CodeGen/SPARC/sret-secondary.ll @@ -2,7 +2,7 @@ ; CHECK: sparc only supports sret on the first parameter -define void @foo(i32 %a, i32* sret %out) { +define void @foo(i32 %a, i32* sret(i32) %out) { store i32 %a, i32* %out ret void } diff --git a/llvm/test/CodeGen/SPARC/zerostructcall.ll b/llvm/test/CodeGen/SPARC/zerostructcall.ll index 0a8ff65e1585f..2aa5e56fe891b 100644 --- a/llvm/test/CodeGen/SPARC/zerostructcall.ll +++ b/llvm/test/CodeGen/SPARC/zerostructcall.ll @@ -12,11 +12,11 @@ entry: %i.addr = alloca i32, align 4 store i32 %i, i32* %i.addr, align 4 %0 = bitcast i32* %i.addr to %struct.S* - call void @struct_ptr_fn(%struct.S* byval align 1 %0) + call void @struct_ptr_fn(%struct.S* byval(%struct.S) align 1 %0) ret void } -declare void @struct_ptr_fn(%struct.S* byval align 1) +declare void @struct_ptr_fn(%struct.S* byval(%struct.S) align 1) ; CHECK-LABEL: struct_test ; CHECK: call struct_fn @@ -29,7 +29,7 @@ declare void @struct_ptr_fn(%struct.S* byval align 1) define void @struct_test() { entry: - tail call void @struct_fn(%struct.U* byval align 1 getelementptr inbounds ([1 x %struct.U], [1 x %struct.U]* @a, i32 0, i32 0)) + tail call void @struct_fn(%struct.U* byval(%struct.U) align 1 getelementptr inbounds ([1 x %struct.U], [1 x %struct.U]* @a, i32 0, i32 0)) ret void } @@ -38,14 +38,14 @@ entry: ; CHECK-NEXT: nop ; CHECK-NEXT: ret -declare void @struct_fn(%struct.U* byval align 1) +declare void @struct_fn(%struct.U* byval(%struct.U) align 1) @b = internal global [1 x %struct.U] zeroinitializer, align 1 define void @struct_arg_test() { entry: - tail call void @struct_arg_fn(%struct.U* byval align 1 getelementptr inbounds ([1 x %struct.U], [1 x %struct.U]* @b, i32 0, i32 0)) + tail call void @struct_arg_fn(%struct.U* byval(%struct.U) align 1 getelementptr inbounds ([1 x %struct.U], [1 x %struct.U]* @b, i32 0, i32 0)) ret void } -declare void @struct_arg_fn(%struct.U* byval align 1) +declare void @struct_arg_fn(%struct.U* byval(%struct.U) align 1) diff --git a/llvm/test/CodeGen/SystemZ/swifterror.ll b/llvm/test/CodeGen/SystemZ/swifterror.ll index d8fe608582c91..5a91914719683 100644 --- a/llvm/test/CodeGen/SystemZ/swifterror.ll +++ b/llvm/test/CodeGen/SystemZ/swifterror.ll @@ -198,7 +198,7 @@ bb_end: ; "foo_sret" is a function that takes a swifterror parameter, it also has a sret ; parameter. -define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { +define void @foo_sret(%struct.S* sret(%struct.S) %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { ; CHECK-LABEL: foo_sret: ; CHECK-DAG: lgr %r[[REG1:[0-9]+]], %r2 ; CHECK-DAG: lr %r[[REG2:[0-9]+]], %r3 @@ -265,7 +265,7 @@ entry: %s = alloca %struct.S, align 8 %error_ptr_ref = alloca swifterror %swift_error* store %swift_error* null, %swift_error** %error_ptr_ref - call void @foo_sret(%struct.S* sret %s, i32 1, %swift_error** swifterror %error_ptr_ref) + call void @foo_sret(%struct.S* sret(%struct.S) %s, i32 1, %swift_error** swifterror %error_ptr_ref) %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null %tmp = bitcast %swift_error* %error_from_foo to i8* diff --git a/llvm/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll b/llvm/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll index 08349a31dfa26..d7303ede4d321 100644 --- a/llvm/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll +++ b/llvm/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll @@ -7,7 +7,7 @@ @llvm.used = appending global [1 x i8*] [i8* bitcast (void (%0*, i32, i32)* @_Z19getClosestDiagonal3ii to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define void @_Z19getClosestDiagonal3ii(%0* noalias sret, i32, i32) nounwind { +define void @_Z19getClosestDiagonal3ii(%0* noalias sret(%0), i32, i32) nounwind { ; CHECK: bl ___muldf3 ; CHECK: beq LBB0 ; CHECK: bl ___muldf3 diff --git a/llvm/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll b/llvm/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll index 1ba0859166824..a9068f01a68f0 100644 --- a/llvm/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll +++ b/llvm/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll @@ -48,7 +48,7 @@ do.body: ; preds = %entry %tmp20 = bitcast %struct.RRRRRRRR* %agg.tmp16 to i8* %tmp21 = bitcast %struct.RRRRRRRR* %arrayidx19 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %tmp20, i8* align 4 %tmp21, i32 312, i1 false) - call void (i8*, i32, i8*, i8*, ...) @CLLoggingLog(i8* %tmp, i32 2, i8* getelementptr inbounds ([62 x i8], [62 x i8]* @__PRETTY_FUNCTION__._ZN12CLGll, i32 0, i32 0), i8* getelementptr inbounds ([75 x i8], [75 x i8]* @.str, i32 0, i32 0), %struct.RRRRRRRR* byval %agg.tmp, %struct.RRRRRRRR* byval %agg.tmp4, %struct.RRRRRRRR* byval %agg.tmp10, %struct.RRRRRRRR* byval %agg.tmp16) + call void (i8*, i32, i8*, i8*, ...) @CLLoggingLog(i8* %tmp, i32 2, i8* getelementptr inbounds ([62 x i8], [62 x i8]* @__PRETTY_FUNCTION__._ZN12CLGll, i32 0, i32 0), i8* getelementptr inbounds ([75 x i8], [75 x i8]* @.str, i32 0, i32 0), %struct.RRRRRRRR* byval(%struct.RRRRRRRR) %agg.tmp, %struct.RRRRRRRR* byval(%struct.RRRRRRRR) %agg.tmp4, %struct.RRRRRRRR* byval(%struct.RRRRRRRR) %agg.tmp10, %struct.RRRRRRRR* byval(%struct.RRRRRRRR) %agg.tmp16) br label %do.end do.end: ; preds = %do.body diff --git a/llvm/test/CodeGen/Thumb/PR17309.ll b/llvm/test/CodeGen/Thumb/PR17309.ll index 9815f899ac84b..804803ce93482 100644 --- a/llvm/test/CodeGen/Thumb/PR17309.ll +++ b/llvm/test/CodeGen/Thumb/PR17309.ll @@ -12,7 +12,7 @@ entry: %c = alloca %struct.C, align 1 %0 = getelementptr inbounds %struct.C, %struct.C* %c, i32 0, i32 0, i32 0 call void @llvm.lifetime.start.p0i8(i64 1000, i8* %0) #1 - call void @use_C(%struct.C* byval %c) #3 + call void @use_C(%struct.C* byval(%struct.C) %c) #3 call void @llvm.lifetime.end.p0i8(i64 1000, i8* %0) #1 ret void } @@ -25,7 +25,7 @@ entry: %s = alloca %struct.S, align 2 %0 = bitcast %struct.S* %s to i8* call void @llvm.lifetime.start.p0i8(i64 2000, i8* %0) #1 - call void @use_S(%struct.S* byval %s) #3 + call void @use_S(%struct.S* byval(%struct.S) %s) #3 call void @llvm.lifetime.end.p0i8(i64 2000, i8* %0) #1 ret void } @@ -38,14 +38,14 @@ entry: %i = alloca %struct.I, align 4 %0 = bitcast %struct.I* %i to i8* call void @llvm.lifetime.start.p0i8(i64 4000, i8* %0) #1 - call void @use_I(%struct.I* byval %i) #3 + call void @use_I(%struct.I* byval(%struct.I) %i) #3 call void @llvm.lifetime.end.p0i8(i64 4000, i8* %0) #1 ret void } -declare void @use_C(%struct.C* byval) #2 -declare void @use_S(%struct.S* byval) #2 -declare void @use_I(%struct.I* byval) #2 +declare void @use_C(%struct.C* byval(%struct.C)) #2 +declare void @use_S(%struct.S* byval(%struct.S)) #2 +declare void @use_I(%struct.I* byval(%struct.I)) #2 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 diff --git a/llvm/test/CodeGen/Thumb/emergency-spill-slot.ll b/llvm/test/CodeGen/Thumb/emergency-spill-slot.ll index e11c5bb7178c4..972cab0e07e31 100644 --- a/llvm/test/CodeGen/Thumb/emergency-spill-slot.ll +++ b/llvm/test/CodeGen/Thumb/emergency-spill-slot.ll @@ -164,7 +164,7 @@ entry: ret void } -define void @arg_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [252 x i32]* byval %p) { +define void @arg_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [252 x i32]* byval([252 x i32]) %p) { ; CHECK-LABEL: arg_emergency_spill: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .save {r4, r5, r6, r7, lr} @@ -206,7 +206,7 @@ entry: ; We currently overestimate the amount of required stack space by 16 bytes, ; so this is the largest stack that doesn't require an emergency spill slot. -define void @arg_no_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [248 x i32]* byval %p) { +define void @arg_no_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [248 x i32]* byval([248 x i32]) %p) { ; CHECK-LABEL: arg_no_emergency_spill: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .save {r4, r5, r6, r7, lr} @@ -235,7 +235,7 @@ entry: ret void } -define void @aligned_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [31 x i32]* byval %p) { +define void @aligned_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [31 x i32]* byval([31 x i32]) %p) { ; CHECK-LABEL: aligned_emergency_spill: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .save {r4, r5, r6, r7, lr} @@ -286,7 +286,7 @@ entry: ; This function should have no emergency spill slot, so its stack should be ; smaller than @aligned_emergency_spill. -define void @aligned_no_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [30 x i32]* byval %p) { +define void @aligned_no_emergency_spill(i32 %n, i32 %n2, i32 %n3, i32 %n4, [30 x i32]* byval([30 x i32]) %p) { ; CHECK-LABEL: aligned_no_emergency_spill: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .save {r4, r5, r6, r7, lr} @@ -333,7 +333,7 @@ entry: ; so we don't generate code that requires an emergency spill slot we never ; allocated. If the store gets eliminated, this testcase probably needs ; to be rewritten.) -define void @aligned_out_of_range_access(i32 %n, i32 %n2, i32 %n3, i32 %n4, [30 x i32]* byval %p) { +define void @aligned_out_of_range_access(i32 %n, i32 %n2, i32 %n3, i32 %n4, [30 x i32]* byval([30 x i32]) %p) { ; CHECK-LABEL: aligned_out_of_range_access: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .save {r4, r5, r6, r7, lr} diff --git a/llvm/test/CodeGen/Thumb/frame-access.ll b/llvm/test/CodeGen/Thumb/frame-access.ll index 8513982da9a9b..d3a5871d3335b 100644 --- a/llvm/test/CodeGen/Thumb/frame-access.ll +++ b/llvm/test/CodeGen/Thumb/frame-access.ll @@ -13,9 +13,9 @@ declare void @llvm.va_start(i8*) declare dso_local i32 @g(i32*, i32, i32, i32, i32, i32) local_unnamed_addr -declare dso_local i32 @f(i32*, i32, i32, i32, %struct.S* byval align 4) local_unnamed_addr +declare dso_local i32 @f(i32*, i32, i32, i32, %struct.S* byval(%struct.S) align 4) local_unnamed_addr declare dso_local i32 @h(i32*, i32*, i32*) local_unnamed_addr -declare dso_local i32 @u(i32*, i32*, i32*, %struct.S* byval align 4, %struct.S* byval align 4) local_unnamed_addr +declare dso_local i32 @u(i32*, i32*, i32*, %struct.S* byval(%struct.S) align 4, %struct.S* byval(%struct.S) align 4) local_unnamed_addr ; ; Test access to arguments, passed on stack (including varargs) @@ -187,7 +187,7 @@ entry: %arraydecay = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 0 %add = add nsw i32 %c, %b %add1 = add nsw i32 %add, %d - %call = call i32 @f(i32* nonnull %arraydecay, i32 %a, i32 %add1, i32 %e, %struct.S* byval nonnull align 4 @s) + %call = call i32 @f(i32* nonnull %arraydecay, i32 %a, i32 %add1, i32 %e, %struct.S* byval(%struct.S) nonnull align 4 @s) %add.ptr = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 1 %add.ptr5 = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 2 %call6 = call i32 @h(i32* nonnull %arraydecay, i32* nonnull %add.ptr, i32* nonnull %add.ptr5) @@ -226,7 +226,7 @@ entry: %1 = bitcast %struct.__va_list* %ap to i8* call void @llvm.va_start(i8* nonnull %1) %arraydecay = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 0 - %call = call i32 @f(i32* nonnull %arraydecay, i32 %a, i32 0, i32 0, %struct.S* byval nonnull align 4 @s) + %call = call i32 @f(i32* nonnull %arraydecay, i32 %a, i32 0, i32 0, %struct.S* byval(%struct.S) nonnull align 4 @s) %add.ptr = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 1 %add.ptr5 = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 2 %call6 = call i32 @h(i32* nonnull %arraydecay, i32* nonnull %add.ptr, i32* nonnull %add.ptr5) @@ -389,8 +389,8 @@ entry: %2 = bitcast i32* %y to i8* %3 = bitcast i32* %z to i8* %arraydecay = getelementptr inbounds [4 x i32], [4 x i32]* %v, i32 0, i32 0 - %call = call i32 @u(i32* nonnull %arraydecay, i32* nonnull %x, i32* nonnull %y, %struct.S* byval nonnull align 4 @s, %struct.S* byval nonnull align 4 @s) - %call2 = call i32 @u(i32* nonnull %arraydecay, i32* nonnull %y, i32* nonnull %z, %struct.S* byval nonnull align 4 @s, %struct.S* byval nonnull align 4 @s) + %call = call i32 @u(i32* nonnull %arraydecay, i32* nonnull %x, i32* nonnull %y, %struct.S* byval(%struct.S) nonnull align 4 @s, %struct.S* byval(%struct.S) nonnull align 4 @s) + %call2 = call i32 @u(i32* nonnull %arraydecay, i32* nonnull %y, i32* nonnull %z, %struct.S* byval(%struct.S) nonnull align 4 @s, %struct.S* byval(%struct.S) nonnull align 4 @s) %add = add nsw i32 %call2, %call ret i32 %add } diff --git a/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll b/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll index cf88de6c7cda7..2c6c05d5e21ea 100644 --- a/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll +++ b/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll @@ -7,7 +7,7 @@ %struct.Results = type { float, float, float } %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } -define void @get_results(%struct.Results* noalias nocapture sret %agg.result, %struct.Village* %village) nounwind { +define void @get_results(%struct.Results* noalias nocapture sret(%struct.Results) %agg.result, %struct.Village* %village) nounwind { entry: br i1 undef, label %bb, label %bb6.preheader diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll index 5c97f1b953cfe..bd927fdcf8598 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll @@ -241,42 +241,18 @@ define arm_aapcs_vfpcc void @nearbyint(float* noalias nocapture readonly %pSrcA, ; CHECK-NEXT: it eq ; CHECK-NEXT: popeq {r7, pc} ; CHECK-NEXT: .LBB5_1: @ %vector.ph -; CHECK-NEXT: adds r3, r2, #3 -; CHECK-NEXT: vdup.32 q1, r2 -; CHECK-NEXT: bic r3, r3, #3 -; CHECK-NEXT: sub.w r12, r3, #4 -; CHECK-NEXT: movs r3, #1 -; CHECK-NEXT: add.w lr, r3, r12, lsr #2 -; CHECK-NEXT: adr r3, .LCPI5_0 -; CHECK-NEXT: dls lr, lr -; CHECK-NEXT: vldrw.u32 q0, [r3] -; CHECK-NEXT: mov.w r12, #0 +; CHECK-NEXT: dlstp.32 lr, r2 ; CHECK-NEXT: .LBB5_2: @ %vector.body ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: vadd.i32 q2, q0, r12 -; CHECK-NEXT: vdup.32 q3, r12 -; CHECK-NEXT: vcmp.u32 hi, q3, q2 -; CHECK-NEXT: add.w r12, r12, #4 -; CHECK-NEXT: vpnot -; CHECK-NEXT: vpstt -; CHECK-NEXT: vcmpt.u32 hi, q1, q2 -; CHECK-NEXT: vldrwt.u32 q2, [r0], #16 -; CHECK-NEXT: vrintr.f32 s15, s11 -; CHECK-NEXT: vrintr.f32 s14, s10 -; CHECK-NEXT: vrintr.f32 s13, s9 -; CHECK-NEXT: vrintr.f32 s12, s8 -; CHECK-NEXT: vpst -; CHECK-NEXT: vstrwt.32 q3, [r1], #16 -; CHECK-NEXT: le lr, .LBB5_2 +; CHECK-NEXT: vldrw.u32 q0, [r0], #16 +; CHECK-NEXT: vrintr.f32 s7, s3 +; CHECK-NEXT: vrintr.f32 s6, s2 +; CHECK-NEXT: vrintr.f32 s5, s1 +; CHECK-NEXT: vrintr.f32 s4, s0 +; CHECK-NEXT: vstrw.32 q1, [r1], #16 +; CHECK-NEXT: letp lr, .LBB5_2 ; CHECK-NEXT: @ %bb.3: @ %for.cond.cleanup ; CHECK-NEXT: pop {r7, pc} -; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: @ %bb.4: -; CHECK-NEXT: .LCPI5_0: -; CHECK-NEXT: .long 0 @ 0x0 -; CHECK-NEXT: .long 1 @ 0x1 -; CHECK-NEXT: .long 2 @ 0x2 -; CHECK-NEXT: .long 3 @ 0x3 entry: %cmp5 = icmp eq i32 %n, 0 br i1 %cmp5, label %for.cond.cleanup, label %vector.ph diff --git a/llvm/test/CodeGen/Thumb2/active_lane_mask.ll b/llvm/test/CodeGen/Thumb2/active_lane_mask.ll index 2a5d32013d473..729493163b819 100644 --- a/llvm/test/CodeGen/Thumb2/active_lane_mask.ll +++ b/llvm/test/CodeGen/Thumb2/active_lane_mask.ll @@ -410,7 +410,156 @@ define <16 x i8> @v16i8(i32 %index, i32 %TC, <16 x i8> %V1, <16 x i8> %V2) { ret <16 x i8> %select } +define void @test_width2(i32* nocapture readnone %x, i32* nocapture %y, i8 zeroext %m) { +; CHECK-LABEL: test_width2: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: push {r4, r5, r6, lr} +; CHECK-NEXT: vpush {d8, d9, d10, d11} +; CHECK-NEXT: sub sp, #8 +; CHECK-NEXT: cmp r2, #0 +; CHECK-NEXT: beq.w .LBB4_3 +; CHECK-NEXT: @ %bb.1: @ %for.body.preheader +; CHECK-NEXT: adds r0, r2, #1 +; CHECK-NEXT: movs r3, #1 +; CHECK-NEXT: bic r0, r0, #1 +; CHECK-NEXT: vmov.32 q2[0], r2 +; CHECK-NEXT: subs r0, #2 +; CHECK-NEXT: vmov.i64 q0, #0xffffffff +; CHECK-NEXT: vmov.32 q2[2], r2 +; CHECK-NEXT: movs r6, #0 +; CHECK-NEXT: add.w lr, r3, r0, lsr #1 +; CHECK-NEXT: adr r3, .LCPI4_0 +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: vldrw.u32 q1, [r3] +; CHECK-NEXT: vand q2, q2, q0 +; CHECK-NEXT: .LBB4_2: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vmov.32 q3[0], r6 +; CHECK-NEXT: vmov r5, s8 +; CHECK-NEXT: vmov.32 q3[2], r6 +; CHECK-NEXT: vmov r0, s9 +; CHECK-NEXT: vand q3, q3, q0 +; CHECK-NEXT: adds r6, #2 +; CHECK-NEXT: vmov r3, s14 +; CHECK-NEXT: vmov r2, s15 +; CHECK-NEXT: adds r3, #1 +; CHECK-NEXT: adc r12, r2, #0 +; CHECK-NEXT: vmov r2, s12 +; CHECK-NEXT: vmov.32 q3[0], r2 +; CHECK-NEXT: vmov.32 q3[2], r3 +; CHECK-NEXT: vand q3, q3, q0 +; CHECK-NEXT: vmov r4, s12 +; CHECK-NEXT: teq.w r4, r2 +; CHECK-NEXT: cset r2, ne +; CHECK-NEXT: tst.w r2, #1 +; CHECK-NEXT: csetm r2, ne +; CHECK-NEXT: vmov.32 q4[0], r2 +; CHECK-NEXT: vmov.32 q4[1], r2 +; CHECK-NEXT: vmov r2, s14 +; CHECK-NEXT: eors r3, r2 +; CHECK-NEXT: orrs.w r3, r3, r12 +; CHECK-NEXT: cset r3, ne +; CHECK-NEXT: tst.w r3, #1 +; CHECK-NEXT: csetm r3, ne +; CHECK-NEXT: subs r5, r4, r5 +; CHECK-NEXT: vmov.32 q4[2], r3 +; CHECK-NEXT: vmov r5, s10 +; CHECK-NEXT: vmov.32 q4[3], r3 +; CHECK-NEXT: vmov r3, s13 +; CHECK-NEXT: veor q4, q4, q1 +; CHECK-NEXT: sbcs.w r0, r3, r0 +; CHECK-NEXT: vmov r3, s11 +; CHECK-NEXT: mov.w r0, #0 +; CHECK-NEXT: it lo +; CHECK-NEXT: movlo r0, #1 +; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: subs r2, r2, r5 +; CHECK-NEXT: vmov.32 q5[0], r0 +; CHECK-NEXT: vmov.32 q5[1], r0 +; CHECK-NEXT: vmov r0, s15 +; CHECK-NEXT: @ implicit-def: $q3 +; CHECK-NEXT: sbcs r0, r3 +; CHECK-NEXT: mov.w r0, #0 +; CHECK-NEXT: it lo +; CHECK-NEXT: movlo r0, #1 +; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: csetm r0, ne +; CHECK-NEXT: vmov.32 q5[2], r0 +; CHECK-NEXT: vmov.32 q5[3], r0 +; CHECK-NEXT: vand q4, q4, q5 +; CHECK-NEXT: vmov r2, s16 +; CHECK-NEXT: vmov r0, s18 +; CHECK-NEXT: and r2, r2, #1 +; CHECK-NEXT: orr.w r3, r2, r0, lsl #1 +; CHECK-NEXT: sub.w r2, r1, #8 +; CHECK-NEXT: lsls r0, r3, #31 +; CHECK-NEXT: itt ne +; CHECK-NEXT: ldrne r0, [r2] +; CHECK-NEXT: vmovne.32 q3[0], r0 +; CHECK-NEXT: and r0, r3, #3 +; CHECK-NEXT: lsls r0, r0, #30 +; CHECK-NEXT: itt mi +; CHECK-NEXT: ldrmi r0, [r2, #4] +; CHECK-NEXT: vmovmi.32 q3[2], r0 +; CHECK-NEXT: vmov r2, s16 +; CHECK-NEXT: vmov r0, s18 +; CHECK-NEXT: and r2, r2, #1 +; CHECK-NEXT: orr.w r2, r2, r0, lsl #1 +; CHECK-NEXT: lsls r0, r2, #31 +; CHECK-NEXT: itt ne +; CHECK-NEXT: vmovne r0, s12 +; CHECK-NEXT: strne r0, [r1] +; CHECK-NEXT: and r0, r2, #3 +; CHECK-NEXT: lsls r0, r0, #30 +; CHECK-NEXT: itt mi +; CHECK-NEXT: vmovmi r0, s14 +; CHECK-NEXT: strmi r0, [r1, #4] +; CHECK-NEXT: adds r1, #8 +; CHECK-NEXT: le lr, .LBB4_2 +; CHECK-NEXT: .LBB4_3: @ %for.cond.cleanup +; CHECK-NEXT: add sp, #8 +; CHECK-NEXT: vpop {d8, d9, d10, d11} +; CHECK-NEXT: pop {r4, r5, r6, pc} +; CHECK-NEXT: .p2align 4 +; CHECK-NEXT: @ %bb.4: +; CHECK-NEXT: .LCPI4_0: +; CHECK-NEXT: .long 1 @ 0x1 +; CHECK-NEXT: .long 0 @ 0x0 +; CHECK-NEXT: .long 1 @ 0x1 +; CHECK-NEXT: .long 0 @ 0x0 +entry: + %cmp9.not = icmp eq i8 %m, 0 + br i1 %cmp9.not, label %for.cond.cleanup, label %for.body.preheader + +for.body.preheader: ; preds = %entry + %wide.trip.count = zext i8 %m to i32 + %n.rnd.up = add nuw nsw i32 %wide.trip.count, 1 + %n.vec = and i32 %n.rnd.up, 510 + br label %vector.body + +vector.body: ; preds = %vector.body, %for.body.preheader + %index = phi i32 [ 0, %for.body.preheader ], [ %index.next, %vector.body ] + %active.lane.mask = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 %index, i32 %wide.trip.count) + %0 = add nsw i32 %index, -2 + %1 = getelementptr inbounds i32, i32* %y, i32 %0 + %2 = bitcast i32* %1 to <2 x i32>* + %wide.masked.load = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %2, i32 4, <2 x i1> %active.lane.mask, <2 x i32> undef) + %3 = getelementptr inbounds i32, i32* %y, i32 %index + %4 = bitcast i32* %3 to <2 x i32>* + call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> %wide.masked.load, <2 x i32>* %4, i32 4, <2 x i1> %active.lane.mask) + %index.next = add i32 %index, 2 + %5 = icmp eq i32 %index.next, %n.vec + br i1 %5, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body, %entry + ret void +} + +declare <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32, i32) declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i32(i32, i32) declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32) declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32) +declare <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>*, i32, <2 x i1>, <2 x i32>) +declare void @llvm.masked.store.v2i32.p0v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>) diff --git a/llvm/test/CodeGen/Thumb2/constant-islands.ll b/llvm/test/CodeGen/Thumb2/constant-islands.ll index ac323adfd3f1d..9021b8c4e95da 100644 --- a/llvm/test/CodeGen/Thumb2/constant-islands.ll +++ b/llvm/test/CodeGen/Thumb2/constant-islands.ll @@ -432,9 +432,9 @@ invoke.cont90: ; preds = %invoke.cont81 store float 1.000000e+00, float* %ref.tmp99, align 4 store float 0.000000e+00, float* %ref.tmp100, align 4 %call101 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp97, float* %ref.tmp98, float* %ref.tmp99, float* %ref.tmp100) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp, float* %scale.addr, %class.btVector3* %ref.tmp97) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp, float* %scale.addr, %class.btVector3* %ref.tmp97) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp) - call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp102, %class.btTransform* %offset, %class.btTransform* %transform) + call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret(%class.btTransform) %ref.tmp102, %class.btTransform* %offset, %class.btTransform* %transform) %m_shapes103 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2 %arrayidx104 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes103, i32 0, i32 0 %47 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx104, align 4 @@ -447,9 +447,9 @@ invoke.cont90: ; preds = %invoke.cont81 store float 0x3FF3333340000000, float* %ref.tmp110, align 4 store float 0.000000e+00, float* %ref.tmp111, align 4 %call112 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp108, float* %ref.tmp109, float* %ref.tmp110, float* %ref.tmp111) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp107, float* %scale.addr, %class.btVector3* %ref.tmp108) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp107, float* %scale.addr, %class.btVector3* %ref.tmp108) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp107) - call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp113, %class.btTransform* %offset, %class.btTransform* %transform) + call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret(%class.btTransform) %ref.tmp113, %class.btTransform* %offset, %class.btTransform* %transform) %m_shapes114 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2 %arrayidx115 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes114, i32 0, i32 1 %48 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx115, align 4 @@ -462,9 +462,9 @@ invoke.cont90: ; preds = %invoke.cont81 store float 0x3FF99999A0000000, float* %ref.tmp122, align 4 store float 0.000000e+00, float* %ref.tmp123, align 4 %call124 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp120, float* %ref.tmp121, float* %ref.tmp122, float* %ref.tmp123) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp119, float* %scale.addr, %class.btVector3* %ref.tmp120) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp119, float* %scale.addr, %class.btVector3* %ref.tmp120) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp119) - call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp125, %class.btTransform* %offset, %class.btTransform* %transform) + call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret(%class.btTransform) %ref.tmp125, %class.btTransform* %offset, %class.btTransform* %transform) %m_shapes126 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2 %arrayidx127 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes126, i32 0, i32 2 %49 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx127, align 4 @@ -477,9 +477,9 @@ invoke.cont90: ; preds = %invoke.cont81 store float 0x3FE4CCCCC0000000, float* %ref.tmp134, align 4 store float 0.000000e+00, float* %ref.tmp135, align 4 %call136 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp132, float* %ref.tmp133, float* %ref.tmp134, float* %ref.tmp135) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp131, float* %scale.addr, %class.btVector3* %ref.tmp132) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp131, float* %scale.addr, %class.btVector3* %ref.tmp132) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp131) - call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp137, %class.btTransform* %offset, %class.btTransform* %transform) + call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret(%class.btTransform) %ref.tmp137, %class.btTransform* %offset, %class.btTransform* %transform) %m_shapes138 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2 %arrayidx139 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes138, i32 0, i32 3 %50 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx139, align 4 @@ -492,9 +492,9 @@ invoke.cont90: ; preds = %invoke.cont81 store float 0x3FC99999A0000000, float* %ref.tmp146, align 4 store float 0.000000e+00, float* %ref.tmp147, align 4 %call148 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp144, float* %ref.tmp145, float* %ref.tmp146, float* %ref.tmp147) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp143, float* %scale.addr, %class.btVector3* %ref.tmp144) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp143, float* %scale.addr, %class.btVector3* %ref.tmp144) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp143) - call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp149, %class.btTransform* %offset, %class.btTransform* %transform) + call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret(%class.btTransform) %ref.tmp149, %class.btTransform* %offset, %class.btTransform* %transform) %m_shapes150 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2 %arrayidx151 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes150, i32 0, i32 4 %51 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx151, align 4 @@ -507,9 +507,9 @@ invoke.cont90: ; preds = %invoke.cont81 store float 0x3FE4CCCCC0000000, float* %ref.tmp158, align 4 store float 0.000000e+00, float* %ref.tmp159, align 4 %call160 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp156, float* %ref.tmp157, float* %ref.tmp158, float* %ref.tmp159) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp155, float* %scale.addr, %class.btVector3* %ref.tmp156) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp155, float* %scale.addr, %class.btVector3* %ref.tmp156) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp155) - call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp161, %class.btTransform* %offset, %class.btTransform* %transform) + call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret(%class.btTransform) %ref.tmp161, %class.btTransform* %offset, %class.btTransform* %transform) %m_shapes162 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2 %arrayidx163 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes162, i32 0, i32 5 %52 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx163, align 4 @@ -522,9 +522,9 @@ invoke.cont90: ; preds = %invoke.cont81 store float 0x3FC99999A0000000, float* %ref.tmp170, align 4 store float 0.000000e+00, float* %ref.tmp171, align 4 %call172 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp168, float* %ref.tmp169, float* %ref.tmp170, float* %ref.tmp171) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp167, float* %scale.addr, %class.btVector3* %ref.tmp168) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp167, float* %scale.addr, %class.btVector3* %ref.tmp168) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp167) - call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp173, %class.btTransform* %offset, %class.btTransform* %transform) + call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret(%class.btTransform) %ref.tmp173, %class.btTransform* %offset, %class.btTransform* %transform) %m_shapes174 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2 %arrayidx175 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes174, i32 0, i32 6 %53 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx175, align 4 @@ -537,11 +537,11 @@ invoke.cont90: ; preds = %invoke.cont81 store float 0x3FF7333340000000, float* %ref.tmp182, align 4 store float 0.000000e+00, float* %ref.tmp183, align 4 %call184 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp180, float* %ref.tmp181, float* %ref.tmp182, float* %ref.tmp183) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp179, float* %scale.addr, %class.btVector3* %ref.tmp180) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp179, float* %scale.addr, %class.btVector3* %ref.tmp180) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp179) %call185 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %transform) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call185, float 0.000000e+00, float 0.000000e+00, float 0x3FF921FB60000000) - call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp186, %class.btTransform* %offset, %class.btTransform* %transform) + call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret(%class.btTransform) %ref.tmp186, %class.btTransform* %offset, %class.btTransform* %transform) %m_shapes187 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2 %arrayidx188 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes187, i32 0, i32 7 %54 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx188, align 4 @@ -554,11 +554,11 @@ invoke.cont90: ; preds = %invoke.cont81 store float 0x3FF7333340000000, float* %ref.tmp195, align 4 store float 0.000000e+00, float* %ref.tmp196, align 4 %call197 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp193, float* %ref.tmp194, float* %ref.tmp195, float* %ref.tmp196) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp192, float* %scale.addr, %class.btVector3* %ref.tmp193) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp192, float* %scale.addr, %class.btVector3* %ref.tmp193) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp192) %call198 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %transform) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call198, float 0.000000e+00, float 0.000000e+00, float 0x3FF921FB60000000) - call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp199, %class.btTransform* %offset, %class.btTransform* %transform) + call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret(%class.btTransform) %ref.tmp199, %class.btTransform* %offset, %class.btTransform* %transform) %m_shapes200 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2 %arrayidx201 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes200, i32 0, i32 8 %55 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx201, align 4 @@ -571,11 +571,11 @@ invoke.cont90: ; preds = %invoke.cont81 store float 0x3FF7333340000000, float* %ref.tmp208, align 4 store float 0.000000e+00, float* %ref.tmp209, align 4 %call210 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp206, float* %ref.tmp207, float* %ref.tmp208, float* %ref.tmp209) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp205, float* %scale.addr, %class.btVector3* %ref.tmp206) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp205, float* %scale.addr, %class.btVector3* %ref.tmp206) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp205) %call211 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %transform) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call211, float 0.000000e+00, float 0.000000e+00, float 0xBFF921FB60000000) - call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp212, %class.btTransform* %offset, %class.btTransform* %transform) + call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret(%class.btTransform) %ref.tmp212, %class.btTransform* %offset, %class.btTransform* %transform) %m_shapes213 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2 %arrayidx214 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes213, i32 0, i32 9 %56 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx214, align 4 @@ -588,11 +588,11 @@ invoke.cont90: ; preds = %invoke.cont81 store float 0x3FF7333340000000, float* %ref.tmp221, align 4 store float 0.000000e+00, float* %ref.tmp222, align 4 %call223 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp219, float* %ref.tmp220, float* %ref.tmp221, float* %ref.tmp222) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp218, float* %scale.addr, %class.btVector3* %ref.tmp219) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp218, float* %scale.addr, %class.btVector3* %ref.tmp219) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %transform, %class.btVector3* %ref.tmp218) %call224 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %transform) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call224, float 0.000000e+00, float 0.000000e+00, float 0xBFF921FB60000000) - call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret %ref.tmp225, %class.btTransform* %offset, %class.btTransform* %transform) + call void @_ZNK11btTransformmlERKS_(%class.btTransform* sret(%class.btTransform) %ref.tmp225, %class.btTransform* %offset, %class.btTransform* %transform) %m_shapes226 = getelementptr inbounds %class.RagDoll, %class.RagDoll* %this1, i32 0, i32 2 %arrayidx227 = getelementptr inbounds [11 x %class.btCollisionShape*], [11 x %class.btCollisionShape*]* %m_shapes226, i32 0, i32 10 %57 = load %class.btCollisionShape*, %class.btCollisionShape** %arrayidx227, align 4 @@ -787,7 +787,7 @@ for.end: ; preds = %for.cond store float 0x3FC3333340000000, float* %ref.tmp243, align 4 store float 0.000000e+00, float* %ref.tmp244, align 4 %call245 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp241, float* %ref.tmp242, float* %ref.tmp243, float* %ref.tmp244) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp240, float* %scale.addr, %class.btVector3* %ref.tmp241) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp240, float* %scale.addr, %class.btVector3* %ref.tmp241) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localA, %class.btVector3* %ref.tmp240) %call246 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %localB) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call246, float 0.000000e+00, float 0x3FF921FB60000000, float 0.000000e+00) @@ -795,7 +795,7 @@ for.end: ; preds = %for.cond store float 0xBFC3333340000000, float* %ref.tmp250, align 4 store float 0.000000e+00, float* %ref.tmp251, align 4 %call252 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp248, float* %ref.tmp249, float* %ref.tmp250, float* %ref.tmp251) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp247, float* %scale.addr, %class.btVector3* %ref.tmp248) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp247, float* %scale.addr, %class.btVector3* %ref.tmp248) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp247) %call253 = call noalias i8* @_Znwm(i32 780) %100 = bitcast i8* %call253 to %class.btHingeConstraint* @@ -835,7 +835,7 @@ invoke.cont259: ; preds = %for.end store float 0x3FD3333340000000, float* %ref.tmp269, align 4 store float 0.000000e+00, float* %ref.tmp270, align 4 %call271 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp267, float* %ref.tmp268, float* %ref.tmp269, float* %ref.tmp270) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp266, float* %scale.addr, %class.btVector3* %ref.tmp267) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp266, float* %scale.addr, %class.btVector3* %ref.tmp267) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localA, %class.btVector3* %ref.tmp266) %call272 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %localB) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call272, float 0.000000e+00, float 0.000000e+00, float 0x3FF921FB60000000) @@ -843,7 +843,7 @@ invoke.cont259: ; preds = %for.end store float 0xBFC1EB8520000000, float* %ref.tmp276, align 4 store float 0.000000e+00, float* %ref.tmp277, align 4 %call278 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp274, float* %ref.tmp275, float* %ref.tmp276, float* %ref.tmp277) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp273, float* %scale.addr, %class.btVector3* %ref.tmp274) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp273, float* %scale.addr, %class.btVector3* %ref.tmp274) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp273) %call279 = call noalias i8* @_Znwm(i32 628) %110 = bitcast i8* %call279 to %class.btConeTwistConstraint* @@ -883,7 +883,7 @@ invoke.cont285: ; preds = %invoke.cont259 store float 0xBFB99999A0000000, float* %ref.tmp298, align 4 store float 0.000000e+00, float* %ref.tmp299, align 4 %call300 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp296, float* %ref.tmp297, float* %ref.tmp298, float* %ref.tmp299) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp295, float* %scale.addr, %class.btVector3* %ref.tmp296) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp295, float* %scale.addr, %class.btVector3* %ref.tmp296) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localA, %class.btVector3* %ref.tmp295) %call301 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %localB) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call301, float 0.000000e+00, float 0.000000e+00, float 0xC00F6A7A20000000) @@ -891,7 +891,7 @@ invoke.cont285: ; preds = %invoke.cont259 store float 0x3FCCCCCCC0000000, float* %ref.tmp305, align 4 store float 0.000000e+00, float* %ref.tmp306, align 4 %call307 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp303, float* %ref.tmp304, float* %ref.tmp305, float* %ref.tmp306) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp302, float* %scale.addr, %class.btVector3* %ref.tmp303) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp302, float* %scale.addr, %class.btVector3* %ref.tmp303) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp302) %call308 = call noalias i8* @_Znwm(i32 628) %120 = bitcast i8* %call308 to %class.btConeTwistConstraint* @@ -931,7 +931,7 @@ invoke.cont314: ; preds = %invoke.cont285 store float 0xBFCCCCCCC0000000, float* %ref.tmp327, align 4 store float 0.000000e+00, float* %ref.tmp328, align 4 %call329 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp325, float* %ref.tmp326, float* %ref.tmp327, float* %ref.tmp328) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp324, float* %scale.addr, %class.btVector3* %ref.tmp325) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp324, float* %scale.addr, %class.btVector3* %ref.tmp325) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localA, %class.btVector3* %ref.tmp324) %call330 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %localB) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call330, float 0.000000e+00, float 0x3FF921FB60000000, float 0.000000e+00) @@ -939,7 +939,7 @@ invoke.cont314: ; preds = %invoke.cont285 store float 0x3FC7AE1480000000, float* %ref.tmp334, align 4 store float 0.000000e+00, float* %ref.tmp335, align 4 %call336 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp332, float* %ref.tmp333, float* %ref.tmp334, float* %ref.tmp335) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp331, float* %scale.addr, %class.btVector3* %ref.tmp332) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp331, float* %scale.addr, %class.btVector3* %ref.tmp332) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp331) %call337 = call noalias i8* @_Znwm(i32 780) %130 = bitcast i8* %call337 to %class.btHingeConstraint* @@ -979,7 +979,7 @@ invoke.cont343: ; preds = %invoke.cont314 store float 0xBFB99999A0000000, float* %ref.tmp356, align 4 store float 0.000000e+00, float* %ref.tmp357, align 4 %call358 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp354, float* %ref.tmp355, float* %ref.tmp356, float* %ref.tmp357) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp353, float* %scale.addr, %class.btVector3* %ref.tmp354) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp353, float* %scale.addr, %class.btVector3* %ref.tmp354) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localA, %class.btVector3* %ref.tmp353) %call359 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %localB) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call359, float 0.000000e+00, float 0.000000e+00, float 0x3FE921FB60000000) @@ -987,7 +987,7 @@ invoke.cont343: ; preds = %invoke.cont314 store float 0x3FCCCCCCC0000000, float* %ref.tmp363, align 4 store float 0.000000e+00, float* %ref.tmp364, align 4 %call365 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp361, float* %ref.tmp362, float* %ref.tmp363, float* %ref.tmp364) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp360, float* %scale.addr, %class.btVector3* %ref.tmp361) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp360, float* %scale.addr, %class.btVector3* %ref.tmp361) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp360) %call366 = call noalias i8* @_Znwm(i32 628) %140 = bitcast i8* %call366 to %class.btConeTwistConstraint* @@ -1027,7 +1027,7 @@ invoke.cont372: ; preds = %invoke.cont343 store float 0xBFCCCCCCC0000000, float* %ref.tmp385, align 4 store float 0.000000e+00, float* %ref.tmp386, align 4 %call387 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp383, float* %ref.tmp384, float* %ref.tmp385, float* %ref.tmp386) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp382, float* %scale.addr, %class.btVector3* %ref.tmp383) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp382, float* %scale.addr, %class.btVector3* %ref.tmp383) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localA, %class.btVector3* %ref.tmp382) %call388 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %localB) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call388, float 0.000000e+00, float 0x3FF921FB60000000, float 0.000000e+00) @@ -1035,7 +1035,7 @@ invoke.cont372: ; preds = %invoke.cont343 store float 0x3FC7AE1480000000, float* %ref.tmp392, align 4 store float 0.000000e+00, float* %ref.tmp393, align 4 %call394 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp390, float* %ref.tmp391, float* %ref.tmp392, float* %ref.tmp393) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp389, float* %scale.addr, %class.btVector3* %ref.tmp390) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp389, float* %scale.addr, %class.btVector3* %ref.tmp390) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp389) %call395 = call noalias i8* @_Znwm(i32 780) %150 = bitcast i8* %call395 to %class.btHingeConstraint* @@ -1075,7 +1075,7 @@ invoke.cont401: ; preds = %invoke.cont372 store float 0x3FC3333340000000, float* %ref.tmp414, align 4 store float 0.000000e+00, float* %ref.tmp415, align 4 %call416 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp412, float* %ref.tmp413, float* %ref.tmp414, float* %ref.tmp415) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp411, float* %scale.addr, %class.btVector3* %ref.tmp412) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp411, float* %scale.addr, %class.btVector3* %ref.tmp412) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localA, %class.btVector3* %ref.tmp411) %call417 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %localB) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call417, float 0.000000e+00, float 0.000000e+00, float 0x3FF921FB60000000) @@ -1083,7 +1083,7 @@ invoke.cont401: ; preds = %invoke.cont372 store float 0xBFC70A3D80000000, float* %ref.tmp421, align 4 store float 0.000000e+00, float* %ref.tmp422, align 4 %call423 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp419, float* %ref.tmp420, float* %ref.tmp421, float* %ref.tmp422) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp418, float* %scale.addr, %class.btVector3* %ref.tmp419) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp418, float* %scale.addr, %class.btVector3* %ref.tmp419) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp418) %call424 = call noalias i8* @_Znwm(i32 628) %160 = bitcast i8* %call424 to %class.btConeTwistConstraint* @@ -1123,7 +1123,7 @@ invoke.cont430: ; preds = %invoke.cont401 store float 0x3FC70A3D80000000, float* %ref.tmp443, align 4 store float 0.000000e+00, float* %ref.tmp444, align 4 %call445 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp441, float* %ref.tmp442, float* %ref.tmp443, float* %ref.tmp444) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp440, float* %scale.addr, %class.btVector3* %ref.tmp441) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp440, float* %scale.addr, %class.btVector3* %ref.tmp441) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localA, %class.btVector3* %ref.tmp440) %call446 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %localB) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call446, float 0.000000e+00, float 0x3FF921FB60000000, float 0.000000e+00) @@ -1131,7 +1131,7 @@ invoke.cont430: ; preds = %invoke.cont401 store float 0xBFC1EB8520000000, float* %ref.tmp450, align 4 store float 0.000000e+00, float* %ref.tmp451, align 4 %call452 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp448, float* %ref.tmp449, float* %ref.tmp450, float* %ref.tmp451) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp447, float* %scale.addr, %class.btVector3* %ref.tmp448) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp447, float* %scale.addr, %class.btVector3* %ref.tmp448) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp447) %call453 = call noalias i8* @_Znwm(i32 780) %170 = bitcast i8* %call453 to %class.btHingeConstraint* @@ -1171,7 +1171,7 @@ invoke.cont459: ; preds = %invoke.cont430 store float 0x3FC3333340000000, float* %ref.tmp472, align 4 store float 0.000000e+00, float* %ref.tmp473, align 4 %call474 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp470, float* %ref.tmp471, float* %ref.tmp472, float* %ref.tmp473) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp469, float* %scale.addr, %class.btVector3* %ref.tmp470) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp469, float* %scale.addr, %class.btVector3* %ref.tmp470) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localA, %class.btVector3* %ref.tmp469) %call475 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %localB) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call475, float 0.000000e+00, float 0.000000e+00, float 0x3FF921FB60000000) @@ -1179,7 +1179,7 @@ invoke.cont459: ; preds = %invoke.cont430 store float 0xBFC70A3D80000000, float* %ref.tmp479, align 4 store float 0.000000e+00, float* %ref.tmp480, align 4 %call481 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp477, float* %ref.tmp478, float* %ref.tmp479, float* %ref.tmp480) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp476, float* %scale.addr, %class.btVector3* %ref.tmp477) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp476, float* %scale.addr, %class.btVector3* %ref.tmp477) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp476) %call482 = call noalias i8* @_Znwm(i32 628) %180 = bitcast i8* %call482 to %class.btConeTwistConstraint* @@ -1219,7 +1219,7 @@ invoke.cont488: ; preds = %invoke.cont459 store float 0x3FC70A3D80000000, float* %ref.tmp501, align 4 store float 0.000000e+00, float* %ref.tmp502, align 4 %call503 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp499, float* %ref.tmp500, float* %ref.tmp501, float* %ref.tmp502) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp498, float* %scale.addr, %class.btVector3* %ref.tmp499) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp498, float* %scale.addr, %class.btVector3* %ref.tmp499) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localA, %class.btVector3* %ref.tmp498) %call504 = call %class.btMatrix3x3* @_ZN11btTransform8getBasisEv(%class.btTransform* %localB) call void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3* %call504, float 0.000000e+00, float 0x3FF921FB60000000, float 0.000000e+00) @@ -1227,7 +1227,7 @@ invoke.cont488: ; preds = %invoke.cont459 store float 0xBFC1EB8520000000, float* %ref.tmp508, align 4 store float 0.000000e+00, float* %ref.tmp509, align 4 %call510 = call %class.btVector3* @_ZN9btVector3C1ERKfS1_S1_(%class.btVector3* %ref.tmp506, float* %ref.tmp507, float* %ref.tmp508, float* %ref.tmp509) - call void @_ZmlRKfRK9btVector3(%class.btVector3* sret %ref.tmp505, float* %scale.addr, %class.btVector3* %ref.tmp506) + call void @_ZmlRKfRK9btVector3(%class.btVector3* sret(%class.btVector3) %ref.tmp505, float* %scale.addr, %class.btVector3* %ref.tmp506) call void @_ZN11btTransform9setOriginERK9btVector3(%class.btTransform* %localB, %class.btVector3* %ref.tmp505) %call511 = call noalias i8* @_Znwm(i32 780) %190 = bitcast i8* %call511 to %class.btHingeConstraint* @@ -1376,11 +1376,11 @@ terminate.lpad: ; preds = %lpad89, %lpad80, %l unreachable } -declare void @_ZmlRKfRK9btVector3(%class.btVector3* noalias sret, float*, %class.btVector3*) inlinehint ssp +declare void @_ZmlRKfRK9btVector3(%class.btVector3* noalias sret(%class.btVector3), float*, %class.btVector3*) inlinehint ssp declare %class.btRigidBody* @_ZN7RagDoll20localCreateRigidBodyEfRK11btTransformP16btCollisionShape(%class.RagDoll*, float, %class.btTransform*, %class.btCollisionShape*) ssp align 2 -declare void @_ZNK11btTransformmlERKS_(%class.btTransform* noalias sret, %class.btTransform*, %class.btTransform*) inlinehint ssp align 2 +declare void @_ZNK11btTransformmlERKS_(%class.btTransform* noalias sret(%class.btTransform), %class.btTransform*, %class.btTransform*) inlinehint ssp align 2 declare void @_ZN11btMatrix3x311setEulerZYXEfff(%class.btMatrix3x3*, float, float, float) ssp align 2 diff --git a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll index 5bf4ebf92f147..fa58c72a0efb5 100644 --- a/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-float16regloops.ll @@ -1077,36 +1077,34 @@ define void @fir(%struct.arm_fir_instance_f32* nocapture readonly %S, half* noca ; CHECK-NEXT: sub sp, #24 ; CHECK-NEXT: cmp r3, #8 ; CHECK-NEXT: blo.w .LBB16_12 -; CHECK-NEXT: @ %bb.1: @ %if.then -; CHECK-NEXT: movs r7, #0 -; CHECK-NEXT: cmp.w r7, r3, lsr #2 +; CHECK-NEXT: @ %bb.1: @ %entry +; CHECK-NEXT: lsrs.w r12, r3, #2 ; CHECK-NEXT: beq.w .LBB16_12 ; CHECK-NEXT: @ %bb.2: @ %while.body.lr.ph ; CHECK-NEXT: ldrh r4, [r0] -; CHECK-NEXT: lsr.w r9, r3, #2 -; CHECK-NEXT: ldrd r5, r12, [r0, #4] -; CHECK-NEXT: movs r3, #1 +; CHECK-NEXT: movs r6, #1 +; CHECK-NEXT: ldrd r5, r3, [r0, #4] ; CHECK-NEXT: sub.w r0, r4, #8 ; CHECK-NEXT: and r8, r0, #7 ; CHECK-NEXT: add.w r7, r0, r0, lsr #29 -; CHECK-NEXT: asrs r6, r7, #3 -; CHECK-NEXT: cmp r6, #1 +; CHECK-NEXT: asr.w lr, r7, #3 +; CHECK-NEXT: cmp.w lr, #1 ; CHECK-NEXT: it gt -; CHECK-NEXT: asrgt r3, r7, #3 +; CHECK-NEXT: asrgt r6, r7, #3 ; CHECK-NEXT: add.w r7, r5, r4, lsl #1 -; CHECK-NEXT: str r3, [sp] @ 4-byte Spill -; CHECK-NEXT: subs r3, r7, #2 -; CHECK-NEXT: str r3, [sp, #20] @ 4-byte Spill -; CHECK-NEXT: rsbs r3, r4, #0 -; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill -; CHECK-NEXT: add.w r3, r12, #16 +; CHECK-NEXT: subs r7, #2 +; CHECK-NEXT: str r7, [sp, #20] @ 4-byte Spill +; CHECK-NEXT: rsbs r7, r4, #0 +; CHECK-NEXT: str r7, [sp, #8] @ 4-byte Spill +; CHECK-NEXT: add.w r7, r3, #16 +; CHECK-NEXT: str r6, [sp] @ 4-byte Spill ; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill -; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill +; CHECK-NEXT: str r7, [sp, #4] @ 4-byte Spill ; CHECK-NEXT: b .LBB16_4 ; CHECK-NEXT: .LBB16_3: @ %while.end ; CHECK-NEXT: @ in Loop: Header=BB16_4 Depth=1 ; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload -; CHECK-NEXT: subs.w r9, r9, #1 +; CHECK-NEXT: subs.w r12, r12, #1 ; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload ; CHECK-NEXT: vstrb.8 q0, [r2], #8 ; CHECK-NEXT: add.w r0, r5, r0, lsl #1 @@ -1117,16 +1115,16 @@ define void @fir(%struct.arm_fir_instance_f32* nocapture readonly %S, half* noca ; CHECK-NEXT: @ Child Loop BB16_6 Depth 2 ; CHECK-NEXT: @ Child Loop BB16_10 Depth 2 ; CHECK-NEXT: vldrw.u32 q0, [r1], #8 -; CHECK-NEXT: ldrh.w lr, [r12, #14] -; CHECK-NEXT: ldrh.w r0, [r12, #12] +; CHECK-NEXT: ldrh.w lr, [r3, #14] +; CHECK-NEXT: ldrh r0, [r3, #12] ; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill ; CHECK-NEXT: ldr r1, [sp, #20] @ 4-byte Reload -; CHECK-NEXT: ldrh.w r4, [r12, #10] -; CHECK-NEXT: ldrh.w r7, [r12, #8] -; CHECK-NEXT: ldrh.w r3, [r12, #6] -; CHECK-NEXT: ldrh.w r6, [r12, #4] -; CHECK-NEXT: ldrh.w r11, [r12, #2] -; CHECK-NEXT: ldrh.w r10, [r12] +; CHECK-NEXT: ldrh r4, [r3, #10] +; CHECK-NEXT: ldrh r7, [r3, #8] +; CHECK-NEXT: ldrh r6, [r3, #6] +; CHECK-NEXT: ldrh.w r9, [r3, #4] +; CHECK-NEXT: ldrh.w r11, [r3, #2] +; CHECK-NEXT: ldrh.w r10, [r3] ; CHECK-NEXT: vstrb.8 q0, [r1], #8 ; CHECK-NEXT: vldrw.u32 q0, [r5] ; CHECK-NEXT: str r1, [sp, #20] @ 4-byte Spill @@ -1136,10 +1134,10 @@ define void @fir(%struct.arm_fir_instance_f32* nocapture readonly %S, half* noca ; CHECK-NEXT: adds r1, r5, #6 ; CHECK-NEXT: vfma.f16 q0, q1, r11 ; CHECK-NEXT: vldrw.u32 q1, [r5, #4] -; CHECK-NEXT: vfma.f16 q0, q1, r6 +; CHECK-NEXT: vfma.f16 q0, q1, r9 ; CHECK-NEXT: vldrw.u32 q1, [r1] ; CHECK-NEXT: add.w r1, r5, #10 -; CHECK-NEXT: vfma.f16 q0, q1, r3 +; CHECK-NEXT: vfma.f16 q0, q1, r6 ; CHECK-NEXT: vldrw.u32 q1, [r5, #8] ; CHECK-NEXT: vfma.f16 q0, q1, r7 ; CHECK-NEXT: vldrw.u32 q1, [r1] diff --git a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll index b8c69146456cc..b0fa52b2b162b 100644 --- a/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll @@ -1049,36 +1049,34 @@ define void @fir(%struct.arm_fir_instance_f32* nocapture readonly %S, float* noc ; CHECK-NEXT: sub sp, #32 ; CHECK-NEXT: cmp r3, #8 ; CHECK-NEXT: blo.w .LBB16_12 -; CHECK-NEXT: @ %bb.1: @ %if.then -; CHECK-NEXT: movs r7, #0 -; CHECK-NEXT: cmp.w r7, r3, lsr #2 +; CHECK-NEXT: @ %bb.1: @ %entry +; CHECK-NEXT: lsrs.w r12, r3, #2 ; CHECK-NEXT: beq.w .LBB16_12 ; CHECK-NEXT: @ %bb.2: @ %while.body.lr.ph -; CHECK-NEXT: ldrh r4, [r0] -; CHECK-NEXT: lsr.w r10, r3, #2 -; CHECK-NEXT: ldrd r5, r12, [r0, #4] -; CHECK-NEXT: movs r3, #1 -; CHECK-NEXT: sub.w r7, r4, #8 -; CHECK-NEXT: add.w r0, r7, r7, lsr #29 -; CHECK-NEXT: asrs r6, r0, #3 -; CHECK-NEXT: cmp r6, #1 +; CHECK-NEXT: ldrh r6, [r0] +; CHECK-NEXT: movs r4, #1 +; CHECK-NEXT: ldrd r5, r10, [r0, #4] +; CHECK-NEXT: sub.w r3, r6, #8 +; CHECK-NEXT: add.w r0, r3, r3, lsr #29 +; CHECK-NEXT: asrs r7, r0, #3 +; CHECK-NEXT: cmp r7, #1 ; CHECK-NEXT: it gt -; CHECK-NEXT: asrgt r3, r0, #3 -; CHECK-NEXT: add.w r0, r5, r4, lsl #2 +; CHECK-NEXT: asrgt r4, r0, #3 +; CHECK-NEXT: add.w r0, r5, r6, lsl #2 ; CHECK-NEXT: sub.w r9, r0, #4 -; CHECK-NEXT: rsbs r0, r4, #0 -; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill -; CHECK-NEXT: and r3, r7, #7 +; CHECK-NEXT: rsbs r0, r6, #0 +; CHECK-NEXT: str r4, [sp, #4] @ 4-byte Spill +; CHECK-NEXT: and r4, r3, #7 ; CHECK-NEXT: str r0, [sp, #16] @ 4-byte Spill -; CHECK-NEXT: add.w r0, r12, #32 -; CHECK-NEXT: str r4, [sp, #20] @ 4-byte Spill +; CHECK-NEXT: add.w r0, r10, #32 +; CHECK-NEXT: str r6, [sp, #20] @ 4-byte Spill ; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill -; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill +; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill ; CHECK-NEXT: b .LBB16_4 ; CHECK-NEXT: .LBB16_3: @ %while.end ; CHECK-NEXT: @ in Loop: Header=BB16_4 Depth=1 ; CHECK-NEXT: ldr r0, [sp, #16] @ 4-byte Reload -; CHECK-NEXT: subs.w r10, r10, #1 +; CHECK-NEXT: subs.w r12, r12, #1 ; CHECK-NEXT: vstrb.8 q0, [r2], #16 ; CHECK-NEXT: add.w r0, r5, r0, lsl #2 ; CHECK-NEXT: add.w r5, r0, #16 @@ -1087,25 +1085,25 @@ define void @fir(%struct.arm_fir_instance_f32* nocapture readonly %S, float* noc ; CHECK-NEXT: @ =>This Loop Header: Depth=1 ; CHECK-NEXT: @ Child Loop BB16_6 Depth 2 ; CHECK-NEXT: @ Child Loop BB16_10 Depth 2 +; CHECK-NEXT: add.w lr, r10, #8 ; CHECK-NEXT: vldrw.u32 q0, [r1], #16 -; CHECK-NEXT: ldrd r7, r6, [r12] -; CHECK-NEXT: ldrd r0, r4, [r12, #8] -; CHECK-NEXT: ldrd r3, lr, [r12, #16] -; CHECK-NEXT: ldrd r11, r8, [r12, #24] +; CHECK-NEXT: ldrd r3, r7, [r10] +; CHECK-NEXT: ldm.w lr, {r0, r4, r6, lr} +; CHECK-NEXT: ldrd r11, r8, [r10, #24] ; CHECK-NEXT: vstrb.8 q0, [r9], #16 ; CHECK-NEXT: vldrw.u32 q0, [r5], #32 ; CHECK-NEXT: strd r9, r1, [sp, #24] @ 8-byte Folded Spill ; CHECK-NEXT: vldrw.u32 q1, [r5, #-28] -; CHECK-NEXT: vmul.f32 q0, q0, r7 +; CHECK-NEXT: vmul.f32 q0, q0, r3 ; CHECK-NEXT: vldrw.u32 q6, [r5, #-24] ; CHECK-NEXT: vldrw.u32 q4, [r5, #-20] -; CHECK-NEXT: vfma.f32 q0, q1, r6 +; CHECK-NEXT: vfma.f32 q0, q1, r7 ; CHECK-NEXT: vldrw.u32 q5, [r5, #-16] ; CHECK-NEXT: vfma.f32 q0, q6, r0 ; CHECK-NEXT: vldrw.u32 q2, [r5, #-12] ; CHECK-NEXT: vfma.f32 q0, q4, r4 ; CHECK-NEXT: vldrw.u32 q3, [r5, #-8] -; CHECK-NEXT: vfma.f32 q0, q5, r3 +; CHECK-NEXT: vfma.f32 q0, q5, r6 ; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload ; CHECK-NEXT: vfma.f32 q0, q2, lr ; CHECK-NEXT: vldrw.u32 q1, [r5, #-4] @@ -1149,26 +1147,26 @@ define void @fir(%struct.arm_fir_instance_f32* nocapture readonly %S, float* noc ; CHECK-NEXT: .LBB16_8: @ %for.end ; CHECK-NEXT: @ in Loop: Header=BB16_4 Depth=1 ; CHECK-NEXT: ldrd r9, r1, [sp, #24] @ 8-byte Folded Reload -; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload -; CHECK-NEXT: cmp.w r3, #0 +; CHECK-NEXT: ldr r4, [sp, #12] @ 4-byte Reload +; CHECK-NEXT: cmp.w r4, #0 ; CHECK-NEXT: beq .LBB16_3 ; CHECK-NEXT: b .LBB16_9 ; CHECK-NEXT: .LBB16_9: @ %while.body76.preheader ; CHECK-NEXT: @ in Loop: Header=BB16_4 Depth=1 -; CHECK-NEXT: mov r6, r5 -; CHECK-NEXT: mov lr, r3 +; CHECK-NEXT: mov r3, r5 +; CHECK-NEXT: mov lr, r4 ; CHECK-NEXT: .LBB16_10: @ %while.body76 ; CHECK-NEXT: @ Parent Loop BB16_4 Depth=1 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 ; CHECK-NEXT: ldr r0, [r7], #4 -; CHECK-NEXT: vldrw.u32 q1, [r6], #4 +; CHECK-NEXT: vldrw.u32 q1, [r3], #4 ; CHECK-NEXT: subs.w lr, lr, #1 ; CHECK-NEXT: vfma.f32 q0, q1, r0 ; CHECK-NEXT: bne .LBB16_10 ; CHECK-NEXT: b .LBB16_11 ; CHECK-NEXT: .LBB16_11: @ %while.end.loopexit ; CHECK-NEXT: @ in Loop: Header=BB16_4 Depth=1 -; CHECK-NEXT: add.w r5, r5, r3, lsl #2 +; CHECK-NEXT: add.w r5, r5, r4, lsl #2 ; CHECK-NEXT: b .LBB16_3 ; CHECK-NEXT: .LBB16_12: @ %if.end ; CHECK-NEXT: add sp, #32 @@ -1592,7 +1590,7 @@ define arm_aapcs_vfpcc void @fms(float* nocapture readonly %pSrc1, float* nocapt ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 ; CHECK-NEXT: vldrw.u32 q1, [r1], #16 ; CHECK-NEXT: vldrw.u32 q2, [r0], #16 -; CHECK-NEXT: vfms.f32 q2, q0, q1 +; CHECK-NEXT: vfms.f32 q2, q1, q0 ; CHECK-NEXT: vstrb.8 q2, [r3], #16 ; CHECK-NEXT: le lr, .LBB18_3 ; CHECK-NEXT: @ %bb.4: @ %while.end diff --git a/llvm/test/CodeGen/Thumb2/mve-fma-loops.ll b/llvm/test/CodeGen/Thumb2/mve-fma-loops.ll index 33f8e1c1b2243..77faf646b5cb8 100644 --- a/llvm/test/CodeGen/Thumb2/mve-fma-loops.ll +++ b/llvm/test/CodeGen/Thumb2/mve-fma-loops.ll @@ -403,8 +403,8 @@ define arm_aapcs_vfpcc void @fmss3(float* nocapture readonly %x, float* nocaptur ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: add.w r12, r12, #4 ; CHECK-NEXT: vmov q3, q0 -; CHECK-NEXT: vldrw.u32 q1, [r1], #16 -; CHECK-NEXT: vldrw.u32 q2, [r0], #16 +; CHECK-NEXT: vldrw.u32 q1, [r0], #16 +; CHECK-NEXT: vldrw.u32 q2, [r1], #16 ; CHECK-NEXT: vfms.f32 q3, q2, q1 ; CHECK-NEXT: vstrw.32 q3, [r2], #16 ; CHECK-NEXT: letp lr, .LBB6_2 diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll index b752aa28e3c3e..f44a5e0a602c2 100644 --- a/llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll +++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll @@ -82,7 +82,7 @@ entry: define arm_aapcs_vfpcc <8 x half> @test_vfmsq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c) { ; CHECK-LABEL: test_vfmsq_f16: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vfms.f16 q0, q1, q2 +; CHECK-NEXT: vfms.f16 q0, q2, q1 ; CHECK-NEXT: bx lr entry: %0 = fneg <8 x half> %c @@ -93,7 +93,7 @@ entry: define arm_aapcs_vfpcc <4 x float> @test_vfmsq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) { ; CHECK-LABEL: test_vfmsq_f32: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vfms.f32 q0, q1, q2 +; CHECK-NEXT: vfms.f32 q0, q2, q1 ; CHECK-NEXT: bx lr entry: %0 = fneg <4 x float> %c diff --git a/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll b/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll index ea9ce9e51a7a3..b297ea03ecee6 100644 --- a/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll +++ b/llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll @@ -213,14 +213,14 @@ define i8* @test(i8* nocapture readonly %input_row, i8* nocapture readonly %inpu ; CHECK-NEXT: cmp r3, #4 ; CHECK-NEXT: strd r0, r1, [sp, #12] @ 8-byte Folded Spill ; CHECK-NEXT: bne .LBB2_8 -; CHECK-NEXT: @ %bb.1: @ %for.cond.preheader +; CHECK-NEXT: @ %bb.1: @ %entry ; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: beq .LBB2_8 ; CHECK-NEXT: @ %bb.2: @ %for.body.lr.ph ; CHECK-NEXT: ldr r3, [sp, #64] ; CHECK-NEXT: mov.w r9, #0 ; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload -; CHECK-NEXT: ldr.w r11, [sp, #56] +; CHECK-NEXT: ldr r4, [sp, #56] ; CHECK-NEXT: add.w r0, r1, r3, lsl #1 ; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill ; CHECK-NEXT: adds r0, r1, r3 @@ -229,57 +229,57 @@ define i8* @test(i8* nocapture readonly %input_row, i8* nocapture readonly %inpu ; CHECK-NEXT: add r0, r1 ; CHECK-NEXT: str r0, [sp] @ 4-byte Spill ; CHECK-NEXT: adds r0, r3, #7 -; CHECK-NEXT: lsrs r0, r0, #3 +; CHECK-NEXT: lsr.w r11, r0, #3 ; CHECK-NEXT: b .LBB2_5 ; CHECK-NEXT: .LBB2_3: @ in Loop: Header=BB2_5 Depth=1 -; CHECK-NEXT: mov r10, r12 -; CHECK-NEXT: mov r8, r12 -; CHECK-NEXT: mov r6, r12 +; CHECK-NEXT: mov r12, r10 +; CHECK-NEXT: mov r8, r10 +; CHECK-NEXT: mov r6, r10 ; CHECK-NEXT: .LBB2_4: @ %for.cond.cleanup23 ; CHECK-NEXT: @ in Loop: Header=BB2_5 Depth=1 -; CHECK-NEXT: ldr r3, [sp, #72] -; CHECK-NEXT: add.w r1, r8, r10 -; CHECK-NEXT: add r1, r6 -; CHECK-NEXT: add r1, r12 -; CHECK-NEXT: strb.w r1, [r3, r9] +; CHECK-NEXT: ldr r1, [sp, #72] +; CHECK-NEXT: add.w r0, r8, r12 +; CHECK-NEXT: add r0, r6 +; CHECK-NEXT: add r0, r10 +; CHECK-NEXT: strb.w r0, [r1, r9] ; CHECK-NEXT: add.w r9, r9, #1 ; CHECK-NEXT: cmp r9, r2 ; CHECK-NEXT: beq .LBB2_8 ; CHECK-NEXT: .LBB2_5: @ %for.body ; CHECK-NEXT: @ =>This Loop Header: Depth=1 ; CHECK-NEXT: @ Child Loop BB2_7 Depth 2 -; CHECK-NEXT: ldr r1, [sp, #68] -; CHECK-NEXT: ldr.w r12, [r1, r9, lsl #2] -; CHECK-NEXT: subs r1, r0, r0 +; CHECK-NEXT: ldr r0, [sp, #68] +; CHECK-NEXT: ldr.w r10, [r0, r9, lsl #2] +; CHECK-NEXT: subs.w r0, r11, r11 ; CHECK-NEXT: ble .LBB2_3 ; CHECK-NEXT: @ %bb.6: @ %for.body24.preheader ; CHECK-NEXT: @ in Loop: Header=BB2_5 Depth=1 -; CHECK-NEXT: ldr r7, [sp, #64] -; CHECK-NEXT: mov r6, r12 -; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload -; CHECK-NEXT: dls lr, r1 +; CHECK-NEXT: ldr r3, [sp, #64] +; CHECK-NEXT: mov r6, r10 +; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload +; CHECK-NEXT: dls lr, r0 +; CHECK-NEXT: ldrd r5, r0, [sp] @ 8-byte Folded Reload +; CHECK-NEXT: mov r8, r10 +; CHECK-NEXT: mla r7, r9, r3, r1 ; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload -; CHECK-NEXT: mov r8, r12 -; CHECK-NEXT: mla r7, r9, r7, r3 -; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload -; CHECK-NEXT: ldrd r4, r3, [sp] @ 8-byte Folded Reload -; CHECK-NEXT: mov r10, r12 +; CHECK-NEXT: ldr r3, [sp, #8] @ 4-byte Reload +; CHECK-NEXT: mov r12, r10 ; CHECK-NEXT: .LBB2_7: @ %for.body24 ; CHECK-NEXT: @ Parent Loop BB2_5 Depth=1 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 -; CHECK-NEXT: vldrb.s16 q0, [r4], #8 -; CHECK-NEXT: vadd.i16 q1, q0, r11 +; CHECK-NEXT: vldrb.s16 q0, [r5], #8 +; CHECK-NEXT: vadd.i16 q1, q0, r4 ; CHECK-NEXT: vldrb.s16 q0, [r7], #8 -; CHECK-NEXT: vmlava.s16 r12, q0, q1 -; CHECK-NEXT: vldrb.s16 q1, [r5], #8 -; CHECK-NEXT: vadd.i16 q1, q1, r11 -; CHECK-NEXT: vmlava.s16 r6, q0, q1 +; CHECK-NEXT: vmlava.s16 r10, q0, q1 ; CHECK-NEXT: vldrb.s16 q1, [r3], #8 -; CHECK-NEXT: vadd.i16 q1, q1, r11 +; CHECK-NEXT: vadd.i16 q1, q1, r4 +; CHECK-NEXT: vmlava.s16 r6, q0, q1 +; CHECK-NEXT: vldrb.s16 q1, [r0], #8 +; CHECK-NEXT: vadd.i16 q1, q1, r4 ; CHECK-NEXT: vmlava.s16 r8, q0, q1 ; CHECK-NEXT: vldrb.s16 q1, [r1], #8 -; CHECK-NEXT: vadd.i16 q1, q1, r11 -; CHECK-NEXT: vmlava.s16 r10, q0, q1 +; CHECK-NEXT: vadd.i16 q1, q1, r4 +; CHECK-NEXT: vmlava.s16 r12, q0, q1 ; CHECK-NEXT: le lr, .LBB2_7 ; CHECK-NEXT: b .LBB2_4 ; CHECK-NEXT: .LBB2_8: @ %if.end @@ -396,14 +396,14 @@ define i8* @test_optsize(i8* nocapture readonly %input_row, i8* nocapture readon ; CHECK-NEXT: cmp r3, #4 ; CHECK-NEXT: strd r0, r1, [sp, #12] @ 8-byte Folded Spill ; CHECK-NEXT: bne .LBB3_8 -; CHECK-NEXT: @ %bb.1: @ %for.cond.preheader +; CHECK-NEXT: @ %bb.1: @ %entry ; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: beq .LBB3_8 ; CHECK-NEXT: @ %bb.2: @ %for.body.lr.ph ; CHECK-NEXT: ldr r3, [sp, #64] ; CHECK-NEXT: mov.w r9, #0 ; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload -; CHECK-NEXT: ldr.w r11, [sp, #56] +; CHECK-NEXT: ldr r4, [sp, #56] ; CHECK-NEXT: add.w r0, r1, r3, lsl #1 ; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill ; CHECK-NEXT: adds r0, r1, r3 @@ -412,55 +412,55 @@ define i8* @test_optsize(i8* nocapture readonly %input_row, i8* nocapture readon ; CHECK-NEXT: add r0, r1 ; CHECK-NEXT: str r0, [sp] @ 4-byte Spill ; CHECK-NEXT: adds r0, r3, #7 -; CHECK-NEXT: lsrs r0, r0, #3 +; CHECK-NEXT: lsr.w r11, r0, #3 ; CHECK-NEXT: .LBB3_3: @ %for.body ; CHECK-NEXT: @ =>This Loop Header: Depth=1 ; CHECK-NEXT: @ Child Loop BB3_5 Depth 2 -; CHECK-NEXT: ldr r1, [sp, #68] -; CHECK-NEXT: ldr.w r12, [r1, r9, lsl #2] -; CHECK-NEXT: subs r1, r0, r0 +; CHECK-NEXT: ldr r0, [sp, #68] +; CHECK-NEXT: ldr.w r10, [r0, r9, lsl #2] +; CHECK-NEXT: subs.w r0, r11, r11 ; CHECK-NEXT: ble .LBB3_6 ; CHECK-NEXT: @ %bb.4: @ %for.body24.preheader ; CHECK-NEXT: @ in Loop: Header=BB3_3 Depth=1 -; CHECK-NEXT: ldr r7, [sp, #64] -; CHECK-NEXT: mov r6, r12 -; CHECK-NEXT: ldr r3, [sp, #12] @ 4-byte Reload -; CHECK-NEXT: dls lr, r1 +; CHECK-NEXT: ldr r3, [sp, #64] +; CHECK-NEXT: mov r6, r10 +; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload +; CHECK-NEXT: dls lr, r0 +; CHECK-NEXT: ldrd r5, r0, [sp] @ 8-byte Folded Reload +; CHECK-NEXT: mov r8, r10 +; CHECK-NEXT: mla r7, r9, r3, r1 ; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload -; CHECK-NEXT: mov r8, r12 -; CHECK-NEXT: mla r7, r9, r7, r3 -; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload -; CHECK-NEXT: ldrd r4, r3, [sp] @ 8-byte Folded Reload -; CHECK-NEXT: mov r10, r12 +; CHECK-NEXT: ldr r3, [sp, #8] @ 4-byte Reload +; CHECK-NEXT: mov r12, r10 ; CHECK-NEXT: .LBB3_5: @ %for.body24 ; CHECK-NEXT: @ Parent Loop BB3_3 Depth=1 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 -; CHECK-NEXT: vldrb.s16 q0, [r4], #8 -; CHECK-NEXT: vadd.i16 q1, q0, r11 +; CHECK-NEXT: vldrb.s16 q0, [r5], #8 +; CHECK-NEXT: vadd.i16 q1, q0, r4 ; CHECK-NEXT: vldrb.s16 q0, [r7], #8 -; CHECK-NEXT: vmlava.s16 r12, q0, q1 -; CHECK-NEXT: vldrb.s16 q1, [r5], #8 -; CHECK-NEXT: vadd.i16 q1, q1, r11 -; CHECK-NEXT: vmlava.s16 r6, q0, q1 +; CHECK-NEXT: vmlava.s16 r10, q0, q1 ; CHECK-NEXT: vldrb.s16 q1, [r3], #8 -; CHECK-NEXT: vadd.i16 q1, q1, r11 +; CHECK-NEXT: vadd.i16 q1, q1, r4 +; CHECK-NEXT: vmlava.s16 r6, q0, q1 +; CHECK-NEXT: vldrb.s16 q1, [r0], #8 +; CHECK-NEXT: vadd.i16 q1, q1, r4 ; CHECK-NEXT: vmlava.s16 r8, q0, q1 ; CHECK-NEXT: vldrb.s16 q1, [r1], #8 -; CHECK-NEXT: vadd.i16 q1, q1, r11 -; CHECK-NEXT: vmlava.s16 r10, q0, q1 +; CHECK-NEXT: vadd.i16 q1, q1, r4 +; CHECK-NEXT: vmlava.s16 r12, q0, q1 ; CHECK-NEXT: le lr, .LBB3_5 ; CHECK-NEXT: b .LBB3_7 ; CHECK-NEXT: .LBB3_6: @ in Loop: Header=BB3_3 Depth=1 -; CHECK-NEXT: mov r10, r12 -; CHECK-NEXT: mov r8, r12 -; CHECK-NEXT: mov r6, r12 +; CHECK-NEXT: mov r12, r10 +; CHECK-NEXT: mov r8, r10 +; CHECK-NEXT: mov r6, r10 ; CHECK-NEXT: .LBB3_7: @ %for.cond.cleanup23 ; CHECK-NEXT: @ in Loop: Header=BB3_3 Depth=1 -; CHECK-NEXT: ldr r3, [sp, #72] -; CHECK-NEXT: add.w r1, r8, r10 -; CHECK-NEXT: add r1, r6 -; CHECK-NEXT: add r1, r12 -; CHECK-NEXT: strb.w r1, [r3, r9] +; CHECK-NEXT: ldr r1, [sp, #72] +; CHECK-NEXT: add.w r0, r8, r12 +; CHECK-NEXT: add r0, r6 +; CHECK-NEXT: add r0, r10 +; CHECK-NEXT: strb.w r0, [r1, r9] ; CHECK-NEXT: add.w r9, r9, #1 ; CHECK-NEXT: cmp r9, r2 ; CHECK-NEXT: bne .LBB3_3 @@ -689,7 +689,7 @@ define i8* @signext(i8* %input_row, i8* %input_col, i16 zeroext %output_ch, i16 ; CHECK-NEXT: cmp r3, #4 ; CHECK-NEXT: stm.w r12, {r0, r1, r2} @ 12-byte Folded Spill ; CHECK-NEXT: bne .LBB5_8 -; CHECK-NEXT: @ %bb.1: @ %for.cond.preheader +; CHECK-NEXT: @ %bb.1: @ %entry ; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: beq .LBB5_8 @@ -697,7 +697,7 @@ define i8* @signext(i8* %input_row, i8* %input_col, i16 zeroext %output_ch, i16 ; CHECK-NEXT: ldr r2, [sp, #88] ; CHECK-NEXT: mov.w r9, #0 ; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload -; CHECK-NEXT: ldr r4, [sp, #72] +; CHECK-NEXT: ldr.w r10, [sp, #72] ; CHECK-NEXT: add.w r0, r1, r2, lsl #1 ; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill ; CHECK-NEXT: adds r0, r1, r2 @@ -709,15 +709,15 @@ define i8* @signext(i8* %input_row, i8* %input_col, i16 zeroext %output_ch, i16 ; CHECK-NEXT: lsrs r2, r0, #3 ; CHECK-NEXT: b .LBB5_5 ; CHECK-NEXT: .LBB5_3: @ in Loop: Header=BB5_5 Depth=1 -; CHECK-NEXT: mov r10, r12 -; CHECK-NEXT: mov r8, r12 -; CHECK-NEXT: mov r6, r12 +; CHECK-NEXT: mov r8, r0 +; CHECK-NEXT: mov r12, r0 +; CHECK-NEXT: mov r6, r0 ; CHECK-NEXT: .LBB5_4: @ %for.cond.cleanup23 ; CHECK-NEXT: @ in Loop: Header=BB5_5 Depth=1 -; CHECK-NEXT: add.w r0, r8, r10 +; CHECK-NEXT: add.w r1, r12, r8 +; CHECK-NEXT: add r1, r6 +; CHECK-NEXT: add r0, r1 ; CHECK-NEXT: ldr r1, [sp, #96] -; CHECK-NEXT: add r0, r6 -; CHECK-NEXT: add r0, r12 ; CHECK-NEXT: strb.w r0, [r1, r9] ; CHECK-NEXT: add.w r9, r9, #1 ; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload @@ -728,36 +728,35 @@ define i8* @signext(i8* %input_row, i8* %input_col, i16 zeroext %output_ch, i16 ; CHECK-NEXT: @ Child Loop BB5_7 Depth 2 ; CHECK-NEXT: ldr r0, [sp, #92] ; CHECK-NEXT: cmp r2, r2 -; CHECK-NEXT: ldr.w r12, [r0, r9, lsl #2] +; CHECK-NEXT: ldr.w r0, [r0, r9, lsl #2] ; CHECK-NEXT: bge .LBB5_3 ; CHECK-NEXT: @ %bb.6: @ %for.body24.preheader ; CHECK-NEXT: @ in Loop: Header=BB5_5 Depth=1 ; CHECK-NEXT: ldr.w r11, [sp, #88] -; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload -; CHECK-NEXT: mov r6, r12 +; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload +; CHECK-NEXT: mov r6, r0 ; CHECK-NEXT: dlstp.16 lr, r11 +; CHECK-NEXT: ldm.w sp, {r4, r5, r7} @ 12-byte Folded Reload +; CHECK-NEXT: mov r12, r0 +; CHECK-NEXT: mla r3, r9, r11, r1 ; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload -; CHECK-NEXT: mla r3, r9, r11, r0 -; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload -; CHECK-NEXT: ldrd r7, r5, [sp] @ 8-byte Folded Reload -; CHECK-NEXT: mov r8, r12 -; CHECK-NEXT: mov r10, r12 +; CHECK-NEXT: mov r8, r0 ; CHECK-NEXT: .LBB5_7: @ %for.body24 ; CHECK-NEXT: @ Parent Loop BB5_5 Depth=1 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 -; CHECK-NEXT: vldrb.s16 q0, [r7], #8 -; CHECK-NEXT: vadd.i16 q1, q0, r4 +; CHECK-NEXT: vldrb.s16 q0, [r4], #8 +; CHECK-NEXT: vadd.i16 q1, q0, r10 ; CHECK-NEXT: vldrb.s16 q0, [r3], #8 -; CHECK-NEXT: vmlava.s16 r12, q0, q1 -; CHECK-NEXT: vldrb.s16 q1, [r0], #8 -; CHECK-NEXT: vadd.i16 q1, q1, r4 +; CHECK-NEXT: vmlava.s16 r0, q0, q1 +; CHECK-NEXT: vldrb.s16 q1, [r7], #8 +; CHECK-NEXT: vadd.i16 q1, q1, r10 ; CHECK-NEXT: vmlava.s16 r6, q0, q1 ; CHECK-NEXT: vldrb.s16 q1, [r5], #8 -; CHECK-NEXT: vadd.i16 q1, q1, r4 -; CHECK-NEXT: vmlava.s16 r8, q0, q1 +; CHECK-NEXT: vadd.i16 q1, q1, r10 +; CHECK-NEXT: vmlava.s16 r12, q0, q1 ; CHECK-NEXT: vldrb.s16 q1, [r1], #8 -; CHECK-NEXT: vadd.i16 q1, q1, r4 -; CHECK-NEXT: vmlava.s16 r10, q0, q1 +; CHECK-NEXT: vadd.i16 q1, q1, r10 +; CHECK-NEXT: vmlava.s16 r8, q0, q1 ; CHECK-NEXT: letp lr, .LBB5_7 ; CHECK-NEXT: b .LBB5_4 ; CHECK-NEXT: .LBB5_8: @ %if.end @@ -877,7 +876,7 @@ define i8* @signext_optsize(i8* %input_row, i8* %input_col, i16 zeroext %output_ ; CHECK-NEXT: cmp r3, #4 ; CHECK-NEXT: stm.w r12, {r0, r1, r2} @ 12-byte Folded Spill ; CHECK-NEXT: bne .LBB6_8 -; CHECK-NEXT: @ %bb.1: @ %for.cond.preheader +; CHECK-NEXT: @ %bb.1: @ %entry ; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: beq .LBB6_8 @@ -885,7 +884,7 @@ define i8* @signext_optsize(i8* %input_row, i8* %input_col, i16 zeroext %output_ ; CHECK-NEXT: ldr r2, [sp, #88] ; CHECK-NEXT: mov.w r9, #0 ; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload -; CHECK-NEXT: ldr r4, [sp, #72] +; CHECK-NEXT: ldr.w r10, [sp, #72] ; CHECK-NEXT: add.w r0, r1, r2, lsl #1 ; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill ; CHECK-NEXT: adds r0, r1, r2 @@ -900,48 +899,47 @@ define i8* @signext_optsize(i8* %input_row, i8* %input_col, i16 zeroext %output_ ; CHECK-NEXT: @ Child Loop BB6_5 Depth 2 ; CHECK-NEXT: ldr r0, [sp, #92] ; CHECK-NEXT: cmp r2, r2 -; CHECK-NEXT: ldr.w r12, [r0, r9, lsl #2] +; CHECK-NEXT: ldr.w r0, [r0, r9, lsl #2] ; CHECK-NEXT: bge .LBB6_6 ; CHECK-NEXT: @ %bb.4: @ %for.body24.preheader ; CHECK-NEXT: @ in Loop: Header=BB6_3 Depth=1 ; CHECK-NEXT: ldr.w r11, [sp, #88] -; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload -; CHECK-NEXT: mov r6, r12 +; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload +; CHECK-NEXT: mov r6, r0 ; CHECK-NEXT: dlstp.16 lr, r11 +; CHECK-NEXT: ldm.w sp, {r4, r5, r7} @ 12-byte Folded Reload +; CHECK-NEXT: mov r12, r0 +; CHECK-NEXT: mla r3, r9, r11, r1 ; CHECK-NEXT: ldr r1, [sp, #16] @ 4-byte Reload -; CHECK-NEXT: mla r3, r9, r11, r0 -; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload -; CHECK-NEXT: ldrd r7, r5, [sp] @ 8-byte Folded Reload -; CHECK-NEXT: mov r8, r12 -; CHECK-NEXT: mov r10, r12 +; CHECK-NEXT: mov r8, r0 ; CHECK-NEXT: .LBB6_5: @ %for.body24 ; CHECK-NEXT: @ Parent Loop BB6_3 Depth=1 ; CHECK-NEXT: @ => This Inner Loop Header: Depth=2 -; CHECK-NEXT: vldrb.s16 q0, [r7], #8 -; CHECK-NEXT: vadd.i16 q1, q0, r4 +; CHECK-NEXT: vldrb.s16 q0, [r4], #8 +; CHECK-NEXT: vadd.i16 q1, q0, r10 ; CHECK-NEXT: vldrb.s16 q0, [r3], #8 -; CHECK-NEXT: vmlava.s16 r12, q0, q1 -; CHECK-NEXT: vldrb.s16 q1, [r0], #8 -; CHECK-NEXT: vadd.i16 q1, q1, r4 +; CHECK-NEXT: vmlava.s16 r0, q0, q1 +; CHECK-NEXT: vldrb.s16 q1, [r7], #8 +; CHECK-NEXT: vadd.i16 q1, q1, r10 ; CHECK-NEXT: vmlava.s16 r6, q0, q1 ; CHECK-NEXT: vldrb.s16 q1, [r5], #8 -; CHECK-NEXT: vadd.i16 q1, q1, r4 -; CHECK-NEXT: vmlava.s16 r8, q0, q1 +; CHECK-NEXT: vadd.i16 q1, q1, r10 +; CHECK-NEXT: vmlava.s16 r12, q0, q1 ; CHECK-NEXT: vldrb.s16 q1, [r1], #8 -; CHECK-NEXT: vadd.i16 q1, q1, r4 -; CHECK-NEXT: vmlava.s16 r10, q0, q1 +; CHECK-NEXT: vadd.i16 q1, q1, r10 +; CHECK-NEXT: vmlava.s16 r8, q0, q1 ; CHECK-NEXT: letp lr, .LBB6_5 ; CHECK-NEXT: b .LBB6_7 ; CHECK-NEXT: .LBB6_6: @ in Loop: Header=BB6_3 Depth=1 -; CHECK-NEXT: mov r10, r12 -; CHECK-NEXT: mov r8, r12 -; CHECK-NEXT: mov r6, r12 +; CHECK-NEXT: mov r8, r0 +; CHECK-NEXT: mov r12, r0 +; CHECK-NEXT: mov r6, r0 ; CHECK-NEXT: .LBB6_7: @ %for.cond.cleanup23 ; CHECK-NEXT: @ in Loop: Header=BB6_3 Depth=1 -; CHECK-NEXT: add.w r0, r8, r10 +; CHECK-NEXT: add.w r1, r12, r8 +; CHECK-NEXT: add r1, r6 +; CHECK-NEXT: add r0, r1 ; CHECK-NEXT: ldr r1, [sp, #96] -; CHECK-NEXT: add r0, r6 -; CHECK-NEXT: add r0, r12 ; CHECK-NEXT: strb.w r0, [r1, r9] ; CHECK-NEXT: add.w r9, r9, #1 ; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload diff --git a/llvm/test/CodeGen/Thumb2/mve-vabdus.ll b/llvm/test/CodeGen/Thumb2/mve-vabdus.ll new file mode 100644 index 0000000000000..cb82f9020d34d --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/mve-vabdus.ll @@ -0,0 +1,942 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s + +define arm_aapcs_vfpcc <16 x i8> @vabd_s8(<16 x i8> %src1, <16 x i8> %src2) { +; CHECK-LABEL: vabd_s8: +; CHECK: @ %bb.0: +; CHECK-NEXT: vmov.u8 r0, q1[0] +; CHECK-NEXT: vmov.16 q2[0], r0 +; CHECK-NEXT: vmov.u8 r0, q1[1] +; CHECK-NEXT: vmov.16 q2[1], r0 +; CHECK-NEXT: vmov.u8 r0, q1[2] +; CHECK-NEXT: vmov.16 q2[2], r0 +; CHECK-NEXT: vmov.u8 r0, q1[3] +; CHECK-NEXT: vmov.16 q2[3], r0 +; CHECK-NEXT: vmov.u8 r0, q1[4] +; CHECK-NEXT: vmov.16 q2[4], r0 +; CHECK-NEXT: vmov.u8 r0, q1[5] +; CHECK-NEXT: vmov.16 q2[5], r0 +; CHECK-NEXT: vmov.u8 r0, q1[6] +; CHECK-NEXT: vmov.16 q2[6], r0 +; CHECK-NEXT: vmov.u8 r0, q1[7] +; CHECK-NEXT: vmov.16 q2[7], r0 +; CHECK-NEXT: vmov.u8 r0, q0[0] +; CHECK-NEXT: vmov.16 q3[0], r0 +; CHECK-NEXT: vmov.u8 r0, q0[1] +; CHECK-NEXT: vmov.16 q3[1], r0 +; CHECK-NEXT: vmov.u8 r0, q0[2] +; CHECK-NEXT: vmov.16 q3[2], r0 +; CHECK-NEXT: vmov.u8 r0, q0[3] +; CHECK-NEXT: vmov.16 q3[3], r0 +; CHECK-NEXT: vmov.u8 r0, q0[4] +; CHECK-NEXT: vmov.16 q3[4], r0 +; CHECK-NEXT: vmov.u8 r0, q0[5] +; CHECK-NEXT: vmov.16 q3[5], r0 +; CHECK-NEXT: vmov.u8 r0, q0[6] +; CHECK-NEXT: vmov.16 q3[6], r0 +; CHECK-NEXT: vmov.u8 r0, q0[7] +; CHECK-NEXT: vmov.16 q3[7], r0 +; CHECK-NEXT: vmovlb.s8 q2, q2 +; CHECK-NEXT: vmovlb.s8 q3, q3 +; CHECK-NEXT: vsub.i16 q2, q3, q2 +; CHECK-NEXT: vabs.s16 q3, q2 +; CHECK-NEXT: vmov.u16 r0, q3[0] +; CHECK-NEXT: vmov.8 q2[0], r0 +; CHECK-NEXT: vmov.u16 r0, q3[1] +; CHECK-NEXT: vmov.8 q2[1], r0 +; CHECK-NEXT: vmov.u16 r0, q3[2] +; CHECK-NEXT: vmov.8 q2[2], r0 +; CHECK-NEXT: vmov.u16 r0, q3[3] +; CHECK-NEXT: vmov.8 q2[3], r0 +; CHECK-NEXT: vmov.u16 r0, q3[4] +; CHECK-NEXT: vmov.8 q2[4], r0 +; CHECK-NEXT: vmov.u16 r0, q3[5] +; CHECK-NEXT: vmov.8 q2[5], r0 +; CHECK-NEXT: vmov.u16 r0, q3[6] +; CHECK-NEXT: vmov.8 q2[6], r0 +; CHECK-NEXT: vmov.u16 r0, q3[7] +; CHECK-NEXT: vmov.8 q2[7], r0 +; CHECK-NEXT: vmov.u8 r0, q1[8] +; CHECK-NEXT: vmov.16 q3[0], r0 +; CHECK-NEXT: vmov.u8 r0, q1[9] +; CHECK-NEXT: vmov.16 q3[1], r0 +; CHECK-NEXT: vmov.u8 r0, q1[10] +; CHECK-NEXT: vmov.16 q3[2], r0 +; CHECK-NEXT: vmov.u8 r0, q1[11] +; CHECK-NEXT: vmov.16 q3[3], r0 +; CHECK-NEXT: vmov.u8 r0, q1[12] +; CHECK-NEXT: vmov.16 q3[4], r0 +; CHECK-NEXT: vmov.u8 r0, q1[13] +; CHECK-NEXT: vmov.16 q3[5], r0 +; CHECK-NEXT: vmov.u8 r0, q1[14] +; CHECK-NEXT: vmov.16 q3[6], r0 +; CHECK-NEXT: vmov.u8 r0, q1[15] +; CHECK-NEXT: vmov.16 q3[7], r0 +; CHECK-NEXT: vmov.u8 r0, q0[8] +; CHECK-NEXT: vmovlb.s8 q1, q3 +; CHECK-NEXT: vmov.16 q3[0], r0 +; CHECK-NEXT: vmov.u8 r0, q0[9] +; CHECK-NEXT: vmov.16 q3[1], r0 +; CHECK-NEXT: vmov.u8 r0, q0[10] +; CHECK-NEXT: vmov.16 q3[2], r0 +; CHECK-NEXT: vmov.u8 r0, q0[11] +; CHECK-NEXT: vmov.16 q3[3], r0 +; CHECK-NEXT: vmov.u8 r0, q0[12] +; CHECK-NEXT: vmov.16 q3[4], r0 +; CHECK-NEXT: vmov.u8 r0, q0[13] +; CHECK-NEXT: vmov.16 q3[5], r0 +; CHECK-NEXT: vmov.u8 r0, q0[14] +; CHECK-NEXT: vmov.16 q3[6], r0 +; CHECK-NEXT: vmov.u8 r0, q0[15] +; CHECK-NEXT: vmov.16 q3[7], r0 +; CHECK-NEXT: vmovlb.s8 q0, q3 +; CHECK-NEXT: vsub.i16 q0, q0, q1 +; CHECK-NEXT: vabs.s16 q0, q0 +; CHECK-NEXT: vmov.u16 r0, q0[0] +; CHECK-NEXT: vmov.8 q2[8], r0 +; CHECK-NEXT: vmov.u16 r0, q0[1] +; CHECK-NEXT: vmov.8 q2[9], r0 +; CHECK-NEXT: vmov.u16 r0, q0[2] +; CHECK-NEXT: vmov.8 q2[10], r0 +; CHECK-NEXT: vmov.u16 r0, q0[3] +; CHECK-NEXT: vmov.8 q2[11], r0 +; CHECK-NEXT: vmov.u16 r0, q0[4] +; CHECK-NEXT: vmov.8 q2[12], r0 +; CHECK-NEXT: vmov.u16 r0, q0[5] +; CHECK-NEXT: vmov.8 q2[13], r0 +; CHECK-NEXT: vmov.u16 r0, q0[6] +; CHECK-NEXT: vmov.8 q2[14], r0 +; CHECK-NEXT: vmov.u16 r0, q0[7] +; CHECK-NEXT: vmov.8 q2[15], r0 +; CHECK-NEXT: vmov q0, q2 +; CHECK-NEXT: bx lr + %sextsrc1 = sext <16 x i8> %src1 to <16 x i16> + %sextsrc2 = sext <16 x i8> %src2 to <16 x i16> + %add1 = sub <16 x i16> %sextsrc1, %sextsrc2 + %add2 = sub <16 x i16> zeroinitializer, %add1 + %c = icmp sge <16 x i16> %add1, zeroinitializer + %s = select <16 x i1> %c, <16 x i16> %add1, <16 x i16> %add2 + %result = trunc <16 x i16> %s to <16 x i8> + ret <16 x i8> %result +} + +define arm_aapcs_vfpcc <8 x i16> @vabd_s16(<8 x i16> %src1, <8 x i16> %src2) { +; CHECK-LABEL: vabd_s16: +; CHECK: @ %bb.0: +; CHECK-NEXT: vmov.u16 r0, q1[0] +; CHECK-NEXT: vmov.32 q2[0], r0 +; CHECK-NEXT: vmov.u16 r0, q1[1] +; CHECK-NEXT: vmov.32 q2[1], r0 +; CHECK-NEXT: vmov.u16 r0, q1[2] +; CHECK-NEXT: vmov.32 q2[2], r0 +; CHECK-NEXT: vmov.u16 r0, q1[3] +; CHECK-NEXT: vmov.32 q2[3], r0 +; CHECK-NEXT: vmov.u16 r0, q0[0] +; CHECK-NEXT: vmov.32 q3[0], r0 +; CHECK-NEXT: vmov.u16 r0, q0[1] +; CHECK-NEXT: vmov.32 q3[1], r0 +; CHECK-NEXT: vmov.u16 r0, q0[2] +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.u16 r0, q0[3] +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: vmovlb.s16 q2, q2 +; CHECK-NEXT: vmovlb.s16 q3, q3 +; CHECK-NEXT: vsub.i32 q2, q3, q2 +; CHECK-NEXT: vabs.s32 q3, q2 +; CHECK-NEXT: vmov r0, s12 +; CHECK-NEXT: vmov.16 q2[0], r0 +; CHECK-NEXT: vmov r0, s13 +; CHECK-NEXT: vmov.16 q2[1], r0 +; CHECK-NEXT: vmov r0, s14 +; CHECK-NEXT: vmov.16 q2[2], r0 +; CHECK-NEXT: vmov r0, s15 +; CHECK-NEXT: vmov.16 q2[3], r0 +; CHECK-NEXT: vmov.u16 r0, q1[4] +; CHECK-NEXT: vmov.32 q3[0], r0 +; CHECK-NEXT: vmov.u16 r0, q1[5] +; CHECK-NEXT: vmov.32 q3[1], r0 +; CHECK-NEXT: vmov.u16 r0, q1[6] +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.u16 r0, q1[7] +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: vmov.u16 r0, q0[4] +; CHECK-NEXT: vmovlb.s16 q1, q3 +; CHECK-NEXT: vmov.32 q3[0], r0 +; CHECK-NEXT: vmov.u16 r0, q0[5] +; CHECK-NEXT: vmov.32 q3[1], r0 +; CHECK-NEXT: vmov.u16 r0, q0[6] +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.u16 r0, q0[7] +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: vmovlb.s16 q0, q3 +; CHECK-NEXT: vsub.i32 q0, q0, q1 +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vmov r0, s0 +; CHECK-NEXT: vmov.16 q2[4], r0 +; CHECK-NEXT: vmov r0, s1 +; CHECK-NEXT: vmov.16 q2[5], r0 +; CHECK-NEXT: vmov r0, s2 +; CHECK-NEXT: vmov.16 q2[6], r0 +; CHECK-NEXT: vmov r0, s3 +; CHECK-NEXT: vmov.16 q2[7], r0 +; CHECK-NEXT: vmov q0, q2 +; CHECK-NEXT: bx lr + %sextsrc1 = sext <8 x i16> %src1 to <8 x i32> + %sextsrc2 = sext <8 x i16> %src2 to <8 x i32> + %add1 = sub <8 x i32> %sextsrc1, %sextsrc2 + %add2 = sub <8 x i32> zeroinitializer, %add1 + %c = icmp sge <8 x i32> %add1, zeroinitializer + %s = select <8 x i1> %c, <8 x i32> %add1, <8 x i32> %add2 + %result = trunc <8 x i32> %s to <8 x i16> + ret <8 x i16> %result +} + +define arm_aapcs_vfpcc <4 x i32> @vabd_s32(<4 x i32> %src1, <4 x i32> %src2) { +; CHECK-LABEL: vabd_s32: +; CHECK: @ %bb.0: +; CHECK-NEXT: vmov.f32 s8, s0 +; CHECK-NEXT: vmov.f32 s12, s4 +; CHECK-NEXT: vmov.f32 s10, s1 +; CHECK-NEXT: vmov.f32 s14, s5 +; CHECK-NEXT: vmov r3, s12 +; CHECK-NEXT: vmov r0, s10 +; CHECK-NEXT: vmov r2, s14 +; CHECK-NEXT: vmov.f32 s12, s2 +; CHECK-NEXT: vmov.f32 s14, s3 +; CHECK-NEXT: vmov.f32 s0, s6 +; CHECK-NEXT: vmov.f32 s2, s7 +; CHECK-NEXT: asrs r1, r0, #31 +; CHECK-NEXT: subs r0, r0, r2 +; CHECK-NEXT: sbc.w r1, r1, r2, asr #31 +; CHECK-NEXT: add.w r0, r0, r1, asr #31 +; CHECK-NEXT: eor.w r0, r0, r1, asr #31 +; CHECK-NEXT: vmov r1, s8 +; CHECK-NEXT: asrs r2, r1, #31 +; CHECK-NEXT: subs r1, r1, r3 +; CHECK-NEXT: sbc.w r2, r2, r3, asr #31 +; CHECK-NEXT: add.w r1, r1, r2, asr #31 +; CHECK-NEXT: eor.w r1, r1, r2, asr #31 +; CHECK-NEXT: vmov r2, s0 +; CHECK-NEXT: vmov.32 q2[0], r1 +; CHECK-NEXT: vmov.32 q2[1], r0 +; CHECK-NEXT: vmov r0, s12 +; CHECK-NEXT: asrs r1, r0, #31 +; CHECK-NEXT: subs r0, r0, r2 +; CHECK-NEXT: sbc.w r1, r1, r2, asr #31 +; CHECK-NEXT: vmov r2, s2 +; CHECK-NEXT: add.w r0, r0, r1, asr #31 +; CHECK-NEXT: eor.w r0, r0, r1, asr #31 +; CHECK-NEXT: vmov.32 q2[2], r0 +; CHECK-NEXT: vmov r0, s14 +; CHECK-NEXT: asrs r1, r0, #31 +; CHECK-NEXT: subs r0, r0, r2 +; CHECK-NEXT: sbc.w r1, r1, r2, asr #31 +; CHECK-NEXT: add.w r0, r0, r1, asr #31 +; CHECK-NEXT: eor.w r0, r0, r1, asr #31 +; CHECK-NEXT: vmov.32 q2[3], r0 +; CHECK-NEXT: vmov q0, q2 +; CHECK-NEXT: bx lr + %sextsrc1 = sext <4 x i32> %src1 to <4 x i64> + %sextsrc2 = sext <4 x i32> %src2 to <4 x i64> + %add1 = sub <4 x i64> %sextsrc1, %sextsrc2 + %add2 = sub <4 x i64> zeroinitializer, %add1 + %c = icmp sge <4 x i64> %add1, zeroinitializer + %s = select <4 x i1> %c, <4 x i64> %add1, <4 x i64> %add2 + %result = trunc <4 x i64> %s to <4 x i32> + ret <4 x i32> %result +} + +define arm_aapcs_vfpcc <16 x i8> @vabd_u8(<16 x i8> %src1, <16 x i8> %src2) { +; CHECK-LABEL: vabd_u8: +; CHECK: @ %bb.0: +; CHECK-NEXT: vmov.u8 r0, q1[0] +; CHECK-NEXT: vmov.16 q2[0], r0 +; CHECK-NEXT: vmov.u8 r0, q1[1] +; CHECK-NEXT: vmov.16 q2[1], r0 +; CHECK-NEXT: vmov.u8 r0, q1[2] +; CHECK-NEXT: vmov.16 q2[2], r0 +; CHECK-NEXT: vmov.u8 r0, q1[3] +; CHECK-NEXT: vmov.16 q2[3], r0 +; CHECK-NEXT: vmov.u8 r0, q1[4] +; CHECK-NEXT: vmov.16 q2[4], r0 +; CHECK-NEXT: vmov.u8 r0, q1[5] +; CHECK-NEXT: vmov.16 q2[5], r0 +; CHECK-NEXT: vmov.u8 r0, q1[6] +; CHECK-NEXT: vmov.16 q2[6], r0 +; CHECK-NEXT: vmov.u8 r0, q1[7] +; CHECK-NEXT: vmov.16 q2[7], r0 +; CHECK-NEXT: vmov.u8 r0, q0[0] +; CHECK-NEXT: vmov.16 q3[0], r0 +; CHECK-NEXT: vmov.u8 r0, q0[1] +; CHECK-NEXT: vmov.16 q3[1], r0 +; CHECK-NEXT: vmov.u8 r0, q0[2] +; CHECK-NEXT: vmov.16 q3[2], r0 +; CHECK-NEXT: vmov.u8 r0, q0[3] +; CHECK-NEXT: vmov.16 q3[3], r0 +; CHECK-NEXT: vmov.u8 r0, q0[4] +; CHECK-NEXT: vmov.16 q3[4], r0 +; CHECK-NEXT: vmov.u8 r0, q0[5] +; CHECK-NEXT: vmov.16 q3[5], r0 +; CHECK-NEXT: vmov.u8 r0, q0[6] +; CHECK-NEXT: vmov.16 q3[6], r0 +; CHECK-NEXT: vmov.u8 r0, q0[7] +; CHECK-NEXT: vmov.16 q3[7], r0 +; CHECK-NEXT: vmovlb.u8 q2, q2 +; CHECK-NEXT: vmovlb.u8 q3, q3 +; CHECK-NEXT: vsub.i16 q2, q3, q2 +; CHECK-NEXT: vabs.s16 q3, q2 +; CHECK-NEXT: vmov.u16 r0, q3[0] +; CHECK-NEXT: vmov.8 q2[0], r0 +; CHECK-NEXT: vmov.u16 r0, q3[1] +; CHECK-NEXT: vmov.8 q2[1], r0 +; CHECK-NEXT: vmov.u16 r0, q3[2] +; CHECK-NEXT: vmov.8 q2[2], r0 +; CHECK-NEXT: vmov.u16 r0, q3[3] +; CHECK-NEXT: vmov.8 q2[3], r0 +; CHECK-NEXT: vmov.u16 r0, q3[4] +; CHECK-NEXT: vmov.8 q2[4], r0 +; CHECK-NEXT: vmov.u16 r0, q3[5] +; CHECK-NEXT: vmov.8 q2[5], r0 +; CHECK-NEXT: vmov.u16 r0, q3[6] +; CHECK-NEXT: vmov.8 q2[6], r0 +; CHECK-NEXT: vmov.u16 r0, q3[7] +; CHECK-NEXT: vmov.8 q2[7], r0 +; CHECK-NEXT: vmov.u8 r0, q1[8] +; CHECK-NEXT: vmov.16 q3[0], r0 +; CHECK-NEXT: vmov.u8 r0, q1[9] +; CHECK-NEXT: vmov.16 q3[1], r0 +; CHECK-NEXT: vmov.u8 r0, q1[10] +; CHECK-NEXT: vmov.16 q3[2], r0 +; CHECK-NEXT: vmov.u8 r0, q1[11] +; CHECK-NEXT: vmov.16 q3[3], r0 +; CHECK-NEXT: vmov.u8 r0, q1[12] +; CHECK-NEXT: vmov.16 q3[4], r0 +; CHECK-NEXT: vmov.u8 r0, q1[13] +; CHECK-NEXT: vmov.16 q3[5], r0 +; CHECK-NEXT: vmov.u8 r0, q1[14] +; CHECK-NEXT: vmov.16 q3[6], r0 +; CHECK-NEXT: vmov.u8 r0, q1[15] +; CHECK-NEXT: vmov.16 q3[7], r0 +; CHECK-NEXT: vmov.u8 r0, q0[8] +; CHECK-NEXT: vmovlb.u8 q1, q3 +; CHECK-NEXT: vmov.16 q3[0], r0 +; CHECK-NEXT: vmov.u8 r0, q0[9] +; CHECK-NEXT: vmov.16 q3[1], r0 +; CHECK-NEXT: vmov.u8 r0, q0[10] +; CHECK-NEXT: vmov.16 q3[2], r0 +; CHECK-NEXT: vmov.u8 r0, q0[11] +; CHECK-NEXT: vmov.16 q3[3], r0 +; CHECK-NEXT: vmov.u8 r0, q0[12] +; CHECK-NEXT: vmov.16 q3[4], r0 +; CHECK-NEXT: vmov.u8 r0, q0[13] +; CHECK-NEXT: vmov.16 q3[5], r0 +; CHECK-NEXT: vmov.u8 r0, q0[14] +; CHECK-NEXT: vmov.16 q3[6], r0 +; CHECK-NEXT: vmov.u8 r0, q0[15] +; CHECK-NEXT: vmov.16 q3[7], r0 +; CHECK-NEXT: vmovlb.u8 q0, q3 +; CHECK-NEXT: vsub.i16 q0, q0, q1 +; CHECK-NEXT: vabs.s16 q0, q0 +; CHECK-NEXT: vmov.u16 r0, q0[0] +; CHECK-NEXT: vmov.8 q2[8], r0 +; CHECK-NEXT: vmov.u16 r0, q0[1] +; CHECK-NEXT: vmov.8 q2[9], r0 +; CHECK-NEXT: vmov.u16 r0, q0[2] +; CHECK-NEXT: vmov.8 q2[10], r0 +; CHECK-NEXT: vmov.u16 r0, q0[3] +; CHECK-NEXT: vmov.8 q2[11], r0 +; CHECK-NEXT: vmov.u16 r0, q0[4] +; CHECK-NEXT: vmov.8 q2[12], r0 +; CHECK-NEXT: vmov.u16 r0, q0[5] +; CHECK-NEXT: vmov.8 q2[13], r0 +; CHECK-NEXT: vmov.u16 r0, q0[6] +; CHECK-NEXT: vmov.8 q2[14], r0 +; CHECK-NEXT: vmov.u16 r0, q0[7] +; CHECK-NEXT: vmov.8 q2[15], r0 +; CHECK-NEXT: vmov q0, q2 +; CHECK-NEXT: bx lr + %zextsrc1 = zext <16 x i8> %src1 to <16 x i16> + %zextsrc2 = zext <16 x i8> %src2 to <16 x i16> + %add1 = sub <16 x i16> %zextsrc1, %zextsrc2 + %add2 = sub <16 x i16> zeroinitializer, %add1 + %c = icmp sge <16 x i16> %add1, zeroinitializer + %s = select <16 x i1> %c, <16 x i16> %add1, <16 x i16> %add2 + %result = trunc <16 x i16> %s to <16 x i8> + ret <16 x i8> %result +} + +define arm_aapcs_vfpcc <8 x i16> @vabd_u16(<8 x i16> %src1, <8 x i16> %src2) { +; CHECK-LABEL: vabd_u16: +; CHECK: @ %bb.0: +; CHECK-NEXT: vmov.u16 r0, q1[0] +; CHECK-NEXT: vmov.32 q2[0], r0 +; CHECK-NEXT: vmov.u16 r0, q1[1] +; CHECK-NEXT: vmov.32 q2[1], r0 +; CHECK-NEXT: vmov.u16 r0, q1[2] +; CHECK-NEXT: vmov.32 q2[2], r0 +; CHECK-NEXT: vmov.u16 r0, q1[3] +; CHECK-NEXT: vmov.32 q2[3], r0 +; CHECK-NEXT: vmov.u16 r0, q0[0] +; CHECK-NEXT: vmov.32 q3[0], r0 +; CHECK-NEXT: vmov.u16 r0, q0[1] +; CHECK-NEXT: vmov.32 q3[1], r0 +; CHECK-NEXT: vmov.u16 r0, q0[2] +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.u16 r0, q0[3] +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: vmovlb.u16 q2, q2 +; CHECK-NEXT: vmovlb.u16 q3, q3 +; CHECK-NEXT: vsub.i32 q2, q3, q2 +; CHECK-NEXT: vabs.s32 q3, q2 +; CHECK-NEXT: vmov r0, s12 +; CHECK-NEXT: vmov.16 q2[0], r0 +; CHECK-NEXT: vmov r0, s13 +; CHECK-NEXT: vmov.16 q2[1], r0 +; CHECK-NEXT: vmov r0, s14 +; CHECK-NEXT: vmov.16 q2[2], r0 +; CHECK-NEXT: vmov r0, s15 +; CHECK-NEXT: vmov.16 q2[3], r0 +; CHECK-NEXT: vmov.u16 r0, q1[4] +; CHECK-NEXT: vmov.32 q3[0], r0 +; CHECK-NEXT: vmov.u16 r0, q1[5] +; CHECK-NEXT: vmov.32 q3[1], r0 +; CHECK-NEXT: vmov.u16 r0, q1[6] +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.u16 r0, q1[7] +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: vmov.u16 r0, q0[4] +; CHECK-NEXT: vmovlb.u16 q1, q3 +; CHECK-NEXT: vmov.32 q3[0], r0 +; CHECK-NEXT: vmov.u16 r0, q0[5] +; CHECK-NEXT: vmov.32 q3[1], r0 +; CHECK-NEXT: vmov.u16 r0, q0[6] +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.u16 r0, q0[7] +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: vmovlb.u16 q0, q3 +; CHECK-NEXT: vsub.i32 q0, q0, q1 +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vmov r0, s0 +; CHECK-NEXT: vmov.16 q2[4], r0 +; CHECK-NEXT: vmov r0, s1 +; CHECK-NEXT: vmov.16 q2[5], r0 +; CHECK-NEXT: vmov r0, s2 +; CHECK-NEXT: vmov.16 q2[6], r0 +; CHECK-NEXT: vmov r0, s3 +; CHECK-NEXT: vmov.16 q2[7], r0 +; CHECK-NEXT: vmov q0, q2 +; CHECK-NEXT: bx lr + %zextsrc1 = zext <8 x i16> %src1 to <8 x i32> + %zextsrc2 = zext <8 x i16> %src2 to <8 x i32> + %add1 = sub <8 x i32> %zextsrc1, %zextsrc2 + %add2 = sub <8 x i32> zeroinitializer, %add1 + %c = icmp sge <8 x i32> %add1, zeroinitializer + %s = select <8 x i1> %c, <8 x i32> %add1, <8 x i32> %add2 + %result = trunc <8 x i32> %s to <8 x i16> + ret <8 x i16> %result +} + +define arm_aapcs_vfpcc <4 x i32> @vabd_u32(<4 x i32> %src1, <4 x i32> %src2) { +; CHECK-LABEL: vabd_u32: +; CHECK: @ %bb.0: +; CHECK-NEXT: .vsave {d8, d9} +; CHECK-NEXT: vpush {d8, d9} +; CHECK-NEXT: vmov.f32 s8, s4 +; CHECK-NEXT: vmov.i64 q3, #0xffffffff +; CHECK-NEXT: vmov.f32 s16, s0 +; CHECK-NEXT: vmov.f32 s10, s5 +; CHECK-NEXT: vmov.f32 s18, s1 +; CHECK-NEXT: vand q2, q2, q3 +; CHECK-NEXT: vand q4, q4, q3 +; CHECK-NEXT: vmov r2, s10 +; CHECK-NEXT: vmov r3, s18 +; CHECK-NEXT: vmov r0, s11 +; CHECK-NEXT: vmov r1, s19 +; CHECK-NEXT: subs r2, r3, r2 +; CHECK-NEXT: vmov r3, s8 +; CHECK-NEXT: sbc.w r0, r1, r0 +; CHECK-NEXT: add.w r1, r2, r0, asr #31 +; CHECK-NEXT: vmov r2, s17 +; CHECK-NEXT: eor.w r12, r1, r0, asr #31 +; CHECK-NEXT: vmov r0, s16 +; CHECK-NEXT: vmov r1, s9 +; CHECK-NEXT: vmov.f32 s16, s6 +; CHECK-NEXT: vmov.f32 s18, s7 +; CHECK-NEXT: vand q1, q4, q3 +; CHECK-NEXT: vmov.f32 s16, s2 +; CHECK-NEXT: vmov.f32 s18, s3 +; CHECK-NEXT: vand q0, q4, q3 +; CHECK-NEXT: subs r0, r0, r3 +; CHECK-NEXT: vmov r3, s0 +; CHECK-NEXT: sbc.w r1, r2, r1 +; CHECK-NEXT: vmov r2, s4 +; CHECK-NEXT: add.w r0, r0, r1, asr #31 +; CHECK-NEXT: eor.w r0, r0, r1, asr #31 +; CHECK-NEXT: vmov r1, s1 +; CHECK-NEXT: vmov.32 q2[0], r0 +; CHECK-NEXT: vmov r0, s5 +; CHECK-NEXT: vmov.32 q2[1], r12 +; CHECK-NEXT: subs r2, r3, r2 +; CHECK-NEXT: vmov r3, s2 +; CHECK-NEXT: sbc.w r0, r1, r0 +; CHECK-NEXT: add.w r1, r2, r0, asr #31 +; CHECK-NEXT: vmov r2, s6 +; CHECK-NEXT: eor.w r0, r1, r0, asr #31 +; CHECK-NEXT: vmov r1, s3 +; CHECK-NEXT: vmov.32 q2[2], r0 +; CHECK-NEXT: vmov r0, s7 +; CHECK-NEXT: subs r2, r3, r2 +; CHECK-NEXT: sbc.w r0, r1, r0 +; CHECK-NEXT: add.w r1, r2, r0, asr #31 +; CHECK-NEXT: eor.w r0, r1, r0, asr #31 +; CHECK-NEXT: vmov.32 q2[3], r0 +; CHECK-NEXT: vmov q0, q2 +; CHECK-NEXT: vpop {d8, d9} +; CHECK-NEXT: bx lr + %zextsrc1 = zext <4 x i32> %src1 to <4 x i64> + %zextsrc2 = zext <4 x i32> %src2 to <4 x i64> + %add1 = sub <4 x i64> %zextsrc1, %zextsrc2 + %add2 = sub <4 x i64> zeroinitializer, %add1 + %c = icmp sge <4 x i64> %add1, zeroinitializer + %s = select <4 x i1> %c, <4 x i64> %add1, <4 x i64> %add2 + %result = trunc <4 x i64> %s to <4 x i32> + ret <4 x i32> %result +} + +define void @vabd_loop_s8(i8* nocapture readonly %x, i8* nocapture readonly %y, i8* noalias nocapture %z, i32 %n) { +; CHECK-LABEL: vabd_loop_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: mov.w lr, #64 +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: .LBB6_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrb.s32 q0, [r1, #12] +; CHECK-NEXT: vldrb.s32 q1, [r0, #12] +; CHECK-NEXT: vsub.i32 q0, q1, q0 +; CHECK-NEXT: vldrb.s32 q1, [r0, #8] +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vstrb.32 q0, [r2, #12] +; CHECK-NEXT: vldrb.s32 q0, [r1, #8] +; CHECK-NEXT: vsub.i32 q0, q1, q0 +; CHECK-NEXT: vldrb.s32 q1, [r0, #4] +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vstrb.32 q0, [r2, #8] +; CHECK-NEXT: vldrb.s32 q0, [r1, #4] +; CHECK-NEXT: vsub.i32 q0, q1, q0 +; CHECK-NEXT: vldrb.s32 q1, [r0], #16 +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vstrb.32 q0, [r2, #4] +; CHECK-NEXT: vldrb.s32 q0, [r1], #16 +; CHECK-NEXT: vsub.i32 q0, q1, q0 +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vstrb.32 q0, [r2], #16 +; CHECK-NEXT: le lr, .LBB6_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i8, i8* %x, i32 %index + %1 = bitcast i8* %0 to <16 x i8>* + %wide.load = load <16 x i8>, <16 x i8>* %1, align 1 + %2 = sext <16 x i8> %wide.load to <16 x i32> + %3 = getelementptr inbounds i8, i8* %y, i32 %index + %4 = bitcast i8* %3 to <16 x i8>* + %wide.load22 = load <16 x i8>, <16 x i8>* %4, align 1 + %5 = sext <16 x i8> %wide.load22 to <16 x i32> + %6 = sub nsw <16 x i32> %2, %5 + %7 = icmp slt <16 x i32> %6, zeroinitializer + %8 = sub nsw <16 x i32> zeroinitializer, %6 + %9 = select <16 x i1> %7, <16 x i32> %8, <16 x i32> %6 + %10 = trunc <16 x i32> %9 to <16 x i8> + %11 = getelementptr inbounds i8, i8* %z, i32 %index + %12 = bitcast i8* %11 to <16 x i8>* + store <16 x i8> %10, <16 x i8>* %12, align 1 + %index.next = add i32 %index, 16 + %13 = icmp eq i32 %index.next, 1024 + br i1 %13, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body + ret void +} + +define void @vabd_loop_s16(i16* nocapture readonly %x, i16* nocapture readonly %y, i16* noalias nocapture %z, i32 %n) { +; CHECK-LABEL: vabd_loop_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: mov.w lr, #128 +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: .LBB7_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrh.s32 q0, [r1, #8] +; CHECK-NEXT: vldrh.s32 q1, [r0, #8] +; CHECK-NEXT: vsub.i32 q0, q1, q0 +; CHECK-NEXT: vldrh.s32 q1, [r0], #16 +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vstrh.32 q0, [r2, #8] +; CHECK-NEXT: vldrh.s32 q0, [r1], #16 +; CHECK-NEXT: vsub.i32 q0, q1, q0 +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vstrh.32 q0, [r2], #16 +; CHECK-NEXT: le lr, .LBB7_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i16, i16* %x, i32 %index + %1 = bitcast i16* %0 to <8 x i16>* + %wide.load = load <8 x i16>, <8 x i16>* %1, align 2 + %2 = sext <8 x i16> %wide.load to <8 x i32> + %3 = getelementptr inbounds i16, i16* %y, i32 %index + %4 = bitcast i16* %3 to <8 x i16>* + %wide.load22 = load <8 x i16>, <8 x i16>* %4, align 2 + %5 = sext <8 x i16> %wide.load22 to <8 x i32> + %6 = sub nsw <8 x i32> %2, %5 + %7 = icmp slt <8 x i32> %6, zeroinitializer + %8 = sub nsw <8 x i32> zeroinitializer, %6 + %9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6 + %10 = trunc <8 x i32> %9 to <8 x i16> + %11 = getelementptr inbounds i16, i16* %z, i32 %index + %12 = bitcast i16* %11 to <8 x i16>* + store <8 x i16> %10, <8 x i16>* %12, align 2 + %index.next = add i32 %index, 8 + %13 = icmp eq i32 %index.next, 1024 + br i1 %13, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body + ret void +} + +define void @vabd_loop_s32(i32* nocapture readonly %x, i32* nocapture readonly %y, i32* noalias nocapture %z, i32 %n) { +; CHECK-LABEL: vabd_loop_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr} +; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr} +; CHECK-NEXT: .pad #4 +; CHECK-NEXT: sub sp, #4 +; CHECK-NEXT: .vsave {d8, d9} +; CHECK-NEXT: vpush {d8, d9} +; CHECK-NEXT: mov.w lr, #256 +; CHECK-NEXT: mov.w r12, #1 +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: vmov.i32 q0, #0x0 +; CHECK-NEXT: .LBB8_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrw.u32 q1, [r0], #16 +; CHECK-NEXT: vldrw.u32 q2, [r1], #16 +; CHECK-NEXT: vmov.f32 s12, s4 +; CHECK-NEXT: vmov.f32 s16, s8 +; CHECK-NEXT: vmov.f32 s14, s5 +; CHECK-NEXT: vmov r3, s12 +; CHECK-NEXT: vmov.f32 s18, s9 +; CHECK-NEXT: vmov r5, s16 +; CHECK-NEXT: vmov r7, s18 +; CHECK-NEXT: asrs r4, r3, #31 +; CHECK-NEXT: subs.w r8, r3, r5 +; CHECK-NEXT: sbc.w r4, r4, r5, asr #31 +; CHECK-NEXT: asrs r5, r4, #31 +; CHECK-NEXT: movs r4, #0 +; CHECK-NEXT: bfi r4, r5, #0, #4 +; CHECK-NEXT: vmov r5, s14 +; CHECK-NEXT: vmov.f32 s12, s6 +; CHECK-NEXT: vmov.f32 s14, s7 +; CHECK-NEXT: vmov.f32 s4, s10 +; CHECK-NEXT: vmov.f32 s6, s11 +; CHECK-NEXT: vmov r3, s4 +; CHECK-NEXT: subs.w r9, r5, r7 +; CHECK-NEXT: asr.w r6, r5, #31 +; CHECK-NEXT: vmov r5, s6 +; CHECK-NEXT: sbc.w r6, r6, r7, asr #31 +; CHECK-NEXT: vmov.32 q1[0], r8 +; CHECK-NEXT: vmov.32 q1[1], r9 +; CHECK-NEXT: and.w r6, r12, r6, asr #31 +; CHECK-NEXT: rsbs r6, r6, #0 +; CHECK-NEXT: bfi r4, r6, #4, #4 +; CHECK-NEXT: vmov r6, s12 +; CHECK-NEXT: asrs r7, r6, #31 +; CHECK-NEXT: subs r6, r6, r3 +; CHECK-NEXT: sbc.w r3, r7, r3, asr #31 +; CHECK-NEXT: vmov.32 q1[2], r6 +; CHECK-NEXT: asrs r3, r3, #31 +; CHECK-NEXT: vmov.32 q2[0], r3 +; CHECK-NEXT: vmov r3, s14 +; CHECK-NEXT: asrs r7, r3, #31 +; CHECK-NEXT: subs r3, r3, r5 +; CHECK-NEXT: sbc.w r5, r7, r5, asr #31 +; CHECK-NEXT: vmov.32 q1[3], r3 +; CHECK-NEXT: asrs r7, r5, #31 +; CHECK-NEXT: and.w r5, r12, r5, asr #31 +; CHECK-NEXT: vmov.32 q2[2], r7 +; CHECK-NEXT: rsbs r5, r5, #0 +; CHECK-NEXT: vmov r7, s8 +; CHECK-NEXT: and r7, r7, #1 +; CHECK-NEXT: rsbs r7, r7, #0 +; CHECK-NEXT: bfi r4, r7, #8, #4 +; CHECK-NEXT: bfi r4, r5, #12, #4 +; CHECK-NEXT: vmsr p0, r4 +; CHECK-NEXT: vpst +; CHECK-NEXT: vsubt.i32 q1, q0, q1 +; CHECK-NEXT: vstrb.8 q1, [r2], #16 +; CHECK-NEXT: le lr, .LBB8_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: vpop {d8, d9} +; CHECK-NEXT: add sp, #4 +; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc} +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i32, i32* %x, i32 %index + %1 = bitcast i32* %0 to <4 x i32>* + %wide.load = load <4 x i32>, <4 x i32>* %1, align 4 + %2 = sext <4 x i32> %wide.load to <4 x i64> + %3 = getelementptr inbounds i32, i32* %y, i32 %index + %4 = bitcast i32* %3 to <4 x i32>* + %wide.load23 = load <4 x i32>, <4 x i32>* %4, align 4 + %5 = sext <4 x i32> %wide.load23 to <4 x i64> + %6 = sub nsw <4 x i64> %2, %5 + %7 = icmp slt <4 x i64> %6, zeroinitializer + %8 = trunc <4 x i64> %6 to <4 x i32> + %9 = sub <4 x i32> zeroinitializer, %8 + %10 = select <4 x i1> %7, <4 x i32> %9, <4 x i32> %8 + %11 = getelementptr inbounds i32, i32* %z, i32 %index + %12 = bitcast i32* %11 to <4 x i32>* + store <4 x i32> %10, <4 x i32>* %12, align 4 + %index.next = add i32 %index, 4 + %13 = icmp eq i32 %index.next, 1024 + br i1 %13, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body + ret void +} + +define void @vabd_loop_u8(i8* nocapture readonly %x, i8* nocapture readonly %y, i8* noalias nocapture %z, i32 %n) { +; CHECK-LABEL: vabd_loop_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: mov.w lr, #64 +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: .LBB9_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrb.u32 q0, [r1, #12] +; CHECK-NEXT: vldrb.u32 q1, [r0, #12] +; CHECK-NEXT: vsub.i32 q0, q1, q0 +; CHECK-NEXT: vldrb.u32 q1, [r0, #8] +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vstrb.32 q0, [r2, #12] +; CHECK-NEXT: vldrb.u32 q0, [r1, #8] +; CHECK-NEXT: vsub.i32 q0, q1, q0 +; CHECK-NEXT: vldrb.u32 q1, [r0, #4] +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vstrb.32 q0, [r2, #8] +; CHECK-NEXT: vldrb.u32 q0, [r1, #4] +; CHECK-NEXT: vsub.i32 q0, q1, q0 +; CHECK-NEXT: vldrb.u32 q1, [r0], #16 +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vstrb.32 q0, [r2, #4] +; CHECK-NEXT: vldrb.u32 q0, [r1], #16 +; CHECK-NEXT: vsub.i32 q0, q1, q0 +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vstrb.32 q0, [r2], #16 +; CHECK-NEXT: le lr, .LBB9_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i8, i8* %x, i32 %index + %1 = bitcast i8* %0 to <16 x i8>* + %wide.load = load <16 x i8>, <16 x i8>* %1, align 1 + %2 = zext <16 x i8> %wide.load to <16 x i32> + %3 = getelementptr inbounds i8, i8* %y, i32 %index + %4 = bitcast i8* %3 to <16 x i8>* + %wide.load22 = load <16 x i8>, <16 x i8>* %4, align 1 + %5 = zext <16 x i8> %wide.load22 to <16 x i32> + %6 = sub nsw <16 x i32> %2, %5 + %7 = icmp slt <16 x i32> %6, zeroinitializer + %8 = sub nsw <16 x i32> zeroinitializer, %6 + %9 = select <16 x i1> %7, <16 x i32> %8, <16 x i32> %6 + %10 = trunc <16 x i32> %9 to <16 x i8> + %11 = getelementptr inbounds i8, i8* %z, i32 %index + %12 = bitcast i8* %11 to <16 x i8>* + store <16 x i8> %10, <16 x i8>* %12, align 1 + %index.next = add i32 %index, 16 + %13 = icmp eq i32 %index.next, 1024 + br i1 %13, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body + ret void +} + +define void @vabd_loop_u16(i16* nocapture readonly %x, i16* nocapture readonly %y, i16* noalias nocapture %z, i32 %n) { +; CHECK-LABEL: vabd_loop_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: mov.w lr, #128 +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: .LBB10_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrh.u32 q0, [r1, #8] +; CHECK-NEXT: vldrh.u32 q1, [r0, #8] +; CHECK-NEXT: vsub.i32 q0, q1, q0 +; CHECK-NEXT: vldrh.u32 q1, [r0], #16 +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vstrh.32 q0, [r2, #8] +; CHECK-NEXT: vldrh.u32 q0, [r1], #16 +; CHECK-NEXT: vsub.i32 q0, q1, q0 +; CHECK-NEXT: vabs.s32 q0, q0 +; CHECK-NEXT: vstrh.32 q0, [r2], #16 +; CHECK-NEXT: le lr, .LBB10_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: pop {r7, pc} +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i16, i16* %x, i32 %index + %1 = bitcast i16* %0 to <8 x i16>* + %wide.load = load <8 x i16>, <8 x i16>* %1, align 2 + %2 = zext <8 x i16> %wide.load to <8 x i32> + %3 = getelementptr inbounds i16, i16* %y, i32 %index + %4 = bitcast i16* %3 to <8 x i16>* + %wide.load22 = load <8 x i16>, <8 x i16>* %4, align 2 + %5 = zext <8 x i16> %wide.load22 to <8 x i32> + %6 = sub nsw <8 x i32> %2, %5 + %7 = icmp slt <8 x i32> %6, zeroinitializer + %8 = sub nsw <8 x i32> zeroinitializer, %6 + %9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6 + %10 = trunc <8 x i32> %9 to <8 x i16> + %11 = getelementptr inbounds i16, i16* %z, i32 %index + %12 = bitcast i16* %11 to <8 x i16>* + store <8 x i16> %10, <8 x i16>* %12, align 2 + %index.next = add i32 %index, 8 + %13 = icmp eq i32 %index.next, 1024 + br i1 %13, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body + ret void +} + +define void @vabd_loop_u32(i32* nocapture readonly %x, i32* nocapture readonly %y, i32* noalias nocapture %z, i32 %n) { +; CHECK-LABEL: vabd_loop_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} +; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr} +; CHECK-NEXT: .vsave {d8, d9, d10, d11} +; CHECK-NEXT: vpush {d8, d9, d10, d11} +; CHECK-NEXT: mov.w lr, #256 +; CHECK-NEXT: vmov.i64 q0, #0xffffffff +; CHECK-NEXT: dls lr, lr +; CHECK-NEXT: mov.w r12, #1 +; CHECK-NEXT: vmov.i32 q1, #0x0 +; CHECK-NEXT: .LBB11_1: @ %vector.body +; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vldrw.u32 q2, [r1], #16 +; CHECK-NEXT: vmov.f32 s12, s8 +; CHECK-NEXT: vmov.f32 s14, s9 +; CHECK-NEXT: vand q4, q3, q0 +; CHECK-NEXT: vldrw.u32 q3, [r0], #16 +; CHECK-NEXT: vmov r3, s16 +; CHECK-NEXT: vmov.f32 s20, s12 +; CHECK-NEXT: vmov.f32 s22, s13 +; CHECK-NEXT: vand q5, q5, q0 +; CHECK-NEXT: vmov r4, s17 +; CHECK-NEXT: vmov r6, s20 +; CHECK-NEXT: vmov r5, s21 +; CHECK-NEXT: vmov r7, s23 +; CHECK-NEXT: subs.w r8, r6, r3 +; CHECK-NEXT: vmov r3, s22 +; CHECK-NEXT: sbc.w r4, r5, r4 +; CHECK-NEXT: vmov r6, s19 +; CHECK-NEXT: asrs r5, r4, #31 +; CHECK-NEXT: movs r4, #0 +; CHECK-NEXT: bfi r4, r5, #0, #4 +; CHECK-NEXT: vmov r5, s18 +; CHECK-NEXT: vmov.f32 s16, s10 +; CHECK-NEXT: vmov.f32 s18, s11 +; CHECK-NEXT: vand q2, q4, q0 +; CHECK-NEXT: vmov.f32 s16, s14 +; CHECK-NEXT: vmov.f32 s18, s15 +; CHECK-NEXT: vand q3, q4, q0 +; CHECK-NEXT: subs.w r9, r3, r5 +; CHECK-NEXT: vmov r5, s12 +; CHECK-NEXT: sbc.w r3, r7, r6 +; CHECK-NEXT: vmov r7, s8 +; CHECK-NEXT: vmov r6, s13 +; CHECK-NEXT: and.w r3, r12, r3, asr #31 +; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: bfi r4, r3, #4, #4 +; CHECK-NEXT: vmov r3, s9 +; CHECK-NEXT: subs.w r10, r5, r7 +; CHECK-NEXT: vmov r7, s10 +; CHECK-NEXT: vmov r5, s14 +; CHECK-NEXT: sbc.w r3, r6, r3 +; CHECK-NEXT: vmov r6, s15 +; CHECK-NEXT: asrs r3, r3, #31 +; CHECK-NEXT: vmov.32 q4[0], r3 +; CHECK-NEXT: vmov r3, s11 +; CHECK-NEXT: vmov.32 q2[0], r8 +; CHECK-NEXT: vmov.32 q2[1], r9 +; CHECK-NEXT: vmov.32 q2[2], r10 +; CHECK-NEXT: subs r5, r5, r7 +; CHECK-NEXT: vmov.32 q2[3], r5 +; CHECK-NEXT: sbc.w r3, r6, r3 +; CHECK-NEXT: asrs r6, r3, #31 +; CHECK-NEXT: and.w r3, r12, r3, asr #31 +; CHECK-NEXT: vmov.32 q4[2], r6 +; CHECK-NEXT: rsbs r3, r3, #0 +; CHECK-NEXT: vmov r6, s16 +; CHECK-NEXT: and r6, r6, #1 +; CHECK-NEXT: rsbs r6, r6, #0 +; CHECK-NEXT: bfi r4, r6, #8, #4 +; CHECK-NEXT: bfi r4, r3, #12, #4 +; CHECK-NEXT: vmsr p0, r4 +; CHECK-NEXT: vpst +; CHECK-NEXT: vsubt.i32 q2, q1, q2 +; CHECK-NEXT: vstrb.8 q2, [r2], #16 +; CHECK-NEXT: le lr, .LBB11_1 +; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup +; CHECK-NEXT: vpop {d8, d9, d10, d11} +; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc} +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ] + %0 = getelementptr inbounds i32, i32* %x, i32 %index + %1 = bitcast i32* %0 to <4 x i32>* + %wide.load = load <4 x i32>, <4 x i32>* %1, align 4 + %2 = zext <4 x i32> %wide.load to <4 x i64> + %3 = getelementptr inbounds i32, i32* %y, i32 %index + %4 = bitcast i32* %3 to <4 x i32>* + %wide.load23 = load <4 x i32>, <4 x i32>* %4, align 4 + %5 = zext <4 x i32> %wide.load23 to <4 x i64> + %6 = sub nsw <4 x i64> %2, %5 + %7 = icmp slt <4 x i64> %6, zeroinitializer + %8 = trunc <4 x i64> %6 to <4 x i32> + %9 = sub <4 x i32> zeroinitializer, %8 + %10 = select <4 x i1> %7, <4 x i32> %9, <4 x i32> %8 + %11 = getelementptr inbounds i32, i32* %z, i32 %index + %12 = bitcast i32* %11 to <4 x i32>* + store <4 x i32> %10, <4 x i32>* %12, align 4 + %index.next = add i32 %index, 4 + %13 = icmp eq i32 %index.next, 1024 + br i1 %13, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body + ret void +} diff --git a/llvm/test/CodeGen/VE/Scalar/callstruct.ll b/llvm/test/CodeGen/VE/Scalar/callstruct.ll index 7241d752a4843..4b5b788adfd4f 100644 --- a/llvm/test/CodeGen/VE/Scalar/callstruct.ll +++ b/llvm/test/CodeGen/VE/Scalar/callstruct.ll @@ -5,7 +5,7 @@ @A = common global %struct.a zeroinitializer, align 4 ; Function Attrs: norecurse nounwind -define void @fun(%struct.a* noalias nocapture sret %a, i32 %p1, i32 %p2) { +define void @fun(%struct.a* noalias nocapture sret(%struct.a) %a, i32 %p1, i32 %p2) { ; CHECK-LABEL: fun: ; CHECK: # %bb.0: ; CHECK-NEXT: stl %s1, (, %s0) @@ -37,10 +37,10 @@ define void @caller() { ; CHECK-NEXT: or %s11, 0, %s9 %a = alloca i64, align 8 %a.bc = bitcast i64* %a to %struct.a* - call void @callee(%struct.a* nonnull sret %a.bc, i32 3, i32 4) + call void @callee(%struct.a* nonnull sret(%struct.a) %a.bc, i32 3, i32 4) %a.val = load i64, i64* %a, align 8 store i64 %a.val, i64* bitcast (%struct.a* @A to i64*), align 4 ret void } -declare void @callee(%struct.a* sret, i32, i32) +declare void @callee(%struct.a* sret(%struct.a), i32, i32) diff --git a/llvm/test/CodeGen/VE/Scalar/stackframe_align.ll b/llvm/test/CodeGen/VE/Scalar/stackframe_align.ll new file mode 100644 index 0000000000000..f180ae531a9dd --- /dev/null +++ b/llvm/test/CodeGen/VE/Scalar/stackframe_align.ll @@ -0,0 +1,582 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=ve | FileCheck %s +; RUN: llc < %s -mtriple=ve --frame-pointer=all \ +; RUN: | FileCheck %s --check-prefix=CHECKFP + +;;; Check stack frame allocation with static and dynamic stack object with +;;; alignments as a test of getFrameIndexReference(). + +;; Allocated buffer places from 9 to 15 bytes in 16 bytes local vars area. + +; Function Attrs: nounwind +define i8* @test_frame7(i8* %0) { +; CHECK-LABEL: test_frame7: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -192 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB0_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB0_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 185(, %s11) +; CHECK-NEXT: st1b %s1, 185(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; CHECKFP-LABEL: test_frame7: +; CHECKFP: # %bb.0: +; CHECKFP-NEXT: st %s9, (, %s11) +; CHECKFP-NEXT: st %s10, 8(, %s11) +; CHECKFP-NEXT: st %s15, 24(, %s11) +; CHECKFP-NEXT: st %s16, 32(, %s11) +; CHECKFP-NEXT: or %s9, 0, %s11 +; CHECKFP-NEXT: lea %s13, -192 +; CHECKFP-NEXT: and %s13, %s13, (32)0 +; CHECKFP-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECKFP-NEXT: brge.l.t %s11, %s8, .LBB0_2 +; CHECKFP-NEXT: # %bb.1: +; CHECKFP-NEXT: ld %s61, 24(, %s14) +; CHECKFP-NEXT: or %s62, 0, %s0 +; CHECKFP-NEXT: lea %s63, 315 +; CHECKFP-NEXT: shm.l %s63, (%s61) +; CHECKFP-NEXT: shm.l %s8, 8(%s61) +; CHECKFP-NEXT: shm.l %s11, 16(%s61) +; CHECKFP-NEXT: monc +; CHECKFP-NEXT: or %s0, 0, %s62 +; CHECKFP-NEXT: .LBB0_2: +; CHECKFP-NEXT: ld1b.zx %s1, (, %s0) +; CHECKFP-NEXT: lea %s0, -7(, %s9) +; CHECKFP-NEXT: st1b %s1, -7(, %s9) +; CHECKFP-NEXT: or %s11, 0, %s9 +; CHECKFP-NEXT: ld %s16, 32(, %s11) +; CHECKFP-NEXT: ld %s15, 24(, %s11) +; CHECKFP-NEXT: ld %s10, 8(, %s11) +; CHECKFP-NEXT: ld %s9, (, %s11) +; CHECKFP-NEXT: b.l.t (, %s10) + %2 = alloca [7 x i8], align 1 + %3 = getelementptr inbounds [7 x i8], [7 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} + +;; Allocated buffer is aligned by 8, so it places from 8 to 14 bytes in 16 +;; bytes local vars area. + +; Function Attrs: nounwind +define i8* @test_frame7_align8(i8* %0) { +; CHECK-LABEL: test_frame7_align8: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -192 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB1_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 184(, %s11) +; CHECK-NEXT: st1b %s1, 184(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; CHECKFP-LABEL: test_frame7_align8: +; CHECKFP: # %bb.0: +; CHECKFP-NEXT: st %s9, (, %s11) +; CHECKFP-NEXT: st %s10, 8(, %s11) +; CHECKFP-NEXT: st %s15, 24(, %s11) +; CHECKFP-NEXT: st %s16, 32(, %s11) +; CHECKFP-NEXT: or %s9, 0, %s11 +; CHECKFP-NEXT: lea %s13, -192 +; CHECKFP-NEXT: and %s13, %s13, (32)0 +; CHECKFP-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECKFP-NEXT: brge.l.t %s11, %s8, .LBB1_2 +; CHECKFP-NEXT: # %bb.1: +; CHECKFP-NEXT: ld %s61, 24(, %s14) +; CHECKFP-NEXT: or %s62, 0, %s0 +; CHECKFP-NEXT: lea %s63, 315 +; CHECKFP-NEXT: shm.l %s63, (%s61) +; CHECKFP-NEXT: shm.l %s8, 8(%s61) +; CHECKFP-NEXT: shm.l %s11, 16(%s61) +; CHECKFP-NEXT: monc +; CHECKFP-NEXT: or %s0, 0, %s62 +; CHECKFP-NEXT: .LBB1_2: +; CHECKFP-NEXT: ld1b.zx %s1, (, %s0) +; CHECKFP-NEXT: lea %s0, -8(, %s9) +; CHECKFP-NEXT: st1b %s1, -8(, %s9) +; CHECKFP-NEXT: or %s11, 0, %s9 +; CHECKFP-NEXT: ld %s16, 32(, %s11) +; CHECKFP-NEXT: ld %s15, 24(, %s11) +; CHECKFP-NEXT: ld %s10, 8(, %s11) +; CHECKFP-NEXT: ld %s9, (, %s11) +; CHECKFP-NEXT: b.l.t (, %s10) + %2 = alloca [7 x i8], align 8 + %3 = getelementptr inbounds [7 x i8], [7 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} + +;; Allocated buffer is aligned by 16, so it places from 0 to 15 bytes in 16 +;; bytes local vars area. + +; Function Attrs: nounwind +define i8* @test_frame16_align16(i8* %0) { +; CHECK-LABEL: test_frame16_align16: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -192 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 176(, %s11) +; CHECK-NEXT: st1b %s1, 176(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; CHECKFP-LABEL: test_frame16_align16: +; CHECKFP: # %bb.0: +; CHECKFP-NEXT: st %s9, (, %s11) +; CHECKFP-NEXT: st %s10, 8(, %s11) +; CHECKFP-NEXT: st %s15, 24(, %s11) +; CHECKFP-NEXT: st %s16, 32(, %s11) +; CHECKFP-NEXT: or %s9, 0, %s11 +; CHECKFP-NEXT: lea %s13, -192 +; CHECKFP-NEXT: and %s13, %s13, (32)0 +; CHECKFP-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECKFP-NEXT: brge.l.t %s11, %s8, .LBB2_2 +; CHECKFP-NEXT: # %bb.1: +; CHECKFP-NEXT: ld %s61, 24(, %s14) +; CHECKFP-NEXT: or %s62, 0, %s0 +; CHECKFP-NEXT: lea %s63, 315 +; CHECKFP-NEXT: shm.l %s63, (%s61) +; CHECKFP-NEXT: shm.l %s8, 8(%s61) +; CHECKFP-NEXT: shm.l %s11, 16(%s61) +; CHECKFP-NEXT: monc +; CHECKFP-NEXT: or %s0, 0, %s62 +; CHECKFP-NEXT: .LBB2_2: +; CHECKFP-NEXT: ld1b.zx %s1, (, %s0) +; CHECKFP-NEXT: lea %s0, -16(, %s9) +; CHECKFP-NEXT: st1b %s1, -16(, %s9) +; CHECKFP-NEXT: or %s11, 0, %s9 +; CHECKFP-NEXT: ld %s16, 32(, %s11) +; CHECKFP-NEXT: ld %s15, 24(, %s11) +; CHECKFP-NEXT: ld %s10, 8(, %s11) +; CHECKFP-NEXT: ld %s9, (, %s11) +; CHECKFP-NEXT: b.l.t (, %s10) + %2 = alloca [16 x i8], align 16 + %3 = getelementptr inbounds [16 x i8], [16 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} + +;; Allocated buffer is aligned by 32, so it places from 0 to 15 bytes in 48 +;; bytes local vars area. Or it places from 192 (aligned to 32 bytes) to +;; 207 bytes in 224 + alpha allocated local vars area. + +; Function Attrs: nounwind +define i8* @test_frame16_align32(i8* %0) { +; CHECK-LABEL: test_frame16_align32: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -224 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: and %s11, %s11, (59)1 +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB3_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 192(, %s11) +; CHECK-NEXT: st1b %s1, 192(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; CHECKFP-LABEL: test_frame16_align32: +; CHECKFP: # %bb.0: +; CHECKFP-NEXT: st %s9, (, %s11) +; CHECKFP-NEXT: st %s10, 8(, %s11) +; CHECKFP-NEXT: st %s15, 24(, %s11) +; CHECKFP-NEXT: st %s16, 32(, %s11) +; CHECKFP-NEXT: or %s9, 0, %s11 +; CHECKFP-NEXT: lea %s13, -224 +; CHECKFP-NEXT: and %s13, %s13, (32)0 +; CHECKFP-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECKFP-NEXT: and %s11, %s11, (59)1 +; CHECKFP-NEXT: brge.l.t %s11, %s8, .LBB3_2 +; CHECKFP-NEXT: # %bb.1: +; CHECKFP-NEXT: ld %s61, 24(, %s14) +; CHECKFP-NEXT: or %s62, 0, %s0 +; CHECKFP-NEXT: lea %s63, 315 +; CHECKFP-NEXT: shm.l %s63, (%s61) +; CHECKFP-NEXT: shm.l %s8, 8(%s61) +; CHECKFP-NEXT: shm.l %s11, 16(%s61) +; CHECKFP-NEXT: monc +; CHECKFP-NEXT: or %s0, 0, %s62 +; CHECKFP-NEXT: .LBB3_2: +; CHECKFP-NEXT: ld1b.zx %s1, (, %s0) +; CHECKFP-NEXT: lea %s0, 192(, %s11) +; CHECKFP-NEXT: st1b %s1, 192(, %s11) +; CHECKFP-NEXT: or %s11, 0, %s9 +; CHECKFP-NEXT: ld %s16, 32(, %s11) +; CHECKFP-NEXT: ld %s15, 24(, %s11) +; CHECKFP-NEXT: ld %s10, 8(, %s11) +; CHECKFP-NEXT: ld %s9, (, %s11) +; CHECKFP-NEXT: b.l.t (, %s10) + %2 = alloca [16 x i8], align 32 + %3 = getelementptr inbounds [16 x i8], [16 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} + +;; Allocated buffer is aligned by 32, so it places from 0 to 31 bytes in 48 +;; + alpha bytes local vars area, or it places from 192 (32 bytes aligned 176) +;; to 223 in 224 + alpha bytes local vars area.. + +; Function Attrs: nounwind +define i8* @test_frame32_align32(i8* %0) { +; CHECK-LABEL: test_frame32_align32: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -224 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: and %s11, %s11, (59)1 +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB4_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB4_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 192(, %s11) +; CHECK-NEXT: st1b %s1, 192(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; CHECKFP-LABEL: test_frame32_align32: +; CHECKFP: # %bb.0: +; CHECKFP-NEXT: st %s9, (, %s11) +; CHECKFP-NEXT: st %s10, 8(, %s11) +; CHECKFP-NEXT: st %s15, 24(, %s11) +; CHECKFP-NEXT: st %s16, 32(, %s11) +; CHECKFP-NEXT: or %s9, 0, %s11 +; CHECKFP-NEXT: lea %s13, -224 +; CHECKFP-NEXT: and %s13, %s13, (32)0 +; CHECKFP-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECKFP-NEXT: and %s11, %s11, (59)1 +; CHECKFP-NEXT: brge.l.t %s11, %s8, .LBB4_2 +; CHECKFP-NEXT: # %bb.1: +; CHECKFP-NEXT: ld %s61, 24(, %s14) +; CHECKFP-NEXT: or %s62, 0, %s0 +; CHECKFP-NEXT: lea %s63, 315 +; CHECKFP-NEXT: shm.l %s63, (%s61) +; CHECKFP-NEXT: shm.l %s8, 8(%s61) +; CHECKFP-NEXT: shm.l %s11, 16(%s61) +; CHECKFP-NEXT: monc +; CHECKFP-NEXT: or %s0, 0, %s62 +; CHECKFP-NEXT: .LBB4_2: +; CHECKFP-NEXT: ld1b.zx %s1, (, %s0) +; CHECKFP-NEXT: lea %s0, 192(, %s11) +; CHECKFP-NEXT: st1b %s1, 192(, %s11) +; CHECKFP-NEXT: or %s11, 0, %s9 +; CHECKFP-NEXT: ld %s16, 32(, %s11) +; CHECKFP-NEXT: ld %s15, 24(, %s11) +; CHECKFP-NEXT: ld %s10, 8(, %s11) +; CHECKFP-NEXT: ld %s9, (, %s11) +; CHECKFP-NEXT: b.l.t (, %s10) + %2 = alloca [32 x i8], align 32 + %3 = getelementptr inbounds [32 x i8], [32 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} + +;; Dynamically allocated buffer is aligned by 16, so it places from 0 to 31 +;; bytes in allocated area, or it places from 240 (32 bytes aligned 176+64) +;; to 271 in allocated area (actually it places not newly allocated area +;; but in somewhere between newly allocated area and allocated area at the +;; prologue since VE ABI requires the reserved area at the top of stack). + +;; FIXME: (size+15)/16*16 is not enough. + +; Function Attrs: nounwind +define i8* @test_frame_dynalign16(i8* %0, i64 %1) { +; CHECK-LABEL: test_frame_dynalign16: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -240 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB5_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: or %s2, 0, %s0 +; CHECK-NEXT: lea %s0, 15(, %s1) +; CHECK-NEXT: and %s0, -16, %s0 +; CHECK-NEXT: lea %s1, __ve_grow_stack@lo +; CHECK-NEXT: and %s1, %s1, (32)0 +; CHECK-NEXT: lea.sl %s12, __ve_grow_stack@hi(, %s1) +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: lea %s0, 240(, %s11) +; CHECK-NEXT: ld1b.zx %s1, (, %s2) +; CHECK-NEXT: st1b %s1, (, %s0) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; CHECKFP-LABEL: test_frame_dynalign16: +; CHECKFP: # %bb.0: +; CHECKFP-NEXT: st %s9, (, %s11) +; CHECKFP-NEXT: st %s10, 8(, %s11) +; CHECKFP-NEXT: st %s15, 24(, %s11) +; CHECKFP-NEXT: st %s16, 32(, %s11) +; CHECKFP-NEXT: or %s9, 0, %s11 +; CHECKFP-NEXT: lea %s13, -240 +; CHECKFP-NEXT: and %s13, %s13, (32)0 +; CHECKFP-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECKFP-NEXT: brge.l.t %s11, %s8, .LBB5_2 +; CHECKFP-NEXT: # %bb.1: +; CHECKFP-NEXT: ld %s61, 24(, %s14) +; CHECKFP-NEXT: or %s62, 0, %s0 +; CHECKFP-NEXT: lea %s63, 315 +; CHECKFP-NEXT: shm.l %s63, (%s61) +; CHECKFP-NEXT: shm.l %s8, 8(%s61) +; CHECKFP-NEXT: shm.l %s11, 16(%s61) +; CHECKFP-NEXT: monc +; CHECKFP-NEXT: or %s0, 0, %s62 +; CHECKFP-NEXT: .LBB5_2: +; CHECKFP-NEXT: or %s2, 0, %s0 +; CHECKFP-NEXT: lea %s0, 15(, %s1) +; CHECKFP-NEXT: and %s0, -16, %s0 +; CHECKFP-NEXT: lea %s1, __ve_grow_stack@lo +; CHECKFP-NEXT: and %s1, %s1, (32)0 +; CHECKFP-NEXT: lea.sl %s12, __ve_grow_stack@hi(, %s1) +; CHECKFP-NEXT: bsic %s10, (, %s12) +; CHECKFP-NEXT: lea %s0, 240(, %s11) +; CHECKFP-NEXT: ld1b.zx %s1, (, %s2) +; CHECKFP-NEXT: st1b %s1, (, %s0) +; CHECKFP-NEXT: or %s11, 0, %s9 +; CHECKFP-NEXT: ld %s16, 32(, %s11) +; CHECKFP-NEXT: ld %s15, 24(, %s11) +; CHECKFP-NEXT: ld %s10, 8(, %s11) +; CHECKFP-NEXT: ld %s9, (, %s11) +; CHECKFP-NEXT: b.l.t (, %s10) + %3 = alloca i8, i64 %1, align 16 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} + +;; This test allocates static buffer with 16 bytes align and dynamic buffer +;; with 32 bytes align. In LLVM, stack frame is always aligned to 32 bytes +;; (bigger one). So, LLVM allocates 176 (RSA) + 64 (call site) + 32 (32 bytes +;; aligned 16 bytes data) + 16 (pad to align) if FP is not eliminated. +;; Statically allocated buffer is aligned to 16, so it places from 16 to 31 +;; bytes from BP in 32 + alpha bytes local vars area, or it places from 272 +;; to 287 bytes from BP in 288 + alpha bytes local vars area. +;; Dynamically allocated buffer is aligned to 32, so it places from aligned +;; address between 240 and 271 from SP. + +; Function Attrs: nounwind +define i8* @test_frame16_align16_dynalign32(i8* %0, i64 %n) { +; CHECK-LABEL: test_frame16_align16_dynalign32: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: st %s17, 40(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -288 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: and %s11, %s11, (59)1 +; CHECK-NEXT: or %s17, 0, %s11 +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB6_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB6_2: +; CHECK-NEXT: ld1b.zx %s0, (, %s0) +; CHECK-NEXT: st1b %s0, 272(, %s17) +; CHECK-NEXT: lea %s0, 15(, %s1) +; CHECK-NEXT: and %s0, -16, %s0 +; CHECK-NEXT: lea %s1, __ve_grow_stack_align@lo +; CHECK-NEXT: and %s1, %s1, (32)0 +; CHECK-NEXT: lea.sl %s12, __ve_grow_stack_align@hi(, %s1) +; CHECK-NEXT: or %s1, -32, (0)1 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: lea %s0, 240(, %s11) +; CHECK-NEXT: ld1b.zx %s1, 272(, %s17) +; CHECK-NEXT: lea %s0, 31(, %s0) +; CHECK-NEXT: and %s0, -32, %s0 +; CHECK-NEXT: st1b %s1, (, %s0) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s17, 40(, %s11) +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; CHECKFP-LABEL: test_frame16_align16_dynalign32: +; CHECKFP: # %bb.0: +; CHECKFP-NEXT: st %s9, (, %s11) +; CHECKFP-NEXT: st %s10, 8(, %s11) +; CHECKFP-NEXT: st %s15, 24(, %s11) +; CHECKFP-NEXT: st %s16, 32(, %s11) +; CHECKFP-NEXT: st %s17, 40(, %s11) +; CHECKFP-NEXT: or %s9, 0, %s11 +; CHECKFP-NEXT: lea %s13, -288 +; CHECKFP-NEXT: and %s13, %s13, (32)0 +; CHECKFP-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECKFP-NEXT: and %s11, %s11, (59)1 +; CHECKFP-NEXT: or %s17, 0, %s11 +; CHECKFP-NEXT: brge.l.t %s11, %s8, .LBB6_2 +; CHECKFP-NEXT: # %bb.1: +; CHECKFP-NEXT: ld %s61, 24(, %s14) +; CHECKFP-NEXT: or %s62, 0, %s0 +; CHECKFP-NEXT: lea %s63, 315 +; CHECKFP-NEXT: shm.l %s63, (%s61) +; CHECKFP-NEXT: shm.l %s8, 8(%s61) +; CHECKFP-NEXT: shm.l %s11, 16(%s61) +; CHECKFP-NEXT: monc +; CHECKFP-NEXT: or %s0, 0, %s62 +; CHECKFP-NEXT: .LBB6_2: +; CHECKFP-NEXT: ld1b.zx %s0, (, %s0) +; CHECKFP-NEXT: st1b %s0, 272(, %s17) +; CHECKFP-NEXT: lea %s0, 15(, %s1) +; CHECKFP-NEXT: and %s0, -16, %s0 +; CHECKFP-NEXT: lea %s1, __ve_grow_stack_align@lo +; CHECKFP-NEXT: and %s1, %s1, (32)0 +; CHECKFP-NEXT: lea.sl %s12, __ve_grow_stack_align@hi(, %s1) +; CHECKFP-NEXT: or %s1, -32, (0)1 +; CHECKFP-NEXT: bsic %s10, (, %s12) +; CHECKFP-NEXT: lea %s0, 240(, %s11) +; CHECKFP-NEXT: ld1b.zx %s1, 272(, %s17) +; CHECKFP-NEXT: lea %s0, 31(, %s0) +; CHECKFP-NEXT: and %s0, -32, %s0 +; CHECKFP-NEXT: st1b %s1, (, %s0) +; CHECKFP-NEXT: or %s11, 0, %s9 +; CHECKFP-NEXT: ld %s17, 40(, %s11) +; CHECKFP-NEXT: ld %s16, 32(, %s11) +; CHECKFP-NEXT: ld %s15, 24(, %s11) +; CHECKFP-NEXT: ld %s10, 8(, %s11) +; CHECKFP-NEXT: ld %s9, (, %s11) +; CHECKFP-NEXT: b.l.t (, %s10) + %2 = alloca [16 x i8], align 16 + %3 = getelementptr inbounds [16 x i8], [16 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + %5 = alloca i8, i64 %n, align 32 + %6 = load i8, i8* %3, align 1 + store i8 %6, i8* %5, align 1 + ret i8* %5 +} + diff --git a/llvm/test/CodeGen/VE/Scalar/stackframe_call.ll b/llvm/test/CodeGen/VE/Scalar/stackframe_call.ll new file mode 100644 index 0000000000000..fe120d091679e --- /dev/null +++ b/llvm/test/CodeGen/VE/Scalar/stackframe_call.ll @@ -0,0 +1,593 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=ve | FileCheck %s +; RUN: llc < %s -mtriple=ve -relocation-model=pic \ +; RUN: | FileCheck %s --check-prefix=PIC + +;;; Check stack frame allocation of a function which calls other functions +;;; under following conditions and combinations of them: +;;; - access variable or not +;;; - no stack object, a stack object using BP, or a stack object not using BP +;;; - isPositionIndependent or not + +@data = external global i8, align 1 + +; Function Attrs: nounwind +define i8* @test_frame0(i8* %0, i8* %1) { +; CHECK-LABEL: test_frame0: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -240 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB0_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB0_2: +; CHECK-NEXT: lea %s2, fun@lo +; CHECK-NEXT: and %s2, %s2, (32)0 +; CHECK-NEXT: lea.sl %s12, fun@hi(, %s2) +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: test_frame0: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -240 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: brge.l.t %s11, %s8, .LBB0_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB0_2: +; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; PIC-NEXT: and %s15, %s15, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; PIC-NEXT: lea %s12, fun@plt_lo(-24) +; PIC-NEXT: and %s12, %s12, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s12, fun@plt_hi(%s16, %s12) +; PIC-NEXT: bsic %s10, (, %s12) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + %3 = tail call i8* @fun(i8* %0, i8* %1) + ret i8* %3 +} + +declare i8* @fun(i8*, i8*) + +; Function Attrs: nounwind +define i8* @test_frame32(i8* %0) { +; CHECK-LABEL: test_frame32: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -272 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB1_2: +; CHECK-NEXT: or %s1, 0, %s0 +; CHECK-NEXT: lea %s0, fun@lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s12, fun@hi(, %s0) +; CHECK-NEXT: lea %s0, 240(, %s11) +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: test_frame32: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -272 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: brge.l.t %s11, %s8, .LBB1_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB1_2: +; PIC-NEXT: or %s1, 0, %s0 +; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; PIC-NEXT: and %s15, %s15, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; PIC-NEXT: lea %s12, fun@plt_lo(-24) +; PIC-NEXT: and %s12, %s12, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s12, fun@plt_hi(%s16, %s12) +; PIC-NEXT: lea %s0, 240(, %s11) +; PIC-NEXT: bsic %s10, (, %s12) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + %2 = alloca [32 x i8], align 1 + %3 = getelementptr inbounds [32 x i8], [32 x i8]* %2, i64 0, i64 0 + call void @llvm.lifetime.start.p0i8(i64 32, i8* nonnull %3) + %4 = call i8* @fun(i8* nonnull %3, i8* %0) + call void @llvm.lifetime.end.p0i8(i64 32, i8* nonnull %3) + ret i8* %4 +} + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) + +; Function Attrs: nounwind +define i8* @test_align32(i32 signext %0, i8* nocapture readnone %1) { +; CHECK-LABEL: test_align32: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: st %s17, 40(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -288 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: and %s11, %s11, (59)1 +; CHECK-NEXT: or %s17, 0, %s11 +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: lea %s0, 15(, %s0) +; CHECK-NEXT: and %s0, -16, %s0 +; CHECK-NEXT: lea %s1, __ve_grow_stack_align@lo +; CHECK-NEXT: and %s1, %s1, (32)0 +; CHECK-NEXT: lea.sl %s12, __ve_grow_stack_align@hi(, %s1) +; CHECK-NEXT: or %s1, -32, (0)1 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: lea %s0, 240(, %s11) +; CHECK-NEXT: lea %s0, 31(, %s0) +; CHECK-NEXT: and %s1, -32, %s0 +; CHECK-NEXT: lea %s0, fun@lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s12, fun@hi(, %s0) +; CHECK-NEXT: lea %s0, 256(, %s17) +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s17, 40(, %s11) +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: test_align32: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: st %s17, 40(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -288 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: and %s11, %s11, (59)1 +; PIC-NEXT: or %s17, 0, %s11 +; PIC-NEXT: brge.l.t %s11, %s8, .LBB2_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB2_2: +; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; PIC-NEXT: and %s15, %s15, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; PIC-NEXT: lea %s0, 15(, %s0) +; PIC-NEXT: and %s0, -16, %s0 +; PIC-NEXT: lea %s12, __ve_grow_stack_align@plt_lo(-24) +; PIC-NEXT: and %s12, %s12, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s12, __ve_grow_stack_align@plt_hi(%s16, %s12) +; PIC-NEXT: or %s1, -32, (0)1 +; PIC-NEXT: bsic %s10, (, %s12) +; PIC-NEXT: lea %s0, 240(, %s11) +; PIC-NEXT: lea %s0, 31(, %s0) +; PIC-NEXT: and %s1, -32, %s0 +; PIC-NEXT: lea %s12, fun@plt_lo(-24) +; PIC-NEXT: and %s12, %s12, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s12, fun@plt_hi(%s16, %s12) +; PIC-NEXT: lea %s0, 256(, %s17) +; PIC-NEXT: bsic %s10, (, %s12) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s17, 40(, %s11) +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + %3 = alloca [32 x i8], align 32 + %4 = getelementptr inbounds [32 x i8], [32 x i8]* %3, i64 0, i64 0 + call void @llvm.lifetime.start.p0i8(i64 32, i8* nonnull %4) + %5 = sext i32 %0 to i64 + %6 = alloca i8, i64 %5, align 32 + %7 = call i8* @fun(i8* nonnull %4, i8* nonnull %6) + call void @llvm.lifetime.end.p0i8(i64 32, i8* nonnull %4) + ret i8* %7 +} + +; Function Attrs: nounwind +define i8* @test_frame0_var(i8* %0, i8* %1) { +; CHECK-LABEL: test_frame0_var: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -240 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB3_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: lea %s2, data@lo +; CHECK-NEXT: and %s2, %s2, (32)0 +; CHECK-NEXT: lea.sl %s2, data@hi(, %s2) +; CHECK-NEXT: ld1b.zx %s2, (, %s2) +; CHECK-NEXT: st1b %s2, (, %s0) +; CHECK-NEXT: lea %s2, fun@lo +; CHECK-NEXT: and %s2, %s2, (32)0 +; CHECK-NEXT: lea.sl %s12, fun@hi(, %s2) +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: test_frame0_var: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -240 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: brge.l.t %s11, %s8, .LBB3_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB3_2: +; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; PIC-NEXT: and %s15, %s15, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; PIC-NEXT: lea %s2, data@got_lo +; PIC-NEXT: and %s2, %s2, (32)0 +; PIC-NEXT: lea.sl %s2, data@got_hi(, %s2) +; PIC-NEXT: ld %s2, (%s2, %s15) +; PIC-NEXT: ld1b.zx %s2, (, %s2) +; PIC-NEXT: st1b %s2, (, %s0) +; PIC-NEXT: lea %s12, fun@plt_lo(-24) +; PIC-NEXT: and %s12, %s12, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s12, fun@plt_hi(%s16, %s12) +; PIC-NEXT: bsic %s10, (, %s12) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + %3 = load i8, i8* @data, align 1 + store i8 %3, i8* %0, align 1 + %4 = tail call i8* @fun(i8* nonnull %0, i8* %1) + ret i8* %4 +} + +; Function Attrs: nounwind +define i8* @test_frame32_var(i8* %0) { +; CHECK-LABEL: test_frame32_var: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -272 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB4_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB4_2: +; CHECK-NEXT: lea %s1, data@lo +; CHECK-NEXT: and %s1, %s1, (32)0 +; CHECK-NEXT: lea.sl %s1, data@hi(, %s1) +; CHECK-NEXT: ld1b.zx %s2, (, %s1) +; CHECK-NEXT: or %s1, 0, %s0 +; CHECK-NEXT: st1b %s2, 240(, %s11) +; CHECK-NEXT: lea %s0, fun@lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s12, fun@hi(, %s0) +; CHECK-NEXT: lea %s0, 240(, %s11) +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: test_frame32_var: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -272 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: brge.l.t %s11, %s8, .LBB4_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB4_2: +; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; PIC-NEXT: and %s15, %s15, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; PIC-NEXT: lea %s1, data@got_lo +; PIC-NEXT: and %s1, %s1, (32)0 +; PIC-NEXT: lea.sl %s1, data@got_hi(, %s1) +; PIC-NEXT: ld %s1, (%s1, %s15) +; PIC-NEXT: ld1b.zx %s2, (, %s1) +; PIC-NEXT: or %s1, 0, %s0 +; PIC-NEXT: st1b %s2, 240(, %s11) +; PIC-NEXT: lea %s12, fun@plt_lo(-24) +; PIC-NEXT: and %s12, %s12, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s12, fun@plt_hi(%s16, %s12) +; PIC-NEXT: lea %s0, 240(, %s11) +; PIC-NEXT: bsic %s10, (, %s12) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + %2 = alloca [32 x i8], align 1 + %3 = getelementptr inbounds [32 x i8], [32 x i8]* %2, i64 0, i64 0 + call void @llvm.lifetime.start.p0i8(i64 32, i8* nonnull %3) + %4 = load i8, i8* @data, align 1 + store i8 %4, i8* %3, align 1 + %5 = call i8* @fun(i8* nonnull %3, i8* %0) + call void @llvm.lifetime.end.p0i8(i64 32, i8* nonnull %3) + ret i8* %5 +} + +; Function Attrs: nounwind +define i8* @test_align32_var(i32 signext %0, i8* nocapture readnone %1) { +; CHECK-LABEL: test_align32_var: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: st %s17, 40(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -288 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: and %s11, %s11, (59)1 +; CHECK-NEXT: or %s17, 0, %s11 +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB5_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: lea %s0, 15(, %s0) +; CHECK-NEXT: and %s0, -16, %s0 +; CHECK-NEXT: lea %s1, __ve_grow_stack_align@lo +; CHECK-NEXT: and %s1, %s1, (32)0 +; CHECK-NEXT: lea.sl %s12, __ve_grow_stack_align@hi(, %s1) +; CHECK-NEXT: or %s1, -32, (0)1 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: lea %s0, 240(, %s11) +; CHECK-NEXT: lea %s1, data@lo +; CHECK-NEXT: and %s1, %s1, (32)0 +; CHECK-NEXT: lea.sl %s1, data@hi(, %s1) +; CHECK-NEXT: ld1b.zx %s2, (, %s1) +; CHECK-NEXT: lea %s0, 31(, %s0) +; CHECK-NEXT: and %s1, -32, %s0 +; CHECK-NEXT: st1b %s2, (, %s1) +; CHECK-NEXT: lea %s0, fun@lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s12, fun@hi(, %s0) +; CHECK-NEXT: lea %s0, 256(, %s17) +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s17, 40(, %s11) +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: test_align32_var: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: st %s17, 40(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -288 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: and %s11, %s11, (59)1 +; PIC-NEXT: or %s17, 0, %s11 +; PIC-NEXT: brge.l.t %s11, %s8, .LBB5_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB5_2: +; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; PIC-NEXT: and %s15, %s15, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; PIC-NEXT: lea %s0, 15(, %s0) +; PIC-NEXT: and %s0, -16, %s0 +; PIC-NEXT: lea %s12, __ve_grow_stack_align@plt_lo(-24) +; PIC-NEXT: and %s12, %s12, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s12, __ve_grow_stack_align@plt_hi(%s16, %s12) +; PIC-NEXT: or %s1, -32, (0)1 +; PIC-NEXT: bsic %s10, (, %s12) +; PIC-NEXT: lea %s0, data@got_lo +; PIC-NEXT: and %s0, %s0, (32)0 +; PIC-NEXT: lea.sl %s0, data@got_hi(, %s0) +; PIC-NEXT: ld %s0, (%s0, %s15) +; PIC-NEXT: lea %s1, 240(, %s11) +; PIC-NEXT: ld1b.zx %s0, (, %s0) +; PIC-NEXT: lea %s1, 31(, %s1) +; PIC-NEXT: and %s1, -32, %s1 +; PIC-NEXT: st1b %s0, (, %s1) +; PIC-NEXT: lea %s12, fun@plt_lo(-24) +; PIC-NEXT: and %s12, %s12, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s12, fun@plt_hi(%s16, %s12) +; PIC-NEXT: lea %s0, 256(, %s17) +; PIC-NEXT: bsic %s10, (, %s12) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s17, 40(, %s11) +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + %3 = alloca [32 x i8], align 32 + %4 = getelementptr inbounds [32 x i8], [32 x i8]* %3, i64 0, i64 0 + call void @llvm.lifetime.start.p0i8(i64 32, i8* nonnull %4) + %5 = sext i32 %0 to i64 + %6 = alloca i8, i64 %5, align 32 + %7 = load i8, i8* @data, align 1 + store i8 %7, i8* %6, align 32 + %8 = call i8* @fun(i8* nonnull %4, i8* nonnull %6) + call void @llvm.lifetime.end.p0i8(i64 32, i8* nonnull %4) + ret i8* %8 +} diff --git a/llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll b/llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll new file mode 100644 index 0000000000000..5488b25ed3b84 --- /dev/null +++ b/llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll @@ -0,0 +1,458 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=ve | FileCheck %s +; RUN: llc < %s -mtriple=ve -relocation-model=pic \ +; RUN: | FileCheck %s --check-prefix=PIC + +;;; Check stack frame allocation of a function which does not calls other +;;; functions under following conditions and combinations of them: +;;; - access variable or not +;;; - no stack object, a stack object using BP, or a stack object not using BP +;;; - isPositionIndependent or not + +@data = external global i8, align 1 + +; Function Attrs: norecurse nounwind readnone +define i8* @test_frame0(i8* nocapture readnone %0, i8* readnone returned %1) { +; CHECK-LABEL: test_frame0: +; CHECK: # %bb.0: +; CHECK-NEXT: or %s0, 0, %s1 +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: test_frame0: +; PIC: # %bb.0: +; PIC-NEXT: or %s0, 0, %s1 +; PIC-NEXT: b.l.t (, %s10) + ret i8* %1 +} + +; Function Attrs: nofree nounwind +define nonnull i8* @test_frame32(i8* nocapture readonly %0) { +; CHECK-LABEL: test_frame32: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -208 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB1_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 176(, %s11) +; CHECK-NEXT: st1b %s1, 176(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: test_frame32: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -208 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: brge.l.t %s11, %s8, .LBB1_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB1_2: +; PIC-NEXT: ld1b.zx %s1, (, %s0) +; PIC-NEXT: lea %s0, 176(, %s11) +; PIC-NEXT: st1b %s1, 176(, %s11) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + %2 = alloca [32 x i8], align 1 + %3 = getelementptr inbounds [32 x i8], [32 x i8]* %2, i64 0, i64 0 + call void @llvm.lifetime.start.p0i8(i64 32, i8* nonnull %3) + %4 = load i8, i8* %0, align 1 + store volatile i8 %4, i8* %3, align 1 + call void @llvm.lifetime.end.p0i8(i64 32, i8* nonnull %3) + ret i8* %3 +} + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) + +; Function Attrs: nofree nounwind +define noalias nonnull i8* @test_align32(i32 signext %0, i8* nocapture readonly %1) { +; CHECK-LABEL: test_align32: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: st %s17, 40(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -288 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: and %s11, %s11, (59)1 +; CHECK-NEXT: or %s17, 0, %s11 +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: or %s2, 0, %s1 +; CHECK-NEXT: lea %s0, 15(, %s0) +; CHECK-NEXT: and %s0, -16, %s0 +; CHECK-NEXT: lea %s1, __ve_grow_stack_align@lo +; CHECK-NEXT: and %s1, %s1, (32)0 +; CHECK-NEXT: lea.sl %s12, __ve_grow_stack_align@hi(, %s1) +; CHECK-NEXT: or %s1, -32, (0)1 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: lea %s0, 240(, %s11) +; CHECK-NEXT: ld1b.zx %s1, (, %s2) +; CHECK-NEXT: lea %s0, 31(, %s0) +; CHECK-NEXT: and %s2, -32, %s0 +; CHECK-NEXT: lea %s0, 256(, %s17) +; CHECK-NEXT: st1b %s1, (, %s2) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s17, 40(, %s11) +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: test_align32: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: st %s17, 40(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -288 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: and %s11, %s11, (59)1 +; PIC-NEXT: or %s17, 0, %s11 +; PIC-NEXT: brge.l.t %s11, %s8, .LBB2_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB2_2: +; PIC-NEXT: or %s2, 0, %s1 +; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; PIC-NEXT: and %s15, %s15, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; PIC-NEXT: lea %s0, 15(, %s0) +; PIC-NEXT: and %s0, -16, %s0 +; PIC-NEXT: lea %s12, __ve_grow_stack_align@plt_lo(-24) +; PIC-NEXT: and %s12, %s12, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s12, __ve_grow_stack_align@plt_hi(%s16, %s12) +; PIC-NEXT: or %s1, -32, (0)1 +; PIC-NEXT: bsic %s10, (, %s12) +; PIC-NEXT: lea %s0, 240(, %s11) +; PIC-NEXT: ld1b.zx %s1, (, %s2) +; PIC-NEXT: lea %s0, 31(, %s0) +; PIC-NEXT: and %s2, -32, %s0 +; PIC-NEXT: lea %s0, 256(, %s17) +; PIC-NEXT: st1b %s1, (, %s2) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s17, 40(, %s11) +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + %3 = alloca [32 x i8], align 32 + %4 = getelementptr inbounds [32 x i8], [32 x i8]* %3, i64 0, i64 0 + call void @llvm.lifetime.start.p0i8(i64 32, i8* nonnull %4) + %5 = sext i32 %0 to i64 + %6 = alloca i8, i64 %5, align 32 + %7 = load i8, i8* %1, align 1 + store volatile i8 %7, i8* %6, align 32 + call void @llvm.lifetime.end.p0i8(i64 32, i8* nonnull %4) + ret i8* %4 +} + +; Function Attrs: nofree norecurse nounwind +define i8* @test_frame0_var(i8* returned %0, i8* nocapture readnone %1) { +; CHECK-LABEL: test_frame0_var: +; CHECK: # %bb.0: +; CHECK-NEXT: lea %s1, data@lo +; CHECK-NEXT: and %s1, %s1, (32)0 +; CHECK-NEXT: lea.sl %s1, data@hi(, %s1) +; CHECK-NEXT: ld1b.zx %s1, (, %s1) +; CHECK-NEXT: st1b %s1, (, %s0) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: test_frame0_var: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -176 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: brge.l.t %s11, %s8, .LBB3_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB3_2: +; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; PIC-NEXT: and %s15, %s15, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; PIC-NEXT: lea %s1, data@got_lo +; PIC-NEXT: and %s1, %s1, (32)0 +; PIC-NEXT: lea.sl %s1, data@got_hi(, %s1) +; PIC-NEXT: ld %s1, (%s1, %s15) +; PIC-NEXT: ld1b.zx %s1, (, %s1) +; PIC-NEXT: st1b %s1, (, %s0) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + %3 = load i8, i8* @data, align 1 + store i8 %3, i8* %0, align 1 + ret i8* %0 +} + +; Function Attrs: nofree nounwind +define nonnull i8* @test_frame32_var(i8* nocapture readnone %0) { +; CHECK-LABEL: test_frame32_var: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -208 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB4_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB4_2: +; CHECK-NEXT: lea %s0, data@lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, data@hi(, %s0) +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 176(, %s11) +; CHECK-NEXT: st1b %s1, 176(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: test_frame32_var: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -208 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: brge.l.t %s11, %s8, .LBB4_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB4_2: +; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; PIC-NEXT: and %s15, %s15, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; PIC-NEXT: lea %s0, data@got_lo +; PIC-NEXT: and %s0, %s0, (32)0 +; PIC-NEXT: lea.sl %s0, data@got_hi(, %s0) +; PIC-NEXT: ld %s0, (%s0, %s15) +; PIC-NEXT: ld1b.zx %s1, (, %s0) +; PIC-NEXT: lea %s0, 176(, %s11) +; PIC-NEXT: st1b %s1, 176(, %s11) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + %2 = alloca [32 x i8], align 1 + %3 = getelementptr inbounds [32 x i8], [32 x i8]* %2, i64 0, i64 0 + call void @llvm.lifetime.start.p0i8(i64 32, i8* nonnull %3) + %4 = load i8, i8* @data, align 1 + store volatile i8 %4, i8* %3, align 1 + call void @llvm.lifetime.end.p0i8(i64 32, i8* nonnull %3) + ret i8* %3 +} + +; Function Attrs: nofree nounwind +define noalias nonnull i8* @test_align32_var(i32 signext %0, i8* nocapture readonly %1) { +; CHECK-LABEL: test_align32_var: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: st %s17, 40(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -288 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: and %s11, %s11, (59)1 +; CHECK-NEXT: or %s17, 0, %s11 +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB5_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: or %s2, 0, %s1 +; CHECK-NEXT: lea %s0, 15(, %s0) +; CHECK-NEXT: and %s0, -16, %s0 +; CHECK-NEXT: lea %s1, __ve_grow_stack_align@lo +; CHECK-NEXT: and %s1, %s1, (32)0 +; CHECK-NEXT: lea.sl %s12, __ve_grow_stack_align@hi(, %s1) +; CHECK-NEXT: or %s1, -32, (0)1 +; CHECK-NEXT: bsic %s10, (, %s12) +; CHECK-NEXT: lea %s0, 240(, %s11) +; CHECK-NEXT: ld1b.zx %s1, (, %s2) +; CHECK-NEXT: lea %s0, 31(, %s0) +; CHECK-NEXT: and %s2, -32, %s0 +; CHECK-NEXT: lea %s0, 256(, %s17) +; CHECK-NEXT: st1b %s1, (, %s2) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s17, 40(, %s11) +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) +; +; PIC-LABEL: test_align32_var: +; PIC: # %bb.0: +; PIC-NEXT: st %s9, (, %s11) +; PIC-NEXT: st %s10, 8(, %s11) +; PIC-NEXT: st %s15, 24(, %s11) +; PIC-NEXT: st %s16, 32(, %s11) +; PIC-NEXT: st %s17, 40(, %s11) +; PIC-NEXT: or %s9, 0, %s11 +; PIC-NEXT: lea %s13, -288 +; PIC-NEXT: and %s13, %s13, (32)0 +; PIC-NEXT: lea.sl %s11, -1(%s13, %s11) +; PIC-NEXT: and %s11, %s11, (59)1 +; PIC-NEXT: or %s17, 0, %s11 +; PIC-NEXT: brge.l.t %s11, %s8, .LBB5_2 +; PIC-NEXT: # %bb.1: +; PIC-NEXT: ld %s61, 24(, %s14) +; PIC-NEXT: or %s62, 0, %s0 +; PIC-NEXT: lea %s63, 315 +; PIC-NEXT: shm.l %s63, (%s61) +; PIC-NEXT: shm.l %s8, 8(%s61) +; PIC-NEXT: shm.l %s11, 16(%s61) +; PIC-NEXT: monc +; PIC-NEXT: or %s0, 0, %s62 +; PIC-NEXT: .LBB5_2: +; PIC-NEXT: or %s2, 0, %s1 +; PIC-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; PIC-NEXT: and %s15, %s15, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; PIC-NEXT: lea %s0, 15(, %s0) +; PIC-NEXT: and %s0, -16, %s0 +; PIC-NEXT: lea %s12, __ve_grow_stack_align@plt_lo(-24) +; PIC-NEXT: and %s12, %s12, (32)0 +; PIC-NEXT: sic %s16 +; PIC-NEXT: lea.sl %s12, __ve_grow_stack_align@plt_hi(%s16, %s12) +; PIC-NEXT: or %s1, -32, (0)1 +; PIC-NEXT: bsic %s10, (, %s12) +; PIC-NEXT: lea %s0, 240(, %s11) +; PIC-NEXT: ld1b.zx %s1, (, %s2) +; PIC-NEXT: lea %s0, 31(, %s0) +; PIC-NEXT: and %s2, -32, %s0 +; PIC-NEXT: lea %s0, 256(, %s17) +; PIC-NEXT: st1b %s1, (, %s2) +; PIC-NEXT: or %s11, 0, %s9 +; PIC-NEXT: ld %s17, 40(, %s11) +; PIC-NEXT: ld %s16, 32(, %s11) +; PIC-NEXT: ld %s15, 24(, %s11) +; PIC-NEXT: ld %s10, 8(, %s11) +; PIC-NEXT: ld %s9, (, %s11) +; PIC-NEXT: b.l.t (, %s10) + %3 = alloca [32 x i8], align 32 + %4 = getelementptr inbounds [32 x i8], [32 x i8]* %3, i64 0, i64 0 + call void @llvm.lifetime.start.p0i8(i64 32, i8* nonnull %4) + %5 = sext i32 %0 to i64 + %6 = alloca i8, i64 %5, align 32 + %7 = load i8, i8* %1, align 1 + store volatile i8 %7, i8* %6, align 32 + call void @llvm.lifetime.end.p0i8(i64 32, i8* nonnull %4) + ret i8* %4 +} diff --git a/llvm/test/CodeGen/VE/Scalar/stackframe_size.ll b/llvm/test/CodeGen/VE/Scalar/stackframe_size.ll new file mode 100644 index 0000000000000..2443023322d14 --- /dev/null +++ b/llvm/test/CodeGen/VE/Scalar/stackframe_size.ll @@ -0,0 +1,289 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=ve | FileCheck %s + +;;; Check stack frame allocation especially about the new SP calculation +;;; using multiple sizes as a test of emitSPAdjustment(). + +; Function Attrs: norecurse nounwind readnone +define signext i32 @test_frame0(i32 signext %0) { +; CHECK-LABEL: test_frame0: +; CHECK: # %bb.0: +; CHECK-NEXT: adds.w.sx %s0, 3, %s0 +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: b.l.t (, %s10) + %2 = add nsw i32 %0, 3 + ret i32 %2 +} + +; Function Attrs: nounwind +define i8* @test_frame8(i8* %0) { +; CHECK-LABEL: test_frame8: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -192 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB1_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 184(, %s11) +; CHECK-NEXT: st1b %s1, 184(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) + %2 = alloca [8 x i8], align 1 + %3 = getelementptr inbounds [8 x i8], [8 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} + +; Function Attrs: nounwind +define i8* @test_frame16(i8* %0) { +; CHECK-LABEL: test_frame16: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -192 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB2_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 176(, %s11) +; CHECK-NEXT: st1b %s1, 176(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) + %2 = alloca [16 x i8], align 1 + %3 = getelementptr inbounds [16 x i8], [16 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} + +; Function Attrs: nounwind +define i8* @test_frame32(i8* %0) { +; CHECK-LABEL: test_frame32: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -208 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB3_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 176(, %s11) +; CHECK-NEXT: st1b %s1, 176(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) + %2 = alloca [32 x i8], align 1 + %3 = getelementptr inbounds [32 x i8], [32 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} + +; Function Attrs: nounwind +define i8* @test_frame64(i8* %0) { +; CHECK-LABEL: test_frame64: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -240 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB4_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB4_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 176(, %s11) +; CHECK-NEXT: st1b %s1, 176(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) + %2 = alloca [64 x i8], align 1 + %3 = getelementptr inbounds [64 x i8], [64 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} + +; Function Attrs: nounwind +define i8* @test_frame128(i8* %0) { +; CHECK-LABEL: test_frame128: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -304 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB5_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 176(, %s11) +; CHECK-NEXT: st1b %s1, 176(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) + %2 = alloca [128 x i8], align 1 + %3 = getelementptr inbounds [128 x i8], [128 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} + +; Function Attrs: nounwind +define i8* @test_frame65536(i8* %0) { +; CHECK-LABEL: test_frame65536: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -65712 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -1(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB6_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB6_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 176(, %s11) +; CHECK-NEXT: st1b %s1, 176(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) + %2 = alloca [65536 x i8], align 1 + %3 = getelementptr inbounds [65536 x i8], [65536 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} + +; Function Attrs: nounwind +define i8* @test_frame4294967296(i8* %0) { +; CHECK-LABEL: test_frame4294967296: +; CHECK: # %bb.0: +; CHECK-NEXT: st %s9, (, %s11) +; CHECK-NEXT: st %s10, 8(, %s11) +; CHECK-NEXT: st %s15, 24(, %s11) +; CHECK-NEXT: st %s16, 32(, %s11) +; CHECK-NEXT: or %s9, 0, %s11 +; CHECK-NEXT: lea %s13, -176 +; CHECK-NEXT: and %s13, %s13, (32)0 +; CHECK-NEXT: lea.sl %s11, -2(%s13, %s11) +; CHECK-NEXT: brge.l.t %s11, %s8, .LBB7_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld %s61, 24(, %s14) +; CHECK-NEXT: or %s62, 0, %s0 +; CHECK-NEXT: lea %s63, 315 +; CHECK-NEXT: shm.l %s63, (%s61) +; CHECK-NEXT: shm.l %s8, 8(%s61) +; CHECK-NEXT: shm.l %s11, 16(%s61) +; CHECK-NEXT: monc +; CHECK-NEXT: or %s0, 0, %s62 +; CHECK-NEXT: .LBB7_2: +; CHECK-NEXT: ld1b.zx %s1, (, %s0) +; CHECK-NEXT: lea %s0, 176(, %s11) +; CHECK-NEXT: st1b %s1, 176(, %s11) +; CHECK-NEXT: or %s11, 0, %s9 +; CHECK-NEXT: ld %s16, 32(, %s11) +; CHECK-NEXT: ld %s15, 24(, %s11) +; CHECK-NEXT: ld %s10, 8(, %s11) +; CHECK-NEXT: ld %s9, (, %s11) +; CHECK-NEXT: b.l.t (, %s10) + %2 = alloca [4294967296 x i8], align 1 + %3 = getelementptr inbounds [4294967296 x i8], [4294967296 x i8]* %2, i64 0, i64 0 + %4 = load i8, i8* %0, align 1 + store i8 %4, i8* %3, align 1 + ret i8* %3 +} diff --git a/llvm/test/CodeGen/VE/Vector/vec_add.ll b/llvm/test/CodeGen/VE/Vector/vec_add.ll new file mode 100644 index 0000000000000..74421332daabf --- /dev/null +++ b/llvm/test/CodeGen/VE/Vector/vec_add.ll @@ -0,0 +1,132 @@ +; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s + +; <256 x i32> + +; Function Attrs: nounwind +define fastcc <256 x i32> @add_vv_v256i32(<256 x i32> %x, <256 x i32> %y) { +; CHECK-LABEL: add_vv_v256i32: +; CHECK: # %bb.0: +; CHECK-NEXT: lea %s0, 256 +; CHECK-NEXT: lvl %s0 +; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1 +; CHECK-NEXT: b.l.t (, %s10) + %z = add <256 x i32> %x, %y + ret <256 x i32> %z +} + +; Function Attrs: nounwind +define fastcc <256 x i32> @add_sv_v256i32(i32 %x, <256 x i32> %y) { +; CHECK-LABEL: add_sv_v256i32: +; CHECK: # %bb.0: +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: lea %s1, 256 +; CHECK-NEXT: lvl %s1 +; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0 +; CHECK-NEXT: b.l.t (, %s10) + %xins = insertelement <256 x i32> undef, i32 %x, i32 0 + %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer + %z = add <256 x i32> %vx, %y + ret <256 x i32> %z +} + +; Function Attrs: nounwind +define fastcc <256 x i32> @add_vs_v256i32(<256 x i32> %x, i32 %y) { +; CHECK-LABEL: add_vs_v256i32: +; CHECK: # %bb.0: +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: lea %s1, 256 +; CHECK-NEXT: lvl %s1 +; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0 +; CHECK-NEXT: b.l.t (, %s10) + %yins = insertelement <256 x i32> undef, i32 %y, i32 0 + %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer + %z = add <256 x i32> %x, %vy + ret <256 x i32> %z +} + + + +; <256 x i64> + +; Function Attrs: nounwind +define fastcc <256 x i64> @add_vv_v256i64(<256 x i64> %x, <256 x i64> %y) { +; CHECK-LABEL: add_vv_v256i64: +; CHECK: # %bb.0: +; CHECK-NEXT: lea %s0, 256 +; CHECK-NEXT: lvl %s0 +; CHECK-NEXT: vadds.l %v0, %v0, %v1 +; CHECK-NEXT: b.l.t (, %s10) + %z = add <256 x i64> %x, %y + ret <256 x i64> %z +} + +; Function Attrs: nounwind +define fastcc <256 x i64> @add_sv_v256i64(i64 %x, <256 x i64> %y) { +; CHECK-LABEL: add_sv_v256i64: +; CHECK: # %bb.0: +; CHECK-NEXT: lea %s1, 256 +; CHECK-NEXT: lvl %s1 +; CHECK-NEXT: vadds.l %v0, %s0, %v0 +; CHECK-NEXT: b.l.t (, %s10) + %xins = insertelement <256 x i64> undef, i64 %x, i32 0 + %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer + %z = add <256 x i64> %vx, %y + ret <256 x i64> %z +} + +; Function Attrs: nounwind +define fastcc <256 x i64> @add_vs_v256i64(<256 x i64> %x, i64 %y) { +; CHECK-LABEL: add_vs_v256i64: +; CHECK: # %bb.0: +; CHECK-NEXT: lea %s1, 256 +; CHECK-NEXT: lvl %s1 +; CHECK-NEXT: vadds.l %v0, %s0, %v0 +; CHECK-NEXT: b.l.t (, %s10) + %yins = insertelement <256 x i64> undef, i64 %y, i32 0 + %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer + %z = add <256 x i64> %x, %vy + ret <256 x i64> %z +} + +; <128 x i64> +; We expect this to be widened. + +; Function Attrs: nounwind +define fastcc <128 x i64> @add_vv_v128i64(<128 x i64> %x, <128 x i64> %y) { +; CHECK-LABEL: add_vv_v128i64: +; CHECK: # %bb.0: +; CHECK-NEXT: lea %s0, 256 +; CHECK-NEXT: lvl %s0 +; CHECK-NEXT: vadds.l %v0, %v0, %v1 +; CHECK-NEXT: b.l.t (, %s10) + %z = add <128 x i64> %x, %y + ret <128 x i64> %z +} + +; <256 x i16> +; We expect promotion. + +; Function Attrs: nounwind +define fastcc <256 x i16> @add_vv_v256i16(<256 x i16> %x, <256 x i16> %y) { +; CHECK-LABEL: add_vv_v256i16: +; CHECK: # %bb.0: +; CHECK-NEXT: lea %s0, 256 +; CHECK-NEXT: lvl %s0 +; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1 +; CHECK-NEXT: b.l.t (, %s10) + %z = add <256 x i16> %x, %y + ret <256 x i16> %z +} + +; <128 x i16> +; We expect this to be scalarized (for now). + +; Function Attrs: nounwind +define fastcc <128 x i16> @add_vv_v128i16(<128 x i16> %x, <128 x i16> %y) { +; CHECK-LABEL: add_vv_v128i16: +; CHECK: # %bb.0: +; CHECK-NOT: vadd + %z = add <128 x i16> %x, %y + ret <128 x i16> %z +} + diff --git a/llvm/test/CodeGen/WebAssembly/add-prototypes.ll b/llvm/test/CodeGen/WebAssembly/add-prototypes.ll index 84d7657e9830f..8730f2ab767ed 100644 --- a/llvm/test/CodeGen/WebAssembly/add-prototypes.ll +++ b/llvm/test/CodeGen/WebAssembly/add-prototypes.ll @@ -58,12 +58,12 @@ define void @as_paramater() { ; Check if a sret parameter works in a no-prototype function. ; CHECK-LABEL: @sret_param -; CHECK: call void @make_struct_foo(%struct.foo* sret %foo) +; CHECK: call void @make_struct_foo(%struct.foo* sret(%struct.foo) %foo) %struct.foo = type { i32, i32 } -declare void @make_struct_foo(%struct.foo* sret, ...) #1 +declare void @make_struct_foo(%struct.foo* sret(%struct.foo), ...) #1 define void @sret_param() { %foo = alloca %struct.foo, align 4 - call void bitcast (void (%struct.foo*, ...)* @make_struct_foo to void (%struct.foo*)*)(%struct.foo* sret %foo) + call void bitcast (void (%struct.foo*, ...)* @make_struct_foo to void (%struct.foo*)*)(%struct.foo* sret(%struct.foo) %foo) ret void } diff --git a/llvm/test/CodeGen/WebAssembly/byval.ll b/llvm/test/CodeGen/WebAssembly/byval.ll index 821f8a36d4eb7..b3b6884fbd0bb 100644 --- a/llvm/test/CodeGen/WebAssembly/byval.ll +++ b/llvm/test/CodeGen/WebAssembly/byval.ll @@ -11,11 +11,11 @@ target triple = "wasm32-unknown-unknown" %EmptyStruct = type { } declare void @ext_func(%SmallStruct*) -declare void @ext_func_empty(%EmptyStruct* byval) -declare void @ext_byval_func(%SmallStruct* byval) -declare void @ext_byval_func_align8(%SmallStruct* byval align 8) -declare void @ext_byval_func_alignedstruct(%AlignedStruct* byval) -declare void @ext_byval_func_empty(%EmptyStruct* byval) +declare void @ext_func_empty(%EmptyStruct* byval(%EmptyStruct)) +declare void @ext_byval_func(%SmallStruct* byval(%SmallStruct)) +declare void @ext_byval_func_align8(%SmallStruct* byval(%SmallStruct) align 8) +declare void @ext_byval_func_alignedstruct(%AlignedStruct* byval(%AlignedStruct)) +declare void @ext_byval_func_empty(%EmptyStruct* byval(%EmptyStruct)) ; CHECK-LABEL: byval_arg define void @byval_arg(%SmallStruct* %ptr) { @@ -34,7 +34,7 @@ define void @byval_arg(%SmallStruct* %ptr) { ; CHECK-NEXT: i32.const $push[[L5:.+]]=, 12{{$}} ; CHECK-NEXT: i32.add $push[[ARG:.+]]=, $[[SP]], $pop[[L5]]{{$}} ; CHECK-NEXT: call ext_byval_func, $pop[[ARG]]{{$}} - call void @ext_byval_func(%SmallStruct* byval %ptr) + call void @ext_byval_func(%SmallStruct* byval(%SmallStruct) %ptr) ; Restore the stack ; CHECK-NEXT: i32.const $push[[L6:.+]]=, 16 ; CHECK-NEXT: i32.add $push[[L8:.+]]=, $[[SP]], $pop[[L6]] @@ -58,7 +58,7 @@ define void @byval_arg_align8(%SmallStruct* %ptr) { ; CHECK-NEXT: i32.const $push[[L5:.+]]=, 8{{$}} ; CHECK-NEXT: i32.add $push[[ARG:.+]]=, $[[SP]], $pop[[L5]]{{$}} ; CHECK-NEXT: call ext_byval_func_align8, $pop[[ARG]]{{$}} - call void @ext_byval_func_align8(%SmallStruct* byval align 8 %ptr) + call void @ext_byval_func_align8(%SmallStruct* byval(%SmallStruct) align 8 %ptr) ret void } @@ -76,12 +76,12 @@ define void @byval_arg_double(%AlignedStruct* %ptr) { ; CHECK-NEXT: i64.store 0($[[SP]]), $pop[[L4]] ; Pass a pointer to the stack slot to the function ; CHECK-NEXT: call ext_byval_func_alignedstruct, $[[SP]] - tail call void @ext_byval_func_alignedstruct(%AlignedStruct* byval %ptr) + tail call void @ext_byval_func_alignedstruct(%AlignedStruct* byval(%AlignedStruct) %ptr) ret void } ; CHECK-LABEL: byval_param -define void @byval_param(%SmallStruct* byval align 32 %ptr) { +define void @byval_param(%SmallStruct* byval(%SmallStruct) align 32 %ptr) { ; CHECK: .functype byval_param (i32) -> () ; %ptr is just a pointer to a struct, so pass it directly through ; CHECK: call ext_func, $0 @@ -93,12 +93,12 @@ define void @byval_param(%SmallStruct* byval align 32 %ptr) { define void @byval_empty_caller(%EmptyStruct* %ptr) { ; CHECK: .functype byval_empty_caller (i32) -> () ; CHECK: call ext_byval_func_empty, $0 - call void @ext_byval_func_empty(%EmptyStruct* byval %ptr) + call void @ext_byval_func_empty(%EmptyStruct* byval(%EmptyStruct) %ptr) ret void } ; CHECK-LABEL: byval_empty_callee -define void @byval_empty_callee(%EmptyStruct* byval %ptr) { +define void @byval_empty_callee(%EmptyStruct* byval(%EmptyStruct) %ptr) { ; CHECK: .functype byval_empty_callee (i32) -> () ; CHECK: call ext_func_empty, $0 call void @ext_func_empty(%EmptyStruct* %ptr) @@ -117,8 +117,8 @@ define void @byval_empty_callee(%EmptyStruct* byval %ptr) { ; CHECK-NEXT: local.tee $push[[L9:.+]]=, $[[SP:.+]]=, $pop[[L11]]{{$}} ; CHECK-NEXT: call big_byval_callee, %big = type [131072 x i8] -declare void @big_byval_callee(%big* byval align 1) -define void @big_byval(%big* byval align 1 %x) { - call void @big_byval_callee(%big* byval align 1 %x) +declare void @big_byval_callee(%big* byval(%big) align 1) +define void @big_byval(%big* byval(%big) align 1 %x) { + call void @big_byval_callee(%big* byval(%big) align 1 %x) ret void } diff --git a/llvm/test/CodeGen/WebAssembly/indirect-import.ll b/llvm/test/CodeGen/WebAssembly/indirect-import.ll index 2c7f17e48d07a..c0f52e95c48ae 100644 --- a/llvm/test/CodeGen/WebAssembly/indirect-import.ll +++ b/llvm/test/CodeGen/WebAssembly/indirect-import.ll @@ -60,9 +60,9 @@ declare void @extern_v() #1 declare i32 @extern_ijidf(i64, i32, double, float) #1 -declare void @extern_struct(%struct.big* byval align 8) #1 +declare void @extern_struct(%struct.big* byval(%struct.big) align 8) #1 -declare void @extern_sret(%struct.big* sret) #1 +declare void @extern_sret(%struct.big* sret(%struct.big)) #1 declare i128 @extern_i128ret(i64) #1 diff --git a/llvm/test/CodeGen/WebAssembly/tailcall.ll b/llvm/test/CodeGen/WebAssembly/tailcall.ll index 4272c0b01a211..149105b01b891 100644 --- a/llvm/test/CodeGen/WebAssembly/tailcall.ll +++ b/llvm/test/CodeGen/WebAssembly/tailcall.ll @@ -166,9 +166,9 @@ define float @mismatched_indirect_f32(%fn %f, i32 %x, i32 %y) { ; CHECK-LABEL: mismatched_byval: ; CHECK: i32.store ; CHECK: return_call quux, $pop{{[0-9]+}}{{$}} -declare i32 @quux(i32* byval) +declare i32 @quux(i32* byval(i32)) define i32 @mismatched_byval(i32* %x) { - %v = tail call i32 @quux(i32* byval %x) + %v = tail call i32 @quux(i32* byval(i32) %x) ret i32 %v } diff --git a/llvm/test/CodeGen/X86/2006-11-12-CSRetCC.ll b/llvm/test/CodeGen/X86/2006-11-12-CSRetCC.ll index 98d627b9ffe7f..4d0eefbd5dd62 100644 --- a/llvm/test/CodeGen/X86/2006-11-12-CSRetCC.ll +++ b/llvm/test/CodeGen/X86/2006-11-12-CSRetCC.ll @@ -44,7 +44,7 @@ entry: %tmp9 = bitcast { double, double }* %tmp to { i64, i64 }* ; <{ i64, i64 }*> [#uses=1] %tmp10 = getelementptr { i64, i64 }, { i64, i64 }* %tmp9, i64 0, i32 1 ; [#uses=1] %tmp11 = load i64, i64* %tmp10 ; [#uses=1] - call void @cexp( { double, double }* sret %tmp2, i64 %tmp.upgrd.5, i64 %tmp11 ) + call void @cexp( { double, double }* sret({ double, double }) %tmp2, i64 %tmp.upgrd.5, i64 %tmp11 ) %tmp12 = getelementptr { double, double }, { double, double }* %z, i64 0, i32 0 ; [#uses=1] %tmp13 = getelementptr { double, double }, { double, double }* %tmp2, i64 0, i32 0 ; [#uses=1] %tmp14 = load double, double* %tmp13 ; [#uses=1] @@ -65,7 +65,7 @@ finish: ret i32 %retval.upgrd.8 } -declare void @cexp({ double, double }* sret , i64, i64) +declare void @cexp({ double, double }* sret({ double, double }), i64, i64) declare i32 @printf(i8*, ...) diff --git a/llvm/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll b/llvm/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll index ba80086a15101..050c12c9c0a5d 100644 --- a/llvm/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll +++ b/llvm/test/CodeGen/X86/2008-02-06-LoadFoldingBug.ll @@ -1,11 +1,11 @@ ; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s ; CHECK: xorps {{.*}}{{LCPI0_0|__xmm@}} -define void @casin({ double, double }* sret %agg.result, double %z.0, double %z.1) nounwind { +define void @casin({ double, double }* sret({ double, double }) %agg.result, double %z.0, double %z.1) nounwind { entry: %memtmp = alloca { double, double }, align 8 ; <{ double, double }*> [#uses=3] %tmp4 = fsub double -0.000000e+00, %z.1 ; [#uses=1] - call void @casinh( { double, double }* sret %memtmp, double %tmp4, double %z.0 ) nounwind + call void @casinh( { double, double }* sret({ double, double }) %memtmp, double %tmp4, double %z.0 ) nounwind %tmp19 = getelementptr { double, double }, { double, double }* %memtmp, i32 0, i32 0 ; [#uses=1] %tmp20 = load double, double* %tmp19, align 8 ; [#uses=1] %tmp22 = getelementptr { double, double }, { double, double }* %memtmp, i32 0, i32 1 ; [#uses=1] @@ -18,4 +18,4 @@ entry: ret void } -declare void @casinh({ double, double }* sret , double, double) nounwind +declare void @casinh({ double, double }* sret({ double, double }) , double, double) nounwind diff --git a/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll b/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll index 65240d5aea71b..5454d7ef1bb4c 100644 --- a/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll +++ b/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll @@ -14,7 +14,7 @@ @.str33 = external constant [29 x i32] ; <[29 x i32]*> [#uses=1] @.str89 = external constant [5 x i32] ; <[5 x i32]*> [#uses=1] -define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(%struct.wxString* noalias sret %agg.result, %struct.wxDateTime* %this, i32* %format, %"struct.wxDateTime::TimeZone"* %tz, i1 %foo) personality i32 (...)* @__gxx_personality_v0 { +define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(%struct.wxString* noalias sret(%struct.wxString) %agg.result, %struct.wxDateTime* %this, i32* %format, %"struct.wxDateTime::TimeZone"* %tz, i1 %foo) personality i32 (...)* @__gxx_personality_v0 { ; CHECK-LABEL: _ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: pushl %ebp @@ -291,13 +291,13 @@ bb448.i8694: ; preds = %bb440.i8663, %bb278.i8617 invcont5814: ; preds = %bb448.i8694, %bb265.i8606 %tmp812.0.0 = phi i16 [ %tmp477478.i8670, %bb448.i8694 ], [ %tmp273274.i8595, %bb265.i8606 ] ; [#uses=1] %tmp58165817 = zext i16 %tmp812.0.0 to i32 ; [#uses=1] - invoke void (%struct.wxString*, i32*, ...) @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret null, i32* null, i32 %tmp58165817 ) + invoke void (%struct.wxString*, i32*, ...) @_ZN8wxString6FormatEPKwz(%struct.wxString* noalias sret(%struct.wxString) null, i32* null, i32 %tmp58165817 ) to label %invcont5831 unwind label %lpad invcont5831: ; preds = %invcont5814 - %tmp5862 = invoke zeroext i8 @_ZN12wxStringBase10ConcatSelfEmPKwm( %struct.wxStringBase* null, i32 0, i32* null, i32 0 ) + %tmp5862 = invoke zeroext i8 @_ZN12wxStringBase10ConcatSelfEmPKwm(%struct.wxStringBase* null, i32 0, i32* null, i32 0 ) to label %bb7834 unwind label %lpad8185 ; [#uses=0] bb5968: ; preds = %bb3314 - invoke void (%struct.wxString*, i32*, ...) @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret null, i32* null, i32 0 ) + invoke void (%struct.wxString*, i32*, ...) @_ZN8wxString6FormatEPKwz(%struct.wxString* noalias sret(%struct.wxString) null, i32* null, i32 0 ) to label %invcont5981 unwind label %lpad invcont5981: ; preds = %bb5968 ret void @@ -346,6 +346,6 @@ declare %struct.wxStringBase* @_ZN12wxStringBase6appendEmw(%struct.wxStringBase* declare %struct.wxStringBase* @_ZN12wxStringBaseaSEPKw(%struct.wxStringBase*, i32*) -declare void @_ZN8wxString6FormatEPKwz(%struct.wxString* noalias sret , i32*, ...) +declare void @_ZN8wxString6FormatEPKwz(%struct.wxString* noalias sret(%struct.wxString) , i32*, ...) declare i32 @__gxx_personality_v0(...) diff --git a/llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll b/llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll index fb6baa20077f6..a450e88b8f75d 100644 --- a/llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll +++ b/llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll @@ -5,7 +5,7 @@ %struct.S63 = type { [63 x i8] } @g1s63 = external global %struct.S63 ; <%struct.S63*> [#uses=1] -declare void @test63(%struct.S63* byval align 4 ) nounwind +declare void @test63(%struct.S63* byval(%struct.S63) align 4 ) nounwind define void @testit63_entry_2E_ce() nounwind { ; CHECK-LABEL: testit63_entry_2E_ce: @@ -26,6 +26,6 @@ define void @testit63_entry_2E_ce() nounwind { ; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %edi ; CHECK-NEXT: retl - tail call void @test63( %struct.S63* byval align 4 @g1s63 ) nounwind + tail call void @test63(%struct.S63* byval(%struct.S63) align 4 @g1s63) nounwind ret void } diff --git a/llvm/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll b/llvm/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll index e8dd814b21673..b2c3f582b75c0 100644 --- a/llvm/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll +++ b/llvm/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll @@ -2,7 +2,7 @@ declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone -define void @__mindd16(<16 x double>* sret %vec.result, <16 x double> %x, double %y) nounwind { +define void @__mindd16(<16 x double>* sret(<16 x double>) %vec.result, <16 x double> %x, double %y) nounwind { entry: %tmp3.i = shufflevector <16 x double> zeroinitializer, <16 x double> undef, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 > ; <<8 x double>> [#uses=1] %tmp10.i.i = shufflevector <8 x double> %tmp3.i, <8 x double> undef, <4 x i32> < i32 4, i32 5, i32 6, i32 7 > ; <<4 x double>> [#uses=1] diff --git a/llvm/test/CodeGen/X86/2009-02-12-SpillerBug.ll b/llvm/test/CodeGen/X86/2009-02-12-SpillerBug.ll index acf2f6d65122d..2a787d95c0b13 100644 --- a/llvm/test/CodeGen/X86/2009-02-12-SpillerBug.ll +++ b/llvm/test/CodeGen/X86/2009-02-12-SpillerBug.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=i386-apple-darwin8 ; PR3561 -define hidden void @__mulxc3({ x86_fp80, x86_fp80 }* noalias nocapture sret %agg.result, x86_fp80 %a, x86_fp80 %b, x86_fp80 %c, x86_fp80 %d) nounwind { +define hidden void @__mulxc3({ x86_fp80, x86_fp80 }* noalias nocapture sret({ x86_fp80, x86_fp80 }) %agg.result, x86_fp80 %a, x86_fp80 %b, x86_fp80 %c, x86_fp80 %d) nounwind { entry: %0 = fmul x86_fp80 %b, %d ; [#uses=1] %1 = fsub x86_fp80 0xK00000000000000000000, %0 ; [#uses=1] diff --git a/llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll b/llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll index 3f4af707ff820..b400a8987cada 100644 --- a/llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll +++ b/llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll @@ -70,7 +70,7 @@ entry: store i8 %5, i8* %7, align 1 %8 = getelementptr %struct.X, %struct.X* %xxx, i32 0, i32 0 ; [#uses=1] store i8 15, i8* %8, align 1 - %9 = call i32 (...) bitcast (i32 (%struct.X*, %struct.X*)* @f to i32 (...)*)(%struct.X* byval align 4 %xxx, %struct.X* byval align 4 %xxx) nounwind ; [#uses=1] + %9 = call i32 (...) bitcast (i32 (%struct.X*, %struct.X*)* @f to i32 (...)*)(%struct.X* byval(%struct.X) align 4 %xxx, %struct.X* byval(%struct.X) align 4 %xxx) nounwind ; [#uses=1] store i32 %9, i32* %0, align 4 %10 = load i32, i32* %0, align 4 ; [#uses=1] store i32 %10, i32* %retval, align 4 @@ -81,4 +81,4 @@ return: ; preds = %entry ret i32 %retval1 } -declare i32 @f(%struct.X* byval align 4, %struct.X* byval align 4) nounwind ssp +declare i32 @f(%struct.X* byval(%struct.X) align 4, %struct.X* byval(%struct.X) align 4) nounwind ssp diff --git a/llvm/test/CodeGen/X86/2009-11-13-VirtRegRewriterBug.ll b/llvm/test/CodeGen/X86/2009-11-13-VirtRegRewriterBug.ll index 3608e09a22b84..f7efd79a5219f 100644 --- a/llvm/test/CodeGen/X86/2009-11-13-VirtRegRewriterBug.ll +++ b/llvm/test/CodeGen/X86/2009-11-13-VirtRegRewriterBug.ll @@ -3,7 +3,7 @@ %struct.JVTLib_100487 = type <{ i8 }> -define i32 @_Z13JVTLib_10335613JVTLib_10266513JVTLib_100579S_S_S_jPhj(i16* nocapture %ResidualX_Array.0, %struct.JVTLib_100487* nocapture byval align 4 %xqp, i16* nocapture %ResidualL_Array.0, i16* %ResidualDCZ_Array.0, i16* nocapture %ResidualACZ_FOArray.0, i32 %useFRextDequant, i8* nocapture %JVTLib_103357, i32 %use_field_scan) ssp { +define i32 @_Z13JVTLib_10335613JVTLib_10266513JVTLib_100579S_S_S_jPhj(i16* nocapture %ResidualX_Array.0, %struct.JVTLib_100487* nocapture byval(%struct.JVTLib_100487) align 4 %xqp, i16* nocapture %ResidualL_Array.0, i16* %ResidualDCZ_Array.0, i16* nocapture %ResidualACZ_FOArray.0, i32 %useFRextDequant, i8* nocapture %JVTLib_103357, i32 %use_field_scan) ssp { bb.nph: %0 = shl i32 undef, 1 ; [#uses=2] %mask133.masked.masked.masked.masked.masked.masked = or i640 undef, undef ; [#uses=1] diff --git a/llvm/test/CodeGen/X86/2010-01-18-DbgValue.ll b/llvm/test/CodeGen/X86/2010-01-18-DbgValue.ll index e95a443a1cc5d..01c60d4ee3946 100644 --- a/llvm/test/CodeGen/X86/2010-01-18-DbgValue.ll +++ b/llvm/test/CodeGen/X86/2010-01-18-DbgValue.ll @@ -11,7 +11,7 @@ %struct.Pt = type { double, double } %struct.Rect = type { %struct.Pt, %struct.Pt } -define double @foo(%struct.Rect* byval %my_r0) nounwind ssp !dbg !1 { +define double @foo(%struct.Rect* byval(%struct.Rect) %my_r0) nounwind ssp !dbg !1 { entry: %retval = alloca double ; [#uses=2] %0 = alloca double ; [#uses=2] diff --git a/llvm/test/CodeGen/X86/2010-04-21-CoalescerBug.ll b/llvm/test/CodeGen/X86/2010-04-21-CoalescerBug.ll index 46dedb48ff1dc..6ec2fd962d5aa 100644 --- a/llvm/test/CodeGen/X86/2010-04-21-CoalescerBug.ll +++ b/llvm/test/CodeGen/X86/2010-04-21-CoalescerBug.ll @@ -5,7 +5,7 @@ %struct.CMTimeMapping = type { %struct.CMTimeRange, %struct.CMTimeRange } %struct.CMTimeRange = type { %struct.CMTime, %struct.CMTime } -define void @t(%struct.CMTimeMapping* noalias nocapture sret %agg.result) nounwind optsize ssp { +define void @t(%struct.CMTimeMapping* noalias nocapture sret(%struct.CMTimeMapping) %agg.result) nounwind optsize ssp { entry: %agg.result1 = bitcast %struct.CMTimeMapping* %agg.result to i8* ; [#uses=1] tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %agg.result1, i8* align 4 null, i64 96, i1 false) diff --git a/llvm/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll b/llvm/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll index 615a57274393a..b210eb0f3201d 100644 --- a/llvm/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll +++ b/llvm/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll @@ -14,7 +14,7 @@ target triple = "i386-apple-darwin10.0.0" ; CHECK: movl %[[reg]],{{.*}}(%ebp) ## 4-byte Spill ; CHECK: calll __Z6throwsv -define i8* @_Z4test1SiS_(%struct.S* byval %s1, i32 %n, %struct.S* byval %s2) ssp personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +define i8* @_Z4test1SiS_(%struct.S* byval(%struct.S) %s1, i32 %n, %struct.S* byval(%struct.S) %s2) ssp personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { entry: %retval = alloca i8*, align 4 ; [#uses=2] %n.addr = alloca i32, align 4 ; [#uses=1] diff --git a/llvm/test/CodeGen/X86/2011-03-30-CreateFixedObjCrash.ll b/llvm/test/CodeGen/X86/2011-03-30-CreateFixedObjCrash.ll index f829c05fc56ed..d1b4df68963b8 100644 --- a/llvm/test/CodeGen/X86/2011-03-30-CreateFixedObjCrash.ll +++ b/llvm/test/CodeGen/X86/2011-03-30-CreateFixedObjCrash.ll @@ -4,7 +4,7 @@ %struct.T0 = type {} -define void @fn4(%struct.T0* byval %arg0) nounwind ssp { +define void @fn4(%struct.T0* byval(%struct.T0) %arg0) nounwind ssp { entry: ret void } diff --git a/llvm/test/CodeGen/X86/2012-01-11-split-cv.ll b/llvm/test/CodeGen/X86/2012-01-11-split-cv.ll index c8424fa69aaf6..342c81e23f10a 100644 --- a/llvm/test/CodeGen/X86/2012-01-11-split-cv.ll +++ b/llvm/test/CodeGen/X86/2012-01-11-split-cv.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mattr=+avx -mtriple=i686-unknown-unknown | FileCheck %s -define void @add18i16(<18 x i16>* nocapture sret %ret, <18 x i16>* %bp) nounwind { +define void @add18i16(<18 x i16>* nocapture sret(<18 x i16>) %ret, <18 x i16>* %bp) nounwind { ; CHECK-LABEL: add18i16: ; CHECK: # %bb.0: ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll b/llvm/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll index 8083af34736d2..3f5548f919d1e 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll @@ -17,13 +17,13 @@ define void @test_x86_fp80_dump(x86_fp80* %ptr){ } ; Check that we fallback on byVal argument -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to translate instruction: call: ' call void @ScaleObjectOverwrite_3(%struct.PointListStruct* %index, %struct.PointListStruct* byval %index)' (in function: ScaleObjectOverwrite_2) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to translate instruction: call: ' call void @ScaleObjectOverwrite_3(%struct.PointListStruct* %index, %struct.PointListStruct* byval(%struct.PointListStruct) %index)' (in function: ScaleObjectOverwrite_2) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for ScaleObjectOverwrite_2 ; FALLBACK-WITH-REPORT-OUT-LABEL: ScaleObjectOverwrite_2: %struct.PointListStruct = type { i8*, i8* } -declare void @ScaleObjectOverwrite_3(%struct.PointListStruct* %index, %struct.PointListStruct* byval %index2) +declare void @ScaleObjectOverwrite_3(%struct.PointListStruct* %index, %struct.PointListStruct* byval(%struct.PointListStruct) %index2) define void @ScaleObjectOverwrite_2(%struct.PointListStruct* %index) { entry: - call void @ScaleObjectOverwrite_3(%struct.PointListStruct* %index, %struct.PointListStruct* byval %index) + call void @ScaleObjectOverwrite_3(%struct.PointListStruct* %index, %struct.PointListStruct* byval(%struct.PointListStruct) %index) ret void } diff --git a/llvm/test/CodeGen/X86/StackColoring-use-between-allocas.mir b/llvm/test/CodeGen/X86/StackColoring-use-between-allocas.mir index 9838aab184899..bf63e2b038c19 100644 --- a/llvm/test/CodeGen/X86/StackColoring-use-between-allocas.mir +++ b/llvm/test/CodeGen/X86/StackColoring-use-between-allocas.mir @@ -50,7 +50,7 @@ call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %6) #3 %7 = bitcast %"struct.e::f"* %tmp to i8* call void @llvm.lifetime.start.p0i8(i64 32, i8* nonnull %7) #3 - call void @_ZN1j1kEv(%"struct.e::f"* nonnull sret align 8 %tmp, %struct.j* nonnull %b) + call void @_ZN1j1kEv(%"struct.e::f"* nonnull sret(%"struct.e::f") align 8 %tmp, %struct.j* nonnull %b) call void @llvm.lifetime.end.p0i8(i64 32, i8* nonnull %7) #3 call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %6) #3 call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %0) #3 @@ -67,7 +67,7 @@ ; Function Attrs: argmemonly nounwind willreturn declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1 - declare void @_ZN1j1kEv(%"struct.e::f"* sret align 8, %struct.j*) local_unnamed_addr #2 + declare void @_ZN1j1kEv(%"struct.e::f"* sret(%"struct.e::f") align 8, %struct.j*) local_unnamed_addr #2 ; Function Attrs: nounwind declare void @llvm.stackprotector(i8*, i8**) #3 diff --git a/llvm/test/CodeGen/X86/abs.ll b/llvm/test/CodeGen/X86/abs.ll index 8e20b001cc3e8..0bbc785034a21 100644 --- a/llvm/test/CodeGen/X86/abs.ll +++ b/llvm/test/CodeGen/X86/abs.ll @@ -397,10 +397,9 @@ define <8 x i32> @test_v8i32(<8 x i32> %a) nounwind { define <8 x i16> @test_v8i16(<8 x i16> %a) nounwind { ; SSE-LABEL: test_v8i16: ; SSE: # %bb.0: -; SSE-NEXT: movdqa %xmm0, %xmm1 -; SSE-NEXT: psraw $15, %xmm1 -; SSE-NEXT: paddw %xmm1, %xmm0 -; SSE-NEXT: pxor %xmm1, %xmm0 +; SSE-NEXT: pxor %xmm1, %xmm1 +; SSE-NEXT: psubw %xmm0, %xmm1 +; SSE-NEXT: pmaxsw %xmm1, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: test_v8i16: @@ -475,9 +474,8 @@ define <16 x i8> @test_v16i8(<16 x i8> %a) nounwind { ; SSE-LABEL: test_v16i8: ; SSE: # %bb.0: ; SSE-NEXT: pxor %xmm1, %xmm1 -; SSE-NEXT: pcmpgtb %xmm0, %xmm1 -; SSE-NEXT: paddb %xmm1, %xmm0 -; SSE-NEXT: pxor %xmm1, %xmm0 +; SSE-NEXT: psubb %xmm0, %xmm1 +; SSE-NEXT: pminub %xmm1, %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: test_v16i8: diff --git a/llvm/test/CodeGen/X86/addcarry.ll b/llvm/test/CodeGen/X86/addcarry.ll index 9edcb9492a3d2..0db0d4ebd43c2 100644 --- a/llvm/test/CodeGen/X86/addcarry.ll +++ b/llvm/test/CodeGen/X86/addcarry.ll @@ -794,7 +794,7 @@ define i32 @add_U320_uaddo(%struct.U320* nocapture dereferenceable(40) %0, i64 % %struct.U192 = type { [3 x i64] } -define void @PR39464(%struct.U192* noalias nocapture sret %0, %struct.U192* nocapture readonly dereferenceable(24) %1, %struct.U192* nocapture readonly dereferenceable(24) %2) { +define void @PR39464(%struct.U192* noalias nocapture sret(%struct.U192) %0, %struct.U192* nocapture readonly dereferenceable(24) %1, %struct.U192* nocapture readonly dereferenceable(24) %2) { ; CHECK-LABEL: PR39464: ; CHECK: # %bb.0: ; CHECK-NEXT: movq %rdi, %rax @@ -873,7 +873,7 @@ define zeroext i1 @uaddo_U128_without_i128_or(i64 %0, i64 %1, i64 %2, i64 %3, %u %uint192 = type { i64, i64, i64 } -define void @add_U192_without_i128_or(%uint192* sret %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6) nounwind { +define void @add_U192_without_i128_or(%uint192* sret(%uint192) %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6) nounwind { ; CHECK-LABEL: add_U192_without_i128_or: ; CHECK: # %bb.0: ; CHECK-NEXT: movq %rdi, %rax @@ -909,7 +909,7 @@ define void @add_U192_without_i128_or(%uint192* sret %0, i64 %1, i64 %2, i64 %3, ; Classic unrolled 256-bit addition implementation using i64 as the word type. ; It starts by adding least significant words and propagates carry to additions of the higher words. -define void @add_U256_without_i128_or_by_i64_words(%uint256* sret %0, %uint256* %1, %uint256* %2) nounwind { +define void @add_U256_without_i128_or_by_i64_words(%uint256* sret(%uint256) %0, %uint256* %1, %uint256* %2) nounwind { ; CHECK-LABEL: add_U256_without_i128_or_by_i64_words: ; CHECK: # %bb.0: ; CHECK-NEXT: movq %rdi, %rax @@ -972,7 +972,7 @@ define void @add_U256_without_i128_or_by_i64_words(%uint256* sret %0, %uint256* ; The 256-bit addition implementation using two inlined uaddo procedures for U128 type { i64, i64 }. ; This is similar to how LLVM legalize types in CodeGen. -define void @add_U256_without_i128_or_recursive(%uint256* sret %0, %uint256* %1, %uint256* %2) nounwind { +define void @add_U256_without_i128_or_recursive(%uint256* sret(%uint256) %0, %uint256* %1, %uint256* %2) nounwind { ; CHECK-LABEL: add_U256_without_i128_or_recursive: ; CHECK: # %bb.0: ; CHECK-NEXT: movq %rdi, %rax diff --git a/llvm/test/CodeGen/X86/aligned-variadic.ll b/llvm/test/CodeGen/X86/aligned-variadic.ll index d8274443e3e39..bf119286c68c1 100644 --- a/llvm/test/CodeGen/X86/aligned-variadic.ll +++ b/llvm/test/CodeGen/X86/aligned-variadic.ll @@ -5,7 +5,7 @@ %struct.__va_list_tag = type { i32, i32, i8*, i8* } ; Function Attrs: nounwind uwtable -define void @bar(%struct.Baz* byval nocapture readnone align 8 %x, ...) { +define void @bar(%struct.Baz* byval(%struct.Baz) nocapture readnone align 8 %x, ...) { entry: %va = alloca [1 x %struct.__va_list_tag], align 16 %arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i64 0, i64 0 diff --git a/llvm/test/CodeGen/X86/arg-copy-elide.ll b/llvm/test/CodeGen/X86/arg-copy-elide.ll index 14db84fae449b..f8761bd0ac9b4 100644 --- a/llvm/test/CodeGen/X86/arg-copy-elide.ll +++ b/llvm/test/CodeGen/X86/arg-copy-elide.ll @@ -217,7 +217,7 @@ entry: ; CHECK: retl -define void @avoid_byval(i32* byval %x) { +define void @avoid_byval(i32* byval(i32) %x) { entry: %x.p.p = alloca i32* store i32* %x, i32** %x.p.p @@ -280,7 +280,7 @@ define void @escape_with_store(i32 %x) { ; This test case exposed issues with the use of TokenFactor. -define void @sret_and_elide(i32* sret %sret, i32 %v) { +define void @sret_and_elide(i32* sret(i32) %sret, i32 %v) { %v.p = alloca i32 store i32 %v, i32* %v.p call void @addrof_i32(i32* %v.p) diff --git a/llvm/test/CodeGen/X86/atom-fixup-lea2.ll b/llvm/test/CodeGen/X86/atom-fixup-lea2.ll index b8a0369a45f4e..9aa51dca4b81b 100644 --- a/llvm/test/CodeGen/X86/atom-fixup-lea2.ll +++ b/llvm/test/CodeGen/X86/atom-fixup-lea2.ll @@ -37,7 +37,7 @@ define i32 @test() { entry: %n = alloca %struct.node_t, align 4 - call void bitcast (void (%struct.node_t*, ...)* @getnode to void (%struct.node_t*)*)(%struct.node_t* sret %n) + call void bitcast (void (%struct.node_t*, ...)* @getnode to void (%struct.node_t*)*)(%struct.node_t* sret(%struct.node_t) %n) %array = getelementptr inbounds %struct.node_t, %struct.node_t* %n, i32 0, i32 4 %0 = load i32*, i32** %array, align 4 %cmp = icmp eq i32* %0, null @@ -82,4 +82,4 @@ if.end: ret i32 %sum.0 } -declare void @getnode(%struct.node_t* sret, ...) +declare void @getnode(%struct.node_t* sret(%struct.node_t), ...) diff --git a/llvm/test/CodeGen/X86/atomic-unordered.ll b/llvm/test/CodeGen/X86/atomic-unordered.ll index 7b255c7b6c1ae..ddd9038831d40 100644 --- a/llvm/test/CodeGen/X86/atomic-unordered.ll +++ b/llvm/test/CodeGen/X86/atomic-unordered.ll @@ -366,18 +366,17 @@ define void @store_i256(i256* %ptr, i256 %v) { ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: subq $40, %rsp ; CHECK-O0-NEXT: .cfi_def_cfa_offset 48 -; CHECK-O0-NEXT: movq %rcx, %rax -; CHECK-O0-NEXT: movq %rdx, (%rsp) # 8-byte Spill -; CHECK-O0-NEXT: movq %rsi, %r9 +; CHECK-O0-NEXT: movq %rdx, %rax +; CHECK-O0-NEXT: movq %rsi, (%rsp) # 8-byte Spill ; CHECK-O0-NEXT: movq %rdi, %rsi ; CHECK-O0-NEXT: movq (%rsp), %rdi # 8-byte Reload -; CHECK-O0-NEXT: xorl %ecx, %ecx ; CHECK-O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx -; CHECK-O0-NEXT: movq %r9, {{[0-9]+}}(%rsp) ; CHECK-O0-NEXT: movq %rdi, {{[0-9]+}}(%rsp) ; CHECK-O0-NEXT: movq %rax, {{[0-9]+}}(%rsp) +; CHECK-O0-NEXT: movq %rcx, {{[0-9]+}}(%rsp) ; CHECK-O0-NEXT: movq %r8, {{[0-9]+}}(%rsp) ; CHECK-O0-NEXT: movl $32, %edi +; CHECK-O0-NEXT: xorl %ecx, %ecx ; CHECK-O0-NEXT: callq __atomic_store ; CHECK-O0-NEXT: addq $40, %rsp ; CHECK-O0-NEXT: .cfi_def_cfa_offset 8 @@ -724,8 +723,8 @@ define i64 @load_fold_sdiv1(i64* %p) { ; CHECK-O0-LABEL: load_fold_sdiv1: ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: movq (%rdi), %rax -; CHECK-O0-NEXT: cqto ; CHECK-O0-NEXT: movl $15, %ecx +; CHECK-O0-NEXT: cqto ; CHECK-O0-NEXT: idivq %rcx ; CHECK-O0-NEXT: retq ; @@ -814,9 +813,9 @@ define i64 @load_fold_udiv1(i64* %p) { ; CHECK-O0-LABEL: load_fold_udiv1: ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: movq (%rdi), %rax -; CHECK-O0-NEXT: xorl %ecx, %ecx -; CHECK-O0-NEXT: movl %ecx, %edx ; CHECK-O0-NEXT: movl $15, %ecx +; CHECK-O0-NEXT: xorl %edx, %edx +; CHECK-O0-NEXT: # kill: def $rdx killed $edx ; CHECK-O0-NEXT: divq %rcx ; CHECK-O0-NEXT: retq ; @@ -908,8 +907,8 @@ define i64 @load_fold_srem1(i64* %p) { ; CHECK-O0-LABEL: load_fold_srem1: ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: movq (%rdi), %rax -; CHECK-O0-NEXT: cqto ; CHECK-O0-NEXT: movl $15, %ecx +; CHECK-O0-NEXT: cqto ; CHECK-O0-NEXT: idivq %rcx ; CHECK-O0-NEXT: movq %rdx, %rax ; CHECK-O0-NEXT: retq @@ -1007,9 +1006,9 @@ define i64 @load_fold_urem1(i64* %p) { ; CHECK-O0-LABEL: load_fold_urem1: ; CHECK-O0: # %bb.0: ; CHECK-O0-NEXT: movq (%rdi), %rax -; CHECK-O0-NEXT: xorl %ecx, %ecx -; CHECK-O0-NEXT: movl %ecx, %edx ; CHECK-O0-NEXT: movl $15, %ecx +; CHECK-O0-NEXT: xorl %edx, %edx +; CHECK-O0-NEXT: # kill: def $rdx killed $edx ; CHECK-O0-NEXT: divq %rcx ; CHECK-O0-NEXT: movq %rdx, %rax ; CHECK-O0-NEXT: retq diff --git a/llvm/test/CodeGen/X86/atomic64.ll b/llvm/test/CodeGen/X86/atomic64.ll index 452bcb254e0d5..c518e1130ef19 100644 --- a/llvm/test/CodeGen/X86/atomic64.ll +++ b/llvm/test/CodeGen/X86/atomic64.ll @@ -705,10 +705,10 @@ define void @atomic_fetch_cmpxchg64() nounwind { ; I486-NEXT: movl %esp, %ebp ; I486-NEXT: andl $-8, %esp ; I486-NEXT: subl $32, %esp -; I486-NEXT: leal sc64, %eax ; I486-NEXT: leal {{[0-9]+}}(%esp), %ecx ; I486-NEXT: movl $0, {{[0-9]+}}(%esp) ; I486-NEXT: movl $0, {{[0-9]+}}(%esp) +; I486-NEXT: leal sc64, %eax ; I486-NEXT: movl %esp, %eax ; I486-NEXT: movl %ecx, 4(%eax) ; I486-NEXT: movl $2, 20(%eax) @@ -786,10 +786,10 @@ define void @atomic_fetch_swapf64(double %x) nounwind { ; I486-NEXT: andl $-8, %esp ; I486-NEXT: subl $24, %esp ; I486-NEXT: fldl 8(%ebp) -; I486-NEXT: leal fsc64, %eax ; I486-NEXT: fstpl {{[0-9]+}}(%esp) ; I486-NEXT: movl {{[0-9]+}}(%esp), %ecx ; I486-NEXT: movl {{[0-9]+}}(%esp), %edx +; I486-NEXT: leal fsc64, %eax ; I486-NEXT: movl %esp, %eax ; I486-NEXT: movl %edx, 8(%eax) ; I486-NEXT: movl %ecx, 4(%eax) diff --git a/llvm/test/CodeGen/X86/avoid-sfb.ll b/llvm/test/CodeGen/X86/avoid-sfb.ll index 37f235288cc2a..5c914286a25c8 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb.ll +++ b/llvm/test/CodeGen/X86/avoid-sfb.ll @@ -724,7 +724,7 @@ if.end: ; preds = %if.then, %entry %struct.S6 = type { [4 x i32], i32, i32, i32, i32 } ; Function Attrs: nounwind uwtable -define void @test_stack(%struct.S6* noalias nocapture sret %agg.result, %struct.S6* byval nocapture readnone align 8 %s1, %struct.S6* byval nocapture align 8 %s2, i32 %x) local_unnamed_addr #0 { +define void @test_stack(%struct.S6* noalias nocapture sret(%struct.S6) %agg.result, %struct.S6* byval(%struct.S6) nocapture readnone align 8 %s1, %struct.S6* byval(%struct.S6) nocapture align 8 %s2, i32 %x) local_unnamed_addr #0 { ; CHECK-LABEL: test_stack: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: movq %rdi, %rax diff --git a/llvm/test/CodeGen/X86/avx512-intel-ocl.ll b/llvm/test/CodeGen/X86/avx512-intel-ocl.ll index d5305f27fa8f3..a7070015bcaee 100644 --- a/llvm/test/CodeGen/X86/avx512-intel-ocl.ll +++ b/llvm/test/CodeGen/X86/avx512-intel-ocl.ll @@ -423,8 +423,6 @@ define <16 x float> @testf16_inp_mask(<16 x float> %a, i16 %mask) { ; WIN64-KNL-NEXT: nop ; WIN64-KNL-NEXT: addq $40, %rsp ; WIN64-KNL-NEXT: retq -; WIN64-KNL-NEXT: .seh_handlerdata -; WIN64-KNL-NEXT: .text ; WIN64-KNL-NEXT: .seh_endproc ; ; WIN64-SKX-LABEL: testf16_inp_mask: @@ -439,8 +437,6 @@ define <16 x float> @testf16_inp_mask(<16 x float> %a, i16 %mask) { ; WIN64-SKX-NEXT: nop ; WIN64-SKX-NEXT: addq $40, %rsp ; WIN64-SKX-NEXT: retq -; WIN64-SKX-NEXT: .seh_handlerdata -; WIN64-SKX-NEXT: .text ; WIN64-SKX-NEXT: .seh_endproc ; ; X64-KNL-LABEL: testf16_inp_mask: diff --git a/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll b/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll index 897632fb10dcf..bbf495619dbd1 100644 --- a/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll +++ b/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll @@ -157,8 +157,6 @@ define i64 @caller_argv64i1() #0 { ; WIN64-NEXT: popq %r14 ; WIN64-NEXT: popq %r15 ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: caller_argv64i1: @@ -263,8 +261,6 @@ define <64 x i1> @caller_retv64i1() #0 { ; WIN64-NEXT: popq %rdi ; WIN64-NEXT: popq %rsi ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: caller_retv64i1: @@ -349,8 +345,6 @@ define x86_regcallcc i32 @test_argv32i1(<32 x i1> %x0, <32 x i1> %x1, <32 x i1> ; WIN64-NEXT: popq %r11 ; WIN64-NEXT: popq %rbp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_argv32i1: @@ -438,8 +432,6 @@ define i32 @caller_argv32i1() #0 { ; WIN64-NEXT: popq %rdi ; WIN64-NEXT: popq %rsi ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: caller_argv32i1: @@ -503,8 +495,6 @@ define i32 @caller_retv32i1() #0 { ; WIN64-NEXT: popq %rdi ; WIN64-NEXT: popq %rsi ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: caller_retv32i1: @@ -584,8 +574,6 @@ define x86_regcallcc i16 @test_argv16i1(<16 x i1> %x0, <16 x i1> %x1, <16 x i1> ; WIN64-NEXT: popq %r10 ; WIN64-NEXT: popq %r11 ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_argv16i1: @@ -672,8 +660,6 @@ define i16 @caller_argv16i1() #0 { ; WIN64-NEXT: popq %rdi ; WIN64-NEXT: popq %rsi ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: caller_argv16i1: @@ -741,8 +727,6 @@ define i16 @caller_retv16i1() #0 { ; WIN64-NEXT: popq %rdi ; WIN64-NEXT: popq %rsi ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: caller_retv16i1: @@ -824,8 +808,6 @@ define x86_regcallcc i8 @test_argv8i1(<8 x i1> %x0, <8 x i1> %x1, <8 x i1> %x2) ; WIN64-NEXT: popq %r10 ; WIN64-NEXT: popq %r11 ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_argv8i1: @@ -912,8 +894,6 @@ define i8 @caller_argv8i1() #0 { ; WIN64-NEXT: popq %rdi ; WIN64-NEXT: popq %rsi ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: caller_argv8i1: @@ -985,8 +965,6 @@ define <8 x i1> @caller_retv8i1() #0 { ; WIN64-NEXT: popq %rsi ; WIN64-NEXT: vzeroupper ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: caller_retv8i1: diff --git a/llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll b/llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll index e832e42fea188..1ab55e17ce05d 100644 --- a/llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll +++ b/llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll @@ -49,8 +49,6 @@ define x86_regcallcc i1 @test_CallargReti1(i1 %a) { ; WIN64-NEXT: incb %al ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargReti1: @@ -117,8 +115,6 @@ define x86_regcallcc i8 @test_CallargReti8(i8 %a) { ; WIN64-NEXT: incb %al ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargReti8: @@ -187,8 +183,6 @@ define x86_regcallcc i16 @test_CallargReti16(i16 %a) { ; WIN64-NEXT: # kill: def $ax killed $ax killed $eax ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargReti16: @@ -251,8 +245,6 @@ define x86_regcallcc i32 @test_CallargReti32(i32 %a) { ; WIN64-NEXT: incl %eax ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargReti32: @@ -318,8 +310,6 @@ define x86_regcallcc i64 @test_CallargReti64(i64 %a) { ; WIN64-NEXT: incq %rax ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargReti64: @@ -392,8 +382,6 @@ define x86_regcallcc float @test_CallargRetFloat(float %a) { ; WIN64-NEXT: addq $16, %rsp ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargRetFloat: @@ -474,8 +462,6 @@ define x86_regcallcc double @test_CallargRetDouble(double %a) { ; WIN64-NEXT: addq $16, %rsp ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargRetDouble: @@ -575,8 +561,6 @@ define x86_regcallcc x86_fp80 @test_CallargRetf80(x86_fp80 %a) { ; WIN64-NEXT: fadd %st, %st(0) ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargRetf80: @@ -616,8 +600,6 @@ define x86_regcallcc double @test_CallargParamf80(x86_fp80 %a) { ; WIN64-NEXT: vaddsd %xmm0, %xmm0, %xmm0 ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargParamf80: @@ -680,8 +662,6 @@ define x86_regcallcc [4 x i32]* @test_CallargRetPointer([4 x i32]* %a) { ; WIN64-NEXT: incl %eax ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargRetPointer: @@ -774,8 +754,6 @@ define x86_regcallcc <4 x i32> @test_CallargRet128Vector(<4 x i1> %x, <4 x i32> ; WIN64-NEXT: addq $32, %rsp ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargRet128Vector: @@ -866,8 +844,6 @@ define x86_regcallcc <8 x i32> @test_CallargRet256Vector(<8 x i1> %x, <8 x i32> ; WIN64-NEXT: addq $80, %rsp ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargRet256Vector: @@ -954,8 +930,6 @@ define x86_regcallcc <16 x i32> @test_CallargRet512Vector(<16 x i1> %x, <16 x i3 ; WIN64-NEXT: addq $176, %rsp ; WIN64-NEXT: popq %rsp ; WIN64-NEXT: retq -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc ; ; LINUXOSX64-LABEL: test_CallargRet512Vector: diff --git a/llvm/test/CodeGen/X86/avx512vl-arith.ll b/llvm/test/CodeGen/X86/avx512vl-arith.ll old mode 100755 new mode 100644 diff --git a/llvm/test/CodeGen/X86/break-false-dep.ll b/llvm/test/CodeGen/X86/break-false-dep.ll index e480ba1313752..9bc2b438caf09 100644 --- a/llvm/test/CodeGen/X86/break-false-dep.ll +++ b/llvm/test/CodeGen/X86/break-false-dep.ll @@ -519,8 +519,6 @@ define void @loopdep3() { ; SSE-WIN-NEXT: addq $160, %rsp ; SSE-WIN-NEXT: popq %rsi ; SSE-WIN-NEXT: retq -; SSE-WIN-NEXT: .seh_handlerdata -; SSE-WIN-NEXT: .text ; SSE-WIN-NEXT: .seh_endproc ; ; AVX-LABEL: loopdep3: @@ -597,8 +595,6 @@ define void @loopdep3() { ; AVX-NEXT: addq $160, %rsp ; AVX-NEXT: popq %rsi ; AVX-NEXT: retq -; AVX-NEXT: .seh_handlerdata -; AVX-NEXT: .text ; AVX-NEXT: .seh_endproc entry: br label %for.cond1.preheader @@ -716,8 +712,6 @@ define double @inlineasmdep(i64 %arg) { ; SSE-WIN-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Reload ; SSE-WIN-NEXT: addq $168, %rsp ; SSE-WIN-NEXT: retq -; SSE-WIN-NEXT: .seh_handlerdata -; SSE-WIN-NEXT: .text ; SSE-WIN-NEXT: .seh_endproc ; ; AVX-LABEL: inlineasmdep: @@ -775,8 +769,6 @@ define double @inlineasmdep(i64 %arg) { ; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Reload ; AVX-NEXT: addq $168, %rsp ; AVX-NEXT: retq -; AVX-NEXT: .seh_handlerdata -; AVX-NEXT: .text ; AVX-NEXT: .seh_endproc top: tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{dirflag},~{fpsr},~{flags}"() @@ -879,8 +871,6 @@ define double @truedeps(float %arg) { ; SSE-WIN-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Reload ; SSE-WIN-NEXT: addq $184, %rsp ; SSE-WIN-NEXT: retq -; SSE-WIN-NEXT: .seh_handlerdata -; SSE-WIN-NEXT: .text ; SSE-WIN-NEXT: .seh_endproc ; ; AVX-LABEL: truedeps: @@ -942,8 +932,6 @@ define double @truedeps(float %arg) { ; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Reload ; AVX-NEXT: addq $184, %rsp ; AVX-NEXT: retq -; AVX-NEXT: .seh_handlerdata -; AVX-NEXT: .text ; AVX-NEXT: .seh_endproc top: tail call void asm sideeffect "", "~{xmm6},~{dirflag},~{fpsr},~{flags}"() @@ -1043,8 +1031,6 @@ define double @clearence(i64 %arg) { ; SSE-WIN-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Reload ; SSE-WIN-NEXT: addq $168, %rsp ; SSE-WIN-NEXT: retq -; SSE-WIN-NEXT: .seh_handlerdata -; SSE-WIN-NEXT: .text ; SSE-WIN-NEXT: .seh_endproc ; ; AVX-LABEL: clearence: @@ -1104,8 +1090,6 @@ define double @clearence(i64 %arg) { ; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Reload ; AVX-NEXT: addq $168, %rsp ; AVX-NEXT: retq -; AVX-NEXT: .seh_handlerdata -; AVX-NEXT: .text ; AVX-NEXT: .seh_endproc top: tail call void asm sideeffect "", "~{xmm6},~{dirflag},~{fpsr},~{flags}"() @@ -1416,8 +1400,6 @@ define void @loopclearance2(double* nocapture %y, i64* %x, double %c1, double %c ; SSE-WIN-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Reload ; SSE-WIN-NEXT: addq $152, %rsp ; SSE-WIN-NEXT: retq -; SSE-WIN-NEXT: .seh_handlerdata -; SSE-WIN-NEXT: .text ; SSE-WIN-NEXT: .seh_endproc ; ; AVX1-LABEL: loopclearance2: @@ -1499,8 +1481,6 @@ define void @loopclearance2(double* nocapture %y, i64* %x, double %c1, double %c ; AVX1-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Reload ; AVX1-NEXT: addq $152, %rsp ; AVX1-NEXT: retq -; AVX1-NEXT: .seh_handlerdata -; AVX1-NEXT: .text ; AVX1-NEXT: .seh_endproc ; ; AVX512VL-LABEL: loopclearance2: @@ -1582,8 +1562,6 @@ define void @loopclearance2(double* nocapture %y, i64* %x, double %c1, double %c ; AVX512VL-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Reload ; AVX512VL-NEXT: addq $152, %rsp ; AVX512VL-NEXT: retq -; AVX512VL-NEXT: .seh_handlerdata -; AVX512VL-NEXT: .text ; AVX512VL-NEXT: .seh_endproc entry: tail call void asm sideeffect "", "~{xmm7},~{dirflag},~{fpsr},~{flags}"() diff --git a/llvm/test/CodeGen/X86/byval-align.ll b/llvm/test/CodeGen/X86/byval-align.ll index 8366ae38333fb..5f03dc83256ec 100644 --- a/llvm/test/CodeGen/X86/byval-align.ll +++ b/llvm/test/CodeGen/X86/byval-align.ll @@ -7,7 +7,7 @@ @.str3 = private constant [7 x i8] c"test.c\00", align 1 ; <[7 x i8]*> [#uses=1] @__PRETTY_FUNCTION__.2067 = internal constant [13 x i8] c"aligned_func\00" ; <[13 x i8]*> [#uses=1] -define void @aligned_func(%struct.S* byval align 64 %obj) nounwind { +define void @aligned_func(%struct.S* byval(%struct.S) align 64 %obj) nounwind { entry: %ptr = alloca i8* ; [#uses=3] %p = alloca i64 ; [#uses=3] @@ -51,7 +51,7 @@ entry: %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %0 = getelementptr inbounds %struct.S, %struct.S* %s1, i32 0, i32 0 ; [#uses=1] store i32 1, i32* %0, align 4 - call void @aligned_func(%struct.S* byval align 64 %s1) nounwind + call void @aligned_func(%struct.S* byval(%struct.S) align 64 %s1) nounwind br label %return return: ; preds = %entry diff --git a/llvm/test/CodeGen/X86/byval.ll b/llvm/test/CodeGen/X86/byval.ll index 079cd61f353a2..0e5f63cbdbf50 100644 --- a/llvm/test/CodeGen/X86/byval.ll +++ b/llvm/test/CodeGen/X86/byval.ll @@ -5,7 +5,7 @@ %struct.s = type { i64, i64, i64 } -define i64 @f(%struct.s* byval %a) { +define i64 @f(%struct.s* byval(%struct.s) %a) { ; X64-LABEL: f: ; X64: # %bb.0: # %entry ; X64-NEXT: movq 8(%rsp), %rax diff --git a/llvm/test/CodeGen/X86/byval2.ll b/llvm/test/CodeGen/X86/byval2.ll index 8e5b92b58c550..181b17793149d 100644 --- a/llvm/test/CodeGen/X86/byval2.ll +++ b/llvm/test/CodeGen/X86/byval2.ll @@ -76,9 +76,9 @@ entry: store i64 %b, i64* %tmp2, align 16 %tmp4 = getelementptr %struct.s, %struct.s* %d, i32 0, i32 2 store i64 %c, i64* %tmp4, align 16 - call void @f( %struct.s* byval %d ) - call void @f( %struct.s* byval %d ) + call void @f(%struct.s* byval(%struct.s) %d) + call void @f(%struct.s* byval(%struct.s) %d) ret void } -declare void @f(%struct.s* byval) +declare void @f(%struct.s* byval(%struct.s)) diff --git a/llvm/test/CodeGen/X86/byval3.ll b/llvm/test/CodeGen/X86/byval3.ll index 790c0130886eb..80f2ec7fd52ce 100644 --- a/llvm/test/CodeGen/X86/byval3.ll +++ b/llvm/test/CodeGen/X86/byval3.ll @@ -91,9 +91,9 @@ entry: store i32 %a5, i32* %tmp8, align 16 %tmp10 = getelementptr %struct.s, %struct.s* %d, i32 0, i32 5 store i32 %a6, i32* %tmp10, align 16 - call void @f( %struct.s* byval %d) - call void @f( %struct.s* byval %d) + call void @f(%struct.s* byval(%struct.s) %d) + call void @f(%struct.s* byval(%struct.s) %d) ret void } -declare void @f(%struct.s* byval) +declare void @f(%struct.s* byval(%struct.s)) diff --git a/llvm/test/CodeGen/X86/byval4.ll b/llvm/test/CodeGen/X86/byval4.ll index 8a8713e66bc60..9e6be9bd86c67 100644 --- a/llvm/test/CodeGen/X86/byval4.ll +++ b/llvm/test/CodeGen/X86/byval4.ll @@ -101,9 +101,9 @@ entry: store i16 %a5, i16* %tmp8, align 16 %tmp10 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 5 store i16 %a6, i16* %tmp10, align 16 - call void @f( %struct.s* byval %a ) - call void @f( %struct.s* byval %a ) + call void @f(%struct.s* byval(%struct.s) %a) + call void @f(%struct.s* byval(%struct.s) %a) ret void } -declare void @f(%struct.s* byval) +declare void @f(%struct.s* byval(%struct.s)) diff --git a/llvm/test/CodeGen/X86/byval5.ll b/llvm/test/CodeGen/X86/byval5.ll index eda8fe5ff4443..c976d0d814e7c 100644 --- a/llvm/test/CodeGen/X86/byval5.ll +++ b/llvm/test/CodeGen/X86/byval5.ll @@ -108,9 +108,9 @@ entry: store i8 %a5, i8* %tmp8, align 8 %tmp10 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 5 store i8 %a6, i8* %tmp10, align 8 - call void @f( %struct.s* byval %a ) - call void @f( %struct.s* byval %a ) + call void @f(%struct.s* byval(%struct.s) %a) + call void @f(%struct.s* byval(%struct.s) %a) ret void } -declare void @f(%struct.s* byval) +declare void @f(%struct.s* byval(%struct.s)) diff --git a/llvm/test/CodeGen/X86/byval6.ll b/llvm/test/CodeGen/X86/byval6.ll index e7e29bf54ae45..09f31527a2226 100644 --- a/llvm/test/CodeGen/X86/byval6.ll +++ b/llvm/test/CodeGen/X86/byval6.ll @@ -46,8 +46,8 @@ define i32 @main() nounwind { ; CHECK-NEXT: popl %ebx ; CHECK-NEXT: retl entry: - tail call void (i32, ...) @bar( i32 3, %struct.W* byval @.cpx ) nounwind - tail call void (i32, ...) @baz( i32 3, %struct.W* byval @B ) nounwind + tail call void (i32, ...) @bar( i32 3, %struct.W* byval(%struct.W) @.cpx ) nounwind + tail call void (i32, ...) @baz( i32 3, %struct.W* byval(%struct.W) @B ) nounwind ret i32 undef } diff --git a/llvm/test/CodeGen/X86/byval7.ll b/llvm/test/CodeGen/X86/byval7.ll index 718cddd504e9d..35a7c768721b6 100644 --- a/llvm/test/CodeGen/X86/byval7.ll +++ b/llvm/test/CodeGen/X86/byval7.ll @@ -32,8 +32,8 @@ entry: %s = alloca %struct.S ; <%struct.S*> [#uses=2] %tmp15 = getelementptr %struct.S, %struct.S* %s, i32 0, i32 0 ; <<2 x i64>*> [#uses=1] store <2 x i64> < i64 8589934595, i64 1 >, <2 x i64>* %tmp15, align 16 - call void @t( i32 1, %struct.S* byval %s ) nounwind + call void @t( i32 1, %struct.S* byval(%struct.S) %s) nounwind ret i32 0 } -declare void @t(i32, %struct.S* byval ) +declare void @t(i32, %struct.S* byval(%struct.S)) diff --git a/llvm/test/CodeGen/X86/combine-abs.ll b/llvm/test/CodeGen/X86/combine-abs.ll index af399e3037049..4ff9fef148fa7 100644 --- a/llvm/test/CodeGen/X86/combine-abs.ll +++ b/llvm/test/CodeGen/X86/combine-abs.ll @@ -55,10 +55,9 @@ define i32 @combine_i32_abs_abs(i32 %a) { define <8 x i16> @combine_v8i16_abs_abs(<8 x i16> %a) { ; SSE2-LABEL: combine_v8i16_abs_abs: ; SSE2: # %bb.0: -; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psraw $15, %xmm1 -; SSE2-NEXT: paddw %xmm1, %xmm0 -; SSE2-NEXT: pxor %xmm1, %xmm0 +; SSE2-NEXT: pxor %xmm1, %xmm1 +; SSE2-NEXT: psubw %xmm0, %xmm1 +; SSE2-NEXT: pmaxsw %xmm1, %xmm0 ; SSE2-NEXT: retq ; ; SSE42-LABEL: combine_v8i16_abs_abs: @@ -82,12 +81,10 @@ define <32 x i8> @combine_v32i8_abs_abs(<32 x i8> %a) { ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm2, %xmm2 ; SSE2-NEXT: pxor %xmm3, %xmm3 -; SSE2-NEXT: pcmpgtb %xmm0, %xmm3 -; SSE2-NEXT: paddb %xmm3, %xmm0 -; SSE2-NEXT: pxor %xmm3, %xmm0 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm2 -; SSE2-NEXT: paddb %xmm2, %xmm1 -; SSE2-NEXT: pxor %xmm2, %xmm1 +; SSE2-NEXT: psubb %xmm0, %xmm3 +; SSE2-NEXT: pminub %xmm3, %xmm0 +; SSE2-NEXT: psubb %xmm1, %xmm2 +; SSE2-NEXT: pminub %xmm2, %xmm1 ; SSE2-NEXT: retq ; ; SSE42-LABEL: combine_v32i8_abs_abs: diff --git a/llvm/test/CodeGen/X86/combine-sbb.ll b/llvm/test/CodeGen/X86/combine-sbb.ll index 6eb0e1e0f0cef..efb69d8924b9c 100644 --- a/llvm/test/CodeGen/X86/combine-sbb.ll +++ b/llvm/test/CodeGen/X86/combine-sbb.ll @@ -4,7 +4,7 @@ %WideUInt32 = type { i32, i32 } -define void @PR25858_i32(%WideUInt32* sret, %WideUInt32*, %WideUInt32*) nounwind { +define void @PR25858_i32(%WideUInt32* sret(%WideUInt32), %WideUInt32*, %WideUInt32*) nounwind { ; X86-LABEL: PR25858_i32: ; X86: # %bb.0: # %top ; X86-NEXT: pushl %esi @@ -55,7 +55,7 @@ declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) %WideUInt64 = type { i64, i64 } -define void @PR25858_i64(%WideUInt64* sret, %WideUInt64*, %WideUInt64*) nounwind { +define void @PR25858_i64(%WideUInt64* sret(%WideUInt64), %WideUInt64*, %WideUInt64*) nounwind { ; X86-LABEL: PR25858_i64: ; X86: # %bb.0: # %top ; X86-NEXT: pushl %ebp diff --git a/llvm/test/CodeGen/X86/complex-fca.ll b/llvm/test/CodeGen/X86/complex-fca.ll index d1da121213d49..62faedfba7a3e 100644 --- a/llvm/test/CodeGen/X86/complex-fca.ll +++ b/llvm/test/CodeGen/X86/complex-fca.ll @@ -1,13 +1,13 @@ ; RUN: llc < %s -mtriple=i686-- | FileCheck %s -define void @ccosl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 } %z) nounwind { +define void @ccosl({ x86_fp80, x86_fp80 }* noalias sret({ x86_fp80, x86_fp80 }) %agg.result, { x86_fp80, x86_fp80 } %z) nounwind { entry: %z8 = extractvalue { x86_fp80, x86_fp80 } %z, 0 %z9 = extractvalue { x86_fp80, x86_fp80 } %z, 1 %0 = fsub x86_fp80 0xK80000000000000000000, %z9 %insert = insertvalue { x86_fp80, x86_fp80 } undef, x86_fp80 %0, 0 %insert7 = insertvalue { x86_fp80, x86_fp80 } %insert, x86_fp80 %z8, 1 - call void @ccoshl({ x86_fp80, x86_fp80 }* noalias sret %agg.result, { x86_fp80, x86_fp80 } %insert7) nounwind + call void @ccoshl({ x86_fp80, x86_fp80 }* noalias sret({ x86_fp80, x86_fp80 }) %agg.result, { x86_fp80, x86_fp80 } %insert7) nounwind ret void } @@ -18,4 +18,4 @@ entry: ; CHECK: movl %[[sret_reg]], %eax ; CHECK: retl -declare void @ccoshl({ x86_fp80, x86_fp80 }* noalias sret, { x86_fp80, x86_fp80 }) nounwind +declare void @ccoshl({ x86_fp80, x86_fp80 }* noalias sret({ x86_fp80, x86_fp80 }), { x86_fp80, x86_fp80 }) nounwind diff --git a/llvm/test/CodeGen/X86/conditional-tailcall-pgso.ll b/llvm/test/CodeGen/X86/conditional-tailcall-pgso.ll index d59e894836b41..a473dd5e9d84a 100644 --- a/llvm/test/CodeGen/X86/conditional-tailcall-pgso.ll +++ b/llvm/test/CodeGen/X86/conditional-tailcall-pgso.ll @@ -124,8 +124,6 @@ define void @f_non_leaf(i32 %x, i32 %y) !prof !14 { ; WIN64-NEXT: jmp bar # TAILCALL ; WIN64-NEXT: # encoding: [0xeb,A] ; WIN64-NEXT: # fixup A - offset: 1, value: bar-1, kind: FK_PCRel_1 -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc entry: ; Force %ebx to be spilled on the stack, turning this into diff --git a/llvm/test/CodeGen/X86/conditional-tailcall.ll b/llvm/test/CodeGen/X86/conditional-tailcall.ll index 07334df9ea111..6c5e0643a8ca5 100644 --- a/llvm/test/CodeGen/X86/conditional-tailcall.ll +++ b/llvm/test/CodeGen/X86/conditional-tailcall.ll @@ -124,8 +124,6 @@ define void @f_non_leaf(i32 %x, i32 %y) optsize { ; WIN64-NEXT: jmp bar # TAILCALL ; WIN64-NEXT: # encoding: [0xeb,A] ; WIN64-NEXT: # fixup A - offset: 1, value: bar-1, kind: FK_PCRel_1 -; WIN64-NEXT: .seh_handlerdata -; WIN64-NEXT: .text ; WIN64-NEXT: .seh_endproc entry: ; Force %ebx to be spilled on the stack, turning this into diff --git a/llvm/test/CodeGen/X86/crash-O0.ll b/llvm/test/CodeGen/X86/crash-O0.ll index 54f7c7597e503..1b64247d170aa 100644 --- a/llvm/test/CodeGen/X86/crash-O0.ll +++ b/llvm/test/CodeGen/X86/crash-O0.ll @@ -14,16 +14,15 @@ define i32 @div8() nounwind { ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: pushq %rbp ; CHECK-NEXT: movq %rsp, %rbp +; CHECK-NEXT: ## implicit-def: $rax +; CHECK-NEXT: movb %al, %cl ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: ## kill: def $al killed $al killed $eax -; CHECK-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) ## 1-byte Spill -; CHECK-NEXT: ## implicit-def: $rcx -; CHECK-NEXT: ## kill: def $cl killed $cl killed $rcx ; CHECK-NEXT: movzbw %al, %ax ; CHECK-NEXT: divb %cl -; CHECK-NEXT: movb %al, %dl -; CHECK-NEXT: movb {{[-0-9]+}}(%r{{[sb]}}p), %al ## 1-byte Reload -; CHECK-NEXT: movb %dl, {{[-0-9]+}}(%r{{[sb]}}p) ## 1-byte Spill +; CHECK-NEXT: movb %al, {{[-0-9]+}}(%r{{[sb]}}p) ## 1-byte Spill +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: ## kill: def $al killed $al killed $eax ; CHECK-NEXT: movzbw %al, %ax ; CHECK-NEXT: divb %cl ; CHECK-NEXT: shrw $8, %ax @@ -35,7 +34,9 @@ define i32 @div8() nounwind { ; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: ## implicit-def: $ecx ; CHECK-NEXT: imull %ecx, %eax +; CHECK-NEXT: ## implicit-def: $ecx ; CHECK-NEXT: addl %ecx, %eax +; CHECK-NEXT: ## implicit-def: $ecx ; CHECK-NEXT: cmpl %ecx, %eax ; CHECK-NEXT: je LBB0_3 ; CHECK-NEXT: LBB0_2: ## %"40" diff --git a/llvm/test/CodeGen/X86/crash.ll b/llvm/test/CodeGen/X86/crash.ll index 537a09b1c6077..b46856374fb1b 100644 --- a/llvm/test/CodeGen/X86/crash.ll +++ b/llvm/test/CodeGen/X86/crash.ll @@ -1,7 +1,7 @@ ; REQUIRES: asserts ; RUN: llc -mtriple=i686-- -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness ; RUN: llc -mtriple=x86_64-- -no-integrated-as < %s -verify-machineinstrs -precompute-phys-liveness - + ; PR6497 ; Chain and flag folding issues. @@ -276,7 +276,7 @@ bb27: ; preds = %bb7 br label %bb29 bb28: ; preds = %bb7 - call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef) + call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval(%t21) align 4 undef, %t13* undef) br label %bb29 bb29: ; preds = %bb28, %bb27 @@ -300,7 +300,7 @@ bb35: ; preds = %bb34 br label %bb37 bb36: ; preds = %bb34 - call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef) + call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval(%t21) align 4 undef, %t13* undef) br label %bb37 bb37: ; preds = %bb36, %bb35, %bb31 @@ -312,7 +312,7 @@ bb37: ; preds = %bb36, %bb35, %bb31 declare %t14* @_ZN4llvm9MCContext16CreateTempSymbolEv(%t2*) -declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10*, %t21* byval align 4, %t13*) +declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10*, %t21* byval(%t21) align 4, %t13*) declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind diff --git a/llvm/test/CodeGen/X86/dagcombine-tokenfactor-limit-crash.ll b/llvm/test/CodeGen/X86/dagcombine-tokenfactor-limit-crash.ll index 412eb7126f5fe..8354491c3cd1d 100644 --- a/llvm/test/CodeGen/X86/dagcombine-tokenfactor-limit-crash.ll +++ b/llvm/test/CodeGen/X86/dagcombine-tokenfactor-limit-crash.ll @@ -27,7 +27,7 @@ target triple = "x86_64-unknown-linux-gnu" ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: .cfi_def_cfa %rsp, 8 ; CHECK-NEXT: retq -define void @spam(%struct.snork* noalias sret %arg, %struct.snork* %arg2) { +define void @spam(%struct.snork* noalias sret(%struct.snork) %arg, %struct.snork* %arg2) { bb: %tmp = alloca i8, i64 66112, align 32 %tmp7 = ptrtoint i8* %tmp to i64 diff --git a/llvm/test/CodeGen/X86/dbg-baseptr.ll b/llvm/test/CodeGen/X86/dbg-baseptr.ll index 159bae12d678a..cf67a518bda1d 100644 --- a/llvm/test/CodeGen/X86/dbg-baseptr.ll +++ b/llvm/test/CodeGen/X86/dbg-baseptr.ll @@ -14,7 +14,7 @@ target triple = "x86_64--" ; CHECK-NOT: pushq ; CHECK: movl $42, %eax ; CHECK: retq -define i32 @f0(%struct.s* byval align 8 %input) !dbg !8 { +define i32 @f0(%struct.s* byval(%struct.s) align 8 %input) !dbg !8 { call void @llvm.dbg.declare(metadata %struct.s* %input, metadata !4, metadata !17), !dbg !18 ret i32 42, !dbg !18 } @@ -36,7 +36,7 @@ define i32 @f0(%struct.s* byval align 8 %input) !dbg !8 { ; CHECK: movl $42, %eax ; CHECK: popq %rbp ; CHECK: retq -define i32 @f1(%struct.s* byval align 8 %input) !dbg !19 { +define i32 @f1(%struct.s* byval(%struct.s) align 8 %input) !dbg !19 { %val = load i64, i64* @glob ; this alloca should force FP usage. %stackspace = alloca i32, i64 %val, align 1 @@ -61,7 +61,7 @@ define i32 @f1(%struct.s* byval align 8 %input) !dbg !19 { ; CHECK: andq $-64, %rsp ; CHECK: subq $64, %rsp ; CHECK: movq %rsp, %rbx -define i32 @f2(%struct.s* byval align 8 %input) !dbg !22 { +define i32 @f2(%struct.s* byval(%struct.s) align 8 %input) !dbg !22 { %val = load i64, i64* @glob %stackspace = alloca i32, i64 %val, align 64 store i32* %stackspace, i32** @ptr diff --git a/llvm/test/CodeGen/X86/dynamic-allocas-VLAs.ll b/llvm/test/CodeGen/X86/dynamic-allocas-VLAs.ll index 37de41ea7db10..cf5e2f7537cb1 100644 --- a/llvm/test/CodeGen/X86/dynamic-allocas-VLAs.ll +++ b/llvm/test/CodeGen/X86/dynamic-allocas-VLAs.ll @@ -152,14 +152,14 @@ declare void @t6_helper2(<8 x float>) ; the base pointer we use the original adjustment. %struct.struct_t = type { [5 x i32] } -define void @t7(i32 %size, %struct.struct_t* byval align 8 %arg1) nounwind uwtable { +define void @t7(i32 %size, %struct.struct_t* byval(%struct.struct_t) align 8 %arg1) nounwind uwtable { entry: %x = alloca i32, align 32 store i32 0, i32* %x, align 32 %0 = zext i32 %size to i64 %vla = alloca i32, i64 %0, align 16 %1 = load i32, i32* %x, align 32 - call void @bar(i32 %1, i32* %vla, %struct.struct_t* byval align 8 %arg1) + call void @bar(i32 %1, i32* %vla, %struct.struct_t* byval(%struct.struct_t) align 8 %arg1) ret void ; CHECK: _t7 @@ -181,7 +181,7 @@ entry: declare i8* @llvm.stacksave() nounwind -declare void @bar(i32, i32*, %struct.struct_t* byval align 8) +declare void @bar(i32, i32*, %struct.struct_t* byval(%struct.struct_t) align 8) declare void @llvm.stackrestore(i8*) nounwind diff --git a/llvm/test/CodeGen/X86/extract-extract.ll b/llvm/test/CodeGen/X86/extract-extract.ll index 88c735e2a080e..c8870838c4694 100644 --- a/llvm/test/CodeGen/X86/extract-extract.ll +++ b/llvm/test/CodeGen/X86/extract-extract.ll @@ -10,7 +10,7 @@ %crd = type { i64, %cr* } %pp = type { %cc } -define fastcc void @foo(%pp* nocapture byval %p_arg) { +define fastcc void @foo(%pp* nocapture byval(%pp) %p_arg) { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: retl diff --git a/llvm/test/CodeGen/X86/extract-store.ll b/llvm/test/CodeGen/X86/extract-store.ll index 1160c6e5d21a9..77a98028b37b0 100644 --- a/llvm/test/CodeGen/X86/extract-store.ll +++ b/llvm/test/CodeGen/X86/extract-store.ll @@ -1,20 +1,20 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32 --check-prefix=SSE-X32 --check-prefix=SSE2-X32 -; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64 --check-prefix=SSE-X64 --check-prefix=SSE2-X64 -; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X32 --check-prefix=SSE-X32 --check-prefix=SSE41-X32 -; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X64 --check-prefix=SSE-X64 --check-prefix=SSE41-X64 -; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32 --check-prefix=AVX-X32 -; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 --check-prefix=AVX-X64 -; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+sse -enable-legalize-types-checking | FileCheck %s --check-prefix=X64 --check-prefix=SSE-X64 --check-prefix=SSE2-X64 -; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+sse -enable-legalize-types-checking | FileCheck %s --check-prefix=X64 --check-prefix=SSE-X64 --check-prefix=SSE2-X64 +; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,SSE-X86,SSE2-X86 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X64,SSE-X64,SSE2-X64 +; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=X86,SSE-X86,SSE41-X86 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=X64,SSE-X64,SSE41-X64 +; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefixes=X86,AVX-X86 +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefixes=X64,AVX-X64 +; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+sse -enable-legalize-types-checking | FileCheck %s --check-prefixes=X64,SSE-X64,SSE2-X64 +; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+sse -enable-legalize-types-checking | FileCheck %s --check-prefixes=X64,SSE-X64,SSE2-X64 define void @extract_i8_0(i8* nocapture %dst, <16 x i8> %foo) nounwind { -; SSE2-X32-LABEL: extract_i8_0: -; SSE2-X32: # %bb.0: -; SSE2-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE2-X32-NEXT: movd %xmm0, %ecx -; SSE2-X32-NEXT: movb %cl, (%eax) -; SSE2-X32-NEXT: retl +; SSE2-X86-LABEL: extract_i8_0: +; SSE2-X86: # %bb.0: +; SSE2-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE2-X86-NEXT: movd %xmm0, %ecx +; SSE2-X86-NEXT: movb %cl, (%eax) +; SSE2-X86-NEXT: retl ; ; SSE2-X64-LABEL: extract_i8_0: ; SSE2-X64: # %bb.0: @@ -22,22 +22,22 @@ define void @extract_i8_0(i8* nocapture %dst, <16 x i8> %foo) nounwind { ; SSE2-X64-NEXT: movb %al, (%rdi) ; SSE2-X64-NEXT: retq ; -; SSE41-X32-LABEL: extract_i8_0: -; SSE41-X32: # %bb.0: -; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE41-X32-NEXT: pextrb $0, %xmm0, (%eax) -; SSE41-X32-NEXT: retl +; SSE41-X86-LABEL: extract_i8_0: +; SSE41-X86: # %bb.0: +; SSE41-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE41-X86-NEXT: pextrb $0, %xmm0, (%eax) +; SSE41-X86-NEXT: retl ; ; SSE41-X64-LABEL: extract_i8_0: ; SSE41-X64: # %bb.0: ; SSE41-X64-NEXT: pextrb $0, %xmm0, (%rdi) ; SSE41-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_i8_0: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vpextrb $0, %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_i8_0: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vpextrb $0, %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_i8_0: ; AVX-X64: # %bb.0: @@ -49,13 +49,13 @@ define void @extract_i8_0(i8* nocapture %dst, <16 x i8> %foo) nounwind { } define void @extract_i8_3(i8* nocapture %dst, <16 x i8> %foo) nounwind { -; SSE2-X32-LABEL: extract_i8_3: -; SSE2-X32: # %bb.0: -; SSE2-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE2-X32-NEXT: movd %xmm0, %ecx -; SSE2-X32-NEXT: shrl $24, %ecx -; SSE2-X32-NEXT: movb %cl, (%eax) -; SSE2-X32-NEXT: retl +; SSE2-X86-LABEL: extract_i8_3: +; SSE2-X86: # %bb.0: +; SSE2-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE2-X86-NEXT: movd %xmm0, %ecx +; SSE2-X86-NEXT: shrl $24, %ecx +; SSE2-X86-NEXT: movb %cl, (%eax) +; SSE2-X86-NEXT: retl ; ; SSE2-X64-LABEL: extract_i8_3: ; SSE2-X64: # %bb.0: @@ -64,22 +64,22 @@ define void @extract_i8_3(i8* nocapture %dst, <16 x i8> %foo) nounwind { ; SSE2-X64-NEXT: movb %al, (%rdi) ; SSE2-X64-NEXT: retq ; -; SSE41-X32-LABEL: extract_i8_3: -; SSE41-X32: # %bb.0: -; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE41-X32-NEXT: pextrb $3, %xmm0, (%eax) -; SSE41-X32-NEXT: retl +; SSE41-X86-LABEL: extract_i8_3: +; SSE41-X86: # %bb.0: +; SSE41-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE41-X86-NEXT: pextrb $3, %xmm0, (%eax) +; SSE41-X86-NEXT: retl ; ; SSE41-X64-LABEL: extract_i8_3: ; SSE41-X64: # %bb.0: ; SSE41-X64-NEXT: pextrb $3, %xmm0, (%rdi) ; SSE41-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_i8_3: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vpextrb $3, %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_i8_3: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vpextrb $3, %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_i8_3: ; AVX-X64: # %bb.0: @@ -91,12 +91,12 @@ define void @extract_i8_3(i8* nocapture %dst, <16 x i8> %foo) nounwind { } define void @extract_i8_15(i8* nocapture %dst, <16 x i8> %foo) nounwind { -; SSE2-X32-LABEL: extract_i8_15: -; SSE2-X32: # %bb.0: -; SSE2-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE2-X32-NEXT: pextrw $7, %xmm0, %ecx -; SSE2-X32-NEXT: movb %ch, (%eax) -; SSE2-X32-NEXT: retl +; SSE2-X86-LABEL: extract_i8_15: +; SSE2-X86: # %bb.0: +; SSE2-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE2-X86-NEXT: pextrw $7, %xmm0, %ecx +; SSE2-X86-NEXT: movb %ch, (%eax) +; SSE2-X86-NEXT: retl ; ; SSE2-X64-LABEL: extract_i8_15: ; SSE2-X64: # %bb.0: @@ -104,22 +104,22 @@ define void @extract_i8_15(i8* nocapture %dst, <16 x i8> %foo) nounwind { ; SSE2-X64-NEXT: movb %ah, (%rdi) ; SSE2-X64-NEXT: retq ; -; SSE41-X32-LABEL: extract_i8_15: -; SSE41-X32: # %bb.0: -; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE41-X32-NEXT: pextrb $15, %xmm0, (%eax) -; SSE41-X32-NEXT: retl +; SSE41-X86-LABEL: extract_i8_15: +; SSE41-X86: # %bb.0: +; SSE41-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE41-X86-NEXT: pextrb $15, %xmm0, (%eax) +; SSE41-X86-NEXT: retl ; ; SSE41-X64-LABEL: extract_i8_15: ; SSE41-X64: # %bb.0: ; SSE41-X64-NEXT: pextrb $15, %xmm0, (%rdi) ; SSE41-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_i8_15: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vpextrb $15, %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_i8_15: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vpextrb $15, %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_i8_15: ; AVX-X64: # %bb.0: @@ -131,12 +131,12 @@ define void @extract_i8_15(i8* nocapture %dst, <16 x i8> %foo) nounwind { } define void @extract_i16_0(i16* nocapture %dst, <8 x i16> %foo) nounwind { -; SSE2-X32-LABEL: extract_i16_0: -; SSE2-X32: # %bb.0: -; SSE2-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE2-X32-NEXT: movd %xmm0, %ecx -; SSE2-X32-NEXT: movw %cx, (%eax) -; SSE2-X32-NEXT: retl +; SSE2-X86-LABEL: extract_i16_0: +; SSE2-X86: # %bb.0: +; SSE2-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE2-X86-NEXT: movd %xmm0, %ecx +; SSE2-X86-NEXT: movw %cx, (%eax) +; SSE2-X86-NEXT: retl ; ; SSE2-X64-LABEL: extract_i16_0: ; SSE2-X64: # %bb.0: @@ -144,22 +144,22 @@ define void @extract_i16_0(i16* nocapture %dst, <8 x i16> %foo) nounwind { ; SSE2-X64-NEXT: movw %ax, (%rdi) ; SSE2-X64-NEXT: retq ; -; SSE41-X32-LABEL: extract_i16_0: -; SSE41-X32: # %bb.0: -; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE41-X32-NEXT: pextrw $0, %xmm0, (%eax) -; SSE41-X32-NEXT: retl +; SSE41-X86-LABEL: extract_i16_0: +; SSE41-X86: # %bb.0: +; SSE41-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE41-X86-NEXT: pextrw $0, %xmm0, (%eax) +; SSE41-X86-NEXT: retl ; ; SSE41-X64-LABEL: extract_i16_0: ; SSE41-X64: # %bb.0: ; SSE41-X64-NEXT: pextrw $0, %xmm0, (%rdi) ; SSE41-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_i16_0: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vpextrw $0, %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_i16_0: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vpextrw $0, %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_i16_0: ; AVX-X64: # %bb.0: @@ -171,12 +171,12 @@ define void @extract_i16_0(i16* nocapture %dst, <8 x i16> %foo) nounwind { } define void @extract_i16_7(i16* nocapture %dst, <8 x i16> %foo) nounwind { -; SSE2-X32-LABEL: extract_i16_7: -; SSE2-X32: # %bb.0: -; SSE2-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE2-X32-NEXT: pextrw $7, %xmm0, %ecx -; SSE2-X32-NEXT: movw %cx, (%eax) -; SSE2-X32-NEXT: retl +; SSE2-X86-LABEL: extract_i16_7: +; SSE2-X86: # %bb.0: +; SSE2-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE2-X86-NEXT: pextrw $7, %xmm0, %ecx +; SSE2-X86-NEXT: movw %cx, (%eax) +; SSE2-X86-NEXT: retl ; ; SSE2-X64-LABEL: extract_i16_7: ; SSE2-X64: # %bb.0: @@ -184,22 +184,22 @@ define void @extract_i16_7(i16* nocapture %dst, <8 x i16> %foo) nounwind { ; SSE2-X64-NEXT: movw %ax, (%rdi) ; SSE2-X64-NEXT: retq ; -; SSE41-X32-LABEL: extract_i16_7: -; SSE41-X32: # %bb.0: -; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE41-X32-NEXT: pextrw $7, %xmm0, (%eax) -; SSE41-X32-NEXT: retl +; SSE41-X86-LABEL: extract_i16_7: +; SSE41-X86: # %bb.0: +; SSE41-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE41-X86-NEXT: pextrw $7, %xmm0, (%eax) +; SSE41-X86-NEXT: retl ; ; SSE41-X64-LABEL: extract_i16_7: ; SSE41-X64: # %bb.0: ; SSE41-X64-NEXT: pextrw $7, %xmm0, (%rdi) ; SSE41-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_i16_7: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vpextrw $7, %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_i16_7: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vpextrw $7, %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_i16_7: ; AVX-X64: # %bb.0: @@ -211,22 +211,22 @@ define void @extract_i16_7(i16* nocapture %dst, <8 x i16> %foo) nounwind { } define void @extract_i32_0(i32* nocapture %dst, <4 x i32> %foo) nounwind { -; SSE-X32-LABEL: extract_i32_0: -; SSE-X32: # %bb.0: -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE-X32-NEXT: movss %xmm0, (%eax) -; SSE-X32-NEXT: retl +; SSE-X86-LABEL: extract_i32_0: +; SSE-X86: # %bb.0: +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE-X86-NEXT: movss %xmm0, (%eax) +; SSE-X86-NEXT: retl ; ; SSE-X64-LABEL: extract_i32_0: ; SSE-X64: # %bb.0: ; SSE-X64-NEXT: movss %xmm0, (%rdi) ; SSE-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_i32_0: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vmovss %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_i32_0: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vmovss %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_i32_0: ; AVX-X64: # %bb.0: @@ -238,12 +238,12 @@ define void @extract_i32_0(i32* nocapture %dst, <4 x i32> %foo) nounwind { } define void @extract_i32_3(i32* nocapture %dst, <4 x i32> %foo) nounwind { -; SSE2-X32-LABEL: extract_i32_3: -; SSE2-X32: # %bb.0: -; SSE2-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE2-X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] -; SSE2-X32-NEXT: movd %xmm0, (%eax) -; SSE2-X32-NEXT: retl +; SSE2-X86-LABEL: extract_i32_3: +; SSE2-X86: # %bb.0: +; SSE2-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE2-X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] +; SSE2-X86-NEXT: movd %xmm0, (%eax) +; SSE2-X86-NEXT: retl ; ; SSE2-X64-LABEL: extract_i32_3: ; SSE2-X64: # %bb.0: @@ -251,22 +251,22 @@ define void @extract_i32_3(i32* nocapture %dst, <4 x i32> %foo) nounwind { ; SSE2-X64-NEXT: movd %xmm0, (%rdi) ; SSE2-X64-NEXT: retq ; -; SSE41-X32-LABEL: extract_i32_3: -; SSE41-X32: # %bb.0: -; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE41-X32-NEXT: extractps $3, %xmm0, (%eax) -; SSE41-X32-NEXT: retl +; SSE41-X86-LABEL: extract_i32_3: +; SSE41-X86: # %bb.0: +; SSE41-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE41-X86-NEXT: extractps $3, %xmm0, (%eax) +; SSE41-X86-NEXT: retl ; ; SSE41-X64-LABEL: extract_i32_3: ; SSE41-X64: # %bb.0: ; SSE41-X64-NEXT: extractps $3, %xmm0, (%rdi) ; SSE41-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_i32_3: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vextractps $3, %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_i32_3: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vextractps $3, %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_i32_3: ; AVX-X64: # %bb.0: @@ -278,22 +278,22 @@ define void @extract_i32_3(i32* nocapture %dst, <4 x i32> %foo) nounwind { } define void @extract_i64_0(i64* nocapture %dst, <2 x i64> %foo) nounwind { -; SSE-X32-LABEL: extract_i64_0: -; SSE-X32: # %bb.0: -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE-X32-NEXT: movlps %xmm0, (%eax) -; SSE-X32-NEXT: retl +; SSE-X86-LABEL: extract_i64_0: +; SSE-X86: # %bb.0: +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE-X86-NEXT: movlps %xmm0, (%eax) +; SSE-X86-NEXT: retl ; ; SSE-X64-LABEL: extract_i64_0: ; SSE-X64: # %bb.0: ; SSE-X64-NEXT: movlps %xmm0, (%rdi) ; SSE-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_i64_0: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vmovlps %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_i64_0: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vmovlps %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_i64_0: ; AVX-X64: # %bb.0: @@ -305,12 +305,12 @@ define void @extract_i64_0(i64* nocapture %dst, <2 x i64> %foo) nounwind { } define void @extract_i64_1(i64* nocapture %dst, <2 x i64> %foo) nounwind { -; SSE-X32-LABEL: extract_i64_1: -; SSE-X32: # %bb.0: -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE-X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] -; SSE-X32-NEXT: movq %xmm0, (%eax) -; SSE-X32-NEXT: retl +; SSE-X86-LABEL: extract_i64_1: +; SSE-X86: # %bb.0: +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE-X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] +; SSE-X86-NEXT: movq %xmm0, (%eax) +; SSE-X86-NEXT: retl ; ; SSE2-X64-LABEL: extract_i64_1: ; SSE2-X64: # %bb.0: @@ -323,12 +323,12 @@ define void @extract_i64_1(i64* nocapture %dst, <2 x i64> %foo) nounwind { ; SSE41-X64-NEXT: pextrq $1, %xmm0, (%rdi) ; SSE41-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_i64_1: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,3,0,1] -; AVX-X32-NEXT: vmovlps %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_i64_1: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,3,0,1] +; AVX-X86-NEXT: vmovlps %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_i64_1: ; AVX-X64: # %bb.0: @@ -340,22 +340,22 @@ define void @extract_i64_1(i64* nocapture %dst, <2 x i64> %foo) nounwind { } define void @extract_f32_0(float* nocapture %dst, <4 x float> %foo) nounwind { -; SSE-X32-LABEL: extract_f32_0: -; SSE-X32: # %bb.0: -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE-X32-NEXT: movss %xmm0, (%eax) -; SSE-X32-NEXT: retl +; SSE-X86-LABEL: extract_f32_0: +; SSE-X86: # %bb.0: +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE-X86-NEXT: movss %xmm0, (%eax) +; SSE-X86-NEXT: retl ; ; SSE-X64-LABEL: extract_f32_0: ; SSE-X64: # %bb.0: ; SSE-X64-NEXT: movss %xmm0, (%rdi) ; SSE-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_f32_0: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vmovss %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_f32_0: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vmovss %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_f32_0: ; AVX-X64: # %bb.0: @@ -367,12 +367,12 @@ define void @extract_f32_0(float* nocapture %dst, <4 x float> %foo) nounwind { } define void @extract_f32_3(float* nocapture %dst, <4 x float> %foo) nounwind { -; SSE2-X32-LABEL: extract_f32_3: -; SSE2-X32: # %bb.0: -; SSE2-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE2-X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] -; SSE2-X32-NEXT: movss %xmm0, (%eax) -; SSE2-X32-NEXT: retl +; SSE2-X86-LABEL: extract_f32_3: +; SSE2-X86: # %bb.0: +; SSE2-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE2-X86-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3] +; SSE2-X86-NEXT: movss %xmm0, (%eax) +; SSE2-X86-NEXT: retl ; ; SSE2-X64-LABEL: extract_f32_3: ; SSE2-X64: # %bb.0: @@ -380,22 +380,22 @@ define void @extract_f32_3(float* nocapture %dst, <4 x float> %foo) nounwind { ; SSE2-X64-NEXT: movss %xmm0, (%rdi) ; SSE2-X64-NEXT: retq ; -; SSE41-X32-LABEL: extract_f32_3: -; SSE41-X32: # %bb.0: -; SSE41-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE41-X32-NEXT: extractps $3, %xmm0, (%eax) -; SSE41-X32-NEXT: retl +; SSE41-X86-LABEL: extract_f32_3: +; SSE41-X86: # %bb.0: +; SSE41-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE41-X86-NEXT: extractps $3, %xmm0, (%eax) +; SSE41-X86-NEXT: retl ; ; SSE41-X64-LABEL: extract_f32_3: ; SSE41-X64: # %bb.0: ; SSE41-X64-NEXT: extractps $3, %xmm0, (%rdi) ; SSE41-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_f32_3: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vextractps $3, %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_f32_3: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vextractps $3, %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_f32_3: ; AVX-X64: # %bb.0: @@ -407,22 +407,22 @@ define void @extract_f32_3(float* nocapture %dst, <4 x float> %foo) nounwind { } define void @extract_f64_0(double* nocapture %dst, <2 x double> %foo) nounwind { -; SSE-X32-LABEL: extract_f64_0: -; SSE-X32: # %bb.0: -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE-X32-NEXT: movlps %xmm0, (%eax) -; SSE-X32-NEXT: retl +; SSE-X86-LABEL: extract_f64_0: +; SSE-X86: # %bb.0: +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE-X86-NEXT: movlps %xmm0, (%eax) +; SSE-X86-NEXT: retl ; ; SSE-X64-LABEL: extract_f64_0: ; SSE-X64: # %bb.0: ; SSE-X64-NEXT: movlps %xmm0, (%rdi) ; SSE-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_f64_0: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vmovlps %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_f64_0: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vmovlps %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_f64_0: ; AVX-X64: # %bb.0: @@ -434,22 +434,22 @@ define void @extract_f64_0(double* nocapture %dst, <2 x double> %foo) nounwind { } define void @extract_f64_1(double* nocapture %dst, <2 x double> %foo) nounwind { -; SSE-X32-LABEL: extract_f64_1: -; SSE-X32: # %bb.0: -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE-X32-NEXT: movhps %xmm0, (%eax) -; SSE-X32-NEXT: retl +; SSE-X86-LABEL: extract_f64_1: +; SSE-X86: # %bb.0: +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE-X86-NEXT: movhps %xmm0, (%eax) +; SSE-X86-NEXT: retl ; ; SSE-X64-LABEL: extract_f64_1: ; SSE-X64: # %bb.0: ; SSE-X64-NEXT: movhps %xmm0, (%rdi) ; SSE-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_f64_1: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vmovhps %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_f64_1: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vmovhps %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_f64_1: ; AVX-X64: # %bb.0: @@ -461,34 +461,34 @@ define void @extract_f64_1(double* nocapture %dst, <2 x double> %foo) nounwind { } define void @extract_f128_0(fp128* nocapture %dst, <2 x fp128> %foo) nounwind { -; SSE-X32-LABEL: extract_f128_0: -; SSE-X32: # %bb.0: -; SSE-X32-NEXT: pushl %edi -; SSE-X32-NEXT: pushl %esi -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %edx -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %esi -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %edi -; SSE-X32-NEXT: movl %esi, 12(%edi) -; SSE-X32-NEXT: movl %edx, 8(%edi) -; SSE-X32-NEXT: movl %ecx, 4(%edi) -; SSE-X32-NEXT: movl %eax, (%edi) -; SSE-X32-NEXT: popl %esi -; SSE-X32-NEXT: popl %edi -; SSE-X32-NEXT: retl +; SSE-X86-LABEL: extract_f128_0: +; SSE-X86: # %bb.0: +; SSE-X86-NEXT: pushl %edi +; SSE-X86-NEXT: pushl %esi +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; SSE-X86-NEXT: movl %esi, 12(%edi) +; SSE-X86-NEXT: movl %edx, 8(%edi) +; SSE-X86-NEXT: movl %ecx, 4(%edi) +; SSE-X86-NEXT: movl %eax, (%edi) +; SSE-X86-NEXT: popl %esi +; SSE-X86-NEXT: popl %edi +; SSE-X86-NEXT: retl ; ; SSE-X64-LABEL: extract_f128_0: ; SSE-X64: # %bb.0: ; SSE-X64-NEXT: movups %xmm0, (%rdi) ; SSE-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_f128_0: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0 -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vmovups %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_f128_0: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0 +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vmovups %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_f128_0: ; AVX-X64: # %bb.0: @@ -500,34 +500,34 @@ define void @extract_f128_0(fp128* nocapture %dst, <2 x fp128> %foo) nounwind { } define void @extract_f128_1(fp128* nocapture %dst, <2 x fp128> %foo) nounwind { -; SSE-X32-LABEL: extract_f128_1: -; SSE-X32: # %bb.0: -; SSE-X32-NEXT: pushl %edi -; SSE-X32-NEXT: pushl %esi -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %ecx -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %edx -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %esi -; SSE-X32-NEXT: movl {{[0-9]+}}(%esp), %edi -; SSE-X32-NEXT: movl %esi, 12(%edi) -; SSE-X32-NEXT: movl %edx, 8(%edi) -; SSE-X32-NEXT: movl %ecx, 4(%edi) -; SSE-X32-NEXT: movl %eax, (%edi) -; SSE-X32-NEXT: popl %esi -; SSE-X32-NEXT: popl %edi -; SSE-X32-NEXT: retl +; SSE-X86-LABEL: extract_f128_1: +; SSE-X86: # %bb.0: +; SSE-X86-NEXT: pushl %edi +; SSE-X86-NEXT: pushl %esi +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; SSE-X86-NEXT: movl %esi, 12(%edi) +; SSE-X86-NEXT: movl %edx, 8(%edi) +; SSE-X86-NEXT: movl %ecx, 4(%edi) +; SSE-X86-NEXT: movl %eax, (%edi) +; SSE-X86-NEXT: popl %esi +; SSE-X86-NEXT: popl %edi +; SSE-X86-NEXT: retl ; ; SSE-X64-LABEL: extract_f128_1: ; SSE-X64: # %bb.0: ; SSE-X64-NEXT: movups %xmm1, (%rdi) ; SSE-X64-NEXT: retq ; -; AVX-X32-LABEL: extract_f128_1: -; AVX-X32: # %bb.0: -; AVX-X32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0 -; AVX-X32-NEXT: movl {{[0-9]+}}(%esp), %eax -; AVX-X32-NEXT: vmovups %xmm0, (%eax) -; AVX-X32-NEXT: retl +; AVX-X86-LABEL: extract_f128_1: +; AVX-X86: # %bb.0: +; AVX-X86-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0 +; AVX-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; AVX-X86-NEXT: vmovups %xmm0, (%eax) +; AVX-X86-NEXT: retl ; ; AVX-X64-LABEL: extract_f128_1: ; AVX-X64: # %bb.0: @@ -539,9 +539,9 @@ define void @extract_f128_1(fp128* nocapture %dst, <2 x fp128> %foo) nounwind { } define void @extract_i8_undef(i8* nocapture %dst, <16 x i8> %foo) nounwind { -; X32-LABEL: extract_i8_undef: -; X32: # %bb.0: -; X32-NEXT: retl +; X86-LABEL: extract_i8_undef: +; X86: # %bb.0: +; X86-NEXT: retl ; ; X64-LABEL: extract_i8_undef: ; X64: # %bb.0: @@ -552,9 +552,9 @@ define void @extract_i8_undef(i8* nocapture %dst, <16 x i8> %foo) nounwind { } define void @extract_i16_undef(i16* nocapture %dst, <8 x i16> %foo) nounwind { -; X32-LABEL: extract_i16_undef: -; X32: # %bb.0: -; X32-NEXT: retl +; X86-LABEL: extract_i16_undef: +; X86: # %bb.0: +; X86-NEXT: retl ; ; X64-LABEL: extract_i16_undef: ; X64: # %bb.0: @@ -565,9 +565,9 @@ define void @extract_i16_undef(i16* nocapture %dst, <8 x i16> %foo) nounwind { } define void @extract_i32_undef(i32* nocapture %dst, <4 x i32> %foo) nounwind { -; X32-LABEL: extract_i32_undef: -; X32: # %bb.0: -; X32-NEXT: retl +; X86-LABEL: extract_i32_undef: +; X86: # %bb.0: +; X86-NEXT: retl ; ; X64-LABEL: extract_i32_undef: ; X64: # %bb.0: @@ -578,9 +578,9 @@ define void @extract_i32_undef(i32* nocapture %dst, <4 x i32> %foo) nounwind { } define void @extract_i64_undef(i64* nocapture %dst, <2 x i64> %foo) nounwind { -; X32-LABEL: extract_i64_undef: -; X32: # %bb.0: -; X32-NEXT: retl +; X86-LABEL: extract_i64_undef: +; X86: # %bb.0: +; X86-NEXT: retl ; ; X64-LABEL: extract_i64_undef: ; X64: # %bb.0: @@ -591,9 +591,9 @@ define void @extract_i64_undef(i64* nocapture %dst, <2 x i64> %foo) nounwind { } define void @extract_f32_undef(float* nocapture %dst, <4 x float> %foo) nounwind { -; X32-LABEL: extract_f32_undef: -; X32: # %bb.0: -; X32-NEXT: retl +; X86-LABEL: extract_f32_undef: +; X86: # %bb.0: +; X86-NEXT: retl ; ; X64-LABEL: extract_f32_undef: ; X64: # %bb.0: @@ -604,9 +604,9 @@ define void @extract_f32_undef(float* nocapture %dst, <4 x float> %foo) nounwind } define void @extract_f64_undef(double* nocapture %dst, <2 x double> %foo) nounwind { -; X32-LABEL: extract_f64_undef: -; X32: # %bb.0: -; X32-NEXT: retl +; X86-LABEL: extract_f64_undef: +; X86: # %bb.0: +; X86-NEXT: retl ; ; X64-LABEL: extract_f64_undef: ; X64: # %bb.0: @@ -617,9 +617,9 @@ define void @extract_f64_undef(double* nocapture %dst, <2 x double> %foo) nounwi } define void @extract_f128_undef(fp128* nocapture %dst, <2 x fp128> %foo) nounwind { -; X32-LABEL: extract_f128_undef: -; X32: # %bb.0: -; X32-NEXT: retl +; X86-LABEL: extract_f128_undef: +; X86: # %bb.0: +; X86-NEXT: retl ; ; X64-LABEL: extract_f128_undef: ; X64: # %bb.0: diff --git a/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll b/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll index 007ac1d9a3c29..b99123d13d4ea 100644 --- a/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll +++ b/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll @@ -3,7 +3,7 @@ %struct.s0 = type { x86_fp80, x86_fp80 } ; FastISel cannot handle this case yet. Make sure that we abort. -define i8* @args_fail(%struct.s0* byval nocapture readonly align 16 %y) { +define i8* @args_fail(%struct.s0* byval(%struct.s0) nocapture readonly align 16 %y) { %1 = bitcast %struct.s0* %y to i8* ret i8* %1 } diff --git a/llvm/test/CodeGen/X86/fast-isel-call.ll b/llvm/test/CodeGen/X86/fast-isel-call.ll index 2f3f415142435..9eed939147f54 100644 --- a/llvm/test/CodeGen/X86/fast-isel-call.ll +++ b/llvm/test/CodeGen/X86/fast-isel-call.ll @@ -17,10 +17,10 @@ BB2: } declare zeroext i1 @foo() nounwind -declare void @foo2(%struct.s* byval) +declare void @foo2(%struct.s* byval(%struct.s)) define void @test2(%struct.s* %d) nounwind { - call void @foo2(%struct.s* byval %d ) + call void @foo2(%struct.s* byval(%struct.s) %d ) ret void ; CHECK-LABEL: test2: ; CHECK: movl (%eax), %ecx diff --git a/llvm/test/CodeGen/X86/fast-isel-constant.ll b/llvm/test/CodeGen/X86/fast-isel-constant.ll deleted file mode 100644 index 2c7cbc64da016..0000000000000 --- a/llvm/test/CodeGen/X86/fast-isel-constant.ll +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-- -O0 | FileCheck %s -; Make sure fast-isel doesn't reset the materialised constant map -; across an intrinsic call. - -; CHECK: movl $100000 -; CHECK-NOT: movl $100000 -define i1 @test1(i32 %v1, i32 %v2, i32* %X) nounwind { -entry: - %a = shl i32 100000, %v1 - %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a, i32 %v2) - %ext = extractvalue {i32, i1} %t, 0 - %sum = shl i32 100000, %ext - %obit = extractvalue {i32, i1} %t, 1 - br i1 %obit, label %overflow, label %normal - -normal: - store i32 %sum, i32* %X - br label %overflow - -overflow: - ret i1 false -} - -declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) diff --git a/llvm/test/CodeGen/X86/fast-isel-mem.ll b/llvm/test/CodeGen/X86/fast-isel-mem.ll index 3f1d9cae9340d..ee45817370f55 100644 --- a/llvm/test/CodeGen/X86/fast-isel-mem.ll +++ b/llvm/test/CodeGen/X86/fast-isel-mem.ll @@ -13,16 +13,20 @@ entry: ret i32 %2 ; This should fold one of the loads into the add. ; CHECK-LABEL: loadgv: +; CHECK: movl L_src$non_lazy_ptr, %eax +; CHECK: movl (%eax), %eax ; CHECK: movl L_src$non_lazy_ptr, %ecx -; CHECK: movl (%ecx), %eax ; CHECK: addl (%ecx), %eax +; CHECK: movl L_src$non_lazy_ptr, %ecx ; CHECK: movl %eax, (%ecx) ; CHECK: ret ; ATOM: loadgv: -; ATOM: movl L_src$non_lazy_ptr, %ecx -; ATOM: movl (%ecx), %eax +; ATOM: movl L_src$non_lazy_ptr, %eax +; ATOM: movl (%eax), %eax +; ATOM: movl L_src$non_lazy_ptr, %ecx ; ATOM: addl (%ecx), %eax +; ATOM: movl L_src$non_lazy_ptr, %ecx ; ATOM: movl %eax, (%ecx) ; ATOM: ret diff --git a/llvm/test/CodeGen/X86/fast-isel-select.ll b/llvm/test/CodeGen/X86/fast-isel-select.ll index 5f65dde68a4a2..94477f3286e48 100644 --- a/llvm/test/CodeGen/X86/fast-isel-select.ll +++ b/llvm/test/CodeGen/X86/fast-isel-select.ll @@ -9,12 +9,12 @@ define i32 @fastisel_select(i1 %exchSub2211_, i1 %trunc_8766) { ; CHECK-LABEL: fastisel_select: ; CHECK: ## %bb.0: -; CHECK-NEXT: movb %sil, %dl -; CHECK-NEXT: movb %dil, %cl +; CHECK-NEXT: movb %sil, %al +; CHECK-NEXT: movb %dil, %dl +; CHECK-NEXT: subb %al, %dl ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: subb %dl, %cl -; CHECK-NEXT: testb $1, %cl ; CHECK-NEXT: movl $1204476887, %ecx ## imm = 0x47CADBD7 +; CHECK-NEXT: testb $1, %dl ; CHECK-NEXT: cmovnel %ecx, %eax ; CHECK-NEXT: retq %shuffleInternal15257_8932 = sub i1 %exchSub2211_, %trunc_8766 diff --git a/llvm/test/CodeGen/X86/fast-isel-x86-64.ll b/llvm/test/CodeGen/X86/fast-isel-x86-64.ll index 5d3c07fb46c31..e2de3f334385b 100644 --- a/llvm/test/CodeGen/X86/fast-isel-x86-64.ll +++ b/llvm/test/CodeGen/X86/fast-isel-x86-64.ll @@ -251,13 +251,13 @@ define void @test19(double* %p1) { define void @test20() nounwind ssp { entry: %tmp = alloca %struct.a, align 8 - call void @test20sret(%struct.a* sret %tmp) + call void @test20sret(%struct.a* sret(%struct.a) %tmp) ret void ; CHECK-LABEL: test20: ; CHECK: movq %rsp, %rdi ; CHECK: callq _test20sret } -declare void @test20sret(%struct.a* sret) +declare void @test20sret(%struct.a* sret(%struct.a)) ; Check that -0.0 is not materialized using xor define void @test21(double* %p1) { @@ -292,7 +292,7 @@ entry: declare void @foo22(i32) ; PR13563 -define void @test23(i8* noalias sret %result) { +define void @test23(i8* noalias sret(i8) %result) { %a = alloca i8 %b = call i8* @foo23() ret void diff --git a/llvm/test/CodeGen/X86/fast-isel-x86.ll b/llvm/test/CodeGen/X86/fast-isel-x86.ll index 3923cf9bb9220..8da199df8135a 100644 --- a/llvm/test/CodeGen/X86/fast-isel-x86.ll +++ b/llvm/test/CodeGen/X86/fast-isel-x86.ll @@ -14,7 +14,7 @@ define float @test0() nounwind { ; This should pop 4 bytes on return. ; CHECK-LABEL: test1: ; CHECK: retl $4 -define void @test1({i32, i32, i32, i32}* sret %p) nounwind { +define void @test1({i32, i32, i32, i32}* sret({i32, i32, i32, i32}) %p) nounwind { store {i32, i32, i32, i32} zeroinitializer, {i32, i32, i32, i32}* %p ret void } @@ -34,7 +34,7 @@ define x86_thiscallcc i32 @thiscallfun(i32* %this, i32 %a, i32 %b) nounwind { ; CHECK-NEXT: addl $65536, %esp ; CHECK-NEXT: pushl %ecx ; CHECK-NEXT: retl -define x86_thiscallcc void @thiscall_large(i32* %this, [65533 x i8]* byval %b) nounwind { +define x86_thiscallcc void @thiscall_large(i32* %this, [65533 x i8]* byval([65533 x i8]) %b) nounwind { ret void } @@ -65,7 +65,7 @@ define i32 @test2() nounwind { define void @test3() nounwind ssp { entry: %tmp = alloca %struct.a, align 8 - call void @test3sret(%struct.a* sret %tmp) + call void @test3sret(%struct.a* sret(%struct.a) %tmp) ret void ; CHECK-LABEL: test3: ; CHECK: subl $44 @@ -73,13 +73,13 @@ entry: ; CHECK: calll _test3sret ; CHECK: addl $40 } -declare void @test3sret(%struct.a* sret) +declare void @test3sret(%struct.a* sret(%struct.a)) ; Check that fast-isel sret works with fastcc (and does not callee-pop) define void @test4() nounwind ssp { entry: %tmp = alloca %struct.a, align 8 - call fastcc void @test4fastccsret(%struct.a* sret %tmp) + call fastcc void @test4fastccsret(%struct.a* sret(%struct.a) %tmp) ret void ; CHECK-LABEL: test4: ; CHECK: subl $28 @@ -87,4 +87,4 @@ entry: ; CHECK: calll _test4fastccsret ; CHECK: addl $28 } -declare fastcc void @test4fastccsret(%struct.a* sret) +declare fastcc void @test4fastccsret(%struct.a* sret(%struct.a)) diff --git a/llvm/test/CodeGen/X86/fastcc-byval.ll b/llvm/test/CodeGen/X86/fastcc-byval.ll index 1706de461116f..913b7baa6713c 100644 --- a/llvm/test/CodeGen/X86/fastcc-byval.ll +++ b/llvm/test/CodeGen/X86/fastcc-byval.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -tailcallopt=false | FileCheck %s -; CHECK: movl 8(%esp), %eax -; CHECK: movl 8(%esp), %eax -; CHECK-NOT: movl 8(%esp), %eax +; CHECK: movl 8(%esp), %eax +; CHECK: movl 8(%esp), %eax +; CHECK-NOT: movl 8(%esp), %eax ; PR3122 ; rdar://6400815 @@ -16,9 +16,9 @@ define fastcc i32 @bar() nounwind { %V = alloca %struct.MVT %a = getelementptr %struct.MVT, %struct.MVT* %V, i32 0, i32 0 store i32 1, i32* %a - call fastcc void @foo(%struct.MVT* byval %V) nounwind + call fastcc void @foo(%struct.MVT* byval(%struct.MVT) %V) nounwind %t = load i32, i32* %a ret i32 %t } -declare fastcc void @foo(%struct.MVT* byval) +declare fastcc void @foo(%struct.MVT* byval(%struct.MVT)) diff --git a/llvm/test/CodeGen/X86/fastcc-sret.ll b/llvm/test/CodeGen/X86/fastcc-sret.ll index 2962f8ec1ffe3..ce715b68b642d 100644 --- a/llvm/test/CodeGen/X86/fastcc-sret.ll +++ b/llvm/test/CodeGen/X86/fastcc-sret.ll @@ -2,7 +2,7 @@ %struct.foo = type { [4 x i32] } -define fastcc void @bar(%struct.foo* noalias sret %agg.result) nounwind { +define fastcc void @bar(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind { entry: %tmp1 = getelementptr %struct.foo, %struct.foo* %agg.result, i32 0, i32 0 %tmp3 = getelementptr [4 x i32], [4 x i32]* %tmp1, i32 0, i32 0 @@ -16,7 +16,7 @@ entry: define void @foo() nounwind { %memtmp = alloca %struct.foo, align 4 - call fastcc void @bar( %struct.foo* sret %memtmp ) nounwind + call fastcc void @bar(%struct.foo* sret(%struct.foo) %memtmp ) nounwind %tmp4 = getelementptr %struct.foo, %struct.foo* %memtmp, i32 0, i32 0 %tmp5 = getelementptr [4 x i32], [4 x i32]* %tmp4, i32 0, i32 0 %tmp6 = load i32, i32* %tmp5 diff --git a/llvm/test/CodeGen/X86/fixed-stack-di-mir.ll b/llvm/test/CodeGen/X86/fixed-stack-di-mir.ll index 30d186300839f..55e7cd125d0b9 100644 --- a/llvm/test/CodeGen/X86/fixed-stack-di-mir.ll +++ b/llvm/test/CodeGen/X86/fixed-stack-di-mir.ll @@ -7,7 +7,7 @@ target triple = "x86_64-apple-unknown" declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 -define hidden void @foo(i32* byval %dstRect) { +define hidden void @foo(i32* byval(i32) %dstRect) { ; CHECK-LABEL: name: foo entry: call void @llvm.dbg.declare(metadata i32* %dstRect, metadata !3, metadata !DIExpression()), !dbg !5 diff --git a/llvm/test/CodeGen/X86/fp-stack-retcopy.ll b/llvm/test/CodeGen/X86/fp-stack-retcopy.ll index c58b00cb0be34..3fa5784e54844 100644 --- a/llvm/test/CodeGen/X86/fp-stack-retcopy.ll +++ b/llvm/test/CodeGen/X86/fp-stack-retcopy.ll @@ -5,7 +5,7 @@ declare double @foo() -define double @carg({ double, double }* byval %z) nounwind { +define double @carg({ double, double }* byval({ double, double }) %z) nounwind { ; CHECK-LABEL: carg: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: jmp _foo ## TAILCALL diff --git a/llvm/test/CodeGen/X86/fp128-i128.ll b/llvm/test/CodeGen/X86/fp128-i128.ll index 0c6b5b555224f..74722a37f38d7 100644 --- a/llvm/test/CodeGen/X86/fp128-i128.ll +++ b/llvm/test/CodeGen/X86/fp128-i128.ll @@ -440,7 +440,7 @@ declare fp128 @fabsl(fp128) #1 declare fp128 @copysignl(fp128, fp128) #1 ; Test more complicated logical operations generated from copysignl. -define void @TestCopySign({ fp128, fp128 }* noalias nocapture sret %agg.result, { fp128, fp128 }* byval nocapture readonly align 16 %z) #0 { +define void @TestCopySign({ fp128, fp128 }* noalias nocapture sret({ fp128, fp128 }) %agg.result, { fp128, fp128 }* byval({ fp128, fp128 }) nocapture readonly align 16 %z) #0 { ; SSE-LABEL: TestCopySign: ; SSE: # %bb.0: # %entry ; SSE-NEXT: pushq %rbp diff --git a/llvm/test/CodeGen/X86/frame-lowering-debug-intrinsic.ll b/llvm/test/CodeGen/X86/frame-lowering-debug-intrinsic.ll index de9d6bf93d6c9..973d95dffba69 100644 --- a/llvm/test/CodeGen/X86/frame-lowering-debug-intrinsic.ll +++ b/llvm/test/CodeGen/X86/frame-lowering-debug-intrinsic.ll @@ -25,7 +25,7 @@ define i64 @fn1WithDebug(i64 %a) !dbg !4 { %struct.Buffer = type { i8, [63 x i8] } -define void @fn2NoDebug(%struct.Buffer* byval align 64 %p1) { +define void @fn2NoDebug(%struct.Buffer* byval(%struct.Buffer) align 64 %p1) { ret void } @@ -38,7 +38,7 @@ define void @fn2NoDebug(%struct.Buffer* byval align 64 %p1) { ; CHECK-NEXT: .cfi_def_cfa %rsp, 8 ; CHECK-NEXT: ret -define void @fn2WithDebug(%struct.Buffer* byval align 64 %p1) !dbg !8 { +define void @fn2WithDebug(%struct.Buffer* byval(%struct.Buffer) align 64 %p1) !dbg !8 { call void @llvm.dbg.declare(metadata %struct.Buffer* %p1, metadata !9, metadata !6), !dbg !10 ret void } diff --git a/llvm/test/CodeGen/X86/gnu-seh-nolpads.ll b/llvm/test/CodeGen/X86/gnu-seh-nolpads.ll index 311f4d522b1df..53912b09e4343 100644 --- a/llvm/test/CodeGen/X86/gnu-seh-nolpads.ll +++ b/llvm/test/CodeGen/X86/gnu-seh-nolpads.ll @@ -15,7 +15,6 @@ entry: ; CHECK: .seh_proc use_gxx_seh ; CHECK-NOT: .seh_handler __gxx_personality_seh0 ; CHECK: callq throwit -; CHECK: .seh_handlerdata ; CHECK: .seh_endproc define void @use_gcc_seh() @@ -29,6 +28,5 @@ entry: ; CHECK: .seh_proc use_gcc_seh ; CHECK-NOT: .seh_handler __gcc_personality_seh0 ; CHECK: callq throwit -; CHECK: .seh_handlerdata ; CHECK: .seh_endproc diff --git a/llvm/test/CodeGen/X86/i64-to-float.ll b/llvm/test/CodeGen/X86/i64-to-float.ll index 6c04c21d636ae..c181f71e0d816 100644 --- a/llvm/test/CodeGen/X86/i64-to-float.ll +++ b/llvm/test/CodeGen/X86/i64-to-float.ll @@ -1,24 +1,40 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE -; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32-AVX +; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86-SSE +; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X86-AVX +; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefix=X86-AVX512F +; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f,+avx512dq,+avx512vl | FileCheck %s --check-prefix=X86-AVX512DQ ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefix=X64-AVX512F +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f,+avx512dq,+avx512vl | FileCheck %s --check-prefix=X64-AVX512DQ ;PR29078 define <2 x double> @mask_sitofp_2i64_2f64(<2 x i64> %a) nounwind { -; X32-SSE-LABEL: mask_sitofp_2i64_2f64: -; X32-SSE: # %bb.0: -; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 -; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm0 -; X32-SSE-NEXT: retl -; -; X32-AVX-LABEL: mask_sitofp_2i64_2f64: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] -; X32-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 -; X32-AVX-NEXT: retl +; X86-SSE-LABEL: mask_sitofp_2i64_2f64: +; X86-SSE: # %bb.0: +; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 +; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm0 +; X86-SSE-NEXT: retl +; +; X86-AVX-LABEL: mask_sitofp_2i64_2f64: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] +; X86-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X86-AVX-NEXT: retl +; +; X86-AVX512F-LABEL: mask_sitofp_2i64_2f64: +; X86-AVX512F: # %bb.0: +; X86-AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] +; X86-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X86-AVX512F-NEXT: retl +; +; X86-AVX512DQ-LABEL: mask_sitofp_2i64_2f64: +; X86-AVX512DQ: # %bb.0: +; X86-AVX512DQ-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 +; X86-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0 +; X86-AVX512DQ-NEXT: retl ; ; X64-SSE-LABEL: mask_sitofp_2i64_2f64: ; X64-SSE: # %bb.0: @@ -32,24 +48,48 @@ define <2 x double> @mask_sitofp_2i64_2f64(<2 x i64> %a) nounwind { ; X64-AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] ; X64-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X64-AVX-NEXT: retq +; +; X64-AVX512F-LABEL: mask_sitofp_2i64_2f64: +; X64-AVX512F: # %bb.0: +; X64-AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] +; X64-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X64-AVX512F-NEXT: retq +; +; X64-AVX512DQ-LABEL: mask_sitofp_2i64_2f64: +; X64-AVX512DQ: # %bb.0: +; X64-AVX512DQ-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 +; X64-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0 +; X64-AVX512DQ-NEXT: retq %and = and <2 x i64> %a, %cvt = sitofp <2 x i64> %and to <2 x double> ret <2 x double> %cvt } define <2 x double> @mask_uitofp_2i64_2f64(<2 x i64> %a) nounwind { -; X32-SSE-LABEL: mask_uitofp_2i64_2f64: -; X32-SSE: # %bb.0: -; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 -; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm0 -; X32-SSE-NEXT: retl -; -; X32-AVX-LABEL: mask_uitofp_2i64_2f64: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] -; X32-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 -; X32-AVX-NEXT: retl +; X86-SSE-LABEL: mask_uitofp_2i64_2f64: +; X86-SSE: # %bb.0: +; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 +; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm0 +; X86-SSE-NEXT: retl +; +; X86-AVX-LABEL: mask_uitofp_2i64_2f64: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] +; X86-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X86-AVX-NEXT: retl +; +; X86-AVX512F-LABEL: mask_uitofp_2i64_2f64: +; X86-AVX512F: # %bb.0: +; X86-AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] +; X86-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X86-AVX512F-NEXT: retl +; +; X86-AVX512DQ-LABEL: mask_uitofp_2i64_2f64: +; X86-AVX512DQ: # %bb.0: +; X86-AVX512DQ-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 +; X86-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0 +; X86-AVX512DQ-NEXT: retl ; ; X64-SSE-LABEL: mask_uitofp_2i64_2f64: ; X64-SSE: # %bb.0: @@ -63,27 +103,54 @@ define <2 x double> @mask_uitofp_2i64_2f64(<2 x i64> %a) nounwind { ; X64-AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] ; X64-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X64-AVX-NEXT: retq +; +; X64-AVX512F-LABEL: mask_uitofp_2i64_2f64: +; X64-AVX512F: # %bb.0: +; X64-AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] +; X64-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X64-AVX512F-NEXT: retq +; +; X64-AVX512DQ-LABEL: mask_uitofp_2i64_2f64: +; X64-AVX512DQ: # %bb.0: +; X64-AVX512DQ-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 +; X64-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0 +; X64-AVX512DQ-NEXT: retq %and = and <2 x i64> %a, %cvt = uitofp <2 x i64> %and to <2 x double> ret <2 x double> %cvt } define <4 x float> @mask_sitofp_4i64_4f32(<4 x i64> %a) nounwind { -; X32-SSE-LABEL: mask_sitofp_4i64_4f32: -; X32-SSE: # %bb.0: -; X32-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] -; X32-SSE-NEXT: andps {{\.LCPI.*}}, %xmm0 -; X32-SSE-NEXT: cvtdq2ps %xmm0, %xmm0 -; X32-SSE-NEXT: retl -; -; X32-AVX-LABEL: mask_sitofp_4i64_4f32: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 -; X32-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] -; X32-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 -; X32-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 -; X32-AVX-NEXT: vzeroupper -; X32-AVX-NEXT: retl +; X86-SSE-LABEL: mask_sitofp_4i64_4f32: +; X86-SSE: # %bb.0: +; X86-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] +; X86-SSE-NEXT: andps {{\.LCPI.*}}, %xmm0 +; X86-SSE-NEXT: cvtdq2ps %xmm0, %xmm0 +; X86-SSE-NEXT: retl +; +; X86-AVX-LABEL: mask_sitofp_4i64_4f32: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 +; X86-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] +; X86-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 +; X86-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 +; X86-AVX-NEXT: vzeroupper +; X86-AVX-NEXT: retl +; +; X86-AVX512F-LABEL: mask_sitofp_4i64_4f32: +; X86-AVX512F: # %bb.0: +; X86-AVX512F-NEXT: vpmovqd %ymm0, %xmm0 +; X86-AVX512F-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 +; X86-AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0 +; X86-AVX512F-NEXT: vzeroupper +; X86-AVX512F-NEXT: retl +; +; X86-AVX512DQ-LABEL: mask_sitofp_4i64_4f32: +; X86-AVX512DQ: # %bb.0: +; X86-AVX512DQ-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 +; X86-AVX512DQ-NEXT: vcvtqq2ps %ymm0, %xmm0 +; X86-AVX512DQ-NEXT: vzeroupper +; X86-AVX512DQ-NEXT: retl ; ; X64-SSE-LABEL: mask_sitofp_4i64_4f32: ; X64-SSE: # %bb.0: @@ -100,27 +167,57 @@ define <4 x float> @mask_sitofp_4i64_4f32(<4 x i64> %a) nounwind { ; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X64-AVX-NEXT: vzeroupper ; X64-AVX-NEXT: retq +; +; X64-AVX512F-LABEL: mask_sitofp_4i64_4f32: +; X64-AVX512F: # %bb.0: +; X64-AVX512F-NEXT: vpmovqd %ymm0, %xmm0 +; X64-AVX512F-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 +; X64-AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0 +; X64-AVX512F-NEXT: vzeroupper +; X64-AVX512F-NEXT: retq +; +; X64-AVX512DQ-LABEL: mask_sitofp_4i64_4f32: +; X64-AVX512DQ: # %bb.0: +; X64-AVX512DQ-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 +; X64-AVX512DQ-NEXT: vcvtqq2ps %ymm0, %xmm0 +; X64-AVX512DQ-NEXT: vzeroupper +; X64-AVX512DQ-NEXT: retq %and = and <4 x i64> %a, %cvt = sitofp <4 x i64> %and to <4 x float> ret <4 x float> %cvt } define <4 x float> @mask_uitofp_4i64_4f32(<4 x i64> %a) nounwind { -; X32-SSE-LABEL: mask_uitofp_4i64_4f32: -; X32-SSE: # %bb.0: -; X32-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] -; X32-SSE-NEXT: andps {{\.LCPI.*}}, %xmm0 -; X32-SSE-NEXT: cvtdq2ps %xmm0, %xmm0 -; X32-SSE-NEXT: retl -; -; X32-AVX-LABEL: mask_uitofp_4i64_4f32: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 -; X32-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] -; X32-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 -; X32-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 -; X32-AVX-NEXT: vzeroupper -; X32-AVX-NEXT: retl +; X86-SSE-LABEL: mask_uitofp_4i64_4f32: +; X86-SSE: # %bb.0: +; X86-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] +; X86-SSE-NEXT: andps {{\.LCPI.*}}, %xmm0 +; X86-SSE-NEXT: cvtdq2ps %xmm0, %xmm0 +; X86-SSE-NEXT: retl +; +; X86-AVX-LABEL: mask_uitofp_4i64_4f32: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 +; X86-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] +; X86-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 +; X86-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 +; X86-AVX-NEXT: vzeroupper +; X86-AVX-NEXT: retl +; +; X86-AVX512F-LABEL: mask_uitofp_4i64_4f32: +; X86-AVX512F: # %bb.0: +; X86-AVX512F-NEXT: vpmovqd %ymm0, %xmm0 +; X86-AVX512F-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 +; X86-AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0 +; X86-AVX512F-NEXT: vzeroupper +; X86-AVX512F-NEXT: retl +; +; X86-AVX512DQ-LABEL: mask_uitofp_4i64_4f32: +; X86-AVX512DQ: # %bb.0: +; X86-AVX512DQ-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 +; X86-AVX512DQ-NEXT: vcvtqq2ps %ymm0, %xmm0 +; X86-AVX512DQ-NEXT: vzeroupper +; X86-AVX512DQ-NEXT: retl ; ; X64-SSE-LABEL: mask_uitofp_4i64_4f32: ; X64-SSE: # %bb.0: @@ -137,59 +234,89 @@ define <4 x float> @mask_uitofp_4i64_4f32(<4 x i64> %a) nounwind { ; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X64-AVX-NEXT: vzeroupper ; X64-AVX-NEXT: retq +; +; X64-AVX512F-LABEL: mask_uitofp_4i64_4f32: +; X64-AVX512F: # %bb.0: +; X64-AVX512F-NEXT: vpmovqd %ymm0, %xmm0 +; X64-AVX512F-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 +; X64-AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0 +; X64-AVX512F-NEXT: vzeroupper +; X64-AVX512F-NEXT: retq +; +; X64-AVX512DQ-LABEL: mask_uitofp_4i64_4f32: +; X64-AVX512DQ: # %bb.0: +; X64-AVX512DQ-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 +; X64-AVX512DQ-NEXT: vcvtqq2ps %ymm0, %xmm0 +; X64-AVX512DQ-NEXT: vzeroupper +; X64-AVX512DQ-NEXT: retq %and = and <4 x i64> %a, %cvt = uitofp <4 x i64> %and to <4 x float> ret <4 x float> %cvt } define <2 x double> @clamp_sitofp_2i64_2f64(<2 x i64> %a) nounwind { -; X32-SSE-LABEL: clamp_sitofp_2i64_2f64: -; X32-SSE: # %bb.0: -; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,0,2147483648,0] -; X32-SSE-NEXT: movdqa %xmm0, %xmm2 -; X32-SSE-NEXT: pxor %xmm1, %xmm2 -; X32-SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483393,4294967295,2147483393,4294967295] -; X32-SSE-NEXT: movdqa %xmm2, %xmm4 -; X32-SSE-NEXT: pcmpgtd %xmm3, %xmm4 -; X32-SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] -; X32-SSE-NEXT: pcmpeqd %xmm3, %xmm2 -; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; X32-SSE-NEXT: pand %xmm5, %xmm2 -; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] -; X32-SSE-NEXT: por %xmm2, %xmm3 -; X32-SSE-NEXT: pand %xmm3, %xmm0 -; X32-SSE-NEXT: pandn {{\.LCPI.*}}, %xmm3 -; X32-SSE-NEXT: por %xmm0, %xmm3 -; X32-SSE-NEXT: pxor %xmm3, %xmm1 -; X32-SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483903,0,2147483903,0] -; X32-SSE-NEXT: movdqa %xmm0, %xmm2 -; X32-SSE-NEXT: pcmpgtd %xmm1, %xmm2 -; X32-SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2] -; X32-SSE-NEXT: pcmpeqd %xmm0, %xmm1 -; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3] -; X32-SSE-NEXT: pand %xmm4, %xmm0 -; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] -; X32-SSE-NEXT: por %xmm0, %xmm1 -; X32-SSE-NEXT: pand %xmm1, %xmm3 -; X32-SSE-NEXT: pandn {{\.LCPI.*}}, %xmm1 -; X32-SSE-NEXT: por %xmm3, %xmm1 -; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] -; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm0 -; X32-SSE-NEXT: retl -; -; X32-AVX-LABEL: clamp_sitofp_2i64_2f64: -; X32-AVX: # %bb.0: -; X32-AVX-NEXT: vmovddup {{.*#+}} xmm1 = [18446744073709551361,18446744073709551361] -; X32-AVX-NEXT: # xmm1 = mem[0,0] -; X32-AVX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2 -; X32-AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 -; X32-AVX-NEXT: vmovddup {{.*#+}} xmm1 = [255,255] -; X32-AVX-NEXT: # xmm1 = mem[0,0] -; X32-AVX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2 -; X32-AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 -; X32-AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3] -; X32-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 -; X32-AVX-NEXT: retl +; X86-SSE-LABEL: clamp_sitofp_2i64_2f64: +; X86-SSE: # %bb.0: +; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,0,2147483648,0] +; X86-SSE-NEXT: movdqa %xmm0, %xmm2 +; X86-SSE-NEXT: pxor %xmm1, %xmm2 +; X86-SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483393,4294967295,2147483393,4294967295] +; X86-SSE-NEXT: movdqa %xmm2, %xmm4 +; X86-SSE-NEXT: pcmpgtd %xmm3, %xmm4 +; X86-SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] +; X86-SSE-NEXT: pcmpeqd %xmm3, %xmm2 +; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; X86-SSE-NEXT: pand %xmm5, %xmm2 +; X86-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] +; X86-SSE-NEXT: por %xmm2, %xmm3 +; X86-SSE-NEXT: pand %xmm3, %xmm0 +; X86-SSE-NEXT: pandn {{\.LCPI.*}}, %xmm3 +; X86-SSE-NEXT: por %xmm0, %xmm3 +; X86-SSE-NEXT: pxor %xmm3, %xmm1 +; X86-SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483903,0,2147483903,0] +; X86-SSE-NEXT: movdqa %xmm0, %xmm2 +; X86-SSE-NEXT: pcmpgtd %xmm1, %xmm2 +; X86-SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2] +; X86-SSE-NEXT: pcmpeqd %xmm0, %xmm1 +; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3] +; X86-SSE-NEXT: pand %xmm4, %xmm0 +; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] +; X86-SSE-NEXT: por %xmm0, %xmm1 +; X86-SSE-NEXT: pand %xmm1, %xmm3 +; X86-SSE-NEXT: pandn {{\.LCPI.*}}, %xmm1 +; X86-SSE-NEXT: por %xmm3, %xmm1 +; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] +; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm0 +; X86-SSE-NEXT: retl +; +; X86-AVX-LABEL: clamp_sitofp_2i64_2f64: +; X86-AVX: # %bb.0: +; X86-AVX-NEXT: vmovddup {{.*#+}} xmm1 = [18446744073709551361,18446744073709551361] +; X86-AVX-NEXT: # xmm1 = mem[0,0] +; X86-AVX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2 +; X86-AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 +; X86-AVX-NEXT: vmovddup {{.*#+}} xmm1 = [255,255] +; X86-AVX-NEXT: # xmm1 = mem[0,0] +; X86-AVX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2 +; X86-AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 +; X86-AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3] +; X86-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X86-AVX-NEXT: retl +; +; X86-AVX512F-LABEL: clamp_sitofp_2i64_2f64: +; X86-AVX512F: # %bb.0: +; X86-AVX512F-NEXT: vpmaxsq {{\.LCPI.*}}, %xmm0, %xmm0 +; X86-AVX512F-NEXT: vpminsq {{\.LCPI.*}}, %xmm0, %xmm0 +; X86-AVX512F-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; X86-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X86-AVX512F-NEXT: retl +; +; X86-AVX512DQ-LABEL: clamp_sitofp_2i64_2f64: +; X86-AVX512DQ: # %bb.0: +; X86-AVX512DQ-NEXT: vpmaxsq {{\.LCPI.*}}, %xmm0, %xmm0 +; X86-AVX512DQ-NEXT: vpminsq {{\.LCPI.*}}, %xmm0, %xmm0 +; X86-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0 +; X86-AVX512DQ-NEXT: retl ; ; X64-SSE-LABEL: clamp_sitofp_2i64_2f64: ; X64-SSE: # %bb.0: @@ -236,6 +363,21 @@ define <2 x double> @clamp_sitofp_2i64_2f64(<2 x i64> %a) nounwind { ; X64-AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X64-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X64-AVX-NEXT: retq +; +; X64-AVX512F-LABEL: clamp_sitofp_2i64_2f64: +; X64-AVX512F: # %bb.0: +; X64-AVX512F-NEXT: vpmaxsq {{.*}}(%rip), %xmm0, %xmm0 +; X64-AVX512F-NEXT: vpminsq {{.*}}(%rip), %xmm0, %xmm0 +; X64-AVX512F-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; X64-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0 +; X64-AVX512F-NEXT: retq +; +; X64-AVX512DQ-LABEL: clamp_sitofp_2i64_2f64: +; X64-AVX512DQ: # %bb.0: +; X64-AVX512DQ-NEXT: vpmaxsq {{.*}}(%rip), %xmm0, %xmm0 +; X64-AVX512DQ-NEXT: vpminsq {{.*}}(%rip), %xmm0, %xmm0 +; X64-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0 +; X64-AVX512DQ-NEXT: retq %clo = icmp slt <2 x i64> %a, %lo = select <2 x i1> %clo, <2 x i64> , <2 x i64> %a %chi = icmp sgt <2 x i64> %lo, diff --git a/llvm/test/CodeGen/X86/inalloca-invoke.ll b/llvm/test/CodeGen/X86/inalloca-invoke.ll index d90e5012ba45b..4623c58210a3e 100644 --- a/llvm/test/CodeGen/X86/inalloca-invoke.ll +++ b/llvm/test/CodeGen/X86/inalloca-invoke.ll @@ -7,8 +7,8 @@ declare i32 @pers(...) declare void @llvm.stackrestore(i8*) declare i8* @llvm.stacksave() -declare void @begin(%Iter* sret) -declare void @plus(%Iter* sret, %Iter*, i32) +declare void @begin(%Iter* sret(%Iter)) +declare void @plus(%Iter* sret(%Iter), %Iter*, i32) declare void @reverse(%frame.reverse* inalloca align 4) define i32 @main() personality i32 (...)* @pers { @@ -26,10 +26,10 @@ blah: ; CHECK: movl %esp, %[[beg:[^ ]*]] ; CHECK: leal 12(%[[beg]]), %[[end:[^ ]*]] - call void @begin(%Iter* sret %temp.lvalue) + call void @begin(%Iter* sret(%Iter) %temp.lvalue) ; CHECK: calll _begin - invoke void @plus(%Iter* sret %end, %Iter* %temp.lvalue, i32 4) + invoke void @plus(%Iter* sret(%Iter) %end, %Iter* %temp.lvalue, i32 4) to label %invoke.cont unwind label %lpad ; Uses end as sret param. @@ -37,7 +37,7 @@ blah: ; CHECK: calll _plus invoke.cont: - call void @begin(%Iter* sret %beg) + call void @begin(%Iter* sret(%Iter) %beg) ; CHECK: pushl %[[beg]] ; CHECK: calll _begin diff --git a/llvm/test/CodeGen/X86/inline-asm-sp-clobber-memcpy.ll b/llvm/test/CodeGen/X86/inline-asm-sp-clobber-memcpy.ll index 970b9943948ff..006d87eaab8f6 100644 --- a/llvm/test/CodeGen/X86/inline-asm-sp-clobber-memcpy.ll +++ b/llvm/test/CodeGen/X86/inline-asm-sp-clobber-memcpy.ll @@ -2,12 +2,12 @@ %struct.foo = type { [88 x i8] } -declare void @bar(i8* nocapture, %struct.foo* align 4 byval) nounwind +declare void @bar(i8* nocapture, %struct.foo* align 4 byval(%struct.foo)) nounwind ; PR19012 ; Don't clobber %esi if we have inline asm that clobbers %esp. define void @test1(%struct.foo* nocapture %x, i32 %y, i8* %z) nounwind { - call void @bar(i8* %z, %struct.foo* align 4 byval %x) + call void @bar(i8* %z, %struct.foo* align 4 byval(%struct.foo) %x) call void asm sideeffect inteldialect "xor esp, esp", "=*m,~{flags},~{esp},~{esp},~{dirflag},~{fpsr},~{flags}"(i8* %z) ret void diff --git a/llvm/test/CodeGen/X86/inreg.ll b/llvm/test/CodeGen/X86/inreg.ll index cf26798c84e21..bb65b67a51e48 100644 --- a/llvm/test/CodeGen/X86/inreg.ll +++ b/llvm/test/CodeGen/X86/inreg.ll @@ -6,7 +6,7 @@ define void @g1() nounwind { entry: %tmp = alloca %struct.s1, align 4 - call void @f(%struct.s1* inreg sret %tmp, i32 inreg 41, i32 inreg 42, i32 43) + call void @f(%struct.s1* inreg sret(%struct.s1) %tmp, i32 inreg 41, i32 inreg 42, i32 43) ret void ; DAG-LABEL: g1: ; DAG: subl $[[AMT:.*]], %esp @@ -29,11 +29,11 @@ entry: ; FAST: ret } -declare void @f(%struct.s1* inreg sret, i32 inreg, i32 inreg, i32) +declare void @f(%struct.s1* inreg sret(%struct.s1), i32 inreg, i32 inreg, i32) %struct.s2 = type {} -define void @g2(%struct.s2* inreg sret %agg.result) nounwind { +define void @g2(%struct.s2* inreg sret(%struct.s2) %agg.result) nounwind { entry: ret void ; DAG: g2 diff --git a/llvm/test/CodeGen/X86/lvi-hardening-loads.ll b/llvm/test/CodeGen/X86/lvi-hardening-loads.ll index ff8276f6f1c22..3656989250745 100644 --- a/llvm/test/CodeGen/X86/lvi-hardening-loads.ll +++ b/llvm/test/CodeGen/X86/lvi-hardening-loads.ll @@ -79,8 +79,8 @@ for.body: ; preds = %for.cond ; X64-NOOPT-NEXT: # in Loop: Header=BB0_1 Depth=1 ; X64-NOOPT-NEXT: lfence ; X64-NOOPT-NEXT: movl -{{[0-9]+}}(%rsp), %eax -; X64-NOOPT-NEXT: cltd ; X64-NOOPT-NEXT: movl $2, %ecx +; X64-NOOPT-NEXT: cltd ; X64-NOOPT-NEXT: idivl %ecx ; X64-NOOPT-NEXT: cmpl $0, %edx ; X64-NOOPT-NEXT: lfence diff --git a/llvm/test/CodeGen/X86/mcu-abi.ll b/llvm/test/CodeGen/X86/mcu-abi.ll index 927f12e86bff4..8a9a466d0a67b 100644 --- a/llvm/test/CodeGen/X86/mcu-abi.ll +++ b/llvm/test/CodeGen/X86/mcu-abi.ll @@ -61,7 +61,7 @@ entry: ret double %rd } -define void @ret_large_struct(%struct.st12_t* noalias nocapture sret %agg.result, %struct.st12_t* byval nocapture readonly align 4 %r) #0 { +define void @ret_large_struct(%struct.st12_t* noalias nocapture sret(%struct.st12_t) %agg.result, %struct.st12_t* byval(%struct.st12_t) nocapture readonly align 4 %r) #0 { ; CHECK-LABEL: ret_large_struct: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pushl %esi diff --git a/llvm/test/CodeGen/X86/membarrier.ll b/llvm/test/CodeGen/X86/membarrier.ll index 59b9365f294a4..b70a0a03d609f 100644 --- a/llvm/test/CodeGen/X86/membarrier.ll +++ b/llvm/test/CodeGen/X86/membarrier.ll @@ -5,11 +5,11 @@ define i32 @t() { ; CHECK-LABEL: t: ; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: movl $1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: mfence ; CHECK-NEXT: lock decl -{{[0-9]+}}(%rsp) ; CHECK-NEXT: mfence +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retq %i = alloca i32, align 4 store i32 1, i32* %i, align 4 diff --git a/llvm/test/CodeGen/X86/memcpy-inline-fsrm.ll b/llvm/test/CodeGen/X86/memcpy-inline-fsrm.ll index 54f7973dea39a..9480d74723fcc 100644 --- a/llvm/test/CodeGen/X86/memcpy-inline-fsrm.ll +++ b/llvm/test/CodeGen/X86/memcpy-inline-fsrm.ll @@ -24,8 +24,8 @@ define void @test1(i8* %a, i8* %b, i64 %s) nounwind { ; Check that we don't crash due to a memcpy size type mismatch error ("Cannot ; emit physreg copy instruction") in X86InstrInfo::copyPhysReg. %struct = type { [4096 x i8] } -declare void @foo(%struct* byval) +declare void @foo(%struct* byval(%struct)) define void @test2(%struct* %x) { - call void @foo(%struct* byval %x) + call void @foo(%struct* byval(%struct) %x) ret void } diff --git a/llvm/test/CodeGen/X86/memcpy-struct-by-value.ll b/llvm/test/CodeGen/X86/memcpy-struct-by-value.ll index 9ebe9d3b6ab5e..bca99064d5d17 100644 --- a/llvm/test/CodeGen/X86/memcpy-struct-by-value.ll +++ b/llvm/test/CodeGen/X86/memcpy-struct-by-value.ll @@ -12,7 +12,7 @@ %struct.large = type { [4096 x i8] } -declare void @foo(%struct.large* align 8 byval) nounwind +declare void @foo(%struct.large* align 8 byval(%struct.large)) nounwind define void @test1(%struct.large* nocapture %x) nounwind { ; NOFAST32-LABEL: test1: @@ -66,7 +66,7 @@ define void @test1(%struct.large* nocapture %x) nounwind { ; FAST-NEXT: callq foo ; FAST-NEXT: addq $4104, %rsp # imm = 0x1008 ; FAST-NEXT: retq - call void @foo(%struct.large* align 8 byval %x) + call void @foo(%struct.large* align 8 byval(%struct.large) %x) ret void } @@ -123,14 +123,14 @@ define void @test2(%struct.large* nocapture %x) nounwind minsize { ; FAST-NEXT: callq foo ; FAST-NEXT: addq $4104, %rsp # imm = 0x1008 ; FAST-NEXT: retq - call void @foo(%struct.large* align 8 byval %x) + call void @foo(%struct.large* align 8 byval(%struct.large) %x) ret void } %struct.large_oddsize = type { [4095 x i8] } -declare void @foo_oddsize(%struct.large_oddsize* align 8 byval) nounwind +declare void @foo_oddsize(%struct.large_oddsize* align 8 byval(%struct.large_oddsize)) nounwind define void @test3(%struct.large_oddsize* nocapture %x) nounwind minsize { ; NOFAST32-LABEL: test3: @@ -184,7 +184,7 @@ define void @test3(%struct.large_oddsize* nocapture %x) nounwind minsize { ; FAST-NEXT: callq foo_oddsize ; FAST-NEXT: addq $4104, %rsp # imm = 0x1008 ; FAST-NEXT: retq - call void @foo_oddsize(%struct.large_oddsize* align 8 byval %x) + call void @foo_oddsize(%struct.large_oddsize* align 8 byval(%struct.large_oddsize) %x) ret void } diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll index c12d90fee09e9..8ef3f307d0b58 100644 --- a/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll +++ b/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll @@ -2179,8 +2179,8 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun ; SSE2-NEXT: psubusw %xmm1, %xmm2 ; SSE2-NEXT: psubusw %xmm0, %xmm1 ; SSE2-NEXT: psubw %xmm0, %xmm2 -; SSE2-NEXT: paddw %xmm0, %xmm2 ; SSE2-NEXT: paddw %xmm1, %xmm2 +; SSE2-NEXT: paddw %xmm0, %xmm2 ; SSE2-NEXT: psrlw $1, %xmm2 ; SSE2-NEXT: pmullw %xmm3, %xmm2 ; SSE2-NEXT: paddw %xmm0, %xmm2 diff --git a/llvm/test/CodeGen/X86/misched-aa-colored.ll b/llvm/test/CodeGen/X86/misched-aa-colored.ll index e118b00fd0987..d4a2ecc924787 100644 --- a/llvm/test/CodeGen/X86/misched-aa-colored.ll +++ b/llvm/test/CodeGen/X86/misched-aa-colored.ll @@ -137,7 +137,7 @@ target triple = "x86_64-unknown-linux-gnu" @.str100 = external hidden unnamed_addr constant [50 x i8], align 1 @__PRETTY_FUNCTION__._ZNK4llvm6SDNode10getOperandEj = external hidden unnamed_addr constant [66 x i8], align 1 -declare { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } @_ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_(%"class.llvm::SelectionDAG.104.704.1064.2024.2144.2384.4184"*, i32, i8*, i32, i32, %"class.llvm::Type.7.607.967.1927.2047.2287.4087"*, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval align 8, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval align 8) +declare { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } @_ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_(%"class.llvm::SelectionDAG.104.704.1064.2024.2144.2384.4184"*, i32, i8*, i32, i32, %"class.llvm::Type.7.607.967.1927.2047.2287.4087"*, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval(%"class.llvm::SDValue.3.603.963.1923.2043.2283.4083") align 8, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval(%"class.llvm::SDValue.3.603.963.1923.2043.2283.4083") align 8) ; Function Attrs: noreturn nounwind declare void @__assert_fail(i8*, i8*, i32, i8*) #0 @@ -172,7 +172,7 @@ entry: ; CHECK: movl $-1, %ecx ; CHECK: callq _ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_ - %call18 = call { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } @_ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_(%"class.llvm::SelectionDAG.104.704.1064.2024.2144.2384.4184"* undef, i32 undef, i8* undef, i32 -1, i32 %retval.sroa.0.0.copyload.i37, %"class.llvm::Type.7.607.967.1927.2047.2287.4087"* undef, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval align 8 undef, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval align 8 undef) #1 + %call18 = call { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } @_ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_(%"class.llvm::SelectionDAG.104.704.1064.2024.2144.2384.4184"* undef, i32 undef, i8* undef, i32 -1, i32 %retval.sroa.0.0.copyload.i37, %"class.llvm::Type.7.607.967.1927.2047.2287.4087"* undef, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval(%"class.llvm::SDValue.3.603.963.1923.2043.2283.4083") align 8 undef, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval(%"class.llvm::SDValue.3.603.963.1923.2043.2283.4083") align 8 undef) #1 ret { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } %call18 } @@ -182,7 +182,7 @@ declare hidden %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* @_ZN4llvm12 declare hidden void @_ZN4llvm16DAGTypeLegalizer10RemapValueERNS_7SDValueE(%"class.llvm::DAGTypeLegalizer.117.717.1077.2037.2157.2397.4197"*, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"*) ; Function Attrs: nounwind uwtable -declare hidden void @_ZNK4llvm18TargetLoweringBase17getTypeConversionERNS_11LLVMContextENS_3EVTE(%"struct.std::pair.112.119.719.1079.2039.2159.2399.4199"* noalias sret, %"class.llvm::TargetLoweringBase.50.650.1010.1970.2090.2330.4130"* readonly, %"class.llvm::LLVMContext.6.606.966.1926.2046.2286.4086"*, i32, %"class.llvm::Type.7.607.967.1927.2047.2287.4087"*) #2 align 2 +declare hidden void @_ZNK4llvm18TargetLoweringBase17getTypeConversionERNS_11LLVMContextENS_3EVTE(%"struct.std::pair.112.119.719.1079.2039.2159.2399.4199"* noalias sret(%"struct.std::pair.112.119.719.1079.2039.2159.2399.4199"), %"class.llvm::TargetLoweringBase.50.650.1010.1970.2090.2330.4130"* readonly, %"class.llvm::LLVMContext.6.606.966.1926.2046.2286.4086"*, i32, %"class.llvm::Type.7.607.967.1927.2047.2287.4087"*) #2 align 2 attributes #0 = { noreturn nounwind } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll index e282f6dc9a5d2..76f775b834e0b 100644 --- a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll +++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll @@ -135,8 +135,6 @@ define dso_local void @test_null_arg(%struct.Foo* %f) { ; ALL-NEXT: nop ; ALL-NEXT: addq $40, %rsp ; ALL-NEXT: retq -; ALL-NEXT: .seh_handlerdata -; ALL-NEXT: .text ; ALL-NEXT: .seh_endproc entry: call void @test_noop1(%struct.Foo* %f, i32 addrspace(270)* null) diff --git a/llvm/test/CodeGen/X86/movtopush.ll b/llvm/test/CodeGen/X86/movtopush.ll index 9f301a22a4817..ae70919361a1b 100644 --- a/llvm/test/CodeGen/X86/movtopush.ll +++ b/llvm/test/CodeGen/X86/movtopush.ll @@ -14,7 +14,7 @@ declare void @oneparam(i32 %a) declare void @eightparams(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) declare void @eightparams16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h) declare void @eightparams64(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h) -declare void @struct(%struct.s* byval %a, i32 %b, i32 %c, i32 %d) +declare void @struct(%struct.s* byval(%struct.s) %a, i32 %b, i32 %c, i32 %d) declare void @inalloca(<{ %struct.s }>* inalloca) declare i8* @llvm.stacksave() @@ -169,7 +169,7 @@ entry: ret void } -; Check that pushing the addresses of globals (Or generally, things that +; Check that pushing the addresses of globals (Or generally, things that ; aren't exactly immediates) isn't broken. ; Fixes PR21878. ; NORMAL-LABEL: test6: @@ -224,7 +224,7 @@ entry: ; (because it has frame-index references), then we must resolve ; these references correctly. ; NORMAL-LABEL: test9: -; NORMAL-NOT: leal (%esp), +; NORMAL-NOT: leal (%esp), ; NORMAL: pushl $4 ; NORMAL-NEXT: pushl $3 ; NORMAL-NEXT: pushl $2 @@ -250,7 +250,7 @@ entry: call void @good(i32 1, i32 2, i32 3, i32 4) %pv = ptrtoint i32* %p to i32 %qv = ptrtoint i32* %q to i32 - call void @struct(%struct.s* byval %s, i32 6, i32 %qv, i32 %pv) + call void @struct(%struct.s* byval(%struct.s) %s, i32 6, i32 %qv, i32 %pv) ret void } @@ -277,7 +277,7 @@ define void @test10() optsize { ret void } -; We can't fold the load from the global into the push because of +; We can't fold the load from the global into the push because of ; interference from the store ; NORMAL-LABEL: test11: ; NORMAL: movl _the_global, [[EAX:%e..]] @@ -296,7 +296,7 @@ define void @test11() optsize { ret void } -; Converting one mov into a push isn't worth it when +; Converting one mov into a push isn't worth it when ; doing so forces too much overhead for other calls. ; NORMAL-LABEL: test12: ; NORMAL: pushl $8 @@ -306,7 +306,7 @@ define void @test11() optsize { ; NORMAL-NEXT: calll _good define void @test12() optsize { entry: - %s = alloca %struct.s, align 4 + %s = alloca %struct.s, align 4 call void @struct(%struct.s* %s, i32 2, i32 3, i32 4) call void @good(i32 5, i32 6, i32 7, i32 8) call void @struct(%struct.s* %s, i32 10, i32 11, i32 12) @@ -338,8 +338,8 @@ entry: ; NORMAL=NEXT: addl $16, %esp define void @test12b() optsize { entry: - %s = alloca %struct.s, align 4 - call void @good(i32 1, i32 2, i32 3, i32 4) + %s = alloca %struct.s, align 4 + call void @good(i32 1, i32 2, i32 3, i32 4) call void @struct(%struct.s* %s, i32 6, i32 7, i32 8) call void @good(i32 9, i32 10, i32 11, i32 12) ret void @@ -402,8 +402,8 @@ entry: ; NORMAL: retl %struct.A = type { i32, i32 } %struct.B = type { i8 } -declare x86_thiscallcc %struct.B* @B_ctor(%struct.B* returned, %struct.A* byval) -declare void @B_func(%struct.B* sret, %struct.B*, i32) +declare x86_thiscallcc %struct.B* @B_ctor(%struct.B* returned, %struct.A* byval(%struct.A)) +declare void @B_func(%struct.B* sret(%struct.B), %struct.B*, i32) define void @test14(%struct.A* %a) { entry: %ref.tmp = alloca %struct.B, align 1 @@ -413,9 +413,9 @@ entry: %0 = bitcast %struct.A* %a to i64* %1 = load i64, i64* %0, align 4 store i64 %1, i64* %agg.tmp, align 4 - %call = call x86_thiscallcc %struct.B* @B_ctor(%struct.B* %ref.tmp, %struct.A* byval %tmpcast) + %call = call x86_thiscallcc %struct.B* @B_ctor(%struct.B* %ref.tmp, %struct.A* byval(%struct.A) %tmpcast) %2 = getelementptr inbounds %struct.B, %struct.B* %tmp, i32 0, i32 0 - call void @B_func(%struct.B* sret %tmp, %struct.B* %ref.tmp, i32 1) + call void @B_func(%struct.B* sret(%struct.B) %tmp, %struct.B* %ref.tmp, i32 1) ret void } @@ -433,17 +433,17 @@ entry: ; NORMAL-NEXT: addl $32, %esp ; ; NOPUSH-LABEL: pr34863_16 -; NOPUSH: subl $32, %esp -; NOPUSH-NEXT: movl 36(%esp), %eax -; NOPUSH-NEXT: movl %eax, 20(%esp) -; NOPUSH-NEXT: movl %eax, 16(%esp) -; NOPUSH-NEXT: movl %eax, 12(%esp) -; NOPUSH-NEXT: movl %eax, 8(%esp) -; NOPUSH-NEXT: movl %eax, 4(%esp) -; NOPUSH-NEXT: movl %eax, (%esp) +; NOPUSH: subl $32, %esp +; NOPUSH-NEXT: movl 36(%esp), %eax +; NOPUSH-NEXT: movl %eax, 20(%esp) +; NOPUSH-NEXT: movl %eax, 16(%esp) +; NOPUSH-NEXT: movl %eax, 12(%esp) +; NOPUSH-NEXT: movl %eax, 8(%esp) +; NOPUSH-NEXT: movl %eax, 4(%esp) +; NOPUSH-NEXT: movl %eax, (%esp) ; NOPUSH-NEXT: movl $65535, 28(%esp) -; NOPUSH-NEXT: andl $0, 24(%esp) -; NOPUSH-NEXT: calll _eightparams16 +; NOPUSH-NEXT: andl $0, 24(%esp) +; NOPUSH-NEXT: calll _eightparams16 ; NOPUSH-NEXT: addl $32, %esp define void @pr34863_16(i16 %x) minsize nounwind { entry: @@ -465,18 +465,18 @@ entry: ; NORMAL-NEXT: addl $32, %esp ; ; NOPUSH-LABEL: pr34863_32 -; NOPUSH: subl $32, %esp +; NOPUSH: subl $32, %esp ; NOPUSH-NEXT: movl 36(%esp), %eax ; NOPUSH-NEXT: movl %eax, 20(%esp) ; NOPUSH-NEXT: movl %eax, 16(%esp) ; NOPUSH-NEXT: movl %eax, 12(%esp) -; NOPUSH-NEXT: movl %eax, 8(%esp) -; NOPUSH-NEXT: movl %eax, 4(%esp) -; NOPUSH-NEXT: movl %eax, (%esp) -; NOPUSH-NEXT: orl $-1, 28(%esp) -; NOPUSH-NEXT: andl $0, 24(%esp) -; NOPUSH-NEXT: calll _eightparams -; NOPUSH-NEXT: addl $32, %esp +; NOPUSH-NEXT: movl %eax, 8(%esp) +; NOPUSH-NEXT: movl %eax, 4(%esp) +; NOPUSH-NEXT: movl %eax, (%esp) +; NOPUSH-NEXT: orl $-1, 28(%esp) +; NOPUSH-NEXT: andl $0, 24(%esp) +; NOPUSH-NEXT: calll _eightparams +; NOPUSH-NEXT: addl $32, %esp define void @pr34863_32(i32 %x) minsize nounwind { entry: tail call void @eightparams(i32 %x, i32 %x, i32 %x, i32 %x, i32 %x, i32 %x, i32 0, i32 -1) @@ -506,7 +506,7 @@ entry: ; NORMAL-NEXT: addl $64, %esp ; ; NOPUSH-LABEL: pr34863_64 -; NOPUSH: subl $64, %esp +; NOPUSH: subl $64, %esp ; NOPUSH-NEXT: movl 68(%esp), %eax ; NOPUSH-NEXT: movl 72(%esp), %ecx ; NOPUSH-NEXT: movl %ecx, 44(%esp) @@ -518,15 +518,15 @@ entry: ; NOPUSH-NEXT: movl %ecx, 20(%esp) ; NOPUSH-NEXT: movl %eax, 16(%esp) ; NOPUSH-NEXT: movl %ecx, 12(%esp) -; NOPUSH-NEXT: movl %eax, 8(%esp) -; NOPUSH-NEXT: movl %ecx, 4(%esp) -; NOPUSH-NEXT: movl %eax, (%esp) -; NOPUSH-NEXT: orl $-1, 60(%esp) -; NOPUSH-NEXT: orl $-1, 56(%esp) -; NOPUSH-NEXT: andl $0, 52(%esp) -; NOPUSH-NEXT: andl $0, 48(%esp) +; NOPUSH-NEXT: movl %eax, 8(%esp) +; NOPUSH-NEXT: movl %ecx, 4(%esp) +; NOPUSH-NEXT: movl %eax, (%esp) +; NOPUSH-NEXT: orl $-1, 60(%esp) +; NOPUSH-NEXT: orl $-1, 56(%esp) +; NOPUSH-NEXT: andl $0, 52(%esp) +; NOPUSH-NEXT: andl $0, 48(%esp) ; NOPUSH-NEXT: calll _eightparams64 -; NOPUSH-NEXT: addl $64, %esp +; NOPUSH-NEXT: addl $64, %esp define void @pr34863_64(i64 %x) minsize nounwind { entry: tail call void @eightparams64(i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 %x, i64 0, i64 -1) diff --git a/llvm/test/CodeGen/X86/movtopush.mir b/llvm/test/CodeGen/X86/movtopush.mir index 3d286bb498d51..051b505813e4f 100644 --- a/llvm/test/CodeGen/X86/movtopush.mir +++ b/llvm/test/CodeGen/X86/movtopush.mir @@ -9,7 +9,7 @@ declare void @good(i32, i32, i32, i32) - declare void @struct(%struct.s* byval, i32, i32, i32) + declare void @struct(%struct.s* byval(%struct.s), i32, i32, i32) ; Function Attrs: optsize define void @test9() #0 { @@ -20,7 +20,7 @@ call void @good(i32 1, i32 2, i32 3, i32 4) %pv = ptrtoint i32* %p to i32 %qv = ptrtoint i32* %q to i32 - call void @struct(%struct.s* byval %s, i32 6, i32 %qv, i32 %pv) + call void @struct(%struct.s* byval(%struct.s) %s, i32 6, i32 %qv, i32 %pv) ret void } diff --git a/llvm/test/CodeGen/X86/musttail-indirect.ll b/llvm/test/CodeGen/X86/musttail-indirect.ll index 5d2e0694e3444..f30d775a343b3 100644 --- a/llvm/test/CodeGen/X86/musttail-indirect.ll +++ b/llvm/test/CodeGen/X86/musttail-indirect.ll @@ -126,13 +126,13 @@ entry: ; CHECK-LABEL: j_thunk: ; CHECK: jmpl ; CHECK-NOT: ret -define x86_thiscallcc void @j_thunk(%struct.A* noalias sret %agg.result, %struct.B* %this, i32) { +define x86_thiscallcc void @j_thunk(%struct.A* noalias sret(%struct.A) %agg.result, %struct.B* %this, i32) { entry: %1 = bitcast %struct.B* %this to void (%struct.A*, %struct.B*, i32)*** %vtable = load void (%struct.A*, %struct.B*, i32)**, void (%struct.A*, %struct.B*, i32)*** %1 %vfn = getelementptr inbounds void (%struct.A*, %struct.B*, i32)*, void (%struct.A*, %struct.B*, i32)** %vtable, i32 4 %2 = load void (%struct.A*, %struct.B*, i32)*, void (%struct.A*, %struct.B*, i32)** %vfn - musttail call x86_thiscallcc void %2(%struct.A* sret %agg.result, %struct.B* %this, i32 %0) + musttail call x86_thiscallcc void %2(%struct.A* sret(%struct.A) %agg.result, %struct.B* %this, i32 %0) ret void } diff --git a/llvm/test/CodeGen/X86/musttail-varargs.ll b/llvm/test/CodeGen/X86/musttail-varargs.ll index 5d88f0dd11cd6..6e293935911d6 100644 --- a/llvm/test/CodeGen/X86/musttail-varargs.ll +++ b/llvm/test/CodeGen/X86/musttail-varargs.ll @@ -236,8 +236,6 @@ define void @f_thunk(i8* %this, ...) { ; WINDOWS-NEXT: popq %rsi ; WINDOWS-NEXT: popq %r14 ; WINDOWS-NEXT: rex64 jmpq *%rax # TAILCALL -; WINDOWS-NEXT: .seh_handlerdata -; WINDOWS-NEXT: .text ; WINDOWS-NEXT: .seh_endproc ; ; X86-NOSSE-LABEL: f_thunk: diff --git a/llvm/test/CodeGen/X86/neg-abs.ll b/llvm/test/CodeGen/X86/neg-abs.ll index 099aa8bdf7924..10896bb564c80 100644 --- a/llvm/test/CodeGen/X86/neg-abs.ll +++ b/llvm/test/CodeGen/X86/neg-abs.ll @@ -1,18 +1,156 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs \ -; RUN: -mtriple=x86_64-unknown-unknown < %s | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64 -declare i64 @llvm.abs.i64(i64, i1 immarg) +declare i8 @llvm.abs.i8(i8, i1) +declare i16 @llvm.abs.i16(i16, i1) +declare i24 @llvm.abs.i24(i24, i1) +declare i32 @llvm.abs.i32(i32, i1) +declare i64 @llvm.abs.i64(i64, i1) +declare i128 @llvm.abs.i128(i128, i1) -define i64@neg_abs(i64 %x) { -; CHECK-LABEL: neg_abs: -; CHECK: # %bb.0: -; CHECK-NEXT: movq %rdi, %rax -; CHECK-NEXT: negq %rax -; CHECK-NEXT: cmovlq %rdi, %rax -; CHECK-NEXT: negq %rax -; CHECK-NEXT: retq +define i8 @neg_abs_i8(i8 %x) nounwind { +; X86-LABEL: neg_abs_i8: +; X86: # %bb.0: +; X86-NEXT: movb {{[0-9]+}}(%esp), %cl +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: sarb $7, %al +; X86-NEXT: xorb %al, %cl +; X86-NEXT: subb %cl, %al +; X86-NEXT: retl +; +; X64-LABEL: neg_abs_i8: +; X64: # %bb.0: +; X64-NEXT: movl %edi, %eax +; X64-NEXT: sarb $7, %al +; X64-NEXT: xorb %al, %dil +; X64-NEXT: subb %dil, %al +; X64-NEXT: retq + %abs = tail call i8 @llvm.abs.i8(i8 %x, i1 true) + %neg = sub nsw i8 0, %abs + ret i8 %neg +} + +define i16 @neg_abs_i16(i16 %x) nounwind { +; X86-LABEL: neg_abs_i16: +; X86: # %bb.0: +; X86-NEXT: movswl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: sarl $15, %eax +; X86-NEXT: xorl %eax, %ecx +; X86-NEXT: subl %ecx, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax +; X86-NEXT: retl +; +; X64-LABEL: neg_abs_i16: +; X64: # %bb.0: +; X64-NEXT: movl %edi, %eax +; X64-NEXT: negw %ax +; X64-NEXT: cmovlw %di, %ax +; X64-NEXT: negl %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax +; X64-NEXT: retq + %abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true) + %neg = sub nsw i16 0, %abs + ret i16 %neg +} + +define i32 @neg_abs_i32(i32 %x) nounwind { +; X86-LABEL: neg_abs_i32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: sarl $31, %eax +; X86-NEXT: xorl %eax, %ecx +; X86-NEXT: subl %ecx, %eax +; X86-NEXT: retl +; +; X64-LABEL: neg_abs_i32: +; X64: # %bb.0: +; X64-NEXT: movl %edi, %eax +; X64-NEXT: negl %eax +; X64-NEXT: cmovll %edi, %eax +; X64-NEXT: negl %eax +; X64-NEXT: retq + %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) + %neg = sub nsw i32 0, %abs + ret i32 %neg +} + +define i64 @neg_abs_i64(i64 %x) nounwind { +; X86-LABEL: neg_abs_i64: +; X86: # %bb.0: +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl %ecx, %edx +; X86-NEXT: sarl $31, %edx +; X86-NEXT: xorl %edx, %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: xorl %edx, %esi +; X86-NEXT: movl %edx, %eax +; X86-NEXT: subl %esi, %eax +; X86-NEXT: sbbl %ecx, %edx +; X86-NEXT: popl %esi +; X86-NEXT: retl +; +; X64-LABEL: neg_abs_i64: +; X64: # %bb.0: +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: negq %rax +; X64-NEXT: cmovlq %rdi, %rax +; X64-NEXT: negq %rax +; X64-NEXT: retq %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) %neg = sub nsw i64 0, %abs ret i64 %neg } + +define i128 @neg_abs_i128(i128 %x) nounwind { +; X86-LABEL: neg_abs_i128: +; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl %ecx, %edx +; X86-NEXT: sarl $31, %edx +; X86-NEXT: xorl %edx, %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: xorl %edx, %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: xorl %edx, %edi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: xorl %edx, %ebx +; X86-NEXT: movl %edx, %ebp +; X86-NEXT: subl %ebx, %ebp +; X86-NEXT: movl %edx, %ebx +; X86-NEXT: sbbl %edi, %ebx +; X86-NEXT: movl %edx, %edi +; X86-NEXT: sbbl %esi, %edi +; X86-NEXT: sbbl %ecx, %edx +; X86-NEXT: movl %ebp, (%eax) +; X86-NEXT: movl %ebx, 4(%eax) +; X86-NEXT: movl %edi, 8(%eax) +; X86-NEXT: movl %edx, 12(%eax) +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: popl %ebp +; X86-NEXT: retl $4 +; +; X64-LABEL: neg_abs_i128: +; X64: # %bb.0: +; X64-NEXT: movq %rsi, %rdx +; X64-NEXT: sarq $63, %rdx +; X64-NEXT: xorq %rdx, %rsi +; X64-NEXT: xorq %rdx, %rdi +; X64-NEXT: movq %rdx, %rax +; X64-NEXT: subq %rdi, %rax +; X64-NEXT: sbbq %rsi, %rdx +; X64-NEXT: retq + %abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true) + %neg = sub nsw i128 0, %abs + ret i128 %neg +} diff --git a/llvm/test/CodeGen/X86/negate-add-zero.ll b/llvm/test/CodeGen/X86/negate-add-zero.ll index 26fac9b5129fe..1609e394312d3 100644 --- a/llvm/test/CodeGen/X86/negate-add-zero.ll +++ b/llvm/test/CodeGen/X86/negate-add-zero.ll @@ -276,23 +276,23 @@ declare %"struct.std::basic_ostream >"* @_ZStlsISt11 declare %"struct.std::basic_ostream >"* @_ZNSolsEd(%"struct.std::basic_ostream >"*, double) -declare void @_Z14orthoTransformIdLi3ELi3EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_Z14orthoTransformIdLi3ELi3EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) declare void @_ZN12HNodeRotate27calcRotEv(%struct.HNodeRotate2*) declare void @_ZN21HNodeTranslateRotate27calcRotEv(%struct.HNodeTranslateRotate2*) -declare void @_ZmlIdLi6ELi6EE11FixedVectorIT_XT0_ELi0EERK11FixedMatrixIS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) +declare void @_ZmlIdLi6ELi6EE11FixedVectorIT_XT0_ELi0EERK11FixedMatrixIS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %struct.Mat6*, %"struct.FixedMatrix"*) -declare void @_ZmlIdLi6ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%struct.Mat6* noalias sret, %struct.Mat6*, %struct.Mat6*) +declare void @_ZmlIdLi6ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%struct.Mat6* noalias sret(%struct.Mat6), %struct.Mat6*, %struct.Mat6*) -declare void @_ZmlIdLi6ELi6ELi3EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) +declare void @_ZmlIdLi6ELi6ELi3EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %struct.Mat6*, %"struct.FixedMatrix"*) -declare void @_ZmlIdLi6ELi6ELi2EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) +declare void @_ZmlIdLi6ELi6ELi2EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %struct.Mat6*, %"struct.FixedMatrix"*) -declare void @_ZmlIdLi5ELi6EE11FixedVectorIT_XT0_ELi0EERK11FixedMatrixIS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_ELi0EE(%"struct.FixedVector"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_ZmlIdLi5ELi6EE11FixedVectorIT_XT0_ELi0EERK11FixedMatrixIS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_ELi0EE(%"struct.FixedVector"* noalias sret(%"struct.FixedVector"), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) -declare void @_ZmlIdLi6ELi6ELi5EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) +declare void @_ZmlIdLi6ELi6ELi5EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %struct.Mat6*, %"struct.FixedMatrix"*) declare void @_ZN12HNodeRotate39setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%struct.HNodeRotate3*, %"struct.CDSVector"*, %"struct.CDSVector"*) @@ -376,7 +376,7 @@ declare void @_ZN13HingeNodeSpecILi3EE9setPosVelERK9CDSVectorIdLi1EN3CDS12Defaul declare void @_ZN13HingeNodeSpecILi3EE18enforceConstraintsER9CDSVectorIdLi1EN3CDS12DefaultAllocEES5_(%"struct.HingeNodeSpec<3>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) nounwind -declare void @_Z14orthoTransformIdLi6ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret, %struct.Mat6*, %struct.Mat6*) +declare void @_Z14orthoTransformIdLi6ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret(%struct.Mat6), %struct.Mat6*, %struct.Mat6*) declare double @_ZN13HingeNodeSpecILi1EE8kineticEEv(%"struct.HingeNodeSpec<1>"*) @@ -388,7 +388,7 @@ declare double @_ZN13HingeNodeSpecILi6EE8kineticEEv(%"struct.HingeNodeSpec<6>"*) declare double @_ZN13HingeNodeSpecILi5EE8kineticEEv(%"struct.HingeNodeSpec<5>"*) -declare void @_ZmlIdLi6ELi5ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_ZmlIdLi6ELi5ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%struct.Mat6* noalias sret(%struct.Mat6), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) declare void @_ZN13HingeNodeSpecILi1EE9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES6_(%"struct.HingeNodeSpec<1>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) @@ -396,29 +396,29 @@ declare void @_ZN13HingeNodeSpecILi5EE9setPosVelERK9CDSVectorIdLi1EN3CDS12Defaul declare void @_ZN13HingeNodeSpecILi2EE9setPosVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEES6_(%"struct.HingeNodeSpec<2>"*, %"struct.CDSVector"*, %"struct.CDSVector"*) -declare void @_Z14orthoTransformIdLi3ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_Z14orthoTransformIdLi3ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret(%struct.Mat6), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) -declare void @_ZmlIdLi6ELi1ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_ZmlIdLi6ELi1ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%struct.Mat6* noalias sret(%struct.Mat6), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) -declare void @_ZmlIdLi6ELi5ELi5EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_ZmlIdLi6ELi5ELi5EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) -declare void @_Z14orthoTransformIdLi5ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_Z14orthoTransformIdLi5ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret(%struct.Mat6), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) -declare void @_Z14orthoTransformIdLi2ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_Z14orthoTransformIdLi2ELi6EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%struct.Mat6* noalias sret(%struct.Mat6), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) -declare void @_ZmlIdLi1ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %struct.Mat6*) +declare void @_ZmlIdLi1ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %struct.Mat6*) -declare void @_ZmlIdLi5ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %struct.Mat6*) +declare void @_ZmlIdLi5ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %struct.Mat6*) -declare void @_Z14orthoTransformIdLi6ELi5EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) +declare void @_Z14orthoTransformIdLi6ELi5EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %struct.Mat6*, %"struct.FixedMatrix"*) -declare void @_ZmlIdLi2ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %struct.Mat6*) +declare void @_ZmlIdLi2ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %struct.Mat6*) -declare void @_Z14orthoTransformIdLi6ELi2EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) +declare void @_Z14orthoTransformIdLi6ELi2EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %struct.Mat6*, %"struct.FixedMatrix"*) -declare void @_ZmlIdLi3ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %struct.Mat6*) +declare void @_ZmlIdLi3ELi6ELi6EE11FixedMatrixIT_XT0_EXT2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT1_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %struct.Mat6*) -declare void @_Z14orthoTransformIdLi6ELi3EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, %"struct.FixedMatrix"*) +declare void @_Z14orthoTransformIdLi6ELi3EE11FixedMatrixIT_XT1_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT0_ELi0ELi0EERKS0_IS1_XT1_EXT0_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %struct.Mat6*, %"struct.FixedMatrix"*) declare void @_ZNSt8ios_base4InitC1Ev(%"struct.CDS::DefaultAlloc"*) @@ -436,7 +436,7 @@ declare void @_ZN9HingeNode8addChildEPS_(%struct.HingeNode*, %struct.HingeNode*) declare void @_ZN7CDSListIP9HingeNodeE6appendES1_(%"struct.CDSList"*, %struct.HingeNode*) -declare void @_ZN9HingeNode4getHEv(%struct.RMat* noalias sret, %struct.HingeNode*) +declare void @_ZN9HingeNode4getHEv(%struct.RMat* noalias sret(%struct.RMat), %struct.HingeNode*) declare i8* @__cxa_allocate_exception(i32) nounwind @@ -622,7 +622,7 @@ declare void @_ZN13HingeNodeSpecILi1EE5printEi(%"struct.HingeNodeSpec<1>"*, i32) declare void @_ZN13HingeNodeSpecILi1EE9calcAccelEv(%"struct.HingeNodeSpec<1>"*) -declare void @_ZN13HingeNodeSpecILi1EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<1>"*) +declare void @_ZN13HingeNodeSpecILi1EE4getHEv(%struct.RMat* noalias sret(%struct.RMat), %"struct.HingeNodeSpec<1>"*) declare void @__cxa_pure_virtual() nounwind @@ -652,7 +652,7 @@ declare void @_ZN13HingeNodeSpecILi3EE5printEi(%"struct.HingeNodeSpec<3>"*, i32) declare void @_ZN13HingeNodeSpecILi3EE9calcAccelEv(%"struct.HingeNodeSpec<3>"*) -declare void @_ZN13HingeNodeSpecILi3EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<3>"*) +declare void @_ZN13HingeNodeSpecILi3EE4getHEv(%struct.RMat* noalias sret(%struct.RMat), %"struct.HingeNodeSpec<3>"*) declare void @_ZN13HingeNodeSpecILi2EED0Ev(%"struct.HingeNodeSpec<2>"*) @@ -680,7 +680,7 @@ declare void @_ZN13HingeNodeSpecILi2EE5printEi(%"struct.HingeNodeSpec<2>"*, i32) declare void @_ZN13HingeNodeSpecILi2EE9calcAccelEv(%"struct.HingeNodeSpec<2>"*) -declare void @_ZN13HingeNodeSpecILi2EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<2>"*) +declare void @_ZN13HingeNodeSpecILi2EE4getHEv(%struct.RMat* noalias sret(%struct.RMat), %"struct.HingeNodeSpec<2>"*) declare void @_ZN13HingeNodeSpecILi6EED0Ev(%"struct.HingeNodeSpec<6>"*) @@ -708,7 +708,7 @@ declare void @_ZN13HingeNodeSpecILi6EE5printEi(%"struct.HingeNodeSpec<6>"*, i32) declare void @_ZN13HingeNodeSpecILi6EE9calcAccelEv(%"struct.HingeNodeSpec<6>"*) -declare void @_ZN13HingeNodeSpecILi6EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<6>"*) +declare void @_ZN13HingeNodeSpecILi6EE4getHEv(%struct.RMat* noalias sret(%struct.RMat), %"struct.HingeNodeSpec<6>"*) declare void @_ZN13HingeNodeSpecILi5EED0Ev(%"struct.HingeNodeSpec<5>"*) @@ -736,7 +736,7 @@ declare void @_ZN13HingeNodeSpecILi5EE5printEi(%"struct.HingeNodeSpec<5>"*, i32) declare void @_ZN13HingeNodeSpecILi5EE9calcAccelEv(%"struct.HingeNodeSpec<5>"*) -declare void @_ZN13HingeNodeSpecILi5EE4getHEv(%struct.RMat* noalias sret, %"struct.HingeNodeSpec<5>"*) +declare void @_ZN13HingeNodeSpecILi5EE4getHEv(%struct.RMat* noalias sret(%struct.RMat), %"struct.HingeNodeSpec<5>"*) declare void @_ZN12HNodeTorsion7calcRotEv(%struct.HNodeTorsion*) @@ -766,9 +766,9 @@ declare void @_ZN13HingeNodeSpecILi6EEC2EPK9HingeNodeRi(%"struct.HingeNodeSpec<6 declare void @_ZN13HingeNodeSpecILi5EEC2EPK9HingeNodeRi(%"struct.HingeNodeSpec<5>"*, %struct.HingeNode*, i32*) -declare void @_ZplI4Vec3K11FixedVectorIdLi6ELi0EEET_RK9SubVectorIT0_ERKS4_(%struct.Vec3* noalias sret, %"struct.SubVector >"*, %struct.Vec3*) +declare void @_ZplI4Vec3K11FixedVectorIdLi6ELi0EEET_RK9SubVectorIT0_ERKS4_(%struct.Vec3* noalias sret(%struct.Vec3), %"struct.SubVector >"*, %struct.Vec3*) -declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi1ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi1ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*) declare void @_ZN12HNodeRotate314setVelFromSVelERK11FixedVectorIdLi6ELi0EE(%struct.HNodeRotate3*, %"struct.FixedMatrix"*) @@ -782,7 +782,7 @@ declare void @_ZN13HingeNodeSpecILi1EE9calcPropsEv(%"struct.HingeNodeSpec<1>"*) declare zeroext i8 @_ZNK3IVM12minimizationEv(%struct.IVM*) -declare void @_Z8blockVecIdLi3ELi3EE11FixedVectorIT_XplT0_T1_ELi0EERKS0_IS1_XT0_ELi0EERKS0_IS1_XT1_ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_Z8blockVecIdLi3ELi3EE11FixedVectorIT_XplT0_T1_ELi0EERKS0_IS1_XT0_ELi0EERKS0_IS1_XT1_ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) declare void @_ZN12HNodeTorsion11toCartesianEv(%struct.HNodeTorsion*) @@ -798,11 +798,11 @@ declare void @_ZN13HingeNodeSpecILi5EE18calcCartesianForceEv(%"struct.HingeNodeS declare void @_ZN12HNodeTorsion5calcHEv(%struct.HNodeTorsion*) -declare void @_Z10blockMat12IdLi1ELi3ELi3EE11FixedMatrixIT_XT0_EXplT1_T2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_Z10blockMat12IdLi1ELi3ELi3EE11FixedMatrixIT_XT0_EXplT1_T2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi1ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase"*, %"struct.FixedMatrix"*) -declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi1ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi1ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*) declare %"struct.std::basic_ostream >"* @_ZStlsIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_St13_Setprecision(%"struct.std::basic_ostream >"*, i32) @@ -814,13 +814,13 @@ declare %"struct.std::basic_ostream >"* @_ZlsIdLi3EE declare %"struct.std::basic_ostream >"* @_ZlsIdLi1EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) -declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi1ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, i32, i32, i32) +declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi1ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, i32, i32, i32) declare %"struct.FixedMatrixBase"* @_ZN15FixedMatrixBaseIdLi6ELi6EEpLERKS0_(%"struct.FixedMatrixBase"*, %"struct.FixedMatrixBase"*) declare void @_ZN13HingeNodeSpecILi6EE9calcPropsEv(%"struct.HingeNodeSpec<6>"*) -declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%struct.Mat6* noalias sret, %struct.Mat6*) +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%struct.Mat6* noalias sret(%struct.Mat6), %struct.Mat6*) declare void @_ZN21HNodeTranslateRotate311toCartesianEv(%struct.HNodeTranslateRotate3*) @@ -941,21 +941,21 @@ define linkonce void @_ZN21HNodeTranslateRotate36setVelERK9CDSVectorIdLi1EN3CDS1 unreachable } -declare void @_ZmlRK11FixedMatrixIdLi6ELi6ELi0ELi0EERK18PhiMatrixTranspose(%struct.Mat6* noalias sret, %struct.Mat6*, %struct.PhiMatrixTranspose*) +declare void @_ZmlRK11FixedMatrixIdLi6ELi6ELi0ELi0EERK18PhiMatrixTranspose(%struct.Mat6* noalias sret(%struct.Mat6), %struct.Mat6*, %struct.PhiMatrixTranspose*) -declare void @_ZmlI4Mat3K11FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS4_(%struct.Mat3* noalias sret, %"struct.SubMatrix >"*, %struct.Mat3*) +declare void @_ZmlI4Mat3K11FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS4_(%struct.Mat3* noalias sret(%struct.Mat3), %"struct.SubMatrix >"*, %struct.Mat3*) -declare void @_ZmiI4Mat3K11FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS4_(%struct.Mat3* noalias sret, %"struct.SubMatrix >"*, %struct.Mat3*) +declare void @_ZmiI4Mat3K11FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS4_(%struct.Mat3* noalias sret(%struct.Mat3), %"struct.SubMatrix >"*, %struct.Mat3*) declare %"struct.FixedMatrixBase"* @_ZN15FixedMatrixBaseIdLi3ELi3EEmIERKS0_(%"struct.FixedMatrixBase"*, %"struct.FixedMatrixBase"*) -declare void @_ZplI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RKS3_RK9SubMatrixIT0_E(%struct.Mat3* noalias sret, %struct.Mat3*, %"struct.SubMatrix >"*) +declare void @_ZplI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RKS3_RK9SubMatrixIT0_E(%struct.Mat3* noalias sret(%struct.Mat3), %struct.Mat3*, %"struct.SubMatrix >"*) declare void @_ZN13CDSVectorBaseIdN3CDS12DefaultAllocEED2Ev(%"struct.CDSVectorBase"*) declare void @_ZN13HingeNodeSpecILi1EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<1>"*, %struct.Mat6*) -declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi1ELi1ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.MatrixTools::InverseResults >"*) +declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi1ELi1ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %"struct.MatrixTools::InverseResults >"*) declare i8* @__cxa_get_exception_ptr(i8*) nounwind @@ -975,15 +975,15 @@ declare %"struct.std::basic_ostream >"* @_ZSt4endlIc declare void @__cxa_end_catch() -declare void @_ZmlI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RKS3_RK9SubMatrixIT0_E(%struct.Mat3* noalias sret, %struct.Mat3*, %"struct.SubMatrix >"*) +declare void @_ZmlI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RKS3_RK9SubMatrixIT0_E(%struct.Mat3* noalias sret(%struct.Mat3), %struct.Mat3*, %"struct.SubMatrix >"*) -declare void @_ZmlI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS3_(%struct.Mat3* noalias sret, %"struct.SubMatrix >"*, %struct.Mat3*) +declare void @_ZmlI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS3_(%struct.Mat3* noalias sret(%struct.Mat3), %"struct.SubMatrix >"*, %struct.Mat3*) -declare void @_ZmiI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS3_(%struct.Mat3* noalias sret, %"struct.SubMatrix >"*, %struct.Mat3*) +declare void @_ZmiI4Mat311FixedMatrixIdLi6ELi6ELi0ELi0EEET_RK9SubMatrixIT0_ERKS3_(%struct.Mat3* noalias sret(%struct.Mat3), %"struct.SubMatrix >"*, %struct.Mat3*) declare %"struct.FixedMatrixBase"* @_ZN15FixedMatrixBaseIdLi6ELi6EEmIERKS0_(%"struct.FixedMatrixBase"*, %"struct.FixedMatrixBase"*) -declare void @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEEC2EiS2_(%"struct.CDSVectorBase"*, i32, %"struct.CDS::DefaultAlloc"* byval align 4) +declare void @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEEC2EiS2_(%"struct.CDSVectorBase"*, i32, %"struct.CDS::DefaultAlloc"* byval(%"struct.CDS::DefaultAlloc") align 4) declare void @_ZN13CDSVectorBaseI4Vec3N3CDS12DefaultAllocEED2Ev(%"struct.CDSVectorBase"*) @@ -1055,7 +1055,7 @@ declare void @_ZN14HNodeTranslate11toCartesianEv(%struct.HNodeTranslate*) declare void @_ZN12HNodeRotate3C2EPK9HingeNodeP7IVMAtomRib(%struct.HNodeRotate3*, %struct.HingeNode*, %struct.IVMAtom*, i32*, i8 zeroext) -declare void @_ZN8AtomTree6findCMEPK9HingeNode(%struct.Vec3* noalias sret, %struct.HingeNode*) +declare void @_ZN8AtomTree6findCMEPK9HingeNode(%struct.Vec3* noalias sret(%struct.Vec3), %struct.HingeNode*) declare %struct.IVMAtom** @_ZN7CDSListIP7IVMAtomE7prependERKS1_(%struct.AtomList*, %struct.IVMAtom**) @@ -1067,15 +1067,15 @@ declare void @_ZN21HNodeTranslateRotate3C2EPK9HingeNodeP7IVMAtomRib(%struct.HNod declare void @_ZN13HingeNodeSpecILi3EE9calcPropsEv(%"struct.HingeNodeSpec<3>"*) -declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi3ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi3ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*) -declare void @_ZN11MatrixTools9transposeI4Mat3EENT_13TransposeTypeERKS2_(%struct.Mat3* noalias sret, %struct.Mat3*) +declare void @_ZN11MatrixTools9transposeI4Mat3EENT_13TransposeTypeERKS2_(%struct.Mat3* noalias sret(%struct.Mat3), %struct.Mat3*) -declare void @_Z10blockMat12IdLi3ELi3ELi3EE11FixedMatrixIT_XT0_EXplT1_T2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_Z10blockMat12IdLi3ELi3ELi3EE11FixedMatrixIT_XT0_EXplT1_T2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi3ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase"*, %"struct.FixedMatrix"*) -declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi3ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi3ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*) declare %"struct.std::basic_ostream >"* @_ZlsIdLi4EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) @@ -1085,17 +1085,17 @@ declare %"struct.FixedMatrixBase"* @_ZN15FixedVectorBaseIdLi4EEdVERK declare %"struct.FixedMatrixBase"* @_ZN15FixedVectorBaseIdLi4EEmIERKS0_(%"struct.FixedMatrixBase"*, %"struct.FixedMatrixBase"*) -declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi3ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, i32, i32, i32) +declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi3ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, i32, i32, i32) declare void @_ZN13HingeNodeSpecILi3EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<3>"*, %struct.Mat6*) -declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi3ELi3ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.MatrixTools::InverseResults >"*) +declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi3ELi3ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %"struct.MatrixTools::InverseResults >"*) declare %"struct.std::basic_ostream >"* @_ZlsIdLi3ELi3EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) declare %"struct.std::basic_ostream >"* @_ZlsIdLi3ELi6EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) -declare void @_Z7unitVecRK4Vec3(%struct.Vec3* noalias sret, %struct.Vec3*) +declare void @_Z7unitVecRK4Vec3(%struct.Vec3* noalias sret(%struct.Vec3), %struct.Vec3*) declare double @_Z4normIdLi3EET_RK11FixedVectorIS0_XT0_ELi0EE(%"struct.FixedMatrix"*) @@ -1109,15 +1109,15 @@ declare void @_ZN21HNodeTranslateRotate2C2EPK9HingeNodeRi(%struct.HNodeTranslate declare void @_ZN13HingeNodeSpecILi2EE9calcPropsEv(%"struct.HingeNodeSpec<2>"*) -declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi2ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi2ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*) -declare void @_Z10blockMat21IdLi1ELi3ELi1EE11FixedMatrixIT_XplT0_T2_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT2_EXT1_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_Z10blockMat21IdLi1ELi3ELi1EE11FixedMatrixIT_XplT0_T2_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT2_EXT1_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) -declare void @_Z10blockMat12IdLi2ELi3ELi3EE11FixedMatrixIT_XT0_EXplT1_T2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) +declare void @_Z10blockMat12IdLi2ELi3ELi3EE11FixedMatrixIT_XT0_EXplT1_T2_ELi0ELi0EERKS0_IS1_XT0_EXT1_ELi0ELi0EERKS0_IS1_XT0_EXT2_ELi0ELi0EE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %"struct.FixedMatrix"*) declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi2ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase"*, %"struct.FixedMatrix"*) -declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi2ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi2ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*) declare %"struct.std::basic_ostream >"* @_ZlsIdLi2EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream >"*, %"struct.FixedVectorBase"*) @@ -1125,11 +1125,11 @@ declare %"struct.FixedMatrixBase"* @_ZN15FixedVectorBaseIdLi3EEdVERK declare %"struct.FixedMatrixBase"* @_ZN15FixedVectorBaseIdLi3EEmIERKS0_(%"struct.FixedMatrixBase"*, %"struct.FixedMatrixBase"*) -declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi2ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, i32, i32, i32) +declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi2ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, i32, i32, i32) declare void @_ZN13HingeNodeSpecILi2EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<2>"*, %struct.Mat6*) -declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi2ELi2ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.MatrixTools::InverseResults >"*) +declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi2ELi2ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %"struct.MatrixTools::InverseResults >"*) declare %"struct.std::basic_ostream >"* @_ZlsIdLi2ELi2EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) @@ -1151,29 +1151,29 @@ declare i32 @_ZNK7CDSListIP9HingeNodeE8getIndexERKS1_(%"struct.CDSList"*, %struct.Mat6*) -declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi6ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret, %struct.Mat6*, i32, i32, i32) +declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi6ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %struct.Mat6*, i32, i32, i32) declare void @_ZN13HingeNodeSpecILi6EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<6>"*, %struct.Mat6*) -declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi6ELi6ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%struct.Mat6* noalias sret, %struct.Mat6*, %"struct.MatrixTools::InverseResults >"*) +declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi6ELi6ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%struct.Mat6* noalias sret(%struct.Mat6), %struct.Mat6*, %"struct.MatrixTools::InverseResults >"*) declare %"struct.std::basic_ostream >"* @_ZlsIdLi6ELi6EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) declare void @_ZN13HingeNodeSpecILi5EE9calcPropsEv(%"struct.HingeNodeSpec<5>"*) -declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi5ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi5ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*) declare void @_ZN13CDSMatrixBaseIdEC2I11FixedMatrixIdLi5ELi6ELi0ELi0EEEERKT_(%"struct.CDSMatrixBase"*, %"struct.FixedMatrix"*) -declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi5ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*) +declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi5ELi0ELi0EEEENT_13TransposeTypeERKS3_(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*) declare %"struct.std::basic_ostream >"* @_ZlsIdLi5EERSoS0_RK15FixedVectorBaseIT_XT0_EE(%"struct.std::basic_ostream >"*, %"struct.FixedVectorBase"*) -declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi5ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, i32, i32, i32) +declare void @_ZN11FixedVectorIdLi3ELi0EE6subColILi6ELi5ELi0ELi0EEES0_RK11FixedMatrixIdXT_EXT0_EXT1_EXT2_EEiii(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, i32, i32, i32) declare void @_ZN13HingeNodeSpecILi5EE7calcD_GERK11FixedMatrixIdLi6ELi6ELi0ELi0EE(%"struct.HingeNodeSpec<5>"*, %struct.Mat6*) -declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi5ELi5ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix"* noalias sret, %"struct.FixedMatrix"*, %"struct.MatrixTools::InverseResults >"*) +declare void @_ZN11MatrixTools7inverseI11FixedMatrixIdLi5ELi5ELi0ELi0EEEET_RKS3_NS_14InverseResultsINS3_10MatrixTypeEEE(%"struct.FixedMatrix"* noalias sret(%"struct.FixedMatrix"), %"struct.FixedMatrix"*, %"struct.MatrixTools::InverseResults >"*) declare %"struct.std::basic_ostream >"* @_ZlsIdLi5ELi5EERSoS0_RK15FixedMatrixBaseIT_XT0_EXT1_EE(%"struct.std::basic_ostream >"*, %"struct.FixedMatrixBase"*) diff --git a/llvm/test/CodeGen/X86/no-sse-win64.ll b/llvm/test/CodeGen/X86/no-sse-win64.ll index c220b9606129b..258cdf25a6fbe 100644 --- a/llvm/test/CodeGen/X86/no-sse-win64.ll +++ b/llvm/test/CodeGen/X86/no-sse-win64.ll @@ -54,8 +54,6 @@ define void @pass_double(double* %p) { ; CHECK-NEXT: nop ; CHECK-NEXT: addq $40, %rsp ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc %v = load double, double* %p call void @take_double(double %v) @@ -73,8 +71,6 @@ define void @pass_float(float* %p) { ; CHECK-NEXT: nop ; CHECK-NEXT: addq $40, %rsp ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc %v = load float, float* %p call void @take_float(float %v) @@ -98,8 +94,6 @@ define void @call_double(double* %p) { ; CHECK-NEXT: addq $32, %rsp ; CHECK-NEXT: popq %rsi ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc %v = call double @produce_double() store double %v, double* %p @@ -120,8 +114,6 @@ define void @call_float(float* %p) { ; CHECK-NEXT: addq $32, %rsp ; CHECK-NEXT: popq %rsi ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc %v = call float @produce_float() store float %v, float* %p diff --git a/llvm/test/CodeGen/X86/nomovtopush.ll b/llvm/test/CodeGen/X86/nomovtopush.ll index f690c2377ddf7..391cc3a16e793 100644 --- a/llvm/test/CodeGen/X86/nomovtopush.ll +++ b/llvm/test/CodeGen/X86/nomovtopush.ll @@ -45,13 +45,13 @@ entry: %2 = load i32, i32* @g_b, align 4, !tbaa !3 %3 = load i32, i32* @g_a, align 4, !tbaa !3 %call = tail call i32 @bar(i32 %3, i32 %2, i32 %1, i32 %0) #2 - tail call void @foo(%struct._param_str* byval nonnull align 4 @g_param) #2 + tail call void @foo(%struct._param_str* byval(%struct._param_str) nonnull align 4 @g_param) #2 ret i32 0 } declare dso_local i32 @bar(i32, i32, i32, i32) local_unnamed_addr -declare dso_local void @foo(%struct._param_str* byval align 4) local_unnamed_addr +declare dso_local void @foo(%struct._param_str* byval(%struct._param_str) align 4) local_unnamed_addr !3 = !{!4, !4, i64 0} !4 = !{!"int", !5, i64 0} diff --git a/llvm/test/CodeGen/X86/noreturn-call-linux.ll b/llvm/test/CodeGen/X86/noreturn-call-linux.ll index da46946903353..e7a3616212156 100644 --- a/llvm/test/CodeGen/X86/noreturn-call-linux.ll +++ b/llvm/test/CodeGen/X86/noreturn-call-linux.ll @@ -34,11 +34,11 @@ if.then: ; preds = %entry unreachable if.end: ; preds = %entry - call void @getbyval(%struct.ByVal* nonnull sret %agg.tmp) #4 + call void @getbyval(%struct.ByVal* nonnull sret(%struct.ByVal) %agg.tmp) #4 call void @make_push_unprofitable(%struct.ByVal* nonnull byval(%struct.ByVal) align 8 %agg.tmp) #4 - call void @getbyval(%struct.ByVal* nonnull sret %agg.tmp1) #4 + call void @getbyval(%struct.ByVal* nonnull sret(%struct.ByVal) %agg.tmp1) #4 call void @make_push_unprofitable(%struct.ByVal* nonnull byval(%struct.ByVal) align 8 %agg.tmp1) #4 - call void @getbyval(%struct.ByVal* nonnull sret %agg.tmp2) #4 + call void @getbyval(%struct.ByVal* nonnull sret(%struct.ByVal) %agg.tmp2) #4 call void @make_push_unprofitable(%struct.ByVal* nonnull byval(%struct.ByVal) align 8 %agg.tmp2) #4 ret i32 0 } @@ -55,5 +55,5 @@ declare dso_local void @exit_manyarg(i32, i32, i32, i32, i32, i32, i32, i32, i32 declare dso_local void @make_push_unprofitable(%struct.ByVal* byval(%struct.ByVal) align 8) -declare dso_local void @getbyval(%struct.ByVal* sret) +declare dso_local void @getbyval(%struct.ByVal* sret(%struct.ByVal)) diff --git a/llvm/test/CodeGen/X86/noreturn-call.ll b/llvm/test/CodeGen/X86/noreturn-call.ll index 6f877b6d1b8fa..13082c50bc4e7 100644 --- a/llvm/test/CodeGen/X86/noreturn-call.ll +++ b/llvm/test/CodeGen/X86/noreturn-call.ll @@ -72,11 +72,11 @@ if.then3: ; preds = %if.end unreachable if.end4: ; preds = %if.end - call void @getbyval(%struct.ByVal* nonnull sret %agg.tmp) + call void @getbyval(%struct.ByVal* nonnull sret(%struct.ByVal) %agg.tmp) call void @make_push_unprofitable(%struct.ByVal* nonnull byval(%struct.ByVal) align 4 %agg.tmp) - call void @getbyval(%struct.ByVal* nonnull sret %agg.tmp5) + call void @getbyval(%struct.ByVal* nonnull sret(%struct.ByVal) %agg.tmp5) call void @make_push_unprofitable(%struct.ByVal* nonnull byval(%struct.ByVal) align 4 %agg.tmp5) - call void @getbyval(%struct.ByVal* nonnull sret %agg.tmp6) + call void @getbyval(%struct.ByVal* nonnull sret(%struct.ByVal) %agg.tmp6) call void @make_push_unprofitable(%struct.ByVal* nonnull byval(%struct.ByVal) align 4 %agg.tmp6) ret i32 0 } @@ -101,4 +101,4 @@ declare dso_local x86_stdcallcc void @stdcall_abort(i32, i32) noreturn declare dso_local void @make_push_unprofitable(%struct.ByVal* byval(%struct.ByVal) align 4) -declare dso_local void @getbyval(%struct.ByVal* sret) +declare dso_local void @getbyval(%struct.ByVal* sret(%struct.ByVal)) diff --git a/llvm/test/CodeGen/X86/pic.ll b/llvm/test/CodeGen/X86/pic.ll index f03dc3f4a2855..1de4ca0059d0e 100644 --- a/llvm/test/CodeGen/X86/pic.ll +++ b/llvm/test/CodeGen/X86/pic.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -mcpu=generic -mtriple=i686-pc-linux-gnu -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX +; RUN: llc < %s -mcpu=generic -mtriple=i686-pc-linux-gnu -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false | FileCheck %s -check-prefixes=CHECK,CHECK-I686 +; RUN: llc < %s -mcpu=generic -mtriple=x86_64-pc-linux-gnux32 -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false | FileCheck %s -check-prefixes=CHECK,CHECK-X32 +; RUN: llc < %s -mcpu=generic -mtriple=x86_64-pc-linux-gnux32 -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false -fast-isel | FileCheck %s -check-prefixes=CHECK,CHECK-X32 @ptr = external global i32* @dst = external global i32 @@ -11,15 +13,19 @@ entry: store i32 %tmp.s, i32* @dst ret void -; LINUX-LABEL: test0: -; LINUX: calll .L0$pb -; LINUX-NEXT: .L0$pb: -; LINUX-NEXT: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L0$pb), -; LINUX: movl dst@GOT(%eax), -; LINUX: movl ptr@GOT(%eax), -; LINUX: movl src@GOT(%eax), -; LINUX: ret +; CHECK-LABEL: test0: +; CHECK-I686: calll .L0$pb +; CHECK-I686-NEXT: .L0$pb: +; CHECK-I686-NEXT: popl +; CHECK-I686: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L0$pb), +; CHECK-I686: movl dst@GOT(%eax), +; CHECK-I686: movl ptr@GOT(%eax), +; CHECK-I686: movl src@GOT(%eax), +; CHECK-I686: ret +; CHECK-X32-DAG: movl dst@GOTPCREL(%rip), +; CHECK-X32-DAG: movl ptr@GOTPCREL(%rip), +; CHECK-X32-DAG: movl src@GOTPCREL(%rip), +; CHECK-X32: retq } @ptr2 = global i32* null @@ -33,15 +39,19 @@ entry: store i32 %tmp.s, i32* @dst2 ret void -; LINUX-LABEL: test1: -; LINUX: calll .L1$pb -; LINUX-NEXT: .L1$pb: -; LINUX-NEXT: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L1$pb), %eax -; LINUX: movl dst2@GOT(%eax), -; LINUX: movl ptr2@GOT(%eax), -; LINUX: movl src2@GOT(%eax), -; LINUX: ret +; CHECK-LABEL: test1: +; CHECK-I686: calll .L1$pb +; CHECK-I686-NEXT: .L1$pb: +; CHECK-I686-NEXT: popl +; CHECK-I686: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L1$pb), %eax +; CHECK-I686: movl dst2@GOT(%eax), +; CHECK-I686: movl ptr2@GOT(%eax), +; CHECK-I686: movl src2@GOT(%eax), +; CHECK-I686: ret +; CHECK-X32-DAG: movl dst2@GOTPCREL(%rip), +; CHECK-X32-DAG: movl ptr2@GOTPCREL(%rip), +; CHECK-X32-DAG: movl src2@GOTPCREL(%rip), +; CHECK-X32: retq } @@ -51,18 +61,24 @@ define void @test2() nounwind { entry: %ptr = call i8* @malloc(i32 40) ret void -; LINUX-LABEL: test2: -; LINUX: pushl %ebx -; LINUX-NEXT: subl $8, %esp -; LINUX-NEXT: calll .L2$pb -; LINUX-NEXT: .L2$pb: -; LINUX-NEXT: popl %ebx -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L2$pb), %ebx -; LINUX: movl $40, (%esp) -; LINUX: calll malloc@PLT -; LINUX: addl $8, %esp -; LINUX: popl %ebx -; LINUX: ret +; CHECK-LABEL: test2: +; CHECK-I686: pushl %ebx +; CHECK-I686-NEXT: subl $8, %esp +; CHECK-I686-NEXT: calll .L2$pb +; CHECK-I686-NEXT: .L2$pb: +; CHECK-I686-NEXT: popl %ebx +; CHECK-I686: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L2$pb), %ebx +; CHECK-I686: movl $40, (%esp) +; CHECK-I686: calll malloc@PLT +; CHECK-I686: addl $8, %esp +; CHECK-I686: popl %ebx +; CHECK-I686: ret +; CHECK-X32: pushq %rax +; CHECK-X32: movl $40, %edi +; CHECK-X32: callq malloc@PLT +; CHECK-X32: popq %rax +; CHECK-X32: retq + } @pfoo = external global void(...)* @@ -74,14 +90,17 @@ entry: %tmp1 = load void(...)*, void(...)** @pfoo call void(...) %tmp1() ret void -; LINUX-LABEL: test3: -; LINUX: calll .L3$pb -; LINUX-NEXT: .L3$pb: -; LINUX: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), %[[REG3:e..]] -; LINUX: calll afoo@PLT -; LINUX: movl pfoo@GOT(%[[REG3]]), -; LINUX: calll * +; CHECK-LABEL: test3: +; CHECK-I686: calll .L3$pb +; CHECK-I686-NEXT: .L3$pb: +; CHECK-I686: popl +; CHECK-I686: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), %[[REG3:e..]] +; CHECK-I686: calll afoo@PLT +; CHECK-I686: movl pfoo@GOT(%[[REG3]]), +; CHECK-I686: calll * +; CHECK-X32: callq afoo@PLT +; CHECK-X32: movl pfoo@GOTPCREL(%rip), +; CHECK-X32: callq * } declare void(...)* @afoo(...) @@ -90,11 +109,13 @@ define void @test4() nounwind { entry: call void(...) @foo() ret void -; LINUX-LABEL: test4: -; LINUX: calll .L4$pb -; LINUX: popl %ebx -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), %ebx -; LINUX: calll foo@PLT +; CHECK-LABEL: test4: +; CHECK-I686: calll .L4$pb +; CHECK-I686: popl %ebx +; CHECK-I686: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), %ebx +; CHECK-I686: calll foo@PLT +; CHECK-X32: callq foo@PLT + } declare void @foo(...) @@ -111,16 +132,21 @@ entry: store i32 %tmp.s, i32* @dst6 ret void -; LINUX-LABEL: test5: -; LINUX: calll .L5$pb -; LINUX-NEXT: .L5$pb: -; LINUX-NEXT: popl %eax -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L5$pb), %eax -; LINUX: leal dst6@GOTOFF(%eax), %ecx -; LINUX: movl %ecx, ptr6@GOTOFF(%eax) -; LINUX: movl src6@GOTOFF(%eax), %ecx -; LINUX: movl %ecx, dst6@GOTOFF(%eax) -; LINUX: ret +; CHECK-LABEL: test5: +; CHECK-I686: calll .L5$pb +; CHECK-I686-NEXT: .L5$pb: +; CHECK-I686-NEXT: popl %eax +; CHECK-I686: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L5$pb), %eax +; CHECK-I686: leal dst6@GOTOFF(%eax), %ecx +; CHECK-I686: movl %ecx, ptr6@GOTOFF(%eax) +; CHECK-I686: movl src6@GOTOFF(%eax), %ecx +; CHECK-I686: movl %ecx, dst6@GOTOFF(%eax) +; CHECK-I686: ret +; CHECK-X32: leal dst6(%rip), %eax +; CHECK-X32: movl %eax, ptr6(%rip) +; CHECK-X32: movl src6(%rip), %eax +; CHECK-X32: movl %eax, dst6(%rip) +; CHECK-X32: retq } @@ -131,13 +157,14 @@ entry: %retval = select i1 %tmp, double 4.561230e+02, double 1.234560e+02 ret double %retval -; LINUX: .LCPI6_0: +; CHECK: .LCPI6_0: -; LINUX-LABEL: test6: -; LINUX: calll .L6$pb -; LINUX: .L6$pb: -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb), -; LINUX: fldl .LCPI6_0@GOTOFF( +; CHECK-LABEL: test6: +; CHECK-I686: calll .L6$pb +; CHECK-I686: .L6$pb: +; CHECK-I686: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb), +; CHECK-I686: fldl .LCPI6_0@GOTOFF( +; CHECK-X32: .LCPI6_0(%rip), } @@ -185,22 +212,38 @@ bb12: tail call void(...) @foo6() ret void -; LINUX-LABEL: test7: -; LINUX: calll .L7$pb -; LINUX: .L7$pb: -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb), -; LINUX: .LJTI7_0@GOTOFF( -; LINUX: jmpl * - -; LINUX: .p2align 2 -; LINUX-NEXT: .LJTI7_0: -; LINUX: .long .LBB7_2@GOTOFF -; LINUX: .long .LBB7_8@GOTOFF -; LINUX: .long .LBB7_4@GOTOFF -; LINUX: .long .LBB7_6@GOTOFF -; LINUX: .long .LBB7_5@GOTOFF -; LINUX: .long .LBB7_8@GOTOFF -; LINUX: .long .LBB7_7@GOTOFF +; CHECK-LABEL: test7: +; CHECK-I686: calll .L7$pb +; CHECK-I686: .L7$pb: +; CHECK-I686: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb), +; CHECK-I686: .LJTI7_0@GOTOFF( +; CHECK-I686: jmpl * +; CHECK-X32: leal .LJTI7_0(%rip), %eax +; CHECK-X32: addl (%eax,%edi,4), %eax +; CHECK-X32: jmpq *%rax + +; CHECK: .p2align 2 +; CHECK-NEXT: .LJTI7_0: +; CHECK-I686: .long .LBB7_2@GOTOFF +; CHECK-I686: .long .LBB7_8@GOTOFF +; CHECK-I686: .long .LBB7_4@GOTOFF +; CHECK-I686: .long .LBB7_6@GOTOFF +; CHECK-I686: .long .LBB7_5@GOTOFF +; CHECK-I686: .long .LBB7_8@GOTOFF +; CHECK-I686: .long .LBB7_7@GOTOFF +; CHECK-X32: .long .LBB7_3-.LJTI7_0 +; CHECK-X32: .long .LBB7_3-.LJTI7_0 +; CHECK-X32: .long .LBB7_12-.LJTI7_0 +; CHECK-X32: .long .LBB7_8-.LJTI7_0 +; CHECK-X32: .long .LBB7_12-.LJTI7_0 +; CHECK-X32: .long .LBB7_10-.LJTI7_0 +; CHECK-X32: .long .LBB7_8-.LJTI7_0 +; CHECK-X32: .long .LBB7_9-.LJTI7_0 +; CHECK-X32: .long .LBB7_10-.LJTI7_0 +; CHECK-X32: .long .LBB7_9-.LJTI7_0 +; CHECK-X32: .long .LBB7_12-.LJTI7_0 +; CHECK-X32: .long .LBB7_14-.LJTI7_0 +; CHECK-X32: .long .LBB7_14-.LJTI7_0 } declare void @foo1(...) diff --git a/llvm/test/CodeGen/X86/poison-ops.ll b/llvm/test/CodeGen/X86/poison-ops.ll new file mode 100644 index 0000000000000..3cd2ceb125ce8 --- /dev/null +++ b/llvm/test/CodeGen/X86/poison-ops.ll @@ -0,0 +1,458 @@ +; NOTE: This test case is borrowed from undef-ops.ll +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s + +define i32 @add_poison_rhs(i32 %x) { +; CHECK-LABEL: add_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = add i32 %x, poison + ret i32 %r +} + +define <4 x i32> @add_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: add_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = add <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @add_poison_lhs(i32 %x) { +; CHECK-LABEL: add_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = add i32 poison, %x + ret i32 %r +} + +define <4 x i32> @add_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: add_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = add <4 x i32> poison, %x + ret <4 x i32> %r +} + +define i32 @sub_poison_rhs(i32 %x) { +; CHECK-LABEL: sub_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = sub i32 %x, poison + ret i32 %r +} + +define <4 x i32> @sub_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: sub_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = sub <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @sub_poison_lhs(i32 %x) { +; CHECK-LABEL: sub_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = sub i32 poison, %x + ret i32 %r +} + +define <4 x i32> @sub_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: sub_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = sub <4 x i32> poison, %x + ret <4 x i32> %r +} + +define i32 @mul_poison_rhs(i32 %x) { +; CHECK-LABEL: mul_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %r = mul i32 %x, poison + ret i32 %r +} + +define <4 x i32> @mul_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: mul_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = mul <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @mul_poison_lhs(i32 %x) { +; CHECK-LABEL: mul_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %r = mul i32 poison, %x + ret i32 %r +} + +define <4 x i32> @mul_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: mul_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = mul <4 x i32> poison, %x + ret <4 x i32> %r +} + +define i32 @sdiv_poison_rhs(i32 %x) { +; CHECK-LABEL: sdiv_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = sdiv i32 %x, poison + ret i32 %r +} + +define <4 x i32> @sdiv_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: sdiv_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = sdiv <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @sdiv_poison_lhs(i32 %x) { +; CHECK-LABEL: sdiv_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %r = sdiv i32 poison, %x + ret i32 %r +} + +define <4 x i32> @sdiv_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: sdiv_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = sdiv <4 x i32> poison, %x + ret <4 x i32> %r +} + +define i32 @udiv_poison_rhs(i32 %x) { +; CHECK-LABEL: udiv_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = udiv i32 %x, poison + ret i32 %r +} + +define <4 x i32> @udiv_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: udiv_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = udiv <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @udiv_poison_lhs(i32 %x) { +; CHECK-LABEL: udiv_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %r = udiv i32 poison, %x + ret i32 %r +} + +define <4 x i32> @udiv_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: udiv_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = udiv <4 x i32> poison, %x + ret <4 x i32> %r +} + +define i32 @srem_poison_rhs(i32 %x) { +; CHECK-LABEL: srem_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = srem i32 %x, poison + ret i32 %r +} + +define <4 x i32> @srem_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: srem_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = srem <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @srem_poison_lhs(i32 %x) { +; CHECK-LABEL: srem_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %r = srem i32 poison, %x + ret i32 %r +} + +define <4 x i32> @srem_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: srem_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = srem <4 x i32> poison, %x + ret <4 x i32> %r +} + +define i32 @urem_poison_rhs(i32 %x) { +; CHECK-LABEL: urem_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = urem i32 %x, poison + ret i32 %r +} + +define <4 x i32> @urem_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: urem_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = urem <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @urem_poison_lhs(i32 %x) { +; CHECK-LABEL: urem_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %r = urem i32 poison, %x + ret i32 %r +} + +define <4 x i32> @urem_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: urem_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = urem <4 x i32> poison, %x + ret <4 x i32> %r +} + +define i32 @ashr_poison_rhs(i32 %x) { +; CHECK-LABEL: ashr_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = ashr i32 %x, poison + ret i32 %r +} + +define <4 x i32> @ashr_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: ashr_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = ashr <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @ashr_poison_lhs(i32 %x) { +; CHECK-LABEL: ashr_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %r = ashr i32 poison, %x + ret i32 %r +} + +define <4 x i32> @ashr_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: ashr_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = ashr <4 x i32> poison, %x + ret <4 x i32> %r +} + +define i32 @lshr_poison_rhs(i32 %x) { +; CHECK-LABEL: lshr_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = lshr i32 %x, poison + ret i32 %r +} + +define <4 x i32> @lshr_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: lshr_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = lshr <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @lshr_poison_lhs(i32 %x) { +; CHECK-LABEL: lshr_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %r = lshr i32 poison, %x + ret i32 %r +} + +define <4 x i32> @lshr_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: lshr_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = lshr <4 x i32> poison, %x + ret <4 x i32> %r +} + +define i32 @shl_poison_rhs(i32 %x) { +; CHECK-LABEL: shl_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = shl i32 %x, poison + ret i32 %r +} + +define <4 x i32> @shl_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: shl_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = shl <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @shl_poison_lhs(i32 %x) { +; CHECK-LABEL: shl_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %r = shl i32 poison, %x + ret i32 %r +} + +define <4 x i32> @shl_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: shl_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = shl <4 x i32> poison, %x + ret <4 x i32> %r +} + +define i32 @and_poison_rhs(i32 %x) { +; CHECK-LABEL: and_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %r = and i32 %x, poison + ret i32 %r +} + +define <4 x i32> @and_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: and_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = and <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @and_poison_lhs(i32 %x) { +; CHECK-LABEL: and_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %r = and i32 poison, %x + ret i32 %r +} + +define <4 x i32> @and_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: and_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: xorps %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = and <4 x i32> poison, %x + ret <4 x i32> %r +} + +define i32 @or_poison_rhs(i32 %x) { +; CHECK-LABEL: or_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: movl $-1, %eax +; CHECK-NEXT: retq + %r = or i32 %x, poison + ret i32 %r +} + +define <4 x i32> @or_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: or_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = or <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @or_poison_lhs(i32 %x) { +; CHECK-LABEL: or_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: movl $-1, %eax +; CHECK-NEXT: retq + %r = or i32 poison, %x + ret i32 %r +} + +define <4 x i32> @or_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: or_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 +; CHECK-NEXT: retq + %r = or <4 x i32> poison, %x + ret <4 x i32> %r +} + +define i32 @xor_poison_rhs(i32 %x) { +; CHECK-LABEL: xor_poison_rhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = xor i32 %x, poison + ret i32 %r +} + +define <4 x i32> @xor_poison_rhs_vec(<4 x i32> %x) { +; CHECK-LABEL: xor_poison_rhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = xor <4 x i32> %x, poison + ret <4 x i32> %r +} + +define i32 @xor_poison_lhs(i32 %x) { +; CHECK-LABEL: xor_poison_lhs: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = xor i32 poison, %x + ret i32 %r +} + +define <4 x i32> @xor_poison_lhs_vec(<4 x i32> %x) { +; CHECK-LABEL: xor_poison_lhs_vec: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %r = xor <4 x i32> poison, %x + ret <4 x i32> %r +} + +; This would crash because the shift amount is an i8 operand, +; but the result of the shift is i32. We can't just propagate +; the existing poison as the result. + +define i1 @poison_operand_size_not_same_as_result() { +; CHECK-LABEL: poison_operand_size_not_same_as_result: +; CHECK: # %bb.0: +; CHECK-NEXT: retq + %sh = shl i32 7, poison + %cmp = icmp eq i32 0, %sh + ret i1 %cmp +} + diff --git a/llvm/test/CodeGen/X86/pr2656.ll b/llvm/test/CodeGen/X86/pr2656.ll index e86f55b1521c2..d4ab0b4d074bb 100644 --- a/llvm/test/CodeGen/X86/pr2656.ll +++ b/llvm/test/CodeGen/X86/pr2656.ll @@ -13,7 +13,7 @@ target triple = "i686-apple-darwin9.4.0" ; We can fold the 16-byte constant load into either 'xor' instruction, ; but we do not. It has more than one use, so it gets loaded into a register. -define void @foo(%struct.anon* byval %p) nounwind { +define void @foo(%struct.anon* byval(%struct.anon) %p) nounwind { ; CHECK-LABEL: foo: ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: subl $28, %esp diff --git a/llvm/test/CodeGen/X86/pr30290.ll b/llvm/test/CodeGen/X86/pr30290.ll index 12b3a88eafe78..5c0118a070186 100644 --- a/llvm/test/CodeGen/X86/pr30290.ll +++ b/llvm/test/CodeGen/X86/pr30290.ll @@ -12,10 +12,10 @@ target triple = "x86_64-pc-linux-gnu" %struct.face = type { [7 x i32] } ; Function Attrs: noinline nounwind uwtable -declare void @bar(%struct.face* byval nocapture readonly align 8); +declare void @bar(%struct.face* byval(%struct.face) nocapture readonly align 8); ; Function Attrs: noinline nounwind uwtable -define void @foo(%struct.face* byval nocapture align 8) local_unnamed_addr { +define void @foo(%struct.face* byval(%struct.face) nocapture align 8) local_unnamed_addr { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: ; CHECK-NEXT: subq $40, %rsp @@ -35,6 +35,6 @@ define void @foo(%struct.face* byval nocapture align 8) local_unnamed_addr { store <4 x i32> , <4 x i32>* %2, align 8 %3 = getelementptr inbounds %struct.face, %struct.face* %0, i64 0, i32 0, i64 4 store i32 1, i32* %3, align 8 - call void @bar(%struct.face* byval nonnull align 8 %0) + call void @bar(%struct.face* byval(%struct.face) nonnull align 8 %0) ret void } diff --git a/llvm/test/CodeGen/X86/pr32241.ll b/llvm/test/CodeGen/X86/pr32241.ll index 6fb770b4a75e7..186839e65e072 100644 --- a/llvm/test/CodeGen/X86/pr32241.ll +++ b/llvm/test/CodeGen/X86/pr32241.ll @@ -11,8 +11,8 @@ define i32 @_Z3foov() { ; CHECK-NEXT: movw $19417, {{[0-9]+}}(%esp) # imm = 0x4BD9 ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; CHECK-NEXT: cmpw $0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: cmpw $0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill ; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: # %bb.1: # %lor.rhs @@ -28,10 +28,10 @@ define i32 @_Z3foov() { ; CHECK-NEXT: cmpl %ecx, %eax ; CHECK-NEXT: setl %al ; CHECK-NEXT: andb $1, %al -; CHECK-NEXT: movzbl %al, %eax -; CHECK-NEXT: xorl $-1, %eax -; CHECK-NEXT: cmpl $0, %eax +; CHECK-NEXT: movzbl %al, %ecx +; CHECK-NEXT: xorl $-1, %ecx ; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: cmpl $0, %ecx ; CHECK-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill ; CHECK-NEXT: jne .LBB0_4 ; CHECK-NEXT: # %bb.3: # %lor.rhs4 diff --git a/llvm/test/CodeGen/X86/pr32256.ll b/llvm/test/CodeGen/X86/pr32256.ll index e898295634a1c..2d2c1bd882a4a 100644 --- a/llvm/test/CodeGen/X86/pr32256.ll +++ b/llvm/test/CodeGen/X86/pr32256.ll @@ -9,10 +9,10 @@ define void @_Z1av() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subl $2, %esp ; CHECK-NEXT: .cfi_def_cfa_offset 6 -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: movb c, %cl ; CHECK-NEXT: xorb $-1, %cl +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: testb $1, %cl ; CHECK-NEXT: movb %al, (%esp) # 1-byte Spill ; CHECK-NEXT: jne .LBB0_1 diff --git a/llvm/test/CodeGen/X86/pr32284.ll b/llvm/test/CodeGen/X86/pr32284.ll index cb9b33ca907b8..69c8adf0eb4d0 100644 --- a/llvm/test/CodeGen/X86/pr32284.ll +++ b/llvm/test/CodeGen/X86/pr32284.ll @@ -9,12 +9,12 @@ define void @foo() { ; X86-O0-LABEL: foo: ; X86-O0: # %bb.0: # %entry +; X86-O0-NEXT: movzbl c, %ecx +; X86-O0-NEXT: xorl %eax, %eax +; X86-O0-NEXT: subl %ecx, %eax +; X86-O0-NEXT: movslq %eax, %rcx ; X86-O0-NEXT: xorl %eax, %eax ; X86-O0-NEXT: # kill: def $rax killed $eax -; X86-O0-NEXT: xorl %ecx, %ecx -; X86-O0-NEXT: movzbl c, %edx -; X86-O0-NEXT: subl %edx, %ecx -; X86-O0-NEXT: movslq %ecx, %rcx ; X86-O0-NEXT: subq %rcx, %rax ; X86-O0-NEXT: # kill: def $al killed $al killed $rax ; X86-O0-NEXT: cmpb $0, %al diff --git a/llvm/test/CodeGen/X86/pr32340.ll b/llvm/test/CodeGen/X86/pr32340.ll index 15774d605e62f..0e934dbe26d40 100644 --- a/llvm/test/CodeGen/X86/pr32340.ll +++ b/llvm/test/CodeGen/X86/pr32340.ll @@ -13,34 +13,34 @@ define void @foo() { ; X64-LABEL: foo: ; X64: # %bb.0: # %entry -; X64-NEXT: xorl %eax, %eax -; X64-NEXT: # kill: def $rax killed $eax ; X64-NEXT: movw $0, var_825 -; X64-NEXT: movzwl var_32, %edx -; X64-NEXT: movzwl var_901, %ecx -; X64-NEXT: movl %edx, %esi -; X64-NEXT: xorl %ecx, %esi -; X64-NEXT: movl %edx, %ecx -; X64-NEXT: xorl %esi, %ecx -; X64-NEXT: addl %edx, %ecx -; X64-NEXT: movslq %ecx, %rcx -; X64-NEXT: movq %rcx, var_826 ; X64-NEXT: movzwl var_32, %ecx -; X64-NEXT: # kill: def $rcx killed $ecx -; X64-NEXT: movzwl var_901, %edx -; X64-NEXT: xorl $51981, %edx # imm = 0xCB0D -; X64-NEXT: movslq %edx, %rsi -; X64-NEXT: movabsq $-1142377792914660288, %rdx # imm = 0xF02575732E06E440 -; X64-NEXT: xorq %rdx, %rsi -; X64-NEXT: movq %rcx, %rdx -; X64-NEXT: xorq %rsi, %rdx -; X64-NEXT: xorq $-1, %rdx +; X64-NEXT: movzwl var_901, %eax +; X64-NEXT: movl %ecx, %edx +; X64-NEXT: xorl %eax, %edx +; X64-NEXT: movl %ecx, %eax +; X64-NEXT: xorl %edx, %eax +; X64-NEXT: addl %ecx, %eax +; X64-NEXT: cltq +; X64-NEXT: movq %rax, var_826 +; X64-NEXT: movzwl var_32, %eax +; X64-NEXT: # kill: def $rax killed $eax +; X64-NEXT: movzwl var_901, %ecx +; X64-NEXT: xorl $51981, %ecx # imm = 0xCB0D +; X64-NEXT: movslq %ecx, %rdx +; X64-NEXT: movabsq $-1142377792914660288, %rcx # imm = 0xF02575732E06E440 +; X64-NEXT: xorq %rcx, %rdx +; X64-NEXT: movq %rax, %rcx ; X64-NEXT: xorq %rdx, %rcx -; X64-NEXT: movq %rcx, %rdx -; X64-NEXT: orq var_57, %rdx -; X64-NEXT: orq %rdx, %rcx -; X64-NEXT: # kill: def $cx killed $cx killed $rcx -; X64-NEXT: movw %cx, var_900 +; X64-NEXT: xorq $-1, %rcx +; X64-NEXT: xorq %rcx, %rax +; X64-NEXT: movq %rax, %rcx +; X64-NEXT: orq var_57, %rcx +; X64-NEXT: orq %rcx, %rax +; X64-NEXT: # kill: def $ax killed $ax killed $rax +; X64-NEXT: movw %ax, var_900 +; X64-NEXT: xorl %eax, %eax +; X64-NEXT: # kill: def $rax killed $eax ; X64-NEXT: cmpq var_28, %rax ; X64-NEXT: setne %al ; X64-NEXT: andb $1, %al diff --git a/llvm/test/CodeGen/X86/pr38865-2.ll b/llvm/test/CodeGen/X86/pr38865-2.ll index ab2e3e34e5f25..a574696f98a41 100644 --- a/llvm/test/CodeGen/X86/pr38865-2.ll +++ b/llvm/test/CodeGen/X86/pr38865-2.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" %struct.a = type { i8 } -define void @_Z1bv(%struct.a* noalias sret %agg.result) { +define void @_Z1bv(%struct.a* noalias sret(%struct.a) %agg.result) { ; CHECK-LABEL: _Z1bv: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pushq %rax @@ -18,6 +18,6 @@ define void @_Z1bv(%struct.a* noalias sret %agg.result) { ; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: retq entry: - call void @_Z1bv(%struct.a* sret %agg.result) + call void @_Z1bv(%struct.a* sret(%struct.a) %agg.result) ret void } diff --git a/llvm/test/CodeGen/X86/pr38865.ll b/llvm/test/CodeGen/X86/pr38865.ll index 1fa59aeadec32..5a85ed42bf3e9 100644 --- a/llvm/test/CodeGen/X86/pr38865.ll +++ b/llvm/test/CodeGen/X86/pr38865.ll @@ -38,10 +38,10 @@ entry: %byval-temp = alloca %struct.a, align 8 %0 = bitcast %struct.a* %byval-temp to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* nonnull align 8 %0, i8* align 4 bitcast (%struct.a* @c to i8*), i32 260, i1 false) - call void @d(%struct.a* byval nonnull align 8 %byval-temp) + call void @d(%struct.a* byval(%struct.a) nonnull align 8 %byval-temp) ret void } -declare void @d(%struct.a* byval align 8) local_unnamed_addr #1 +declare void @d(%struct.a* byval(%struct.a) align 8) local_unnamed_addr #1 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) diff --git a/llvm/test/CodeGen/X86/pr44749.ll b/llvm/test/CodeGen/X86/pr44749.ll index daf7e25884a46..7f3db698ed69f 100644 --- a/llvm/test/CodeGen/X86/pr44749.ll +++ b/llvm/test/CodeGen/X86/pr44749.ll @@ -6,8 +6,6 @@ define i32 @a() { ; CHECK: ## %bb.0: ## %entry ; CHECK-NEXT: pushq %rax ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: ## kill: def $al killed $al killed $eax ; CHECK-NEXT: callq _b diff --git a/llvm/test/CodeGen/X86/preallocated.ll b/llvm/test/CodeGen/X86/preallocated.ll index 8de69883e091e..4b6bdbb6fb7dd 100644 --- a/llvm/test/CodeGen/X86/preallocated.ll +++ b/llvm/test/CodeGen/X86/preallocated.ll @@ -107,7 +107,7 @@ define void @one_preallocated_one_normal() { ret void } -declare void @foo_ret_p(%Foo* sret, %Foo* preallocated(%Foo)) +declare void @foo_ret_p(%Foo* sret(%Foo), %Foo* preallocated(%Foo)) define void @nested_with_init() { ; CHECK-LABEL: _nested_with_init: diff --git a/llvm/test/CodeGen/X86/sat-add.ll b/llvm/test/CodeGen/X86/sat-add.ll index 53df6d440830b..1dae100e0994f 100644 --- a/llvm/test/CodeGen/X86/sat-add.ll +++ b/llvm/test/CodeGen/X86/sat-add.ll @@ -1,6 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=ANY,SSE2 -; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=ANY,SSE41 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=ANY,SSE,SSE2 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=ANY,SSE,SSE4,SSE41 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.2 | FileCheck %s --check-prefixes=ANY,SSE,SSE4,SSE42 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=ANY,AVX,AVX2 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl | FileCheck %s --check-prefixes=ANY,AVX,AVX512 ; There are at least 3 potential patterns corresponding to an unsigned saturated add: min, cmp with sum, cmp with not. ; Test each of those patterns with i8/i16/i32/i64. @@ -359,11 +362,17 @@ define i64 @unsigned_sat_variable_i64_using_cmp_notval(i64 %x, i64 %y) { } define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) { -; ANY-LABEL: unsigned_sat_constant_v16i8_using_min: -; ANY: # %bb.0: -; ANY-NEXT: pminub {{.*}}(%rip), %xmm0 -; ANY-NEXT: paddb {{.*}}(%rip), %xmm0 -; ANY-NEXT: retq +; SSE-LABEL: unsigned_sat_constant_v16i8_using_min: +; SSE: # %bb.0: +; SSE-NEXT: pminub {{.*}}(%rip), %xmm0 +; SSE-NEXT: paddb {{.*}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: unsigned_sat_constant_v16i8_using_min: +; AVX: # %bb.0: +; AVX-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: retq %c = icmp ult <16 x i8> %x, %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %r = add <16 x i8> %s, @@ -371,10 +380,24 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) { } define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) { -; ANY-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum: -; ANY: # %bb.0: -; ANY-NEXT: paddusb {{.*}}(%rip), %xmm0 -; ANY-NEXT: retq +; SSE-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum: +; SSE: # %bb.0: +; SSE-NEXT: paddusb {{.*}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum: +; AVX2: # %bb.0: +; AVX2-NEXT: vpaddusb {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm1 +; AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm2 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vpternlogq $222, %xmm2, %xmm1, %xmm0 +; AVX512-NEXT: retq %a = add <16 x i8> %x, %c = icmp ugt <16 x i8> %x, %a %r = select <16 x i1> %c, <16 x i8> , <16 x i8> %a @@ -382,10 +405,23 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) { } define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) { -; ANY-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval: -; ANY: # %bb.0: -; ANY-NEXT: paddusb {{.*}}(%rip), %xmm0 -; ANY-NEXT: retq +; SSE-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval: +; SSE: # %bb.0: +; SSE-NEXT: paddusb {{.*}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval: +; AVX2: # %bb.0: +; AVX2-NEXT: vpaddusb {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm1 +; AVX512-NEXT: vpmaxub {{.*}}(%rip), %xmm0, %xmm2 +; AVX512-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0 +; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq %a = add <16 x i8> %x, %c = icmp ugt <16 x i8> %x, %r = select <16 x i1> %c, <16 x i8> , <16 x i8> %a @@ -401,11 +437,17 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) { ; SSE2-NEXT: paddw {{.*}}(%rip), %xmm0 ; SSE2-NEXT: retq ; -; SSE41-LABEL: unsigned_sat_constant_v8i16_using_min: -; SSE41: # %bb.0: -; SSE41-NEXT: pminuw {{.*}}(%rip), %xmm0 -; SSE41-NEXT: paddw {{.*}}(%rip), %xmm0 -; SSE41-NEXT: retq +; SSE4-LABEL: unsigned_sat_constant_v8i16_using_min: +; SSE4: # %bb.0: +; SSE4-NEXT: pminuw {{.*}}(%rip), %xmm0 +; SSE4-NEXT: paddw {{.*}}(%rip), %xmm0 +; SSE4-NEXT: retq +; +; AVX-LABEL: unsigned_sat_constant_v8i16_using_min: +; AVX: # %bb.0: +; AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: retq %c = icmp ult <8 x i16> %x, %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %r = add <8 x i16> %s, @@ -413,10 +455,24 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) { } define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) { -; ANY-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum: -; ANY: # %bb.0: -; ANY-NEXT: paddusw {{.*}}(%rip), %xmm0 -; ANY-NEXT: retq +; SSE-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum: +; SSE: # %bb.0: +; SSE-NEXT: paddusw {{.*}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum: +; AVX2: # %bb.0: +; AVX2-NEXT: vpaddusw {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm1 +; AVX512-NEXT: vpminuw %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm2 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vpternlogq $222, %xmm2, %xmm1, %xmm0 +; AVX512-NEXT: retq %a = add <8 x i16> %x, %c = icmp ugt <8 x i16> %x, %a %r = select <8 x i1> %c, <8 x i16> , <8 x i16> %a @@ -424,10 +480,23 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) { } define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) { -; ANY-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval: -; ANY: # %bb.0: -; ANY-NEXT: paddusw {{.*}}(%rip), %xmm0 -; ANY-NEXT: retq +; SSE-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval: +; SSE: # %bb.0: +; SSE-NEXT: paddusw {{.*}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval: +; AVX2: # %bb.0: +; AVX2-NEXT: vpaddusw {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm1 +; AVX512-NEXT: vpmaxuw {{.*}}(%rip), %xmm0, %xmm2 +; AVX512-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm0 +; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq %a = add <8 x i16> %x, %c = icmp ugt <8 x i16> %x, %r = select <8 x i1> %c, <8 x i16> , <8 x i16> %a @@ -447,11 +516,25 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) { ; SSE2-NEXT: paddd {{.*}}(%rip), %xmm0 ; SSE2-NEXT: retq ; -; SSE41-LABEL: unsigned_sat_constant_v4i32_using_min: -; SSE41: # %bb.0: -; SSE41-NEXT: pminud {{.*}}(%rip), %xmm0 -; SSE41-NEXT: paddd {{.*}}(%rip), %xmm0 -; SSE41-NEXT: retq +; SSE4-LABEL: unsigned_sat_constant_v4i32_using_min: +; SSE4: # %bb.0: +; SSE4-NEXT: pminud {{.*}}(%rip), %xmm0 +; SSE4-NEXT: paddd {{.*}}(%rip), %xmm0 +; SSE4-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_constant_v4i32_using_min: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294967253,4294967253,4294967253,4294967253] +; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [42,42,42,42] +; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_constant_v4i32_using_min: +; AVX512: # %bb.0: +; AVX512-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm0 +; AVX512-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0 +; AVX512-NEXT: retq %c = icmp ult <4 x i32> %x, %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %r = add <4 x i32> %s, @@ -470,18 +553,38 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) { ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: retq ; -; SSE41-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum: -; SSE41: # %bb.0: -; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [42,42,42,42] -; SSE41-NEXT: paddd %xmm0, %xmm2 -; SSE41-NEXT: movdqa %xmm0, %xmm1 -; SSE41-NEXT: pminud %xmm2, %xmm1 -; SSE41-NEXT: pcmpeqd %xmm0, %xmm1 -; SSE41-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE41-NEXT: pxor %xmm0, %xmm1 -; SSE41-NEXT: por %xmm2, %xmm1 -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: retq +; SSE4-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum: +; SSE4: # %bb.0: +; SSE4-NEXT: movdqa {{.*#+}} xmm2 = [42,42,42,42] +; SSE4-NEXT: paddd %xmm0, %xmm2 +; SSE4-NEXT: movdqa %xmm0, %xmm1 +; SSE4-NEXT: pminud %xmm2, %xmm1 +; SSE4-NEXT: pcmpeqd %xmm0, %xmm1 +; SSE4-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE4-NEXT: pxor %xmm0, %xmm1 +; SSE4-NEXT: por %xmm2, %xmm1 +; SSE4-NEXT: movdqa %xmm1, %xmm0 +; SSE4-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [42,42,42,42] +; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1 +; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm2 +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm1 +; AVX512-NEXT: vpcmpnleud %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa32 %xmm0, %xmm1 {%k1} +; AVX512-NEXT: vmovdqa %xmm1, %xmm0 +; AVX512-NEXT: retq %a = add <4 x i32> %x, %c = icmp ugt <4 x i32> %x, %a %r = select <4 x i1> %c, <4 x i32> , <4 x i32> %a @@ -498,15 +601,34 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) { ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: retq ; -; SSE41-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval: -; SSE41: # %bb.0: -; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [42,42,42,42] -; SSE41-NEXT: paddd %xmm0, %xmm1 -; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [4294967254,4294967254,4294967254,4294967254] -; SSE41-NEXT: pmaxud %xmm0, %xmm2 -; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 -; SSE41-NEXT: por %xmm1, %xmm0 -; SSE41-NEXT: retq +; SSE4-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval: +; SSE4: # %bb.0: +; SSE4-NEXT: movdqa {{.*#+}} xmm1 = [42,42,42,42] +; SSE4-NEXT: paddd %xmm0, %xmm1 +; SSE4-NEXT: movdqa {{.*#+}} xmm2 = [4294967254,4294967254,4294967254,4294967254] +; SSE4-NEXT: pmaxud %xmm0, %xmm2 +; SSE4-NEXT: pcmpeqd %xmm2, %xmm0 +; SSE4-NEXT: por %xmm1, %xmm0 +; SSE4-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [42,42,42,42] +; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1 +; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [4294967254,4294967254,4294967254,4294967254] +; AVX2-NEXT: vpmaxud %xmm2, %xmm0, %xmm2 +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm1 +; AVX512-NEXT: vpcmpnleud {{.*}}(%rip){1to4}, %xmm0, %k1 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa32 %xmm0, %xmm1 {%k1} +; AVX512-NEXT: vmovdqa %xmm1, %xmm0 +; AVX512-NEXT: retq %a = add <4 x i32> %x, %c = icmp ugt <4 x i32> %x, %r = select <4 x i1> %c, <4 x i32> , <4 x i32> %a @@ -523,15 +645,32 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat(<4 x i32 ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: retq ; -; SSE41-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat: -; SSE41: # %bb.0: -; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [43,44,45,46] -; SSE41-NEXT: paddd %xmm0, %xmm1 -; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [4294967253,4294967252,4294967251,4294967250] -; SSE41-NEXT: pmaxud %xmm0, %xmm2 -; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 -; SSE41-NEXT: por %xmm1, %xmm0 -; SSE41-NEXT: retq +; SSE4-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat: +; SSE4: # %bb.0: +; SSE4-NEXT: movdqa {{.*#+}} xmm1 = [43,44,45,46] +; SSE4-NEXT: paddd %xmm0, %xmm1 +; SSE4-NEXT: movdqa {{.*#+}} xmm2 = [4294967253,4294967252,4294967251,4294967250] +; SSE4-NEXT: pmaxud %xmm0, %xmm2 +; SSE4-NEXT: pcmpeqd %xmm2, %xmm0 +; SSE4-NEXT: por %xmm1, %xmm0 +; SSE4-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat: +; AVX2: # %bb.0: +; AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm1 +; AVX2-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm2 +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm1 +; AVX512-NEXT: vpcmpnleud {{.*}}(%rip), %xmm0, %k1 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa32 %xmm0, %xmm1 {%k1} +; AVX512-NEXT: vmovdqa %xmm1, %xmm0 +; AVX512-NEXT: retq %a = add <4 x i32> %x, %c = icmp ugt <4 x i32> %x, %r = select <4 x i1> %c, <4 x i32> , <4 x i32> %a @@ -575,6 +714,35 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) { ; SSE41-NEXT: paddq {{.*}}(%rip), %xmm2 ; SSE41-NEXT: movdqa %xmm2, %xmm0 ; SSE41-NEXT: retq +; +; SSE42-LABEL: unsigned_sat_constant_v2i64_using_min: +; SSE42: # %bb.0: +; SSE42-NEXT: movdqa %xmm0, %xmm1 +; SSE42-NEXT: movapd {{.*#+}} xmm2 = [18446744073709551573,18446744073709551573] +; SSE42-NEXT: movdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] +; SSE42-NEXT: pxor %xmm0, %xmm3 +; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775765,9223372036854775765] +; SSE42-NEXT: pcmpgtq %xmm3, %xmm0 +; SSE42-NEXT: blendvpd %xmm0, %xmm1, %xmm2 +; SSE42-NEXT: paddq {{.*}}(%rip), %xmm2 +; SSE42-NEXT: movdqa %xmm2, %xmm0 +; SSE42-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_constant_v2i64_using_min: +; AVX2: # %bb.0: +; AVX2-NEXT: vmovapd {{.*#+}} xmm1 = [18446744073709551573,18446744073709551573] +; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm2 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775765,9223372036854775765] +; AVX2-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2 +; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 +; AVX2-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_constant_v2i64_using_min: +; AVX512: # %bb.0: +; AVX512-NEXT: vpminuq {{.*}}(%rip), %xmm0, %xmm0 +; AVX512-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0 +; AVX512-NEXT: retq %c = icmp ult <2 x i64> %x, %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> %r = add <2 x i64> %s, @@ -582,23 +750,71 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) { } define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) { -; ANY-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum: -; ANY: # %bb.0: -; ANY-NEXT: movdqa {{.*#+}} xmm1 = [42,42] -; ANY-NEXT: paddq %xmm0, %xmm1 -; ANY-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] -; ANY-NEXT: pxor %xmm2, %xmm0 -; ANY-NEXT: pxor %xmm1, %xmm2 -; ANY-NEXT: movdqa %xmm0, %xmm3 -; ANY-NEXT: pcmpgtd %xmm2, %xmm3 -; ANY-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] -; ANY-NEXT: pcmpeqd %xmm0, %xmm2 -; ANY-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; ANY-NEXT: pand %xmm4, %xmm2 -; ANY-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] -; ANY-NEXT: por %xmm1, %xmm0 -; ANY-NEXT: por %xmm2, %xmm0 -; ANY-NEXT: retq +; SSE2-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [42,42] +; SSE2-NEXT: paddq %xmm0, %xmm1 +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] +; SSE2-NEXT: pxor %xmm2, %xmm0 +; SSE2-NEXT: pxor %xmm1, %xmm2 +; SSE2-NEXT: movdqa %xmm0, %xmm3 +; SSE2-NEXT: pcmpgtd %xmm2, %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] +; SSE2-NEXT: pcmpeqd %xmm0, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-NEXT: pand %xmm4, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] +; SSE2-NEXT: por %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [42,42] +; SSE41-NEXT: paddq %xmm0, %xmm1 +; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] +; SSE41-NEXT: pxor %xmm2, %xmm0 +; SSE41-NEXT: pxor %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm0, %xmm3 +; SSE41-NEXT: pcmpgtd %xmm2, %xmm3 +; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] +; SSE41-NEXT: pcmpeqd %xmm0, %xmm2 +; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE41-NEXT: pand %xmm4, %xmm2 +; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] +; SSE41-NEXT: por %xmm1, %xmm0 +; SSE41-NEXT: por %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; SSE42-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum: +; SSE42: # %bb.0: +; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [42,42] +; SSE42-NEXT: paddq %xmm0, %xmm1 +; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] +; SSE42-NEXT: pxor %xmm2, %xmm0 +; SSE42-NEXT: pxor %xmm1, %xmm2 +; SSE42-NEXT: pcmpgtq %xmm2, %xmm0 +; SSE42-NEXT: por %xmm1, %xmm0 +; SSE42-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum: +; AVX2: # %bb.0: +; AVX2-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] +; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2 +; AVX2-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1 +; AVX512-NEXT: vpcmpnleuq %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1} +; AVX512-NEXT: vmovdqa %xmm1, %xmm0 +; AVX512-NEXT: retq %a = add <2 x i64> %x, %c = icmp ugt <2 x i64> %x, %a %r = select <2 x i1> %c, <2 x i64> , <2 x i64> %a @@ -606,22 +822,65 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) { } define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) { -; ANY-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval: -; ANY: # %bb.0: -; ANY-NEXT: movdqa {{.*#+}} xmm1 = [42,42] -; ANY-NEXT: paddq %xmm0, %xmm1 -; ANY-NEXT: pxor {{.*}}(%rip), %xmm0 -; ANY-NEXT: movdqa {{.*#+}} xmm2 = [9223372034707292117,9223372034707292117] -; ANY-NEXT: movdqa %xmm0, %xmm3 -; ANY-NEXT: pcmpgtd %xmm2, %xmm3 -; ANY-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] -; ANY-NEXT: pcmpeqd %xmm2, %xmm0 -; ANY-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] -; ANY-NEXT: pand %xmm4, %xmm2 -; ANY-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] -; ANY-NEXT: por %xmm1, %xmm0 -; ANY-NEXT: por %xmm2, %xmm0 -; ANY-NEXT: retq +; SSE2-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [42,42] +; SSE2-NEXT: paddq %xmm0, %xmm1 +; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0 +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372034707292117,9223372034707292117] +; SSE2-NEXT: movdqa %xmm0, %xmm3 +; SSE2-NEXT: pcmpgtd %xmm2, %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] +; SSE2-NEXT: pcmpeqd %xmm2, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; SSE2-NEXT: pand %xmm4, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] +; SSE2-NEXT: por %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [42,42] +; SSE41-NEXT: paddq %xmm0, %xmm1 +; SSE41-NEXT: pxor {{.*}}(%rip), %xmm0 +; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [9223372034707292117,9223372034707292117] +; SSE41-NEXT: movdqa %xmm0, %xmm3 +; SSE41-NEXT: pcmpgtd %xmm2, %xmm3 +; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] +; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 +; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] +; SSE41-NEXT: pand %xmm4, %xmm2 +; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] +; SSE41-NEXT: por %xmm1, %xmm0 +; SSE41-NEXT: por %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; SSE42-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval: +; SSE42: # %bb.0: +; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [42,42] +; SSE42-NEXT: paddq %xmm0, %xmm1 +; SSE42-NEXT: pxor {{.*}}(%rip), %xmm0 +; SSE42-NEXT: pcmpgtq {{.*}}(%rip), %xmm0 +; SSE42-NEXT: por %xmm1, %xmm0 +; SSE42-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval: +; AVX2: # %bb.0: +; AVX2-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1 +; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm1 +; AVX512-NEXT: vpcmpnleuq {{.*}}(%rip), %xmm0, %k1 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1} +; AVX512-NEXT: vmovdqa %xmm1, %xmm0 +; AVX512-NEXT: retq %a = add <2 x i64> %x, %c = icmp ugt <2 x i64> %x, %r = select <2 x i1> %c, <2 x i64> , <2 x i64> %a @@ -629,13 +888,29 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) { } define <16 x i8> @unsigned_sat_variable_v16i8_using_min(<16 x i8> %x, <16 x i8> %y) { -; ANY-LABEL: unsigned_sat_variable_v16i8_using_min: -; ANY: # %bb.0: -; ANY-NEXT: pcmpeqd %xmm2, %xmm2 -; ANY-NEXT: pxor %xmm1, %xmm2 -; ANY-NEXT: pminub %xmm2, %xmm0 -; ANY-NEXT: paddb %xmm1, %xmm0 -; ANY-NEXT: retq +; SSE-LABEL: unsigned_sat_variable_v16i8_using_min: +; SSE: # %bb.0: +; SSE-NEXT: pcmpeqd %xmm2, %xmm2 +; SSE-NEXT: pxor %xmm1, %xmm2 +; SSE-NEXT: pminub %xmm2, %xmm0 +; SSE-NEXT: paddb %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_variable_v16i8_using_min: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2 +; AVX2-NEXT: vpminub %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpaddb %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_variable_v16i8_using_min: +; AVX512: # %bb.0: +; AVX512-NEXT: vmovdqa %xmm1, %xmm2 +; AVX512-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm2 +; AVX512-NEXT: vpminub %xmm2, %xmm0, %xmm0 +; AVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq %noty = xor <16 x i8> %y, %c = icmp ult <16 x i8> %x, %noty %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> %noty @@ -644,10 +919,24 @@ define <16 x i8> @unsigned_sat_variable_v16i8_using_min(<16 x i8> %x, <16 x i8> } define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_sum(<16 x i8> %x, <16 x i8> %y) { -; ANY-LABEL: unsigned_sat_variable_v16i8_using_cmp_sum: -; ANY: # %bb.0: -; ANY-NEXT: paddusb %xmm1, %xmm0 -; ANY-NEXT: retq +; SSE-LABEL: unsigned_sat_variable_v16i8_using_cmp_sum: +; SSE: # %bb.0: +; SSE-NEXT: paddusb %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_variable_v16i8_using_cmp_sum: +; AVX2: # %bb.0: +; AVX2-NEXT: vpaddusb %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_variable_v16i8_using_cmp_sum: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm1 +; AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm2 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vpternlogq $222, %xmm2, %xmm1, %xmm0 +; AVX512-NEXT: retq %a = add <16 x i8> %x, %y %c = icmp ugt <16 x i8> %x, %a %r = select <16 x i1> %c, <16 x i8> , <16 x i8> %a @@ -655,17 +944,38 @@ define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_sum(<16 x i8> %x, <16 x } define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_notval(<16 x i8> %x, <16 x i8> %y) { -; ANY-LABEL: unsigned_sat_variable_v16i8_using_cmp_notval: -; ANY: # %bb.0: -; ANY-NEXT: pcmpeqd %xmm2, %xmm2 -; ANY-NEXT: movdqa %xmm0, %xmm3 -; ANY-NEXT: paddb %xmm1, %xmm3 -; ANY-NEXT: pxor %xmm2, %xmm1 -; ANY-NEXT: pminub %xmm0, %xmm1 -; ANY-NEXT: pcmpeqb %xmm1, %xmm0 -; ANY-NEXT: pxor %xmm2, %xmm0 -; ANY-NEXT: por %xmm3, %xmm0 -; ANY-NEXT: retq +; SSE-LABEL: unsigned_sat_variable_v16i8_using_cmp_notval: +; SSE: # %bb.0: +; SSE-NEXT: pcmpeqd %xmm2, %xmm2 +; SSE-NEXT: movdqa %xmm0, %xmm3 +; SSE-NEXT: paddb %xmm1, %xmm3 +; SSE-NEXT: pxor %xmm2, %xmm1 +; SSE-NEXT: pminub %xmm0, %xmm1 +; SSE-NEXT: pcmpeqb %xmm1, %xmm0 +; SSE-NEXT: pxor %xmm2, %xmm0 +; SSE-NEXT: por %xmm3, %xmm0 +; SSE-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_variable_v16i8_using_cmp_notval: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3 +; AVX2-NEXT: vpaddb %xmm1, %xmm0, %xmm1 +; AVX2-NEXT: vpminub %xmm3, %xmm0, %xmm3 +; AVX2-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0 +; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_variable_v16i8_using_cmp_notval: +; AVX512: # %bb.0: +; AVX512-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; AVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm3 +; AVX512-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm1 +; AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm1 +; AVX512-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: vpternlogq $222, %xmm2, %xmm3, %xmm0 +; AVX512-NEXT: retq %noty = xor <16 x i8> %y, %a = add <16 x i8> %x, %y %c = icmp ugt <16 x i8> %x, %noty @@ -684,13 +994,29 @@ define <8 x i16> @unsigned_sat_variable_v8i16_using_min(<8 x i16> %x, <8 x i16> ; SSE2-NEXT: paddw %xmm1, %xmm0 ; SSE2-NEXT: retq ; -; SSE41-LABEL: unsigned_sat_variable_v8i16_using_min: -; SSE41: # %bb.0: -; SSE41-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE41-NEXT: pxor %xmm1, %xmm2 -; SSE41-NEXT: pminuw %xmm2, %xmm0 -; SSE41-NEXT: paddw %xmm1, %xmm0 -; SSE41-NEXT: retq +; SSE4-LABEL: unsigned_sat_variable_v8i16_using_min: +; SSE4: # %bb.0: +; SSE4-NEXT: pcmpeqd %xmm2, %xmm2 +; SSE4-NEXT: pxor %xmm1, %xmm2 +; SSE4-NEXT: pminuw %xmm2, %xmm0 +; SSE4-NEXT: paddw %xmm1, %xmm0 +; SSE4-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_variable_v8i16_using_min: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2 +; AVX2-NEXT: vpminuw %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpaddw %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_variable_v8i16_using_min: +; AVX512: # %bb.0: +; AVX512-NEXT: vmovdqa %xmm1, %xmm2 +; AVX512-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm2 +; AVX512-NEXT: vpminuw %xmm2, %xmm0, %xmm0 +; AVX512-NEXT: vpaddw %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq %noty = xor <8 x i16> %y, %c = icmp ult <8 x i16> %x, %noty %s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> %noty @@ -699,10 +1025,24 @@ define <8 x i16> @unsigned_sat_variable_v8i16_using_min(<8 x i16> %x, <8 x i16> } define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_sum(<8 x i16> %x, <8 x i16> %y) { -; ANY-LABEL: unsigned_sat_variable_v8i16_using_cmp_sum: -; ANY: # %bb.0: -; ANY-NEXT: paddusw %xmm1, %xmm0 -; ANY-NEXT: retq +; SSE-LABEL: unsigned_sat_variable_v8i16_using_cmp_sum: +; SSE: # %bb.0: +; SSE-NEXT: paddusw %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_variable_v8i16_using_cmp_sum: +; AVX2: # %bb.0: +; AVX2-NEXT: vpaddusw %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_variable_v8i16_using_cmp_sum: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddw %xmm1, %xmm0, %xmm1 +; AVX512-NEXT: vpminuw %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm2 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vpternlogq $222, %xmm2, %xmm1, %xmm0 +; AVX512-NEXT: retq %a = add <8 x i16> %x, %y %c = icmp ugt <8 x i16> %x, %a %r = select <8 x i1> %c, <8 x i16> , <8 x i16> %a @@ -720,17 +1060,38 @@ define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_notval(<8 x i16> %x, <8 ; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: retq ; -; SSE41-LABEL: unsigned_sat_variable_v8i16_using_cmp_notval: -; SSE41: # %bb.0: -; SSE41-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE41-NEXT: movdqa %xmm0, %xmm3 -; SSE41-NEXT: paddw %xmm1, %xmm3 -; SSE41-NEXT: pxor %xmm2, %xmm1 -; SSE41-NEXT: pminuw %xmm0, %xmm1 -; SSE41-NEXT: pcmpeqw %xmm1, %xmm0 -; SSE41-NEXT: pxor %xmm2, %xmm0 -; SSE41-NEXT: por %xmm3, %xmm0 -; SSE41-NEXT: retq +; SSE4-LABEL: unsigned_sat_variable_v8i16_using_cmp_notval: +; SSE4: # %bb.0: +; SSE4-NEXT: pcmpeqd %xmm2, %xmm2 +; SSE4-NEXT: movdqa %xmm0, %xmm3 +; SSE4-NEXT: paddw %xmm1, %xmm3 +; SSE4-NEXT: pxor %xmm2, %xmm1 +; SSE4-NEXT: pminuw %xmm0, %xmm1 +; SSE4-NEXT: pcmpeqw %xmm1, %xmm0 +; SSE4-NEXT: pxor %xmm2, %xmm0 +; SSE4-NEXT: por %xmm3, %xmm0 +; SSE4-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_variable_v8i16_using_cmp_notval: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3 +; AVX2-NEXT: vpaddw %xmm1, %xmm0, %xmm1 +; AVX2-NEXT: vpminuw %xmm3, %xmm0, %xmm3 +; AVX2-NEXT: vpcmpeqw %xmm3, %xmm0, %xmm0 +; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_variable_v8i16_using_cmp_notval: +; AVX512: # %bb.0: +; AVX512-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; AVX512-NEXT: vpaddw %xmm1, %xmm0, %xmm3 +; AVX512-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm1 +; AVX512-NEXT: vpminuw %xmm1, %xmm0, %xmm1 +; AVX512-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: vpternlogq $222, %xmm2, %xmm3, %xmm0 +; AVX512-NEXT: retq %noty = xor <8 x i16> %y, %a = add <8 x i16> %x, %y %c = icmp ugt <8 x i16> %x, %noty @@ -755,13 +1116,29 @@ define <4 x i32> @unsigned_sat_variable_v4i32_using_min(<4 x i32> %x, <4 x i32> ; SSE2-NEXT: paddd %xmm1, %xmm0 ; SSE2-NEXT: retq ; -; SSE41-LABEL: unsigned_sat_variable_v4i32_using_min: -; SSE41: # %bb.0: -; SSE41-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE41-NEXT: pxor %xmm1, %xmm2 -; SSE41-NEXT: pminud %xmm2, %xmm0 -; SSE41-NEXT: paddd %xmm1, %xmm0 -; SSE41-NEXT: retq +; SSE4-LABEL: unsigned_sat_variable_v4i32_using_min: +; SSE4: # %bb.0: +; SSE4-NEXT: pcmpeqd %xmm2, %xmm2 +; SSE4-NEXT: pxor %xmm1, %xmm2 +; SSE4-NEXT: pminud %xmm2, %xmm0 +; SSE4-NEXT: paddd %xmm1, %xmm0 +; SSE4-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_variable_v4i32_using_min: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2 +; AVX2-NEXT: vpminud %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_variable_v4i32_using_min: +; AVX512: # %bb.0: +; AVX512-NEXT: vmovdqa %xmm1, %xmm2 +; AVX512-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm2 +; AVX512-NEXT: vpminud %xmm2, %xmm0, %xmm0 +; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq %noty = xor <4 x i32> %y, %c = icmp ult <4 x i32> %x, %noty %s = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %noty @@ -780,17 +1157,36 @@ define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_sum(<4 x i32> %x, <4 x i ; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: retq ; -; SSE41-LABEL: unsigned_sat_variable_v4i32_using_cmp_sum: -; SSE41: # %bb.0: -; SSE41-NEXT: paddd %xmm0, %xmm1 -; SSE41-NEXT: movdqa %xmm0, %xmm2 -; SSE41-NEXT: pminud %xmm1, %xmm2 -; SSE41-NEXT: pcmpeqd %xmm0, %xmm2 -; SSE41-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE41-NEXT: pxor %xmm0, %xmm2 -; SSE41-NEXT: por %xmm1, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm0 -; SSE41-NEXT: retq +; SSE4-LABEL: unsigned_sat_variable_v4i32_using_cmp_sum: +; SSE4: # %bb.0: +; SSE4-NEXT: paddd %xmm0, %xmm1 +; SSE4-NEXT: movdqa %xmm0, %xmm2 +; SSE4-NEXT: pminud %xmm1, %xmm2 +; SSE4-NEXT: pcmpeqd %xmm0, %xmm2 +; SSE4-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE4-NEXT: pxor %xmm0, %xmm2 +; SSE4-NEXT: por %xmm1, %xmm2 +; SSE4-NEXT: movdqa %xmm2, %xmm0 +; SSE4-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_variable_v4i32_using_cmp_sum: +; AVX2: # %bb.0: +; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1 +; AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm2 +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_variable_v4i32_using_cmp_sum: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm1 +; AVX512-NEXT: vpcmpnleud %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa32 %xmm0, %xmm1 {%k1} +; AVX512-NEXT: vmovdqa %xmm1, %xmm0 +; AVX512-NEXT: retq %a = add <4 x i32> %x, %y %c = icmp ugt <4 x i32> %x, %a %r = select <4 x i1> %c, <4 x i32> , <4 x i32> %a @@ -808,17 +1204,38 @@ define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_notval(<4 x i32> %x, <4 ; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: retq ; -; SSE41-LABEL: unsigned_sat_variable_v4i32_using_cmp_notval: -; SSE41: # %bb.0: -; SSE41-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE41-NEXT: movdqa %xmm0, %xmm3 -; SSE41-NEXT: paddd %xmm1, %xmm3 -; SSE41-NEXT: pxor %xmm2, %xmm1 -; SSE41-NEXT: pminud %xmm0, %xmm1 -; SSE41-NEXT: pcmpeqd %xmm1, %xmm0 -; SSE41-NEXT: pxor %xmm2, %xmm0 -; SSE41-NEXT: por %xmm3, %xmm0 -; SSE41-NEXT: retq +; SSE4-LABEL: unsigned_sat_variable_v4i32_using_cmp_notval: +; SSE4: # %bb.0: +; SSE4-NEXT: pcmpeqd %xmm2, %xmm2 +; SSE4-NEXT: movdqa %xmm0, %xmm3 +; SSE4-NEXT: paddd %xmm1, %xmm3 +; SSE4-NEXT: pxor %xmm2, %xmm1 +; SSE4-NEXT: pminud %xmm0, %xmm1 +; SSE4-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE4-NEXT: pxor %xmm2, %xmm0 +; SSE4-NEXT: por %xmm3, %xmm0 +; SSE4-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_variable_v4i32_using_cmp_notval: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3 +; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1 +; AVX2-NEXT: vpminud %xmm3, %xmm0, %xmm3 +; AVX2-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0 +; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_variable_v4i32_using_cmp_notval: +; AVX512: # %bb.0: +; AVX512-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3 +; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm1 +; AVX512-NEXT: vpcmpnleud %xmm1, %xmm0, %k1 +; AVX512-NEXT: vmovdqa32 %xmm3, %xmm2 {%k1} +; AVX512-NEXT: vmovdqa %xmm2, %xmm0 +; AVX512-NEXT: retq %noty = xor <4 x i32> %y, %a = add <4 x i32> %x, %y %c = icmp ugt <4 x i32> %x, %noty @@ -869,6 +1286,40 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_min(<2 x i64> %x, <2 x i64> ; SSE41-NEXT: paddq %xmm1, %xmm3 ; SSE41-NEXT: movdqa %xmm3, %xmm0 ; SSE41-NEXT: retq +; +; SSE42-LABEL: unsigned_sat_variable_v2i64_using_min: +; SSE42: # %bb.0: +; SSE42-NEXT: movdqa %xmm0, %xmm2 +; SSE42-NEXT: pcmpeqd %xmm3, %xmm3 +; SSE42-NEXT: pxor %xmm1, %xmm3 +; SSE42-NEXT: movdqa {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808] +; SSE42-NEXT: pxor %xmm0, %xmm4 +; SSE42-NEXT: movdqa {{.*#+}} xmm0 = [9223372036854775807,9223372036854775807] +; SSE42-NEXT: pxor %xmm1, %xmm0 +; SSE42-NEXT: pcmpgtq %xmm4, %xmm0 +; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm3 +; SSE42-NEXT: paddq %xmm1, %xmm3 +; SSE42-NEXT: movdqa %xmm3, %xmm0 +; SSE42-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_variable_v2i64_using_min: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2 +; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm3 +; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm1, %xmm4 +; AVX2-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm3 +; AVX2-NEXT: vblendvpd %xmm3, %xmm0, %xmm2, %xmm0 +; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_variable_v2i64_using_min: +; AVX512: # %bb.0: +; AVX512-NEXT: vmovdqa %xmm1, %xmm2 +; AVX512-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm2 +; AVX512-NEXT: vpminuq %xmm2, %xmm0, %xmm0 +; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq %noty = xor <2 x i64> %y, %c = icmp ult <2 x i64> %x, %noty %s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> %noty @@ -877,22 +1328,68 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_min(<2 x i64> %x, <2 x i64> } define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_sum(<2 x i64> %x, <2 x i64> %y) { -; ANY-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum: -; ANY: # %bb.0: -; ANY-NEXT: paddq %xmm0, %xmm1 -; ANY-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] -; ANY-NEXT: pxor %xmm2, %xmm0 -; ANY-NEXT: pxor %xmm1, %xmm2 -; ANY-NEXT: movdqa %xmm0, %xmm3 -; ANY-NEXT: pcmpgtd %xmm2, %xmm3 -; ANY-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] -; ANY-NEXT: pcmpeqd %xmm0, %xmm2 -; ANY-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; ANY-NEXT: pand %xmm4, %xmm2 -; ANY-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] -; ANY-NEXT: por %xmm1, %xmm0 -; ANY-NEXT: por %xmm2, %xmm0 -; ANY-NEXT: retq +; SSE2-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum: +; SSE2: # %bb.0: +; SSE2-NEXT: paddq %xmm0, %xmm1 +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] +; SSE2-NEXT: pxor %xmm2, %xmm0 +; SSE2-NEXT: pxor %xmm1, %xmm2 +; SSE2-NEXT: movdqa %xmm0, %xmm3 +; SSE2-NEXT: pcmpgtd %xmm2, %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] +; SSE2-NEXT: pcmpeqd %xmm0, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE2-NEXT: pand %xmm4, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] +; SSE2-NEXT: por %xmm1, %xmm0 +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum: +; SSE41: # %bb.0: +; SSE41-NEXT: paddq %xmm0, %xmm1 +; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] +; SSE41-NEXT: pxor %xmm2, %xmm0 +; SSE41-NEXT: pxor %xmm1, %xmm2 +; SSE41-NEXT: movdqa %xmm0, %xmm3 +; SSE41-NEXT: pcmpgtd %xmm2, %xmm3 +; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] +; SSE41-NEXT: pcmpeqd %xmm0, %xmm2 +; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE41-NEXT: pand %xmm4, %xmm2 +; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] +; SSE41-NEXT: por %xmm1, %xmm0 +; SSE41-NEXT: por %xmm2, %xmm0 +; SSE41-NEXT: retq +; +; SSE42-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum: +; SSE42: # %bb.0: +; SSE42-NEXT: paddq %xmm0, %xmm1 +; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] +; SSE42-NEXT: pxor %xmm2, %xmm0 +; SSE42-NEXT: pxor %xmm1, %xmm2 +; SSE42-NEXT: pcmpgtq %xmm2, %xmm0 +; SSE42-NEXT: por %xmm1, %xmm0 +; SSE42-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum: +; AVX2: # %bb.0: +; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm1 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] +; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2 +; AVX2-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum: +; AVX512: # %bb.0: +; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm1 +; AVX512-NEXT: vpcmpnleuq %xmm1, %xmm0, %k1 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1} +; AVX512-NEXT: vmovdqa %xmm1, %xmm0 +; AVX512-NEXT: retq %a = add <2 x i64> %x, %y %c = icmp ugt <2 x i64> %x, %a %r = select <2 x i1> %c, <2 x i64> , <2 x i64> %a @@ -900,22 +1397,68 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_sum(<2 x i64> %x, <2 x i } define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2 x i64> %y) { -; ANY-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval: -; ANY: # %bb.0: -; ANY-NEXT: movdqa %xmm0, %xmm2 -; ANY-NEXT: paddq %xmm1, %xmm2 -; ANY-NEXT: pxor {{.*}}(%rip), %xmm1 -; ANY-NEXT: pxor {{.*}}(%rip), %xmm0 -; ANY-NEXT: movdqa %xmm0, %xmm3 -; ANY-NEXT: pcmpgtd %xmm1, %xmm3 -; ANY-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] -; ANY-NEXT: pcmpeqd %xmm1, %xmm0 -; ANY-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] -; ANY-NEXT: pand %xmm4, %xmm1 -; ANY-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] -; ANY-NEXT: por %xmm2, %xmm0 -; ANY-NEXT: por %xmm1, %xmm0 -; ANY-NEXT: retq +; SSE2-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa %xmm0, %xmm2 +; SSE2-NEXT: paddq %xmm1, %xmm2 +; SSE2-NEXT: pxor {{.*}}(%rip), %xmm1 +; SSE2-NEXT: pxor {{.*}}(%rip), %xmm0 +; SSE2-NEXT: movdqa %xmm0, %xmm3 +; SSE2-NEXT: pcmpgtd %xmm1, %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] +; SSE2-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] +; SSE2-NEXT: pand %xmm4, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] +; SSE2-NEXT: por %xmm2, %xmm0 +; SSE2-NEXT: por %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE41-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval: +; SSE41: # %bb.0: +; SSE41-NEXT: movdqa %xmm0, %xmm2 +; SSE41-NEXT: paddq %xmm1, %xmm2 +; SSE41-NEXT: pxor {{.*}}(%rip), %xmm1 +; SSE41-NEXT: pxor {{.*}}(%rip), %xmm0 +; SSE41-NEXT: movdqa %xmm0, %xmm3 +; SSE41-NEXT: pcmpgtd %xmm1, %xmm3 +; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] +; SSE41-NEXT: pcmpeqd %xmm1, %xmm0 +; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] +; SSE41-NEXT: pand %xmm4, %xmm1 +; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] +; SSE41-NEXT: por %xmm2, %xmm0 +; SSE41-NEXT: por %xmm1, %xmm0 +; SSE41-NEXT: retq +; +; SSE42-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval: +; SSE42: # %bb.0: +; SSE42-NEXT: movdqa %xmm0, %xmm2 +; SSE42-NEXT: paddq %xmm1, %xmm2 +; SSE42-NEXT: pxor {{.*}}(%rip), %xmm1 +; SSE42-NEXT: pxor {{.*}}(%rip), %xmm0 +; SSE42-NEXT: pcmpgtq %xmm1, %xmm0 +; SSE42-NEXT: por %xmm2, %xmm0 +; SSE42-NEXT: retq +; +; AVX2-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval: +; AVX2: # %bb.0: +; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm2 +; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm1, %xmm1 +; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpor %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval: +; AVX512: # %bb.0: +; AVX512-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3 +; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm1 +; AVX512-NEXT: vpcmpnleuq %xmm1, %xmm0, %k1 +; AVX512-NEXT: vmovdqa64 %xmm3, %xmm2 {%k1} +; AVX512-NEXT: vmovdqa %xmm2, %xmm0 +; AVX512-NEXT: retq %noty = xor <2 x i64> %y, %a = add <2 x i64> %x, %y %c = icmp ugt <2 x i64> %x, %noty diff --git a/llvm/test/CodeGen/X86/scev-interchange.ll b/llvm/test/CodeGen/X86/scev-interchange.ll index 9cbb462e47da4..9fa3180a75e72 100644 --- a/llvm/test/CodeGen/X86/scev-interchange.ll +++ b/llvm/test/CodeGen/X86/scev-interchange.ll @@ -47,9 +47,9 @@ declare fastcc void @_ZN24TensorProductPolynomialsILi3EEC2IN11Polynomials10Polyn declare fastcc void @_ZN7FE_PolyI24TensorProductPolynomialsILi3EELi3EEC2EjRKS1_RK17FiniteElementDataILi3EERKSt6vectorIbSaIbEERKS9_ISB_SaISB_EE(%"struct.FE_DGPNonparametric<3>"*, i32, %"struct.PolynomialSpace<1>"* nocapture, %"struct.FiniteElementData<1>"* nocapture, %"struct.std::vector >"* nocapture, %"struct.std::vector >,std::allocator > > >"* nocapture) -declare fastcc void @_ZN11FE_Q_Helper12_GLOBAL__N_116invert_numberingERKSt6vectorIjSaIjEE(%"struct.std::vector >"* noalias nocapture sret, %"struct.std::vector >"* nocapture) +declare fastcc void @_ZN11FE_Q_Helper12_GLOBAL__N_116invert_numberingERKSt6vectorIjSaIjEE(%"struct.std::vector >"* noalias nocapture sret(%"struct.std::vector >"), %"struct.std::vector >"* nocapture) -declare fastcc void @_ZN4FE_QILi3EE14get_dpo_vectorEj(%"struct.std::vector >"* noalias nocapture sret, i32) +declare fastcc void @_ZN4FE_QILi3EE14get_dpo_vectorEj(%"struct.std::vector >"* noalias nocapture sret(%"struct.std::vector >"), i32) define fastcc void @_ZN4FE_QILi3EEC1Ej(i32 %degree) personality i32 (...)* @__gxx_personality_v0 { entry: @@ -57,7 +57,7 @@ entry: to label %invcont.i unwind label %lpad.i invcont.i: ; preds = %entry - invoke fastcc void @_ZN4FE_QILi3EE14get_dpo_vectorEj(%"struct.std::vector >"* noalias sret undef, i32 %degree) + invoke fastcc void @_ZN4FE_QILi3EE14get_dpo_vectorEj(%"struct.std::vector >"* noalias sret(%"struct.std::vector >") undef, i32 %degree) to label %invcont1.i unwind label %lpad120.i invcont1.i: ; preds = %invcont.i @@ -65,7 +65,7 @@ invcont1.i: ; preds = %invcont.i to label %invcont3.i unwind label %lpad124.i invcont3.i: ; preds = %invcont1.i - invoke fastcc void @_ZN4FE_QILi3EE14get_dpo_vectorEj(%"struct.std::vector >"* noalias sret undef, i32 %degree) + invoke fastcc void @_ZN4FE_QILi3EE14get_dpo_vectorEj(%"struct.std::vector >"* noalias sret(%"struct.std::vector >") undef, i32 %degree) to label %invcont4.i unwind label %lpad128.i invcont4.i: ; preds = %invcont3.i @@ -73,11 +73,11 @@ invcont4.i: ; preds = %invcont3.i to label %invcont6.i unwind label %lpad132.i invcont6.i: ; preds = %invcont4.i - invoke fastcc void @_ZN4FE_QILi3EE14get_dpo_vectorEj(%"struct.std::vector >"* noalias sret undef, i32 %degree) + invoke fastcc void @_ZN4FE_QILi3EE14get_dpo_vectorEj(%"struct.std::vector >"* noalias sret(%"struct.std::vector >") undef, i32 %degree) to label %invcont7.i unwind label %lpad136.i invcont7.i: ; preds = %invcont6.i - invoke fastcc void @_ZN11Polynomials19LagrangeEquidistant23generate_complete_basisEj(%"struct.std::vector,std::allocator > >"* noalias sret undef, i32 %degree) + invoke fastcc void @_ZN11Polynomials19LagrangeEquidistant23generate_complete_basisEj(%"struct.std::vector,std::allocator > >"* noalias sret(%"struct.std::vector,std::allocator > >") undef, i32 %degree) to label %invcont9.i unwind label %lpad140.i invcont9.i: ; preds = %invcont7.i @@ -179,7 +179,7 @@ bb.i.i.i.i.i.i.i.i.i.i: ; preds = %bb.i.i.i.i.i.i.i.i.i.i, %_ZNSt12_Vector_base br i1 undef, label %bb50.i.i.i, label %bb.i.i.i.i.i.i.i.i.i.i bb50.i.i.i: ; preds = %bb.i.i.i.i.i.i.i.i.i.i, %_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i12.i.i - invoke fastcc void @_ZN11FE_Q_Helper12_GLOBAL__N_116invert_numberingERKSt6vectorIjSaIjEE(%"struct.std::vector >"* noalias sret undef, %"struct.std::vector >"* undef) + invoke fastcc void @_ZN11FE_Q_Helper12_GLOBAL__N_116invert_numberingERKSt6vectorIjSaIjEE(%"struct.std::vector >"* noalias sret(%"struct.std::vector >") undef, %"struct.std::vector >"* undef) to label %bb83.i unwind label %lpad188.i lpad.i19.i.i: ; preds = %lpad.i.i.i.i8.i.i @@ -213,7 +213,7 @@ bb.i.i.i.i.i.i.i.i320.i: ; preds = %bb.i.i.i.i.i.i.i.i320.i, %_ZNSt12_Vector_ba br i1 undef, label %bb50.i.i, label %bb.i.i.i.i.i.i.i.i320.i bb50.i.i: ; preds = %bb.i.i.i.i.i.i.i.i320.i, %_ZNSt12_Vector_baseIjSaIjEEC2EmRKS0_.exit.i.i.i.i - invoke fastcc void @_ZN11FE_Q_Helper12_GLOBAL__N_116invert_numberingERKSt6vectorIjSaIjEE(%"struct.std::vector >"* noalias sret undef, %"struct.std::vector >"* undef) + invoke fastcc void @_ZN11FE_Q_Helper12_GLOBAL__N_116invert_numberingERKSt6vectorIjSaIjEE(%"struct.std::vector >"* noalias sret(%"struct.std::vector >") undef, %"struct.std::vector >"* undef) to label %invcont86.i unwind label %lpad200.i lpad.i352.i: ; preds = %lpad.i.i.i.i315.i @@ -377,6 +377,6 @@ lpad204.i: ; preds = %invcont86.i unreachable } -declare fastcc void @_ZN11Polynomials19LagrangeEquidistant23generate_complete_basisEj(%"struct.std::vector,std::allocator > >"* noalias nocapture sret, i32) +declare fastcc void @_ZN11Polynomials19LagrangeEquidistant23generate_complete_basisEj(%"struct.std::vector,std::allocator > >"* noalias nocapture sret(%"struct.std::vector,std::allocator > >"), i32) declare i32 @__gxx_personality_v0(...) diff --git a/llvm/test/CodeGen/X86/sibcall-byval.ll b/llvm/test/CodeGen/X86/sibcall-byval.ll index 8f5833adf5a32..999e12334c6c3 100644 --- a/llvm/test/CodeGen/X86/sibcall-byval.ll +++ b/llvm/test/CodeGen/X86/sibcall-byval.ll @@ -3,20 +3,20 @@ %struct.p = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } -define i32 @f(%struct.p* byval align 4 %q) nounwind ssp { +define i32 @f(%struct.p* byval(%struct.p) align 4 %q) nounwind ssp { entry: ; 32: _f: ; 32: jmp _g ; 64: _f: ; 64: jmp _g - %call = tail call i32 @g(%struct.p* byval align 4 %q) nounwind + %call = tail call i32 @g(%struct.p* byval(%struct.p) align 4 %q) nounwind ret i32 %call } -declare i32 @g(%struct.p* byval align 4) +declare i32 @g(%struct.p* byval(%struct.p) align 4) -define i32 @h(%struct.p* byval align 4 %q, i32 %r) nounwind ssp { +define i32 @h(%struct.p* byval(%struct.p) align 4 %q, i32 %r) nounwind ssp { entry: ; 32: _h: ; 32: jmp _i @@ -24,8 +24,8 @@ entry: ; 64: _h: ; 64: jmp _i - %call = tail call i32 @i(%struct.p* byval align 4 %q, i32 %r) nounwind + %call = tail call i32 @i(%struct.p* byval(%struct.p) align 4 %q, i32 %r) nounwind ret i32 %call } -declare i32 @i(%struct.p* byval align 4, i32) +declare i32 @i(%struct.p* byval(%struct.p) align 4, i32) diff --git a/llvm/test/CodeGen/X86/sibcall.ll b/llvm/test/CodeGen/X86/sibcall.ll index 98e17b1aa601b..d0fd7a66e54b5 100644 --- a/llvm/test/CodeGen/X86/sibcall.ll +++ b/llvm/test/CodeGen/X86/sibcall.ll @@ -307,7 +307,7 @@ declare i32 @foo5(i32, i32, i32, i32, i32) %struct.t = type { i32, i32, i32, i32, i32 } -define i32 @t12(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind ssp { +define i32 @t12(i32 %x, i32 %y, %struct.t* byval(%struct.t) align 4 %z) nounwind ssp { ; X86-LABEL: t12: ; X86: # %bb.0: # %entry ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) @@ -342,14 +342,14 @@ entry: br i1 %0, label %bb2, label %bb bb: - %1 = tail call i32 @foo6(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind + %1 = tail call i32 @foo6(i32 %x, i32 %y, %struct.t* byval(%struct.t) align 4 %z) nounwind ret i32 %1 bb2: ret i32 0 } -declare i32 @foo6(i32, i32, %struct.t* byval align 4) +declare i32 @foo6(i32, i32, %struct.t* byval(%struct.t) align 4) ; rdar://r7717598 %struct.ns = type { i32, i32 } @@ -403,13 +403,13 @@ define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp { ; X32-NEXT: popq %rcx ; X32-NEXT: retq entry: - %0 = tail call fastcc %struct.ns* @foo7(%struct.cp* byval align 4 %yy, i8 signext 0) nounwind + %0 = tail call fastcc %struct.ns* @foo7(%struct.cp* byval(%struct.cp) align 4 %yy, i8 signext 0) nounwind ret %struct.ns* %0 } ; rdar://6195379 ; llvm can't do sibcall for this in 32-bit mode (yet). -declare fastcc %struct.ns* @foo7(%struct.cp* byval align 4, i8 signext) nounwind ssp +declare fastcc %struct.ns* @foo7(%struct.cp* byval(%struct.cp) align 4, i8 signext) nounwind ssp %struct.__block_descriptor = type { i64, i64 } %struct.__block_descriptor_withcopydispose = type { i64, i64, i8*, i8* } @@ -452,7 +452,7 @@ entry: ; rdar://7726868 %struct.foo = type { [4 x i32] } -define void @t15(%struct.foo* noalias sret %agg.result) nounwind { +define void @t15(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind { ; X86-LABEL: t15: ; X86: # %bb.0: ; X86-NEXT: pushl %esi @@ -482,11 +482,11 @@ define void @t15(%struct.foo* noalias sret %agg.result) nounwind { ; X32-NEXT: movl %ebx, %eax ; X32-NEXT: popq %rbx ; X32-NEXT: retq - tail call fastcc void @f(%struct.foo* noalias sret %agg.result) nounwind + tail call fastcc void @f(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind ret void } -declare void @f(%struct.foo* noalias sret) nounwind +declare void @f(%struct.foo* noalias sret(%struct.foo)) nounwind define void @t16() nounwind ssp { ; X86-LABEL: t16: @@ -627,7 +627,7 @@ entry: declare fastcc double @foo20(double) nounwind ; bug 28417 -define fastcc void @t21_sret_to_sret(%struct.foo* noalias sret %agg.result) nounwind { +define fastcc void @t21_sret_to_sret(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind { ; X86-LABEL: t21_sret_to_sret: ; X86: # %bb.0: ; X86-NEXT: pushl %esi @@ -656,11 +656,11 @@ define fastcc void @t21_sret_to_sret(%struct.foo* noalias sret %agg.result) noun ; X32-NEXT: movl %ebx, %eax ; X32-NEXT: popq %rbx ; X32-NEXT: retq - tail call fastcc void @t21_f_sret(%struct.foo* noalias sret %agg.result) nounwind + tail call fastcc void @t21_f_sret(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind ret void } -define fastcc void @t21_sret_to_sret_alloca(%struct.foo* noalias sret %agg.result) nounwind { +define fastcc void @t21_sret_to_sret_alloca(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind { ; X86-LABEL: t21_sret_to_sret_alloca: ; X86: # %bb.0: ; X86-NEXT: pushl %esi @@ -697,11 +697,11 @@ define fastcc void @t21_sret_to_sret_alloca(%struct.foo* noalias sret %agg.resul ; X32-NEXT: popq %rbx ; X32-NEXT: retq %a = alloca %struct.foo, align 8 - tail call fastcc void @t21_f_sret(%struct.foo* noalias sret %a) nounwind + tail call fastcc void @t21_f_sret(%struct.foo* noalias sret(%struct.foo) %a) nounwind ret void } -define fastcc void @t21_sret_to_sret_more_args(%struct.foo* noalias sret %agg.result, i32 %a, i32 %b) nounwind { +define fastcc void @t21_sret_to_sret_more_args(%struct.foo* noalias sret(%struct.foo) %agg.result, i32 %a, i32 %b) nounwind { ; X86-LABEL: t21_sret_to_sret_more_args: ; X86: # %bb.0: ; X86-NEXT: pushl %esi @@ -732,11 +732,11 @@ define fastcc void @t21_sret_to_sret_more_args(%struct.foo* noalias sret %agg.re ; X32-NEXT: movl %ebx, %eax ; X32-NEXT: popq %rbx ; X32-NEXT: retq - tail call fastcc void @f_sret(%struct.foo* noalias sret %agg.result, i32 %a, i32 %b) nounwind + tail call fastcc void @f_sret(%struct.foo* noalias sret(%struct.foo) %agg.result, i32 %a, i32 %b) nounwind ret void } -define fastcc void @t21_sret_to_sret_second_arg_sret(%struct.foo* noalias %agg.result, %struct.foo* noalias sret %ret) nounwind { +define fastcc void @t21_sret_to_sret_second_arg_sret(%struct.foo* noalias %agg.result, %struct.foo* noalias sret(%struct.foo) %ret) nounwind { ; X86-LABEL: t21_sret_to_sret_second_arg_sret: ; X86: # %bb.0: ; X86-NEXT: pushl %esi @@ -768,11 +768,11 @@ define fastcc void @t21_sret_to_sret_second_arg_sret(%struct.foo* noalias %agg.r ; X32-NEXT: movl %ebx, %eax ; X32-NEXT: popq %rbx ; X32-NEXT: retq - tail call fastcc void @t21_f_sret(%struct.foo* noalias sret %ret) nounwind + tail call fastcc void @t21_f_sret(%struct.foo* noalias sret(%struct.foo) %ret) nounwind ret void } -define fastcc void @t21_sret_to_sret_more_args2(%struct.foo* noalias sret %agg.result, i32 %a, i32 %b) nounwind { +define fastcc void @t21_sret_to_sret_more_args2(%struct.foo* noalias sret(%struct.foo) %agg.result, i32 %a, i32 %b) nounwind { ; X86-LABEL: t21_sret_to_sret_more_args2: ; X86: # %bb.0: ; X86-NEXT: pushl %esi @@ -810,12 +810,12 @@ define fastcc void @t21_sret_to_sret_more_args2(%struct.foo* noalias sret %agg.r ; X32-NEXT: movl %ebx, %eax ; X32-NEXT: popq %rbx ; X32-NEXT: retq - tail call fastcc void @f_sret(%struct.foo* noalias sret %agg.result, i32 %b, i32 %a) nounwind + tail call fastcc void @f_sret(%struct.foo* noalias sret(%struct.foo) %agg.result, i32 %b, i32 %a) nounwind ret void } -define fastcc void @t21_sret_to_sret_args_mismatch(%struct.foo* noalias sret %agg.result, %struct.foo* noalias %ret) nounwind { +define fastcc void @t21_sret_to_sret_args_mismatch(%struct.foo* noalias sret(%struct.foo) %agg.result, %struct.foo* noalias %ret) nounwind { ; X86-LABEL: t21_sret_to_sret_args_mismatch: ; X86: # %bb.0: ; X86-NEXT: pushl %esi @@ -847,11 +847,11 @@ define fastcc void @t21_sret_to_sret_args_mismatch(%struct.foo* noalias sret %ag ; X32-NEXT: movl %ebx, %eax ; X32-NEXT: popq %rbx ; X32-NEXT: retq - tail call fastcc void @t21_f_sret(%struct.foo* noalias sret %ret) nounwind + tail call fastcc void @t21_f_sret(%struct.foo* noalias sret(%struct.foo) %ret) nounwind ret void } -define fastcc void @t21_sret_to_sret_args_mismatch2(%struct.foo* noalias sret %agg.result, %struct.foo* noalias %ret) nounwind { +define fastcc void @t21_sret_to_sret_args_mismatch2(%struct.foo* noalias sret(%struct.foo) %agg.result, %struct.foo* noalias %ret) nounwind { ; X86-LABEL: t21_sret_to_sret_args_mismatch2: ; X86: # %bb.0: ; X86-NEXT: pushl %esi @@ -883,11 +883,11 @@ define fastcc void @t21_sret_to_sret_args_mismatch2(%struct.foo* noalias sret %a ; X32-NEXT: movl %ebx, %eax ; X32-NEXT: popq %rbx ; X32-NEXT: retq - tail call fastcc void @t21_f_sret(%struct.foo* noalias sret %ret) nounwind + tail call fastcc void @t21_f_sret(%struct.foo* noalias sret(%struct.foo) %ret) nounwind ret void } -define fastcc void @t21_sret_to_sret_arg_mismatch(%struct.foo* noalias sret %agg.result) nounwind { +define fastcc void @t21_sret_to_sret_arg_mismatch(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind { ; X86-LABEL: t21_sret_to_sret_arg_mismatch: ; X86: # %bb.0: ; X86-NEXT: pushl %esi @@ -923,11 +923,11 @@ define fastcc void @t21_sret_to_sret_arg_mismatch(%struct.foo* noalias sret %agg ; X32-NEXT: popq %rbx ; X32-NEXT: retq %a = call fastcc %struct.foo* @ret_struct() - tail call fastcc void @t21_f_sret(%struct.foo* noalias sret %a) nounwind + tail call fastcc void @t21_f_sret(%struct.foo* noalias sret(%struct.foo) %a) nounwind ret void } -define fastcc void @t21_sret_to_sret_structs_mismatch(%struct.foo* noalias sret %agg.result, %struct.foo* noalias %a) nounwind { +define fastcc void @t21_sret_to_sret_structs_mismatch(%struct.foo* noalias sret(%struct.foo) %agg.result, %struct.foo* noalias %a) nounwind { ; X86-LABEL: t21_sret_to_sret_structs_mismatch: ; X86: # %bb.0: ; X86-NEXT: pushl %edi @@ -979,14 +979,14 @@ define fastcc void @t21_sret_to_sret_structs_mismatch(%struct.foo* noalias sret ; X32-NEXT: popq %rbp ; X32-NEXT: retq %b = call fastcc %struct.foo* @ret_struct() - tail call fastcc void @t21_f_sret2(%struct.foo* noalias sret %a, %struct.foo* noalias %b) nounwind + tail call fastcc void @t21_f_sret2(%struct.foo* noalias sret(%struct.foo) %a, %struct.foo* noalias %b) nounwind ret void } declare ccc %struct.foo* @ret_struct() nounwind -define fastcc void @t21_sret_to_non_sret(%struct.foo* noalias sret %agg.result) nounwind { +define fastcc void @t21_sret_to_non_sret(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind { ; X86-LABEL: t21_sret_to_non_sret: ; X86: # %bb.0: ; X86-NEXT: pushl %esi @@ -1043,14 +1043,14 @@ define ccc void @t22_non_sret_to_sret(%struct.foo* %agg.result) nounwind { ; X32-NEXT: callq t22_f_sret ; X32-NEXT: popq %rax ; X32-NEXT: retq - tail call ccc void @t22_f_sret(%struct.foo* noalias sret %agg.result) nounwind + tail call ccc void @t22_f_sret(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind ret void } -declare fastcc void @t21_f_sret(%struct.foo* noalias sret) nounwind -declare fastcc void @t21_f_sret2(%struct.foo* noalias sret, %struct.foo* noalias) nounwind +declare fastcc void @t21_f_sret(%struct.foo* noalias sret(%struct.foo)) nounwind +declare fastcc void @t21_f_sret2(%struct.foo* noalias sret(%struct.foo), %struct.foo* noalias) nounwind declare fastcc void @t21_f_non_sret(%struct.foo*) nounwind -declare ccc void @t22_f_sret(%struct.foo* noalias sret) nounwind +declare ccc void @t22_f_sret(%struct.foo* noalias sret(%struct.foo)) nounwind -declare ccc void @f_sret(%struct.foo* noalias sret, i32, i32) nounwind +declare ccc void @f_sret(%struct.foo* noalias sret(%struct.foo), i32, i32) nounwind diff --git a/llvm/test/CodeGen/X86/sjlj-baseptr.ll b/llvm/test/CodeGen/X86/sjlj-baseptr.ll index 93ff0eb8abf96..c32d5c5480cc8 100644 --- a/llvm/test/CodeGen/X86/sjlj-baseptr.ll +++ b/llvm/test/CodeGen/X86/sjlj-baseptr.ll @@ -11,7 +11,7 @@ declare void @whatever(i64, %Foo*, i8**, i8*, i8*, i32) #0 attributes #0 = { nounwind uwtable "frame-pointer"="all" } -define i32 @test1(i64 %n, %Foo* byval nocapture readnone align 8 %f) #0 { +define i32 @test1(i64 %n, %Foo* byval(%Foo) nocapture readnone align 8 %f) #0 { entry: %buf = alloca [5 x i8*], align 16 %p = alloca i8*, align 8 diff --git a/llvm/test/CodeGen/X86/sret-implicit.ll b/llvm/test/CodeGen/X86/sret-implicit.ll index 75aaf46188c6f..242082deb0585 100644 --- a/llvm/test/CodeGen/X86/sret-implicit.ll +++ b/llvm/test/CodeGen/X86/sret-implicit.ll @@ -4,7 +4,7 @@ ; RUN: llc -mtriple=x86_64-apple-darwin8 -terminal-rule < %s | FileCheck %s --check-prefix=X64 ; RUN: llc -mtriple=x86_64-pc-linux -terminal-rule < %s | FileCheck %s --check-prefix=X64 -define void @sret_void(i32* sret %p) { +define void @sret_void(i32* sret(i32) %p) { store i32 0, i32* %p ret void } diff --git a/llvm/test/CodeGen/X86/ssp-data-layout.ll b/llvm/test/CodeGen/X86/ssp-data-layout.ll index 409dd7cb85324..3826d942f8b1b 100644 --- a/llvm/test/CodeGen/X86/ssp-data-layout.ll +++ b/llvm/test/CodeGen/X86/ssp-data-layout.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -stack-symbol-ordering=0 -frame-pointer=all -mtriple=x86_64-pc-linux-gnu -mcpu=corei7 -o - | FileCheck %s ; This test is fairly fragile. The goal is to ensure that "large" stack -; objects are allocated closest to the stack protector (i.e., farthest away +; objects are allocated closest to the stack protector (i.e., farthest away ; from the Stack Pointer.) In standard SSP mode this means that large (>= ; ssp-buffer-size) arrays and structures containing such arrays are ; closet to the protector. With sspstrong and sspreq this means large @@ -165,7 +165,7 @@ entry: %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* %8 = load i32, i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } @@ -176,7 +176,7 @@ entry: ; -56 large_char . arrays >= ssp-buffer-size ; -64 struct_large_char . ; -96 struct_large_nonchar . -; -100 small_non_char | Group 2, nested arrays, +; -100 small_non_char | Group 2, nested arrays, ; -102 small_char | arrays < ssp-buffer-size ; -104 struct_small_char | ; -112 struct_small_nonchar | @@ -184,7 +184,7 @@ entry: ; -120 scalar + Group 4, everything else ; -124 scalar + ; -128 scalar + -; +; ; CHECK: layout_sspstrong: ; CHECK: call{{l|q}} get_scalar1 ; CHECK: movl %eax, -120( @@ -309,14 +309,14 @@ entry: %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* %8 = load i32, i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } define void @layout_sspreq() nounwind uwtable sspreq { entry: ; Expected stack layout for sspreq is the same as sspstrong -; +; ; CHECK: layout_sspreq: ; CHECK: call{{l|q}} get_scalar1 ; CHECK: movl %eax, -120( @@ -441,7 +441,7 @@ entry: %coerce.dive26 = getelementptr %struct.struct_small_nonchar, %struct.struct_small_nonchar* %d, i32 0, i32 0 %7 = bitcast [2 x i16]* %coerce.dive26 to i32* %8 = load i32, i32* %7, align 1 - call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) + call void @takes_all(i64 %4, i16 %6, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 8 %c, i32 %8, i8* %arraydecay, i8* %arraydecay22, i32* %arraydecay23, i16* %arraydecay24, i32* %ptr, i32 %0, i32 %1, i32 %2) ret void } @@ -506,5 +506,5 @@ declare void @end_struct_large_nonchar() declare signext i16 @get_struct_small_nonchar() declare void @end_struct_small_nonchar() -declare void @takes_all(i64, i16, %struct.struct_large_nonchar* byval align 8, i32, i8*, i8*, i32*, i16*, i32*, i32, i32, i32) +declare void @takes_all(i64, i16, %struct.struct_large_nonchar* byval(%struct.struct_large_nonchar) align 8, i32, i8*, i8*, i32*, i16*, i32*, i32, i32, i32) declare void @takes_two(i32, i8*) diff --git a/llvm/test/CodeGen/X86/stack-align-memcpy.ll b/llvm/test/CodeGen/X86/stack-align-memcpy.ll index 25d3617662189..0dbab832156f8 100644 --- a/llvm/test/CodeGen/X86/stack-align-memcpy.ll +++ b/llvm/test/CodeGen/X86/stack-align-memcpy.ll @@ -3,7 +3,7 @@ %struct.foo = type { [88 x i8] } -declare void @bar(i8* nocapture, %struct.foo* align 4 byval) nounwind +declare void @bar(i8* nocapture, %struct.foo* align 4 byval(%struct.foo)) nounwind declare void @baz(i8*) nounwind ; PR15249 @@ -99,7 +99,7 @@ define void @test1(%struct.foo* nocapture %x, i32 %y) nounwind { ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl %dynalloc = alloca i8, i32 %y, align 1 - call void @bar(i8* %dynalloc, %struct.foo* align 4 byval %x) + call void @bar(i8* %dynalloc, %struct.foo* align 4 byval(%struct.foo) %x) ret void } @@ -199,7 +199,7 @@ define void @test2(%struct.foo* nocapture %x, i32 %y, i8* %z) nounwind { ; CHECK-NEXT: popl %ebx ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl - call void @bar(i8* %z, %struct.foo* align 4 byval %x) + call void @bar(i8* %z, %struct.foo* align 4 byval(%struct.foo) %x) %dynalloc = alloca i8, i32 %y, align 1 call void @baz(i8* %dynalloc) ret void @@ -230,7 +230,7 @@ define void @test3(%struct.foo* nocapture %x, i32 %y, i8* %z) nounwind { ; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %ebp ; CHECK-NEXT: retl - call void @bar(i8* %z, %struct.foo* align 4 byval %x) + call void @bar(i8* %z, %struct.foo* align 4 byval(%struct.foo) %x) %statalloc = alloca i8, i32 8, align 1 call void @baz(i8* %statalloc) ret void diff --git a/llvm/test/CodeGen/X86/stack-align.ll b/llvm/test/CodeGen/X86/stack-align.ll index 5987828f6fdf5..6b11efd4d6cbe 100644 --- a/llvm/test/CodeGen/X86/stack-align.ll +++ b/llvm/test/CodeGen/X86/stack-align.ll @@ -10,7 +10,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3 target triple = "i686-apple-darwin8" @G = external global double -define void @test({ double, double }* byval %z, double* %P) nounwind { +define void @test({ double, double }* byval({ double, double }) %z, double* %P) nounwind { entry: %tmp3 = load double, double* @G, align 16 ; [#uses=1] %tmp4 = tail call double @fabs( double %tmp3 ) readnone ; [#uses=1] @@ -66,7 +66,7 @@ entry: ; Accessing stack parameters shouldn't assume stack alignment. Here we should ; emit two 8-byte loads, followed by two 8-byte stores. -define x86_stdcallcc void @test5(%struct.sixteen* byval nocapture readonly align 4 %s) #0 { +define x86_stdcallcc void @test5(%struct.sixteen* byval(%struct.sixteen) nocapture readonly align 4 %s) #0 { %d.sroa.0 = alloca [16 x i8], align 1 %1 = getelementptr inbounds [16 x i8], [16 x i8]* %d.sroa.0, i32 0, i32 0 call void @llvm.lifetime.start.p0i8(i64 16, i8* %1) diff --git a/llvm/test/CodeGen/X86/stack-size-section-function-sections.ll b/llvm/test/CodeGen/X86/stack-size-section-function-sections.ll index 3fb2fa97e775b..92f312bd1185c 100644 --- a/llvm/test/CodeGen/X86/stack-size-section-function-sections.ll +++ b/llvm/test/CodeGen/X86/stack-size-section-function-sections.ll @@ -1,14 +1,23 @@ -; RUN: llc < %s -mtriple=x86_64-linux -stack-size-section -function-sections | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux -stack-size-section -function-sections | \ +; RUN: FileCheck %s --check-prefix=UNIQ +; RUN: llc < %s -mtriple=x86_64-linux -stack-size-section -function-sections -unique-section-names=0 | \ +; RUN: FileCheck %s --check-prefix=NOUNIQ ; Check we add SHF_LINK_ORDER for .stack_sizes and link it with the corresponding .text sections. -; CHECK: .section .text._Z3barv,"ax",@progbits -; CHECK: .section .stack_sizes,"o",@progbits,.text._Z3barv{{$}} -; CHECK: .section .text._Z3foov,"ax",@progbits -; CHECK: .section .stack_sizes,"o",@progbits,.text._Z3foov{{$}} +; UNIQ: .section .text._Z3barv,"ax",@progbits{{$}} +; UNIQ: .section .stack_sizes,"o",@progbits,.text._Z3barv{{$}} +; UNIQ: .section .text._Z3foov,"ax",@progbits{{$}} +; UNIQ: .section .stack_sizes,"o",@progbits,.text._Z3foov{{$}} +; NOUNIQ: .section .text,"ax",@progbits,unique,1 +; NOUNIQ: .section .stack_sizes,"o",@progbits,.text,unique,1 +; NOUNIQ: .section .text,"ax",@progbits,unique,2 +; NOUNIQ: .section .stack_sizes,"o",@progbits,.text,unique,2 ; Check we add .stack_size section to a COMDAT group with the corresponding .text section if such a COMDAT exists. -; CHECK: .section .text._Z4fooTIiET_v,"axG",@progbits,_Z4fooTIiET_v,comdat -; CHECK: .section .stack_sizes,"Go",@progbits,_Z4fooTIiET_v,comdat,.text._Z4fooTIiET_v{{$}} +; UNIQ: .section .text._Z4fooTIiET_v,"axG",@progbits,_Z4fooTIiET_v,comdat{{$}} +; UNIQ: .section .stack_sizes,"Go",@progbits,_Z4fooTIiET_v,comdat,.text._Z4fooTIiET_v{{$}} +; NOUNIQ: .section .text,"axG",@progbits,_Z4fooTIiET_v,comdat,unique,3 +; NOUNIQ: .section .stack_sizes,"Go",@progbits,_Z4fooTIiET_v,comdat,.text,unique,3 $_Z4fooTIiET_v = comdat any diff --git a/llvm/test/CodeGen/X86/statepoint-call-lowering.ll b/llvm/test/CodeGen/X86/statepoint-call-lowering.ll index 3fac4b784a407..a371db4c0bb69 100644 --- a/llvm/test/CodeGen/X86/statepoint-call-lowering.ll +++ b/llvm/test/CodeGen/X86/statepoint-call-lowering.ll @@ -204,9 +204,9 @@ right: %struct2 = type { i64, i64, i64 } -declare void @consume_attributes(i32, i8* nest, i32, %struct2* byval) +declare void @consume_attributes(i32, i8* nest, i32, %struct2* byval(%struct2)) -define void @test_attributes(%struct2* byval %s) gc "statepoint-example" { +define void @test_attributes(%struct2* byval(%struct2) %s) gc "statepoint-example" { ; CHECK-LABEL: test_attributes: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pushq %rax @@ -235,7 +235,7 @@ define void @test_attributes(%struct2* byval %s) gc "statepoint-example" { entry: ; Check that arguments with attributes are lowered correctly. ; We call a function that has a nest argument and a byval argument. - %statepoint_token = call token (i64, i32, void (i32, i8*, i32, %struct2*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32p0i8i32p0s_struct2sf(i64 0, i32 0, void (i32, i8*, i32, %struct2*)* @consume_attributes, i32 4, i32 0, i32 42, i8* nest null, i32 17, %struct2* byval %s, i32 0, i32 0) + %statepoint_token = call token (i64, i32, void (i32, i8*, i32, %struct2*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidi32p0i8i32p0s_struct2sf(i64 0, i32 0, void (i32, i8*, i32, %struct2*)* @consume_attributes, i32 4, i32 0, i32 42, i8* nest null, i32 17, %struct2* byval(%struct2) %s, i32 0, i32 0) ret void } diff --git a/llvm/test/CodeGen/X86/statepoint-stackmap-format.ll b/llvm/test/CodeGen/X86/statepoint-stackmap-format.ll index 896aedfaeb273..370b8006b969a 100644 --- a/llvm/test/CodeGen/X86/statepoint-stackmap-format.ll +++ b/llvm/test/CodeGen/X86/statepoint-stackmap-format.ll @@ -103,7 +103,7 @@ define i32 @test_spadj(i32 addrspace(1)* %p) gc "statepoint-example" { declare void @use(%struct*) -define void @test_fixed_arg(%struct* byval %x) gc "statepoint-example" { +define void @test_fixed_arg(%struct* byval(%struct) %x) gc "statepoint-example" { ; CHECK-LABEL: test_fixed_arg ; CHECK: pushq %rax ; CHECK: leaq 16(%rsp), %rdi diff --git a/llvm/test/CodeGen/X86/subcarry.ll b/llvm/test/CodeGen/X86/subcarry.ll index f5476cdebdd35..18167458bd610 100644 --- a/llvm/test/CodeGen/X86/subcarry.ll +++ b/llvm/test/CodeGen/X86/subcarry.ll @@ -312,7 +312,7 @@ define i32 @sub_U320_usubo(%struct.U320* nocapture dereferenceable(40) %0, i64 % %struct.U192 = type { [3 x i64] } -define void @PR39464(%struct.U192* noalias nocapture sret %0, %struct.U192* nocapture readonly dereferenceable(24) %1, %struct.U192* nocapture readonly dereferenceable(24) %2) { +define void @PR39464(%struct.U192* noalias nocapture sret(%struct.U192) %0, %struct.U192* nocapture readonly dereferenceable(24) %1, %struct.U192* nocapture readonly dereferenceable(24) %2) { ; CHECK-LABEL: PR39464: ; CHECK: # %bb.0: ; CHECK-NEXT: movq %rdi, %rax @@ -366,7 +366,7 @@ define void @PR39464(%struct.U192* noalias nocapture sret %0, %struct.U192* noca ; The 256-bit subtraction implementation using two inlined usubo procedures for U128 type { i64, i64 }. ; This is similar to how LLVM legalize types in CodeGen. -define void @sub_U256_without_i128_or_recursive(%uint256* sret %0, %uint256* %1, %uint256* %2) nounwind { +define void @sub_U256_without_i128_or_recursive(%uint256* sret(%uint256) %0, %uint256* %1, %uint256* %2) nounwind { ; CHECK-LABEL: sub_U256_without_i128_or_recursive: ; CHECK: # %bb.0: ; CHECK-NEXT: movq %rdi, %rax diff --git a/llvm/test/CodeGen/X86/swift-return.ll b/llvm/test/CodeGen/X86/swift-return.ll index 11312f08edfa3..fc31154059630 100644 --- a/llvm/test/CodeGen/X86/swift-return.ll +++ b/llvm/test/CodeGen/X86/swift-return.ll @@ -294,7 +294,7 @@ define void @consume_i1_ret() { declare swiftcc { i1, i1, i1, i1 } @produce_i1_ret() -define swiftcc void @foo(i64* sret %agg.result, i64 %val) { +define swiftcc void @foo(i64* sret(i64) %agg.result, i64 %val) { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: ; CHECK-NEXT: movq %rdi, (%rax) diff --git a/llvm/test/CodeGen/X86/swifterror.ll b/llvm/test/CodeGen/X86/swifterror.ll index ffb896926738b..ac23473b8eccd 100644 --- a/llvm/test/CodeGen/X86/swifterror.ll +++ b/llvm/test/CodeGen/X86/swifterror.ll @@ -204,7 +204,7 @@ bb_end: ; "foo_sret" is a function that takes a swifterror parameter, it also has a sret ; parameter. -define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { +define void @foo_sret(%struct.S* sret(%struct.S) %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { ; CHECK-APPLE-LABEL: foo_sret: ; CHECK-APPLE: movq %rdi, %{{.*}} ; CHECK-APPLE: movl $16, %edi @@ -269,7 +269,7 @@ entry: %s = alloca %struct.S, align 8 %error_ptr_ref = alloca swifterror %swift_error* store %swift_error* null, %swift_error** %error_ptr_ref - call void @foo_sret(%struct.S* sret %s, i32 1, %swift_error** swifterror %error_ptr_ref) + call void @foo_sret(%struct.S* sret(%struct.S) %s, i32 1, %swift_error** swifterror %error_ptr_ref) %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null %tmp = bitcast %swift_error* %error_from_foo to i8* diff --git a/llvm/test/CodeGen/X86/tailcallbyval.ll b/llvm/test/CodeGen/X86/tailcallbyval.ll index 8a0113a645a35..66d88d05c48b0 100644 --- a/llvm/test/CodeGen/X86/tailcallbyval.ll +++ b/llvm/test/CodeGen/X86/tailcallbyval.ll @@ -3,7 +3,7 @@ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } -define fastcc i32 @tailcallee(%struct.s* byval %a) nounwind { +define fastcc i32 @tailcallee(%struct.s* byval(%struct.s) %a) nounwind { entry: %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 0 %tmp3 = load i32, i32* %tmp2 @@ -12,9 +12,9 @@ entry: ; CHECK: movl 4(%esp), %eax } -define fastcc i32 @tailcaller(%struct.s* byval %a) nounwind { +define fastcc i32 @tailcaller(%struct.s* byval(%struct.s) %a) nounwind { entry: - %tmp4 = tail call fastcc i32 @tailcallee(%struct.s* byval %a ) + %tmp4 = tail call fastcc i32 @tailcallee(%struct.s* byval(%struct.s) %a ) ret i32 %tmp4 ; CHECK: tailcaller ; CHECK: jmp tailcallee diff --git a/llvm/test/CodeGen/X86/tailcallbyval64.ll b/llvm/test/CodeGen/X86/tailcallbyval64.ll index 9df1470c67f13..66ef596931709 100644 --- a/llvm/test/CodeGen/X86/tailcallbyval64.ll +++ b/llvm/test/CodeGen/X86/tailcallbyval64.ll @@ -12,7 +12,7 @@ ; A sequence of copyto/copyfrom virtual registers is used to deal with byval ; lowering appearing after moving arguments to registers. The following two ; checks verify that the register allocator changes those sequences to direct -; moves to argument register where it can (for registers that are not used in +; moves to argument register where it can (for registers that are not used in ; byval lowering - not rsi, not rdi, not rcx). ; Expect argument 4 to be moved directly to register edx. ; CHECK: movl $7, %edx @@ -30,13 +30,13 @@ i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } -declare fastcc i64 @tailcallee(%struct.s* byval %a, i64 %val, i64 %val2, i64 %val3, i64 %val4, i64 %val5) +declare fastcc i64 @tailcallee(%struct.s* byval(%struct.s) %a, i64 %val, i64 %val2, i64 %val3, i64 %val4, i64 %val5) -define fastcc i64 @tailcaller(i64 %b, %struct.s* byval %a) { +define fastcc i64 @tailcaller(i64 %b, %struct.s* byval(%struct.s) %a) { entry: %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 1 %tmp3 = load i64, i64* %tmp2, align 8 - %tmp4 = tail call fastcc i64 @tailcallee(%struct.s* byval %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17) + %tmp4 = tail call fastcc i64 @tailcallee(%struct.s* byval(%struct.s) %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17) ret i64 %tmp4 } diff --git a/llvm/test/CodeGen/X86/tailccbyval.ll b/llvm/test/CodeGen/X86/tailccbyval.ll index dbde868e51114..cdb492569bf6b 100644 --- a/llvm/test/CodeGen/X86/tailccbyval.ll +++ b/llvm/test/CodeGen/X86/tailccbyval.ll @@ -3,7 +3,7 @@ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } -define tailcc i32 @tailcallee(%struct.s* byval %a) nounwind { +define tailcc i32 @tailcallee(%struct.s* byval(%struct.s) %a) nounwind { entry: %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 0 %tmp3 = load i32, i32* %tmp2 @@ -12,9 +12,9 @@ entry: ; CHECK: movl 4(%esp), %eax } -define tailcc i32 @tailcaller(%struct.s* byval %a) nounwind { +define tailcc i32 @tailcaller(%struct.s* byval(%struct.s) %a) nounwind { entry: - %tmp4 = tail call tailcc i32 @tailcallee(%struct.s* byval %a ) + %tmp4 = tail call tailcc i32 @tailcallee(%struct.s* byval(%struct.s) %a ) ret i32 %tmp4 ; CHECK: tailcaller ; CHECK: jmp tailcallee diff --git a/llvm/test/CodeGen/X86/tailccbyval64.ll b/llvm/test/CodeGen/X86/tailccbyval64.ll index 47d20ea972adb..3363b319e3751 100644 --- a/llvm/test/CodeGen/X86/tailccbyval64.ll +++ b/llvm/test/CodeGen/X86/tailccbyval64.ll @@ -12,7 +12,7 @@ ; A sequence of copyto/copyfrom virtual registers is used to deal with byval ; lowering appearing after moving arguments to registers. The following two ; checks verify that the register allocator changes those sequences to direct -; moves to argument register where it can (for registers that are not used in +; moves to argument register where it can (for registers that are not used in ; byval lowering - not rsi, not rdi, not rcx). ; Expect argument 4 to be moved directly to register edx. ; CHECK: movl $7, %edx @@ -30,13 +30,13 @@ i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64 } -declare tailcc i64 @tailcallee(%struct.s* byval %a, i64 %val, i64 %val2, i64 %val3, i64 %val4, i64 %val5) +declare tailcc i64 @tailcallee(%struct.s* byval(%struct.s) %a, i64 %val, i64 %val2, i64 %val3, i64 %val4, i64 %val5) -define tailcc i64 @tailcaller(i64 %b, %struct.s* byval %a) { +define tailcc i64 @tailcaller(i64 %b, %struct.s* byval(%struct.s) %a) { entry: %tmp2 = getelementptr %struct.s, %struct.s* %a, i32 0, i32 1 %tmp3 = load i64, i64* %tmp2, align 8 - %tmp4 = tail call tailcc i64 @tailcallee(%struct.s* byval %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17) + %tmp4 = tail call tailcc i64 @tailcallee(%struct.s* byval(%struct.s) %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17) ret i64 %tmp4 } diff --git a/llvm/test/CodeGen/X86/uadd_sat_vec.ll b/llvm/test/CodeGen/X86/uadd_sat_vec.ll index 1a50b30d14eb8..45fe82feb8b5c 100644 --- a/llvm/test/CodeGen/X86/uadd_sat_vec.ll +++ b/llvm/test/CodeGen/X86/uadd_sat_vec.ll @@ -750,17 +750,16 @@ define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind { ; ; AVX1-LABEL: v8i32: ; AVX1: # %bb.0: -; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2 -; AVX1-NEXT: vcmptrueps %ymm2, %ymm2, %ymm2 -; AVX1-NEXT: vxorps %ymm2, %ymm1, %ymm2 -; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3 -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 -; AVX1-NEXT: vpminud %xmm3, %xmm4, %xmm3 -; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 -; AVX1-NEXT: vpaddd %xmm4, %xmm3, %xmm3 -; AVX1-NEXT: vpminud %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3 +; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm4 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5 +; AVX1-NEXT: vpminud %xmm4, %xmm5, %xmm4 +; AVX1-NEXT: vpaddd %xmm2, %xmm4, %xmm2 +; AVX1-NEXT: vpxor %xmm3, %xmm1, %xmm3 +; AVX1-NEXT: vpminud %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: v8i32: @@ -870,26 +869,25 @@ define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind { ; ; AVX1-LABEL: v16i32: ; AVX1: # %bb.0: -; AVX1-NEXT: vxorps %xmm4, %xmm4, %xmm4 -; AVX1-NEXT: vcmptrueps %ymm4, %ymm4, %ymm4 -; AVX1-NEXT: vxorps %ymm4, %ymm2, %ymm5 -; AVX1-NEXT: vextractf128 $1, %ymm5, %xmm6 +; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4 +; AVX1-NEXT: vpcmpeqd %xmm5, %xmm5, %xmm5 +; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm6 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm7 ; AVX1-NEXT: vpminud %xmm6, %xmm7, %xmm6 -; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm7 -; AVX1-NEXT: vpaddd %xmm7, %xmm6, %xmm6 -; AVX1-NEXT: vpminud %xmm5, %xmm0, %xmm0 +; AVX1-NEXT: vpaddd %xmm4, %xmm6, %xmm4 +; AVX1-NEXT: vpxor %xmm5, %xmm2, %xmm6 +; AVX1-NEXT: vpminud %xmm6, %xmm0, %xmm0 ; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm6, %ymm0, %ymm0 -; AVX1-NEXT: vxorps %ymm4, %ymm3, %ymm2 -; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4 -; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 -; AVX1-NEXT: vpminud %xmm4, %xmm5, %xmm4 -; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm5 -; AVX1-NEXT: vpaddd %xmm5, %xmm4, %xmm4 -; AVX1-NEXT: vpminud %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 +; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2 +; AVX1-NEXT: vpxor %xmm5, %xmm2, %xmm4 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm6 +; AVX1-NEXT: vpminud %xmm4, %xmm6, %xmm4 +; AVX1-NEXT: vpaddd %xmm2, %xmm4, %xmm2 +; AVX1-NEXT: vpxor %xmm5, %xmm3, %xmm4 +; AVX1-NEXT: vpminud %xmm4, %xmm1, %xmm1 ; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1 -; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm1, %ymm1 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; AVX1-NEXT: retq ; ; AVX2-LABEL: v16i32: @@ -915,57 +913,22 @@ define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind { } define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { -; SSE2-LABEL: v2i64: -; SSE2: # %bb.0: -; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] -; SSE2-NEXT: paddq %xmm0, %xmm1 -; SSE2-NEXT: pxor %xmm2, %xmm0 -; SSE2-NEXT: pxor %xmm1, %xmm2 -; SSE2-NEXT: movdqa %xmm0, %xmm3 -; SSE2-NEXT: pcmpgtd %xmm2, %xmm3 -; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm0, %xmm2 -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; SSE2-NEXT: pand %xmm4, %xmm2 -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] -; SSE2-NEXT: por %xmm1, %xmm0 -; SSE2-NEXT: por %xmm2, %xmm0 -; SSE2-NEXT: retq -; -; SSSE3-LABEL: v2i64: -; SSSE3: # %bb.0: -; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] -; SSSE3-NEXT: paddq %xmm0, %xmm1 -; SSSE3-NEXT: pxor %xmm2, %xmm0 -; SSSE3-NEXT: pxor %xmm1, %xmm2 -; SSSE3-NEXT: movdqa %xmm0, %xmm3 -; SSSE3-NEXT: pcmpgtd %xmm2, %xmm3 -; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm0, %xmm2 -; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; SSSE3-NEXT: pand %xmm4, %xmm2 -; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] -; SSSE3-NEXT: por %xmm1, %xmm0 -; SSSE3-NEXT: por %xmm2, %xmm0 -; SSSE3-NEXT: retq -; -; SSE41-LABEL: v2i64: -; SSE41: # %bb.0: -; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] -; SSE41-NEXT: paddq %xmm0, %xmm1 -; SSE41-NEXT: movdqa %xmm0, %xmm3 -; SSE41-NEXT: pxor %xmm2, %xmm3 -; SSE41-NEXT: pxor %xmm1, %xmm2 -; SSE41-NEXT: movdqa %xmm3, %xmm0 -; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 -; SSE41-NEXT: pcmpgtd %xmm2, %xmm3 -; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,0,2,2] -; SSE41-NEXT: pand %xmm2, %xmm0 -; SSE41-NEXT: por %xmm3, %xmm0 -; SSE41-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1 -; SSE41-NEXT: movapd %xmm1, %xmm0 -; SSE41-NEXT: retq +; SSE-LABEL: v2i64: +; SSE: # %bb.0: +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] +; SSE-NEXT: paddq %xmm0, %xmm1 +; SSE-NEXT: pxor %xmm2, %xmm0 +; SSE-NEXT: pxor %xmm1, %xmm2 +; SSE-NEXT: movdqa %xmm0, %xmm3 +; SSE-NEXT: pcmpgtd %xmm2, %xmm3 +; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm0, %xmm2 +; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE-NEXT: pand %xmm4, %xmm2 +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3] +; SSE-NEXT: por %xmm1, %xmm0 +; SSE-NEXT: por %xmm2, %xmm0 +; SSE-NEXT: retq ; ; AVX1-LABEL: v2i64: ; AVX1: # %bb.0: @@ -1010,129 +973,62 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { } define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { -; SSE2-LABEL: v4i64: -; SSE2: # %bb.0: -; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] -; SSE2-NEXT: paddq %xmm0, %xmm2 -; SSE2-NEXT: pxor %xmm4, %xmm0 -; SSE2-NEXT: movdqa %xmm2, %xmm5 -; SSE2-NEXT: pxor %xmm4, %xmm5 -; SSE2-NEXT: movdqa %xmm0, %xmm6 -; SSE2-NEXT: pcmpgtd %xmm5, %xmm6 -; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm0, %xmm5 -; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] -; SSE2-NEXT: pand %xmm7, %xmm5 -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] -; SSE2-NEXT: por %xmm2, %xmm0 -; SSE2-NEXT: por %xmm5, %xmm0 -; SSE2-NEXT: paddq %xmm1, %xmm3 -; SSE2-NEXT: pxor %xmm4, %xmm1 -; SSE2-NEXT: pxor %xmm3, %xmm4 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: pcmpgtd %xmm4, %xmm2 -; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm2[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm1, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] -; SSE2-NEXT: pand %xmm5, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] -; SSE2-NEXT: por %xmm3, %xmm1 -; SSE2-NEXT: por %xmm4, %xmm1 -; SSE2-NEXT: retq -; -; SSSE3-LABEL: v4i64: -; SSSE3: # %bb.0: -; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] -; SSSE3-NEXT: paddq %xmm0, %xmm2 -; SSSE3-NEXT: pxor %xmm4, %xmm0 -; SSSE3-NEXT: movdqa %xmm2, %xmm5 -; SSSE3-NEXT: pxor %xmm4, %xmm5 -; SSSE3-NEXT: movdqa %xmm0, %xmm6 -; SSSE3-NEXT: pcmpgtd %xmm5, %xmm6 -; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm0, %xmm5 -; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] -; SSSE3-NEXT: pand %xmm7, %xmm5 -; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] -; SSSE3-NEXT: por %xmm2, %xmm0 -; SSSE3-NEXT: por %xmm5, %xmm0 -; SSSE3-NEXT: paddq %xmm1, %xmm3 -; SSSE3-NEXT: pxor %xmm4, %xmm1 -; SSSE3-NEXT: pxor %xmm3, %xmm4 -; SSSE3-NEXT: movdqa %xmm1, %xmm2 -; SSSE3-NEXT: pcmpgtd %xmm4, %xmm2 -; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm2[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm1, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] -; SSSE3-NEXT: pand %xmm5, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] -; SSSE3-NEXT: por %xmm3, %xmm1 -; SSSE3-NEXT: por %xmm4, %xmm1 -; SSSE3-NEXT: retq -; -; SSE41-LABEL: v4i64: -; SSE41: # %bb.0: -; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] -; SSE41-NEXT: paddq %xmm0, %xmm2 -; SSE41-NEXT: movdqa %xmm0, %xmm5 -; SSE41-NEXT: pxor %xmm4, %xmm5 -; SSE41-NEXT: movdqa %xmm2, %xmm6 -; SSE41-NEXT: pxor %xmm4, %xmm6 -; SSE41-NEXT: movdqa %xmm5, %xmm0 -; SSE41-NEXT: pcmpeqd %xmm6, %xmm0 -; SSE41-NEXT: pcmpgtd %xmm6, %xmm5 -; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] -; SSE41-NEXT: pand %xmm6, %xmm0 -; SSE41-NEXT: por %xmm5, %xmm0 -; SSE41-NEXT: pcmpeqd %xmm5, %xmm5 -; SSE41-NEXT: blendvpd %xmm0, %xmm5, %xmm2 -; SSE41-NEXT: paddq %xmm1, %xmm3 -; SSE41-NEXT: pxor %xmm4, %xmm1 -; SSE41-NEXT: pxor %xmm3, %xmm4 -; SSE41-NEXT: movdqa %xmm1, %xmm6 -; SSE41-NEXT: pcmpeqd %xmm4, %xmm6 -; SSE41-NEXT: pcmpgtd %xmm4, %xmm1 -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,2,2] -; SSE41-NEXT: pand %xmm6, %xmm0 -; SSE41-NEXT: por %xmm1, %xmm0 -; SSE41-NEXT: blendvpd %xmm0, %xmm5, %xmm3 -; SSE41-NEXT: movapd %xmm2, %xmm0 -; SSE41-NEXT: movapd %xmm3, %xmm1 -; SSE41-NEXT: retq +; SSE-LABEL: v4i64: +; SSE: # %bb.0: +; SSE-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] +; SSE-NEXT: paddq %xmm0, %xmm2 +; SSE-NEXT: pxor %xmm4, %xmm0 +; SSE-NEXT: movdqa %xmm2, %xmm5 +; SSE-NEXT: pxor %xmm4, %xmm5 +; SSE-NEXT: movdqa %xmm0, %xmm6 +; SSE-NEXT: pcmpgtd %xmm5, %xmm6 +; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm0, %xmm5 +; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] +; SSE-NEXT: pand %xmm7, %xmm5 +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] +; SSE-NEXT: por %xmm2, %xmm0 +; SSE-NEXT: por %xmm5, %xmm0 +; SSE-NEXT: paddq %xmm1, %xmm3 +; SSE-NEXT: pxor %xmm4, %xmm1 +; SSE-NEXT: pxor %xmm3, %xmm4 +; SSE-NEXT: movdqa %xmm1, %xmm2 +; SSE-NEXT: pcmpgtd %xmm4, %xmm2 +; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm2[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm1, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] +; SSE-NEXT: pand %xmm5, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] +; SSE-NEXT: por %xmm3, %xmm1 +; SSE-NEXT: por %xmm4, %xmm1 +; SSE-NEXT: retq ; ; AVX1-LABEL: v4i64: ; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808] ; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm4 -; AVX1-NEXT: vxorps %xmm5, %xmm5, %xmm5 -; AVX1-NEXT: vcmptrueps %ymm5, %ymm5, %ymm5 -; AVX1-NEXT: vxorps %ymm5, %ymm1, %ymm5 -; AVX1-NEXT: vextractf128 $1, %ymm5, %xmm6 -; AVX1-NEXT: vpxor %xmm3, %xmm6, %xmm7 -; AVX1-NEXT: vpcmpgtq %xmm4, %xmm7, %xmm4 -; AVX1-NEXT: vblendvpd %xmm4, %xmm2, %xmm6, %xmm2 -; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 -; AVX1-NEXT: vpaddq %xmm4, %xmm2, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 +; AVX1-NEXT: vpaddq %xmm5, %xmm2, %xmm2 +; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm5 +; AVX1-NEXT: vpcmpgtq %xmm5, %xmm4, %xmm4 +; AVX1-NEXT: vpor %xmm2, %xmm4, %xmm2 ; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm4 -; AVX1-NEXT: vxorps %xmm3, %xmm5, %xmm3 -; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm3 -; AVX1-NEXT: vblendvpd %xmm3, %xmm0, %xmm5, %xmm0 ; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm1 +; AVX1-NEXT: vpcmpgtq %xmm1, %xmm4, %xmm1 +; AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: v4i64: ; AVX2: # %bb.0: ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] -; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm2 -; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [9223372036854775807,9223372036854775807,9223372036854775807,9223372036854775807] -; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm3 -; AVX2-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2 -; AVX2-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3 -; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm3 -; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm3, %ymm0 +; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm3 ; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm1 +; AVX2-NEXT: vpcmpgtq %ymm1, %ymm3, %ymm1 +; AVX2-NEXT: vpor %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: retq ; ; AVX512F-LABEL: v4i64: @@ -1157,210 +1053,90 @@ define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { } define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind { -; SSE2-LABEL: v8i64: -; SSE2: # %bb.0: -; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456] -; SSE2-NEXT: paddq %xmm0, %xmm4 -; SSE2-NEXT: pxor %xmm8, %xmm0 -; SSE2-NEXT: movdqa %xmm4, %xmm9 -; SSE2-NEXT: pxor %xmm8, %xmm9 -; SSE2-NEXT: movdqa %xmm0, %xmm10 -; SSE2-NEXT: pcmpgtd %xmm9, %xmm10 -; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm10[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm0, %xmm9 -; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm9[1,1,3,3] -; SSE2-NEXT: pand %xmm11, %xmm9 -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm10[1,1,3,3] -; SSE2-NEXT: por %xmm4, %xmm0 -; SSE2-NEXT: por %xmm9, %xmm0 -; SSE2-NEXT: paddq %xmm1, %xmm5 -; SSE2-NEXT: pxor %xmm8, %xmm1 -; SSE2-NEXT: movdqa %xmm5, %xmm4 -; SSE2-NEXT: pxor %xmm8, %xmm4 -; SSE2-NEXT: movdqa %xmm1, %xmm9 -; SSE2-NEXT: pcmpgtd %xmm4, %xmm9 -; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm1, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] -; SSE2-NEXT: pand %xmm10, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm9[1,1,3,3] -; SSE2-NEXT: por %xmm5, %xmm1 -; SSE2-NEXT: por %xmm4, %xmm1 -; SSE2-NEXT: paddq %xmm2, %xmm6 -; SSE2-NEXT: pxor %xmm8, %xmm2 -; SSE2-NEXT: movdqa %xmm6, %xmm4 -; SSE2-NEXT: pxor %xmm8, %xmm4 -; SSE2-NEXT: movdqa %xmm2, %xmm5 -; SSE2-NEXT: pcmpgtd %xmm4, %xmm5 -; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm2, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] -; SSE2-NEXT: pand %xmm9, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] -; SSE2-NEXT: por %xmm6, %xmm2 -; SSE2-NEXT: por %xmm4, %xmm2 -; SSE2-NEXT: paddq %xmm3, %xmm7 -; SSE2-NEXT: pxor %xmm8, %xmm3 -; SSE2-NEXT: pxor %xmm7, %xmm8 -; SSE2-NEXT: movdqa %xmm3, %xmm4 -; SSE2-NEXT: pcmpgtd %xmm8, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm3, %xmm8 -; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm8[1,1,3,3] -; SSE2-NEXT: pand %xmm5, %xmm6 -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] -; SSE2-NEXT: por %xmm7, %xmm3 -; SSE2-NEXT: por %xmm6, %xmm3 -; SSE2-NEXT: retq -; -; SSSE3-LABEL: v8i64: -; SSSE3: # %bb.0: -; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456] -; SSSE3-NEXT: paddq %xmm0, %xmm4 -; SSSE3-NEXT: pxor %xmm8, %xmm0 -; SSSE3-NEXT: movdqa %xmm4, %xmm9 -; SSSE3-NEXT: pxor %xmm8, %xmm9 -; SSSE3-NEXT: movdqa %xmm0, %xmm10 -; SSSE3-NEXT: pcmpgtd %xmm9, %xmm10 -; SSSE3-NEXT: pshufd {{.*#+}} xmm11 = xmm10[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm0, %xmm9 -; SSSE3-NEXT: pshufd {{.*#+}} xmm9 = xmm9[1,1,3,3] -; SSSE3-NEXT: pand %xmm11, %xmm9 -; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm10[1,1,3,3] -; SSSE3-NEXT: por %xmm4, %xmm0 -; SSSE3-NEXT: por %xmm9, %xmm0 -; SSSE3-NEXT: paddq %xmm1, %xmm5 -; SSSE3-NEXT: pxor %xmm8, %xmm1 -; SSSE3-NEXT: movdqa %xmm5, %xmm4 -; SSSE3-NEXT: pxor %xmm8, %xmm4 -; SSSE3-NEXT: movdqa %xmm1, %xmm9 -; SSSE3-NEXT: pcmpgtd %xmm4, %xmm9 -; SSSE3-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm1, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] -; SSSE3-NEXT: pand %xmm10, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm9[1,1,3,3] -; SSSE3-NEXT: por %xmm5, %xmm1 -; SSSE3-NEXT: por %xmm4, %xmm1 -; SSSE3-NEXT: paddq %xmm2, %xmm6 -; SSSE3-NEXT: pxor %xmm8, %xmm2 -; SSSE3-NEXT: movdqa %xmm6, %xmm4 -; SSSE3-NEXT: pxor %xmm8, %xmm4 -; SSSE3-NEXT: movdqa %xmm2, %xmm5 -; SSSE3-NEXT: pcmpgtd %xmm4, %xmm5 -; SSSE3-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm2, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] -; SSSE3-NEXT: pand %xmm9, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] -; SSSE3-NEXT: por %xmm6, %xmm2 -; SSSE3-NEXT: por %xmm4, %xmm2 -; SSSE3-NEXT: paddq %xmm3, %xmm7 -; SSSE3-NEXT: pxor %xmm8, %xmm3 -; SSSE3-NEXT: pxor %xmm7, %xmm8 -; SSSE3-NEXT: movdqa %xmm3, %xmm4 -; SSSE3-NEXT: pcmpgtd %xmm8, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm3, %xmm8 -; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm8[1,1,3,3] -; SSSE3-NEXT: pand %xmm5, %xmm6 -; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] -; SSSE3-NEXT: por %xmm7, %xmm3 -; SSSE3-NEXT: por %xmm6, %xmm3 -; SSSE3-NEXT: retq -; -; SSE41-LABEL: v8i64: -; SSE41: # %bb.0: -; SSE41-NEXT: movdqa %xmm7, %xmm8 -; SSE41-NEXT: movdqa %xmm6, %xmm10 -; SSE41-NEXT: movdqa %xmm5, %xmm11 -; SSE41-NEXT: movdqa %xmm4, %xmm5 -; SSE41-NEXT: movdqa {{.*#+}} xmm7 = [9223372039002259456,9223372039002259456] -; SSE41-NEXT: paddq %xmm0, %xmm5 -; SSE41-NEXT: movdqa %xmm0, %xmm6 -; SSE41-NEXT: pxor %xmm7, %xmm6 -; SSE41-NEXT: movdqa %xmm5, %xmm4 -; SSE41-NEXT: pxor %xmm7, %xmm4 -; SSE41-NEXT: movdqa %xmm6, %xmm0 -; SSE41-NEXT: pcmpeqd %xmm4, %xmm0 -; SSE41-NEXT: pcmpgtd %xmm4, %xmm6 -; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm6[0,0,2,2] -; SSE41-NEXT: pand %xmm4, %xmm0 -; SSE41-NEXT: por %xmm6, %xmm0 -; SSE41-NEXT: pcmpeqd %xmm9, %xmm9 -; SSE41-NEXT: blendvpd %xmm0, %xmm9, %xmm5 -; SSE41-NEXT: paddq %xmm1, %xmm11 -; SSE41-NEXT: pxor %xmm7, %xmm1 -; SSE41-NEXT: movdqa %xmm11, %xmm0 -; SSE41-NEXT: pxor %xmm7, %xmm0 -; SSE41-NEXT: movdqa %xmm1, %xmm4 -; SSE41-NEXT: pcmpeqd %xmm0, %xmm4 -; SSE41-NEXT: pcmpgtd %xmm0, %xmm1 -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,2,2] -; SSE41-NEXT: pand %xmm4, %xmm0 -; SSE41-NEXT: por %xmm1, %xmm0 -; SSE41-NEXT: blendvpd %xmm0, %xmm9, %xmm11 -; SSE41-NEXT: paddq %xmm2, %xmm10 -; SSE41-NEXT: pxor %xmm7, %xmm2 -; SSE41-NEXT: movdqa %xmm10, %xmm0 -; SSE41-NEXT: pxor %xmm7, %xmm0 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: pcmpeqd %xmm0, %xmm1 -; SSE41-NEXT: pcmpgtd %xmm0, %xmm2 -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2] -; SSE41-NEXT: pand %xmm1, %xmm0 -; SSE41-NEXT: por %xmm2, %xmm0 -; SSE41-NEXT: blendvpd %xmm0, %xmm9, %xmm10 -; SSE41-NEXT: paddq %xmm3, %xmm8 -; SSE41-NEXT: pxor %xmm7, %xmm3 -; SSE41-NEXT: pxor %xmm8, %xmm7 -; SSE41-NEXT: movdqa %xmm3, %xmm1 -; SSE41-NEXT: pcmpeqd %xmm7, %xmm1 -; SSE41-NEXT: pcmpgtd %xmm7, %xmm3 -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,2,2] -; SSE41-NEXT: pand %xmm1, %xmm0 -; SSE41-NEXT: por %xmm3, %xmm0 -; SSE41-NEXT: blendvpd %xmm0, %xmm9, %xmm8 -; SSE41-NEXT: movapd %xmm5, %xmm0 -; SSE41-NEXT: movapd %xmm11, %xmm1 -; SSE41-NEXT: movapd %xmm10, %xmm2 -; SSE41-NEXT: movapd %xmm8, %xmm3 -; SSE41-NEXT: retq +; SSE-LABEL: v8i64: +; SSE: # %bb.0: +; SSE-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456] +; SSE-NEXT: paddq %xmm0, %xmm4 +; SSE-NEXT: pxor %xmm8, %xmm0 +; SSE-NEXT: movdqa %xmm4, %xmm9 +; SSE-NEXT: pxor %xmm8, %xmm9 +; SSE-NEXT: movdqa %xmm0, %xmm10 +; SSE-NEXT: pcmpgtd %xmm9, %xmm10 +; SSE-NEXT: pshufd {{.*#+}} xmm11 = xmm10[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm0, %xmm9 +; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm9[1,1,3,3] +; SSE-NEXT: pand %xmm11, %xmm9 +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm10[1,1,3,3] +; SSE-NEXT: por %xmm4, %xmm0 +; SSE-NEXT: por %xmm9, %xmm0 +; SSE-NEXT: paddq %xmm1, %xmm5 +; SSE-NEXT: pxor %xmm8, %xmm1 +; SSE-NEXT: movdqa %xmm5, %xmm4 +; SSE-NEXT: pxor %xmm8, %xmm4 +; SSE-NEXT: movdqa %xmm1, %xmm9 +; SSE-NEXT: pcmpgtd %xmm4, %xmm9 +; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm1, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] +; SSE-NEXT: pand %xmm10, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm9[1,1,3,3] +; SSE-NEXT: por %xmm5, %xmm1 +; SSE-NEXT: por %xmm4, %xmm1 +; SSE-NEXT: paddq %xmm2, %xmm6 +; SSE-NEXT: pxor %xmm8, %xmm2 +; SSE-NEXT: movdqa %xmm6, %xmm4 +; SSE-NEXT: pxor %xmm8, %xmm4 +; SSE-NEXT: movdqa %xmm2, %xmm5 +; SSE-NEXT: pcmpgtd %xmm4, %xmm5 +; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm2, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] +; SSE-NEXT: pand %xmm9, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] +; SSE-NEXT: por %xmm6, %xmm2 +; SSE-NEXT: por %xmm4, %xmm2 +; SSE-NEXT: paddq %xmm3, %xmm7 +; SSE-NEXT: pxor %xmm8, %xmm3 +; SSE-NEXT: pxor %xmm7, %xmm8 +; SSE-NEXT: movdqa %xmm3, %xmm4 +; SSE-NEXT: pcmpgtd %xmm8, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm3, %xmm8 +; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm8[1,1,3,3] +; SSE-NEXT: pand %xmm5, %xmm6 +; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] +; SSE-NEXT: por %xmm7, %xmm3 +; SSE-NEXT: por %xmm6, %xmm3 +; SSE-NEXT: retq ; ; AVX1-LABEL: v8i64: ; AVX1: # %bb.0: -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5 -; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808] -; AVX1-NEXT: vpxor %xmm4, %xmm5, %xmm9 -; AVX1-NEXT: vxorps %xmm7, %xmm7, %xmm7 -; AVX1-NEXT: vcmptrueps %ymm7, %ymm7, %ymm10 -; AVX1-NEXT: vxorps %ymm2, %ymm10, %ymm8 -; AVX1-NEXT: vextractf128 $1, %ymm8, %xmm6 -; AVX1-NEXT: vpxor %xmm4, %xmm6, %xmm7 -; AVX1-NEXT: vpcmpgtq %xmm9, %xmm7, %xmm7 -; AVX1-NEXT: vblendvpd %xmm7, %xmm5, %xmm6, %xmm5 -; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6 -; AVX1-NEXT: vpaddq %xmm6, %xmm5, %xmm5 -; AVX1-NEXT: vpxor %xmm4, %xmm0, %xmm6 -; AVX1-NEXT: vxorps %xmm4, %xmm8, %xmm7 -; AVX1-NEXT: vpcmpgtq %xmm6, %xmm7, %xmm6 -; AVX1-NEXT: vblendvpd %xmm6, %xmm0, %xmm8, %xmm0 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [9223372036854775808,9223372036854775808] +; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm6 +; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm7 +; AVX1-NEXT: vpaddq %xmm7, %xmm4, %xmm4 +; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm7 +; AVX1-NEXT: vpcmpgtq %xmm7, %xmm6, %xmm6 +; AVX1-NEXT: vpor %xmm4, %xmm6, %xmm4 +; AVX1-NEXT: vpxor %xmm5, %xmm0, %xmm6 ; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm0, %ymm0 +; AVX1-NEXT: vpxor %xmm5, %xmm0, %xmm2 +; AVX1-NEXT: vpcmpgtq %xmm2, %xmm6, %xmm2 +; AVX1-NEXT: vpor %xmm0, %xmm2, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 -; AVX1-NEXT: vpxor %xmm4, %xmm2, %xmm8 -; AVX1-NEXT: vxorps %ymm3, %ymm10, %ymm6 -; AVX1-NEXT: vextractf128 $1, %ymm6, %xmm7 -; AVX1-NEXT: vpxor %xmm4, %xmm7, %xmm5 -; AVX1-NEXT: vpcmpgtq %xmm8, %xmm5, %xmm5 -; AVX1-NEXT: vblendvpd %xmm5, %xmm2, %xmm7, %xmm2 -; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm5 -; AVX1-NEXT: vpaddq %xmm5, %xmm2, %xmm2 -; AVX1-NEXT: vpxor %xmm4, %xmm1, %xmm5 -; AVX1-NEXT: vxorps %xmm4, %xmm6, %xmm4 -; AVX1-NEXT: vpcmpgtq %xmm5, %xmm4, %xmm4 -; AVX1-NEXT: vblendvpd %xmm4, %xmm1, %xmm6, %xmm1 +; AVX1-NEXT: vpxor %xmm5, %xmm2, %xmm4 +; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm6 +; AVX1-NEXT: vpaddq %xmm6, %xmm2, %xmm2 +; AVX1-NEXT: vpxor %xmm5, %xmm2, %xmm6 +; AVX1-NEXT: vpcmpgtq %xmm6, %xmm4, %xmm4 +; AVX1-NEXT: vpor %xmm2, %xmm4, %xmm2 +; AVX1-NEXT: vpxor %xmm5, %xmm1, %xmm4 ; AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpxor %xmm5, %xmm1, %xmm3 +; AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm3 +; AVX1-NEXT: vpor %xmm1, %xmm3, %xmm1 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; AVX1-NEXT: retq ; @@ -1368,19 +1144,15 @@ define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind { ; AVX2: # %bb.0: ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; AVX2-NEXT: vpxor %ymm4, %ymm0, %ymm5 -; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm6 = [9223372036854775807,9223372036854775807,9223372036854775807,9223372036854775807] -; AVX2-NEXT: vpxor %ymm6, %ymm2, %ymm7 -; AVX2-NEXT: vpcmpgtq %ymm5, %ymm7, %ymm5 -; AVX2-NEXT: vpcmpeqd %ymm7, %ymm7, %ymm7 -; AVX2-NEXT: vpxor %ymm7, %ymm2, %ymm8 -; AVX2-NEXT: vblendvpd %ymm5, %ymm0, %ymm8, %ymm0 ; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpxor %ymm4, %ymm0, %ymm2 +; AVX2-NEXT: vpcmpgtq %ymm2, %ymm5, %ymm2 +; AVX2-NEXT: vpor %ymm0, %ymm2, %ymm0 ; AVX2-NEXT: vpxor %ymm4, %ymm1, %ymm2 -; AVX2-NEXT: vpxor %ymm6, %ymm3, %ymm4 -; AVX2-NEXT: vpcmpgtq %ymm2, %ymm4, %ymm2 -; AVX2-NEXT: vpxor %ymm7, %ymm3, %ymm4 -; AVX2-NEXT: vblendvpd %ymm2, %ymm1, %ymm4, %ymm1 ; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1 +; AVX2-NEXT: vpxor %ymm4, %ymm1, %ymm3 +; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2 +; AVX2-NEXT: vpor %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: retq ; ; AVX512-LABEL: v8i64: diff --git a/llvm/test/CodeGen/X86/usub_sat_vec.ll b/llvm/test/CodeGen/X86/usub_sat_vec.ll index 9d3a519d6b679..6d54503f85094 100644 --- a/llvm/test/CodeGen/X86/usub_sat_vec.ll +++ b/llvm/test/CodeGen/X86/usub_sat_vec.ll @@ -823,60 +823,23 @@ define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind { } define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { -; SSE2-LABEL: v2i64: -; SSE2: # %bb.0: -; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] -; SSE2-NEXT: movdqa %xmm1, %xmm3 -; SSE2-NEXT: pxor %xmm2, %xmm3 -; SSE2-NEXT: pxor %xmm0, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm4 -; SSE2-NEXT: pcmpgtd %xmm3, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm3, %xmm2 -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; SSE2-NEXT: pand %xmm5, %xmm2 -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] -; SSE2-NEXT: por %xmm2, %xmm3 -; SSE2-NEXT: psubq %xmm1, %xmm0 -; SSE2-NEXT: pand %xmm3, %xmm0 -; SSE2-NEXT: retq -; -; SSSE3-LABEL: v2i64: -; SSSE3: # %bb.0: -; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] -; SSSE3-NEXT: movdqa %xmm1, %xmm3 -; SSSE3-NEXT: pxor %xmm2, %xmm3 -; SSSE3-NEXT: pxor %xmm0, %xmm2 -; SSSE3-NEXT: movdqa %xmm2, %xmm4 -; SSSE3-NEXT: pcmpgtd %xmm3, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm3, %xmm2 -; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] -; SSSE3-NEXT: pand %xmm5, %xmm2 -; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] -; SSSE3-NEXT: por %xmm2, %xmm3 -; SSSE3-NEXT: psubq %xmm1, %xmm0 -; SSSE3-NEXT: pand %xmm3, %xmm0 -; SSSE3-NEXT: retq -; -; SSE41-LABEL: v2i64: -; SSE41: # %bb.0: -; SSE41-NEXT: movdqa %xmm0, %xmm2 -; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [9223372039002259456,9223372039002259456] -; SSE41-NEXT: movdqa %xmm1, %xmm0 -; SSE41-NEXT: pxor %xmm3, %xmm0 -; SSE41-NEXT: pxor %xmm2, %xmm3 -; SSE41-NEXT: movdqa %xmm3, %xmm4 -; SSE41-NEXT: pcmpeqd %xmm0, %xmm4 -; SSE41-NEXT: pcmpgtd %xmm0, %xmm3 -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,2,2] -; SSE41-NEXT: pand %xmm4, %xmm0 -; SSE41-NEXT: por %xmm3, %xmm0 -; SSE41-NEXT: psubq %xmm1, %xmm2 -; SSE41-NEXT: pxor %xmm1, %xmm1 -; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1 -; SSE41-NEXT: movapd %xmm1, %xmm0 -; SSE41-NEXT: retq +; SSE-LABEL: v2i64: +; SSE: # %bb.0: +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456] +; SSE-NEXT: movdqa %xmm1, %xmm3 +; SSE-NEXT: pxor %xmm2, %xmm3 +; SSE-NEXT: pxor %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm2, %xmm4 +; SSE-NEXT: pcmpgtd %xmm3, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm3, %xmm2 +; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE-NEXT: pand %xmm5, %xmm2 +; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] +; SSE-NEXT: por %xmm2, %xmm3 +; SSE-NEXT: psubq %xmm1, %xmm0 +; SSE-NEXT: pand %xmm3, %xmm0 +; SSE-NEXT: retq ; ; AVX1-LABEL: v2i64: ; AVX1: # %bb.0: @@ -917,99 +880,36 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { } define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { -; SSE2-LABEL: v4i64: -; SSE2: # %bb.0: -; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] -; SSE2-NEXT: movdqa %xmm0, %xmm5 -; SSE2-NEXT: psubq %xmm2, %xmm0 -; SSE2-NEXT: pxor %xmm4, %xmm2 -; SSE2-NEXT: pxor %xmm4, %xmm5 -; SSE2-NEXT: movdqa %xmm5, %xmm6 -; SSE2-NEXT: pcmpgtd %xmm2, %xmm6 -; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm2, %xmm5 -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] -; SSE2-NEXT: pand %xmm7, %xmm2 -; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3] -; SSE2-NEXT: por %xmm2, %xmm5 -; SSE2-NEXT: pand %xmm5, %xmm0 -; SSE2-NEXT: movdqa %xmm3, %xmm2 -; SSE2-NEXT: pxor %xmm4, %xmm2 -; SSE2-NEXT: pxor %xmm1, %xmm4 -; SSE2-NEXT: movdqa %xmm4, %xmm5 -; SSE2-NEXT: pcmpgtd %xmm2, %xmm5 -; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm2, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3] -; SSE2-NEXT: pand %xmm6, %xmm2 -; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3] -; SSE2-NEXT: por %xmm2, %xmm4 -; SSE2-NEXT: psubq %xmm3, %xmm1 -; SSE2-NEXT: pand %xmm4, %xmm1 -; SSE2-NEXT: retq -; -; SSSE3-LABEL: v4i64: -; SSSE3: # %bb.0: -; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] -; SSSE3-NEXT: movdqa %xmm0, %xmm5 -; SSSE3-NEXT: psubq %xmm2, %xmm0 -; SSSE3-NEXT: pxor %xmm4, %xmm2 -; SSSE3-NEXT: pxor %xmm4, %xmm5 -; SSSE3-NEXT: movdqa %xmm5, %xmm6 -; SSSE3-NEXT: pcmpgtd %xmm2, %xmm6 -; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm2, %xmm5 -; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] -; SSSE3-NEXT: pand %xmm7, %xmm2 -; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3] -; SSSE3-NEXT: por %xmm2, %xmm5 -; SSSE3-NEXT: pand %xmm5, %xmm0 -; SSSE3-NEXT: movdqa %xmm3, %xmm2 -; SSSE3-NEXT: pxor %xmm4, %xmm2 -; SSSE3-NEXT: pxor %xmm1, %xmm4 -; SSSE3-NEXT: movdqa %xmm4, %xmm5 -; SSSE3-NEXT: pcmpgtd %xmm2, %xmm5 -; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm2, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3] -; SSSE3-NEXT: pand %xmm6, %xmm2 -; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3] -; SSSE3-NEXT: por %xmm2, %xmm4 -; SSSE3-NEXT: psubq %xmm3, %xmm1 -; SSSE3-NEXT: pand %xmm4, %xmm1 -; SSSE3-NEXT: retq -; -; SSE41-LABEL: v4i64: -; SSE41: # %bb.0: -; SSE41-NEXT: movdqa %xmm0, %xmm4 -; SSE41-NEXT: movdqa {{.*#+}} xmm6 = [9223372039002259456,9223372039002259456] -; SSE41-NEXT: movdqa %xmm0, %xmm5 -; SSE41-NEXT: psubq %xmm2, %xmm4 -; SSE41-NEXT: pxor %xmm6, %xmm2 -; SSE41-NEXT: pxor %xmm6, %xmm5 -; SSE41-NEXT: movdqa %xmm5, %xmm0 -; SSE41-NEXT: pcmpeqd %xmm2, %xmm0 -; SSE41-NEXT: pcmpgtd %xmm2, %xmm5 -; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm5[0,0,2,2] -; SSE41-NEXT: pand %xmm2, %xmm0 -; SSE41-NEXT: por %xmm5, %xmm0 -; SSE41-NEXT: pxor %xmm2, %xmm2 -; SSE41-NEXT: pxor %xmm5, %xmm5 -; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm5 -; SSE41-NEXT: movdqa %xmm3, %xmm0 -; SSE41-NEXT: pxor %xmm6, %xmm0 -; SSE41-NEXT: pxor %xmm1, %xmm6 -; SSE41-NEXT: movdqa %xmm6, %xmm4 -; SSE41-NEXT: pcmpeqd %xmm0, %xmm4 -; SSE41-NEXT: pcmpgtd %xmm0, %xmm6 -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2] -; SSE41-NEXT: pand %xmm4, %xmm0 -; SSE41-NEXT: por %xmm6, %xmm0 -; SSE41-NEXT: psubq %xmm3, %xmm1 -; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2 -; SSE41-NEXT: movapd %xmm5, %xmm0 -; SSE41-NEXT: movapd %xmm2, %xmm1 -; SSE41-NEXT: retq +; SSE-LABEL: v4i64: +; SSE: # %bb.0: +; SSE-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] +; SSE-NEXT: movdqa %xmm0, %xmm5 +; SSE-NEXT: psubq %xmm2, %xmm0 +; SSE-NEXT: pxor %xmm4, %xmm2 +; SSE-NEXT: pxor %xmm4, %xmm5 +; SSE-NEXT: movdqa %xmm5, %xmm6 +; SSE-NEXT: pcmpgtd %xmm2, %xmm6 +; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm2, %xmm5 +; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] +; SSE-NEXT: pand %xmm7, %xmm2 +; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3] +; SSE-NEXT: por %xmm2, %xmm5 +; SSE-NEXT: pand %xmm5, %xmm0 +; SSE-NEXT: movdqa %xmm3, %xmm2 +; SSE-NEXT: pxor %xmm4, %xmm2 +; SSE-NEXT: pxor %xmm1, %xmm4 +; SSE-NEXT: movdqa %xmm4, %xmm5 +; SSE-NEXT: pcmpgtd %xmm2, %xmm5 +; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm2, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3] +; SSE-NEXT: pand %xmm6, %xmm2 +; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3] +; SSE-NEXT: por %xmm2, %xmm4 +; SSE-NEXT: psubq %xmm3, %xmm1 +; SSE-NEXT: pand %xmm4, %xmm1 +; SSE-NEXT: retq ; ; AVX1-LABEL: v4i64: ; AVX1: # %bb.0: @@ -1019,13 +919,13 @@ define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5 ; AVX1-NEXT: vpxor %xmm3, %xmm5, %xmm6 ; AVX1-NEXT: vpcmpgtq %xmm4, %xmm6, %xmm4 -; AVX1-NEXT: vblendvpd %xmm4, %xmm5, %xmm2, %xmm4 -; AVX1-NEXT: vpsubq %xmm2, %xmm4, %xmm2 +; AVX1-NEXT: vpsubq %xmm2, %xmm5, %xmm2 +; AVX1-NEXT: vpand %xmm2, %xmm4, %xmm2 ; AVX1-NEXT: vpxor %xmm3, %xmm1, %xmm4 ; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm3 ; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm3 -; AVX1-NEXT: vblendvpd %xmm3, %xmm0, %xmm1, %xmm0 ; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpand %xmm0, %xmm3, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: retq ; @@ -1035,8 +935,8 @@ define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { ; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm3 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2 -; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0 ; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpand %ymm0, %ymm2, %ymm0 ; AVX2-NEXT: retq ; ; AVX512F-LABEL: v4i64: @@ -1057,177 +957,62 @@ define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { } define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind { -; SSE2-LABEL: v8i64: -; SSE2: # %bb.0: -; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456] -; SSE2-NEXT: movdqa %xmm0, %xmm9 -; SSE2-NEXT: psubq %xmm4, %xmm0 -; SSE2-NEXT: pxor %xmm8, %xmm4 -; SSE2-NEXT: pxor %xmm8, %xmm9 -; SSE2-NEXT: movdqa %xmm9, %xmm10 -; SSE2-NEXT: pcmpgtd %xmm4, %xmm10 -; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm10[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm4, %xmm9 -; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm9[1,1,3,3] -; SSE2-NEXT: pand %xmm11, %xmm9 -; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm10[1,1,3,3] -; SSE2-NEXT: por %xmm9, %xmm4 -; SSE2-NEXT: pand %xmm4, %xmm0 -; SSE2-NEXT: movdqa %xmm1, %xmm9 -; SSE2-NEXT: psubq %xmm5, %xmm1 -; SSE2-NEXT: pxor %xmm8, %xmm5 -; SSE2-NEXT: pxor %xmm8, %xmm9 -; SSE2-NEXT: movdqa %xmm9, %xmm4 -; SSE2-NEXT: pcmpgtd %xmm5, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm4[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm5, %xmm9 -; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm9[1,1,3,3] -; SSE2-NEXT: pand %xmm10, %xmm5 -; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] -; SSE2-NEXT: por %xmm5, %xmm4 -; SSE2-NEXT: pand %xmm4, %xmm1 -; SSE2-NEXT: movdqa %xmm2, %xmm4 -; SSE2-NEXT: psubq %xmm6, %xmm2 -; SSE2-NEXT: pxor %xmm8, %xmm6 -; SSE2-NEXT: pxor %xmm8, %xmm4 -; SSE2-NEXT: movdqa %xmm4, %xmm5 -; SSE2-NEXT: pcmpgtd %xmm6, %xmm5 -; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm6, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] -; SSE2-NEXT: pand %xmm9, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] -; SSE2-NEXT: por %xmm4, %xmm5 -; SSE2-NEXT: pand %xmm5, %xmm2 -; SSE2-NEXT: movdqa %xmm7, %xmm4 -; SSE2-NEXT: pxor %xmm8, %xmm4 -; SSE2-NEXT: pxor %xmm3, %xmm8 -; SSE2-NEXT: movdqa %xmm8, %xmm5 -; SSE2-NEXT: pcmpgtd %xmm4, %xmm5 -; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] -; SSE2-NEXT: pcmpeqd %xmm4, %xmm8 -; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm8[1,1,3,3] -; SSE2-NEXT: pand %xmm6, %xmm4 -; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] -; SSE2-NEXT: por %xmm4, %xmm5 -; SSE2-NEXT: psubq %xmm7, %xmm3 -; SSE2-NEXT: pand %xmm5, %xmm3 -; SSE2-NEXT: retq -; -; SSSE3-LABEL: v8i64: -; SSSE3: # %bb.0: -; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456] -; SSSE3-NEXT: movdqa %xmm0, %xmm9 -; SSSE3-NEXT: psubq %xmm4, %xmm0 -; SSSE3-NEXT: pxor %xmm8, %xmm4 -; SSSE3-NEXT: pxor %xmm8, %xmm9 -; SSSE3-NEXT: movdqa %xmm9, %xmm10 -; SSSE3-NEXT: pcmpgtd %xmm4, %xmm10 -; SSSE3-NEXT: pshufd {{.*#+}} xmm11 = xmm10[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm4, %xmm9 -; SSSE3-NEXT: pshufd {{.*#+}} xmm9 = xmm9[1,1,3,3] -; SSSE3-NEXT: pand %xmm11, %xmm9 -; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm10[1,1,3,3] -; SSSE3-NEXT: por %xmm9, %xmm4 -; SSSE3-NEXT: pand %xmm4, %xmm0 -; SSSE3-NEXT: movdqa %xmm1, %xmm9 -; SSSE3-NEXT: psubq %xmm5, %xmm1 -; SSSE3-NEXT: pxor %xmm8, %xmm5 -; SSSE3-NEXT: pxor %xmm8, %xmm9 -; SSSE3-NEXT: movdqa %xmm9, %xmm4 -; SSSE3-NEXT: pcmpgtd %xmm5, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm10 = xmm4[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm5, %xmm9 -; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm9[1,1,3,3] -; SSSE3-NEXT: pand %xmm10, %xmm5 -; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] -; SSSE3-NEXT: por %xmm5, %xmm4 -; SSSE3-NEXT: pand %xmm4, %xmm1 -; SSSE3-NEXT: movdqa %xmm2, %xmm4 -; SSSE3-NEXT: psubq %xmm6, %xmm2 -; SSSE3-NEXT: pxor %xmm8, %xmm6 -; SSSE3-NEXT: pxor %xmm8, %xmm4 -; SSSE3-NEXT: movdqa %xmm4, %xmm5 -; SSSE3-NEXT: pcmpgtd %xmm6, %xmm5 -; SSSE3-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm6, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] -; SSSE3-NEXT: pand %xmm9, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] -; SSSE3-NEXT: por %xmm4, %xmm5 -; SSSE3-NEXT: pand %xmm5, %xmm2 -; SSSE3-NEXT: movdqa %xmm7, %xmm4 -; SSSE3-NEXT: pxor %xmm8, %xmm4 -; SSSE3-NEXT: pxor %xmm3, %xmm8 -; SSSE3-NEXT: movdqa %xmm8, %xmm5 -; SSSE3-NEXT: pcmpgtd %xmm4, %xmm5 -; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] -; SSSE3-NEXT: pcmpeqd %xmm4, %xmm8 -; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm8[1,1,3,3] -; SSSE3-NEXT: pand %xmm6, %xmm4 -; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] -; SSSE3-NEXT: por %xmm4, %xmm5 -; SSSE3-NEXT: psubq %xmm7, %xmm3 -; SSSE3-NEXT: pand %xmm5, %xmm3 -; SSSE3-NEXT: retq -; -; SSE41-LABEL: v8i64: -; SSE41: # %bb.0: -; SSE41-NEXT: movdqa %xmm0, %xmm9 -; SSE41-NEXT: movdqa {{.*#+}} xmm10 = [9223372039002259456,9223372039002259456] -; SSE41-NEXT: movdqa %xmm0, %xmm8 -; SSE41-NEXT: psubq %xmm4, %xmm9 -; SSE41-NEXT: pxor %xmm10, %xmm4 -; SSE41-NEXT: pxor %xmm10, %xmm8 -; SSE41-NEXT: movdqa %xmm8, %xmm0 -; SSE41-NEXT: pcmpeqd %xmm4, %xmm0 -; SSE41-NEXT: pcmpgtd %xmm4, %xmm8 -; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm8[0,0,2,2] -; SSE41-NEXT: pand %xmm4, %xmm0 -; SSE41-NEXT: por %xmm8, %xmm0 -; SSE41-NEXT: pxor %xmm8, %xmm8 -; SSE41-NEXT: xorpd %xmm11, %xmm11 -; SSE41-NEXT: blendvpd %xmm0, %xmm9, %xmm11 -; SSE41-NEXT: movdqa %xmm1, %xmm4 -; SSE41-NEXT: psubq %xmm5, %xmm1 -; SSE41-NEXT: pxor %xmm10, %xmm5 -; SSE41-NEXT: pxor %xmm10, %xmm4 -; SSE41-NEXT: movdqa %xmm4, %xmm9 -; SSE41-NEXT: pcmpeqd %xmm5, %xmm9 -; SSE41-NEXT: pcmpgtd %xmm5, %xmm4 -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm4[0,0,2,2] -; SSE41-NEXT: pand %xmm9, %xmm0 -; SSE41-NEXT: por %xmm4, %xmm0 -; SSE41-NEXT: pxor %xmm5, %xmm5 -; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm5 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: psubq %xmm6, %xmm2 -; SSE41-NEXT: pxor %xmm10, %xmm6 -; SSE41-NEXT: pxor %xmm10, %xmm1 -; SSE41-NEXT: movdqa %xmm1, %xmm4 -; SSE41-NEXT: pcmpeqd %xmm6, %xmm4 -; SSE41-NEXT: pcmpgtd %xmm6, %xmm1 -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,2,2] -; SSE41-NEXT: pand %xmm4, %xmm0 -; SSE41-NEXT: por %xmm1, %xmm0 -; SSE41-NEXT: pxor %xmm6, %xmm6 -; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm6 -; SSE41-NEXT: movdqa %xmm7, %xmm0 -; SSE41-NEXT: pxor %xmm10, %xmm0 -; SSE41-NEXT: pxor %xmm3, %xmm10 -; SSE41-NEXT: movdqa %xmm10, %xmm1 -; SSE41-NEXT: pcmpeqd %xmm0, %xmm1 -; SSE41-NEXT: pcmpgtd %xmm0, %xmm10 -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm10[0,0,2,2] -; SSE41-NEXT: pand %xmm1, %xmm0 -; SSE41-NEXT: por %xmm10, %xmm0 -; SSE41-NEXT: psubq %xmm7, %xmm3 -; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm8 -; SSE41-NEXT: movapd %xmm11, %xmm0 -; SSE41-NEXT: movapd %xmm5, %xmm1 -; SSE41-NEXT: movapd %xmm6, %xmm2 -; SSE41-NEXT: movapd %xmm8, %xmm3 -; SSE41-NEXT: retq +; SSE-LABEL: v8i64: +; SSE: # %bb.0: +; SSE-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456] +; SSE-NEXT: movdqa %xmm0, %xmm9 +; SSE-NEXT: psubq %xmm4, %xmm0 +; SSE-NEXT: pxor %xmm8, %xmm4 +; SSE-NEXT: pxor %xmm8, %xmm9 +; SSE-NEXT: movdqa %xmm9, %xmm10 +; SSE-NEXT: pcmpgtd %xmm4, %xmm10 +; SSE-NEXT: pshufd {{.*#+}} xmm11 = xmm10[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm4, %xmm9 +; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm9[1,1,3,3] +; SSE-NEXT: pand %xmm11, %xmm9 +; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm10[1,1,3,3] +; SSE-NEXT: por %xmm9, %xmm4 +; SSE-NEXT: pand %xmm4, %xmm0 +; SSE-NEXT: movdqa %xmm1, %xmm9 +; SSE-NEXT: psubq %xmm5, %xmm1 +; SSE-NEXT: pxor %xmm8, %xmm5 +; SSE-NEXT: pxor %xmm8, %xmm9 +; SSE-NEXT: movdqa %xmm9, %xmm4 +; SSE-NEXT: pcmpgtd %xmm5, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm4[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm5, %xmm9 +; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm9[1,1,3,3] +; SSE-NEXT: pand %xmm10, %xmm5 +; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] +; SSE-NEXT: por %xmm5, %xmm4 +; SSE-NEXT: pand %xmm4, %xmm1 +; SSE-NEXT: movdqa %xmm2, %xmm4 +; SSE-NEXT: psubq %xmm6, %xmm2 +; SSE-NEXT: pxor %xmm8, %xmm6 +; SSE-NEXT: pxor %xmm8, %xmm4 +; SSE-NEXT: movdqa %xmm4, %xmm5 +; SSE-NEXT: pcmpgtd %xmm6, %xmm5 +; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm6, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] +; SSE-NEXT: pand %xmm9, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] +; SSE-NEXT: por %xmm4, %xmm5 +; SSE-NEXT: pand %xmm5, %xmm2 +; SSE-NEXT: movdqa %xmm7, %xmm4 +; SSE-NEXT: pxor %xmm8, %xmm4 +; SSE-NEXT: pxor %xmm3, %xmm8 +; SSE-NEXT: movdqa %xmm8, %xmm5 +; SSE-NEXT: pcmpgtd %xmm4, %xmm5 +; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2] +; SSE-NEXT: pcmpeqd %xmm4, %xmm8 +; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm8[1,1,3,3] +; SSE-NEXT: pand %xmm6, %xmm4 +; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] +; SSE-NEXT: por %xmm4, %xmm5 +; SSE-NEXT: psubq %xmm7, %xmm3 +; SSE-NEXT: pand %xmm5, %xmm3 +; SSE-NEXT: retq ; ; AVX1-LABEL: v8i64: ; AVX1: # %bb.0: @@ -1237,26 +1022,26 @@ define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind { ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm7 ; AVX1-NEXT: vpxor %xmm5, %xmm7, %xmm6 ; AVX1-NEXT: vpcmpgtq %xmm8, %xmm6, %xmm6 -; AVX1-NEXT: vblendvpd %xmm6, %xmm7, %xmm4, %xmm6 -; AVX1-NEXT: vpsubq %xmm4, %xmm6, %xmm4 +; AVX1-NEXT: vpsubq %xmm4, %xmm7, %xmm4 +; AVX1-NEXT: vpand %xmm4, %xmm6, %xmm4 ; AVX1-NEXT: vpxor %xmm5, %xmm2, %xmm6 ; AVX1-NEXT: vpxor %xmm5, %xmm0, %xmm7 ; AVX1-NEXT: vpcmpgtq %xmm6, %xmm7, %xmm6 -; AVX1-NEXT: vblendvpd %xmm6, %xmm0, %xmm2, %xmm0 ; AVX1-NEXT: vpsubq %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpand %xmm0, %xmm6, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2 ; AVX1-NEXT: vpxor %xmm5, %xmm2, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm6 ; AVX1-NEXT: vpxor %xmm5, %xmm6, %xmm7 ; AVX1-NEXT: vpcmpgtq %xmm4, %xmm7, %xmm4 -; AVX1-NEXT: vblendvpd %xmm4, %xmm6, %xmm2, %xmm4 -; AVX1-NEXT: vpsubq %xmm2, %xmm4, %xmm2 +; AVX1-NEXT: vpsubq %xmm2, %xmm6, %xmm2 +; AVX1-NEXT: vpand %xmm2, %xmm4, %xmm2 ; AVX1-NEXT: vpxor %xmm5, %xmm3, %xmm4 ; AVX1-NEXT: vpxor %xmm5, %xmm1, %xmm5 ; AVX1-NEXT: vpcmpgtq %xmm4, %xmm5, %xmm4 -; AVX1-NEXT: vblendvpd %xmm4, %xmm1, %xmm3, %xmm1 ; AVX1-NEXT: vpsubq %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpand %xmm1, %xmm4, %xmm1 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; AVX1-NEXT: retq ; @@ -1266,13 +1051,13 @@ define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind { ; AVX2-NEXT: vpxor %ymm4, %ymm2, %ymm5 ; AVX2-NEXT: vpxor %ymm4, %ymm0, %ymm6 ; AVX2-NEXT: vpcmpgtq %ymm5, %ymm6, %ymm5 -; AVX2-NEXT: vblendvpd %ymm5, %ymm0, %ymm2, %ymm0 ; AVX2-NEXT: vpsubq %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpand %ymm0, %ymm5, %ymm0 ; AVX2-NEXT: vpxor %ymm4, %ymm3, %ymm2 ; AVX2-NEXT: vpxor %ymm4, %ymm1, %ymm4 ; AVX2-NEXT: vpcmpgtq %ymm2, %ymm4, %ymm2 -; AVX2-NEXT: vblendvpd %ymm2, %ymm1, %ymm3, %ymm1 ; AVX2-NEXT: vpsubq %ymm3, %ymm1, %ymm1 +; AVX2-NEXT: vpand %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: retq ; ; AVX512-LABEL: v8i64: diff --git a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll index 1d00782f21778..a06c7052044e6 100644 --- a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll +++ b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll @@ -3,8 +3,8 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX,AVX512 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512,AVX512BW +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX,AVX512,AVX512BWVL ; ; vXi64 @@ -1122,22 +1122,43 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) { ; AVX2-NEXT: movl $1, %eax ; AVX2-NEXT: retq ; -; AVX512-LABEL: mask_v3i1: -; AVX512: # %bb.0: -; AVX512: vpcmpneqd %{{.}}mm1, %{{.}}mm0, %k0 -; AVX512-NEXT: kshiftrw $2, %k0, %k1 -; AVX512-NEXT: korw %k1, %k0, %k1 -; AVX512-NEXT: kshiftrw $1, %k0, %k0 -; AVX512-NEXT: korw %k0, %k1, %k0 -; AVX512-NEXT: kmovd %k0, %eax -; AVX512-NEXT: testb $1, %al -; AVX512-NEXT: je .LBB27_2 -; AVX512-NEXT: # %bb.1: -; AVX512-NEXT: xorl %eax, %eax -; AVX512: retq -; AVX512-NEXT: .LBB27_2: -; AVX512-NEXT: movl $1, %eax -; AVX512: retq +; AVX512BW-LABEL: mask_v3i1: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 +; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 +; AVX512BW-NEXT: vpcmpneqd %zmm1, %zmm0, %k0 +; AVX512BW-NEXT: kshiftrw $2, %k0, %k1 +; AVX512BW-NEXT: korw %k1, %k0, %k1 +; AVX512BW-NEXT: kshiftrw $1, %k0, %k0 +; AVX512BW-NEXT: korw %k0, %k1, %k0 +; AVX512BW-NEXT: kmovd %k0, %eax +; AVX512BW-NEXT: testb $1, %al +; AVX512BW-NEXT: je .LBB27_2 +; AVX512BW-NEXT: # %bb.1: +; AVX512BW-NEXT: xorl %eax, %eax +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq +; AVX512BW-NEXT: .LBB27_2: +; AVX512BW-NEXT: movl $1, %eax +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq +; +; AVX512BWVL-LABEL: mask_v3i1: +; AVX512BWVL: # %bb.0: +; AVX512BWVL-NEXT: vpcmpneqd %xmm1, %xmm0, %k0 +; AVX512BWVL-NEXT: kshiftrw $2, %k0, %k1 +; AVX512BWVL-NEXT: korw %k1, %k0, %k1 +; AVX512BWVL-NEXT: kshiftrw $1, %k0, %k0 +; AVX512BWVL-NEXT: korw %k0, %k1, %k0 +; AVX512BWVL-NEXT: kmovd %k0, %eax +; AVX512BWVL-NEXT: testb $1, %al +; AVX512BWVL-NEXT: je .LBB27_2 +; AVX512BWVL-NEXT: # %bb.1: +; AVX512BWVL-NEXT: xorl %eax, %eax +; AVX512BWVL-NEXT: retq +; AVX512BWVL-NEXT: .LBB27_2: +; AVX512BWVL-NEXT: movl $1, %eax +; AVX512BWVL-NEXT: retq %1 = icmp ne <3 x i32> %a, %b %2 = call i1 @llvm.vector.reduce.or.v3i1(<3 x i1> %1) br i1 %2, label %3, label %4 diff --git a/llvm/test/CodeGen/X86/vectorcall.ll b/llvm/test/CodeGen/X86/vectorcall.ll index 4a375acc4b979..d3d44f6bdd7a6 100644 --- a/llvm/test/CodeGen/X86/vectorcall.ll +++ b/llvm/test/CodeGen/X86/vectorcall.ll @@ -171,7 +171,7 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1) declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) -define x86_vectorcallcc void @test_mixed_7(%struct.HVA5* noalias sret %agg.result) { +define x86_vectorcallcc void @test_mixed_7(%struct.HVA5* noalias sret(%struct.HVA5) %agg.result) { ; X86-LABEL: test_mixed_7@@4 ; X64-LABEL: test_mixed_7@@8 ; X64: mov{{[ql]}} %rcx, %rax diff --git a/llvm/test/CodeGen/X86/viabs.ll b/llvm/test/CodeGen/X86/viabs.ll index 588246d7ded61..405d9eaa2c834 100644 --- a/llvm/test/CodeGen/X86/viabs.ll +++ b/llvm/test/CodeGen/X86/viabs.ll @@ -88,10 +88,9 @@ define <4 x i32> @test_abs_ge_v4i32(<4 x i32> %a) nounwind { define <8 x i16> @test_abs_gt_v8i16(<8 x i16> %a) nounwind { ; SSE2-LABEL: test_abs_gt_v8i16: ; SSE2: # %bb.0: -; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psraw $15, %xmm1 -; SSE2-NEXT: paddw %xmm1, %xmm0 -; SSE2-NEXT: pxor %xmm1, %xmm0 +; SSE2-NEXT: pxor %xmm1, %xmm1 +; SSE2-NEXT: psubw %xmm0, %xmm1 +; SSE2-NEXT: pmaxsw %xmm1, %xmm0 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test_abs_gt_v8i16: @@ -133,9 +132,8 @@ define <16 x i8> @test_abs_lt_v16i8(<16 x i8> %a) nounwind { ; SSE2-LABEL: test_abs_lt_v16i8: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm1, %xmm1 -; SSE2-NEXT: pcmpgtb %xmm0, %xmm1 -; SSE2-NEXT: paddb %xmm1, %xmm0 -; SSE2-NEXT: pxor %xmm1, %xmm0 +; SSE2-NEXT: psubb %xmm0, %xmm1 +; SSE2-NEXT: pminub %xmm1, %xmm0 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test_abs_lt_v16i8: @@ -311,14 +309,12 @@ define <8 x i32> @test_abs_ge_v8i32(<8 x i32> %a) nounwind { define <16 x i16> @test_abs_gt_v16i16(<16 x i16> %a) nounwind { ; SSE2-LABEL: test_abs_gt_v16i16: ; SSE2: # %bb.0: -; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: psraw $15, %xmm2 -; SSE2-NEXT: paddw %xmm2, %xmm0 -; SSE2-NEXT: pxor %xmm2, %xmm0 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: psraw $15, %xmm2 -; SSE2-NEXT: paddw %xmm2, %xmm1 -; SSE2-NEXT: pxor %xmm2, %xmm1 +; SSE2-NEXT: pxor %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: psubw %xmm0, %xmm3 +; SSE2-NEXT: pmaxsw %xmm3, %xmm0 +; SSE2-NEXT: psubw %xmm1, %xmm2 +; SSE2-NEXT: pmaxsw %xmm2, %xmm1 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test_abs_gt_v16i16: @@ -366,12 +362,10 @@ define <32 x i8> @test_abs_lt_v32i8(<32 x i8> %a) nounwind { ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm2, %xmm2 ; SSE2-NEXT: pxor %xmm3, %xmm3 -; SSE2-NEXT: pcmpgtb %xmm0, %xmm3 -; SSE2-NEXT: paddb %xmm3, %xmm0 -; SSE2-NEXT: pxor %xmm3, %xmm0 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm2 -; SSE2-NEXT: paddb %xmm2, %xmm1 -; SSE2-NEXT: pxor %xmm2, %xmm1 +; SSE2-NEXT: psubb %xmm0, %xmm3 +; SSE2-NEXT: pminub %xmm3, %xmm0 +; SSE2-NEXT: psubb %xmm1, %xmm2 +; SSE2-NEXT: pminub %xmm2, %xmm1 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test_abs_lt_v32i8: @@ -877,20 +871,16 @@ define <64 x i8> @test_abs_lt_v64i8(<64 x i8> %a) nounwind { ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: pxor %xmm5, %xmm5 -; SSE2-NEXT: pcmpgtb %xmm0, %xmm5 -; SSE2-NEXT: paddb %xmm5, %xmm0 -; SSE2-NEXT: pxor %xmm5, %xmm0 +; SSE2-NEXT: psubb %xmm0, %xmm5 +; SSE2-NEXT: pminub %xmm5, %xmm0 ; SSE2-NEXT: pxor %xmm5, %xmm5 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm5 -; SSE2-NEXT: paddb %xmm5, %xmm1 -; SSE2-NEXT: pxor %xmm5, %xmm1 +; SSE2-NEXT: psubb %xmm1, %xmm5 +; SSE2-NEXT: pminub %xmm5, %xmm1 ; SSE2-NEXT: pxor %xmm5, %xmm5 -; SSE2-NEXT: pcmpgtb %xmm2, %xmm5 -; SSE2-NEXT: paddb %xmm5, %xmm2 -; SSE2-NEXT: pxor %xmm5, %xmm2 -; SSE2-NEXT: pcmpgtb %xmm3, %xmm4 -; SSE2-NEXT: paddb %xmm4, %xmm3 -; SSE2-NEXT: pxor %xmm4, %xmm3 +; SSE2-NEXT: psubb %xmm2, %xmm5 +; SSE2-NEXT: pminub %xmm5, %xmm2 +; SSE2-NEXT: psubb %xmm3, %xmm4 +; SSE2-NEXT: pminub %xmm4, %xmm3 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test_abs_lt_v64i8: @@ -948,22 +938,18 @@ define <64 x i8> @test_abs_lt_v64i8(<64 x i8> %a) nounwind { define <32 x i16> @test_abs_gt_v32i16(<32 x i16> %a) nounwind { ; SSE2-LABEL: test_abs_gt_v32i16: ; SSE2: # %bb.0: -; SSE2-NEXT: movdqa %xmm0, %xmm4 -; SSE2-NEXT: psraw $15, %xmm4 -; SSE2-NEXT: paddw %xmm4, %xmm0 -; SSE2-NEXT: pxor %xmm4, %xmm0 -; SSE2-NEXT: movdqa %xmm1, %xmm4 -; SSE2-NEXT: psraw $15, %xmm4 -; SSE2-NEXT: paddw %xmm4, %xmm1 -; SSE2-NEXT: pxor %xmm4, %xmm1 -; SSE2-NEXT: movdqa %xmm2, %xmm4 -; SSE2-NEXT: psraw $15, %xmm4 -; SSE2-NEXT: paddw %xmm4, %xmm2 -; SSE2-NEXT: pxor %xmm4, %xmm2 -; SSE2-NEXT: movdqa %xmm3, %xmm4 -; SSE2-NEXT: psraw $15, %xmm4 -; SSE2-NEXT: paddw %xmm4, %xmm3 -; SSE2-NEXT: pxor %xmm4, %xmm3 +; SSE2-NEXT: pxor %xmm4, %xmm4 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: psubw %xmm0, %xmm5 +; SSE2-NEXT: pmaxsw %xmm5, %xmm0 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: psubw %xmm1, %xmm5 +; SSE2-NEXT: pmaxsw %xmm5, %xmm1 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: psubw %xmm2, %xmm5 +; SSE2-NEXT: pmaxsw %xmm5, %xmm2 +; SSE2-NEXT: psubw %xmm3, %xmm4 +; SSE2-NEXT: pmaxsw %xmm4, %xmm3 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test_abs_gt_v32i16: diff --git a/llvm/test/CodeGen/X86/volatile.ll b/llvm/test/CodeGen/X86/volatile.ll index 8e293e44e86d5..2e6cac486afe3 100644 --- a/llvm/test/CodeGen/X86/volatile.ll +++ b/llvm/test/CodeGen/X86/volatile.ll @@ -1,18 +1,28 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-- -mattr=sse2 | FileCheck %s -; RUN: llc < %s -mtriple=i686-- -mattr=sse2 -O0 | FileCheck %s +; RUN: llc < %s -mtriple=i686-- -mattr=sse2 | FileCheck %s --check-prefixes=ALL,OPT +; RUN: llc < %s -mtriple=i686-- -mattr=sse2 -O0 | FileCheck %s --check-prefixes=ALL,NOOPT @x = external global double define void @foo() nounwind { -; CHECK-LABEL: foo: -; CHECK: # %bb.0: -; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; CHECK-NEXT: xorps %xmm0, %xmm0 -; CHECK-NEXT: movsd %xmm0, x -; CHECK-NEXT: movsd %xmm0, x -; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; CHECK-NEXT: retl +; OPT-LABEL: foo: +; OPT: # %bb.0: +; OPT-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; OPT-NEXT: xorps %xmm0, %xmm0 +; OPT-NEXT: movsd %xmm0, x +; OPT-NEXT: movsd %xmm0, x +; OPT-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; OPT-NEXT: retl +; +; NOOPT-LABEL: foo: +; NOOPT: # %bb.0: +; NOOPT-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; NOOPT-NEXT: xorps %xmm0, %xmm0 +; NOOPT-NEXT: movsd %xmm0, x +; NOOPT-NEXT: xorps %xmm0, %xmm0 +; NOOPT-NEXT: movsd %xmm0, x +; NOOPT-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; NOOPT-NEXT: retl %a = load volatile double, double* @x store volatile double 0.0, double* @x store volatile double 0.0, double* @x @@ -21,10 +31,10 @@ define void @foo() nounwind { } define void @bar() nounwind { -; CHECK-LABEL: bar: -; CHECK: # %bb.0: -; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; CHECK-NEXT: retl +; ALL-LABEL: bar: +; ALL: # %bb.0: +; ALL-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; ALL-NEXT: retl %c = load volatile double, double* @x ret void } diff --git a/llvm/test/CodeGen/X86/widen_load-2.ll b/llvm/test/CodeGen/X86/widen_load-2.ll index 4ca71ceb2e0f5..c9531f2c9ced3 100644 --- a/llvm/test/CodeGen/X86/widen_load-2.ll +++ b/llvm/test/CodeGen/X86/widen_load-2.ll @@ -6,7 +6,7 @@ ; %i32vec3 = type <3 x i32> -define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { +define void @add3i32(%i32vec3* sret(%i32vec3) %ret, %i32vec3* %ap, %i32vec3* %bp) { ; X86-LABEL: add3i32: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -34,7 +34,7 @@ define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { ret void } -define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { +define void @add3i32_2(%i32vec3* sret(%i32vec3) %ret, %i32vec3* %ap, %i32vec3* %bp) { ; X86-LABEL: add3i32_2: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -71,7 +71,7 @@ define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { } %i32vec7 = type <7 x i32> -define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) { +define void @add7i32(%i32vec7* sret(%i32vec7) %ret, %i32vec7* %ap, %i32vec7* %bp) { ; X86-LABEL: add7i32: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -106,7 +106,7 @@ define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) { } %i32vec12 = type <12 x i32> -define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) { +define void @add12i32(%i32vec12* sret(%i32vec12) %ret, %i32vec12* %ap, %i32vec12* %bp) { ; X86-LABEL: add12i32: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -145,7 +145,7 @@ define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) { %i16vec3 = type <3 x i16> -define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind { +define void @add3i16(%i16vec3* nocapture sret(%i16vec3) %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind { ; X86-LABEL: add3i16: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -177,7 +177,7 @@ define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp } %i16vec4 = type <4 x i16> -define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind { +define void @add4i16(%i16vec4* nocapture sret(%i16vec4) %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind { ; X86-LABEL: add4i16: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -205,7 +205,7 @@ define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp } %i16vec12 = type <12 x i16> -define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind { +define void @add12i16(%i16vec12* nocapture sret(%i16vec12) %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind { ; X86-LABEL: add12i16: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -238,7 +238,7 @@ define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* } %i16vec18 = type <18 x i16> -define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind { +define void @add18i16(%i16vec18* nocapture sret(%i16vec18) %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind { ; X86-LABEL: add18i16: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -277,7 +277,7 @@ define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %i8vec3 = type <3 x i8> -define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind { +define void @add3i8(%i8vec3* nocapture sret(%i8vec3) %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind { ; X86-LABEL: add3i8: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -307,7 +307,7 @@ define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) no } %i8vec31 = type <31 x i8> -define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind { +define void @add31i8(%i8vec31* nocapture sret(%i8vec31) %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind { ; X86-LABEL: add31i8: ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax @@ -347,7 +347,7 @@ define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp %i8vec3pack = type { <3 x i8>, i8 } -define void @rot(%i8vec3pack* nocapture sret %result, %i8vec3pack* %X, %i8vec3pack* %rot) nounwind { +define void @rot(%i8vec3pack* nocapture sret(%i8vec3pack) %result, %i8vec3pack* %X, %i8vec3pack* %rot) nounwind { ; X86-LABEL: rot: ; X86: # %bb.0: # %entry ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax diff --git a/llvm/test/CodeGen/X86/win32_sret.ll b/llvm/test/CodeGen/X86/win32_sret.ll index ea164ae28f876..14e4fba01e6b7 100644 --- a/llvm/test/CodeGen/X86/win32_sret.ll +++ b/llvm/test/CodeGen/X86/win32_sret.ll @@ -13,7 +13,7 @@ ; is callee-cleanup. However, in MSVC's cdecl calling convention, sret pointer ; arguments are caller-cleanup like normal arguments. -define void @sret1(i8* sret %x) nounwind { +define void @sret1(i8* sret(i8) %x) nounwind { entry: ; WIN32-LABEL: _sret1: ; WIN32: movb $42, ({{%e[abcd]x}}) @@ -33,7 +33,7 @@ entry: ret void } -define void @sret2(i8* sret %x, i8 %y) nounwind { +define void @sret2(i8* sret(i8) %x, i8 %y) nounwind { entry: ; WIN32-LABEL: _sret2: ; WIN32: movb {{.*}}, ({{%e[abcd]x}}) @@ -53,7 +53,7 @@ entry: ret void } -define void @sret3(i8* sret %x, i8* %y) nounwind { +define void @sret3(i8* sret(i8) %x, i8* %y) nounwind { entry: ; WIN32-LABEL: _sret3: ; WIN32: movb $42, ([[REG1:%e[abcd]x]]) @@ -78,7 +78,7 @@ entry: ; PR15556 %struct.S4 = type { i32, i32, i32 } -define void @sret4(%struct.S4* noalias sret %agg.result) { +define void @sret4(%struct.S4* noalias sret(%struct.S4) %agg.result) { entry: ; WIN32-LABEL: _sret4: ; WIN32: movl $42, ({{%e[abcd]x}}) @@ -102,7 +102,7 @@ entry: %struct.S5 = type { i32 } %class.C5 = type { i8 } -define x86_thiscallcc void @"\01?foo@C5@@QAE?AUS5@@XZ"(%struct.S5* noalias sret %agg.result, %class.C5* %this) { +define x86_thiscallcc void @"\01?foo@C5@@QAE?AUS5@@XZ"(%struct.S5* noalias sret(%struct.S5) %agg.result, %class.C5* %this) { entry: %this.addr = alloca %class.C5*, align 4 store %class.C5* %this, %class.C5** %this.addr, align 4 @@ -127,7 +127,7 @@ define void @call_foo5() { entry: %c = alloca %class.C5, align 1 %s = alloca %struct.S5, align 4 - call x86_thiscallcc void @"\01?foo@C5@@QAE?AUS5@@XZ"(%struct.S5* sret %s, %class.C5* %c) + call x86_thiscallcc void @"\01?foo@C5@@QAE?AUS5@@XZ"(%struct.S5* sret(%struct.S5) %s, %class.C5* %c) ; WIN32-LABEL: {{^}}_call_foo5: ; MINGW_X86-LABEL: {{^}}_call_foo5: ; CYGWIN-LABEL: {{^}}_call_foo5: @@ -172,10 +172,10 @@ define void @test6_f(%struct.test6* %x) nounwind { ; CYGWIN-NEXT: calll _test6_g %tmp = alloca %struct.test6, align 4 - call x86_thiscallcc void @test6_g(%struct.test6* sret %tmp, %struct.test6* %x) + call x86_thiscallcc void @test6_g(%struct.test6* sret(%struct.test6) %tmp, %struct.test6* %x) ret void } -declare x86_thiscallcc void @test6_g(%struct.test6* sret, %struct.test6*) +declare x86_thiscallcc void @test6_g(%struct.test6* sret(%struct.test6), %struct.test6*) ; Flipping the parameters at the IR level generates the same code. %struct.test7 = type { i32, i32, i32 } @@ -199,11 +199,11 @@ define void @test7_f(%struct.test7* %x) nounwind { ; CYGWIN-NEXT: {{pushl %eax|movl %eax, \(%esp\)}} %tmp = alloca %struct.test7, align 4 - call x86_thiscallcc void @test7_g(%struct.test7* %x, %struct.test7* sret %tmp) + call x86_thiscallcc void @test7_g(%struct.test7* %x, %struct.test7* sret(%struct.test7) %tmp) ret void } -define x86_thiscallcc void @test7_g(%struct.test7* %in, %struct.test7* sret %out) { +define x86_thiscallcc void @test7_g(%struct.test7* %in, %struct.test7* sret(%struct.test7) %out) { %s = getelementptr %struct.test7, %struct.test7* %in, i32 0, i32 0 %d = getelementptr %struct.test7, %struct.test7* %out, i32 0, i32 0 %v = load i32, i32* %s @@ -223,7 +223,7 @@ declare void @clobber_eax() ; Test what happens if the first parameter has to be split by codegen. ; Realistically, no frontend will generate code like this, but here it is for ; completeness. -define void @test8_f(i64 inreg %a, i64* sret %out) { +define void @test8_f(i64 inreg %a, i64* sret(i64) %out) { store i64 %a, i64* %out call void @clobber_eax() ret void diff --git a/llvm/test/CodeGen/X86/win64-byval.ll b/llvm/test/CodeGen/X86/win64-byval.ll index af2af4e6e9b9e..61d4b90b96f45 100644 --- a/llvm/test/CodeGen/X86/win64-byval.ll +++ b/llvm/test/CodeGen/X86/win64-byval.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple x86_64-w64-mingw32 %s -o - | FileCheck %s -declare void @foo({ float, double }* byval) +declare void @foo({ float, double }* byval({ float, double })) @G = external constant { float, double } define void @bar() @@ -14,11 +14,11 @@ define void @bar() ; CHECK: movq %rax, 40(%rsp) ; CHECK: movq %rcx, 32(%rsp) ; CHECK: leaq 32(%rsp), %rcx - call void @foo({ float, double }* byval @G) + call void @foo({ float, double }* byval({ float, double }) @G) ret void } -define void @baz({ float, double }* byval %arg) +define void @baz({ float, double }* byval({ float, double }) %arg) { ; On Win64 the byval is effectively ignored on declarations, since we do ; pass a real pointer in registers. However, by our semantics if we pass @@ -29,11 +29,11 @@ define void @baz({ float, double }* byval %arg) ; CHECK: movq %rcx, 40(%rsp) ; CHECK: movq %rax, 32(%rsp) ; CHECK: leaq 32(%rsp), %rcx - call void @foo({ float, double }* byval %arg) + call void @foo({ float, double }* byval({ float, double }) %arg) ret void } -declare void @foo2({ float, double }* byval, { float, double }* byval, { float, double }* byval, { float, double }* byval, { float, double }* byval, i64 %f) +declare void @foo2({ float, double }* byval({ float, double }), { float, double }* byval({ float, double }), { float, double }* byval({ float, double }), { float, double }* byval({ float, double }), { float, double }* byval({ float, double }), i64 %f) @data = external constant { float, double } define void @test() { @@ -57,6 +57,6 @@ define void @test() { ; CHECK-NEXT: leaq 96(%rsp), %rdx ; CHECK-NEXT: leaq 80(%rsp), %r8 ; CHECK-NEXT: leaq 64(%rsp), %r9 - call void @foo2({ float, double }* byval @G, { float, double }* byval @G, { float, double }* byval @G, { float, double }* byval @G, { float, double }* byval @G, i64 10) + call void @foo2({ float, double }* byval({ float, double }) @G, { float, double }* byval({ float, double }) @G, { float, double }* byval({ float, double }) @G, { float, double }* byval({ float, double }) @G, { float, double }* byval({ float, double }) @G, i64 10) ret void } diff --git a/llvm/test/CodeGen/X86/win64-jumptable.ll b/llvm/test/CodeGen/X86/win64-jumptable.ll index 6bb9d64c05c01..000f176c2a64c 100644 --- a/llvm/test/CodeGen/X86/win64-jumptable.ll +++ b/llvm/test/CodeGen/X86/win64-jumptable.ll @@ -53,7 +53,6 @@ declare void @g(i32) ; CHECK: .quad .LBB0_ ; CHECK: .quad .LBB0_ ; CHECK: .quad .LBB0_ -; CHECK: .seh_handlerdata ; It's important that we switch back to .text here, not .rdata. ; CHECK: .text diff --git a/llvm/test/CodeGen/X86/win64_frame.ll b/llvm/test/CodeGen/X86/win64_frame.ll index ee917615e5b96..242ea8b142082 100644 --- a/llvm/test/CodeGen/X86/win64_frame.ll +++ b/llvm/test/CodeGen/X86/win64_frame.ll @@ -13,8 +13,6 @@ define i32 @f1(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) "frame-pointer"="all ; CHECK-NEXT: movl 48(%rbp), %eax ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc ret i32 %p5 } @@ -37,8 +35,6 @@ define void @f2(i32 %p, ...) "frame-pointer"="all" { ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc %ap = alloca i8, align 8 call void @llvm.va_start(i8* %ap) @@ -56,8 +52,6 @@ define i8* @f3() "frame-pointer"="all" { ; CHECK-NEXT: movq 8(%rbp), %rax ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc %ra = call i8* @llvm.returnaddress(i32 0) ret i8* %ra @@ -77,8 +71,6 @@ define i8* @f4() "frame-pointer"="all" { ; CHECK-NEXT: addq $304, %rsp # imm = 0x130 ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc alloca [300 x i8] %ra = call i8* @llvm.returnaddress(i32 0) @@ -103,8 +95,6 @@ define void @f5() "frame-pointer"="all" { ; CHECK-NEXT: addq $336, %rsp # imm = 0x150 ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc %a = alloca [300 x i8] %gep = getelementptr [300 x i8], [300 x i8]* %a, i32 0, i32 0 @@ -128,8 +118,6 @@ define void @f6(i32 %p, ...) "frame-pointer"="all" { ; CHECK-NEXT: addq $336, %rsp # imm = 0x150 ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc %a = alloca [300 x i8] %gep = getelementptr [300 x i8], [300 x i8]* %a, i32 0, i32 0 @@ -152,8 +140,6 @@ define i32 @f7(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) "frame-pointer"="all" { ; CHECK-NEXT: leaq 176(%rbp), %rsp ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc alloca [300 x i8], align 64 ret i32 %e @@ -191,8 +177,6 @@ define i32 @f8(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) "frame-pointer"="all" { ; CHECK-NEXT: popq %rsi ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc %alloca = alloca [300 x i8], align 64 alloca i32, i32 %a @@ -213,8 +197,6 @@ define i64 @f9() { ; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc entry: %call = call i64 @llvm.x86.flags.read.u64() @@ -244,8 +226,6 @@ define i64 @f10(i64* %foo, i64 %bar, i64 %baz) { ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rsi ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc %cx = cmpxchg i64* %foo, i64 %bar, i64 %baz seq_cst seq_cst %v = extractvalue { i64, i1 } %cx, 0 @@ -266,8 +246,6 @@ define i8* @f11() "frame-pointer"="all" { ; CHECK-NEXT: leaq 8(%rbp), %rax ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq -; CHECK-NEXT: .seh_handlerdata -; CHECK-NEXT: .text ; CHECK-NEXT: .seh_endproc %aora = call i8* @llvm.addressofreturnaddress() ret i8* %aora diff --git a/llvm/test/CodeGen/X86/win64_vararg.ll b/llvm/test/CodeGen/X86/win64_vararg.ll index 91841ced39f24..cf99725f0525c 100644 --- a/llvm/test/CodeGen/X86/win64_vararg.ll +++ b/llvm/test/CodeGen/X86/win64_vararg.ll @@ -110,7 +110,7 @@ entry: ret i32 %tmp } -define void @sret_arg(i32* sret %agg.result, i8* nocapture readnone %format, ...) { +define void @sret_arg(i32* sret(i32) %agg.result, i8* nocapture readnone %format, ...) { entry: %ap = alloca i8* %ap_i8 = bitcast i8** %ap to i8* diff --git a/llvm/test/CodeGen/X86/x86-64-sret-return-2.ll b/llvm/test/CodeGen/X86/x86-64-sret-return-2.ll index 9f57ee1960e12..62a7e83871b9d 100644 --- a/llvm/test/CodeGen/X86/x86-64-sret-return-2.ll +++ b/llvm/test/CodeGen/X86/x86-64-sret-return-2.ll @@ -6,7 +6,7 @@ ; RUNX: llc -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s ; This used to crash due to topological sorting issues in selection DAG. -define void @foo(i32* sret %agg.result, i32, i32, i32, i32, i32, void (i32)* %pred) { +define void @foo(i32* sret(i32) %agg.result, i32, i32, i32, i32, i32, void (i32)* %pred) { entry: call void %pred(i32 undef) ret void diff --git a/llvm/test/CodeGen/X86/x86-64-sret-return.ll b/llvm/test/CodeGen/X86/x86-64-sret-return.ll index a0c43488db1ed..3b685134ec4d9 100644 --- a/llvm/test/CodeGen/X86/x86-64-sret-return.ll +++ b/llvm/test/CodeGen/X86/x86-64-sret-return.ll @@ -11,7 +11,7 @@ ; X32ABI-LABEL: bar: ; X32ABI: movl %edi, %eax -define void @bar(%struct.foo* noalias sret %agg.result, %struct.foo* %d) nounwind { +define void @bar(%struct.foo* noalias sret(%struct.foo) %agg.result, %struct.foo* %d) nounwind { entry: %d_addr = alloca %struct.foo* ; <%struct.foo**> [#uses=2] %memtmp = alloca %struct.foo, align 8 ; <%struct.foo*> [#uses=1] @@ -67,7 +67,7 @@ return: ; preds = %entry ; X32ABI-LABEL: foo: ; X32ABI: movl %edi, %eax -define void @foo({ i64 }* noalias nocapture sret %agg.result) nounwind { +define void @foo({ i64 }* noalias nocapture sret({ i64 }) %agg.result) nounwind { store { i64 } { i64 0 }, { i64 }* %agg.result ret void } diff --git a/llvm/test/CodeGen/X86/x86-big-ret.ll b/llvm/test/CodeGen/X86/x86-big-ret.ll index b7fed33f396b9..a5ad4b0720598 100644 --- a/llvm/test/CodeGen/X86/x86-big-ret.ll +++ b/llvm/test/CodeGen/X86/x86-big-ret.ll @@ -2,7 +2,7 @@ target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" target triple = "i386-pc-windows-msvc" -define x86_fastcallcc i32 @test1(i32 inreg %V, [65533 x i8]* byval %p_arg) { +define x86_fastcallcc i32 @test1(i32 inreg %V, [65533 x i8]* byval([65533 x i8]) %p_arg) { ret i32 %V } ; CHECK-LABEL: @test1@65540: @@ -12,7 +12,7 @@ define x86_fastcallcc i32 @test1(i32 inreg %V, [65533 x i8]* byval %p_arg) { ; CHECK-NEXT: pushl %ecx ; CHECK-NEXT: retl -define x86_stdcallcc void @test2([65533 x i8]* byval %p_arg) { +define x86_stdcallcc void @test2([65533 x i8]* byval([65533 x i8]) %p_arg) { ret void } ; CHECK-LABEL: _test2@65536: diff --git a/llvm/test/CodeGen/XCore/byVal.ll b/llvm/test/CodeGen/XCore/byVal.ll index fde63f41e0db1..71182f359f881 100644 --- a/llvm/test/CodeGen/XCore/byVal.ll +++ b/llvm/test/CodeGen/XCore/byVal.ll @@ -6,7 +6,7 @@ ; CHECK: retsp 1 %struct.st0 = type { [0 x i32] } declare void @f0(%struct.st0*) nounwind -define void @f0Test(%struct.st0* byval %s0) nounwind { +define void @f0Test(%struct.st0* byval(%struct.st0) %s0) nounwind { entry: call void @f0(%struct.st0* %s0) nounwind ret void @@ -29,7 +29,7 @@ entry: ; CHECK: retsp 13 %struct.st1 = type { [10 x i32] } declare void @f1(%struct.st1*) nounwind -define i32 @f1Test(i32 %i, %struct.st1* byval %s1) nounwind { +define i32 @f1Test(i32 %i, %struct.st1* byval(%struct.st1) %s1) nounwind { entry: call void @f1(%struct.st1* %s1) nounwind ret i32 %i @@ -51,7 +51,7 @@ entry: ; CHECK: retsp 0 %struct.st2 = type { i32 } declare void @f2(i32, %struct.st2*) nounwind -define void @f2Test(%struct.st2* byval %s2, i32 %i, ...) nounwind { +define void @f2Test(%struct.st2* byval(%struct.st2) %s2, i32 %i, ...) nounwind { entry: call void @f2(i32 %i, %struct.st2* %s2) ret void @@ -66,7 +66,7 @@ entry: ; CHECK: bl f ; CHECK: retsp 2 declare void @f3(i8*) nounwind -define void @f3Test(i8* byval %v) nounwind { +define void @f3Test(i8* byval(i8) %v) nounwind { entry: call void @f3(i8* %v) nounwind ret void diff --git a/llvm/test/DebugInfo/ARM/selectiondag-deadcode.ll b/llvm/test/DebugInfo/ARM/selectiondag-deadcode.ll index d4d0207bf07db..5246575efd1df 100644 --- a/llvm/test/DebugInfo/ARM/selectiondag-deadcode.ll +++ b/llvm/test/DebugInfo/ARM/selectiondag-deadcode.ll @@ -1,7 +1,7 @@ ; RUN: llc -filetype=asm < %s | FileCheck %s target triple = "thumbv7-apple-ios7.0.0" %class.Matrix3.0.6.10 = type { [9 x float] } -define arm_aapcscc void @_Z9GetMatrixv(%class.Matrix3.0.6.10* noalias nocapture sret %agg.result) #0 !dbg !39 { +define arm_aapcscc void @_Z9GetMatrixv(%class.Matrix3.0.6.10* noalias nocapture sret(%class.Matrix3.0.6.10) %agg.result) #0 !dbg !39 { br i1 fcmp oeq (float fadd (float fadd (float fmul (float undef, float undef), float fmul (float undef, float undef)), float fmul (float undef, float undef)), float 0.000000e+00), label %_ZN7Vector39NormalizeEv.exit, label %1 tail call arm_aapcscc void @_ZL4Sqrtd() #3 br label %_ZN7Vector39NormalizeEv.exit diff --git a/llvm/test/DebugInfo/COFF/class-options-common.ll b/llvm/test/DebugInfo/COFF/class-options-common.ll index da29415489c96..b50c5555c2066 100644 --- a/llvm/test/DebugInfo/COFF/class-options-common.ll +++ b/llvm/test/DebugInfo/COFF/class-options-common.ll @@ -708,7 +708,7 @@ entry: declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_ExplicitCtorClass@@YA?AVExplicitCtorClass@@AEAV1@@Z"(%class.ExplicitCtorClass* noalias sret %agg.result, %class.ExplicitCtorClass* dereferenceable(1) %arg) #0 !dbg !37 { +define dso_local void @"?Func_ExplicitCtorClass@@YA?AVExplicitCtorClass@@AEAV1@@Z"(%class.ExplicitCtorClass* noalias sret(%class.ExplicitCtorClass) %agg.result, %class.ExplicitCtorClass* dereferenceable(1) %arg) #0 !dbg !37 { entry: %arg.addr = alloca %class.ExplicitCtorClass*, align 8 store %class.ExplicitCtorClass* %arg, %class.ExplicitCtorClass** %arg.addr, align 8 @@ -718,7 +718,7 @@ entry: } ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_DefaultedCtorClass@@YA?AVDefaultedCtorClass@@AEAV1@@Z"(%class.DefaultedCtorClass* noalias sret %agg.result, %class.DefaultedCtorClass* dereferenceable(1) %arg) #0 !dbg !49 { +define dso_local void @"?Func_DefaultedCtorClass@@YA?AVDefaultedCtorClass@@AEAV1@@Z"(%class.DefaultedCtorClass* noalias sret(%class.DefaultedCtorClass) %agg.result, %class.DefaultedCtorClass* dereferenceable(1) %arg) #0 !dbg !49 { entry: %arg.addr = alloca %class.DefaultedCtorClass*, align 8 store %class.DefaultedCtorClass* %arg, %class.DefaultedCtorClass** %arg.addr, align 8 @@ -728,7 +728,7 @@ entry: } ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_DefaultArgumentCtorClass@@YA?AVDefaultArgumentCtorClass@@AEAV1@@Z"(%class.DefaultArgumentCtorClass* noalias sret %agg.result, %class.DefaultArgumentCtorClass* dereferenceable(1) %arg) #0 !dbg !61 { +define dso_local void @"?Func_DefaultArgumentCtorClass@@YA?AVDefaultArgumentCtorClass@@AEAV1@@Z"(%class.DefaultArgumentCtorClass* noalias sret(%class.DefaultArgumentCtorClass) %agg.result, %class.DefaultArgumentCtorClass* dereferenceable(1) %arg) #0 !dbg !61 { entry: %arg.addr = alloca %class.DefaultArgumentCtorClass*, align 8 store %class.DefaultArgumentCtorClass* %arg, %class.DefaultArgumentCtorClass** %arg.addr, align 8 @@ -738,7 +738,7 @@ entry: } ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_UserDtorClass@@YA?AVUserDtorClass@@AEAV1@@Z"(%class.UserDtorClass* noalias sret %agg.result, %class.UserDtorClass* dereferenceable(1) %arg) #0 !dbg !73 { +define dso_local void @"?Func_UserDtorClass@@YA?AVUserDtorClass@@AEAV1@@Z"(%class.UserDtorClass* noalias sret(%class.UserDtorClass) %agg.result, %class.UserDtorClass* dereferenceable(1) %arg) #0 !dbg !73 { entry: %arg.addr = alloca %class.UserDtorClass*, align 8 store %class.UserDtorClass* %arg, %class.UserDtorClass** %arg.addr, align 8 @@ -748,7 +748,7 @@ entry: } ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_DefaultedDtorClass@@YA?AVDefaultedDtorClass@@AEAV1@@Z"(%class.DefaultedDtorClass* noalias sret %agg.result, %class.DefaultedDtorClass* dereferenceable(1) %arg) #0 !dbg !85 { +define dso_local void @"?Func_DefaultedDtorClass@@YA?AVDefaultedDtorClass@@AEAV1@@Z"(%class.DefaultedDtorClass* noalias sret(%class.DefaultedDtorClass) %agg.result, %class.DefaultedDtorClass* dereferenceable(1) %arg) #0 !dbg !85 { entry: %arg.addr = alloca %class.DefaultedDtorClass*, align 8 store %class.DefaultedDtorClass* %arg, %class.DefaultedDtorClass** %arg.addr, align 8 @@ -758,7 +758,7 @@ entry: } ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_AClass@@YA?AVAClass@@AEAV1@@Z"(%class.AClass* noalias sret %agg.result, %class.AClass* dereferenceable(1) %arg) #0 !dbg !97 { +define dso_local void @"?Func_AClass@@YA?AVAClass@@AEAV1@@Z"(%class.AClass* noalias sret(%class.AClass) %agg.result, %class.AClass* dereferenceable(1) %arg) #0 !dbg !97 { entry: %arg.addr = alloca %class.AClass*, align 8 store %class.AClass* %arg, %class.AClass** %arg.addr, align 8 @@ -794,7 +794,7 @@ entry: } ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_BStruct@@YA?AUBStruct@@AEAU1@@Z"(%struct.BStruct* noalias sret %agg.result, %struct.BStruct* dereferenceable(1) %arg) #0 !dbg !122 { +define dso_local void @"?Func_BStruct@@YA?AUBStruct@@AEAU1@@Z"(%struct.BStruct* noalias sret(%struct.BStruct) %agg.result, %struct.BStruct* dereferenceable(1) %arg) #0 !dbg !122 { entry: %arg.addr = alloca %struct.BStruct*, align 8 store %struct.BStruct* %arg, %struct.BStruct** %arg.addr, align 8 @@ -825,7 +825,7 @@ entry: } ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_BUnion@@YA?ATBUnion@@AEAT1@@Z"(%union.BUnion* noalias sret %agg.result, %union.BUnion* dereferenceable(1) %arg) #0 !dbg !151 { +define dso_local void @"?Func_BUnion@@YA?ATBUnion@@AEAT1@@Z"(%union.BUnion* noalias sret(%union.BUnion) %agg.result, %union.BUnion* dereferenceable(1) %arg) #0 !dbg !151 { entry: %arg.addr = alloca %union.BUnion*, align 8 store %union.BUnion* %arg, %union.BUnion** %arg.addr, align 8 diff --git a/llvm/test/DebugInfo/COFF/empty-globals-subsection.ll b/llvm/test/DebugInfo/COFF/empty-globals-subsection.ll new file mode 100644 index 0000000000000..b6f3c9a752d05 --- /dev/null +++ b/llvm/test/DebugInfo/COFF/empty-globals-subsection.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s | FileCheck %s + +; The debug info contains a struct with a non-const static member. +; Check that we don't emit a symbol subsection for globals. + +; CHECK-NOT: Symbol subsection for globals + +; ModuleID = 'a.cpp' +source_filename = "a.cpp" +target triple = "x86_64-pc-windows-msvc19.25.28614" + +define dso_local i32 @main() { +entry: + ret i32 0 +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!8, !9} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, nameTableKind: None) +!1 = !DIFile(filename: "a.cpp", directory: "C:/path/to/test", checksumkind: CSK_MD5, checksum: "a1dbf3aabea9e8f9d1be48f60287942f") +!2 = !{} +!3 = !{!4} +!4 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "S", file: !1, line: 5, size: 32, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: !5, identifier: ".?AU?$A@J@@") +!5 = !{!6} +!6 = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: !4, file: !1, line: 6, baseType: !7, size: 32, flags: DIFlagStaticMember) +!7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!8 = !{i32 2, !"CodeView", i32 1} +!9 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/llvm/test/DebugInfo/COFF/fpo-shrink-wrap.ll b/llvm/test/DebugInfo/COFF/fpo-shrink-wrap.ll index e8f37a370666c..08aecdac5b794 100644 --- a/llvm/test/DebugInfo/COFF/fpo-shrink-wrap.ll +++ b/llvm/test/DebugInfo/COFF/fpo-shrink-wrap.ll @@ -33,7 +33,7 @@ ; ASM: popl %ebx ; ASM: [[EPILOGUE]]: # %return ; ASM: retl $8 -; ASM: Ltmp11: +; ASM: Ltmp10: ; ASM: .cv_fpo_endproc ; Note how RvaStart advances 7 bytes to skip the shrink-wrapped portion. diff --git a/llvm/test/DebugInfo/COFF/function-options.ll b/llvm/test/DebugInfo/COFF/function-options.ll index 7e166facf3825..835f3fbe3c8ae 100644 --- a/llvm/test/DebugInfo/COFF/function-options.ll +++ b/llvm/test/DebugInfo/COFF/function-options.ll @@ -409,7 +409,7 @@ entry: declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_BClass@@YA?AVBClass@@AEAV1@@Z"(%class.BClass* noalias sret %agg.result, %class.BClass* dereferenceable(1) %arg) #0 !dbg !15 { +define dso_local void @"?Func_BClass@@YA?AVBClass@@AEAV1@@Z"(%class.BClass* noalias sret(%class.BClass) %agg.result, %class.BClass* dereferenceable(1) %arg) #0 !dbg !15 { entry: %result.ptr = alloca i8*, align 8 %arg.addr = alloca %class.BClass*, align 8 @@ -422,7 +422,7 @@ entry: } ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_C1Class@@YA?AVC1Class@@AEAV1@@Z"(%class.C1Class* noalias sret %agg.result, %class.C1Class* dereferenceable(1) %arg) #0 !dbg !27 { +define dso_local void @"?Func_C1Class@@YA?AVC1Class@@AEAV1@@Z"(%class.C1Class* noalias sret(%class.C1Class) %agg.result, %class.C1Class* dereferenceable(1) %arg) #0 !dbg !27 { entry: %result.ptr = alloca i8*, align 8 %arg.addr = alloca %class.C1Class*, align 8 @@ -435,7 +435,7 @@ entry: } ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_C2Class@@YA?AVC2Class@@AEAV1@@Z"(%class.C2Class* noalias sret %agg.result, %class.C2Class* dereferenceable(1) %arg) #0 !dbg !39 { +define dso_local void @"?Func_C2Class@@YA?AVC2Class@@AEAV1@@Z"(%class.C2Class* noalias sret(%class.C2Class) %agg.result, %class.C2Class* dereferenceable(1) %arg) #0 !dbg !39 { entry: %result.ptr = alloca i8*, align 8 %arg.addr = alloca %class.C2Class*, align 8 @@ -448,7 +448,7 @@ entry: } ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_DClass@@YA?AVDClass@@AEAV1@@Z"(%class.DClass* noalias sret %agg.result, %class.DClass* dereferenceable(1) %arg) #0 !dbg !51 { +define dso_local void @"?Func_DClass@@YA?AVDClass@@AEAV1@@Z"(%class.DClass* noalias sret(%class.DClass) %agg.result, %class.DClass* dereferenceable(1) %arg) #0 !dbg !51 { entry: %result.ptr = alloca i8*, align 8 %arg.addr = alloca %class.DClass*, align 8 @@ -487,7 +487,7 @@ entry: } ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_BStruct@@YA?AUBStruct@@AEAU1@@Z"(%struct.BStruct* noalias sret %agg.result, %struct.BStruct* dereferenceable(1) %arg) #0 !dbg !84 { +define dso_local void @"?Func_BStruct@@YA?AUBStruct@@AEAU1@@Z"(%struct.BStruct* noalias sret(%struct.BStruct) %agg.result, %struct.BStruct* dereferenceable(1) %arg) #0 !dbg !84 { entry: %result.ptr = alloca i8*, align 8 %arg.addr = alloca %struct.BStruct*, align 8 @@ -513,7 +513,7 @@ entry: } ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?Func_BUnion@@YA?ATBUnion@@AEAT1@@Z"(%union.BUnion* noalias sret %agg.result, %union.BUnion* dereferenceable(1) %arg) #0 !dbg !103 { +define dso_local void @"?Func_BUnion@@YA?ATBUnion@@AEAT1@@Z"(%union.BUnion* noalias sret(%union.BUnion) %agg.result, %union.BUnion* dereferenceable(1) %arg) #0 !dbg !103 { entry: %result.ptr = alloca i8*, align 8 %arg.addr = alloca %union.BUnion*, align 8 diff --git a/llvm/test/DebugInfo/COFF/lines-bb-start.ll b/llvm/test/DebugInfo/COFF/lines-bb-start.ll index 711ba704ffd38..4fb9234240938 100644 --- a/llvm/test/DebugInfo/COFF/lines-bb-start.ll +++ b/llvm/test/DebugInfo/COFF/lines-bb-start.ll @@ -92,7 +92,6 @@ return: ; preds = %if.end, %if.then ; CHECK: LBB2_{{.*}}: # %if.end ; CHECK-NEXT: .cv_loc {{.*}} # t.c:5:3 ; CHECK: leal 4(%esp), %[[reg:[^ ]*]] -; CHECK: #DEBUG_VALUE: lea_dbg_value:v <- [DW_OP_deref] $[[reg]] ; CHECK: movl %[[reg]], (%esp) ; CHECK: calll _use_i32 diff --git a/llvm/test/DebugInfo/COFF/nrvo.ll b/llvm/test/DebugInfo/COFF/nrvo.ll index 77f13fcb7daf3..7bd9d35b7a00e 100644 --- a/llvm/test/DebugInfo/COFF/nrvo.ll +++ b/llvm/test/DebugInfo/COFF/nrvo.ll @@ -68,7 +68,7 @@ entry: declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 ; Function Attrs: noinline nounwind optnone uwtable -define dso_local void @"?GetFoo@@YA?AUFoo@@XZ"(%struct.Foo* noalias sret %agg.result) #0 !dbg !14 { +define dso_local void @"?GetFoo@@YA?AUFoo@@XZ"(%struct.Foo* noalias sret(%struct.Foo) %agg.result) #0 !dbg !14 { entry: %result.ptr = alloca i8*, align 8 %0 = bitcast %struct.Foo* %agg.result to i8* @@ -89,7 +89,7 @@ entry: %bar = alloca %struct.Foo, align 4 store i32 0, i32* %retval, align 4 call void @llvm.dbg.declare(metadata %struct.Foo* %bar, metadata !36, metadata !DIExpression()), !dbg !37 - call void @"?GetFoo@@YA?AUFoo@@XZ"(%struct.Foo* sret %bar), !dbg !37 + call void @"?GetFoo@@YA?AUFoo@@XZ"(%struct.Foo* sret(%struct.Foo) %bar), !dbg !37 %x = getelementptr inbounds %struct.Foo, %struct.Foo* %bar, i32 0, i32 0, !dbg !38 %0 = load i32, i32* %x, align 4, !dbg !38 ret i32 %0, !dbg !38 diff --git a/llvm/test/DebugInfo/Generic/2010-10-01-crash.ll b/llvm/test/DebugInfo/Generic/2010-10-01-crash.ll index 3e5f4db7d75aa..acab6e8a33d48 100644 --- a/llvm/test/DebugInfo/Generic/2010-10-01-crash.ll +++ b/llvm/test/DebugInfo/Generic/2010-10-01-crash.ll @@ -1,6 +1,6 @@ ; RUN: llc -O0 %s -o /dev/null -define void @CGRectStandardize(i32* sret %agg.result, i32* byval %rect) nounwind ssp !dbg !0 { +define void @CGRectStandardize(i32* sret(i32) %agg.result, i32* byval(i32) %rect) nounwind ssp !dbg !0 { entry: call void @llvm.dbg.declare(metadata i32* %rect, metadata !23, metadata !DIExpression()), !dbg !24 ret void diff --git a/llvm/test/DebugInfo/Mips/delay-slot.ll b/llvm/test/DebugInfo/Mips/delay-slot.ll index 07c2caa8999c3..c4c5417929574 100644 --- a/llvm/test/DebugInfo/Mips/delay-slot.ll +++ b/llvm/test/DebugInfo/Mips/delay-slot.ll @@ -14,8 +14,11 @@ ; CHECK: ------------------ ------ ------ ------ --- ------------- ------------- ; CHECK: 0x0000000000000000 1 0 1 0 0 is_stmt ; CHECK: 0x0000000000000004 2 0 1 0 0 is_stmt prologue_end -; CHECK: 0x0000000000000020 3 0 1 0 0 is_stmt -; CHECK: 0x0000000000000030 4 0 1 0 0 is_stmt +; CHECK: 0x0000000000000020 0 0 1 0 0 +; CHECK: 0x0000000000000028 3 0 1 0 0 is_stmt +; CHECK: 0x0000000000000030 0 0 1 0 0 +; CHECK: 0x0000000000000038 4 0 1 0 0 is_stmt +; CHECK: 0x0000000000000040 0 0 1 0 0 ; CHECK: 0x0000000000000048 5 0 1 0 0 is_stmt ; CHECK: 0x0000000000000050 5 0 1 0 0 is_stmt end_sequence diff --git a/llvm/test/DebugInfo/X86/DIModuleContext.ll b/llvm/test/DebugInfo/X86/DIModuleContext.ll index e9dd9116b3939..aee57033f431e 100644 --- a/llvm/test/DebugInfo/X86/DIModuleContext.ll +++ b/llvm/test/DebugInfo/X86/DIModuleContext.ll @@ -1,6 +1,6 @@ source_filename = "test/DebugInfo/X86/DIModuleContext.ll" target triple = "x86_64-apple-macosx" -; RUN: %llc_dwarf %s -o - -filetype=obj \ +; RUN: llc %s -o - -filetype=obj \ ; RUN: | llvm-dwarfdump -debug-info - | FileCheck %s ; CHECK: DW_TAG_module ; CHECK-NOT: NULL diff --git a/llvm/test/DebugInfo/X86/Fortran-DIModule.ll b/llvm/test/DebugInfo/X86/Fortran-DIModule.ll index 37c46d1d02e86..39ada5e42f40e 100644 --- a/llvm/test/DebugInfo/X86/Fortran-DIModule.ll +++ b/llvm/test/DebugInfo/X86/Fortran-DIModule.ll @@ -1,5 +1,5 @@ ; This test checks attributes of a Fortran module. -; RUN: %llc_dwarf %s -filetype=obj -o - | \ +; RUN: llc %s -filetype=obj -o - | \ ; RUN: llvm-dwarfdump - | FileCheck %s ; CHECK: DW_TAG_module diff --git a/llvm/test/DebugInfo/X86/abstract_origin.ll b/llvm/test/DebugInfo/X86/abstract_origin.ll index 36992177e341c..a9eb970cfb629 100644 --- a/llvm/test/DebugInfo/X86/abstract_origin.ll +++ b/llvm/test/DebugInfo/X86/abstract_origin.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj %s -o - | llvm-dwarfdump -debug-info - | FileCheck %s +; RUN: llc -filetype=obj %s -o - | llvm-dwarfdump -debug-info - | FileCheck %s ; Generated at -O2 from: ; void f(); ; __attribute__((always_inline)) void g() { diff --git a/llvm/test/DebugInfo/X86/align_c11.ll b/llvm/test/DebugInfo/X86/align_c11.ll index cc0383a8ca93a..baadca1ba6a42 100644 --- a/llvm/test/DebugInfo/X86/align_c11.ll +++ b/llvm/test/DebugInfo/X86/align_c11.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s +; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s ; Generated by clang -c -g -std=c11 -S -emit-llvm from the following C11 source ; diff --git a/llvm/test/DebugInfo/X86/align_cpp11.ll b/llvm/test/DebugInfo/X86/align_cpp11.ll index 92dfdaee53908..10116e3c6a893 100644 --- a/llvm/test/DebugInfo/X86/align_cpp11.ll +++ b/llvm/test/DebugInfo/X86/align_cpp11.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s +; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s ; Generated by clang++ -c -g -std=c++11 -S -emit-llvm from the following C++11 source ; struct S { diff --git a/llvm/test/DebugInfo/X86/align_objc.ll b/llvm/test/DebugInfo/X86/align_objc.ll index 9ce6dea0a41da..13bbf862e9b13 100644 --- a/llvm/test/DebugInfo/X86/align_objc.ll +++ b/llvm/test/DebugInfo/X86/align_objc.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s +; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s ; typedef struct __attribute__((aligned (128))) { ; char c; diff --git a/llvm/test/DebugInfo/X86/atomic-c11-dwarf-4.ll b/llvm/test/DebugInfo/X86/atomic-c11-dwarf-4.ll index c31b7d168c455..820182d9031f5 100644 --- a/llvm/test/DebugInfo/X86/atomic-c11-dwarf-4.ll +++ b/llvm/test/DebugInfo/X86/atomic-c11-dwarf-4.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s +; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s ; Generated by clang -c -g -std=c11 -S -emit-llvm from the following C11 source ; diff --git a/llvm/test/DebugInfo/X86/atomic-c11-dwarf-5.ll b/llvm/test/DebugInfo/X86/atomic-c11-dwarf-5.ll index 88ada8dc6027e..5a06d32bc4207 100644 --- a/llvm/test/DebugInfo/X86/atomic-c11-dwarf-5.ll +++ b/llvm/test/DebugInfo/X86/atomic-c11-dwarf-5.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s +; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s ; Generated by clang -c -g -std=c11 -S -emit-llvm from the following C11 source ; diff --git a/llvm/test/DebugInfo/X86/byvalstruct.ll b/llvm/test/DebugInfo/X86/byvalstruct.ll index 9db9d733e8a36..63f6e8a4c7514 100644 --- a/llvm/test/DebugInfo/X86/byvalstruct.ll +++ b/llvm/test/DebugInfo/X86/byvalstruct.ll @@ -58,7 +58,7 @@ target triple = "x86_64-apple-macosx10.8.0" @llvm.used = appending global [5 x i8*] [i8* getelementptr inbounds ([7 x i8], [7 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* getelementptr inbounds ([23 x i8], [23 x i8]* @"\01L_OBJC_METH_VAR_TYPE_", i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_INSTANCE_METHODS_Bitmap" to i8*), i8* bitcast ([1 x i8*]* @"\01L_OBJC_LABEL_CLASS_$" to i8*)], section "llvm.metadata" ; Function Attrs: ssp uwtable -define internal i8* @"\01-[Bitmap initWithCopy:andInfo:andLength:]"(%0* %self, i8* %_cmd, %0* %otherBitmap, %struct.ImageInfo* byval align 8 %info, i64 %length) #0 !dbg !7 { +define internal i8* @"\01-[Bitmap initWithCopy:andInfo:andLength:]"(%0* %self, i8* %_cmd, %0* %otherBitmap, %struct.ImageInfo* byval(%struct.ImageInfo) align 8 %info, i64 %length) #0 !dbg !7 { entry: %retval = alloca i8*, align 8 %self.addr = alloca %0*, align 8 diff --git a/llvm/test/DebugInfo/X86/constant-loclist.ll b/llvm/test/DebugInfo/X86/constant-loclist.ll index 7bc68ad007635..86bcf113b6574 100644 --- a/llvm/test/DebugInfo/X86/constant-loclist.ll +++ b/llvm/test/DebugInfo/X86/constant-loclist.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj %s -o - | llvm-dwarfdump -v -debug-info - | FileCheck %s +; RUN: llc -filetype=obj %s -o - | llvm-dwarfdump -v -debug-info - | FileCheck %s ; A hand-written testcase to check 64-bit constant handling in location lists. diff --git a/llvm/test/DebugInfo/X86/containing-type-extension-rust.ll b/llvm/test/DebugInfo/X86/containing-type-extension-rust.ll index fd7ee96fc304e..3e6c6d2690824 100644 --- a/llvm/test/DebugInfo/X86/containing-type-extension-rust.ll +++ b/llvm/test/DebugInfo/X86/containing-type-extension-rust.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -O0 -filetype=obj < %s > %t +; RUN: llc -O0 -filetype=obj < %s > %t ; RUN: llvm-dwarfdump -v -debug-info %t | FileCheck %s ; Check that any type can have a vtable holder. diff --git a/llvm/test/DebugInfo/X86/convert-debugloc.ll b/llvm/test/DebugInfo/X86/convert-debugloc.ll index a61127ab6932f..fc31c3f72549e 100644 --- a/llvm/test/DebugInfo/X86/convert-debugloc.ll +++ b/llvm/test/DebugInfo/X86/convert-debugloc.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -dwarf-version=4 -filetype=obj -O0 < %s | llvm-dwarfdump - \ +; RUN: llc -mtriple=x86_64 -dwarf-version=4 -filetype=obj -O0 < %s | llvm-dwarfdump - \ ; RUN: | FileCheck %s --check-prefix=NOCONV "--implicit-check-not={{DW_TAG|NULL}}" ; Test lldb default: OP_convert is unsupported when using MachO @@ -8,13 +8,13 @@ ; RUN: | FileCheck %s --check-prefix=NOCONV "--implicit-check-not={{DW_TAG|NULL}}" ; Test gdb default: OP_convert is only disabled in split DWARF -; RUN: %llc_dwarf -dwarf-version=5 -filetype=obj -O0 < %s -debugger-tune=gdb | llvm-dwarfdump - \ +; RUN: llc -mtriple=x86_64 -dwarf-version=5 -filetype=obj -O0 < %s -debugger-tune=gdb | llvm-dwarfdump - \ ; RUN: | FileCheck %s --check-prefix=CONV "--implicit-check-not={{DW_TAG|NULL}}" ; RUN: llc -mtriple=x86_64-pc-linux-gnu -dwarf-version=5 -filetype=obj -O0 < %s -debugger-tune=gdb -split-dwarf-file=baz.dwo | llvm-dwarfdump - \ ; RUN: | FileCheck %s --check-prefix=NOCONV --check-prefix=SPLIT "--implicit-check-not={{DW_TAG|NULL}}" ; Test the ability to override the platform default in either direction -; RUN: %llc_dwarf -dwarf-version=5 -filetype=obj -O0 < %s -debugger-tune=gdb -dwarf-op-convert=Disable | llvm-dwarfdump - \ +; RUN: llc -mtriple=x86_64 -dwarf-version=5 -filetype=obj -O0 < %s -debugger-tune=gdb -dwarf-op-convert=Disable | llvm-dwarfdump - \ ; RUN: | FileCheck %s --check-prefix=NOCONV "--implicit-check-not={{DW_TAG|NULL}}" ; RUN: llc -mtriple=x86_64-pc-linux-gnu -dwarf-version=5 -filetype=obj -O0 < %s -debugger-tune=lldb -dwarf-op-convert=Enable | llvm-dwarfdump - \ ; RUN: | FileCheck %s --check-prefix=CONV "--implicit-check-not={{DW_TAG|NULL}}" @@ -23,7 +23,7 @@ ; RUN: llc -mtriple=x86_64-pc-linux-gnu -dwarf-version=5 -filetype=obj -O0 < %s -debugger-tune=lldb -dwarf-op-convert=Enable -split-dwarf-file=baz.dwo | llvm-dwarfdump - \ ; RUN: | FileCheck %s --check-prefix=CONV --check-prefix=SPLITCONV --check-prefix=SPLIT "--implicit-check-not={{DW_TAG|NULL}}" -; RUN: %llc_dwarf -dwarf-version=5 -filetype=obj -O0 < %s -debugger-tune=gdb | llvm-dwarfdump -v -debug-info - \ +; RUN: llc -mtriple=x86_64 -dwarf-version=5 -filetype=obj -O0 < %s -debugger-tune=gdb | llvm-dwarfdump -v -debug-info - \ ; RUN: | FileCheck %s --check-prefix=VERBOSE --check-prefix=CONV "--implicit-check-not={{DW_TAG|NULL}}" diff --git a/llvm/test/DebugInfo/X86/convert-inlined.ll b/llvm/test/DebugInfo/X86/convert-inlined.ll index 5e28a7293d80b..14f9a8a3e26ed 100644 --- a/llvm/test/DebugInfo/X86/convert-inlined.ll +++ b/llvm/test/DebugInfo/X86/convert-inlined.ll @@ -1,6 +1,6 @@ -; RUN: %llc_dwarf -dwarf-version=5 -filetype=obj -O0 < %s | llvm-dwarfdump - \ +; RUN: llc -mtriple=x86_64 -dwarf-version=5 -filetype=obj -O0 < %s | llvm-dwarfdump - \ ; RUN: | FileCheck %s --check-prefix=DW5 "--implicit-check-not={{DW_TAG|NULL}}" -; RUN: %llc_dwarf -dwarf-version=4 -filetype=obj -O0 < %s | llvm-dwarfdump - \ +; RUN: llc -mtriple=x86_64 -dwarf-version=4 -filetype=obj -O0 < %s | llvm-dwarfdump - \ ; RUN: | FileCheck %s --check-prefix=DW4 "--implicit-check-not={{DW_TAG|NULL}}" ; DW5: .debug_info contents: diff --git a/llvm/test/DebugInfo/X86/convert-linked.ll b/llvm/test/DebugInfo/X86/convert-linked.ll index 4635941b9b141..97218e65075bb 100644 --- a/llvm/test/DebugInfo/X86/convert-linked.ll +++ b/llvm/test/DebugInfo/X86/convert-linked.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj -O0 < %s | llvm-dwarfdump - | FileCheck %s +; RUN: llc -mtriple=x86_64 -filetype=obj -O0 < %s | llvm-dwarfdump - | FileCheck %s ; CHECK: DW_TAG_compile_unit ; CHECK: [[CU0BT0:0x[0-9a-f]+]]: DW_TAG_base_type diff --git a/llvm/test/DebugInfo/X86/convert-loclist.ll b/llvm/test/DebugInfo/X86/convert-loclist.ll index 06b91cada1305..b34e0420fb92f 100644 --- a/llvm/test/DebugInfo/X86/convert-loclist.ll +++ b/llvm/test/DebugInfo/X86/convert-loclist.ll @@ -1,8 +1,8 @@ -; RUN: %llc_dwarf -filetype=obj < %s \ +; RUN: llc -mtriple=x86_64 -filetype=obj < %s \ ; RUN: | llvm-dwarfdump -debug-info -debug-loclists - | FileCheck %s -; RUN: llc -mtriple x86_64-pc-linux -split-dwarf-file=foo.dwo -filetype=obj -dwarf-op-convert=Enable < %s \ +; RUN: llc -mtriple=x86_64 -split-dwarf-file=foo.dwo -filetype=obj -dwarf-op-convert=Enable < %s \ ; RUN: | llvm-dwarfdump -debug-info -debug-loclists - | FileCheck --check-prefix=SPLIT --check-prefix=CHECK %s -; RUN: llc -mtriple x86_64-pc-linux -split-dwarf-file=foo.dwo -filetype=asm -dwarf-op-convert=Enable < %s \ +; RUN: llc -mtriple=x86_64 -split-dwarf-file=foo.dwo -filetype=asm -dwarf-op-convert=Enable < %s \ ; RUN: | FileCheck --check-prefix=ASM %s ; A bit of a brittle test - this is testing the specific DWO_id. The diff --git a/llvm/test/DebugInfo/X86/dbg-byval-parameter.ll b/llvm/test/DebugInfo/X86/dbg-byval-parameter.ll index fdf5d49b31adf..c35c4aa9d346d 100644 --- a/llvm/test/DebugInfo/X86/dbg-byval-parameter.ll +++ b/llvm/test/DebugInfo/X86/dbg-byval-parameter.ll @@ -1,10 +1,10 @@ -; RUN: %llc_dwarf -march=x86 -asm-verbose < %s | grep DW_TAG_formal_parameter +; RUN: llc -mtriple=x86_64 -asm-verbose < %s | grep DW_TAG_formal_parameter %struct.Pt = type { double, double } %struct.Rect = type { %struct.Pt, %struct.Pt } -define double @foo(%struct.Rect* byval %my_r0) nounwind ssp !dbg !1 { +define double @foo(%struct.Rect* byval(%struct.Rect) %my_r0) nounwind ssp !dbg !1 { entry: %retval = alloca double ; [#uses=2] %0 = alloca double ; [#uses=2] diff --git a/llvm/test/DebugInfo/X86/dbg-declare-arg.ll b/llvm/test/DebugInfo/X86/dbg-declare-arg.ll index b2b88cb8b1b82..3498cc3038b7d 100644 --- a/llvm/test/DebugInfo/X86/dbg-declare-arg.ll +++ b/llvm/test/DebugInfo/X86/dbg-declare-arg.ll @@ -25,7 +25,7 @@ target triple = "x86_64-apple-macosx10.6.7" %class.A = type { i32, i32, i32, i32 } -define void @_Z3fooi(%class.A* sret %agg.result, i32 %i) ssp !dbg !19 { +define void @_Z3fooi(%class.A* sret(%class.A) %agg.result, i32 %i) ssp !dbg !19 { entry: %i.addr = alloca i32, align 4 %j = alloca i32, align 4 diff --git a/llvm/test/DebugInfo/X86/dbg_value_direct.ll b/llvm/test/DebugInfo/X86/dbg_value_direct.ll index 9b2d63a5ea2f1..daaca2ffb600c 100644 --- a/llvm/test/DebugInfo/X86/dbg_value_direct.ll +++ b/llvm/test/DebugInfo/X86/dbg_value_direct.ll @@ -23,7 +23,7 @@ target triple = "x86_64-unknown-linux-gnu" @___asan_gen_ = private unnamed_addr constant [16 x i8] c"1 32 4 5 .addr \00", align 1 ; Function Attrs: sanitize_address uwtable -define void @_Z4funci(%struct.A* noalias sret %agg.result, i32) #0 "stack-protector-buffer-size"="1" !dbg !4 { +define void @_Z4funci(%struct.A* noalias sret(%struct.A) %agg.result, i32) #0 "stack-protector-buffer-size"="1" !dbg !4 { entry: %MyAlloca = alloca [96 x i8], align 32 %1 = ptrtoint [96 x i8]* %MyAlloca to i64 diff --git a/llvm/test/DebugInfo/X86/debug-info-auto-return.ll b/llvm/test/DebugInfo/X86/debug-info-auto-return.ll index cce4b8005d1f4..09486c2fd248d 100644 --- a/llvm/test/DebugInfo/X86/debug-info-auto-return.ll +++ b/llvm/test/DebugInfo/X86/debug-info-auto-return.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf %s -filetype=obj -o - | llvm-dwarfdump -v - | FileCheck %s +; RUN: llc %s -filetype=obj -o - | llvm-dwarfdump -v - | FileCheck %s ; CHECK: .debug_info contents: diff --git a/llvm/test/DebugInfo/X86/debug-info-packed-struct.ll b/llvm/test/DebugInfo/X86/debug-info-packed-struct.ll index c7304471e7273..d9eeab4ccd37f 100644 --- a/llvm/test/DebugInfo/X86/debug-info-packed-struct.ll +++ b/llvm/test/DebugInfo/X86/debug-info-packed-struct.ll @@ -3,7 +3,7 @@ source_filename = "test/DebugInfo/X86/debug-info-packed-struct.ll" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-darwin" -; RUN: %llc_dwarf -O0 -filetype=obj -o %t.o %s +; RUN: llc -O0 -filetype=obj -o %t.o %s ; RUN: llvm-dwarfdump -v -debug-info %t.o | FileCheck %s ; // --------------------------------------------------------------------- diff --git a/llvm/test/DebugInfo/X86/debug-info-template-parameter.ll b/llvm/test/DebugInfo/X86/debug-info-template-parameter.ll index cf4b65d00694a..48dfd7d3dce93 100755 --- a/llvm/test/DebugInfo/X86/debug-info-template-parameter.ll +++ b/llvm/test/DebugInfo/X86/debug-info-template-parameter.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf %s -filetype=obj -o - | llvm-dwarfdump -v - | FileCheck %s +; RUN: llc %s -filetype=obj -o - | llvm-dwarfdump -v - | FileCheck %s ; C++ source to regenerate: diff --git a/llvm/test/DebugInfo/X86/debug-macinfo-split-dwarf.ll b/llvm/test/DebugInfo/X86/debug-macinfo-split-dwarf.ll index f7cbff4013ca7..459ae54806dbb 100644 --- a/llvm/test/DebugInfo/X86/debug-macinfo-split-dwarf.ll +++ b/llvm/test/DebugInfo/X86/debug-macinfo-split-dwarf.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -O0 -split-dwarf-file=foo.dwo -filetype=obj < %s | llvm-dwarfdump --debug-info --debug-macro - | FileCheck %s +; RUN: llc -O0 -split-dwarf-file=foo.dwo -filetype=obj < %s | llvm-dwarfdump --debug-info --debug-macro - | FileCheck %s ; CHECK:.debug_info.dwo contents: ; CHECK: DW_TAG_compile_unit diff --git a/llvm/test/DebugInfo/X86/debug-macro-dwo.ll b/llvm/test/DebugInfo/X86/debug-macro-dwo.ll index 23e889f5efced..90b1088d0051d 100644 --- a/llvm/test/DebugInfo/X86/debug-macro-dwo.ll +++ b/llvm/test/DebugInfo/X86/debug-macro-dwo.ll @@ -1,7 +1,7 @@ ; This test checks emission of .debug_macro.dwo section when ; -gdwarf-5 -gsplit-dwarf -fdebug-macro is specified. -; RUN: %llc_dwarf -dwarf-version=5 -O0 -filetype=obj \ +; RUN: llc -dwarf-version=5 -O0 -filetype=obj \ ; RUN: -split-dwarf-file=foo.dwo < %s | llvm-dwarfdump -debug-macro -debug-info -debug-line -v - | FileCheck %s ; CHECK-LABEL: .debug_info contents: diff --git a/llvm/test/DebugInfo/X86/debug-macro-gnu-dwo.ll b/llvm/test/DebugInfo/X86/debug-macro-gnu-dwo.ll index b9050a681f7c6..4c71b82d24be3 100644 --- a/llvm/test/DebugInfo/X86/debug-macro-gnu-dwo.ll +++ b/llvm/test/DebugInfo/X86/debug-macro-gnu-dwo.ll @@ -3,7 +3,7 @@ ; -gdwarf-4 -gsplit-dwarf -fdebug-macro is specified, regardless of the GNU ; extension being requested. -; RUN: %llc_dwarf -dwarf-version=4 -O0 -filetype=obj -use-gnu-debug-macro \ +; RUN: llc -dwarf-version=4 -O0 -filetype=obj -use-gnu-debug-macro \ ; RUN: -split-dwarf-file=foo.dwo < %s | llvm-dwarfdump -v - | FileCheck %s ; CHECK: .debug_info.dwo contents: diff --git a/llvm/test/DebugInfo/X86/debug-macro-gnu.ll b/llvm/test/DebugInfo/X86/debug-macro-gnu.ll index 24b90192c99c7..cb322b5cddd74 100644 --- a/llvm/test/DebugInfo/X86/debug-macro-gnu.ll +++ b/llvm/test/DebugInfo/X86/debug-macro-gnu.ll @@ -1,6 +1,6 @@ ; This test checks emission of the GNU extension for the .debug_macro section. -; RUN: %llc_dwarf -dwarf-version=4 -O0 -use-gnu-debug-macro -filetype=obj < %s | llvm-dwarfdump -v - | FileCheck %s +; RUN: llc -dwarf-version=4 -O0 -use-gnu-debug-macro -filetype=obj < %s | llvm-dwarfdump -v - | FileCheck %s ; CHECK-LABEL: .debug_info contents: ; CHECK: DW_AT_GNU_macros [DW_FORM_sec_offset] (0x00000000) diff --git a/llvm/test/DebugInfo/X86/debug-macro-v5.ll b/llvm/test/DebugInfo/X86/debug-macro-v5.ll index a0334c027e716..549d8f0cadd14 100644 --- a/llvm/test/DebugInfo/X86/debug-macro-v5.ll +++ b/llvm/test/DebugInfo/X86/debug-macro-v5.ll @@ -1,7 +1,7 @@ ; This test checks emission of .debug_macro section when ; -gdwarf-5 -fdebug-macro is specified. -; RUN: %llc_dwarf -dwarf-version=5 -O0 -filetype=obj < %s | llvm-dwarfdump -v - | FileCheck %s +; RUN: llc -dwarf-version=5 -O0 -filetype=obj < %s | llvm-dwarfdump -v - | FileCheck %s ; CHECK-LABEL: .debug_info contents: ; CHECK: DW_AT_macros [DW_FORM_sec_offset] (0x00000000) diff --git a/llvm/test/DebugInfo/X86/debug-macro.ll b/llvm/test/DebugInfo/X86/debug-macro.ll index fbcfab6610d5e..74dc1893ea7f4 100644 --- a/llvm/test/DebugInfo/X86/debug-macro.ll +++ b/llvm/test/DebugInfo/X86/debug-macro.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -O0 -filetype=obj < %s | llvm-dwarfdump -v - | FileCheck %s +; RUN: llc -mtriple=x86_64 -O0 -filetype=obj < %s | llvm-dwarfdump -v - | FileCheck %s ; CHECK-LABEL: .debug_info contents: diff --git a/llvm/test/DebugInfo/X86/distringtype.ll b/llvm/test/DebugInfo/X86/distringtype.ll index 6987bc405d897..65fac64ae3b1b 100644 --- a/llvm/test/DebugInfo/X86/distringtype.ll +++ b/llvm/test/DebugInfo/X86/distringtype.ll @@ -5,7 +5,7 @@ ;; !DIStringType(name: "character(*)", stringLength: !{{[0-9]+}}, ;; stringLengthExpression: !DIExpression(), size: 32) -; RUN: %llc_dwarf -filetype=obj %s -o - | llvm-dwarfdump - | FileCheck %s +; RUN: llc -filetype=obj %s -o - | llvm-dwarfdump - | FileCheck %s ; CHECK: DW_TAG_string_type ; CHECK: DW_AT_name ("character(*)!2") ; CHECK-NEXT: DW_AT_string_length diff --git a/llvm/test/DebugInfo/X86/double-declare.ll b/llvm/test/DebugInfo/X86/double-declare.ll index da6c4d04ebbbe..303d86353b710 100644 --- a/llvm/test/DebugInfo/X86/double-declare.ll +++ b/llvm/test/DebugInfo/X86/double-declare.ll @@ -8,7 +8,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) -define void @f(i32* byval %p, i1 %c) !dbg !5 { +define void @f(i32* byval(i32) %p, i1 %c) !dbg !5 { br i1 %c, label %x, label %y x: diff --git a/llvm/test/DebugInfo/X86/dwarf-callsite-related-attrs.ll b/llvm/test/DebugInfo/X86/dwarf-callsite-related-attrs.ll index b49f7b5fdb0c6..02cb98c9da0e5 100644 --- a/llvm/test/DebugInfo/X86/dwarf-callsite-related-attrs.ll +++ b/llvm/test/DebugInfo/X86/dwarf-callsite-related-attrs.ll @@ -12,8 +12,8 @@ ; and fail with "failed to compute relocation: IMAGE_REL_AMD64_ADDR32". ; UNSUPPORTED: cygwin,windows-gnu,windows-msvc -; RUN: %llc_dwarf -mtriple=x86_64-- < %s -o - | FileCheck %s -check-prefix=ASM -; RUN: %llc_dwarf -debugger-tune=lldb -mtriple=x86_64-- < %s -filetype=obj -o %t.o +; RUN: llc -mtriple=x86_64 < %s -o - | FileCheck %s -check-prefix=ASM +; RUN: llc -mtriple=x86_64 -debugger-tune=lldb < %s -filetype=obj -o %t.o ; RUN: llvm-dwarfdump %t.o -o - | FileCheck %s -check-prefix=OBJ -implicit-check-not=DW_TAG_call -implicit-check-not=DW_AT_call ; RUN: llvm-dwarfdump -verify %t.o 2>&1 | FileCheck %s -check-prefix=VERIFY ; RUN: llvm-dwarfdump -statistics %t.o | FileCheck %s -check-prefix=STATS diff --git a/llvm/test/DebugInfo/X86/fission-ranges.ll b/llvm/test/DebugInfo/X86/fission-ranges.ll index bb6320f73f721..32a97763033d0 100644 --- a/llvm/test/DebugInfo/X86/fission-ranges.ll +++ b/llvm/test/DebugInfo/X86/fission-ranges.ll @@ -45,31 +45,31 @@ ; if they've changed due to a bugfix, change in register allocation, etc. ; CHECK: [[A]]: -; CHECK-NEXT: DW_LLE_startx_length (0x00000002, 0x0000000f): DW_OP_consts +0, DW_OP_stack_value -; CHECK-NEXT: DW_LLE_startx_length (0x00000003, 0x0000000b): DW_OP_reg0 RAX -; CHECK-NEXT: DW_LLE_startx_length (0x00000004, 0x00000012): DW_OP_breg7 RSP-4 +; CHECK-NEXT: DW_LLE_startx_length (0x00000001, 0x00000011): DW_OP_consts +0, DW_OP_stack_value +; CHECK-NEXT: DW_LLE_startx_length (0x00000002, 0x0000000b): DW_OP_reg0 RAX +; CHECK-NEXT: DW_LLE_startx_length (0x00000003, 0x00000012): DW_OP_breg7 RSP-4 ; CHECK-NEXT: DW_LLE_end_of_list () ; CHECK: [[E]]: -; CHECK-NEXT: DW_LLE_startx_length (0x00000005, 0x0000000b): DW_OP_reg0 RAX -; CHECK-NEXT: DW_LLE_startx_length (0x00000006, 0x0000005a): DW_OP_breg7 RSP-48 +; CHECK-NEXT: DW_LLE_startx_length (0x00000004, 0x0000000b): DW_OP_reg0 RAX +; CHECK-NEXT: DW_LLE_startx_length (0x00000005, 0x0000005a): DW_OP_breg7 RSP-48 ; CHECK-NEXT: DW_LLE_end_of_list () ; CHECK: [[B]]: -; CHECK-NEXT: DW_LLE_startx_length (0x00000007, 0x0000000b): DW_OP_reg0 RAX -; CHECK-NEXT: DW_LLE_startx_length (0x00000008, 0x00000042): DW_OP_breg7 RSP-24 +; CHECK-NEXT: DW_LLE_startx_length (0x00000006, 0x0000000b): DW_OP_reg0 RAX +; CHECK-NEXT: DW_LLE_startx_length (0x00000007, 0x00000042): DW_OP_breg7 RSP-24 ; CHECK-NEXT: DW_LLE_end_of_list () ; CHECK: [[D]]: -; CHECK-NEXT: DW_LLE_startx_length (0x00000009, 0x0000000b): DW_OP_reg0 RAX -; CHECK-NEXT: DW_LLE_startx_length (0x0000000a, 0x0000002a): DW_OP_breg7 RSP-12 +; CHECK-NEXT: DW_LLE_startx_length (0x00000008, 0x0000000b): DW_OP_reg0 RAX +; CHECK-NEXT: DW_LLE_startx_length (0x00000009, 0x0000002a): DW_OP_breg7 RSP-12 ; CHECK-NEXT: DW_LLE_end_of_list () ; Make sure we don't produce any relocations in any .dwo section (though in particular, debug_info.dwo) ; HDR-NOT: .rela.{{.*}}.dwo ; Make sure we have enough stuff in the debug_addr to cover the address indexes -; (10 is the last index in debug_loc.dwo, making 11 entries of 8 bytes each, -; 11 * 8 == 88 base 10 == 58 base 16) +; (9 is the last index in debug_loc.dwo, making 10 entries of 8 bytes each, +; 10 * 8 == 80 base 10 == 50 base 16) -; HDR: .debug_addr 00000058 +; HDR: .debug_addr 00000050 ; HDR-NOT: .rela.{{.*}}.dwo ; Check for the existence of a DWARF v5-style range list table in the .debug_rnglists diff --git a/llvm/test/DebugInfo/X86/gmlt-no-split-dwarf-inlining-empty.ll b/llvm/test/DebugInfo/X86/gmlt-no-split-dwarf-inlining-empty.ll index e540492eb1d59..d270c2784a23f 100644 --- a/llvm/test/DebugInfo/X86/gmlt-no-split-dwarf-inlining-empty.ll +++ b/llvm/test/DebugInfo/X86/gmlt-no-split-dwarf-inlining-empty.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -split-dwarf-file=foo.dwo %s -filetype=obj -o - | llvm-objdump -h - | FileCheck %s +; RUN: llc -split-dwarf-file=foo.dwo %s -filetype=obj -o - | llvm-objdump -h - | FileCheck %s ; Created from: ; void f1() { diff --git a/llvm/test/DebugInfo/X86/inline-namespace.ll b/llvm/test/DebugInfo/X86/inline-namespace.ll index ab53f6592dd91..fd600d6fb2046 100644 --- a/llvm/test/DebugInfo/X86/inline-namespace.ll +++ b/llvm/test/DebugInfo/X86/inline-namespace.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf %s -o - -filetype=obj | llvm-dwarfdump -v -debug-info - | FileCheck %s +; RUN: llc %s -o - -filetype=obj | llvm-dwarfdump -v -debug-info - | FileCheck %s ; Generated from: ; namespace normal { inline namespace inlined { int i; } } ; Check that an inline namespace is emitted with DW_AT_export_symbols diff --git a/llvm/test/DebugInfo/X86/live-debug-vars-nodebug.ll b/llvm/test/DebugInfo/X86/live-debug-vars-nodebug.ll new file mode 100644 index 0000000000000..35d05392209db --- /dev/null +++ b/llvm/test/DebugInfo/X86/live-debug-vars-nodebug.ll @@ -0,0 +1,101 @@ +; RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -stop-before=finalize-isel \ +; RUN: | FileCheck %s --check-prefix=NORMAL-INPUT + +; RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -stop-before=finalize-isel \ +; RUN: -experimental-debug-variable-locations \ +; RUN: | FileCheck %s --check-prefix=EXPER-INPUT + +; RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -stop-after=livedebugvars \ +; RUN: | FileCheck %s --check-prefix=OUTPUT + +; RUN: llc %s -mtriple=x86_64-unknown-unknown -o - -stop-after=livedebugvars \ +; RUN: -experimental-debug-variable-locations \ +; RUN: | FileCheck %s --check-prefix=OUTPUT + +; This test checks that LiveDebugVariables strips all debug instructions +; from nodebug functions. Such instructions occur when a function with debug +; info is inlined into a nodebug function. + +; The test first verifies that DBG_VALUE/DBG_LABEL instructions are present in +; the input to LiveDebugVariables. It then verifies that after the pass is ran +; no debug instructions are present. + +; When -experimental-debug-variable-locations is enabled, certain variable +; locations are represented by DBG_INSTR_REF instead of DBG_VALUE. The test +; verifies that a DBG_INSTR_REF is emitted by the option, and that it is also +; stripped. + +; Generated from: +; +; extern int foobar(); +; +; int bar(int a) { +; int b = 10; +; b += foobar(); +; label: +; if (a) goto label; +; return b; +; } +; +; __attribute__((nodebug)) +; int foo(int a) { +; return bar(a); +; } + +; NORMAL-INPUT-DAG: DBG_VALUE +; NORMAL-INPUT-DAG: DBG_LABEL + +; EXPER-INPUT-DAG: DBG_INSTR_REF +; EXPER-INPUT-DAG: DBG_LABEL + +; OUTPUT-NOT: DBG_VALUE +; OUTPUT-NOT: DBG_INSTR_REF +; OUTPUT-NOT: DBG_LABEL + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define dso_local i32 @_Z3fooi(i32 %a) local_unnamed_addr #0 { +entry: + call void @llvm.dbg.value(metadata i32 %a, metadata !12, metadata !DIExpression()), !dbg !15 + call void @llvm.dbg.value(metadata i32 10, metadata !13, metadata !DIExpression()), !dbg !15 + %call.i = tail call i32 @_Z6foobarv() + call void @llvm.dbg.value(metadata i32 undef, metadata !13, metadata !DIExpression()), !dbg !15 + %tobool.not.i = icmp eq i32 %a, 0 + br i1 %tobool.not.i, label %_Z3bari.exit, label %label.i + +label.i: ; preds = %entry, %label.i + call void @llvm.dbg.label(metadata !14), !dbg !18 + br label %label.i + +_Z3bari.exit: ; preds = %entry + %add.i = add nsw i32 %call.i, 10 + call void @llvm.dbg.value(metadata i32 %add.i, metadata !13, metadata !DIExpression()), !dbg !15 + ret i32 %add.i +} + +declare void @llvm.dbg.value(metadata, metadata, metadata) #2 +declare dso_local i32 @_Z6foobarv() local_unnamed_addr #1 +declare void @llvm.dbg.label(metadata) #2 + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5} +!llvm.ident = !{!6} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "f.cpp", directory: "") +!2 = !{} +!3 = !{i32 7, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{!"clang version 12.0.0"} +!7 = distinct !DISubprogram(name: "bar", linkageName: "_Z3bari", scope: !1, file: !1, line: 3, type: !8, scopeLine: 3, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !11) +!8 = !DISubroutineType(types: !9) +!9 = !{!10, !10} +!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!11 = !{!12, !13, !14} +!12 = !DILocalVariable(name: "a", arg: 1, scope: !7, file: !1, line: 3, type: !10) +!13 = !DILocalVariable(name: "b", scope: !7, file: !1, line: 4, type: !10) +!14 = !DILabel(scope: !7, name: "label", file: !1, line: 6) +!15 = !DILocation(line: 0, scope: !7) +!18 = !DILocation(line: 6, column: 1, scope: !7) diff --git a/llvm/test/DebugInfo/X86/noreturn_c11.ll b/llvm/test/DebugInfo/X86/noreturn_c11.ll index cfa7be7b19aa6..d1afaadc3b40e 100644 --- a/llvm/test/DebugInfo/X86/noreturn_c11.ll +++ b/llvm/test/DebugInfo/X86/noreturn_c11.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s +; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s ; Generated by clang -S -c -std=c++11 --emit-llvm -g from the following C11 source: ; _Noreturn void f() { diff --git a/llvm/test/DebugInfo/X86/noreturn_cpp11.ll b/llvm/test/DebugInfo/X86/noreturn_cpp11.ll index 422857b74b901..88c9b1e8db9ba 100644 --- a/llvm/test/DebugInfo/X86/noreturn_cpp11.ll +++ b/llvm/test/DebugInfo/X86/noreturn_cpp11.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s +; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s ; Generated by clang++ -S -c -std=c++11 --emit-llvm -g from the following C++11 source: ;class foo { diff --git a/llvm/test/DebugInfo/X86/noreturn_objc.ll b/llvm/test/DebugInfo/X86/noreturn_objc.ll index f9eac062dfbee..7fb2b186eb8f9 100644 --- a/llvm/test/DebugInfo/X86/noreturn_objc.ll +++ b/llvm/test/DebugInfo/X86/noreturn_objc.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s +; RUN: llc -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s ; Generated by clang++ -S -c --emit-llvm -g from the following ObjC source: ; #include diff --git a/llvm/test/DebugInfo/X86/parameters.ll b/llvm/test/DebugInfo/X86/parameters.ll index dafde9acceff2..2eff34a43c6e7 100644 --- a/llvm/test/DebugInfo/X86/parameters.ll +++ b/llvm/test/DebugInfo/X86/parameters.ll @@ -46,7 +46,7 @@ %"struct.pr14763::foo" = type { i8 } ; Function Attrs: uwtable -define void @_ZN7pr147634funcENS_3fooE(%"struct.pr14763::foo"* noalias sret %agg.result, %"struct.pr14763::foo"* %f) #0 !dbg !4 { +define void @_ZN7pr147634funcENS_3fooE(%"struct.pr14763::foo"* noalias sret(%"struct.pr14763::foo") %agg.result, %"struct.pr14763::foo"* %f) #0 !dbg !4 { entry: call void @llvm.dbg.declare(metadata %"struct.pr14763::foo"* %f, metadata !22, metadata !DIExpression(DW_OP_deref)), !dbg !24 call void @_ZN7pr147633fooC1ERKS0_(%"struct.pr14763::foo"* %agg.result, %"struct.pr14763::foo"* %f), !dbg !25 diff --git a/llvm/test/DebugInfo/X86/partial-constant.ll b/llvm/test/DebugInfo/X86/partial-constant.ll index 831d6165c0b3a..a610aa2c9d7a6 100644 --- a/llvm/test/DebugInfo/X86/partial-constant.ll +++ b/llvm/test/DebugInfo/X86/partial-constant.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj < %s | llvm-dwarfdump -v - | FileCheck %s +; RUN: llc -filetype=obj < %s | llvm-dwarfdump -v - | FileCheck %s ; Generated at -O2 from: ; bool c(); ; void f(); diff --git a/llvm/test/DebugInfo/X86/pieces-2.ll b/llvm/test/DebugInfo/X86/pieces-2.ll index 55ada6e472a48..80003a3f5e72e 100644 --- a/llvm/test/DebugInfo/X86/pieces-2.ll +++ b/llvm/test/DebugInfo/X86/pieces-2.ll @@ -29,7 +29,7 @@ target triple = "x86_64-apple-macosx10.9.0" %struct.Inner = type { i32, i64 } ; Function Attrs: nounwind ssp uwtable -define i32 @foo(%struct.Outer* byval align 8 %outer) #0 !dbg !4 { +define i32 @foo(%struct.Outer* byval(%struct.Outer) align 8 %outer) #0 !dbg !4 { entry: call void @llvm.dbg.declare(metadata %struct.Outer* %outer, metadata !25, metadata !DIExpression()), !dbg !26 %i1.sroa.0.0..sroa_idx = getelementptr inbounds %struct.Outer, %struct.Outer* %outer, i64 0, i32 0, i64 1, i32 0, !dbg !27 diff --git a/llvm/test/DebugInfo/X86/safestack-byval.ll b/llvm/test/DebugInfo/X86/safestack-byval.ll index a653cd78b91d1..7e4d9fc5ab5f2 100644 --- a/llvm/test/DebugInfo/X86/safestack-byval.ll +++ b/llvm/test/DebugInfo/X86/safestack-byval.ll @@ -21,7 +21,7 @@ @__safestack_unsafe_stack_ptr = external thread_local(initialexec) global i8* ; Function Attrs: norecurse nounwind readonly safestack uwtable -define i32 @_Z1f1Sm(%struct.S* byval nocapture readonly align 8 %zzz, i64 %len) #0 !dbg !12 { +define i32 @_Z1f1Sm(%struct.S* byval(%struct.S) nocapture readonly align 8 %zzz, i64 %len) #0 !dbg !12 { entry: %unsafe_stack_ptr = load i8*, i8** @__safestack_unsafe_stack_ptr, !dbg !22 %unsafe_stack_static_top = getelementptr i8, i8* %unsafe_stack_ptr, i32 -400, !dbg !22 diff --git a/llvm/test/DebugInfo/X86/single-dbg_value.ll b/llvm/test/DebugInfo/X86/single-dbg_value.ll index d98b872f38df6..102d96d0e0a4f 100644 --- a/llvm/test/DebugInfo/X86/single-dbg_value.ll +++ b/llvm/test/DebugInfo/X86/single-dbg_value.ll @@ -1,6 +1,6 @@ -; RUN: %llc_dwarf -stop-after=livedebugvalues -o - %s \ +; RUN: llc -stop-after=livedebugvalues -o - %s \ ; RUN: | FileCheck %s --check-prefix=SANITY -; RUN: %llc_dwarf -march=x86-64 -o - %s -filetype=obj \ +; RUN: llc -march=x86-64 -o - %s -filetype=obj \ ; RUN: | llvm-dwarfdump -v -all - | FileCheck %s ; ; CHECK: .debug_info contents: diff --git a/llvm/test/DebugInfo/X86/spill-indirect-nrvo.ll b/llvm/test/DebugInfo/X86/spill-indirect-nrvo.ll index fb0c5779ca8bb..aa2490ecb46ab 100644 --- a/llvm/test/DebugInfo/X86/spill-indirect-nrvo.ll +++ b/llvm/test/DebugInfo/X86/spill-indirect-nrvo.ll @@ -44,7 +44,7 @@ target triple = "x86_64--linux" %struct.string = type { i32 } ; Function Attrs: uwtable -define void @_Z10get_stringv(%struct.string* noalias sret %agg.result) #0 !dbg !7 { +define void @_Z10get_stringv(%struct.string* noalias sret(%struct.string) %agg.result) #0 !dbg !7 { entry: %nrvo = alloca i1, align 1 store i1 false, i1* %nrvo, align 1, !dbg !24 diff --git a/llvm/test/DebugInfo/X86/split-dwarf-multiple-cu-hash.ll b/llvm/test/DebugInfo/X86/split-dwarf-multiple-cu-hash.ll index 3a69c0f25ea03..89c2c8c07e4b9 100644 --- a/llvm/test/DebugInfo/X86/split-dwarf-multiple-cu-hash.ll +++ b/llvm/test/DebugInfo/X86/split-dwarf-multiple-cu-hash.ll @@ -1,6 +1,6 @@ ; RUN: rm -rf %t && mkdir -p %t -; RUN: %llc_dwarf -split-dwarf-file=foo.dwo %s -filetype=obj -o %t/a.o -; RUN: %llc_dwarf -split-dwarf-file=bar.dwo %s -filetype=obj -o %t/b.o +; RUN: llc -split-dwarf-file=foo.dwo %s -filetype=obj -o %t/a.o +; RUN: llc -split-dwarf-file=bar.dwo %s -filetype=obj -o %t/b.o ; RUN: llvm-dwarfdump -debug-info %t/a.o %t/b.o | FileCheck %s ; CHECK: .debug_info contents: diff --git a/llvm/test/DebugInfo/X86/split-dwarf-omit-empty.ll b/llvm/test/DebugInfo/X86/split-dwarf-omit-empty.ll index 5d727f7a2539d..f4cee1ec78b1d 100644 --- a/llvm/test/DebugInfo/X86/split-dwarf-omit-empty.ll +++ b/llvm/test/DebugInfo/X86/split-dwarf-omit-empty.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -split-dwarf-file=foo.dwo %s -filetype=obj -o - | llvm-dwarfdump -debug-info - | FileCheck %s +; RUN: llc -split-dwarf-file=foo.dwo %s -filetype=obj -o - | llvm-dwarfdump -debug-info - | FileCheck %s ; Created from: ; a.cpp: diff --git a/llvm/test/DebugInfo/X86/split-dwarf-sysroot.ll b/llvm/test/DebugInfo/X86/split-dwarf-sysroot.ll index be61ff72380c7..453a3109a65c7 100644 --- a/llvm/test/DebugInfo/X86/split-dwarf-sysroot.ll +++ b/llvm/test/DebugInfo/X86/split-dwarf-sysroot.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -split-dwarf-file=foo.dwo %s -filetype=obj -o - | llvm-dwarfdump -debug-info - | FileCheck %s +; RUN: llc -split-dwarf-file=foo.dwo %s -filetype=obj -o - | llvm-dwarfdump -debug-info - | FileCheck %s ; DW_AT_LLVM_sysroot goes into the .dwo, not in the skeleton. diff --git a/llvm/test/DebugInfo/X86/sret.ll b/llvm/test/DebugInfo/X86/sret.ll index 59d98866e0912..479f2f605421a 100644 --- a/llvm/test/DebugInfo/X86/sret.ll +++ b/llvm/test/DebugInfo/X86/sret.ll @@ -101,7 +101,7 @@ entry: } ; Function Attrs: uwtable -define void @_ZN1B9AInstanceEv(%class.A* noalias sret %agg.result, %class.B* %this) #2 align 2 !dbg !53 { +define void @_ZN1B9AInstanceEv(%class.A* noalias sret(%class.A) %agg.result, %class.B* %this) #2 align 2 !dbg !53 { entry: %this.addr = alloca %class.B*, align 8 %nrvo = alloca i1 @@ -156,7 +156,7 @@ entry: call void @llvm.dbg.declare(metadata %class.B* %b, metadata !107, metadata !DIExpression()), !dbg !108 call void @_ZN1BC2Ev(%class.B* %b), !dbg !108 call void @llvm.dbg.declare(metadata i32* %return_val, metadata !109, metadata !DIExpression()), !dbg !110 - call void @_ZN1B9AInstanceEv(%class.A* sret %temp.lvalue, %class.B* %b), !dbg !110 + call void @_ZN1B9AInstanceEv(%class.A* sret(%class.A) %temp.lvalue, %class.B* %b), !dbg !110 %call = invoke i32 @_ZN1A7get_intEv(%class.A* %temp.lvalue) to label %invoke.cont unwind label %lpad, !dbg !110 @@ -164,7 +164,7 @@ invoke.cont: ; preds = %entry call void @_ZN1AD2Ev(%class.A* %temp.lvalue), !dbg !111 store i32 %call, i32* %return_val, align 4, !dbg !111 call void @llvm.dbg.declare(metadata %class.A* %a, metadata !113, metadata !DIExpression()), !dbg !114 - call void @_ZN1B9AInstanceEv(%class.A* sret %a, %class.B* %b), !dbg !114 + call void @_ZN1B9AInstanceEv(%class.A* sret(%class.A) %a, %class.B* %b), !dbg !114 %0 = load i32, i32* %return_val, align 4, !dbg !115 store i32 %0, i32* %retval, !dbg !115 store i32 1, i32* %cleanup.dest.slot diff --git a/llvm/test/DebugInfo/X86/sroasplit-1.ll b/llvm/test/DebugInfo/X86/sroasplit-1.ll index 2372ab6428c53..0ec368130da28 100644 --- a/llvm/test/DebugInfo/X86/sroasplit-1.ll +++ b/llvm/test/DebugInfo/X86/sroasplit-1.ll @@ -34,7 +34,7 @@ target triple = "x86_64-apple-macosx10.9.0" %struct.Inner = type { i32, i64 } ; Function Attrs: nounwind ssp uwtable -define i32 @foo(%struct.Outer* byval align 8 %outer) #0 !dbg !4 { +define i32 @foo(%struct.Outer* byval(%struct.Outer) align 8 %outer) #0 !dbg !4 { entry: %i1 = alloca %struct.Inner, align 8 call void @llvm.dbg.declare(metadata %struct.Outer* %outer, metadata !25, metadata !2), !dbg !26 diff --git a/llvm/test/DebugInfo/X86/sroasplit-4.ll b/llvm/test/DebugInfo/X86/sroasplit-4.ll index 6e47cb7d86928..0d5594ef867dd 100644 --- a/llvm/test/DebugInfo/X86/sroasplit-4.ll +++ b/llvm/test/DebugInfo/X86/sroasplit-4.ll @@ -78,7 +78,7 @@ if.end: ; preds = %entry %4 = bitcast %struct.r* %agg.tmp to i8*, !dbg !33 %5 = bitcast %struct.r* %r to i8*, !dbg !33 call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %4, i8* align 8 %5, i64 40, i1 false), !dbg !33 - %call4 = call i32 @_Z7call_me1r(%struct.r* byval align 8 %agg.tmp), !dbg !33 + %call4 = call i32 @_Z7call_me1r(%struct.r* byval(%struct.r) align 8 %agg.tmp), !dbg !33 store i32 %call4, i32* %retval, !dbg !33 br label %return, !dbg !33 @@ -95,7 +95,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) #2 ; Function Attrs: nounwind declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) #3 -declare i32 @_Z7call_me1r(%struct.r* byval align 8) +declare i32 @_Z7call_me1r(%struct.r* byval(%struct.r) align 8) attributes #0 = { nounwind } attributes #2 = { nounwind readnone } diff --git a/llvm/test/DebugInfo/X86/static_member_array.ll b/llvm/test/DebugInfo/X86/static_member_array.ll index 128478d55f032..1795a4284b69c 100644 --- a/llvm/test/DebugInfo/X86/static_member_array.ll +++ b/llvm/test/DebugInfo/X86/static_member_array.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf %s -filetype=obj -o - | llvm-dwarfdump -v -debug-info - | FileCheck %s +; RUN: llc %s -filetype=obj -o - | llvm-dwarfdump -v -debug-info - | FileCheck %s ; Generated from: ; ; struct A { diff --git a/llvm/test/DebugInfo/X86/unattached-global.ll b/llvm/test/DebugInfo/X86/unattached-global.ll index 5e9af695c8dc0..343f3a74df43a 100644 --- a/llvm/test/DebugInfo/X86/unattached-global.ll +++ b/llvm/test/DebugInfo/X86/unattached-global.ll @@ -1,4 +1,4 @@ -; RUN: %llc_dwarf -filetype=obj -o - %s | llvm-dwarfdump - | FileCheck %s +; RUN: llc -filetype=obj -o - %s | llvm-dwarfdump - | FileCheck %s target datalayout = "e-p:64:64" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Feature/callingconventions.ll b/llvm/test/Feature/callingconventions.ll index ac4c5090a51d6..ea30a8e7f4d16 100644 --- a/llvm/test/Feature/callingconventions.ll +++ b/llvm/test/Feature/callingconventions.ll @@ -11,8 +11,8 @@ define coldcc void @bar() { ret void } -define void @structret({ i8 }* sret %P) { - call void @structret( { i8 }* sret %P ) +define void @structret({ i8 }* sret({ i8 }) %P) { + call void @structret( { i8 }* sret({ i8 }) %P ) ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll index 616c18ea09d60..986dfcb519801 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll @@ -18,7 +18,7 @@ declare i32 @bar(%struct.A*) ; Test behavior for named argument with explicit alignment. The memcpy and ; alloca alignments should match the explicit alignment of 64. -define void @foo(%struct.A* byval align 64 %a) sanitize_address { +define void @foo(%struct.A* byval(%struct.A) align 64 %a) sanitize_address { entry: ; CHECK-LABEL: foo ; CHECK: call i64 @__asan_stack_malloc @@ -39,7 +39,7 @@ entry: ; minimum alignment of 4 bytes since struct.A contains i32s which have 4-byte ; alignment. However, the alloca alignment will be 32 since that is the value ; passed via the -asan-realign-stack option, which is greater than 4. -define void @baz(%struct.A* byval) sanitize_address { +define void @baz(%struct.A* byval(%struct.A)) sanitize_address { entry: ; CHECK-LABEL: baz ; CHECK: call i64 @__asan_stack_malloc diff --git a/llvm/test/Instrumentation/BoundsChecking/simple.ll b/llvm/test/Instrumentation/BoundsChecking/simple.ll index c95bfbdd4fe95..994a5dc22717e 100644 --- a/llvm/test/Instrumentation/BoundsChecking/simple.ll +++ b/llvm/test/Instrumentation/BoundsChecking/simple.ll @@ -133,7 +133,7 @@ define void @f10(i64 %x, i64 %y) nounwind { } ; CHECK: @f11 -define void @f11(i128* byval %x) nounwind { +define void @f11(i128* byval(i128) %x) nounwind { %1 = bitcast i128* %x to i8* %2 = getelementptr inbounds i8, i8* %1, i64 16 ; CHECK: br label @@ -142,7 +142,7 @@ define void @f11(i128* byval %x) nounwind { } ; CHECK: @f11_as1 -define void @f11_as1(i128 addrspace(1)* byval %x) nounwind { +define void @f11_as1(i128 addrspace(1)* byval(i128) %x) nounwind { %1 = bitcast i128 addrspace(1)* %x to i8 addrspace(1)* %2 = getelementptr inbounds i8, i8 addrspace(1)* %1, i16 16 ; CHECK: br label diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll index 33f3d82c3683d..4c68d4439a699 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll @@ -77,7 +77,7 @@ define i32 @bar5() { ; Check 8-aligned byval. define i32 @bar6([2 x i64]* %arg) { - %1 = call i32 (i32, ...) @foo(i32 0, [2 x i64]* byval align 8 %arg) + %1 = call i32 (i32, ...) @foo(i32 0, [2 x i64]* byval([2 x i64]) align 8 %arg) ret i32 %1 } @@ -87,7 +87,7 @@ define i32 @bar6([2 x i64]* %arg) { ; Check 16-aligned byval. define i32 @bar7([4 x i64]* %arg) { - %1 = call i32 (i32, ...) @foo(i32 0, [4 x i64]* byval align 16 %arg) + %1 = call i32 (i32, ...) @foo(i32 0, [4 x i64]* byval([4 x i64]) align 16 %arg) ret i32 %1 } diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll index ac8df55fee486..87b429aa5ef9f 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll @@ -76,7 +76,7 @@ define i32 @bar5() { ; Check 8-aligned byval. define i32 @bar6([2 x i64]* %arg) { - %1 = call i32 (i32, ...) @foo(i32 0, [2 x i64]* byval align 8 %arg) + %1 = call i32 (i32, ...) @foo(i32 0, [2 x i64]* byval([2 x i64]) align 8 %arg) ret i32 %1 } @@ -86,7 +86,7 @@ define i32 @bar6([2 x i64]* %arg) { ; Check 16-aligned byval. define i32 @bar7([4 x i64]* %arg) { - %1 = call i32 (i32, ...) @foo(i32 0, [4 x i64]* byval align 16 %arg) + %1 = call i32 (i32, ...) @foo(i32 0, [4 x i64]* byval([4 x i64]) align 16 %arg) ret i32 %1 } diff --git a/llvm/test/Instrumentation/MemorySanitizer/byval-alignment.ll b/llvm/test/Instrumentation/MemorySanitizer/byval-alignment.ll index acf9c27fb5be5..71db2356ac295 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/byval-alignment.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/byval-alignment.ll @@ -14,8 +14,8 @@ target triple = "x86_64-unknown-linux-gnu" define void @Caller() sanitize_memory { entry: %agg.tmp = alloca %struct.S, align 16 - call void @Callee(i32 1, %struct.S* byval align 16 %agg.tmp) + call void @Callee(i32 1, %struct.S* byval(%struct.S) align 16 %agg.tmp) ret void } -declare void @Callee(i32, %struct.S* byval align 16) +declare void @Callee(i32, %struct.S* byval(%struct.S) align 16) diff --git a/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll b/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll index c4c295c797261..d69d898369e0e 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll @@ -8,7 +8,7 @@ target triple = "x86_64-unknown-linux-gnu" ; Test byval argument shadow alignment -define <2 x i64> @ByValArgumentShadowLargeAlignment(<2 x i64>* byval %p) sanitize_memory { +define <2 x i64> @ByValArgumentShadowLargeAlignment(<2 x i64>* byval(<2 x i64>) %p) sanitize_memory { entry: %x = load <2 x i64>, <2 x i64>* %p ret <2 x i64> %x @@ -19,7 +19,7 @@ entry: ; CHECK: ret <2 x i64> -define i16 @ByValArgumentShadowSmallAlignment(i16* byval %p) sanitize_memory { +define i16 @ByValArgumentShadowSmallAlignment(i16* byval(i16) %p) sanitize_memory { entry: %x = load i16, i16* %p ret i16 %x diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll index 6abdb4486a499..6a33b398ef6e1 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll @@ -94,7 +94,7 @@ declare void @foo(...) ; CHECK-ORIGINS: %[[ORIGIN:.*]] = load ; CHECK: call void @__msan_warning_with_origin_noreturn(i32 ; CHECK-ORIGINS-SAME %[[ORIGIN]]) -; CHECK-CONT: +; CHECK-CONT: ; CHECK-NEXT: unreachable ; CHECK: br i1 %tobool ; CHECK: ret void @@ -920,7 +920,7 @@ entry: %agg.tmp.sroa.2.0.copyload = load i64, i64* %agg.tmp.sroa.2.0..sroa_cast, align 4 %1 = bitcast %struct.StructByVal* %agg.tmp2 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %1, i8* align 4 %0, i64 16, i1 false) - call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval align 8 %agg.tmp2) + call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval(%struct.StructByVal) align 8 %agg.tmp2) ret void } @@ -955,7 +955,7 @@ entry: %agg.tmp.sroa.2.0.copyload = load i64, i64* %agg.tmp.sroa.2.0..sroa_cast, align 4 %1 = bitcast %struct.StructByVal* %agg.tmp2 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %1, i8* align 4 %0, i64 16, i1 false) - call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval align 8 %agg.tmp2) + call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval(%struct.StructByVal) align 8 %agg.tmp2) ret void } diff --git a/llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll b/llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll index bb60145709b54..096b1011e55f0 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll @@ -9,6 +9,7 @@ target triple = "x86_64-unknown-linux-gnu" declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone declare <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double>, i32) nounwind readnone declare x86_mmx @llvm.x86.sse.cvtps2pi(<4 x float>) nounwind readnone +declare i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float>, i32) nounwind readnone ; Single argument vector conversion. @@ -45,3 +46,20 @@ entry: ; CHECK: call x86_mmx @llvm.x86.sse.cvtps2pi ; CHECK: store i64 0, {{.*}} @__msan_retval_tls ; CHECK: ret x86_mmx + +; avx512 rounding conversion. + +define i32 @pr48298(<4 x float> %value) sanitize_memory { +entry: + %0 = tail call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> %value, i32 11) + ret i32 %0 +} + +; CHECK-LABEL: @pr48298 +; CHECK: extractelement <4 x i32> {{.*}}, i32 0 +; CHECK: icmp ne i32 {{.*}}, 0 +; CHECK: br +; CHECK: call void @__msan_warning_with_origin_noreturn +; CHECK: call i32 @llvm.x86.avx512.vcvtss2usi32 +; CHECK: store i32 0, {{.*}} @__msan_retval_tls +; CHECK: ret i32 diff --git a/llvm/test/Linker/func-attrs-a.ll b/llvm/test/Linker/func-attrs-a.ll index d5495e1e3fdc1..55b27aae79f6a 100644 --- a/llvm/test/Linker/func-attrs-a.ll +++ b/llvm/test/Linker/func-attrs-a.ll @@ -1,13 +1,13 @@ ; RUN: llvm-link %s %p/func-attrs-b.ll -S -o - | FileCheck %s ; PR2382 -; CHECK: call void @check0(%struct.S0* sret null, %struct.S0* byval align 4 null, %struct.S0* align 4 null, %struct.S0* byval align 4 null) -; CHECK: define void @check0(%struct.S0* sret %agg.result, %struct.S0* byval %arg0, %struct.S0* %arg1, %struct.S0* byval %arg2) +; CHECK: call void @check0(%struct.S0* sret(%struct.S0) null, %struct.S0* byval(%struct.S0) align 4 null, %struct.S0* align 4 null, %struct.S0* byval(%struct.S0) align 4 null) +; CHECK: define void @check0(%struct.S0* sret(%struct.S0) %agg.result, %struct.S0* byval(%struct.S0) %arg0, %struct.S0* %arg1, %struct.S0* byval(%struct.S0) %arg2) %struct.S0 = type <{ i8, i8, i8, i8 }> define void @a() { - call void @check0(%struct.S0* sret null, %struct.S0* byval align 4 null, %struct.S0* align 4 null, %struct.S0* byval align 4 null) + call void @check0(%struct.S0* sret(%struct.S0) null, %struct.S0* byval(%struct.S0) align 4 null, %struct.S0* align 4 null, %struct.S0* byval(%struct.S0) align 4 null) ret void } diff --git a/llvm/test/Linker/func-attrs-b.ll b/llvm/test/Linker/func-attrs-b.ll index df78e5f54ab7b..beb373207c1bb 100644 --- a/llvm/test/Linker/func-attrs-b.ll +++ b/llvm/test/Linker/func-attrs-b.ll @@ -3,6 +3,6 @@ %struct.S0 = type <{ i8, i8, i8, i8 }> -define void @check0(%struct.S0* sret %agg.result, %struct.S0* byval %arg0, %struct.S0* %arg1, %struct.S0* byval %arg2) { +define void @check0(%struct.S0* sret(%struct.S0) %agg.result, %struct.S0* byval(%struct.S0) %arg0, %struct.S0* %arg1, %struct.S0* byval(%struct.S0) %arg2) { ret void } diff --git a/llvm/test/MC/AArch64/armv8.2a-dotprod.s b/llvm/test/MC/AArch64/armv8.2a-dotprod.s index 3b9f416a63fb6..79ced55d68eb4 100644 --- a/llvm/test/MC/AArch64/armv8.2a-dotprod.s +++ b/llvm/test/MC/AArch64/armv8.2a-dotprod.s @@ -9,6 +9,7 @@ // RUN: llvm-mc -triple aarch64 -mcpu=cortex-x1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD // RUN: llvm-mc -triple aarch64 -mcpu=neoverse-e1 -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD // RUN: llvm-mc -triple aarch64 -mcpu=neoverse-n1 -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD +// RUN: llvm-mc -triple aarch64 -mcpu=neoverse-n2 -show-encoding < %s| FileCheck %s --check-prefix=CHECK-DOTPROD // RUN: llvm-mc -triple aarch64 -mcpu=tsv110 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD // RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t @@ -27,6 +28,8 @@ // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s // RUN: not llvm-mc -triple aarch64 -mcpu=neoverse-n1 -mattr=-dotprod -show-encoding < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s +// RUN: not llvm-mc -triple aarch64 -mcpu=neoverse-n2 -mattr=-dotprod -show-encoding < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s udot v0.2s, v1.8b, v2.8b sdot v0.2s, v1.8b, v2.8b diff --git a/llvm/test/MC/AArch64/armv8.3a-rcpc.s b/llvm/test/MC/AArch64/armv8.3a-rcpc.s index f38161ee21e85..1660cc4c75043 100644 --- a/llvm/test/MC/AArch64/armv8.3a-rcpc.s +++ b/llvm/test/MC/AArch64/armv8.3a-rcpc.s @@ -5,6 +5,7 @@ // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=cortex-a55 < %s 2>&1 | FileCheck %s // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-e1 < %s 2>&1 | FileCheck %s // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n1 < %s 2>&1 | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mcpu=neoverse-n2 < %s 2>&1 | FileCheck %s // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a -mattr=+rcpc < %s 2>&1 | FileCheck %s // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-REQ %s < %t diff --git a/llvm/test/MC/AArch64/armv8.5a-ssbs.s b/llvm/test/MC/AArch64/armv8.5a-ssbs.s index 81f1a48a1a4f6..ec6670f8ecc34 100644 --- a/llvm/test/MC/AArch64/armv8.5a-ssbs.s +++ b/llvm/test/MC/AArch64/armv8.5a-ssbs.s @@ -6,6 +6,7 @@ // RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=cortex-a76ae < %s | FileCheck %s // RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=neoverse-e1 < %s | FileCheck %s // RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=neoverse-n1 < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64 -show-encoding -mcpu=neoverse-n2 < %s | FileCheck %s // RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-ssbs < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID mrs x2, SSBS diff --git a/llvm/test/MC/AMDGPU/expressions-gfx10.s b/llvm/test/MC/AMDGPU/expressions-gfx10.s index 643001b18f463..ab8bdd11ec6fa 100644 --- a/llvm/test/MC/AMDGPU/expressions-gfx10.s +++ b/llvm/test/MC/AMDGPU/expressions-gfx10.s @@ -64,10 +64,10 @@ s_sub_u32 s0, u, u1 // NOGFX10: error: only one literal operand is allowed v_bfe_u32 v0, v2, 123, u -// NOGFX10: error: invalid literal operand +// NOGFX10: error: only one literal operand is allowed v_bfe_u32 v0, v2, u, u -// NOGFX10: error: invalid literal operand +// NOGFX10: error: only one literal operand is allowed v_bfe_u32 v0, v2, u, u1 -// NOGFX10: error: invalid literal operand +// NOGFX10: error: only one literal operand is allowed diff --git a/llvm/test/MC/AMDGPU/expressions-gfx9.s b/llvm/test/MC/AMDGPU/expressions-gfx9.s index 5419c8ed5cb9f..1305d9eb4d9cb 100644 --- a/llvm/test/MC/AMDGPU/expressions-gfx9.s +++ b/llvm/test/MC/AMDGPU/expressions-gfx9.s @@ -23,7 +23,7 @@ s_sub_u32 s0, u, u1 // NOGFX9: error: only one literal operand is allowed v_bfe_u32 v0, v2, v3, u -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported //===----------------------------------------------------------------------===// // Constant expressions may be used with 'sext' modifier diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s b/llvm/test/MC/AMDGPU/gfx10_err_pos.s index c09de27811358..c1aa9f860b5ca 100644 --- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s +++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s @@ -6,7 +6,22 @@ v_mqsad_pk_u16_u8 v[0:1], v[1:2], v9, v[4:5] // CHECK: error: destination must be different than all sources // CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[1:2], v9, v[4:5] -// CHECK-NEXT:{{^}}^ +// CHECK-NEXT:{{^}} ^ + +v_mqsad_pk_u16_u8 v[0:1], v[2:3], v0, v[4:5] +// CHECK: error: destination must be different than all sources +// CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[2:3], v0, v[4:5] +// CHECK-NEXT:{{^}} ^ + +v_mqsad_pk_u16_u8 v[0:1], v[2:3], v1, v[4:5] +// CHECK: error: destination must be different than all sources +// CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[2:3], v1, v[4:5] +// CHECK-NEXT:{{^}} ^ + +v_mqsad_pk_u16_u8 v[0:1], v[2:3], v9, v[0:1] +// CHECK: error: destination must be different than all sources +// CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[2:3], v9, v[0:1] +// CHECK-NEXT:{{^}} ^ //============================================================================== // dim modifier is required on this GPU @@ -545,24 +560,6 @@ v_dot_f32_f16 v0, v1, v2 // CHECK-NEXT:{{^}}v_dot_f32_f16 v0, v1, v2 // CHECK-NEXT:{{^}}^ -//============================================================================== -// invalid literal operand - -v_add_f64 v[0:1], 1.23456, -abs(1.2345) -// CHECK: error: invalid literal operand -// CHECK-NEXT:{{^}}v_add_f64 v[0:1], 1.23456, -abs(1.2345) -// CHECK-NEXT:{{^}}^ - -v_min3_i16 v5, 0x5678, 0x5678, 0x5679 -// CHECK: error: invalid literal operand -// CHECK-NEXT:{{^}}v_min3_i16 v5, 0x5678, 0x5678, 0x5679 -// CHECK-NEXT:{{^}}^ - -v_pk_add_f16 v1, 25.0, 25.1 -// CHECK: error: invalid literal operand -// CHECK-NEXT:{{^}}v_pk_add_f16 v1, 25.0, 25.1 -// CHECK-NEXT:{{^}}^ - //============================================================================== // invalid mask @@ -622,17 +619,42 @@ v_pk_add_u16 v1, v2, v3 op_sel:[-1,0] v_ashrrev_i64 v[0:1], 0x100, s[0:1] // CHECK: error: invalid operand (violates constant bus restrictions) // CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], 0x100, s[0:1] -// CHECK-NEXT:{{^}}^ +// CHECK-NEXT:{{^}} ^ + +v_ashrrev_i64 v[0:1], s3, s[0:1] +// CHECK: error: invalid operand (violates constant bus restrictions) +// CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], s3, s[0:1] +// CHECK-NEXT:{{^}} ^ v_bfe_u32 v0, s1, 0x3039, s2 // CHECK: error: invalid operand (violates constant bus restrictions) // CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, 0x3039, s2 -// CHECK-NEXT:{{^}}^ +// CHECK-NEXT:{{^}} ^ + +v_bfe_u32 v0, s1, s2, s3 +// CHECK: error: invalid operand (violates constant bus restrictions) +// CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, s2, s3 +// CHECK-NEXT:{{^}} ^ v_div_fmas_f32 v5, s3, 0x123, v3 // CHECK: error: invalid operand (violates constant bus restrictions) // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, 0x123, v3 -// CHECK-NEXT:{{^}}^ +// CHECK-NEXT:{{^}} ^ + +v_div_fmas_f32 v5, s3, v3, 0x123 +// CHECK: error: invalid operand (violates constant bus restrictions) +// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, v3, 0x123 +// CHECK-NEXT:{{^}} ^ + +v_div_fmas_f32 v5, 0x123, v3, s3 +// CHECK: error: invalid operand (violates constant bus restrictions) +// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, 0x123, v3, s3 +// CHECK-NEXT:{{^}} ^ + +v_div_fmas_f32 v5, s3, s4, v3 +// CHECK: error: invalid operand (violates constant bus restrictions) +// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, s4, v3 +// CHECK-NEXT:{{^}} ^ //============================================================================== // invalid operand for instruction @@ -777,7 +799,47 @@ v_mov_b32 v0, v0 row_bcast:0 s_and_b32 s2, 0x12345678, 0x12345679 // CHECK: error: only one literal operand is allowed // CHECK-NEXT:{{^}}s_and_b32 s2, 0x12345678, 0x12345679 -// CHECK-NEXT:{{^}}^ +// CHECK-NEXT:{{^}} ^ + +v_add_f64 v[0:1], 1.23456, -abs(1.2345) +// CHECK: error: only one literal operand is allowed +// CHECK-NEXT:{{^}}v_add_f64 v[0:1], 1.23456, -abs(1.2345) +// CHECK-NEXT:{{^}} ^ + +v_min3_i16 v5, 0x5678, 0x5678, 0x5679 +// CHECK: error: only one literal operand is allowed +// CHECK-NEXT:{{^}}v_min3_i16 v5, 0x5678, 0x5678, 0x5679 +// CHECK-NEXT:{{^}} ^ + +v_pk_add_f16 v1, 25.0, 25.1 +// CHECK: error: only one literal operand is allowed +// CHECK-NEXT:{{^}}v_pk_add_f16 v1, 25.0, 25.1 +// CHECK-NEXT:{{^}} ^ + +v_fma_mix_f32 v5, 0x7c, 0x7b, 1 +// CHECK: error: only one literal operand is allowed +// CHECK-NEXT:{{^}}v_fma_mix_f32 v5, 0x7c, 0x7b, 1 +// CHECK-NEXT:{{^}} ^ + +v_pk_add_i16 v5, 0x7c, 0x4000 +// CHECK: error: only one literal operand is allowed +// CHECK-NEXT:{{^}}v_pk_add_i16 v5, 0x7c, 0x4000 +// CHECK-NEXT:{{^}} ^ + +v_pk_add_i16 v5, 0x4400, 0x4000 +// CHECK: error: only one literal operand is allowed +// CHECK-NEXT:{{^}}v_pk_add_i16 v5, 0x4400, 0x4000 +// CHECK-NEXT:{{^}} ^ + +v_bfe_u32 v0, v2, 123, undef +// CHECK: error: only one literal operand is allowed +// CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, 123, undef +// CHECK-NEXT:{{^}} ^ + +v_bfe_u32 v0, v2, undef, 123 +// CHECK: error: only one literal operand is allowed +// CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, undef, 123 +// CHECK-NEXT:{{^}} ^ //============================================================================== // out of bounds attr diff --git a/llvm/test/MC/AMDGPU/gfx7_err_pos.s b/llvm/test/MC/AMDGPU/gfx7_err_pos.s index 00146b0b11e17..531c75084831e 100644 --- a/llvm/test/MC/AMDGPU/gfx7_err_pos.s +++ b/llvm/test/MC/AMDGPU/gfx7_err_pos.s @@ -17,9 +17,9 @@ v_add_co_u32 v84, s[4:5], v13, v31 clamp // CHECK-NEXT:{{^}} ^ //============================================================================== -// invalid literal operand +// literal operands are not supported v_and_b32_e64 v0, 0.159154943091895317852646485335, v1 -// CHECK: error: invalid literal operand +// CHECK: error: literal operands are not supported // CHECK-NEXT:{{^}}v_and_b32_e64 v0, 0.159154943091895317852646485335, v1 -// CHECK-NEXT:{{^}}^ +// CHECK-NEXT:{{^}} ^ diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_all.s b/llvm/test/MC/AMDGPU/gfx8_asm_all.s index 1362a4f871b2d..d4142d922993d 100644 --- a/llvm/test/MC/AMDGPU/gfx8_asm_all.s +++ b/llvm/test/MC/AMDGPU/gfx8_asm_all.s @@ -31646,10 +31646,10 @@ v_cvt_f16_u16_e64 v5, -1 // CHECK: [0x05,0x00,0x79,0xd1,0xc1,0x00,0x00,0x00] v_cvt_f16_u16_e64 v5, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cvt_f16_u16_e64 v5, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cvt_f16_u16_e64 v5, v1 clamp // CHECK: [0x05,0x80,0x79,0xd1,0x01,0x01,0x00,0x00] @@ -31781,10 +31781,10 @@ v_cvt_f16_i16_e64 v5, -1 // CHECK: [0x05,0x00,0x7a,0xd1,0xc1,0x00,0x00,0x00] v_cvt_f16_i16_e64 v5, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cvt_f16_i16_e64 v5, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cvt_f16_i16_e64 v5, v1 clamp // CHECK: [0x05,0x80,0x7a,0xd1,0x01,0x01,0x00,0x00] @@ -41129,10 +41129,10 @@ v_add_u16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x26,0xd1,0xc1,0x04,0x02,0x00] v_add_u16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_add_u16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_add_u16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x26,0xd1,0x01,0xff,0x03,0x00] @@ -41186,10 +41186,10 @@ v_add_u16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x26,0xd1,0x01,0x83,0x01,0x00] v_add_u16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_add_u16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_sub_u16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x4e] @@ -41321,10 +41321,10 @@ v_sub_u16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x27,0xd1,0xc1,0x04,0x02,0x00] v_sub_u16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_sub_u16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_sub_u16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x27,0xd1,0x01,0xff,0x03,0x00] @@ -41378,10 +41378,10 @@ v_sub_u16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x27,0xd1,0x01,0x83,0x01,0x00] v_sub_u16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_sub_u16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_subrev_u16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x50] @@ -41513,10 +41513,10 @@ v_subrev_u16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x28,0xd1,0xc1,0x04,0x02,0x00] v_subrev_u16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_subrev_u16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_subrev_u16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x28,0xd1,0x01,0xff,0x03,0x00] @@ -41570,10 +41570,10 @@ v_subrev_u16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x28,0xd1,0x01,0x83,0x01,0x00] v_subrev_u16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_subrev_u16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mul_lo_u16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x52] @@ -41705,10 +41705,10 @@ v_mul_lo_u16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x29,0xd1,0xc1,0x04,0x02,0x00] v_mul_lo_u16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mul_lo_u16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mul_lo_u16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x29,0xd1,0x01,0xff,0x03,0x00] @@ -41762,10 +41762,10 @@ v_mul_lo_u16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x29,0xd1,0x01,0x83,0x01,0x00] v_mul_lo_u16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mul_lo_u16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshlrev_b16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x54] @@ -41897,10 +41897,10 @@ v_lshlrev_b16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x2a,0xd1,0xc1,0x04,0x02,0x00] v_lshlrev_b16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshlrev_b16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshlrev_b16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xff,0x03,0x00] @@ -41954,10 +41954,10 @@ v_lshlrev_b16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x83,0x01,0x00] v_lshlrev_b16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshlrev_b16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshrrev_b16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x56] @@ -42089,10 +42089,10 @@ v_lshrrev_b16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x2b,0xd1,0xc1,0x04,0x02,0x00] v_lshrrev_b16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshrrev_b16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshrrev_b16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xff,0x03,0x00] @@ -42146,10 +42146,10 @@ v_lshrrev_b16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x83,0x01,0x00] v_lshrrev_b16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshrrev_b16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_ashrrev_i16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x58] @@ -42281,10 +42281,10 @@ v_ashrrev_i16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x2c,0xd1,0xc1,0x04,0x02,0x00] v_ashrrev_i16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_ashrrev_i16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_ashrrev_i16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xff,0x03,0x00] @@ -42338,10 +42338,10 @@ v_ashrrev_i16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x83,0x01,0x00] v_ashrrev_i16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_ashrrev_i16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_f16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x5a] @@ -42899,10 +42899,10 @@ v_max_u16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x2f,0xd1,0xc1,0x04,0x02,0x00] v_max_u16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_u16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_u16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xff,0x03,0x00] @@ -42956,10 +42956,10 @@ v_max_u16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x83,0x01,0x00] v_max_u16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_u16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_i16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x60] @@ -43091,10 +43091,10 @@ v_max_i16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x30,0xd1,0xc1,0x04,0x02,0x00] v_max_i16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_i16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_i16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x30,0xd1,0x01,0xff,0x03,0x00] @@ -43148,10 +43148,10 @@ v_max_i16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x30,0xd1,0x01,0x83,0x01,0x00] v_max_i16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_i16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_u16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x62] @@ -43283,10 +43283,10 @@ v_min_u16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x31,0xd1,0xc1,0x04,0x02,0x00] v_min_u16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_u16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_u16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x31,0xd1,0x01,0xff,0x03,0x00] @@ -43340,10 +43340,10 @@ v_min_u16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x31,0xd1,0x01,0x83,0x01,0x00] v_min_u16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_u16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_i16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x64] @@ -43475,10 +43475,10 @@ v_min_i16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x32,0xd1,0xc1,0x04,0x02,0x00] v_min_i16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_i16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_i16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x32,0xd1,0x01,0xff,0x03,0x00] @@ -43532,10 +43532,10 @@ v_min_i16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x32,0xd1,0x01,0x83,0x01,0x00] v_min_i16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_i16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_ldexp_f16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x66] @@ -51509,10 +51509,10 @@ v_mad_u16 v5, -1, v2, v3 // CHECK: [0x05,0x00,0xeb,0xd1,0xc1,0x04,0x0e,0x04] v_mad_u16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u16 v5, v1, v255, v3 // CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xff,0x0f,0x04] @@ -51566,10 +51566,10 @@ v_mad_u16 v5, v1, -1, v3 // CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04] v_mad_u16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u16 v5, v1, v2, v255 // CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x07] @@ -51623,10 +51623,10 @@ v_mad_u16 v5, v1, v2, -1 // CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x06,0x03] v_mad_u16 v5, v1, v2, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u16 v5, v1, v2, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u16 v5, v1, v2, v3 clamp // CHECK: [0x05,0x80,0xeb,0xd1,0x01,0x05,0x0e,0x04] @@ -51689,10 +51689,10 @@ v_mad_i16 v5, -1, v2, v3 // CHECK: [0x05,0x00,0xec,0xd1,0xc1,0x04,0x0e,0x04] v_mad_i16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i16 v5, v1, v255, v3 // CHECK: [0x05,0x00,0xec,0xd1,0x01,0xff,0x0f,0x04] @@ -51746,10 +51746,10 @@ v_mad_i16 v5, v1, -1, v3 // CHECK: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04] v_mad_i16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i16 v5, v1, v2, v255 // CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x07] @@ -51803,10 +51803,10 @@ v_mad_i16 v5, v1, v2, -1 // CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x06,0x03] v_mad_i16 v5, v1, v2, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i16 v5, v1, v2, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i16 v5, v1, v2, v3 clamp // CHECK: [0x05,0x80,0xec,0xd1,0x01,0x05,0x0e,0x04] @@ -76394,10 +76394,10 @@ v_cmp_f_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa0,0xd0,0xc1,0x04,0x02,0x00] v_cmp_f_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x03,0x00] @@ -76451,10 +76451,10 @@ v_cmp_f_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x83,0x01,0x00] v_cmp_f_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x42,0x7d] @@ -76601,10 +76601,10 @@ v_cmp_lt_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa1,0xd0,0xc1,0x04,0x02,0x00] v_cmp_lt_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xff,0x03,0x00] @@ -76658,10 +76658,10 @@ v_cmp_lt_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x83,0x01,0x00] v_cmp_lt_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x44,0x7d] @@ -76808,10 +76808,10 @@ v_cmp_eq_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa2,0xd0,0xc1,0x04,0x02,0x00] v_cmp_eq_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x03,0x00] @@ -76865,10 +76865,10 @@ v_cmp_eq_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x83,0x01,0x00] v_cmp_eq_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x46,0x7d] @@ -77015,10 +77015,10 @@ v_cmp_le_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa3,0xd0,0xc1,0x04,0x02,0x00] v_cmp_le_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xff,0x03,0x00] @@ -77072,10 +77072,10 @@ v_cmp_le_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x83,0x01,0x00] v_cmp_le_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x48,0x7d] @@ -77222,10 +77222,10 @@ v_cmp_gt_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa4,0xd0,0xc1,0x04,0x02,0x00] v_cmp_gt_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x03,0x00] @@ -77279,10 +77279,10 @@ v_cmp_gt_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x83,0x01,0x00] v_cmp_gt_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x4a,0x7d] @@ -77429,10 +77429,10 @@ v_cmp_ne_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa5,0xd0,0xc1,0x04,0x02,0x00] v_cmp_ne_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xff,0x03,0x00] @@ -77486,10 +77486,10 @@ v_cmp_ne_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x83,0x01,0x00] v_cmp_ne_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x4c,0x7d] @@ -77636,10 +77636,10 @@ v_cmp_ge_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa6,0xd0,0xc1,0x04,0x02,0x00] v_cmp_ge_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x03,0x00] @@ -77693,10 +77693,10 @@ v_cmp_ge_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x83,0x01,0x00] v_cmp_ge_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x4e,0x7d] @@ -77843,10 +77843,10 @@ v_cmp_t_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa7,0xd0,0xc1,0x04,0x02,0x00] v_cmp_t_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xff,0x03,0x00] @@ -77900,10 +77900,10 @@ v_cmp_t_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x83,0x01,0x00] v_cmp_t_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x50,0x7d] @@ -78050,10 +78050,10 @@ v_cmp_f_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa8,0xd0,0xc1,0x04,0x02,0x00] v_cmp_f_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x03,0x00] @@ -78107,10 +78107,10 @@ v_cmp_f_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x83,0x01,0x00] v_cmp_f_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x52,0x7d] @@ -78257,10 +78257,10 @@ v_cmp_lt_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa9,0xd0,0xc1,0x04,0x02,0x00] v_cmp_lt_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xff,0x03,0x00] @@ -78314,10 +78314,10 @@ v_cmp_lt_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x83,0x01,0x00] v_cmp_lt_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x54,0x7d] @@ -78464,10 +78464,10 @@ v_cmp_eq_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xaa,0xd0,0xc1,0x04,0x02,0x00] v_cmp_eq_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x03,0x00] @@ -78521,10 +78521,10 @@ v_cmp_eq_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x83,0x01,0x00] v_cmp_eq_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x56,0x7d] @@ -78671,10 +78671,10 @@ v_cmp_le_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xab,0xd0,0xc1,0x04,0x02,0x00] v_cmp_le_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xff,0x03,0x00] @@ -78728,10 +78728,10 @@ v_cmp_le_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x83,0x01,0x00] v_cmp_le_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x58,0x7d] @@ -78878,10 +78878,10 @@ v_cmp_gt_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xac,0xd0,0xc1,0x04,0x02,0x00] v_cmp_gt_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x03,0x00] @@ -78935,10 +78935,10 @@ v_cmp_gt_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x83,0x01,0x00] v_cmp_gt_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x5a,0x7d] @@ -79085,10 +79085,10 @@ v_cmp_ne_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xad,0xd0,0xc1,0x04,0x02,0x00] v_cmp_ne_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xff,0x03,0x00] @@ -79142,10 +79142,10 @@ v_cmp_ne_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x83,0x01,0x00] v_cmp_ne_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x5c,0x7d] @@ -79292,10 +79292,10 @@ v_cmp_ge_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xae,0xd0,0xc1,0x04,0x02,0x00] v_cmp_ge_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x03,0x00] @@ -79349,10 +79349,10 @@ v_cmp_ge_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x83,0x01,0x00] v_cmp_ge_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x5e,0x7d] @@ -79499,10 +79499,10 @@ v_cmp_t_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xaf,0xd0,0xc1,0x04,0x02,0x00] v_cmp_t_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xff,0x03,0x00] @@ -79556,10 +79556,10 @@ v_cmp_t_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x83,0x01,0x00] v_cmp_t_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x60,0x7d] @@ -79706,10 +79706,10 @@ v_cmpx_f_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb0,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_f_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x03,0x00] @@ -79763,10 +79763,10 @@ v_cmpx_f_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x83,0x01,0x00] v_cmpx_f_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x62,0x7d] @@ -79913,10 +79913,10 @@ v_cmpx_lt_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb1,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_lt_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xff,0x03,0x00] @@ -79970,10 +79970,10 @@ v_cmpx_lt_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x83,0x01,0x00] v_cmpx_lt_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x64,0x7d] @@ -80120,10 +80120,10 @@ v_cmpx_eq_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb2,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_eq_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x03,0x00] @@ -80177,10 +80177,10 @@ v_cmpx_eq_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x83,0x01,0x00] v_cmpx_eq_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x66,0x7d] @@ -80327,10 +80327,10 @@ v_cmpx_le_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb3,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_le_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xff,0x03,0x00] @@ -80384,10 +80384,10 @@ v_cmpx_le_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x83,0x01,0x00] v_cmpx_le_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x68,0x7d] @@ -80534,10 +80534,10 @@ v_cmpx_gt_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb4,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_gt_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x03,0x00] @@ -80591,10 +80591,10 @@ v_cmpx_gt_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x83,0x01,0x00] v_cmpx_gt_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x6a,0x7d] @@ -80741,10 +80741,10 @@ v_cmpx_ne_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb5,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_ne_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xff,0x03,0x00] @@ -80798,10 +80798,10 @@ v_cmpx_ne_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x83,0x01,0x00] v_cmpx_ne_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x6c,0x7d] @@ -80948,10 +80948,10 @@ v_cmpx_ge_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb6,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_ge_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x03,0x00] @@ -81005,10 +81005,10 @@ v_cmpx_ge_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x83,0x01,0x00] v_cmpx_ge_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x6e,0x7d] @@ -81155,10 +81155,10 @@ v_cmpx_t_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb7,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_t_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xff,0x03,0x00] @@ -81212,10 +81212,10 @@ v_cmpx_t_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x83,0x01,0x00] v_cmpx_t_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x70,0x7d] @@ -81362,10 +81362,10 @@ v_cmpx_f_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb8,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_f_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x03,0x00] @@ -81419,10 +81419,10 @@ v_cmpx_f_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x83,0x01,0x00] v_cmpx_f_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x72,0x7d] @@ -81569,10 +81569,10 @@ v_cmpx_lt_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb9,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_lt_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xff,0x03,0x00] @@ -81626,10 +81626,10 @@ v_cmpx_lt_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x83,0x01,0x00] v_cmpx_lt_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x74,0x7d] @@ -81776,10 +81776,10 @@ v_cmpx_eq_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xba,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_eq_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x03,0x00] @@ -81833,10 +81833,10 @@ v_cmpx_eq_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x83,0x01,0x00] v_cmpx_eq_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x76,0x7d] @@ -81983,10 +81983,10 @@ v_cmpx_le_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xbb,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_le_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xff,0x03,0x00] @@ -82040,10 +82040,10 @@ v_cmpx_le_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x83,0x01,0x00] v_cmpx_le_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x78,0x7d] @@ -82190,10 +82190,10 @@ v_cmpx_gt_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xbc,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_gt_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x03,0x00] @@ -82247,10 +82247,10 @@ v_cmpx_gt_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x83,0x01,0x00] v_cmpx_gt_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x7a,0x7d] @@ -82397,10 +82397,10 @@ v_cmpx_ne_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xbd,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_ne_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xff,0x03,0x00] @@ -82454,10 +82454,10 @@ v_cmpx_ne_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x83,0x01,0x00] v_cmpx_ne_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x7c,0x7d] @@ -82604,10 +82604,10 @@ v_cmpx_ge_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xbe,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_ge_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x03,0x00] @@ -82661,10 +82661,10 @@ v_cmpx_ge_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x83,0x01,0x00] v_cmpx_ge_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x7e,0x7d] @@ -82811,10 +82811,10 @@ v_cmpx_t_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xbf,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_t_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xff,0x03,0x00] @@ -82868,10 +82868,10 @@ v_cmpx_t_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x83,0x01,0x00] v_cmpx_t_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_i32 vcc, v1, v2 // CHECK: [0x01,0x05,0x80,0x7d] diff --git a/llvm/test/MC/AMDGPU/gfx9-asm-err.s b/llvm/test/MC/AMDGPU/gfx9-asm-err.s index de0930cf952a2..20c521f7ee3c5 100644 --- a/llvm/test/MC/AMDGPU/gfx9-asm-err.s +++ b/llvm/test/MC/AMDGPU/gfx9-asm-err.s @@ -1,31 +1,31 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 %s 2>&1 | FileCheck -check-prefix=GFX9ERR --implicit-check-not=error: %s v_cvt_f16_u16_e64 v5, 0.5 -// GFX9ERR: error: invalid literal operand +// GFX9ERR: error: literal operands are not supported v_cvt_f16_u16_e64 v5, -4.0 -// GFX9ERR: error: invalid literal operand +// GFX9ERR: error: literal operands are not supported v_add_u16_e64 v5, v1, 0.5 -// GFX9ERR: error: invalid literal operand +// GFX9ERR: error: literal operands are not supported v_add_u16_e64 v5, v1, -4.0 -// GFX9ERR: error: invalid literal operand +// GFX9ERR: error: literal operands are not supported v_cvt_f16_i16_e64 v5, 0.5 -// GFX9ERR: error: invalid literal operand +// GFX9ERR: error: literal operands are not supported v_cvt_f16_i16_e64 v5, -4.0 -// GFX9ERR: error: invalid literal operand +// GFX9ERR: error: literal operands are not supported v_add_u16_e64 v5, 0.5, v2 -// GFX9ERR: error: invalid literal operand +// GFX9ERR: error: literal operands are not supported v_add_u16_e64 v5, -4.0, v2 -// GFX9ERR: error: invalid literal operand +// GFX9ERR: error: literal operands are not supported v_subrev_u16_e64 v5, v1, 0.5 -// GFX9ERR: error: invalid literal operand +// GFX9ERR: error: literal operands are not supported v_subrev_u16_e64 v5, v1, -4.0 -// GFX9ERR: error: invalid literal operand +// GFX9ERR: error: literal operands are not supported diff --git a/llvm/test/MC/AMDGPU/gfx908_err_pos.s b/llvm/test/MC/AMDGPU/gfx908_err_pos.s index fcb7863fd642e..3fa641b176fed 100644 --- a/llvm/test/MC/AMDGPU/gfx908_err_pos.s +++ b/llvm/test/MC/AMDGPU/gfx908_err_pos.s @@ -1,5 +1,13 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx908 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace +//============================================================================== +// inline constants are not allowed for this operand + +v_mfma_f32_32x32x1f32 a[0:31], v0, v1, 0 +// CHECK: error: inline constants are not allowed for this operand +// CHECK-NEXT:{{^}}v_mfma_f32_32x32x1f32 a[0:31], v0, v1, 0 +// CHECK-NEXT:{{^}} ^ + //============================================================================== // invalid neg_hi value @@ -30,4 +38,4 @@ v_dot2_f32_f16 v0, v1, v2, v3 op_sel_hi:[2,0] v_accvgpr_write a2, execz // CHECK: error: source operand must be either a VGPR or an inline constant // CHECK-NEXT:{{^}}v_accvgpr_write a2, execz -// CHECK-NEXT:{{^}} ^ +// CHECK-NEXT:{{^}} ^ diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_all.s b/llvm/test/MC/AMDGPU/gfx9_asm_all.s index 93050e4c292b6..3b44acb877429 100644 --- a/llvm/test/MC/AMDGPU/gfx9_asm_all.s +++ b/llvm/test/MC/AMDGPU/gfx9_asm_all.s @@ -34899,10 +34899,10 @@ v_sub_u16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x27,0xd1,0xc1,0x04,0x02,0x00] v_sub_u16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_sub_u16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_sub_u16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x27,0xd1,0x01,0xff,0x03,0x00] @@ -34941,10 +34941,10 @@ v_sub_u16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x27,0xd1,0x01,0x83,0x01,0x00] v_sub_u16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_sub_u16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_subrev_u16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x50] @@ -35046,10 +35046,10 @@ v_subrev_u16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x28,0xd1,0xc1,0x04,0x02,0x00] v_subrev_u16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_subrev_u16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_subrev_u16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x28,0xd1,0x01,0xff,0x03,0x00] @@ -35187,10 +35187,10 @@ v_mul_lo_u16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x29,0xd1,0xc1,0x04,0x02,0x00] v_mul_lo_u16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mul_lo_u16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mul_lo_u16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x29,0xd1,0x01,0xff,0x03,0x00] @@ -35229,10 +35229,10 @@ v_mul_lo_u16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x29,0xd1,0x01,0x83,0x01,0x00] v_mul_lo_u16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mul_lo_u16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshlrev_b16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x54] @@ -35334,10 +35334,10 @@ v_lshlrev_b16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x2a,0xd1,0xc1,0x04,0x02,0x00] v_lshlrev_b16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshlrev_b16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshlrev_b16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xff,0x03,0x00] @@ -35376,10 +35376,10 @@ v_lshlrev_b16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x83,0x01,0x00] v_lshlrev_b16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshlrev_b16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshrrev_b16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x56] @@ -35481,10 +35481,10 @@ v_lshrrev_b16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x2b,0xd1,0xc1,0x04,0x02,0x00] v_lshrrev_b16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshrrev_b16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshrrev_b16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xff,0x03,0x00] @@ -35523,10 +35523,10 @@ v_lshrrev_b16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x83,0x01,0x00] v_lshrrev_b16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_lshrrev_b16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_ashrrev_i16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x58] @@ -35628,10 +35628,10 @@ v_ashrrev_i16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x2c,0xd1,0xc1,0x04,0x02,0x00] v_ashrrev_i16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_ashrrev_i16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_ashrrev_i16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xff,0x03,0x00] @@ -35670,10 +35670,10 @@ v_ashrrev_i16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x83,0x01,0x00] v_ashrrev_i16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_ashrrev_i16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_f16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x5a] @@ -36111,10 +36111,10 @@ v_max_u16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x2f,0xd1,0xc1,0x04,0x02,0x00] v_max_u16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_u16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_u16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xff,0x03,0x00] @@ -36153,10 +36153,10 @@ v_max_u16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x83,0x01,0x00] v_max_u16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_u16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_i16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x60] @@ -36258,10 +36258,10 @@ v_max_i16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x30,0xd1,0xc1,0x04,0x02,0x00] v_max_i16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_i16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_i16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x30,0xd1,0x01,0xff,0x03,0x00] @@ -36300,10 +36300,10 @@ v_max_i16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x30,0xd1,0x01,0x83,0x01,0x00] v_max_i16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max_i16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_u16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x62] @@ -36405,10 +36405,10 @@ v_min_u16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x31,0xd1,0xc1,0x04,0x02,0x00] v_min_u16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_u16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_u16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x31,0xd1,0x01,0xff,0x03,0x00] @@ -36447,10 +36447,10 @@ v_min_u16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x31,0xd1,0x01,0x83,0x01,0x00] v_min_u16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_u16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_i16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x64] @@ -36552,10 +36552,10 @@ v_min_i16_e64 v5, -1, v2 // CHECK: [0x05,0x00,0x32,0xd1,0xc1,0x04,0x02,0x00] v_min_i16_e64 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_i16_e64 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_i16_e64 v5, v1, v255 // CHECK: [0x05,0x00,0x32,0xd1,0x01,0xff,0x03,0x00] @@ -36594,10 +36594,10 @@ v_min_i16_e64 v5, v1, -1 // CHECK: [0x05,0x00,0x32,0xd1,0x01,0x83,0x01,0x00] v_min_i16_e64 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min_i16_e64 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_ldexp_f16 v5, v1, v2 // CHECK: [0x01,0x05,0x0a,0x66] @@ -43764,10 +43764,10 @@ v_mad_u32_u16 v5, -1, v2, v3 // CHECK: [0x05,0x00,0xf1,0xd1,0xc1,0x04,0x0e,0x04] v_mad_u32_u16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u32_u16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u32_u16 v5, v1, v255, v3 // CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xff,0x0f,0x04] @@ -43806,10 +43806,10 @@ v_mad_u32_u16 v5, v1, -1, v3 // CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x83,0x0d,0x04] v_mad_u32_u16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u32_u16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u32_u16 v5, v1, v2, v255 // CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xfe,0x07] @@ -43917,10 +43917,10 @@ v_mad_i32_i16 v5, -1, v2, v3 // CHECK: [0x05,0x00,0xf2,0xd1,0xc1,0x04,0x0e,0x04] v_mad_i32_i16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i32_i16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i32_i16 v5, v1, v255, v3 // CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xff,0x0f,0x04] @@ -43959,10 +43959,10 @@ v_mad_i32_i16 v5, v1, -1, v3 // CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x83,0x0d,0x04] v_mad_i32_i16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i32_i16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i32_i16 v5, v1, v2, v255 // CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xfe,0x07] @@ -44379,10 +44379,10 @@ v_min3_i16 v5, -1, v2, v3 // CHECK: [0x05,0x00,0xf5,0xd1,0xc1,0x04,0x0e,0x04] v_min3_i16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min3_i16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min3_i16 v5, v1, v255, v3 // CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xff,0x0f,0x04] @@ -44421,10 +44421,10 @@ v_min3_i16 v5, v1, -1, v3 // CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x83,0x0d,0x04] v_min3_i16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min3_i16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min3_i16 v5, v1, v2, v255 // CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xfe,0x07] @@ -44463,10 +44463,10 @@ v_min3_i16 v5, v1, v2, -1 // CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x06,0x03] v_min3_i16 v5, v1, v2, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min3_i16 v5, v1, v2, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0] // CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04] @@ -44529,10 +44529,10 @@ v_min3_u16 v5, -1, v2, v3 // CHECK: [0x05,0x00,0xf6,0xd1,0xc1,0x04,0x0e,0x04] v_min3_u16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min3_u16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min3_u16 v5, v1, v255, v3 // CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xff,0x0f,0x04] @@ -44571,10 +44571,10 @@ v_min3_u16 v5, v1, -1, v3 // CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x83,0x0d,0x04] v_min3_u16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min3_u16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min3_u16 v5, v1, v2, v255 // CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xfe,0x07] @@ -44613,10 +44613,10 @@ v_min3_u16 v5, v1, v2, -1 // CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x06,0x03] v_min3_u16 v5, v1, v2, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min3_u16 v5, v1, v2, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0] // CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x0e,0x04] @@ -44856,10 +44856,10 @@ v_max3_i16 v5, -1, v2, v3 // CHECK: [0x05,0x00,0xf8,0xd1,0xc1,0x04,0x0e,0x04] v_max3_i16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max3_i16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max3_i16 v5, v1, v255, v3 // CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xff,0x0f,0x04] @@ -44898,10 +44898,10 @@ v_max3_i16 v5, v1, -1, v3 // CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x83,0x0d,0x04] v_max3_i16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max3_i16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max3_i16 v5, v1, v2, v255 // CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xfe,0x07] @@ -44940,10 +44940,10 @@ v_max3_i16 v5, v1, v2, -1 // CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x06,0x03] v_max3_i16 v5, v1, v2, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max3_i16 v5, v1, v2, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0] // CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04] @@ -45006,10 +45006,10 @@ v_max3_u16 v5, -1, v2, v3 // CHECK: [0x05,0x00,0xf9,0xd1,0xc1,0x04,0x0e,0x04] v_max3_u16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max3_u16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max3_u16 v5, v1, v255, v3 // CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xff,0x0f,0x04] @@ -45048,10 +45048,10 @@ v_max3_u16 v5, v1, -1, v3 // CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x83,0x0d,0x04] v_max3_u16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max3_u16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max3_u16 v5, v1, v2, v255 // CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xfe,0x07] @@ -45090,10 +45090,10 @@ v_max3_u16 v5, v1, v2, -1 // CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x06,0x03] v_max3_u16 v5, v1, v2, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max3_u16 v5, v1, v2, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0] // CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x0e,0x04] @@ -45333,10 +45333,10 @@ v_med3_i16 v5, -1, v2, v3 // CHECK: [0x05,0x00,0xfb,0xd1,0xc1,0x04,0x0e,0x04] v_med3_i16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_med3_i16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_med3_i16 v5, v1, v255, v3 // CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xff,0x0f,0x04] @@ -45375,10 +45375,10 @@ v_med3_i16 v5, v1, -1, v3 // CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x83,0x0d,0x04] v_med3_i16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_med3_i16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_med3_i16 v5, v1, v2, v255 // CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xfe,0x07] @@ -45417,10 +45417,10 @@ v_med3_i16 v5, v1, v2, -1 // CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x06,0x03] v_med3_i16 v5, v1, v2, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_med3_i16 v5, v1, v2, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0] // CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04] @@ -45483,10 +45483,10 @@ v_med3_u16 v5, -1, v2, v3 // CHECK: [0x05,0x00,0xfc,0xd1,0xc1,0x04,0x0e,0x04] v_med3_u16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_med3_u16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_med3_u16 v5, v1, v255, v3 // CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xff,0x0f,0x04] @@ -45525,10 +45525,10 @@ v_med3_u16 v5, v1, -1, v3 // CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x83,0x0d,0x04] v_med3_u16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_med3_u16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_med3_u16 v5, v1, v2, v255 // CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xfe,0x07] @@ -45567,10 +45567,10 @@ v_med3_u16 v5, v1, v2, -1 // CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x06,0x03] v_med3_u16 v5, v1, v2, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_med3_u16 v5, v1, v2, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0] // CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x0e,0x04] @@ -46602,10 +46602,10 @@ v_mad_u16 v5, -1, v2, v3 // CHECK: [0x05,0x00,0x04,0xd2,0xc1,0x04,0x0e,0x04] v_mad_u16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u16 v5, v1, v255, v3 // CHECK: [0x05,0x00,0x04,0xd2,0x01,0xff,0x0f,0x04] @@ -46644,10 +46644,10 @@ v_mad_u16 v5, v1, -1, v3 // CHECK: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04] v_mad_u16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u16 v5, v1, v2, v255 // CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xfe,0x07] @@ -46686,10 +46686,10 @@ v_mad_u16 v5, v1, v2, -1 // CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x06,0x03] v_mad_u16 v5, v1, v2, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u16 v5, v1, v2, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,0] // CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x0e,0x04] @@ -46755,10 +46755,10 @@ v_mad_i16 v5, -1, v2, v3 // CHECK: [0x05,0x00,0x05,0xd2,0xc1,0x04,0x0e,0x04] v_mad_i16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i16 v5, v1, v255, v3 // CHECK: [0x05,0x00,0x05,0xd2,0x01,0xff,0x0f,0x04] @@ -46797,10 +46797,10 @@ v_mad_i16 v5, v1, -1, v3 // CHECK: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04] v_mad_i16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i16 v5, v1, v2, v255 // CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xfe,0x07] @@ -46839,10 +46839,10 @@ v_mad_i16 v5, v1, v2, -1 // CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x06,0x03] v_mad_i16 v5, v1, v2, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i16 v5, v1, v2, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,0] // CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x0e,0x04] @@ -50052,10 +50052,10 @@ v_add_i16 v5, -1, v2 // CHECK: [0x05,0x00,0x9e,0xd2,0xc1,0x04,0x02,0x00] v_add_i16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_add_i16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_add_i16 v5, v1, v255 // CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xff,0x03,0x00] @@ -50094,10 +50094,10 @@ v_add_i16 v5, v1, -1 // CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x83,0x01,0x00] v_add_i16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_add_i16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_add_i16 v5, v1, v2 op_sel:[0,0,0] // CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x02,0x00] @@ -50160,10 +50160,10 @@ v_sub_i16 v5, -1, v2 // CHECK: [0x05,0x00,0x9f,0xd2,0xc1,0x04,0x02,0x00] v_sub_i16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_sub_i16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_sub_i16 v5, v1, v255 // CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xff,0x03,0x00] @@ -50202,10 +50202,10 @@ v_sub_i16 v5, v1, -1 // CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x83,0x01,0x00] v_sub_i16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_sub_i16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_sub_i16 v5, v1, v2 op_sel:[0,0,0] // CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x05,0x02,0x00] @@ -50391,10 +50391,10 @@ v_pk_mad_i16 v5, -1, v2, v3 // CHECK: [0x05,0x40,0x80,0xd3,0xc1,0x04,0x0e,0x1c] v_pk_mad_i16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mad_i16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mad_i16 v5, v1, v255, v3 // CHECK: [0x05,0x40,0x80,0xd3,0x01,0xff,0x0f,0x1c] @@ -50433,10 +50433,10 @@ v_pk_mad_i16 v5, v1, -1, v3 // CHECK: [0x05,0x40,0x80,0xd3,0x01,0x83,0x0d,0x1c] v_pk_mad_i16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mad_i16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mad_i16 v5, v1, v2, v255 // CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xfe,0x1f] @@ -50475,10 +50475,10 @@ v_pk_mad_i16 v5, v1, v2, -1 // CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x06,0x1b] v_pk_mad_i16 v5, v1, v2, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mad_i16 v5, v1, v2, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mad_i16 v5, v1, v2, v3 op_sel:[1,0,0] // CHECK: [0x05,0x48,0x80,0xd3,0x01,0x05,0x0e,0x1c] @@ -50550,10 +50550,10 @@ v_pk_mul_lo_u16 v5, -1, v2 // CHECK: [0x05,0x00,0x81,0xd3,0xc1,0x04,0x02,0x18] v_pk_mul_lo_u16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mul_lo_u16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mul_lo_u16 v5, v1, v255 // CHECK: [0x05,0x00,0x81,0xd3,0x01,0xff,0x03,0x18] @@ -50595,10 +50595,10 @@ v_pk_mul_lo_u16 v5, v1, -1 // CHECK: [0x05,0x00,0x81,0xd3,0x01,0x83,0x01,0x18] v_pk_mul_lo_u16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mul_lo_u16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mul_lo_u16 v5, v1, v2 op_sel:[1,0] // CHECK: [0x05,0x08,0x81,0xd3,0x01,0x05,0x02,0x18] @@ -50664,10 +50664,10 @@ v_pk_add_i16 v5, -1, v2 // CHECK: [0x05,0x00,0x82,0xd3,0xc1,0x04,0x02,0x18] v_pk_add_i16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_add_i16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_add_i16 v5, v1, v255 // CHECK: [0x05,0x00,0x82,0xd3,0x01,0xff,0x03,0x18] @@ -50709,10 +50709,10 @@ v_pk_add_i16 v5, v1, -1 // CHECK: [0x05,0x00,0x82,0xd3,0x01,0x83,0x01,0x18] v_pk_add_i16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_add_i16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_add_i16 v5, v1, v2 op_sel:[1,0] // CHECK: [0x05,0x08,0x82,0xd3,0x01,0x05,0x02,0x18] @@ -50781,10 +50781,10 @@ v_pk_sub_i16 v5, -1, v2 // CHECK: [0x05,0x00,0x83,0xd3,0xc1,0x04,0x02,0x18] v_pk_sub_i16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_sub_i16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_sub_i16 v5, v1, v255 // CHECK: [0x05,0x00,0x83,0xd3,0x01,0xff,0x03,0x18] @@ -50826,10 +50826,10 @@ v_pk_sub_i16 v5, v1, -1 // CHECK: [0x05,0x00,0x83,0xd3,0x01,0x83,0x01,0x18] v_pk_sub_i16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_sub_i16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_sub_i16 v5, v1, v2 op_sel:[1,0] // CHECK: [0x05,0x08,0x83,0xd3,0x01,0x05,0x02,0x18] @@ -50898,10 +50898,10 @@ v_pk_lshlrev_b16 v5, -1, v2 // CHECK: [0x05,0x00,0x84,0xd3,0xc1,0x04,0x02,0x18] v_pk_lshlrev_b16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_lshlrev_b16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_lshlrev_b16 v5, v1, v255 // CHECK: [0x05,0x00,0x84,0xd3,0x01,0xff,0x03,0x18] @@ -50943,10 +50943,10 @@ v_pk_lshlrev_b16 v5, v1, -1 // CHECK: [0x05,0x00,0x84,0xd3,0x01,0x83,0x01,0x18] v_pk_lshlrev_b16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_lshlrev_b16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_lshlrev_b16 v5, v1, v2 op_sel:[1,0] // CHECK: [0x05,0x08,0x84,0xd3,0x01,0x05,0x02,0x18] @@ -51012,10 +51012,10 @@ v_pk_lshrrev_b16 v5, -1, v2 // CHECK: [0x05,0x00,0x85,0xd3,0xc1,0x04,0x02,0x18] v_pk_lshrrev_b16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_lshrrev_b16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_lshrrev_b16 v5, v1, v255 // CHECK: [0x05,0x00,0x85,0xd3,0x01,0xff,0x03,0x18] @@ -51057,10 +51057,10 @@ v_pk_lshrrev_b16 v5, v1, -1 // CHECK: [0x05,0x00,0x85,0xd3,0x01,0x83,0x01,0x18] v_pk_lshrrev_b16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_lshrrev_b16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_lshrrev_b16 v5, v1, v2 op_sel:[1,0] // CHECK: [0x05,0x08,0x85,0xd3,0x01,0x05,0x02,0x18] @@ -51126,10 +51126,10 @@ v_pk_ashrrev_i16 v5, -1, v2 // CHECK: [0x05,0x00,0x86,0xd3,0xc1,0x04,0x02,0x18] v_pk_ashrrev_i16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_ashrrev_i16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_ashrrev_i16 v5, v1, v255 // CHECK: [0x05,0x00,0x86,0xd3,0x01,0xff,0x03,0x18] @@ -51171,10 +51171,10 @@ v_pk_ashrrev_i16 v5, v1, -1 // CHECK: [0x05,0x00,0x86,0xd3,0x01,0x83,0x01,0x18] v_pk_ashrrev_i16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_ashrrev_i16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_ashrrev_i16 v5, v1, v2 op_sel:[1,0] // CHECK: [0x05,0x08,0x86,0xd3,0x01,0x05,0x02,0x18] @@ -51240,10 +51240,10 @@ v_pk_max_i16 v5, -1, v2 // CHECK: [0x05,0x00,0x87,0xd3,0xc1,0x04,0x02,0x18] v_pk_max_i16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_max_i16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_max_i16 v5, v1, v255 // CHECK: [0x05,0x00,0x87,0xd3,0x01,0xff,0x03,0x18] @@ -51285,10 +51285,10 @@ v_pk_max_i16 v5, v1, -1 // CHECK: [0x05,0x00,0x87,0xd3,0x01,0x83,0x01,0x18] v_pk_max_i16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_max_i16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_max_i16 v5, v1, v2 op_sel:[1,0] // CHECK: [0x05,0x08,0x87,0xd3,0x01,0x05,0x02,0x18] @@ -51354,10 +51354,10 @@ v_pk_min_i16 v5, -1, v2 // CHECK: [0x05,0x00,0x88,0xd3,0xc1,0x04,0x02,0x18] v_pk_min_i16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_min_i16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_min_i16 v5, v1, v255 // CHECK: [0x05,0x00,0x88,0xd3,0x01,0xff,0x03,0x18] @@ -51399,10 +51399,10 @@ v_pk_min_i16 v5, v1, -1 // CHECK: [0x05,0x00,0x88,0xd3,0x01,0x83,0x01,0x18] v_pk_min_i16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_min_i16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_min_i16 v5, v1, v2 op_sel:[1,0] // CHECK: [0x05,0x08,0x88,0xd3,0x01,0x05,0x02,0x18] @@ -51468,10 +51468,10 @@ v_pk_mad_u16 v5, -1, v2, v3 // CHECK: [0x05,0x40,0x89,0xd3,0xc1,0x04,0x0e,0x1c] v_pk_mad_u16 v5, 0.5, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mad_u16 v5, -4.0, v2, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mad_u16 v5, v1, v255, v3 // CHECK: [0x05,0x40,0x89,0xd3,0x01,0xff,0x0f,0x1c] @@ -51510,10 +51510,10 @@ v_pk_mad_u16 v5, v1, -1, v3 // CHECK: [0x05,0x40,0x89,0xd3,0x01,0x83,0x0d,0x1c] v_pk_mad_u16 v5, v1, 0.5, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mad_u16 v5, v1, -4.0, v3 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mad_u16 v5, v1, v2, v255 // CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xfe,0x1f] @@ -51552,10 +51552,10 @@ v_pk_mad_u16 v5, v1, v2, -1 // CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x06,0x1b] v_pk_mad_u16 v5, v1, v2, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mad_u16 v5, v1, v2, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0] // CHECK: [0x05,0x48,0x89,0xd3,0x01,0x05,0x0e,0x1c] @@ -51627,10 +51627,10 @@ v_pk_add_u16 v5, -1, v2 // CHECK: [0x05,0x00,0x8a,0xd3,0xc1,0x04,0x02,0x18] v_pk_add_u16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_add_u16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_add_u16 v5, v1, v255 // CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xff,0x03,0x18] @@ -51672,10 +51672,10 @@ v_pk_add_u16 v5, v1, -1 // CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x83,0x01,0x18] v_pk_add_u16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_add_u16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_add_u16 v5, v1, v2 op_sel:[1,0] // CHECK: [0x05,0x08,0x8a,0xd3,0x01,0x05,0x02,0x18] @@ -51744,10 +51744,10 @@ v_pk_sub_u16 v5, -1, v2 // CHECK: [0x05,0x00,0x8b,0xd3,0xc1,0x04,0x02,0x18] v_pk_sub_u16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_sub_u16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_sub_u16 v5, v1, v255 // CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xff,0x03,0x18] @@ -51789,10 +51789,10 @@ v_pk_sub_u16 v5, v1, -1 // CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x83,0x01,0x18] v_pk_sub_u16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_sub_u16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_sub_u16 v5, v1, v2 op_sel:[1,0] // CHECK: [0x05,0x08,0x8b,0xd3,0x01,0x05,0x02,0x18] @@ -51861,10 +51861,10 @@ v_pk_max_u16 v5, -1, v2 // CHECK: [0x05,0x00,0x8c,0xd3,0xc1,0x04,0x02,0x18] v_pk_max_u16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_max_u16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_max_u16 v5, v1, v255 // CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xff,0x03,0x18] @@ -51906,10 +51906,10 @@ v_pk_max_u16 v5, v1, -1 // CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x83,0x01,0x18] v_pk_max_u16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_max_u16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_max_u16 v5, v1, v2 op_sel:[1,0] // CHECK: [0x05,0x08,0x8c,0xd3,0x01,0x05,0x02,0x18] @@ -51975,10 +51975,10 @@ v_pk_min_u16 v5, -1, v2 // CHECK: [0x05,0x00,0x8d,0xd3,0xc1,0x04,0x02,0x18] v_pk_min_u16 v5, 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_min_u16 v5, -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_min_u16 v5, v1, v255 // CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xff,0x03,0x18] @@ -52020,10 +52020,10 @@ v_pk_min_u16 v5, v1, -1 // CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x83,0x01,0x18] v_pk_min_u16 v5, v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_min_u16 v5, v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_pk_min_u16 v5, v1, v2 op_sel:[1,0] // CHECK: [0x05,0x08,0x8d,0xd3,0x01,0x05,0x02,0x18] @@ -69471,10 +69471,10 @@ v_cmp_f_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa0,0xd0,0xc1,0x04,0x02,0x00] v_cmp_f_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x03,0x00] @@ -69513,10 +69513,10 @@ v_cmp_f_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x83,0x01,0x00] v_cmp_f_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x42,0x7d] @@ -69624,10 +69624,10 @@ v_cmp_lt_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa1,0xd0,0xc1,0x04,0x02,0x00] v_cmp_lt_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xff,0x03,0x00] @@ -69666,10 +69666,10 @@ v_cmp_lt_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x83,0x01,0x00] v_cmp_lt_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x44,0x7d] @@ -69777,10 +69777,10 @@ v_cmp_eq_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa2,0xd0,0xc1,0x04,0x02,0x00] v_cmp_eq_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x03,0x00] @@ -69819,10 +69819,10 @@ v_cmp_eq_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x83,0x01,0x00] v_cmp_eq_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x46,0x7d] @@ -69930,10 +69930,10 @@ v_cmp_le_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa3,0xd0,0xc1,0x04,0x02,0x00] v_cmp_le_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xff,0x03,0x00] @@ -69972,10 +69972,10 @@ v_cmp_le_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x83,0x01,0x00] v_cmp_le_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x48,0x7d] @@ -70083,10 +70083,10 @@ v_cmp_gt_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa4,0xd0,0xc1,0x04,0x02,0x00] v_cmp_gt_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x03,0x00] @@ -70125,10 +70125,10 @@ v_cmp_gt_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x83,0x01,0x00] v_cmp_gt_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x4a,0x7d] @@ -70236,10 +70236,10 @@ v_cmp_ne_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa5,0xd0,0xc1,0x04,0x02,0x00] v_cmp_ne_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xff,0x03,0x00] @@ -70278,10 +70278,10 @@ v_cmp_ne_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x83,0x01,0x00] v_cmp_ne_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x4c,0x7d] @@ -70389,10 +70389,10 @@ v_cmp_ge_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa6,0xd0,0xc1,0x04,0x02,0x00] v_cmp_ge_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x03,0x00] @@ -70431,10 +70431,10 @@ v_cmp_ge_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x83,0x01,0x00] v_cmp_ge_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x4e,0x7d] @@ -70542,10 +70542,10 @@ v_cmp_t_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa7,0xd0,0xc1,0x04,0x02,0x00] v_cmp_t_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xff,0x03,0x00] @@ -70584,10 +70584,10 @@ v_cmp_t_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x83,0x01,0x00] v_cmp_t_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x50,0x7d] @@ -70695,10 +70695,10 @@ v_cmp_f_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa8,0xd0,0xc1,0x04,0x02,0x00] v_cmp_f_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x03,0x00] @@ -70737,10 +70737,10 @@ v_cmp_f_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x83,0x01,0x00] v_cmp_f_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x52,0x7d] @@ -70848,10 +70848,10 @@ v_cmp_lt_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xa9,0xd0,0xc1,0x04,0x02,0x00] v_cmp_lt_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xff,0x03,0x00] @@ -70890,10 +70890,10 @@ v_cmp_lt_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x83,0x01,0x00] v_cmp_lt_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_lt_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x54,0x7d] @@ -71001,10 +71001,10 @@ v_cmp_eq_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xaa,0xd0,0xc1,0x04,0x02,0x00] v_cmp_eq_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x03,0x00] @@ -71043,10 +71043,10 @@ v_cmp_eq_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x83,0x01,0x00] v_cmp_eq_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_eq_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x56,0x7d] @@ -71154,10 +71154,10 @@ v_cmp_le_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xab,0xd0,0xc1,0x04,0x02,0x00] v_cmp_le_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xff,0x03,0x00] @@ -71196,10 +71196,10 @@ v_cmp_le_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x83,0x01,0x00] v_cmp_le_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_le_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x58,0x7d] @@ -71307,10 +71307,10 @@ v_cmp_gt_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xac,0xd0,0xc1,0x04,0x02,0x00] v_cmp_gt_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x03,0x00] @@ -71349,10 +71349,10 @@ v_cmp_gt_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x83,0x01,0x00] v_cmp_gt_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_gt_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x5a,0x7d] @@ -71460,10 +71460,10 @@ v_cmp_ne_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xad,0xd0,0xc1,0x04,0x02,0x00] v_cmp_ne_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xff,0x03,0x00] @@ -71502,10 +71502,10 @@ v_cmp_ne_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x83,0x01,0x00] v_cmp_ne_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ne_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x5c,0x7d] @@ -71613,10 +71613,10 @@ v_cmp_ge_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xae,0xd0,0xc1,0x04,0x02,0x00] v_cmp_ge_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x03,0x00] @@ -71655,10 +71655,10 @@ v_cmp_ge_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x83,0x01,0x00] v_cmp_ge_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_ge_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x5e,0x7d] @@ -71766,10 +71766,10 @@ v_cmp_t_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xaf,0xd0,0xc1,0x04,0x02,0x00] v_cmp_t_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xff,0x03,0x00] @@ -71808,10 +71808,10 @@ v_cmp_t_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x83,0x01,0x00] v_cmp_t_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_t_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x60,0x7d] @@ -71922,10 +71922,10 @@ v_cmpx_f_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb0,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_f_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x03,0x00] @@ -71964,10 +71964,10 @@ v_cmpx_f_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x83,0x01,0x00] v_cmpx_f_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x62,0x7d] @@ -72078,10 +72078,10 @@ v_cmpx_lt_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb1,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_lt_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xff,0x03,0x00] @@ -72120,10 +72120,10 @@ v_cmpx_lt_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x83,0x01,0x00] v_cmpx_lt_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x64,0x7d] @@ -72234,10 +72234,10 @@ v_cmpx_eq_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb2,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_eq_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x03,0x00] @@ -72276,10 +72276,10 @@ v_cmpx_eq_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x83,0x01,0x00] v_cmpx_eq_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x66,0x7d] @@ -72390,10 +72390,10 @@ v_cmpx_le_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb3,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_le_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xff,0x03,0x00] @@ -72432,10 +72432,10 @@ v_cmpx_le_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x83,0x01,0x00] v_cmpx_le_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x68,0x7d] @@ -72546,10 +72546,10 @@ v_cmpx_gt_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb4,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_gt_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x03,0x00] @@ -72588,10 +72588,10 @@ v_cmpx_gt_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x83,0x01,0x00] v_cmpx_gt_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x6a,0x7d] @@ -72702,10 +72702,10 @@ v_cmpx_ne_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb5,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_ne_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xff,0x03,0x00] @@ -72744,10 +72744,10 @@ v_cmpx_ne_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x83,0x01,0x00] v_cmpx_ne_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x6c,0x7d] @@ -72858,10 +72858,10 @@ v_cmpx_ge_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb6,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_ge_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x03,0x00] @@ -72900,10 +72900,10 @@ v_cmpx_ge_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x83,0x01,0x00] v_cmpx_ge_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_i16 vcc, v1, v2 // CHECK: [0x01,0x05,0x6e,0x7d] @@ -73014,10 +73014,10 @@ v_cmpx_t_i16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb7,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_t_i16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_i16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_i16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xff,0x03,0x00] @@ -73056,10 +73056,10 @@ v_cmpx_t_i16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x83,0x01,0x00] v_cmpx_t_i16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_i16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x70,0x7d] @@ -73170,10 +73170,10 @@ v_cmpx_f_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb8,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_f_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x03,0x00] @@ -73212,10 +73212,10 @@ v_cmpx_f_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x83,0x01,0x00] v_cmpx_f_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_f_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x72,0x7d] @@ -73326,10 +73326,10 @@ v_cmpx_lt_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xb9,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_lt_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xff,0x03,0x00] @@ -73368,10 +73368,10 @@ v_cmpx_lt_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x83,0x01,0x00] v_cmpx_lt_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_lt_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x74,0x7d] @@ -73482,10 +73482,10 @@ v_cmpx_eq_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xba,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_eq_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x03,0x00] @@ -73524,10 +73524,10 @@ v_cmpx_eq_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x83,0x01,0x00] v_cmpx_eq_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_eq_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x76,0x7d] @@ -73638,10 +73638,10 @@ v_cmpx_le_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xbb,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_le_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xff,0x03,0x00] @@ -73680,10 +73680,10 @@ v_cmpx_le_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x83,0x01,0x00] v_cmpx_le_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_le_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x78,0x7d] @@ -73794,10 +73794,10 @@ v_cmpx_gt_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xbc,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_gt_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x03,0x00] @@ -73836,10 +73836,10 @@ v_cmpx_gt_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x83,0x01,0x00] v_cmpx_gt_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_gt_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x7a,0x7d] @@ -73950,10 +73950,10 @@ v_cmpx_ne_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xbd,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_ne_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xff,0x03,0x00] @@ -73992,10 +73992,10 @@ v_cmpx_ne_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x83,0x01,0x00] v_cmpx_ne_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ne_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x7c,0x7d] @@ -74106,10 +74106,10 @@ v_cmpx_ge_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xbe,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_ge_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x03,0x00] @@ -74148,10 +74148,10 @@ v_cmpx_ge_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x83,0x01,0x00] v_cmpx_ge_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_ge_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_u16 vcc, v1, v2 // CHECK: [0x01,0x05,0x7e,0x7d] @@ -74262,10 +74262,10 @@ v_cmpx_t_u16_e64 s[10:11], -1, v2 // CHECK: [0x0a,0x00,0xbf,0xd0,0xc1,0x04,0x02,0x00] v_cmpx_t_u16_e64 s[10:11], 0.5, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_u16_e64 s[10:11], -4.0, v2 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_u16_e64 s[10:11], v1, v255 // CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xff,0x03,0x00] @@ -74304,10 +74304,10 @@ v_cmpx_t_u16_e64 s[10:11], v1, -1 // CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x83,0x01,0x00] v_cmpx_t_u16_e64 s[10:11], v1, 0.5 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmpx_t_u16_e64 s[10:11], v1, -4.0 -// CHECK-ERR: error: invalid literal operand +// CHECK-ERR: error: literal operands are not supported v_cmp_f_i32 vcc, v1, v2 // CHECK: [0x01,0x05,0x80,0x7d] diff --git a/llvm/test/MC/AMDGPU/gfx9_err_pos.s b/llvm/test/MC/AMDGPU/gfx9_err_pos.s index aca62a043ae32..6b83ce2af9dd1 100644 --- a/llvm/test/MC/AMDGPU/gfx9_err_pos.s +++ b/llvm/test/MC/AMDGPU/gfx9_err_pos.s @@ -122,7 +122,40 @@ s_set_gpr_idx_on s0, 16 v_add_f32_e64 v0, flat_scratch_hi, m0 // CHECK: error: invalid operand (violates constant bus restrictions) // CHECK-NEXT:{{^}}v_add_f32_e64 v0, flat_scratch_hi, m0 -// CHECK-NEXT:{{^}}^ +// CHECK-NEXT:{{^}} ^ + +v_madak_f32 v5, s1, v2, 0xa1b1c1d1 +// CHECK: error: invalid operand (violates constant bus restrictions) +// CHECK-NEXT:{{^}}v_madak_f32 v5, s1, v2, 0xa1b1c1d1 +// CHECK-NEXT:{{^}} ^ + +v_madmk_f32 v5, s1, 0x11213141, v255 +// CHECK: error: invalid operand (violates constant bus restrictions) +// CHECK-NEXT:{{^}}v_madmk_f32 v5, s1, 0x11213141, v255 +// CHECK-NEXT:{{^}} ^ + +//============================================================================== +// literal operands are not supported + +v_bfe_u32 v0, v2, v3, undef +// CHECK: error: literal operands are not supported +// CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, v3, undef +// CHECK-NEXT:{{^}} ^ + +v_bfe_u32 v0, v2, undef, v3 +// CHECK: error: literal operands are not supported +// CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, undef, v3 +// CHECK-NEXT:{{^}} ^ + +v_add_i16 v5, v1, 0.5 +// CHECK: error: literal operands are not supported +// CHECK-NEXT:{{^}}v_add_i16 v5, v1, 0.5 +// CHECK-NEXT:{{^}} ^ + +v_add_i16 v5, 0.5, v2 +// CHECK: error: literal operands are not supported +// CHECK-NEXT:{{^}}v_add_i16 v5, 0.5, v2 +// CHECK-NEXT:{{^}} ^ //============================================================================== // r128 modifier is not supported on this GPU diff --git a/llvm/test/MC/AMDGPU/literals.s b/llvm/test/MC/AMDGPU/literals.s index 7d33414c904b4..7cf0d1f5480a8 100644 --- a/llvm/test/MC/AMDGPU/literals.s +++ b/llvm/test/MC/AMDGPU/literals.s @@ -282,12 +282,12 @@ v_trunc_f32_e32 v0, 1234 // GFX89: v_fract_f64_e32 v[0:1], 0x4d2 ; encoding: [0xff,0x64,0x00,0x7e,0xd2,0x04,0x00,0x00] v_fract_f64_e32 v[0:1], 1234 -// NOSICI: error: invalid literal operand -// NOGFX89: error: invalid literal operand +// NOSICI: error: literal operands are not supported +// NOGFX89: error: literal operands are not supported v_trunc_f32_e64 v0, 1234 -// NOSICI: error: invalid literal operand -// NOGFX89: error: invalid literal operand +// NOSICI: error: literal operands are not supported +// NOGFX89: error: literal operands are not supported v_fract_f64_e64 v[0:1], 1234 // SICI: v_trunc_f32_e32 v0, 0xffff2bcf ; encoding: [0xff,0x42,0x00,0x7e,0xcf,0x2b,0xff,0xff] @@ -378,8 +378,8 @@ s_mov_b64_e32 s[0:1], 1234 // GFX89: v_and_b32_e32 v0, 0x4d2, v1 ; encoding: [0xff,0x02,0x00,0x26,0xd2,0x04,0x00,0x00] v_and_b32_e32 v0, 1234, v1 -// NOSICI: error: invalid literal operand -// NOGFX89: error: invalid literal operand +// NOSICI: error: literal operands are not supported +// NOGFX89: error: literal operands are not supported v_and_b32_e64 v0, 1234, v1 // SICI: s_mov_b64 s[0:1], 0xffff2bcf ; encoding: [0xff,0x04,0x80,0xbe,0xcf,0x2b,0xff,0xff] @@ -450,12 +450,12 @@ v_trunc_f32_e64 v0, 0x3fc45f306dc9c882 // GFX89: v_fract_f64_e64 v[0:1], 0.15915494309189532 ; encoding: [0x00,0x00,0x72,0xd1,0xf8,0x00,0x00,0x00] v_fract_f64_e64 v[0:1], 0x3fc45f306dc9c882 -// NOSICI: error: invalid literal operand +// NOSICI: error: literal operands are not supported // GFX89: v_trunc_f32_e64 v0, 0.15915494 ; encoding: [0x00,0x00,0x5c,0xd1,0xf8,0x00,0x00,0x00] v_trunc_f32_e64 v0, 0x3e22f983 -// NOSICI: error: invalid literal operand -// NOGFX89: error: invalid literal operand +// NOSICI: error: literal operands are not supported +// NOGFX89: error: literal operands are not supported v_fract_f64_e64 v[0:1], 0x3e22f983 // NOSICI: error: invalid operand for instruction @@ -466,7 +466,7 @@ s_mov_b64_e32 s[0:1], 0.159154943091895317852646485335 // GFX89: v_and_b32_e32 v0, 0.15915494, v1 ; encoding: [0xf8,0x02,0x00,0x26] v_and_b32_e32 v0, 0.159154943091895317852646485335, v1 -// NOSICI: error: invalid literal operand +// NOSICI: error: literal operands are not supported // GFX89: v_and_b32_e64 v0, 0.15915494, v1 ; encoding: [0x00,0x00,0x13,0xd1,0xf8,0x02,0x02,0x00] v_and_b32_e64 v0, 0.159154943091895317852646485335, v1 diff --git a/llvm/test/MC/AMDGPU/literalv216-err.s b/llvm/test/MC/AMDGPU/literalv216-err.s index eefe1b343c3a1..4ee47cdf01184 100644 --- a/llvm/test/MC/AMDGPU/literalv216-err.s +++ b/llvm/test/MC/AMDGPU/literalv216-err.s @@ -2,45 +2,45 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 %s 2>&1 | FileCheck -check-prefix=GFX10 --implicit-check-not=error: %s v_pk_add_f16 v1, -17, v2 -// GFX9: error: invalid literal operand +// GFX9: error: literal operands are not supported v_pk_add_f16 v1, 65, v2 -// GFX9: error: invalid literal operand +// GFX9: error: literal operands are not supported v_pk_add_f16 v1, 64.0, v2 -// GFX9: error: invalid literal operand +// GFX9: error: literal operands are not supported v_pk_add_f16 v1, -0.15915494, v2 -// GFX9: error: invalid literal operand +// GFX9: error: literal operands are not supported v_pk_add_f16 v1, -0.0, v2 -// GFX9: error: invalid literal operand +// GFX9: error: literal operands are not supported v_pk_add_f16 v1, -32768, v2 -// GFX9: error: invalid literal operand +// GFX9: error: literal operands are not supported v_pk_add_f16 v1, 32767, v2 -// GFX9: error: invalid literal operand +// GFX9: error: literal operands are not supported v_pk_add_f16 v1, 0xffffffffffff000f, v2 -// GFX9: error: invalid literal operand +// GFX9: error: literal operands are not supported v_pk_add_f16 v1, 0x1000ffff, v2 -// GFX9: error: invalid literal operand +// GFX9: error: literal operands are not supported v_pk_mad_i16 v5, 0x3c00, 0x4000, 0x4400 -// GFX9: error: invalid literal operand -// GFX10: error: invalid literal operand +// GFX9: error: literal operands are not supported +// GFX10: error: only one literal operand is allowed v_pk_mad_i16 v5, 0x3c00, 0x4000, 2 -// GFX9: error: invalid literal operand -// GFX10: error: invalid literal operand +// GFX9: error: literal operands are not supported +// GFX10: error: only one literal operand is allowed v_pk_mad_i16 v5, 0x3c00, 3, 2 -// GFX9: error: invalid literal operand +// GFX9: error: literal operands are not supported v_pk_mad_i16 v5, 3, 0x3c00, 2 -// GFX9: error: invalid literal operand +// GFX9: error: literal operands are not supported v_pk_mad_i16 v5, 3, 2, 0x3c00 -// GFX9: error: invalid literal operand +// GFX9: error: literal operands are not supported diff --git a/llvm/test/MC/AMDGPU/literalv216.s b/llvm/test/MC/AMDGPU/literalv216.s index ac05c280f0490..f55216619578d 100644 --- a/llvm/test/MC/AMDGPU/literalv216.s +++ b/llvm/test/MC/AMDGPU/literalv216.s @@ -161,35 +161,35 @@ v_pk_add_f16 v1, 65535, v2 //===----------------------------------------------------------------------===// v_pk_add_f16 v5, v1, 0x12345678 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_add_f16 v5, v1, 0x12345678 ; encoding: [0x05,0x00,0x0f,0xcc,0x01,0xff,0x01,0x18,0x78,0x56,0x34,0x12] v_pk_add_f16 v5, 0x12345678, v2 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_add_f16 v5, 0x12345678, v2 ; encoding: [0x05,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x78,0x56,0x34,0x12] v_pk_add_f16 v5, -256, v2 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_add_f16 v5, 0xffffff00, v2 ; encoding: [0x05,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x00,0xff,0xff,0xff] v_pk_add_f16 v5, v1, 256 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_add_f16 v5, v1, 0x100 ; encoding: [0x05,0x00,0x0f,0xcc,0x01,0xff,0x01,0x18,0x00,0x01,0x00,0x00] v_pk_add_u16 v5, v1, 0x12345678 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_add_u16 v5, v1, 0x12345678 ; encoding: [0x05,0x00,0x0a,0xcc,0x01,0xff,0x01,0x18,0x78,0x56,0x34,0x12] v_pk_add_u16 v5, 0x12345678, v2 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_add_u16 v5, 0x12345678, v2 ; encoding: [0x05,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x78,0x56,0x34,0x12] v_pk_add_u16 v5, -256, v2 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_add_u16 v5, 0xffffff00, v2 ; encoding: [0x05,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x00,0xff,0xff,0xff] v_pk_add_u16 v5, v1, 256 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_add_u16 v5, v1, 0x100 ; encoding: [0x05,0x00,0x0a,0xcc,0x01,0xff,0x01,0x18,0x00,0x01,0x00,0x00] v_pk_add_f16 v5, v1, 0x123456780 @@ -201,35 +201,35 @@ v_pk_add_u16 v5, v1, 0x123456780 // NOGFX10: error: invalid operand for instruction v_pk_fma_f16 v5, 0xaf123456, v2, v3 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_fma_f16 v5, 0xaf123456, v2, v3 ; encoding: [0x05,0x40,0x0e,0xcc,0xff,0x04,0x0e,0x1c,0x56,0x34,0x12,0xaf] v_pk_fma_f16 v5, v1, 0xaf123456, v3 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_fma_f16 v5, v1, 0xaf123456, v3 ; encoding: [0x05,0x40,0x0e,0xcc,0x01,0xff,0x0d,0x1c,0x56,0x34,0x12,0xaf] v_pk_fma_f16 v5, v1, v2, 0xaf123456 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_fma_f16 v5, v1, v2, 0xaf123456 ; encoding: [0x05,0x40,0x0e,0xcc,0x01,0x05,0xfe,0x1b,0x56,0x34,0x12,0xaf] v_pk_mad_i16 v5, 0xaf123456, v2, v3 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_mad_i16 v5, 0xaf123456, v2, v3 ; encoding: [0x05,0x40,0x00,0xcc,0xff,0x04,0x0e,0x1c,0x56,0x34,0x12,0xaf] v_pk_mad_i16 v5, v1, 0xaf123456, v3 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_mad_i16 v5, v1, 0xaf123456, v3 ; encoding: [0x05,0x40,0x00,0xcc,0x01,0xff,0x0d,0x1c,0x56,0x34,0x12,0xaf] v_pk_mad_i16 v5, v1, v2, 0xaf123456 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_mad_i16 v5, v1, v2, 0xaf123456 ; encoding: [0x05,0x40,0x00,0xcc,0x01,0x05,0xfe,0x1b,0x56,0x34,0x12,0xaf] v_pk_ashrrev_i16 v5, 0x12345678, v2 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_ashrrev_i16 v5, 0x12345678, v2 ; encoding: [0x05,0x00,0x06,0xcc,0xff,0x04,0x02,0x18,0x78,0x56,0x34,0x12] v_pk_ashrrev_i16 v5, v1, 0x12345678 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_ashrrev_i16 v5, v1, 0x12345678 ; encoding: [0x05,0x00,0x06,0xcc,0x01,0xff,0x01,0x18,0x78,0x56,0x34,0x12] //===----------------------------------------------------------------------===// @@ -237,35 +237,35 @@ v_pk_ashrrev_i16 v5, v1, 0x12345678 //===----------------------------------------------------------------------===// v_pk_add_f16 v5, v1, 0.1234 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_add_f16 v5, v1, 0x2fe6 ; encoding: [0x05,0x00,0x0f,0xcc,0x01,0xff,0x01,0x18,0xe6,0x2f,0x00,0x00] v_pk_add_u16 v5, v1, 0.1234 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_add_u16 v5, v1, 0x2fe6 ; encoding: [0x05,0x00,0x0a,0xcc,0x01,0xff,0x01,0x18,0xe6,0x2f,0x00,0x00] v_pk_fma_f16 v5, 0.1234, v2, v3 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_fma_f16 v5, 0x2fe6, v2, v3 ; encoding: [0x05,0x40,0x0e,0xcc,0xff,0x04,0x0e,0x1c,0xe6,0x2f,0x00,0x00] v_pk_fma_f16 v5, v1, 0.1234, v3 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_fma_f16 v5, v1, 0x2fe6, v3 ; encoding: [0x05,0x40,0x0e,0xcc,0x01,0xff,0x0d,0x1c,0xe6,0x2f,0x00,0x00] v_pk_fma_f16 v5, v1, v2, 0.1234 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_fma_f16 v5, v1, v2, 0x2fe6 ; encoding: [0x05,0x40,0x0e,0xcc,0x01,0x05,0xfe,0x1b,0xe6,0x2f,0x00,0x00] v_pk_mad_i16 v5, 0.1234, v2, v3 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_mad_i16 v5, 0x2fe6, v2, v3 ; encoding: [0x05,0x40,0x00,0xcc,0xff,0x04,0x0e,0x1c,0xe6,0x2f,0x00,0x00] v_pk_mad_i16 v5, v1, 0.1234, v3 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_mad_i16 v5, v1, 0x2fe6, v3 ; encoding: [0x05,0x40,0x00,0xcc,0x01,0xff,0x0d,0x1c,0xe6,0x2f,0x00,0x00] v_pk_mad_i16 v5, v1, v2, 0.1234 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // GFX10: v_pk_mad_i16 v5, v1, v2, 0x2fe6 ; encoding: [0x05,0x40,0x00,0xcc,0x01,0x05,0xfe,0x1b,0xe6,0x2f,0x00,0x00] v_pk_add_f16 v5, v1, 123456.0 diff --git a/llvm/test/MC/AMDGPU/mai-err.s b/llvm/test/MC/AMDGPU/mai-err.s index 32a7d8e186c88..5a1c6e7045a52 100644 --- a/llvm/test/MC/AMDGPU/mai-err.s +++ b/llvm/test/MC/AMDGPU/mai-err.s @@ -61,640 +61,640 @@ v_mfma_f32_32x32x1f32 a[0:31], v0, v1, 65 v_mfma_f32_32x32x1f32 a[0:31], v0, v1, 0 // GFX900: error: instruction not supported on this GPU -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand v_mfma_f32_32x32x1f32 a[0:31], v0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x1f32 a[0:31], v0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x1f32 a[0:31], v0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x1f32 a[0:31], v0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x1f32 a[0:31], a0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x1f32 a[0:31], a0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x1f32 a[0:31], a0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x1f32 a[0:31], a0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x1f32 a[0:15], v0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x1f32 a[0:15], v0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x1f32 a[0:15], v0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x1f32 a[0:15], v0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x1f32 a[0:15], a0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x1f32 a[0:15], a0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x1f32 a[0:15], a0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x1f32 a[0:15], a0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x1f32 a[0:3], v0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x1f32 a[0:3], v0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x1f32 a[0:3], v0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x1f32 a[0:3], v0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x1f32 a[0:3], a0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x1f32 a[0:3], a0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x1f32 a[0:3], a0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x1f32 a[0:3], a0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2f32 a[0:15], v0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2f32 a[0:15], v0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2f32 a[0:15], v0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2f32 a[0:15], v0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2f32 a[0:15], a0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2f32 a[0:15], a0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2f32 a[0:15], a0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2f32 a[0:15], a0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f32 a[0:3], v0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f32 a[0:3], v0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f32 a[0:3], v0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f32 a[0:3], v0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f32 a[0:3], a0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f32 a[0:3], a0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f32 a[0:3], a0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f32 a[0:3], a0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4f16 a[0:31], v[0:1], v[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4f16 a[0:31], v[0:1], v[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4f16 a[0:31], v[0:1], a[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4f16 a[0:31], v[0:1], a[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4f16 a[0:31], a[0:1], v[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4f16 a[0:31], a[0:1], v[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4f16 a[0:31], a[0:1], a[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4f16 a[0:31], a[0:1], a[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f16 a[0:15], v[0:1], v[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f16 a[0:15], v[0:1], v[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f16 a[0:15], v[0:1], a[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f16 a[0:15], v[0:1], a[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f16 a[0:15], a[0:1], v[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f16 a[0:15], a[0:1], v[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f16 a[0:15], a[0:1], a[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x4f16 a[0:15], a[0:1], a[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x4f16 a[0:3], v[0:1], v[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x4f16 a[0:3], v[0:1], v[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x4f16 a[0:3], v[0:1], a[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x4f16 a[0:3], v[0:1], a[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x4f16 a[0:3], a[0:1], v[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x4f16 a[0:3], a[0:1], v[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x4f16 a[0:3], a[0:1], a[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x4f16 a[0:3], a[0:1], a[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x8f16 a[0:15], v[0:1], v[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x8f16 a[0:15], v[0:1], v[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x8f16 a[0:15], v[0:1], a[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x8f16 a[0:15], v[0:1], a[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x8f16 a[0:15], a[0:1], v[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x8f16 a[0:15], a[0:1], v[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x8f16 a[0:15], a[0:1], a[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x8f16 a[0:15], a[0:1], a[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x16f16 a[0:3], v[0:1], v[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x16f16 a[0:3], v[0:1], v[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x16f16 a[0:3], v[0:1], a[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x16f16 a[0:3], v[0:1], a[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x16f16 a[0:3], a[0:1], v[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x16f16 a[0:3], a[0:1], v[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x16f16 a[0:3], a[0:1], a[1:2], -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x16f16 a[0:3], a[0:1], a[1:2], -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x4i8 a[0:31], v0, v1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x4i8 a[0:31], v0, v1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x4i8 a[0:31], v0, a1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x4i8 a[0:31], v0, a1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x4i8 a[0:31], a0, v1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x4i8 a[0:31], a0, v1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x4i8 a[0:31], a0, a1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x4i8 a[0:31], a0, a1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x4i8 a[0:15], v0, v1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x4i8 a[0:15], v0, v1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x4i8 a[0:15], v0, a1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x4i8 a[0:15], v0, a1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x4i8 a[0:15], a0, v1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x4i8 a[0:15], a0, v1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x4i8 a[0:15], a0, a1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x4i8 a[0:15], a0, a1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_4x4x4i8 a[0:3], v0, v1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_4x4x4i8 a[0:3], v0, v1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_4x4x4i8 a[0:3], v0, a1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_4x4x4i8 a[0:3], v0, a1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_4x4x4i8 a[0:3], a0, v1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_4x4x4i8 a[0:3], a0, v1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_4x4x4i8 a[0:3], a0, a1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_4x4x4i8 a[0:3], a0, a1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x8i8 a[0:15], v0, v1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x8i8 a[0:15], v0, v1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x8i8 a[0:15], v0, a1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x8i8 a[0:15], v0, a1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x8i8 a[0:15], a0, v1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x8i8 a[0:15], a0, v1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x8i8 a[0:15], a0, a1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_32x32x8i8 a[0:15], a0, a1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x16i8 a[0:3], v0, v1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x16i8 a[0:3], v0, v1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x16i8 a[0:3], v0, a1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x16i8 a[0:3], v0, a1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x16i8 a[0:3], a0, v1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x16i8 a[0:3], a0, v1, 2 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_i32_16x16x16i8 a[0:3], a0, a1, 2 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2bf16 a[0:31], v0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2bf16 a[0:31], v0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2bf16 a[0:31], v0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2bf16 a[0:31], v0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2bf16 a[0:31], a0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2bf16 a[0:31], a0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2bf16 a[0:31], a0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x2bf16 a[0:31], a0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x2bf16 a[0:15], v0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x2bf16 a[0:15], v0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x2bf16 a[0:15], v0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x2bf16 a[0:15], v0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x2bf16 a[0:15], a0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x2bf16 a[0:15], a0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x2bf16 a[0:15], a0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x2bf16 a[0:15], a0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x2bf16 a[0:3], v0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x2bf16 a[0:3], v0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x2bf16 a[0:3], v0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x2bf16 a[0:3], v0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x2bf16 a[0:3], a0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x2bf16 a[0:3], a0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x2bf16 a[0:3], a0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_4x4x2bf16 a[0:3], a0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4bf16 a[0:15], v0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4bf16 a[0:15], v0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4bf16 a[0:15], v0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4bf16 a[0:15], v0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4bf16 a[0:15], a0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4bf16 a[0:15], a0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4bf16 a[0:15], a0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_32x32x4bf16 a[0:15], a0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x8bf16 a[0:3], v0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x8bf16 a[0:3], v0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x8bf16 a[0:3], v0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x8bf16 a[0:3], v0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x8bf16 a[0:3], a0, v1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x8bf16 a[0:3], a0, v1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x8bf16 a[0:3], a0, a1, -2.0 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU v_mfma_f32_16x16x8bf16 a[0:3], a0, a1, -2.0 cbsz:3 abid:2 blgp:7 -// GFX908: error: invalid literal operand +// GFX908: error: inline constants are not allowed for this operand // GFX900: error: instruction not supported on this GPU diff --git a/llvm/test/MC/AMDGPU/vop2-err.s b/llvm/test/MC/AMDGPU/vop2-err.s index 526483b1f5c32..079e81d1e1248 100644 --- a/llvm/test/MC/AMDGPU/vop2-err.s +++ b/llvm/test/MC/AMDGPU/vop2-err.s @@ -6,7 +6,7 @@ //===----------------------------------------------------------------------===// v_mul_i32_i24 v1, v2, 100 -// CHECK: error: invalid literal operand +// CHECK: error: literal operands are not supported //===----------------------------------------------------------------------===// // _e32 checks @@ -29,11 +29,11 @@ v_cndmask_b32_e32 v1, v2, v3, s[0:1] // Immediate src0 v_mul_i32_i24_e64 v1, 100, v3 -// CHECK: error: invalid literal operand +// CHECK: error: literal operands are not supported // Immediate src1 v_mul_i32_i24_e64 v1, v2, 100 -// CHECK: error: invalid literal operand +// CHECK: error: literal operands are not supported v_add_i32_e32 v1, s[0:1], v2, v3 // CHECK: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/vop3-errs.s b/llvm/test/MC/AMDGPU/vop3-errs.s index 166e0a19e41e4..2d7d1a9937b29 100644 --- a/llvm/test/MC/AMDGPU/vop3-errs.s +++ b/llvm/test/MC/AMDGPU/vop3-errs.s @@ -7,7 +7,7 @@ v_add_f32_e64 v0, v1 // GCN: error: too few operands for instruction v_div_scale_f32 v24, vcc, v22, 1.1, v22 -// GCN: error: invalid literal operand +// GCN: error: literal operands are not supported v_mqsad_u32_u8 v[0:3], s[2:3], v4, v[0:3] // GFX67: error: instruction not supported on this GPU diff --git a/llvm/test/MC/AMDGPU/vop3-gfx9.s b/llvm/test/MC/AMDGPU/vop3-gfx9.s index 2414bf68cc150..f9fbd9cfb80a1 100644 --- a/llvm/test/MC/AMDGPU/vop3-gfx9.s +++ b/llvm/test/MC/AMDGPU/vop3-gfx9.s @@ -426,9 +426,9 @@ v_mad_i16 v5, v1, -1, v3 // VI: v_mad_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04] v_mad_i16 v5, v1, v2, -4.0 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // NOSICI: error: instruction not supported on this GPU -// NOVI: error: invalid literal operand +// NOVI: error: literal operands are not supported v_mad_i16 v5, v1, v2, v3 clamp // GFX9: v_mad_i16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x05,0xd2,0x01,0x05,0x0e,0x04] @@ -478,11 +478,11 @@ v_mad_legacy_i16 v5, v1, -1, v3 // NOGCN: error: instruction not supported on this GPU v_mad_legacy_i16 v5, v1, v2, -4.0 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // NOGCN: error: instruction not supported on this GPU v_mad_legacy_i16 v5, v1, v2, -4.0 clamp -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // NOGCN: error: instruction not supported on this GPU v_mad_legacy_u16_e64 v5, 0, v2, v3 @@ -494,11 +494,11 @@ v_mad_legacy_u16 v5, v1, -1, v3 // NOGCN: error: instruction not supported on this GPU v_mad_legacy_u16 v5, v1, v2, -4.0 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // NOGCN: error: instruction not supported on this GPU v_mad_legacy_u16 v5, v1, v2, -4.0 clamp -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // NOGCN: error: instruction not supported on this GPU v_mad_u16_e64 v5, 0, v2, v3 @@ -512,9 +512,9 @@ v_mad_u16 v5, v1, -1, v3 // VI: v_mad_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04] v_mad_u16 v5, v1, v2, -4.0 -// NOGFX9: error: invalid literal operand +// NOGFX9: error: literal operands are not supported // NOSICI: error: instruction not supported on this GPU -// NOVI: error: invalid literal operand +// NOVI: error: literal operands are not supported v_mad_u16 v5, v1, v2, v3 clamp // GFX9: v_mad_u16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04] diff --git a/llvm/test/MC/AMDGPU/vop3-literal.s b/llvm/test/MC/AMDGPU/vop3-literal.s index b3458a99af43d..76bae508656ba 100644 --- a/llvm/test/MC/AMDGPU/vop3-literal.s +++ b/llvm/test/MC/AMDGPU/vop3-literal.s @@ -5,91 +5,91 @@ v_bfe_u32 v0, 0x3039, v1, s1 // GFX10: v_bfe_u32 v0, 0x3039, v1, s1 ; encoding: [0x00,0x00,0x48,0xd5,0xff,0x02,0x06,0x00,0x39,0x30,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_bfe_u32 v0, v1, 0x3039, s1 // GFX10: v_bfe_u32 v0, v1, 0x3039, s1 ; encoding: [0x00,0x00,0x48,0xd5,0x01,0xff,0x05,0x00,0x39,0x30,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_bfe_u32 v0, v1, s1, 0x3039 // GFX10: v_bfe_u32 v0, v1, s1, 0x3039 ; encoding: [0x00,0x00,0x48,0xd5,0x01,0x03,0xfc,0x03,0x39,0x30,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_bfe_u32 v0, 0x3039, 0x3039, s1 // GFX10: v_bfe_u32 v0, 0x3039, 0x3039, s1 ; encoding: [0x00,0x00,0x48,0xd5,0xff,0xfe,0x05,0x00,0x39,0x30,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_bfe_u32 v0, 0x3039, s1, 0x3039 // GFX10: v_bfe_u32 v0, 0x3039, s1, 0x3039 ; encoding: [0x00,0x00,0x48,0xd5,0xff,0x02,0xfc,0x03,0x39,0x30,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_bfe_u32 v0, v1, 0x3039, 0x3039 // GFX10: v_bfe_u32 v0, v1, 0x3039, 0x3039 ; encoding: [0x00,0x00,0x48,0xd5,0x01,0xff,0xfd,0x03,0x39,0x30,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_bfe_u32 v0, 0x3039, 0x3039, 0x3039 // GFX10: v_bfe_u32 v0, 0x3039, 0x3039, 0x3039 ; encoding: [0x00,0x00,0x48,0xd5,0xff,0xfe,0xfd,0x03,0x39,0x30,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_bfe_u32 v0, 0x3039, s1, 0x3038 -// GFX10-ERR: error: invalid literal operand -// GFX9-ERR: error: invalid literal operand +// GFX10-ERR: error: only one literal operand is allowed +// GFX9-ERR: error: literal operands are not supported v_bfe_u32 v0, 0x3039, v1, v2 // GFX10: v_bfe_u32 v0, 0x3039, v1, v2 ; encoding: [0x00,0x00,0x48,0xd5,0xff,0x02,0x0a,0x04,0x39,0x30,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_bfe_u32 v0, 0x3039, 0x12345, v2 -// GFX10-ERR: error: invalid literal operand -// GFX9-ERR: error: invalid literal operand +// GFX10-ERR: error: only one literal operand is allowed +// GFX9-ERR: error: literal operands are not supported v_bfe_u32 v0, s1, 0x3039, s1 -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported // GFX10: v_bfe_u32 v0, s1, 0x3039, s1 ; encoding: [0x00,0x00,0x48,0xd5,0x01,0xfe,0x05,0x00,0x39,0x30,0x00,0x00] v_bfe_u32 v0, s1, 0x3039, s2 -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported // GFX10-ERR: error: invalid operand (violates constant bus restrictions) v_bfm_b32_e64 v0, 0x3039, s1 // GFX10: v_bfm_b32_e64 v0, 0x3039, s1 ; encoding: [0x00,0x00,0x63,0xd7,0xff,0x02,0x00,0x00,0x39,0x30,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_bfm_b32_e64 v0, 0x3039, v1 // GFX10: v_bfm_b32_e64 v0, 0x3039, v1 ; encoding: [0x00,0x00,0x63,0xd7,0xff,0x02,0x02,0x00,0x39,0x30,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_bfm_b32_e64 v0, 0x3039, 0x3039 // GFX10: v_bfm_b32_e64 v0, 0x3039, 0x3039 ; encoding: [0x00,0x00,0x63,0xd7,0xff,0xfe,0x01,0x00,0x39,0x30,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_bfm_b32_e64 v0, 0x3039, 0x3038 -// GFX10-ERR: error: invalid literal operand -// GFX9-ERR: error: invalid literal operand +// GFX10-ERR: error: only one literal operand is allowed +// GFX9-ERR: error: literal operands are not supported v_pk_add_f16 v1, 25.0, v2 // GFX10: v_pk_add_f16 v1, 0x4e40, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x40,0x4e,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_f16 v1, 123456, v2 // GFX10: v_pk_add_f16 v1, 0x1e240, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x40,0xe2,0x01,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_f16 v1, -200, v2 // GFX10: v_pk_add_f16 v1, 0xffffff38, v2 ; encoding: [0x01,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x38,0xff,0xff,0xff] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_f16 v1, 25.0, 25.0 // GFX10: v_pk_add_f16 v1, 0x4e40, 0x4e40 ; encoding: [0x01,0x00,0x0f,0xcc,0xff,0xfe,0x01,0x18,0x40,0x4e,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_f16 v1, 25.0, 25.1 -// GFX10-ERR: error: invalid literal operand -// GFX9-ERR: error: invalid literal operand +// GFX10-ERR: error: only one literal operand is allowed +// GFX9-ERR: error: literal operands are not supported v_pk_add_u16 v1, -200, v2 // GFX10: v_pk_add_u16 v1, 0xffffff38, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x38,0xff,0xff,0xff] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_u16 v1, 64, v2 // GFX10: v_pk_add_u16 v1, 64, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xc0,0x04,0x02,0x18] @@ -97,7 +97,7 @@ v_pk_add_u16 v1, 64, v2 v_pk_add_u16 v1, 65, v2 // GFX10: v_pk_add_u16 v1, 0x41, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x41,0x00,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_u16 v1, -1, v2 // GFX10: v_pk_add_u16 v1, -1, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xc1,0x04,0x02,0x18] @@ -109,91 +109,91 @@ v_pk_add_u16 v1, -5, v2 v_pk_add_u16 v1, -100, v2 // GFX10: v_pk_add_u16 v1, 0xffffff9c, v2 ; encoding: [0x01,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x9c,0xff,0xff,0xff] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_u16 v1, -100, -100 // GFX10: v_pk_add_u16 v1, 0xffffff9c, 0xffffff9c ; encoding: [0x01,0x00,0x0a,0xcc,0xff,0xfe,0x01,0x18,0x9c,0xff,0xff,0xff] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_add_f32_e64 v1, neg(abs(0x123)), v3 // GFX10: v_add_f32_e64 v1, -|0x123|, v3 ; encoding: [0x01,0x01,0x03,0xd5,0xff,0x06,0x02,0x20,0x23,0x01,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_add_f32_e64 v1, v3, neg(0x123) // GFX10: v_add_f32_e64 v1, v3, neg(0x123) ; encoding: [0x01,0x00,0x03,0xd5,0x03,0xff,0x01,0x40,0x23,0x01,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_add_f32_e64 v1, neg(abs(0x12345678)), neg(0x12345678) // GFX10: v_add_f32_e64 v1, -|0x12345678|, neg(0x12345678) ; encoding: [0x01,0x01,0x03,0xd5,0xff,0xfe,0x01,0x60,0x78,0x56,0x34,0x12] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_add_f16_e64 v0, v0, 0xfe0b // GFX10: v_add_f16_e64 v0, v0, 0xfe0b ; encoding: [0x00,0x00,0x32,0xd5,0x00,0xff,0x01,0x00,0x0b,0xfe,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_add_f16_e64 v0, v0, neg(0xfe0b) // GFX10: v_add_f16_e64 v0, v0, neg(0xfe0b) ; encoding: [0x00,0x00,0x32,0xd5,0x00,0xff,0x01,0x40,0x0b,0xfe,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_add_f16_e64 v0, 0x3456, v0 // GFX10: v_add_f16_e64 v0, 0x3456, v0 ; encoding: [0x00,0x00,0x32,0xd5,0xff,0x00,0x02,0x00,0x56,0x34,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_add_f16_e64 v0, 0xfe0b, neg(0xfe0b) // GFX10: v_add_f16_e64 v0, 0xfe0b, neg(0xfe0b) ; encoding: [0x00,0x00,0x32,0xd5,0xff,0xfe,0x01,0x40,0x0b,0xfe,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_add_f64 v[0:1], 1.23456, v[0:1] // GFX10: v_add_f64 v[0:1], 0x3ff3c0c1, v[0:1] ; encoding: [0x00,0x00,0x64,0xd5,0xff,0x00,0x02,0x00,0xc1,0xc0,0xf3,0x3f] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_add_f64 v[0:1], v[0:1], -abs(1.23456) // GFX10: v_add_f64 v[0:1], v[0:1], -|0x3ff3c0c1| ; encoding: [0x00,0x02,0x64,0xd5,0x00,0xff,0x01,0x40,0xc1,0xc0,0xf3,0x3f] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_add_f64 v[0:1], 1.23456, -abs(1.23456) // GFX10: v_add_f64 v[0:1], 0x3ff3c0c1, -|0x3ff3c0c1| ; encoding: [0x00,0x02,0x64,0xd5,0xff,0xfe,0x01,0x40,0xc1,0xc0,0xf3,0x3f] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_add_f64 v[0:1], 1.23456, -abs(1.2345) -// GFX10-ERR: error: invalid literal operand -// GFX9-ERR: error: invalid literal operand +// GFX10-ERR: error: only one literal operand is allowed +// GFX9-ERR: error: literal operands are not supported v_max_i16_e64 v5, 0xfe0b, v2 // GFX10: v_max_i16_e64 v5, 0xfe0b, v2 ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0x04,0x02,0x00,0x0b,0xfe,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_max_i16_e64 v5, v1, 0x123 // GFX10: v_max_i16_e64 v5, v1, 0x123 ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x01,0x00,0x23,0x01,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_max_i16_e64 v5, 0x1234, 0x1234 // GFX10: v_max_i16_e64 v5, 0x1234, 0x1234 ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0xfe,0x01,0x00,0x34,0x12,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_min3_i16 v5, 0xfe0b, v2, v3 // GFX10: v_min3_i16 v5, 0xfe0b, v2, v3 ; encoding: [0x05,0x00,0x52,0xd7,0xff,0x04,0x0e,0x04,0x0b,0xfe,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_min3_i16 v5, v1, 0x1234, v3 // GFX10: v_min3_i16 v5, v1, 0x1234, v3 ; encoding: [0x05,0x00,0x52,0xd7,0x01,0xff,0x0d,0x04,0x34,0x12,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_min3_i16 v5, v1, v2, 0x5678 // GFX10: v_min3_i16 v5, v1, v2, 0x5678 ; encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xfe,0x03,0x78,0x56,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_min3_i16 v5, 0x5678, 0x5678, 0x5678 // GFX10: v_min3_i16 v5, 0x5678, 0x5678, 0x5678 ; encoding: [0x05,0x00,0x52,0xd7,0xff,0xfe,0xfd,0x03,0x78,0x56,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_min3_i16 v5, 0x5678, 0x5679, 0x5678 -// GFX10-ERR: error: invalid literal operand -// GFX9-ERR: error: invalid literal operand +// GFX10-ERR: error: only one literal operand is allowed +// GFX9-ERR: error: literal operands are not supported v_min3_i16 v5, 0x5678, 0x5678, 0x5679 -// GFX10-ERR: error: invalid literal operand -// GFX9-ERR: error: invalid literal operand +// GFX10-ERR: error: only one literal operand is allowed +// GFX9-ERR: error: literal operands are not supported v_add_nc_u16 v5, 0xfe0b, v2 // GFX10: v_add_nc_u16_e64 v5, 0xfe0b, v2 ; encoding: [0x05,0x00,0x03,0xd7,0xff,0x04,0x02,0x00,0x0b,0xfe,0x00,0x00] @@ -209,67 +209,67 @@ v_add_nc_u16 v5, 0x1234, 0x1234 v_ashrrev_i16_e64 v5, 0x3456, v2 // GFX10: v_ashrrev_i16_e64 v5, 0x3456, v2 ; encoding: [0x05,0x00,0x08,0xd7,0xff,0x04,0x02,0x00,0x56,0x34,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_mad_u16 v5, 0xfe0b, v2, v3 // GFX10: v_mad_u16 v5, 0xfe0b, v2, v3 ; encoding: [0x05,0x00,0x40,0xd7,0xff,0x04,0x0e,0x04,0x0b,0xfe,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_mad_u16 v5, v1, 0x1234, v3 // GFX10: v_mad_u16 v5, v1, 0x1234, v3 ; encoding: [0x05,0x00,0x40,0xd7,0x01,0xff,0x0d,0x04,0x34,0x12,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_mad_u16 v5, v1, v2, 0x5678 // GFX10: v_mad_u16 v5, v1, v2, 0x5678 ; encoding: [0x05,0x00,0x40,0xd7,0x01,0x05,0xfe,0x03,0x78,0x56,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_mad_u16 v5, 0x5678, 0x5678, 0x5678 // GFX10: v_mad_u16 v5, 0x5678, 0x5678, 0x5678 ; encoding: [0x05,0x00,0x40,0xd7,0xff,0xfe,0xfd,0x03,0x78,0x56,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_mad_legacy_f32 v5, 0xaf123456, v2, v3 // GFX10: v_mad_legacy_f32 v5, 0xaf123456, v2, v3 ; encoding: [0x05,0x00,0x40,0xd5,0xff,0x04,0x0e,0x04,0x56,0x34,0x12,0xaf] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_mad_legacy_f32 v5, v1, 0xaf123456, v3 // GFX10: v_mad_legacy_f32 v5, v1, 0xaf123456, v3 ; encoding: [0x05,0x00,0x40,0xd5,0x01,0xff,0x0d,0x04,0x56,0x34,0x12,0xaf] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_mad_legacy_f32 v5, v1, v2, 0xaf123456 // GFX10: v_mad_legacy_f32 v5, v1, v2, 0xaf123456 ; encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xfe,0x03,0x56,0x34,0x12,0xaf] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_mad_legacy_f32 v5, 0xaf123456, 0xaf123456, 0xaf123456 // GFX10: v_mad_legacy_f32 v5, 0xaf123456, 0xaf123456, 0xaf123456 ; encoding: [0x05,0x00,0x40,0xd5,0xff,0xfe,0xfd,0x03,0x56,0x34,0x12,0xaf] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_cmp_f_i32_e64 s[10:11], 0xaf123456, v2 // GFX10: v_cmp_f_i32_e64 s[10:11], 0xaf123456, v2 ; encoding: [0x0a,0x00,0x80,0xd4,0xff,0x04,0x02,0x00,0x56,0x34,0x12,0xaf] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_cmp_f_i32_e64 s[10:11], v1, 0xaf123456 // GFX10: v_cmp_f_i32_e64 s[10:11], v1, 0xaf123456 ; encoding: [0x0a,0x00,0x80,0xd4,0x01,0xff,0x01,0x00,0x56,0x34,0x12,0xaf] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_cmp_f_i32_e64 s[10:11], 0xaf123456, 0xaf123456 // GFX10: v_cmp_f_i32_e64 s[10:11], 0xaf123456, 0xaf123456 ; encoding: [0x0a,0x00,0x80,0xd4,0xff,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_cmp_f_i32_e64 s[10:11], 0xaf123456, 0xaf123455 -// GFX10-ERR: error: invalid literal operand -// GFX9-ERR: error: invalid literal operand +// GFX10-ERR: error: only one literal operand is allowed +// GFX9-ERR: error: literal operands are not supported v_cmp_f_u64_e64 s[10:11], 0xaf123456, v[2:3] // GFX10: v_cmp_f_u64_e64 s[10:11], 0xaf123456, v[2:3] ; encoding: [0x0a,0x00,0xe0,0xd4,0xff,0x04,0x02,0x00,0x56,0x34,0x12,0xaf] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_cmp_f_u64_e64 s[10:11], v[1:2], 0x3f717273 // GFX10: v_cmp_f_u64_e64 s[10:11], v[1:2], 0x3f717273 ; encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xff,0x01,0x00,0x73,0x72,0x71,0x3f] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_cmp_f_u64_e64 s[10:11], 0x3f717273, 0x3f717273 // GFX10: v_cmp_f_u64_e64 s[10:11], 0x3f717273, 0x3f717273 ; encoding: [0x0a,0x00,0xe0,0xd4,0xff,0xfe,0x01,0x00,0x73,0x72,0x71,0x3f] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_cmpx_class_f32_e64 0xaf123456, v2 // GFX10: v_cmpx_class_f32_e64 0xaf123456, v2 ; encoding: [0x00,0x00,0x98,0xd4,0xff,0x04,0x02,0x00,0x56,0x34,0x12,0xaf] @@ -284,7 +284,7 @@ v_cmpx_class_f32_e64 0xaf123456, 0xaf123456 // GFX9-ERR: error: operands are not valid for this GPU or mode v_cmpx_class_f32_e64 0xaf123456, 0xaf123455 -// GFX10-ERR: error: invalid literal operand +// GFX10-ERR: error: only one literal operand is allowed // GFX9-ERR: error: operands are not valid for this GPU or mode v_cmpx_lt_i16_e64 v1, 0x3456 @@ -313,11 +313,11 @@ v_cmpx_f_i64_e64 0x3f717273, 0x3f717273 v_lshlrev_b64 v[5:6], 0xaf123456, v[2:3] // GFX10: v_lshlrev_b64 v[5:6], 0xaf123456, v[2:3] ; encoding: [0x05,0x00,0xff,0xd6,0xff,0x04,0x02,0x00,0x56,0x34,0x12,0xaf] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_lshlrev_b64 v[5:6], v1, 0x3f717273 // GFX10: v_lshlrev_b64 v[5:6], v1, 0x3f717273 ; encoding: [0x05,0x00,0xff,0xd6,0x01,0xff,0x01,0x00,0x73,0x72,0x71,0x3f] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_fma_mix_f32 v5, 0x123, v2, v3 // GFX10: v_fma_mix_f32 v5, 0x123, v2, v3 ; encoding: [0x05,0x00,0x20,0xcc,0xff,0x04,0x0e,0x04,0x23,0x01,0x00,0x00] @@ -341,64 +341,64 @@ v_fma_mix_f32 v5, 0x1c8a, 0x1c8a, 0x1c8a v_pk_add_f16 v5, 0xaf123456, v2 // GFX10: v_pk_add_f16 v5, 0xaf123456, v2 ; encoding: [0x05,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x56,0x34,0x12,0xaf] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_f16 v5, v1, 0x3f717273 // GFX10: v_pk_add_f16 v5, v1, 0x3f717273 ; encoding: [0x05,0x00,0x0f,0xcc,0x01,0xff,0x01,0x18,0x73,0x72,0x71,0x3f] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_f16 v5, 0x3f717273, 0x3f717273 // GFX10: v_pk_add_f16 v5, 0x3f717273, 0x3f717273 ; encoding: [0x05,0x00,0x0f,0xcc,0xff,0xfe,0x01,0x18,0x73,0x72,0x71,0x3f] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_i16 v5, 0x7b, v2 // GFX10: v_pk_add_i16 v5, 0x7b, v2 ; encoding: [0x05,0x00,0x02,0xcc,0xff,0x04,0x02,0x18,0x7b,0x00,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_i16 v5, v1, 0x7b // GFX10: v_pk_add_i16 v5, v1, 0x7b ; encoding: [0x05,0x00,0x02,0xcc,0x01,0xff,0x01,0x18,0x7b,0x00,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_i16 v5, 0xab7b, 0xab7b // GFX10: v_pk_add_i16 v5, 0xab7b, 0xab7b ; encoding: [0x05,0x00,0x02,0xcc,0xff,0xfe,0x01,0x18,0x7b,0xab,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_pk_add_i16 v5, 0xab7b, 0xab7a -// GFX10-ERR: error: invalid literal operand -// GFX9-ERR: error: invalid literal operand +// GFX10-ERR: error: only one literal operand is allowed +// GFX9-ERR: error: literal operands are not supported v_div_fmas_f32 v5, v1, 0x123, v3 // GFX10: v_div_fmas_f32 v5, v1, 0x123, v3 ; encoding: [0x05,0x00,0x6f,0xd5,0x01,0xff,0x0d,0x04,0x23,0x01,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_div_fmas_f32 v5, v1, 0x123, 0x123 // GFX10: v_div_fmas_f32 v5, v1, 0x123, 0x123 ; encoding: [0x05,0x00,0x6f,0xd5,0x01,0xff,0xfd,0x03,0x23,0x01,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_div_fmas_f32 v5, 0x123, 0x123, 0x123 // GFX10: v_div_fmas_f32 v5, 0x123, 0x123, 0x123 ; encoding: [0x05,0x00,0x6f,0xd5,0xff,0xfe,0xfd,0x03,0x23,0x01,0x00,0x00] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_div_fmas_f64 v[5:6], 0x12345678, v[2:3], v[3:4] // GFX10: v_div_fmas_f64 v[5:6], 0x12345678, v[2:3], v[3:4] ; encoding: [0x05,0x00,0x70,0xd5,0xff,0x04,0x0e,0x04,0x78,0x56,0x34,0x12] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_div_fmas_f64 v[5:6], 0x12345678, 0x12345678, 0x12345678 // GFX10: v_div_fmas_f64 v[5:6], 0x12345678, 0x12345678, 0x12345678 ; encoding: [0x05,0x00,0x70,0xd5,0xff,0xfe,0xfd,0x03,0x78,0x56,0x34,0x12] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_div_fmas_f64 v[5:6], v[1:2], 0x123457, 0x123456 -// GFX10-ERR: error: invalid literal operand -// GFX9-ERR: error: invalid literal operand +// GFX10-ERR: error: only one literal operand is allowed +// GFX9-ERR: error: literal operands are not supported v_ldexp_f64 v[5:6], 0.12345, v2 // GFX10: v_ldexp_f64 v[5:6], 0x3fbf9a6b, v2 ; encoding: [0x05,0x00,0x68,0xd5,0xff,0x04,0x02,0x00,0x6b,0x9a,0xbf,0x3f] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_ldexp_f64 v[5:6], 0.12345, 0x3fbf9a6b // GFX10: v_ldexp_f64 v[5:6], 0x3fbf9a6b, 0x3fbf9a6b ; encoding: [0x05,0x00,0x68,0xd5,0xff,0xfe,0x01,0x00,0x6b,0x9a,0xbf,0x3f] -// GFX9-ERR: error: invalid literal operand +// GFX9-ERR: error: literal operands are not supported v_ldexp_f64 v[5:6], 0.12345, 0x3fbf9a6c -// GFX10-ERR: error: invalid literal operand -// GFX9-ERR: error: invalid literal operand +// GFX10-ERR: error: only one literal operand is allowed +// GFX9-ERR: error: literal operands are not supported diff --git a/llvm/test/MC/AMDGPU/vop3.s b/llvm/test/MC/AMDGPU/vop3.s index eb11d6e0bffd1..5b9b4231e5f11 100644 --- a/llvm/test/MC/AMDGPU/vop3.s +++ b/llvm/test/MC/AMDGPU/vop3.s @@ -599,7 +599,7 @@ v_mad_i16_e64 v5, -1, v2, v3 // NOSICI: error: instruction not supported on this GPU v_mad_i16 v5, v1, -4.0, v3 -// NOVI: error: invalid literal operand +// NOVI: error: literal operands are not supported // NOSICI: error: instruction not supported on this GPU v_mad_i16 v5, v1, v2, 0 @@ -615,7 +615,7 @@ v_mad_u16 v5, v1, 0, v3 // NOSICI: error: instruction not supported on this GPU v_mad_u16 v5, v1, v2, -4.0 -// NOVI: error: invalid literal operand +// NOVI: error: literal operands are not supported // NOSICI: error: instruction not supported on this GPU ///===---------------------------------------------------------------------===// diff --git a/llvm/test/MC/ARM/armv8.2a-dotprod-a32.s b/llvm/test/MC/ARM/armv8.2a-dotprod-a32.s index 8ca2a97c602dc..5c574538ff2a0 100644 --- a/llvm/test/MC/ARM/armv8.2a-dotprod-a32.s +++ b/llvm/test/MC/ARM/armv8.2a-dotprod-a32.s @@ -3,6 +3,7 @@ // RUN: llvm-mc -triple arm -mcpu=cortex-a75 -show-encoding < %s | FileCheck %s --check-prefix=CHECK // RUN: llvm-mc -triple arm -mcpu=cortex-a76 -show-encoding < %s | FileCheck %s --check-prefix=CHECK // RUN: llvm-mc -triple arm -mcpu=neoverse-n1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK +// RUN: llvm-mc -triple arm -mcpu=neoverse-n2 -show-encoding < %s | FileCheck %s --check-prefix=CHECK // RUN: llvm-mc -triple arm -mcpu=cortex-a77 -show-encoding < %s | FileCheck %s --check-prefix=CHECK // RUN: llvm-mc -triple arm -mcpu=cortex-a78 -show-encoding < %s | FileCheck %s --check-prefix=CHECK // RUN: llvm-mc -triple arm -mcpu=cortex-x1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK diff --git a/llvm/test/MC/ARM/armv8.2a-dotprod-t32.s b/llvm/test/MC/ARM/armv8.2a-dotprod-t32.s index 8570a7be3150e..83f5b7807ddc9 100644 --- a/llvm/test/MC/ARM/armv8.2a-dotprod-t32.s +++ b/llvm/test/MC/ARM/armv8.2a-dotprod-t32.s @@ -6,6 +6,7 @@ // RUN: llvm-mc -triple thumb -mcpu=cortex-a78 -show-encoding < %s | FileCheck %s --check-prefix=CHECK // RUN: llvm-mc -triple thumb -mcpu=cortex-x1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK // RUN: llvm-mc -triple thumb -mcpu=neoverse-n1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK +// RUN: llvm-mc -triple thumb -mcpu=neoverse-n2 -show-encoding < %s | FileCheck %s --check-prefix=CHECK // RUN: not llvm-mc -triple thumb -mattr=-dotprod -show-encoding < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s diff --git a/llvm/test/MC/ARM/tMOVSr.s b/llvm/test/MC/ARM/tMOVSr.s new file mode 100644 index 0000000000000..198c90aa5ceb4 --- /dev/null +++ b/llvm/test/MC/ARM/tMOVSr.s @@ -0,0 +1,6 @@ +@ REQUIRES: asserts +@ RUN: llvm-mc --triple=thumbv8 --debug %s 2>&1 | FileCheck %s --match-full-lines + +@ CHECK: Changed to: > +.text + movs r2, r3 diff --git a/llvm/test/MC/AsmParser/include.ll b/llvm/test/MC/AsmParser/include.ll index 28561819a6039..51e9c88bc6492 100644 --- a/llvm/test/MC/AsmParser/include.ll +++ b/llvm/test/MC/AsmParser/include.ll @@ -3,7 +3,7 @@ module asm ".include \22module.x\22" -define arm_aapcscc void @f() { +define void @f() { entry: call void asm sideeffect ".include \22function.x\22", ""() ret void diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt b/llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt index 8b0aac5269990..c356895bb5356 100644 --- a/llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt +++ b/llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt @@ -9,6 +9,7 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=cortex-x1 --disassemble < %s | FileCheck %s # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-e1 --disassemble < %s | FileCheck %s # RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n1 --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s # CHECK: ldaprb w0, [x0] # CHECK: ldaprh w0, [x0] diff --git a/llvm/test/MC/WebAssembly/assembler-binary.ll b/llvm/test/MC/WebAssembly/assembler-binary.ll index 4d57ed3f212ce..e3a9a1b76a231 100644 --- a/llvm/test/MC/WebAssembly/assembler-binary.ll +++ b/llvm/test/MC/WebAssembly/assembler-binary.ll @@ -52,14 +52,6 @@ entry: ; CHECK-NEXT: Memory: ; CHECK-NEXT: Initial: 0x0 ; CHECK-NEXT: - Module: env -; CHECK-NEXT: Field: __indirect_function_table -; CHECK-NEXT: Kind: TABLE -; CHECK-NEXT: Table: -; CHECK-NEXT: Index: 0 -; CHECK-NEXT: ElemType: FUNCREF -; CHECK-NEXT: Limits: -; CHECK-NEXT: Initial: 0x0 -; CHECK-NEXT: - Module: env ; CHECK-NEXT: Field: bar ; CHECK-NEXT: Kind: FUNCTION ; CHECK-NEXT: SigIndex: 1 diff --git a/llvm/test/MC/WebAssembly/comdat.ll b/llvm/test/MC/WebAssembly/comdat.ll index 0e7ac4af3a61d..f7809e859ef67 100644 --- a/llvm/test/MC/WebAssembly/comdat.ll +++ b/llvm/test/MC/WebAssembly/comdat.ll @@ -39,14 +39,6 @@ define linkonce_odr i32 @sharedFn() #1 comdat($sharedComdat) { ; CHECK-NEXT: Memory: ; CHECK-NEXT: Initial: 0x1 ; CHECK-NEXT: - Module: env -; CHECK-NEXT: Field: __indirect_function_table -; CHECK-NEXT: Kind: TABLE -; CHECK-NEXT: Table: -; CHECK-NEXT: Index: 0 -; CHECK-NEXT: ElemType: FUNCREF -; CHECK-NEXT: Limits: -; CHECK-NEXT: Initial: 0x0 -; CHECK-NEXT: - Module: env ; CHECK-NEXT: Field: funcImport ; CHECK-NEXT: Kind: FUNCTION ; CHECK-NEXT: SigIndex: 0 diff --git a/llvm/test/MC/WebAssembly/custom-sections.ll b/llvm/test/MC/WebAssembly/custom-sections.ll index d92399947cb1f..cf2d7098ae4b1 100644 --- a/llvm/test/MC/WebAssembly/custom-sections.ll +++ b/llvm/test/MC/WebAssembly/custom-sections.ll @@ -15,18 +15,18 @@ target triple = "wasm32-unknown-unknown" ; CHECK: Section { ; CHECK: Type: CUSTOM (0x0) ; CHECK: Size: 3 -; CHECK: Offset: 72 +; CHECK: Offset: 38 ; CHECK: Name: red ; CHECK: } ; CHECK: Section { ; CHECK: Type: CUSTOM (0x0) ; CHECK: Size: 6 -; CHECK: Offset: 85 +; CHECK: Offset: 51 ; CHECK: Name: green ; CHECK: } ; CHECK: Section { ; CHECK: Type: CUSTOM (0x0) ; CHECK: Size: 25 -; CHECK: Offset: 118 +; CHECK: Offset: 84 ; CHECK: Name: producers ; CHECK: } diff --git a/llvm/test/MC/WebAssembly/data-section.s b/llvm/test/MC/WebAssembly/data-section.s index 31154cf3164dd..36427603120d8 100644 --- a/llvm/test/MC/WebAssembly/data-section.s +++ b/llvm/test/MC/WebAssembly/data-section.s @@ -45,14 +45,6 @@ test0: # BIN-NEXT: Kind: MEMORY # BIN-NEXT: Memory: # BIN-NEXT: Initial: 0x1 -# BIN-NEXT: - Module: env -# BIN-NEXT: Field: __indirect_function_table -# BIN-NEXT: Kind: TABLE -# BIN-NEXT: Table: -# BIN-NEXT: Index: 0 -# BIN-NEXT: ElemType: FUNCREF -# BIN-NEXT: Limits: -# BIN-NEXT: Initial: 0x0 # BIN-NEXT: - Type: FUNCTION # BIN-NEXT: FunctionTypes: [ 0 ] # BIN-NEXT: - Type: DATACOUNT diff --git a/llvm/test/MC/WebAssembly/event-section.ll b/llvm/test/MC/WebAssembly/event-section.ll index e81f687d7100b..96487e88f935e 100644 --- a/llvm/test/MC/WebAssembly/event-section.ll +++ b/llvm/test/MC/WebAssembly/event-section.ll @@ -56,4 +56,4 @@ define i32 @test_throw1(i8* %p) { ; SEC: Type: EVENT (0xD) ; SEC-NEXT: Size: 3 -; SEC-NEXT: Offset: 97 +; SEC-NEXT: Offset: 63 diff --git a/llvm/test/MC/WebAssembly/external-func-address.ll b/llvm/test/MC/WebAssembly/external-func-address.ll index 3c59eaa701afa..5481a4b1e7f8f 100644 --- a/llvm/test/MC/WebAssembly/external-func-address.ll +++ b/llvm/test/MC/WebAssembly/external-func-address.ll @@ -42,8 +42,6 @@ define void @call(i32) { ; CHECK: - Module: env ; CHECK-NEXT: Field: __linear_memory ; CHECK: - Module: env -; CHECK-NEXT: Field: __indirect_function_table -; CHECK: - Module: env ; CHECK-NEXT: Field: varargs ; CHECK-NEXT: Kind: FUNCTION ; CHECK-NEXT: SigIndex: 1 @@ -53,6 +51,8 @@ define void @call(i32) { ; CHECK-NEXT: Field: f1 ; CHECK-NEXT: Kind: FUNCTION ; CHECK-NEXT: SigIndex: 0 +; CHECK: - Module: env +; CHECK-NEXT: Field: __indirect_function_table ; CHECK: - Type: ELEM ; CHECK-NEXT: Segments: ; CHECK-NEXT: - Offset: diff --git a/llvm/test/MC/WebAssembly/global-ctor-dtor.ll b/llvm/test/MC/WebAssembly/global-ctor-dtor.ll index 6cd7fe636fe21..5f56cb6e280dc 100644 --- a/llvm/test/MC/WebAssembly/global-ctor-dtor.ll +++ b/llvm/test/MC/WebAssembly/global-ctor-dtor.ll @@ -27,14 +27,6 @@ declare void @func3() ; CHECK-NEXT: Memory: ; CHECK-NEXT: Initial: 0x1 ; CHECK-NEXT: - Module: env -; CHECK-NEXT: Field: __indirect_function_table -; CHECK-NEXT: Kind: TABLE -; CHECK-NEXT: Table: -; CHECK-NEXT: Index: 0 -; CHECK-NEXT: ElemType: FUNCREF -; CHECK-NEXT: Limits: -; CHECK-NEXT: Initial: 0x2 -; CHECK-NEXT: - Module: env ; CHECK-NEXT: Field: func3 ; CHECK-NEXT: Kind: FUNCTION ; CHECK-NEXT: SigIndex: 1 @@ -54,6 +46,14 @@ declare void @func3() ; CHECK-NEXT: Field: func0 ; CHECK-NEXT: Kind: FUNCTION ; CHECK-NEXT: SigIndex: 1 +; CHECK-NEXT: - Module: env +; CHECK-NEXT: Field: __indirect_function_table +; CHECK-NEXT: Kind: TABLE +; CHECK-NEXT: Table: +; CHECK-NEXT: Index: 0 +; CHECK-NEXT: ElemType: FUNCREF +; CHECK-NEXT: Limits: +; CHECK-NEXT: Initial: 0x2 ; CHECK-NEXT: - Type: FUNCTION ; CHECK-NEXT: FunctionTypes: [ 0, 1, 0, 1 ] ; CHECK-NEXT: - Type: ELEM diff --git a/llvm/test/MC/WebAssembly/reloc-pic.s b/llvm/test/MC/WebAssembly/reloc-pic.s index b3cc618d96a3b..b7995ebf97fa0 100644 --- a/llvm/test/MC/WebAssembly/reloc-pic.s +++ b/llvm/test/MC/WebAssembly/reloc-pic.s @@ -63,6 +63,10 @@ hidden_func: # CHECK-NEXT: Memory: # CHECK-NEXT: Initial: 0x1 # CHECK-NEXT: - Module: env +# CHECK-NEXT: Field: default_func +# CHECK-NEXT: Kind: FUNCTION +# CHECK-NEXT: SigIndex: 0 +# CHECK-NEXT: - Module: env # CHECK-NEXT: Field: __indirect_function_table # CHECK-NEXT: Kind: TABLE # CHECK-NEXT: Table: @@ -70,10 +74,6 @@ hidden_func: # CHECK-NEXT: ElemType: FUNCREF # CHECK-NEXT: Limits: # CHECK-NEXT: Initial: 0x1 -# CHECK-NEXT: - Module: env -# CHECK-NEXT: Field: default_func -# CHECK-NEXT: Kind: FUNCTION -# CHECK-NEXT: SigIndex: 0 # CHECK-NEXT: - Module: GOT.mem # CHECK-NEXT: Field: default_data # CHECK-NEXT: Kind: GLOBAL diff --git a/llvm/test/MC/WebAssembly/tables.s b/llvm/test/MC/WebAssembly/tables.s index 3bee36cda2ce1..a023b9970a838 100644 --- a/llvm/test/MC/WebAssembly/tables.s +++ b/llvm/test/MC/WebAssembly/tables.s @@ -121,14 +121,22 @@ table_fill: # BIN: - Type: TABLE # BIN-NEXT: Tables: -# BIN-NEXT: - Index: 1 +# BIN-NEXT: - Index: 0 # BIN-NEXT: ElemType: EXTERNREF # BIN-NEXT: Limits: # BIN-NEXT: Initial: 0x0 +# BIN-NEXT: - Index: 1 +# BIN-NEXT: ElemType: FUNCREF +# BIN-NEXT: Limits: +# BIN-NEXT: Initial: 0x0 # BIN-NEXT: - Index: 2 # BIN-NEXT: ElemType: FUNCREF # BIN-NEXT: Limits: # BIN-NEXT: Initial: 0x0 +# BIN-NEXT: - Index: 3 +# BIN-NEXT: ElemType: FUNCREF +# BIN-NEXT: Limits: +# BIN-NEXT: Initial: 0x0 # BIN: - Type: CODE # BIN-NEXT: Relocations: @@ -162,19 +170,19 @@ table_fill: # BIN-NEXT: Functions: # BIN-NEXT: - Index: 0 # BIN-NEXT: Locals: [] -# BIN-NEXT: Body: 20002001FC108380808000FC0E838080800084808080000B +# BIN-NEXT: Body: 20002001FC108280808000FC0E828080800083808080000B # BIN-NEXT: - Index: 1 # BIN-NEXT: Locals: [] -# BIN-NEXT: Body: 20002581808080000B +# BIN-NEXT: Body: 20002580808080000B # BIN-NEXT: - Index: 2 # BIN-NEXT: Locals: [] -# BIN-NEXT: Body: 200020012681808080000B +# BIN-NEXT: Body: 200020012680808080000B # BIN-NEXT: - Index: 3 # BIN-NEXT: Locals: [] -# BIN-NEXT: Body: 41002581808080002000FC0F818080800020006A0B +# BIN-NEXT: Body: 41002580808080002000FC0F808080800020006A0B # BIN-NEXT: - Index: 4 # BIN-NEXT: Locals: [] -# BIN-NEXT: Body: 200041002583808080002001FC1183808080000B +# BIN-NEXT: Body: 200041002582808080002001FC1182808080000B # BIN: - Type: CUSTOM # BIN-NEXT: Name: linking @@ -184,9 +192,20 @@ table_fill: # BIN-NEXT: Kind: TABLE # BIN-NEXT: Name: foo # BIN-NEXT: Flags: [ BINDING_LOCAL ] -# BIN-NEXT: Table: 1 +# BIN-NEXT: Table: 0 # BIN-NEXT: - Index: 1 # BIN-NEXT: Kind: TABLE # BIN-NEXT: Name: bar # BIN-NEXT: Flags: [ BINDING_LOCAL ] +# BIN-NEXT: Table: 1 +# BIN-NEXT: - Index: 2 +# BIN-NEXT: Kind: TABLE +# BIN-NEXT: Name: table1 +# BIN-NEXT: Flags: [ BINDING_LOCAL ] # BIN-NEXT: Table: 2 +# BIN-NEXT: - Index: 3 +# BIN-NEXT: Kind: TABLE +# BIN-NEXT: Name: table2 +# BIN-NEXT: Flags: [ BINDING_LOCAL ] +# BIN-NEXT: Table: 3 +# BIN-NEXT: - Index: 4 diff --git a/llvm/test/MC/WebAssembly/type-index.s b/llvm/test/MC/WebAssembly/type-index.s index 298e5e2f9de32..501b71d6d6a8a 100644 --- a/llvm/test/MC/WebAssembly/type-index.s +++ b/llvm/test/MC/WebAssembly/type-index.s @@ -38,14 +38,6 @@ test0: # BIN-NEXT: Kind: MEMORY # BIN-NEXT: Memory: # BIN-NEXT: Initial: 0x0 -# BIN-NEXT: - Module: env -# BIN-NEXT: Field: __indirect_function_table -# BIN-NEXT: Kind: TABLE -# BIN-NEXT: Table: -# BIN-NEXT: Index: 0 -# BIN-NEXT: ElemType: FUNCREF -# BIN-NEXT: Limits: -# BIN-NEXT: Initial: 0x0 # BIN-NEXT: - Type: FUNCTION # BIN-NEXT: FunctionTypes: [ 0 ] # BIN-NEXT: - Type: CODE diff --git a/llvm/test/MC/WebAssembly/wasm64.s b/llvm/test/MC/WebAssembly/wasm64.s index eda11a472825c..a7eb510cb0501 100644 --- a/llvm/test/MC/WebAssembly/wasm64.s +++ b/llvm/test/MC/WebAssembly/wasm64.s @@ -150,14 +150,6 @@ test: # BIN-NEXT: Flags: [ IS_64 ] # BIN-NEXT: Initial: 0x1 # BIN-NEXT: - Module: env -# BIN-NEXT: Field: __indirect_function_table -# BIN-NEXT: Kind: TABLE -# BIN-NEXT: Table: -# BIN-NEXT: Index: 0 -# BIN-NEXT: ElemType: FUNCREF -# BIN-NEXT: Limits: -# BIN-NEXT: Initial: 0x0 -# BIN-NEXT: - Module: env # BIN-NEXT: Field: myglob64 # BIN-NEXT: Kind: GLOBAL # BIN-NEXT: GlobalType: I64 diff --git a/llvm/test/Object/obj2yaml.test b/llvm/test/Object/obj2yaml.test index ea6194dee9a66..8404404064565 100644 --- a/llvm/test/Object/obj2yaml.test +++ b/llvm/test/Object/obj2yaml.test @@ -362,6 +362,7 @@ # ELF-MIPSEL-NEXT: Type: SHT_REL # ELF-MIPSEL-NEXT: Link: .symtab # ELF-MIPSEL-NEXT: AddressAlign: 0x4 +# ELF-MIPSEL-NEXT: Offset: 0x434 # ELF-MIPSEL-NEXT: Info: .text # ELF-MIPSEL-NEXT: Relocations: # ELF-MIPSEL-NEXT: - Symbol: _gp_disp @@ -385,6 +386,7 @@ # ELF-MIPSEL-NEXT: Type: SHT_PROGBITS # ELF-MIPSEL-NEXT: Flags: [ SHF_WRITE, SHF_ALLOC ] # ELF-MIPSEL-NEXT: AddressAlign: 0x4 +# ELF-MIPSEL-NEXT: Offset: 0x80 # ELF-MIPSEL-NEXT: - Name: .bss # ELF-MIPSEL-NEXT: Type: SHT_NOBITS # ELF-MIPSEL-NEXT: Flags: [ SHF_WRITE, SHF_ALLOC ] @@ -482,6 +484,7 @@ # ELF-MIPS64EL-NEXT: Type: SHT_RELA # ELF-MIPS64EL-NEXT: Link: .symtab # ELF-MIPS64EL-NEXT: AddressAlign: 0x8 +# ELF-MIPS64EL-NEXT: Offset: 0x410 # ELF-MIPS64EL-NEXT: Info: .data # ELF-MIPS64EL-NEXT: Relocations: # ELF-MIPS64EL-NEXT: - Symbol: zed @@ -490,6 +493,7 @@ # ELF-MIPS64EL-NEXT: Type: SHT_NOBITS # ELF-MIPS64EL-NEXT: Flags: [ SHF_WRITE, SHF_ALLOC ] # ELF-MIPS64EL-NEXT: AddressAlign: 0x10 +# ELF-MIPS64EL-NEXT: Offset: 0x50 # ELF-MIPS64EL-NEXT: - Name: .MIPS.options # ELF-MIPS64EL-NEXT: Type: SHT_MIPS_OPTIONS # ELF-MIPS64EL-NEXT: Flags: [ SHF_ALLOC, SHF_MIPS_NOSTRIP ] diff --git a/llvm/test/Other/devirtualization-undef.ll b/llvm/test/Other/devirtualization-undef.ll new file mode 100644 index 0000000000000..9099c575ac191 --- /dev/null +++ b/llvm/test/Other/devirtualization-undef.ll @@ -0,0 +1,12 @@ +; RUN: opt -passes='devirt<2>(function(simplifycfg))' %s -S | FileCheck %s + +; CHECK: unreachable + +declare void @llvm.assume(i1 noundef) +declare i1 @bar(i8* nonnull dereferenceable(1)) + +define void @foo() { + %a = call i1 null() + call void @llvm.assume(i1 %a) + ret void +} diff --git a/llvm/test/Other/heat-colors-graphs.ll b/llvm/test/Other/heat-colors-graphs.ll index 4cc58a640cd5f..cf19820c4ff05 100644 --- a/llvm/test/Other/heat-colors-graphs.ll +++ b/llvm/test/Other/heat-colors-graphs.ll @@ -1,6 +1,6 @@ -; RUN: opt < %s -dot-cfg -cfg-heat-colors -cfg-dot-filename-prefix=%t 2>/dev/null +; RUN: opt %s -dot-cfg -cfg-heat-colors -cfg-dot-filename-prefix=%t -disable-output ; RUN: FileCheck %s -input-file=%t.f.dot --check-prefixes=CHECK-CFG,CHECK-BOTH -; RUN: opt %s -dot-callgraph -callgraph-heat-colors -callgraph-dot-filename-prefix=%t 2>/dev/null +; RUN: opt -enable-new-pm=0 %s -dot-callgraph -callgraph-heat-colors -callgraph-dot-filename-prefix=%t -disable-output ; RUN: FileCheck %s -input-file=%t.callgraph.dot --check-prefix=CHECK-BOTH ; CHECK-BOTH: color="#{{[(a-z)(0-9)]+}}", style={{[a-z]+}}, fillcolor="#{{[(a-z)(0-9)]+}}" diff --git a/llvm/test/Other/heat-colors-multigraph.ll b/llvm/test/Other/heat-colors-multigraph.ll index a951ec29a1944..4aab4f4ba06c3 100644 --- a/llvm/test/Other/heat-colors-multigraph.ll +++ b/llvm/test/Other/heat-colors-multigraph.ll @@ -1,6 +1,6 @@ -; RUN: opt %s -dot-callgraph -callgraph-multigraph -callgraph-dot-filename-prefix=%t 2>/dev/null +; RUN: opt -enable-new-pm=0 %s -dot-callgraph -callgraph-multigraph -callgraph-dot-filename-prefix=%t -disable-output ; RUN: FileCheck %s -input-file=%t.callgraph.dot --check-prefix=CHECK-MULTIGRAPH -; RUN: opt %s -dot-callgraph -callgraph-dot-filename-prefix=%t 2>/dev/null +; RUN: opt -enable-new-pm=0 %s -dot-callgraph -callgraph-dot-filename-prefix=%t -disable-output ; RUN: FileCheck %s -input-file=%t.callgraph.dot --check-prefix=CHECK ; CHECK-MULTIGRAPH: {external caller} diff --git a/llvm/test/Other/lint.ll b/llvm/test/Other/lint.ll index a156301c1c26b..5e9b4660ec17c 100644 --- a/llvm/test/Other/lint.ll +++ b/llvm/test/Other/lint.ll @@ -6,7 +6,7 @@ declare fastcc void @bar() declare void @llvm.stackrestore(i8*) declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind declare void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind -declare void @has_sret(i8* sret %p) +declare void @has_sret(i8* sret(i8) %p) declare void @has_noaliases(i32* noalias %p, i32* %q) declare void @one_arg(i32) diff --git a/llvm/test/Other/new-pm-O0-ep-callbacks.ll b/llvm/test/Other/new-pm-O0-ep-callbacks.ll index 1645156c1b28e..8fc8af0ec277d 100644 --- a/llvm/test/Other/new-pm-O0-ep-callbacks.ll +++ b/llvm/test/Other/new-pm-O0-ep-callbacks.ll @@ -4,6 +4,7 @@ ; RUN: opt -disable-output -debug-pass-manager -passes-ep-cgscc-optimizer-late=no-op-cgscc -passes='default' 2>&1 < %s | FileCheck %s ; RUN: opt -disable-output -debug-pass-manager -passes-ep-vectorizer-start=no-op-function -passes='default' 2>&1 < %s | FileCheck %s ; RUN: opt -disable-output -debug-pass-manager -passes-ep-pipeline-start=no-op-module -passes='default' 2>&1 < %s | FileCheck %s +; RUN: opt -disable-output -debug-pass-manager -passes-ep-pipeline-early-simplification=no-op-module -passes='default' 2>&1 < %s | FileCheck %s ; RUN: opt -disable-output -debug-pass-manager -passes-ep-optimizer-last=no-op-function -passes='default' 2>&1 < %s | FileCheck %s ; CHECK: Running pass: NoOp diff --git a/llvm/test/Other/new-pm-defaults.ll b/llvm/test/Other/new-pm-defaults.ll index 1f2142c5bcd1c..261dbe0057f3a 100644 --- a/llvm/test/Other/new-pm-defaults.ll +++ b/llvm/test/Other/new-pm-defaults.ll @@ -55,6 +55,10 @@ ; RUN: -passes='default' -S %s 2>&1 \ ; RUN: | FileCheck %s --check-prefixes=CHECK-O,CHECK-DEFAULT,CHECK-O3,%llvmcheckext,CHECK-EP-PIPELINE-START,CHECK-O23SZ ; RUN: opt -disable-verify -debug-pass-manager \ +; RUN: -passes-ep-pipeline-early-simplification='no-op-module' \ +; RUN: -passes='default' -S %s 2>&1 \ +; RUN: | FileCheck %s --check-prefixes=CHECK-O,CHECK-DEFAULT,CHECK-O3,%llvmcheckext,CHECK-EP-PIPELINE-EARLY-SIMPLIFICATION,CHECK-O23SZ +; RUN: opt -disable-verify -debug-pass-manager \ ; RUN: -passes-ep-pipeline-start='no-op-module' \ ; RUN: -passes='lto-pre-link' -S %s 2>&1 \ ; RUN: | FileCheck %s --check-prefixes=CHECK-O,CHECK-LTO,CHECK-O3,%llvmcheckext,CHECK-EP-PIPELINE-START,CHECK-O23SZ @@ -84,6 +88,7 @@ ; CHECK-O-NEXT: Running pass: LowerExpectIntrinsicPass ; CHECK-O3-NEXT: Running pass: CallSiteSplittingPass ; CHECK-O-NEXT: Finished llvm::Function pass manager run. +; CHECK-EP-PIPELINE-EARLY-SIMPLIFICATION-NEXT: Running pass: NoOpModulePass ; CHECK-O-NEXT: Running pass: IPSCCPPass ; CHECK-O-NEXT: Running pass: CalledValuePropagationPass ; CHECK-O-NEXT: Running pass: GlobalOptPass @@ -158,8 +163,8 @@ ; CHECK-O-NEXT: Running pass: LCSSAPass ; CHECK-O-NEXT: Finished llvm::Function pass manager run. ; CHECK-O-NEXT: Starting Loop pass manager run. -; CHECK-O-NEXT: Running pass: IndVarSimplifyPass ; CHECK-O-NEXT: Running pass: LoopIdiomRecognizePass +; CHECK-O-NEXT: Running pass: IndVarSimplifyPass ; CHECK-EP-LOOP-LATE-NEXT: Running pass: NoOpLoopPass ; CHECK-O-NEXT: Running pass: LoopDeletionPass ; CHECK-O-NEXT: Running pass: LoopFullUnrollPass diff --git a/llvm/test/Other/new-pm-thinlto-defaults.ll b/llvm/test/Other/new-pm-thinlto-defaults.ll index 675047421503b..a62f27f79c2c9 100644 --- a/llvm/test/Other/new-pm-thinlto-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-defaults.ll @@ -147,8 +147,8 @@ ; CHECK-O-NEXT: Running pass: LCSSAPass ; CHECK-O-NEXT: Finished llvm::Function pass manager run ; CHECK-O-NEXT: Starting Loop pass manager run. -; CHECK-O-NEXT: Running pass: IndVarSimplifyPass ; CHECK-O-NEXT: Running pass: LoopIdiomRecognizePass +; CHECK-O-NEXT: Running pass: IndVarSimplifyPass ; CHECK-O-NEXT: Running pass: LoopDeletionPass ; CHECK-O-NEXT: Running pass: LoopFullUnrollPass ; CHECK-O-NEXT: Finished Loop pass manager run. diff --git a/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll index b53f85e2db8e1..996f5f49b42b4 100644 --- a/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll @@ -120,8 +120,8 @@ ; CHECK-O-NEXT: Running pass: LCSSAPass ; CHECK-O-NEXT: Finished {{.*}}Function pass manager run ; CHECK-O-NEXT: Starting Loop pass manager run. -; CHECK-O-NEXT: Running pass: IndVarSimplifyPass ; CHECK-O-NEXT: Running pass: LoopIdiomRecognizePass +; CHECK-O-NEXT: Running pass: IndVarSimplifyPass ; CHECK-O-NEXT: Running pass: LoopDeletionPass ; CHECK-O-NEXT: Running pass: LoopFullUnrollPass ; CHECK-O-NEXT: Finished Loop pass manager run. diff --git a/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll index 4f3c00e659084..2587d07b229ba 100644 --- a/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll @@ -128,8 +128,8 @@ ; CHECK-O-NEXT: Running pass: LCSSAPass ; CHECK-O-NEXT: Finished {{.*}}Function pass manager run ; CHECK-O-NEXT: Starting Loop pass manager run. -; CHECK-O-NEXT: Running pass: IndVarSimplifyPass ; CHECK-O-NEXT: Running pass: LoopIdiomRecognizePass +; CHECK-O-NEXT: Running pass: IndVarSimplifyPass ; CHECK-O-NEXT: Running pass: LoopDeletionPass ; CHECK-O-NEXT: Running pass: LoopFullUnrollPass ; CHECK-O-NEXT: Finished Loop pass manager run. diff --git a/llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll index a420062390d0b..d1a9b00e65f76 100644 --- a/llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll @@ -168,8 +168,8 @@ ; CHECK-O-NEXT: Running pass: LCSSAPass ; CHECK-O-NEXT: Finished {{.*}}Function pass manager run ; CHECK-O-NEXT: Starting Loop pass manager run. -; CHECK-O-NEXT: Running pass: IndVarSimplifyPass ; CHECK-O-NEXT: Running pass: LoopIdiomRecognizePass +; CHECK-O-NEXT: Running pass: IndVarSimplifyPass ; CHECK-O-NEXT: Running pass: LoopDeletionPass ; CHECK-O-NEXT: Running pass: LoopFullUnrollPass ; CHECK-O-NEXT: Finished Loop pass manager run. diff --git a/llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll index 57e1cd9269485..7078c6d8cb75a 100644 --- a/llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll @@ -124,8 +124,8 @@ ; CHECK-O-NEXT: Running pass: LCSSAPass ; CHECK-O-NEXT: Finished {{.*}}Function pass manager run ; CHECK-O-NEXT: Starting Loop pass manager run. -; CHECK-O-NEXT: Running pass: IndVarSimplifyPass ; CHECK-O-NEXT: Running pass: LoopIdiomRecognizePass +; CHECK-O-NEXT: Running pass: IndVarSimplifyPass ; CHECK-O-NEXT: Running pass: LoopDeletionPass ; CHECK-O-NEXT: Finished Loop pass manager run. ; CHECK-O-NEXT: Running pass: SROA on foo diff --git a/llvm/test/Other/opt-O2-pipeline.ll b/llvm/test/Other/opt-O2-pipeline.ll index 46ed056f267db..7d7934e6e4abe 100644 --- a/llvm/test/Other/opt-O2-pipeline.ll +++ b/llvm/test/Other/opt-O2-pipeline.ll @@ -131,8 +131,8 @@ ; CHECK-NEXT: Loop-Closed SSA Form Pass ; CHECK-NEXT: Scalar Evolution Analysis ; CHECK-NEXT: Loop Pass Manager -; CHECK-NEXT: Induction Variable Simplification ; CHECK-NEXT: Recognize loop idioms +; CHECK-NEXT: Induction Variable Simplification ; CHECK-NEXT: Delete dead loops ; CHECK-NEXT: Unroll loops ; CHECK-NEXT: SROA diff --git a/llvm/test/Other/opt-O3-pipeline-enable-matrix.ll b/llvm/test/Other/opt-O3-pipeline-enable-matrix.ll index 218f9c09f21d8..bd77a8bac87c2 100644 --- a/llvm/test/Other/opt-O3-pipeline-enable-matrix.ll +++ b/llvm/test/Other/opt-O3-pipeline-enable-matrix.ll @@ -136,8 +136,8 @@ ; CHECK-NEXT: Loop-Closed SSA Form Pass ; CHECK-NEXT: Scalar Evolution Analysis ; CHECK-NEXT: Loop Pass Manager -; CHECK-NEXT: Induction Variable Simplification ; CHECK-NEXT: Recognize loop idioms +; CHECK-NEXT: Induction Variable Simplification ; CHECK-NEXT: Delete dead loops ; CHECK-NEXT: Unroll loops ; CHECK-NEXT: SROA diff --git a/llvm/test/Other/opt-O3-pipeline.ll b/llvm/test/Other/opt-O3-pipeline.ll index 5875049dd0efa..85f25363d2321 100644 --- a/llvm/test/Other/opt-O3-pipeline.ll +++ b/llvm/test/Other/opt-O3-pipeline.ll @@ -136,8 +136,8 @@ ; CHECK-NEXT: Loop-Closed SSA Form Pass ; CHECK-NEXT: Scalar Evolution Analysis ; CHECK-NEXT: Loop Pass Manager -; CHECK-NEXT: Induction Variable Simplification ; CHECK-NEXT: Recognize loop idioms +; CHECK-NEXT: Induction Variable Simplification ; CHECK-NEXT: Delete dead loops ; CHECK-NEXT: Unroll loops ; CHECK-NEXT: SROA diff --git a/llvm/test/Other/opt-Os-pipeline.ll b/llvm/test/Other/opt-Os-pipeline.ll index f5a03d2a92940..6d42b39fb8a54 100644 --- a/llvm/test/Other/opt-Os-pipeline.ll +++ b/llvm/test/Other/opt-Os-pipeline.ll @@ -117,8 +117,8 @@ ; CHECK-NEXT: Loop-Closed SSA Form Pass ; CHECK-NEXT: Scalar Evolution Analysis ; CHECK-NEXT: Loop Pass Manager -; CHECK-NEXT: Induction Variable Simplification ; CHECK-NEXT: Recognize loop idioms +; CHECK-NEXT: Induction Variable Simplification ; CHECK-NEXT: Delete dead loops ; CHECK-NEXT: Unroll loops ; CHECK-NEXT: SROA diff --git a/llvm/test/Other/pass-pipeline-parsing.ll b/llvm/test/Other/pass-pipeline-parsing.ll index adf7554ac503b..4cff050f52df0 100644 --- a/llvm/test/Other/pass-pipeline-parsing.ll +++ b/llvm/test/Other/pass-pipeline-parsing.ll @@ -276,6 +276,9 @@ ; RUN: opt -passes-ep-pipeline-start=bad -passes=no-op-function \ ; RUN: /dev/null -disable-output 2>&1 | FileCheck %s -check-prefix=PASSES-EP-PIPELINESTART-ERR ; PASSES-EP-PIPELINESTART-ERR: Could not parse -passes-ep-pipeline-start pipeline: unknown pass name 'bad' +; RUN: opt -passes-ep-pipeline-early-simplification=bad -passes=no-op-function \ +; RUN: /dev/null -disable-output 2>&1 | FileCheck %s -check-prefix=PASSES-EP-PIPELINEEARLYSIMPLIFICATION-ERR +; PASSES-EP-PIPELINEEARLYSIMPLIFICATION-ERR: Could not parse -passes-ep-pipeline-early-simplification pipeline: unknown pass name 'bad' define void @f() { entry: diff --git a/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td b/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td new file mode 100644 index 0000000000000..c8a8cab2b6523 --- /dev/null +++ b/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td @@ -0,0 +1,8 @@ +// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o /dev/null --warn-on-skipped-patterns 2>&1 < %s 2>&1 | FileCheck %s + +include "llvm/Target/Target.td" +include "GlobalISelEmitterCommon.td" + +// CHECK: warning: Skipped pattern: Dst pattern root isn't a known leaf +def : Pat<(zext (i16 (trunc i32:$src))), + (i32 $src)>; diff --git a/llvm/test/Transforms/ArgumentPromotion/attrs.ll b/llvm/test/Transforms/ArgumentPromotion/attrs.ll index 07b96038d62af..9fc5023e786bd 100644 --- a/llvm/test/Transforms/ArgumentPromotion/attrs.ll +++ b/llvm/test/Transforms/ArgumentPromotion/attrs.ll @@ -5,9 +5,9 @@ %struct.ss = type { i32, i64 } ; Don't drop 'byval' on %X here. -define internal void @f(%struct.ss* byval %b, i32* byval %X, i32 %i) nounwind { +define internal void @f(%struct.ss* byval(%struct.ss) %b, i32* byval(i32) %X, i32 %i) nounwind { ; CHECK-LABEL: define {{[^@]+}}@f -; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]], i32* byval [[X:%.*]], i32 [[I:%.*]]) +; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]], i32* byval(i32) [[X:%.*]], i32 [[I:%.*]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: [[B:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 ; CHECK-NEXT: [[DOT0:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[B]], i32 0, i32 0 @@ -46,7 +46,7 @@ define i32 @test(i32* %X) { ; CHECK-NEXT: [[S_0_VAL:%.*]] = load i32, i32* [[S_0]], align 4 ; CHECK-NEXT: [[S_1:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; CHECK-NEXT: [[S_1_VAL:%.*]] = load i64, i64* [[S_1]], align 4 -; CHECK-NEXT: call void @f(i32 [[S_0_VAL]], i64 [[S_1_VAL]], i32* byval [[X]], i32 zeroext 0) +; CHECK-NEXT: call void @f(i32 [[S_0_VAL]], i64 [[S_1_VAL]], i32* byval(i32) [[X]], i32 zeroext 0) ; CHECK-NEXT: ret i32 0 ; entry: @@ -56,7 +56,7 @@ entry: %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 store i64 2, i64* %tmp4, align 4 - call void @f( %struct.ss* byval %S, i32* byval %X, i32 zeroext 0) + call void @f(%struct.ss* byval(%struct.ss) %S, i32* byval(i32) %X, i32 zeroext 0) ret i32 0 } diff --git a/llvm/test/Transforms/ArgumentPromotion/byval-2.ll b/llvm/test/Transforms/ArgumentPromotion/byval-2.ll index f95493f606889..cab1957c24640 100644 --- a/llvm/test/Transforms/ArgumentPromotion/byval-2.ll +++ b/llvm/test/Transforms/ArgumentPromotion/byval-2.ll @@ -7,9 +7,9 @@ %struct.ss = type { i32, i64 } -define internal void @f(%struct.ss* byval %b, i32* byval %X) nounwind { +define internal void @f(%struct.ss* byval(%struct.ss) %b, i32* byval(i32) %X) nounwind { ; CHECK-LABEL: define {{[^@]+}}@f -; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]], i32* byval [[X:%.*]]) +; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]], i32* byval(i32) [[X:%.*]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: [[B:%.*]] = alloca [[STRUCT_SS:%.*]], align 8 ; CHECK-NEXT: [[DOT0:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[B]], i32 0, i32 0 @@ -46,7 +46,7 @@ define i32 @test(i32* %X) { ; CHECK-NEXT: [[S_0_VAL:%.*]] = load i32, i32* [[S_0]], align 4 ; CHECK-NEXT: [[S_1:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; CHECK-NEXT: [[S_1_VAL:%.*]] = load i64, i64* [[S_1]], align 4 -; CHECK-NEXT: call void @f(i32 [[S_0_VAL]], i64 [[S_1_VAL]], i32* byval [[X]]) +; CHECK-NEXT: call void @f(i32 [[S_0_VAL]], i64 [[S_1_VAL]], i32* byval(i32) [[X]]) ; CHECK-NEXT: ret i32 0 ; entry: @@ -55,6 +55,6 @@ entry: store i32 1, i32* %tmp1, align 8 %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 store i64 2, i64* %tmp4, align 4 - call void @f( %struct.ss* byval %S, i32* byval %X) + call void @f(%struct.ss* byval(%struct.ss) %S, i32* byval(i32) %X) ret i32 0 } diff --git a/llvm/test/Transforms/ArgumentPromotion/byval.ll b/llvm/test/Transforms/ArgumentPromotion/byval.ll index 359ce4ef848c4..1c7f8224c6d59 100644 --- a/llvm/test/Transforms/ArgumentPromotion/byval.ll +++ b/llvm/test/Transforms/ArgumentPromotion/byval.ll @@ -6,7 +6,7 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1 %struct.ss = type { i32, i64 } -define internal void @f(%struct.ss* byval %b) nounwind { +define internal void @f(%struct.ss* byval(%struct.ss) %b) nounwind { ; CHECK-LABEL: define {{[^@]+}}@f ; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]]) ; CHECK-NEXT: entry: @@ -30,7 +30,7 @@ entry: } -define internal void @g(%struct.ss* byval align 32 %b) nounwind { +define internal void @g(%struct.ss* byval(%struct.ss) align 32 %b) nounwind { ; CHECK-LABEL: define {{[^@]+}}@g ; CHECK-SAME: (i32 [[B_0:%.*]], i64 [[B_1:%.*]]) ; CHECK-NEXT: entry: @@ -80,8 +80,8 @@ entry: store i32 1, i32* %tmp1, align 8 %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 store i64 2, i64* %tmp4, align 4 - call void @f(%struct.ss* byval %S) nounwind - call void @g(%struct.ss* byval %S) nounwind + call void @f(%struct.ss* byval(%struct.ss) %S) nounwind + call void @g(%struct.ss* byval(%struct.ss) %S) nounwind ret i32 0 } diff --git a/llvm/test/Transforms/ArgumentPromotion/dbg.ll b/llvm/test/Transforms/ArgumentPromotion/dbg.ll index 1da97c3144e9e..56f0fe4f13241 100644 --- a/llvm/test/Transforms/ArgumentPromotion/dbg.ll +++ b/llvm/test/Transforms/ArgumentPromotion/dbg.ll @@ -18,7 +18,7 @@ define internal void @test(i32** %X) !dbg !2 { %struct.pair = type { i32, i32 } -define internal void @test_byval(%struct.pair* byval %P) { +define internal void @test_byval(%struct.pair* byval(%struct.pair) %P) { ; CHECK-LABEL: define {{[^@]+}}@test_byval ; CHECK-SAME: (i32 [[P_0:%.*]], i32 [[P_1:%.*]]) ; CHECK-NEXT: [[P:%.*]] = alloca [[STRUCT_PAIR:%.*]], align 8 diff --git a/llvm/test/Transforms/ArgumentPromotion/fp80.ll b/llvm/test/Transforms/ArgumentPromotion/fp80.ll index dd7cebf5a1c1c..7f39f7e7c5f93 100644 --- a/llvm/test/Transforms/ArgumentPromotion/fp80.ll +++ b/llvm/test/Transforms/ArgumentPromotion/fp80.ll @@ -16,7 +16,7 @@ target triple = "x86_64-unknown-linux-gnu" define void @run() { ; CHECK-LABEL: define {{[^@]+}}@run() ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @UseLongDoubleUnsafely(%union.u* byval align 16 bitcast (%struct.s* @b to %union.u*)) +; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @UseLongDoubleUnsafely(%union.u* byval(%union.u) align 16 bitcast (%struct.s* @b to %union.u*)) ; CHECK-NEXT: [[DOT0:%.*]] = getelementptr [[UNION_U:%.*]], %union.u* bitcast (%struct.s* @b to %union.u*), i32 0, i32 0 ; CHECK-NEXT: [[DOT0_VAL:%.*]] = load x86_fp80, x86_fp80* [[DOT0]] ; CHECK-NEXT: [[TMP1:%.*]] = tail call x86_fp80 @UseLongDoubleSafely(x86_fp80 [[DOT0_VAL]]) @@ -25,16 +25,16 @@ define void @run() { ; CHECK-NEXT: ret void ; entry: - tail call i8 @UseLongDoubleUnsafely(%union.u* byval align 16 bitcast (%struct.s* @b to %union.u*)) - tail call x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 bitcast (%struct.s* @b to %union.u*)) + tail call i8 @UseLongDoubleUnsafely(%union.u* byval(%union.u) align 16 bitcast (%struct.s* @b to %union.u*)) + tail call x86_fp80 @UseLongDoubleSafely(%union.u* byval(%union.u) align 16 bitcast (%struct.s* @b to %union.u*)) call i64 @AccessPaddingOfStruct(%struct.Foo* @a) call i64 @CaptureAStruct(%struct.Foo* @a) ret void } -define internal i8 @UseLongDoubleUnsafely(%union.u* byval align 16 %arg) { +define internal i8 @UseLongDoubleUnsafely(%union.u* byval(%union.u) align 16 %arg) { ; CHECK-LABEL: define {{[^@]+}}@UseLongDoubleUnsafely -; CHECK-SAME: (%union.u* byval align 16 [[ARG:%.*]]) +; CHECK-SAME: (%union.u* byval(%union.u) align 16 [[ARG:%.*]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: [[BITCAST:%.*]] = bitcast %union.u* [[ARG]] to %struct.s* ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.s* [[BITCAST]], i64 0, i32 2 @@ -48,7 +48,7 @@ entry: ret i8 %result } -define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 %arg) { +define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval(%union.u) align 16 %arg) { ; CHECK-LABEL: define {{[^@]+}}@UseLongDoubleSafely ; CHECK-SAME: (x86_fp80 [[ARG_0:%.*]]) ; CHECK-NEXT: [[ARG:%.*]] = alloca [[UNION_U:%.*]], align 16 @@ -63,9 +63,9 @@ define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 %arg) { ret x86_fp80 %fp80 } -define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval %a) { +define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval(%struct.Foo) %a) { ; CHECK-LABEL: define {{[^@]+}}@AccessPaddingOfStruct -; CHECK-SAME: (%struct.Foo* byval [[A:%.*]]) +; CHECK-SAME: (%struct.Foo* byval(%struct.Foo) [[A:%.*]]) ; CHECK-NEXT: [[P:%.*]] = bitcast %struct.Foo* [[A]] to i64* ; CHECK-NEXT: [[V:%.*]] = load i64, i64* [[P]] ; CHECK-NEXT: ret i64 [[V]] @@ -75,9 +75,9 @@ define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval %a) { ret i64 %v } -define internal i64 @CaptureAStruct(%struct.Foo* byval %a) { +define internal i64 @CaptureAStruct(%struct.Foo* byval(%struct.Foo) %a) { ; CHECK-LABEL: define {{[^@]+}}@CaptureAStruct -; CHECK-SAME: (%struct.Foo* byval [[A:%.*]]) +; CHECK-SAME: (%struct.Foo* byval(%struct.Foo) [[A:%.*]]) ; CHECK-NEXT: entry: ; CHECK-NEXT: [[A_PTR:%.*]] = alloca %struct.Foo* ; CHECK-NEXT: br label [[LOOP:%.*]] diff --git a/llvm/test/Transforms/ArgumentPromotion/sret.ll b/llvm/test/Transforms/ArgumentPromotion/sret.ll index c4328e41bb26d..ea4a9070a5fc2 100644 --- a/llvm/test/Transforms/ArgumentPromotion/sret.ll +++ b/llvm/test/Transforms/ArgumentPromotion/sret.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc" -define internal void @add({i32, i32}* %this, i32* sret %r) { +define internal void @add({i32, i32}* %this, i32* sret(i32) %r) { ; CHECK-LABEL: define {{[^@]+}}@add ; CHECK-SAME: (i32 [[THIS_0_0_VAL:%.*]], i32 [[THIS_0_1_VAL:%.*]], i32* noalias [[R:%.*]]) ; CHECK-NEXT: [[AB:%.*]] = add i32 [[THIS_0_0_VAL]], [[THIS_0_1_VAL]] @@ -35,6 +35,6 @@ define void @f() { %r = alloca i32 %pair = alloca {i32, i32} - call void @add({i32, i32}* %pair, i32* sret %r) + call void @add({i32, i32}* %pair, i32* sret(i32) %r) ret void } diff --git a/llvm/test/Transforms/ArgumentPromotion/tail.ll b/llvm/test/Transforms/ArgumentPromotion/tail.ll index 62c6f202dc7df..4c1d435fa2819 100644 --- a/llvm/test/Transforms/ArgumentPromotion/tail.ll +++ b/llvm/test/Transforms/ArgumentPromotion/tail.ll @@ -9,7 +9,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" declare i8* @foo(%pair*) -define internal void @bar(%pair* byval %Data) { +define internal void @bar(%pair* byval(%pair) %Data) { ; CHECK-LABEL: define {{[^@]+}}@bar ; CHECK-SAME: (i32 [[DATA_0:%.*]], i32 [[DATA_1:%.*]]) ; CHECK-NEXT: [[DATA:%.*]] = alloca [[PAIR:%.*]], align 8 @@ -24,9 +24,9 @@ define internal void @bar(%pair* byval %Data) { ret void } -define void @zed(%pair* byval %Data) { +define void @zed(%pair* byval(%pair) %Data) { ; CHECK-LABEL: define {{[^@]+}}@zed -; CHECK-SAME: (%pair* byval [[DATA:%.*]]) +; CHECK-SAME: (%pair* byval(%pair) [[DATA:%.*]]) ; CHECK-NEXT: [[DATA_0:%.*]] = getelementptr [[PAIR:%.*]], %pair* [[DATA]], i32 0, i32 0 ; CHECK-NEXT: [[DATA_0_VAL:%.*]] = load i32, i32* [[DATA_0]], align 4 ; CHECK-NEXT: [[DATA_1:%.*]] = getelementptr [[PAIR]], %pair* [[DATA]], i32 0, i32 1 @@ -34,6 +34,6 @@ define void @zed(%pair* byval %Data) { ; CHECK-NEXT: call void @bar(i32 [[DATA_0_VAL]], i32 [[DATA_1_VAL]]) ; CHECK-NEXT: ret void ; - call void @bar(%pair* byval %Data) + call void @bar(%pair* byval(%pair) %Data) ret void } diff --git a/llvm/test/Transforms/ArgumentPromotion/variadic.ll b/llvm/test/Transforms/ArgumentPromotion/variadic.ll index 2b35c5aceb929..98e9afc352812 100644 --- a/llvm/test/Transforms/ArgumentPromotion/variadic.ll +++ b/llvm/test/Transforms/ArgumentPromotion/variadic.ll @@ -19,11 +19,11 @@ define i32 @main(i32 %argc, i8** nocapture readnone %argv) #0 { ; CHECK-LABEL: define {{[^@]+}}@main ; CHECK-SAME: (i32 [[ARGC:%.*]], i8** nocapture readnone [[ARGV:%.*]]) ; CHECK-NEXT: entry: -; CHECK-NEXT: tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval align 8 @t45) +; CHECK-NEXT: tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval(%struct.tt0) align 8 @t45) ; CHECK-NEXT: ret i32 0 ; entry: - tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval align 8 @t45) + tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval(%struct.tt0) align 8 @t45) ret i32 0 } diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll index 5b17d8b29d470..034151a0f1700 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll @@ -7,11 +7,11 @@ %struct.ss = type { i32, i64 } ; Don't drop 'byval' on %X here. -define internal i32 @f(%struct.ss* byval %b, i32* byval %X, i32 %i) nounwind { +define internal i32 @f(%struct.ss* byval(%struct.ss) %b, i32* byval(i32) %X, i32 %i) nounwind { ; ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@f -; IS__TUNIT_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 8 dereferenceable(12) [[B:%.*]], i32* noalias nocapture nofree nonnull byval align 4 dereferenceable(4) [[X:%.*]], i32 noundef [[I:%.*]]) [[ATTR0:#.*]] { +; IS__TUNIT_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 8 dereferenceable(12) [[B:%.*]], i32* noalias nocapture nofree nonnull byval(i32) align 4 dereferenceable(4) [[X:%.*]], i32 noundef [[I:%.*]]) [[ATTR0:#.*]] { ; IS__TUNIT_OPM-NEXT: entry: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__TUNIT_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 8 @@ -44,7 +44,7 @@ define internal i32 @f(%struct.ss* byval %b, i32* byval %X, i32 %i) nounwind { ; ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f -; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 8 dereferenceable(12) [[B:%.*]], i32* noalias nocapture nofree nonnull byval align 4 dereferenceable(4) [[X:%.*]]) [[ATTR0:#.*]] { +; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 8 dereferenceable(12) [[B:%.*]], i32* noalias nocapture nofree nonnull byval(i32) align 4 dereferenceable(4) [[X:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__CGSCC_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 8 @@ -100,7 +100,7 @@ define i32 @test(i32* %X) { ; IS__TUNIT_OPM-NEXT: store i32 1, i32* [[TMP1]], align 8 ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; IS__TUNIT_OPM-NEXT: store i64 2, i64* [[TMP4]], align 4 -; IS__TUNIT_OPM-NEXT: [[C:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readonly byval align 8 dereferenceable(12) [[S]], i32* nocapture nofree readonly byval align 4 [[X]], i32 noundef zeroext 0) [[ATTR0]] +; IS__TUNIT_OPM-NEXT: [[C:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readonly byval(%struct.ss) align 8 dereferenceable(12) [[S]], i32* nocapture nofree readonly byval(i32) align 4 [[X]], i32 noundef zeroext 0) [[ATTR0]] ; IS__TUNIT_OPM-NEXT: ret i32 [[C]] ; ; IS__TUNIT_NPM: Function Attrs: nofree nosync nounwind readnone willreturn @@ -129,7 +129,7 @@ define i32 @test(i32* %X) { ; IS__CGSCC_OPM-NEXT: store i32 1, i32* [[TMP1]], align 8 ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; IS__CGSCC_OPM-NEXT: store i64 2, i64* [[TMP4]], align 4 -; IS__CGSCC_OPM-NEXT: [[C:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readnone byval align 8 dereferenceable(12) [[S]], i32* noalias nocapture nofree nonnull readnone byval align 4 dereferenceable(4) [[X]]) [[ATTR1:#.*]] +; IS__CGSCC_OPM-NEXT: [[C:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readnone byval(%struct.ss) align 8 dereferenceable(12) [[S]], i32* noalias nocapture nofree nonnull readnone byval(i32) align 4 dereferenceable(4) [[X]]) [[ATTR1:#.*]] ; IS__CGSCC_OPM-NEXT: ret i32 [[C]] ; ; IS__CGSCC_NPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn @@ -156,7 +156,7 @@ entry: %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 store i64 2, i64* %tmp4, align 4 - %c = call i32 @f( %struct.ss* byval %S, i32* byval %X, i32 zeroext 0) + %c = call i32 @f(%struct.ss* byval(%struct.ss) %S, i32* byval(i32) %X, i32 zeroext 0) ret i32 %c } diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll index 898c6abb2e45f..1728b3c6ecc00 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll @@ -6,10 +6,10 @@ %struct.ss = type { i32, i64 } -define internal void @f(%struct.ss* byval %b, i32* byval %X) nounwind { +define internal void @f(%struct.ss* byval(%struct.ss) %b, i32* byval(i32) %X) nounwind { ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f -; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 8 dereferenceable(12) [[B:%.*]], i32* noalias nocapture nofree nonnull writeonly byval align 4 dereferenceable(4) [[X:%.*]]) [[ATTR0:#.*]] { +; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 8 dereferenceable(12) [[B:%.*]], i32* noalias nocapture nofree nonnull writeonly byval(i32) align 4 dereferenceable(4) [[X:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__CGSCC_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 8 @@ -87,6 +87,6 @@ entry: store i32 1, i32* %tmp1, align 8 %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 store i64 2, i64* %tmp4, align 4 - call void @f( %struct.ss* byval %S, i32* byval %X) + call void @f(%struct.ss* byval(%struct.ss) %S, i32* byval(i32) %X) ret i32 0 } diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll index f9ada827e25e3..4332e7fed5f0e 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll @@ -8,10 +8,10 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1 %struct.ss = type { i32, i64 } -define internal i32 @f(%struct.ss* byval %b) nounwind { +define internal i32 @f(%struct.ss* byval(%struct.ss) %b) nounwind { ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@f -; IS__TUNIT_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 8 dereferenceable(12) [[B:%.*]]) [[ATTR0:#.*]] { +; IS__TUNIT_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 8 dereferenceable(12) [[B:%.*]]) [[ATTR0:#.*]] { ; IS__TUNIT_OPM-NEXT: entry: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__TUNIT_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 8 @@ -36,7 +36,7 @@ define internal i32 @f(%struct.ss* byval %b) nounwind { ; ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f -; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 32 dereferenceable(12) [[B:%.*]]) [[ATTR0:#.*]] { +; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 32 dereferenceable(12) [[B:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__CGSCC_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 32 @@ -68,10 +68,10 @@ entry: } -define internal i32 @g(%struct.ss* byval align 32 %b) nounwind { +define internal i32 @g(%struct.ss* byval(%struct.ss) align 32 %b) nounwind { ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@g -; IS__TUNIT_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 32 dereferenceable(12) [[B:%.*]]) [[ATTR0]] { +; IS__TUNIT_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 32 dereferenceable(12) [[B:%.*]]) [[ATTR0]] { ; IS__TUNIT_OPM-NEXT: entry: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__TUNIT_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 32 @@ -96,7 +96,7 @@ define internal i32 @g(%struct.ss* byval align 32 %b) nounwind { ; ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@g -; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval align 32 dereferenceable(12) [[B:%.*]]) [[ATTR0]] { +; IS__CGSCC_OPM-SAME: (%struct.ss* noalias nocapture nofree noundef nonnull byval(%struct.ss) align 32 dereferenceable(12) [[B:%.*]]) [[ATTR0]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = getelementptr [[STRUCT_SS:%.*]], %struct.ss* [[B]], i32 0, i32 0 ; IS__CGSCC_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP]], align 32 @@ -138,8 +138,8 @@ define i32 @main() nounwind { ; IS__TUNIT_OPM-NEXT: store i32 1, i32* [[TMP1]], align 8 ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; IS__TUNIT_OPM-NEXT: store i64 2, i64* [[TMP4]], align 4 -; IS__TUNIT_OPM-NEXT: [[C0:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readonly byval align 8 dereferenceable(12) [[S]]) [[ATTR0]] -; IS__TUNIT_OPM-NEXT: [[C1:%.*]] = call i32 @g(%struct.ss* noalias nocapture nofree noundef nonnull readonly byval align 32 dereferenceable(12) [[S]]) [[ATTR0]] +; IS__TUNIT_OPM-NEXT: [[C0:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readonly byval(%struct.ss) align 8 dereferenceable(12) [[S]]) [[ATTR0]] +; IS__TUNIT_OPM-NEXT: [[C1:%.*]] = call i32 @g(%struct.ss* noalias nocapture nofree noundef nonnull readonly byval(%struct.ss) align 32 dereferenceable(12) [[S]]) [[ATTR0]] ; IS__TUNIT_OPM-NEXT: [[A:%.*]] = add i32 [[C0]], [[C1]] ; IS__TUNIT_OPM-NEXT: ret i32 [[A]] ; @@ -174,8 +174,8 @@ define i32 @main() nounwind { ; IS__CGSCC_OPM-NEXT: store i32 1, i32* [[TMP1]], align 32 ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; IS__CGSCC_OPM-NEXT: store i64 2, i64* [[TMP4]], align 4 -; IS__CGSCC_OPM-NEXT: [[C0:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readnone byval align 32 dereferenceable(12) [[S]]) [[ATTR1:#.*]] -; IS__CGSCC_OPM-NEXT: [[C1:%.*]] = call i32 @g(%struct.ss* noalias nocapture nofree noundef nonnull readnone byval align 32 dereferenceable(12) [[S]]) [[ATTR1]] +; IS__CGSCC_OPM-NEXT: [[C0:%.*]] = call i32 @f(%struct.ss* noalias nocapture nofree noundef nonnull readnone byval(%struct.ss) align 32 dereferenceable(12) [[S]]) [[ATTR1:#.*]] +; IS__CGSCC_OPM-NEXT: [[C1:%.*]] = call i32 @g(%struct.ss* noalias nocapture nofree noundef nonnull readnone byval(%struct.ss) align 32 dereferenceable(12) [[S]]) [[ATTR1]] ; IS__CGSCC_OPM-NEXT: [[A:%.*]] = add i32 [[C0]], [[C1]] ; IS__CGSCC_OPM-NEXT: ret i32 [[A]] ; @@ -207,8 +207,8 @@ entry: store i32 1, i32* %tmp1, align 8 %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 store i64 2, i64* %tmp4, align 4 - %c0 = call i32 @f(%struct.ss* byval %S) nounwind - %c1 = call i32 @g(%struct.ss* byval %S) nounwind + %c0 = call i32 @f(%struct.ss* byval(%struct.ss) %S) nounwind + %c1 = call i32 @g(%struct.ss* byval(%struct.ss) %S) nounwind %a = add i32 %c0, %c1 ret i32 %a } diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/dbg.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/dbg.ll index 64d5adaa75020..bd14a2b636ab1 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/dbg.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/dbg.ll @@ -22,7 +22,7 @@ define internal void @test(i32** %X) !dbg !2 { %struct.pair = type { i32, i32 } -define internal void @test_byval(%struct.pair* byval %P) { +define internal void @test_byval(%struct.pair* byval(%struct.pair) %P) { ; CHECK-LABEL: define {{[^@]+}}@test_byval() { ; CHECK-NEXT: call void @sink(i32 noundef 0) ; CHECK-NEXT: ret void diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll index 6dffe1e893e13..47c5eba84b77f 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll @@ -30,14 +30,14 @@ define void @run() { ; IS__CGSCC____-NEXT: unreachable ; entry: - tail call i8 @UseLongDoubleUnsafely(%union.u* byval align 16 bitcast (%struct.s* @b to %union.u*)) - tail call x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 bitcast (%struct.s* @b to %union.u*)) + tail call i8 @UseLongDoubleUnsafely(%union.u* byval(%union.u) align 16 bitcast (%struct.s* @b to %union.u*)) + tail call x86_fp80 @UseLongDoubleSafely(%union.u* byval(%union.u) align 16 bitcast (%struct.s* @b to %union.u*)) call i64 @AccessPaddingOfStruct(%struct.Foo* @a) call i64 @CaptureAStruct(%struct.Foo* @a) ret void } -define internal i8 @UseLongDoubleUnsafely(%union.u* byval align 16 %arg) { +define internal i8 @UseLongDoubleUnsafely(%union.u* byval(%union.u) align 16 %arg) { ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@UseLongDoubleUnsafely ; IS__CGSCC____-SAME: () [[ATTR1:#.*]] { @@ -51,7 +51,7 @@ entry: ret i8 %result } -define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 %arg) { +define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval(%union.u) align 16 %arg) { ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@UseLongDoubleSafely ; IS__CGSCC____-SAME: () [[ATTR1]] { @@ -62,7 +62,7 @@ define internal x86_fp80 @UseLongDoubleSafely(%union.u* byval align 16 %arg) { ret x86_fp80 %fp80 } -define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval %a) { +define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval(%struct.Foo) %a) { ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@AccessPaddingOfStruct ; IS__CGSCC____-SAME: () [[ATTR1]] { @@ -73,9 +73,9 @@ define internal i64 @AccessPaddingOfStruct(%struct.Foo* byval %a) { ret i64 %v } -define internal i64 @CaptureAStruct(%struct.Foo* byval %a) { +define internal i64 @CaptureAStruct(%struct.Foo* byval(%struct.Foo) %a) { ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@CaptureAStruct -; IS__CGSCC_OPM-SAME: (%struct.Foo* noalias nofree byval [[A:%.*]]) +; IS__CGSCC_OPM-SAME: (%struct.Foo* noalias nofree byval(%struct.Foo) [[A:%.*]]) ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[A_PTR:%.*]] = alloca %struct.Foo* ; IS__CGSCC_OPM-NEXT: br label [[LOOP:%.*]] diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/tail.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/tail.ll index c8c4dc4fb5288..7aa467a780c9c 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/tail.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/tail.ll @@ -11,9 +11,9 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" declare i8* @foo(%pair*) -define internal void @bar(%pair* byval %Data) { +define internal void @bar(%pair* byval(%pair) %Data) { ; IS________OPM-LABEL: define {{[^@]+}}@bar -; IS________OPM-SAME: (%pair* noalias nonnull byval dereferenceable(8) [[DATA:%.*]]) { +; IS________OPM-SAME: (%pair* noalias nonnull byval(%pair) dereferenceable(8) [[DATA:%.*]]) { ; IS________OPM-NEXT: [[TMP1:%.*]] = tail call i8* @foo(%pair* nonnull dereferenceable(8) [[DATA]]) ; IS________OPM-NEXT: ret void ; @@ -41,14 +41,14 @@ define internal void @bar(%pair* byval %Data) { ret void } -define void @zed(%pair* byval %Data) { +define void @zed(%pair* byval(%pair) %Data) { ; IS________OPM-LABEL: define {{[^@]+}}@zed -; IS________OPM-SAME: (%pair* noalias nocapture nonnull readonly byval dereferenceable(8) [[DATA:%.*]]) { -; IS________OPM-NEXT: call void @bar(%pair* noalias nocapture nonnull readonly byval dereferenceable(8) [[DATA]]) +; IS________OPM-SAME: (%pair* noalias nocapture nonnull readonly byval(%pair) dereferenceable(8) [[DATA:%.*]]) { +; IS________OPM-NEXT: call void @bar(%pair* noalias nocapture nonnull readonly byval(%pair) dereferenceable(8) [[DATA]]) ; IS________OPM-NEXT: ret void ; ; IS________NPM-LABEL: define {{[^@]+}}@zed -; IS________NPM-SAME: (%pair* noalias nocapture nonnull readonly byval dereferenceable(8) [[DATA:%.*]]) { +; IS________NPM-SAME: (%pair* noalias nocapture nonnull readonly byval(%pair) dereferenceable(8) [[DATA:%.*]]) { ; IS________NPM-NEXT: [[DATA_CAST:%.*]] = bitcast %pair* [[DATA]] to i32* ; IS________NPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[DATA_CAST]], align 1 ; IS________NPM-NEXT: [[DATA_0_1:%.*]] = getelementptr [[PAIR:%.*]], %pair* [[DATA]], i32 0, i32 1 @@ -56,6 +56,6 @@ define void @zed(%pair* byval %Data) { ; IS________NPM-NEXT: call void @bar(i32 [[TMP1]], i32 [[TMP2]]) ; IS________NPM-NEXT: ret void ; - call void @bar(%pair* byval %Data) + call void @bar(%pair* byval(%pair) %Data) ret void } diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/variadic.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/variadic.ll index e33c5e5e65175..39672674f10ab 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/variadic.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/variadic.ll @@ -21,11 +21,11 @@ define i32 @main(i32 %argc, i8** nocapture readnone %argv) #0 { ; CHECK-LABEL: define {{[^@]+}}@main ; CHECK-SAME: (i32 [[ARGC:%.*]], i8** nocapture nofree readnone [[ARGV:%.*]]) { ; CHECK-NEXT: entry: -; CHECK-NEXT: tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* noundef nonnull byval align 8 dereferenceable(16) @t45) +; CHECK-NEXT: tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* noundef nonnull byval(%struct.tt0) align 8 dereferenceable(16) @t45) ; CHECK-NEXT: ret i32 0 ; entry: - tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval align 8 @t45) + tail call void (i8*, i8*, i8*, i8*, i8*, ...) @callee_t0f(i8* undef, i8* undef, i8* undef, i8* undef, i8* undef, %struct.tt0* byval(%struct.tt0) align 8 @t45) ret i32 0 } diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll b/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll index 8334ae066a69e..e2fbaa8ec284a 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll @@ -8,10 +8,10 @@ ; PR5038 %struct.MYstr = type { i8, i32 } @mystr = internal global %struct.MYstr zeroinitializer ; <%struct.MYstr*> [#uses=3] -define internal void @vfu1(%struct.MYstr* byval align 4 %u) nounwind { +define internal void @vfu1(%struct.MYstr* byval(%struct.MYstr) align 4 %u) nounwind { ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@vfu1 -; IS__CGSCC_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull writeonly byval align 8 dereferenceable(8) [[U:%.*]]) [[ATTR0:#.*]] { +; IS__CGSCC_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull writeonly byval(%struct.MYstr) align 8 dereferenceable(8) [[U:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[TMP0:%.*]] = getelementptr [[STRUCT_MYSTR:%.*]], %struct.MYstr* [[U]], i32 0, i32 1 ; IS__CGSCC_OPM-NEXT: store i32 99, i32* [[TMP0]], align 4 @@ -49,10 +49,10 @@ return: ; preds = %entry ret void } -define internal i32 @vfu2(%struct.MYstr* byval align 4 %u) nounwind readonly { +define internal i32 @vfu2(%struct.MYstr* byval(%struct.MYstr) align 4 %u) nounwind readonly { ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readonly willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@vfu2 -; IS__TUNIT_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull readonly byval align 8 dereferenceable(8) [[U:%.*]]) [[ATTR0:#.*]] { +; IS__TUNIT_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull readonly byval(%struct.MYstr) align 8 dereferenceable(8) [[U:%.*]]) [[ATTR0:#.*]] { ; IS__TUNIT_OPM-NEXT: entry: ; IS__TUNIT_OPM-NEXT: [[TMP0:%.*]] = getelementptr [[STRUCT_MYSTR:%.*]], %struct.MYstr* @mystr, i32 0, i32 1 ; IS__TUNIT_OPM-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 @@ -106,7 +106,7 @@ define i32 @unions() nounwind { ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@unions ; IS__TUNIT_OPM-SAME: () [[ATTR1:#.*]] { ; IS__TUNIT_OPM-NEXT: entry: -; IS__TUNIT_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2(%struct.MYstr* nocapture nofree noundef nonnull readonly byval align 8 dereferenceable(8) @mystr) [[ATTR0]] +; IS__TUNIT_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2(%struct.MYstr* nocapture nofree noundef nonnull readonly byval(%struct.MYstr) align 8 dereferenceable(8) @mystr) [[ATTR0]] ; IS__TUNIT_OPM-NEXT: ret i32 [[RESULT]] ; ; IS__TUNIT_NPM: Function Attrs: nofree nosync nounwind willreturn @@ -128,15 +128,15 @@ define i32 @unions() nounwind { ; IS__CGSCC____-NEXT: ret i32 [[RESULT]] ; entry: - call void @vfu1(%struct.MYstr* byval align 4 @mystr) nounwind - %result = call i32 @vfu2(%struct.MYstr* byval align 4 @mystr) nounwind + call void @vfu1(%struct.MYstr* byval(%struct.MYstr) align 4 @mystr) nounwind + %result = call i32 @vfu2(%struct.MYstr* byval(%struct.MYstr) align 4 @mystr) nounwind ret i32 %result } -define internal i32 @vfu2_v2(%struct.MYstr* byval align 4 %u) nounwind readonly { +define internal i32 @vfu2_v2(%struct.MYstr* byval(%struct.MYstr) align 4 %u) nounwind readonly { ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@vfu2_v2 -; IS__TUNIT_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull byval align 8 dereferenceable(8) [[U:%.*]]) [[ATTR2:#.*]] { +; IS__TUNIT_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull byval(%struct.MYstr) align 8 dereferenceable(8) [[U:%.*]]) [[ATTR2:#.*]] { ; IS__TUNIT_OPM-NEXT: entry: ; IS__TUNIT_OPM-NEXT: [[Z:%.*]] = getelementptr [[STRUCT_MYSTR:%.*]], %struct.MYstr* [[U]], i32 0, i32 1 ; IS__TUNIT_OPM-NEXT: store i32 99, i32* [[Z]], align 4 @@ -169,7 +169,7 @@ define internal i32 @vfu2_v2(%struct.MYstr* byval align 4 %u) nounwind readonly ; ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@vfu2_v2 -; IS__CGSCC_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull byval align 8 dereferenceable(8) [[U:%.*]]) [[ATTR0]] { +; IS__CGSCC_OPM-SAME: (%struct.MYstr* noalias nocapture nofree noundef nonnull byval(%struct.MYstr) align 8 dereferenceable(8) [[U:%.*]]) [[ATTR0]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[Z:%.*]] = getelementptr [[STRUCT_MYSTR:%.*]], %struct.MYstr* [[U]], i32 0, i32 1 ; IS__CGSCC_OPM-NEXT: store i32 99, i32* [[Z]], align 4 @@ -217,7 +217,7 @@ define i32 @unions_v2() nounwind { ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@unions_v2 ; IS__TUNIT_OPM-SAME: () [[ATTR2]] { ; IS__TUNIT_OPM-NEXT: entry: -; IS__TUNIT_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2_v2(%struct.MYstr* nocapture nofree noundef nonnull readonly byval align 8 dereferenceable(8) @mystr) [[ATTR2]] +; IS__TUNIT_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2_v2(%struct.MYstr* nocapture nofree noundef nonnull readonly byval(%struct.MYstr) align 8 dereferenceable(8) @mystr) [[ATTR2]] ; IS__TUNIT_OPM-NEXT: ret i32 [[RESULT]] ; ; IS__TUNIT_NPM: Function Attrs: nofree nosync nounwind readnone willreturn @@ -235,7 +235,7 @@ define i32 @unions_v2() nounwind { ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@unions_v2 ; IS__CGSCC_OPM-SAME: () [[ATTR0]] { ; IS__CGSCC_OPM-NEXT: entry: -; IS__CGSCC_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2_v2(%struct.MYstr* noalias nocapture nofree noundef nonnull readnone byval align 8 dereferenceable(8) @mystr) [[ATTR3:#.*]] +; IS__CGSCC_OPM-NEXT: [[RESULT:%.*]] = call i32 @vfu2_v2(%struct.MYstr* noalias nocapture nofree noundef nonnull readnone byval(%struct.MYstr) align 8 dereferenceable(8) @mystr) [[ATTR3:#.*]] ; IS__CGSCC_OPM-NEXT: ret i32 [[RESULT]] ; ; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readonly willreturn @@ -250,7 +250,7 @@ define i32 @unions_v2() nounwind { ; IS__CGSCC_NPM-NEXT: ret i32 [[RESULT]] ; entry: - call void @vfu1(%struct.MYstr* byval align 4 @mystr) nounwind - %result = call i32 @vfu2_v2(%struct.MYstr* byval align 4 @mystr) nounwind + call void @vfu1(%struct.MYstr* byval(%struct.MYstr) align 4 @mystr) nounwind + %result = call i32 @vfu2_v2(%struct.MYstr* byval(%struct.MYstr) align 4 @mystr) nounwind ret i32 %result } diff --git a/llvm/test/Transforms/Attributor/readattrs.ll b/llvm/test/Transforms/Attributor/readattrs.ll index c70cd1f5a6727..e7e02c791b7ec 100644 --- a/llvm/test/Transforms/Attributor/readattrs.ll +++ b/llvm/test/Transforms/Attributor/readattrs.ll @@ -292,10 +292,10 @@ define void @unsound_readonly(i8* %ignored, i8* %escaped_then_written) { ;{ declare void @escape_i8(i8* %ptr) -define void @byval_not_readonly_1(i8* byval %written) readonly { +define void @byval_not_readonly_1(i8* byval(i8) %written) readonly { ; CHECK: Function Attrs: readonly ; CHECK-LABEL: define {{[^@]+}}@byval_not_readonly_1 -; CHECK-SAME: (i8* noalias nonnull byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR2]] { +; CHECK-SAME: (i8* noalias nonnull byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR2]] { ; CHECK-NEXT: call void @escape_i8(i8* nonnull dereferenceable(1) [[WRITTEN]]) ; CHECK-NEXT: ret void ; @@ -303,16 +303,16 @@ define void @byval_not_readonly_1(i8* byval %written) readonly { ret void } -define void @byval_not_readonly_2(i8* byval %written) readonly { +define void @byval_not_readonly_2(i8* byval(i8) %written) readonly { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@byval_not_readonly_2 -; IS__TUNIT____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { +; IS__TUNIT____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { ; IS__TUNIT____-NEXT: store i8 0, i8* [[WRITTEN]], align 1 ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@byval_not_readonly_2 -; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { +; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { ; IS__CGSCC____-NEXT: store i8 0, i8* [[WRITTEN]], align 1 ; IS__CGSCC____-NEXT: ret void ; @@ -320,10 +320,10 @@ define void @byval_not_readonly_2(i8* byval %written) readonly { ret void } -define void @byval_not_readnone_1(i8* byval %written) readnone { +define void @byval_not_readnone_1(i8* byval(i8) %written) readnone { ; CHECK: Function Attrs: readnone ; CHECK-LABEL: define {{[^@]+}}@byval_not_readnone_1 -; CHECK-SAME: (i8* noalias nonnull byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR9:#.*]] { +; CHECK-SAME: (i8* noalias nonnull byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR9:#.*]] { ; CHECK-NEXT: call void @escape_i8(i8* nonnull dereferenceable(1) [[WRITTEN]]) ; CHECK-NEXT: ret void ; @@ -331,16 +331,16 @@ define void @byval_not_readnone_1(i8* byval %written) readnone { ret void } -define void @byval_not_readnone_2(i8* byval %written) readnone { +define void @byval_not_readnone_2(i8* byval(i8) %written) readnone { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@byval_not_readnone_2 -; IS__TUNIT____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { +; IS__TUNIT____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { ; IS__TUNIT____-NEXT: store i8 0, i8* [[WRITTEN]], align 1 ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@byval_not_readnone_2 -; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { +; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { ; IS__CGSCC____-NEXT: store i8 0, i8* [[WRITTEN]], align 1 ; IS__CGSCC____-NEXT: ret void ; @@ -348,16 +348,16 @@ define void @byval_not_readnone_2(i8* byval %written) readnone { ret void } -define void @byval_no_fnarg(i8* byval %written) { +define void @byval_no_fnarg(i8* byval(i8) %written) { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@byval_no_fnarg -; IS__TUNIT____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { +; IS__TUNIT____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { ; IS__TUNIT____-NEXT: store i8 0, i8* [[WRITTEN]], align 1 ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@byval_no_fnarg -; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { +; IS__CGSCC____-SAME: (i8* noalias nocapture nofree nonnull writeonly byval(i8) dereferenceable(1) [[WRITTEN:%.*]]) [[ATTR1]] { ; IS__CGSCC____-NEXT: store i8 0, i8* [[WRITTEN]], align 1 ; IS__CGSCC____-NEXT: ret void ; diff --git a/llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll b/llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll index f7a203b1ded0c..c75b71301aad3 100644 --- a/llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll +++ b/llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll @@ -426,7 +426,7 @@ declare dso_local void @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2E declare dso_local i8* @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_M_local_dataEv(%"class.std::__cxx11::basic_string.3.189.282.375.468.561.747.840.933.1398.1677.1956.2235.2793.3351.3444.3537.3630.3723.3816.4095"*) #4 align 2 ; Function Attrs: uwtable -declare dso_local void @_ZN9__gnu_cxx14__alloc_traitsISaIcEcE17_S_select_on_copyERKS1_(%"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"* noalias sret, %"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"* dereferenceable(1)) #0 align 2 +declare dso_local void @_ZN9__gnu_cxx14__alloc_traitsISaIcEcE17_S_select_on_copyERKS1_(%"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"* noalias sret(%"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"), %"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"* dereferenceable(1)) #0 align 2 ; Function Attrs: nounwind uwtable declare dso_local dereferenceable(1) %"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"* @_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE16_M_get_allocatorEv(%"class.std::__cxx11::basic_string.3.189.282.375.468.561.747.840.933.1398.1677.1956.2235.2793.3351.3444.3537.3630.3723.3816.4095"*) #4 align 2 @@ -459,7 +459,7 @@ declare dso_local i8* @_ZSt9addressofIcEPT_RS0_(i8* dereferenceable(1)) #11 declare dso_local i8* @_ZSt11__addressofIcEPT_RS0_(i8* dereferenceable(1)) #11 ; Function Attrs: nounwind uwtable -declare dso_local void @_ZNSt16allocator_traitsISaIcEE37select_on_container_copy_constructionERKS0_(%"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"* noalias sret, %"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"* dereferenceable(1)) #4 align 2 +declare dso_local void @_ZNSt16allocator_traitsISaIcEE37select_on_container_copy_constructionERKS0_(%"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"* noalias sret(%"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"), %"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"* dereferenceable(1)) #4 align 2 ; Function Attrs: nounwind uwtable declare dso_local void @_ZNSaIcEC2ERKS_(%"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"*, %"class.std::allocator.0.72.258.351.444.537.630.816.909.1002.1467.1746.2025.2304.2862.3420.3513.3606.3699.3792.3885.4164"* dereferenceable(1)) unnamed_addr #4 align 2 @@ -1278,13 +1278,13 @@ declare dso_local void @_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_trait declare dso_local %"struct.std::_Rb_tree_node.83.269.362.455.548.641.827.920.1013.1478.1757.2036.2315.2873.3431.3524.3617.3710.3803.3896.4175"* @_ZNSt8_Rb_treeINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESt4pairIKS5_N9benchmark7CounterEESt10_Select1stISA_ESt4lessIS5_ESaISA_EE7_M_copyERKSG_(%"class.std::_Rb_tree.49.235.328.421.514.607.793.886.979.1444.1723.2002.2281.2839.3397.3490.3583.3676.3769.3862.4141"*, %"class.std::_Rb_tree.49.235.328.421.514.607.793.886.979.1444.1723.2002.2281.2839.3397.3490.3583.3676.3769.3862.4141"* dereferenceable(48)) #0 align 2 ; Function Attrs: uwtable -declare dso_local void @_ZN9__gnu_cxx14__alloc_traitsISaISt13_Rb_tree_nodeISt4pairIKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEN9benchmark7CounterEEEESD_E17_S_select_on_copyERKSE_(%"class.std::allocator.8.76.262.355.448.541.634.820.913.1006.1471.1750.2029.2308.2866.3424.3517.3610.3703.3796.3889.4168"* noalias sret, %"class.std::allocator.8.76.262.355.448.541.634.820.913.1006.1471.1750.2029.2308.2866.3424.3517.3610.3703.3796.3889.4168"* dereferenceable(1)) #0 align 2 +declare dso_local void @_ZN9__gnu_cxx14__alloc_traitsISaISt13_Rb_tree_nodeISt4pairIKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEN9benchmark7CounterEEEESD_E17_S_select_on_copyERKSE_(%"class.std::allocator.8.76.262.355.448.541.634.820.913.1006.1471.1750.2029.2308.2866.3424.3517.3610.3703.3796.3889.4168"* noalias sret(%"class.std::allocator.8.76.262.355.448.541.634.820.913.1006.1471.1750.2029.2308.2866.3424.3517.3610.3703.3796.3889.4168"), %"class.std::allocator.8.76.262.355.448.541.634.820.913.1006.1471.1750.2029.2308.2866.3424.3517.3610.3703.3796.3889.4168"* dereferenceable(1)) #0 align 2 ; Function Attrs: nounwind uwtable declare dso_local void @_ZNSt20_Rb_tree_key_compareISt4lessINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEEEC2ERKS7_(%"struct.std::_Rb_tree_key_compare.45.231.324.417.510.603.789.882.975.1440.1719.1998.2277.2835.3393.3486.3579.3672.3765.3858.4137"*, %"struct.std::less.44.230.323.416.509.602.788.881.974.1439.1718.1997.2276.2834.3392.3485.3578.3671.3764.3857.4136"* dereferenceable(1)) unnamed_addr #4 align 2 ; Function Attrs: nounwind uwtable -declare dso_local void @_ZNSt16allocator_traitsISaISt13_Rb_tree_nodeISt4pairIKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEN9benchmark7CounterEEEEE37select_on_container_copy_constructionERKSD_(%"class.std::allocator.8.76.262.355.448.541.634.820.913.1006.1471.1750.2029.2308.2866.3424.3517.3610.3703.3796.3889.4168"* noalias sret, %"class.std::allocator.8.76.262.355.448.541.634.820.913.1006.1471.1750.2029.2308.2866.3424.3517.3610.3703.3796.3889.4168"* dereferenceable(1)) #4 align 2 +declare dso_local void @_ZNSt16allocator_traitsISaISt13_Rb_tree_nodeISt4pairIKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEN9benchmark7CounterEEEEE37select_on_container_copy_constructionERKSD_(%"class.std::allocator.8.76.262.355.448.541.634.820.913.1006.1471.1750.2029.2308.2866.3424.3517.3610.3703.3796.3889.4168"* noalias sret(%"class.std::allocator.8.76.262.355.448.541.634.820.913.1006.1471.1750.2029.2308.2866.3424.3517.3610.3703.3796.3889.4168"), %"class.std::allocator.8.76.262.355.448.541.634.820.913.1006.1471.1750.2029.2308.2866.3424.3517.3610.3703.3796.3889.4168"* dereferenceable(1)) #4 align 2 ; Function Attrs: nounwind uwtable declare dso_local void @_ZNSaISt13_Rb_tree_nodeISt4pairIKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEN9benchmark7CounterEEEEC2ERKSC_(%"class.std::allocator.8.76.262.355.448.541.634.820.913.1006.1471.1750.2029.2308.2866.3424.3517.3610.3703.3796.3889.4168"*, %"class.std::allocator.8.76.262.355.448.541.634.820.913.1006.1471.1750.2029.2308.2866.3424.3517.3610.3703.3796.3889.4168"* dereferenceable(1)) unnamed_addr #4 align 2 diff --git a/llvm/test/Transforms/Attributor/value-simplify.ll b/llvm/test/Transforms/Attributor/value-simplify.ll index ae96761507ba5..586f3486c6fb2 100644 --- a/llvm/test/Transforms/Attributor/value-simplify.ll +++ b/llvm/test/Transforms/Attributor/value-simplify.ll @@ -490,10 +490,10 @@ define %struct.X* @complicated_args_nest() { } @S = external global %struct.X -define internal void @test_byval(%struct.X* byval %a) { +define internal void @test_byval(%struct.X* byval(%struct.X) %a) { ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test_byval -; IS__CGSCC_OPM-SAME: (%struct.X* noalias nocapture nofree noundef nonnull writeonly byval align 8 dereferenceable(8) [[A:%.*]]) [[ATTR1]] { +; IS__CGSCC_OPM-SAME: (%struct.X* noalias nocapture nofree noundef nonnull writeonly byval(%struct.X) align 8 dereferenceable(8) [[A:%.*]]) [[ATTR1]] { ; IS__CGSCC_OPM-NEXT: [[G0:%.*]] = getelementptr [[STRUCT_X:%.*]], %struct.X* [[A]], i32 0, i32 0 ; IS__CGSCC_OPM-NEXT: store i8* null, i8** [[G0]], align 8 ; IS__CGSCC_OPM-NEXT: ret void @@ -532,7 +532,7 @@ define void @complicated_args_byval() { ret void } -define internal i8*@test_byval2(%struct.X* byval %a) { +define internal i8*@test_byval2(%struct.X* byval(%struct.X) %a) { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readonly willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@test_byval2 ; IS__TUNIT____-SAME: () [[ATTR3:#.*]] { diff --git a/llvm/test/Transforms/DeadArgElim/2006-06-27-struct-ret.ll b/llvm/test/Transforms/DeadArgElim/2006-06-27-struct-ret.ll index fac6dd24efb1f..571519e6eaf5f 100644 --- a/llvm/test/Transforms/DeadArgElim/2006-06-27-struct-ret.ll +++ b/llvm/test/Transforms/DeadArgElim/2006-06-27-struct-ret.ll @@ -1,11 +1,11 @@ ; RUN: opt < %s -deadargelim -disable-output -define internal void @build_delaunay({ i32 }* sret %agg.result) { +define internal void @build_delaunay({ i32 }* sret({ i32 }) %agg.result) { ret void } define void @test() { - call void @build_delaunay( { i32 }* sret null ) + call void @build_delaunay({ i32 }* sret({ i32 }) null) ret void } diff --git a/llvm/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll b/llvm/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll index ab378e9df1eec..b6c9241435e2f 100644 --- a/llvm/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll +++ b/llvm/test/Transforms/DeadArgElim/2007-12-20-ParamAttrs.ll @@ -13,7 +13,7 @@ define internal zeroext i8 @foo(i8* inreg %p, i8 signext %y, ... ) nounwind { define i32 @bar() { ; CHECK: call void @foo(i8 signext 1) [[NUW]] - %A = call zeroext i8(i8*, i8, ...) @foo(i8* inreg null, i8 signext 1, %struct* byval null ) nounwind + %A = call zeroext i8(i8*, i8, ...) @foo(i8* inreg null, i8 signext 1, %struct* byval(%struct) null ) nounwind ret i32 0 } diff --git a/llvm/test/Transforms/DeadArgElim/2008-01-16-VarargsParamAttrs.ll b/llvm/test/Transforms/DeadArgElim/2008-01-16-VarargsParamAttrs.ll index 48e43961e7a16..4032e9d3e3bf7 100644 --- a/llvm/test/Transforms/DeadArgElim/2008-01-16-VarargsParamAttrs.ll +++ b/llvm/test/Transforms/DeadArgElim/2008-01-16-VarargsParamAttrs.ll @@ -15,17 +15,17 @@ entry: ret i32 undef } -declare void @llvm.va_start(i8*) nounwind +declare void @llvm.va_start(i8*) nounwind -declare void @llvm.va_end(i8*) nounwind +declare void @llvm.va_end(i8*) nounwind define i32 @main() { entry: %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %tmp = getelementptr [4 x %struct.point], [4 x %struct.point]* @pts, i32 0, i32 0 ; <%struct.point*> [#uses=1] - %tmp1 = call i32 (i32, ...) @va1( i32 1, %struct.point* byval %tmp ) nounwind ; [#uses=0] - call void @exit( i32 0 ) noreturn nounwind + %tmp1 = call i32 (i32, ...) @va1(i32 1, %struct.point* byval(%struct.point) %tmp) nounwind ; [#uses=0] + call void @exit( i32 0 ) noreturn nounwind unreachable } -declare void @exit(i32) noreturn nounwind +declare void @exit(i32) noreturn nounwind diff --git a/llvm/test/Transforms/DeadArgElim/variadic_safety.ll b/llvm/test/Transforms/DeadArgElim/variadic_safety.ll index 2dac2f9180ed9..0e10dce3fbcd5 100644 --- a/llvm/test/Transforms/DeadArgElim/variadic_safety.ll +++ b/llvm/test/Transforms/DeadArgElim/variadic_safety.ll @@ -17,9 +17,9 @@ define internal i32 @va_func(i32 %a, i32 %b, ...) { define i32 @call_va(i32 %in) { %stacked = alloca i32 store i32 42, i32* %stacked - %res = call i32(i32, i32, ...) @va_func(i32 %in, i32 %in, [6 x i32] undef, i32* byval %stacked) + %res = call i32(i32, i32, ...) @va_func(i32 %in, i32 %in, [6 x i32] undef, i32* byval(i32) %stacked) ret i32 %res -; CHECK: call i32 (i32, i32, ...) @va_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval %stacked) +; CHECK: call i32 (i32, i32, ...) @va_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval(i32) %stacked) } define internal i32 @va_deadret_func(i32 %a, i32 %b, ...) { @@ -32,7 +32,7 @@ define internal i32 @va_deadret_func(i32 %a, i32 %b, ...) { define void @call_deadret(i32 %in) { %stacked = alloca i32 store i32 42, i32* %stacked - call i32 (i32, i32, ...) @va_deadret_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval %stacked) + call i32 (i32, i32, ...) @va_deadret_func(i32 undef, i32 %in, [6 x i32] undef, i32* byval(i32) %stacked) ret void -; CHECK: call void (i32, i32, ...) @va_deadret_func(i32 undef, i32 undef, [6 x i32] undef, i32* byval %stacked) +; CHECK: call void (i32, i32, ...) @va_deadret_func(i32 undef, i32 undef, [6 x i32] undef, i32* byval(i32) %stacked) } diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/2011-09-06-EndOfFunction.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/2011-09-06-EndOfFunction.ll index 7e46d28a9c47f..e94fd9cb23d43 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/2011-09-06-EndOfFunction.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/2011-09-06-EndOfFunction.ll @@ -6,10 +6,10 @@ target triple = "x86_64-apple-darwin" %"class.std::auto_ptr" = type { i32* } ; CHECK-LABEL: @_Z3foov( -define void @_Z3foov(%"class.std::auto_ptr"* noalias nocapture sret %agg.result) uwtable ssp { +define void @_Z3foov(%"class.std::auto_ptr"* noalias nocapture sret(%"class.std::auto_ptr") %agg.result) uwtable ssp { _ZNSt8auto_ptrIiED1Ev.exit: %temp.lvalue = alloca %"class.std::auto_ptr", align 8 - call void @_Z3barv(%"class.std::auto_ptr"* sret %temp.lvalue) + call void @_Z3barv(%"class.std::auto_ptr"* sret(%"class.std::auto_ptr") %temp.lvalue) %_M_ptr.i.i = getelementptr inbounds %"class.std::auto_ptr", %"class.std::auto_ptr"* %temp.lvalue, i64 0, i32 0 %tmp.i.i = load i32*, i32** %_M_ptr.i.i, align 8 ; CHECK-NOT: store i32* null @@ -20,4 +20,4 @@ _ZNSt8auto_ptrIiED1Ev.exit: ret void } -declare void @_Z3barv(%"class.std::auto_ptr"* sret) +declare void @_Z3barv(%"class.std::auto_ptr"* sret(%"class.std::auto_ptr")) diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/combined-partial-overwrites.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/combined-partial-overwrites.ll index ab957e0c3cf0e..9cf847b36eebb 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/combined-partial-overwrites.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/combined-partial-overwrites.ll @@ -5,7 +5,7 @@ target triple = "powerpc64le-unknown-linux" %"struct.std::complex" = type { { float, float } } -define void @_Z4testSt7complexIfE(%"struct.std::complex"* noalias nocapture sret %agg.result, i64 %c.coerce) { +define void @_Z4testSt7complexIfE(%"struct.std::complex"* noalias nocapture sret(%"struct.std::complex") %agg.result, i64 %c.coerce) { ; CHECK-LABEL: @_Z4testSt7complexIfE( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[REF_TMP:%.*]] = alloca i64, align 8 @@ -15,7 +15,7 @@ define void @_Z4testSt7complexIfE(%"struct.std::complex"* noalias nocapture sret ; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32 [[C_SROA_0_0_EXTRACT_TRUNC]] to float ; CHECK-NEXT: [[C_SROA_2_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[C_COERCE]] to i32 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[C_SROA_2_0_EXTRACT_TRUNC]] to float -; CHECK-NEXT: call void @_Z3barSt7complexIfE(%"struct.std::complex"* nonnull sret [[TMPCAST]], i64 [[C_COERCE]]) +; CHECK-NEXT: call void @_Z3barSt7complexIfE(%"struct.std::complex"* nonnull sret(%"struct.std::complex") [[TMPCAST]], i64 [[C_COERCE]]) ; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[REF_TMP]], align 8 ; CHECK-NEXT: [[_M_VALUE_REALP_I_I:%.*]] = getelementptr inbounds %"struct.std::complex", %"struct.std::complex"* [[AGG_RESULT:%.*]], i64 0, i32 0, i32 0 ; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 32 @@ -43,7 +43,7 @@ entry: %0 = bitcast i32 %c.sroa.0.0.extract.trunc to float %c.sroa.2.0.extract.trunc = trunc i64 %c.coerce to i32 %1 = bitcast i32 %c.sroa.2.0.extract.trunc to float - call void @_Z3barSt7complexIfE(%"struct.std::complex"* nonnull sret %tmpcast, i64 %c.coerce) + call void @_Z3barSt7complexIfE(%"struct.std::complex"* nonnull sret(%"struct.std::complex") %tmpcast, i64 %c.coerce) %2 = bitcast %"struct.std::complex"* %agg.result to i64* %3 = load i64, i64* %ref.tmp, align 8 store i64 %3, i64* %2, align 4 @@ -66,7 +66,7 @@ entry: ret void } -declare void @_Z3barSt7complexIfE(%"struct.std::complex"* sret, i64) +declare void @_Z3barSt7complexIfE(%"struct.std::complex"* sret(%"struct.std::complex"), i64) define void @test1(i32 *%ptr) { ; CHECK-LABEL: @test1( diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll index ab4e65edaab9e..a00ef9cbf244d 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll @@ -7,7 +7,7 @@ ; Right now the DSE in presence of fence is only done in end blocks (with no successors), ; but the same logic applies to other basic blocks as well. ; The store to %addr.i can be removed since it is a byval attribute -define void @test3(i32* byval %addr.i) { +define void @test3(i32* byval(i32) %addr.i) { ; CHECK-LABEL: @test3 ; CHECK-NOT: store ; CHECK: fence diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/out-of-bounds-stores.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/out-of-bounds-stores.ll new file mode 100644 index 0000000000000..3a16a62dddd4e --- /dev/null +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/out-of-bounds-stores.ll @@ -0,0 +1,71 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -dse -S %s | FileCheck %s + +declare void @use(i32) + +; Out-of-bounds stores can be considered killing any other stores to the same +; object in the same BB, because they are UB and guaranteed to execute. Note +; that cases in which the BB is exited through unwinding are handled separately +; by DSE and the unwinding call will be considered as clobber. +define i32 @test_out_of_bounds_store_local(i1 %c) { +; CHECK-LABEL: @test_out_of_bounds_store_local( +; CHECK-NEXT: [[D:%.*]] = alloca [1 x i32], align 4 +; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [1 x i32], [1 x i32]* [[D]], i64 0, i64 0 +; CHECK-NEXT: [[LV1:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 +; CHECK-NEXT: call void @use(i32 [[LV1]]) +; CHECK-NEXT: ret i32 0 +; + %d = alloca [1 x i32], align 4 + %arrayidx = getelementptr inbounds [1 x i32], [1 x i32]* %d, i64 0, i64 0 + store i32 10, i32* %arrayidx, align 4 + %arrayidx.1 = getelementptr inbounds [1 x i32], [1 x i32]* %d, i64 0, i64 1 + store i32 20, i32* %arrayidx.1, align 4 + %arrayidx1 = getelementptr inbounds [1 x i32], [1 x i32]* %d, i64 0, i64 0 + %lv1 = load i32, i32* %arrayidx1, align 4 + call void @use(i32 %lv1) + ret i32 0 +} + +; Make sure that out-of-bound stores are not considered killing other stores to +; the same underlying object, if they are in different basic blocks. The +; out-of-bounds store may not be executed. +; +; Test case from PR48279. FIXME. +define i32 @test_out_of_bounds_store_nonlocal(i1 %c) { +; CHECK-LABEL: @test_out_of_bounds_store_nonlocal( +; CHECK-NEXT: [[D:%.*]] = alloca [1 x i32], align 4 +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.body: +; CHECK-NEXT: br label [[FOR_INC:%.*]] +; CHECK: for.inc: +; CHECK-NEXT: br i1 [[C:%.*]], label [[FOR_BODY_1:%.*]], label [[FOR_END:%.*]] +; CHECK: for.body.1: +; CHECK-NEXT: ret i32 1 +; CHECK: for.end: +; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [1 x i32], [1 x i32]* [[D]], i64 0, i64 0 +; CHECK-NEXT: [[LV1:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4 +; CHECK-NEXT: call void @use(i32 [[LV1]]) +; CHECK-NEXT: ret i32 0 +; + %d = alloca [1 x i32], align 4 + br label %for.body + +for.body: ; preds = %for.cond + %arrayidx = getelementptr inbounds [1 x i32], [1 x i32]* %d, i64 0, i64 0 + store i32 10, i32* %arrayidx, align 4 + br label %for.inc + +for.inc: ; preds = %for.body + br i1 %c, label %for.body.1, label %for.end + +for.body.1: ; preds = %for.inc + %arrayidx.1 = getelementptr inbounds [1 x i32], [1 x i32]* %d, i64 0, i64 1 + store i32 20, i32* %arrayidx.1, align 4 + ret i32 1 + +for.end: ; preds = %for.inc + %arrayidx1 = getelementptr inbounds [1 x i32], [1 x i32]* %d, i64 0, i64 0 + %lv1 = load i32, i32* %arrayidx1, align 4 + call void @use(i32 %lv1) + ret i32 0 +} diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/simple.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/simple.ll index 5ee1a55a7369f..8fe4155d487c5 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/simple.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/simple.ll @@ -138,7 +138,7 @@ define i32 @test8() { ; Test for byval handling. %struct.x = type { i32, i32, i32, i32 } -define void @test9(%struct.x* byval %a) nounwind { +define void @test9(%struct.x* byval(%struct.x) %a) nounwind { ; CHECK-LABEL: @test9( ; CHECK-NEXT: ret void ; @@ -249,20 +249,20 @@ define void @test14(i32* %Q) { } ; The store here is not dead because the byval call reads it. -declare void @test19f({i32}* byval align 4 %P) +declare void @test19f({i32}* byval({i32}) align 4 %P) -define void @test19({i32} * nocapture byval align 4 %arg5) nounwind ssp { +define void @test19({i32}* nocapture byval({i32}) align 4 %arg5) nounwind ssp { ; CHECK-LABEL: @test19( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { i32 }, { i32 }* [[ARG5:%.*]], i32 0, i32 0 ; CHECK-NEXT: store i32 912, i32* [[TMP7]], align 4 -; CHECK-NEXT: call void @test19f({ i32 }* byval align 4 [[ARG5]]) +; CHECK-NEXT: call void @test19f({ i32 }* byval({ i32 }) align 4 [[ARG5]]) ; CHECK-NEXT: ret void ; bb: %tmp7 = getelementptr inbounds {i32}, {i32}* %arg5, i32 0, i32 0 store i32 912, i32* %tmp7 - call void @test19f({i32}* byval align 4 %arg5) + call void @test19f({i32}* byval({i32}) align 4 %arg5) ret void } diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/tail-byval.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/tail-byval.ll index ed2fbd434a75d..c11315a188bd4 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/tail-byval.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/tail-byval.ll @@ -8,16 +8,16 @@ target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" target triple = "i386-unknown-linux-gnu" -declare void @g(i32* byval %p) +declare void @g(i32* byval(i32) %p) -define void @f(i32* byval %x) { +define void @f(i32* byval(i32) %x) { entry: %p = alloca i32 %v = load i32, i32* %x store i32 %v, i32* %p - tail call void @g(i32* byval %p) + tail call void @g(i32* byval(i32) %p) ret void } -; CHECK-LABEL: define void @f(i32* byval %x) +; CHECK-LABEL: define void @f(i32* byval(i32) %x) ; CHECK: store i32 %v, i32* %p -; CHECK: tail call void @g(i32* byval %p) +; CHECK: tail call void @g(i32* byval(i32) %p) diff --git a/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/2011-09-06-EndOfFunction.ll b/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/2011-09-06-EndOfFunction.ll index 3f77349879170..635498336ff25 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/2011-09-06-EndOfFunction.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/2011-09-06-EndOfFunction.ll @@ -6,10 +6,10 @@ target triple = "x86_64-apple-darwin" %"class.std::auto_ptr" = type { i32* } ; CHECK-LABEL: @_Z3foov( -define void @_Z3foov(%"class.std::auto_ptr"* noalias nocapture sret %agg.result) uwtable ssp { +define void @_Z3foov(%"class.std::auto_ptr"* noalias nocapture sret(%"class.std::auto_ptr") %agg.result) uwtable ssp { _ZNSt8auto_ptrIiED1Ev.exit: %temp.lvalue = alloca %"class.std::auto_ptr", align 8 - call void @_Z3barv(%"class.std::auto_ptr"* sret %temp.lvalue) + call void @_Z3barv(%"class.std::auto_ptr"* sret(%"class.std::auto_ptr") %temp.lvalue) %_M_ptr.i.i = getelementptr inbounds %"class.std::auto_ptr", %"class.std::auto_ptr"* %temp.lvalue, i64 0, i32 0 %tmp.i.i = load i32*, i32** %_M_ptr.i.i, align 8 ; CHECK-NOT: store i32* null @@ -20,4 +20,4 @@ _ZNSt8auto_ptrIiED1Ev.exit: ret void } -declare void @_Z3barv(%"class.std::auto_ptr"* sret) +declare void @_Z3barv(%"class.std::auto_ptr"* sret(%"class.std::auto_ptr")) diff --git a/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/combined-partial-overwrites.ll b/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/combined-partial-overwrites.ll index 0e98e966ce1db..b0bbf7ef0186d 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/combined-partial-overwrites.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/combined-partial-overwrites.ll @@ -4,7 +4,7 @@ target triple = "powerpc64le-unknown-linux" %"struct.std::complex" = type { { float, float } } -define void @_Z4testSt7complexIfE(%"struct.std::complex"* noalias nocapture sret %agg.result, i64 %c.coerce) { +define void @_Z4testSt7complexIfE(%"struct.std::complex"* noalias nocapture sret(%"struct.std::complex") %agg.result, i64 %c.coerce) { entry: ; CHECK-LABEL: @_Z4testSt7complexIfE @@ -15,7 +15,7 @@ entry: %0 = bitcast i32 %c.sroa.0.0.extract.trunc to float %c.sroa.2.0.extract.trunc = trunc i64 %c.coerce to i32 %1 = bitcast i32 %c.sroa.2.0.extract.trunc to float - call void @_Z3barSt7complexIfE(%"struct.std::complex"* nonnull sret %tmpcast, i64 %c.coerce) + call void @_Z3barSt7complexIfE(%"struct.std::complex"* nonnull sret(%"struct.std::complex") %tmpcast, i64 %c.coerce) %2 = bitcast %"struct.std::complex"* %agg.result to i64* %3 = load i64, i64* %ref.tmp, align 8 store i64 %3, i64* %2, align 4 @@ -40,7 +40,7 @@ entry: ; CHECK: ret void } -declare void @_Z3barSt7complexIfE(%"struct.std::complex"* sret, i64) +declare void @_Z3barSt7complexIfE(%"struct.std::complex"* sret(%"struct.std::complex"), i64) define void @test1(i32 *%ptr) { entry: diff --git a/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/fence.ll b/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/fence.ll index ce2dcd3236b74..55b6b8a6d5abc 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/fence.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/fence.ll @@ -52,7 +52,7 @@ define void @test2(i32* %addr.i) { ; Right now the DSE in presence of fence is only done in end blocks (with no successors), ; but the same logic applies to other basic blocks as well. ; The store to %addr.i can be removed since it is a byval attribute -define void @test3(i32* byval %addr.i) { +define void @test3(i32* byval(i32) %addr.i) { ; CHECK-LABEL: @test3 ; CHECK-NOT: store ; CHECK: fence diff --git a/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll b/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll index 26674ec382baf..15caa6c898dcb 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll @@ -150,7 +150,7 @@ define i32 @test8() { ; Test for byval handling. %struct.x = type { i32, i32, i32, i32 } -define void @test9(%struct.x* byval %a) nounwind { +define void @test9(%struct.x* byval(%struct.x) %a) nounwind { ; CHECK-LABEL: @test9( ; CHECK-NEXT: ret void ; @@ -476,20 +476,20 @@ define void @test18_atomic(i8* %P, i8* %Q, i8* %R) nounwind ssp { ; The store here is not dead because the byval call reads it. -declare void @test19f({i32}* byval align 4 %P) +declare void @test19f({i32}* byval({i32}) align 4 %P) -define void @test19({i32} * nocapture byval align 4 %arg5) nounwind ssp { +define void @test19({i32} * nocapture byval({i32}) align 4 %arg5) nounwind ssp { ; CHECK-LABEL: @test19( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { i32 }, { i32 }* [[ARG5:%.*]], i32 0, i32 0 ; CHECK-NEXT: store i32 912, i32* [[TMP7]], align 4 -; CHECK-NEXT: call void @test19f({ i32 }* byval align 4 [[ARG5]]) +; CHECK-NEXT: call void @test19f({ i32 }* byval({ i32 }) align 4 [[ARG5]]) ; CHECK-NEXT: ret void ; bb: %tmp7 = getelementptr inbounds {i32}, {i32}* %arg5, i32 0, i32 0 store i32 912, i32* %tmp7 - call void @test19f({i32}* byval align 4 %arg5) + call void @test19f({i32}* byval({i32}) align 4 %arg5) ret void } diff --git a/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/tail-byval.ll b/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/tail-byval.ll index 0b4a76fee55cd..698f49a49b4bd 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/tail-byval.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/tail-byval.ll @@ -8,16 +8,16 @@ target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" target triple = "i386-unknown-linux-gnu" -declare void @g(i32* byval %p) +declare void @g(i32* byval(i32) %p) -define void @f(i32* byval %x) { +define void @f(i32* byval(i32) %x) { entry: %p = alloca i32 %v = load i32, i32* %x store i32 %v, i32* %p - tail call void @g(i32* byval %p) + tail call void @g(i32* byval(i32) %p) ret void } -; CHECK-LABEL: define void @f(i32* byval %x) +; CHECK-LABEL: define void @f(i32* byval(i32) %x) ; CHECK: store i32 %v, i32* %p -; CHECK: tail call void @g(i32* byval %p) +; CHECK: tail call void @g(i32* byval(i32) %p) diff --git a/llvm/test/Transforms/EarlyCSE/getmatchingvalue-crash.ll b/llvm/test/Transforms/EarlyCSE/getmatchingvalue-crash.ll index 5a8b244db83a1..60791e78ba3ae 100644 --- a/llvm/test/Transforms/EarlyCSE/getmatchingvalue-crash.ll +++ b/llvm/test/Transforms/EarlyCSE/getmatchingvalue-crash.ll @@ -54,7 +54,7 @@ b0: br label %b1 b1: ; preds = %b0 - invoke void @f5(%s.10* nonnull sret align 8 undef, i8* nonnull undef) + invoke void @f5(%s.10* nonnull sret(%s.10) align 8 undef, i8* nonnull undef) to label %b6 unwind label %b3 b2: ; preds = %b2 @@ -84,7 +84,7 @@ b7: ; preds = %b6 br label %b20 b8: ; preds = %b6 - invoke void @f2(%s.10* sret align 8 undef, %s.2* undef) + invoke void @f2(%s.10* sret(%s.10) align 8 undef, %s.2* undef) to label %b10 unwind label %b14 b9: ; No predecessors! @@ -100,7 +100,7 @@ b11: ; preds = %b10 unreachable b12: ; preds = %b10 - invoke void @f3(%s.10* nonnull sret align 8 undef, i8* %a1, i32 %a2) + invoke void @f3(%s.10* nonnull sret(%s.10) align 8 undef, i8* %a1, i32 %a2) to label %b13 unwind label %b15 b13: ; preds = %b12 diff --git a/llvm/test/Transforms/FunctionAttrs/convergent.ll b/llvm/test/Transforms/FunctionAttrs/convergent.ll index 8b764f502307f..277b1de3a4073 100644 --- a/llvm/test/Transforms/FunctionAttrs/convergent.ll +++ b/llvm/test/Transforms/FunctionAttrs/convergent.ll @@ -1,7 +1,4 @@ -; FIXME: convert CHECK-INDIRECT into CHECK (and remove -check-prefixes) as soon -; FIXME: as new-pass-manager's handling of indirect_non_convergent_call is fixed -; -; RUN: opt -function-attrs -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-INDIRECT +; RUN: opt -function-attrs -S < %s | FileCheck %s ; RUN: opt -passes=function-attrs -S < %s | FileCheck %s ; CHECK: Function Attrs @@ -54,8 +51,8 @@ define i32 @indirect_convergent_call(i32 ()* %f) convergent { ; "Function Attrs" comment in the output. ; ; CHECK: Function Attrs -; CHECK-INDIRECT-NOT: convergent -; CHECK-INDIRECT-NEXT: define i32 @indirect_non_convergent_call( +; CHECK-NOT: convergent +; CHECK-NEXT: define i32 @indirect_non_convergent_call( define i32 @indirect_non_convergent_call(i32 ()* %f) convergent norecurse { %a = call i32 %f() ret i32 %a diff --git a/llvm/test/Transforms/GVN/2009-03-10-PREOnVoid.ll b/llvm/test/Transforms/GVN/2009-03-10-PREOnVoid.ll index a0cf92989b818..0822ebb4a4e79 100644 --- a/llvm/test/Transforms/GVN/2009-03-10-PREOnVoid.ll +++ b/llvm/test/Transforms/GVN/2009-03-10-PREOnVoid.ll @@ -34,7 +34,7 @@ target triple = "i386-pc-linux-gnu" declare fastcc void @_ZNSt10_Select1stISt4pairIKPvS1_EEC1Ev() nounwind readnone -define fastcc void @_ZNSt8_Rb_treeIPvSt4pairIKS0_S0_ESt10_Select1stIS3_ESt4lessIS0_ESaIS3_EE16_M_insert_uniqueERKS3_(%"struct.std::pair > > >,bool>"* noalias nocapture sret %agg.result, %"struct.std::_Rb_tree > >,std::_Select1st > > >,std::less,std::allocator > > > >"* %this, %"struct.std::pair"* %__v) nounwind { +define fastcc void @_ZNSt8_Rb_treeIPvSt4pairIKS0_S0_ESt10_Select1stIS3_ESt4lessIS0_ESaIS3_EE16_M_insert_uniqueERKS3_(%"struct.std::pair > > >,bool>"* noalias nocapture sret(%"struct.std::pair > > >,bool>") %agg.result, %"struct.std::_Rb_tree > >,std::_Select1st > > >,std::less,std::allocator > > > >"* %this, %"struct.std::pair"* %__v) nounwind { entry: br i1 false, label %bb7, label %bb diff --git a/llvm/test/Transforms/GVN/pr17852.ll b/llvm/test/Transforms/GVN/pr17852.ll index 3d41a357f0052..25caab9ab0783 100644 --- a/llvm/test/Transforms/GVN/pr17852.ll +++ b/llvm/test/Transforms/GVN/pr17852.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -basic-aa -gvn target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" %struct.S0 = type { [2 x i8], [2 x i8], [4 x i8], [2 x i8], i32, i32, i32, i32 } -define void @fn1(%struct.S0* byval align 8 %p1) { +define void @fn1(%struct.S0* byval(%struct.S0) align 8 %p1) { br label %for.cond for.cond: ; preds = %1, %0 br label %for.end diff --git a/llvm/test/Transforms/GlobalOpt/2006-07-07-InlineAsmCrash.ll b/llvm/test/Transforms/GlobalOpt/2006-07-07-InlineAsmCrash.ll index a8531964fb110..d70a7534b5699 100644 --- a/llvm/test/Transforms/GlobalOpt/2006-07-07-InlineAsmCrash.ll +++ b/llvm/test/Transforms/GlobalOpt/2006-07-07-InlineAsmCrash.ll @@ -67,7 +67,7 @@ entry: ret void } -define void @_ZNSt3mapIPKc15FlagDescriptionIiE9StringCmpSaISt4pairIKS1_S3_EEE3endEv(%"struct.std::_Rb_tree_const_iterator, std::allocator > >"* sret %agg.result) { +define void @_ZNSt3mapIPKc15FlagDescriptionIiE9StringCmpSaISt4pairIKS1_S3_EEE3endEv(%"struct.std::_Rb_tree_const_iterator, std::allocator > >"* sret(%"struct.std::_Rb_tree_const_iterator, std::allocator > >") %agg.result) { entry: unreachable } diff --git a/llvm/test/Transforms/IndVarSimplify/interesting-invoke-use.ll b/llvm/test/Transforms/IndVarSimplify/interesting-invoke-use.ll index 131b02c3aaedf..38ee11cc68362 100644 --- a/llvm/test/Transforms/IndVarSimplify/interesting-invoke-use.ll +++ b/llvm/test/Transforms/IndVarSimplify/interesting-invoke-use.ll @@ -32,11 +32,11 @@ invcont127: ; preds = %bb123 br i1 %2, label %bb178, label %bb128 bb128: ; preds = %invcont127 - invoke void @system__img_int__image_integer(%struct.string___XUP* noalias sret null, i32 %i.0) + invoke void @system__img_int__image_integer(%struct.string___XUP* noalias sret(%struct.string___XUP) null, i32 %i.0) to label %invcont129 unwind label %lpad266 invcont129: ; preds = %bb128 - invoke void @system__string_ops__str_concat(%struct.string___XUP* noalias sret null, [0 x i8]* bitcast ([24 x i8]* @.str7 to [0 x i8]*), %struct.string___XUB* @C.17.316, [0 x i8]* null, %struct.string___XUB* null) + invoke void @system__string_ops__str_concat(%struct.string___XUP* noalias sret(%struct.string___XUP) null, [0 x i8]* bitcast ([24 x i8]* @.str7 to [0 x i8]*), %struct.string___XUB* @C.17.316, [0 x i8]* null, %struct.string___XUB* null) to label %invcont138 unwind label %lpad266 invcont138: ; preds = %invcont129 @@ -54,8 +54,8 @@ lpad266: ; preds = %invcont129, %bb128, %bb123 declare i32 @__gxx_personality_v0(...) -declare void @system__img_int__image_integer(%struct.string___XUP* noalias sret, i32) +declare void @system__img_int__image_integer(%struct.string___XUP* noalias sret(%struct.string___XUP), i32) -declare void @system__string_ops__str_concat(%struct.string___XUP* noalias sret, [0 x i8]*, %struct.string___XUB*, [0 x i8]*, %struct.string___XUB*) +declare void @system__string_ops__str_concat(%struct.string___XUP* noalias sret(%struct.string___XUP), [0 x i8]*, %struct.string___XUB*, [0 x i8]*, %struct.string___XUB*) declare i32 @report__ident_int(i32) diff --git a/llvm/test/Transforms/IndVarSimplify/loop_evaluate9.ll b/llvm/test/Transforms/IndVarSimplify/loop_evaluate9.ll index 96f2f30bd3bb5..824268b278752 100644 --- a/llvm/test/Transforms/IndVarSimplify/loop_evaluate9.ll +++ b/llvm/test/Transforms/IndVarSimplify/loop_evaluate9.ll @@ -72,13 +72,13 @@ return: ; preds = %cc70a02__complex_multiplication.170.exit ret void } -declare fastcc void @cc70a02__complex_integers__complex.164(%struct.cc70a02__complex_integers__complex_type* noalias nocapture sret, i8 signext, i8 signext) nounwind +declare fastcc void @cc70a02__complex_integers__complex.164(%struct.cc70a02__complex_integers__complex_type* noalias nocapture sret(%struct.cc70a02__complex_integers__complex_type), i8 signext, i8 signext) nounwind -declare fastcc void @cc70a02__complex_integers__Osubtract.149(%struct.cc70a02__complex_integers__complex_type* noalias sret, %struct.cc70a02__complex_integers__complex_type* byval align 4) +declare fastcc void @cc70a02__complex_integers__Osubtract.149(%struct.cc70a02__complex_integers__complex_type* noalias sret(%struct.cc70a02__complex_integers__complex_type), %struct.cc70a02__complex_integers__complex_type* byval(%struct.cc70a02__complex_integers__complex_type) align 4) -declare fastcc void @cc70a02__complex_integers__Oadd.153(%struct.cc70a02__complex_integers__complex_type* noalias sret, %struct.cc70a02__complex_integers__complex_type* byval align 4, %struct.cc70a02__complex_integers__complex_type* byval align 4) +declare fastcc void @cc70a02__complex_integers__Oadd.153(%struct.cc70a02__complex_integers__complex_type* noalias sret(%struct.cc70a02__complex_integers__complex_type), %struct.cc70a02__complex_integers__complex_type* byval(%struct.cc70a02__complex_integers__complex_type) align 4, %struct.cc70a02__complex_integers__complex_type* byval(%struct.cc70a02__complex_integers__complex_type) align 4) -declare fastcc void @cc70a02__complex_multiplication.170(%struct.cc70a02__complex_integers__complex_type* noalias sret, %struct.cc70a02__complex_integers__complex_type* byval align 4) +declare fastcc void @cc70a02__complex_multiplication.170(%struct.cc70a02__complex_integers__complex_type* noalias sret(%struct.cc70a02__complex_integers__complex_type), %struct.cc70a02__complex_integers__complex_type* byval(%struct.cc70a02__complex_integers__complex_type) align 4) declare void @__gnat_rcheck_12(i8*, i32) noreturn diff --git a/llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll b/llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll index 85946bbe59e64..ffe4db9435488 100644 --- a/llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll +++ b/llvm/test/Transforms/IndVarSimplify/predicated_ranges.ll @@ -835,15 +835,16 @@ define void @test_can_predicate_simple_unsigned_different_start(i32 %start, i32* ; CHECK-LABEL: @test_can_predicate_simple_unsigned_different_start( ; CHECK-NEXT: preheader: ; CHECK-NEXT: [[LEN:%.*]] = load i32, i32* [[P:%.*]], align 4 +; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[START:%.*]], -1 ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ] +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START]], [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ] ; CHECK-NEXT: [[ZERO_COND:%.*]] = icmp eq i32 [[IV]], 0 ; CHECK-NEXT: br i1 [[ZERO_COND]], label [[EXIT:%.*]], label [[RANGE_CHECK_BLOCK:%.*]] ; CHECK: range_check_block: ; CHECK-NEXT: [[IV_NEXT]] = sub i32 [[IV]], 1 -; CHECK-NEXT: [[RANGE_CHECK:%.*]] = icmp ult i32 [[IV_NEXT]], [[LEN]] -; CHECK-NEXT: br i1 [[RANGE_CHECK]], label [[BACKEDGE]], label [[FAIL:%.*]] +; CHECK-NEXT: [[RANGE_CHECK1:%.*]] = icmp ult i32 [[TMP0]], [[LEN]] +; CHECK-NEXT: br i1 [[RANGE_CHECK1]], label [[BACKEDGE]], label [[FAIL:%.*]] ; CHECK: backedge: ; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, i32* [[P]], i32 [[IV]] ; CHECK-NEXT: [[EL:%.*]] = load i32, i32* [[EL_PTR]], align 4 @@ -885,15 +886,16 @@ define void @test_can_predicate_simple_unsigned_inverted_different_start(i32 %st ; CHECK-LABEL: @test_can_predicate_simple_unsigned_inverted_different_start( ; CHECK-NEXT: preheader: ; CHECK-NEXT: [[LEN:%.*]] = load i32, i32* [[P:%.*]], align 4 +; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[START:%.*]], -1 ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ] +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START]], [[PREHEADER:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ] ; CHECK-NEXT: [[ZERO_COND:%.*]] = icmp eq i32 [[IV]], 0 ; CHECK-NEXT: br i1 [[ZERO_COND]], label [[EXIT:%.*]], label [[RANGE_CHECK_BLOCK:%.*]] ; CHECK: range_check_block: ; CHECK-NEXT: [[IV_NEXT]] = sub i32 [[IV]], 1 -; CHECK-NEXT: [[RANGE_CHECK:%.*]] = icmp uge i32 [[IV_NEXT]], [[LEN]] -; CHECK-NEXT: br i1 [[RANGE_CHECK]], label [[FAIL:%.*]], label [[BACKEDGE]] +; CHECK-NEXT: [[RANGE_CHECK1:%.*]] = icmp uge i32 [[TMP0]], [[LEN]] +; CHECK-NEXT: br i1 [[RANGE_CHECK1]], label [[FAIL:%.*]], label [[BACKEDGE]] ; CHECK: backedge: ; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, i32* [[P]], i32 [[IV]] ; CHECK-NEXT: [[EL:%.*]] = load i32, i32* [[EL_PTR]], align 4 diff --git a/llvm/test/Transforms/IndVarSimplify/rewrite-loop-exit-values-phi.ll b/llvm/test/Transforms/IndVarSimplify/rewrite-loop-exit-values-phi.ll new file mode 100644 index 0000000000000..21eb9892f9c95 --- /dev/null +++ b/llvm/test/Transforms/IndVarSimplify/rewrite-loop-exit-values-phi.ll @@ -0,0 +1,51 @@ +; RUN: opt -indvars -S %s -o - | FileCheck %s + +; When bailing out in rewriteLoopExitValues() you would be left with a PHI node +; that was not deleted, and the IndVar pass would return an incorrect modified +; status. This was caught by the expensive check introduced in D86589. + +; CHECK-LABEL: header: +; CHECK-NEXT: %idx = phi i64 [ %idx.next, %latch ], [ undef, %entry ] +; CHECK-NEXT: %cond = icmp sgt i64 %n, %idx +; CHECK-NEXT: br i1 %cond, label %end, label %inner.preheader + +; CHECK-LABEL: latch: +; CHECK-NEXT: %idx.next = add nsw i64 %idx, -1 +; CHECK-NEXT: br label %header + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@ptr = external global i64 + +define dso_local void @hoge() local_unnamed_addr { +entry: ; preds = %entry + %n = sdiv exact i64 undef, 40 + br label %header + +header: ; preds = %latch, %entry + %idx = phi i64 [ %idx.next, %latch ], [ undef, %entry ] + %cond = icmp sgt i64 %n, %idx + br i1 %cond, label %end, label %inner + +inner: ; preds = %inner, %header + %i = phi i64 [ %i.next, %inner ], [ 0, %header ] + %j = phi i64 [ %j.next, %inner ], [ %n, %header ] + %i.next = add nsw i64 %i, 1 + %j.next = add nsw i64 %j, 1 + store i64 undef, i64* @ptr + %cond1 = icmp slt i64 %j, %idx + br i1 %cond1, label %inner, label %inner_exit + +inner_exit: ; preds = %inner + %indvar = phi i64 [ %i.next, %inner ] + %indvar_use = add i64 %indvar, 1 + br label %latch + +latch: ; preds = %inner_exit + %idx.next = add nsw i64 %idx, -1 + br label %header + +end: ; preds = %header + ret void +} diff --git a/llvm/test/Transforms/IndVarSimplify/widen-loop-comp.ll b/llvm/test/Transforms/IndVarSimplify/widen-loop-comp.ll index cad5d3c66eca7..dd095c008772d 100644 --- a/llvm/test/Transforms/IndVarSimplify/widen-loop-comp.ll +++ b/llvm/test/Transforms/IndVarSimplify/widen-loop-comp.ll @@ -554,16 +554,13 @@ define i32 @test11(i32 %start, i32* %p, i32* %q) { ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[TMP0]], [[ENTRY:%.*]] ] -; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV]] to i32 -; CHECK-NEXT: [[IV_NEXT:%.*]] = add i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV]], -1 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[INDVARS_IV]], 0 ; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[BACKEDGE]] ; CHECK: backedge: -; CHECK-NEXT: [[INDEX:%.*]] = zext i32 [[IV_NEXT]] to i64 -; CHECK-NEXT: [[STORE_ADDR:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 [[INDEX]] +; CHECK-NEXT: [[STORE_ADDR:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 [[TMP1]] ; CHECK-NEXT: store i32 1, i32* [[STORE_ADDR]], align 4 -; CHECK-NEXT: [[LOAD_ADDR:%.*]] = getelementptr i32, i32* [[Q:%.*]], i64 [[INDEX]] -; CHECK-NEXT: [[STOP:%.*]] = load i32, i32* [[Q]], align 4 +; CHECK-NEXT: [[STOP:%.*]] = load i32, i32* [[Q:%.*]], align 4 ; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i32 [[STOP]], 0 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1 ; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[FAILURE:%.*]] @@ -700,10 +697,121 @@ define i32 @test14(i32 %start, i32* %p, i32* %q) { ; CHECK: loop: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[TMP0]], [[ENTRY:%.*]] ] ; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[INDVARS_IV]], 0 -; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV]] to i32 -; CHECK-NEXT: [[FOO:%.*]] = add i32 [[TMP1]], -1 +; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV]], -1 +; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[BACKEDGE]] +; CHECK: backedge: +; CHECK-NEXT: [[STORE_ADDR:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 [[TMP1]] +; CHECK-NEXT: store i32 1, i32* [[STORE_ADDR]], align 4 +; CHECK-NEXT: [[STOP:%.*]] = load i32, i32* [[Q:%.*]], align 4 +; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i32 [[STOP]], 0 +; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1 +; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[FAILURE:%.*]] +; CHECK: exit: +; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 -1 to i32 +; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK: failure: +; CHECK-NEXT: unreachable +; +entry: + br label %loop + +loop: + %iv = phi i32 [%start, %entry], [%iv.next.1, %backedge] + %cond = icmp eq i32 %iv, 0 + %foo = add i32 %iv, -1 + br i1 %cond, label %exit, label %backedge + +backedge: + %index = zext i32 %foo to i64 + %store.addr = getelementptr i32, i32* %p, i64 %index + store i32 1, i32* %store.addr + %load.addr = getelementptr i32, i32* %q, i64 %index + %stop = load i32, i32* %q + %loop.cond = icmp eq i32 %stop, 0 + %iv.next.1 = add i32 %iv, -1 + br i1 %loop.cond, label %loop, label %failure + +exit: + ret i32 %foo + +failure: + unreachable +} + +declare void @use(i32 %arg) + +define i32 @test15(i32 %start, i32* %p, i32* %q) { +; CHECK-LABEL: @test15( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[START:%.*]] to i64 +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[TMP0]], [[ENTRY:%.*]] ] +; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[INDVARS_IV]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV]], -1 ; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[BACKEDGE]] ; CHECK: backedge: +; CHECK-NEXT: [[STORE_ADDR:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 [[TMP1]] +; CHECK-NEXT: store i32 1, i32* [[STORE_ADDR]], align 4 +; CHECK-NEXT: [[STOP:%.*]] = load i32, i32* [[Q:%.*]], align 4 +; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i32 [[STOP]], 0 +; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1 +; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[FAILURE:%.*]] +; CHECK: exit: +; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 -1 to i32 +; CHECK-NEXT: call void @use(i32 [[TMP2]]) +; CHECK-NEXT: ret i32 [[TMP2]] +; CHECK: failure: +; CHECK-NEXT: [[FOO_LCSSA1_WIDE:%.*]] = phi i64 [ [[TMP1]], [[BACKEDGE]] ] +; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[FOO_LCSSA1_WIDE]] to i32 +; CHECK-NEXT: call void @use(i32 [[TMP3]]) +; CHECK-NEXT: unreachable +; +entry: + br label %loop + +loop: + %iv = phi i32 [%start, %entry], [%iv.next.1, %backedge] + %cond = icmp eq i32 %iv, 0 + %foo = add i32 %iv, -1 + br i1 %cond, label %exit, label %backedge + +backedge: + %index = zext i32 %foo to i64 + %store.addr = getelementptr i32, i32* %p, i64 %index + store i32 1, i32* %store.addr + %load.addr = getelementptr i32, i32* %q, i64 %index + %stop = load i32, i32* %q + %loop.cond = icmp eq i32 %stop, 0 + %iv.next.1 = add i32 %iv, -1 + br i1 %loop.cond, label %loop, label %failure + +exit: + call void @use(i32 %foo) + ret i32 %foo + +failure: + call void @use(i32 %foo) + unreachable +} + +; TODO: We can widen here despite the icmp user of %foo in guarded block. +define i32 @test16_unsigned_pos1(i32 %start, i32* %p, i32* %q, i32 %x) { +; CHECK-LABEL: @test16_unsigned_pos1( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[START:%.*]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[START]], -1 +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[TMP0]], [[ENTRY:%.*]] ] +; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[INDVARS_IV]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[INDVARS_IV]] to i32 +; CHECK-NEXT: [[FOO:%.*]] = add i32 [[TMP2]], -1 +; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[GUARDED:%.*]] +; CHECK: guarded: +; CHECK-NEXT: [[ICMP_USER3:%.*]] = icmp ult i32 [[TMP1]], [[X:%.*]] +; CHECK-NEXT: br i1 [[ICMP_USER3]], label [[BACKEDGE]], label [[SIDE_EXIT:%.*]] +; CHECK: backedge: ; CHECK-NEXT: [[INDEX:%.*]] = zext i32 [[FOO]] to i64 ; CHECK-NEXT: [[STORE_ADDR:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 [[INDEX]] ; CHECK-NEXT: store i32 1, i32* [[STORE_ADDR]], align 4 @@ -713,9 +821,14 @@ define i32 @test14(i32 %start, i32* %p, i32* %q) { ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1 ; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[FAILURE:%.*]] ; CHECK: exit: +; CHECK-NEXT: call void @use(i32 -1) ; CHECK-NEXT: ret i32 -1 ; CHECK: failure: +; CHECK-NEXT: [[FOO_LCSSA2:%.*]] = phi i32 [ [[FOO]], [[BACKEDGE]] ] +; CHECK-NEXT: call void @use(i32 [[FOO_LCSSA2]]) ; CHECK-NEXT: unreachable +; CHECK: side_exit: +; CHECK-NEXT: ret i32 0 ; entry: br label %loop @@ -724,7 +837,11 @@ loop: %iv = phi i32 [%start, %entry], [%iv.next.1, %backedge] %cond = icmp eq i32 %iv, 0 %foo = add i32 %iv, -1 - br i1 %cond, label %exit, label %backedge + br i1 %cond, label %exit, label %guarded + +guarded: + %icmp_user = icmp ult i32 %foo, %x + br i1 %icmp_user, label %backedge, label %side_exit backedge: %index = zext i32 %foo to i64 @@ -737,16 +854,89 @@ backedge: br i1 %loop.cond, label %loop, label %failure exit: + call void @use(i32 %foo) ret i32 %foo failure: + call void @use(i32 %foo) unreachable + +side_exit: + ret i32 0 } -declare void @use(i32 %arg) +; TODO: We can widen here despite the icmp user of %foo in guarded block. +define i32 @test16_unsigned_pos2(i32 %start, i32* %p, i32* %q, i32 %x) { +; CHECK-LABEL: @test16_unsigned_pos2( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[START:%.*]] to i64 +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[TMP0]], [[ENTRY:%.*]] ] +; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[INDVARS_IV]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV]] to i32 +; CHECK-NEXT: [[FOO:%.*]] = add i32 [[TMP1]], -1 +; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[GUARDED:%.*]] +; CHECK: guarded: +; CHECK-NEXT: [[ICMP_USER:%.*]] = icmp ne i32 [[FOO]], [[X:%.*]] +; CHECK-NEXT: br i1 [[ICMP_USER]], label [[BACKEDGE]], label [[SIDE_EXIT:%.*]] +; CHECK: backedge: +; CHECK-NEXT: [[INDEX:%.*]] = zext i32 [[FOO]] to i64 +; CHECK-NEXT: [[STORE_ADDR:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 [[INDEX]] +; CHECK-NEXT: store i32 1, i32* [[STORE_ADDR]], align 4 +; CHECK-NEXT: [[LOAD_ADDR:%.*]] = getelementptr i32, i32* [[Q:%.*]], i64 [[INDEX]] +; CHECK-NEXT: [[STOP:%.*]] = load i32, i32* [[Q]], align 4 +; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i32 [[STOP]], 0 +; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -1 +; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[FAILURE:%.*]] +; CHECK: exit: +; CHECK-NEXT: call void @use(i32 -1) +; CHECK-NEXT: ret i32 -1 +; CHECK: failure: +; CHECK-NEXT: [[FOO_LCSSA2:%.*]] = phi i32 [ [[FOO]], [[BACKEDGE]] ] +; CHECK-NEXT: call void @use(i32 [[FOO_LCSSA2]]) +; CHECK-NEXT: unreachable +; CHECK: side_exit: +; CHECK-NEXT: ret i32 0 +; +entry: + br label %loop -define i32 @test15(i32 %start, i32* %p, i32* %q) { -; CHECK-LABEL: @test15( +loop: + %iv = phi i32 [%start, %entry], [%iv.next.1, %backedge] + %cond = icmp eq i32 %iv, 0 + %foo = add i32 %iv, -1 + br i1 %cond, label %exit, label %guarded + +guarded: + %icmp_user = icmp ne i32 %foo, %x + br i1 %icmp_user, label %backedge, label %side_exit + +backedge: + %index = zext i32 %foo to i64 + %store.addr = getelementptr i32, i32* %p, i64 %index + store i32 1, i32* %store.addr + %load.addr = getelementptr i32, i32* %q, i64 %index + %stop = load i32, i32* %q + %loop.cond = icmp eq i32 %stop, 0 + %iv.next.1 = add i32 %iv, -1 + br i1 %loop.cond, label %loop, label %failure + +exit: + call void @use(i32 %foo) + ret i32 %foo + +failure: + call void @use(i32 %foo) + unreachable + +side_exit: + ret i32 0 +} + +; icmp slt user in guarded block prevents widening. +define i32 @test16_unsigned_neg(i32 %start, i32* %p, i32* %q, i32 %x) { +; CHECK-LABEL: @test16_unsigned_neg( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[START:%.*]] to i64 ; CHECK-NEXT: br label [[LOOP:%.*]] @@ -755,7 +945,10 @@ define i32 @test15(i32 %start, i32* %p, i32* %q) { ; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[INDVARS_IV]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV]] to i32 ; CHECK-NEXT: [[FOO:%.*]] = add i32 [[TMP1]], -1 -; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[BACKEDGE]] +; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[GUARDED:%.*]] +; CHECK: guarded: +; CHECK-NEXT: [[ICMP_USER:%.*]] = icmp slt i32 [[FOO]], [[X:%.*]] +; CHECK-NEXT: br i1 [[ICMP_USER]], label [[BACKEDGE]], label [[SIDE_EXIT:%.*]] ; CHECK: backedge: ; CHECK-NEXT: [[INDEX:%.*]] = zext i32 [[FOO]] to i64 ; CHECK-NEXT: [[STORE_ADDR:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 [[INDEX]] @@ -769,9 +962,11 @@ define i32 @test15(i32 %start, i32* %p, i32* %q) { ; CHECK-NEXT: call void @use(i32 -1) ; CHECK-NEXT: ret i32 -1 ; CHECK: failure: -; CHECK-NEXT: [[FOO_LCSSA1:%.*]] = phi i32 [ [[FOO]], [[BACKEDGE]] ] -; CHECK-NEXT: call void @use(i32 [[FOO_LCSSA1]]) +; CHECK-NEXT: [[FOO_LCSSA2:%.*]] = phi i32 [ [[FOO]], [[BACKEDGE]] ] +; CHECK-NEXT: call void @use(i32 [[FOO_LCSSA2]]) ; CHECK-NEXT: unreachable +; CHECK: side_exit: +; CHECK-NEXT: ret i32 0 ; entry: br label %loop @@ -780,7 +975,11 @@ loop: %iv = phi i32 [%start, %entry], [%iv.next.1, %backedge] %cond = icmp eq i32 %iv, 0 %foo = add i32 %iv, -1 - br i1 %cond, label %exit, label %backedge + br i1 %cond, label %exit, label %guarded + +guarded: + %icmp_user = icmp slt i32 %foo, %x + br i1 %icmp_user, label %backedge, label %side_exit backedge: %index = zext i32 %foo to i64 @@ -799,4 +998,209 @@ exit: failure: call void @use(i32 %foo) unreachable + +side_exit: + ret i32 0 +} + +; TODO: We can widen here despite the icmp user of %foo in guarded block. +define i32 @test16_signed_pos1(i32 %start, i32* %p, i32* %q, i32 %x) { +; CHECK-LABEL: @test16_signed_pos1( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT_1:%.*]], [[BACKEDGE:%.*]] ] +; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 0 +; CHECK-NEXT: [[FOO:%.*]] = add i32 [[IV]], -1 +; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[GUARDED:%.*]] +; CHECK: guarded: +; CHECK-NEXT: [[ICMP_USER:%.*]] = icmp slt i32 [[FOO]], [[X:%.*]] +; CHECK-NEXT: br i1 [[ICMP_USER]], label [[BACKEDGE]], label [[SIDE_EXIT:%.*]] +; CHECK: backedge: +; CHECK-NEXT: [[INDEX:%.*]] = sext i32 [[FOO]] to i64 +; CHECK-NEXT: [[STORE_ADDR:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 [[INDEX]] +; CHECK-NEXT: store i32 1, i32* [[STORE_ADDR]], align 4 +; CHECK-NEXT: [[LOAD_ADDR:%.*]] = getelementptr i32, i32* [[Q:%.*]], i64 [[INDEX]] +; CHECK-NEXT: [[STOP:%.*]] = load i32, i32* [[Q]], align 4 +; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i32 [[STOP]], 0 +; CHECK-NEXT: [[IV_NEXT_1]] = add i32 [[IV]], -1 +; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[FAILURE:%.*]] +; CHECK: exit: +; CHECK-NEXT: call void @use(i32 -1) +; CHECK-NEXT: ret i32 -1 +; CHECK: failure: +; CHECK-NEXT: [[FOO_LCSSA2:%.*]] = phi i32 [ [[FOO]], [[BACKEDGE]] ] +; CHECK-NEXT: call void @use(i32 [[FOO_LCSSA2]]) +; CHECK-NEXT: unreachable +; CHECK: side_exit: +; CHECK-NEXT: ret i32 0 +; +entry: + br label %loop + +loop: + %iv = phi i32 [%start, %entry], [%iv.next.1, %backedge] + %cond = icmp eq i32 %iv, 0 + %foo = add i32 %iv, -1 + br i1 %cond, label %exit, label %guarded + +guarded: + %icmp_user = icmp slt i32 %foo, %x + br i1 %icmp_user, label %backedge, label %side_exit + +backedge: + %index = sext i32 %foo to i64 + %store.addr = getelementptr i32, i32* %p, i64 %index + store i32 1, i32* %store.addr + %load.addr = getelementptr i32, i32* %q, i64 %index + %stop = load i32, i32* %q + %loop.cond = icmp eq i32 %stop, 0 + %iv.next.1 = add i32 %iv, -1 + br i1 %loop.cond, label %loop, label %failure + +exit: + call void @use(i32 %foo) + ret i32 %foo + +failure: + call void @use(i32 %foo) + unreachable + +side_exit: + ret i32 0 +} + +; TODO: We can widen here despite the icmp user of %foo in guarded block. +define i32 @test16_signed_pos2(i32 %start, i32* %p, i32* %q, i32 %x) { +; CHECK-LABEL: @test16_signed_pos2( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT_1:%.*]], [[BACKEDGE:%.*]] ] +; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 0 +; CHECK-NEXT: [[FOO:%.*]] = add i32 [[IV]], -1 +; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[GUARDED:%.*]] +; CHECK: guarded: +; CHECK-NEXT: [[ICMP_USER:%.*]] = icmp ne i32 [[FOO]], [[X:%.*]] +; CHECK-NEXT: br i1 [[ICMP_USER]], label [[BACKEDGE]], label [[SIDE_EXIT:%.*]] +; CHECK: backedge: +; CHECK-NEXT: [[INDEX:%.*]] = sext i32 [[FOO]] to i64 +; CHECK-NEXT: [[STORE_ADDR:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 [[INDEX]] +; CHECK-NEXT: store i32 1, i32* [[STORE_ADDR]], align 4 +; CHECK-NEXT: [[LOAD_ADDR:%.*]] = getelementptr i32, i32* [[Q:%.*]], i64 [[INDEX]] +; CHECK-NEXT: [[STOP:%.*]] = load i32, i32* [[Q]], align 4 +; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i32 [[STOP]], 0 +; CHECK-NEXT: [[IV_NEXT_1]] = add i32 [[IV]], -1 +; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[FAILURE:%.*]] +; CHECK: exit: +; CHECK-NEXT: call void @use(i32 -1) +; CHECK-NEXT: ret i32 -1 +; CHECK: failure: +; CHECK-NEXT: [[FOO_LCSSA2:%.*]] = phi i32 [ [[FOO]], [[BACKEDGE]] ] +; CHECK-NEXT: call void @use(i32 [[FOO_LCSSA2]]) +; CHECK-NEXT: unreachable +; CHECK: side_exit: +; CHECK-NEXT: ret i32 0 +; +entry: + br label %loop + +loop: + %iv = phi i32 [%start, %entry], [%iv.next.1, %backedge] + %cond = icmp eq i32 %iv, 0 + %foo = add i32 %iv, -1 + br i1 %cond, label %exit, label %guarded + +guarded: + %icmp_user = icmp ne i32 %foo, %x + br i1 %icmp_user, label %backedge, label %side_exit + +backedge: + %index = sext i32 %foo to i64 + %store.addr = getelementptr i32, i32* %p, i64 %index + store i32 1, i32* %store.addr + %load.addr = getelementptr i32, i32* %q, i64 %index + %stop = load i32, i32* %q + %loop.cond = icmp eq i32 %stop, 0 + %iv.next.1 = add i32 %iv, -1 + br i1 %loop.cond, label %loop, label %failure + +exit: + call void @use(i32 %foo) + ret i32 %foo + +failure: + call void @use(i32 %foo) + unreachable + +side_exit: + ret i32 0 +} + +; icmp ult user in guarded block prevents widening. +define i32 @test16_signed_neg(i32 %start, i32* %p, i32* %q, i32 %x) { +; CHECK-LABEL: @test16_signed_neg( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[START:%.*]], -1 +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START]], [[ENTRY:%.*]] ], [ [[IV_NEXT_1:%.*]], [[BACKEDGE:%.*]] ] +; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV]], 0 +; CHECK-NEXT: [[FOO:%.*]] = add i32 [[IV]], -1 +; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[GUARDED:%.*]] +; CHECK: guarded: +; CHECK-NEXT: [[ICMP_USER3:%.*]] = icmp ult i32 [[TMP0]], [[X:%.*]] +; CHECK-NEXT: br i1 [[ICMP_USER3]], label [[BACKEDGE]], label [[SIDE_EXIT:%.*]] +; CHECK: backedge: +; CHECK-NEXT: [[INDEX:%.*]] = sext i32 [[FOO]] to i64 +; CHECK-NEXT: [[STORE_ADDR:%.*]] = getelementptr i32, i32* [[P:%.*]], i64 [[INDEX]] +; CHECK-NEXT: store i32 1, i32* [[STORE_ADDR]], align 4 +; CHECK-NEXT: [[LOAD_ADDR:%.*]] = getelementptr i32, i32* [[Q:%.*]], i64 [[INDEX]] +; CHECK-NEXT: [[STOP:%.*]] = load i32, i32* [[Q]], align 4 +; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp eq i32 [[STOP]], 0 +; CHECK-NEXT: [[IV_NEXT_1]] = add i32 [[IV]], -1 +; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[FAILURE:%.*]] +; CHECK: exit: +; CHECK-NEXT: call void @use(i32 -1) +; CHECK-NEXT: ret i32 -1 +; CHECK: failure: +; CHECK-NEXT: [[FOO_LCSSA2:%.*]] = phi i32 [ [[FOO]], [[BACKEDGE]] ] +; CHECK-NEXT: call void @use(i32 [[FOO_LCSSA2]]) +; CHECK-NEXT: unreachable +; CHECK: side_exit: +; CHECK-NEXT: ret i32 0 +; +entry: + br label %loop + +loop: + %iv = phi i32 [%start, %entry], [%iv.next.1, %backedge] + %cond = icmp eq i32 %iv, 0 + %foo = add i32 %iv, -1 + br i1 %cond, label %exit, label %guarded + +guarded: + %icmp_user = icmp ult i32 %foo, %x + br i1 %icmp_user, label %backedge, label %side_exit + +backedge: + %index = sext i32 %foo to i64 + %store.addr = getelementptr i32, i32* %p, i64 %index + store i32 1, i32* %store.addr + %load.addr = getelementptr i32, i32* %q, i64 %index + %stop = load i32, i32* %q + %loop.cond = icmp eq i32 %stop, 0 + %iv.next.1 = add i32 %iv, -1 + br i1 %loop.cond, label %loop, label %failure + +exit: + call void @use(i32 %foo) + ret i32 %foo + +failure: + call void @use(i32 %foo) + unreachable + +side_exit: + ret i32 0 } diff --git a/llvm/test/Transforms/Inline/2009-05-07-CallUsingSelfCrash.ll b/llvm/test/Transforms/Inline/2009-05-07-CallUsingSelfCrash.ll index c8629ea22eb1a..0b6e1196141ef 100644 --- a/llvm/test/Transforms/Inline/2009-05-07-CallUsingSelfCrash.ll +++ b/llvm/test/Transforms/Inline/2009-05-07-CallUsingSelfCrash.ll @@ -4,7 +4,7 @@ %struct.S1 = type <{ i8, i8, i8, i8, %struct.S0 }> %struct.S2 = type <{ %struct.S1, i32 }> -define void @func_113(%struct.S1* noalias nocapture sret %agg.result, i8 signext %p_114) noreturn nounwind { +define void @func_113(%struct.S1* noalias nocapture sret(%struct.S1) %agg.result, i8 signext %p_114) noreturn nounwind { entry: unreachable diff --git a/llvm/test/Transforms/Inline/alloca-merge-align.ll b/llvm/test/Transforms/Inline/alloca-merge-align.ll index e3b819d561f91..9ff1280062b4b 100644 --- a/llvm/test/Transforms/Inline/alloca-merge-align.ll +++ b/llvm/test/Transforms/Inline/alloca-merge-align.ll @@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu" %struct.s = type { i32, i32 } -define void @foo(%struct.s* byval nocapture readonly %a) { +define void @foo(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [2 x i32], align 4 %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 @@ -20,7 +20,7 @@ entry: ret void } -define void @foo0(%struct.s* byval nocapture readonly %a) { +define void @foo0(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [2 x i32] %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 @@ -35,7 +35,7 @@ entry: ret void } -define void @foo1(%struct.s* byval nocapture readonly %a) { +define void @foo1(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [2 x i32], align 1 %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 @@ -52,7 +52,7 @@ entry: declare void @bar(i32*) #1 -define void @goo(%struct.s* byval nocapture readonly %a) { +define void @goo(%struct.s* byval(%struct.s) nocapture readonly %a) { entry: %x = alloca [2 x i32], align 32 %a1 = getelementptr inbounds %struct.s, %struct.s* %a, i64 0, i32 0 @@ -79,9 +79,9 @@ entry: store i64 0, i64* %a, align 8 %a1 = bitcast i64* %a to i32* store i32 1, i32* %a1, align 8 - call void @foo(%struct.s* byval %tmpcast) + call void @foo(%struct.s* byval(%struct.s) %tmpcast) store i32 2, i32* %a1, align 8 - call void @goo(%struct.s* byval %tmpcast) + call void @goo(%struct.s* byval(%struct.s) %tmpcast) ret i32 0 } @@ -97,8 +97,8 @@ entry: store i64 0, i64* %a, align 8 %a1 = bitcast i64* %a to i32* store i32 1, i32* %a1, align 8 - call void @foo0(%struct.s* byval %tmpcast) + call void @foo0(%struct.s* byval(%struct.s) %tmpcast) store i32 2, i32* %a1, align 8 - call void @goo(%struct.s* byval %tmpcast) + call void @goo(%struct.s* byval(%struct.s) %tmpcast) ret i32 0 } diff --git a/llvm/test/Transforms/Inline/byval-tail-call.ll b/llvm/test/Transforms/Inline/byval-tail-call.ll index 1a3cdc558e6b9..56a784a077c09 100644 --- a/llvm/test/Transforms/Inline/byval-tail-call.ll +++ b/llvm/test/Transforms/Inline/byval-tail-call.ll @@ -10,7 +10,7 @@ target triple = "i386-pc-linux-gnu" declare void @ext(i32*) -define void @bar(i32* byval %x) { +define void @bar(i32* byval(i32) %x) { call void @ext(i32* %x) ret void } @@ -19,11 +19,11 @@ define void @foo(i32* %x) { ; CHECK-LABEL: define void @foo( ; CHECK: llvm.lifetime.start ; CHECK: store i32 %2, i32* %x - call void @bar(i32* byval %x) + call void @bar(i32* byval(i32) %x) ret void } -define internal void @qux(i32* byval %x) { +define internal void @qux(i32* byval(i32) %x) { call void @ext(i32* %x) tail call void @ext(i32* null) ret void @@ -37,17 +37,17 @@ define void @frob(i32* %x) { ; CHECK: {{^ *}}call void @ext(i32* nonnull %[[POS]] ; CHECK: tail call void @ext(i32* null) ; CHECK: ret void - tail call void @qux(i32* byval %x) + tail call void @qux(i32* byval(i32) %x) ret void } ; A byval parameter passed into a function which is passed out as byval does ; not block the call from being marked as tail. -declare void @ext2(i32* byval) +declare void @ext2(i32* byval(i32)) -define void @bar2(i32* byval %x) { - call void @ext2(i32* byval %x) +define void @bar2(i32* byval(i32) %x) { + call void @ext2(i32* byval(i32) %x) ret void } @@ -56,9 +56,9 @@ define void @foobar(i32* %x) { ; CHECK: %[[POS:.*]] = alloca i32 ; CHECK: %[[VAL:.*]] = load i32, i32* %x ; CHECK: store i32 %[[VAL]], i32* %[[POS]] -; CHECK: tail call void @ext2(i32* nonnull byval %[[POS]] +; CHECK: tail call void @ext2(i32* nonnull byval(i32) %[[POS]] ; CHECK: ret void - tail call void @bar2(i32* byval %x) + tail call void @bar2(i32* byval(i32) %x) ret void } @@ -67,9 +67,9 @@ define void @barfoo() { ; CHECK: %[[POS:.*]] = alloca i32 ; CHECK: %[[VAL:.*]] = load i32, i32* %x ; CHECK: store i32 %[[VAL]], i32* %[[POS]] -; CHECK: tail call void @ext2(i32* nonnull byval %[[POS]] +; CHECK: tail call void @ext2(i32* nonnull byval(i32) %[[POS]] ; CHECK: ret void %x = alloca i32 - tail call void @bar2(i32* byval %x) + tail call void @bar2(i32* byval(i32) %x) ret void } diff --git a/llvm/test/Transforms/Inline/byval.ll b/llvm/test/Transforms/Inline/byval.ll index ea2bec2cee3fe..ea8aef323317a 100644 --- a/llvm/test/Transforms/Inline/byval.ll +++ b/llvm/test/Transforms/Inline/byval.ll @@ -13,7 +13,7 @@ target datalayout = "p:32:32-p1:64:64-p2:16:16-n16:32:64" %struct.ss = type { i32, i64 } @.str = internal constant [10 x i8] c"%d, %lld\0A\00" ; <[10 x i8]*> [#uses=1] -define internal void @f(%struct.ss* byval %b) nounwind { +define internal void @f(%struct.ss* byval(%struct.ss) %b) nounwind { entry: %tmp = getelementptr %struct.ss, %struct.ss* %b, i32 0, i32 0 ; [#uses=2] %tmp1 = load i32, i32* %tmp, align 4 ; [#uses=1] @@ -22,7 +22,7 @@ entry: ret void } -declare i32 @printf(i8*, ...) nounwind +declare i32 @printf(i8*, ...) nounwind define i32 @test1() nounwind { entry: @@ -31,7 +31,7 @@ entry: store i32 1, i32* %tmp1, align 8 %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 ; [#uses=1] store i64 2, i64* %tmp4, align 4 - call void @f( %struct.ss* byval %S ) nounwind + call void @f(%struct.ss* byval(%struct.ss) %S) nounwind ret i32 0 ; CHECK: @test1() ; CHECK: %S1 = alloca %struct.ss @@ -40,10 +40,10 @@ entry: ; CHECK: ret i32 0 } -; Inlining a byval struct should NOT cause an explicit copy +; Inlining a byval struct should NOT cause an explicit copy ; into an alloca if the function is readonly -define internal i32 @f2(%struct.ss* byval %b) nounwind readonly { +define internal i32 @f2(%struct.ss* byval(%struct.ss) %b) nounwind readonly { entry: %tmp = getelementptr %struct.ss, %struct.ss* %b, i32 0, i32 0 ; [#uses=2] %tmp1 = load i32, i32* %tmp, align 4 ; [#uses=1] @@ -58,7 +58,7 @@ entry: store i32 1, i32* %tmp1, align 8 %tmp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1 ; [#uses=1] store i64 2, i64* %tmp4, align 4 - %X = call i32 @f2( %struct.ss* byval %S ) nounwind + %X = call i32 @f2(%struct.ss* byval(%struct.ss) %S) nounwind ret i32 %X ; CHECK: @test2() ; CHECK: %S = alloca %struct.ss @@ -72,7 +72,7 @@ entry: ; PR8769 declare void @g3(%struct.ss* %p) -define internal void @f3(%struct.ss* byval align 64 %b) nounwind { +define internal void @f3(%struct.ss* byval(%struct.ss) align 64 %b) nounwind { call void @g3(%struct.ss* %b) ;; Could make alignment assumptions! ret void } @@ -80,7 +80,7 @@ define internal void @f3(%struct.ss* byval align 64 %b) nounwind { define void @test3() nounwind { entry: %S = alloca %struct.ss, align 1 ;; May not be aligned. - call void @f3( %struct.ss* byval align 64 %S) nounwind + call void @f3(%struct.ss* byval(%struct.ss) align 64 %S) nounwind ret void ; CHECK: @test3() ; CHECK: %S1 = alloca %struct.ss, align 64 @@ -91,11 +91,11 @@ entry: } -; Inlining a byval struct should NOT cause an explicit copy +; Inlining a byval struct should NOT cause an explicit copy ; into an alloca if the function is readonly, but should increase an alloca's ; alignment to satisfy an explicit alignment request. -define internal i32 @f4(%struct.ss* byval align 64 %b) nounwind readonly { +define internal i32 @f4(%struct.ss* byval(%struct.ss) align 64 %b) nounwind readonly { call void @g3(%struct.ss* %b) ret i32 4 } @@ -103,7 +103,7 @@ define internal i32 @f4(%struct.ss* byval align 64 %b) nounwind readonly { define i32 @test4() nounwind { entry: %S = alloca %struct.ss, align 2 ; <%struct.ss*> [#uses=4] - %X = call i32 @f4( %struct.ss* byval align 64 %S ) nounwind + %X = call i32 @f4(%struct.ss* byval(%struct.ss) align 64 %S) nounwind ret i32 %X ; CHECK: @test4() ; CHECK: %S = alloca %struct.ss, align 64 @@ -117,7 +117,7 @@ entry: @b = global %struct.S0 { i32 1 }, align 4 @a = common global i32 0, align 4 -define internal void @f5(%struct.S0* byval nocapture readonly align 4 %p) { +define internal void @f5(%struct.S0* byval(%struct.S0) nocapture readonly align 4 %p) { entry: store i32 0, i32* getelementptr inbounds (%struct.S0, %struct.S0* @b, i64 0, i32 0), align 4 %f2 = getelementptr inbounds %struct.S0, %struct.S0* %p, i64 0, i32 0 @@ -128,7 +128,7 @@ entry: define i32 @test5() { entry: - tail call void @f5(%struct.S0* byval align 4 @b) + tail call void @f5(%struct.S0* byval(%struct.S0) align 4 @b) %0 = load i32, i32* @a, align 4 ret i32 %0 ; CHECK: @test5() @@ -146,7 +146,7 @@ entry: @d = addrspace(1) global %struct.S1 { i32 1 }, align 4 @c = common addrspace(1) global i32 0, align 4 -define internal void @f5_as1(%struct.S1 addrspace(1)* byval nocapture readonly align 4 %p) { +define internal void @f5_as1(%struct.S1 addrspace(1)* byval(%struct.S1) nocapture readonly align 4 %p) { entry: store i32 0, i32 addrspace(1)* getelementptr inbounds (%struct.S1, %struct.S1 addrspace(1)* @d, i64 0, i32 0), align 4 %f2 = getelementptr inbounds %struct.S1, %struct.S1 addrspace(1)* %p, i64 0, i32 0 @@ -157,7 +157,7 @@ entry: define i32 @test5_as1() { entry: - tail call void @f5_as1(%struct.S1 addrspace(1)* byval align 4 @d) + tail call void @f5_as1(%struct.S1 addrspace(1)* byval(%struct.S1) align 4 @d) %0 = load i32, i32 addrspace(1)* @c, align 4 ret i32 %0 ; CHECK: @test5_as1() diff --git a/llvm/test/Transforms/Inline/byval_lifetime.ll b/llvm/test/Transforms/Inline/byval_lifetime.ll index 4517e448018ba..3d9b2c27660d1 100644 --- a/llvm/test/Transforms/Inline/byval_lifetime.ll +++ b/llvm/test/Transforms/Inline/byval_lifetime.ll @@ -8,7 +8,7 @@ @gFoo = global %struct.foo zeroinitializer, align 8 -define i32 @foo(%struct.foo* byval align 8 %f, i32 %a) { +define i32 @foo(%struct.foo* byval(%struct.foo) align 8 %f, i32 %a) { entry: %a1 = getelementptr inbounds %struct.foo, %struct.foo* %f, i32 0, i32 1 %arrayidx = getelementptr inbounds [16 x i32], [16 x i32]* %a1, i32 0, i32 %a @@ -21,6 +21,6 @@ define i32 @main(i32 %argc, i8** %argv) { ; CHECK: llvm.lifetime.start ; CHECK: memcpy entry: - %call = call i32 @foo(%struct.foo* byval align 8 @gFoo, i32 %argc) + %call = call i32 @foo(%struct.foo* byval(%struct.foo) align 8 @gFoo, i32 %argc) ret i32 %call } diff --git a/llvm/test/Transforms/Inline/crash2.ll b/llvm/test/Transforms/Inline/crash2.ll index e3a136010ee86..b3ca00308a4e1 100644 --- a/llvm/test/Transforms/Inline/crash2.ll +++ b/llvm/test/Transforms/Inline/crash2.ll @@ -1,4 +1,4 @@ -; RUN: opt -inline -sroa -max-cg-scc-iterations=1 -disable-output < %s +; RUN: opt -inline -sroa -max-devirt-iterations=1 -disable-output < %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.3" diff --git a/llvm/test/Transforms/Inline/devirtualize-3.ll b/llvm/test/Transforms/Inline/devirtualize-3.ll index 4165b2125dfc8..987463a037662 100644 --- a/llvm/test/Transforms/Inline/devirtualize-3.ll +++ b/llvm/test/Transforms/Inline/devirtualize-3.ll @@ -1,4 +1,5 @@ ; RUN: opt -basic-aa -S -O2 < %s | FileCheck %s +; RUN: opt -aa-pipeline=basic-aa -S -passes='default' < %s | FileCheck %s ; PR5009 ; CHECK: define i32 @main() diff --git a/llvm/test/Transforms/Inline/devirtualize-5.ll b/llvm/test/Transforms/Inline/devirtualize-5.ll new file mode 100644 index 0000000000000..ab507d1d58a1d --- /dev/null +++ b/llvm/test/Transforms/Inline/devirtualize-5.ll @@ -0,0 +1,22 @@ +; RUN: opt -abort-on-max-devirt-iterations-reached -passes='cgscc(devirt<1>(inline,instcombine))' -S < %s | FileCheck %s +; RUN: opt -abort-on-max-devirt-iterations-reached -passes='default' -S < %s | FileCheck %s + +define i32 @i() alwaysinline { + ret i32 45 +} + +; CHECK-LABEL: define i32 @main +; CHECK-NEXT: ret i32 45 + +define i32 @main() { + %a = alloca i32 ()* + store i32 ()* @i, i32 ()** %a + %r = call i32 @call(i32 ()** %a) + ret i32 %r +} + +define i32 @call(i32 ()** %a) alwaysinline { + %c = load i32 ()*, i32 ()** %a + %r = call i32 %c() + ret i32 %r +} diff --git a/llvm/test/Transforms/Inline/devirtualize-6.ll b/llvm/test/Transforms/Inline/devirtualize-6.ll new file mode 100644 index 0000000000000..fb0d021548b2a --- /dev/null +++ b/llvm/test/Transforms/Inline/devirtualize-6.ll @@ -0,0 +1,18 @@ +; Make sure we don't detect devirtualization on inlining a function with a direct call +; RUN: opt -abort-on-max-devirt-iterations-reached -passes='cgscc(devirt<0>(inline))' -S < %s | FileCheck %s + +define i32 @i() noinline { + ret i32 45 +} + +; CHECK-NOT: call i32 @call() + +define i32 @main() { + %r = call i32 @call() + ret i32 %r +} + +define i32 @call() alwaysinline { + %r = call i32 @i() + ret i32 %r +} diff --git a/llvm/test/Transforms/Inline/devirtualize.ll b/llvm/test/Transforms/Inline/devirtualize.ll index 561bb62ae6448..eaba1a8c19c51 100644 --- a/llvm/test/Transforms/Inline/devirtualize.ll +++ b/llvm/test/Transforms/Inline/devirtualize.ll @@ -1,4 +1,5 @@ ; RUN: opt -S -Os < %s | FileCheck %s +; RUN: opt -S -aa-pipeline=basic-aa -passes='default' < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.0.0" diff --git a/llvm/test/Transforms/Inline/gvn-inline-iteration.ll b/llvm/test/Transforms/Inline/gvn-inline-iteration.ll index e0f59af15cae0..ca35ecbc40223 100644 --- a/llvm/test/Transforms/Inline/gvn-inline-iteration.ll +++ b/llvm/test/Transforms/Inline/gvn-inline-iteration.ll @@ -1,4 +1,5 @@ -; RUN: opt -basic-aa -inline -gvn -S -max-cg-scc-iterations=1 < %s | FileCheck %s +; RUN: opt -basic-aa -inline -gvn -S -max-devirt-iterations=1 < %s -enable-new-pm=0 | FileCheck %s +; RUN: opt -aa-pipeline=basic-aa -passes='devirt<1>(inline,function(gvn))' -S < %s | FileCheck %s ; rdar://6295824 and PR6724 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" diff --git a/llvm/test/Transforms/Inline/inline-byval-bonus.ll b/llvm/test/Transforms/Inline/inline-byval-bonus.ll index 785de04c3f125..ec4610ed9a77f 100644 --- a/llvm/test/Transforms/Inline/inline-byval-bonus.ll +++ b/llvm/test/Transforms/Inline/inline-byval-bonus.ll @@ -19,7 +19,7 @@ define i32 @caller(%struct.sphere* %i) { %shadow_ray = alloca %struct.ray, align 8 call void @fix(%struct.ray* %shadow_ray) - %call = call i32 @ray_sphere(%struct.sphere* %i, %struct.ray* byval align 8 %shadow_ray, %struct.spoint* null) + %call = call i32 @ray_sphere(%struct.sphere* %i, %struct.ray* byval(%struct.ray) align 8 %shadow_ray, %struct.spoint* null) ret i32 %call ; CHECK-LABEL: @caller( @@ -29,7 +29,7 @@ define i32 @caller(%struct.sphere* %i) { declare void @fix(%struct.ray*) -define i32 @ray_sphere(%struct.sphere* nocapture %sph, %struct.ray* nocapture byval align 8 %ray, %struct.spoint* %sp) nounwind uwtable ssp { +define i32 @ray_sphere(%struct.sphere* nocapture %sph, %struct.ray* nocapture byval(%struct.ray) align 8 %ray, %struct.spoint* %sp) nounwind uwtable ssp { %1 = getelementptr inbounds %struct.ray, %struct.ray* %ray, i64 0, i32 1, i32 0 %2 = load double, double* %1, align 8 %3 = fmul double %2, %2 diff --git a/llvm/test/Transforms/Inline/inline-ptrtoint-different-sizes.ll b/llvm/test/Transforms/Inline/inline-ptrtoint-different-sizes.ll new file mode 100644 index 0000000000000..818792fb55a98 --- /dev/null +++ b/llvm/test/Transforms/Inline/inline-ptrtoint-different-sizes.ll @@ -0,0 +1,40 @@ +; RUN: opt < %s -inline -S | FileCheck %s + +; InlineCost used to have problems with the ptrtoint, leading to +; crashes when visiting the trunc in pr47969_help and the icmp in +; pr38500_help. + +target datalayout = "p:16:16" +target triple = "x86_64-unknown-linux-gnu" + +define void @pr47969_help(i16* %p) { + %cast = ptrtoint i16* %p to i32 + %sub = sub i32 %cast, %cast + %conv = trunc i32 %sub to i16 + ret void +} + +define void @pr47969(i16* %x) { + call void @pr47969_help(i16* %x) + ret void +} + +; CHECK-LABEL: @pr47969(i16* %x) +; CHECK-NOT: call +; CHECK: ret void + +define void @pr38500_help(i16* %p) { + %cast = ptrtoint i16* %p to i32 + %sub = sub i32 %cast, %cast + %cmp = icmp eq i32 %sub, 0 + ret void +} + +define void @pr38500(i16* %x) { + call void @pr38500_help(i16* %x) + ret void +} + +; CHECK-LABEL: @pr38500(i16* %x) +; CHECK-NOT: call +; CHECK: ret void diff --git a/llvm/test/Transforms/Inline/inline-tail.ll b/llvm/test/Transforms/Inline/inline-tail.ll index 10b486c5154ad..dbb2ae6058eb5 100644 --- a/llvm/test/Transforms/Inline/inline-tail.ll +++ b/llvm/test/Transforms/Inline/inline-tail.ll @@ -56,13 +56,13 @@ define void @test_musttail_basic_a(i32* %p) { ; CHECK: musttail call void @test_byval_c( ; CHECK-NEXT: ret void -declare void @test_byval_c(i32* byval %p) -define internal void @test_byval_b(i32* byval %p) { - musttail call void @test_byval_c(i32* byval %p) +declare void @test_byval_c(i32* byval(i32) %p) +define internal void @test_byval_b(i32* byval(i32) %p) { + musttail call void @test_byval_c(i32* byval(i32) %p) ret void } -define void @test_byval_a(i32* byval %p) { - musttail call void @test_byval_b(i32* byval %p) +define void @test_byval_a(i32* byval(i32) %p) { + musttail call void @test_byval_b(i32* byval(i32) %p) ret void } @@ -74,15 +74,15 @@ define void @test_byval_a(i32* byval %p) { ; CHECK-NEXT: ret void declare void @escape(i8* %buf) -declare void @test_dynalloca_c(i32* byval %p, i32 %n) -define internal void @test_dynalloca_b(i32* byval %p, i32 %n) alwaysinline { +declare void @test_dynalloca_c(i32* byval(i32) %p, i32 %n) +define internal void @test_dynalloca_b(i32* byval(i32) %p, i32 %n) alwaysinline { %buf = alloca i8, i32 %n ; dynamic alloca call void @escape(i8* %buf) ; escape it - musttail call void @test_dynalloca_c(i32* byval %p, i32 %n) + musttail call void @test_dynalloca_c(i32* byval(i32) %p, i32 %n) ret void } -define void @test_dynalloca_a(i32* byval %p, i32 %n) { - musttail call void @test_dynalloca_b(i32* byval %p, i32 %n) +define void @test_dynalloca_a(i32* byval(i32) %p, i32 %n) { + musttail call void @test_dynalloca_b(i32* byval(i32) %p, i32 %n) ret void } diff --git a/llvm/test/Transforms/Inline/inline-varargs.ll b/llvm/test/Transforms/Inline/inline-varargs.ll index d229ef39d594c..6fbcd123ddfeb 100644 --- a/llvm/test/Transforms/Inline/inline-varargs.ll +++ b/llvm/test/Transforms/Inline/inline-varargs.ll @@ -24,11 +24,11 @@ define signext i16 @test_callee_2(...) { } define void @test_caller_2(i8* %p, i8* %q, i16 %r) { - call signext i16 (...) @test_callee_2(i8* %p, i8* byval %q, i16 signext %r) + call signext i16 (...) @test_callee_2(i8* %p, i8* byval(i8) %q, i16 signext %r) ret void } ; CHECK-LABEL: define void @test_caller_2 -; CHECK: call signext i16 (...) @vararg_fn(i8* %p, i8* byval %q, i16 signext %r) [[FN_ATTRS:#[0-9]+]] +; CHECK: call signext i16 (...) @vararg_fn(i8* %p, i8* byval(i8) %q, i16 signext %r) [[FN_ATTRS:#[0-9]+]] define void @test_callee_3(i8* %p, ...) { call signext i16 (...) @vararg_fn() diff --git a/llvm/test/Transforms/Inline/prof-update-sample-alwaysinline.ll b/llvm/test/Transforms/Inline/prof-update-sample-alwaysinline.ll index 5bb5834faefd6..45d62c4c3c3cf 100644 --- a/llvm/test/Transforms/Inline/prof-update-sample-alwaysinline.ll +++ b/llvm/test/Transforms/Inline/prof-update-sample-alwaysinline.ll @@ -48,13 +48,13 @@ define void @caller() { !13 = !{i32 999000, i64 100, i32 1} !14 = !{i32 999999, i64 1, i32 2} !15 = !{!"function_entry_count", i64 1000} -!16 = !{!"branch_weights", i64 2000} -!17 = !{!"branch_weights", i64 400} +!16 = !{!"branch_weights", i32 2000} +!17 = !{!"branch_weights", i32 400} !18 = !{!"VP", i32 0, i64 140, i64 111, i64 80, i64 222, i64 40, i64 333, i64 20} attributes #0 = { alwaysinline } ; CHECK: ![[ENTRY_COUNT]] = !{!"function_entry_count", i64 600} -; CHECK: ![[COUNT_CALLEE1]] = !{!"branch_weights", i64 2000} -; CHECK: ![[COUNT_CALLEE]] = !{!"branch_weights", i64 1200} +; CHECK: ![[COUNT_CALLEE1]] = !{!"branch_weights", i32 2000} +; CHECK: ![[COUNT_CALLEE]] = !{!"branch_weights", i32 1200} ; CHECK: ![[COUNT_IND_CALLEE]] = !{!"VP", i32 0, i64 84, i64 111, i64 48, i64 222, i64 24, i64 333, i64 12} -; CHECK: ![[COUNT_CALLER]] = !{!"branch_weights", i64 800} +; CHECK: ![[COUNT_CALLER]] = !{!"branch_weights", i32 800} ; CHECK: ![[COUNT_IND_CALLER]] = !{!"VP", i32 0, i64 56, i64 111, i64 32, i64 222, i64 16, i64 333, i64 8} diff --git a/llvm/test/Transforms/Inline/prof-update-sample.ll b/llvm/test/Transforms/Inline/prof-update-sample.ll index ee475a6f3b2b7..76cba190c2645 100644 --- a/llvm/test/Transforms/Inline/prof-update-sample.ll +++ b/llvm/test/Transforms/Inline/prof-update-sample.ll @@ -49,12 +49,12 @@ define void @caller() { !13 = !{i32 999000, i64 100, i32 1} !14 = !{i32 999999, i64 1, i32 2} !15 = !{!"function_entry_count", i64 1000} -!16 = !{!"branch_weights", i64 2000} -!17 = !{!"branch_weights", i64 400} +!16 = !{!"branch_weights", i32 2000} +!17 = !{!"branch_weights", i32 400} !18 = !{!"VP", i32 0, i64 140, i64 111, i64 80, i64 222, i64 40, i64 333, i64 20} ; CHECK: ![[ENTRY_COUNT]] = !{!"function_entry_count", i64 600} -; CHECK: ![[COUNT_CALLEE1]] = !{!"branch_weights", i64 2000} -; CHECK: ![[COUNT_CALLEE]] = !{!"branch_weights", i64 1200} +; CHECK: ![[COUNT_CALLEE1]] = !{!"branch_weights", i32 2000} +; CHECK: ![[COUNT_CALLEE]] = !{!"branch_weights", i32 1200} ; CHECK: ![[COUNT_IND_CALLEE]] = !{!"VP", i32 0, i64 84, i64 111, i64 48, i64 222, i64 24, i64 333, i64 12} -; CHECK: ![[COUNT_CALLER]] = !{!"branch_weights", i64 800} +; CHECK: ![[COUNT_CALLER]] = !{!"branch_weights", i32 800} ; CHECK: ![[COUNT_IND_CALLER]] = !{!"VP", i32 0, i64 56, i64 111, i64 32, i64 222, i64 16, i64 333, i64 8} diff --git a/llvm/test/Transforms/InstCombine/2007-05-18-CastFoldBug.ll b/llvm/test/Transforms/InstCombine/2007-05-18-CastFoldBug.ll index eb0c364bfa25c..4cc14a4fd6df5 100644 --- a/llvm/test/Transforms/InstCombine/2007-05-18-CastFoldBug.ll +++ b/llvm/test/Transforms/InstCombine/2007-05-18-CastFoldBug.ll @@ -3,7 +3,7 @@ define void @blah(i16* %tmp10) { entry: - call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend_stret to void (i16*)*)( i16* sret %tmp10 ) + call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend_stret to void (i16*)*)(i16* sret(i16) %tmp10) ret void } diff --git a/llvm/test/Transforms/InstCombine/2008-04-22-ByValBitcast.ll b/llvm/test/Transforms/InstCombine/2008-04-22-ByValBitcast.ll index 1ea0998bf70e7..e4452c863aafd 100644 --- a/llvm/test/Transforms/InstCombine/2008-04-22-ByValBitcast.ll +++ b/llvm/test/Transforms/InstCombine/2008-04-22-ByValBitcast.ll @@ -8,7 +8,7 @@ target triple = "i386-apple-darwin9" define void @foo(i8* %context) nounwind { entry: %tmp1 = bitcast i8* %context to %struct.NSRect* ; <%struct.NSRect*> [#uses=1] - call void (i32, ...) @bar( i32 3, %struct.NSRect* byval align 4 %tmp1 ) nounwind + call void (i32, ...) @bar( i32 3, %struct.NSRect* byval(%struct.NSRect) align 4 %tmp1 ) nounwind ret void } diff --git a/llvm/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll b/llvm/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll index f6d0c4eb95c62..3c1c04a3f8fd4 100644 --- a/llvm/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll +++ b/llvm/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll @@ -18,7 +18,7 @@ define i32 @bar(i64 %key_token2) nounwind { ; CHECK-NEXT: store i32 0, i32* [[TMP1]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast %struct.Key* [[IOSPEC]] to i64* ; CHECK-NEXT: store i64 [[KEY_TOKEN2:%.*]], i64* [[TMP2]], align 8 -; CHECK-NEXT: [[TMP3:%.*]] = call i32 (...) @foo(%struct.Key* nonnull byval align 4 [[IOSPEC]], i32* nonnull [[RET]]) [[ATTR0:#.*]] +; CHECK-NEXT: [[TMP3:%.*]] = call i32 (...) @foo(%struct.Key* nonnull byval(%struct.Key) align 4 [[IOSPEC]], i32* nonnull [[RET]]) [[ATTR0:#.*]] ; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[RET]], align 4 ; CHECK-NEXT: ret i32 [[TMP4]] ; @@ -34,7 +34,7 @@ entry: %3 = getelementptr %struct.Key, %struct.Key* %iospec, i32 0, i32 0 ; <{ i32, i32 }*> [#uses=1] %4 = bitcast { i32, i32 }* %3 to i64* ; [#uses=1] store i64 %key_token2, i64* %4, align 4 - %5 = call i32 (...) @foo(%struct.Key* byval align 4 %iospec, i32* %ret) nounwind ; [#uses=0] + %5 = call i32 (...) @foo(%struct.Key* byval(%struct.Key) align 4 %iospec, i32* %ret) nounwind ; [#uses=0] %6 = load i32, i32* %ret, align 4 ; [#uses=1] ret i32 %6 } diff --git a/llvm/test/Transforms/InstCombine/align-addr.ll b/llvm/test/Transforms/InstCombine/align-addr.ll index d6dc5e91da45e..68cd13a2c537d 100644 --- a/llvm/test/Transforms/InstCombine/align-addr.ll +++ b/llvm/test/Transforms/InstCombine/align-addr.ll @@ -110,7 +110,7 @@ declare void @use(i8*) %struct.s = type { i32, i32, i32, i32 } -define void @test3(%struct.s* sret %a4) { +define void @test3(%struct.s* sret(%struct.s) %a4) { ; Check that the alignment is bumped up the alignment of the sret type. ; CHECK-LABEL: @test3( ; CHECK-NEXT: [[A4_CAST:%.*]] = bitcast %struct.s* [[A4:%.*]] to i8* diff --git a/llvm/test/Transforms/InstCombine/call-cast-attrs.ll b/llvm/test/Transforms/InstCombine/call-cast-attrs.ll index ddaf90c3e74fd..87ac3dc763131 100644 --- a/llvm/test/Transforms/InstCombine/call-cast-attrs.ll +++ b/llvm/test/Transforms/InstCombine/call-cast-attrs.ll @@ -18,12 +18,12 @@ define void @d(i32 %x, ...) { define void @g(i32* %y) { call i32 bitcast (i32 (i32*)* @b to i32 (i32)*)(i32 zeroext 0) call void bitcast (void (...)* @c to void (i32*)*)(i32* %y) - call void bitcast (void (...)* @c to void (i32*)*)(i32* sret %y) - call void bitcast (void (i32, ...)* @d to void (i32, i32*)*)(i32 0, i32* sret %y) + call void bitcast (void (...)* @c to void (i32*)*)(i32* sret(i32) %y) + call void bitcast (void (i32, ...)* @d to void (i32, i32*)*)(i32 0, i32* sret(i32) %y) ret void } ; CHECK-LABEL: define void @g(i32* %y) ; CHECK: call i32 bitcast (i32 (i32*)* @b to i32 (i32)*)(i32 zeroext 0) ; CHECK: call void (...) @c(i32* %y) -; CHECK: call void bitcast (void (...)* @c to void (i32*)*)(i32* sret %y) -; CHECK: call void bitcast (void (i32, ...)* @d to void (i32, i32*)*)(i32 0, i32* sret %y) +; CHECK: call void bitcast (void (...)* @c to void (i32*)*)(i32* sret(i32) %y) +; CHECK: call void bitcast (void (i32, ...)* @d to void (i32, i32*)*)(i32 0, i32* sret(i32) %y) diff --git a/llvm/test/Transforms/InstCombine/call-cast-target.ll b/llvm/test/Transforms/InstCombine/call-cast-target.ll index 881e80762ea6b..309cac32414c6 100644 --- a/llvm/test/Transforms/InstCombine/call-cast-target.ll +++ b/llvm/test/Transforms/InstCombine/call-cast-target.ll @@ -73,7 +73,7 @@ entry: ret i32 %call } -declare i1 @fn5({ i32, i32 }* byval align 4 %r) +declare i1 @fn5({ i32, i32 }* byval({ i32, i32 }) align 4 %r) define i1 @test5() { ; CHECK-LABEL: @test5 diff --git a/llvm/test/Transforms/InstCombine/crash.ll b/llvm/test/Transforms/InstCombine/crash.ll index fbb9675c0f112..ab6ca2671432c 100644 --- a/llvm/test/Transforms/InstCombine/crash.ll +++ b/llvm/test/Transforms/InstCombine/crash.ll @@ -294,7 +294,7 @@ declare i32 @test14f(i8* (i8*)*) nounwind define void @test14() nounwind readnone { entry: %tmp = bitcast i32 (i8* (i8*)*)* @test14f to i32 (i32*)* - %call10 = call i32 %tmp(i32* byval undef) + %call10 = call i32 %tmp(i32* byval(i32) undef) ret void } diff --git a/llvm/test/Transforms/InstCombine/insert-val-extract-elem.ll b/llvm/test/Transforms/InstCombine/insert-val-extract-elem.ll index db7b4031f3727..9b708de88a900 100644 --- a/llvm/test/Transforms/InstCombine/insert-val-extract-elem.ll +++ b/llvm/test/Transforms/InstCombine/insert-val-extract-elem.ll @@ -4,7 +4,7 @@ ; CHECK-NOT: insertvalue ; CHECK-NOT: extractelement ; CHECK: store <2 x double> -define void @julia_2xdouble([2 x double]* sret, <2 x double>*) { +define void @julia_2xdouble([2 x double]* sret([2 x double]), <2 x double>*) { top: %x = load <2 x double>, <2 x double>* %1 %x0 = extractelement <2 x double> %x, i32 0 @@ -20,7 +20,7 @@ top: ; CHECK-NOT: insertvalue ; CHECK-NOT: extractelement ; CHECK: store <2 x i64> -define void @julia_2xi64([2 x i64]* sret, <2 x i64>*) { +define void @julia_2xi64([2 x i64]* sret([2 x i64]), <2 x i64>*) { top: %x = load <2 x i64>, <2 x i64>* %1 %x0 = extractelement <2 x i64> %x, i32 1 @@ -37,7 +37,7 @@ top: ; CHECK-NOT: insertvalue ; CHECK-NOT: extractelement ; CHECK: store <4 x float> -define void @julia_4xfloat([4 x float]* sret, <4 x float>*) { +define void @julia_4xfloat([4 x float]* sret([4 x float]), <4 x float>*) { top: %x = load <4 x float>, <4 x float>* %1 %x0 = extractelement <4 x float> %x, i32 0 @@ -58,7 +58,7 @@ top: ; CHECK-NOT: insertvalue ; CHECK-NOT: extractelement ; CHECK: store <4 x float> -define void @julia_pseudovec(%pseudovec* sret, <4 x float>*) { +define void @julia_pseudovec(%pseudovec* sret(%pseudovec), <4 x float>*) { top: %x = load <4 x float>, <4 x float>* %1 %x0 = extractelement <4 x float> %x, i32 0 diff --git a/llvm/test/Transforms/InstCombine/memcpy-from-global.ll b/llvm/test/Transforms/InstCombine/memcpy-from-global.ll index 738cb9ba5a368..7757f002713f6 100644 --- a/llvm/test/Transforms/InstCombine/memcpy-from-global.ll +++ b/llvm/test/Transforms/InstCombine/memcpy-from-global.ll @@ -178,32 +178,32 @@ define void @test3_addrspacecast() { define void @test4() { ; CHECK-LABEL: @test4( -; CHECK-NEXT: call void @baz(i8* byval getelementptr inbounds (%T, %T* @G, i64 0, i32 0)) +; CHECK-NEXT: call void @baz(i8* byval(i8) getelementptr inbounds (%T, %T* @G, i64 0, i32 0)) ; CHECK-NEXT: ret void ; %A = alloca %T %a = bitcast %T* %A to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %a, i8* align 4 bitcast (%T* @G to i8*), i64 124, i1 false) - call void @baz(i8* byval %a) + call void @baz(i8* byval(i8) %a) ret void } declare void @llvm.lifetime.start.p0i8(i64, i8*) define void @test5() { ; CHECK-LABEL: @test5( -; CHECK-NEXT: call void @baz(i8* byval getelementptr inbounds (%T, %T* @G, i64 0, i32 0)) +; CHECK-NEXT: call void @baz(i8* byval(i8) getelementptr inbounds (%T, %T* @G, i64 0, i32 0)) ; CHECK-NEXT: ret void ; %A = alloca %T %a = bitcast %T* %A to i8* call void @llvm.lifetime.start.p0i8(i64 -1, i8* %a) call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %a, i8* align 4 bitcast (%T* @G to i8*), i64 124, i1 false) - call void @baz(i8* byval %a) + call void @baz(i8* byval(i8) %a) ret void } -declare void @baz(i8* byval) +declare void @baz(i8* byval(i8)) define void @test6() { diff --git a/llvm/test/Transforms/InstCombine/object-size-opaque.ll b/llvm/test/Transforms/InstCombine/object-size-opaque.ll index 741586fead1f3..123c6160a3ffa 100644 --- a/llvm/test/Transforms/InstCombine/object-size-opaque.ll +++ b/llvm/test/Transforms/InstCombine/object-size-opaque.ll @@ -2,7 +2,7 @@ %opaque = type opaque ; CHECK: call i64 @llvm.objectsize.i64 -define void @foo(%opaque* sret %in, i64* %sizeptr) { +define void @foo(%opaque* sret(%opaque) %in, i64* %sizeptr) { %ptr = bitcast %opaque* %in to i8* %size = call i64 @llvm.objectsize.i64(i8* %ptr, i1 0, i1 0, i1 0) store i64 %size, i64* %sizeptr diff --git a/llvm/test/Transforms/InstCombine/sub-gep.ll b/llvm/test/Transforms/InstCombine/sub-gep.ll index 9868ed1cdf575..bc18608da7a57 100644 --- a/llvm/test/Transforms/InstCombine/sub-gep.ll +++ b/llvm/test/Transforms/InstCombine/sub-gep.ll @@ -123,12 +123,38 @@ define i64 @test_inbounds2_nuw_swapped([0 x i32]* %base, i64 %idx) { ret i64 %d } -; The sub and shl here could be nuw, but this is harder to handle. +define i64 @test_inbounds_two_gep([0 x i32]* %base, i64 %idx, i64 %idx2) { +; CHECK-LABEL: @test_inbounds_two_gep( +; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i64 [[IDX2:%.*]], [[IDX:%.*]] +; CHECK-NEXT: [[GEPDIFF:%.*]] = shl nsw i64 [[TMP1]], 2 +; CHECK-NEXT: ret i64 [[GEPDIFF]] +; + %p1 = getelementptr inbounds [0 x i32], [0 x i32]* %base, i64 0, i64 %idx + %p2 = getelementptr inbounds [0 x i32], [0 x i32]* %base, i64 0, i64 %idx2 + %i1 = ptrtoint i32* %p1 to i64 + %i2 = ptrtoint i32* %p2 to i64 + %d = sub i64 %i2, %i1 + ret i64 %d +} + +define i64 @test_inbounds_nsw_two_gep([0 x i32]* %base, i64 %idx, i64 %idx2) { +; CHECK-LABEL: @test_inbounds_nsw_two_gep( +; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i64 [[IDX2:%.*]], [[IDX:%.*]] +; CHECK-NEXT: [[GEPDIFF:%.*]] = shl nsw i64 [[TMP1]], 2 +; CHECK-NEXT: ret i64 [[GEPDIFF]] +; + %p1 = getelementptr inbounds [0 x i32], [0 x i32]* %base, i64 0, i64 %idx + %p2 = getelementptr inbounds [0 x i32], [0 x i32]* %base, i64 0, i64 %idx2 + %i1 = ptrtoint i32* %p1 to i64 + %i2 = ptrtoint i32* %p2 to i64 + %d = sub nsw i64 %i2, %i1 + ret i64 %d +} + define i64 @test_inbounds_nuw_two_gep([0 x i32]* %base, i64 %idx, i64 %idx2) { ; CHECK-LABEL: @test_inbounds_nuw_two_gep( -; CHECK-NEXT: [[P2_IDX:%.*]] = shl nsw i64 [[IDX2:%.*]], 2 -; CHECK-NEXT: [[P1_IDX_NEG:%.*]] = mul i64 [[IDX:%.*]], -4 -; CHECK-NEXT: [[GEPDIFF:%.*]] = add i64 [[P1_IDX_NEG]], [[P2_IDX]] +; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i64 [[IDX2:%.*]], [[IDX:%.*]] +; CHECK-NEXT: [[GEPDIFF:%.*]] = shl nsw i64 [[TMP1]], 2 ; CHECK-NEXT: ret i64 [[GEPDIFF]] ; %p1 = getelementptr inbounds [0 x i32], [0 x i32]* %base, i64 0, i64 %idx @@ -245,7 +271,7 @@ define i64 @test24b(i8* %P, i64 %A){ define i64 @test25(i8* %P, i64 %A){ ; CHECK-LABEL: @test25( ; CHECK-NEXT: [[B_IDX:%.*]] = shl nsw i64 [[A:%.*]], 1 -; CHECK-NEXT: [[GEPDIFF:%.*]] = add i64 [[B_IDX]], -84 +; CHECK-NEXT: [[GEPDIFF:%.*]] = add nsw i64 [[B_IDX]], -84 ; CHECK-NEXT: ret i64 [[GEPDIFF]] ; %B = getelementptr inbounds [42 x i16], [42 x i16]* @Arr, i64 0, i64 %A @@ -260,7 +286,7 @@ define i16 @test25_as1(i8 addrspace(1)* %P, i64 %A) { ; CHECK-LABEL: @test25_as1( ; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A:%.*]] to i16 ; CHECK-NEXT: [[B_IDX:%.*]] = shl nsw i16 [[TMP1]], 1 -; CHECK-NEXT: [[GEPDIFF:%.*]] = add i16 [[B_IDX]], -84 +; CHECK-NEXT: [[GEPDIFF:%.*]] = add nsw i16 [[B_IDX]], -84 ; CHECK-NEXT: ret i16 [[GEPDIFF]] ; %B = getelementptr inbounds [42 x i16], [42 x i16] addrspace(1)* @Arr_as1, i64 0, i64 %A @@ -272,7 +298,7 @@ define i16 @test25_as1(i8 addrspace(1)* %P, i64 %A) { define i64 @test30(i8* %foo, i64 %i, i64 %j) { ; CHECK-LABEL: @test30( ; CHECK-NEXT: [[GEP1_IDX:%.*]] = shl nsw i64 [[I:%.*]], 2 -; CHECK-NEXT: [[GEPDIFF:%.*]] = sub i64 [[GEP1_IDX]], [[J:%.*]] +; CHECK-NEXT: [[GEPDIFF:%.*]] = sub nsw i64 [[GEP1_IDX]], [[J:%.*]] ; CHECK-NEXT: ret i64 [[GEPDIFF]] ; %bit = bitcast i8* %foo to i32* @@ -287,7 +313,7 @@ define i64 @test30(i8* %foo, i64 %i, i64 %j) { define i16 @test30_as1(i8 addrspace(1)* %foo, i16 %i, i16 %j) { ; CHECK-LABEL: @test30_as1( ; CHECK-NEXT: [[GEP1_IDX:%.*]] = shl nsw i16 [[I:%.*]], 2 -; CHECK-NEXT: [[GEPDIFF:%.*]] = sub i16 [[GEP1_IDX]], [[J:%.*]] +; CHECK-NEXT: [[GEPDIFF:%.*]] = sub nsw i16 [[GEP1_IDX]], [[J:%.*]] ; CHECK-NEXT: ret i16 [[GEPDIFF]] ; %bit = bitcast i8 addrspace(1)* %foo to i32 addrspace(1)* @@ -299,9 +325,11 @@ define i16 @test30_as1(i8 addrspace(1)* %foo, i16 %i, i16 %j) { ret i16 %sub } +; Inbounds translates to 'nsw' on sub + define i64 @gep_diff_both_inbounds(i8* %foo, i64 %i, i64 %j) { ; CHECK-LABEL: @gep_diff_both_inbounds( -; CHECK-NEXT: [[GEPDIFF:%.*]] = sub i64 [[I:%.*]], [[J:%.*]] +; CHECK-NEXT: [[GEPDIFF:%.*]] = sub nsw i64 [[I:%.*]], [[J:%.*]] ; CHECK-NEXT: ret i64 [[GEPDIFF]] ; %gep1 = getelementptr inbounds i8, i8* %foo, i64 %i @@ -312,6 +340,8 @@ define i64 @gep_diff_both_inbounds(i8* %foo, i64 %i, i64 %j) { ret i64 %sub } +; Negative test for 'nsw' - both geps must be inbounds + define i64 @gep_diff_first_inbounds(i8* %foo, i64 %i, i64 %j) { ; CHECK-LABEL: @gep_diff_first_inbounds( ; CHECK-NEXT: [[GEPDIFF:%.*]] = sub i64 [[I:%.*]], [[J:%.*]] @@ -325,6 +355,8 @@ define i64 @gep_diff_first_inbounds(i8* %foo, i64 %i, i64 %j) { ret i64 %sub } +; Negative test for 'nsw' - both geps must be inbounds + define i64 @gep_diff_second_inbounds(i8* %foo, i64 %i, i64 %j) { ; CHECK-LABEL: @gep_diff_second_inbounds( ; CHECK-NEXT: [[GEPDIFF:%.*]] = sub i64 [[I:%.*]], [[J:%.*]] diff --git a/llvm/test/Transforms/InstCombine/sub.ll b/llvm/test/Transforms/InstCombine/sub.ll index d9c67d0568f74..066085fc25351 100644 --- a/llvm/test/Transforms/InstCombine/sub.ll +++ b/llvm/test/Transforms/InstCombine/sub.ll @@ -1077,7 +1077,7 @@ define i64 @test58([100 x [100 x i8]]* %foo, i64 %i, i64 %j) { ; CHECK-LABEL: @test58( ; CHECK-NEXT: [[GEP1_OFFS:%.*]] = add nsw i64 [[I:%.*]], 4200 ; CHECK-NEXT: [[GEP2_OFFS:%.*]] = add nsw i64 [[J:%.*]], 4200 -; CHECK-NEXT: [[GEPDIFF:%.*]] = sub i64 [[GEP1_OFFS]], [[GEP2_OFFS]] +; CHECK-NEXT: [[GEPDIFF:%.*]] = sub nsw i64 [[GEP1_OFFS]], [[GEP2_OFFS]] ; CHECK-NEXT: ret i64 [[GEPDIFF]] ; %gep1 = getelementptr inbounds [100 x [100 x i8]], [100 x [100 x i8]]* %foo, i64 0, i64 42, i64 %i @@ -1502,3 +1502,75 @@ define <2 x i8> @sub_mask_lowbits_splat_extra_use(<2 x i8> %x, <2 x i8>* %p) { %r = sub <2 x i8> %a1, %a2 ret <2 x i8> %r } + +define i16 @sub_nsw_mul_nsw(i16 %x, i16 %y) { +; CHECK-LABEL: @sub_nsw_mul_nsw( +; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i16 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = shl nsw i16 [[TMP1]], 3 +; CHECK-NEXT: ret i16 [[R]] +; + %x8 = mul nsw i16 %x, 8 + %y8 = mul nsw i16 %y, 8 + %r = sub nsw i16 %x8, %y8 + ret i16 %r +} + +define i16 @sub_nuw_mul_nsw(i16 %x, i16 %y) { +; CHECK-LABEL: @sub_nuw_mul_nsw( +; CHECK-NEXT: [[TMP1:%.*]] = sub i16 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = shl i16 [[TMP1]], 2 +; CHECK-NEXT: ret i16 [[R]] +; + %x8 = mul nsw i16 %x, 4 + %y8 = mul nsw i16 %y, 4 + %r = sub nuw i16 %x8, %y8 + ret i16 %r +} + +define i16 @sub_mul_nsw(i16 %x, i16 %y) { +; CHECK-LABEL: @sub_mul_nsw( +; CHECK-NEXT: [[TMP1:%.*]] = sub i16 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = shl i16 [[TMP1]], 4 +; CHECK-NEXT: ret i16 [[R]] +; + %x8 = mul nsw i16 %x, 16 + %y8 = mul nsw i16 %y, 16 + %r = sub i16 %x8, %y8 + ret i16 %r +} + +define i16 @sub_nsw_mul_nuw(i16 %x, i16 %y) { +; CHECK-LABEL: @sub_nsw_mul_nuw( +; CHECK-NEXT: [[TMP1:%.*]] = sub i16 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = shl i16 [[TMP1]], 3 +; CHECK-NEXT: ret i16 [[R]] +; + %x8 = mul nuw i16 %x, 8 + %y8 = mul nuw i16 %y, 8 + %r = sub nsw i16 %x8, %y8 + ret i16 %r +} + +define i16 @sub_nuw_mul_nuw(i16 %x, i16 %y) { +; CHECK-LABEL: @sub_nuw_mul_nuw( +; CHECK-NEXT: [[TMP1:%.*]] = sub nuw i16 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = shl nuw i16 [[TMP1]], 4 +; CHECK-NEXT: ret i16 [[R]] +; + %x8 = mul nuw i16 %x, 16 + %y8 = mul nuw i16 %y, 16 + %r = sub nuw i16 %x8, %y8 + ret i16 %r +} + +define i16 @sub_mul_nuw(i16 %x, i16 %y) { +; CHECK-LABEL: @sub_mul_nuw( +; CHECK-NEXT: [[TMP1:%.*]] = sub i16 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = shl i16 [[TMP1]], 5 +; CHECK-NEXT: ret i16 [[R]] +; + %x8 = mul nuw i16 %x, 32 + %y8 = mul nuw i16 %y, 32 + %r = sub i16 %x8, %y8 + ret i16 %r +} diff --git a/llvm/test/Transforms/InstCombine/vscale_extractelement.ll b/llvm/test/Transforms/InstCombine/vscale_extractelement.ll index 0b148172a42ae..8d49ae712a191 100644 --- a/llvm/test/Transforms/InstCombine/vscale_extractelement.ll +++ b/llvm/test/Transforms/InstCombine/vscale_extractelement.ll @@ -168,3 +168,18 @@ define i1 @extractelement_is_zero( %d, i1 %b, i32 %z) { %bb = icmp eq i32 %ext, 0 ret i1 %bb } + +; OSS-Fuzz #25272 +; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=25272 +define i32 @ossfuzz_25272(float %f) { +; CHECK-LABEL: @ossfuzz_25272( +; CHECK-NEXT: [[VEC_FLOAT:%.*]] = insertelement undef, float [[F:%.*]], i32 0 +; CHECK-NEXT: [[VEC_INT:%.*]] = bitcast [[VEC_FLOAT]] to +; CHECK-NEXT: [[E:%.*]] = extractelement [[VEC_INT]], i32 2147483647 +; CHECK-NEXT: ret i32 [[E]] +; + %vec_float = insertelement undef, float %f, i32 0 + %vec_int = bitcast %vec_float to + %E = extractelement %vec_int, i32 2147483647 + ret i32 %E +} diff --git a/llvm/test/Transforms/InstMerge/st_sink_debuginvariant.ll b/llvm/test/Transforms/InstMerge/st_sink_debuginvariant.ll index 4a2d80407263a..d85a3a34596e5 100644 --- a/llvm/test/Transforms/InstMerge/st_sink_debuginvariant.ll +++ b/llvm/test/Transforms/InstMerge/st_sink_debuginvariant.ll @@ -19,7 +19,7 @@ @g_173 = dso_local local_unnamed_addr global i16 0, !dbg !0 ; Function Attrs: noinline norecurse nounwind -define dso_local void @func_34(%struct.S0* noalias sret %agg.result) local_unnamed_addr #0 !dbg !11 { +define dso_local void @func_34(%struct.S0* noalias sret(%struct.S0) %agg.result) local_unnamed_addr #0 !dbg !11 { entry: br i1 undef, label %if.end, label %if.then, !dbg !18 diff --git a/llvm/test/Transforms/InstSimplify/select.ll b/llvm/test/Transforms/InstSimplify/select.ll index 2dcd29753788e..4cbc5832d234e 100644 --- a/llvm/test/Transforms/InstSimplify/select.ll +++ b/llvm/test/Transforms/InstSimplify/select.ll @@ -957,3 +957,14 @@ define i32 @pr47322_more_poisonous_replacement(i32 %arg) { ret i32 %r1.sroa.0.1 } declare i32 @llvm.cttz.i32(i32, i1 immarg) + +; Partial undef scalable vectors should be ignored. +define @ignore_scalable_undef( %cond) { +; CHECK-LABEL: @ignore_scalable_undef( +; CHECK-NEXT: [[S:%.*]] = select [[COND:%.*]], undef, insertelement ( undef, i1 true, i32 0) +; CHECK-NEXT: ret [[S]] +; + %vec = insertelement undef, i1 true, i32 0 + %s = select %cond, undef, %vec + ret %s +} diff --git a/llvm/test/Transforms/JumpThreading/ddt-crash2.ll b/llvm/test/Transforms/JumpThreading/ddt-crash2.ll index 92bea6a7dffd1..f9b7b89f5054d 100644 --- a/llvm/test/Transforms/JumpThreading/ddt-crash2.ll +++ b/llvm/test/Transforms/JumpThreading/ddt-crash2.ll @@ -2,7 +2,7 @@ %struct.aaa = type { i8 } -define void @chrome(%struct.aaa* noalias sret %arg) local_unnamed_addr #0 align 2 personality i8* bitcast (i32 (...)* @chrome2 to i8*) { +define void @chrome(%struct.aaa* noalias sret(%struct.aaa) %arg) local_unnamed_addr #0 align 2 personality i8* bitcast (i32 (...)* @chrome2 to i8*) { bb: %tmp = load i32, i32* undef, align 4 %tmp1 = icmp eq i32 %tmp, 0 diff --git a/llvm/test/Transforms/LoopFlatten/widen-iv.ll b/llvm/test/Transforms/LoopFlatten/widen-iv.ll index 579061833bf48..9ac9215a8d958 100644 --- a/llvm/test/Transforms/LoopFlatten/widen-iv.ll +++ b/llvm/test/Transforms/LoopFlatten/widen-iv.ll @@ -4,6 +4,9 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +; DONTWIDEN-NOT: %flatten.tripcount +; DONTWIDEN-NOT: %flatten.trunciv + ; Function Attrs: nounwind define void @foo(i32* %A, i32 %N, i32 %M) { ; CHECK-LABEL: @foo( @@ -22,13 +25,14 @@ define void @foo(i32* %A, i32 %N, i32 %M) { ; CHECK-NEXT: [[INDVAR1:%.*]] = phi i64 [ [[INDVAR_NEXT2:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ] ; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[INDVAR1]] to i32 ; CHECK-NEXT: [[MUL_US:%.*]] = mul nsw i32 [[TMP2]], [[M]] +; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc i64 [[INDVAR1]] to i32 ; CHECK-NEXT: br label [[FOR_BODY4_US:%.*]] ; CHECK: for.body4.us: ; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER_US]] ] ; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[INDVAR]] to i32 ; CHECK-NEXT: [[ADD_US:%.*]] = add nsw i32 [[TMP3]], [[MUL_US]] -; CHECK-NEXT: [[IDXPROM_US:%.*]] = sext i32 [[ADD_US]] to i64 -; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVAR1]] +; CHECK-NEXT: [[IDXPROM_US:%.*]] = sext i32 [[FLATTEN_TRUNCIV]] to i64 +; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[IDXPROM_US]] ; CHECK-NEXT: tail call void @f(i32* [[ARRAYIDX_US]]) ; CHECK-NEXT: [[INDVAR_NEXT:%.*]] = add i64 [[INDVAR]], 1 ; CHECK-NEXT: [[CMP2_US:%.*]] = icmp slt i64 [[INDVAR_NEXT]], [[TMP0]] @@ -42,37 +46,6 @@ define void @foo(i32* %A, i32 %N, i32 %M) { ; CHECK: for.cond.cleanup: ; CHECK-NEXT: ret void ; -; DONTWIDEN-LABEL: @foo( -; DONTWIDEN-NEXT: entry: -; DONTWIDEN-NEXT: [[CMP17:%.*]] = icmp sgt i32 [[N:%.*]], 0 -; DONTWIDEN-NEXT: br i1 [[CMP17]], label [[FOR_COND1_PREHEADER_LR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] -; DONTWIDEN: for.cond1.preheader.lr.ph: -; DONTWIDEN-NEXT: [[CMP215:%.*]] = icmp sgt i32 [[M:%.*]], 0 -; DONTWIDEN-NEXT: br i1 [[CMP215]], label [[FOR_COND1_PREHEADER_US_PREHEADER:%.*]], label [[FOR_COND_CLEANUP]] -; DONTWIDEN: for.cond1.preheader.us.preheader: -; DONTWIDEN-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]] -; DONTWIDEN: for.cond1.preheader.us: -; DONTWIDEN-NEXT: [[I_018_US:%.*]] = phi i32 [ [[INC6_US:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ] -; DONTWIDEN-NEXT: [[MUL_US:%.*]] = mul nsw i32 [[I_018_US]], [[M]] -; DONTWIDEN-NEXT: br label [[FOR_BODY4_US:%.*]] -; DONTWIDEN: for.body4.us: -; DONTWIDEN-NEXT: [[J_016_US:%.*]] = phi i32 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[INC_US:%.*]], [[FOR_BODY4_US]] ] -; DONTWIDEN-NEXT: [[ADD_US:%.*]] = add nsw i32 [[J_016_US]], [[MUL_US]] -; DONTWIDEN-NEXT: [[IDXPROM_US:%.*]] = sext i32 [[ADD_US]] to i64 -; DONTWIDEN-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[IDXPROM_US]] -; DONTWIDEN-NEXT: tail call void @f(i32* [[ARRAYIDX_US]]) -; DONTWIDEN-NEXT: [[INC_US]] = add nuw nsw i32 [[J_016_US]], 1 -; DONTWIDEN-NEXT: [[CMP2_US:%.*]] = icmp slt i32 [[INC_US]], [[M]] -; DONTWIDEN-NEXT: br i1 [[CMP2_US]], label [[FOR_BODY4_US]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]] -; DONTWIDEN: for.cond1.for.cond.cleanup3_crit_edge.us: -; DONTWIDEN-NEXT: [[INC6_US]] = add nuw nsw i32 [[I_018_US]], 1 -; DONTWIDEN-NEXT: [[CMP_US:%.*]] = icmp slt i32 [[INC6_US]], [[N]] -; DONTWIDEN-NEXT: br i1 [[CMP_US]], label [[FOR_COND1_PREHEADER_US]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]] -; DONTWIDEN: for.cond.cleanup.loopexit: -; DONTWIDEN-NEXT: br label [[FOR_COND_CLEANUP]] -; DONTWIDEN: for.cond.cleanup: -; DONTWIDEN-NEXT: ret void -; entry: %cmp17 = icmp sgt i32 %N, 0 br i1 %cmp17, label %for.cond1.preheader.lr.ph, label %for.cond.cleanup @@ -108,4 +81,452 @@ for.cond.cleanup: ret void } +define void @zext(i32 %N, i16* nocapture %A, i16 %val) { +; CHECK-LABEL: @zext( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP20_NOT:%.*]] = icmp eq i32 [[N:%.*]], 0 +; CHECK-NEXT: br i1 [[CMP20_NOT]], label [[FOR_END9:%.*]], label [[FOR_COND1_PREHEADER_US_PREHEADER:%.*]] +; CHECK: for.cond1.preheader.us.preheader: +; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[N]] to i64 +; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = mul i64 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]] +; CHECK: for.cond1.preheader.us: +; CHECK-NEXT: [[INDVAR1:%.*]] = phi i64 [ [[INDVAR_NEXT2:%.*]], [[FOR_COND1_FOR_INC7_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ] +; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[INDVAR1]] to i32 +; CHECK-NEXT: [[MUL_US:%.*]] = mul i32 [[TMP2]], [[N]] +; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc i64 [[INDVAR1]] to i32 +; CHECK-NEXT: br label [[FOR_BODY3_US:%.*]] +; CHECK: for.body3.us: +; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER_US]] ] +; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[INDVAR]] to i32 +; CHECK-NEXT: [[ADD_US:%.*]] = add i32 [[TMP3]], [[MUL_US]] +; CHECK-NEXT: [[IDXPROM_US:%.*]] = zext i32 [[FLATTEN_TRUNCIV]] to i64 +; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i16, i16* [[A:%.*]], i64 [[IDXPROM_US]] +; CHECK-NEXT: [[TMP4:%.*]] = load i16, i16* [[ARRAYIDX_US]], align 2 +; CHECK-NEXT: [[ADD5_US:%.*]] = add i16 [[TMP4]], [[VAL:%.*]] +; CHECK-NEXT: store i16 [[ADD5_US]], i16* [[ARRAYIDX_US]], align 2 +; CHECK-NEXT: [[INDVAR_NEXT:%.*]] = add i64 [[INDVAR]], 1 +; CHECK-NEXT: [[CMP2_US:%.*]] = icmp ult i64 [[INDVAR_NEXT]], [[TMP0]] +; CHECK-NEXT: br label [[FOR_COND1_FOR_INC7_CRIT_EDGE_US]] +; CHECK: for.cond1.for.inc7_crit_edge.us: +; CHECK-NEXT: [[INDVAR_NEXT2]] = add i64 [[INDVAR1]], 1 +; CHECK-NEXT: [[CMP_US:%.*]] = icmp ult i64 [[INDVAR_NEXT2]], [[FLATTEN_TRIPCOUNT]] +; CHECK-NEXT: br i1 [[CMP_US]], label [[FOR_COND1_PREHEADER_US]], label [[FOR_END9_LOOPEXIT:%.*]] +; CHECK: for.end9.loopexit: +; CHECK-NEXT: br label [[FOR_END9]] +; CHECK: for.end9: +; CHECK-NEXT: ret void +; +entry: + %cmp20.not = icmp eq i32 %N, 0 + br i1 %cmp20.not, label %for.end9, label %for.cond1.preheader.us.preheader + +for.cond1.preheader.us.preheader: + br label %for.cond1.preheader.us + +for.cond1.preheader.us: + %i.021.us = phi i32 [ %inc8.us, %for.cond1.for.inc7_crit_edge.us ], [ 0, %for.cond1.preheader.us.preheader ] + %mul.us = mul i32 %i.021.us, %N + br label %for.body3.us + +for.body3.us: + %j.019.us = phi i32 [ 0, %for.cond1.preheader.us ], [ %inc.us, %for.body3.us ] + %add.us = add i32 %j.019.us, %mul.us + %idxprom.us = zext i32 %add.us to i64 + %arrayidx.us = getelementptr inbounds i16, i16* %A, i64 %idxprom.us + %0 = load i16, i16* %arrayidx.us, align 2 + %add5.us = add i16 %0, %val + store i16 %add5.us, i16* %arrayidx.us, align 2 + %inc.us = add nuw i32 %j.019.us, 1 + %cmp2.us = icmp ult i32 %inc.us, %N + br i1 %cmp2.us, label %for.body3.us, label %for.cond1.for.inc7_crit_edge.us + +for.cond1.for.inc7_crit_edge.us: + %inc8.us = add i32 %i.021.us, 1 + %cmp.us = icmp ult i32 %inc8.us, %N + br i1 %cmp.us, label %for.cond1.preheader.us, label %for.end9.loopexit + +for.end9.loopexit: + br label %for.end9 + +for.end9: + ret void +} + +; This IR corresponds to this input: +; +; void test(char n, char m) { +; for(char i = 0; i < n; i++) +; for(char j = 0; j < m; j++) { +; char x = i*m+j; +; use_32(x); +; } +; } +; +define void @test(i8 %n, i8 %m) { +; CHECK-LABEL: @test( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP25_NOT:%.*]] = icmp eq i8 [[N:%.*]], 0 +; CHECK-NEXT: br i1 [[CMP25_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND3_PREHEADER_LR_PH:%.*]] +; CHECK: for.cond3.preheader.lr.ph: +; CHECK-NEXT: [[CMP623_NOT:%.*]] = icmp eq i8 [[M:%.*]], 0 +; CHECK-NEXT: br i1 [[CMP623_NOT]], label [[FOR_COND3_PREHEADER_PREHEADER:%.*]], label [[FOR_COND3_PREHEADER_US_PREHEADER:%.*]] +; CHECK: for.cond3.preheader.preheader: +; CHECK-NEXT: br label [[FOR_COND3_PREHEADER:%.*]] +; CHECK: for.cond3.preheader.us.preheader: +; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[M]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[N]] to i64 +; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = mul i64 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br label [[FOR_COND3_PREHEADER_US:%.*]] +; CHECK: for.cond3.preheader.us: +; CHECK-NEXT: [[INDVAR2:%.*]] = phi i64 [ [[INDVAR_NEXT3:%.*]], [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND3_PREHEADER_US_PREHEADER]] ] +; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[INDVAR2]] to i8 +; CHECK-NEXT: [[MUL_US:%.*]] = mul i8 [[TMP2]], [[M]] +; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc i64 [[INDVAR2]] to i8 +; CHECK-NEXT: br label [[FOR_BODY9_US:%.*]] +; CHECK: for.body9.us: +; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ 0, [[FOR_COND3_PREHEADER_US]] ] +; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[INDVAR]] to i8 +; CHECK-NEXT: [[ADD_US:%.*]] = add i8 [[TMP3]], [[MUL_US]] +; CHECK-NEXT: [[CONV14_US:%.*]] = zext i8 [[FLATTEN_TRUNCIV]] to i32 +; CHECK-NEXT: [[CALL_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]]) +; CHECK-NEXT: [[INDVAR_NEXT:%.*]] = add i64 [[INDVAR]], 1 +; CHECK-NEXT: [[CMP6_US:%.*]] = icmp ult i64 [[INDVAR_NEXT]], [[TMP0]] +; CHECK-NEXT: br label [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US]] +; CHECK: for.cond3.for.cond.cleanup8_crit_edge.us: +; CHECK-NEXT: [[INDVAR_NEXT3]] = add i64 [[INDVAR2]], 1 +; CHECK-NEXT: [[CMP_US:%.*]] = icmp ult i64 [[INDVAR_NEXT3]], [[FLATTEN_TRIPCOUNT]] +; CHECK-NEXT: br i1 [[CMP_US]], label [[FOR_COND3_PREHEADER_US]], label [[FOR_COND_CLEANUP_LOOPEXIT1:%.*]] +; CHECK: for.cond3.preheader: +; CHECK-NEXT: [[I_026:%.*]] = phi i8 [ [[INC16:%.*]], [[FOR_COND3_PREHEADER]] ], [ 0, [[FOR_COND3_PREHEADER_PREHEADER]] ] +; CHECK-NEXT: [[INC16]] = add i8 [[I_026]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[INC16]], [[N]] +; CHECK-NEXT: br i1 [[CMP]], label [[FOR_COND3_PREHEADER]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]] +; CHECK: for.cond.cleanup.loopexit: +; CHECK-NEXT: br label [[FOR_COND_CLEANUP]] +; CHECK: for.cond.cleanup.loopexit1: +; CHECK-NEXT: br label [[FOR_COND_CLEANUP]] +; CHECK: for.cond.cleanup: +; CHECK-NEXT: ret void +; +entry: + %cmp25.not = icmp eq i8 %n, 0 + br i1 %cmp25.not, label %for.cond.cleanup, label %for.cond3.preheader.lr.ph + +for.cond3.preheader.lr.ph: + %cmp623.not = icmp eq i8 %m, 0 + br i1 %cmp623.not, label %for.cond3.preheader.preheader, label %for.cond3.preheader.us.preheader + +for.cond3.preheader.preheader: + br label %for.cond3.preheader + +for.cond3.preheader.us.preheader: + br label %for.cond3.preheader.us + +for.cond3.preheader.us: + %i.026.us = phi i8 [ %inc16.us, %for.cond3.for.cond.cleanup8_crit_edge.us ], [ 0, %for.cond3.preheader.us.preheader ] + %mul.us = mul i8 %i.026.us, %m + br label %for.body9.us + +for.body9.us: + %j.024.us = phi i8 [ 0, %for.cond3.preheader.us ], [ %inc.us, %for.body9.us ] + %add.us = add i8 %j.024.us, %mul.us + %conv14.us = zext i8 %add.us to i32 + %call.us = tail call i32 @use_32(i32 %conv14.us) #2 + %inc.us = add nuw i8 %j.024.us, 1 + %cmp6.us = icmp ult i8 %inc.us, %m + br i1 %cmp6.us, label %for.body9.us, label %for.cond3.for.cond.cleanup8_crit_edge.us + +for.cond3.for.cond.cleanup8_crit_edge.us: + %inc16.us = add i8 %i.026.us, 1 + %cmp.us = icmp ult i8 %inc16.us, %n + br i1 %cmp.us, label %for.cond3.preheader.us, label %for.cond.cleanup + +for.cond3.preheader: + %i.026 = phi i8 [ %inc16, %for.cond3.preheader ], [ 0, %for.cond3.preheader.preheader ] + %inc16 = add i8 %i.026, 1 + %cmp = icmp ult i8 %inc16, %n + br i1 %cmp, label %for.cond3.preheader, label %for.cond.cleanup + +for.cond.cleanup: + ret void +} + +; This IR corresponds to this input: +; +; void test3(char n, char m) { +; for(char i = 0; i < n; i++) +; for(char j = 0; j < m; j++) { +; char x = i*m+j; +; use_32(x); +; use_16(x); +; use_32(x); +; use_16(x); +; use_64(x); +; } +; } +; +define void @test3(i8 %n, i8 %m) { +; CHECK-LABEL: @test3( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP37_NOT:%.*]] = icmp eq i8 [[N:%.*]], 0 +; CHECK-NEXT: br i1 [[CMP37_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND3_PREHEADER_LR_PH:%.*]] +; CHECK: for.cond3.preheader.lr.ph: +; CHECK-NEXT: [[CMP635_NOT:%.*]] = icmp eq i8 [[M:%.*]], 0 +; CHECK-NEXT: br i1 [[CMP635_NOT]], label [[FOR_COND3_PREHEADER_PREHEADER:%.*]], label [[FOR_COND3_PREHEADER_US_PREHEADER:%.*]] +; CHECK: for.cond3.preheader.preheader: +; CHECK-NEXT: br label [[FOR_COND3_PREHEADER:%.*]] +; CHECK: for.cond3.preheader.us.preheader: +; CHECK-NEXT: [[TMP0:%.*]] = zext i8 [[M]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[N]] to i64 +; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = mul i64 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br label [[FOR_COND3_PREHEADER_US:%.*]] +; CHECK: for.cond3.preheader.us: +; CHECK-NEXT: [[INDVAR2:%.*]] = phi i64 [ [[INDVAR_NEXT3:%.*]], [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND3_PREHEADER_US_PREHEADER]] ] +; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[INDVAR2]] to i8 +; CHECK-NEXT: [[MUL_US:%.*]] = mul i8 [[TMP2]], [[M]] +; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc i64 [[INDVAR2]] to i8 +; CHECK-NEXT: br label [[FOR_BODY9_US:%.*]] +; CHECK: for.body9.us: +; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ 0, [[FOR_COND3_PREHEADER_US]] ] +; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[INDVAR]] to i8 +; CHECK-NEXT: [[ADD_US:%.*]] = add i8 [[TMP3]], [[MUL_US]] +; CHECK-NEXT: [[CONV14_US:%.*]] = zext i8 [[FLATTEN_TRUNCIV]] to i32 +; CHECK-NEXT: [[CALL_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]]) +; CHECK-NEXT: [[CONV15_US:%.*]] = zext i8 [[FLATTEN_TRUNCIV]] to i16 +; CHECK-NEXT: [[CALL16_US:%.*]] = tail call i32 @use_16(i16 [[CONV15_US]]) +; CHECK-NEXT: [[CALL18_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]]) +; CHECK-NEXT: [[CALL20_US:%.*]] = tail call i32 @use_16(i16 [[CONV15_US]]) +; CHECK-NEXT: [[CONV21_US:%.*]] = zext i8 [[FLATTEN_TRUNCIV]] to i64 +; CHECK-NEXT: [[CALL22_US:%.*]] = tail call i32 @use_64(i64 [[CONV21_US]]) +; CHECK-NEXT: [[INDVAR_NEXT:%.*]] = add i64 [[INDVAR]], 1 +; CHECK-NEXT: [[CMP6_US:%.*]] = icmp ult i64 [[INDVAR_NEXT]], [[TMP0]] +; CHECK-NEXT: br label [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US]] +; CHECK: for.cond3.for.cond.cleanup8_crit_edge.us: +; CHECK-NEXT: [[INDVAR_NEXT3]] = add i64 [[INDVAR2]], 1 +; CHECK-NEXT: [[CMP_US:%.*]] = icmp ult i64 [[INDVAR_NEXT3]], [[FLATTEN_TRIPCOUNT]] +; CHECK-NEXT: br i1 [[CMP_US]], label [[FOR_COND3_PREHEADER_US]], label [[FOR_COND_CLEANUP_LOOPEXIT1:%.*]] +; CHECK: for.cond3.preheader: +; CHECK-NEXT: [[I_038:%.*]] = phi i8 [ [[INC24:%.*]], [[FOR_COND3_PREHEADER]] ], [ 0, [[FOR_COND3_PREHEADER_PREHEADER]] ] +; CHECK-NEXT: [[INC24]] = add i8 [[I_038]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[INC24]], [[N]] +; CHECK-NEXT: br i1 [[CMP]], label [[FOR_COND3_PREHEADER]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]] +; CHECK: for.cond.cleanup.loopexit: +; CHECK-NEXT: br label [[FOR_COND_CLEANUP]] +; CHECK: for.cond.cleanup.loopexit1: +; CHECK-NEXT: br label [[FOR_COND_CLEANUP]] +; CHECK: for.cond.cleanup: +; CHECK-NEXT: ret void +; +entry: + %cmp37.not = icmp eq i8 %n, 0 + br i1 %cmp37.not, label %for.cond.cleanup, label %for.cond3.preheader.lr.ph + +for.cond3.preheader.lr.ph: + %cmp635.not = icmp eq i8 %m, 0 + br i1 %cmp635.not, label %for.cond3.preheader.preheader, label %for.cond3.preheader.us.preheader + +for.cond3.preheader.preheader: + br label %for.cond3.preheader + +for.cond3.preheader.us.preheader: + br label %for.cond3.preheader.us + +for.cond3.preheader.us: + %i.038.us = phi i8 [ %inc24.us, %for.cond3.for.cond.cleanup8_crit_edge.us ], [ 0, %for.cond3.preheader.us.preheader ] + %mul.us = mul i8 %i.038.us, %m + br label %for.body9.us + +for.body9.us: + %j.036.us = phi i8 [ 0, %for.cond3.preheader.us ], [ %inc.us, %for.body9.us ] + %add.us = add i8 %j.036.us, %mul.us + %conv14.us = zext i8 %add.us to i32 + %call.us = tail call i32 @use_32(i32 %conv14.us) + %conv15.us = zext i8 %add.us to i16 + %call16.us = tail call i32 @use_16(i16 %conv15.us) + %call18.us = tail call i32 @use_32(i32 %conv14.us) + %call20.us = tail call i32 @use_16(i16 %conv15.us) + %conv21.us = zext i8 %add.us to i64 + %call22.us = tail call i32 @use_64(i64 %conv21.us) + %inc.us = add nuw i8 %j.036.us, 1 + %cmp6.us = icmp ult i8 %inc.us, %m + br i1 %cmp6.us, label %for.body9.us, label %for.cond3.for.cond.cleanup8_crit_edge.us + +for.cond3.for.cond.cleanup8_crit_edge.us: + %inc24.us = add i8 %i.038.us, 1 + %cmp.us = icmp ult i8 %inc24.us, %n + br i1 %cmp.us, label %for.cond3.preheader.us, label %for.cond.cleanup + +for.cond3.preheader: + %i.038 = phi i8 [ %inc24, %for.cond3.preheader ], [ 0, %for.cond3.preheader.preheader ] + %inc24 = add i8 %i.038, 1 + %cmp = icmp ult i8 %inc24, %n + br i1 %cmp, label %for.cond3.preheader, label %for.cond.cleanup + +for.cond.cleanup: + ret void +} + +; This IR corresponds to this input: +; +; void test4(short n, short m) { +; for(short i = 0; i < n; i++) +; for(short j = 0; j < m; j++) { +; short x = i*m+j; +; use_32(x); +; use_16(x); +; use_32(x); +; use_16(x); +; use_64(x); +; } +; } +; +define void @test4(i16 %n, i16 %m) { +; CHECK-LABEL: @test4( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP38:%.*]] = icmp sgt i16 [[N:%.*]], 0 +; CHECK-NEXT: br i1 [[CMP38]], label [[FOR_COND3_PREHEADER_LR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] +; CHECK: for.cond3.preheader.lr.ph: +; CHECK-NEXT: [[CMP636:%.*]] = icmp sgt i16 [[M:%.*]], 0 +; CHECK-NEXT: br i1 [[CMP636]], label [[FOR_COND3_PREHEADER_US_PREHEADER:%.*]], label [[FOR_COND3_PREHEADER_PREHEADER:%.*]] +; CHECK: for.cond3.preheader.preheader: +; CHECK-NEXT: br label [[FOR_COND3_PREHEADER:%.*]] +; CHECK: for.cond3.preheader.us.preheader: +; CHECK-NEXT: [[TMP0:%.*]] = sext i16 [[M]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[N]] to i64 +; CHECK-NEXT: [[FLATTEN_TRIPCOUNT:%.*]] = mul i64 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br label [[FOR_COND3_PREHEADER_US:%.*]] +; CHECK: for.cond3.preheader.us: +; CHECK-NEXT: [[INDVAR2:%.*]] = phi i64 [ [[INDVAR_NEXT3:%.*]], [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND3_PREHEADER_US_PREHEADER]] ] +; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[INDVAR2]] to i16 +; CHECK-NEXT: [[MUL_US:%.*]] = mul i16 [[TMP2]], [[M]] +; CHECK-NEXT: [[FLATTEN_TRUNCIV:%.*]] = trunc i64 [[INDVAR2]] to i16 +; CHECK-NEXT: br label [[FOR_BODY9_US:%.*]] +; CHECK: for.body9.us: +; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ 0, [[FOR_COND3_PREHEADER_US]] ] +; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[INDVAR]] to i16 +; CHECK-NEXT: [[ADD_US:%.*]] = add i16 [[TMP3]], [[MUL_US]] +; CHECK-NEXT: [[CONV14_US:%.*]] = sext i16 [[FLATTEN_TRUNCIV]] to i32 +; CHECK-NEXT: [[CALL_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]]) +; CHECK-NEXT: [[CALL15_US:%.*]] = tail call i32 @use_16(i16 [[FLATTEN_TRUNCIV]]) +; CHECK-NEXT: [[CALL17_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]]) +; CHECK-NEXT: [[CALL18_US:%.*]] = tail call i32 @use_16(i16 [[FLATTEN_TRUNCIV]]) +; CHECK-NEXT: [[CONV19_US:%.*]] = sext i16 [[FLATTEN_TRUNCIV]] to i64 +; CHECK-NEXT: [[CALL20_US:%.*]] = tail call i32 @use_64(i64 [[CONV19_US]]) +; CHECK-NEXT: [[INDVAR_NEXT:%.*]] = add i64 [[INDVAR]], 1 +; CHECK-NEXT: [[CMP6_US:%.*]] = icmp slt i64 [[INDVAR_NEXT]], [[TMP0]] +; CHECK-NEXT: br label [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US]] +; CHECK: for.cond3.for.cond.cleanup8_crit_edge.us: +; CHECK-NEXT: [[INDVAR_NEXT3]] = add i64 [[INDVAR2]], 1 +; CHECK-NEXT: [[CMP_US:%.*]] = icmp slt i64 [[INDVAR_NEXT3]], [[FLATTEN_TRIPCOUNT]] +; CHECK-NEXT: br i1 [[CMP_US]], label [[FOR_COND3_PREHEADER_US]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]] +; CHECK: for.cond3.preheader: +; CHECK-NEXT: [[I_039:%.*]] = phi i16 [ [[INC22:%.*]], [[FOR_COND3_PREHEADER]] ], [ 0, [[FOR_COND3_PREHEADER_PREHEADER]] ] +; CHECK-NEXT: [[INC22]] = add i16 [[I_039]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[INC22]], [[N]] +; CHECK-NEXT: br i1 [[CMP]], label [[FOR_COND3_PREHEADER]], label [[FOR_COND_CLEANUP_LOOPEXIT1:%.*]] +; CHECK: for.cond.cleanup.loopexit: +; CHECK-NEXT: br label [[FOR_COND_CLEANUP]] +; CHECK: for.cond.cleanup.loopexit1: +; CHECK-NEXT: br label [[FOR_COND_CLEANUP]] +; CHECK: for.cond.cleanup: +; CHECK-NEXT: ret void +; +; DONTWIDEN-LABEL: @test4( +; DONTWIDEN-NEXT: entry: +; DONTWIDEN-NEXT: [[CMP38:%.*]] = icmp sgt i16 [[N:%.*]], 0 +; DONTWIDEN-NEXT: br i1 [[CMP38]], label [[FOR_COND3_PREHEADER_LR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]] +; DONTWIDEN: for.cond3.preheader.lr.ph: +; DONTWIDEN-NEXT: [[CMP636:%.*]] = icmp sgt i16 [[M:%.*]], 0 +; DONTWIDEN-NEXT: br i1 [[CMP636]], label [[FOR_COND3_PREHEADER_US_PREHEADER:%.*]], label [[FOR_COND3_PREHEADER_PREHEADER:%.*]] +; DONTWIDEN: for.cond3.preheader.preheader: +; DONTWIDEN-NEXT: br label [[FOR_COND3_PREHEADER:%.*]] +; DONTWIDEN: for.cond3.preheader.us.preheader: +; DONTWIDEN-NEXT: br label [[FOR_COND3_PREHEADER_US:%.*]] +; DONTWIDEN: for.cond3.preheader.us: +; DONTWIDEN-NEXT: [[I_039_US:%.*]] = phi i16 [ [[INC22_US:%.*]], [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND3_PREHEADER_US_PREHEADER]] ] +; DONTWIDEN-NEXT: [[MUL_US:%.*]] = mul i16 [[I_039_US]], [[M]] +; DONTWIDEN-NEXT: br label [[FOR_BODY9_US:%.*]] +; DONTWIDEN: for.body9.us: +; DONTWIDEN-NEXT: [[J_037_US:%.*]] = phi i16 [ 0, [[FOR_COND3_PREHEADER_US]] ], [ [[INC_US:%.*]], [[FOR_BODY9_US]] ] +; DONTWIDEN-NEXT: [[ADD_US:%.*]] = add i16 [[J_037_US]], [[MUL_US]] +; DONTWIDEN-NEXT: [[CONV14_US:%.*]] = sext i16 [[ADD_US]] to i32 +; DONTWIDEN-NEXT: [[CALL_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]]) +; DONTWIDEN-NEXT: [[CALL15_US:%.*]] = tail call i32 @use_16(i16 [[ADD_US]]) +; DONTWIDEN-NEXT: [[CALL17_US:%.*]] = tail call i32 @use_32(i32 [[CONV14_US]]) +; DONTWIDEN-NEXT: [[CALL18_US:%.*]] = tail call i32 @use_16(i16 [[ADD_US]]) +; DONTWIDEN-NEXT: [[CONV19_US:%.*]] = sext i16 [[ADD_US]] to i64 +; DONTWIDEN-NEXT: [[CALL20_US:%.*]] = tail call i32 @use_64(i64 [[CONV19_US]]) +; DONTWIDEN-NEXT: [[INC_US]] = add nuw nsw i16 [[J_037_US]], 1 +; DONTWIDEN-NEXT: [[CMP6_US:%.*]] = icmp slt i16 [[INC_US]], [[M]] +; DONTWIDEN-NEXT: br i1 [[CMP6_US]], label [[FOR_BODY9_US]], label [[FOR_COND3_FOR_COND_CLEANUP8_CRIT_EDGE_US]] +; DONTWIDEN: for.cond3.for.cond.cleanup8_crit_edge.us: +; DONTWIDEN-NEXT: [[INC22_US]] = add i16 [[I_039_US]], 1 +; DONTWIDEN-NEXT: [[CMP_US:%.*]] = icmp slt i16 [[INC22_US]], [[N]] +; DONTWIDEN-NEXT: br i1 [[CMP_US]], label [[FOR_COND3_PREHEADER_US]], label [[FOR_COND_CLEANUP_LOOPEXIT:%.*]] +; DONTWIDEN: for.cond3.preheader: +; DONTWIDEN-NEXT: [[I_039:%.*]] = phi i16 [ [[INC22:%.*]], [[FOR_COND3_PREHEADER]] ], [ 0, [[FOR_COND3_PREHEADER_PREHEADER]] ] +; DONTWIDEN-NEXT: [[INC22]] = add i16 [[I_039]], 1 +; DONTWIDEN-NEXT: [[CMP:%.*]] = icmp slt i16 [[INC22]], [[N]] +; DONTWIDEN-NEXT: br i1 [[CMP]], label [[FOR_COND3_PREHEADER]], label [[FOR_COND_CLEANUP_LOOPEXIT1:%.*]] +; DONTWIDEN: for.cond.cleanup.loopexit: +; DONTWIDEN-NEXT: br label [[FOR_COND_CLEANUP]] +; DONTWIDEN: for.cond.cleanup.loopexit1: +; DONTWIDEN-NEXT: br label [[FOR_COND_CLEANUP]] +; DONTWIDEN: for.cond.cleanup: +; DONTWIDEN-NEXT: ret void +; +entry: + %cmp38 = icmp sgt i16 %n, 0 + br i1 %cmp38, label %for.cond3.preheader.lr.ph, label %for.cond.cleanup + +for.cond3.preheader.lr.ph: + %cmp636 = icmp sgt i16 %m, 0 + br i1 %cmp636, label %for.cond3.preheader.us.preheader, label %for.cond3.preheader.preheader + +for.cond3.preheader.preheader: + br label %for.cond3.preheader + +for.cond3.preheader.us.preheader: + br label %for.cond3.preheader.us + +for.cond3.preheader.us: + %i.039.us = phi i16 [ %inc22.us, %for.cond3.for.cond.cleanup8_crit_edge.us ], [ 0, %for.cond3.preheader.us.preheader ] + %mul.us = mul i16 %i.039.us, %m + br label %for.body9.us + +for.body9.us: + %j.037.us = phi i16 [ 0, %for.cond3.preheader.us ], [ %inc.us, %for.body9.us ] + %add.us = add i16 %j.037.us, %mul.us + %conv14.us = sext i16 %add.us to i32 + %call.us = tail call i32 @use_32(i32 %conv14.us) #2 + %call15.us = tail call i32 @use_16(i16 %add.us) #2 + %call17.us = tail call i32 @use_32(i32 %conv14.us) #2 + %call18.us = tail call i32 @use_16(i16 %add.us) #2 + %conv19.us = sext i16 %add.us to i64 + %call20.us = tail call i32 @use_64(i64 %conv19.us) #2 + %inc.us = add nuw nsw i16 %j.037.us, 1 + %cmp6.us = icmp slt i16 %inc.us, %m + br i1 %cmp6.us, label %for.body9.us, label %for.cond3.for.cond.cleanup8_crit_edge.us + +for.cond3.for.cond.cleanup8_crit_edge.us: + %inc22.us = add i16 %i.039.us, 1 + %cmp.us = icmp slt i16 %inc22.us, %n + br i1 %cmp.us, label %for.cond3.preheader.us, label %for.cond.cleanup + +for.cond3.preheader: + %i.039 = phi i16 [ %inc22, %for.cond3.preheader ], [ 0, %for.cond3.preheader.preheader ] + %inc22 = add i16 %i.039, 1 + %cmp = icmp slt i16 %inc22, %n + br i1 %cmp, label %for.cond3.preheader, label %for.cond.cleanup + +for.cond.cleanup: + ret void +} + +declare dso_local i32 @use_32(i32) +declare dso_local i32 @use_16(i16) +declare dso_local i32 @use_64(i64) + declare dso_local void @f(i32* %0) local_unnamed_addr #1 diff --git a/llvm/test/Transforms/LoopLoadElim/pr-48150.ll b/llvm/test/Transforms/LoopLoadElim/pr-48150.ll index 60cc02c50ad4e..a88fd9b9d938f 100644 --- a/llvm/test/Transforms/LoopLoadElim/pr-48150.ll +++ b/llvm/test/Transforms/LoopLoadElim/pr-48150.ll @@ -1,6 +1,4 @@ ; RUN: opt -passes=loop-load-elim -S < %s | FileCheck %s -; REQUIRES: asserts -; XFAIL: * target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/LoopStrengthReduce/dbg-preserve-0.ll b/llvm/test/Transforms/LoopStrengthReduce/dbg-preserve-0.ll deleted file mode 100644 index 71031aabb95b7..0000000000000 --- a/llvm/test/Transforms/LoopStrengthReduce/dbg-preserve-0.ll +++ /dev/null @@ -1,74 +0,0 @@ -; RUN: opt < %s -loop-reduce -S | FileCheck %s - -; Test that LSR preserves debug-info for induction variables. - -target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" - -define dso_local void @foo(i8* nocapture %p) local_unnamed_addr !dbg !7 { -; CHECK-LABEL: @foo( -entry: - call void @llvm.dbg.value(metadata i8* %p, metadata !13, metadata !DIExpression()), !dbg !16 - call void @llvm.dbg.value(metadata i8 0, metadata !14, metadata !DIExpression()), !dbg !17 - br label %for.body, !dbg !18 - -for.cond.cleanup: ; preds = %for.body - ret void, !dbg !19 - -for.body: ; preds = %entry, %for.body -; CHECK-LABEL: for.body: - %i.06 = phi i8 [ 0, %entry ], [ %inc, %for.body ] - %p.addr.05 = phi i8* [ %p, %entry ], [ %add.ptr, %for.body ] - call void @llvm.dbg.value(metadata i8 %i.06, metadata !14, metadata !DIExpression()), !dbg !17 - call void @llvm.dbg.value(metadata i8* %p.addr.05, metadata !13, metadata !DIExpression()), !dbg !16 -; CHECK-NOT: call void @llvm.dbg.value(metadata i8* undef -; CHECK: call void @llvm.dbg.value(metadata i8* %lsr.iv, metadata ![[MID_p:[0-9]+]], metadata !DIExpression(DW_OP_constu, 3, DW_OP_minus, DW_OP_stack_value)), !dbg !16 - %add.ptr = getelementptr inbounds i8, i8* %p.addr.05, i64 3, !dbg !20 - call void @llvm.dbg.value(metadata i8* %add.ptr, metadata !13, metadata !DIExpression()), !dbg !16 -; CHECK-NOT: call void @llvm.dbg.value(metadata i8* undef -; CHECK: call void @llvm.dbg.value(metadata i8* %lsr.iv, metadata ![[MID_p]], metadata !DIExpression()), !dbg !16 - store i8 %i.06, i8* %add.ptr, align 1, !dbg !23, !tbaa !24 - %inc = add nuw nsw i8 %i.06, 1, !dbg !27 - call void @llvm.dbg.value(metadata i8 %inc, metadata !14, metadata !DIExpression()), !dbg !17 - %exitcond.not = icmp eq i8 %inc, 32, !dbg !28 - br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !dbg !18, !llvm.loop !29 -} - -declare void @llvm.dbg.value(metadata, metadata, metadata) - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!3, !4, !5} -!llvm.ident = !{!6} - -!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "lsrdbg.c", directory: "/") -!2 = !{} -!3 = !{i32 7, !"Dwarf Version", i32 4} -!4 = !{i32 2, !"Debug Info Version", i32 3} -!5 = !{i32 1, !"wchar_size", i32 4} -!6 = !{!"clang version 12.0.0"} -!7 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 2, type: !8, scopeLine: 2, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !12) -!8 = !DISubroutineType(types: !9) -!9 = !{null, !10} -!10 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !11, size: 64) -!11 = !DIBasicType(name: "unsigned char", size: 8, encoding: DW_ATE_unsigned_char) -!12 = !{!13, !14} -!13 = !DILocalVariable(name: "p", arg: 1, scope: !7, file: !1, line: 2, type: !10) -; CHECK: ![[MID_p]] = !DILocalVariable(name: "p", arg: 1, scope: !7, file: !1, line: 2, type: !10) -!14 = !DILocalVariable(name: "i", scope: !15, file: !1, line: 4, type: !11) -!15 = distinct !DILexicalBlock(scope: !7, file: !1, line: 4, column: 3) -!16 = !DILocation(line: 0, scope: !7) -!17 = !DILocation(line: 0, scope: !15) -!18 = !DILocation(line: 4, column: 3, scope: !15) -!19 = !DILocation(line: 8, column: 1, scope: !7) -!20 = !DILocation(line: 5, column: 7, scope: !21) -!21 = distinct !DILexicalBlock(scope: !22, file: !1, line: 4, column: 42) -!22 = distinct !DILexicalBlock(scope: !15, file: !1, line: 4, column: 3) -!23 = !DILocation(line: 6, column: 8, scope: !21) -!24 = !{!25, !25, i64 0} -!25 = !{!"omnipotent char", !26, i64 0} -!26 = !{!"Simple C/C++ TBAA"} -!27 = !DILocation(line: 4, column: 38, scope: !22) -!28 = !DILocation(line: 4, column: 31, scope: !22) -!29 = distinct !{!29, !18, !30, !31} -!30 = !DILocation(line: 7, column: 3, scope: !15) -!31 = !{!"llvm.loop.unroll.disable"} diff --git a/llvm/test/Transforms/LoopUnroll/peel-loop-inner.ll b/llvm/test/Transforms/LoopUnroll/peel-loop-inner.ll index 7b088b31a54c4..8d89053c96f13 100644 --- a/llvm/test/Transforms/LoopUnroll/peel-loop-inner.ll +++ b/llvm/test/Transforms/LoopUnroll/peel-loop-inner.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -S -passes='require,loop-unroll,simplify-cfg,instcombine' -unroll-force-peel-count=3 -verify-dom-info | FileCheck %s define void @basic(i32 %K, i32 %N) { @@ -6,24 +7,19 @@ define void @basic(i32 %K, i32 %N) { ; CHECK-NEXT: br label [[OUTER:%.*]] ; CHECK: outer: ; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[I_INC:%.*]], [[OUTER_BACKEDGE:%.*]] ] -; CHECK-NEXT: [[CMP_INNER_PEEL:%.*]] = icmp sgt i32 [[K:%.*]], 1 -; CHECK-NEXT: br i1 [[CMP_INNER_PEEL]], label [[INNER_PEEL2:%.*]], label [[OUTER_BACKEDGE]] -; CHECK: inner.peel2: -; CHECK-NEXT: [[CMP_INNER_PEEL4:%.*]] = icmp eq i32 [[K]], 2 -; CHECK-NEXT: br i1 [[CMP_INNER_PEEL4]], label [[OUTER_BACKEDGE]], label [[INNER_PEEL6:%.*]] -; CHECK: inner.peel6: -; CHECK-NEXT: [[CMP_INNER_PEEL8:%.*]] = icmp sgt i32 [[K]], 3 +; CHECK-NEXT: [[CMP_INNER_PEEL8:%.*]] = icmp sgt i32 [[K:%.*]], 3 ; CHECK-NEXT: br i1 [[CMP_INNER_PEEL8]], label [[INNER:%.*]], label [[OUTER_BACKEDGE]] ; CHECK: inner: -; CHECK-NEXT: [[J:%.*]] = phi i32 [ [[J_INC:%.*]], [[INNER]] ], [ 3, [[INNER_PEEL6]] ] +; CHECK-NEXT: [[J:%.*]] = phi i32 [ [[J_INC:%.*]], [[INNER]] ], [ 3, [[OUTER]] ] ; CHECK-NEXT: [[J_INC]] = add nuw nsw i32 [[J]], 1 ; CHECK-NEXT: [[CMP_INNER:%.*]] = icmp slt i32 [[J_INC]], [[K]] -; CHECK-NEXT: br i1 [[CMP_INNER]], label [[INNER]], label [[OUTER_BACKEDGE]], !llvm.loop !0 +; CHECK-NEXT: br i1 [[CMP_INNER]], label [[INNER]], label [[OUTER_BACKEDGE]], [[LOOP0:!llvm.loop !.*]] ; CHECK: outer.backedge: ; CHECK-NEXT: [[I_INC]] = add i32 [[I]], 1 ; CHECK-NEXT: [[CMP_OUTER:%.*]] = icmp slt i32 [[I_INC]], [[N:%.*]] -; CHECK-NOT: !llvm.loop +; CHECK-NEXT: br i1 [[CMP_OUTER]], label [[OUTER]], label [[END:%.*]] ; CHECK: end: +; CHECK-NEXT: ret void ; entry: br label %outer diff --git a/llvm/test/Transforms/LoopUnrollAndJam/opt-levels.ll b/llvm/test/Transforms/LoopUnrollAndJam/opt-levels.ll index ef6d2c7502fbd..09a5b10c9ee14 100644 --- a/llvm/test/Transforms/LoopUnrollAndJam/opt-levels.ll +++ b/llvm/test/Transforms/LoopUnrollAndJam/opt-levels.ll @@ -1,7 +1,7 @@ -; RUN: opt < %s -S -passes="default" -unroll-runtime=true -enable-npm-unroll-and-jam -unroll-threshold-default=0 -unroll-threshold-aggressive=300 | FileCheck %s -check-prefix=O2 -; RUN: opt < %s -S -passes="default" -unroll-runtime=true -enable-npm-unroll-and-jam -unroll-threshold-default=0 -unroll-threshold-aggressive=300 | FileCheck %s -check-prefix=O3 -; RUN: opt < %s -S -passes="default" -unroll-runtime=true -enable-npm-unroll-and-jam -unroll-threshold-default=0 -unroll-threshold-aggressive=300 | FileCheck %s -check-prefix=Os -; RUN: opt < %s -S -passes="default" -unroll-runtime=true -enable-npm-unroll-and-jam -unroll-threshold-default=0 -unroll-threshold-aggressive=300 | FileCheck %s -check-prefix=Oz +; RUN: opt < %s -S -passes="default" -unroll-runtime=true -enable-unroll-and-jam -unroll-threshold-default=0 -unroll-threshold-aggressive=300 | FileCheck %s -check-prefix=O2 +; RUN: opt < %s -S -passes="default" -unroll-runtime=true -enable-unroll-and-jam -unroll-threshold-default=0 -unroll-threshold-aggressive=300 | FileCheck %s -check-prefix=O3 +; RUN: opt < %s -S -passes="default" -unroll-runtime=true -enable-unroll-and-jam -unroll-threshold-default=0 -unroll-threshold-aggressive=300 | FileCheck %s -check-prefix=Os +; RUN: opt < %s -S -passes="default" -unroll-runtime=true -enable-unroll-and-jam -unroll-threshold-default=0 -unroll-threshold-aggressive=300 | FileCheck %s -check-prefix=Oz ; Check that Os and Oz are optimized like O2, not like O3. To easily highlight ; the behavior, we artificially disable unrolling for anything but O3 by setting diff --git a/llvm/test/Transforms/LoopUnswitch/2007-08-01-Dom.ll b/llvm/test/Transforms/LoopUnswitch/2007-08-01-Dom.ll index a5bf368d9833f..69bc3eddf4121 100644 --- a/llvm/test/Transforms/LoopUnswitch/2007-08-01-Dom.ll +++ b/llvm/test/Transforms/LoopUnswitch/2007-08-01-Dom.ll @@ -3,7 +3,7 @@ %struct.QBasicAtomic = type { i32 } -define void @_ZNK5QDate9addMonthsEi(%struct.QBasicAtomic* sret %agg.result, %struct.QBasicAtomic* %this, i32 %nmonths) { +define void @_ZNK5QDate9addMonthsEi(%struct.QBasicAtomic* sret(%struct.QBasicAtomic) %agg.result, %struct.QBasicAtomic* %this, i32 %nmonths) { entry: br label %cond_true90 diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll b/llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll new file mode 100644 index 0000000000000..903b467c7581f --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll @@ -0,0 +1,292 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -loop-vectorize -instcombine -simplifycfg < %s -S -o - | FileCheck %s + +target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "thumbv8.1m.main-arm-none-eabi" + +define void @arm_abs_q7(i8* nocapture readonly %pSrc, i8* nocapture %pDst, i32 %blockSize) #0 { +; CHECK-LABEL: @arm_abs_q7( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP_NOT19:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0 +; CHECK-NEXT: br i1 [[CMP_NOT19]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]] +; CHECK: while.body.preheader: +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[BLOCKSIZE]], 16 +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] +; CHECK: vector.memcheck: +; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, i8* [[PDST:%.*]], i32 [[BLOCKSIZE]] +; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, i8* [[PSRC:%.*]], i32 [[BLOCKSIZE]] +; CHECK-NEXT: [[BOUND0:%.*]] = icmp ugt i8* [[SCEVGEP1]], [[PDST]] +; CHECK-NEXT: [[BOUND1:%.*]] = icmp ugt i8* [[SCEVGEP]], [[PSRC]] +; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] +; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[BLOCKSIZE]], -16 +; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, i8* [[PSRC]], i32 [[N_VEC]] +; CHECK-NEXT: [[IND_END3:%.*]] = and i32 [[BLOCKSIZE]], 15 +; CHECK-NEXT: [[IND_END5:%.*]] = getelementptr i8, i8* [[PDST]], i32 [[N_VEC]] +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[PSRC]], i32 [[INDEX]] +; CHECK-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, i8* [[PDST]], i32 [[INDEX]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[NEXT_GEP]] to <16 x i8>* +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1, !alias.scope !0 +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <16 x i8> [[WIDE_LOAD]], zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <16 x i8> [[WIDE_LOAD]], +; CHECK-NEXT: [[TMP3:%.*]] = sub <16 x i8> zeroinitializer, [[WIDE_LOAD]] +; CHECK-NEXT: [[TMP4:%.*]] = select <16 x i1> [[TMP2]], <16 x i8> , <16 x i8> [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = select <16 x i1> [[TMP1]], <16 x i8> [[WIDE_LOAD]], <16 x i8> [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[NEXT_GEP6]] to <16 x i8>* +; CHECK-NEXT: store <16 x i8> [[TMP5]], <16 x i8>* [[TMP6]], align 1, !alias.scope !3, !noalias !0 +; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 16 +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP5:!llvm.loop !.*]] +; CHECK: middle.block: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N_VEC]], [[BLOCKSIZE]] +; CHECK-NEXT: br i1 [[CMP_N]], label [[WHILE_END]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8* [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[PSRC]], [[WHILE_BODY_PREHEADER]] ], [ [[PSRC]], [[VECTOR_MEMCHECK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i32 [ [[IND_END3]], [[MIDDLE_BLOCK]] ], [ [[BLOCKSIZE]], [[WHILE_BODY_PREHEADER]] ], [ [[BLOCKSIZE]], [[VECTOR_MEMCHECK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL4:%.*]] = phi i8* [ [[IND_END5]], [[MIDDLE_BLOCK]] ], [ [[PDST]], [[WHILE_BODY_PREHEADER]] ], [ [[PDST]], [[VECTOR_MEMCHECK]] ] +; CHECK-NEXT: br label [[WHILE_BODY:%.*]] +; CHECK: while.body: +; CHECK-NEXT: [[PSRC_ADDR_022:%.*]] = phi i8* [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[BLKCNT_021:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[PDST_ADDR_020:%.*]] = phi i8* [ [[INCDEC_PTR13:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL4]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, i8* [[PSRC_ADDR_022]], i32 1 +; CHECK-NEXT: [[TMP8:%.*]] = load i8, i8* [[PSRC_ADDR_022]], align 1 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i8 [[TMP8]], 0 +; CHECK-NEXT: [[CMP5:%.*]] = icmp eq i8 [[TMP8]], -128 +; CHECK-NEXT: [[SUB:%.*]] = sub i8 0, [[TMP8]] +; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP5]], i8 127, i8 [[SUB]] +; CHECK-NEXT: [[COND11:%.*]] = select i1 [[CMP1]], i8 [[TMP8]], i8 [[COND]] +; CHECK-NEXT: [[INCDEC_PTR13]] = getelementptr inbounds i8, i8* [[PDST_ADDR_020]], i32 1 +; CHECK-NEXT: store i8 [[COND11]], i8* [[PDST_ADDR_020]], align 1 +; CHECK-NEXT: [[DEC]] = add i32 [[BLKCNT_021]], -1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0 +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END]], label [[WHILE_BODY]], [[LOOP7:!llvm.loop !.*]] +; CHECK: while.end: +; CHECK-NEXT: ret void +; +entry: + %cmp.not19 = icmp eq i32 %blockSize, 0 + br i1 %cmp.not19, label %while.end, label %while.body.preheader + +while.body.preheader: ; preds = %entry + br label %while.body + +while.body: ; preds = %while.body.preheader, %while.body + %pSrc.addr.022 = phi i8* [ %incdec.ptr, %while.body ], [ %pSrc, %while.body.preheader ] + %blkCnt.021 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.preheader ] + %pDst.addr.020 = phi i8* [ %incdec.ptr13, %while.body ], [ %pDst, %while.body.preheader ] + %incdec.ptr = getelementptr inbounds i8, i8* %pSrc.addr.022, i32 1 + %0 = load i8, i8* %pSrc.addr.022, align 1 + %cmp1 = icmp sgt i8 %0, 0 + %cmp5 = icmp eq i8 %0, -128 + %sub = sub i8 0, %0 + %cond = select i1 %cmp5, i8 127, i8 %sub + %cond11 = select i1 %cmp1, i8 %0, i8 %cond + %incdec.ptr13 = getelementptr inbounds i8, i8* %pDst.addr.020, i32 1 + store i8 %cond11, i8* %pDst.addr.020, align 1 + %dec = add i32 %blkCnt.021, -1 + %cmp.not = icmp eq i32 %dec, 0 + br i1 %cmp.not, label %while.end.loopexit, label %while.body + +while.end.loopexit: ; preds = %while.body + br label %while.end + +while.end: ; preds = %while.end.loopexit, %entry + ret void +} + +define void @arm_abs_q15(i16* nocapture readonly %pSrc, i16* nocapture %pDst, i32 %blockSize) #0 { +; CHECK-LABEL: @arm_abs_q15( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP_NOT20:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0 +; CHECK-NEXT: br i1 [[CMP_NOT20]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]] +; CHECK: while.body.preheader: +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[BLOCKSIZE]], 8 +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] +; CHECK: vector.memcheck: +; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i16, i16* [[PDST:%.*]], i32 [[BLOCKSIZE]] +; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i16, i16* [[PSRC:%.*]], i32 [[BLOCKSIZE]] +; CHECK-NEXT: [[BOUND0:%.*]] = icmp ugt i16* [[SCEVGEP4]], [[PDST]] +; CHECK-NEXT: [[BOUND1:%.*]] = icmp ugt i16* [[SCEVGEP]], [[PSRC]] +; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] +; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[BLOCKSIZE]], -8 +; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i16, i16* [[PSRC]], i32 [[N_VEC]] +; CHECK-NEXT: [[IND_END7:%.*]] = and i32 [[BLOCKSIZE]], 7 +; CHECK-NEXT: [[IND_END9:%.*]] = getelementptr i16, i16* [[PDST]], i32 [[N_VEC]] +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i16, i16* [[PSRC]], i32 [[INDEX]] +; CHECK-NEXT: [[NEXT_GEP10:%.*]] = getelementptr i16, i16* [[PDST]], i32 [[INDEX]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[NEXT_GEP]] to <8 x i16>* +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, <8 x i16>* [[TMP0]], align 2, !alias.scope !8 +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <8 x i16> [[WIDE_LOAD]], zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <8 x i16> [[WIDE_LOAD]], +; CHECK-NEXT: [[TMP3:%.*]] = sub <8 x i16> zeroinitializer, [[WIDE_LOAD]] +; CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP2]], <8 x i16> , <8 x i16> [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> [[WIDE_LOAD]], <8 x i16> [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = bitcast i16* [[NEXT_GEP10]] to <8 x i16>* +; CHECK-NEXT: store <8 x i16> [[TMP5]], <8 x i16>* [[TMP6]], align 2, !alias.scope !11, !noalias !8 +; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 8 +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP13:!llvm.loop !.*]] +; CHECK: middle.block: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N_VEC]], [[BLOCKSIZE]] +; CHECK-NEXT: br i1 [[CMP_N]], label [[WHILE_END]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16* [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[PSRC]], [[WHILE_BODY_PREHEADER]] ], [ [[PSRC]], [[VECTOR_MEMCHECK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL6:%.*]] = phi i32 [ [[IND_END7]], [[MIDDLE_BLOCK]] ], [ [[BLOCKSIZE]], [[WHILE_BODY_PREHEADER]] ], [ [[BLOCKSIZE]], [[VECTOR_MEMCHECK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL8:%.*]] = phi i16* [ [[IND_END9]], [[MIDDLE_BLOCK]] ], [ [[PDST]], [[WHILE_BODY_PREHEADER]] ], [ [[PDST]], [[VECTOR_MEMCHECK]] ] +; CHECK-NEXT: br label [[WHILE_BODY:%.*]] +; CHECK: while.body: +; CHECK-NEXT: [[PSRC_ADDR_023:%.*]] = phi i16* [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[BLKCNT_022:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL6]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[PDST_ADDR_021:%.*]] = phi i16* [ [[INCDEC_PTR13:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL8]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i16, i16* [[PSRC_ADDR_023]], i32 1 +; CHECK-NEXT: [[TMP8:%.*]] = load i16, i16* [[PSRC_ADDR_023]], align 2 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i16 [[TMP8]], 0 +; CHECK-NEXT: [[CMP5:%.*]] = icmp eq i16 [[TMP8]], -32768 +; CHECK-NEXT: [[SUB:%.*]] = sub i16 0, [[TMP8]] +; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP5]], i16 32767, i16 [[SUB]] +; CHECK-NEXT: [[COND11:%.*]] = select i1 [[CMP1]], i16 [[TMP8]], i16 [[COND]] +; CHECK-NEXT: [[INCDEC_PTR13]] = getelementptr inbounds i16, i16* [[PDST_ADDR_021]], i32 1 +; CHECK-NEXT: store i16 [[COND11]], i16* [[PDST_ADDR_021]], align 2 +; CHECK-NEXT: [[DEC]] = add i32 [[BLKCNT_022]], -1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0 +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END]], label [[WHILE_BODY]], [[LOOP14:!llvm.loop !.*]] +; CHECK: while.end: +; CHECK-NEXT: ret void +; +entry: + %cmp.not20 = icmp eq i32 %blockSize, 0 + br i1 %cmp.not20, label %while.end, label %while.body.preheader + +while.body.preheader: ; preds = %entry + br label %while.body + +while.body: ; preds = %while.body.preheader, %while.body + %pSrc.addr.023 = phi i16* [ %incdec.ptr, %while.body ], [ %pSrc, %while.body.preheader ] + %blkCnt.022 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.preheader ] + %pDst.addr.021 = phi i16* [ %incdec.ptr13, %while.body ], [ %pDst, %while.body.preheader ] + %incdec.ptr = getelementptr inbounds i16, i16* %pSrc.addr.023, i32 1 + %0 = load i16, i16* %pSrc.addr.023, align 2 + %cmp1 = icmp sgt i16 %0, 0 + %cmp5 = icmp eq i16 %0, -32768 + %sub = sub i16 0, %0 + %cond = select i1 %cmp5, i16 32767, i16 %sub + %cond11 = select i1 %cmp1, i16 %0, i16 %cond + %incdec.ptr13 = getelementptr inbounds i16, i16* %pDst.addr.021, i32 1 + store i16 %cond11, i16* %pDst.addr.021, align 2 + %dec = add i32 %blkCnt.022, -1 + %cmp.not = icmp eq i32 %dec, 0 + br i1 %cmp.not, label %while.end.loopexit, label %while.body + +while.end.loopexit: ; preds = %while.body + br label %while.end + +while.end: ; preds = %while.end.loopexit, %entry + ret void +} + +define void @arm_abs_q31(i32* nocapture readonly %pSrc, i32* nocapture %pDst, i32 %blockSize) #0 { +; CHECK-LABEL: @arm_abs_q31( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP_NOT14:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0 +; CHECK-NEXT: br i1 [[CMP_NOT14]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]] +; CHECK: while.body.preheader: +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[BLOCKSIZE]], 4 +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] +; CHECK: vector.memcheck: +; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i32, i32* [[PDST:%.*]], i32 [[BLOCKSIZE]] +; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr i32, i32* [[PSRC:%.*]], i32 [[BLOCKSIZE]] +; CHECK-NEXT: [[BOUND0:%.*]] = icmp ugt i32* [[SCEVGEP4]], [[PDST]] +; CHECK-NEXT: [[BOUND1:%.*]] = icmp ugt i32* [[SCEVGEP]], [[PSRC]] +; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] +; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[BLOCKSIZE]], -4 +; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i32, i32* [[PSRC]], i32 [[N_VEC]] +; CHECK-NEXT: [[IND_END7:%.*]] = and i32 [[BLOCKSIZE]], 3 +; CHECK-NEXT: [[IND_END9:%.*]] = getelementptr i32, i32* [[PDST]], i32 [[N_VEC]] +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i32, i32* [[PSRC]], i32 [[INDEX]] +; CHECK-NEXT: [[NEXT_GEP10:%.*]] = getelementptr i32, i32* [[PDST]], i32 [[INDEX]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[NEXT_GEP]] to <4 x i32>* +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4, !alias.scope !15 +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], +; CHECK-NEXT: [[TMP3:%.*]] = sub nsw <4 x i32> zeroinitializer, [[WIDE_LOAD]] +; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> , <4 x i32> [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[WIDE_LOAD]], <4 x i32> [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = bitcast i32* [[NEXT_GEP10]] to <4 x i32>* +; CHECK-NEXT: store <4 x i32> [[TMP5]], <4 x i32>* [[TMP6]], align 4, !alias.scope !18, !noalias !15 +; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4 +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP20:!llvm.loop !.*]] +; CHECK: middle.block: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N_VEC]], [[BLOCKSIZE]] +; CHECK-NEXT: br i1 [[CMP_N]], label [[WHILE_END]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32* [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[PSRC]], [[WHILE_BODY_PREHEADER]] ], [ [[PSRC]], [[VECTOR_MEMCHECK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL6:%.*]] = phi i32 [ [[IND_END7]], [[MIDDLE_BLOCK]] ], [ [[BLOCKSIZE]], [[WHILE_BODY_PREHEADER]] ], [ [[BLOCKSIZE]], [[VECTOR_MEMCHECK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL8:%.*]] = phi i32* [ [[IND_END9]], [[MIDDLE_BLOCK]] ], [ [[PDST]], [[WHILE_BODY_PREHEADER]] ], [ [[PDST]], [[VECTOR_MEMCHECK]] ] +; CHECK-NEXT: br label [[WHILE_BODY:%.*]] +; CHECK: while.body: +; CHECK-NEXT: [[PSRC_ADDR_017:%.*]] = phi i32* [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[BLKCNT_016:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL6]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[PDST_ADDR_015:%.*]] = phi i32* [ [[INCDEC_PTR7:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL8]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i32, i32* [[PSRC_ADDR_017]], i32 1 +; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[PSRC_ADDR_017]], align 4 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP8]], 0 +; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[TMP8]], -2147483648 +; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[TMP8]] +; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP2]], i32 2147483647, i32 [[SUB]] +; CHECK-NEXT: [[COND6:%.*]] = select i1 [[CMP1]], i32 [[TMP8]], i32 [[COND]] +; CHECK-NEXT: [[INCDEC_PTR7]] = getelementptr inbounds i32, i32* [[PDST_ADDR_015]], i32 1 +; CHECK-NEXT: store i32 [[COND6]], i32* [[PDST_ADDR_015]], align 4 +; CHECK-NEXT: [[DEC]] = add i32 [[BLKCNT_016]], -1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0 +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END]], label [[WHILE_BODY]], [[LOOP21:!llvm.loop !.*]] +; CHECK: while.end: +; CHECK-NEXT: ret void +; +entry: + %cmp.not14 = icmp eq i32 %blockSize, 0 + br i1 %cmp.not14, label %while.end, label %while.body.preheader + +while.body.preheader: ; preds = %entry + br label %while.body + +while.body: ; preds = %while.body.preheader, %while.body + %pSrc.addr.017 = phi i32* [ %incdec.ptr, %while.body ], [ %pSrc, %while.body.preheader ] + %blkCnt.016 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.preheader ] + %pDst.addr.015 = phi i32* [ %incdec.ptr7, %while.body ], [ %pDst, %while.body.preheader ] + %incdec.ptr = getelementptr inbounds i32, i32* %pSrc.addr.017, i32 1 + %0 = load i32, i32* %pSrc.addr.017, align 4 + %cmp1 = icmp sgt i32 %0, 0 + %cmp2 = icmp eq i32 %0, -2147483648 + %sub = sub nsw i32 0, %0 + %cond = select i1 %cmp2, i32 2147483647, i32 %sub + %cond6 = select i1 %cmp1, i32 %0, i32 %cond + %incdec.ptr7 = getelementptr inbounds i32, i32* %pDst.addr.015, i32 1 + store i32 %cond6, i32* %pDst.addr.015, align 4 + %dec = add i32 %blkCnt.016, -1 + %cmp.not = icmp eq i32 %dec, 0 + br i1 %cmp.not, label %while.end.loopexit, label %while.body + +while.end.loopexit: ; preds = %while.body + br label %while.end + +while.end: ; preds = %while.end.loopexit, %entry + ret void +} + +attributes #0 = { "target-features"="+mve" } diff --git a/llvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll b/llvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll index 90f0ae4cd865c..b37ce8476c60c 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll @@ -28,34 +28,29 @@ define void @cff_index_load_offsets(i1 %cond, i8 %x, i8* %p) #0 { ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* null, i64 [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT]] to <4 x i32> ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <4 x i32> [[TMP2]], -; CHECK-NEXT: [[TMP4:%.*]] = load i8, i8* [[P:%.*]], align 1, !tbaa !1 -; CHECK-NEXT: [[TMP5:%.*]] = load i8, i8* [[P]], align 1, !tbaa !1 -; CHECK-NEXT: [[TMP6:%.*]] = load i8, i8* [[P]], align 1, !tbaa !1 -; CHECK-NEXT: [[TMP7:%.*]] = load i8, i8* [[P]], align 1, !tbaa !1 -; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i8> undef, i8 [[TMP4]], i32 0 -; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i8> [[TMP8]], i8 [[TMP5]], i32 1 -; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i8> [[TMP9]], i8 [[TMP6]], i32 2 -; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i8> [[TMP10]], i8 [[TMP7]], i32 3 -; CHECK-NEXT: [[TMP12:%.*]] = zext <4 x i8> [[TMP11]] to <4 x i32> -; CHECK-NEXT: [[TMP13:%.*]] = shl nuw nsw <4 x i32> [[TMP12]], -; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP13]], [[TMP3]] -; CHECK-NEXT: [[TMP15:%.*]] = load i8, i8* undef, align 1, !tbaa !1 -; CHECK-NEXT: [[TMP16:%.*]] = load i8, i8* undef, align 1, !tbaa !1 -; CHECK-NEXT: [[TMP17:%.*]] = load i8, i8* undef, align 1, !tbaa !1 -; CHECK-NEXT: [[TMP18:%.*]] = load i8, i8* undef, align 1, !tbaa !1 -; CHECK-NEXT: [[TMP19:%.*]] = or <4 x i32> [[TMP14]], zeroinitializer -; CHECK-NEXT: [[TMP20:%.*]] = or <4 x i32> [[TMP19]], zeroinitializer -; CHECK-NEXT: [[TMP21:%.*]] = extractelement <4 x i32> [[TMP20]], i32 0 -; CHECK-NEXT: store i32 [[TMP21]], i32* undef, align 4, !tbaa !4 -; CHECK-NEXT: [[TMP22:%.*]] = extractelement <4 x i32> [[TMP20]], i32 1 -; CHECK-NEXT: store i32 [[TMP22]], i32* undef, align 4, !tbaa !4 -; CHECK-NEXT: [[TMP23:%.*]] = extractelement <4 x i32> [[TMP20]], i32 2 -; CHECK-NEXT: store i32 [[TMP23]], i32* undef, align 4, !tbaa !4 -; CHECK-NEXT: [[TMP24:%.*]] = extractelement <4 x i32> [[TMP20]], i32 3 -; CHECK-NEXT: store i32 [[TMP24]], i32* undef, align 4, !tbaa !4 +; CHECK-NEXT: [[TMP4:%.*]] = load i8, i8* [[P:%.*]], align 1, [[TBAA1:!tbaa !.*]] +; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i8> undef, i8 [[TMP4]], i32 0 +; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT1]], <4 x i8> undef, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[BROADCAST_SPLAT2]] to <4 x i32> +; CHECK-NEXT: [[TMP6:%.*]] = shl nuw nsw <4 x i32> [[TMP5]], +; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i32> [[TMP6]], [[TMP3]] +; CHECK-NEXT: [[TMP8:%.*]] = load i8, i8* undef, align 1, [[TBAA1]] +; CHECK-NEXT: [[TMP9:%.*]] = load i8, i8* undef, align 1, [[TBAA1]] +; CHECK-NEXT: [[TMP10:%.*]] = load i8, i8* undef, align 1, [[TBAA1]] +; CHECK-NEXT: [[TMP11:%.*]] = load i8, i8* undef, align 1, [[TBAA1]] +; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer +; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i32> [[TMP12]], zeroinitializer +; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i32> [[TMP13]], i32 0 +; CHECK-NEXT: store i32 [[TMP14]], i32* undef, align 4, [[TBAA4:!tbaa !.*]] +; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP13]], i32 1 +; CHECK-NEXT: store i32 [[TMP15]], i32* undef, align 4, [[TBAA4]] +; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i32> [[TMP13]], i32 2 +; CHECK-NEXT: store i32 [[TMP16]], i32* undef, align 4, [[TBAA4]] +; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i32> [[TMP13]], i32 3 +; CHECK-NEXT: store i32 [[TMP17]], i32* undef, align 4, [[TBAA4]] ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 -; CHECK-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], 0 -; CHECK-NEXT: br i1 [[TMP25]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !6 +; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 0 +; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP6:!llvm.loop !.*]] ; CHECK: middle.block: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1, 0 ; CHECK-NEXT: br i1 [[CMP_N]], label [[SW_EPILOG:%.*]], label [[SCALAR_PH]] @@ -66,19 +61,19 @@ define void @cff_index_load_offsets(i1 %cond, i8 %x, i8* %p) #0 { ; CHECK-NEXT: [[P_359:%.*]] = phi i8* [ [[ADD_PTR86:%.*]], [[FOR_BODY68]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] ; CHECK-NEXT: [[CONV70:%.*]] = zext i8 [[X]] to i32 ; CHECK-NEXT: [[SHL71:%.*]] = shl nuw i32 [[CONV70]], 24 -; CHECK-NEXT: [[TMP26:%.*]] = load i8, i8* [[P]], align 1, !tbaa !1 -; CHECK-NEXT: [[CONV73:%.*]] = zext i8 [[TMP26]] to i32 +; CHECK-NEXT: [[TMP19:%.*]] = load i8, i8* [[P]], align 1, [[TBAA1]] +; CHECK-NEXT: [[CONV73:%.*]] = zext i8 [[TMP19]] to i32 ; CHECK-NEXT: [[SHL74:%.*]] = shl nuw nsw i32 [[CONV73]], 16 ; CHECK-NEXT: [[OR75:%.*]] = or i32 [[SHL74]], [[SHL71]] -; CHECK-NEXT: [[TMP27:%.*]] = load i8, i8* undef, align 1, !tbaa !1 +; CHECK-NEXT: [[TMP20:%.*]] = load i8, i8* undef, align 1, [[TBAA1]] ; CHECK-NEXT: [[SHL78:%.*]] = shl nuw nsw i32 undef, 8 ; CHECK-NEXT: [[OR79:%.*]] = or i32 [[OR75]], [[SHL78]] ; CHECK-NEXT: [[CONV81:%.*]] = zext i8 undef to i32 ; CHECK-NEXT: [[OR83:%.*]] = or i32 [[OR79]], [[CONV81]] -; CHECK-NEXT: store i32 [[OR83]], i32* undef, align 4, !tbaa !4 +; CHECK-NEXT: store i32 [[OR83]], i32* undef, align 4, [[TBAA4]] ; CHECK-NEXT: [[ADD_PTR86]] = getelementptr inbounds i8, i8* [[P_359]], i64 4 ; CHECK-NEXT: [[CMP66:%.*]] = icmp ult i8* [[ADD_PTR86]], undef -; CHECK-NEXT: br i1 [[CMP66]], label [[FOR_BODY68]], label [[SW_EPILOG]], !llvm.loop !8 +; CHECK-NEXT: br i1 [[CMP66]], label [[FOR_BODY68]], label [[SW_EPILOG]], [[LOOP8:!llvm.loop !.*]] ; CHECK: sw.epilog: ; CHECK-NEXT: unreachable ; CHECK: Exit: diff --git a/llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll b/llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll index b55babaea3df7..f2dd89ea7d9ff 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll @@ -95,7 +95,7 @@ define void @foo1(float* noalias %in, float* noalias %out, i32* noalias %trigger ; FVW2-NEXT: entry: ; FVW2-NEXT: br label [[VECTOR_BODY:%.*]] ; FVW2: vector.body: -; FVW2-NEXT: [[INDEX6:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_3:%.*]], [[VECTOR_BODY]] ] +; FVW2-NEXT: [[INDEX6:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT_1:%.*]], [[VECTOR_BODY]] ] ; FVW2-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER:%.*]], i64 [[INDEX6]] ; FVW2-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to <2 x i32>* ; FVW2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, <2 x i32>* [[TMP1]], align 4 @@ -125,39 +125,9 @@ define void @foo1(float* noalias %in, float* noalias %out, i32* noalias %trigger ; FVW2-NEXT: [[TMP18:%.*]] = getelementptr inbounds float, float* [[OUT]], i64 [[INDEX_NEXT]] ; FVW2-NEXT: [[TMP19:%.*]] = bitcast float* [[TMP18]] to <2 x float>* ; FVW2-NEXT: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> [[TMP17]], <2 x float>* [[TMP19]], i32 4, <2 x i1> [[TMP12]]) -; FVW2-NEXT: [[INDEX_NEXT_1:%.*]] = or i64 [[INDEX6]], 4 -; FVW2-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDEX_NEXT_1]] -; FVW2-NEXT: [[TMP21:%.*]] = bitcast i32* [[TMP20]] to <2 x i32>* -; FVW2-NEXT: [[WIDE_LOAD_2:%.*]] = load <2 x i32>, <2 x i32>* [[TMP21]], align 4 -; FVW2-NEXT: [[TMP22:%.*]] = icmp sgt <2 x i32> [[WIDE_LOAD_2]], zeroinitializer -; FVW2-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, i32* [[INDEX]], i64 [[INDEX_NEXT_1]] -; FVW2-NEXT: [[TMP24:%.*]] = bitcast i32* [[TMP23]] to <2 x i32>* -; FVW2-NEXT: [[WIDE_MASKED_LOAD_2:%.*]] = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* nonnull [[TMP24]], i32 4, <2 x i1> [[TMP22]], <2 x i32> undef) -; FVW2-NEXT: [[TMP25:%.*]] = sext <2 x i32> [[WIDE_MASKED_LOAD_2]] to <2 x i64> -; FVW2-NEXT: [[TMP26:%.*]] = getelementptr inbounds float, float* [[IN]], <2 x i64> [[TMP25]] -; FVW2-NEXT: [[WIDE_MASKED_GATHER_2:%.*]] = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> [[TMP26]], i32 4, <2 x i1> [[TMP22]], <2 x float> undef) -; FVW2-NEXT: [[TMP27:%.*]] = fadd <2 x float> [[WIDE_MASKED_GATHER_2]], -; FVW2-NEXT: [[TMP28:%.*]] = getelementptr inbounds float, float* [[OUT]], i64 [[INDEX_NEXT_1]] -; FVW2-NEXT: [[TMP29:%.*]] = bitcast float* [[TMP28]] to <2 x float>* -; FVW2-NEXT: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> [[TMP27]], <2 x float>* [[TMP29]], i32 4, <2 x i1> [[TMP22]]) -; FVW2-NEXT: [[INDEX_NEXT_2:%.*]] = or i64 [[INDEX6]], 6 -; FVW2-NEXT: [[TMP30:%.*]] = getelementptr inbounds i32, i32* [[TRIGGER]], i64 [[INDEX_NEXT_2]] -; FVW2-NEXT: [[TMP31:%.*]] = bitcast i32* [[TMP30]] to <2 x i32>* -; FVW2-NEXT: [[WIDE_LOAD_3:%.*]] = load <2 x i32>, <2 x i32>* [[TMP31]], align 4 -; FVW2-NEXT: [[TMP32:%.*]] = icmp sgt <2 x i32> [[WIDE_LOAD_3]], zeroinitializer -; FVW2-NEXT: [[TMP33:%.*]] = getelementptr inbounds i32, i32* [[INDEX]], i64 [[INDEX_NEXT_2]] -; FVW2-NEXT: [[TMP34:%.*]] = bitcast i32* [[TMP33]] to <2 x i32>* -; FVW2-NEXT: [[WIDE_MASKED_LOAD_3:%.*]] = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* nonnull [[TMP34]], i32 4, <2 x i1> [[TMP32]], <2 x i32> undef) -; FVW2-NEXT: [[TMP35:%.*]] = sext <2 x i32> [[WIDE_MASKED_LOAD_3]] to <2 x i64> -; FVW2-NEXT: [[TMP36:%.*]] = getelementptr inbounds float, float* [[IN]], <2 x i64> [[TMP35]] -; FVW2-NEXT: [[WIDE_MASKED_GATHER_3:%.*]] = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> [[TMP36]], i32 4, <2 x i1> [[TMP32]], <2 x float> undef) -; FVW2-NEXT: [[TMP37:%.*]] = fadd <2 x float> [[WIDE_MASKED_GATHER_3]], -; FVW2-NEXT: [[TMP38:%.*]] = getelementptr inbounds float, float* [[OUT]], i64 [[INDEX_NEXT_2]] -; FVW2-NEXT: [[TMP39:%.*]] = bitcast float* [[TMP38]] to <2 x float>* -; FVW2-NEXT: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> [[TMP37]], <2 x float>* [[TMP39]], i32 4, <2 x i1> [[TMP32]]) -; FVW2-NEXT: [[INDEX_NEXT_3]] = add nuw nsw i64 [[INDEX6]], 8 -; FVW2-NEXT: [[TMP40:%.*]] = icmp eq i64 [[INDEX_NEXT_3]], 4096 -; FVW2-NEXT: br i1 [[TMP40]], label [[FOR_END:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]] +; FVW2-NEXT: [[INDEX_NEXT_1]] = add nuw nsw i64 [[INDEX6]], 4 +; FVW2-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT_1]], 4096 +; FVW2-NEXT: br i1 [[TMP20]], label [[FOR_END:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]] ; FVW2: for.end: ; FVW2-NEXT: ret void ; diff --git a/llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll b/llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll index 72e42ff40d9cb..a7e38c2115fb3 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll @@ -24,21 +24,9 @@ define i32 @uniform_load(i32* align(4) %addr) { ; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ADDR]], align 4 ; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ADDR]], align 4 ; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP12:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP13:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP18:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[ADDR]], align 4 ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 16 -; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 -; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 +; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]] ; CHECK: middle.block: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4097, 4096 ; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOPEXIT:%.*]], label [[SCALAR_PH]] @@ -52,7 +40,7 @@ define i32 @uniform_load(i32* align(4) %addr) { ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 4096 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOPEXIT]], label [[FOR_BODY]], [[LOOP2:!llvm.loop !.*]] ; CHECK: loopexit: -; CHECK-NEXT: [[LOAD_LCSSA:%.*]] = phi i32 [ [[LOAD]], [[FOR_BODY]] ], [ [[TMP19]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[LOAD_LCSSA:%.*]] = phi i32 [ [[LOAD]], [[FOR_BODY]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret i32 [[LOAD_LCSSA]] ; entry: @@ -77,63 +65,43 @@ define i32 @uniform_load2(i32* align(4) %addr) { ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP36:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP37:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP38:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP39:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP8:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 8 ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 12 ; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ADDR:%.*]], align 4 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> undef, i32 [[TMP4]], i32 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> undef, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ADDR]], align 4 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement <4 x i32> undef, i32 [[TMP5]], i32 0 +; CHECK-NEXT: [[BROADCAST_SPLAT5:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT4]], <4 x i32> undef, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ADDR]], align 4 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT6:%.*]] = insertelement <4 x i32> undef, i32 [[TMP6]], i32 0 +; CHECK-NEXT: [[BROADCAST_SPLAT7:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT6]], <4 x i32> undef, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> undef, i32 [[TMP4]], i32 0 -; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[TMP5]], i32 1 -; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[TMP6]], i32 2 -; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP7]], i32 3 -; CHECK-NEXT: [[TMP12:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP13:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i32> undef, i32 [[TMP12]], i32 0 -; CHECK-NEXT: [[TMP17:%.*]] = insertelement <4 x i32> [[TMP16]], i32 [[TMP13]], i32 1 -; CHECK-NEXT: [[TMP18:%.*]] = insertelement <4 x i32> [[TMP17]], i32 [[TMP14]], i32 2 -; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i32> [[TMP18]], i32 [[TMP15]], i32 3 -; CHECK-NEXT: [[TMP20:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP21:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP22:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP23:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP24:%.*]] = insertelement <4 x i32> undef, i32 [[TMP20]], i32 0 -; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x i32> [[TMP24]], i32 [[TMP21]], i32 1 -; CHECK-NEXT: [[TMP26:%.*]] = insertelement <4 x i32> [[TMP25]], i32 [[TMP22]], i32 2 -; CHECK-NEXT: [[TMP27:%.*]] = insertelement <4 x i32> [[TMP26]], i32 [[TMP23]], i32 3 -; CHECK-NEXT: [[TMP28:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP29:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP30:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP31:%.*]] = load i32, i32* [[ADDR]], align 4 -; CHECK-NEXT: [[TMP32:%.*]] = insertelement <4 x i32> undef, i32 [[TMP28]], i32 0 -; CHECK-NEXT: [[TMP33:%.*]] = insertelement <4 x i32> [[TMP32]], i32 [[TMP29]], i32 1 -; CHECK-NEXT: [[TMP34:%.*]] = insertelement <4 x i32> [[TMP33]], i32 [[TMP30]], i32 2 -; CHECK-NEXT: [[TMP35:%.*]] = insertelement <4 x i32> [[TMP34]], i32 [[TMP31]], i32 3 -; CHECK-NEXT: [[TMP36]] = add <4 x i32> [[VEC_PHI]], [[TMP11]] -; CHECK-NEXT: [[TMP37]] = add <4 x i32> [[VEC_PHI1]], [[TMP19]] -; CHECK-NEXT: [[TMP38]] = add <4 x i32> [[VEC_PHI2]], [[TMP27]] -; CHECK-NEXT: [[TMP39]] = add <4 x i32> [[VEC_PHI3]], [[TMP35]] +; CHECK-NEXT: [[BROADCAST_SPLATINSERT8:%.*]] = insertelement <4 x i32> undef, i32 [[TMP7]], i32 0 +; CHECK-NEXT: [[BROADCAST_SPLAT9:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT8]], <4 x i32> undef, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP8]] = add <4 x i32> [[VEC_PHI]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[TMP9]] = add <4 x i32> [[VEC_PHI1]], [[BROADCAST_SPLAT5]] +; CHECK-NEXT: [[TMP10]] = add <4 x i32> [[VEC_PHI2]], [[BROADCAST_SPLAT7]] +; CHECK-NEXT: [[TMP11]] = add <4 x i32> [[VEC_PHI3]], [[BROADCAST_SPLAT9]] ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 16 -; CHECK-NEXT: [[TMP40:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 -; CHECK-NEXT: br i1 [[TMP40]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP4:!llvm.loop !.*]] +; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 +; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP4:!llvm.loop !.*]] ; CHECK: middle.block: -; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP37]], [[TMP36]] -; CHECK-NEXT: [[BIN_RDX4:%.*]] = add <4 x i32> [[TMP38]], [[BIN_RDX]] -; CHECK-NEXT: [[BIN_RDX5:%.*]] = add <4 x i32> [[TMP39]], [[BIN_RDX4]] -; CHECK-NEXT: [[TMP41:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX5]]) +; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP9]], [[TMP8]] +; CHECK-NEXT: [[BIN_RDX10:%.*]] = add <4 x i32> [[TMP10]], [[BIN_RDX]] +; CHECK-NEXT: [[BIN_RDX11:%.*]] = add <4 x i32> [[TMP11]], [[BIN_RDX10]] +; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX11]]) ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4097, 4096 ; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOPEXIT:%.*]], label [[SCALAR_PH]] ; CHECK: scalar.ph: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] -; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP41]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP13]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[FOR_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] @@ -144,7 +112,7 @@ define i32 @uniform_load2(i32* align(4) %addr) { ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 4096 ; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOPEXIT]], label [[FOR_BODY]], [[LOOP5:!llvm.loop !.*]] ; CHECK: loopexit: -; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[FOR_BODY]] ], [ [[TMP41]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[FOR_BODY]] ], [ [[TMP13]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] ; entry: @@ -163,6 +131,68 @@ loopexit: ret i32 %accum.next } +define i32 @uniform_address(i32* align(4) %addr, i32 %byte_offset) { +; CHECK-LABEL: @uniform_address( +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 8 +; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 12 +; CHECK-NEXT: [[TMP4:%.*]] = udiv i32 [[BYTE_OFFSET:%.*]], 4 +; CHECK-NEXT: [[TMP5:%.*]] = udiv i32 [[BYTE_OFFSET]], 4 +; CHECK-NEXT: [[TMP6:%.*]] = udiv i32 [[BYTE_OFFSET]], 4 +; CHECK-NEXT: [[TMP7:%.*]] = udiv i32 [[BYTE_OFFSET]], 4 +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i32, i32* [[ADDR:%.*]], i32 [[TMP4]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i32, i32* [[ADDR]], i32 [[TMP5]] +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i32, i32* [[ADDR]], i32 [[TMP6]] +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, i32* [[ADDR]], i32 [[TMP7]] +; CHECK-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP8]], align 4 +; CHECK-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP9]], align 4 +; CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP10]], align 4 +; CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP11]], align 4 +; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 16 +; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 +; CHECK-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP6:!llvm.loop !.*]] +; CHECK: middle.block: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4097, 4096 +; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOPEXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.body: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[FOR_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[OFFSET:%.*]] = udiv i32 [[BYTE_OFFSET]], 4 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, i32* [[ADDR]], i32 [[OFFSET]] +; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32* [[GEP]], align 4 +; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 4096 +; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOPEXIT]], label [[FOR_BODY]], [[LOOP7:!llvm.loop !.*]] +; CHECK: loopexit: +; CHECK-NEXT: [[LOAD_LCSSA:%.*]] = phi i32 [ [[LOAD]], [[FOR_BODY]] ], [ [[TMP15]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: ret i32 [[LOAD_LCSSA]] +; +entry: + br label %for.body + +for.body: + %iv = phi i64 [ %iv.next, %for.body ], [ 0, %entry ] + %offset = udiv i32 %byte_offset, 4 + %gep = getelementptr i32, i32* %addr, i32 %offset + %load = load i32, i32* %gep + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond = icmp eq i64 %iv, 4096 + br i1 %exitcond, label %loopexit, label %for.body + +loopexit: + ret i32 %load +} + + define void @uniform_store_uniform_value(i32* align(4) %addr) { ; CHECK-LABEL: @uniform_store_uniform_value( @@ -194,7 +224,7 @@ define void @uniform_store_uniform_value(i32* align(4) %addr) { ; CHECK-NEXT: store i32 0, i32* [[ADDR]], align 4 ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 16 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 -; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP6:!llvm.loop !.*]] +; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP8:!llvm.loop !.*]] ; CHECK: middle.block: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4097, 4096 ; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOPEXIT:%.*]], label [[SCALAR_PH]] @@ -206,7 +236,7 @@ define void @uniform_store_uniform_value(i32* align(4) %addr) { ; CHECK-NEXT: store i32 0, i32* [[ADDR]], align 4 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 4096 -; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOPEXIT]], label [[FOR_BODY]], [[LOOP7:!llvm.loop !.*]] +; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOPEXIT]], label [[FOR_BODY]], [[LOOP9:!llvm.loop !.*]] ; CHECK: loopexit: ; CHECK-NEXT: ret void ; @@ -292,7 +322,7 @@ define void @uniform_store_varying_value(i32* align(4) %addr) { ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD2]], ; CHECK-NEXT: [[VEC_IND_NEXT9]] = add <4 x i32> [[STEP_ADD7]], ; CHECK-NEXT: [[TMP32:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 -; CHECK-NEXT: br i1 [[TMP32]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP8:!llvm.loop !.*]] +; CHECK-NEXT: br i1 [[TMP32]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP10:!llvm.loop !.*]] ; CHECK: middle.block: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4097, 4096 ; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOPEXIT:%.*]], label [[SCALAR_PH]] @@ -305,7 +335,7 @@ define void @uniform_store_varying_value(i32* align(4) %addr) { ; CHECK-NEXT: store i32 [[IV_I32]], i32* [[ADDR]], align 4 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 4096 -; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOPEXIT]], label [[FOR_BODY]], [[LOOP9:!llvm.loop !.*]] +; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOPEXIT]], label [[FOR_BODY]], [[LOOP11:!llvm.loop !.*]] ; CHECK: loopexit: ; CHECK-NEXT: ret void ; @@ -379,41 +409,29 @@ define void @uniform_copy(i32* %A, i32* %B) { ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 8 ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 12 -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !10 -; CHECK-NEXT: store i32 [[TMP4]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP5]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP6]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP7]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP8]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP9]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP10]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP11]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP12]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP13]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP14]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP15]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP16]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP17]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP18]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 -; CHECK-NEXT: store i32 [[TMP19]], i32* [[B]], align 4, !alias.scope !13, !noalias !10 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !12 +; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !12 +; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !12 +; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4, !alias.scope !12 +; CHECK-NEXT: store i32 [[TMP4]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP4]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP4]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP4]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP5]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP5]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP5]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP5]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP6]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP6]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP6]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP6]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP7]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP7]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP7]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 +; CHECK-NEXT: store i32 [[TMP7]], i32* [[B]], align 4, !alias.scope !15, !noalias !12 ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 16 -; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 -; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP15:!llvm.loop !.*]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 +; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP17:!llvm.loop !.*]] ; CHECK: middle.block: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4097, 4096 ; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOPEXIT:%.*]], label [[SCALAR_PH]] @@ -426,7 +444,7 @@ define void @uniform_copy(i32* %A, i32* %B) { ; CHECK-NEXT: store i32 [[LOAD]], i32* [[B]], align 4 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 ; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 4096 -; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOPEXIT]], label [[FOR_BODY]], [[LOOP16:!llvm.loop !.*]] +; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOPEXIT]], label [[FOR_BODY]], [[LOOP18:!llvm.loop !.*]] ; CHECK: loopexit: ; CHECK-NEXT: ret void ; @@ -522,7 +540,7 @@ define i32 @test_count_bits(i8* %test_base) { ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 8 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD]], ; CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4096 -; CHECK-NEXT: br i1 [[TMP54]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP17:!llvm.loop !.*]] +; CHECK-NEXT: br i1 [[TMP54]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP19:!llvm.loop !.*]] ; CHECK: middle.block: ; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP53]], [[TMP52]] ; CHECK-NEXT: [[TMP55:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]]) @@ -546,7 +564,7 @@ define i32 @test_count_bits(i8* %test_base) { ; CHECK-NEXT: [[VAL:%.*]] = zext i8 [[TEST]] to i32 ; CHECK-NEXT: [[ACCUM_NEXT]] = add i32 [[ACCUM]], [[VAL]] ; CHECK-NEXT: [[EXIT:%.*]] = icmp ugt i64 [[IV]], 4094 -; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], [[LOOP18:!llvm.loop !.*]] +; CHECK-NEXT: br i1 [[EXIT]], label [[LOOP_EXIT]], label [[LOOP]], [[LOOP20:!llvm.loop !.*]] ; CHECK: loop_exit: ; CHECK-NEXT: [[ACCUM_NEXT_LCSSA:%.*]] = phi i32 [ [[ACCUM_NEXT]], [[LOOP]] ], [ [[TMP55]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret i32 [[ACCUM_NEXT_LCSSA]] diff --git a/llvm/test/Transforms/LoopVectorize/dead_instructions.ll b/llvm/test/Transforms/LoopVectorize/dead_instructions.ll index fb929ee4ebda8..06215aac9b5ce 100644 --- a/llvm/test/Transforms/LoopVectorize/dead_instructions.ll +++ b/llvm/test/Transforms/LoopVectorize/dead_instructions.ll @@ -40,3 +40,32 @@ for.end: %tmp3 = phi i64 [ %tmp2, %for.body ] ret i64 %tmp3 } + + +; CHECK-LABEL: @pr47390 +; +; This test ensures that the primary induction is not considered dead when +; acting as the 'add' of another induction, and otherwise feeding only its own +; 'add' (recognized earlier as 'dead'), when the tail of the loop is folded by +; masking. Such masking uses the primary induction. +; +; CHECK: vector.body: +; +define void @pr47390(i32 *%a) { +entry: + br label %loop + +exit: + ret void + +loop: + %primary = phi i32 [ 0, %entry ], [ %primary_add, %loop ] + %use_primary = phi i32 [ -1, %entry ], [ %primary, %loop ] + %secondary = phi i32 [ 1, %entry ], [ %secondary_add, %loop ] + %primary_add = add i32 %primary, 1 + %secondary_add = add i32 %secondary, 1 + %gep = getelementptr inbounds i32, i32* %a, i32 %secondary + %load = load i32, i32* %gep, align 8 + %cmp = icmp eq i32 %secondary, 5 + br i1 %cmp, label %exit, label %loop +} diff --git a/llvm/test/Transforms/LoopVectorize/float-reduction.ll b/llvm/test/Transforms/LoopVectorize/float-reduction.ll index f3b95d0ead7d8..dec854845800a 100644 --- a/llvm/test/Transforms/LoopVectorize/float-reduction.ll +++ b/llvm/test/Transforms/LoopVectorize/float-reduction.ll @@ -44,3 +44,47 @@ for.body: ; preds = %for.body, %entry for.end: ; preds = %for.body ret float %sub } + +;CHECK-LABEL: @foodiv( +;CHECK: fdiv fast <4 x float> +;CHECK: ret +define float @foodiv(float* nocapture %A, i32* nocapture %n) nounwind uwtable readonly ssp { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %sum.04 = phi float [ 1.000000e+00, %entry ], [ %sub, %for.body ] + %arrayidx = getelementptr inbounds float, float* %A, i64 %indvars.iv + %0 = load float, float* %arrayidx, align 4 + %sub = fdiv fast float %sum.04, %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 200 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret float %sub +} + +;CHECK-LABEL: @foonodiv( +;CHECK-NOT: fdiv fast <4 x float> +;CHECK: ret +define float @foonodiv(float* nocapture %A, i32* nocapture %n) nounwind uwtable readonly ssp { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %sum.04 = phi float [ 1.000000e+00, %entry ], [ %sub, %for.body ] + %arrayidx = getelementptr inbounds float, float* %A, i64 %indvars.iv + %0 = load float, float* %arrayidx, align 4 + %sub = fdiv fast float %0, %sum.04 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 200 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret float %sub +} diff --git a/llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll b/llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll index e8e80d19bc759..dae6a63e93628 100644 --- a/llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll +++ b/llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll @@ -38,7 +38,7 @@ for.end: ; CHECK: N0 [label = ; CHECK-NEXT: "loop:\n" + ; CHECK-NEXT: "WIDEN-INDUCTION %iv = phi 0, %iv.next\l" + -; CHECK-NEXT: "WIDEN\l"" %cond0 = icmp %iv, 13\l" + +; CHECK-NEXT: "WIDEN ir<%cond0> = icmp ir<%iv>, ir<13>\l" + ; CHECK-NEXT: "WIDEN-SELECT ir<%s> = select ir<%cond0>, ir<10>, ir<20>\l" ; CHECK-NEXT: ] define void @test() { diff --git a/llvm/test/Transforms/LoopVectorize/multiple-strides-vectorization.ll b/llvm/test/Transforms/LoopVectorize/multiple-strides-vectorization.ll index 7ee8b64591983..aa1c429185ce6 100644 --- a/llvm/test/Transforms/LoopVectorize/multiple-strides-vectorization.ll +++ b/llvm/test/Transforms/LoopVectorize/multiple-strides-vectorization.ll @@ -68,24 +68,19 @@ define void @Test(%struct.s* nocapture %obj, i64 %z) #0 { ; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32* [[TMP4]] to <4 x i32>* ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP5]], align 4, !alias.scope !0 ; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP1]], align 4, !alias.scope !3 -; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[TMP1]], align 4, !alias.scope !3 -; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP1]], align 4, !alias.scope !3 -; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP1]], align 4, !alias.scope !3 -; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> undef, i32 [[TMP6]], i32 0 -; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP7]], i32 1 -; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i32 2 -; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP9]], i32 3 -; CHECK-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[TMP13]], [[WIDE_LOAD]] -; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.s* [[OBJ]], i64 0, i32 2, i64 [[I]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[TMP15]], i32 0 -; CHECK-NEXT: [[TMP17:%.*]] = bitcast i32* [[TMP16]] to <4 x i32>* -; CHECK-NEXT: [[WIDE_LOAD12:%.*]] = load <4 x i32>, <4 x i32>* [[TMP17]], align 4, !alias.scope !5, !noalias !7 -; CHECK-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[TMP14]], [[WIDE_LOAD12]] -; CHECK-NEXT: [[TMP19:%.*]] = bitcast i32* [[TMP16]] to <4 x i32>* -; CHECK-NEXT: store <4 x i32> [[TMP18]], <4 x i32>* [[TMP19]], align 4, !alias.scope !5, !noalias !7 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> undef, i32 [[TMP6]], i32 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> undef, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> [[BROADCAST_SPLAT]], [[WIDE_LOAD]] +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.s* [[OBJ]], i64 0, i32 2, i64 [[I]], i64 [[TMP2]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i32 0 +; CHECK-NEXT: [[TMP10:%.*]] = bitcast i32* [[TMP9]] to <4 x i32>* +; CHECK-NEXT: [[WIDE_LOAD12:%.*]] = load <4 x i32>, <4 x i32>* [[TMP10]], align 4, !alias.scope !5, !noalias !7 +; CHECK-NEXT: [[TMP11:%.*]] = add nsw <4 x i32> [[TMP7]], [[WIDE_LOAD12]] +; CHECK-NEXT: [[TMP12:%.*]] = bitcast i32* [[TMP9]] to <4 x i32>* +; CHECK-NEXT: store <4 x i32> [[TMP11]], <4 x i32>* [[TMP12]], align 4, !alias.scope !5, !noalias !7 ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 -; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; CHECK-NEXT: br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !8 +; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP8:!llvm.loop !.*]] ; CHECK: middle.block: ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[Z]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label [[DOTOUTER]], label [[SCALAR_PH]] @@ -100,17 +95,17 @@ define void @Test(%struct.s* nocapture %obj, i64 %z) #0 { ; CHECK-NEXT: br i1 [[EXITCOND_OUTER]], label [[DOTEXIT:%.*]], label [[DOTOUTER_PREHEADER]] ; CHECK: .inner: ; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[J_NEXT:%.*]], [[DOTINNER]] ] -; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.s* [[OBJ]], i64 0, i32 0, i64 [[J]] -; CHECK-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 -; CHECK-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP1]], align 4 -; CHECK-NEXT: [[TMP24:%.*]] = add nsw i32 [[TMP23]], [[TMP22]] -; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.s* [[OBJ]], i64 0, i32 2, i64 [[I]], i64 [[J]] -; CHECK-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 -; CHECK-NEXT: [[TMP27:%.*]] = add nsw i32 [[TMP24]], [[TMP26]] -; CHECK-NEXT: store i32 [[TMP27]], i32* [[TMP25]] +; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.s* [[OBJ]], i64 0, i32 0, i64 [[J]] +; CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4 +; CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP1]], align 4 +; CHECK-NEXT: [[TMP17:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] +; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.s* [[OBJ]], i64 0, i32 2, i64 [[I]], i64 [[J]] +; CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 +; CHECK-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP17]], [[TMP19]] +; CHECK-NEXT: store i32 [[TMP20]], i32* [[TMP18]], align 4 ; CHECK-NEXT: [[J_NEXT]] = add nuw nsw i64 [[J]], 1 ; CHECK-NEXT: [[EXITCOND_INNER:%.*]] = icmp eq i64 [[J_NEXT]], [[Z]] -; CHECK-NEXT: br i1 [[EXITCOND_INNER]], label [[DOTOUTER]], label [[DOTINNER]], !llvm.loop !10 +; CHECK-NEXT: br i1 [[EXITCOND_INNER]], label [[DOTOUTER]], label [[DOTINNER]], [[LOOP10:!llvm.loop !.*]] ; br label %.outer.preheader diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll index a77922490bbfd..21d236ac76b2a 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts -; RUN: opt -loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s +; RUN: opt -loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -disable-output %s 2>&1 | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" @@ -42,9 +42,9 @@ define void @print_widen_gep_and_select(i64 %n, float* noalias %y, float* noalia ; CHECK-NEXT: "WIDEN-INDUCTION %iv = phi %iv.next, 0\l" + ; CHECK-NEXT: "WIDEN-GEP Inv[Var] ir<%arrayidx> = getelementptr ir<%y>, ir<%iv>\l" + ; CHECK-NEXT: "WIDEN ir<%lv> = load ir<%arrayidx>\l" + -; CHECK-NEXT: "WIDEN\l"" %cmp = icmp %arrayidx, %z\l" + +; CHECK-NEXT: "WIDEN ir<%cmp> = icmp ir<%arrayidx>, ir<%z>\l" + ; CHECK-NEXT: "WIDEN-SELECT ir<%sel> = select ir<%cmp>, ir<1.000000e+01>, ir<2.000000e+01>\l" + -; CHECK-NEXT: "WIDEN\l"" %add = fadd %lv, %sel\l" + +; CHECK-NEXT: "WIDEN ir<%add> = fadd ir<%lv>, ir<%sel>\l" + ; CHECK-NEXT: "CLONE %arrayidx2 = getelementptr %x, %iv\l" + ; CHECK-NEXT: "WIDEN store ir<%arrayidx2>, ir<%add>\l" ; CHECK-NEXT: ] @@ -70,4 +70,31 @@ for.end: ; preds = %for.body, %entry ret void } +define float @print_reduction(i64 %n, float* noalias %y) { +; CHECK: N0 [label = +; CHECK-NEXT: "for.body:\n" + +; CHECK-NEXT: "WIDEN-INDUCTION %iv = phi %iv.next, 0\l" + +; CHECK-NEXT: "WIDEN-PHI %red = phi %red.next, 0.000000e+00\l" + +; CHECK-NEXT: "CLONE %arrayidx = getelementptr %y, %iv\l" + +; CHECK-NEXT: "WIDEN ir<%lv> = load ir<%arrayidx>\l" + +; CHECK-NEXT: "REDUCE ir<%red.next> = ir<%red> + reduce.fadd (ir<%lv>)\l" +; CHECK-NEXT: ] + +entry: + br label %for.body + +for.body: ; preds = %entry, %for.body + %iv = phi i64 [ %iv.next, %for.body ], [ 0, %entry ] + %red = phi float [ %red.next, %for.body ], [ 0.0, %entry ] + %arrayidx = getelementptr inbounds float, float* %y, i64 %iv + %lv = load float, float* %arrayidx, align 4 + %red.next = fadd fast float %lv, %red + %iv.next = add i64 %iv, 1 + %exitcond = icmp eq i64 %iv.next, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret float %red.next +} + declare float @llvm.sqrt.f32(float) nounwind readnone diff --git a/llvm/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll b/llvm/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll index 17867dc52db85..361341ffba9a0 100644 --- a/llvm/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll +++ b/llvm/test/Transforms/MemCpyOpt/2008-02-24-MultipleUseofSRet.ll @@ -8,7 +8,7 @@ target triple = "i386-pc-linux-gnu" %0 = type { x86_fp80, x86_fp80 } -define internal fastcc void @initialize(%0* noalias nocapture sret %agg.result) nounwind { +define internal fastcc void @initialize(%0* noalias nocapture sret(%0) %agg.result) nounwind { ; CHECK-LABEL: @initialize( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[AGG_RESULT_03:%.*]] = getelementptr [[TMP0:%.*]], %0* [[AGG_RESULT:%.*]], i32 0, i32 0 @@ -33,7 +33,7 @@ define fastcc void @badly_optimized() nounwind { ; CHECK-NEXT: [[Z:%.*]] = alloca [[TMP0:%.*]], align 8 ; CHECK-NEXT: [[TMP:%.*]] = alloca [[TMP0]], align 8 ; CHECK-NEXT: [[MEMTMP:%.*]] = alloca [[TMP0]], align 8 -; CHECK-NEXT: call fastcc void @initialize(%0* noalias sret [[Z]]) +; CHECK-NEXT: call fastcc void @initialize(%0* noalias sret(%0) [[Z]]) ; CHECK-NEXT: [[TMP1:%.*]] = bitcast %0* [[TMP]] to i8* ; CHECK-NEXT: [[MEMTMP2:%.*]] = bitcast %0* [[MEMTMP]] to i8* ; CHECK-NEXT: [[Z3:%.*]] = bitcast %0* [[Z]] to i8* @@ -45,7 +45,7 @@ entry: %z = alloca %0 %tmp = alloca %0 %memtmp = alloca %0, align 8 - call fastcc void @initialize(%0* noalias sret %memtmp) + call fastcc void @initialize(%0* noalias sret(%0) %memtmp) %tmp1 = bitcast %0* %tmp to i8* %memtmp2 = bitcast %0* %memtmp to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %tmp1, i8* align 8 %memtmp2, i32 24, i1 false) diff --git a/llvm/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll b/llvm/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll index f12d77709d0e2..3835b749b834c 100644 --- a/llvm/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll +++ b/llvm/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll @@ -11,13 +11,13 @@ target triple = "i386-apple-darwin10" %struct1 = type { i32, i32 } %struct2 = type { %struct1, i8* } -declare void @bar(%struct1* nocapture sret %agg.result) nounwind +declare void @bar(%struct1* nocapture sret(%struct1) %agg.result) nounwind define i32 @foo() nounwind { ; CHECK-LABEL: @foo( ; CHECK-NEXT: [[X:%.*]] = alloca [[STRUCT1:%.*]], align 8 ; CHECK-NEXT: [[Y:%.*]] = alloca [[STRUCT2:%.*]], align 8 -; CHECK-NEXT: call void @bar(%struct1* sret [[X]]) [[ATTR0:#.*]] +; CHECK-NEXT: call void @bar(%struct1* sret(%struct1) [[X]]) [[ATTR0:#.*]] ; CHECK-NEXT: [[GEPN1:%.*]] = getelementptr inbounds [[STRUCT2]], %struct2* [[Y]], i32 0, i32 0, i32 0 ; CHECK-NEXT: store i32 0, i32* [[GEPN1]], align 8 ; CHECK-NEXT: [[GEPN2:%.*]] = getelementptr inbounds [[STRUCT2]], %struct2* [[Y]], i32 0, i32 0, i32 1 @@ -32,7 +32,7 @@ define i32 @foo() nounwind { ; %x = alloca %struct1, align 8 %y = alloca %struct2, align 8 - call void @bar(%struct1* sret %x) nounwind + call void @bar(%struct1* sret(%struct1) %x) nounwind %gepn1 = getelementptr inbounds %struct2, %struct2* %y, i32 0, i32 0, i32 0 store i32 0, i32* %gepn1, align 8 diff --git a/llvm/test/Transforms/MemCpyOpt/crash.ll b/llvm/test/Transforms/MemCpyOpt/crash.ll index f70f10429f848..73635891c6831 100644 --- a/llvm/test/Transforms/MemCpyOpt/crash.ll +++ b/llvm/test/Transforms/MemCpyOpt/crash.ll @@ -83,3 +83,16 @@ define void @test2(i32 %cmd) nounwind { call void @llvm.memcpy.p0i8.p0i8.i64(i8* null, i8* undef, i64 20, i1 false) nounwind ret void } + +; https://llvm.org/PR48075 + +@g = external global i16, align 1 + +define void @inttoptr_constexpr_crash(<1 x i16*>* %p) { +; CHECK-LABEL: @inttoptr_constexpr_crash( +; CHECK-NEXT: store <1 x i16*> inttoptr (<1 x i16> bitcast (<2 x i8> to <1 x i16>) to <1 x i16*>), <1 x i16*>* [[P:%.*]], align 1 +; CHECK-NEXT: ret void +; + store <1 x i16*> inttoptr (<1 x i16> bitcast (<2 x i8> to <1 x i16>) to <1 x i16*>), <1 x i16*>* %p, align 1 + ret void +} diff --git a/llvm/test/Transforms/MemCpyOpt/loadstore-sret.ll b/llvm/test/Transforms/MemCpyOpt/loadstore-sret.ll index a7ff65fa0523d..155958aeb3eeb 100644 --- a/llvm/test/Transforms/MemCpyOpt/loadstore-sret.ll +++ b/llvm/test/Transforms/MemCpyOpt/loadstore-sret.ll @@ -8,18 +8,18 @@ target triple = "x86_64-apple-darwin10.0.0" %"class.std::auto_ptr" = type { i32* } -define void @_Z3foov(%"class.std::auto_ptr"* noalias nocapture sret %agg.result) ssp { +define void @_Z3foov(%"class.std::auto_ptr"* noalias nocapture sret(%"class.std::auto_ptr") %agg.result) ssp { ; CHECK-LABEL: @_Z3foov( ; CHECK-NEXT: _ZNSt8auto_ptrIiED1Ev.exit: ; CHECK-NEXT: [[TEMP_LVALUE:%.*]] = alloca %"class.std::auto_ptr", align 8 -; CHECK-NEXT: call void @_Z3barv(%"class.std::auto_ptr"* sret [[AGG_RESULT:%.*]]) +; CHECK-NEXT: call void @_Z3barv(%"class.std::auto_ptr"* sret(%"class.std::auto_ptr") [[AGG_RESULT:%.*]]) ; CHECK-NEXT: [[TMP_I_I:%.*]] = getelementptr inbounds %"class.std::auto_ptr", %"class.std::auto_ptr"* [[TEMP_LVALUE]], i64 0, i32 0 ; CHECK-NEXT: [[TMP_I_I4:%.*]] = getelementptr inbounds %"class.std::auto_ptr", %"class.std::auto_ptr"* [[AGG_RESULT]], i64 0, i32 0 ; CHECK-NEXT: ret void ; _ZNSt8auto_ptrIiED1Ev.exit: %temp.lvalue = alloca %"class.std::auto_ptr", align 8 - call void @_Z3barv(%"class.std::auto_ptr"* sret %temp.lvalue) + call void @_Z3barv(%"class.std::auto_ptr"* sret(%"class.std::auto_ptr") %temp.lvalue) %tmp.i.i = getelementptr inbounds %"class.std::auto_ptr", %"class.std::auto_ptr"* %temp.lvalue, i64 0, i32 0 %tmp2.i.i = load i32*, i32** %tmp.i.i, align 8 %tmp.i.i4 = getelementptr inbounds %"class.std::auto_ptr", %"class.std::auto_ptr"* %agg.result, i64 0, i32 0 @@ -27,4 +27,4 @@ _ZNSt8auto_ptrIiED1Ev.exit: ret void } -declare void @_Z3barv(%"class.std::auto_ptr"* nocapture sret) nounwind +declare void @_Z3barv(%"class.std::auto_ptr"* nocapture sret(%"class.std::auto_ptr")) nounwind diff --git a/llvm/test/Transforms/MemCpyOpt/memcpy-to-memset-with-lifetimes.ll b/llvm/test/Transforms/MemCpyOpt/memcpy-to-memset-with-lifetimes.ll index 9ce335d07842b..1594138d8333c 100644 --- a/llvm/test/Transforms/MemCpyOpt/memcpy-to-memset-with-lifetimes.ll +++ b/llvm/test/Transforms/MemCpyOpt/memcpy-to-memset-with-lifetimes.ll @@ -5,7 +5,7 @@ target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define void @foo([8 x i64]* noalias nocapture sret dereferenceable(64) %sret) { +define void @foo([8 x i64]* noalias nocapture sret([8 x i64]) dereferenceable(64) %sret) { ; CHECK-LABEL: @foo( ; CHECK-NEXT: entry-block: ; CHECK-NEXT: [[SRET1:%.*]] = bitcast [8 x i64]* [[SRET:%.*]] to i8* @@ -24,7 +24,7 @@ entry-block: } -define void @bar([8 x i64]* noalias nocapture sret dereferenceable(64) %sret, [8 x i64]* noalias nocapture dereferenceable(64) %out) { +define void @bar([8 x i64]* noalias nocapture sret([8 x i64]) dereferenceable(64) %sret, [8 x i64]* noalias nocapture dereferenceable(64) %out) { ; CHECK-LABEL: @bar( ; CHECK-NEXT: entry-block: ; CHECK-NEXT: [[A:%.*]] = alloca [8 x i64], align 8 diff --git a/llvm/test/Transforms/MemCpyOpt/memcpy-undef.ll b/llvm/test/Transforms/MemCpyOpt/memcpy-undef.ll index 64a7d8df96838..360ccde6c8911 100644 --- a/llvm/test/Transforms/MemCpyOpt/memcpy-undef.ll +++ b/llvm/test/Transforms/MemCpyOpt/memcpy-undef.ll @@ -31,7 +31,7 @@ define i32 @test1(%struct.foo* nocapture %foobie) nounwind noinline ssp uwtable } ; Check that the memcpy is removed. -define void @test2(i8* sret noalias nocapture %out, i8* %in) nounwind noinline ssp uwtable { +define void @test2(i8* sret(i8) noalias nocapture %out, i8* %in) nounwind noinline ssp uwtable { ; CHECK-LABEL: @test2( ; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* [[IN:%.*]]) ; CHECK-NEXT: ret void @@ -42,7 +42,7 @@ define void @test2(i8* sret noalias nocapture %out, i8* %in) nounwind noinline s } ; Check that the memcpy is not removed. -define void @test3(i8* sret noalias nocapture %out, i8* %in) nounwind noinline ssp uwtable { +define void @test3(i8* sret(i8) noalias nocapture %out, i8* %in) nounwind noinline ssp uwtable { ; CHECK-LABEL: @test3( ; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[IN:%.*]]) ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[OUT:%.*]], i8* [[IN]], i64 8, i1 false) diff --git a/llvm/test/Transforms/MemCpyOpt/memcpy.ll b/llvm/test/Transforms/MemCpyOpt/memcpy.ll index a2dd706d3237b..bb6a4fcc12576 100644 --- a/llvm/test/Transforms/MemCpyOpt/memcpy.ll +++ b/llvm/test/Transforms/MemCpyOpt/memcpy.ll @@ -8,13 +8,13 @@ target triple = "i686-apple-darwin9" %0 = type { x86_fp80, x86_fp80 } %1 = type { i32, i32 } -define void @test1(%0* sret %agg.result, x86_fp80 %z.0, x86_fp80 %z.1) nounwind { +define void @test1(%0* sret(%0) %agg.result, x86_fp80 %z.0, x86_fp80 %z.1) nounwind { ; CHECK-LABEL: @test1( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP2:%.*]] = alloca [[TMP0:%.*]], align 16 ; CHECK-NEXT: [[MEMTMP:%.*]] = alloca [[TMP0]], align 16 ; CHECK-NEXT: [[TMP5:%.*]] = fsub x86_fp80 0xK80000000000000000000, [[Z_1:%.*]] -; CHECK-NEXT: call void @ccoshl(%0* sret [[TMP2]], x86_fp80 [[TMP5]], x86_fp80 [[Z_0:%.*]]) [[ATTR0:#.*]] +; CHECK-NEXT: call void @ccoshl(%0* sret(%0) [[TMP2]], x86_fp80 [[TMP5]], x86_fp80 [[Z_0:%.*]]) [[ATTR0:#.*]] ; CHECK-NEXT: [[TMP219:%.*]] = bitcast %0* [[TMP2]] to i8* ; CHECK-NEXT: [[MEMTMP20:%.*]] = bitcast %0* [[MEMTMP]] to i8* ; CHECK-NEXT: [[AGG_RESULT21:%.*]] = bitcast %0* [[AGG_RESULT:%.*]] to i8* @@ -25,7 +25,7 @@ entry: %tmp2 = alloca %0 %memtmp = alloca %0, align 16 %tmp5 = fsub x86_fp80 0xK80000000000000000000, %z.1 - call void @ccoshl(%0* sret %memtmp, x86_fp80 %tmp5, x86_fp80 %z.0) nounwind + call void @ccoshl(%0* sret(%0) %memtmp, x86_fp80 %tmp5, x86_fp80 %z.0) nounwind %tmp219 = bitcast %0* %tmp2 to i8* %memtmp20 = bitcast %0* %memtmp to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 16 %tmp219, i8* align 16 %memtmp20, i32 32, i1 false) @@ -38,7 +38,7 @@ entry: } -declare void @ccoshl(%0* nocapture sret, x86_fp80, x86_fp80) nounwind +declare void @ccoshl(%0* nocapture sret(%0), x86_fp80, x86_fp80) nounwind ; The intermediate alloca and one of the memcpy's should be eliminated, the @@ -76,7 +76,7 @@ define void @test2_memcpy(i8* noalias %P, i8* noalias %Q) nounwind { @x = external global %0 -define void @test3(%0* noalias sret %agg.result) nounwind { +define void @test3(%0* noalias sret(%0) %agg.result) nounwind { ; CHECK-LABEL: @test3( ; CHECK-NEXT: [[X_0:%.*]] = alloca [[TMP0:%.*]], align 16 ; CHECK-NEXT: [[X_01:%.*]] = bitcast %0* [[X_0]] to i8* @@ -97,13 +97,13 @@ define void @test3(%0* noalias sret %agg.result) nounwind { ; PR8644 define void @test4(i8 *%P) { ; CHECK-LABEL: @test4( -; CHECK-NEXT: call void @test4a(i8* byval align 1 [[P:%.*]]) +; CHECK-NEXT: call void @test4a(i8* byval(i8) align 1 [[P:%.*]]) ; CHECK-NEXT: ret void ; %A = alloca %1 %a = bitcast %1* %A to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %a, i8* align 4 %P, i64 8, i1 false) - call void @test4a(i8* align 1 byval %a) + call void @test4a(i8* align 1 byval(i8) %a) ret void } @@ -113,13 +113,13 @@ define void @test4_addrspace(i8 addrspace(1)* %P) { ; CHECK-NEXT: [[A1:%.*]] = alloca [[TMP1:%.*]], align 8 ; CHECK-NEXT: [[A2:%.*]] = bitcast %1* [[A1]] to i8* ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p1i8.i64(i8* align 4 [[A2]], i8 addrspace(1)* align 4 [[P:%.*]], i64 8, i1 false) -; CHECK-NEXT: call void @test4a(i8* byval align 1 [[A2]]) +; CHECK-NEXT: call void @test4a(i8* byval(i8) align 1 [[A2]]) ; CHECK-NEXT: ret void ; %a1 = alloca %1 %a2 = bitcast %1* %a1 to i8* call void @llvm.memcpy.p0i8.p1i8.i64(i8* align 4 %a2, i8 addrspace(1)* align 4 %P, i64 8, i1 false) - call void @test4a(i8* align 1 byval %a2) + call void @test4a(i8* align 1 byval(i8) %a2) ret void } @@ -129,14 +129,14 @@ define void @test4_write_between(i8 *%P) { ; CHECK-NEXT: [[A2:%.*]] = bitcast %1* [[A1]] to i8* ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[A2]], i8* align 4 [[P:%.*]], i64 8, i1 false) ; CHECK-NEXT: store i8 0, i8* [[A2]], align 1 -; CHECK-NEXT: call void @test4a(i8* byval align 1 [[A2]]) +; CHECK-NEXT: call void @test4a(i8* byval(i8) align 1 [[A2]]) ; CHECK-NEXT: ret void ; %a1 = alloca %1 %a2 = bitcast %1* %a1 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %a2, i8* align 4 %P, i64 8, i1 false) store i8 0, i8* %a2 - call void @test4a(i8* align 1 byval %a2) + call void @test4a(i8* align 1 byval(i8) %a2) ret void } @@ -146,14 +146,14 @@ define i8 @test4_read_between(i8 *%P) { ; CHECK-NEXT: [[A2:%.*]] = bitcast %1* [[A1]] to i8* ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[A2]], i8* align 4 [[P:%.*]], i64 8, i1 false) ; CHECK-NEXT: [[X:%.*]] = load i8, i8* [[A2]], align 1 -; CHECK-NEXT: call void @test4a(i8* byval align 1 [[A2]]) +; CHECK-NEXT: call void @test4a(i8* byval(i8) align 1 [[A2]]) ; CHECK-NEXT: ret i8 [[X]] ; %a1 = alloca %1 %a2 = bitcast %1* %a1 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %a2, i8* align 4 %P, i64 8, i1 false) %x = load i8, i8* %a2 - call void @test4a(i8* align 1 byval %a2) + call void @test4a(i8* align 1 byval(i8) %a2) ret i8 %x } @@ -164,7 +164,7 @@ define void @test4_non_local(i8 *%P, i1 %c) { ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[A2]], i8* align 4 [[P:%.*]], i64 8, i1 false) ; CHECK-NEXT: br i1 [[C:%.*]], label [[CALL:%.*]], label [[EXIT:%.*]] ; CHECK: call: -; CHECK-NEXT: call void @test4a(i8* byval align 1 [[A2]]) +; CHECK-NEXT: call void @test4a(i8* byval(i8) align 1 [[A2]]) ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: ; CHECK-NEXT: ret void @@ -175,14 +175,14 @@ define void @test4_non_local(i8 *%P, i1 %c) { br i1 %c, label %call, label %exit call: - call void @test4a(i8* align 1 byval %a2) + call void @test4a(i8* align 1 byval(i8) %a2) br label %exit exit: ret void } -declare void @test4a(i8* align 1 byval) +declare void @test4a(i8* align 1 byval(i8)) declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind declare void @llvm.memcpy.p0i8.p1i8.i64(i8* nocapture, i8 addrspace(1)* nocapture, i64, i1) nounwind declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(1)* nocapture, i64, i1) nounwind @@ -191,7 +191,7 @@ declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace @sS = external global %struct.S, align 16 -declare void @test5a(%struct.S* align 16 byval) nounwind ssp +declare void @test5a(%struct.S* align 16 byval(%struct.S)) nounwind ssp ; rdar://8713376 - This memcpy can't be eliminated. @@ -203,7 +203,7 @@ define i32 @test5(i32 %x) nounwind ssp { ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP]], i8* align 16 bitcast (%struct.S* @sS to i8*), i64 32, i1 false) ; CHECK-NEXT: [[A:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[Y]], i64 0, i32 1, i64 0 ; CHECK-NEXT: store i8 4, i8* [[A]], align 1 -; CHECK-NEXT: call void @test5a(%struct.S* byval align 16 [[Y]]) +; CHECK-NEXT: call void @test5a(%struct.S* byval(%struct.S) align 16 [[Y]]) ; CHECK-NEXT: ret i32 0 ; entry: @@ -212,7 +212,7 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %tmp, i8* align 16 bitcast (%struct.S* @sS to i8*), i64 32, i1 false) %a = getelementptr %struct.S, %struct.S* %y, i64 0, i32 1, i64 0 store i8 4, i8* %a - call void @test5a(%struct.S* align 16 byval %y) + call void @test5a(%struct.S* align 16 byval(%struct.S) %y) ret i32 0 } @@ -230,10 +230,10 @@ define void @test6(i8 *%P) { ; isn't itself 8 byte aligned. %struct.p = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } -define i32 @test7(%struct.p* nocapture align 8 byval %q) nounwind ssp { +define i32 @test7(%struct.p* nocapture align 8 byval(%struct.p) %q) nounwind ssp { ; CHECK-LABEL: @test7( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL:%.*]] = call i32 @g(%struct.p* byval align 8 [[Q:%.*]]) [[ATTR0]] +; CHECK-NEXT: [[CALL:%.*]] = call i32 @g(%struct.p* byval(%struct.p) align 8 [[Q:%.*]]) [[ATTR0]] ; CHECK-NEXT: ret i32 [[CALL]] ; entry: @@ -241,11 +241,11 @@ entry: %tmp = bitcast %struct.p* %agg.tmp to i8* %tmp1 = bitcast %struct.p* %q to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %tmp, i8* align 4 %tmp1, i64 48, i1 false) - %call = call i32 @g(%struct.p* align 8 byval %agg.tmp) nounwind + %call = call i32 @g(%struct.p* align 8 byval(%struct.p) %agg.tmp) nounwind ret i32 %call } -declare i32 @g(%struct.p* align 8 byval) +declare i32 @g(%struct.p* align 8 byval(%struct.p)) declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind @@ -276,7 +276,7 @@ define void @test9_addrspacecast() nounwind ssp uwtable { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[B:%.*]] = alloca [[STRUCT_BIG:%.*]], align 4 ; CHECK-NEXT: [[TMP:%.*]] = alloca [[STRUCT_BIG]], align 4 -; CHECK-NEXT: call void @f1(%struct.big* sret [[B]]) +; CHECK-NEXT: call void @f1(%struct.big* sret(%struct.big) [[B]]) ; CHECK-NEXT: [[TMP0:%.*]] = addrspacecast %struct.big* [[B]] to i8 addrspace(1)* ; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast %struct.big* [[TMP]] to i8 addrspace(1)* ; CHECK-NEXT: call void @f2(%struct.big* [[B]]) @@ -285,7 +285,7 @@ define void @test9_addrspacecast() nounwind ssp uwtable { entry: %b = alloca %struct.big, align 4 %tmp = alloca %struct.big, align 4 - call void @f1(%struct.big* sret %tmp) + call void @f1(%struct.big* sret(%struct.big) %tmp) %0 = addrspacecast %struct.big* %b to i8 addrspace(1)* %1 = addrspacecast %struct.big* %tmp to i8 addrspace(1)* call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* align 4 %0, i8 addrspace(1)* align 4 %1, i64 200, i1 false) @@ -298,7 +298,7 @@ define void @test9() nounwind ssp uwtable { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[B:%.*]] = alloca [[STRUCT_BIG:%.*]], align 4 ; CHECK-NEXT: [[TMP:%.*]] = alloca [[STRUCT_BIG]], align 4 -; CHECK-NEXT: call void @f1(%struct.big* sret [[B]]) +; CHECK-NEXT: call void @f1(%struct.big* sret(%struct.big) [[B]]) ; CHECK-NEXT: [[TMP0:%.*]] = bitcast %struct.big* [[B]] to i8* ; CHECK-NEXT: [[TMP1:%.*]] = bitcast %struct.big* [[TMP]] to i8* ; CHECK-NEXT: call void @f2(%struct.big* [[B]]) @@ -307,7 +307,7 @@ define void @test9() nounwind ssp uwtable { entry: %b = alloca %struct.big, align 4 %tmp = alloca %struct.big, align 4 - call void @f1(%struct.big* sret %tmp) + call void @f1(%struct.big* sret(%struct.big) %tmp) %0 = bitcast %struct.big* %b to i8* %1 = bitcast %struct.big* %tmp to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %0, i8* align 4 %1, i64 200, i1 false) @@ -322,7 +322,7 @@ entry: %opaque = type opaque declare void @foo(i32* noalias nocapture) -define void @test10(%opaque* noalias nocapture sret %x, i32 %y) { +define void @test10(%opaque* noalias nocapture sret(%opaque) %x, i32 %y) { ; CHECK-LABEL: @test10( ; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 ; CHECK-NEXT: store i32 [[Y:%.*]], i32* [[A]], align 4 @@ -359,7 +359,7 @@ define void @test11([20 x i32] addrspace(1)* nocapture dereferenceable(80) %P) { declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind declare void @llvm.memcpy.p1i8.p0i8.i64(i8 addrspace(1)* nocapture, i8* nocapture, i64, i1) nounwind -declare void @f1(%struct.big* nocapture sret) +declare void @f1(%struct.big* nocapture sret(%struct.big)) declare void @f2(%struct.big*) ; CHECK: attributes [[ATTR0]] = { nounwind } diff --git a/llvm/test/Transforms/MemCpyOpt/smaller.ll b/llvm/test/Transforms/MemCpyOpt/smaller.ll index cd5fa957d8b4f..19ececdd815a8 100644 --- a/llvm/test/Transforms/MemCpyOpt/smaller.ll +++ b/llvm/test/Transforms/MemCpyOpt/smaller.ll @@ -15,7 +15,7 @@ target datalayout = "e-p:32:32:32" @.str = private constant [11 x i8] c"0123456789\00" @cell = external global %struct.s -declare void @check(%struct.s* byval %p) nounwind +declare void @check(%struct.s* byval(%struct.s) %p) nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind define void @foo() nounwind { @@ -26,7 +26,7 @@ define void @foo() nounwind { ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 getelementptr inbounds (%struct.s, %struct.s* @cell, i32 0, i32 0, i32 0), i8* align 1 getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i32 11, i1 false) ; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.s* [[AGG_TMP]], i32 0, i32 0, i32 0 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP]], i8* align 4 getelementptr inbounds (%struct.s, %struct.s* @cell, i32 0, i32 0, i32 0), i32 16, i1 false) -; CHECK-NEXT: call void @check(%struct.s* byval [[AGG_TMP]]) +; CHECK-NEXT: call void @check(%struct.s* byval(%struct.s) [[AGG_TMP]]) ; CHECK-NEXT: ret void ; entry: @@ -35,6 +35,6 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 getelementptr inbounds (%struct.s, %struct.s* @cell, i32 0, i32 0, i32 0), i8* align 1 getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i32 11, i1 false) %tmp = getelementptr inbounds %struct.s, %struct.s* %agg.tmp, i32 0, i32 0, i32 0 call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %tmp, i8* align 4 getelementptr inbounds (%struct.s, %struct.s* @cell, i32 0, i32 0, i32 0), i32 16, i1 false) - call void @check(%struct.s* byval %agg.tmp) + call void @check(%struct.s* byval(%struct.s) %agg.tmp) ret void } diff --git a/llvm/test/Transforms/MemCpyOpt/sret.ll b/llvm/test/Transforms/MemCpyOpt/sret.ll index c509364d04873..12608edb84a7c 100644 --- a/llvm/test/Transforms/MemCpyOpt/sret.ll +++ b/llvm/test/Transforms/MemCpyOpt/sret.ll @@ -7,7 +7,7 @@ target triple = "i686-apple-darwin9" %0 = type { x86_fp80, x86_fp80 } -define void @ccosl(%0* noalias sret %agg.result, %0* byval align 8 %z) nounwind { +define void @ccosl(%0* noalias sret(%0) %agg.result, %0* byval(%0) align 8 %z) nounwind { ; CHECK-LABEL: @ccosl( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[IZ:%.*]] = alloca [[TMP0:%.*]], align 16 @@ -21,7 +21,7 @@ define void @ccosl(%0* noalias sret %agg.result, %0* byval align 8 %z) nounwind ; CHECK-NEXT: [[TMP8:%.*]] = load x86_fp80, x86_fp80* [[TMP7]], align 16 ; CHECK-NEXT: store x86_fp80 [[TMP3]], x86_fp80* [[REAL]], align 16 ; CHECK-NEXT: store x86_fp80 [[TMP8]], x86_fp80* [[TMP4]], align 16 -; CHECK-NEXT: call void @ccoshl(%0* noalias sret [[AGG_RESULT:%.*]], %0* byval align 8 [[IZ]]) [[ATTR0:#.*]] +; CHECK-NEXT: call void @ccoshl(%0* noalias sret(%0) [[AGG_RESULT:%.*]], %0* byval(%0) align 8 [[IZ]]) [[ATTR0:#.*]] ; CHECK-NEXT: [[MEMTMP14:%.*]] = bitcast %0* [[MEMTMP]] to i8* ; CHECK-NEXT: [[AGG_RESULT15:%.*]] = bitcast %0* [[AGG_RESULT]] to i8* ; CHECK-NEXT: ret void @@ -38,13 +38,13 @@ entry: %tmp8 = load x86_fp80, x86_fp80* %tmp7, align 16 store x86_fp80 %tmp3, x86_fp80* %real, align 16 store x86_fp80 %tmp8, x86_fp80* %tmp4, align 16 - call void @ccoshl(%0* noalias sret %memtmp, %0* byval align 8 %iz) nounwind + call void @ccoshl(%0* noalias sret(%0) %memtmp, %0* byval(%0) align 8 %iz) nounwind %memtmp14 = bitcast %0* %memtmp to i8* %agg.result15 = bitcast %0* %agg.result to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 16 %agg.result15, i8* align 16 %memtmp14, i32 32, i1 false) ret void } -declare void @ccoshl(%0* noalias nocapture sret, %0* byval) nounwind +declare void @ccoshl(%0* noalias nocapture sret(%0), %0* byval(%0)) nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind diff --git a/llvm/test/Transforms/MergeFunc/apply_function_attributes.ll b/llvm/test/Transforms/MergeFunc/apply_function_attributes.ll index e9ede4518206a..2ed0e1da79c91 100644 --- a/llvm/test/Transforms/MergeFunc/apply_function_attributes.ll +++ b/llvm/test/Transforms/MergeFunc/apply_function_attributes.ll @@ -6,7 +6,7 @@ %Di = type <{ i32 }> %Si = type <{ i32 }> -define void @B(%Opaque_type* sret %a, %S2i* %b, i32* %xp, i32* %yp) { +define void @B(%Opaque_type* sret(%Opaque_type) %a, %S2i* %b, i32* %xp, i32* %yp) { %x = load i32, i32* %xp %y = load i32, i32* %yp %sum = add i32 %x, %y @@ -15,7 +15,7 @@ define void @B(%Opaque_type* sret %a, %S2i* %b, i32* %xp, i32* %yp) { ret void } -define void @C(%Opaque_type* sret %a, %S2i* %b, i32* %xp, i32* %yp) { +define void @C(%Opaque_type* sret(%Opaque_type) %a, %S2i* %b, i32* %xp, i32* %yp) { %x = load i32, i32* %xp %y = load i32, i32* %yp %sum = add i32 %x, %y @@ -24,7 +24,7 @@ define void @C(%Opaque_type* sret %a, %S2i* %b, i32* %xp, i32* %yp) { ret void } -define void @A(%Opaque_type* sret %a, %D2i* %b, i32* %xp, i32* %yp) { +define void @A(%Opaque_type* sret(%Opaque_type) %a, %D2i* %b, i32* %xp, i32* %yp) { %x = load i32, i32* %xp %y = load i32, i32* %yp %sum = add i32 %x, %y @@ -35,13 +35,13 @@ define void @A(%Opaque_type* sret %a, %D2i* %b, i32* %xp, i32* %yp) { ; Make sure we transfer the parameter attributes to the call site. ; CHECK-LABEL: define void @C(%Opaque_type* sret -; CHECK: tail call void bitcast (void (%Opaque_type*, %D2i*, i32*, i32*)* @A to void (%Opaque_type*, %S2i*, i32*, i32*)*)(%Opaque_type* sret %0, %S2i* %1, i32* %2, i32* %3) +; CHECK: tail call void bitcast (void (%Opaque_type*, %D2i*, i32*, i32*)* @A to void (%Opaque_type*, %S2i*, i32*, i32*)*)(%Opaque_type* sret(%Opaque_type) %0, %S2i* %1, i32* %2, i32* %3) ; CHECK: ret void ; Make sure we transfer the parameter attributes to the call site. ; CHECK-LABEL: define void @B(%Opaque_type* sret ; CHECK: %5 = bitcast -; CHECK: tail call void @A(%Opaque_type* sret %0, %D2i* %5, i32* %2, i32* %3) +; CHECK: tail call void @A(%Opaque_type* sret(%Opaque_type) %0, %D2i* %5, i32* %2, i32* %3) ; CHECK: ret void diff --git a/llvm/test/Transforms/MergeFunc/mismatching-attr-crash.ll b/llvm/test/Transforms/MergeFunc/mismatching-attr-crash.ll index e3f81c5776fce..65d71d110fe24 100644 --- a/llvm/test/Transforms/MergeFunc/mismatching-attr-crash.ll +++ b/llvm/test/Transforms/MergeFunc/mismatching-attr-crash.ll @@ -2,10 +2,10 @@ ; CHECK-LABEL: define void @foo ; CHECK: call void %bc -define void @foo(i8* byval %a0, i8* swiftself %a4) { +define void @foo(i8* byval(i8) %a0, i8* swiftself %a4) { entry: %bc = bitcast i8* %a0 to void (i8*, i8*)* - call void %bc(i8* byval %a0, i8* swiftself %a4) + call void %bc(i8* byval(i8) %a0, i8* swiftself %a4) ret void } diff --git a/llvm/test/Transforms/MergeICmps/X86/pr41917.ll b/llvm/test/Transforms/MergeICmps/X86/pr41917.ll index a697b462259f2..22cba94c582cf 100644 --- a/llvm/test/Transforms/MergeICmps/X86/pr41917.ll +++ b/llvm/test/Transforms/MergeICmps/X86/pr41917.ll @@ -7,7 +7,7 @@ target triple = "i386-pc-windows-msvc19.11.0" %class.a = type { i32, i32, i32, i32, i32 } ; Function Attrs: nounwind optsize -define dso_local zeroext i1 @pr41917(%class.a* byval nocapture readonly align 4 %g, %class.a* byval nocapture readonly align 4 %p2) local_unnamed_addr #0 { +define dso_local zeroext i1 @pr41917(%class.a* byval(%class.a) nocapture readonly align 4 %g, %class.a* byval(%class.a) nocapture readonly align 4 %p2) local_unnamed_addr #0 { ; CHECK-LABEL: @pr41917( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[CALL:%.*]] = tail call zeroext i1 @f2() #3 diff --git a/llvm/test/Transforms/MetaRenamer/metarenamer.ll b/llvm/test/Transforms/MetaRenamer/metarenamer.ll index 19e49b1892e8f..041dac86f886d 100644 --- a/llvm/test/Transforms/MetaRenamer/metarenamer.ll +++ b/llvm/test/Transforms/MetaRenamer/metarenamer.ll @@ -23,7 +23,7 @@ define i32 @func_3_xxx() nounwind uwtable ssp { ret i32 3 } -define void @func_4_xxx(%struct.foo_xxx* sret %agg.result) nounwind uwtable ssp { +define void @func_4_xxx(%struct.foo_xxx* sret(%struct.foo_xxx) %agg.result) nounwind uwtable ssp { %1 = alloca %struct.foo_xxx, align 8 %2 = getelementptr inbounds %struct.foo_xxx, %struct.foo_xxx* %1, i32 0, i32 0 store i32 1, i32* %2, align 4 diff --git a/llvm/test/Transforms/NewGVN/2009-03-10-PREOnVoid.ll b/llvm/test/Transforms/NewGVN/2009-03-10-PREOnVoid.ll index 701556e57eb2c..8b7f7b8c4eec0 100644 --- a/llvm/test/Transforms/NewGVN/2009-03-10-PREOnVoid.ll +++ b/llvm/test/Transforms/NewGVN/2009-03-10-PREOnVoid.ll @@ -34,7 +34,7 @@ target triple = "i386-pc-linux-gnu" declare fastcc void @_ZNSt10_Select1stISt4pairIKPvS1_EEC1Ev() nounwind readnone -define fastcc void @_ZNSt8_Rb_treeIPvSt4pairIKS0_S0_ESt10_Select1stIS3_ESt4lessIS0_ESaIS3_EE16_M_insert_uniqueERKS3_(%"struct.std::pair > > >,bool>"* noalias nocapture sret %agg.result, %"struct.std::_Rb_tree > >,std::_Select1st > > >,std::less,std::allocator > > > >"* %this, %"struct.std::pair"* %__v) nounwind { +define fastcc void @_ZNSt8_Rb_treeIPvSt4pairIKS0_S0_ESt10_Select1stIS3_ESt4lessIS0_ESaIS3_EE16_M_insert_uniqueERKS3_(%"struct.std::pair > > >,bool>"* noalias nocapture sret(%"struct.std::pair > > >,bool>") %agg.result, %"struct.std::_Rb_tree > >,std::_Select1st > > >,std::less,std::allocator > > > >"* %this, %"struct.std::pair"* %__v) nounwind { entry: br i1 false, label %bb7, label %bb diff --git a/llvm/test/Transforms/NewGVN/pr17852.ll b/llvm/test/Transforms/NewGVN/pr17852.ll index a7907bd2f6d45..7d888e95a0d3c 100644 --- a/llvm/test/Transforms/NewGVN/pr17852.ll +++ b/llvm/test/Transforms/NewGVN/pr17852.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -basic-aa -newgvn target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" %struct.S0 = type { [2 x i8], [2 x i8], [4 x i8], [2 x i8], i32, i32, i32, i32 } -define void @fn1(%struct.S0* byval align 8 %p1) { +define void @fn1(%struct.S0* byval(%struct.S0) align 8 %p1) { br label %for.cond for.cond: ; preds = %1, %0 br label %for.end diff --git a/llvm/test/Transforms/ObjCARC/path-overflow.ll b/llvm/test/Transforms/ObjCARC/path-overflow.ll index 227d6e5b047af..e84cfc3154065 100644 --- a/llvm/test/Transforms/ObjCARC/path-overflow.ll +++ b/llvm/test/Transforms/ObjCARC/path-overflow.ll @@ -1567,7 +1567,7 @@ invoke.cont512: ; preds = %invoke.cont509 br i1 undef, label %msgSend.null-receiver, label %msgSend.call msgSend.call: ; preds = %invoke.cont512 - invoke void bitcast (void (i8*, i8*, ...)* @llvm.objc.msgSend_stret to void (%struct.CGPoint*, i8*, i8*)*)(%struct.CGPoint* sret undef, i8* undef, i8* undef) + invoke void bitcast (void (i8*, i8*, ...)* @llvm.objc.msgSend_stret to void (%struct.CGPoint*, i8*, i8*)*)(%struct.CGPoint* sret(%struct.CGPoint) undef, i8* undef, i8* undef) to label %msgSend.cont unwind label %lpad514 msgSend.null-receiver: ; preds = %invoke.cont512 diff --git a/llvm/test/Transforms/OpenMP/parallel_deletion_cg_update.ll b/llvm/test/Transforms/OpenMP/parallel_deletion_cg_update.ll index 168d5bf46b3c8..848af21e18dbf 100644 --- a/llvm/test/Transforms/OpenMP/parallel_deletion_cg_update.ll +++ b/llvm/test/Transforms/OpenMP/parallel_deletion_cg_update.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -instcombine -attributor-cgscc -print-callgraph -disable-output -verify 2>&1 | FileCheck %s +; RUN: opt < %s -instcombine -attributor-cgscc -print-callgraph -disable-output -verify 2>&1 -enable-new-pm=0 | FileCheck %s ; CHECK: Call graph node <><<{{.*}}>> #uses=0 ; CHECK: CS calls function 'dead_fork_call' diff --git a/llvm/test/Transforms/OpenMP/parallel_region_merging.ll b/llvm/test/Transforms/OpenMP/parallel_region_merging.ll index 188f21d44b1de..56e6edf9883e0 100644 --- a/llvm/test/Transforms/OpenMP/parallel_region_merging.ll +++ b/llvm/test/Transforms/OpenMP/parallel_region_merging.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs -; RUN: opt -S -passes='attributor,cgscc(openmpopt)' -openmp-opt-enable-merging < %s | FileCheck %s +; RUN: opt -S -attributor -openmpopt -openmp-opt-enable-merging < %s -enable-new-pm=0 | FileCheck %s +; RUN: opt -S -passes='attributor,cgscc(openmpopt)' -openmp-opt-enable-merging < %s | FileCheck %s target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/OpenMP/parallel_region_merging_legacy_pm.ll b/llvm/test/Transforms/OpenMP/parallel_region_merging_legacy_pm.ll deleted file mode 100644 index 5da416b8c61ab..0000000000000 --- a/llvm/test/Transforms/OpenMP/parallel_region_merging_legacy_pm.ll +++ /dev/null @@ -1,412 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs -; RUN: opt -S -attributor -openmpopt -openmp-opt-enable-merging < %s | FileCheck %s - -target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" - -%struct.ident_t = type { i32, i32, i32, i32, i8* } - -@0 = private unnamed_addr constant [23 x i8] c";unknown;unknown;0;0;;\00", align 1 -@1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, i8* getelementptr inbounds ([23 x i8], [23 x i8]* @0, i32 0, i32 0) }, align 8 - -; void merge_all() { -; int a = 1; -; #pragma omp parallel -; { -; a = 2; -; } -; #pragma omp parallel -; { -; a = 3; -; } -; } -; -; Merge all parallel regions. -define dso_local void @merge_all() local_unnamed_addr { - %1 = alloca i32, align 4 - %2 = bitcast i32* %1 to i8* - store i32 1, i32* %1, align 4 - %3 = call i32 @__kmpc_global_thread_num(%struct.ident_t* nonnull @1) - call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @1, i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @merge_all..omp_par to void (i32*, i32*, ...)*), i32* nonnull %1) - %4 = call i32 @__kmpc_global_thread_num(%struct.ident_t* nonnull @1) - call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @1, i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @merge_all..omp_par.1 to void (i32*, i32*, ...)*), i32* nonnull %1) - ret void -} - -define internal void @merge_all..omp_par.1(i32* noalias nocapture readnone %0, i32* noalias nocapture readnone %1, i32* nocapture %2) { - store i32 3, i32* %2, align 4 - ret void -} - -define internal void @merge_all..omp_par(i32* noalias nocapture readnone %0, i32* noalias nocapture readnone %1, i32* nocapture %2) { - store i32 2, i32* %2, align 4 - ret void -} - - -declare i32 @__kmpc_global_thread_num(%struct.ident_t*) local_unnamed_addr - -declare !callback !1 void @__kmpc_fork_call(%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) local_unnamed_addr - -; void merge_none() { -; int a = 1; -; #pragma omp parallel -; { -; a = 2; -; } -; a = 3; -; #pragma omp parallel -; { -; a = 4; -; } -; } -; -; Does not merge parallel regions, in-between store -; instruction is unsafe to execute in parallel. -define dso_local void @merge_none() local_unnamed_addr { - %1 = alloca i32, align 4 - %2 = bitcast i32* %1 to i8* - store i32 1, i32* %1, align 4 - %3 = call i32 @__kmpc_global_thread_num(%struct.ident_t* nonnull @1) - call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @1, i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @merge_none..omp_par to void (i32*, i32*, ...)*), i32* nonnull %1) - store i32 3, i32* %1, align 4 - %4 = call i32 @__kmpc_global_thread_num(%struct.ident_t* nonnull @1) - call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @1, i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @merge_none..omp_par.2 to void (i32*, i32*, ...)*), i32* nonnull %1) - ret void -} - -define internal void @merge_none..omp_par.2(i32* noalias nocapture readnone %0, i32* noalias nocapture readnone %1, i32* nocapture %2) { - store i32 4, i32* %2, align 4 - ret void -} - -define internal void @merge_none..omp_par(i32* noalias nocapture readnone %0, i32* noalias nocapture readnone %1, i32* nocapture %2) { - store i32 2, i32* %2, align 4 - ret void -} - -; void merge_some() { -; int a = 1; -; #pragma omp parallel -; { -; a = 2; -; } -; a = 3; -; #pragma omp parallel -; { -; a = 4; -; } -; #pragma omp parallel -; { -; a = 5; -; } -; } -; -; Do not merge first parallel region, due to the -; unsafe store, but merge the two next parallel -; regions. -define dso_local void @merge_some() local_unnamed_addr { - %1 = alloca i32, align 4 - %2 = bitcast i32* %1 to i8* - store i32 1, i32* %1, align 4 - %3 = call i32 @__kmpc_global_thread_num(%struct.ident_t* nonnull @1) - call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @1, i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @merge_some..omp_par to void (i32*, i32*, ...)*), i32* nonnull %1) - store i32 3, i32* %1, align 4 - %4 = call i32 @__kmpc_global_thread_num(%struct.ident_t* nonnull @1) - call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @1, i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @merge_some..omp_par.3 to void (i32*, i32*, ...)*), i32* nonnull %1) - %5 = call i32 @__kmpc_global_thread_num(%struct.ident_t* nonnull @1) - call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @1, i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @merge_some..omp_par.4 to void (i32*, i32*, ...)*), i32* nonnull %1) - ret void -} - -define internal void @merge_some..omp_par.4(i32* noalias nocapture readnone %0, i32* noalias nocapture readnone %1, i32* nocapture %2) { - store i32 5, i32* %2, align 4 - ret void -} - -define internal void @merge_some..omp_par.3(i32* noalias nocapture readnone %0, i32* noalias nocapture readnone %1, i32* nocapture %2) { - store i32 4, i32* %2, align 4 - ret void -} - -define internal void @merge_some..omp_par(i32* noalias nocapture readnone %0, i32* noalias nocapture readnone %1, i32* nocapture %2) { - store i32 2, i32* %2, align 4 - ret void -} - -; void merge_cancellable_regions(int cancel1, int cancel2) -; { -; #pragma omp parallel -; { -; if(cancel1) { -; #pragma omp cancel parallel -; } -; } -; -; #pragma omp parallel -; { -; if (cancel2) { -; #pragma omp cancel parallel -; } -; } -; } -; -; Merge correctly cancellable regions. -define dso_local void @merge_cancellable_regions(i32 %0, i32 %1) local_unnamed_addr { - %3 = alloca i32, align 4 - %4 = alloca i32, align 4 - store i32 %0, i32* %3, align 4 - store i32 %1, i32* %4, align 4 - %5 = call i32 @__kmpc_global_thread_num(%struct.ident_t* nonnull @1) - call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @1, i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @merge_cancellable_regions..omp_par to void (i32*, i32*, ...)*), i32* nonnull %3) - %6 = call i32 @__kmpc_global_thread_num(%struct.ident_t* nonnull @1) - call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @1, i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @merge_cancellable_regions..omp_par.5 to void (i32*, i32*, ...)*), i32* nonnull %4) - ret void -} - -define internal void @merge_cancellable_regions..omp_par.5(i32* noalias nocapture readnone %0, i32* noalias nocapture readnone %1, i32* nocapture readonly %2) { - %4 = load i32, i32* %2, align 4 - %5 = icmp eq i32 %4, 0 - br i1 %5, label %6, label %7 - -6: ; preds = %3 - ret void - -7: ; preds = %3 - %8 = call i32 @__kmpc_global_thread_num(%struct.ident_t* nonnull @1) - %9 = call i32 @__kmpc_cancel(%struct.ident_t* nonnull @1, i32 %8, i32 1) - ret void -} - -define internal void @merge_cancellable_regions..omp_par(i32* noalias nocapture readnone %0, i32* noalias nocapture readnone %1, i32* nocapture readonly %2) { - %4 = load i32, i32* %2, align 4 - %5 = icmp eq i32 %4, 0 - br i1 %5, label %6, label %7 - -6: ; preds = %3 - ret void - -7: ; preds = %3 - %8 = call i32 @__kmpc_global_thread_num(%struct.ident_t* nonnull @1) - %9 = call i32 @__kmpc_cancel(%struct.ident_t* nonnull @1, i32 %8, i32 1) - ret void -} - -declare i32 @__kmpc_cancel(%struct.ident_t*, i32, i32) local_unnamed_addr - - -!llvm.module.flags = !{!0} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!2} -!2 = !{i64 2, i64 -1, i64 -1, i1 true} -; CHECK-LABEL: define {{[^@]+}}@merge_all() local_unnamed_addr { -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* noundef nonnull align 8 dereferenceable(24) [[GLOB1:@.*]]) -; CHECK-NEXT: [[TMP2:%.*]] = alloca i32, align 4 -; CHECK-NEXT: store i32 1, i32* [[TMP2]], align 4 -; CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* [[GLOB1]]) -; CHECK-NEXT: br label [[OMP_PARALLEL:%.*]] -; CHECK: omp_parallel: -; CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* [[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @merge_all..omp_par.2 to void (i32*, i32*, ...)*), i32* [[TMP2]]) -; CHECK-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] -; CHECK: omp.par.outlined.exit: -; CHECK-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] -; CHECK: omp.par.exit.split: -; CHECK-NEXT: br label [[DOTSPLIT_SPLIT:%.*]] -; CHECK: .split.split: -; CHECK-NEXT: ret void -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_all..omp_par.2 -; CHECK-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[TMP0:%.*]]) [[ATTR0:#.*]] { -; CHECK-NEXT: omp.par.entry: -; CHECK-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TID_ADDR]], align 4 -; CHECK-NEXT: store i32 [[TMP1]], i32* [[TID_ADDR_LOCAL]], align 4 -; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 -; CHECK-NEXT: br label [[OMP_PAR_REGION:%.*]] -; CHECK: omp.par.outlined.exit.exitStub: -; CHECK-NEXT: ret void -; CHECK: omp.par.region: -; CHECK-NEXT: br label [[OMP_PAR_MERGED:%.*]] -; CHECK: omp.par.merged: -; CHECK-NEXT: call void @merge_all..omp_par(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP0]]) -; CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* [[GLOB1]]) -; CHECK-NEXT: call void @__kmpc_barrier(%struct.ident_t* [[GLOB2:@.*]], i32 [[OMP_GLOBAL_THREAD_NUM]]) -; CHECK-NEXT: call void @merge_all..omp_par.1(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP0]]) -; CHECK-NEXT: br label [[DOTSPLIT:%.*]] -; CHECK: .split: -; CHECK-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]] -; CHECK: omp.par.region.split: -; CHECK-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] -; CHECK: omp.par.pre_finalize: -; CHECK-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_all..omp_par.1 -; CHECK-SAME: (i32* noalias nocapture nofree readnone [[TMP0:%.*]], i32* noalias nocapture nofree readnone [[TMP1:%.*]], i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP2:%.*]]) [[ATTR1:#.*]] { -; CHECK-NEXT: store i32 3, i32* [[TMP2]], align 4 -; CHECK-NEXT: ret void -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_all..omp_par -; CHECK-SAME: (i32* noalias nocapture nofree readnone [[TMP0:%.*]], i32* noalias nocapture nofree readnone [[TMP1:%.*]], i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP2:%.*]]) [[ATTR1]] { -; CHECK-NEXT: store i32 2, i32* [[TMP2]], align 4 -; CHECK-NEXT: ret void -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_none() local_unnamed_addr { -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* noundef nonnull align 8 dereferenceable(24) [[GLOB1]]) -; CHECK-NEXT: [[TMP2:%.*]] = alloca i32, align 4 -; CHECK-NEXT: store i32 1, i32* [[TMP2]], align 4 -; CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* noundef nonnull align 8 dereferenceable(24) [[GLOB1]], i32 noundef 1, void (i32*, i32*, ...)* noundef bitcast (void (i32*, i32*, i32*)* @merge_none..omp_par to void (i32*, i32*, ...)*), i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP2]]) -; CHECK-NEXT: store i32 3, i32* [[TMP2]], align 4 -; CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* noundef nonnull align 8 dereferenceable(24) [[GLOB1]], i32 noundef 1, void (i32*, i32*, ...)* noundef bitcast (void (i32*, i32*, i32*)* @merge_none..omp_par.2 to void (i32*, i32*, ...)*), i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP2]]) -; CHECK-NEXT: ret void -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_none..omp_par.2 -; CHECK-SAME: (i32* noalias nocapture nofree readnone [[TMP0:%.*]], i32* noalias nocapture nofree readnone [[TMP1:%.*]], i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP2:%.*]]) [[ATTR1]] { -; CHECK-NEXT: store i32 4, i32* [[TMP2]], align 4 -; CHECK-NEXT: ret void -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_none..omp_par -; CHECK-SAME: (i32* noalias nocapture nofree readnone [[TMP0:%.*]], i32* noalias nocapture nofree readnone [[TMP1:%.*]], i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP2:%.*]]) [[ATTR1]] { -; CHECK-NEXT: store i32 2, i32* [[TMP2]], align 4 -; CHECK-NEXT: ret void -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_some() local_unnamed_addr { -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* noundef nonnull align 8 dereferenceable(24) [[GLOB1]]) -; CHECK-NEXT: [[TMP2:%.*]] = alloca i32, align 4 -; CHECK-NEXT: store i32 1, i32* [[TMP2]], align 4 -; CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* noundef nonnull align 8 dereferenceable(24) [[GLOB1]], i32 noundef 1, void (i32*, i32*, ...)* noundef bitcast (void (i32*, i32*, i32*)* @merge_some..omp_par to void (i32*, i32*, ...)*), i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP2]]) -; CHECK-NEXT: store i32 3, i32* [[TMP2]], align 4 -; CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* [[GLOB1]]) -; CHECK-NEXT: br label [[OMP_PARALLEL:%.*]] -; CHECK: omp_parallel: -; CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* [[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @merge_some..omp_par.5 to void (i32*, i32*, ...)*), i32* [[TMP2]]) -; CHECK-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] -; CHECK: omp.par.outlined.exit: -; CHECK-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] -; CHECK: omp.par.exit.split: -; CHECK-NEXT: br label [[DOTSPLIT_SPLIT:%.*]] -; CHECK: .split.split: -; CHECK-NEXT: ret void -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_some..omp_par.5 -; CHECK-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[TMP0:%.*]]) [[ATTR0]] { -; CHECK-NEXT: omp.par.entry: -; CHECK-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[TID_ADDR]], align 4 -; CHECK-NEXT: store i32 [[TMP1]], i32* [[TID_ADDR_LOCAL]], align 4 -; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 -; CHECK-NEXT: br label [[OMP_PAR_REGION:%.*]] -; CHECK: omp.par.outlined.exit.exitStub: -; CHECK-NEXT: ret void -; CHECK: omp.par.region: -; CHECK-NEXT: br label [[OMP_PAR_MERGED:%.*]] -; CHECK: omp.par.merged: -; CHECK-NEXT: call void @merge_some..omp_par.3(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP0]]) -; CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* [[GLOB1]]) -; CHECK-NEXT: call void @__kmpc_barrier(%struct.ident_t* [[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]]) -; CHECK-NEXT: call void @merge_some..omp_par.4(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP0]]) -; CHECK-NEXT: br label [[DOTSPLIT:%.*]] -; CHECK: .split: -; CHECK-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]] -; CHECK: omp.par.region.split: -; CHECK-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] -; CHECK: omp.par.pre_finalize: -; CHECK-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_some..omp_par.4 -; CHECK-SAME: (i32* noalias nocapture nofree readnone [[TMP0:%.*]], i32* noalias nocapture nofree readnone [[TMP1:%.*]], i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP2:%.*]]) [[ATTR1]] { -; CHECK-NEXT: store i32 5, i32* [[TMP2]], align 4 -; CHECK-NEXT: ret void -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_some..omp_par.3 -; CHECK-SAME: (i32* noalias nocapture nofree readnone [[TMP0:%.*]], i32* noalias nocapture nofree readnone [[TMP1:%.*]], i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP2:%.*]]) [[ATTR1]] { -; CHECK-NEXT: store i32 4, i32* [[TMP2]], align 4 -; CHECK-NEXT: ret void -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_some..omp_par -; CHECK-SAME: (i32* noalias nocapture nofree readnone [[TMP0:%.*]], i32* noalias nocapture nofree readnone [[TMP1:%.*]], i32* nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[TMP2:%.*]]) [[ATTR1]] { -; CHECK-NEXT: store i32 2, i32* [[TMP2]], align 4 -; CHECK-NEXT: ret void -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_cancellable_regions -; CHECK-SAME: (i32 [[TMP0:%.*]], i32 [[TMP1:%.*]]) local_unnamed_addr { -; CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* noundef nonnull align 8 dereferenceable(24) [[GLOB1]]) -; CHECK-NEXT: [[TMP4:%.*]] = alloca i32, align 4 -; CHECK-NEXT: [[TMP5:%.*]] = alloca i32, align 4 -; CHECK-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 -; CHECK-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 -; CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* [[GLOB1]]) -; CHECK-NEXT: br label [[OMP_PARALLEL:%.*]] -; CHECK: omp_parallel: -; CHECK-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* [[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, i32*)* @merge_cancellable_regions..omp_par.6 to void (i32*, i32*, ...)*), i32* [[TMP4]], i32* [[TMP5]]) -; CHECK-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]] -; CHECK: omp.par.outlined.exit: -; CHECK-NEXT: br label [[OMP_PAR_EXIT_SPLIT:%.*]] -; CHECK: omp.par.exit.split: -; CHECK-NEXT: br label [[DOTSPLIT_SPLIT:%.*]] -; CHECK: .split.split: -; CHECK-NEXT: ret void -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_cancellable_regions..omp_par.6 -; CHECK-SAME: (i32* noalias [[TID_ADDR:%.*]], i32* noalias [[ZERO_ADDR:%.*]], i32* [[TMP0:%.*]], i32* [[TMP1:%.*]]) [[ATTR0]] { -; CHECK-NEXT: omp.par.entry: -; CHECK-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4 -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[TID_ADDR]], align 4 -; CHECK-NEXT: store i32 [[TMP2]], i32* [[TID_ADDR_LOCAL]], align 4 -; CHECK-NEXT: [[TID:%.*]] = load i32, i32* [[TID_ADDR_LOCAL]], align 4 -; CHECK-NEXT: br label [[OMP_PAR_REGION:%.*]] -; CHECK: omp.par.outlined.exit.exitStub: -; CHECK-NEXT: ret void -; CHECK: omp.par.region: -; CHECK-NEXT: br label [[OMP_PAR_MERGED:%.*]] -; CHECK: omp.par.merged: -; CHECK-NEXT: call void @merge_cancellable_regions..omp_par(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture noundef nonnull readonly align 4 dereferenceable(4) [[TMP0]]) -; CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* [[GLOB1]]) -; CHECK-NEXT: call void @__kmpc_barrier(%struct.ident_t* [[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]]) -; CHECK-NEXT: call void @merge_cancellable_regions..omp_par.5(i32* [[TID_ADDR]], i32* [[ZERO_ADDR]], i32* nocapture noundef nonnull readonly align 4 dereferenceable(4) [[TMP1]]) -; CHECK-NEXT: br label [[DOTSPLIT:%.*]] -; CHECK: .split: -; CHECK-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]] -; CHECK: omp.par.region.split: -; CHECK-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]] -; CHECK: omp.par.pre_finalize: -; CHECK-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]] -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_cancellable_regions..omp_par.5 -; CHECK-SAME: (i32* noalias nocapture nofree readnone [[TMP0:%.*]], i32* noalias nocapture nofree readnone [[TMP1:%.*]], i32* nocapture noundef nonnull readonly align 4 dereferenceable(4) [[TMP2:%.*]]) { -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4 -; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP7:%.*]] -; CHECK: 6: -; CHECK-NEXT: ret void -; CHECK: 7: -; CHECK-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* noundef nonnull [[GLOB1]]) -; CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* noundef nonnull [[GLOB1]], i32 [[TMP8]], i32 noundef 1) -; CHECK-NEXT: ret void -; -; -; CHECK-LABEL: define {{[^@]+}}@merge_cancellable_regions..omp_par -; CHECK-SAME: (i32* noalias nocapture nofree readnone [[TMP0:%.*]], i32* noalias nocapture nofree readnone [[TMP1:%.*]], i32* nocapture noundef nonnull readonly align 4 dereferenceable(4) [[TMP2:%.*]]) { -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP2]], align 4 -; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP7:%.*]] -; CHECK: 6: -; CHECK-NEXT: ret void -; CHECK: 7: -; CHECK-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* noundef nonnull [[GLOB1]]) -; CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* noundef nonnull [[GLOB1]], i32 [[TMP8]], i32 noundef 1) -; CHECK-NEXT: ret void -; diff --git a/llvm/test/Transforms/OpenMP/rtf_type_checking.ll b/llvm/test/Transforms/OpenMP/rtf_type_checking.ll index e355c13508ca8..5433adcd8abdd 100644 --- a/llvm/test/Transforms/OpenMP/rtf_type_checking.ll +++ b/llvm/test/Transforms/OpenMP/rtf_type_checking.ll @@ -1,5 +1,7 @@ -; RUN: opt -S -openmpopt -stats < %s 2>&1 | FileCheck %s -; RUN: opt -S -attributor -openmpopt -stats < %s 2>&1 | FileCheck %s +; RUN: opt -S -openmpopt -stats < %s 2>&1 -enable-new-pm=0 | FileCheck %s --check-prefixes=CHECK,LPM +; RUN: opt -S -passes='devirt<2>(cgscc(openmpopt))' -stats -debug-pass-manager < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,NPM +; RUN: opt -S -attributor -openmpopt -stats < %s 2>&1 -enable-new-pm=0 | FileCheck %s --check-prefixes=CHECK,LPM +; RUN: opt -S -passes='attributor,cgscc(devirt<2>(openmpopt))' -stats -debug-pass-manager < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,NPM ; REQUIRES: asserts target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" @@ -54,11 +56,16 @@ declare void @omp_get_thread_num() !1 = !{!"clang"} !2 = !{!3} !3 = !{i64 2, i64 -1, i64 -1, i1 true} + +; NPM: Running pass: OpenMPOptPass on (.omp_outlined.) +; NPM-NOT: Running pass: OpenMPOptPass on (.omp_outlined.) +; NPM: Running pass: OpenMPOptPass on (main) +; NPM-NOT: Running pass: OpenMPOptPass on (main) ; ===-------------------------------------------------------------------------=== ; ... Statistics Collected ... ; ===-------------------------------------------------------------------------=== ; -; CHECK: 1 cgscc-passmgr - Maximum CGSCCPassMgr iterations on one SCC +; LPM: 1 cgscc-passmgr - Maximum CGSCCPassMgr iterations on one SCC ; CHECK: 2 openmp-opt{{.*}}Number of OpenMP runtime functions identified ; -; There are two matches since the pass is run once per function. \ No newline at end of file +; There are two matches since the pass is run once per function. diff --git a/llvm/test/Transforms/PGOProfile/icp_vararg_sret.ll b/llvm/test/Transforms/PGOProfile/icp_vararg_sret.ll index 5f1232a09e58a..3dc43b9f29126 100644 --- a/llvm/test/Transforms/PGOProfile/icp_vararg_sret.ll +++ b/llvm/test/Transforms/PGOProfile/icp_vararg_sret.ll @@ -22,7 +22,7 @@ define void @test() { %s = alloca %struct %tmp = load void (i32, %struct*)*, void (i32, %struct*)** @func_ptr, align 8 - call void %tmp(i32 1, %struct* sret %s), !prof !1 + call void %tmp(i32 1, %struct* sret(%struct) %s), !prof !1 ret void } diff --git a/llvm/test/Transforms/PGOProfile/indirect_call_promotion_byval.ll b/llvm/test/Transforms/PGOProfile/indirect_call_promotion_byval.ll index 9664d203a9226..844b03c645968 100644 --- a/llvm/test/Transforms/PGOProfile/indirect_call_promotion_byval.ll +++ b/llvm/test/Transforms/PGOProfile/indirect_call_promotion_byval.ll @@ -19,7 +19,7 @@ entry: ret i32 %v } -define i32 @func5(%struct.Foo.1* byval %p) { +define i32 @func5(%struct.Foo.1* byval(%struct.Foo.1) %p) { entry: %gep = getelementptr inbounds %struct.Foo.1, %struct.Foo.1* %p, i32 0, i32 0 %v = load i32, i32* %gep diff --git a/llvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll b/llvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll new file mode 100644 index 0000000000000..dc5d363400b9f --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll @@ -0,0 +1,212 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -O3 -S | FileCheck -check-prefixes=ALL,OLDPM %s +; RUN: opt < %s -passes='default' -aa-pipeline=default -S | FileCheck -check-prefixes=ALL,NEWPM %s + +target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "thumbv6m-none-none-eabi" + +; Not only should we be able to to form memsets here, the original loops +; should be deleted, too. + +; Function Attrs: nounwind +define dso_local void @arm_fill_q7(i8 signext %value, i8* %pDst, i32 %blockSize) #0 { +; OLDPM-LABEL: @arm_fill_q7( +; OLDPM-NEXT: entry: +; OLDPM-NEXT: [[CMP_NOT20:%.*]] = icmp ult i32 [[BLOCKSIZE:%.*]], 4 +; OLDPM-NEXT: br i1 [[CMP_NOT20]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]] +; OLDPM: while.body.preheader: +; OLDPM-NEXT: [[TMP0:%.*]] = and i32 [[BLOCKSIZE]], -4 +; OLDPM-NEXT: call void @llvm.memset.p0i8.i32(i8* align 1 [[PDST:%.*]], i8 [[VALUE:%.*]], i32 [[TMP0]], i1 false) +; OLDPM-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, i8* [[PDST]], i32 [[TMP0]] +; OLDPM-NEXT: br label [[WHILE_END]] +; OLDPM: while.end: +; OLDPM-NEXT: [[PDST_ADDR_0_LCSSA:%.*]] = phi i8* [ [[PDST]], [[ENTRY:%.*]] ], [ [[SCEVGEP]], [[WHILE_BODY_PREHEADER]] ] +; OLDPM-NEXT: [[REM:%.*]] = and i32 [[BLOCKSIZE]], 3 +; OLDPM-NEXT: [[CMP14_NOT17:%.*]] = icmp eq i32 [[REM]], 0 +; OLDPM-NEXT: br i1 [[CMP14_NOT17]], label [[WHILE_END18:%.*]], label [[WHILE_BODY16_PREHEADER:%.*]] +; OLDPM: while.body16.preheader: +; OLDPM-NEXT: call void @llvm.memset.p0i8.i32(i8* align 1 [[PDST_ADDR_0_LCSSA]], i8 [[VALUE]], i32 [[REM]], i1 false) +; OLDPM-NEXT: br label [[WHILE_END18]] +; OLDPM: while.end18: +; OLDPM-NEXT: ret void +; +; NEWPM-LABEL: @arm_fill_q7( +; NEWPM-NEXT: entry: +; NEWPM-NEXT: [[CMP_NOT17:%.*]] = icmp ult i32 [[BLOCKSIZE:%.*]], 4 +; NEWPM-NEXT: br i1 [[CMP_NOT17]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]] +; NEWPM: while.body.preheader: +; NEWPM-NEXT: [[TMP0:%.*]] = and i32 [[BLOCKSIZE]], -4 +; NEWPM-NEXT: call void @llvm.memset.p0i8.i32(i8* align 1 [[PDST:%.*]], i8 [[VALUE:%.*]], i32 [[TMP0]], i1 false) +; NEWPM-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, i8* [[PDST]], i32 [[TMP0]] +; NEWPM-NEXT: br label [[WHILE_END]] +; NEWPM: while.end: +; NEWPM-NEXT: [[PDST_ADDR_0_LCSSA:%.*]] = phi i8* [ [[PDST]], [[ENTRY:%.*]] ], [ [[SCEVGEP]], [[WHILE_BODY_PREHEADER]] ] +; NEWPM-NEXT: [[REM:%.*]] = and i32 [[BLOCKSIZE]], 3 +; NEWPM-NEXT: [[CMP14_NOT20:%.*]] = icmp eq i32 [[REM]], 0 +; NEWPM-NEXT: br i1 [[CMP14_NOT20]], label [[WHILE_END18:%.*]], label [[WHILE_BODY16_PREHEADER:%.*]] +; NEWPM: while.body16.preheader: +; NEWPM-NEXT: call void @llvm.memset.p0i8.i32(i8* align 1 [[PDST_ADDR_0_LCSSA]], i8 [[VALUE]], i32 [[REM]], i1 false) +; NEWPM-NEXT: br label [[WHILE_END18]] +; NEWPM: while.end18: +; NEWPM-NEXT: ret void +; +entry: + %value.addr = alloca i8, align 1 + %pDst.addr = alloca i8*, align 4 + %blockSize.addr = alloca i32, align 4 + %blkCnt = alloca i32, align 4 + %packedValue = alloca i32, align 4 + store i8 %value, i8* %value.addr, align 1, !tbaa !3 + store i8* %pDst, i8** %pDst.addr, align 4, !tbaa !6 + store i32 %blockSize, i32* %blockSize.addr, align 4, !tbaa !8 + %0 = bitcast i32* %blkCnt to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3 + %1 = bitcast i32* %packedValue to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %1) #3 + %2 = load i8, i8* %value.addr, align 1, !tbaa !3 + %conv = sext i8 %2 to i32 + %shl = shl i32 %conv, 0 + %and = and i32 %shl, 255 + %3 = load i8, i8* %value.addr, align 1, !tbaa !3 + %conv1 = sext i8 %3 to i32 + %shl2 = shl i32 %conv1, 8 + %and3 = and i32 %shl2, 65280 + %or = or i32 %and, %and3 + %4 = load i8, i8* %value.addr, align 1, !tbaa !3 + %conv4 = sext i8 %4 to i32 + %shl5 = shl i32 %conv4, 16 + %and6 = and i32 %shl5, 16711680 + %or7 = or i32 %or, %and6 + %5 = load i8, i8* %value.addr, align 1, !tbaa !3 + %conv8 = sext i8 %5 to i32 + %shl9 = shl i32 %conv8, 24 + %and10 = and i32 %shl9, -16777216 + %or11 = or i32 %or7, %and10 + store i32 %or11, i32* %packedValue, align 4, !tbaa !8 + %6 = load i32, i32* %blockSize.addr, align 4, !tbaa !8 + %shr = lshr i32 %6, 2 + store i32 %shr, i32* %blkCnt, align 4, !tbaa !8 + br label %while.cond + +while.cond: ; preds = %while.body, %entry + %7 = load i32, i32* %blkCnt, align 4, !tbaa !8 + %cmp = icmp ugt i32 %7, 0 + br i1 %cmp, label %while.body, label %while.end + +while.body: ; preds = %while.cond + %8 = load i32, i32* %packedValue, align 4, !tbaa !8 + call void @write_q7x4_ia(i8** %pDst.addr, i32 %8) + %9 = load i32, i32* %blkCnt, align 4, !tbaa !8 + %dec = add i32 %9, -1 + store i32 %dec, i32* %blkCnt, align 4, !tbaa !8 + br label %while.cond, !llvm.loop !10 + +while.end: ; preds = %while.cond + %10 = load i32, i32* %blockSize.addr, align 4, !tbaa !8 + %rem = urem i32 %10, 4 + store i32 %rem, i32* %blkCnt, align 4, !tbaa !8 + br label %while.cond13 + +while.cond13: ; preds = %while.body16, %while.end + %11 = load i32, i32* %blkCnt, align 4, !tbaa !8 + %cmp14 = icmp ugt i32 %11, 0 + br i1 %cmp14, label %while.body16, label %while.end18 + +while.body16: ; preds = %while.cond13 + %12 = load i8, i8* %value.addr, align 1, !tbaa !3 + %13 = load i8*, i8** %pDst.addr, align 4, !tbaa !6 + %incdec.ptr = getelementptr inbounds i8, i8* %13, i32 1 + store i8* %incdec.ptr, i8** %pDst.addr, align 4, !tbaa !6 + store i8 %12, i8* %13, align 1, !tbaa !3 + %14 = load i32, i32* %blkCnt, align 4, !tbaa !8 + %dec17 = add i32 %14, -1 + store i32 %dec17, i32* %blkCnt, align 4, !tbaa !8 + br label %while.cond13, !llvm.loop !12 + +while.end18: ; preds = %while.cond13 + %15 = bitcast i32* %packedValue to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %15) #3 + %16 = bitcast i32* %blkCnt to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %16) #3 + ret void +} + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1 + +; Function Attrs: alwaysinline nounwind +define internal void @write_q7x4_ia(i8** %pQ7, i32 %value) #2 { +entry: + %pQ7.addr = alloca i8**, align 4 + %value.addr = alloca i32, align 4 + %val = alloca i32, align 4 + store i8** %pQ7, i8*** %pQ7.addr, align 4, !tbaa !6 + store i32 %value, i32* %value.addr, align 4, !tbaa !8 + %0 = bitcast i32* %val to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3 + %1 = load i32, i32* %value.addr, align 4, !tbaa !8 + store i32 %1, i32* %val, align 4, !tbaa !8 + %2 = load i32, i32* %val, align 4, !tbaa !8 + %and = and i32 %2, 255 + %conv = trunc i32 %and to i8 + %3 = load i8**, i8*** %pQ7.addr, align 4, !tbaa !6 + %4 = load i8*, i8** %3, align 4, !tbaa !6 + %arrayidx = getelementptr inbounds i8, i8* %4, i32 0 + store i8 %conv, i8* %arrayidx, align 1, !tbaa !3 + %5 = load i32, i32* %val, align 4, !tbaa !8 + %shr = ashr i32 %5, 8 + %and1 = and i32 %shr, 255 + %conv2 = trunc i32 %and1 to i8 + %6 = load i8**, i8*** %pQ7.addr, align 4, !tbaa !6 + %7 = load i8*, i8** %6, align 4, !tbaa !6 + %arrayidx3 = getelementptr inbounds i8, i8* %7, i32 1 + store i8 %conv2, i8* %arrayidx3, align 1, !tbaa !3 + %8 = load i32, i32* %val, align 4, !tbaa !8 + %shr4 = ashr i32 %8, 16 + %and5 = and i32 %shr4, 255 + %conv6 = trunc i32 %and5 to i8 + %9 = load i8**, i8*** %pQ7.addr, align 4, !tbaa !6 + %10 = load i8*, i8** %9, align 4, !tbaa !6 + %arrayidx7 = getelementptr inbounds i8, i8* %10, i32 2 + store i8 %conv6, i8* %arrayidx7, align 1, !tbaa !3 + %11 = load i32, i32* %val, align 4, !tbaa !8 + %shr8 = ashr i32 %11, 24 + %and9 = and i32 %shr8, 255 + %conv10 = trunc i32 %and9 to i8 + %12 = load i8**, i8*** %pQ7.addr, align 4, !tbaa !6 + %13 = load i8*, i8** %12, align 4, !tbaa !6 + %arrayidx11 = getelementptr inbounds i8, i8* %13, i32 3 + store i8 %conv10, i8* %arrayidx11, align 1, !tbaa !3 + %14 = load i8**, i8*** %pQ7.addr, align 4, !tbaa !6 + %15 = load i8*, i8** %14, align 4, !tbaa !6 + %add.ptr = getelementptr inbounds i8, i8* %15, i32 4 + store i8* %add.ptr, i8** %14, align 4, !tbaa !6 + %16 = bitcast i32* %val to i8* + call void @llvm.lifetime.end.p0i8(i64 4, i8* %16) #3 + ret void +} + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1 + +attributes #0 = { nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m0plus" "target-features"="+armv6-m,+strict-align,+thumb-mode,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-dotprod,-dsp,-fp16fml,-fullfp16,-hwdiv,-hwdiv-arm,-i8mm,-lob,-mve,-mve.fp,-ras,-sb,-sha2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { argmemonly nofree nosync nounwind willreturn } +attributes #2 = { alwaysinline nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m0plus" "target-features"="+armv6-m,+strict-align,+thumb-mode,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-dotprod,-dsp,-fp16fml,-fullfp16,-hwdiv,-hwdiv-arm,-i8mm,-lob,-mve,-mve.fp,-ras,-sb,-sha2" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { nounwind } + +!llvm.module.flags = !{!0, !1} +!llvm.ident = !{!2} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"min_enum_size", i32 4} +!2 = !{!"clang version 12.0.0 (https://github.com/llvm/llvm-project.git 07f234be1ccbce131704f580aa3f117083a887f7)"} +!3 = !{!4, !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} +!6 = !{!7, !7, i64 0} +!7 = !{!"any pointer", !4, i64 0} +!8 = !{!9, !9, i64 0} +!9 = !{!"int", !4, i64 0} +!10 = distinct !{!10, !11} +!11 = !{!"llvm.loop.mustprogress"} +!12 = distinct !{!12, !11} diff --git a/llvm/test/Transforms/PhaseOrdering/ARM/lit.local.cfg b/llvm/test/Transforms/PhaseOrdering/ARM/lit.local.cfg new file mode 100644 index 0000000000000..236e1d3441665 --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/ARM/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'ARM' in config.root.targets: + config.unsupported = True diff --git a/llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll b/llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll index ee1430b9def47..c06342d6022a6 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll @@ -13,62 +13,10 @@ define i32 @cttz(i32 %n, i32* %p1) { ; ALL-NEXT: entry: ; ALL-NEXT: [[TMP0:%.*]] = shl i32 [[N:%.*]], 1 ; ALL-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false), [[RNG0:!range !.*]] -; ALL-NEXT: [[TMP2:%.*]] = sub nuw nsw i32 33, [[TMP1]] -; ALL-NEXT: [[TMP3:%.*]] = sub nuw nsw i32 33, [[TMP1]] -; ALL-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ugt i32 [[TMP1]], 25 -; ALL-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[WHILE_COND_PREHEADER:%.*]], label [[VECTOR_PH:%.*]] -; ALL: vector.ph: -; ALL-NEXT: [[N_VEC:%.*]] = and i32 [[TMP3]], -8 -; ALL-NEXT: [[IND_END:%.*]] = sub nsw i32 [[TMP2]], [[N_VEC]] -; ALL-NEXT: [[TMP4:%.*]] = add nsw i32 [[N_VEC]], -8 -; ALL-NEXT: [[TMP5:%.*]] = lshr exact i32 [[TMP4]], 3 -; ALL-NEXT: [[TMP6:%.*]] = add nuw nsw i32 [[TMP5]], 1 -; ALL-NEXT: [[XTRAITER:%.*]] = and i32 [[TMP6]], 7 -; ALL-NEXT: [[TMP7:%.*]] = icmp ult i32 [[TMP4]], 56 -; ALL-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK_UNR_LCSSA:%.*]], label [[VECTOR_PH_NEW:%.*]] -; ALL: vector.ph.new: -; ALL-NEXT: [[UNROLL_ITER:%.*]] = and i32 [[TMP6]], 1073741816 -; ALL-NEXT: br label [[VECTOR_BODY:%.*]] -; ALL: vector.body: -; ALL-NEXT: [[VEC_PHI:%.*]] = phi <8 x i32> [ , [[VECTOR_PH_NEW]] ], [ [[TMP8:%.*]], [[VECTOR_BODY]] ] -; ALL-NEXT: [[NITER:%.*]] = phi i32 [ [[UNROLL_ITER]], [[VECTOR_PH_NEW]] ], [ [[NITER_NSUB_7:%.*]], [[VECTOR_BODY]] ] -; ALL-NEXT: [[TMP8]] = add <8 x i32> [[VEC_PHI]], -; ALL-NEXT: [[NITER_NSUB_7]] = add i32 [[NITER]], -8 -; ALL-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i32 [[NITER_NSUB_7]], 0 -; ALL-NEXT: br i1 [[NITER_NCMP_7]], label [[MIDDLE_BLOCK_UNR_LCSSA]], label [[VECTOR_BODY]], [[LOOP1:!llvm.loop !.*]] -; ALL: middle.block.unr-lcssa: -; ALL-NEXT: [[DOTLCSSA_PH:%.*]] = phi <8 x i32> [ undef, [[VECTOR_PH]] ], [ [[TMP8]], [[VECTOR_BODY]] ] -; ALL-NEXT: [[VEC_PHI_UNR:%.*]] = phi <8 x i32> [ , [[VECTOR_PH]] ], [ [[TMP8]], [[VECTOR_BODY]] ] -; ALL-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i32 [[XTRAITER]], 0 -; ALL-NEXT: br i1 [[LCMP_MOD_NOT]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY_EPIL:%.*]] -; ALL: vector.body.epil: -; ALL-NEXT: [[VEC_PHI_EPIL:%.*]] = phi <8 x i32> [ [[TMP9:%.*]], [[VECTOR_BODY_EPIL]] ], [ [[VEC_PHI_UNR]], [[MIDDLE_BLOCK_UNR_LCSSA]] ] -; ALL-NEXT: [[EPIL_ITER:%.*]] = phi i32 [ [[EPIL_ITER_SUB:%.*]], [[VECTOR_BODY_EPIL]] ], [ [[XTRAITER]], [[MIDDLE_BLOCK_UNR_LCSSA]] ] -; ALL-NEXT: [[TMP9]] = add <8 x i32> [[VEC_PHI_EPIL]], -; ALL-NEXT: [[EPIL_ITER_SUB]] = add i32 [[EPIL_ITER]], -1 -; ALL-NEXT: [[EPIL_ITER_CMP_NOT:%.*]] = icmp eq i32 [[EPIL_ITER_SUB]], 0 -; ALL-NEXT: br i1 [[EPIL_ITER_CMP_NOT]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY_EPIL]], [[LOOP3:!llvm.loop !.*]] -; ALL: middle.block: -; ALL-NEXT: [[DOTLCSSA:%.*]] = phi <8 x i32> [ [[DOTLCSSA_PH]], [[MIDDLE_BLOCK_UNR_LCSSA]] ], [ [[TMP9]], [[VECTOR_BODY_EPIL]] ] -; ALL-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[DOTLCSSA]]) -; ALL-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP3]], [[N_VEC]] -; ALL-NEXT: br i1 [[CMP_N]], label [[WHILE_END:%.*]], label [[WHILE_COND_PREHEADER]] -; ALL: while.cond.preheader: -; ALL-NEXT: [[TCPHI_PH:%.*]] = phi i32 [ [[TMP2]], [[ENTRY:%.*]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ] -; ALL-NEXT: [[WHATEVER_PH:%.*]] = phi i32 [ 42, [[ENTRY]] ], [ [[TMP10]], [[MIDDLE_BLOCK]] ] -; ALL-NEXT: br label [[WHILE_COND:%.*]] -; ALL: while.cond: -; ALL-NEXT: [[TCPHI:%.*]] = phi i32 [ [[TCDEC:%.*]], [[WHILE_COND]] ], [ [[TCPHI_PH]], [[WHILE_COND_PREHEADER]] ] -; ALL-NEXT: [[WHATEVER:%.*]] = phi i32 [ [[WHATEVER_NEXT:%.*]], [[WHILE_COND]] ], [ [[WHATEVER_PH]], [[WHILE_COND_PREHEADER]] ] -; ALL-NEXT: [[TCDEC]] = add nsw i32 [[TCPHI]], -1 -; ALL-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TCDEC]], 0 -; ALL-NEXT: [[WHATEVER_NEXT]] = add nuw nsw i32 [[WHATEVER]], 1 -; ALL-NEXT: br i1 [[TOBOOL]], label [[WHILE_END]], label [[WHILE_COND]], [[LOOP5:!llvm.loop !.*]] -; ALL: while.end: -; ALL-NEXT: [[WHATEVER_NEXT_LCSSA:%.*]] = phi i32 [ [[TMP10]], [[MIDDLE_BLOCK]] ], [ [[WHATEVER_NEXT]], [[WHILE_COND]] ] -; ALL-NEXT: [[TMP11:%.*]] = sub nuw nsw i32 32, [[TMP1]] -; ALL-NEXT: store i32 [[WHATEVER_NEXT_LCSSA]], i32* [[P1:%.*]], align 4 -; ALL-NEXT: ret i32 [[TMP11]] +; ALL-NEXT: [[TMP2:%.*]] = sub nuw nsw i32 32, [[TMP1]] +; ALL-NEXT: [[TMP3:%.*]] = sub nuw nsw i32 75, [[TMP1]] +; ALL-NEXT: store i32 [[TMP3]], i32* [[P1:%.*]], align 4 +; ALL-NEXT: ret i32 [[TMP2]] ; entry: br label %while.cond diff --git a/llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll b/llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll index 59243a9ff8c9f..4fe75883959e3 100644 --- a/llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll +++ b/llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll @@ -88,7 +88,7 @@ false2: ; This test checks that alignment assumptions do not prevent SROA. ; See PR45763. -define internal void @callee2(i64* noalias sret align 32 %arg) { +define internal void @callee2(i64* noalias sret(i64) align 32 %arg) { store i64 0, i64* %arg, align 8 ret void } @@ -99,6 +99,6 @@ define amdgpu_kernel void @caller2() { ; %alloca = alloca i64, align 8, addrspace(5) %cast = addrspacecast i64 addrspace(5)* %alloca to i64* - call void @callee2(i64* sret align 32 %cast) + call void @callee2(i64* sret(i64) align 32 %cast) ret void } diff --git a/llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll b/llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll index d8cf0cb6ff6ab..f54bc424856c5 100644 --- a/llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll +++ b/llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll @@ -47,7 +47,7 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16 %0 = type { i32*, i32, i32, i32 } -define dso_local void @_Z3gen1S(%0* noalias sret align 8 %arg, %0* byval(%0) align 8 %arg1) { +define dso_local void @_Z3gen1S(%0* noalias sret(%0) align 8 %arg, %0* byval(%0) align 8 %arg1) { ; CHECK-LABEL: @_Z3gen1S( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[I:%.*]] = getelementptr inbounds [[TMP0:%.*]], %0* [[ARG1:%.*]], i64 0, i32 0 @@ -84,7 +84,7 @@ bb: %i4 = bitcast %0* %i1 to i8* %i5 = bitcast %0* %arg to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %i4, i8* align 8 %i5, i64 24, i1 false) - call void @_Z3gen1S(%0* sret align 8 %i, %0* byval(%0) align 8 %i1) + call void @_Z3gen1S(%0* sret(%0) align 8 %i, %0* byval(%0) align 8 %i1) %i6 = bitcast %0* %i2 to i8* %i7 = bitcast %0* %i to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %i6, i8* align 8 %i7, i64 24, i1 false) @@ -131,7 +131,7 @@ bb: %i3 = bitcast %0* %i1 to i8* %i4 = bitcast %0* %arg to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %i3, i8* align 8 %i4, i64 24, i1 false) - call void @_Z3gen1S(%0* sret align 8 %i, %0* byval(%0) align 8 %i1) + call void @_Z3gen1S(%0* sret(%0) align 8 %i, %0* byval(%0) align 8 %i1) %i5 = call i32 @_Z4condv() %i6 = icmp ne i32 %i5, 0 br i1 %i6, label %bb7, label %bb10 diff --git a/llvm/test/Transforms/SCCP/2009-09-24-byval-ptr.ll b/llvm/test/Transforms/SCCP/2009-09-24-byval-ptr.ll index 9a027668036c8..e491e04122853 100644 --- a/llvm/test/Transforms/SCCP/2009-09-24-byval-ptr.ll +++ b/llvm/test/Transforms/SCCP/2009-09-24-byval-ptr.ll @@ -3,7 +3,7 @@ ; PR5038 %struct.MYstr = type { i8, i32 } @mystr = internal global %struct.MYstr zeroinitializer ; <%struct.MYstr*> [#uses=3] -define internal void @vfu1(%struct.MYstr* byval align 4 %u) nounwind { +define internal void @vfu1(%struct.MYstr* byval(%struct.MYstr) align 4 %u) nounwind { entry: %0 = getelementptr %struct.MYstr, %struct.MYstr* %u, i32 0, i32 1 ; [#uses=1] store i32 99, i32* %0, align 4 @@ -17,7 +17,7 @@ return: ; preds = %entry ret void } -define internal i32 @vfu2(%struct.MYstr* byval align 4 %u) nounwind readonly { +define internal i32 @vfu2(%struct.MYstr* byval(%struct.MYstr) align 4 %u) nounwind readonly { entry: %0 = getelementptr %struct.MYstr, %struct.MYstr* %u, i32 0, i32 1 ; [#uses=1] %1 = load i32, i32* %0 @@ -32,8 +32,8 @@ entry: define i32 @unions() nounwind { entry: - call void @vfu1(%struct.MYstr* byval align 4 @mystr) nounwind - %result = call i32 @vfu2(%struct.MYstr* byval align 4 @mystr) nounwind + call void @vfu1(%struct.MYstr* byval(%struct.MYstr) align 4 @mystr) nounwind + %result = call i32 @vfu2(%struct.MYstr* byval(%struct.MYstr) align 4 @mystr) nounwind ; CHECK: ret i32 %result ret i32 %result } diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll index 4c2d51b188e62..0c16daa1ef3dc 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -S -slp-vectorizer -instcombine -pass-remarks-output=%t | FileCheck %s ; RUN: cat %t | FileCheck -check-prefix=REMARK %s -; RUN: opt < %s -S -passes='slp-vectorizer,instcombine' -pass-remarks-output=%t | FileCheck %s +; RUN: opt < %s -S -aa-pipeline=basic-aa -passes='slp-vectorizer,instcombine' -pass-remarks-output=%t | FileCheck %s ; RUN: cat %t | FileCheck -check-prefix=REMARK %s target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" @@ -12,6 +12,8 @@ target triple = "aarch64--linux-gnu" ; REMARK-NEXT: - String: 'Vectorized horizontal reduction with cost ' ; REMARK-NEXT: - Cost: '-7' ; +; REMARK-NOT: Function: gather_load + define internal i32 @gather_multiple_use(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK-LABEL: @gather_multiple_use( ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> undef, i32 [[C:%.*]], i32 0 @@ -51,3 +53,55 @@ define internal i32 @gather_multiple_use(i32 %a, i32 %b, i32 %c, i32 %d) { %tmp22 = add i32 %tmp21, %tmp19 ret i32 %tmp22 } + +@data = global [6 x [258 x i8]] zeroinitializer, align 1 +define void @gather_load(i16* noalias %ptr) { +; CHECK-LABEL: @gather_load( +; CHECK-NEXT: [[ARRAYIDX182:%.*]] = getelementptr inbounds i16, i16* [[PTR:%.*]], i64 1 +; CHECK-NEXT: [[ARRAYIDX183:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 2 +; CHECK-NEXT: [[ARRAYIDX184:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 3 +; CHECK-NEXT: [[ARRAYIDX185:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 4 +; CHECK-NEXT: [[L0:%.*]] = load i8, i8* getelementptr inbounds ([6 x [258 x i8]], [6 x [258 x i8]]* @data, i64 0, i64 1, i64 0), align 1 +; CHECK-NEXT: [[CONV150:%.*]] = zext i8 [[L0]] to i16 +; CHECK-NEXT: [[ADD152:%.*]] = add nuw nsw i16 [[CONV150]], 10 +; CHECK-NEXT: [[L1:%.*]] = load i8, i8* getelementptr inbounds ([6 x [258 x i8]], [6 x [258 x i8]]* @data, i64 0, i64 2, i64 1), align 1 +; CHECK-NEXT: [[CONV156:%.*]] = zext i8 [[L1]] to i16 +; CHECK-NEXT: [[ADD158:%.*]] = add nuw nsw i16 [[CONV156]], 20 +; CHECK-NEXT: [[L2:%.*]] = load i8, i8* getelementptr inbounds ([6 x [258 x i8]], [6 x [258 x i8]]* @data, i64 0, i64 3, i64 2), align 1 +; CHECK-NEXT: [[CONV162:%.*]] = zext i8 [[L2]] to i16 +; CHECK-NEXT: [[ADD164:%.*]] = add nuw nsw i16 [[CONV162]], 30 +; CHECK-NEXT: [[L3:%.*]] = load i8, i8* getelementptr inbounds ([6 x [258 x i8]], [6 x [258 x i8]]* @data, i64 0, i64 4, i64 3), align 1 +; CHECK-NEXT: [[CONV168:%.*]] = zext i8 [[L3]] to i16 +; CHECK-NEXT: [[ADD170:%.*]] = add nuw nsw i16 [[CONV168]], 40 +; CHECK-NEXT: store i16 [[ADD152]], i16* [[ARRAYIDX182]], align 2 +; CHECK-NEXT: store i16 [[ADD158]], i16* [[ARRAYIDX183]], align 2 +; CHECK-NEXT: store i16 [[ADD164]], i16* [[ARRAYIDX184]], align 2 +; CHECK-NEXT: store i16 [[ADD170]], i16* [[ARRAYIDX185]], align 2 +; CHECK-NEXT: ret void +; + %arrayidx182 = getelementptr inbounds i16, i16* %ptr, i64 1 + %arrayidx183 = getelementptr inbounds i16, i16* %ptr, i64 2 + %arrayidx184 = getelementptr inbounds i16, i16* %ptr, i64 3 + %arrayidx185 = getelementptr inbounds i16, i16* %ptr, i64 4 + %arrayidx149 = getelementptr inbounds [6 x [258 x i8]], [6 x [258 x i8]]* @data, i64 0, i64 1, i64 0 + %l0 = load i8, i8* %arrayidx149, align 1 + %conv150 = zext i8 %l0 to i16 + %add152 = add i16 10, %conv150 + %arrayidx155 = getelementptr inbounds [6 x [258 x i8]], [6 x [258 x i8]]* @data, i64 0, i64 2, i64 1 + %l1 = load i8, i8* %arrayidx155, align 1 + %conv156 = zext i8 %l1 to i16 + %add158 = add i16 20, %conv156 + %arrayidx161 = getelementptr inbounds [6 x [258 x i8]], [6 x [258 x i8]]* @data, i64 0, i64 3, i64 2 + %l2 = load i8, i8* %arrayidx161, align 1 + %conv162 = zext i8 %l2 to i16 + %add164 = add i16 30, %conv162 + %arrayidx167 = getelementptr inbounds [6 x [258 x i8]], [6 x [258 x i8]]* @data, i64 0, i64 4, i64 3 + %l3 = load i8, i8* %arrayidx167, align 1 + %conv168 = zext i8 %l3 to i16 + %add170 = add i16 40, %conv168 + store i16 %add152, i16* %arrayidx182, align 2 + store i16 %add158, i16* %arrayidx183, align 2 + store i16 %add164, i16* %arrayidx184, align 2 + store i16 %add170, i16* %arrayidx185, align 2 + ret void +} diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/mul.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/mul.ll new file mode 100644 index 0000000000000..228a4d773f0c8 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/mul.ll @@ -0,0 +1,108 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -basic-aa -slp-vectorizer -S | FileCheck %s + +target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-gnu" + +; These examples correspond to input code like: +; +; void t(long * __restrict a, long * __restrict b) { +; a[0] *= b[0]; +; a[1] *= b[1]; +; } +; +; If we SLP vectorise this then we end up with something like this because we +; don't have a mul.2d: +; +; ldr q0, [x1] +; ldr q1, [x0] +; fmov x8, d0 +; mov x10, v0.d[1] +; fmov x9, d1 +; mov x11, v1.d[1] +; mul x8, x9, x8 +; mul x9, x11, x10 +; fmov d0, x8 +; mov v0.d[1], x9 +; str q0, [x0] +; ret +; +; but if we don't SLP vectorise these examples we get this which is smaller +; and faster: +; +; ldp x8, x9, [x1] +; ldp x10, x11, [x0] +; mul x9, x11, x9 +; mul x8, x10, x8 +; stp x8, x9, [x0] +; ret +; +; FIXME: don't SLP vectorise this. + +define void @mul(i64* noalias nocapture %a, i64* noalias nocapture readonly %b) { +; CHECK-LABEL: @mul( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, i64* [[B:%.*]], i64 1 +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i64* [[B]] to <2 x i64>* +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[TMP0]], align 8 +; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i64, i64* [[A:%.*]], i64 1 +; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64* [[A]] to <2 x i64>* +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* [[TMP2]], align 8 +; CHECK-NEXT: [[TMP4:%.*]] = mul nsw <2 x i64> [[TMP3]], [[TMP1]] +; CHECK-NEXT: [[TMP5:%.*]] = bitcast i64* [[A]] to <2 x i64>* +; CHECK-NEXT: store <2 x i64> [[TMP4]], <2 x i64>* [[TMP5]], align 8 +; CHECK-NEXT: ret void +; +entry: + %0 = load i64, i64* %b, align 8 + %1 = load i64, i64* %a, align 8 + %mul = mul nsw i64 %1, %0 + store i64 %mul, i64* %a, align 8 + %arrayidx2 = getelementptr inbounds i64, i64* %b, i64 1 + %2 = load i64, i64* %arrayidx2, align 8 + %arrayidx3 = getelementptr inbounds i64, i64* %a, i64 1 + %3 = load i64, i64* %arrayidx3, align 8 + %mul4 = mul nsw i64 %3, %2 + store i64 %mul4, i64* %arrayidx3, align 8 + ret void +} + +; Similar example, but now a multiply-accumulate: +; +; void x (long * __restrict a, long * __restrict b) { +; a[0] *= b[0]; +; a[1] *= b[1]; +; a[0] += b[0]; +; a[1] += b[1]; +; } +; +define void @mac(i64* noalias nocapture %a, i64* noalias nocapture readonly %b) { +; CHECK-LABEL: @mac( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, i64* [[B:%.*]], i64 1 +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i64* [[B]] to <2 x i64>* +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[TMP0]], align 8 +; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i64, i64* [[A:%.*]], i64 1 +; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64* [[A]] to <2 x i64>* +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* [[TMP2]], align 8 +; CHECK-NEXT: [[TMP4:%.*]] = mul nsw <2 x i64> [[TMP3]], [[TMP1]] +; CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i64> [[TMP4]], [[TMP1]] +; CHECK-NEXT: [[TMP6:%.*]] = bitcast i64* [[A]] to <2 x i64>* +; CHECK-NEXT: store <2 x i64> [[TMP5]], <2 x i64>* [[TMP6]], align 8 +; CHECK-NEXT: ret void +; +entry: + %0 = load i64, i64* %b, align 8 + %1 = load i64, i64* %a, align 8 + %mul = mul nsw i64 %1, %0 + %arrayidx2 = getelementptr inbounds i64, i64* %b, i64 1 + %2 = load i64, i64* %arrayidx2, align 8 + %arrayidx3 = getelementptr inbounds i64, i64* %a, i64 1 + %3 = load i64, i64* %arrayidx3, align 8 + %mul4 = mul nsw i64 %3, %2 + %add = add nsw i64 %mul, %0 + store i64 %add, i64* %a, align 8 + %add9 = add nsw i64 %mul4, %2 + store i64 %add9, i64* %arrayidx3, align 8 + ret void +} diff --git a/llvm/test/Transforms/SLPVectorizer/ARM/sroa.ll b/llvm/test/Transforms/SLPVectorizer/ARM/sroa.ll index cd17cd83bfa4f..6019c3c1e46e0 100644 --- a/llvm/test/Transforms/SLPVectorizer/ARM/sroa.ll +++ b/llvm/test/Transforms/SLPVectorizer/ARM/sroa.ll @@ -9,7 +9,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64- ; because the scalar version of the shl/or are handled by the ; backend and disappear, the vectorized code stays. -define void @SROAed(%class.Complex* noalias nocapture sret %agg.result, [4 x i32] %a.coerce, [4 x i32] %b.coerce) { +define void @SROAed(%class.Complex* noalias nocapture sret(%class.Complex) %agg.result, [4 x i32] %a.coerce, [4 x i32] %b.coerce) { ; CHECK-LABEL: @SROAed( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[A_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [4 x i32] [[A_COERCE:%.*]], 0 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll b/llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll index dd126c61dd7db..7974bce183d45 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -basic-aa -slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7-avx | FileCheck %s -define void @julia_2xdouble([2 x double]* sret, [2 x double]*, [2 x double]*, [2 x double]*) { +define void @julia_2xdouble([2 x double]* sret([2 x double]), [2 x double]*, [2 x double]*, [2 x double]*) { ; CHECK-LABEL: @julia_2xdouble( ; CHECK-NEXT: top: ; CHECK-NEXT: [[PX0:%.*]] = getelementptr inbounds [2 x double], [2 x double]* [[TMP2:%.*]], i64 0, i64 0 @@ -48,7 +48,7 @@ top: ret void } -define void @julia_4xfloat([4 x float]* sret, [4 x float]*, [4 x float]*, [4 x float]*) { +define void @julia_4xfloat([4 x float]* sret([4 x float]), [4 x float]*, [4 x float]*, [4 x float]*) { ; CHECK-LABEL: @julia_4xfloat( ; CHECK-NEXT: top: ; CHECK-NEXT: [[PX0:%.*]] = getelementptr inbounds [4 x float], [4 x float]* [[TMP2:%.*]], i64 0, i64 0 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll b/llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll index 6843e852416a9..928457ea43037 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/reverse_extract_elements.ll @@ -27,7 +27,7 @@ entry: ret float %add.3 } -define double @dotd(<4 x double>* byval nocapture readonly align 32, <4 x double>* byval nocapture readonly align 32) { +define double @dotd(<4 x double>* byval(<4 x double>) nocapture readonly align 32, <4 x double>* byval(<4 x double>) nocapture readonly align 32) { ; CHECK-LABEL: @dotd( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[X:%.*]] = load <4 x double>, <4 x double>* [[TMP0:%.*]], align 32 diff --git a/llvm/test/Transforms/SROA/dead-inst.ll b/llvm/test/Transforms/SROA/dead-inst.ll index 043d8509f3f42..5fc8096bdb14b 100644 --- a/llvm/test/Transforms/SROA/dead-inst.ll +++ b/llvm/test/Transforms/SROA/dead-inst.ll @@ -15,7 +15,7 @@ target triple = "powerpc64le-grtev4-linux-gnu" %class.b = type { i64 } -declare void @D(%class.b* sret, %class.b* dereferenceable(32)) local_unnamed_addr +declare void @D(%class.b* sret(%class.b), %class.b* dereferenceable(32)) local_unnamed_addr ; Function Attrs: nounwind define hidden fastcc void @H(%class.b* noalias nocapture readnone, [2 x i64]) unnamed_addr { @@ -75,7 +75,7 @@ a.exit: unreachable ;