Implement L1 caches

[howardlau1999]

The processor is now fetching instructions and doing memory operations via a shared bus. It can be seen that the pipeline is mostly stalled due to slow bus operations. Modern processors offer caches to fill the gap between the core and the bus.

Although we have a von-Neumann architecture CPU, L1 caches are usually split into I-cache(I$) and D-cache(D$) for instructions and data respectively.

These caches are commonly set-associative and implemented as SRAMs. The caches should keep record of cache line status and request bus for memory operations if needed.