diff --git a/Branch-Predictor/src/hazard_unit.sv b/Branch-Predictor/src/hazard_unit.sv deleted file mode 100644 index 77785ba..0000000 --- a/Branch-Predictor/src/hazard_unit.sv +++ /dev/null @@ -1,68 +0,0 @@ -`timescale 1ns / 1ps - -// Hazard handler -module hazard_unit ( - input predict_miss_i, - input [4:0] rs_d_i, - input [4:0] rt_d_i, - input [1:0] branch_d_i, - input pc_src_d_i, - input [2:0] jump_d_i, - input [4:0] rs_e_i, - input [4:0] rt_e_i, - input [4:0] write_reg_e_i, - input mem_to_reg_e_i, - input reg_write_e_i, - input [4:0] write_reg_m_i, - input mem_to_reg_m_i, - input reg_write_m_i, - input [4:0] write_reg_w_i, - input reg_write_w_i, - output logic stall_f_o, - output logic stall_d_o, - output logic flush_d_o, - output logic forward_a_d_o, - output logic forward_b_d_o, - output logic flush_e_o, - output logic [1:0] forward_a_e_o, - output logic [1:0] forward_b_e_o -); - - logic lw_stall, branch_stall, branch_predict_stall; - - // Solves data hazards with forwarding - always_comb begin - if (rs_e_i && rs_e_i == write_reg_m_i && reg_write_m_i) begin - forward_a_e_o = 2'b10; - end else if (rs_e_i && rs_e_i == write_reg_w_i && reg_write_w_i) begin - forward_a_e_o = 2'b01; - end else begin - forward_a_e_o = 2'b00; - end - if (rt_e_i && rt_e_i == write_reg_m_i && reg_write_m_i) begin - forward_b_e_o = 2'b10; - end else if (rt_e_i && rt_e_i == write_reg_w_i && reg_write_w_i) begin - forward_b_e_o = 2'b01; - end else begin - forward_b_e_o = 2'b00; - end - end - - // Solves control hazards with forwarding - assign forward_a_d_o = rs_d_i && rs_d_i == write_reg_m_i && reg_write_m_i; - assign forward_b_d_o = rt_d_i && rt_d_i == write_reg_m_i && reg_write_m_i; - - // Solves data hazards with stalls - assign lw_stall = (rs_d_i == rt_e_i || rt_d_i == rt_e_i) && mem_to_reg_e_i; - - // Solves control hazards with stalls - assign branch_stall = (branch_d_i || jump_d_i[1]) - && (reg_write_e_i && (rs_d_i == write_reg_e_i || rt_d_i == write_reg_e_i) - || mem_to_reg_m_i && (rs_d_i == write_reg_m_i || rt_d_i == write_reg_m_i)); - - assign stall_d_o = lw_stall || branch_stall; - assign flush_e_o = stall_d_o || predict_miss_i; - assign flush_d_o = predict_miss_i || jump_d_i[1]; // wrong prediction or JR - assign stall_f_o = stall_d_o; - -endmodule : hazard_unit diff --git a/Branch-Predictor/src/mips.sv b/Branch-Predictor/src/mips.sv deleted file mode 100644 index e083173..0000000 --- a/Branch-Predictor/src/mips.sv +++ /dev/null @@ -1,205 +0,0 @@ -`timescale 1ns / 1ps - -// Since our TA has hard-coded variable names into the grader, we have -// to name the variables like this, regardless of the coding style. - -// Pipeline 32-bit MIPS processor -module mips ( - input clk, - input reset, - input [31:0] instr, - input [31:0] readdata, - input ihit, - input dhit, - output logic [31:0] pc, - output logic memwrite, - output logic [31:0] aluout, - output logic [31:0] writedata, - output dcen -); - - logic is_branch_d; - logic last_taken, predict_miss; - logic [31:0] predict_pc; - - logic [1:0] branch_d; - logic pc_src_d; - logic [31:0] pc_branch_d, pc_plus_4_d; - logic [31:0] src_a_d; - logic [2:0] jump_d; - logic [31:0] instr_d; - logic [4:0] rs_d, rt_d; - - logic reg_write_e, reg_dst_e; - logic [1:0] alu_src_e; - logic [3:0] alu_control_e; - logic [2:0] jump_e; - logic mem_write_e, mem_to_reg_e; - logic [31:0] pc_plus_4_e, reg_data_1_e, reg_data_2_e; - logic [4:0] rs_e, rt_e, rd_e, shamt_e, write_reg_e; - logic [31:0] ext_imm_e; - - logic reg_write_m, mem_to_reg_m; - logic [4:0] write_reg_m; - - logic reg_write_w, mem_to_reg_w; - logic [31:0] read_data_w, alu_out_w, result_w; - logic [4:0] write_reg_w; - - logic stall_f, stall_d, flush_d, flush_e; - logic forward_a_d, forward_b_d; - logic [1:0] forward_a_e, forward_b_e; - - assign dcen = memwrite | mem_to_reg_m; - - assign is_branch_d = |branch_d; - assign predict_miss = is_branch_d && pc_src_d != last_taken; - - bpb u_bpb ( - .clk_i(clk), - .rst_i(reset), - .en_i(~stall_f), - .pc_f_i(pc), - .instr_f_i(instr), - .is_branch_d_i(is_branch_d), - .miss_i(predict_miss), - .pc_branch_i(pc_branch_d), - .last_taken_o(last_taken), - .predict_pc_o(predict_pc) - ); - - fetch u_fetch ( - .clk_i(clk), - .rst_i(reset), - .instr_f_i(instr), - .predict_pc_i(predict_pc), - .predict_miss_i(predict_miss), - .pc_branch_d_i(pc_branch_d), - .pc_src_d_i(pc_src_d), - .src_a_d_i(src_a_d), - .jump_d_i(jump_d), - .stall_f_i(stall_f), - .stall_d_i(stall_d), - .flush_d_i(flush_d), - .pc_f_o(pc), - .pc_plus_4_d_o(pc_plus_4_d), - .instr_d_o(instr_d) - ); - - decode u_decode ( - .clk_i(clk), - .rst_i(reset), - .pc_plus_4_d_i(pc_plus_4_d), - .instr_d_i(instr_d), - .alu_out_m_i(aluout), - .reg_write_w_i(reg_write_w), - .write_reg_w_i(write_reg_w), - .result_w_i(result_w), - .forward_a_d_i(forward_a_d), - .forward_b_d_i(forward_b_d), - .flush_e_i(flush_e), - .branch_d_o(branch_d), - .pc_src_d_o(pc_src_d), - .jump_d_o(jump_d), - .pc_branch_d_o(pc_branch_d), - .src_a_d_o(src_a_d), - .rs_d_o(rs_d), - .rt_d_o(rt_d), - .reg_write_e_o(reg_write_e), - .reg_dst_e_o(reg_dst_e), - .alu_src_e_o(alu_src_e), - .alu_control_e_o(alu_control_e), - .jump_e_o(jump_e), - .mem_write_e_o(mem_write_e), - .mem_to_reg_e_o(mem_to_reg_e), - .pc_plus_4_e_o(pc_plus_4_e), - .reg_data_1_e_o(reg_data_1_e), - .reg_data_2_e_o(reg_data_2_e), - .rs_e_o(rs_e), - .rt_e_o(rt_e), - .rd_e_o(rd_e), - .shamt_e_o(shamt_e), - .ext_imm_e_o(ext_imm_e) - ); - - execute u_execute ( - .clk_i(clk), - .rst_i(reset), - .reg_write_e_i(reg_write_e), - .reg_dst_e_i(reg_dst_e), - .alu_src_e_i(alu_src_e), - .alu_control_e_i(alu_control_e), - .jump_e_i(jump_e), - .mem_write_e_i(mem_write_e), - .mem_to_reg_e_i(mem_to_reg_e), - .pc_plus_4_e_i(pc_plus_4_e), - .reg_data_1_e_i(reg_data_1_e), - .reg_data_2_e_i(reg_data_2_e), - .rt_e_i(rt_e), - .rd_e_i(rd_e), - .shamt_e_i(shamt_e), - .ext_imm_e_i(ext_imm_e), - .result_w_i(result_w), - .forward_a_e_i(forward_a_e), - .forward_b_e_i(forward_b_e), - .write_reg_e_o(write_reg_e), - .reg_write_m_o(reg_write_m), - .mem_write_m_o(memwrite), - .mem_to_reg_m_o(mem_to_reg_m), - .alu_out_m_o(aluout), - .write_data_m_o(writedata), - .write_reg_m_o(write_reg_m) - ); - - memory u_memory ( - .clk_i(clk), - .rst_i(reset), - .reg_write_m_i(reg_write_m), - .mem_to_reg_m_i(mem_to_reg_m), - .alu_out_m_i(aluout), - .write_reg_m_i(write_reg_m), - .read_data_m_i(readdata), - .reg_write_w_o(reg_write_w), - .mem_to_reg_w_o(mem_to_reg_w), - .alu_out_w_o(alu_out_w), - .read_data_w_o(read_data_w), - .write_reg_w_o(write_reg_w) - ); - - writeback u_writeback ( - .clk_i(clk), - .rst_i(reset), - .mem_to_reg_w_i(mem_to_reg_w), - .alu_out_w_i(alu_out_w), - .read_data_w_i(read_data_w), - .result_w_o(result_w) - ); - - hazard_unit u_hazard_unit ( - .predict_miss_i(predict_miss), - .rs_d_i(rs_d), - .rt_d_i(rt_d), - .branch_d_i(branch_d), - .pc_src_d_i(pc_src_d), - .jump_d_i(jump_d), - .rs_e_i(rs_e), - .rt_e_i(rt_e), - .write_reg_e_i(write_reg_e), - .mem_to_reg_e_i(mem_to_reg_e), - .reg_write_e_i(reg_write_e), - .write_reg_m_i(write_reg_m), - .mem_to_reg_m_i(mem_to_reg_m), - .reg_write_m_i(reg_write_m), - .write_reg_w_i(write_reg_w), - .reg_write_w_i(reg_write_w), - .stall_f_o(stall_f), - .stall_d_o(stall_d), - .flush_d_o(flush_d), - .forward_a_d_o(forward_a_d), - .forward_b_d_o(forward_b_d), - .flush_e_o(flush_e), - .forward_a_e_o(forward_a_e), - .forward_b_e_o(forward_b_e) - ); - -endmodule : mips diff --git a/Branch-Predictor/src/pipeline_stages/fetch.sv b/Branch-Predictor/src/pipeline_stages/fetch.sv deleted file mode 100644 index 59b94de..0000000 --- a/Branch-Predictor/src/pipeline_stages/fetch.sv +++ /dev/null @@ -1,69 +0,0 @@ -`timescale 1ns / 1ps - -module fetch ( - input clk_i, - input rst_i, - input [31:0] predict_pc_i, - input predict_miss_i, - input [31:0] instr_f_i, - input [31:0] pc_branch_d_i, - input pc_src_d_i, - input [31:0] src_a_d_i, - input [2:0] jump_d_i, - input stall_f_i, - input stall_d_i, - input flush_d_i, - output logic [31:0] pc_f_o, - output logic [31:0] pc_plus_4_d_o, - output logic [31:0] instr_d_o -); - - logic [31:0] pc_next_f, real_pc_next_f, pc_branch_next_f, pc_plus_4_f; - - // PC logic - fetch_reg u_fetch_reg ( - .clk_i, - .rst_i, - .stall_f_i, - .pc_next_f_i(real_pc_next_f), - .pc_f_o - ); - adder u_adder ( - .a_i(pc_f_o), - .b_i(32'd4), - .result_o(pc_plus_4_f) - ); - mux2 pc_branch_next_mux2 ( - .data0_i(pc_plus_4_d_o), - .data1_i(pc_branch_d_i), - .select_i(pc_src_d_i), - .result_o(pc_branch_next_f) - ); - mux4 pc_next_mux4 ( - .data0_i(pc_branch_next_f), - .data1_i({pc_plus_4_d_o[31:28], instr_d_o[25:0], 2'b00}), // word aligned - .data2_i(src_a_d_i), // the value in register $ra - .data3_i(), // not used - .select_i(jump_d_i[1:0]), - .result_o(pc_next_f) - ); - mux2 real_pc_next_mux2 ( - .data0_i(predict_pc_i), - .data1_i(pc_next_f), - .select_i(predict_miss_i | jump_d_i[1]), // wrong prediction or JR - .result_o(real_pc_next_f) - ); - - // Decode stage pipeline register logic - decode_reg u_decode_reg ( - .clk_i, - .rst_i, - .stall_d_i, - .flush_d_i, - .pc_plus_4_f_i(pc_plus_4_f), - .instr_f_i, - .pc_plus_4_d_o, - .instr_d_o - ); - -endmodule : fetch diff --git a/Cache/assets/test_1-4.png b/Cache/assets/test_1-4.png deleted file mode 100644 index 624646f..0000000 Binary files a/Cache/assets/test_1-4.png and /dev/null differ diff --git a/Cache/assets/test_5-8.png b/Cache/assets/test_5-8.png deleted file mode 100644 index d47ae9a..0000000 Binary files a/Cache/assets/test_5-8.png and /dev/null differ diff --git a/Cache/assets/test_9-11.png b/Cache/assets/test_9-11.png deleted file mode 100644 index 0d2f107..0000000 Binary files a/Cache/assets/test_9-11.png and /dev/null differ diff --git a/Cache/src/dmem.sv b/Cache/src/dmem.sv deleted file mode 100644 index 9ba103f..0000000 --- a/Cache/src/dmem.sv +++ /dev/null @@ -1,19 +0,0 @@ -`timescale 1ns / 1ps - -// Since our TA has hard-coded variable names into the grader, we have -// to name the variables like this, regardless of the coding style. - -// 32-bit data memory -module dmem ( - input clk, - input we, // mem_write_en - input [31:0] a, // mem_write_addr - input [31:0] wd, // mem_write_data - output logic [31:0] rd // mem_read_data -); - logic [31:0] RAM[127:0]; - always_ff @(posedge clk) begin - if (we) RAM[a[31:2]] <= wd; - end - assign rd = RAM[a[31:2]]; // word aligned -endmodule : dmem diff --git a/Cache/src/mips.sv b/Cache/src/mips.sv deleted file mode 100644 index fd8982f..0000000 --- a/Cache/src/mips.sv +++ /dev/null @@ -1,182 +0,0 @@ -`timescale 1ns / 1ps - -// Since our TA has hard-coded variable names into the grader, we have -// to name the variables like this, regardless of the coding style. - -// Pipeline 32-bit MIPS processor -module mips ( - input clk, - input reset, - input [31:0] instr, - input [31:0] readdata, - input ihit, - input dhit, - output logic [31:0] pc, - output logic memwrite, - output logic [31:0] aluout, - output logic [31:0] writedata, - output dcen -); - - logic [1:0] branch_d; - logic pc_src_d; - logic [31:0] pc_branch_d, pc_plus_4_d; - logic [31:0] src_a_d; - logic [2:0] jump_d; - logic [31:0] instr_d; - logic [4:0] rs_d, rt_d; - - logic reg_write_e, reg_dst_e; - logic [1:0] alu_src_e; - logic [3:0] alu_control_e; - logic [2:0] jump_e; - logic mem_write_e, mem_to_reg_e; - logic [31:0] pc_plus_4_e, reg_data_1_e, reg_data_2_e; - logic [4:0] rs_e, rt_e, rd_e, shamt_e, write_reg_e; - logic [31:0] ext_imm_e; - - logic reg_write_m, mem_to_reg_m; - logic [4:0] write_reg_m; - - logic reg_write_w, mem_to_reg_w; - logic [31:0] read_data_w, alu_out_w, result_w; - logic [4:0] write_reg_w; - - logic stall_f, stall_d, flush_d, flush_e; - logic forward_a_d, forward_b_d; - logic [1:0] forward_a_e, forward_b_e; - - assign dcen = memwrite | mem_to_reg_m; - - fetch u_fetch ( - .clk_i(clk), - .rst_i(reset), - .instr_f_i(instr), - .pc_branch_d_i(pc_branch_d), - .pc_src_d_i(pc_src_d), - .src_a_d_i(src_a_d), - .jump_d_i(jump_d), - .stall_f_i(stall_f), - .stall_d_i(stall_d), - .flush_d_i(flush_d), - .pc_f_o(pc), - .pc_plus_4_d_o(pc_plus_4_d), - .instr_d_o(instr_d) - ); - - decode u_decode ( - .clk_i(clk), - .rst_i(reset), - .pc_plus_4_d_i(pc_plus_4_d), - .instr_d_i(instr_d), - .alu_out_m_i(aluout), - .reg_write_w_i(reg_write_w), - .write_reg_w_i(write_reg_w), - .result_w_i(result_w), - .forward_a_d_i(forward_a_d), - .forward_b_d_i(forward_b_d), - .flush_e_i(flush_e), - .branch_d_o(branch_d), - .pc_src_d_o(pc_src_d), - .jump_d_o(jump_d), - .pc_branch_d_o(pc_branch_d), - .src_a_d_o(src_a_d), - .rs_d_o(rs_d), - .rt_d_o(rt_d), - .reg_write_e_o(reg_write_e), - .reg_dst_e_o(reg_dst_e), - .alu_src_e_o(alu_src_e), - .alu_control_e_o(alu_control_e), - .jump_e_o(jump_e), - .mem_write_e_o(mem_write_e), - .mem_to_reg_e_o(mem_to_reg_e), - .pc_plus_4_e_o(pc_plus_4_e), - .reg_data_1_e_o(reg_data_1_e), - .reg_data_2_e_o(reg_data_2_e), - .rs_e_o(rs_e), - .rt_e_o(rt_e), - .rd_e_o(rd_e), - .shamt_e_o(shamt_e), - .ext_imm_e_o(ext_imm_e) - ); - - execute u_execute ( - .clk_i(clk), - .rst_i(reset), - .reg_write_e_i(reg_write_e), - .reg_dst_e_i(reg_dst_e), - .alu_src_e_i(alu_src_e), - .alu_control_e_i(alu_control_e), - .jump_e_i(jump_e), - .mem_write_e_i(mem_write_e), - .mem_to_reg_e_i(mem_to_reg_e), - .pc_plus_4_e_i(pc_plus_4_e), - .reg_data_1_e_i(reg_data_1_e), - .reg_data_2_e_i(reg_data_2_e), - .rt_e_i(rt_e), - .rd_e_i(rd_e), - .shamt_e_i(shamt_e), - .ext_imm_e_i(ext_imm_e), - .result_w_i(result_w), - .forward_a_e_i(forward_a_e), - .forward_b_e_i(forward_b_e), - .write_reg_e_o(write_reg_e), - .reg_write_m_o(reg_write_m), - .mem_write_m_o(memwrite), - .mem_to_reg_m_o(mem_to_reg_m), - .alu_out_m_o(aluout), - .write_data_m_o(writedata), - .write_reg_m_o(write_reg_m) - ); - - memory u_memory ( - .clk_i(clk), - .rst_i(reset), - .reg_write_m_i(reg_write_m), - .mem_to_reg_m_i(mem_to_reg_m), - .alu_out_m_i(aluout), - .write_reg_m_i(write_reg_m), - .read_data_m_i(readdata), - .reg_write_w_o(reg_write_w), - .mem_to_reg_w_o(mem_to_reg_w), - .alu_out_w_o(alu_out_w), - .read_data_w_o(read_data_w), - .write_reg_w_o(write_reg_w) - ); - - writeback u_writeback ( - .clk_i(clk), - .rst_i(reset), - .mem_to_reg_w_i(mem_to_reg_w), - .alu_out_w_i(alu_out_w), - .read_data_w_i(read_data_w), - .result_w_o(result_w) - ); - - hazard_unit u_hazard_unit ( - .rs_d_i(rs_d), - .rt_d_i(rt_d), - .branch_d_i(branch_d), - .pc_src_d_i(pc_src_d), - .jump_d_i(jump_d), - .rs_e_i(rs_e), - .rt_e_i(rt_e), - .write_reg_e_i(write_reg_e), - .mem_to_reg_e_i(mem_to_reg_e), - .reg_write_e_i(reg_write_e), - .write_reg_m_i(write_reg_m), - .mem_to_reg_m_i(mem_to_reg_m), - .reg_write_m_i(reg_write_m), - .write_reg_w_i(write_reg_w), - .reg_write_w_i(reg_write_w), - .stall_f_o(stall_f), - .stall_d_o(stall_d), - .flush_d_o(flush_d), - .forward_a_d_o(forward_a_d), - .forward_b_d_o(forward_b_d), - .flush_e_o(flush_e), - .forward_a_e_o(forward_a_e), - .forward_b_e_o(forward_b_e) - ); - -endmodule : mips diff --git a/Pipeline/README.md b/Pipeline/1. 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a/Branch-Predictor/src/branch-predictor/ght.sv b/Pipeline/src/branch-predictor/ght.sv similarity index 100% rename from Branch-Predictor/src/branch-predictor/ght.sv rename to Pipeline/src/branch-predictor/ght.sv diff --git a/Branch-Predictor/src/branch-predictor/parser.sv b/Pipeline/src/branch-predictor/parser.sv similarity index 100% rename from Branch-Predictor/src/branch-predictor/parser.sv rename to Pipeline/src/branch-predictor/parser.sv diff --git a/Branch-Predictor/src/branch-predictor/pht.sv b/Pipeline/src/branch-predictor/pht.sv similarity index 100% rename from Branch-Predictor/src/branch-predictor/pht.sv rename to Pipeline/src/branch-predictor/pht.sv diff --git a/Branch-Predictor/src/branch-predictor/state_switch.sv b/Pipeline/src/branch-predictor/state_switch.sv similarity index 100% rename from Branch-Predictor/src/branch-predictor/state_switch.sv rename to Pipeline/src/branch-predictor/state_switch.sv diff --git a/Branch-Predictor/src/branch-predictor/static_predictor.sv b/Pipeline/src/branch-predictor/static_predictor.sv similarity index 100% rename from Branch-Predictor/src/branch-predictor/static_predictor.sv rename to Pipeline/src/branch-predictor/static_predictor.sv diff --git a/Branch-Predictor/src/branch-predictor/static_predictor.svh b/Pipeline/src/branch-predictor/static_predictor.svh similarity index 100% rename from Branch-Predictor/src/branch-predictor/static_predictor.svh rename to Pipeline/src/branch-predictor/static_predictor.svh diff --git a/Cache/src/cache/cache.sv b/Pipeline/src/cache/cache.sv similarity index 100% rename from Cache/src/cache/cache.sv rename to Pipeline/src/cache/cache.sv diff --git a/Cache/src/cache/cache.svh b/Pipeline/src/cache/cache.svh similarity index 100% rename from Cache/src/cache/cache.svh rename to Pipeline/src/cache/cache.svh diff --git a/Cache/src/cache/cache_controller.sv b/Pipeline/src/cache/cache_controller.sv similarity index 100% rename from Cache/src/cache/cache_controller.sv rename to Pipeline/src/cache/cache_controller.sv diff --git a/Cache/src/cache/cache_controller.svh b/Pipeline/src/cache/cache_controller.svh similarity index 100% rename from Cache/src/cache/cache_controller.svh rename to Pipeline/src/cache/cache_controller.svh diff --git a/Cache/src/cache/line.sv b/Pipeline/src/cache/line.sv similarity index 100% rename from Cache/src/cache/line.sv rename to Pipeline/src/cache/line.sv diff --git a/Cache/src/cache/replace_controller.sv b/Pipeline/src/cache/replace_controller.sv similarity index 100% rename from Cache/src/cache/replace_controller.sv rename to Pipeline/src/cache/replace_controller.sv diff --git a/Cache/src/cache/replace_controller.svh b/Pipeline/src/cache/replace_controller.svh similarity index 100% rename from Cache/src/cache/replace_controller.svh rename to Pipeline/src/cache/replace_controller.svh diff --git a/Cache/src/cache/set.sv b/Pipeline/src/cache/set.sv similarity index 100% rename from Cache/src/cache/set.sv rename to Pipeline/src/cache/set.sv diff --git a/Pipeline/src/dmem.sv b/Pipeline/src/dmem.sv index fd36bf7..9ba103f 100644 --- a/Pipeline/src/dmem.sv +++ b/Pipeline/src/dmem.sv @@ -11,7 +11,7 @@ module dmem ( input [31:0] wd, // mem_write_data output logic [31:0] rd // mem_read_data ); - logic [31:0] RAM[63:0]; + logic [31:0] RAM[127:0]; always_ff @(posedge clk) begin if (we) RAM[a[31:2]] <= wd; end diff --git a/Pipeline/src/hazard_unit.sv b/Pipeline/src/hazard_unit.sv index 8374da0..77785ba 100644 --- a/Pipeline/src/hazard_unit.sv +++ b/Pipeline/src/hazard_unit.sv @@ -2,6 +2,7 @@ // Hazard handler module hazard_unit ( + input predict_miss_i, input [4:0] rs_d_i, input [4:0] rt_d_i, input [1:0] branch_d_i, @@ -27,7 +28,7 @@ module hazard_unit ( output logic [1:0] forward_b_e_o ); - logic lw_stall, branch_stall; + logic lw_stall, branch_stall, branch_predict_stall; // Solves data hazards with forwarding always_comb begin @@ -60,8 +61,8 @@ module hazard_unit ( || mem_to_reg_m_i && (rs_d_i == write_reg_m_i || rt_d_i == write_reg_m_i)); assign stall_d_o = lw_stall || branch_stall; - assign flush_e_o = stall_d_o; - assign flush_d_o = pc_src_d_i || jump_d_i; + assign flush_e_o = stall_d_o || predict_miss_i; + assign flush_d_o = predict_miss_i || jump_d_i[1]; // wrong prediction or JR assign stall_f_o = stall_d_o; endmodule : hazard_unit diff --git a/Pipeline/src/mips.sv b/Pipeline/src/mips.sv index b8bd8ab..e083173 100644 --- a/Pipeline/src/mips.sv +++ b/Pipeline/src/mips.sv @@ -9,12 +9,19 @@ module mips ( input reset, input [31:0] instr, input [31:0] readdata, + input ihit, + input dhit, output logic [31:0] pc, output logic memwrite, output logic [31:0] aluout, - output logic [31:0] writedata + output logic [31:0] writedata, + output dcen ); + logic is_branch_d; + logic last_taken, predict_miss; + logic [31:0] predict_pc; + logic [1:0] branch_d; logic pc_src_d; logic [31:0] pc_branch_d, pc_plus_4_d; @@ -43,10 +50,30 @@ module mips ( logic forward_a_d, forward_b_d; logic [1:0] forward_a_e, forward_b_e; + assign dcen = memwrite | mem_to_reg_m; + + assign is_branch_d = |branch_d; + assign predict_miss = is_branch_d && pc_src_d != last_taken; + + bpb u_bpb ( + .clk_i(clk), + .rst_i(reset), + .en_i(~stall_f), + .pc_f_i(pc), + .instr_f_i(instr), + .is_branch_d_i(is_branch_d), + .miss_i(predict_miss), + .pc_branch_i(pc_branch_d), + .last_taken_o(last_taken), + .predict_pc_o(predict_pc) + ); + fetch u_fetch ( .clk_i(clk), .rst_i(reset), .instr_f_i(instr), + .predict_pc_i(predict_pc), + .predict_miss_i(predict_miss), .pc_branch_d_i(pc_branch_d), .pc_src_d_i(pc_src_d), .src_a_d_i(src_a_d), @@ -149,6 +176,7 @@ module mips ( ); hazard_unit u_hazard_unit ( + .predict_miss_i(predict_miss), .rs_d_i(rs_d), .rt_d_i(rt_d), .branch_d_i(branch_d), diff --git a/Pipeline/src/pipeline_stages/fetch.sv b/Pipeline/src/pipeline_stages/fetch.sv index 69bdac7..59b94de 100644 --- a/Pipeline/src/pipeline_stages/fetch.sv +++ b/Pipeline/src/pipeline_stages/fetch.sv @@ -3,6 +3,8 @@ module fetch ( input clk_i, input rst_i, + input [31:0] predict_pc_i, + input predict_miss_i, input [31:0] instr_f_i, input [31:0] pc_branch_d_i, input pc_src_d_i, @@ -16,14 +18,14 @@ module fetch ( output logic [31:0] instr_d_o ); - logic [31:0] pc_next_f, pc_branch_next_f, pc_plus_4_f; + logic [31:0] pc_next_f, real_pc_next_f, pc_branch_next_f, pc_plus_4_f; // PC logic fetch_reg u_fetch_reg ( .clk_i, .rst_i, .stall_f_i, - .pc_next_f_i(pc_next_f), + .pc_next_f_i(real_pc_next_f), .pc_f_o ); adder u_adder ( @@ -32,19 +34,25 @@ module fetch ( .result_o(pc_plus_4_f) ); mux2 pc_branch_next_mux2 ( - .data0_i(pc_plus_4_f), + .data0_i(pc_plus_4_d_o), .data1_i(pc_branch_d_i), .select_i(pc_src_d_i), .result_o(pc_branch_next_f) ); mux4 pc_next_mux4 ( .data0_i(pc_branch_next_f), - .data1_i({pc_plus_4_f[31:28], instr_d_o[25:0], 2'b00}), // word aligned + .data1_i({pc_plus_4_d_o[31:28], instr_d_o[25:0], 2'b00}), // word aligned .data2_i(src_a_d_i), // the value in register $ra .data3_i(), // not used .select_i(jump_d_i[1:0]), .result_o(pc_next_f) ); + mux2 real_pc_next_mux2 ( + .data0_i(predict_pc_i), + .data1_i(pc_next_f), + .select_i(predict_miss_i | jump_d_i[1]), // wrong prediction or JR + .result_o(real_pc_next_f) + ); // Decode stage pipeline register logic decode_reg u_decode_reg ( diff --git a/Single-Cycle/README.md b/Single-Cycle/0. Single-Cycle.md similarity index 100% rename from Single-Cycle/README.md rename to Single-Cycle/0. Single-Cycle.md