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ram_2_syn.v
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// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altsyncram ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" DEVICE_FAMILY="Cyclone II" INDATA_REG_B="CLOCK1" INIT_FILE="../MEMINIT.MIF" NUMWORDS_A=65536 NUMWORDS_B=65536 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="CLOCK0" OUTDATA_REG_B="CLOCK1" POWER_UP_UNINITIALIZED="FALSE" WIDTH_A=1 WIDTH_B=1 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=16 WIDTHAD_B=16 WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 data_a data_b q_a q_b wren_a wren_b
//VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//lpm_decode DEVICE_FAMILY="Cyclone II" LPM_DECODES=16 LPM_WIDTH=4 data enable eq
//VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END
//synthesis_resources = lut 18
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module ram_2_decode
(
data,
enable,
eq) /* synthesis synthesis_clearbox=1 */;
input [3:0] data;
input enable;
output [15:0] eq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [3:0] data;
tri1 enable;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] data_wire;
wire enable_wire;
wire [15:0] eq_node;
wire [15:0] eq_wire;
wire [1:0] w_anode269w;
wire [3:0] w_anode278w;
wire [3:0] w_anode295w;
wire [3:0] w_anode305w;
wire [3:0] w_anode315w;
wire [3:0] w_anode325w;
wire [3:0] w_anode335w;
wire [3:0] w_anode345w;
wire [3:0] w_anode355w;
wire [1:0] w_anode367w;
wire [3:0] w_anode374w;
wire [3:0] w_anode385w;
wire [3:0] w_anode395w;
wire [3:0] w_anode405w;
wire [3:0] w_anode415w;
wire [3:0] w_anode425w;
wire [3:0] w_anode435w;
wire [3:0] w_anode445w;
wire [2:0] w_data267w;
assign
data_wire = data,
enable_wire = enable,
eq = eq_node,
eq_node = eq_wire[15:0],
eq_wire = {{w_anode445w[3], w_anode435w[3], w_anode425w[3], w_anode415w[3], w_anode405w[3], w_anode395w[3], w_anode385w[3], w_anode374w[3]}, {w_anode355w[3], w_anode345w[3], w_anode335w[3], w_anode325w[3], w_anode315w[3], w_anode305w[3], w_anode295w[3], w_anode278w[3]}},
w_anode269w = {(w_anode269w[0] & (~ data_wire[3])), enable_wire},
w_anode278w = {(w_anode278w[2] & (~ w_data267w[2])), (w_anode278w[1] & (~ w_data267w[1])), (w_anode278w[0] & (~ w_data267w[0])), w_anode269w[1]},
w_anode295w = {(w_anode295w[2] & (~ w_data267w[2])), (w_anode295w[1] & (~ w_data267w[1])), (w_anode295w[0] & w_data267w[0]), w_anode269w[1]},
w_anode305w = {(w_anode305w[2] & (~ w_data267w[2])), (w_anode305w[1] & w_data267w[1]), (w_anode305w[0] & (~ w_data267w[0])), w_anode269w[1]},
w_anode315w = {(w_anode315w[2] & (~ w_data267w[2])), (w_anode315w[1] & w_data267w[1]), (w_anode315w[0] & w_data267w[0]), w_anode269w[1]},
w_anode325w = {(w_anode325w[2] & w_data267w[2]), (w_anode325w[1] & (~ w_data267w[1])), (w_anode325w[0] & (~ w_data267w[0])), w_anode269w[1]},
w_anode335w = {(w_anode335w[2] & w_data267w[2]), (w_anode335w[1] & (~ w_data267w[1])), (w_anode335w[0] & w_data267w[0]), w_anode269w[1]},
w_anode345w = {(w_anode345w[2] & w_data267w[2]), (w_anode345w[1] & w_data267w[1]), (w_anode345w[0] & (~ w_data267w[0])), w_anode269w[1]},
w_anode355w = {(w_anode355w[2] & w_data267w[2]), (w_anode355w[1] & w_data267w[1]), (w_anode355w[0] & w_data267w[0]), w_anode269w[1]},
w_anode367w = {(w_anode367w[0] & data_wire[3]), enable_wire},
w_anode374w = {(w_anode374w[2] & (~ w_data267w[2])), (w_anode374w[1] & (~ w_data267w[1])), (w_anode374w[0] & (~ w_data267w[0])), w_anode367w[1]},
w_anode385w = {(w_anode385w[2] & (~ w_data267w[2])), (w_anode385w[1] & (~ w_data267w[1])), (w_anode385w[0] & w_data267w[0]), w_anode367w[1]},
w_anode395w = {(w_anode395w[2] & (~ w_data267w[2])), (w_anode395w[1] & w_data267w[1]), (w_anode395w[0] & (~ w_data267w[0])), w_anode367w[1]},
w_anode405w = {(w_anode405w[2] & (~ w_data267w[2])), (w_anode405w[1] & w_data267w[1]), (w_anode405w[0] & w_data267w[0]), w_anode367w[1]},
w_anode415w = {(w_anode415w[2] & w_data267w[2]), (w_anode415w[1] & (~ w_data267w[1])), (w_anode415w[0] & (~ w_data267w[0])), w_anode367w[1]},
w_anode425w = {(w_anode425w[2] & w_data267w[2]), (w_anode425w[1] & (~ w_data267w[1])), (w_anode425w[0] & w_data267w[0]), w_anode367w[1]},
w_anode435w = {(w_anode435w[2] & w_data267w[2]), (w_anode435w[1] & w_data267w[1]), (w_anode435w[0] & (~ w_data267w[0])), w_anode367w[1]},
w_anode445w = {(w_anode445w[2] & w_data267w[2]), (w_anode445w[1] & w_data267w[1]), (w_anode445w[0] & w_data267w[0]), w_anode367w[1]},
w_data267w = data_wire[2:0];
endmodule //ram_2_decode
//lpm_mux DEVICE_FAMILY="Cyclone II" LPM_SIZE=16 LPM_WIDTH=1 LPM_WIDTHS=4 data result sel
//VERSION_BEGIN 13.0 cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ VERSION_END
//synthesis_resources = lut 10
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module ram_2_mux
(
data,
result,
sel) /* synthesis synthesis_clearbox=1 */;
input [15:0] data;
output [0:0] result;
input [3:0] sel;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [15:0] data;
tri0 [3:0] sel;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] result_node;
wire [3:0] sel_ffs_wire;
wire [3:0] sel_node;
wire [15:0] w_data465w;
wire [3:0] w_data520w;
wire [3:0] w_data521w;
wire [3:0] w_data522w;
wire [3:0] w_data523w;
wire [1:0] w_sel524w;
assign
result = result_node,
result_node = {((((((w_data521w[1] & w_sel524w[0]) & (~ (((w_data521w[0] & (~ w_sel524w[1])) & (~ w_sel524w[0])) | (w_sel524w[1] & (w_sel524w[0] | w_data521w[2]))))) | ((((w_data521w[0] & (~ w_sel524w[1])) & (~ w_sel524w[0])) | (w_sel524w[1] & (w_sel524w[0] | w_data521w[2]))) & (w_data521w[3] | (~ w_sel524w[0])))) & sel_node[2]) & (~ ((((((w_data520w[1] & w_sel524w[0]) & (~ (((w_data520w[0] & (~ w_sel524w[1])) & (~ w_sel524w[0])) | (w_sel524w[1] & (w_sel524w[0] | w_data520w[2]))))) | ((((w_data520w[0] & (~ w_sel524w[1])) & (~ w_sel524w[0])) | (w_sel524w[1] & (w_sel524w[0] | w_data520w[2]))) & (w_data520w[3] | (~ w_sel524w[0])))) & (~ sel_node[3])) & (~ sel_node[2])) | (sel_node[3] & (sel_node[2] | (((w_data522w[1] & w_sel524w[0]) & (~ (((w_data522w[0] & (~ w_sel524w[1])) & (~ w_sel524w[0])) | (w_sel524w[1] & (w_sel524w[0] | w_data522w[2]))))) | ((((w_data522w[0] & (~ w_sel524w[1])) & (~ w_sel524w[0])) | (w_sel524w[1] & (w_sel524w[0] | w_data522w[2]))) & (w_data522w[3] | (~ w_sel524w[0]))))))))) | (((((((w_data520w[1] & w_sel524w[0]) & (~ (((w_data520w[0] & (~ w_sel524w[1])) & (~ w_sel524w[0])) | (w_sel524w[1] & (w_sel524w[0] | w_data520w[2]))))) | ((((w_data520w[0] & (~ w_sel524w[1])) & (~ w_sel524w[0])) | (w_sel524w[1] & (w_sel524w[0] | w_data520w[2]))) & (w_data520w[3] | (~ w_sel524w[0])))) & (~ sel_node[3])) & (~ sel_node[2])) | (sel_node[3] & (sel_node[2] | (((w_data522w[1] & w_sel524w[0]) & (~ (((w_data522w[0] & (~ w_sel524w[1])) & (~ w_sel524w[0])) | (w_sel524w[1] & (w_sel524w[0] | w_data522w[2]))))) | ((((w_data522w[0] & (~ w_sel524w[1])) & (~ w_sel524w[0])) | (w_sel524w[1] & (w_sel524w[0] | w_data522w[2]))) & (w_data522w[3] | (~ w_sel524w[0]))))))) & ((((w_data523w[1] & w_sel524w[0]) & (~ (((w_data523w[0] & (~ w_sel524w[1])) & (~ w_sel524w[0])) | (w_sel524w[1] & (w_sel524w[0] | w_data523w[2]))))) | ((((w_data523w[0] & (~ w_sel524w[1])) & (~ w_sel524w[0])) | (w_sel524w[1] & (w_sel524w[0] | w_data523w[2]))) & (w_data523w[3] | (~ w_sel524w[0])))) | (~ sel_node[2]))))},
sel_ffs_wire = {sel[3:0]},
sel_node = {sel_ffs_wire[3:2], sel[1:0]},
w_data465w = {data[15:0]},
w_data520w = w_data465w[3:0],
w_data521w = w_data465w[7:4],
w_data522w = w_data465w[11:8],
w_data523w = w_data465w[15:12],
w_sel524w = sel_node[1:0];
endmodule //ram_2_mux
//synthesis_resources = lut 92 M4K 16 reg 16
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"} *)
module ram_2_altsyncram
(
address_a,
address_b,
clock0,
clock1,
data_a,
data_b,
q_a,
q_b,
wren_a,
wren_b) /* synthesis synthesis_clearbox=1 */;
input [15:0] address_a;
input [15:0] address_b;
input clock0;
input clock1;
input [0:0] data_a;
input [0:0] data_b;
output [0:0] q_a;
output [0:0] q_b;
input wren_a;
input wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [15:0] address_b;
tri1 clock0;
tri1 clock1;
tri1 [0:0] data_a;
tri1 [0:0] data_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [3:0] address_reg_a;
reg [3:0] address_reg_b;
reg [3:0] out_address_reg_a;
reg [3:0] out_address_reg_b;
wire [15:0] wire_decode2_eq;
wire [15:0] wire_decode3_eq;
wire [15:0] wire_decode_a_eq;
wire [15:0] wire_decode_b_eq;
wire [0:0] wire_mux4_result;
wire [0:0] wire_mux5_result;
wire [0:0] wire_ram_block1a_0portadataout;
wire [0:0] wire_ram_block1a_1portadataout;
wire [0:0] wire_ram_block1a_2portadataout;
wire [0:0] wire_ram_block1a_3portadataout;
wire [0:0] wire_ram_block1a_4portadataout;
wire [0:0] wire_ram_block1a_5portadataout;
wire [0:0] wire_ram_block1a_6portadataout;
wire [0:0] wire_ram_block1a_7portadataout;
wire [0:0] wire_ram_block1a_8portadataout;
wire [0:0] wire_ram_block1a_9portadataout;
wire [0:0] wire_ram_block1a_10portadataout;
wire [0:0] wire_ram_block1a_11portadataout;
wire [0:0] wire_ram_block1a_12portadataout;
wire [0:0] wire_ram_block1a_13portadataout;
wire [0:0] wire_ram_block1a_14portadataout;
wire [0:0] wire_ram_block1a_15portadataout;
wire [0:0] wire_ram_block1a_0portbdataout;
wire [0:0] wire_ram_block1a_1portbdataout;
wire [0:0] wire_ram_block1a_2portbdataout;
wire [0:0] wire_ram_block1a_3portbdataout;
wire [0:0] wire_ram_block1a_4portbdataout;
wire [0:0] wire_ram_block1a_5portbdataout;
wire [0:0] wire_ram_block1a_6portbdataout;
wire [0:0] wire_ram_block1a_7portbdataout;
wire [0:0] wire_ram_block1a_8portbdataout;
wire [0:0] wire_ram_block1a_9portbdataout;
wire [0:0] wire_ram_block1a_10portbdataout;
wire [0:0] wire_ram_block1a_11portbdataout;
wire [0:0] wire_ram_block1a_12portbdataout;
wire [0:0] wire_ram_block1a_13portbdataout;
wire [0:0] wire_ram_block1a_14portbdataout;
wire [0:0] wire_ram_block1a_15portbdataout;
wire [3:0] address_a_sel;
wire [15:0] address_a_wire;
wire [3:0] address_b_sel;
wire [15:0] address_b_wire;
// synopsys translate_off
initial
address_reg_a = 0;
// synopsys translate_on
always @ ( posedge clock0)
address_reg_a <= address_a_sel;
// synopsys translate_off
initial
address_reg_b = 0;
// synopsys translate_on
always @ ( posedge clock1)
address_reg_b <= address_b_sel;
// synopsys translate_off
initial
out_address_reg_a = 0;
// synopsys translate_on
always @ ( posedge clock0)
out_address_reg_a <= address_reg_a;
// synopsys translate_off
initial
out_address_reg_b = 0;
// synopsys translate_on
always @ ( posedge clock1)
out_address_reg_b <= address_reg_b;
ram_2_decode decode2
(
.data(address_a_wire[15:12]),
.enable(wren_a),
.eq(wire_decode2_eq));
ram_2_decode decode3
(
.data(address_b_wire[15:12]),
.enable(wren_b),
.eq(wire_decode3_eq));
ram_2_decode decode_a
(
.data(address_a_wire[15:12]),
.enable(1'b1),
.eq(wire_decode_a_eq));
ram_2_decode decode_b
(
.data(address_b_wire[15:12]),
.enable(1'b1),
.eq(wire_decode_b_eq));
ram_2_mux mux4
(
.data({wire_ram_block1a_15portadataout[0], wire_ram_block1a_14portadataout[0], wire_ram_block1a_13portadataout[0], wire_ram_block1a_12portadataout[0], wire_ram_block1a_11portadataout[0], wire_ram_block1a_10portadataout[0], wire_ram_block1a_9portadataout[0], wire_ram_block1a_8portadataout[0], wire_ram_block1a_7portadataout[0], wire_ram_block1a_6portadataout[0], wire_ram_block1a_5portadataout[0], wire_ram_block1a_4portadataout[0], wire_ram_block1a_3portadataout[0], wire_ram_block1a_2portadataout[0], wire_ram_block1a_1portadataout[0], wire_ram_block1a_0portadataout[0]}),
.result(wire_mux4_result),
.sel(out_address_reg_a));
ram_2_mux mux5
(
.data({wire_ram_block1a_15portbdataout[0], wire_ram_block1a_14portbdataout[0], wire_ram_block1a_13portbdataout[0], wire_ram_block1a_12portbdataout[0], wire_ram_block1a_11portbdataout[0], wire_ram_block1a_10portbdataout[0], wire_ram_block1a_9portbdataout[0], wire_ram_block1a_8portbdataout[0], wire_ram_block1a_7portbdataout[0], wire_ram_block1a_6portbdataout[0], wire_ram_block1a_5portbdataout[0], wire_ram_block1a_4portbdataout[0], wire_ram_block1a_3portbdataout[0], wire_ram_block1a_2portbdataout[0], wire_ram_block1a_1portbdataout[0], wire_ram_block1a_0portbdataout[0]}),
.result(wire_mux5_result),
.sel(out_address_reg_b));
cycloneii_ram_block ram_block1a_0
(
.clk0(clock0),
.clk1(clock1),
.ena0(wire_decode_a_eq[0]),
.ena1(wire_decode_b_eq[0]),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(wire_ram_block1a_0portadataout[0:0]),
.portawe(wire_decode2_eq[0]),
.portbaddr({address_b_wire[11:0]}),
.portbdatain({data_b[0]}),
.portbdataout(wire_ram_block1a_0portbdataout[0:0]),
.portbrewe(wire_decode3_eq[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_0.connectivity_checking = "OFF",
ram_block1a_0.init_file = "../MEMINIT.MIF",
ram_block1a_0.init_file_layout = "port_a",
ram_block1a_0.logical_ram_name = "ALTSYNCRAM",
ram_block1a_0.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_0.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_0.mixed_port_feed_through_mode = "dont_care",
ram_block1a_0.operation_mode = "bidir_dual_port",
ram_block1a_0.port_a_address_width = 12,
ram_block1a_0.port_a_data_out_clear = "none",
ram_block1a_0.port_a_data_out_clock = "clock0",
ram_block1a_0.port_a_data_width = 1,
ram_block1a_0.port_a_disable_ce_on_input_registers = "off",
ram_block1a_0.port_a_disable_ce_on_output_registers = "on",
ram_block1a_0.port_a_first_address = 0,
ram_block1a_0.port_a_first_bit_number = 0,
ram_block1a_0.port_a_last_address = 4095,
ram_block1a_0.port_a_logical_ram_depth = 65536,
ram_block1a_0.port_a_logical_ram_width = 1,
ram_block1a_0.port_b_address_clock = "clock1",
ram_block1a_0.port_b_address_width = 12,
ram_block1a_0.port_b_data_in_clock = "clock1",
ram_block1a_0.port_b_data_out_clear = "none",
ram_block1a_0.port_b_data_out_clock = "clock1",
ram_block1a_0.port_b_data_width = 1,
ram_block1a_0.port_b_disable_ce_on_input_registers = "off",
ram_block1a_0.port_b_disable_ce_on_output_registers = "on",
ram_block1a_0.port_b_first_address = 0,
ram_block1a_0.port_b_first_bit_number = 0,
ram_block1a_0.port_b_last_address = 4095,
ram_block1a_0.port_b_logical_ram_depth = 65536,
ram_block1a_0.port_b_logical_ram_width = 1,
ram_block1a_0.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_0.power_up_uninitialized = "false",
ram_block1a_0.ram_block_type = "AUTO",
ram_block1a_0.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_1
(
.clk0(clock0),
.clk1(clock1),
.ena0(wire_decode_a_eq[1]),
.ena1(wire_decode_b_eq[1]),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(wire_ram_block1a_1portadataout[0:0]),
.portawe(wire_decode2_eq[1]),
.portbaddr({address_b_wire[11:0]}),
.portbdatain({data_b[0]}),
.portbdataout(wire_ram_block1a_1portbdataout[0:0]),
.portbrewe(wire_decode3_eq[1])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_1.connectivity_checking = "OFF",
ram_block1a_1.init_file = "../MEMINIT.MIF",
ram_block1a_1.init_file_layout = "port_a",
ram_block1a_1.logical_ram_name = "ALTSYNCRAM",
ram_block1a_1.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_1.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_1.mixed_port_feed_through_mode = "dont_care",
ram_block1a_1.operation_mode = "bidir_dual_port",
ram_block1a_1.port_a_address_width = 12,
ram_block1a_1.port_a_data_out_clear = "none",
ram_block1a_1.port_a_data_out_clock = "clock0",
ram_block1a_1.port_a_data_width = 1,
ram_block1a_1.port_a_disable_ce_on_input_registers = "off",
ram_block1a_1.port_a_disable_ce_on_output_registers = "on",
ram_block1a_1.port_a_first_address = 4096,
ram_block1a_1.port_a_first_bit_number = 0,
ram_block1a_1.port_a_last_address = 8191,
ram_block1a_1.port_a_logical_ram_depth = 65536,
ram_block1a_1.port_a_logical_ram_width = 1,
ram_block1a_1.port_b_address_clock = "clock1",
ram_block1a_1.port_b_address_width = 12,
ram_block1a_1.port_b_data_in_clock = "clock1",
ram_block1a_1.port_b_data_out_clear = "none",
ram_block1a_1.port_b_data_out_clock = "clock1",
ram_block1a_1.port_b_data_width = 1,
ram_block1a_1.port_b_disable_ce_on_input_registers = "off",
ram_block1a_1.port_b_disable_ce_on_output_registers = "on",
ram_block1a_1.port_b_first_address = 4096,
ram_block1a_1.port_b_first_bit_number = 0,
ram_block1a_1.port_b_last_address = 8191,
ram_block1a_1.port_b_logical_ram_depth = 65536,
ram_block1a_1.port_b_logical_ram_width = 1,
ram_block1a_1.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_1.power_up_uninitialized = "false",
ram_block1a_1.ram_block_type = "AUTO",
ram_block1a_1.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_2
(
.clk0(clock0),
.clk1(clock1),
.ena0(wire_decode_a_eq[2]),
.ena1(wire_decode_b_eq[2]),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(wire_ram_block1a_2portadataout[0:0]),
.portawe(wire_decode2_eq[2]),
.portbaddr({address_b_wire[11:0]}),
.portbdatain({data_b[0]}),
.portbdataout(wire_ram_block1a_2portbdataout[0:0]),
.portbrewe(wire_decode3_eq[2])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_2.connectivity_checking = "OFF",
ram_block1a_2.init_file = "../MEMINIT.MIF",
ram_block1a_2.init_file_layout = "port_a",
ram_block1a_2.logical_ram_name = "ALTSYNCRAM",
ram_block1a_2.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_2.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_2.mixed_port_feed_through_mode = "dont_care",
ram_block1a_2.operation_mode = "bidir_dual_port",
ram_block1a_2.port_a_address_width = 12,
ram_block1a_2.port_a_data_out_clear = "none",
ram_block1a_2.port_a_data_out_clock = "clock0",
ram_block1a_2.port_a_data_width = 1,
ram_block1a_2.port_a_disable_ce_on_input_registers = "off",
ram_block1a_2.port_a_disable_ce_on_output_registers = "on",
ram_block1a_2.port_a_first_address = 8192,
ram_block1a_2.port_a_first_bit_number = 0,
ram_block1a_2.port_a_last_address = 12287,
ram_block1a_2.port_a_logical_ram_depth = 65536,
ram_block1a_2.port_a_logical_ram_width = 1,
ram_block1a_2.port_b_address_clock = "clock1",
ram_block1a_2.port_b_address_width = 12,
ram_block1a_2.port_b_data_in_clock = "clock1",
ram_block1a_2.port_b_data_out_clear = "none",
ram_block1a_2.port_b_data_out_clock = "clock1",
ram_block1a_2.port_b_data_width = 1,
ram_block1a_2.port_b_disable_ce_on_input_registers = "off",
ram_block1a_2.port_b_disable_ce_on_output_registers = "on",
ram_block1a_2.port_b_first_address = 8192,
ram_block1a_2.port_b_first_bit_number = 0,
ram_block1a_2.port_b_last_address = 12287,
ram_block1a_2.port_b_logical_ram_depth = 65536,
ram_block1a_2.port_b_logical_ram_width = 1,
ram_block1a_2.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_2.power_up_uninitialized = "false",
ram_block1a_2.ram_block_type = "AUTO",
ram_block1a_2.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_3
(
.clk0(clock0),
.clk1(clock1),
.ena0(wire_decode_a_eq[3]),
.ena1(wire_decode_b_eq[3]),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(wire_ram_block1a_3portadataout[0:0]),
.portawe(wire_decode2_eq[3]),
.portbaddr({address_b_wire[11:0]}),
.portbdatain({data_b[0]}),
.portbdataout(wire_ram_block1a_3portbdataout[0:0]),
.portbrewe(wire_decode3_eq[3])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_3.connectivity_checking = "OFF",
ram_block1a_3.init_file = "../MEMINIT.MIF",
ram_block1a_3.init_file_layout = "port_a",
ram_block1a_3.logical_ram_name = "ALTSYNCRAM",
ram_block1a_3.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_3.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_3.mixed_port_feed_through_mode = "dont_care",
ram_block1a_3.operation_mode = "bidir_dual_port",
ram_block1a_3.port_a_address_width = 12,
ram_block1a_3.port_a_data_out_clear = "none",
ram_block1a_3.port_a_data_out_clock = "clock0",
ram_block1a_3.port_a_data_width = 1,
ram_block1a_3.port_a_disable_ce_on_input_registers = "off",
ram_block1a_3.port_a_disable_ce_on_output_registers = "on",
ram_block1a_3.port_a_first_address = 12288,
ram_block1a_3.port_a_first_bit_number = 0,
ram_block1a_3.port_a_last_address = 16383,
ram_block1a_3.port_a_logical_ram_depth = 65536,
ram_block1a_3.port_a_logical_ram_width = 1,
ram_block1a_3.port_b_address_clock = "clock1",
ram_block1a_3.port_b_address_width = 12,
ram_block1a_3.port_b_data_in_clock = "clock1",
ram_block1a_3.port_b_data_out_clear = "none",
ram_block1a_3.port_b_data_out_clock = "clock1",
ram_block1a_3.port_b_data_width = 1,
ram_block1a_3.port_b_disable_ce_on_input_registers = "off",
ram_block1a_3.port_b_disable_ce_on_output_registers = "on",
ram_block1a_3.port_b_first_address = 12288,
ram_block1a_3.port_b_first_bit_number = 0,
ram_block1a_3.port_b_last_address = 16383,
ram_block1a_3.port_b_logical_ram_depth = 65536,
ram_block1a_3.port_b_logical_ram_width = 1,
ram_block1a_3.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_3.power_up_uninitialized = "false",
ram_block1a_3.ram_block_type = "AUTO",
ram_block1a_3.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_4
(
.clk0(clock0),
.clk1(clock1),
.ena0(wire_decode_a_eq[4]),
.ena1(wire_decode_b_eq[4]),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(wire_ram_block1a_4portadataout[0:0]),
.portawe(wire_decode2_eq[4]),
.portbaddr({address_b_wire[11:0]}),
.portbdatain({data_b[0]}),
.portbdataout(wire_ram_block1a_4portbdataout[0:0]),
.portbrewe(wire_decode3_eq[4])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_4.connectivity_checking = "OFF",
ram_block1a_4.init_file = "../MEMINIT.MIF",
ram_block1a_4.init_file_layout = "port_a",
ram_block1a_4.logical_ram_name = "ALTSYNCRAM",
ram_block1a_4.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_4.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_4.mixed_port_feed_through_mode = "dont_care",
ram_block1a_4.operation_mode = "bidir_dual_port",
ram_block1a_4.port_a_address_width = 12,
ram_block1a_4.port_a_data_out_clear = "none",
ram_block1a_4.port_a_data_out_clock = "clock0",
ram_block1a_4.port_a_data_width = 1,
ram_block1a_4.port_a_disable_ce_on_input_registers = "off",
ram_block1a_4.port_a_disable_ce_on_output_registers = "on",
ram_block1a_4.port_a_first_address = 16384,
ram_block1a_4.port_a_first_bit_number = 0,
ram_block1a_4.port_a_last_address = 20479,
ram_block1a_4.port_a_logical_ram_depth = 65536,
ram_block1a_4.port_a_logical_ram_width = 1,
ram_block1a_4.port_b_address_clock = "clock1",
ram_block1a_4.port_b_address_width = 12,
ram_block1a_4.port_b_data_in_clock = "clock1",
ram_block1a_4.port_b_data_out_clear = "none",
ram_block1a_4.port_b_data_out_clock = "clock1",
ram_block1a_4.port_b_data_width = 1,
ram_block1a_4.port_b_disable_ce_on_input_registers = "off",
ram_block1a_4.port_b_disable_ce_on_output_registers = "on",
ram_block1a_4.port_b_first_address = 16384,
ram_block1a_4.port_b_first_bit_number = 0,
ram_block1a_4.port_b_last_address = 20479,
ram_block1a_4.port_b_logical_ram_depth = 65536,
ram_block1a_4.port_b_logical_ram_width = 1,
ram_block1a_4.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_4.power_up_uninitialized = "false",
ram_block1a_4.ram_block_type = "AUTO",
ram_block1a_4.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_5
(
.clk0(clock0),
.clk1(clock1),
.ena0(wire_decode_a_eq[5]),
.ena1(wire_decode_b_eq[5]),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(wire_ram_block1a_5portadataout[0:0]),
.portawe(wire_decode2_eq[5]),
.portbaddr({address_b_wire[11:0]}),
.portbdatain({data_b[0]}),
.portbdataout(wire_ram_block1a_5portbdataout[0:0]),
.portbrewe(wire_decode3_eq[5])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_5.connectivity_checking = "OFF",
ram_block1a_5.init_file = "../MEMINIT.MIF",
ram_block1a_5.init_file_layout = "port_a",
ram_block1a_5.logical_ram_name = "ALTSYNCRAM",
ram_block1a_5.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_5.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_5.mixed_port_feed_through_mode = "dont_care",
ram_block1a_5.operation_mode = "bidir_dual_port",
ram_block1a_5.port_a_address_width = 12,
ram_block1a_5.port_a_data_out_clear = "none",
ram_block1a_5.port_a_data_out_clock = "clock0",
ram_block1a_5.port_a_data_width = 1,
ram_block1a_5.port_a_disable_ce_on_input_registers = "off",
ram_block1a_5.port_a_disable_ce_on_output_registers = "on",
ram_block1a_5.port_a_first_address = 20480,
ram_block1a_5.port_a_first_bit_number = 0,
ram_block1a_5.port_a_last_address = 24575,
ram_block1a_5.port_a_logical_ram_depth = 65536,
ram_block1a_5.port_a_logical_ram_width = 1,
ram_block1a_5.port_b_address_clock = "clock1",
ram_block1a_5.port_b_address_width = 12,
ram_block1a_5.port_b_data_in_clock = "clock1",
ram_block1a_5.port_b_data_out_clear = "none",
ram_block1a_5.port_b_data_out_clock = "clock1",
ram_block1a_5.port_b_data_width = 1,
ram_block1a_5.port_b_disable_ce_on_input_registers = "off",
ram_block1a_5.port_b_disable_ce_on_output_registers = "on",
ram_block1a_5.port_b_first_address = 20480,
ram_block1a_5.port_b_first_bit_number = 0,
ram_block1a_5.port_b_last_address = 24575,
ram_block1a_5.port_b_logical_ram_depth = 65536,
ram_block1a_5.port_b_logical_ram_width = 1,
ram_block1a_5.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_5.power_up_uninitialized = "false",
ram_block1a_5.ram_block_type = "AUTO",
ram_block1a_5.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_6
(
.clk0(clock0),
.clk1(clock1),
.ena0(wire_decode_a_eq[6]),
.ena1(wire_decode_b_eq[6]),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(wire_ram_block1a_6portadataout[0:0]),
.portawe(wire_decode2_eq[6]),
.portbaddr({address_b_wire[11:0]}),
.portbdatain({data_b[0]}),
.portbdataout(wire_ram_block1a_6portbdataout[0:0]),
.portbrewe(wire_decode3_eq[6])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_6.connectivity_checking = "OFF",
ram_block1a_6.init_file = "../MEMINIT.MIF",
ram_block1a_6.init_file_layout = "port_a",
ram_block1a_6.logical_ram_name = "ALTSYNCRAM",
ram_block1a_6.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_6.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_6.mixed_port_feed_through_mode = "dont_care",
ram_block1a_6.operation_mode = "bidir_dual_port",
ram_block1a_6.port_a_address_width = 12,
ram_block1a_6.port_a_data_out_clear = "none",
ram_block1a_6.port_a_data_out_clock = "clock0",
ram_block1a_6.port_a_data_width = 1,
ram_block1a_6.port_a_disable_ce_on_input_registers = "off",
ram_block1a_6.port_a_disable_ce_on_output_registers = "on",
ram_block1a_6.port_a_first_address = 24576,
ram_block1a_6.port_a_first_bit_number = 0,
ram_block1a_6.port_a_last_address = 28671,
ram_block1a_6.port_a_logical_ram_depth = 65536,
ram_block1a_6.port_a_logical_ram_width = 1,
ram_block1a_6.port_b_address_clock = "clock1",
ram_block1a_6.port_b_address_width = 12,
ram_block1a_6.port_b_data_in_clock = "clock1",
ram_block1a_6.port_b_data_out_clear = "none",
ram_block1a_6.port_b_data_out_clock = "clock1",
ram_block1a_6.port_b_data_width = 1,
ram_block1a_6.port_b_disable_ce_on_input_registers = "off",
ram_block1a_6.port_b_disable_ce_on_output_registers = "on",
ram_block1a_6.port_b_first_address = 24576,
ram_block1a_6.port_b_first_bit_number = 0,
ram_block1a_6.port_b_last_address = 28671,
ram_block1a_6.port_b_logical_ram_depth = 65536,
ram_block1a_6.port_b_logical_ram_width = 1,
ram_block1a_6.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_6.power_up_uninitialized = "false",
ram_block1a_6.ram_block_type = "AUTO",
ram_block1a_6.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_7
(
.clk0(clock0),
.clk1(clock1),
.ena0(wire_decode_a_eq[7]),
.ena1(wire_decode_b_eq[7]),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(wire_ram_block1a_7portadataout[0:0]),
.portawe(wire_decode2_eq[7]),
.portbaddr({address_b_wire[11:0]}),
.portbdatain({data_b[0]}),
.portbdataout(wire_ram_block1a_7portbdataout[0:0]),
.portbrewe(wire_decode3_eq[7])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_7.connectivity_checking = "OFF",
ram_block1a_7.init_file = "../MEMINIT.MIF",
ram_block1a_7.init_file_layout = "port_a",
ram_block1a_7.logical_ram_name = "ALTSYNCRAM",
ram_block1a_7.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_7.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_7.mixed_port_feed_through_mode = "dont_care",
ram_block1a_7.operation_mode = "bidir_dual_port",
ram_block1a_7.port_a_address_width = 12,
ram_block1a_7.port_a_data_out_clear = "none",
ram_block1a_7.port_a_data_out_clock = "clock0",
ram_block1a_7.port_a_data_width = 1,
ram_block1a_7.port_a_disable_ce_on_input_registers = "off",
ram_block1a_7.port_a_disable_ce_on_output_registers = "on",
ram_block1a_7.port_a_first_address = 28672,
ram_block1a_7.port_a_first_bit_number = 0,
ram_block1a_7.port_a_last_address = 32767,
ram_block1a_7.port_a_logical_ram_depth = 65536,
ram_block1a_7.port_a_logical_ram_width = 1,
ram_block1a_7.port_b_address_clock = "clock1",
ram_block1a_7.port_b_address_width = 12,
ram_block1a_7.port_b_data_in_clock = "clock1",
ram_block1a_7.port_b_data_out_clear = "none",
ram_block1a_7.port_b_data_out_clock = "clock1",
ram_block1a_7.port_b_data_width = 1,
ram_block1a_7.port_b_disable_ce_on_input_registers = "off",
ram_block1a_7.port_b_disable_ce_on_output_registers = "on",
ram_block1a_7.port_b_first_address = 28672,
ram_block1a_7.port_b_first_bit_number = 0,
ram_block1a_7.port_b_last_address = 32767,
ram_block1a_7.port_b_logical_ram_depth = 65536,
ram_block1a_7.port_b_logical_ram_width = 1,
ram_block1a_7.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_7.power_up_uninitialized = "false",
ram_block1a_7.ram_block_type = "AUTO",
ram_block1a_7.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_8
(
.clk0(clock0),
.clk1(clock1),
.ena0(wire_decode_a_eq[8]),
.ena1(wire_decode_b_eq[8]),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(wire_ram_block1a_8portadataout[0:0]),
.portawe(wire_decode2_eq[8]),
.portbaddr({address_b_wire[11:0]}),
.portbdatain({data_b[0]}),
.portbdataout(wire_ram_block1a_8portbdataout[0:0]),
.portbrewe(wire_decode3_eq[8])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_8.connectivity_checking = "OFF",
ram_block1a_8.init_file = "../MEMINIT.MIF",
ram_block1a_8.init_file_layout = "port_a",
ram_block1a_8.logical_ram_name = "ALTSYNCRAM",
ram_block1a_8.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_8.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_8.mixed_port_feed_through_mode = "dont_care",
ram_block1a_8.operation_mode = "bidir_dual_port",
ram_block1a_8.port_a_address_width = 12,
ram_block1a_8.port_a_data_out_clear = "none",
ram_block1a_8.port_a_data_out_clock = "clock0",
ram_block1a_8.port_a_data_width = 1,
ram_block1a_8.port_a_disable_ce_on_input_registers = "off",
ram_block1a_8.port_a_disable_ce_on_output_registers = "on",
ram_block1a_8.port_a_first_address = 32768,
ram_block1a_8.port_a_first_bit_number = 0,
ram_block1a_8.port_a_last_address = 36863,
ram_block1a_8.port_a_logical_ram_depth = 65536,
ram_block1a_8.port_a_logical_ram_width = 1,
ram_block1a_8.port_b_address_clock = "clock1",
ram_block1a_8.port_b_address_width = 12,
ram_block1a_8.port_b_data_in_clock = "clock1",
ram_block1a_8.port_b_data_out_clear = "none",
ram_block1a_8.port_b_data_out_clock = "clock1",
ram_block1a_8.port_b_data_width = 1,
ram_block1a_8.port_b_disable_ce_on_input_registers = "off",
ram_block1a_8.port_b_disable_ce_on_output_registers = "on",
ram_block1a_8.port_b_first_address = 32768,
ram_block1a_8.port_b_first_bit_number = 0,
ram_block1a_8.port_b_last_address = 36863,
ram_block1a_8.port_b_logical_ram_depth = 65536,
ram_block1a_8.port_b_logical_ram_width = 1,
ram_block1a_8.port_b_read_enable_write_enable_clock = "clock1",
ram_block1a_8.power_up_uninitialized = "false",
ram_block1a_8.ram_block_type = "AUTO",
ram_block1a_8.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block1a_9
(
.clk0(clock0),
.clk1(clock1),
.ena0(wire_decode_a_eq[9]),
.ena1(wire_decode_b_eq[9]),
.portaaddr({address_a_wire[11:0]}),
.portadatain({data_a[0]}),
.portadataout(wire_ram_block1a_9portadataout[0:0]),
.portawe(wire_decode2_eq[9]),
.portbaddr({address_b_wire[11:0]}),
.portbdatain({data_b[0]}),
.portbdataout(wire_ram_block1a_9portbdataout[0:0]),
.portbrewe(wire_decode3_eq[9])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_9.connectivity_checking = "OFF",
ram_block1a_9.init_file = "../MEMINIT.MIF",
ram_block1a_9.init_file_layout = "port_a",
ram_block1a_9.logical_ram_name = "ALTSYNCRAM",
ram_block1a_9.mem_init0 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_9.mem_init1 = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
ram_block1a_9.mixed_port_feed_through_mode = "dont_care",
ram_block1a_9.operation_mode = "bidir_dual_port",
ram_block1a_9.port_a_address_width = 12,
ram_block1a_9.port_a_data_out_clear = "none",
ram_block1a_9.port_a_data_out_clock = "clock0",
ram_block1a_9.port_a_data_width = 1,
ram_block1a_9.port_a_disable_ce_on_input_registers = "off",
ram_block1a_9.port_a_disable_ce_on_output_registers = "on",
ram_block1a_9.port_a_first_address = 36864,
ram_block1a_9.port_a_first_bit_number = 0,
ram_block1a_9.port_a_last_address = 40959,
ram_block1a_9.port_a_logical_ram_depth = 65536,
ram_block1a_9.port_a_logical_ram_width = 1,
ram_block1a_9.port_b_address_clock = "clock1",
ram_block1a_9.port_b_address_width = 12,
ram_block1a_9.port_b_data_in_clock = "clock1",
ram_block1a_9.port_b_data_out_clear = "none",
ram_block1a_9.port_b_data_out_clock = "clock1",
ram_block1a_9.port_b_data_width = 1,
ram_block1a_9.port_b_disable_ce_on_input_registers = "off",
ram_block1a_9.port_b_disable_ce_on_output_registers = "on",
ram_block1a_9.port_b_first_address = 36864,
ram_block1a_9.port_b_first_bit_number = 0,