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Is your feature request related to a problem? Please describe.
AMD gpus can rasterize in parallel, which produces significant throughput advantages (I have a scene where the difference is 16ms -> 8ms). The driver is sometimes smart enough to enable parallel rasterization automatically if the change in order cannot be viewed by the user, but they must be extremely conservative.
Describe the solution you'd like
A native feature that would add a "relaxed_rasterization_order" boolean to the pipeline descriptor.
Describe alternatives you've considered
Not having this extension.
Additional context
I know this is a IHV extension, and we generally don't do that, but this is quite low lift (a single pnext struct + boolean) with some pretty crazy gains.
The text was updated successfully, but these errors were encountered:
Is your feature request related to a problem? Please describe.
AMD gpus can rasterize in parallel, which produces significant throughput advantages (I have a scene where the difference is 16ms -> 8ms). The driver is sometimes smart enough to enable parallel rasterization automatically if the change in order cannot be viewed by the user, but they must be extremely conservative.
Describe the solution you'd like
A native feature that would add a "relaxed_rasterization_order" boolean to the pipeline descriptor.
Describe alternatives you've considered
Not having this extension.
Additional context
I know this is a IHV extension, and we generally don't do that, but this is quite low lift (a single pnext struct + boolean) with some pretty crazy gains.
The text was updated successfully, but these errors were encountered: