forked from deltabeard/Peanut-GB
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathpeanut_gb.h
3804 lines (3207 loc) · 92.9 KB
/
peanut_gb.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/**
* MIT License
*
* Copyright (c) 2018-2023 Mahyar Koshkouei
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Please note that at least three parts of source code within this project was
* taken from the SameBoy project at https://github.com/LIJI32/SameBoy/ which at
* the time of this writing is released under the MIT License. Occurrences of
* this code is marked as being taken from SameBoy with a comment.
* SameBoy, and code marked as being taken from SameBoy,
* is Copyright (c) 2015-2019 Lior Halphon.
*/
#ifndef PEANUT_GB_H
#define PEANUT_GB_H
#if defined(__has_include)
# if __has_include("version.all")
# include "version.all" /* Version information */
# endif
#else
/* Stub __has_include for later. */
# define __has_include(x) 0
#endif
#include <stdlib.h> /* Required for qsort and abort */
#include <stdint.h> /* Required for int types */
#include <string.h> /* Required for memset */
#include <time.h> /* Required for tm struct */
/**
* If PEANUT_GB_IS_LITTLE_ENDIAN is positive, then Peanut-GB will be configured
* for a little endian platform. If 0, then big endian.
*/
#if !defined(PEANUT_GB_IS_LITTLE_ENDIAN)
/* If endian is not defined, then attempt to detect it. */
# if defined(__BYTE_ORDER__)
# if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
/* Building for a big endian platform. */
# define PEANUT_GB_IS_LITTLE_ENDIAN 0
# else
# define PEANUT_GB_IS_LITTLE_ENDIAN 1
# endif /* __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__ */
# elif defined(_WIN32)
/* We assume that Windows is always little endian by default. */
# define PEANUT_GB_IS_LITTLE_ENDIAN 1
# elif !defined(PEANUT_GB_IS_LITTLE_ENDIAN)
# error "Could not detect target platform endian. Please define PEANUT_GB_IS_LITTLE_ENDIAN"
# endif
#endif /* !defined(PEANUT_GB_IS_LITTLE_ENDIAN) */
#if PEANUT_GB_IS_LITTLE_ENDIAN == 0
# error "Peanut-GB only supports little endian targets"
/* This is because the logic has been written with assumption of little
* endian byte order. */
#endif
/** Definitions for compile-time setting of features. **/
/**
* Sound support must be provided by an external library. When audio_read() and
* audio_write() functions are provided, define ENABLE_SOUND to a non-zero value
* before including peanut_gb.h in order for these functions to be used.
*/
#ifndef ENABLE_SOUND
# define ENABLE_SOUND 0
#endif
/* Enable LCD drawing. On by default. May be turned off for testing purposes. */
#ifndef ENABLE_LCD
# define ENABLE_LCD 1
#endif
/* Adds more code to improve LCD rendering accuracy. */
#ifndef PEANUT_GB_HIGH_LCD_ACCURACY
# define PEANUT_GB_HIGH_LCD_ACCURACY 1
#endif
/* Use intrinsic functions. This may produce smaller and faster code. */
#ifndef PEANUT_GB_USE_INTRINSICS
# define PEANUT_GB_USE_INTRINSICS 1
#endif
/* Only include function prototypes. At least one file must *not* have this
* defined. */
// #define PEANUT_GB_HEADER_ONLY
/** Internal source code. **/
/* Interrupt masks */
#define VBLANK_INTR 0x01
#define LCDC_INTR 0x02
#define TIMER_INTR 0x04
#define SERIAL_INTR 0x08
#define CONTROL_INTR 0x10
#define ANY_INTR 0x1F
/* Memory section sizes for DMG */
#define WRAM_SIZE 0x2000
#define VRAM_SIZE 0x2000
#define HRAM_IO_SIZE 0x0100
#define OAM_SIZE 0x00A0
/* Memory addresses */
#define ROM_0_ADDR 0x0000
#define ROM_N_ADDR 0x4000
#define VRAM_ADDR 0x8000
#define CART_RAM_ADDR 0xA000
#define WRAM_0_ADDR 0xC000
#define WRAM_1_ADDR 0xD000
#define ECHO_ADDR 0xE000
#define OAM_ADDR 0xFE00
#define UNUSED_ADDR 0xFEA0
#define IO_ADDR 0xFF00
#define HRAM_ADDR 0xFF80
#define INTR_EN_ADDR 0xFFFF
/* Cart section sizes */
#define ROM_BANK_SIZE 0x4000
#define WRAM_BANK_SIZE 0x1000
#define CRAM_BANK_SIZE 0x2000
#define VRAM_BANK_SIZE 0x2000
/* DIV Register is incremented at rate of 16384Hz.
* 4194304 / 16384 = 256 clock cycles for one increment. */
#define DIV_CYCLES 256
/* Serial clock locked to 8192Hz on DMG.
* 4194304 / (8192 / 8) = 4096 clock cycles for sending 1 byte. */
#define SERIAL_CYCLES 4096
/* Calculating VSYNC. */
#define DMG_CLOCK_FREQ 4194304.0
#define SCREEN_REFRESH_CYCLES 70224.0
#define VERTICAL_SYNC (DMG_CLOCK_FREQ/SCREEN_REFRESH_CYCLES)
/* SERIAL SC register masks. */
#define SERIAL_SC_TX_START 0x80
#define SERIAL_SC_CLOCK_SRC 0x01
/* STAT register masks */
#define STAT_LYC_INTR 0x40
#define STAT_MODE_2_INTR 0x20
#define STAT_MODE_1_INTR 0x10
#define STAT_MODE_0_INTR 0x08
#define STAT_LYC_COINC 0x04
#define STAT_MODE 0x03
#define STAT_USER_BITS 0xF8
/* LCDC control masks */
#define LCDC_ENABLE 0x80
#define LCDC_WINDOW_MAP 0x40
#define LCDC_WINDOW_ENABLE 0x20
#define LCDC_TILE_SELECT 0x10
#define LCDC_BG_MAP 0x08
#define LCDC_OBJ_SIZE 0x04
#define LCDC_OBJ_ENABLE 0x02
#define LCDC_BG_ENABLE 0x01
/* LCD characteristics */
#define LCD_LINE_CYCLES (456 + 4)
#define LCD_MODE_0_CYCLES 0
#define LCD_MODE_2_CYCLES 204
#define LCD_MODE_3_CYCLES 284
#define LCD_VERT_LINES 154
#define LCD_WIDTH 160
#define LCD_HEIGHT 144
/* VRAM Locations */
#define VRAM_TILES_1 (0x8000 - VRAM_ADDR)
#define VRAM_TILES_2 (0x8800 - VRAM_ADDR)
#define VRAM_BMAP_1 (0x9800 - VRAM_ADDR)
#define VRAM_BMAP_2 (0x9C00 - VRAM_ADDR)
#define VRAM_TILES_3 (0x8000 - VRAM_ADDR + VRAM_BANK_SIZE)
#define VRAM_TILES_4 (0x8800 - VRAM_ADDR + VRAM_BANK_SIZE)
/* Interrupt jump addresses */
#define VBLANK_INTR_ADDR 0x0040
#define LCDC_INTR_ADDR 0x0048
#define TIMER_INTR_ADDR 0x0050
#define SERIAL_INTR_ADDR 0x0058
#define CONTROL_INTR_ADDR 0x0060
/* SPRITE controls */
#define NUM_SPRITES 0x28
#define MAX_SPRITES_LINE 0x0A
#define OBJ_PRIORITY 0x80
#define OBJ_FLIP_Y 0x40
#define OBJ_FLIP_X 0x20
#define OBJ_PALETTE 0x10
#define ROM_HEADER_CHECKSUM_LOC 0x014D
/* Local macros. */
#ifndef MIN
# define MIN(a, b) ((a) < (b) ? (a) : (b))
#endif
#define PEANUT_GB_ARRAYSIZE(array) (sizeof(array)/sizeof(array[0]))
#if !defined(__has_builtin)
/* Stub __has_builtin if it isn't available. */
# define __has_builtin(x) 0
#endif
/* The PGB_UNREACHABLE() macro tells the compiler that the code path will never
* be reached, allowing for further optimisation. */
#if !defined(PGB_UNREACHABLE)
# if __has_builtin(__builtin_unreachable)
# define PGB_UNREACHABLE() __builtin_unreachable()
# elif defined(_MSC_VER)
# define PGB_UNREACHABLE() __assume(0)
# else
# define PGB_UNREACHABLE() abort()
# endif
#endif /* !defined(PGB_UNREACHABLE) */
#if PEANUT_GB_USE_INTRINSICS
/* If using MSVC, only enable intrinsics for x86 platforms*/
# if defined(_MSC_VER) && __has_include("intrin.h") && \
(defined(_M_IX86_FP) || defined(_M_AMD64) || defined(_M_X64))
/* Define intrinsic functions for MSVC. */
# include <intrin.h>
# define PGB_INTRIN_SBC(x,y,cin,res) _subborrow_u8(cin,x,y,&res)
# define PGB_INTRIN_ADC(x,y,cin,res) _addcarry_u8(cin,x,y,&res)
# endif /* MSVC */
/* Check for intrinsic functions in GCC and Clang. */
# if __has_builtin(__builtin_sub_overflow)
# define PGB_INTRIN_SBC(x,y,cin,res) __builtin_sub_overflow(x,y+cin,&res)
# define PGB_INTRIN_ADC(x,y,cin,res) __builtin_add_overflow(x,y+cin,&res)
# endif
#endif /* PEANUT_GB_USE_INTRINSICS */
#if defined(PGB_INTRIN_SBC)
# define PGB_INSTR_SBC_R8(r,cin) \
{ \
uint8_t temp; \
gb->cpu_reg.f_bits.c = PGB_INTRIN_SBC(gb->cpu_reg.a,r,cin,temp);\
gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a ^ r ^ temp) & 0x10) > 0; \
gb->cpu_reg.f_bits.n = 1; \
gb->cpu_reg.f_bits.z = (temp == 0x00); \
gb->cpu_reg.a = temp; \
}
# define PGB_INSTR_CP_R8(r) \
{ \
uint8_t temp; \
gb->cpu_reg.f_bits.c = PGB_INTRIN_SBC(gb->cpu_reg.a,r,0,temp); \
gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a ^ r ^ temp) & 0x10) > 0; \
gb->cpu_reg.f_bits.n = 1; \
gb->cpu_reg.f_bits.z = (temp == 0x00); \
}
#else
# define PGB_INSTR_SBC_R8(r,cin) \
{ \
uint16_t temp = gb->cpu_reg.a - (r + cin); \
gb->cpu_reg.f_bits.c = (temp & 0xFF00) ? 1 : 0; \
gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a ^ r ^ temp) & 0x10) > 0; \
gb->cpu_reg.f_bits.n = 1; \
gb->cpu_reg.f_bits.z = ((temp & 0xFF) == 0x00); \
gb->cpu_reg.a = (temp & 0xFF); \
}
# define PGB_INSTR_CP_R8(r) \
{ \
uint16_t temp = gb->cpu_reg.a - r; \
gb->cpu_reg.f_bits.c = (temp & 0xFF00) ? 1 : 0; \
gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a ^ r ^ temp) & 0x10) > 0; \
gb->cpu_reg.f_bits.n = 1; \
gb->cpu_reg.f_bits.z = ((temp & 0xFF) == 0x00); \
}
#endif /* PGB_INTRIN_SBC */
#if defined(PGB_INTRIN_ADC)
# define PGB_INSTR_ADC_R8(r,cin) \
{ \
uint8_t temp; \
gb->cpu_reg.f_bits.c = PGB_INTRIN_ADC(gb->cpu_reg.a,r,cin,temp);\
gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a ^ r ^ temp) & 0x10) > 0; \
gb->cpu_reg.f_bits.n = 0; \
gb->cpu_reg.f_bits.z = (temp == 0x00); \
gb->cpu_reg.a = temp; \
}
#else
# define PGB_INSTR_ADC_R8(r,cin) \
{ \
uint16_t temp = gb->cpu_reg.a + r + cin; \
gb->cpu_reg.f_bits.c = (temp & 0xFF00) ? 1 : 0; \
gb->cpu_reg.f_bits.h = ((gb->cpu_reg.a ^ r ^ temp) & 0x10) > 0; \
gb->cpu_reg.f_bits.n = 0; \
gb->cpu_reg.f_bits.z = ((temp & 0xFF) == 0x00); \
gb->cpu_reg.a = (temp & 0xFF); \
}
#endif /* PGB_INTRIN_ADC */
#define PGB_INSTR_DEC_R8(r) \
r--; \
gb->cpu_reg.f_bits.h = ((r & 0x0F) == 0x0F); \
gb->cpu_reg.f_bits.n = 1; \
gb->cpu_reg.f_bits.z = (r == 0x00);
#define PGB_INSTR_XOR_R8(r) \
gb->cpu_reg.a ^= r; \
gb->cpu_reg.f_bits.z = (gb->cpu_reg.a == 0x00); \
gb->cpu_reg.f_bits.n = 0; \
gb->cpu_reg.f_bits.h = 0; \
gb->cpu_reg.f_bits.c = 0;
#define PGB_INSTR_OR_R8(r) \
gb->cpu_reg.a |= r; \
gb->cpu_reg.f_bits.z = (gb->cpu_reg.a == 0x00); \
gb->cpu_reg.f_bits.n = 0; \
gb->cpu_reg.f_bits.h = 0; \
gb->cpu_reg.f_bits.c = 0;
#define PGB_INSTR_AND_R8(r) \
gb->cpu_reg.a &= r; \
gb->cpu_reg.f_bits.z = (gb->cpu_reg.a == 0x00); \
gb->cpu_reg.f_bits.n = 0; \
gb->cpu_reg.f_bits.h = 1; \
gb->cpu_reg.f_bits.c = 0;
#if PEANUT_GB_IS_LITTLE_ENDIAN
# define PEANUT_GB_GET_LSB16(x) (x & 0xFF)
# define PEANUT_GB_GET_MSB16(x) (x >> 8)
# define PEANUT_GB_GET_MSN16(x) (x >> 12)
# define PEANUT_GB_U8_TO_U16(h,l) ((l) | ((h) << 8))
#else
# define PEANUT_GB_GET_LSB16(x) (x >> 8)
# define PEANUT_GB_GET_MSB16(x) (x & 0xFF)
# define PEANUT_GB_GET_MSN16(x) ((x & 0xF0) >> 4)
# define PEANUT_GB_U8_TO_U16(h,l) ((h) | ((l) << 8))
#endif
struct cpu_registers_s
{
/* Change register order if big endian.
* Macro receives registers in little endian order. */
#if PEANUT_GB_IS_LITTLE_ENDIAN
# define PEANUT_GB_LE_REG(x,y) x,y
#else
# define PEANUT_GB_LE_REG(x,y) y,x
#endif
/* Define specific bits of Flag register. */
struct
{
uint8_t c : 1; /* Carry flag. */
uint8_t h : 1; /* Half carry flag. */
uint8_t n : 1; /* Add/sub flag. */
uint8_t z : 1; /* Zero flag. */
} f_bits;
uint8_t a;
union
{
struct
{
uint8_t PEANUT_GB_LE_REG(c,b);
} bytes;
uint16_t reg;
} bc;
union
{
struct
{
uint8_t PEANUT_GB_LE_REG(e,d);
} bytes;
uint16_t reg;
} de;
union
{
struct
{
uint8_t PEANUT_GB_LE_REG(l,h);
} bytes;
uint16_t reg;
} hl;
/* Stack pointer */
union
{
struct
{
uint8_t PEANUT_GB_LE_REG(p, s);
} bytes;
uint16_t reg;
} sp;
/* Program counter */
union
{
struct
{
uint8_t PEANUT_GB_LE_REG(c, p);
} bytes;
uint16_t reg;
} pc;
#undef PEANUT_GB_LE_REG
};
struct count_s
{
uint_fast16_t lcd_count; /* LCD Timing */
uint_fast16_t div_count; /* Divider Register Counter */
uint_fast16_t tima_count; /* Timer Counter */
uint_fast16_t serial_count; /* Serial Counter */
};
#if ENABLE_LCD
/* Bit mask for the shade of pixel to display */
#define LCD_COLOUR 0x03
/**
* Bit mask for whether a pixel is OBJ0, OBJ1, or BG. Each may have a different
* palette when playing a DMG game on CGB.
*/
#define LCD_PALETTE_OBJ 0x10
#define LCD_PALETTE_BG 0x20
/**
* Bit mask for the two bits listed above.
* LCD_PALETTE_ALL == 0b00 --> OBJ0
* LCD_PALETTE_ALL == 0b01 --> OBJ1
* LCD_PALETTE_ALL == 0b10 --> BG
* LCD_PALETTE_ALL == 0b11 --> NOT POSSIBLE
*/
#define LCD_PALETTE_ALL 0x30
#endif
/**
* Errors that may occur during emulation.
*/
enum gb_error_e
{
GB_UNKNOWN_ERROR = 0,
GB_INVALID_OPCODE,
GB_INVALID_READ,
GB_INVALID_WRITE,
GB_HALT_FOREVER,
GB_INVALID_MAX
};
/**
* Errors that may occur during library initialisation.
*/
enum gb_init_error_e
{
GB_INIT_NO_ERROR = 0,
GB_INIT_CARTRIDGE_UNSUPPORTED,
GB_INIT_INVALID_CHECKSUM
};
/**
* Return codes for serial receive function, mainly for clarity.
*/
enum gb_serial_rx_ret_e
{
GB_SERIAL_RX_SUCCESS = 0,
GB_SERIAL_RX_NO_CONNECTION = 1
};
/**
* Emulator context.
*
* Only values within the `direct` struct may be modified directly by the
* front-end implementation. Other variables must not be modified.
*/
struct gb_s
{
/**
* Return byte from ROM at given address.
*
* \param gb_s emulator context
* \param addr address
* \return byte at address in ROM
*/
uint8_t (*gb_rom_read)(struct gb_s*, const uint_fast32_t addr);
/**
* Return byte from cart RAM at given address.
*
* \param gb_s emulator context
* \param addr address
* \return byte at address in RAM
*/
uint8_t (*gb_cart_ram_read)(struct gb_s*, const uint_fast32_t addr);
/**
* Write byte to cart RAM at given address.
*
* \param gb_s emulator context
* \param addr address
* \param val value to write to address in RAM
*/
void (*gb_cart_ram_write)(struct gb_s*, const uint_fast32_t addr,
const uint8_t val);
/**
* Notify front-end of error.
*
* \param gb_s emulator context
* \param gb_error_e error code
* \param addr address of where error occurred
*/
void (*gb_error)(struct gb_s*, const enum gb_error_e, const uint16_t addr);
/* Transmit one byte and return the received byte. */
void (*gb_serial_tx)(struct gb_s*, const uint8_t tx);
enum gb_serial_rx_ret_e (*gb_serial_rx)(struct gb_s*, uint8_t* rx);
/* Read byte from boot ROM at given address. */
uint8_t (*gb_bootrom_read)(struct gb_s*, const uint_fast16_t addr);
struct
{
unsigned gb_halt : 1;
unsigned gb_ime : 1;
unsigned gb_frame : 1; /* New frame drawn. */
unsigned lcd_blank : 1;
};
/* Cartridge information:
* Memory Bank Controller (MBC) type. */
int8_t mbc;
/* Whether the MBC has internal RAM. */
uint8_t cart_ram;
/* Number of ROM banks in cartridge. */
uint16_t num_rom_banks_mask;
/* Number of RAM banks in cartridge. */
uint8_t num_ram_banks;
uint16_t selected_rom_bank;
/* WRAM and VRAM bank selection not available. */
uint8_t cart_ram_bank;
uint8_t enable_cart_ram;
/* Cartridge ROM/RAM mode select. */
uint8_t cart_mode_select;
union
{
struct
{
uint8_t sec;
uint8_t min;
uint8_t hour;
uint8_t yday;
uint8_t high;
} rtc_bits;
uint8_t cart_rtc[5];
};
struct cpu_registers_s cpu_reg;
//struct gb_registers_s gb_reg;
struct count_s counter;
/* TODO: Allow implementation to allocate WRAM, VRAM and Frame Buffer. */
uint8_t wram[WRAM_SIZE];
uint8_t vram[VRAM_SIZE];
uint8_t oam[OAM_SIZE];
uint8_t hram_io[HRAM_IO_SIZE];
struct
{
/**
* Draw line on screen.
*
* \param gb_s emulator context
* \param pixels The 160 pixels to draw.
* Bits 1-0 are the colour to draw.
* Bits 5-4 are the palette, where:
* OBJ0 = 0b00,
* OBJ1 = 0b01,
* BG = 0b10
* Other bits are undefined.
* Bits 5-4 are only required by front-ends
* which want to use a different colour for
* different object palettes. This is what
* the Game Boy Color (CGB) does to DMG
* games.
* \param line Line to draw pixels on. This is
* guaranteed to be between 0-144 inclusive.
*/
void (*lcd_draw_line)(struct gb_s *gb,
const uint8_t *pixels,
const uint_fast8_t line);
/* Palettes */
uint8_t bg_palette[4];
uint8_t sp_palette[8];
uint8_t window_clear;
uint8_t WY;
/* Only support 30fps frame skip. */
unsigned frame_skip_count : 1;
unsigned interlace_count : 1;
} display;
/**
* Variables that may be modified directly by the front-end.
* This method seems to be easier and possibly less overhead than
* calling a function to modify these variables each time.
*
* None of this is thread-safe.
*/
struct
{
/* Set to enable interlacing. Interlacing will start immediately
* (at the next line drawing).
*/
unsigned interlace : 1;
unsigned frame_skip : 1;
union
{
struct
{
unsigned a : 1;
unsigned b : 1;
unsigned select : 1;
unsigned start : 1;
unsigned right : 1;
unsigned left : 1;
unsigned up : 1;
unsigned down : 1;
} joypad_bits;
uint8_t joypad;
};
/* Implementation defined data. Set to NULL if not required. */
void *priv;
} direct;
};
#ifndef PEANUT_GB_HEADER_ONLY
#define IO_JOYP 0x00
#define IO_SB 0x01
#define IO_SC 0x02
#define IO_DIV 0x04
#define IO_TIMA 0x05
#define IO_TMA 0x06
#define IO_TAC 0x07
#define IO_IF 0x0F
#define IO_BOOT 0x50
#define IO_LCDC 0x40
#define IO_STAT 0x41
#define IO_SCY 0x42
#define IO_SCX 0x43
#define IO_LY 0x44
#define IO_LYC 0x45
#define IO_DMA 0x46
#define IO_BGP 0x47
#define IO_OBP0 0x48
#define IO_OBP1 0x49
#define IO_WY 0x4A
#define IO_WX 0x4B
#define IO_BANK 0x50
#define IO_IE 0xFF
#define IO_TAC_RATE_MASK 0x3
#define IO_TAC_ENABLE_MASK 0x4
/* LCD Mode defines. */
#define IO_STAT_MODE_HBLANK 0
#define IO_STAT_MODE_VBLANK 1
#define IO_STAT_MODE_SEARCH_OAM 2
#define IO_STAT_MODE_SEARCH_TRANSFER 3
#define IO_STAT_MODE_VBLANK_OR_TRANSFER_MASK 0x1
/**
* Internal function used to read bytes.
* addr is host platform endian.
*/
uint8_t __gb_read(struct gb_s *gb, const uint16_t addr)
{
switch(PEANUT_GB_GET_MSN16(addr))
{
case 0x0:
/* IO_BANK is only set to 1 if gb->gb_bootrom_read was not NULL
* on reset. */
if(gb->hram_io[IO_BANK] == 0 && addr < 0x0100)
{
return gb->gb_bootrom_read(gb, addr);
}
/* Fallthrough */
case 0x1:
case 0x2:
case 0x3:
return gb->gb_rom_read(gb, addr);
case 0x4:
case 0x5:
case 0x6:
case 0x7:
if(gb->mbc == 1 && gb->cart_mode_select)
return gb->gb_rom_read(gb,
addr + ((gb->selected_rom_bank & 0x1F) - 1) * ROM_BANK_SIZE);
else
return gb->gb_rom_read(gb, addr + (gb->selected_rom_bank - 1) * ROM_BANK_SIZE);
case 0x8:
case 0x9:
return gb->vram[addr - VRAM_ADDR];
case 0xA:
case 0xB:
if(gb->cart_ram && gb->enable_cart_ram)
{
if(gb->mbc == 3 && gb->cart_ram_bank >= 0x08)
return gb->cart_rtc[gb->cart_ram_bank - 0x08];
else if((gb->cart_mode_select || gb->mbc != 1) &&
gb->cart_ram_bank < gb->num_ram_banks)
{
return gb->gb_cart_ram_read(gb, addr - CART_RAM_ADDR +
(gb->cart_ram_bank * CRAM_BANK_SIZE));
}
else
return gb->gb_cart_ram_read(gb, addr - CART_RAM_ADDR);
}
return 0xFF;
case 0xC:
return gb->wram[addr - WRAM_0_ADDR];
case 0xD:
return gb->wram[addr - WRAM_1_ADDR + WRAM_BANK_SIZE];
case 0xE:
return gb->wram[addr - ECHO_ADDR];
case 0xF:
if(addr < OAM_ADDR)
return gb->wram[addr - ECHO_ADDR];
if(addr < UNUSED_ADDR)
return gb->oam[addr - OAM_ADDR];
/* Unusable memory area. Reading from this area returns 0xFF.*/
if(addr < IO_ADDR)
return 0xFF;
/* APU registers. */
if((addr >= 0xFF10) && (addr <= 0xFF3F))
{
#if ENABLE_SOUND
return audio_read(addr);
#else
static const uint8_t ortab[] = {
0x80, 0x3f, 0x00, 0xff, 0xbf,
0xff, 0x3f, 0x00, 0xff, 0xbf,
0x7f, 0xff, 0x9f, 0xff, 0xbf,
0xff, 0xff, 0x00, 0x00, 0xbf,
0x00, 0x00, 0x70,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
return gb->hram_io[addr - IO_ADDR] | ortab[addr - IO_ADDR];
#endif
}
/* HRAM */
if(addr >= IO_ADDR)
return gb->hram_io[addr - IO_ADDR];
}
/* Return address that caused read error. */
(gb->gb_error)(gb, GB_INVALID_READ, addr);
PGB_UNREACHABLE();
}
/**
* Internal function used to write bytes.
*/
void __gb_write(struct gb_s *gb, const uint_fast16_t addr, const uint8_t val)
{
switch(PEANUT_GB_GET_MSN16(addr))
{
case 0x0:
case 0x1:
if(gb->mbc == 2 && addr & 0x10)
return;
else if(gb->mbc > 0 && gb->cart_ram)
gb->enable_cart_ram = ((val & 0x0F) == 0x0A);
return;
case 0x2:
if(gb->mbc == 5)
{
gb->selected_rom_bank = (gb->selected_rom_bank & 0x100) | val;
gb->selected_rom_bank =
gb->selected_rom_bank & gb->num_rom_banks_mask;
return;
}
/* Intentional fall through. */
case 0x3:
if(gb->mbc == 1)
{
//selected_rom_bank = val & 0x7;
gb->selected_rom_bank = (val & 0x1F) | (gb->selected_rom_bank & 0x60);
if((gb->selected_rom_bank & 0x1F) == 0x00)
gb->selected_rom_bank++;
}
else if(gb->mbc == 2 && addr & 0x10)
{
gb->selected_rom_bank = val & 0x0F;
if(!gb->selected_rom_bank)
gb->selected_rom_bank++;
}
else if(gb->mbc == 3)
{
gb->selected_rom_bank = val & 0x7F;
if(!gb->selected_rom_bank)
gb->selected_rom_bank++;
}
else if(gb->mbc == 5)
gb->selected_rom_bank = (val & 0x01) << 8 | (gb->selected_rom_bank & 0xFF);
gb->selected_rom_bank = gb->selected_rom_bank & gb->num_rom_banks_mask;
return;
case 0x4:
case 0x5:
if(gb->mbc == 1)
{
gb->cart_ram_bank = (val & 3);
gb->selected_rom_bank = ((val & 3) << 5) | (gb->selected_rom_bank & 0x1F);
gb->selected_rom_bank = gb->selected_rom_bank & gb->num_rom_banks_mask;
}
else if(gb->mbc == 3)
gb->cart_ram_bank = val;
else if(gb->mbc == 5)
gb->cart_ram_bank = (val & 0x0F);
return;
case 0x6:
case 0x7:
gb->cart_mode_select = (val & 1);
return;
case 0x8:
case 0x9:
gb->vram[addr - VRAM_ADDR] = val;
return;
case 0xA:
case 0xB:
if(gb->cart_ram && gb->enable_cart_ram)
{
if(gb->mbc == 3 && gb->cart_ram_bank >= 0x08)
gb->cart_rtc[gb->cart_ram_bank - 0x08] = val;
else if(gb->cart_mode_select &&
gb->cart_ram_bank < gb->num_ram_banks)
{
gb->gb_cart_ram_write(gb,
addr - CART_RAM_ADDR + (gb->cart_ram_bank * CRAM_BANK_SIZE), val);
}
else if(gb->num_ram_banks)
gb->gb_cart_ram_write(gb, addr - CART_RAM_ADDR, val);
}
return;
case 0xC:
gb->wram[addr - WRAM_0_ADDR] = val;
return;
case 0xD:
gb->wram[addr - WRAM_1_ADDR + WRAM_BANK_SIZE] = val;
return;
case 0xE:
gb->wram[addr - ECHO_ADDR] = val;
return;
case 0xF:
if(addr < OAM_ADDR)
{
gb->wram[addr - ECHO_ADDR] = val;
return;
}
if(addr < UNUSED_ADDR)
{
gb->oam[addr - OAM_ADDR] = val;
return;
}
/* Unusable memory area. */
if(addr < IO_ADDR)
return;
if(HRAM_ADDR <= addr && addr < INTR_EN_ADDR)
{
gb->hram_io[addr - IO_ADDR] = val;
return;
}
if((addr >= 0xFF10) && (addr <= 0xFF3F))
{
#if ENABLE_SOUND
audio_write(addr, val);
#else
gb->hram_io[addr - IO_ADDR] = val;
#endif
return;
}
/* IO and Interrupts. */
switch(PEANUT_GB_GET_LSB16(addr))
{
/* Joypad */
case 0x00:
/* Only bits 5 and 4 are R/W.
* The lower bits are overwritten later, and the two most
* significant bits are unused. */
gb->hram_io[IO_JOYP] = val;
/* Direction keys selected */
if((gb->hram_io[IO_JOYP] & 0b010000) == 0)
gb->hram_io[IO_JOYP] |= (gb->direct.joypad >> 4);
/* Button keys selected */
else
gb->hram_io[IO_JOYP] |= (gb->direct.joypad & 0x0F);
return;
/* Serial */
case 0x01:
gb->hram_io[IO_SB] = val;
return;
case 0x02:
gb->hram_io[IO_SC] = val;
return;
/* Timer Registers */
case 0x04:
gb->hram_io[IO_DIV] = 0x00;
return;
case 0x05:
gb->hram_io[IO_TIMA] = val;
return;
case 0x06:
gb->hram_io[IO_TMA] = val;
return;
case 0x07:
gb->hram_io[IO_TAC] = val;
return;
/* Interrupt Flag Register */
case 0x0F:
gb->hram_io[IO_IF] = (val | 0b11100000);
return;
/* LCD Registers */
case 0x40:
if(((gb->hram_io[IO_LCDC] & LCDC_ENABLE) == 0) &&
(val & LCDC_ENABLE))
{
gb->counter.lcd_count = 0;
gb->lcd_blank = 1;
}
gb->hram_io[IO_LCDC] = val;
/* LY fixed to 0 when LCD turned off. */
if((gb->hram_io[IO_LCDC] & LCDC_ENABLE) == 0)
{