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ARCv3: Fix displayed L2$ size #161

Merged
merged 1 commit into from
Jul 12, 2024
Merged

ARCv3: Fix displayed L2$ size #161

merged 1 commit into from
Jul 12, 2024

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xxkent
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@xxkent xxkent commented Feb 28, 2024

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@xxkent xxkent requested a review from pavelvkozlov April 1, 2024 15:35
data_bank_wid:2, data_sub_banks:2, cache_sets:5,
data_bank_sz:5, data_banks:3, cache_tag_banks:3,
cache_blk_sz:1, cache_assoc:4, scm_cache:1, res:1;
#else
unsigned int res:1, scm_cache:1, cache_assoc:4, cache_blk_sz:1,
cache_tag_banks:3, data_banks:3, data_bank_sz:5,
cache_sets:5, data_sub_banks:2, data_bank_wid:2,
superblocks:3, res1:2;
superblocks:3, data_bank_sz_75:1, res1:1;

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Changes in this file are not linked with the L2$ size fix. Please, add this change by a separate commit.

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Done

@@ -51,7 +52,9 @@ static int read_decode_cache_bcr_arcv3(int c, char *buf, int len)
if (cln0.has_scm) {
READ_BCR(ARC_REG_CLNR_SCM_BCR_0, scm0);

p_l2->sz_k = (1 << scm0.data_bank_sz) * (1 << scm0.data_banks);
assoc = (scm0.cache_assoc == 0) ? 16 : scm0.cache_assoc;
p_l2->sz_k = (scm0.cache_blk_sz << 6) * assoc * (1 << scm0.cache_sets);

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I think you need to use the L1_CACHE_SHIFT definition instead of decimal-literal 6. The definition is formed from the CONFIG_ARC_CACHE_LINE_SHIFT option.

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The documentation states that the cache line size for ARСv3 is fixed and the size is 64 bytes. Let's rely on this and also fix the size = 64 bytes in code.

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Looks good

@xxkent xxkent merged commit 3c03c5c into arc64 Jul 12, 2024
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@xxkent xxkent deleted the bolsh-fix-cache-size branch July 12, 2024 17:58
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2 participants