How to Integrate hls4ml-generated IP into Artix-7 FPGA (Vivado Block Design)

[Smitashree-code]

Hi everyone,

I’ve successfully generated an IP using hls4ml and Vivado HLS, and imported it into a Vivado block design for implementation on an Artix-7 FPGA (XC7A100T-2CSG324).However, I’m currently stuck at the integration and bitstream generation phase. The IP block appears correctly in the block design, but I’m not sure:

1.What connections (e.g., AXI, clocks, resets, control signals) I need to manually make for Artix-7
2.How to configure the design to enable dumping the bitstream to the board
3.Whether additional steps (e.g., constraints, wrapper modifications) are required beyond the PYNQ-Z2 setup shown in hls4ml tutorials

I’ve seen that most examples are for PYNQ-Z2, but my target is Artix-7. I want to know if anyone has successfully integrated and run hls4ml IP on Artix-7 and what steps were needed.

Any help, reference designs, or guidance on how to set up the environment, create necessary interfaces, or constraints would be greatly appreciated!