diff --git a/wgpu-hal/examples/ray-traced-triangle/main.rs b/wgpu-hal/examples/ray-traced-triangle/main.rs
index 49fb58686b..dacd484eaa 100644
--- a/wgpu-hal/examples/ray-traced-triangle/main.rs
+++ b/wgpu-hal/examples/ray-traced-triangle/main.rs
@@ -125,13 +125,19 @@ impl<A: hal::Api> Example<A> {
             unsafe { adapter.open(features, &wgt::Limits::default()).unwrap() };
 
         let window_size: (u32, u32) = window.inner_size().into();
+        dbg!(&surface_caps.formats);
+        let surface_format = if surface_caps.formats.contains(&wgt::TextureFormat::Rgba8Snorm) {
+            wgt::TextureFormat::Rgba8Unorm
+        }else{
+            *surface_caps.formats.first().unwrap()
+        };
         let surface_config = hal::SurfaceConfiguration {
             swap_chain_size: DESIRED_FRAMES
                 .max(*surface_caps.swap_chain_sizes.start())
                 .min(*surface_caps.swap_chain_sizes.end()),
             present_mode: wgt::PresentMode::Fifo,
             composite_alpha_mode: hal::CompositeAlphaMode::Opaque,
-            format: wgt::TextureFormat::Rgba8Unorm,
+            format: surface_format,
             extent: wgt::Extent3d {
                 width: window_size.0,
                 height: window_size.1,
diff --git a/wgpu-hal/src/lib.rs b/wgpu-hal/src/lib.rs
index 321d8664ee..8888508d4e 100644
--- a/wgpu-hal/src/lib.rs
+++ b/wgpu-hal/src/lib.rs
@@ -690,9 +690,11 @@ bitflags::bitflags! {
         /// The combination of states that a buffer may be in _at the same time_.
         const INCLUSIVE = Self::MAP_READ.bits | Self::COPY_SRC.bits |
             Self::INDEX.bits | Self::VERTEX.bits | Self::UNIFORM.bits |
-            Self::STORAGE_READ.bits | Self::INDIRECT.bits;
+            Self::STORAGE_READ.bits | Self::INDIRECT.bits |
+            Self::BOTTOM_LEVEL_ACCELERATION_STRUCTURE_INPUT.bits | Self::TOP_LEVEL_ACCELERATION_STRUCTURE_INPUT.bits;
         /// The combination of states that a buffer must exclusively be in.
-        const EXCLUSIVE = Self::MAP_WRITE.bits | Self::COPY_DST.bits | Self::STORAGE_READ_WRITE.bits;
+        const EXCLUSIVE = Self::MAP_WRITE.bits | Self::COPY_DST.bits |
+            Self::STORAGE_READ_WRITE.bits | Self::ACCELERATION_STRUCTURE_SCRATCH.bits;
         /// The combination of all usages that the are guaranteed to be be ordered by the hardware.
         /// If a usage is ordered, then if the buffer state doesn't change between draw calls, there
         /// are no barriers needed for synchronization.
diff --git a/wgpu-hal/src/vulkan/command.rs b/wgpu-hal/src/vulkan/command.rs
index 02768f3c74..2f5e1ea59e 100644
--- a/wgpu-hal/src/vulkan/command.rs
+++ b/wgpu-hal/src/vulkan/command.rs
@@ -441,13 +441,13 @@ impl crate::CommandEncoder<super::Api> for super::CommandEncoder {
 
         let geometry_info = geometry_info.build();
 
-        let range = &[range][..];
-        let range = &[range][..];
-        let geometry_info = &[geometry_info];
+        //each geometry has multiple ranges; building requires a vector of geometry_infos and a vector of vectors of ranges
+        let ranges : &[&[vk::AccelerationStructureBuildRangeInfoKHR]] = &[&[range]];
+        let geometry_infos = &[geometry_info];
 
         ray_tracing_functions
             .acceleration_structure
-            .cmd_build_acceleration_structures(self.active, geometry_info, range);
+            .cmd_build_acceleration_structures(self.active, geometry_infos, ranges);
     }
 
     // render
diff --git a/wgpu-hal/src/vulkan/device.rs b/wgpu-hal/src/vulkan/device.rs
index afff881b18..428554ecbc 100644
--- a/wgpu-hal/src/vulkan/device.rs
+++ b/wgpu-hal/src/vulkan/device.rs
@@ -784,18 +784,18 @@ impl crate::Device<super::Api> for super::Device {
             desc.memory_flags.contains(crate::MemoryFlags::TRANSIENT),
         );
 
+        let alignment_mask = if desc.usage
+            .contains(crate::BufferUses::TOP_LEVEL_ACCELERATION_STRUCTURE_INPUT){
+            16
+        } else {
+            req.alignment
+        } - 1;
+
         let block = self.mem_allocator.lock().alloc(
             &*self.shared,
             gpu_alloc::Request {
                 size: req.size,
-                align_mask: if desc
-                    .usage
-                    .contains(crate::BufferUses::TOP_LEVEL_ACCELERATION_STRUCTURE_INPUT)
-                {
-                    16
-                } else {
-                    req.alignment
-                } - 1,
+                align_mask: alignment_mask,
                 usage: alloc_usage,
                 memory_types: req.memory_type_bits & self.valid_ash_memory_types,
             },
@@ -1429,6 +1429,7 @@ impl crate::Device<super::Api> for super::Device {
                     // `raw_acceleration_structures`.
                     let acceleration_structure_info: vk::WriteDescriptorSetAccelerationStructureKHR = *acceleration_structure_info;
 
+                    assert!(index < desc.acceleration_structures.len(), "Encountered more acceleration structures then expected");
                     acceleration_structure_infos.push(acceleration_structure_info);
 
                     extra_descriptor_count += 1;