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If you are using Windows, please specify command line type.
None
Development Kit.
ESP32-C6-DevkitC-N8
YD-ESP32-C6 (N8)
Power Supply used.
USB
What is the expected behavior?
LP UART should be capable of generate correct baud rate under all supported ranges.
What is the actual behavior?
The secondary divider of LP UART, LP_UART_CLK_CONF_REG.CLK_CONF.LP_UART_SCLK_DIV_NUM, might not work as expected.
This register only appears in the LL/SOC code and not shown in the TRM.
When the required baud rate is too low and overflow the main divider, LP_UART_CLKDIV_SYNC_REG's 12-bit range, the second divider SCLK_DIV_NUM will become non-zero value. But the resulting baud rate are expected_baud_rate * (SCLK_DIV_NUM + 1).
The register values of dividers are correct, but the resulting signal is not.
Steps to reproduce.
Configure the LP UART's baud rate to any value outside the LP_UART_CLKDIV_SYNC_REG's range, such as 2400bps.
See the output from the GPIO5. Tested via both CP2102N and FT232RL.
sclk_div in this case becomes 2 and LP_UART_SCLK_DIV_NUM is 1, the resulting baud rate becomes 2400 * (LP_UART_SCLK_DIV_NUM + 1) = 4800bps
Try other baud rate, such as 1700bps, and the corresponding sclk_div is 3
The resulting baud rate becomes 1700 * 3 = 5100bps
andylinpersonal
changed the title
ESP32-C6's LP UART cannot generate some low baud rate
ESP32-C6's LP UART cannot generate some low baud rates
Feb 19, 2025
github-actionsbot
changed the title
ESP32-C6's LP UART cannot generate some low baud rates
ESP32-C6's LP UART cannot generate some low baud rates (IDFGH-14685)
Feb 19, 2025
Answers checklist.
IDF version.
release/v5.4 e37d33c
master 0d6099e
Espressif SoC revision.
ESP32-C6 (QFN40) (revision v0.0)
Operating System used.
Linux
How did you build your project?
Command line with idf.py
If you are using Windows, please specify command line type.
None
Development Kit.
ESP32-C6-DevkitC-N8
YD-ESP32-C6 (N8)
Power Supply used.
USB
What is the expected behavior?
LP UART should be capable of generate correct baud rate under all supported ranges.
What is the actual behavior?
The secondary divider of
LP UART
,LP_UART_CLK_CONF_REG.CLK_CONF.LP_UART_SCLK_DIV_NUM
, might not work as expected.This register only appears in the
LL
/SOC
code and not shown in the TRM.When the required baud rate is too low and overflow the main divider,
LP_UART_CLKDIV_SYNC_REG
's 12-bit range, the second dividerSCLK_DIV_NUM
will become non-zero value. But the resulting baud rate areexpected_baud_rate * (SCLK_DIV_NUM + 1)
.The register values of dividers are correct, but the resulting signal is not.
Steps to reproduce.
LP UART
's baud rate to any value outside theLP_UART_CLKDIV_SYNC_REG
's range, such as 2400bps.GPIO5
. Tested via both CP2102N and FT232RL.2
andLP_UART_SCLK_DIV_NUM
is1
, the resulting baud rate becomes2400 * (LP_UART_SCLK_DIV_NUM + 1) = 4800bps
1700bps
, and the correspondingsclk_div
is 31700 * 3 = 5100bps
Debug Logs.
More Information.
CMakeLists.txt
main/CMakeLists.txt
main/defines.h
main/main.c
main/ulp/main.c
sdkconfig.defaults
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