From ae6e95380dbe4aebd345a622f1b07418e7ee6ce8 Mon Sep 17 00:00:00 2001 From: Kirill Mikhailov Date: Tue, 3 Sep 2024 12:51:28 +0200 Subject: [PATCH] rebase --- hil-test/tests/i2c.rs | 10 +++------- hil-test/tests/pcnt.rs | 4 ++-- hil-test/tests/qspi_read.rs | 20 +++++++++++--------- hil-test/tests/qspi_write.rs | 19 +++++++++++-------- hil-test/tests/qspi_write_read.rs | 21 ++++++++++++--------- hil-test/tests/rmt.rs | 2 +- hil-test/tests/spi_full_duplex_dma_pcnt.rs | 8 ++++---- hil-test/tests/spi_half_duplex_read.rs | 4 ++-- hil-test/tests/spi_half_duplex_write.rs | 2 +- hil-test/tests/uart_async.rs | 5 ++--- 10 files changed, 49 insertions(+), 46 deletions(-) diff --git a/hil-test/tests/i2c.rs b/hil-test/tests/i2c.rs index be1885e44de..072402a3465 100644 --- a/hil-test/tests/i2c.rs +++ b/hil-test/tests/i2c.rs @@ -4,8 +4,8 @@ //! SDA GPIO2 (esp32s2 and esp32s3) //! GPIO6 (esp32c6) //! GPIO18 (esp32c2) -//! GPIO4 (esp32, esp32h2 and esp32c3) -//! +//! GPIO4 (esp32, esp32h2 and esp32c3) +//! //! SCL GPIO3 (esp32s2 and esp32s3) //! GPIO7 (esp32c6, esp32 and esp32c3) //! GPIO22 (esp32h2) @@ -22,7 +22,6 @@ use esp_hal::{ i2c::I2C, peripherals::{Peripherals, I2C0}, prelude::*, - system::SystemControl, Blocking, }; use hil_test as _; @@ -39,10 +38,7 @@ mod tests { #[init] fn init() -> Context { - let peripherals = Peripherals::take(); - let system = SystemControl::new(peripherals.SYSTEM); - let clocks = ClockControl::boot_defaults(system.clock_control).freeze(); - + let (peripherals, clocks) = esp_hal::init(esp_hal::Config::default()); let io = Io::new(peripherals.GPIO, peripherals.IO_MUX); let (sda, scl) = hil_test::i2c_pins!(io); diff --git a/hil-test/tests/pcnt.rs b/hil-test/tests/pcnt.rs index c7c64e63d47..f0ca372ed91 100644 --- a/hil-test/tests/pcnt.rs +++ b/hil-test/tests/pcnt.rs @@ -1,7 +1,7 @@ //! PCNT tests //! //! It's assumed GPIO2 is connected to GPIO3 -//! (GPIO9 and GPIO10 for esp32s3) +//! (GPIO9 and GPIO10 for esp32s2 and esp32s3) //% CHIPS: esp32 esp32c6 esp32h2 esp32s2 esp32s3 @@ -10,7 +10,7 @@ use esp_hal::{ delay::Delay, - gpio::{GpioPin, AnyPin, Io, Level, Output, Pull}, + gpio::{AnyPin, Io, Level, Output, Pull}, pcnt::{ channel::{EdgeMode, PcntInputConfig, PcntSource}, Pcnt, diff --git a/hil-test/tests/qspi_read.rs b/hil-test/tests/qspi_read.rs index 6abeab451db..a58455d4515 100644 --- a/hil-test/tests/qspi_read.rs +++ b/hil-test/tests/qspi_read.rs @@ -1,11 +1,11 @@ //! QSPI Read Test //! //! Following pins are used: -//! MISO GPIO2 +//! MISO GPIO2 / GPIO9 (esp32s2 and esp32s3) //! -//! GPIO GPIO3 +//! GPIO GPIO3 / GPIO10 (esp32s2 and esp32s3) //! -//! Connect MISO (GPIO2) and GPIO (GPIO3) pins. +//! Connect MISO and GPIO pins. //% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3 @@ -16,7 +16,7 @@ use esp_hal::{ clock::Clocks, dma::{Channel, Dma, DmaPriority, DmaRxBuf}, dma_buffers, - gpio::{GpioPin, Io, Level, Output}, + gpio::{AnyOutput, AnyPin, Io, Level}, prelude::*, spi::{ master::{Address, Command, Spi, SpiDma}, @@ -42,14 +42,14 @@ cfg_if::cfg_if! { struct Context { spi: esp_hal::peripherals::SPI2, dma_channel: Channel<'static, DmaChannel0, Blocking>, - miso: esp_hal::gpio::GpioPin<2>, - miso_mirror: Output<'static, GpioPin<3>>, + miso: AnyPin<'static>, + miso_mirror: AnyOutput<'static>, clocks: Clocks<'static>, } fn execute( mut spi: SpiDma<'static, esp_hal::peripherals::SPI2, DmaChannel0, HalfDuplexMode, Blocking>, - mut miso_mirror: Output<'static, GpioPin<3>>, + mut miso_mirror: AnyOutput<'static>, wanted: u8, ) { const DMA_BUFFER_SIZE: usize = 4; @@ -102,9 +102,11 @@ mod tests { let (peripherals, clocks) = esp_hal::init(esp_hal::Config::default()); let io = Io::new(peripherals.GPIO, peripherals.IO_MUX); - let miso = io.pins.gpio2; - let miso_mirror = Output::new(io.pins.gpio3, Level::High); + let (miso, miso_mirror) = hil_test::common_test_pins!(io); + + let miso = AnyPin::new(miso); + let miso_mirror = AnyOutput::new(miso_mirror, Level::High); let dma = Dma::new(peripherals.DMA); diff --git a/hil-test/tests/qspi_write.rs b/hil-test/tests/qspi_write.rs index bc2b01f9273..0e5ab14c229 100644 --- a/hil-test/tests/qspi_write.rs +++ b/hil-test/tests/qspi_write.rs @@ -3,11 +3,11 @@ //! This uses PCNT to count the edges of the MOSI signal //! //! Following pins are used: -//! MOSI GPIO2 +//! MOSI GPIO2 / GPIO9 (esp32s2 and esp32s3) //! -//! PCNT GPIO3 +//! PCNT GPIO3 / GPIO10 (esp32s2 and esp32s3) //! -//! Connect MOSI (GPIO2) and PCNT (GPIO3) pins. +//! Connect MOSI and PCNT pins. //% CHIPS: esp32 esp32c6 esp32h2 esp32s2 esp32s3 @@ -18,7 +18,7 @@ use esp_hal::{ clock::Clocks, dma::{Channel, Dma, DmaPriority, DmaTxBuf}, dma_buffers, - gpio::{Io, Pull}, + gpio::{AnyPin, Io, Pull}, pcnt::{ channel::{EdgeMode, PcntInputConfig, PcntSource}, unit::Unit, @@ -50,8 +50,8 @@ struct Context { spi: esp_hal::peripherals::SPI2, pcnt: esp_hal::peripherals::PCNT, dma_channel: Channel<'static, DmaChannel0, Blocking>, - mosi: esp_hal::gpio::GpioPin<2>, - mosi_mirror: esp_hal::gpio::GpioPin<3>, + mosi: AnyPin<'static>, + mosi_mirror: AnyPin<'static>, clocks: Clocks<'static>, } @@ -113,8 +113,11 @@ mod tests { let (peripherals, clocks) = esp_hal::init(esp_hal::Config::default()); let io = Io::new(peripherals.GPIO, peripherals.IO_MUX); - let mosi = io.pins.gpio2; - let mosi_mirror = io.pins.gpio3; + + let (mosi, mosi_mirror) = hil_test::common_test_pins!(io); + + let mosi = AnyPin::new(mosi); + let mosi_mirror = AnyPin::new(mosi_mirror); let dma = Dma::new(peripherals.DMA); diff --git a/hil-test/tests/qspi_write_read.rs b/hil-test/tests/qspi_write_read.rs index 602a6a964f3..c4a8c6fb640 100644 --- a/hil-test/tests/qspi_write_read.rs +++ b/hil-test/tests/qspi_write_read.rs @@ -3,11 +3,11 @@ //! Make sure issue #1860 doesn't affect us //! //! Following pins are used: -//! MOSI/MISO GPIO2 +//! MOSI/MISO GPIO2 / GPIO9 (esp32s2 and esp32s3) //! -//! GPIO GPIO3 +//! GPIO GPIO3 / GPIO10 (esp32s2 and esp32s3) //! -//! Connect MOSI/MISO (GPIO2) and GPIO (GPIO3) pins. +//! Connect MOSI/MISO and GPIO pins. //% CHIPS: esp32 esp32c6 esp32h2 esp32s2 esp32s3 @@ -18,7 +18,7 @@ use esp_hal::{ clock::Clocks, dma::{Channel, Dma, DmaPriority, DmaRxBuf, DmaTxBuf}, dma_buffers, - gpio::{GpioPin, Io, Level, Output}, + gpio::{AnyOutput, AnyPin, Io, Level}, prelude::*, spi::{ master::{Address, Command, Spi, SpiDma}, @@ -44,14 +44,14 @@ cfg_if::cfg_if! { struct Context { spi: esp_hal::peripherals::SPI2, dma_channel: Channel<'static, DmaChannel0, Blocking>, - mosi: esp_hal::gpio::GpioPin<2>, - mosi_mirror: Output<'static, GpioPin<3>>, + mosi: AnyPin<'static>, + mosi_mirror: AnyOutput<'static>, clocks: Clocks<'static>, } fn execute( mut spi: SpiDma<'static, esp_hal::peripherals::SPI2, DmaChannel0, HalfDuplexMode, Blocking>, - mut mosi_mirror: Output<'static, GpioPin<3>>, + mut mosi_mirror: AnyOutput<'static>, wanted: u8, ) { const DMA_BUFFER_SIZE: usize = 4; @@ -104,8 +104,11 @@ mod tests { let (peripherals, clocks) = esp_hal::init(esp_hal::Config::default()); let io = Io::new(peripherals.GPIO, peripherals.IO_MUX); - let mosi = io.pins.gpio2; - let mosi_mirror = Output::new(io.pins.gpio3, Level::High); + + let (mosi, mosi_mirror) = hil_test::common_test_pins!(io); + + let mosi = AnyPin::new(mosi); + let mosi_mirror = AnyOutput::new(mosi_mirror, Level::High); let dma = Dma::new(peripherals.DMA); diff --git a/hil-test/tests/rmt.rs b/hil-test/tests/rmt.rs index 99211e35943..460e82b0de8 100644 --- a/hil-test/tests/rmt.rs +++ b/hil-test/tests/rmt.rs @@ -1,7 +1,7 @@ //! RMT Loopback Test //! //! It's assumed GPIO2 is connected to GPIO3 -//! (GPIO9 and GPIO10 for esp32s3) +//! (GPIO9 and GPIO10 for esp32s2 and esp32s3) //% CHIPS: esp32 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3 diff --git a/hil-test/tests/spi_full_duplex_dma_pcnt.rs b/hil-test/tests/spi_full_duplex_dma_pcnt.rs index cc3429ae81c..541cca6b859 100644 --- a/hil-test/tests/spi_full_duplex_dma_pcnt.rs +++ b/hil-test/tests/spi_full_duplex_dma_pcnt.rs @@ -20,7 +20,7 @@ use esp_hal::{ dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf}, dma_buffers, - gpio::{GpioPin, Io, Level, Output, Pull}, + gpio::{AnyPin, GpioPin, Io, Level, Output, Pull}, pcnt::{ channel::{EdgeMode, PcntInputConfig, PcntSource}, unit::Unit, @@ -52,7 +52,7 @@ struct Context { spi: SpiDma<'static, SPI2, DmaChannel0, FullDuplexMode, Blocking>, pcnt_unit: Unit<'static, 0>, out_pin: Output<'static, GpioPin<5>>, - mosi_mirror: GpioPin<2>, + mosi_mirror: AnyPin<'static>, } #[cfg(test)] @@ -68,7 +68,7 @@ mod tests { let io = Io::new(peripherals.GPIO, peripherals.IO_MUX); let sclk = io.pins.gpio0; - let (_, mosi) = hil_test::common_test_pins!(io); + let (mosi_mirror, mosi) = hil_test::common_test_pins!(io); let miso = io.pins.gpio4; let cs = io.pins.gpio8; @@ -91,7 +91,7 @@ mod tests { let mut out_pin = Output::new(io.pins.gpio5, Level::Low); out_pin.set_low(); assert_eq!(out_pin.is_set_low(), true); - let mosi_mirror = io.pins.gpio2; + let mosi_mirror = AnyPin::new(mosi_mirror); Context { spi, diff --git a/hil-test/tests/spi_half_duplex_read.rs b/hil-test/tests/spi_half_duplex_read.rs index fffe8386283..e7b2f821444 100644 --- a/hil-test/tests/spi_half_duplex_read.rs +++ b/hil-test/tests/spi_half_duplex_read.rs @@ -3,7 +3,7 @@ //! Folowing pins are used: //! SCLK GPIO0 //! MISO GPIO2 / GPIO9 (esp32s2 and esp32s3) -//! +//! //! GPIO GPIO3 / GPIO10 (esp32s2 and esp32s3) //! //! Connect MISO and GPIO pins. @@ -16,7 +16,7 @@ use esp_hal::{ dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf}, dma_buffers, - gpio::{AnyOutput, Io, Level, Output}, + gpio::{AnyOutput, Io, Level}, peripherals::SPI2, prelude::*, spi::{ diff --git a/hil-test/tests/spi_half_duplex_write.rs b/hil-test/tests/spi_half_duplex_write.rs index f094341500a..9adfb508881 100644 --- a/hil-test/tests/spi_half_duplex_write.rs +++ b/hil-test/tests/spi_half_duplex_write.rs @@ -3,7 +3,7 @@ //! Following pins are used: //! SCLK GPIO0 //! MOSI GPIO2 / GPIO9 (esp32s2 and esp32s3) -//! +//! //! PCNT GPIO3 / GPIO10 (esp32s2 and esp32s3) //! //! Connect MOSI and PCNT pins. diff --git a/hil-test/tests/uart_async.rs b/hil-test/tests/uart_async.rs index dc0d10ff677..940231710d5 100644 --- a/hil-test/tests/uart_async.rs +++ b/hil-test/tests/uart_async.rs @@ -33,9 +33,8 @@ mod tests { let io = Io::new(peripherals.GPIO, peripherals.IO_MUX); let (tx, rx) = hil_test::common_test_pins!(io); - - let uart = - Uart::new_async(peripherals.UART0, &clocks, tx, rx).unwrap(); + + let uart = Uart::new_async(peripherals.UART0, &clocks, tx, rx).unwrap(); Context { uart } }