From 56a41a14599d288444b1583df434ab9068d84a81 Mon Sep 17 00:00:00 2001 From: TekkamanV Date: Sat, 23 Jan 2021 02:52:17 +0800 Subject: [PATCH] riscv: dts: Add JH7100 and BeagleV Starlight support Based on the device tree in https://github.com/starfive-tech/u-boot/ with contributions from: yanhong.wang Huan.Feng ke.zhu yiming.li jack.zhu Samin Guo Chenjieqin bo.li Rearranged, cleanups, fixes and TPS65086 added by Emil. Cleanups, fixes and LED added by Geert. Cleanups and GPIO fixes from Drew. Thermal zone added by Stephen. Signed-off-by: Emil Renner Berthing Signed-off-by: Geert Uytterhoeven Signed-off-by: Stephen L Arnold Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/Makefile | 2 +- arch/riscv/boot/dts/starfive/Makefile | 2 + .../dts/starfive/jh7100-beaglev-starlight.dts | 439 +++++++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 599 ++++++++++++++++++ 4 files changed, 1041 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/starfive/Makefile create mode 100644 arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts create mode 100644 arch/riscv/boot/dts/starfive/jh7100.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index fe996b88319eb7..f2a652103b4e21 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -subdir-y += sifive +subdir-y += sifive starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan subdir-y += microchip diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile new file mode 100644 index 00000000000000..b0a89a15fc5cd5 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_STARFIVE_VIC7100) += jh7100-beaglev-starlight.dtb diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts new file mode 100644 index 00000000000000..3698e78d6a2141 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2021 StarFive Technology Co., Ltd. */ + +/dts-v1/; +#include "jh7100.dtsi" +#include +#include +#include + +/ { + model = "BeagleV Starlight Beta"; + compatible = "beagle,beaglev-starlight-jh7100", "starfive,jh7100"; + + aliases { + mshc0 = &sdio0; + mshc1 = &sdio1; + serial0 = &uart3; + serial1 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = <6250000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x0>; + }; + + leds { + compatible = "gpio-leds"; + + led-ack { + gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + label = "ack"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x28000000>; + alignment = <0x0 0x1000>; + alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>; + linux,cma-default; + }; + + jpu_reserved: framebuffer@c9000000 { + reg = <0x0 0xc9000000 0x0 0x4000000>; + }; + + nvdla_reserved: framebuffer@d0000000 { + reg = <0x0 0xd0000000 0x0 0x28000000>; + }; + + vin_reserved: framebuffer@f9000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0xf9000000 0x0 0x1000000>; + }; + + sffb_reserved: framebuffer@fb000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0xfb000000 0x0 0x2000000>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c0 { + imx219@10 { + compatible = "imx219"; + reg = <0x10>; + reset-gpio = <&gpio 58 0>; + }; + + tps65086@5e { + compatible = "ti,tps65086"; + reg = <0x5e>; + /* + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + */ + gpio-controller; + #gpio-cells = <2>; + }; + + tda998x@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + }; +}; + +&i2c2 { + seeed_plane_i2c@45 { + compatible = "seeed_panel"; + reg = <0x45>; + }; +}; + +&osc0_clk { + clock-frequency = <25000000>; +}; + +&osc1_clk { + clock-frequency = <27000000>; +}; + +&qspi { + nor_flash: nor-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <31250000>; + page-size = <256>; + block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <1>; + cdns,tsd2d-ns = <1>; + cdns,tchsh-ns = <1>; + cdns,tslch-ns = <1>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; + + nand_flash: nand-flash@1 { + compatible = "spi-flash-nand"; + reg = <1>; + spi-max-frequency = <31250000>; + page-size = <2048>; + block-size = <17>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <1>; + cdns,tsd2d-ns = <1>; + cdns,tchsh-ns = <1>; + cdns,tslch-ns = <1>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + +&sdio0 { + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <10000000>; + status = "okay"; +}; + +&sdio1 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + cap-power-off-card; + max-frequency = <10000000>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&sfivefb { + /* + pp1 { + pp-id = <1>; + fifo-out; + src-format = ; + src-width = <800>; + src-height = <480>; + dst-format = ; + dst-width = <800>; + dst-height = <480>; + }; + */ + + tda_998x_1080p { + compatible = "starfive,display-dev"; + panel_name = "tda_998x_1080p"; + panel_lcd_id = <22>; /* 1080p */ + interface_info = "rgb_interface"; + refresh_en = <1>; + bits-per-pixel = <16>; + physical-width = <62>; + physical-height = <114>; + panel-width = <1920>; + panel-height = <1080>; + pixel-clock = <78000000>; + /*dyn_fps;*/ /*dynamic frame rate support*/ + + /*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/ + /*gamma-command-monolithic;*/ + /*ce-command-monolithic;*/ + /*resume-with-gamma;*/ + /*resume-with-ce;*/ + + /*mipi info*/ + mipi-byte-clock = <78000>; + mipi-escape-clock = <13000>; + lane-no = <4>; + display_mode = "video_mode"; /*video_mode, command_mode*/ + + /* + auto_stop_clklane_en; + im_pin_val;*/ + + color_bits = ; + /*is_18bit_loosely;*/ + + /*video mode info*/ + h-pulse-width = <44>; + h-back-porch = <148>; + h-front-porch = <88>; + v-pulse-width = <5>; + v-back-porch = <36>; + v-front-porch = <4>; + status = "okay"; + sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/ + lp_cmd_en; + /*lp_hfp_en;*/ + /*lp_hbp_en;*/ + /*lp_vact_en;*/ + lp_vfp_en; + lp_vbp_en; + lp_vsa_en; + traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/ + + /*phy info*/ + data_tprepare = /bits/ 8 <0>; + data_hs_zero = /bits/ 8 <0>; + data_hs_exit = /bits/ 8 <0>; + data_hs_trail = /bits/ 8 <0>; + + /*te info*/ + te_source = "external_pin"; /*external_pin, dsi_te_trigger*/ + te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/ + te_enable = <0>; + cm_te_effect_sync_enable = <0>; /*used in command mode*/ + te_count_per_sec = <64>; /*used in esd*/ + + /*ext info*/ + /* + crc_rx_en; + ecc_rx_en; + eotp_rx_en; + */ + eotp_tx_en; + + dev_read_time = <0x7fff>; + /*type cmd return_count return_code*/ + /*id_read_cmd_info = [];*/ + /*pre_id_cmd = [];*/ + /*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/ + /*pre_esd_cmd = [];*/ + /*panel-on-command = [];*/ + /*panel-off-command = [];*/ + /*reset-sequence = <1 5>, <0 10>, <1 30>;*/ + /* + panel-gamma-warm-command = [ + + ]; + panel-gamma-nature-command = [ + + ]; + panel-gamma-cool-command = [ + + ]; + + panel-ce-std-command = [ + + ]; + panel-ce-vivid-command = [ + + ]; + */ + }; + + seeed_5_inch { + compatible = "starfive,display-dev"; + panel_name = "seeed_5_inch"; + panel_lcd_id = <22>; /* 480p */ + interface_info = "mipi_interface"; + refresh_en = <1>; + bits-per-pixel = <24>; + physical-width = <62>; + physical-height = <114>; + panel-width = <800>; + panel-height = <480>; + pixel-clock = <27500000>; + /*dyn_fps;*/ /*dynamic frame rate support*/ + fps = <50>; + /*.flags = PREFER_CMD_SEND_MONOLITHIC | CE_CMD_SEND_MONOLITHIC | RESUME_WITH_PREFER | RESUME_WITH_CE*/ + /*gamma-command-monolithic;*/ + /*ce-command-monolithic;*/ + /*resume-with-gamma;*/ + /*resume-with-ce;*/ + + /*mipi info*/ + mipi-byte-clock = <78000>; + mipi-escape-clock = <13000>; + lane-no = <1>; + display_mode = "video_mode"; /*video_mode, command_mode*/ + + /* + auto_stop_clklane_en; + im_pin_val; + */ + + color_bits = ; + /*is_18bit_loosely;*/ + + /*video mode info*/ + h-pulse-width = <10>; + h-back-porch = <20>; + h-front-porch = <50>; + v-pulse-width = <5>; + v-back-porch = <5>; + v-front-porch = <135>; + + /*seeed panel mode info*/ + dphy_bps = <700000000>; + dsi_burst_mode = <0>; + dsi_sync_pulse = <1>; + // bytes + dsi_hsa = <30>; + dsi_hbp = <211>; + dsi_hfp = <159>; + // lines + dsi_vsa = <5>; + dsi_vbp = <5>; + dsi_vfp = <134>; + + status = "okay"; + sync_pol = "vsync_high_act"; /*vsync_high_act, hsync_high_act*/ + lp_cmd_en; + /*lp_hfp_en;*/ + /*lp_hbp_en;*/ + /*lp_vact_en;*/ + lp_vfp_en; + lp_vbp_en; + lp_vsa_en; + traffic-mode = "burst_with_sync_pulses"; /*non_burst_with_sync_pulses, non_burst_with_sync_events*/ + + /*phy info*/ + data_tprepare = /bits/ 8 <0>; + data_hs_zero = /bits/ 8 <0>; + data_hs_exit = /bits/ 8 <0>; + data_hs_trail = /bits/ 8 <0>; + + /*te info*/ + te_source = "external_pin"; /*external_pin, dsi_te_trigger*/ + te_trigger_mode = "rising_edge"; /*rising_edge, high_1000us*/ + te_enable = <0>; + cm_te_effect_sync_enable = <0>; /*used in command mode*/ + te_count_per_sec = <64>; /*used in esd*/ + + /*ext info*/ + /* + crc_rx_en; + ecc_rx_en; + eotp_rx_en; + */ + eotp_tx_en; + + dev_read_time = <0x7fff>; + /*type cmd return_count return_code*/ + /*id_read_cmd_info = [];*/ + /*pre_id_cmd = [];*/ + /*esd_read_cmd_info = [DCS_CMD 0A 01 9C];*/ + /*pre_esd_cmd = [];*/ + /*panel-on-command = [];*/ + /*panel-off-command = [];*/ + /*reset-sequence = <1 5>, <0 10>, <1 30>;*/ + /* + panel-gamma-warm-command = [ + + ]; + panel-gamma-nature-command = [ + + ]; + panel-gamma-cool-command = [ + + ]; + + panel-ce-std-command = [ + + ]; + panel-ce-vivid-command = [ + + ]; + */ + }; +}; + +&spi2 { + status = "okay"; + + spi_dev0: spi@0 { + compatible = "rohm,dh2228fv"; + spi-max-frequency = <10000000>; + reg = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usb3 { + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi new file mode 100644 index 00000000000000..af075f1bef0065 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -0,0 +1,599 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2021 StarFive Technology Co., Ltd. */ + +/dts-v1/; +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "starfive,jh7100"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "sifive,u74-mc", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <0>; + riscv,isa = "rv64imafdc"; + starfive,itim = <&itim0>; + status = "okay"; + tlb-split; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@1 { + compatible = "sifive,u74-mc", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + reg = <1>; + riscv,isa = "rv64imafdc"; + starfive,itim = <&itim1>; + status = "okay"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + osc0_clk: osc0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + osc1_clk: osc1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc { + compatible = "starfive,jh7100", "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ccache: cache-controller@2010000 { + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache"; + interrupts = <128 131 129 130>; + /*next-level-cache = <&L40 &L36>;*/ + reg = <0x0 0x2010000 0x0 0x1000>, + <0x0 0x8000000 0x0 0x2000000>; + reg-names = "control", "sideband"; + }; + + dtim: dtim@1000000 { + compatible = "starfive,dtim0"; + reg = <0x0 0x1000000 0x0 0x2000>; + reg-names = "mem"; + }; + + itim0: itim@1808000 { + compatible = "starfive,itim0"; + reg = <0x0 0x1808000 0x0 0x8000>; + reg-names = "mem"; + }; + + itim1: itim@1820000 { + compatible = "starfive,itim0"; + reg = <0x0 0x1820000 0x0 0x8000>; + reg-names = "mem"; + }; + + clint: clint@2000000 { + #interrupt-cells = <1>; + compatible = "riscv,clint0"; + interrupts-extended = <&cpu0_intc 3>, + <&cpu0_intc 7>, + <&cpu1_intc 3>, + <&cpu1_intc 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + reg-names = "control"; + }; + + plic: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, + <&cpu0_intc 9>, + <&cpu1_intc 11>, + <&cpu1_intc 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <127>; + }; + + clkgen: clock-controller@11800000 { + compatible = "starfive,jh7100-clkgen"; + reg = <0x0 0x11800000 0x0 0x10000>; + clocks = <&osc0_clk>, <&osc1_clk>; + clock-names = "osc0", "osc1"; + #clock-cells = <1>; + }; + + uart0: serial@11870000 { + compatible = "snps,dw-apb-uart"; + interrupts = <92>; + reg = <0x0 0x11870000 0x0 0x10000>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&clkgen JH7100_CLK_HS_UART>, + <&clkgen JH7100_CLK_APB1>; + clock-names = "baudclk", "apb_pclk"; + current-clock = <74250000>; + current-speed = <115200>; + status = "disabled"; + }; + + uart1: serial@11880000 { + compatible = "snps,dw-apb-uart"; + interrupts = <93>; + reg = <0x0 0x11880000 0x0 0x10000>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&clkgen JH7100_CLK_HS_UART>, + <&clkgen JH7100_CLK_APB1>; + clock-names = "baudclk", "apb_pclk"; + current-clock = <74250000>; + current-speed = <115200>; + status = "disabled"; + }; + + uart2: serial@12430000 { + compatible = "snps,dw-apb-uart"; + interrupts = <72>; + reg = <0x0 0x12430000 0x0 0x10000>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&clkgen JH7100_CLK_UART>, + <&clkgen JH7100_CLK_APB2>; + clock-names = "baudclk", "apb_pclk"; + current-clock = <100000000>; + current-speed = <115200>; + status = "disabled"; + }; + + uart3: serial@12440000 { + compatible = "snps,dw-apb-uart"; + interrupts = <73>; + reg = <0x0 0x12440000 0x0 0x10000>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&clkgen JH7100_CLK_UART>, + <&clkgen JH7100_CLK_APB2>; + clock-names = "baudclk", "apb_pclk"; + current-clock = <100000000>; + current-speed = <115200>; + status = "disabled"; + }; + + dma2p: dma-controller@100b0000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x0 0x100b0000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_AXI>, + <&clkgen JH7100_CLK_AHB0>; + clock-names = "core-clk", "cfgr-clk"; + interrupts = <2>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,block-size = <4096 4096 4096 4096>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <128>; + status = "okay"; + }; + + dma1p: dma-controller@10500000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x0 0x10500000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_AXI>, + <&clkgen JH7100_CLK_AHB0>; + clock-names = "core-clk", "cfgr-clk"; + interrupts = <1>; + #dma-cells = <1>; + dma-channels = <16>; + snps,dma-masters = <1>; + snps,data-width = <3>; + snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>; + snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + snps,axi-max-burst-len = <64>; + status = "okay"; + }; + + usb3: usb@104c0000 { + compatible = "cdns,usb3"; + reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers + <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers + <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers + reg-names = "otg", "xhci", "dev"; + interrupts = <44>, <52>, <43>; + interrupt-names = "host", "peripheral", "otg"; + phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy"; + maximum-speed = "super-speed"; + status = "disabled"; + }; + + gpio: gpio@11910000 { + compatible = "starfive,jh7100-gpio"; + reg = <0x0 0x11910000 0x0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <32>; + }; + + i2c0: i2c@118b0000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x118b0000 0x0 0x10000>; + interrupts = <96>; + clocks = <&clkgen JH7100_CLK_I2C0>; + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <500>; + i2c-scl-falling-time-ns = <500>; + scl-gpio = <&gpio 62 0>; + sda-gpio = <&gpio 61 0>; + }; + + i2c1: i2c@118c0000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x118c0000 0x0 0x10000>; + interrupts = <97>; + clocks = <&clkgen JH7100_CLK_I2C0>; + clock-frequency = <400000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <100>; + i2c-scl-falling-time-ns = <100>; + scl-gpio = <&gpio 47 0>; + sda-gpio = <&gpio 48 0>; + }; + + i2c2: i2c@12450000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x12450000 0x0 0x10000>; + interrupts = <74>; + clocks = <&clkgen JH7100_CLK_I2C2>; + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <500>; + i2c-scl-falling-time-ns = <500>; + scl-gpio = <&gpio 60 0>; + sda-gpio = <&gpio 59 0>; + }; + + trng: trng@118d0000 { + compatible = "starfive,vic-rng"; + reg = <0x0 0x118d0000 0x0 0x10000>; + interrupts = <98>; + clocks = <&clkgen JH7100_CLK_HF>; + }; + + crypto: crypto@100d0000 { + compatible = "starfive,vic-sec"; + reg = <0x0 0x100d0000 0x0 0x20000>, + <0x0 0x11800234 0x0 0xc>; + reg-names = "secmem", "secclk"; + interrupts = <31>; + clocks = <&clkgen JH7100_CLK_HF>; + }; + + /* gmac device configuration */ + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <256 128 64 32 0 0 0>; + }; + + gmac: ethernet@10020000 { + compatible = "snps,dwmac"; + reg = <0x0 0x10020000 0x0 0x10000>; + interrupts = <6 7>; + interrupt-names = "macirq", "eth_wake_irq"; + max-frame-size = <9000>; + phy-mode = "rgmii-txid"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + rx-fifo-depth = <32768>; + tx-fifo-depth = <16384>; + clocks = <&clkgen JH7100_CLK_GMAC>; + clock-names = "stmmaceth"; + snps,fixed-burst; + snps,no-pbl-x8 = <1>; + /*snps,force_sf_dma_mode;*/ + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + }; + + nbdla: nvdla@11940000 { + compatible = "nvidia,nvdla_os_initial"; + interrupts = <22>; + memory-region = <&nvdla_reserved>; + reg = <0x0 0x11940000 0x0 0x40000>; + status = "okay"; + }; + + jpu: coadj12@11900000 { + compatible = "cm,codaj12-jpu-1"; + reg = <0x0 0x11900000 0x0 0x300>; + memory-region = <&jpu_reserved>; + interrupts = <24>; + clocks = <&clkgen JH7100_CLK_JPU>; + clock-names = "jpege"; + reg-names = "control"; + status = "okay"; + }; + + vpu_dec: vpu_dec@118f0000 { + compatible = "c&m,cm511-vpu"; + reg = <0 0x118f0000 0 0x10000>; + //memory-region = <&vpu_reserved>; + interrupts = <23>; + clocks = <&clkgen JH7100_CLK_VPU>; + clock-names = "vcodec"; + status = "okay"; + }; + + vpu_enc: vpu_enc@118e0000 { + compatible = "cm,cm521-vpu"; + reg = <0x0 0x118e0000 0x0 0x4000>; + interrupts = <26>; + clocks = <&clkgen JH7100_CLK_VPU>; + clock-names = "vcodec"; + reg-names = "control"; + }; + + ptc: pwm@12490000 { + compatible = "starfive,pwm0"; + reg = <0x0 0x12490000 0x0 0x10000>; + reg-names = "control"; + sifive,approx-period = <100000000>; + clocks = <&clkgen JH7100_CLK_PWM>; + #pwm-cells = <3>; + sifive,npwm = <8>; + + }; + + qspi: spi@11860000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x11860000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x20000000>; + interrupts = <3>; + clocks = <&clkgen JH7100_CLK_QSPI>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + status = "disabled"; + spi-max-frequency = <250000000>; + }; + + /* + spi0: spi@11890000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + reg = <0x0 0x11890000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_SPI>; + status = "disabled"; + }; + + spi1: spi@118a0000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + reg = <0x0 0x118a0000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_SPI>; + status = "disabled"; + }; + */ + + spi2: spi@12410000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <70>; + reg = <0x0 0x12410000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_SPI>; + status = "disabled"; + }; + + xrp@f0000000 { + compatible = "cdns,xrp"; + reg = <0x0 0xf0000000 0x0 0x01ffffff>, + <0x10 0x72000000 0x0 0x00001000>, + <0x10 0x72001000 0x0 0x00fff000>, + <0x0 0x124b0000 0x0 0x00010000>; + clocks = <&clkgen JH7100_CLK_HF>; + firmware-name = "vp6_elf"; + dsp-irq = <19 20>; + dsp-irq-src = <0x20 0x21>; + intc-irq-mode = <1>; + intc-irq = <0 1>; + interrupts = <27 28>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x40000000 0x0 0x40000000 0x01000000>, + <0xb0000000 0x10 0x70000000 0x3000000>; + dsp@0 { + }; + }; + + sdio0: mmc@10000000 { + compatible = "snps,dw-mshc"; + reg = <0x0 0x10000000 0x0 0x10000>; + interrupts = <4>; + clocks = <&clkgen JH7100_CLK_DWMMC_BIU>; + clock-names = "biu"; + clock-frequency = <100000000>; + data-addr = <0>; + fifo-depth = <32>; + fifo-watermark-aligned; + status = "disabled"; + }; + + sdio1: mmc@10010000 { + compatible = "snps,dw-mshc"; + reg = <0x0 0x10010000 0x0 0x10000>; + interrupts = <5>; + clocks = <&clkgen JH7100_CLK_DWMMC_BIU>; + clock-names = "biu"; + clock-frequency = <100000000>; + data-addr = <0>; + fifo-depth = <32>; + fifo-watermark-aligned; + status = "disabled"; + }; + + sfivefb: sfivefb@12000000 { + compatible = "starfive,vpp-lcdc"; + interrupts = <101>, <103>; + interrupt-names = "lcdc_irq", "vpp1_irq"; + reg = <0x0 0x12000000 0x0 0x10000>, + <0x0 0x12100000 0x0 0x10000>, + <0x0 0x12040000 0x0 0x10000>, + <0x0 0x12080000 0x0 0x10000>, + <0x0 0x120c0000 0x0 0x10000>, + <0x0 0x12240000 0x0 0x10000>, + <0x0 0x12250000 0x0 0x10000>, + <0x0 0x12260000 0x0 0x10000>; + reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys"; + memory-region = <&sffb_reserved>; + clocks = <&clkgen JH7100_CLK_UART>, + <&clkgen JH7100_CLK_APB2>; + clock-names = "baudclk", "apb_pclk"; + status = "okay"; + ddr-format = ;/*LCDC win_format*/ + }; + + vin_sysctl: vin_sysctl@19800000 { + compatible = "starfive,stf-vin"; + reg = <0x0 0x19800000 0x0 0x10000>, + <0x0 0x19810000 0x0 0x10000>, + <0x0 0x19820000 0x0 0x10000>, + <0x0 0x19830000 0x0 0x10000>, + <0x0 0x19840000 0x0 0x10000>, + <0x0 0x19870000 0x0 0x30000>, + <0x0 0x198a0000 0x0 0x30000>, + <0x0 0x11800000 0x0 0x10000>, + <0x0 0x11840000 0x0 0x10000>, + <0x0 0x11858000 0x0 0x10000>; + reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", + "isp0", "isp1", "tclk", "trst", "iopad"; + interrupts = <119 109>; + memory-region = <&vin_reserved>; + /*defaule config for imx219 vin&isp*/ + format = ; + frame-width = <800>; + frame-height =<480>; + isp0_enable; + csi-lane = <2>; + csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>; + csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>; + csi-clane-swap = /bits/ 8 <0>; + csi-clane-pn-swap = /bits/ 8 <0>; + csi-mipiID = <0>; + csi-width = <1920>; + csi-height = <1080>; + csi-dt = <0x2b>; + }; + + sfctemp: tmon@124a0000 { + compatible = "starfive,jh7100-temp"; + reg = <0x0 0x124a0000 0x0 0x10000>; + #thermal-sensor-cells = <0>; + interrupts = <122>; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <15000>; + + thermal-sensors = <&sfctemp>; + + cooling-maps { + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit { + /* milliCelsius */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + otp: otp@11810000 { + compatible = "starfive,fu740-otp"; + reg = <0x0 0x11810000 0x0 0x10000>; + fuse-count = <0x200>; + }; + }; +};